From 8ae0bb88fa5f13f1620e931667a86b97b199c48e Mon Sep 17 00:00:00 2001 From: LapinFou Date: Mon, 20 Mar 2017 16:47:53 +0100 Subject: [PATCH 001/203] @3djc send me the new French .ts file. --- companion/src/translations/companion_fr.ts | 2433 ++++++++++++++++---- 1 file changed, 1954 insertions(+), 479 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index e8010acef..01de95e97 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -61,41 +61,49 @@ AppPreferencesDialog + Edit Settings Modifier les réglages + Radio Profile Profil de radio + Default Channel Order Ordre des voies par défaut + Build Options Options de compilation + Menu Language Langue des menus + Default Stick Mode Mode par défaut + Select Image Sélectionner une image + Mode selection: Mode 1: @@ -137,172 +145,207 @@ Manche Droit: Profondeur, Direction + Mode 1 (RUD ELE THR AIL) Mode 1 (DIR PROF GAZ AIL) + Mode 2 (RUD THR ELE AIL) Mode 2 (DIR GAZ PROF AIL) + Mode 3 (AIL ELE THR RUD) Mode 3 (AIL PROF GAZ DIR) + Mode 4 (AIL THR ELE RUD) Mode 4 (AIL GAZ PROF DIR) + Splash Screen Ecran d'accueil + + The profile specific folder, if set, will override general Backup folder Dossier de sauvegarde spécifique au profil courant, si défini remplace le réglage de l'application + Backup folder Dossier de sauvegarde + If set it will override the application general setting Si défini, remplace le réglage de l'application pour ce profil + if set, will override general backup enable Si défini, remplace le réglage de l'application pour ce profil + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> <html><head/><body><p>Ordre des voies</p><p><br/></p><p>Détermine l'ordre des mixages par défaut sur un nouveau modèle.</p></body></html> + R E T A D P G A + R E A T D P A G + R T E A D G P A + R T A E D G A P + R A E T D A P G + R A T E D A G P + E R T A P D G A + E R A T P D A G + E T R A P G D A + E T A R P G A D + E A R T P A D G + E A T R P A G D + T R E A G D P A + T R A E G D A P + T E R A G P D A + T E A R G P A D + T A R E G A D P + T A E R G A P D + A R E T A D P G + A R T E A D G P + A E R T A P D G + A E T R A P G D + A T R E A G D P + A T E R A G P D @@ -312,76 +355,95 @@ Manche Droit: Profondeur, Direction + + + + + Select Folder Sélectionner dossier + Select Executable Sélectionner exécutable + Use OpenTX firmware nightly builds Utlilser les nightly builds du firmware + Use Companion nightly builds Utlilser les nightly builds de Companion + Simulator Volume Gain Gain de volume du simulateur + Profile Name Nom du profil + Remove Profile Supprimer le profil + Clear Image Effacer l'image + Append version number to FW file name Ajouter le numéro de version au nom du fichier téléchargé + Offer to write FW to Tx after download Proposer de transférer le firmware à la radio après téléchargement + Radio Type Type de radio + Other Settings Autres réglages + General Settings Paramètres généraux + SD Structure path Chemin de la structure de la carte SD + Set voice language. May be different from firmware language Langue des voix. @@ -389,137 +451,165 @@ Peut être différente de la langue du firmware + Voice Language Langue des voix + Application Settings Réglages de l'application + Show splash screen when Companion starts Afficher l'écran d'accueil au lancement de Companion + Automatic check for Companion updates Vérifier la présence de mises à jour de Companion automatiquement + + Enable automatic backup before writing firmware Sauvegarder les réglages et modèles automatiquement lors des transferts + Automatic check for OpenTX firmware updates Vérifier la présence de mises à jour de firmware automatiquement + Splash Screen Library Bibliothèque d'écrans d'accueil + Files to keep Fichiers à conserver + Google Earth Executable Exécutable Google Earth + Only show user splash images Ne montrer que les images de l'utilisateur + Show user and companion splash images Montrer les images de Companion et de l'utilisateur + User Splash Screens Ecrans d'accueil personnalisés + Automatic Backup Folder Dossier de sauvegardes automatiques + Use model wizard when creating a new model Utiliser l'assistant à la création d'un nouveau modèle + Simulator Settings Paramètres du simulateur + Simulator BackLight Rétroéclairage du simulateur + Enable Actif + Blue Bleu + Green Vert + Red Rouge + Orange Orange + Yellow Jaune + Joystick Joystick + Calibrate Calibrer + Simulator capture folder Dossier des captures d'écran + Only capture to clipboard Capturer dans le presse-papiers uniquement + Remember simulator switch values Mémoriser les positions des inters du simulateur @@ -658,31 +748,37 @@ Peut être différente de la langue du firmware CompareDialog + Compare Models Comparer les modèles + Drag first model here Glisser le premier modèle ici + Drag second model here Glisser le second modèle ici + Close Fermer + Print Imprimer + Print to file Imprimer vers un fichier @@ -805,82 +901,99 @@ Peut être différente de la langue du firmware Curves + Fixed X X fixe + Custom X X configurable + Lines Linéaire + Smooth Adoucie + + Curve type Type de courbe + Curve Creator Créateur de courbe + Y at X=0 Y pour X=0 + Y at X=100 Y pour X=100 + Both Les 2 + x>0 + x<0 + Apply Appliquer + Side Côté + Y at X=-100 Y pour X=-100 + Coefficient + Curve name Nom de la courbe @@ -1070,21 +1183,29 @@ Peut être différente de la langue du firmware DebugOutput + + Debug Output Sortie débogage + + <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> <html><head/><body><p>Activer ou désactiver le filtre. Si le bouton ne reste pas actif, c'est qu'il y a probablement une erreur dans la <i>Regular Expression</i>.</p></body></html> + + Filter: Filtre: + + <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> <html><head/><body><p>Entrer le filtre ici. Cliquer sur le bouton d'aide/info pour plus de détails sur l'utilisation du filtre. </p><p> @@ -1092,51 +1213,71 @@ Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le + + Buffer: Tampon: + + Number of lines to keep in display. Nombre de lignes du tampon. + + Filter &Help Filtre &Aide + + Show information about using the filter. Affiche les informations concernant l'usage du filtre. + + Word &Wrap Renvoi &Ligne + + Toggle word wrapping on/off. Retour automatique à la ligne on/off. + + &Clear &Effacer + + Clear the output window of all text. Effacer tout le texte dans la fenêtre de sortie. + + Enable &Filter Activer &Filtre + + Turn the filter on/off. Basculer le filtre on/off. @@ -1262,16 +1403,19 @@ Il est recommandé d'"Enregistrer Sous" au plus vite pour ne pas ExpoDialog + Weight Ratio + Flight modes Phases de vol + Input name Nom de l'entrée @@ -1279,41 +1423,51 @@ Il est recommandé d'"Enregistrer Sous" au plus vite pour ne pas + + + GV VG + Switch Interrupteur + Curve applied to the source. Courbe appliquée à la source. + Source + Line name Nom de la ligne + Stick Side Direction + Source for the mixer. La voie maître du mixage. + Switch used to enable the line. If blank then the input is considered to be "ON" all the time. Interrupteur utilisé pour activer la ligne. @@ -1321,51 +1475,61 @@ Si vide, la ligne est toujours active. + Scale Echelle + Include Trim Inclure Trim + No Non + Yes Oui + Curve Courbe + Offset Décalage + The source for the mixer La voie maître du mixage + NEG Négative + POS Positive + ALL Les 2 @@ -1422,21 +1586,25 @@ Si vide, la ligne est toujours active. FirmwarePreferencesDialog + Downloads Téléchargements + Check for updates Vérifier les mises à jour + Voice Voix + Set voice language. May be different from firmware language Langue des voix. @@ -1444,21 +1612,25 @@ Peut être différente de la langue du firmware + Download Voice Télécharger les fichiers son + Download FW Télécharger le firmware + Firmware + Latest Download Dernière version téléchargée @@ -1495,67 +1667,80 @@ Peut être différente de la langue du firmware FlashEEpromDialog + Write Models and Settings to Radio Transférer les réglages et modèles vers la radio + Load... Parcourir... + Current Profile Profil courant + Allows Companion to write to older version of the firmware Permet à Companion de transférer des réglages à une ancienne version de firmware + Check Firmware compatibility Vérifier la compatibilité du firmware + <html><head/><body><p>Saves a dated copy of your eeprom to the backup folder you specified in the Companion settings before writing the current model to the radio.</p></body></html> <html><head/><body><p>Enregistre une copie datée de votre eeprom actuelle dans le dossier de sauvegarde avant de transférer les modèles à la radio.</p></body></html> + Backup before Write Sauvegarder les réglages actuels avant d'écrire + <html><head/><body><p>Modify calibration parameters using settings from current profile</p></body></html> <html><head/><body><p>Charger l'étalonnage du profil courant</p></body></html> + Patch calibration setting from profile Patcher l'étalonnage du profil courant + <html><head/><body><p>Modify HW parameters using settings from current profile</p></body></html> <html><head/><body><p>Charger les paramètres hardware du profil courant</p></body></html> + Patch HW settings from profile Patcher les paramètres hardware du profil courant + Cancel Annuler + Write to TX Transférer @@ -1628,71 +1813,85 @@ Peut être différente de la langue du firmware FlashFirmwareDialog + Flash Firmware Programmer le firmware + Load... Parcourir... + Date & Time Date et heure + Variant Variante + Version + Use profile start screen Utiliser l'écran d'accueil du profil + Use firmware start screen Utiliser l'écran d'accueil du firmware + Use library start screen Utiliser un écran d'accueil de la bibliothèque + Use another start screen Utiliser un autre écran d'accueil + Allows Companion to write to older version of the firmware Permet à Companion de transférer des réglages à une ancienne version de firmware + Check Hardware compatibility Vérifier la compatibilité du hardware + Backup and restore Models and Settings Sauvegarder et restaurer les réglages et modèles + Cancel Annuler + Write to TX Transférer @@ -1917,21 +2116,25 @@ Veuillez utiliser Zadig pour installer le pilote. FlightMode + Fade In Fondu en entrée + Fade Out Fondu en sortie + Name Nom + Switch Interrupteur @@ -2009,11 +2212,13 @@ Veuillez utiliser Zadig pour installer le pilote. FusesDialog + Fuses Fusibles + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2043,11 +2248,13 @@ p, li { white-space: pre-wrap; } + Read Fuses Lire Fusibles + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2082,6 +2289,7 @@ p, li { white-space: pre-wrap; } + Reset Fuses EEPROM - PROTECT Réinitialiser Fusibles @@ -2089,6 +2297,7 @@ PROTECTION EEPROM + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2121,6 +2330,7 @@ p, li { white-space: pre-wrap; } + Reset Fuses EEPROM - DELETE Réinitialiser Fusibles @@ -2128,6 +2338,7 @@ EFFACEMENT EEPROM + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2166,11 +2377,13 @@ p, li { white-space: pre-wrap; } + Radio settings Réglages Radio + General settings used throught the transmitter. These will be relevant for all models in the same EEPROM. Paramètres généraux de l'émetteur. @@ -2183,11 +2396,13 @@ Communs à tous les modèles d'une même EEPROM. + Store calib. and hw settings in selected profile Sauver étalonnage et réglages hw dans profil + Retrieve calib. and hw settings from profile Lire étalonnage et réglages hw du profil @@ -2243,213 +2458,257 @@ Communs à tous les modèles d'une même EEPROM. GeneralSetup + Form Formulaire + Readonly Unlock Débloquage lecture seule + SC + SE + SA + SF + SH + SD + SB + SG + Timeshift from UTC Décalage horaire (UTC) + Voice Language Langue des voix + Country Code Zone géograhpique RF + Stick reverse Inversion des manches + FAI Mode Mode FAI + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Lorsque le mode FAI est activé, le variomètre ainsi que l'écran et la lecture des valeurs de télémesure sont désactivés. Ce mode ne peut pas être désactivé sur la radio. + Adjust RTC Ajuster l'heure par GPS + Vario pitch at max Tonalité du vario au max + + Hz + Speaker Volume Volume haut-parleur + Backlight Switch Inter de rétroéclairage + Sound Mode Mode Son + Color 1 Couleur 1 + Color 2 Couleur 2 + Speaker Pitch (spkr only) Tonalité (HP uniquement) + If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. Si cette valeur est différente de 0, l'appui sur une touche de navigation déclenche le rétroéclairage qui s'éteint après la durée spécifiée (en secondes). + sec + Backlight color Couleur du rétroéclairage + Beeper Bipeur + Speaker Haut-parleur + BeeperVoice Bipeur/Voix + SpeakerVoice Haut-parleur/Voix + Beep volume Volume des bips + Wav volume Volume des fichiers audio + Vario volume Volume du variomètre + Background volume Volume de la musique d'ambiance + + ms + Backlight Auto OFF after Arrêt rétroéclairage après + Backlight flash on alarm Clignotement rétroécl. alarmes + Vario pitch at zero Tonalité du vario à 0 + Vario repeat at zero Répétition du vario à 0 + This is the switch selectrion for turning on the backlight (if installed). @@ -2458,6 +2717,8 @@ Communs à tous les modèles d'une même EEPROM. + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2473,41 +2734,49 @@ p, li { white-space: pre-wrap; } + Backlight Brightness Luminosité du rétroéclairage + RotEnc Navigation Navigation sélecteur rotatif + Automatically adjust the radio's clock if a GPS is connected to telemetry. Régle automatique l'heure de la radio si un GPS est présent. + America Amérique + Japan Japon + Europe + Backlight OFF Brightness Luminosité écran éteint + Mode selection: Mode 1: @@ -2549,270 +2818,327 @@ Mode 4: + Mode 1 (RUD ELE THR AIL) Mode 1 (DIR PRF GAZ AIL) + Mode 2 (RUD THR ELE AIL) Mode 2 (DIR GAZ PRF AIL) + Mode 3 (AIL ELE THR RUD) Mode 3 (AIL PRF GAZ DIR) + Mode 4 (AIL THR ELE RUD) Mode 4 (AIL GAZ PRF DIR) + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> <html><head/><body><p>Ordre des voies</p><p><br/></p><p>Détermine l'ordre des mixages par défaut sur un nouveau modèle.</p></body></html> + R E T A D P G A + R E A T D P A G + R T E A D G P A + R T A E D G A P + R A E T D A P G + R A T E D A G P + E R T A P D G A + E R A T P D A G + E T R A P G D A + E T A R P G A D + E A R T P A D G + E A T R P A G D + T R E A G D P A + T R A E G D A P + T E R A G P D A + T E A R G P A D + T A R E G A D P + T A E R G A P D + A R E T A D P G + A R T E A D G P + A E R T A P D G + A E T R A P G D + A T R E A G D P + A T E R A G P D + Stick Mode Mode + Metric Métrique + Imperial Impérial + Default Channel Order Ordre des voies par défaut + GPS Coordinates Coordonnées GPS + Min + + v + Max + Low Memory Warning Alerte mémoire pleine + Inactivity Timer Alerte d'inactivité + Show Splash Screen on Startup Afficher l'écran de démarrage + Contrast Contraste + Battery Meter Range Plage de l'indicateur de batterie + Haptic Strength Puissance vibreur + LCD Display Type Type de LCD + "No Sound" Warning Alerte "son coupé" + Battery Warning Alerte batterie + Haptic Length Durée vibreur + MAVLink Baud Rate Baudrate Mavlink + + Quiet Mode silencieux + Only Alarms Seulement les alarmes + + No Keys Touches silencieuses + + All Tous + Battery warning voltage. This is the threashhold where the battery warning sounds. @@ -2824,114 +3150,138 @@ Plage de valeurs: 5v...10v + Standard + Optrex + If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. Si différent de 0, émission d'un bip sonore régulier si aucune action n'a été effectuée sur l'émetteur depuis le temps spécifié (en minutes). Réinitialisation en agissant sur n'importe lequel des manches / touches de navigation. + min + + Show splash screen on startup Affiche l'écran d'accueil au démarrage + --- + 2s + 3s + 4s + 6s + 8s + 10s + 15s + 4800 Baud + 9600 Baud + 14400 Baud + 19200 Baud + 38400 Baud + 57600 Baud + 76800 Baud + 115200 Baud + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2958,70 +3308,88 @@ p, li { white-space: pre-wrap; } + + X-Short Très court + + Short Court + + Normal + + Long + + X-Long Très long + hh° (N/S) mm' ss''.dd + NMEA + Play Delay (switch mid position) Délai position centrale inters + Measurement Units Unités de mesure + Haptic Mode Mode du vibreur + Beeper Length Durée des bips + Beeper Mode Réglage des bips + Beeper volume 0 - Quiet. No beeps at all. @@ -3039,6 +3407,7 @@ Extra long : bips extra longs. + Alarms Only Seulement les Alarmes @@ -3075,51 +3444,61 @@ Are you sure ? Hardware + Form Formulaire + SQ + SR + LS2 + SP + SO + S4 + RS + SB + PPM 2 @@ -3134,6 +3513,16 @@ Are you sure ? + + + + + + + + + + Beeper volume 0 - Quiet. No beeps at all. @@ -3151,186 +3540,223 @@ Extra long : bips extra longs. + OFF Eteint + S-Port Mirror Recopie S. Port + Telemetry Télémetrie + SBUS Trainer Écolage SBUS + Debug Débogage + Rud Dir + PPM 3 + S1 + S2 + S3 + PPM 1 + Serial Port Port série + v + PPM Multiplier Coeff. multiplicateur PPM + Current Offset Correction courant + PPM 4 + SA + Ele Prf + Ail Ail + Thr Gaz + SC + LS + SD + Battery Offset Correction tension + SE + SF + SG + SH + SI + SJ + SK + SL + SM + SN + RS2 + Bluetooth + ADC Filter Filtre ADC @@ -3384,71 +3810,85 @@ Extra long : bips extra longs. Heli + Invert Elevator Profondeur + Invert Aileron Aileron + Invert Collective Pas collectif + Invert Inversion + Off Aucun + 120 + 120X + 140 + 90 + Long. cyc Cyc. longitudinal + Lateral cyc Cyc. latéral + Collective Source du pas collectif + Swash Type Type de plateau cyclique + Swash Ring Limite cyclique @@ -3691,41 +4131,49 @@ Extra long : bips extra longs. LogsDialog + Companion Log Viewer Visualiseur de Log + Filename Nom de fichier + Open LogFile Ouvrir fichier de Log + Zoom + X + Y + Reset Remise à zéro + Fly sessions Sessions de vol @@ -3864,111 +4312,111 @@ Les colonnes contenant l'altitude "GAlt" et la vitesse "GSpd MainWindow - - + + Edit Edition - - + + File Fichier - + Display previous warning again at startup ? Afficher les alertes précédentes lors du prochain démarrage ? - + New release available Nouvelle version disponible - - + + Error Erreur - + Error opening file %1: %2. Erreur à l'ouverture du fichier %1: %2. - + Compilation server too busy, try later Serveur de compilation surchargé, veuillez réessayer plus tard - + Unknown server failure, try later Erreur inconnue du serveur de compilation, veuillez réessayer plus tard - + Do you want to write the firmware to the radio now ? Voulez vous transférer le firmware à la radio maintenant ? - - + + Yes Oui - - + + No Non - - + + Release Notes Notes de version - - + + Do you want to download release %1 now ? Voulez-vous télécharger la version %1 maintenant ? - + Firmware updates Mises à jour de firmware - + Current firmware does not provide release notes informations. Le firmware actuel ne contient pas de notes de version. - + Load backup from file Charger une sauvegarde à partir du fichier - + Compare models Comparer les modèles - + Show fuses dialog Afficher les réglages des fusibles - + A monochrome black icon theme Thème avec icônes monochromes noires - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -3981,7 +4429,7 @@ Voulez-vous la télécharger maintenant ? Nous recommandons de lire attentivement les notes de version à l'aide du bouton ci-dessous, celles-ci peuvent contenir des infos importantes concernant les changements effectués depuis la version précédente. - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -3998,756 +4446,756 @@ Voulez vous la télécharger maintenant ? Nous recommandons de lire attentivement les notes de version à l'aide du bouton ci-dessous, celles-ci peuvent contenir des infos importantes concernant les changements effectués depuis la version précédente. - - + + Synchronize SD Synchroniser la carte SD - + New Nouveau - + Open... Ouvrir... - + Copy Model Copier le modèle - + A monochrome white icon theme Thème avec icônes monochromes blanches - + A monochrome blue icon theme Thème avec icônes monochromes bleues - + Small Petites - + Use small toolbar icons Petites icônes de barre d'outils - + Use normal size toolbar icons Icônes de barre d'outils normales - + Normal Normales - + Use big toolbar icons Grosses icônes de barre d'outils - + Big Grandes - + Use huge toolbar icons Immenses icônes de barre d'outils - + Huge Immenses - + Czech Tchèque - + Use Czech in menus Menus en Tchèque - + German Allemand - + Use German in menus Menus en Allemand - + English Anglais - + Use English in menus Menus en Anglais - + French Français - + Use French in menus Menus en Français - + Italian Italien - + Use Italian in menus Menus en Italien - + Polish Polonais - + Use Polish in menus Menus en Polonais - + Swedish Suédois - + Use Swedish in menus Menus en Suédois - + List programmers... Lister les programmateurs... - + Fuses... Fusibles... - - + + Read Firmware from Radio Lire le firmware de la radio - + Read firmware from Radio Lire le firmware de la radio - + Write Firmware to Radio Transférer le firmware à la radio - + Write firmware to Radio Transférer le firmware à la radio - + Add Radio Profile Ajouter un profil de radio - + Create a new Radio Setting Profile Créér un nouveau profil de radio - + Manuals and other Documents Manuels et documents - + Open the OpenTX document page in a web browser Ouvre la page de documentation d'OpenTX dans un navigateur - + Write Models and Settings To Radio Transférer les réglages et modèles vers la radio - + Write Models and Settings to Radio Transférer les réglages et modèles vers la radio - - - + + + Companion - - + + Read Models and Settings from Radio Lire les réglages et modèles depuis la radio - + OpenTX Companion %1 - Radio: %2 - Profile: %3 OpenTX Companion %1 - Radio: %2 - Profil: %3 - + Configure Communications... Configurer les communications... - + Configure software for communicating with the Radio Configurer le programme gérant les communications avec la radio - + Write Backup to Radio Transférer une sauvegarde à la radio - + Write Backup from file to Radio Transférer une sauvegarde à la radio - + Backup Radio to File Sauvegarder la radio - + Save a complete backup file of all settings and model data in the Radio Créer une copie de sauvegarde de tous les réglages et modèles de la radio - + Contributors... Contributeurs... - + A tribute to those who have contributed to OpenTX and Companion Remerciements à tout ceux qui ont contribué à OpenTX et Companion - + SD card synchronization Synchronisation de la carte SD - + Recent Files Fichiers récents - + Recent Models+Settings Fichiers de réglages et modèles récents - + Set Icon Theme Choisir le thème d'icônes - + Set Icon Size Choisir la taille des icônes - + Write Ecrire - + A new version of Companion is available (version %1)<br>Would you like to download it? Une nouvelle version de Companion est disponible (version %1)<br>Voulez-vous la télécharger ? - + OpenTX Home Page: <a href='%1'>%1</a> Page d'accueil d'OpenTX: <a href='%1'>%1</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> Si vous trouvez ce programme utile, merci de le supporter par une <a href='%1'>donation</a> - + Show the list of radio profiles Voir la liste des profils de radio - + Ready Prêt - + Show the application's About box Afficher la fenêtre "A propos" de l'application - - + + File loaded Fichier chargé - + A new release of Companion is available, please check the OpenTX website! Une nouvelle version de Companion est disponible, veuillez vous référer au site web d'OpenTX ! - - + + Open Models and Settings file Ouvrir un fichier de réglages et modèles - - + + File saved Fichier sauvegardé - + Read Models and Settings From Radio Lire les réglages et modèles depuis la radio - + Ignore this release %1? Ignorer la version %1 ? - + Not enough flash available on this board for all the selected options Pas assez de place disponible pour les options sélectionnées - + Compilation server temporary failure, try later Erreur de compilation sur le serveur, veuillez réessayer plus tard - + Compilation error Erreur de compilation - + Invalid firmware Firmware invalide - + Invalid board Carte non valide - + Invalid language Language non valide - + Models and Settings read Lecture des modèles et réglages - - + + This function is not yet implemented Cette fonction n'est pas implémentée pour l'instant - + Save Radio Backup to File Sauvegarder la radio - + Read Radio Firmware to File Sauvegarder le firmware de la radio - + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> Le projet OpenTX Companion a été créé à partir d'<a href='%1'>eePe</a> - + Copyright OpenTX Team - + Create a new Models and Settings file Créer un nouveau fichier de réglages et modèles - - + + Save Models and Settings file Enregistrer le fichier de réglages et modèles - + Save Enregistrer - + Save As... Enregistrer sous... - + Exit the application Quitter l'application - + Exit Quitter - + Cut Model Couper le modèle - + Cut current model to the clipboard Couper le modèle courant dans le presse-papier - + Copy current model to the clipboard Copier le modèle courant dans le presse-papier - + Paste model from clipboard Coller le modèle depuis le presse-papier - + Paste Model Coller le modèle - + Classical Classique - + The classic companion9x icon theme Thème d'icônes classique de Companion - + Yerico - + Yellow round honey sweet icon theme Thème d'icônes rondes jaunes - + Monochrome - + MonoWhite Monochrome Blanc - + MonoBlue Monochrome Bleu - + System language Langue du système - + Use system language in menus Utiliser la langue système dans les menus - + Finnish Finlandais - + Use Finnish in menus Menus en Finlandais - + Spanish Espagnol - + Use Spanish in menus Menus en espagnol - + Chinese Chinois - + Use Chinese in menus Utiliser les menus Chinois - + About... A propos... - + Print... Imprimer... - + Print current model Imprimer le modèle courant - + Simulate... Simuler... - + Simulate current model Simuler le modèle courant - + Alt+S - + Load Backup... Ouvrir la sauvegarde... - + View Log File... Ouvrir un Log... - + Open and view log file Ouvrir et visualiser un log - + Settings... Préférences... - + Edit Settings Modifier les réglages - + Download... Télécharger... - + Download firmware and voice files Télécharger firmware et fichiers son - + Check for Updates... Vérifier les mises à jour... - + Check OpenTX and Companion updates Vérifier les mises à jour d'OpenTX et Companion - + Companion Changes... Changements de Companion... - + Show Companion change log Voir l'historique des changements de Companion - + Firmware Changes... Changements du firmware... - + Show firmware change log Voir l'historique des changements du firmware - + Compare Models... Comparer 2 modèles... - + Edit Radio Splash Image... Modifier l'écran d'accueil de la radio... - + Edit the splash image of your Radio Modifier l'écran d'accueil de la radio - + List available programmers Lister les programmateurs supportés - - + + Save As Enregistrer Sous - + Executable (*.exe) Exécutable (*.exe) - - + + No updates available at this time. Aucune mise à jour disponible. - + Unable to check for updates. Impossible de rechercher des mises à jour. - + Would you like to launch the installer? Voulez-vous lancer l'installation ? - - + + Help Aide - + Checking for updates Recherche de mises à jour - + The selected language will be used the next time you start Companion. La langue sélectionnée sera utilisée lors du prochain lancement de Companion. - + The new theme will be loaded the next time you start Companion. Le nouveau thème sera utilisé lors du prochain lancement de Companion. - + The icon size will be used the next time you start Companion. La nouvelle taille d'icônes sera utilisée lors du prochain lancement de Companion. - + About Companion A propos de Companion - + Set Menu Language Choisir la langue des menus - + Settings Réglages - + Read/Write Transfert - - + + Radio Profile Profil de radio - + Show recent Models+Settings documents Voir les fichiers récents - + %2 - + New Radio Nouvelle radio @@ -5003,11 +5451,13 @@ Enregistrer les changements ? + Radio settings Réglage Radio + Simulate Tx Simulation de l'émetteur @@ -5016,41 +5466,49 @@ Enregistrer les changements ? MixerDialog + Up Haut + ADD Ajouter + OFF + Down Bas + Slow Ralenti + Delay Délai + Curve Courbe + Multiplexer This determines how mixer values are added. @@ -5068,6 +5526,7 @@ Spécifie comment les valeurs de mixage sont interprétées. + The curve used by the mix Courbe utilisée par le mixage @@ -5075,21 +5534,27 @@ Spécifie comment les valeurs de mixage sont interprétées. + + + GV VG + Yes Oui + No Non + Mixer warning. Setting this value will cause a beep to be emmitted when this value is active. Alerte de mixage. @@ -5097,26 +5562,31 @@ Si activée, signale par des bips que le mixage est actif. + 1 Beep 1 Bip + 2 Beep 2 Bips + 3 Beep 3 Bips + Multiplex Multiplexage + Dialog Dialogue @@ -5125,6 +5595,10 @@ Si activée, signale par des bips que le mixage est actif. + + + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -5150,26 +5624,31 @@ p, li { white-space: pre-wrap; } + Offset Décalage + Source Source + Switch Interrupteur + Weight Ratio + REPLACE Remplacer @@ -5178,16 +5657,22 @@ p, li { white-space: pre-wrap; } + + + + The source for the mixer La source du mixage + MULTIPLY Multiplier + Switch used by the mix. If blank then the mix is considered to be "ON" all the time. Interrupteur utilisé par le mixage. @@ -5195,11 +5680,13 @@ Mixage actif par défaut si non-renseigné. + Warning Avertissement + Name Nom @@ -5230,16 +5717,19 @@ Mixage actif par défaut si non-renseigné. + Include Trim Inclure Trim + Flight modes Phases de vol + Include DR/Expo Inclure DR/Expo @@ -5380,6 +5870,7 @@ Mixage actif par défaut si non-renseigné. ModelEdit + Simulate Simulation @@ -5415,6 +5906,7 @@ Mixage actif par défaut si non-renseigné. + Dialog Dialogue @@ -5788,198 +6280,237 @@ Mixage actif par défaut si non-renseigné. Module + Failsafe Mode Mode Failsafe + Start 1ère voie + PPM delay Impulsion + Negative Négative + Positive + Polarity Polarité + Trainer Mode Mode écolage + PPM Frame Length Longueur de trame PPM + CH VOIE + Antenna Antenne + Internal Interne + Ext. + Int. Ext. + Int. + Option value + us µs + Master/Jack Maître/Jack + Slave/Jack Elève/Jack + Master/SBUS Module Maître/SBUS module + Master/CPPM Module Maître/CPPM Module + Master/SBUS in battery compartment Maître/SBUS dans compartiment batterie + Show values in: Afficher les valeurs en: + % abbreviation for percent + μs abbreviation for microseconds + ms + Channels Nb de voies + Not set Non défini + Hold Maintien + Custom Prédéfini + No Pulses Pas d'impulsions + Receiver Récepteur + Failsafe Positions Positions + Protocol Protocole + Multi Radio Protocol Protocol Multi + Receiver No. Récepteur No. + Output type Type de sortie + Open Drain + Push Pull + SubType SousType + Bind on startup Bind au démarage + Low Power Puiss Réd @@ -6330,16 +6861,19 @@ Mixage actif par défaut si non-renseigné. PrintDialog + Close Fermer + Print Imprimer + Print to file Imprimer vers un fichier @@ -6363,11 +6897,13 @@ Mixage actif par défaut si non-renseigné. ProgressDialog + Flash Firmware Flasher le firmware + Close Fermer @@ -6376,11 +6912,13 @@ Mixage actif par défaut si non-renseigné. ProgressWidget + Form Formulaire + Show Details Voir les détails @@ -6468,7 +7006,7 @@ Mixage actif par défaut si non-renseigné. Vibreur - + S3 @@ -6573,12 +7111,12 @@ Mixage actif par défaut si non-renseigné. Heure GPS - + L1 - + L2 @@ -7236,7 +7774,7 @@ Mixage actif par défaut si non-renseigné. - + P1 @@ -7338,13 +7876,13 @@ Mixage actif par défaut si non-renseigné. - + P2 - + P3 @@ -7500,25 +8038,25 @@ Mixage actif par défaut si non-renseigné. !Courbe(%1) - + Rud Dir - + Ele Prf - + Thr Gaz - + Ail Ail @@ -7544,9 +8082,9 @@ Mixage actif par défaut si non-renseigné. TrmA - - - + + + S1 @@ -7616,43 +8154,43 @@ Mixage actif par défaut si non-renseigné. - - - + + + S2 - - - + + + LS - - - + + + RS - + F1 - + F2 - + F3 - + F4 @@ -7823,70 +8361,67 @@ Mixage actif par défaut si non-renseigné. - - + + Support for frsky telemetry mod Support de la télémétrie FrSky - - + + Support for jeti telemetry mod Support de la télémétrie JETI - - + + Support for receiving ardupilot data Support de la télémétrie ARDUPILOT - - + + Support for receiving NMEA data Support de la télémétrie NMEA - + Support for telemetry easy board Support de la carte TelemetrEZ - - + + Support for MAVLINK devices Support du protocole MAVLINK - + Rotary Encoder use in menus navigation Utiliser le sélecteur rotatif pour la navigation - - - - - - + + + + + + Enable heli menu and cyclic mix support Activer le menu hélico et les mixages CCPM - - - - - - - - - + + + + + + Enable TEMPLATES menu Inclure les gabarits - + 6P @@ -7921,103 +8456,112 @@ Mixage actif par défaut si non-renseigné. Impossible d'écrire le modèle %1 - + JSx - + JSy - + KS108 LCD - + + WTV20 voice module + + + + + JQ6500 voice module + + + + FrSky Taranis X9D+ - + FrSky Taranis X9D - + Horus gimbals installed (Hall sensors) Manches à effet HALL de Horus installés - + FrSky Taranis X7 - + FrSky Horus - + Use ONLY with first DEV pcb version Exclusivement pour les Horus DEV - + Turnigy 9XR-PRO - + Turnigy 9XR with m128 chip Turnigy 9XR avec une puce m128 - - - - + + + + No splash screen Pas d'écran de démarrage - - - - - - + + + + + + Disable curves menus Désactiver le menu des courbes - - - - - + + + + + Support for radio modified with regular speaker Haut-parleur au lieu du buzzer d'origine - - - - - - + + + + + Used if you have modified your radio with voice mode Support du module vocal - - - - - + + + + + Used if you have modified your radio with haptic mode Support du vibreur @@ -8027,30 +8571,30 @@ Mixage actif par défaut si non-renseigné. Positions de voies affichées en µs - - - - - - - - - + + + + + + + + + Battery graph Graphique de batterie - - - - - - - - - - - + + + + + + + + + + + Use alternative SQT5 font Utiliser la police alternative SQT5 @@ -8080,117 +8624,111 @@ Mixage actif par défaut si non-renseigné. Masque le protocole D8. Légalement obligatoire sur les radios Européennes importées après le 1er janvier 2015 - - + + Support for PPM internal module hack Support du remplacement du module interne par un module PPM - + ST7565P LCD or compatible ST7565P LCD ou compatible - + ST7565R LCD or compatible ST7565R LCD ou compatible - + ERC12864FSF LCD LCD ERC12864FSF - + ST7920 LCD LCD ST7920 - - - - + + + + Enable the throttle trace in Statistics Activer l'historique du manche des gaz dans les statistiques - + EEprom write progress bar Barre de progression pour l'écriture de l'EEPROM - - + + No Winged Shadow How High support Supprimer le support du variomètre Winged Shadow How High - + Turnigy 9XR - - + + No vario support Supprimer la fonction variomètre audio - - + + No GPS support Supprimer le support du GPS - - + + No gauges in the custom telemetry screen Supprimer l'affichage des valeurs de télémesure par barres - + 9X with stock board 9X avec carte mère d'origine - + Allow compensating for offset errors in FrSky FAS current sensors Permettre la compensation d'un décalage des capteurs de courant FASxx FrSky - - + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) Ajoute le support de l'inversion des manches (nécessaire pour l'utilisation de manches FrSky) - + DIY MEGA2560 radio - + Power management by soft-off circuitry Gestion alim. par software - + FrSky Taranis X9E - + Confirmation before radio shutdown Confirmation avant l'arrêt de la radio - - - Adds mixers output view to the CHANNELS MONITOR screen, pressing [ENT] switches between the views - Ajoute une vue de la sortie des mixeurs au moniteur de canaux, ENT pour passer d'une vue à l'autre - - - + Haptic module installed Module vibreur installé @@ -8200,8 +8738,8 @@ Mixage actif par défaut si non-renseigné. Support des scripts Lua - - + + Support of FrSky PXX protocol Support du protocole PXX FrSky @@ -8216,42 +8754,42 @@ Mixage actif par défaut si non-renseigné. Supprimer le support des variables globales - - - - - + + + + + Support for DSM2 modules Support du protocole DSM2 - - - - - - + + + + + + PPM center adjustment in limits Neutres PPM ajustables - - - - - - + + + + + + Symetrical Limits Limites symétriques - - - - - - - + + + + + + + Pots use in menus navigation Support de la navigation dans les menus avec les POTS @@ -8260,161 +8798,161 @@ Mixage actif par défaut si non-renseigné. No OverrideCH functions available Désactive la fonction spéciale "Remplacer VOIEx" - - - - - - - - - - - No flight modes - Pas de phases de vol - - - - - SmartieParts 2.2 Backlight support - Support du rétroéclairage pour la carte SmartieParts 2.2 - - - - - - - - - Enable resetting values by pressing up and down at the same time - Permet la remise à zéro des valeurs en pressant haut-bas en même temps, valeur min avec gauche/bas, valeur max avec haut/droite, inversion avec gauche/droite - - - - - - - - - - - - No graphical check boxes and sliders - Pas de cases à cocher et de curseurs graphiques - - - - - - - - - - - - Don't use bold font for highlighting active items - Ne pas mettre les lignes actives en gras - - - - - - - - EEprom write Progress bar - Barre de progression affichée lors des écritures EEPROM - - - - - - - - - Imperial units - Unités Impériales - - - - Bluetooth interface - Interface Bluetooth - - - - - - - + + + + + No flight modes + Pas de phases de vol + + + + + SmartieParts 2.2 Backlight support + Support du rétroéclairage pour la carte SmartieParts 2.2 + + + + + + + + + Enable resetting values by pressing up and down at the same time + Permet la remise à zéro des valeurs en pressant haut-bas en même temps, valeur min avec gauche/bas, valeur max avec haut/droite, inversion avec gauche/droite + + + + + + + + + + + + No graphical check boxes and sliders + Pas de cases à cocher et de curseurs graphiques + + + + + + + + + + + + Don't use bold font for highlighting active items + Ne pas mettre les lignes actives en gras + + + + + + + + EEprom write Progress bar + Barre de progression affichée lors des écritures EEPROM + + + + + + + + + Imperial units + Unités Impériales + + + + + + Bluetooth interface + Interface Bluetooth + + + + + + + + + + + Global variables Variables globales - - - - - - - - - + + + + + + + + + In model setup menus automatically set source by moving the control Sélectionner les sources des mixeurs en bougeant le contrôle désiré - - - - - - - - - + + + + + + + + + In model setup menus automatically set switch by moving the control Sélectionner les interrupteurs en bougeant le contrôle désiré - + 9X with stock board and m128 chip Carte 9x avec un chip m128 - + 9X with AR9X board 9X avec carte AR9X - + 9X with Sky9x board 9X avec carte Sky9x - + 9X with Gruvin9x board 9X avec carte Gruvin9x - - + + Support for SD memory card Support de la carte SD - + Support for DSM2 modules using ppm instead of true serial Support pour les modules DSM2 par le signal PPM - - - + + + Enable HELI menu and cyclic mix support Activer le menu hélico et les mixages CCPM @@ -8564,8 +9102,8 @@ The OpenTX Team. L'équipe OpenTX. - - + + @@ -8573,12 +9111,12 @@ L'équipe OpenTX. Erreur de synchronisation - + No SD directory configured! Aucun dossier SD configuré ! - + No Radio connected! Aucune radio connectée ! @@ -9077,16 +9615,19 @@ Profil ID: [%1]; Radio ID: [%2] RadioNotFoundDialog + No Radio Found Radio non détectée + <html><head/><body><p>No Radio was found!</p><p>Make sure that you hold the lower trim buttons towards the center while you turn it on.</p><p>Then connect the USB wire.</p><p><span style=" font-family:'arial,sans-serif'; font-size:13px; font-style:italic; color:#222222; background-color:#ffffff;">Note: if you have a Taranis that has not had the firmware upgraded to 2.0 then this version of Companion will not work.</span></p></body></html> <html><head/><body><p>Aucune radio détectée !</p><p>Veuillez vous assurer de maintenir les 2 trims horizontaux vers l'intérieur lors de la mise sous tension de la radio.</p><p>Ensuite connecter le câble USB.</p><p><span style=" font-family:'arial,sans-serif'; font-size:13px; font-style:italic; color:#222222; background-color:#ffffff;">Note: Cette version de Companion ne doit être utilisée pour éditer des réglages que si la version du firmware de la radio est au moins 2.0.</span></p></body></html> + OK @@ -9095,31 +9636,43 @@ Profil ID: [%1]; Radio ID: [%2] RadioOutputsWidget + + Form Formulaire + + View: Vue: + + Logical Switches Inters Logiques + + Global Variables Variables Globales + + Channel Outputs Sorties Voies + + L o g @@ -9130,6 +9683,8 @@ L + + G l o @@ -9141,6 +9696,8 @@ G + + C h a @@ -9201,156 +9758,187 @@ E Setup + Center beep Bip de centrage + OFF + Model Image Image du modèle + Exponential Exponentiel + Throttle Trim Idle Only Trim ralenti uniquement + Timer 3 Chrono 3 + Extra Fine Extra fin + Fine Fin + Medium Moyen + Coarse Grossier + Display Checklist Afficher la checklist + Timer 2 Chrono 2 + Timer 1 Chrono 1 + Never Jamais + On change Au changement + Always Toujours + Global Functions Fonctions globales + Throttle Source Source des gaz + Trim Step Pas des trims + Trims Display Affichage des trims + Warnings Avertissements + Top LCD Timer Chrono LCD supérieur + Switch Warnings Positions des interrupteurs + Pot Warnings Positions des potentiomètres + Manual Manuel + Auto + Model Modèle + Extended Limits Débattements étendus + Extended Trims Trims étendus + Throttle Warning Alerte gaz + Reverse throttle operation. If this is checked the throttle will be reversed. Idle will be forward, trim will also be reversed and the throttle warning will be reversed as well. @@ -9362,6 +9950,7 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo + Reverse Throttle Gaz inversés @@ -9581,6 +10170,8 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo SimulatedUIWidgetX7 + + Taranis X7 Simulator Simulateur Taranis X7 @@ -9801,155 +10392,424 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo Appuyer Sel.Rot. + + SimulatorDialog + + + Companion Simulator + Simulateur Companion + + + + Radio Simulator + + + + + Show Help/Keymap (F1) + + + + + Show Help/Keymap + + + + + Keymap + + + + + F1 + + + + + help + + + + + Open the Joystick Settings window (F3) + + + + + Joystick Configuration + + + + + Joystick Config. + + + + + F3 + + + + + joystick + + + + + Open Telemetry Simulator window (F4) + + + + + Telemetry Simulator + Simulateur de télémesure + + + + Telemetry Sim. + + + + + F4 + + + + + telemetry + + + + + Open Trainer Simulator window (F5) + + + + + Trainer Simulator + Simulateur d'écolage + + + + Trainer Sim. + + + + + F5 + + + + + trainer + + + + + Open Debug Console window (F6) + + + + + + Debug Console + + + + + F6 + + + + + debug + + + + + Reload Lua Scripts (F7) + + + + + Reload Lua Scripts + Recharger le script Lua + + + + Reload Lua + + + + + F7 + + + + + reloadLua + + + + + Save a screenshot of the radio LCD screen (F8) + + + + + LCD Screenshot + Capture LCD + + + + Screenshot + Capture d'écran + + + + F8 + + + + + lcdScreenshot + + + + + Reload all radio data (F9) + + + + + Reload Radio Data + Recharger les données radio + + + + Reload Radio + + + + + F9 + + + + + reloadradio + + + SimulatorMainWindow + + OpenTx Simulator Simulateur OpenTX + + View Vue + + Radio Window Fenêtre radio + + Reload... Recharger... + + Tools Outils + + Toolbar Barre d'outils + + Reload Lua Scripts Recharger le script Lua + + Reload the Lua environment on the simulated radio. Recharger l'environnement Lua dans le simulateur. + + F7 + + Reload Radio Data Recharger les données radio + + Reload all radio data without restarting the simulator. Recharger les données radio sans redémarrer le simulateur. + + F9 + + Key Mapping Raccourcis clavier + + Show keyboard maping reference. Afficher les raccourcis clavier. + + F1 + + Joystick Settings Paramètres joystick + + Open joystick configuration settings dialog. Ouvrir la boite de dialogue de la configuration du joystick. + + F3 + + LCD Screenshot Capture LCD + + Save a screenshot of the current simulated LCD screen. Enregistrez une capture de l'écran LCD actuellement simulé. + + F8 + + Dock In Main Window Ancrer dans la fenêtre principale + + Show the radio in the main window or as a separate "floating" window. Afficher la radio dans la fenêtre principale ou comme une fenêtre "flottante" séparée. + + Menu Bar Barre de menus + + Show or hide the top menu bar. Afficher ou masquer la barre de menus. + + Alt+M + + Constrain Width Contraindre la largeur + + Set radio widget width to be a fixed size. Défini la largeur du widget radio comme étant une taille fixe. + + Constrain Height Contraindre la hauteur + + Set radio widget height to be a fixed size. Défini la hauteur du widget radio comme étant une taille fixe. @@ -10018,21 +10878,29 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo SimulatorStartupDialog + + OpenTX Simulator - Startup Options Simulateur OpenTX - Options de démarrage + + Simulator Startup Options: Options de démarrage: + + Radio Profile: Profil Radio: + + Existing radio profiles are shown here.<br /> Create or edit profiles using the Companion application. Les profils existants sont affichés ici.<br /> @@ -10040,11 +10908,15 @@ Créer ou éditer les profils avec l'application Companion. + + Radio Type: Type de Radio: + + Existing radio simulators are shown here.<br /> The radio type specified in the selected profile is used by default. Les simulateurs radios existants sont affichés ici.<br /> @@ -10052,26 +10924,36 @@ Le type de radio choisi par défaut est celui défini dans le profil selectionn + + Data Source: Source Données: + + Data File: Fichier Données: + + Data Folder: Répertoire Données: + + SD Image Path: Répertoire Image SD: + + Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> <b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! Fichier de données utilisé (.bin/.eeprom/.otx).Un nouveau fichier avec une nouvelle image sera créé si nécessaire.<br /> @@ -10079,6 +10961,8 @@ Le type de radio choisi par défaut est celui défini dans le profil selectionn + + Select data file... Choisir le fichier de données... @@ -10086,11 +10970,19 @@ Le type de radio choisi par défaut est celui défini dans le profil selectionn + + + + + + ... + + Directory containing RADIO and MODELS folders to use.<br /> New folder(s) with default radio/model will be created here if necessary. Chemin contenant les répertoires RADIO et MODELS à utiliser.<br /> @@ -10098,11 +10990,15 @@ Un (ou plusieurs) répertoire peut être créé ici si nécessaire. + + Select data folder... Sélectionner le répertoire de données... + + Directory containing the SD card image to use.<br/> The default is configured in the chosen Radio Profile. Répertoire contenant l'image de la carte SD.<br/> @@ -10110,26 +11006,36 @@ La valeur par défaut est configurée dans le profil radio sélectionné. + + Select SD card image folder... Choisir le répertoire contenant l'image de la carte SD... + + Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. Choisir la source (Fichier/Répertoire/Image SD) du type de donnée utilisé par le simulateur. + + File Fichier + + Folder Répertoire + + SD Path Image SD @@ -10143,6 +11049,8 @@ La valeur par défaut est configurée dans le profil radio sélectionné.SimulatorWidget + + Companion Simulator Simulateur Companion @@ -10231,6 +11139,8 @@ La valeur par défaut est configurée dans le profil radio sélectionné. + + ... @@ -10337,180 +11247,219 @@ La valeur par défaut est configurée dans le profil radio sélectionné.Telemetry + A1 + A2 + RSSI + Alarm 1 Alarme 1 + + ---- ---- + + Yellow Jaune + + Orange Orange + + Red Rouge + Alarm 2 Alarme 2 + Serial Protocol Protocole Série + Volt source Source de mesure de tension + Current source Source de mesure de courant + Protocol Protocole + None Aucun + FrSky Sensor Hub Sensor Hub FrSky + Blades Pales + Sink Max Chute max + Climb Max Montée max + Sink Min Chute min + Climb Min Montée min + Center Silent Neutre silencieux + Vario source Source vario + Vario limits Limites vario + Altimetry Altitude + Altitude source Source de l'altitude + Volts source Source de la tension + Top Bar Barre de titre de l'écran d'accueil + mAh + A + Various Divers + Sensors Capteurs + Disable multi sensor handling Désactiver la gestion des capteurs multiples + mAh count Valeur enregistrée + FAS Offset Décalage FAS + Persistent mAh Mémorisation des mAh @@ -10519,107 +11468,133 @@ La valeur par défaut est configurée dans le profil radio sélectionné.TelemetryAnalog + Unit Unité + Max Value Valeur Max + Alarm 1 Alarme 1 + + ---- + + Yellow Jaune + + Orange + + Red Rouge + + < + + > + Alarm 2 Alarme 2 + Offset Décalage + Volts (V) Tension (V) + Amps (A) Courant (A) + Speed (m/s or ft/s) Vitesse (m/s ou ft/s) + Raw (-) Chiffres bruts (-) + Speed (km/h or miles/h) Vitesse (km/h ou miles/h) + Meters (m or ft) Distance (m ou ft) + Temp (°) Température (°) + Fuel (%) Carburant (%) + mAmps (mA) Courant (mA) @@ -10633,6 +11608,7 @@ La valeur par défaut est configurée dans le profil radio sélectionné.TelemetryCustomScreen + Custom Screen Type Type d'écran personnalisé @@ -10658,21 +11634,25 @@ La valeur par défaut est configurée dans le profil radio sélectionné. + Min + Source + Gauge Jauge + Max @@ -10781,76 +11761,91 @@ La valeur par défaut est configurée dans le profil radio sélectionné.TelemetrySensor + Form Formulaire + Custom Prédéfini + Calculated Calculé + Id + Instance + Add Addition + Average Moyenne + Min + Max + Multiply Multiplication + Totalize Totalisation + Cell Element LiPo + Consumption Consommation + Dist Distance + Cells Sensor : Capteur d'éléments: @@ -10863,191 +11858,236 @@ La valeur par défaut est configurée dans le profil radio sélectionné. + + + + + + + + --- + GPS Sensor : Capteur GPS: + Alt. Sensor : Capteur d'altitude: + Sensor : Capteur: + V + A + mA + kt + m/s + ft/s + km/h + mph + m + ft + °C + °F + % + mAh + W + mW + dBm + g + ° + Rad + mL + US fl.Oz. + Raw (-) Chiffres bruts (-) + RPM Tours/minute + Precision Précision + Ratio + Blades Pales + Offset Décalage + Multiplier Multiplicateur + Auto Offset Offset auto + Filter Filtre + Persistent Persistant + Positive + Logs @@ -11079,86 +12119,120 @@ La valeur par défaut est configurée dans le profil radio sélectionné.TelemetrySimulator + + Telemetry Simulator Simulateur de télémesure + + VFAS + + RSSI + + SWR + + Simulate Simuler + + Replay SD Log File Rejouer le fichier de Log SD + + Replay rate Vitesse + + |> + + <| + + > + + <- + + X + + 1/5x + + 5x + + No Log File Currently Loaded Pas de fichier de Log chargé + + Load Charger + + Row # Timestamp Ligne # @@ -11166,6 +12240,8 @@ Horodatage + + RxBt @@ -11173,6 +12249,12 @@ Horodatage + + + + + + V / ratio @@ -11190,105 +12272,175 @@ Horodatage + + + + + + + + + + + + + + + + + + + + + + + + + + <html><head/><body><p><br/></p></body></html> + + + + Volts + + Db dB + + Curr Courant + + Amps + + Cels Elément + + A1 + + A2 + + ASpd + + + + km/h + + A3 + + GAlt + + + + Meters Mètres + + A4 + + GSpd + + Tmp1 + + Deg. C + + Hdg + + Lat,Lon (dec.deg.) + + dd-MM-yyyy hh:mm:ss jj-MM-aaaa @@ -11296,41 +12448,57 @@ hh:mm:ss + + Degrees + + Tmp2 + + °C + + Date + + GPS + + Fuel Carburant + + % + + AccX @@ -11338,52 +12506,78 @@ hh:mm:ss + + + + + + G + + Fuel Qty Qté Carburant + + ml + + AccY + + VSpd Vitesse Verticale + + m/s + + AccZ + + Alt Altitude + + + + RPM + + When enabled, sends any non-blank values as simulated telemetry data. Transmet les valeurs non vides au simulateur. @@ -11642,11 +12836,13 @@ hh:mm:ss Timer + Countdown Compte à rebours + Minute Call Annonces minutes @@ -11693,26 +12889,31 @@ hh:mm:ss Trainer + Form Formulaire + Mode + Input Entrée + Weight Ratio + Rud Dir @@ -11725,6 +12926,14 @@ hh:mm:ss + + + + + + + + Beeper volume 0 - Quiet. No beeps at all. @@ -11745,6 +12954,10 @@ Extra long : bips extra longs. + + + + Off @@ -11753,6 +12966,10 @@ Extra long : bips extra longs. + + + + += (Sum) += (Additionner) @@ -11761,6 +12978,10 @@ Extra long : bips extra longs. + + + + := (Replace) := (Remplacer) @@ -11769,6 +12990,10 @@ Extra long : bips extra longs. + + + + chn1 VOIE1 @@ -11777,6 +13002,10 @@ Extra long : bips extra longs. + + + + chn2 VOIE2 @@ -11785,6 +13014,10 @@ Extra long : bips extra longs. + + + + chn3 VOIE3 @@ -11793,21 +13026,28 @@ Extra long : bips extra longs. + + + + chn4 VOIE4 + Ele Prf + Thr Gaz + Ail @@ -11816,6 +13056,8 @@ Extra long : bips extra longs. TrainerSimulator + + Trainer simulator Simulateur d'écolage @@ -12204,11 +13446,14 @@ Extra long : bips extra longs. + + Port + List all available programmers. Lister tous les programmateurs supportés. @@ -12217,12 +13462,17 @@ Extra long : bips extra longs. + + + + The location of the AVRDUDE executable. The location of the AVRDUDE.EXE executable. Chemin d'accès de l'exécutable AVRDUDE. + DFU-Util Location Chemin de DFU-UTIL @@ -12230,11 +13480,15 @@ Extra long : bips extra longs. + + + Use this button to browse and look for the AVRDUDE executable file. Utiliser ce bouton pour parcourir à la recherche du fichier exécutable AVRDUDE.EXE. + Programmer used for communicating with the controller. Please consult the programmer's documentation and the AVRDUDE documentation to select the appropriate programmer. Programmateur utilisé pour la communication avec le contrôleur. @@ -12242,6 +13496,7 @@ Consulter la documentation du programmateur utilisé et celle d'AVRDUDE pou + Communication port to the programmer. Port de communication pour le programmateur. @@ -12249,31 +13504,37 @@ Consulter la documentation du programmateur utilisé et celle d'AVRDUDE pou + MCU Processeur + at91sam3s8-9xr + Alternate device Dispositif alternatif + Use advanced controls Utiliser les contrôles avancés + Extra Arguments Paramètres supplémentaires + Show Help Aide @@ -12281,6 +13542,9 @@ Consulter la documentation du programmateur utilisé et celle d'AVRDUDE pou + + + Browse... Parcourir... @@ -12323,12 +13587,15 @@ Consulter la documentation du programmateur utilisé et celle d'AVRDUDE pou + List Available Affiche Liste + + Extra arguments used in AVRDUDE. This can be used for providing extra information to AVRDUDE. @@ -12340,16 +13607,19 @@ A n'utiliser qu'en connaissance de cause: il n'y a pas de contrô + AVRDUDE Location Emplacement d'AVRDUDE + Show AVRDUDE help Affiche l'aide d'AVRDUDE + Programmer Configuration Configuration AVRDUDE / SAM-BA Configuration du programmateur @@ -12357,6 +13627,8 @@ A n'utiliser qu'en connaissance de cause: il n'y a pas de contrô + + Extra arguments that will be passed to AVRDUDE on every call Paramètres complémentaires passés à chaque appel d'AVRDUDE @@ -12367,23 +13639,29 @@ A n'utiliser qu'en connaissance de cause: il n'y a pas de contrô + Location of AVRDUDE executable Chemin d'accès de l'exécutable AVRDUDE + Programmer Programmateur + + CPU of your TX CPU de l'émetteur + + CPU present on your 9x radio Should be m64 for stock radios m2560 for v4.1 boards @@ -12391,22 +13669,27 @@ m2560 for v4.1 boards + SAM-BA Location Emplacement de SAM-BA + + Location of sam-ba executable Emplacement de l'exécutable SAM-BA + ARM MCU Processeur ARM + sam-ba serial port Port série de SAM-BA @@ -12415,42 +13698,55 @@ m2560 for v4.1 boards customizeSplashDialog + Transmitter Splash Screen Editor Editeur d'écran d'accueil + + Invert Inverser + + Load FW Ouvrir le firmware + + Load Pict Ouvrir l'image + + Load Profile Charger le profil + + Save Sauvegarder + + Open Splash Library Ouvrir la bibliothèque des écrans d'accueil @@ -12459,6 +13755,10 @@ m2560 for v4.1 boards + + + + ... @@ -12540,6 +13840,7 @@ m2560 for v4.1 boards downloadDialog + Downloading: Téléchargement: @@ -12563,11 +13864,15 @@ m2560 for v4.1 boards joystickDialog + + Configure Joystick Configuration du Joystick + + Ch2 VOIE2 @@ -12580,6 +13885,22 @@ m2560 for v4.1 boards + + + + + + + + + + + + + + + + Not Assigned Non assignée @@ -12592,6 +13913,22 @@ m2560 for v4.1 boards + + + + + + + + + + + + + + + + Right Vertical Droit Vertical @@ -12604,6 +13941,22 @@ m2560 for v4.1 boards + + + + + + + + + + + + + + + + Right Horizontal Droit Horizontal @@ -12616,6 +13969,22 @@ m2560 for v4.1 boards + + + + + + + + + + + + + + + + Left Vertical Gauche Vertical @@ -12628,6 +13997,22 @@ m2560 for v4.1 boards + + + + + + + + + + + + + + + + Left Horizontal Gauche Horizontal @@ -12640,6 +14025,22 @@ m2560 for v4.1 boards + + + + + + + + + + + + + + + + P1 @@ -12652,6 +14053,22 @@ m2560 for v4.1 boards + + + + + + + + + + + + + + + + P2 @@ -12664,6 +14081,22 @@ m2560 for v4.1 boards + + + + + + + + + + + + + + + + P3/LS @@ -12676,66 +14109,106 @@ m2560 for v4.1 boards + + + + + + + + + + + + + + + + RS + + Ch1 VOIE1 + + Ch4 VOIE4 + + Ch6 VOIE6 + + Ch3 VOIE3 + + Ch5 VOIE5 + + Ch7 VOIE7 + + Ch8 VOIE8 + + Instructions + + Enable Actif + + Cancel Annuler + + Back Précédent + + Start Démarrer @@ -12746,6 +14219,8 @@ m2560 for v4.1 boards + + Ok OK From 1f1098e270d69068fdc9ce692e86c4f0bfb60ccf Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Mon, 20 Mar 2017 17:51:02 +0100 Subject: [PATCH 002/203] Lua getValue() docs updated (fixed source links for 2.2 added) --- radio/src/lua/api_general.cpp | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/radio/src/lua/api_general.cpp b/radio/src/lua/api_general.cpp index 498dea2de..1d69b2568 100644 --- a/radio/src/lua/api_general.cpp +++ b/radio/src/lua/api_general.cpp @@ -514,11 +514,14 @@ static int luaGetFieldInfo(lua_State * L) Returns the value of a source. -The list of valid sources is available: -* for OpenTX 2.0.x at http://downloads-20.open-tx.org/firmware/lua_fields.txt -* for OpenTX 2.1.x at http://downloads-21.open-tx.org/firmware/lua_fields.txt (depreciated) -* for OpenTX 2.1.x Taranis and Taranis Plus at http://downloads-21.open-tx.org/firmware/lua_fields_taranis.txt -* for OpenTX 2.1.x Taranis X9E at http://downloads-21.open-tx.org/firmware/lua_fields_taranis_x9e.txt +The list of fixed sources: + +| OpenTX Version | Radio | +|----------------|-------| +| 2.0 | [all](http://downloads-20.open-tx.org/firmware/lua_fields.txt) | +| 2.1 | [X9D and X9D+](http://downloads-21.open-tx.org/firmware/lua_fields_taranis.txt), [X9E](http://downloads-21.open-tx.org/firmware/lua_fields_taranis_x9e.txt) | +| 2.2 | [X9D and X9D+](http://downloads.open-tx.org/2.2/firmware/lua_fields_x9d.txt), [X9E](http://downloads.open-tx.org/2.2/firmware/lua_fields_x9e.txt), [Horus](http://downloads.open-tx.org/2.2/firmware/lua_fields_x12s.txt) | + In OpenTX 2.1.x the telemetry sources no longer have a predefined name. To get a telemetry value simply use it's sensor name. For example: From 8375304d618384d5e8e0c78940df92050a896349 Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Tue, 21 Mar 2017 07:42:00 +0100 Subject: [PATCH 003/203] Several fixes for Lua Widgets and Themes options (#4648) --- radio/src/gui/480x272/widget.h | 1 + radio/src/lua/widgets.cpp | 24 +++++++++++++++++++----- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/radio/src/gui/480x272/widget.h b/radio/src/gui/480x272/widget.h index d13b79d7d..d5a14156e 100644 --- a/radio/src/gui/480x272/widget.h +++ b/radio/src/gui/480x272/widget.h @@ -106,6 +106,7 @@ class WidgetFactory if (options) { int i = 0; for (const ZoneOption * option = options; option->name; option++) { + TRACE("WidgetFactory::initPersistentData() setting option '%s'", option->name); // TODO compiler bug? The CPU freezes ... persistentData->options[i++] = option->deflt; memcpy(&persistentData->options[i++], &option->deflt, sizeof(ZoneOptionValue)); } diff --git a/radio/src/lua/widgets.cpp b/radio/src/lua/widgets.cpp index 5f9d30a28..fcedeaefd 100644 --- a/radio/src/lua/widgets.cpp +++ b/radio/src/lua/widgets.cpp @@ -47,9 +47,10 @@ void exec(int function, int nresults=0) } } -ZoneOption * createOptionsArray(int reference) +ZoneOption * createOptionsArray(int reference, uint8_t maxOptions) { if (reference == 0) { + // TRACE("createOptionsArray() no options"); return NULL; } @@ -59,6 +60,12 @@ ZoneOption * createOptionsArray(int reference) count++; } + // TRACE("we have %d options", count); + if (count > maxOptions) { + count = maxOptions; + // TRACE("limited to %d options", count); + } + ZoneOption * options = (ZoneOption *)malloc(sizeof(ZoneOption) * (count+1)); if (!options) { return NULL; @@ -67,7 +74,8 @@ ZoneOption * createOptionsArray(int reference) PROTECT_LUA() { lua_rawgeti(lsWidgets, LUA_REGISTRYINDEX, reference); ZoneOption * option = options; - for (lua_pushnil(lsWidgets); lua_next(lsWidgets, -2); lua_pop(lsWidgets, 1)) { + for (lua_pushnil(lsWidgets); lua_next(lsWidgets, -2), count-- > 0; lua_pop(lsWidgets, 1)) { + // TRACE("parsing option %d", count); luaL_checktype(lsWidgets, -2, LUA_TNUMBER); // key is number luaL_checktype(lsWidgets, -1, LUA_TTABLE); // value is table uint8_t field = 0; @@ -77,11 +85,13 @@ ZoneOption * createOptionsArray(int reference) luaL_checktype(lsWidgets, -2, LUA_TNUMBER); // key is number luaL_checktype(lsWidgets, -1, LUA_TSTRING); // value is string option->name = lua_tostring(lsWidgets, -1); + // TRACE("name = %s", option->name); break; case 1: luaL_checktype(lsWidgets, -2, LUA_TNUMBER); // key is number luaL_checktype(lsWidgets, -1, LUA_TNUMBER); // value is number option->type = (ZoneOption::Type)lua_tointeger(lsWidgets, -1); + // TRACE("type = %d", option->type); if (option->type > ZoneOption::Color) { // wrong type option->type = ZoneOption::Integer; @@ -98,6 +108,7 @@ ZoneOption * createOptionsArray(int reference) if (option->type == ZoneOption::Integer) { luaL_checktype(lsWidgets, -1, LUA_TNUMBER); // value is number option->deflt.signedValue = lua_tointeger(lsWidgets, -1); + // TRACE("default signed = %d", option->deflt.signedValue); } else if (option->type == ZoneOption::Source || option->type == ZoneOption::TextSize || @@ -105,13 +116,16 @@ ZoneOption * createOptionsArray(int reference) option->type == ZoneOption::Color) { luaL_checktype(lsWidgets, -1, LUA_TNUMBER); // value is number option->deflt.unsignedValue = lua_tounsigned(lsWidgets, -1); + // TRACE("default unsigned = %u", option->deflt.unsignedValue); } else if (option->type == ZoneOption::Bool) { luaL_checktype(lsWidgets, -1, LUA_TNUMBER); // value is number option->deflt.boolValue = (lua_tounsigned(lsWidgets, -1) != 0); + // TRACE("default bool = %d", (int)(option->deflt.boolValue)); } else if (option->type == ZoneOption::String) { - strncpy(option->deflt.stringValue, lua_tostring(lsWidgets, -1), sizeof(option->deflt.stringValue)-1); + str2zchar(option->deflt.stringValue, lua_tostring(lsWidgets, -1), sizeof(option->deflt.stringValue)); // stringValue is ZCHAR + // TRACE("default string = %s", lua_tostring(lsWidgets, -1)); } break; case 3: @@ -219,7 +233,7 @@ void luaLoadThemeCallback() } if (name) { - ZoneOption * options = createOptionsArray(themeOptions); + ZoneOption * options = createOptionsArray(themeOptions, MAX_THEME_OPTIONS); if (options) { LuaTheme * theme = new LuaTheme(name, options); theme->loadFunction = loadFunction; @@ -426,7 +440,7 @@ void luaLoadWidgetCallback() } if (name && createFunction) { - ZoneOption * options = createOptionsArray(widgetOptions); + ZoneOption * options = createOptionsArray(widgetOptions, MAX_WIDGET_OPTIONS); if (options) { LuaWidgetFactory * factory = new LuaWidgetFactory(name, options, createFunction); factory->updateFunction = updateFunction; From 52e65179a8e91c91407439110c035a56df509d3f Mon Sep 17 00:00:00 2001 From: 3djc Date: Tue, 21 Mar 2017 07:43:13 +0100 Subject: [PATCH 004/203] Tools for 2.2 release handling (#4649) * Scripts * No suffix for docker image * generate sdcard file to subdirectories to match companion changes * Massively increase options for simus backup lua_fields info for lua docs * Allow both nightly and release to be built * $ ambiguity * Cleanup * Tidy up * Cosmetics --- tools/build-companion.sh | 21 +++---- tools/nightly22/build-sdcard.sh | 12 ++-- tools/release22/build-release.sh | 54 ++++++++++++++++ tools/release22/build-sdcard.sh | 47 ++++++++++++++ tools/release22/tts.py | 104 +++++++++++++++++++++++++++++++ tools/release22/tts_common.py | 14 +++++ 6 files changed, 234 insertions(+), 18 deletions(-) create mode 100755 tools/release22/build-release.sh create mode 100644 tools/release22/build-sdcard.sh create mode 100755 tools/release22/tts.py create mode 100644 tools/release22/tts_common.py diff --git a/tools/build-companion.sh b/tools/build-companion.sh index 6ebf5fa84..998d073b3 100755 --- a/tools/build-companion.sh +++ b/tools/build-companion.sh @@ -25,16 +25,13 @@ done SRCDIR=$1 OUTDIR=$2 -COMMON_OPTIONS="-DALLOW_NIGHTLY_BUILDS=YES -DVERSION_SUFFIX=$3 -DGVARS=YES -DHELI=YES" +COMMON_OPTIONS="-DALLOW_NIGHTLY_BUILDS=YES -DGVARS=YES -DHELI=YES -DLUA=YES -DMULTIMODULE=YES -DTELEMETRY=FRSKY -DPPM_LIMITS_SYMETRICAL=YES -DVARIO=YES -DGAUGES=YES -DAUTOSWITCH=YES -DAUTOSOURCE=YES -DAUDIO=YES -DGPS=YES -DPPM_CENTER_ADJUSTABLE=YES -DFLIGHT_MODES=YES -DOVERRIDE_CHANNEL_FUNCTION=YES -DFRSKY_STICKS=YES" if [ "$(uname)" = "Darwin" ]; then COMMON_OPTIONS="${COMMON_OPTIONS} -DCMAKE_PREFIX_PATH=~/Qt/5.7/clang_64/ -DCMAKE_OSX_DEPLOYMENT_TARGET='10.9'" fi -STM32_OPTIONS="${COMMON_OPTIONS} -DLUA=YES" - -if [ "$3" == "" ]; then - echo "Usage $0 SRCDIR OUTDIR VERSION_SUFFIX" - exit 1 +if [ "$3" != "" ]; then + COMMON_OPTIONS="${COMMON_OPTIONS} -DVERSION_SUFFIX=$3" fi rm -rf build @@ -56,22 +53,22 @@ make -j${JOBS} libsimulator cmake ${COMMON_OPTIONS} -DPCB=9XRPRO ${SRCDIR} make -j${JOBS} libsimulator -cmake ${STM32_OPTIONS} -DPCB=X7 ${SRCDIR} +cmake ${COMMON_OPTIONS} -DPCB=X7 ${SRCDIR} make -j${JOBS} libsimulator -cmake ${STM32_OPTIONS} -DPCB=X9D ${SRCDIR} +cmake ${COMMON_OPTIONS} -DPCB=X9D ${SRCDIR} make -j${JOBS} libsimulator -cmake ${STM32_OPTIONS} -DPCB=X9D+ ${SRCDIR} +cmake ${COMMON_OPTIONS} -DPCB=X9D+ ${SRCDIR} make -j${JOBS} libsimulator -cmake ${STM32_OPTIONS} -DPCB=X9E ${SRCDIR} +cmake ${COMMON_OPTIONS} -DPCB=X9E ${SRCDIR} make -j${JOBS} libsimulator -cmake ${STM32_OPTIONS} -DPCB=X10 ${SRCDIR} +cmake ${COMMON_OPTIONS} -DPCB=X10 ${SRCDIR} make -j${JOBS} libsimulator -cmake ${STM32_OPTIONS} -DPCB=X12S ${SRCDIR} +cmake ${COMMON_OPTIONS} -DPCB=X12S ${SRCDIR} make -j${JOBS} libsimulator make -j${JOBS} package diff --git a/tools/nightly22/build-sdcard.sh b/tools/nightly22/build-sdcard.sh index ea343ea39..897401350 100644 --- a/tools/nightly22/build-sdcard.sh +++ b/tools/nightly22/build-sdcard.sh @@ -8,9 +8,9 @@ output=/var/www/html/2.2/nightly # Handle opentx.sdcard.version sdcard_version="2.2V"$(grep 'set(SDCARD_REVISION' ${workdir}/code/CMakeLists.txt | grep -o '".*"' | sed 's/"//g') -echo $sdcard_version > ${workdir}/code/radio/sdcard/horus/opentx.sdcard.version -echo $sdcard_version > ${workdir}/code/radio/sdcard/taranis-x9/opentx.sdcard.version -echo $sdcard_version > ${workdir}/code/radio/sdcard/taranis-x7/opentx.sdcard.version +echo ${sdcard_version} > ${workdir}/code/radio/sdcard/horus/opentx.sdcard.version +echo ${sdcard_version} > ${workdir}/code/radio/sdcard/taranis-x9/opentx.sdcard.version +echo ${sdcard_version} > ${workdir}/code/radio/sdcard/taranis-x7/opentx.sdcard.version if cmp --silent ${workdir}/code/radio/sdcard/horus/opentx.sdcard.version ${workdir}/opentx.sdcard.version then @@ -40,8 +40,8 @@ else mkdir ${workdir}/sdcard/taranis-x7/SOUNDS cp -r ${workdir}/sdcard/horus/SOUNDS ${workdir}/sdcard/taranis-x9/ cp -r ${workdir}/sdcard/horus/SOUNDS ${workdir}/sdcard/taranis-x7/ - cd ${workdir}/sdcard/horus && zip -r ${output}/sdcard/sdcard-horus-$sdcard_version.zip * - cd ${workdir}/sdcard/taranis-x9 && zip -r ${output}/sdcard/sdcard-taranis-x9-$sdcard_version.zip * - cd ${workdir}/sdcard/taranis-x7 && zip -r ${output}/sdcard/sdcard-taranis-x7-$sdcard_version.zip * + cd ${workdir}/sdcard/horus && zip -r ${output}/sdcard/sdcard-horus-${sdcard_version}.zip * + cd ${workdir}/sdcard/taranis-x9 && zip -r ${output}/sdcard/sdcard-taranis-x9-${sdcard_version}.zip * + cd ${workdir}/sdcard/taranis-x7 && zip -r ${output}/sdcard/sdcard-taranis-x7-${sdcard_version}.zip * rm -Rf ${workdir}/sdcard fi diff --git a/tools/release22/build-release.sh b/tools/release22/build-release.sh new file mode 100755 index 000000000..f069690c6 --- /dev/null +++ b/tools/release22/build-release.sh @@ -0,0 +1,54 @@ +#!/bin/bash + +set -e + +branch=master +docker=release22 +workdir=/home/opentx/release22 +output=/var/www/html/2.2 +version=2.2.0 + +cd ${workdir} + +# Create on-demand build environment +cp code/radio/util/Dockerfile . +docker build -t new-${docker} . +docker rmi -f ${docker} || true +docker tag new-${docker} ${docker} +docker rmi -f new-${docker} + +# Call sdcard generation +code/tools/release22/build-sdcard.sh + +# Build Linux companion +docker run -dit --name companion -v /home/opentx/${docker}:/opentx ${docker} +docker exec companion sh -c "mkdir -p build && cd build && cmake /opentx/code && cp radio/src/stamp.h /opentx/binaries/stamp-opentx.txt" +docker exec companion rm -rf build +docker exec companion /opentx/code/tools/build-companion.sh /opentx/code /opentx/binaries/ +docker stop companion +docker rm companion +cp -f binaries/*.deb ${output}/companion/linux/companion22_${version}_amd64.deb +cp -f binaries/radio/src/lua/lua_fields_*.txt ${output}/firmware + +# Request companion compilation on Windows +cd ${output}/companion/windows +wget -qO- http://winbox.open-tx.org/companion-builds/compile22.php?branch=$branch +wget -O companion-windows-${version}.exe http://winbox.open-tx.org/companion-builds/companion-windows-${version}.exe +chmod -f g+w companion-windows-${version.exe + +# Request companion compilation on Mac OS X +cd ${output}/companion/macosx +wget -qO- http://opentx.blinkt.de:8080/~opentx/build-opentx.py?branch=${branch} +wget -O opentx-companion-${version}.dmg http://opentx.blinkt.de:8080/~opentx/builds/opentx-companion-${version}.dmg +chmod -f g+w opentx-companion-${version}.dmg + +# Update stamps +cp -f $workdir/binaries/stamp-opentx.txt ${output}/firmware +rm -f ${output}/companion/windows/companion-windows.stamp +echo "#define VERSION "'"2.2.0"' >> ${output}/companion/windows/companion-windows.stamp +cp -f ${output}/companion/windows/companion-windows.stamp ${output}/companion/linux/companion-windows.stamp +cp -f ${output}/companion/windows/companion-windows.stamp ${output}/companion/linux/companion-macosx.stamp + +# Clean binaries It will be hosting built on demand firmware +rm -rf $workdir/binaries/* +rm -rf $workdir/binaries/.lock diff --git a/tools/release22/build-sdcard.sh b/tools/release22/build-sdcard.sh new file mode 100644 index 000000000..e7718f8f2 --- /dev/null +++ b/tools/release22/build-sdcard.sh @@ -0,0 +1,47 @@ +#!/bin/bash + +set -e + +branch=master +workdir=/home/opentx/release22 +output=/var/www/html/2.2 + +# Handle opentx.sdcard.version +sdcard_version="2.2V"$(grep 'set(SDCARD_REVISION' ${workdir}/code/CMakeLists.txt | grep -o '".*"' | sed 's/"//g') +echo ${sdcard_version} > ${workdir}/code/radio/sdcard/horus/opentx.sdcard.version +echo ${sdcard_version} > ${workdir}/code/radio/sdcard/taranis-x9/opentx.sdcard.version +echo ${sdcard_version} > ${workdir}/code/radio/sdcard/taranis-x7/opentx.sdcard.version + +if cmp --silent ${workdir}/code/radio/sdcard/horus/opentx.sdcard.version ${workdir}/opentx.sdcard.version +then + exit +else + cp -r ${workdir}/code/radio/sdcard/horus/opentx.sdcard.version ${workdir} + cd ${workdir} + + # Copy git sdcard data + rm -Rf ${workdir}/sdcard + cp -r ${workdir}/code/radio/sdcard . + + # Get images for Horus + mkdir -p ${workdir}/sdcard/horus/IMAGES + cp /home/opentx/horus-bitmaps/* ${workdir}/sdcard/horus/IMAGES/ + + # Request sound pack generation + python3 -B ${workdir}/code/tools/release22/tts.py en csv files + python3 -B ${workdir}/code/tools/release22/tts.py fr csv files + python3 -B ${workdir}/code/tools/release22/tts.py es csv files + python3 -B ${workdir}/code/tools/release22/tts.py it csv files + python3 -B ${workdir}/code/tools/release22/tts.py de csv files + + # Create sdcards.zips for supported platforms + mv /tmp/SOUNDS ${workdir}/sdcard/horus/ + mkdir ${workdir}/sdcard/taranis-x9/SOUNDS + mkdir ${workdir}/sdcard/taranis-x7/SOUNDS + cp -r ${workdir}/sdcard/horus/SOUNDS ${workdir}/sdcard/taranis-x9/ + cp -r ${workdir}/sdcard/horus/SOUNDS ${workdir}/sdcard/taranis-x7/ + cd ${workdir}/sdcard/horus && zip -r ${output}/sdcard/x12/sdcard-horus-${sdcard_version}.zip * + cd ${workdir}/sdcard/taranis-x9 && zip -r ${output}/sdcard/x9/sdcard-taranis-x9-${sdcard_version}.zip * + cd ${workdir}/sdcard/taranis-x7 && zip -r ${output}/sdcard/x7/sdcard-taranis-x7-${sdcard_version}.zip * + rm -Rf ${workdir}/sdcard +fi diff --git a/tools/release22/tts.py b/tools/release22/tts.py new file mode 100755 index 000000000..4f2bbcfe0 --- /dev/null +++ b/tools/release22/tts.py @@ -0,0 +1,104 @@ +#!/usr/bin/env python +# -*- coding: utf-8 -*- + + +# This script is a modified version to support Linux TTS fiel genration using PicoTTS + +# Sound pack maintainers (incomplete list) by language alphabetical order +# Czech : Martin Hotar +# French : Bertrand Songis & André Bernet +# English : Rob Thompson & Martin Hotar +# German : Romolo Manfredini (Some corrections by Peer) +# Italian : Romolo Manfredini +# Portuguese : Romolo Manfredini +# Spanish : Romolo Manfredini (With the help of Jose Moreno) + +# from __future__ import print_function + +import os +import sys +import subprocess +import zipfile +from tts_common import * +board = "taranis" + +lib_path = os.path.abspath(os.path.join('code', 'radio', 'util')) +sys.path.append(lib_path) + +def generate(str, filename): + + command = "pico2wave -l=" + voice + " -w=" + filename + " \"" + str + "\"" + os.system(command.encode('utf-8')) + +################################################################ + +if __name__ == "__main__": + + + if "en" in sys.argv: + from tts_en import systemSounds, sounds + + directory = "en" + voice = "en-US" + + elif "fr" in sys.argv: + from tts_fr import systemSounds, sounds + + directory = "fr" + voice = "fr-FR" + + elif "it" in sys.argv: + from tts_it import systemSounds, sounds + + directory = "it" + voice = "it-IT" + + elif "de" in sys.argv: + from tts_de import systemSounds, sounds + + directory = "de" + voice = "de-DE" + + elif "es" in sys.argv: + from tts_es import systemSounds, sounds + + directory = "es" + voice = "es-ES" + + else: + print("which language?") + exit() + + if "csv" in sys.argv: + path = "/tmp/SOUNDS/" + directory + "/SYSTEM/" + if not os.path.exists(path): + os.makedirs(path) + os.chdir(path) + with open("%s-%s.csv" % (voice, board), "wb") as csvFile: + for s, f in systemSounds: + if s and f: + l = u"" + if board in ("sky9x", "taranis"): + l += u"SOUNDS/%s/SYSTEM;" % directory + l += f + u";" + s + u"\n" + csvFile.write(l.encode("utf-8")) + for s, f in sounds: + if s and f: + l = u"" + if board in ("sky9x", "taranis"): + l += u"SOUNDS/%s;" % directory + l += f + u";" + s + u"\n" + csvFile.write(l.encode("utf-8")) + + if "files" in sys.argv: + path = "/tmp/SOUNDS/" + directory + "/SYSTEM/" + if not os.path.exists(path): + os.makedirs(path) + os.chdir(path) + for s, f in systemSounds: + if s and f: + generate(s, f) + os.chdir("..") + for s, f in sounds: + if s and f: + generate(s, f) diff --git a/tools/release22/tts_common.py b/tools/release22/tts_common.py new file mode 100644 index 000000000..25623b005 --- /dev/null +++ b/tools/release22/tts_common.py @@ -0,0 +1,14 @@ +NO_ALTERNATE = 1024 +PROMPT_CUSTOM_BASE = 256 +PROMPT_SYSTEM_BASE = 0 +board = "taranis" + +import sys + +def filename(idx, alternate=0): + ext = ".wav" + if isinstance(idx, int): + result = "%04d%s" % (idx, ext) + elif board in ('sky9x', 'taranis'): + result = idx + ext + return result From 4aa0c1bbe495e88ac15e66c8d79a5d32ae35dd65 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Tue, 21 Mar 2017 02:43:40 -0400 Subject: [PATCH 005/203] [simulation] Fix some potential crashes & 26 memory leaks, improve LCD redraws. (#4634) * [simulation] Hardening: Fix some potential crashes & 26 memory leaks, improve LCD performance. * [simpgmspace] Init trims; Make sure `REa` is really defined (to match board files). * [simpgmspace][opentxsimulator] Verify current running state before start/stop; Move rotary enc. init. * [simpgmspace][LcdWidget] Improve performance by moving LCD content change check to lcdRefresh() & limiting LcdWidget refresh time to 60 fps max. * [simueeprom] Ensure thread could be started, set default running state to false. * [simufatfs] Fix paths report trace. * [eepromimportexport] Fix memory leaks resulting from import debugging scheme being used. * [customdebug] Introduce new scheme for custom debug output in compliance with Qt recommendations (see docs for QLoggingCategory). * [opentxeeprom] Fix extra conversion table cache elements being created and also not properly deleted (and hence leaking). * [opentxinterface] Unregister EEpromInterfaces in unregisterOpenTxFirmwares(); * [storage] Unregister storage factories on exit (fixes leak); create virtual StorageFormat/StorageFactory destructors (prevents warnings). * [helpers] GVarGroup now emits own signal, no need to pass ModelPanel pointer (removes dependency on modeledit.h) * [DebugOutput] Clear simulator trace hook before exiting (prevent possible issues); Fix leak and possible bad QString allocations when reading from buffer; Fix leak with combo box event filter. * [TelemetrySimulator] Fix leak by deleting LogPlaybackController object on exit; Only set up data fields once; convert timers to static. * [build] Consolidate all Companion/Simulator shared items in `common` library to reduce build time/etc (node & edge still remain awkward). * [simulatorwidget] Delete removed spacer object (previously-forgotten "26th" leak). * [DebugOutput] Fix stray trailing characters issue with new text buffer allocation (from previous commit); Increase maximum buffer sizes to better accommodate slower systems. * Cosmetics. --- companion/src/CMakeLists.txt | 29 +++++------ companion/src/companion.cpp | 5 +- companion/src/customdebug.cpp | 36 ++++++++++++++ companion/src/customdebug.h | 14 +++--- companion/src/eepromimportexport.h | 22 ++++----- .../src/firmwares/opentx/opentxeeprom.cpp | 49 ++++++++++--------- .../src/firmwares/opentx/opentxinterface.cpp | 1 + companion/src/helpers.cpp | 24 ++++++--- companion/src/helpers.h | 33 +++---------- companion/src/macros.h | 8 ++- companion/src/modeledit/CMakeLists.txt | 8 +-- companion/src/modeledit/channels.cpp | 5 +- companion/src/simulation/debugoutput.cpp | 12 +++-- companion/src/simulation/debugoutput.h | 9 ++-- .../src/simulation/simulatormainwindow.cpp | 2 + companion/src/simulation/simulatorwidget.cpp | 2 + companion/src/simulation/simulatorwidget.h | 1 + companion/src/simulation/telemetrysimu.cpp | 48 ++++++++---------- companion/src/simulation/telemetrysimu.h | 9 ++-- companion/src/simulation/widgets/lcdwidget.h | 38 ++++++++------ companion/src/simulator.cpp | 4 ++ companion/src/storage/firmwareinterface.cpp | 2 + companion/src/storage/storage.cpp | 41 ++++++++++------ companion/src/storage/storage.h | 28 ++++++----- radio/src/targets/simu/opentxsimulator.cpp | 23 ++------- radio/src/targets/simu/simpgmspace.cpp | 29 +++++++++-- radio/src/targets/simu/simueeprom.cpp | 14 ++++-- radio/src/targets/simu/simufatfs.cpp | 4 +- 28 files changed, 290 insertions(+), 210 deletions(-) create mode 100644 companion/src/customdebug.cpp diff --git a/companion/src/CMakeLists.txt b/companion/src/CMakeLists.txt index 40dd6ce2b..9233a1486 100644 --- a/companion/src/CMakeLists.txt +++ b/companion/src/CMakeLists.txt @@ -124,7 +124,9 @@ add_subdirectory(thirdparty/qxtcommandoptions) set(common_SRCS appdebugmessagehandler.cpp boards.cpp + customdebug.cpp eeprominterface.cpp + helpers.cpp radiodata.cpp firmwares/er9x/er9xeeprom.cpp firmwares/er9x/er9xinterface.cpp @@ -132,21 +134,25 @@ set(common_SRCS firmwares/ersky9x/ersky9xinterface.cpp firmwares/opentx/opentxeeprom.cpp firmwares/opentx/opentxinterface.cpp + modeledit/node.cpp # used in simulator + modeledit/edge.cpp # used by node ) set(common_MOC_HDRS appdebugmessagehandler.h + helpers.h + modeledit/node.h ) qt5_wrap_cpp(common_SRCS ${common_MOC_HDRS}) add_library(common ${common_SRCS}) qt5_use_modules(common Core Xml Widgets) +target_link_libraries(common simulation) ############# Companion ############### set(companion_SRCS - helpers.cpp helpers_html.cpp mdichild.cpp modelslist.cpp @@ -206,7 +212,6 @@ set(companion_MOC_HDRS mdichild.h mainwindow.h radionotfound.h - helpers.h wizarddialog.h modelprinter.h multimodelprinter.h @@ -259,9 +264,9 @@ qt5_wrap_ui(companion_SRCS ${companion_UIS}) qt5_wrap_cpp(companion_SRCS ${companion_MOC_HDRS}) qt5_add_translation(companion_QM ${companion_TS}) qt5_add_resources(companion_RCC ${companion_RESOURCES}) -add_custom_target(gen_qrc DEPENDS ${companion_RCC}) +add_custom_target(gen_qrc DEPENDS ${companion_RCC} ${companion_QM}) -add_executable(${COMPANION_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${companion_SRCS} ${companion_RCC} ${companion_QM}) +add_executable(${COMPANION_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${companion_SRCS} ${companion_RCC}) add_dependencies(${COMPANION_NAME} gen_qrc) qt5_use_modules(${COMPANION_NAME} Core Widgets Network) @@ -272,19 +277,7 @@ PrintTargetReport("${COMPANION_NAME}") ############# Standalone simulator ############### -set(simu_SRCS - modeledit/node.cpp - modeledit/edge.cpp - helpers.cpp - simulator.cpp - ) - -set(simu_MOC_HDRS - modeledit/node.h - helpers.h - ) - -qt5_wrap_cpp(simu_SRCS ${simu_MOC_HDRS} ) +set(simu_SRCS simulator.cpp ) if(WIN32) list(APPEND simu_SRCS icon.rc) @@ -293,7 +286,7 @@ endif() add_executable(${SIMULATOR_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${simu_SRCS} ${companion_RCC}) add_dependencies(${SIMULATOR_NAME} gen_qrc) -target_link_libraries(${SIMULATOR_NAME} PRIVATE simulation common shared storage qxtcommandoptions ${PTHREAD_LIBRARY} ${SDL_LIBRARY} ${WIN_LINK_LIBRARIES}) +target_link_libraries(${SIMULATOR_NAME} PRIVATE simulation common storage qxtcommandoptions ${PTHREAD_LIBRARY} ${SDL_LIBRARY} ${WIN_LINK_LIBRARIES}) ############# Translations #################### diff --git a/companion/src/companion.cpp b/companion/src/companion.cpp index 6f58684f1..718ab2b06 100644 --- a/companion/src/companion.cpp +++ b/companion/src/companion.cpp @@ -28,6 +28,7 @@ #endif #include "appdebugmessagehandler.h" +#include "customdebug.h" #include "mainwindow.h" #include "version.h" #include "appdata.h" @@ -65,6 +66,8 @@ int main(int argc, char *argv[]) if (AppDebugMessageHandler::instance()) AppDebugMessageHandler::instance()->installAppMessageHandler(); + CustomDebug::setFilterRules(); + g.init(); QStringList strl = QApplication::arguments(); @@ -134,7 +137,7 @@ int main(int argc, char *argv[]) unregisterSimulators(); unregisterOpenTxFirmwares(); - unregisterEEpromInterfaces(); + unregisterStorageFactories(); #if defined(JOYSTICKS) || defined(SIMU_AUDIO) SDL_Quit(); diff --git a/companion/src/customdebug.cpp b/companion/src/customdebug.cpp new file mode 100644 index 000000000..3447364e6 --- /dev/null +++ b/companion/src/customdebug.cpp @@ -0,0 +1,36 @@ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "customdebug.h" + +Q_LOGGING_CATEGORY(eepromImport, "eeprom.import") + +void CustomDebug::setFilterRules() +{ + QString rules; + rules.append("eeprom.import="); +#if defined(DEBUG_STORAGE_IMPORT) + rules.append("true"); +#else + rules.append("false"); +#endif + + QLoggingCategory::setFilterRules(rules); +} diff --git a/companion/src/customdebug.h b/companion/src/customdebug.h index e082ede9d..84a68e66e 100644 --- a/companion/src/customdebug.h +++ b/companion/src/customdebug.h @@ -21,15 +21,15 @@ #ifndef _CUSTOMDEBUG_H_ #define _CUSTOMDEBUG_H_ -#include +#include // Controls the generation of debug output for EEPROM import -#if defined(DEBUG_STORAGE_IMPORT) - inline QDebug eepromImportDebug() { return QDebug(QtDebugMsg); } -#else - #undef eepromImportDebug - inline QNoDebug eepromImportDebug() { return QNoDebug(); } -#endif +Q_DECLARE_LOGGING_CATEGORY(eepromImport) +class CustomDebug +{ + public: + static void setFilterRules(); +}; #endif // _CUSTOMDEBUG_H_ diff --git a/companion/src/eepromimportexport.h b/companion/src/eepromimportexport.h index 4898927bc..96c1d2fd9 100644 --- a/companion/src/eepromimportexport.h +++ b/companion/src/eepromimportexport.h @@ -181,7 +181,7 @@ class BaseUnsignedField: public DataField { if (input[i]) field |= ((container)1<: 0x%3(%4)").arg(name).arg(N).arg(field, 0, 16).arg(field); + qCDebug(eepromImport) << QString("\timported %1<%2>: 0x%3(%4)").arg(name).arg(N).arg(field, 0, 16).arg(field); } virtual unsigned int size() @@ -238,7 +238,7 @@ class BoolField: public DataField { virtual void ImportBits(const QBitArray & input) { field = input[0] ? true : false; - eepromImportDebug() << QString("\timported %1<%2>: 0x%3(%4)").arg(name).arg(N).arg(field, 0, 16).arg(field); + qCDebug(eepromImport) << QString("\timported %1<%2>: 0x%3(%4)").arg(name).arg(N).arg(field, 0, 16).arg(field); } virtual unsigned int size() @@ -308,7 +308,7 @@ class SignedField: public DataField { } field = (int)value; - eepromImportDebug() << QString("\timported %1<%2>: 0x%3(%4)").arg(name).arg(N).arg(field, 0, 16).arg(field); + qCDebug(eepromImport) << QString("\timported %1<%2>: 0x%3(%4)").arg(name).arg(N).arg(field, 0, 16).arg(field); } virtual unsigned int size() @@ -369,7 +369,7 @@ class CharField: public DataField { } field[i] = idx; } - eepromImportDebug() << QString("\timported %1<%2>: '%3'").arg(name).arg(N).arg(field); + qCDebug(eepromImport) << QString("\timported %1<%2>: '%3'").arg(name).arg(N).arg(field); } virtual unsigned int size() @@ -427,7 +427,7 @@ class ZCharField: public DataField { else break; } - eepromImportDebug() << QString("\timported %1<%2>: '%3'").arg(name).arg(N).arg(field); + qCDebug(eepromImport) << QString("\timported %1<%2>: '%3'").arg(name).arg(N).arg(field); } virtual unsigned int size() @@ -453,7 +453,7 @@ class StructField: public DataField { } inline void Append(DataField * field) { - //eepromImportDebug() << QString("StructField(%1) appending field: %2").arg(name).arg(field->getName()); + //qCDebug(eepromImport) << QString("StructField(%1) appending field: %2").arg(name).arg(field->getName()); fields.append(field); } @@ -471,7 +471,7 @@ class StructField: public DataField { virtual void ImportBits(const QBitArray & input) { - eepromImportDebug() << QString("\timporting %1[%2]:").arg(name).arg(fields.size()); + qCDebug(eepromImport) << QString("\timporting %1[%2]:").arg(name).arg(fields.size()); int offset = 0; foreach(DataField *field, fields) { unsigned int size = field->size(); @@ -526,7 +526,7 @@ class TransformedField: public DataField { virtual void ImportBits(const QBitArray & input) { - eepromImportDebug() << QString("\timporting TransformedField %1:").arg(field.getName()); + qCDebug(eepromImport) << QString("\timporting TransformedField %1:").arg(field.getName()); field.ImportBits(input); afterImport(); } @@ -564,7 +564,7 @@ class ConversionTable { after = 0; for (std::list::iterator it=exportTable.begin(); it!=exportTable.end(); it++) { - ConversionTuple tuple = *it; + ConversionTuple & tuple = *it; if (before == tuple.a) { after = tuple.b; return true; @@ -579,7 +579,7 @@ class ConversionTable { after = 0; for (std::list::iterator it=importTable.begin(); it!=importTable.end(); it++) { - ConversionTuple tuple = *it; + ConversionTuple & tuple = *it; if (before == tuple.b) { after = tuple.a; return true; @@ -756,7 +756,7 @@ class ConversionField: public TransformedField { if (scale) { field *= scale; } - eepromImportDebug() << QString("\timported ConversionField<%1>:").arg(internalField.getName()) << QString(" before: %1, after: %2").arg(_field).arg(field); + qCDebug(eepromImport) << QString("\timported ConversionField<%1>:").arg(internalField.getName()) << QString(" before: %1, after: %2").arg(_field).arg(field); } protected: diff --git a/companion/src/firmwares/opentx/opentxeeprom.cpp b/companion/src/firmwares/opentx/opentxeeprom.cpp index 08deb1caa..151d8b580 100644 --- a/companion/src/firmwares/opentx/opentxeeprom.cpp +++ b/companion/src/firmwares/opentx/opentxeeprom.cpp @@ -160,6 +160,7 @@ class SwitchesConversionTable: public ConversionTable { } } + protected: void addConversion(const RawSwitch & sw, const int b) @@ -199,7 +200,7 @@ class SwitchesConversionTable: public ConversionTable { static SwitchesConversionTable * getInstance(Board::Type board, unsigned int version, unsigned long flags=0) { for (std::list::iterator it=internalCache.begin(); it!=internalCache.end(); it++) { - Cache element = *it; + Cache & element = *it; if (element.board == board && element.version == version && element.flags == flags) return element.table; } @@ -211,8 +212,9 @@ class SwitchesConversionTable: public ConversionTable { static void Cleanup() { for (std::list::iterator it=internalCache.begin(); it!=internalCache.end(); it++) { - Cache element = *it; - delete element.table; + Cache & element = *it; + if (element.table) + delete element.table; } internalCache.clear(); } @@ -386,7 +388,7 @@ class SourcesConversionTable: public ConversionTable { static SourcesConversionTable * getInstance(Board::Type board, unsigned int version, unsigned int variant, unsigned long flags=0) { for (std::list::iterator it=internalCache.begin(); it!=internalCache.end(); it++) { - Cache element = *it; + Cache & element = *it; if (element.board == board && element.version == version && element.variant == variant && element.flags == flags) return element.table; } @@ -398,8 +400,9 @@ class SourcesConversionTable: public ConversionTable { static void Cleanup() { for (std::list::iterator it=internalCache.begin(); it!=internalCache.end(); it++) { - Cache element = *it; - delete element.table; + Cache & element = *it; + if (element.table) + delete element.table; } internalCache.clear(); } @@ -439,7 +442,7 @@ class SwitchField: public ConversionField< SignedField > { { ConversionField< SignedField >::afterImport(); sw = RawSwitch(_switch); - eepromImportDebug() << QString("imported %1: %2").arg(ConversionField< SignedField >::internalField.getName()).arg(sw.toString(board)); + qCDebug(eepromImport) << QString("imported %1: %2").arg(ConversionField< SignedField >::internalField.getName()).arg(sw.toString(board)); } protected: @@ -565,7 +568,7 @@ class TelemetrySourceField: public ConversionField< UnsignedField > { { ConversionField< UnsignedField >::afterImport(); source = (_source == 0 ? RawSource(0) : RawSource(SOURCE_TYPE_TELEMETRY, _source-1)); - eepromImportDebug() << QString("imported %1: %2").arg(ConversionField< UnsignedField >::internalField.getName()).arg(source.toString()); + qCDebug(eepromImport) << QString("imported %1: %2").arg(ConversionField< UnsignedField >::internalField.getName()).arg(source.toString()); } protected: @@ -601,7 +604,7 @@ class SourceField: public ConversionField< UnsignedField > { { ConversionField< UnsignedField >::afterImport(); source = RawSource(_source); - eepromImportDebug() << QString("imported %1: %2").arg(ConversionField< UnsignedField >::internalField.getName()).arg(source.toString()); + qCDebug(eepromImport) << QString("imported %1: %2").arg(ConversionField< UnsignedField >::internalField.getName()).arg(source.toString()); } protected: @@ -760,7 +763,7 @@ class CurveReferenceField: public TransformedField { { curve.type = (CurveReference::CurveRefType)_curve_type; curve.value = smallGvarToC9x(_curve_value); - eepromImportDebug() << QString("imported CurveReference(%1)").arg(curve.toString()); + qCDebug(eepromImport) << QString("imported CurveReference(%1)").arg(curve.toString()); } protected: @@ -942,7 +945,7 @@ class FlightModeField: public TransformedField { } } } - eepromImportDebug() << QString("imported %1: '%2'").arg(internalField.getName()).arg(phase.name); + qCDebug(eepromImport) << QString("imported %1: '%2'").arg(internalField.getName()).arg(phase.name); } protected: @@ -1231,7 +1234,7 @@ class MixField: public TransformedField { } if (mix.carryTrim < 0) mix.carryTrim = 0; } - eepromImportDebug() << QString("imported %1: ch %2, name '%3'").arg(internalField.getName()).arg(mix.destCh).arg(mix.name); + qCDebug(eepromImport) << QString("imported %1: ch %2, name '%3'").arg(internalField.getName()).arg(mix.destCh).arg(mix.name); } protected: @@ -1412,7 +1415,7 @@ class InputField: public TransformedField { else expo.curve = CurveReference(CurveReference::CURVE_REF_FUNC, _curveParam); } - eepromImportDebug() << QString("imported %1: ch %2 name '%3'").arg(internalField.getName()).arg(expo.chn).arg(expo.name); + qCDebug(eepromImport) << QString("imported %1: ch %2 name '%3'").arg(internalField.getName()).arg(expo.chn).arg(expo.name); } protected: @@ -1626,7 +1629,7 @@ class CurvesField: public TransformedField { for (int j=0; jcount; j++) curve->points[j].x = -100 + (200*i) / (curve->count-1); } - eepromImportDebug() << QString("imported curve: %3 points").arg(curve->count); + qCDebug(eepromImport) << QString("imported curve: %3 points").arg(curve->count); } } @@ -1955,7 +1958,7 @@ class LogicalSwitchField: public TransformedField { } } } - eepromImportDebug() << QString("imported %1: %2").arg(internalField.getName()).arg(csw.funcToString()); + qCDebug(eepromImport) << QString("imported %1: %2").arg(internalField.getName()).arg(csw.funcToString()); } protected: @@ -2115,7 +2118,7 @@ class SwitchesWarningField: public TransformedField { else { sw = _sw; } - eepromImportDebug() << QString("imported %1").arg(internalField.getName()); + qCDebug(eepromImport) << QString("imported %1").arg(internalField.getName()); } protected: @@ -2350,7 +2353,7 @@ class ArmCustomFunctionField: public TransformedField { else { fn.param = value; } - eepromImportDebug() << QString("imported %1").arg(internalField.getName()); + qCDebug(eepromImport) << QString("imported %1").arg(internalField.getName()); } protected: @@ -2539,7 +2542,7 @@ class AvrCustomFunctionField: public TransformedField { else if (version >= 213) fn.repeatParam = _active * 10; } - eepromImportDebug() << QString("imported %1").arg(internalField.getName()); + qCDebug(eepromImport) << QString("imported %1").arg(internalField.getName()); } protected: @@ -2634,7 +2637,7 @@ class FrskyScreenField: public DataField { virtual void ImportBits(const QBitArray & input) { - eepromImportDebug() << QString("importing %1: type: %2").arg(name).arg(screen.type); + qCDebug(eepromImport) << QString("importing %1: type: %2").arg(name).arg(screen.type); // NOTA: screen.type should have been imported first! if (IS_ARM(board) && version >= 217) { @@ -3007,7 +3010,7 @@ class SensorField: public TransformedField { sensor.unit++; } - eepromImportDebug() << QString("imported %1").arg(internalField.getName()); + qCDebug(eepromImport) << QString("imported %1").arg(internalField.getName()); } protected: @@ -3041,7 +3044,7 @@ OpenTxModelData::OpenTxModelData(ModelData & modelData, Board::Type board, unsig { sprintf(name, "Model %s", modelData.name); - eepromImportDebug() << QString("OpenTxModelData::OpenTxModelData(name: %1, board: %2, ver: %3, var: %4)").arg(name).arg(board).arg(version).arg(variant); + qCDebug(eepromImport) << QString("OpenTxModelData::OpenTxModelData(name: %1, board: %2, ver: %3, var: %4)").arg(name).arg(board).arg(version).arg(variant); if (IS_HORUS(board)) internalField.Append(new ZCharField<15>(this, modelData.name, "Model name")); @@ -3452,7 +3455,7 @@ void OpenTxModelData::beforeExport() void OpenTxModelData::afterImport() { - eepromImportDebug() << QString("OpenTxModelData::afterImport()") << modelData.name; + qCDebug(eepromImport) << QString("OpenTxModelData::afterImport()") << modelData.name; if (IS_TARANIS(board) && version < 216) { for (unsigned int i=0; i diff --git a/companion/src/helpers.cpp b/companion/src/helpers.cpp index cadbd56ce..59eda22df 100644 --- a/companion/src/helpers.cpp +++ b/companion/src/helpers.cpp @@ -31,10 +31,12 @@ #include "appdata.h" #include "helpers.h" -#include "modeledit/modeledit.h" #include "simulatormainwindow.h" #include "storage/sdcard.h" +#include +#include + Stopwatch gStopwatch("global"); const QColor colors[CPN_MAX_CURVES] = { @@ -126,7 +128,11 @@ void populatePhasesCB(QComboBox *b, int value) b->setCurrentIndex(value + getCurrentFirmware()->getCapability(FlightModes)); } -GVarGroup::GVarGroup(QCheckBox * weightGV, QAbstractSpinBox * weightSB, QComboBox * weightCB, int & weight, const ModelData & model, const int deflt, const int mini, const int maxi, const double step, bool allowGvars, ModelPanel * panel): +/* + * GVarGroup +*/ + +GVarGroup::GVarGroup(QCheckBox * weightGV, QAbstractSpinBox * weightSB, QComboBox * weightCB, int & weight, const ModelData & model, const int deflt, const int mini, const int maxi, const double step, bool allowGvars): QObject(), weightGV(weightGV), weightSB(weightSB), @@ -135,8 +141,7 @@ GVarGroup::GVarGroup(QCheckBox * weightGV, QAbstractSpinBox * weightSB, QComboBo weightCB(weightCB), weight(weight), step(step), - lock(true), - panel(panel) + lock(true) { if (allowGvars && getCurrentFirmware()->getCapability(Gvars)) { populateGVCB(*weightCB, weight, model); @@ -200,12 +205,15 @@ void GVarGroup::valuesChanged() weight = sb->value(); else weight = round(dsb->value()/step); - if (panel) - emit panel->modified(); + emit valueChanged(); } } +/* + * CurveGroup +*/ + CurveGroup::CurveGroup(QComboBox * curveTypeCB, QCheckBox * curveGVarCB, QComboBox * curveValueCB, QSpinBox * curveValueSB, CurveReference & curve, const ModelData & model, unsigned int flags): QObject(), curveTypeCB(curveTypeCB), @@ -364,6 +372,10 @@ void CurveGroup::valuesChanged() } } +/* + * Helpers +*/ + void populateGvarUseCB(QComboBox *b, unsigned int phase) { b->addItem(QObject::tr("Own value")); diff --git a/companion/src/helpers.h b/companion/src/helpers.h index eab93e8a7..c9a0b5170 100644 --- a/companion/src/helpers.h +++ b/companion/src/helpers.h @@ -22,7 +22,6 @@ #define _HELPERS_H_ #include "eeprominterface.h" -#include "modeledit/modeledit.h" #include #include #include @@ -69,7 +68,10 @@ class GVarGroup: public QObject { Q_OBJECT public: - GVarGroup(QCheckBox * weightGV, QAbstractSpinBox * weightSB, QComboBox * weightCB, int & weight, const ModelData & model, const int deflt, const int mini, const int maxi, const double step=1.0, bool allowGVars=true, ModelPanel * panel=NULL); + GVarGroup(QCheckBox * weightGV, QAbstractSpinBox * weightSB, QComboBox * weightCB, int & weight, const ModelData & model, const int deflt, const int mini, const int maxi, const double step=1.0, bool allowGVars=true); + + signals: + void valueChanged(); protected slots: void gvarCBChanged(int); @@ -84,7 +86,6 @@ class GVarGroup: public QObject { int & weight; double step; bool lock; - ModelPanel * panel; }; #define HIDE_DIFF 0x01 @@ -157,26 +158,6 @@ QString getFrSkySrc(int index); void startSimulation(QWidget * parent, RadioData & radioData, int modelIdx); -template -QVector findWidgets(QObject * object, const QString & name) -{ - QVector result; - QRegExp rx(name.arg("([0-9]+)")); - QList children = object->findChildren(); - foreach(T child, children) { - int pos = rx.indexIn(child->objectName()); - if (pos >= 0) { - QStringList list = rx.capturedTexts(); - int index = list[1].toInt(); - if (result.size() <= index) { - result.resize(index+1); - } - result[index] = child; - } - } - return result; -} - // Format a pixmap to fit on the current firmware QPixmap makePixMap(const QImage & image); @@ -249,13 +230,13 @@ public: void resizeColumnsToContents(); void setColumnWidth(int col, int width); - void pushRowsUp(int row); + void pushRowsUp(int row); private: #if defined(TABLE_LAYOUT) - QTableWidget * tableWidget; + QTableWidget * tableWidget; #else - QGridLayout * gridWidget; + QGridLayout * gridWidget; #endif }; diff --git a/companion/src/macros.h b/companion/src/macros.h index 7ff39a753..0b29f12c3 100644 --- a/companion/src/macros.h +++ b/companion/src/macros.h @@ -21,6 +21,10 @@ #ifndef _MACROS_H_ #define _MACROS_H_ -#define DIM(arr) (sizeof((arr))/sizeof((arr)[0])) +#include -#endif // _MACROS_H_ \ No newline at end of file +// #define DIM(arr) (sizeof((arr))/sizeof((arr)[0])) +// new way for c++11 +#define DIM(arr__) ((size_t)(std::end((arr__)) - std::begin((arr__)))) + +#endif // _MACROS_H_ diff --git a/companion/src/modeledit/CMakeLists.txt b/companion/src/modeledit/CMakeLists.txt index 945a68f96..20726bce9 100644 --- a/companion/src/modeledit/CMakeLists.txt +++ b/companion/src/modeledit/CMakeLists.txt @@ -23,8 +23,8 @@ set(modeledit_SRCS customfunctions.cpp # templates.cpp mixerslistwidget.cpp - node.cpp - edge.cpp + # node.cpp ## node and edge are built in common lib because also used by simulator + # edge.cpp ## commenting them here avoids a "duplicate target" warning eg. from ninja ) set(modeledit_HDRS @@ -36,7 +36,7 @@ set(modeledit_HDRS customfunctions.h # templates.h mixerslistwidget.h - node.h + # node.h ) set(modeledit_UIS @@ -53,7 +53,7 @@ foreach(name ${modeledit_NAMES}) set(modeledit_HDRS ${modeledit_HDRS} ${name}.h) set(modeledit_UIS ${modeledit_UIS} ${name}.ui) endforeach() - + qt5_wrap_ui(modeledit_SRCS ${modeledit_UIS}) qt5_wrap_cpp(modeledit_SRCS ${modeledit_HDRS}) diff --git a/companion/src/modeledit/channels.cpp b/companion/src/modeledit/channels.cpp index 2ca124c67..1cdfd5376 100644 --- a/companion/src/modeledit/channels.cpp +++ b/companion/src/modeledit/channels.cpp @@ -64,7 +64,8 @@ LimitsGroup::LimitsGroup(Firmware * firmware, TableLayout * tableLayout, int row horizontalLayout->addWidget(cb); horizontalLayout->addWidget(spinbox); tableLayout->addLayout(row, col, horizontalLayout); - gvarGroup = new GVarGroup(gv, spinbox, cb, value, model, deflt, min, max, displayStep, allowGVars, panel); + gvarGroup = new GVarGroup(gv, spinbox, cb, value, model, deflt, min, max, displayStep, allowGVars); + QObject::connect(gvarGroup, &GVarGroup::valueChanged, panel, &ModelPanel::modified); } LimitsGroup::~LimitsGroup() @@ -227,7 +228,7 @@ void Channels::refreshExtendedLimits() group->updateMinMax(10*channelMax); } - emit modified(); + emit modified(); } void Channels::invEdited() diff --git a/companion/src/simulation/debugoutput.cpp b/companion/src/simulation/debugoutput.cpp index 80013b527..0cb582fb1 100644 --- a/companion/src/simulation/debugoutput.cpp +++ b/companion/src/simulation/debugoutput.cpp @@ -71,7 +71,7 @@ DebugOutput::DebugOutput(QWidget * parent, SimulatorInterface *simulator): ui->filterText->addItem(fltr, "no_delete"); ui->filterText->setValidator(new DebugOutputFilterValidator(ui->filterText)); - ui->filterText->installEventFilter(new DeleteComboBoxItemEventFilter()); + ui->filterText->installEventFilter(new DeleteComboBoxItemEventFilter(this)); ui->actionShowFilterHelp->setIcon(SimulatorIcon("info")); ui->actionWordWrap->setIcon(SimulatorIcon("word_wrap")); @@ -115,6 +115,7 @@ DebugOutput::DebugOutput(QWidget * parent, SimulatorInterface *simulator): DebugOutput::~DebugOutput() { + m_simulator->installTraceHook(NULL); saveState(); if (AppDebugMessageHandler::instance()) @@ -173,15 +174,18 @@ void DebugOutput::restoreState() void DebugOutput::processBytesReceived() { + static char buf[512]; const QTextCursor savedCursor(ui->console->textCursor()); const int sbValue = ui->console->verticalScrollBar()->value(); const bool sbAtBottom = (sbValue == ui->console->verticalScrollBar()->maximum()); qint64 len; + QString text; - while ((len = m_dataBufferDevice->bytesAvailable()) > 0) { - QString text(m_dataBufferDevice->read(qMin(len, qint64(512)))); - if (text.isEmpty()) + while (m_dataBufferDevice && m_dataBufferDevice->bytesAvailable() > 0) { + len = m_dataBufferDevice->read(buf, sizeof(buf)); + if (len <= 0) break; + text = QString::fromLocal8Bit(buf, len); ui->console->moveCursor(QTextCursor::End); ui->console->textCursor().insertText(text); if (sbAtBottom) { diff --git a/companion/src/simulation/debugoutput.h b/companion/src/simulation/debugoutput.h index 72b51b9b4..6cf67acdc 100644 --- a/companion/src/simulation/debugoutput.h +++ b/companion/src/simulation/debugoutput.h @@ -29,14 +29,15 @@ #include #include -// NOTE : The buffer sizes need to be large enough to handle the flood of data when X12/X10 simulator starts up (almost 40K!). +// NOTE : The buffer sizes need to be large enough to handle the flood of data when X12/X10 simulator starts up with TRACE_SIMPGMSPACE=1 (> 40K!). +// These are maximum sizes, not necessarily allocated sizes. #ifndef DEBUG_OUTPUT_WIDGET_OUT_BUFF_SIZE // This buffer holds received and processed data until it can be printed to our console. - #define DEBUG_OUTPUT_WIDGET_OUT_BUFF_SIZE (40 * 1024) // [bytes] + #define DEBUG_OUTPUT_WIDGET_OUT_BUFF_SIZE (50 * 1024) // [bytes] #endif #ifndef DEBUG_OUTPUT_WIDGET_INP_BUFF_SIZE // This buffer is active if line filter is enabled and holds received data until it can be filtered and placed in output buffer. - #define DEBUG_OUTPUT_WIDGET_INP_BUFF_SIZE (30 * 1024) // [bytes] + #define DEBUG_OUTPUT_WIDGET_INP_BUFF_SIZE (50 * 1024) // [bytes] #endif namespace Ui { @@ -101,6 +102,8 @@ class DebugOutputFilterValidator : public QValidator class DeleteComboBoxItemEventFilter : public QObject { Q_OBJECT + public: + DeleteComboBoxItemEventFilter(QObject *parent = Q_NULLPTR) : QObject(parent) { } protected: bool eventFilter(QObject *obj, QEvent *event); }; diff --git a/companion/src/simulation/simulatormainwindow.cpp b/companion/src/simulation/simulatormainwindow.cpp index c530fc82c..a85f4b419 100644 --- a/companion/src/simulation/simulatormainwindow.cpp +++ b/companion/src/simulation/simulatormainwindow.cpp @@ -33,6 +33,8 @@ #endif #include +#include +#include extern AppData g; // ensure what "g" means diff --git a/companion/src/simulation/simulatorwidget.cpp b/companion/src/simulation/simulatorwidget.cpp index 55ab9adab..cdb23f3d9 100644 --- a/companion/src/simulation/simulatorwidget.cpp +++ b/companion/src/simulation/simulatorwidget.cpp @@ -38,6 +38,7 @@ #endif #include +#include #include SimulatorWidget::SimulatorWidget(QWidget * parent, SimulatorInterface *simulator, quint8 flags): @@ -99,6 +100,7 @@ SimulatorWidget::SimulatorWidget(QWidget * parent, SimulatorInterface *simulator keymapHelp.append(item); ui->radioUiWidget->layout()->removeItem(ui->radioUiTempSpacer); + delete ui->radioUiTempSpacer; ui->radioUiWidget->layout()->addWidget(radioUiWidget); radioUiWidget->setFocusPolicy(Qt::WheelFocus); radioUiWidget->setFocus(); diff --git a/companion/src/simulation/simulatorwidget.h b/companion/src/simulation/simulatorwidget.h index 69e798ec3..78c5d311b 100644 --- a/companion/src/simulation/simulatorwidget.h +++ b/companion/src/simulation/simulatorwidget.h @@ -26,6 +26,7 @@ #include "radiodata.h" #include "simulator.h" +#include #include #include diff --git a/companion/src/simulation/telemetrysimu.cpp b/companion/src/simulation/telemetrysimu.cpp index 46ff5f3e9..fb85ad25e 100644 --- a/companion/src/simulation/telemetrysimu.cpp +++ b/companion/src/simulation/telemetrysimu.cpp @@ -31,12 +31,12 @@ TelemetrySimulator::TelemetrySimulator(QWidget * parent, SimulatorInterface * si { ui->setupUi(this); - timer = new QTimer(this); - timer->setInterval(10); - connect(timer, SIGNAL(timeout()), this, SLOT(onTimerEvent())); + setupDataFields(); - logTimer = new QTimer(this); - connect(logTimer, SIGNAL(timeout()), this, SLOT(onLogTimerEvent())); + timer.setInterval(10); + connect(&timer, &QTimer::timeout, this, &TelemetrySimulator::generateTelemetryFrame); + + connect(&logTimer, &QTimer::timeout, this, &TelemetrySimulator::onLogTimerEvent); connect(ui->Simulate, SIGNAL(toggled(bool)), this, SLOT(onSimulateToggled(bool))); connect(ui->loadLogFile, SIGNAL(released()), this, SLOT(onLoadLogFile())); @@ -64,33 +64,27 @@ TelemetrySimulator::TelemetrySimulator(QWidget * parent, SimulatorInterface * si TelemetrySimulator::~TelemetrySimulator() { - timer->stop(); - logTimer->stop(); + timer.stop(); + logTimer.stop(); + delete logPlayback; delete ui; } void TelemetrySimulator::onSimulateToggled(bool isChecked) { if (isChecked) { - timer->start(); + timer.start(); } else { - timer->stop(); + timer.stop(); } } - void TelemetrySimulator::onLogTimerEvent() { logPlayback->stepForward(false); } - -void TelemetrySimulator::onTimerEvent() -{ - generateTelemetryFrame(); -} - void TelemetrySimulator::onLoadLogFile() { onStop(); // in case we are in playback mode @@ -100,7 +94,7 @@ void TelemetrySimulator::onLoadLogFile() void TelemetrySimulator::onPlay() { if (logPlayback->isReady()) { - logTimer->start(logPlayback->logFrequency * 1000 / SPEEDS[ui->replayRate->value()]); + logTimer.start(logPlayback->logFrequency * 1000 / SPEEDS[ui->replayRate->value()]); logPlayback->play(); } } @@ -108,7 +102,7 @@ void TelemetrySimulator::onPlay() void TelemetrySimulator::onRewind() { if (logPlayback->isReady()) { - logTimer->stop(); + logTimer.stop(); logPlayback->rewind(); } } @@ -116,7 +110,7 @@ void TelemetrySimulator::onRewind() void TelemetrySimulator::onStepForward() { if (logPlayback->isReady()) { - logTimer->stop(); + logTimer.stop(); logPlayback->stepForward(true); } } @@ -124,7 +118,7 @@ void TelemetrySimulator::onStepForward() void TelemetrySimulator::onStepBack() { if (logPlayback->isReady()) { - logTimer->stop(); + logTimer.stop(); logPlayback->stepBack(); } } @@ -132,7 +126,7 @@ void TelemetrySimulator::onStepBack() void TelemetrySimulator::onStop() { if (logPlayback->isReady()) { - logTimer->stop(); + logTimer.stop(); logPlayback->stop(); } } @@ -147,21 +141,21 @@ void TelemetrySimulator::onPositionIndicatorChanged(int value) void TelemetrySimulator::onReplayRateChanged(int value) { - if (logTimer->isActive()) { - logTimer->setInterval(logPlayback->logFrequency * 1000 / SPEEDS[ui->replayRate->value()]); + if (logTimer.isActive()) { + logTimer.setInterval(logPlayback->logFrequency * 1000 / SPEEDS[ui->replayRate->value()]); } } void TelemetrySimulator::closeEvent(QCloseEvent *event) { - timer->stop(); - logTimer->stop(); + timer.stop(); + logTimer.stop(); event->accept(); } #define SET_INSTANCE(control, id, def) ui->control->setText(QString::number(simulator->getSensorInstance(id, ((def) & 0x1F) + 1))) -void TelemetrySimulator::showEvent(QShowEvent *event) +void TelemetrySimulator::setupDataFields() { SET_INSTANCE(rxbt_inst, BATT_ID, 0); SET_INSTANCE(rssi_inst, RSSI_ID, 24); @@ -410,7 +404,7 @@ void TelemetrySimulator::generateTelemetryFrame() if (ok && (buffer[2] || buffer[3])) simulator->sendTelemetry(buffer, FRSKY_SPORT_PACKET_SIZE); else - onTimerEvent(); + generateTelemetryFrame(); } uint32_t TelemetrySimulator::FlvssEmulator::encodeCellPair(uint8_t cellNum, uint8_t firstCellNo, double cell1, double cell2) diff --git a/companion/src/simulation/telemetrysimu.h b/companion/src/simulation/telemetrysimu.h index bd0096ba8..42e63296f 100644 --- a/companion/src/simulation/telemetrysimu.h +++ b/companion/src/simulation/telemetrysimu.h @@ -49,9 +49,9 @@ class TelemetrySimulator : public QWidget protected slots: virtual void closeEvent(QCloseEvent *event); - virtual void showEvent(QShowEvent *event); + void setupDataFields(); void onSimulateToggled(bool isChecked); - void onTimerEvent(); + void generateTelemetryFrame(); void onLogTimerEvent(); void onLoadLogFile(); void onPlay(); @@ -65,10 +65,9 @@ class TelemetrySimulator : public QWidget protected: Ui::TelemetrySimulator * ui; - QTimer * timer; - QTimer * logTimer; + QTimer timer; + QTimer logTimer; SimulatorInterface *simulator; - void generateTelemetryFrame(); // protected classes follow diff --git a/companion/src/simulation/widgets/lcdwidget.h b/companion/src/simulation/widgets/lcdwidget.h index 355c9b5b5..879ce3236 100644 --- a/companion/src/simulation/widgets/lcdwidget.h +++ b/companion/src/simulation/widgets/lcdwidget.h @@ -26,10 +26,15 @@ #include #include #include +#include +#include +#include #include "appdata.h" #include "appdebugmessagehandler.h" +#define LCD_WIDGET_REFRESH_PERIOD 16 // [ms] 16 = 62.5fps + class LcdWidget : public QWidget { Q_OBJECT @@ -39,7 +44,7 @@ class LcdWidget : public QWidget LcdWidget(QWidget * parent = 0): QWidget(parent), lcdBuf(NULL), - previousBuf(NULL), + localBuf(NULL), lightEnable(false), bgDefaultColor(QColor(198, 208, 199)) { @@ -47,8 +52,8 @@ class LcdWidget : public QWidget ~LcdWidget() { - if (previousBuf) { - free(previousBuf); + if (localBuf) { + free(localBuf); } } @@ -62,8 +67,9 @@ class LcdWidget : public QWidget lcdSize = (width * height) * ((depth+7) / 8); else lcdSize = (width * ((height+7)/8)) * depth; - previousBuf = (unsigned char *)malloc(lcdSize); - memset(previousBuf, 0, lcdSize); + + localBuf = (unsigned char *)malloc(lcdSize); + memset(localBuf, 0, lcdSize); } void setBgDefaultColor(const QColor & color) @@ -102,10 +108,12 @@ class LcdWidget : public QWidget void onLcdChanged(bool light) { - if (light != lightEnable || memcmp(previousBuf, lcdBuf, lcdSize)) { - lightEnable = light; - memcpy(previousBuf, lcdBuf, lcdSize); + QMutexLocker locker(&lcdMtx); + lightEnable = light; + memcpy(localBuf, lcdBuf, lcdSize); + if (!redrawTimer.isValid() || redrawTimer.hasExpired(LCD_WIDGET_REFRESH_PERIOD)) { update(); + redrawTimer.start(); } } @@ -117,24 +125,26 @@ class LcdWidget : public QWidget int lcdSize; unsigned char *lcdBuf; - unsigned char *previousBuf; + unsigned char *localBuf; bool lightEnable; QColor bgColor; QColor bgDefaultColor; + QMutex lcdMtx; + QElapsedTimer redrawTimer; inline void doPaint(QPainter & p) { QRgb rgb; uint16_t z; - if (!lcdBuf) + if (!localBuf) return; if (lcdDepth == 16) { for (int x = 0; x < lcdWidth; x++) { for (int y = 0; y < lcdHeight; y++) { - z = ((uint16_t *)lcdBuf)[y * lcdWidth + x]; + z = ((uint16_t *)localBuf)[y * lcdWidth + x]; rgb = qRgb(255 * ((z & 0xF800) >> 11) / 0x1F, 255 * ((z & 0x07E0) >> 5) / 0x3F, 255 * (z & 0x001F) / 0x1F); @@ -147,7 +157,7 @@ class LcdWidget : public QWidget if (lcdDepth == 12) { for (int x = 0; x < lcdWidth; x++) { for (int y = 0; y < lcdHeight; y++) { - z = ((uint16_t *)lcdBuf)[y * lcdWidth + x]; + z = ((uint16_t *)localBuf)[y * lcdWidth + x]; rgb = qRgb(255 * ((z & 0xF00) >> 8) / 0x0F, 255 * ((z & 0x0F0) >> 4) / 0x0F, 255 * (z & 0x00F) / 0x0F); @@ -181,12 +191,12 @@ class LcdWidget : public QWidget mask = (1 << (y % 8)); for (int x = 0; x < lcdWidth; x++, idx++) { if (lcdDepth == 1) { - if (lcdBuf[idx] & mask) + if (localBuf[idx] & mask) p.drawRect(2 * x, 2 * y, 1, 1); continue; } // lcdDepth == 4 - z = (y & 1) ? (lcdBuf[idx] >> 4) : (lcdBuf[idx] & 0x0F); + z = (y & 1) ? (localBuf[idx] >> 4) : (localBuf[idx] & 0x0F); if (!z) continue; if (z != previousDepth) { diff --git a/companion/src/simulator.cpp b/companion/src/simulator.cpp index 3a767da7d..054c28179 100644 --- a/companion/src/simulator.cpp +++ b/companion/src/simulator.cpp @@ -34,6 +34,7 @@ #include "appdata.h" #include "appdebugmessagehandler.h" #include "constants.h" +#include "customdebug.h" #include "eeprominterface.h" #include "simulator.h" #include "simulatormainwindow.h" @@ -95,6 +96,8 @@ int main(int argc, char *argv[]) if (AppDebugMessageHandler::instance()) AppDebugMessageHandler::instance()->installAppMessageHandler(); + CustomDebug::setFilterRules(); + g.init(); QTranslator companionTranslator; @@ -257,6 +260,7 @@ int finish(int exitCode) qDebug() << "SIMULATOR EXIT" << exitCode; unregisterSimulators(); unregisterOpenTxFirmwares(); + unregisterStorageFactories(); #if defined(JOYSTICKS) || defined(SIMU_AUDIO) SDL_Quit(); diff --git a/companion/src/storage/firmwareinterface.cpp b/companion/src/storage/firmwareinterface.cpp index 0e0b222e2..2ba04471a 100644 --- a/companion/src/storage/firmwareinterface.cpp +++ b/companion/src/storage/firmwareinterface.cpp @@ -24,6 +24,8 @@ #include "helpers.h" #include "storage.h" +#include + #define FW_MARK "FW" #define VERS_MARK "VERS" #define DATE_MARK "DATE" diff --git a/companion/src/storage/storage.cpp b/companion/src/storage/storage.cpp index 936af71c5..0d19e1396 100644 --- a/companion/src/storage/storage.cpp +++ b/companion/src/storage/storage.cpp @@ -64,6 +64,12 @@ void registerStorageFactories() registerStorageFactory(new SdcardStorageFactory()); } +void unregisterStorageFactories() +{ + foreach (StorageFactory * factory, registeredStorageFactories) + delete factory; +} + bool Storage::load(RadioData & radioData) { QFile file(filename); @@ -71,30 +77,37 @@ bool Storage::load(RadioData & radioData) setError(QObject::tr("Unable to find file %1!").arg(filename)); return false; } - + + bool ret = false; foreach(StorageFactory * factory, registeredStorageFactories) { StorageFormat * format = factory->instance(filename); if (format->load(radioData)) { board = format->getBoard(); setWarning(format->warning()); - return true; + ret = true; + break; } else { setError(format->error()); } + delete format; } - return false; + return ret; } bool Storage::write(const RadioData & radioData) { + bool ret = false; foreach(StorageFactory * factory, registeredStorageFactories) { if (factory->probe(filename)) { - return factory->instance(filename)->write(radioData); + StorageFormat * format = factory->instance(filename); + ret = format->write(radioData); + delete format; + break; } } - return false; + return ret; } bool convertEEprom(const QString & sourceEEprom, const QString & destinationEEprom, const QString & firmwareFilename) @@ -102,26 +115,26 @@ bool convertEEprom(const QString & sourceEEprom, const QString & destinationEEpr FirmwareInterface firmware(firmwareFilename); if (!firmware.isValid()) return false; - + uint8_t version = firmware.getEEpromVersion(); unsigned int variant = firmware.getEEpromVariant(); - + QSharedPointer radioData = QSharedPointer(new RadioData()); Storage storage(sourceEEprom); if (!storage.load(*radioData)) return false; - + QByteArray eeprom(EESIZE_MAX, 0); int size = getCurrentEEpromInterface()->save((uint8_t *)eeprom.data(), *radioData, version, variant); if (size == 0) { return false; } - + QFile destinationFile(destinationEEprom); if (!destinationFile.open(QIODevice::WriteOnly)) { return false; } - + int result = destinationFile.write(eeprom.constData(), size); destinationFile.close(); return (result == size); @@ -131,7 +144,7 @@ bool convertEEprom(const QString & sourceEEprom, const QString & destinationEEpr unsigned long LoadBackup(RadioData & radioData, uint8_t * eeprom, int size, int index) { std::bitset errors; - + foreach(EEPROMInterface *eepromInterface, eepromInterfaces) { std::bitset result((unsigned long long)eepromInterface->loadBackup(radioData, eeprom, size, index)); if (result.test(ALL_OK)) { @@ -141,7 +154,7 @@ unsigned long LoadBackup(RadioData & radioData, uint8_t * eeprom, int size, int errors |= result; } } - + if (errors.none()) { errors.set(UNKNOWN_ERROR); } @@ -152,7 +165,7 @@ unsigned long LoadBackup(RadioData & radioData, uint8_t * eeprom, int size, int unsigned long LoadEepromXml(RadioData & radioData, QDomDocument & doc) { std::bitset errors; - + foreach(EEPROMInterface *eepromInterface, eepromInterfaces) { std::bitset result((unsigned long long)eepromInterface->loadxml(radioData, doc)); if (result.test(ALL_OK)) { @@ -162,7 +175,7 @@ unsigned long LoadEepromXml(RadioData & radioData, QDomDocument & doc) errors |= result; } } - + if (errors.none()) { errors.set(UNKNOWN_ERROR); } diff --git a/companion/src/storage/storage.h b/companion/src/storage/storage.h index eaaa0d8f0..e1af73b5c 100644 --- a/companion/src/storage/storage.h +++ b/companion/src/storage/storage.h @@ -48,14 +48,14 @@ class StorageFormat board(Board::BOARD_UNKNOWN) { } - + virtual ~StorageFormat() {} virtual bool load(RadioData & radioData) = 0; virtual bool write(const RadioData & radioData) = 0; QString error() { return _error; } - + QString warning() { return _warning; } @@ -84,13 +84,13 @@ class StorageFormat qDebug() << qPrintable(QString("[%1] error: %2").arg(name()).arg(error)); _error = error; } - + void setWarning(const QString & warning) { qDebug() << qPrintable(QString("[%1] warning: %2").arg(name()).arg(warning)); _warning = warning; } - + QString filename; uint8_t version; QString _error; @@ -104,6 +104,7 @@ class StorageFactory StorageFactory() { } + virtual ~StorageFactory() {} virtual QString name() = 0; virtual bool probe(const QString & filename) = 0; virtual StorageFormat * instance(const QString & filename) = 0; @@ -118,22 +119,22 @@ class DefaultStorageFactory : public StorageFactory _name(name) { } - + virtual QString name() { return _name; } - + virtual bool probe(const QString & filename) { return filename.toLower().endsWith("." + _name); } - + virtual StorageFormat * instance(const QString & filename) { return new T(filename); } - + QString _name; }; @@ -144,24 +145,25 @@ class Storage : public StorageFormat StorageFormat(filename) { } - - virtual QString name() { return "storage"; }; - + + virtual QString name() { return "storage"; } + void setError(const QString & error) { _error = error; } - + void setWarning(const QString & warning) { _warning = warning; } - + virtual bool load(RadioData & radioData); virtual bool write(const RadioData & radioData); }; void registerStorageFactories(); +void unregisterStorageFactories(); #if 0 unsigned long LoadBackup(RadioData &radioData, uint8_t *eeprom, int esize, int index); diff --git a/radio/src/targets/simu/opentxsimulator.cpp b/radio/src/targets/simu/opentxsimulator.cpp index 46a6a4a5a..b0d1973de 100644 --- a/radio/src/targets/simu/opentxsimulator.cpp +++ b/radio/src/targets/simu/opentxsimulator.cpp @@ -40,19 +40,6 @@ uint8_t getStickMode() return limit(0, g_eeGeneral.stickMode, 3); } -#if defined(PCBTARANIS) -void resetTrims() -{ - TRIMS_GPIO_REG_RVD |= TRIMS_GPIO_PIN_RVD; - TRIMS_GPIO_REG_RVU |= TRIMS_GPIO_PIN_RVU; - TRIMS_GPIO_REG_RHL |= TRIMS_GPIO_PIN_RHL; - TRIMS_GPIO_REG_RHR |= TRIMS_GPIO_PIN_RHR; - TRIMS_GPIO_REG_LVD |= TRIMS_GPIO_PIN_LVD; - TRIMS_GPIO_REG_LVU |= TRIMS_GPIO_PIN_LVU; - TRIMS_GPIO_REG_LHL |= TRIMS_GPIO_PIN_LHL; - TRIMS_GPIO_REG_LHR |= TRIMS_GPIO_PIN_LHR; -} -#endif OpenTxSimulator::OpenTxSimulator() { @@ -96,11 +83,8 @@ void OpenTxSimulator::start(QByteArray & ee, bool tests) void OpenTxSimulator::start(const char * filename, bool tests) { -#if defined(ROTARY_ENCODER_NAVIGATION) - for (uint8_t i=0; i #include -#if !defined _MSC_VER || defined __GNUC__ +#if !defined (_MSC_VER) || defined (__GNUC__) #include #include #endif @@ -135,6 +135,13 @@ void simuInit() simuSetSwitch(i, 0); simuSetKey(i, false); // a little dirty, but setting keys that don't exist is perfectly OK here } + for (int i=0; i<(NUM_STICKS+NUM_AUX_TRIMS)*2; i++) + simuSetTrim(i, false); + +#if defined(ROTARY_ENCODER_NAVIGATION) + for (uint8_t i=0; iPIO_PDSR, 0x40) -#elif defined(PCBGRUVIN9X) || defined(PCBMEGA2560) +#elif (defined(PCBGRUVIN9X) || defined(PCBMEGA2560)) && (defined(ROTARY_ENCODERS) || defined(ROTARY_ENCODER_NAVIGATION)) KEY_CASE(BTN_REa, pind, 0x20) #elif defined(PCB9X) && defined(ROTARY_ENCODER_NAVIGATION) KEY_CASE(BTN_REa, RotEncoder, 0x20) @@ -337,6 +344,9 @@ void simuSetSwitch(uint8_t swtch, int8_t state) void StartSimu(bool tests, const char * sdPath, const char * settingsPath) { + if (main_thread_running) + return; + s_current_protocol[0] = 255; menuLevel = 0; @@ -380,6 +390,9 @@ void StartSimu(bool tests, const char * sdPath, const char * settingsPath) void StopSimu() { + if (!main_thread_running) + return; + main_thread_running = 0; #if defined(CPUARM) @@ -525,6 +538,7 @@ void StartAudioThread(int volumeGain) simuAudio.leftoverLen = 0; simuAudio.threadRunning = true; simuAudio.volumeGain = volumeGain; + TRACE_SIMPGMSPACE("StartAudioThread(%d)", volumeGain); setScaledVolume(VOLUME_LEVEL_DEF); pthread_attr_t attr; @@ -569,12 +583,17 @@ void lcdOff() void lcdRefresh() { + static bool lightEnabled = (bool)isBacklightEnabled(); + #if defined(PCBFLAMENCO) TW8823_SendScreen(); #endif - memcpy(simuLcdBuf, displayBuf, sizeof(simuLcdBuf)); - simuLcdRefresh = true; + if ((bool(isBacklightEnabled()) != lightEnabled) || memcmp(simuLcdBuf, displayBuf, DISPLAY_BUFFER_SIZE)) { + memcpy(simuLcdBuf, displayBuf, DISPLAY_BUFFER_SIZE); + lightEnabled = (bool)isBacklightEnabled(); + simuLcdRefresh = true; + } } void telemetryPortInit(uint8_t baudrate) diff --git a/radio/src/targets/simu/simueeprom.cpp b/radio/src/targets/simu/simueeprom.cpp index be37e9541..5aaaa4a7a 100644 --- a/radio/src/targets/simu/simueeprom.cpp +++ b/radio/src/targets/simu/simueeprom.cpp @@ -28,7 +28,7 @@ uint8_t * eeprom_buffer_data; volatile int32_t eeprom_buffer_size; bool eeprom_read_operation; -bool eeprom_thread_running = true; +bool eeprom_thread_running = false; #if defined(EEPROM_SIZE) uint8_t eeprom[EEPROM_SIZE]; @@ -41,7 +41,7 @@ sem_t * eeprom_write_sem; void eepromReadBlock (uint8_t * buffer, size_t address, size_t size) { assert(size); - + if (fp) { // TRACE("EEPROM read (pos=%d, size=%d)", pointer_eeprom, size); if (fseek(fp, address, SEEK_SET) < 0) @@ -154,6 +154,7 @@ void StartEepromThread(const char * filename) if (!fp) perror("error in fopen"); } + #ifdef __APPLE__ eeprom_write_sem = sem_open("eepromsem", O_CREAT, S_IRUSR | S_IWUSR, 0); #else @@ -161,8 +162,10 @@ void StartEepromThread(const char * filename) sem_init(eeprom_write_sem, 0, 0); #endif - eeprom_thread_running = true; - pthread_create(&eeprom_thread_pid, NULL, &eeprom_thread_function, NULL); + if (!pthread_create(&eeprom_thread_pid, NULL, &eeprom_thread_function, NULL)) + eeprom_thread_running = true; + else + perror("Could not create eeprom thread."); } void StopEepromThread() @@ -178,5 +181,6 @@ void StopEepromThread() free(eeprom_write_sem); #endif - if (fp) fclose(fp); + if (fp) + fclose(fp); } diff --git a/radio/src/targets/simu/simufatfs.cpp b/radio/src/targets/simu/simufatfs.cpp index 443426870..40c49d154 100644 --- a/radio/src/targets/simu/simufatfs.cpp +++ b/radio/src/targets/simu/simufatfs.cpp @@ -97,8 +97,8 @@ void simuFatfsSetPaths(const char * sdPath, const char * settingsPath) if (settingsPath) { simuSettingsDirectory = removeTrailingPathDelimiter(fixPathDelimiters(settingsPath)); } - TRACE_SIMPGMSPACE("simuFatfsSetPaths(): simuSdDirectory: \"\"", simuSdDirectory.c_str()); - TRACE_SIMPGMSPACE("simuFatfsSetPaths(): simuSettingsDirectory: \"\"", simuSettingsDirectory.c_str()); + TRACE_SIMPGMSPACE("simuFatfsSetPaths(): simuSdDirectory: \"%s\"", simuSdDirectory.c_str()); + TRACE_SIMPGMSPACE("simuFatfsSetPaths(): simuSettingsDirectory: \"%s\"", simuSettingsDirectory.c_str()); } bool startsWith(const char *path, const char * start) From 91a042200bf61e53373612acb24f2275fc84feaa Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Tue, 21 Mar 2017 07:45:05 +0100 Subject: [PATCH 006/203] Fixes #4619 (#4645) --- companion/src/simulation/radiooutputswidget.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/companion/src/simulation/radiooutputswidget.cpp b/companion/src/simulation/radiooutputswidget.cpp index 76e257269..1721fb358 100644 --- a/companion/src/simulation/radiooutputswidget.cpp +++ b/companion/src/simulation/radiooutputswidget.cpp @@ -313,7 +313,7 @@ void RadioOutputsWidget::setValues() for (ch = m_channelsMap.constBegin(); ch != m_channelsMap.constEnd(); ++ch) { if (ch.key() >= CPN_MAX_CHNOUT) continue; - ch.value().first->setText(QString("%1%").arg(outputs.chans[ch.key()] * 100 / 1024)); + ch.value().first->setText(QString("%1%").arg((outputs.chans[ch.key()] * 100 + 512) / 1024)); ch.value().second->setValue(qMin(1024, qMax(-1024, outputs.chans[ch.key()]))); } } From c16256bb8ab4806698e3d29dbd486374d5105222 Mon Sep 17 00:00:00 2001 From: 3djc Date: Tue, 21 Mar 2017 10:06:01 +0100 Subject: [PATCH 007/203] Fix 4652 (#4653) --- radio/src/gui/128x64/model_outputs_arm.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/gui/128x64/model_outputs_arm.cpp b/radio/src/gui/128x64/model_outputs_arm.cpp index e0035a979..de52cea0c 100644 --- a/radio/src/gui/128x64/model_outputs_arm.cpp +++ b/radio/src/gui/128x64/model_outputs_arm.cpp @@ -197,7 +197,7 @@ void menuModelLimitsOne(event_t event) void onLimitsMenu(const char *result) { - s_currIdx = menuVerticalPosition; + s_currIdx = menuVerticalPosition - HEADER_LINE; if (result == STR_RESET) { LimitData *ld = limitAddress(s_currIdx); From cfcc120183d08dc920e32fd769e8a3425b764be7 Mon Sep 17 00:00:00 2001 From: LapinFou Date: Tue, 21 Mar 2017 13:47:14 +0100 Subject: [PATCH 008/203] Intermediate version. --- companion/src/translations/companion_fr.ts | 108 ++++++++++----------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 01de95e97..188663782 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -587,7 +587,7 @@ Peut être différente de la langue du firmware Joystick - Joystick + @@ -627,7 +627,7 @@ Peut être différente de la langue du firmware No joysticks found - Aucun joystick trouvé + Aucun Joystick trouvé @@ -8473,12 +8473,12 @@ Mixage actif par défaut si non-renseigné. WTV20 voice module - + Module voix WTV20 JQ6500 voice module - + Module voix JQ6500 @@ -8611,12 +8611,12 @@ Mixage actif par défaut si non-renseigné. Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) - Le port USB connecte les disques virtuels au lieu du joystick (comme dans le bootloader) + Le port USB connecte les disques virtuels au lieu du Joystick (comme dans le bootloader) Instead of Joystick emulation, USB connection is Command Line Interface - Le port USB est utilisé pour un port série avec interface par ligne de commande au lieu du joystick + Le port USB est utilisé pour un port série avec interface par ligne de commande au lieu du Joystick @@ -9608,7 +9608,7 @@ Profil ID: [%1]; Radio ID: [%2] Right-double-click to reset to center. - Double-clic pour recentrer. + Double-clic droit pour recentrer. @@ -10397,208 +10397,208 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo Companion Simulator - Simulateur Companion + Simulateur Companion Radio Simulator - + Simulateur radio Show Help/Keymap (F1) - + Afficher Aide/Raccourci (F1) Show Help/Keymap - + Afficher Aide/Raccourci Keymap - + Raccourci F1 - + help - + aide Open the Joystick Settings window (F3) - + Ouvrir la boite de dialogue de la configuration du Joystick (F3) Joystick Configuration - + Configuration du Joystick Joystick Config. - + Configuration Joy. F3 - + joystick - + Open Telemetry Simulator window (F4) - + Ouvrir la boite de dialogue de la télémétrie (F4) Telemetry Simulator - Simulateur de télémesure + Simulateur de télémesure Telemetry Sim. - + Simulateur Telem. F4 - + telemetry - + télémétrie Open Trainer Simulator window (F5) - + Ouvrir le simulateur d'écolage (F5) Trainer Simulator - Simulateur d'écolage + Simulateur d'écolage Trainer Sim. - + Simulateur Écol. F5 - + trainer - + écolage Open Debug Console window (F6) - + Ouvrir la console de débogage (F6) Debug Console - + Console de débogage F6 - + debug - + débogage Reload Lua Scripts (F7) - + Recharger le script Lua (F7) Reload Lua Scripts - Recharger le script Lua + Recharger le script Lua Reload Lua - + Recharger Lua F7 - + reloadLua - + rechargeLua Save a screenshot of the radio LCD screen (F8) - + Enregistrez une capture de l'écran LCD de la radio (F8) LCD Screenshot - Capture LCD + Capture LCD Screenshot - Capture d'écran + Capture d'écran F8 - + lcdScreenshot - + captureLcd Reload all radio data (F9) - + Recharger les données radio (F9) Reload Radio Data - Recharger les données radio + Recharger les données radio Reload Radio - + Recharger la radio F9 - + reloadradio - + rechargerRadio @@ -10713,14 +10713,14 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo Joystick Settings - Paramètres joystick + Paramètres Joystick Open joystick configuration settings dialog. - Ouvrir la boite de dialogue de la configuration du joystick. + Ouvrir la boite de dialogue de la configuration du Joystick. @@ -11118,7 +11118,7 @@ La valeur par défaut est configurée dans le profil radio sélectionné. Cannot open joystick, joystick disabled - Impossible d'accéder au joystick, joystick désactivé + Impossible d'accéder au Joystick, Joystick désactivé @@ -14227,7 +14227,7 @@ m2560 for v4.1 boards No joysticks found - Aucun joystick trouvé + Aucun Joystick trouvé @@ -14238,7 +14238,7 @@ m2560 for v4.1 boards Cannot open joystick. - Impossible d'accéder au joystick. + Impossible d'accéder au Joystick. @@ -14265,7 +14265,7 @@ Cliquer sur Suivant lorsque vous êtes prêts Map joystick channels to controls using comboboxes. Press Next when done. - Assigner les voies du Joytick en utilisant les boutons. + Assigner les voies du Joystick en utilisant les boutons. Cliquer sur Suivant lorsque vous êtes prêts. From facbfc7cf80eca7406d03e2cbfa58ef16eade2b6 Mon Sep 17 00:00:00 2001 From: LapinFou Date: Tue, 21 Mar 2017 13:47:55 +0100 Subject: [PATCH 009/203] Small typo. --- companion/src/translations/companion_fr.ts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 188663782..71ce9a35f 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -8428,7 +8428,7 @@ Mixage actif par défaut si non-renseigné. Enable Lua compiler - Active le compilateur LUA + Active le compilateur Lua From fc376b36031f00f60d3628e6e58ef47fed51f4f0 Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Tue, 21 Mar 2017 19:40:08 +0100 Subject: [PATCH 010/203] Define multi subtype strings in the same way as all other strings (#4656) --- radio/src/gui/gui_common_arm.cpp | 42 ++++++++++++++++---------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/radio/src/gui/gui_common_arm.cpp b/radio/src/gui/gui_common_arm.cpp index cfacd920f..a1c787bdf 100644 --- a/radio/src/gui/gui_common_arm.cpp +++ b/radio/src/gui/gui_common_arm.cpp @@ -607,45 +607,45 @@ int getFirstAvailable(int min, int max, IsValueAvailable isValueAvailable) // we don't need the special eeprom/flash string handling, just define them as // local strings -static const char* STR_SUBTYPE_FLYSKY = "\004""Std\0""V9x9""V6x6""V912""CX20"; +const pm_char STR_SUBTYPE_FLYSKY[] PROGMEM = "\004""Std\0""V9x9""V6x6""V912""CX20"; -static const char* STR_SUBTYPE_AFHDS2A = "\010""PWM,IBUS""PPM,IBUS""PWM,SBUS""PPM,SBUS"; +const pm_char STR_SUBTYPE_AFHDS2A[] PROGMEM = "\010""PWM,IBUS""PPM,IBUS""PWM,SBUS""PPM,SBUS"; -static const char* STR_SUBTYPE_FRSKY = "\007""D16\0 ""D8\0 ""D16 8ch""V8\0 ""LBT(EU)""LBT 8ch"; +const pm_char STR_SUBTYPE_FRSKY[] PROGMEM = "\007""D16\0 ""D8\0 ""D16 8ch""V8\0 ""LBT(EU)""LBT 8ch"; -static const char* STR_SUBTYPE_HISKY = "\005""HiSky""HK310"; +const pm_char STR_SUBTYPE_HISKY[] PROGMEM = "\005""HiSky""HK310"; -static const char* STR_SUBTYPE_DSM = "\006""2 22ms""2 11ms""X 22ms""X 11ms"; +const pm_char STR_SUBTYPE_DSM[] PROGMEM = "\006""2 22ms""2 11ms""X 22ms""X 11ms"; -static const char* STR_SUBTYPE_YD717 = "\007""YD717\0 ""SKYWLKR""Syma X2""XINXUN\0""NIHUI\0 "; +const pm_char STR_SUBTYPE_YD717[] PROGMEM = "\007""YD717\0 ""SKYWLKR""Syma X2""XINXUN\0""NIHUI\0 "; -static const char* STR_SUBTYPE_SYMAX = "\003""Std""5c\0"; +const pm_char STR_SUBTYPE_SYMAX[] PROGMEM = "\003""Std""5c\0"; -static const char* STR_SUBTYPE_SLT = "\005""SLT\0 ""Vista"; +const pm_char STR_SUBTYPE_SLT[] PROGMEM = "\005""SLT\0 ""Vista"; -static const char* STR_SUBTYPE_CX10 = "\007""Green\0 ""Blue\0 ""DM007\0 ""-\0 ""JC3015a""JC3015b""MK33041""Q242\0 "; +const pm_char STR_SUBTYPE_CX10[] PROGMEM = "\007""Green\0 ""Blue\0 ""DM007\0 ""-\0 ""JC3015a""JC3015b""MK33041""Q242\0 "; -static const char* STR_SUBTYPE_CG023 = "\005""CG023""YD829""H3 3d"; +const pm_char STR_SUBTYPE_CG023[] PROGMEM = "\005""CG023""YD829""H3 3d"; -static const char* STR_SUBTYPE_KN = "\006""WLtoys""FeiLun"; +const pm_char STR_SUBTYPE_KN[] PROGMEM = "\006""WLtoys""FeiLun"; -static const char* STR_SUBTYPE_MT99 = "\005""MT99\0""H7\0 ""YZ\0 ""LS\0 ""FY805"; +const pm_char STR_SUBTYPE_MT99[] PROGMEM = "\005""MT99\0""H7\0 ""YZ\0 ""LS\0 ""FY805"; -static const char* STR_SUBTYPE_MJXQ = "\005""WLH08""X600\0""X800\0""H26D\0""E010\0""H26WH"; +const pm_char STR_SUBTYPE_MJXQ[] PROGMEM = "\005""WLH08""X600\0""X800\0""H26D\0""E010\0""H26WH"; -static const char* STR_SUBTYPE_HONTAI= "\007""Std\0 ""JJRC X1""X5C1cln"; +const pm_char STR_SUBTYPE_HONTAI[] PROGMEM = "\007""Std\0 ""JJRC X1""X5C1cln"; -static const char* STR_SUBTYPE_Q2X2 = "\004""Q222""Q242""Q282"; +const pm_char STR_SUBTYPE_Q2X2[] PROGMEM = "\004""Q222""Q242""Q282"; -static const char* STR_SUBTYPE_Q303 = "\006""Q303\0 ""CX35\0 ""CX10D\0""CX10WD"; +const pm_char STR_SUBTYPE_Q303[] PROGMEM = "\006""Q303\0 ""CX35\0 ""CX10D\0""CX10WD"; -static const char* STR_SUBTYPE_WK2x01 = "\006""WK2801""WK2401""W6_5_1""W6_6_1""W6_Hel""W6_HeI"; +const pm_char STR_SUBTYPE_WK2x01[] PROGMEM = "\006""WK2801""WK2401""W6_5_1""W6_6_1""W6_Hel""W6_HeI"; -static const char* STR_SUBTYPE_V2X2 = "\006""V2x2\0 ""JXD506"; +const pm_char STR_SUBTYPE_V2X2[] PROGMEM = "\006""V2x2\0 ""JXD506"; -static const char* STR_SUBTYPE_BAYANG = "\006""Bayang""H8S3D"; +const pm_char STR_SUBTYPE_BAYANG[] PROGMEM = "\006""Bayang""H8S3D"; -static const char* STR_SUBTYPE_FY326 = "\005""FY326""FY319"; +const pm_char STR_SUBTYPE_FY326[] PROGMEM = "\005""FY326""FY319"; const mm_protocol_definition multi_protocols[] = { { MM_RF_PROTO_FLYSKY, STR_SUBTYPE_FLYSKY, 4, nullptr }, @@ -671,7 +671,7 @@ const mm_protocol_definition multi_protocols[] = { { MM_RF_PROTO_Q2X2, STR_SUBTYPE_Q2X2, 2, nullptr }, { MM_RF_PROTO_WK_2X01, STR_SUBTYPE_WK2x01, 5, nullptr }, { MM_RF_PROTO_Q303, STR_SUBTYPE_Q303, 3, nullptr }, - { MM_RF_PROTO_GW08, NO_SUBTYPE, 0, nullptr }, + { MM_RF_PROTO_GW08, NO_SUBTYPE, 0, nullptr }, { MM_RF_CUSTOM_SELECTED, NO_SUBTYPE, 7, STR_MULTI_OPTION }, //Sential and default for protocols not listed above (MM_RF_CUSTOM is 0xff() From dc89d2d630c73021353c2bf7be4ff2a7ce738881 Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Tue, 21 Mar 2017 19:47:41 +0100 Subject: [PATCH 011/203] Projectkk2glider/performance tests (#4658) * Transparency and fonts gtests added (Horus) * Added to CLI: Graphics performance test, memory speed test (Horus) * Gtests fixes --- radio/src/cli.cpp | 300 ++++++++++++++++++++++- radio/src/tasks_arm.cpp | 11 +- radio/src/tests/fonts_480x272.png | Bin 0 -> 10423 bytes radio/src/tests/lcd_480x272.cpp | 59 ++++- radio/src/tests/transparency_480x272.png | Bin 0 -> 6126 bytes 5 files changed, 366 insertions(+), 4 deletions(-) create mode 100644 radio/src/tests/fonts_480x272.png create mode 100644 radio/src/tests/transparency_480x272.png diff --git a/radio/src/cli.cpp b/radio/src/cli.cpp index 63dec054b..fd31784ac 100644 --- a/radio/src/cli.cpp +++ b/radio/src/cli.cpp @@ -346,6 +346,296 @@ int cliTestNew() return 0; } +#if defined(COLORLCD) + +extern bool perMainEnabled; +typedef void (*graphichTestFunc)(void); + +void testDrawSolidFilledRectangle() +{ + lcdDrawFilledRect(0, 0, LCD_W, LCD_H, SOLID, TEXT_BGCOLOR); +} + +void testDrawFilledRectangle() +{ + lcdDrawFilledRect(0, 0, LCD_W, LCD_H, DOTTED, TEXT_BGCOLOR); +} + +void testDrawSolidFilledRoundedRectangle() +{ + lcdDrawFilledRect(0, 0, LCD_W/2, LCD_H/2, SOLID, ROUND|TEXT_BGCOLOR); +} + +void testDrawBlackOverlay() +{ + lcdDrawBlackOverlay(); +} + +void testDrawSolidHorizontalLine1() +{ + lcdDrawSolidHorizontalLine(0, 0, 1, 0); +} + +void testDrawSolidHorizontalLine2() +{ + lcdDrawSolidHorizontalLine(0, 0, LCD_W, 0); +} + +void testDrawSolidVerticalLine1() +{ + lcdDrawSolidVerticalLine(0, 0, 1, 0); +} + +void testDrawSolidVerticalLine2() +{ + lcdDrawSolidVerticalLine(0, 0, LCD_H, 0); +} + +void testDrawDiagonalLine() +{ + lcdDrawLine(0,0, LCD_W, LCD_H, SOLID, TEXT_COLOR); +} + +void testEmpty() +{ +} + +void testDrawRect() +{ + lcdDrawRect(0, 0, LCD_W, LCD_H, 2, SOLID, TEXT_COLOR); +} + +void testDrawText() +{ + lcdDrawText(0, LCD_H/2, "The quick brown fox jumps over the lazy dog", TEXT_COLOR); +} + +void testDrawTextVertical() +{ + lcdDrawText(30, LCD_H, "The quick brown fox ", TEXT_COLOR|VERTICAL|NO_FONTCACHE); +} + +void testClear() +{ + lcdClear(); +} + +#define GRAPHICS_TEST_RUN_STEP 100 +#define RUN_GRAPHICS_TEST(name, runtime) runGraphicsTest(name, #name, runtime) + +float runGraphicsTest(graphichTestFunc func, const char * name, uint32_t runtime) +{ + uint32_t start = (uint32_t)CoGetOSTime(); + uint32_t noRuns = 0; + while (((uint32_t)CoGetOSTime() - start) < runtime/2 ) { + for (int n=0; n " }, { "stackinfo", cliStackInfo, "" }, { "meminfo", cliMemoryInfo, "" }, - { "test", cliTest, "new | std::exception" }, + { "test", cliTest, "new | std::exception | graphics | memspd" }, { "trace", cliTrace, "on | off" }, #if defined(PCBFLAMENCO) { "read_bq24195", cliReadBQ24195, "" }, diff --git a/radio/src/tasks_arm.cpp b/radio/src/tasks_arm.cpp index 264d88db2..2617a5153 100644 --- a/radio/src/tasks_arm.cpp +++ b/radio/src/tasks_arm.cpp @@ -206,6 +206,10 @@ void scheduleNextMixerCalculation(uint8_t module, uint16_t delay) #define MENU_TASK_PERIOD_TICKS 25 // 50ms +#if defined(COLORLCD) && defined(CLI) +bool perMainEnabled = true; +#endif + void menusTask(void * pdata) { opentxInit(); @@ -225,8 +229,13 @@ void menusTask(void * pdata) #endif uint32_t start = (uint32_t)CoGetOSTime(); DEBUG_TIMER_START(debugTimerPerMain); - DEBUG_TIMER_SAMPLE(debugTimerPerMainPeriod); +#if defined(COLORLCD) && defined(CLI) + if (perMainEnabled) { + perMain(); + } +#else perMain(); +#endif DEBUG_TIMER_STOP(debugTimerPerMain); // TODO remove completely massstorage from sky9x firmware uint32_t runtime = ((uint32_t)CoGetOSTime() - start); diff --git a/radio/src/tests/fonts_480x272.png b/radio/src/tests/fonts_480x272.png new file mode 100644 index 0000000000000000000000000000000000000000..bbd77c3949f74f81e35f7aea039baf1e749d1605 GIT binary patch literal 10423 zcmdsdg;!Kz*Y5#T1PPIp6hyiOVMytaA*5TRyHiRL=`MvK1R0PR5Tr|`WWYgkq;ni_ zC@E>~LEm?+d%yMl1$VJ#&BHlop0ne(_x|mDPOOfWDk(8NF#rIh>S{`l0RV3S{M@{b z4<5m?3r&MxM4oCUJ^(;&efhyFlPh%sfIEP?lDvK(Y-3i?by@R}a~m7bD0!QYPA9KY z@3|jwjMmj_SMjc1!@CB4U%OGMC+}-|Q|F0J9zHP%F$oPF6!aGmoA3m4A{M*-i z`1~_||PR{`LO z>=j2K;*~$pyV;)kxJb>#Fhx*6kBwVe}sDD60=lva=2J8>0+z z;iz5gDJ3spH_vm?==N;*T@E}bUsdV6o@MT3K`V7vuBRu&I5_*8se#*<;40K^+h@$f z^Y+=+L_^o<_DngfNtR!d6h^$Uem5j|S*k%%skn96!2m%13jW?TZ5=|pRnCDMHqG&~ z5B2Alg`UI61qdT6o*x>yo;{h{ZLmOg9wa9Ho~(~(*V&L))zv?(VlHbzWY0U1oeVY% z(fA)+1e;`0qz;S8KK=P@t^xS=;Yj(*@6jLYIlrDyxz|VDDGRZkZU`7OOLi4 z)>H{7MtP|o!F`jYid$20EeISkS$YV!AB>58)^7RR$(P}ch0o@#>8b|JoTfd;Sn`SJfOFH=lWDt!^|{Sf(TxGMrF==tPh*44v{^|>iH4F%7O6+HO5gWnKe_FAGS{6H zI;KdUO~Ug9=bQ6ADt#%cYOUj1qaVLgMTuMIz^!j0FM7RT@b_>h%#on;j~ByYw!~i~ z>yF()fwK)2wbrdpl*c?>IR|Prw)5Pk@0nS*e93{Ez%ecEfs|xzpBJ1{;O|cb-sFY3 z-!Owy&-V~`2r-fp&PBxhwD)tF&`0l!LhVTS57A-6U-wV2MNo54G7EHU+19~{dnfG1 z6jEMze9TEhsa6c;1L__xsI~vl50$rMmuKRXgPfgP&&j0uTHtdrl|7#C){hkCqHXz@ zH(+PCf7~8+bQrafqCVIx*!$X=u5Rm(;IWb@BWZkqD6|g6chqQ2mjll%Mf-(rhVbb1 zs%t9sWK6s%!5tSJksz)qV@SK6B-jN#Xe>_<{$0Htex#(&?uPAH2|nsPRTj&je5otZ z%I3|zlbNK)_RDH7UOV3Te(wq^{{;>vRkv$3R)ax%in13;#2Qt}AsZfAn|=>9;Cq3;7p z(Bsze3BS-lsf-J;mRIX3Nd>(ypP(zqIlU0tp@U%>vGvFM<9CYgT=%sQmsAO)e5L!t zz1|4s)9&4vBy4DTx2j~=rMFFI6hy!gI?R`0oIJYBN)J2JUt76a@JhZ67yO~NV!eQ& zbYVVRM}K7~$d@4~AKQX3|2+BF9z9s=DnU;Z{qUk_2qJjAbzbj5*E>V-?wqdD1B)zG zHd&EuC<{*YR8IKt{(`w?ox2!KIkL@B39~_^=^3(l+ci|YmMRcIHHUAQIZW`VT9n{> zH^6q4DXFN-Xk49?O}kdJ=LW4C^m_Zn%5u z=qGHdWH~wIz*%q!A9liwSNDUx82i-C&s#E2UT+e;gEl7Aw?@OkD(y20sc_}|AYBcz z*NIzCCllG&aD#DMPn(OgPt3PIe57Y5#5NN^M@K~Y9l`?McSK?Cjq(kB;j&GDG~Ca9 zVPyx+^HKHRv(@D5xN0;n*XXz$b?__{H%Kp+SjaJwU=SHERi+o z(EDR%w(_s#b84-r+&%AfnNN3)w|bjeD2~F91H4bek4AUGcd;SE+>0akrW_7DMM*rq z7(Dfbuzj5rfL_%%d>I2`4>3!TYE9>@(@gSR1+6yf8z?p7E@$@ouqZLO@%4 z^PSG5vz`pvCy)vdc1^z>OdhJ=qpNhnA~g~VdTZBvn>Ak7p8+!4*PL=_?s~_uPt9c6GJ|)Q_*}T8GC=|?P3=dcl9$%E4UzL(W1_$ zle&4e)X7xe;J^@h6{GBrYL?F82>lhPg?}vbtAgUn=WTyFmAAo#*W?SGOrhyChV#TO zV?Od=wE*vck&jl=Cu`+JaJT0#lh4R!*k2lWDtzY-!Cpcw(PHwiVBH^*-d-)O6&?IELJ|oVJgy$8>2cZQO3HEmN-dbYnquIM%2USGA`M?x z3E5OiYd6mnika^CgM;SjfP>3e79z%QjEeFnC|IB|OQO&&&!nohbHxzj11Op4lZ5fo z>nkRia3^m-4qAYpEob2s%d2HB7^L>#wf0U5pT#^=po7@T!=K&(u2oevOEB8{8uN*` z{qUh2L{qps`r3_5nN?CAZdGA&)vgjWB+GrCdb*h|ud30nOKAIH@}HAWK>PDafV9=Y zABsBSX>6%-d9c^jm)f-@yEhqF+^S1)1`>=wO8D}a2tOo_fNtuH_rds^IBJYyEe8gVYzIqOW`_I>9dKIZcQhn7J(#lZBl+z9Ri3^D(J7}Y zn%(xjvnn;JMr|kMtL!?VTi>MJ@Lq)O8=Nt2gm-Yf60mrPC?-n59ZH25B9=!5drz;X zEJZ;69&kr2D`q!w(oaRIAeMbt(Z2%@_sj{~^b`q10bs$X9S@)<#-j%c-`*_zf0xds zc)^<35&;W>HKWYF!k@IzepMyE9hm!sDWY_Z)inu#PYA(Vy#ZdZZp=LI{Z{)N_~Drj z5D}LLmsn~I^b{*Q&3VUi2-_t;>$e6XsvXe~NB>XdTS6*IJ6H}pps;2XsKT{u9c7B2 zxfE;@fV$l8*zmR{@Oa`&a>+cHdg-vz9r2^0Oy;EiCZs@wpf!5A5ag^2WGf4#Y$Kvo z;lq6dCwPE;=u{%lkxvr#2Oco?DeooNoa`^s5`pH!EtrF5^xE)zEGNLSAW7??EGFqP0H&P`7@Sf0i%a#5krMsV@OM>`4;1^>ZjF z%Pwid*dc3O!|1hz58*ff94h!r#wl`0rhEec84Wxw4}f`X5II-1;`4L_qpQy8FuiT=%?(FL8sYo{Bc8x@blZ7NT7&tY4Y z^x%)aXsLS9y?X03C6Ij`*!EkrRtJp}B}D`R7(}gPkXnk%HNbdSi@>)Njn=Q4b^a49 zlYjw$vc^$Huo>#}Vw~^!ZNV2lXNLAGcA>K%kPEsB==^rNwC?hu0P`H#vINJeBOmZ7 z!9wnvmIia$;)c+r&+f5x3CWg#B0w8J^!PGF$#b<1wjc(q4tqVm;sb;Aqrfa=^PQ7( zo=IedeCzn!r1vGj!5BIEcz!7G6Xue`AxI9EI}{H9Y)6Hllof)abdpvVV7QhfD}6km z><||Ja>Fp!2L&0*uN8%2N)!NqYuYISK~i-Wy!okB$FSHx*ep^C+@gQQS~o=3i3jM| zfYEv?+PeS(ih9wj7_>({t}pTDWewRdG?UQ*8y&al%PWP@2t7uSr!W8dnAKa*+-6Fr z!m6T30O+qDixVxkN`RS{V`@FeDQ5{X3<5_A>eU_admTC#w%~&Ttz$891t>i7&x^Dt ztUM;OQR;@wdqDw!-n|sh6zw;^%j0-AVl( zS@Bt*0uR`}w;s&syOTmPBkxtw2zNS*535E`+c5z^$4l*2-FxAvae{q48W2GD7PJ(= z4tHuzSpn^*8c_TX=TlA*WF876r39dx5z&(+1g->!}S}1G=!HzdFTt1D2{&ox6cxj{6(QRiiNb679Ce%QXu1;K5XX& zBFghD*D$b$H9wXWG>cz|QaQ0KT* zklOXmGJHVD2Hjb9*{)RvDqO6(k8SOrS&h$s#s?zEhvdO7UZs!g+)VnL*7=ITZ*lki zYan8_nMG{|Apx?%+yD^HGV_ZR_^#75&hWpa^#3c-J8u9RL31;IjDpx^pCR#q_1t;_ z-w;|_ac5d&=d}}gJ3QdvTX_3vXSNHq<5{)g#l>FdS)&IhC+AL{Wi{;?WsiEup&XeU z0t}K4lM}-&l$V19y(zq;Ui4&eb3b?yD#1u<6vX)7&7XZ&8apniio6K>elp+QcM+0s z9{Z~J?W9Uwgr0uL44yg3)wzj4UltPJE_?ES096rN-o zk)K6%o0D(i;)ds1RL7r;tH2L&7eX)-O^on(G?=-uA#2x{{~7}7{e4o;Fv#Ill%r^; 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- lcdDrawText(8, 8, "The quick brown fox jumps over the lazy dog", CURVE_AXIS_COLOR); - lcdDrawText(5, 5, "The quick brown fox jumps over the lazy dog", TEXT_COLOR); + lcdDrawText(8, 8, "The quick brown fox jumps over the lazy dog", CURVE_AXIS_COLOR|NO_FONTCACHE); + lcdDrawText(5, 5, "The quick brown fox jumps over the lazy dog", TEXT_COLOR|NO_FONTCACHE); lcdDrawFilledRect(10, 30, 30, 30, SOLID, TITLE_BGCOLOR); lcdDrawFilledRect(50, 30, 30, 30, DOTTED, TEXT_COLOR); @@ -116,4 +116,59 @@ TEST(Lcd_480x272, primitives) EXPECT_TRUE(checkScreenshot_480x272("primitives")); } +TEST(Lcd_480x272, transparency) +{ + lcd->clear(TEXT_BGCOLOR); + lcdDrawText(8, 8, "The quick brown fox jumps over the lazy dog", TEXT_COLOR|OPACITY(4)|NO_FONTCACHE); + lcdDrawText(5, 5, "The quick brown fox jumps over the lazy dog", TEXT_COLOR|OPACITY(12)|NO_FONTCACHE); + + lcdDrawFilledRect(10, 30, 30, 30, SOLID, TITLE_BGCOLOR|OPACITY(8)); + lcdDrawFilledRect(50, 30, 30, 30, DOTTED, TEXT_COLOR|OPACITY(10)); + lcdDrawFilledRect(90, 30, 30, 30, SOLID, ROUND|TITLE_BGCOLOR|OPACITY(12)); + lcdDrawRect(130, 30, 30, 30, 1, SOLID, TITLE_BGCOLOR|OPACITY(8)); + lcdDrawRect(170, 30, 30, 30, 2, SOLID, TITLE_BGCOLOR|OPACITY(8)); + lcdDrawRect(210, 30, 30, 30, 5, SOLID, TITLE_BGCOLOR|OPACITY(8)); + + lcdDrawVerticalLine(10, 70, 100, SOLID, TITLE_BGCOLOR|OPACITY(2)); + lcdDrawVerticalLine(15, 70, 90, SOLID, TITLE_BGCOLOR|OPACITY(6)); + lcdDrawVerticalLine(20, 70, 80, SOLID, TITLE_BGCOLOR|OPACITY(10)); + lcdDrawVerticalLine(25, 70, 70, SOLID, TITLE_BGCOLOR|OPACITY(OPACITY_MAX)); + + lcdDrawHorizontalLine(30, 70, 100, SOLID, TEXT_COLOR|OPACITY(2)); + lcdDrawHorizontalLine(30, 75, 90, SOLID, TEXT_COLOR|OPACITY(6)); + lcdDrawHorizontalLine(30, 80, 80, SOLID, TEXT_COLOR|OPACITY(10)); + lcdDrawHorizontalLine(30, 85, 70, SOLID, TEXT_COLOR|OPACITY(OPACITY_MAX)); + + + for(int n=0; n<10; n++) { + int x = 120 + n * 20; + int y = 80 + n * 10; + int color = COLOR(n/2 + 5); + int size = 100; + lcdDrawFilledRect(x, y, size, size, SOLID, color|OPACITY(8)); + + } + + EXPECT_TRUE(checkScreenshot_480x272("transparency")); +} + +TEST(Lcd_480x272, fonts) +{ + loadFontCache(); + lcd->clear(TEXT_BGCOLOR); + + lcdDrawText(8, 8, "The quick brown fox jumps over the lazy dog", TEXT_COLOR|OPACITY(4)); + lcdDrawText(5, 5, "The quick brown fox jumps over the lazy dog", TEXT_COLOR|OPACITY(12)); + + lcdDrawText(10, 200, "The quick", TEXT_COLOR|VERTICAL|NO_FONTCACHE); + lcdDrawText(30, 200, "The quick brown fox", TEXT_COLOR|VERTICAL|NO_FONTCACHE); + // lcdDrawText(50, 200, "The quick brown fox jumps over the lazy dog", TEXT_COLOR|VERTICAL|NO_FONTCACHE); + + lcdDrawText(8, 208, "The quick brown fox jumps over the lazy dog", TITLE_BGCOLOR|OPACITY(4)); + lcdDrawText(5, 205, "The quick brown fox jumps over the lazy dog", TITLE_BGCOLOR|OPACITY(12)); + + EXPECT_TRUE(checkScreenshot_480x272("fonts")); +} + + #endif \ No newline at end of file diff --git a/radio/src/tests/transparency_480x272.png b/radio/src/tests/transparency_480x272.png new file mode 100644 index 0000000000000000000000000000000000000000..18fa167cf1985e86aaae5abafe14faf71440516c GIT binary patch literal 6126 zcmb7I2T)V#_K$THK`bDG2#QgvV4;aL1w>#2QbJRRi1a2sp{q*~Ff0&Yr35JfDT1`n zgNg_eLxccP0%QfLA%uV-kU;Y8zWKj-@6G?cx9*)eb7$_{^L^+0o!|LRd2-9#SV%xZ z00aUFncOtA0)ck?4#=T>JAp5A;0qMswg16QhhPv$*yRt|@j|cM3j`8-Zen=N2A)r! zI2}^*nfjjD&JcfS|L}!=s=m!B+fxcM|0jnOWo{UzCLKR~ai=99buz_&h|E1B!#z_f zheVS^lLX!g81A{Z``$ann3D;o_d_y6B0OffSFQwWnZ)7uNGXf?bIrCZY(b#yEvlIq z2=q#PhY%=N=J^hN>)om#&*ZqhAjsiQpy%>CB|xf87Wz4Cx0oF1PC24wf~+Vskrh$7 zrK}h6tgANy9@tyiC|0|*ic@0X#gsr}&Y?W%-EXk9V_2O$0?KMIQ4W_33sZb=7r3Dt z6@nsUCRcVx(EZi(;u!{;n=K_z!>TETwg}iUql=m+8mZc&18Y-RdIC30D@F*57=bt} z?%4O$h-c$qY9-jhwQ!6V&mY3TFU~}ZGoOcQ&}o@yGEa|toFn$dR_bJ+O6p7`q+lMkPNVC#g?*kzR;cCQ1gP#s7bVX z7yj|7SLRBzcM@n}5+#IUWvfy3=F4lio8Z9Ss=Sd9tpfA%)j?nN6KTD4m9*aJSyB({ z9$eSPw8yTF)tgt@g-`&Qed;JS_G)nykhWp#KJ z*sm6pDeU!lJlj=|OQ9tOJ0oBR2lhg?LuR|2X@y)u1DoO)Cu#-Bflj>>wt^U& zL%Zoa@mA^sUDnMyw_Q442YG215(})2u`%3A7>+6u6uk$}4bqmnT8?D)KQJ#qA8hvX zQBWIS@czxbobJF{D%8nq*}NVls)*U^v5OpvDIN>f-FkiqGNaKnsGPcVr64EDB}c-O zCi$4aExD^Ia6>0@nA1p~7Bj9RLEf@($jZvCq5ulk<@oZmtB9*!>V7dfk-KVJ6pIle zgfnaJQ1|Z?`bFe%45+FE_~Eq4)EjRAx-?LJ)+N+eZ*G1qpr|lJ!sGL0m#ir#B5J1H zn;qcd?^EEb{xU)zk!>}d4?POUbhx)7J3E2{R>OvVsj#Y)OP*m3oq#VtJ3%NZ+mSa} zHu<`$QX$v)tJ`nm;K|pSXWm^2tyl8#Rsl9rN|~$M(lE(T!uwMEiBxIMWUCmV#Joqn zBiN$t)YgGmRjHRe2NRfa#yLvzX&6%15aONs$kI}zV8yBSHmzx-Srn)I%8$bPRA^q# zgh~#)UAgqJ{^x6H0in!HL1d7Zu-l z+rgA`{w*Fgv^LX<46_^y=(rOb&KxbD)h zJ_2?_T1I|70uqLNqr|Omt*Tu7Qj+V1foC#Hqqn9sOOFOm<5eNVwK2UupH=^2lw(bH zX82K(D$Sw^ur*$#FaqsC35(PP!b3K|xgg-2S24;Pw*cFyq50=oz{S<$+1f-^Lb1}Q z*dXc_vayU5Hf=Vl$Wi268X=!Wsk}>pM;m?PuJ*6~EU$*p@Y3~5_RB51U$qtf-Mvwl zKjZzSgH-c*-KW)20h6JcZfZ94ZSY>-6w1m0t)}N&oftN;9uRN-Fs1&MX%qg?wx~QN z7eX3d!A3t{Tfo}!b2(x$k!Yrjf2}W{*Xnn)mLW@*UYtHD0-0%Uz8+Z;Fz#JL8^cZv zugw!)cqoQ=2T?A{WsP^avL(AZkgH>Q&uK(v&df8f+{LVVzuRH)gL#(O9uDa9c4h(d zCdSQkh>SC^?1{0@_z|mtmG`v?OEc>g=LZitCzNQEv^7}(JlxwQTq+o}@j-0SA~f3r zfb43vALTLir!p_oheF++#|lcH%pnRomaFYD&LOAeFiQB0VNV=zlufaiY>)b*&31;f zO0s&JNJ%dT^oQ~LDuqUu$)SX!)~3#=cv{<=!fPHpda|Dw6ge^o2MZaHx5uj~&VmSP zsM8lo$lec*jdN5(gN`J^(FPC277zdO*Na&hJI%b)s7SZG2(%r_sC*~c=QGxif}J)} z@;L0!&T6pX=bFyk6cTg$if|4_rtkc|R7g<|(BmIsr~^~Kx{t4uNP zFKx{p?~*W;U;9?|R>bWz<0^7G=A7*BE0<6bul(Ah_j=p86EDg&jad`v$A}yzMHyV% z35z^vlkQ|4jjL{OzP;{qTbVXIw|to#xLs6OeS~H50Xc%J&OC7T%FaBWvlQ%ke8wLa zz_+{;T&;e7|18N}chhNdf%c*jc;*f67mg*k^nrnE5{p9)L6~9O?m?k52>;x&;Ki1jt9&1{n?oqfsv>$qtgz0vJ-=L zTyQUpqcw@-q?{JjeP(_?*oG}ULZOleqx{xvC#MOGscG<2&cjTo~k$Ha{{|*`A58N+rFDND7 zyHxO^35Vpl01k&B8q-c^^Sy{SEtJUP= zQET%fym;8SXi$D%diFSYDEy0cT|o>KgPPVnB01U0_PkguY>9xGLKQLR0%SLxln3P@ z1KmbzeHR3|!`b-U4Fx10=@#9MzhIKlR>SqN_kU(;_r#B~=2?RhP<{lYWo`3MUxL+Z z7Ul__EMkAx3Z@-q?h5e;C-S~5TiX_D1U@(%;=fm+)dW6UNfhqv!{|r8)j60P%8M_g z&MfeUwy4@jR}6~5Wy+XmfV=P>4GvMFy(#v~FM#|y!?GG%%3J`OWc*G%g-eEzP^&7n zIi?k}AtSMZqtY~V#Bvnp0$tXv3kaJIE;A*@c;Eaw&WD0!R-NWv%K%Td${I|3n?bkI zZy&HT7tu_1=j=GUSm@`b=J$Jm^HZoQ75af2cMEiCqeT+6<#1F&eT8k+f}`IOOk zaN#Sj7yZjMs37x#LAZ^Gkw>Us7#ZWXBdlegtD zf*4drm}yXEb@QN>C`Hx18PRw=vl(zn#`mwJH(&G*GI$=XVN?P7ZTm7WEcs>xsB~wf zx4qO6pzxqzF;81L9^FY#jL9M2-EE**(cX4Iq@b6MFtxL#;?UdH>bFY1yz_&Ywf0W_ zWMtglbRwb1%A3i)?k?I}r+omZ0pPj-Gg}=UWo;iE{;kY`+{7tO;2F38ezrbAQ)^`& zU#jq6E#d<;A};qcR@WQTY!8P8dg_OV*{;0<>Jue=soU_K(GOJnxihC+ zBgTX(okU(jIK_$|8FFTRXgA4r%lu%##z^K1A4QKrp&#PQe@0K1K^^2V^{SUGJ_7z; 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(#4655) * [simulatormainwindow] Move sub-window destructors to main destructor. * [simulation] Move SimulatorInterface creation/ownership to SimulatorMainWindow. * [simulation] Add option to unload simulator libraries after each use (eg. from Companion) so as to properly reset all statically initialized firmware variables; Introduce new SimulatorLoader class. --- companion/src/companion.cpp | 4 +- companion/src/customdebug.cpp | 8 +- companion/src/customdebug.h | 5 +- companion/src/eeprominterface.cpp | 10 -- companion/src/eeprominterface.h | 13 +- companion/src/helpers.cpp | 61 +++---- .../src/simulation/simulatorinterface.cpp | 159 +++++++++++++----- companion/src/simulation/simulatorinterface.h | 27 ++- .../src/simulation/simulatormainwindow.cpp | 48 ++++-- .../src/simulation/simulatormainwindow.h | 9 +- .../src/simulation/simulatorstartupdialog.cpp | 13 +- .../src/simulation/simulatorstartupdialog.h | 2 - companion/src/simulator.cpp | 76 ++++----- 13 files changed, 268 insertions(+), 167 deletions(-) diff --git a/companion/src/companion.cpp b/companion/src/companion.cpp index 718ab2b06..297b5613f 100644 --- a/companion/src/companion.cpp +++ b/companion/src/companion.cpp @@ -105,7 +105,7 @@ int main(int argc, char *argv[]) registerStorageFactories(); registerOpenTxFirmwares(); - registerSimulators(); + SimulatorLoader::registerSimulators(); if (g.profile[g.id()].fwType().isEmpty()){ g.profile[g.id()].fwType(default_firmware_variant->getId()); @@ -135,7 +135,7 @@ int main(int argc, char *argv[]) delete splash; delete mainWin; - unregisterSimulators(); + SimulatorLoader::unregisterSimulators(); unregisterOpenTxFirmwares(); unregisterStorageFactories(); diff --git a/companion/src/customdebug.cpp b/companion/src/customdebug.cpp index 3447364e6..d4be03194 100644 --- a/companion/src/customdebug.cpp +++ b/companion/src/customdebug.cpp @@ -22,15 +22,19 @@ Q_LOGGING_CATEGORY(eepromImport, "eeprom.import") +Q_LOGGING_CATEGORY(simulatorInterfaceLoader, "simulator.interface.loader") + void CustomDebug::setFilterRules() { QString rules; rules.append("eeprom.import="); #if defined(DEBUG_STORAGE_IMPORT) - rules.append("true"); + rules.append("true\n"); #else - rules.append("false"); + rules.append("false\n"); #endif + rules.append("simulator.interface.*=true\n"); + QLoggingCategory::setFilterRules(rules); } diff --git a/companion/src/customdebug.h b/companion/src/customdebug.h index 84a68e66e..28e6c2668 100644 --- a/companion/src/customdebug.h +++ b/companion/src/customdebug.h @@ -24,7 +24,10 @@ #include // Controls the generation of debug output for EEPROM import -Q_DECLARE_LOGGING_CATEGORY(eepromImport) +Q_DECLARE_LOGGING_CATEGORY(eepromImport) // "eeprom.import" + +// Controls the generation of debug output of SimulatorLoader class +Q_DECLARE_LOGGING_CATEGORY(simulatorInterfaceLoader) // "simulator.interface.loader" class CustomDebug { diff --git a/companion/src/eeprominterface.cpp b/companion/src/eeprominterface.cpp index 772aecc7b..073c8949f 100644 --- a/companion/src/eeprominterface.cpp +++ b/companion/src/eeprominterface.cpp @@ -1837,16 +1837,6 @@ void Firmware::addOptions(Option options[]) this->opts.push_back(opts); } -SimulatorInterface * getCurrentSimulator() -{ - QString firmwareId = getCurrentFirmware()->getId(); - SimulatorFactory * factory = getSimulatorFactory(firmwareId); - if (factory) - return factory->create(); - else - return NULL; -} - void FlightModeData::clear(const int phase) { memset(this, 0, sizeof(FlightModeData)); diff --git a/companion/src/eeprominterface.h b/companion/src/eeprominterface.h index 1d88094fd..0589e294a 100644 --- a/companion/src/eeprominterface.h +++ b/companion/src/eeprominterface.h @@ -21,6 +21,7 @@ #ifndef _EEPROMINTERFACE_H_ #define _EEPROMINTERFACE_H_ +#include "macros.h" #include "radiodata.h" #include "../../radio/src/definitions.h" #include "simulatorinterface.h" @@ -195,14 +196,8 @@ inline int applyStickMode(int stick, unsigned int mode) return stick; } - const unsigned int stickModes[]= { - 1, 2, 3, 4, - 1, 3, 2, 4, - 4, 2, 3, 1, - 4, 3, 2, 1 }; - if (stick >= 1 && stick <= 4) - return stickModes[(mode-1)*4 + stick - 1]; + return modn12x3[mode-1][stick-1]; else return stick; } @@ -358,8 +353,6 @@ inline Firmware * getCurrentFirmware() return current_firmware_variant; } -SimulatorInterface * getCurrentSimulator(); - inline EEPROMInterface * getCurrentEEpromInterface() { return getCurrentFirmware()->getEEpromInterface(); @@ -375,7 +368,7 @@ inline int divRoundClosest(const int n, const int d) return ((n < 0) ^ (d < 0)) ? ((n - d/2)/d) : ((n + d/2)/d); } -#define CHECK_IN_ARRAY(T, index) ((unsigned int)index < (unsigned int)(sizeof(T)/sizeof(T[0])) ? T[(unsigned int)index] : "???") +#define CHECK_IN_ARRAY(T, index) ((unsigned int)index < DIM(T) ? T[(unsigned int)index] : "???") extern QList eepromInterfaces; diff --git a/companion/src/helpers.cpp b/companion/src/helpers.cpp index 59eda22df..3e3609ce9 100644 --- a/companion/src/helpers.cpp +++ b/companion/src/helpers.cpp @@ -25,9 +25,6 @@ #elif defined __GNUC__ #include #endif -#if defined(WIN32) && defined(WIN_USE_CONSOLE_STDIO) - #include "windows.h" -#endif #include "appdata.h" #include "helpers.h" @@ -811,39 +808,45 @@ CompanionIcon::CompanionIcon(const QString &baseimage) void startSimulation(QWidget * parent, RadioData & radioData, int modelIdx) { - SimulatorInterface * simulator = getCurrentSimulator(); - if (simulator) { - RadioData * simuData = new RadioData(radioData); - unsigned int flags = 0; + QString fwId = SimulatorLoader::findSimulatorByFirmwareName(getCurrentFirmware()->getId()); + if (fwId.isEmpty()) { + QMessageBox::warning(NULL, + QObject::tr("Warning"), + QObject::tr("Simulator for this firmware is not yet available")); + return; + } - if (modelIdx >= 0) { - flags |= SIMULATOR_FLAGS_NOTX; - simuData->setCurrentModel(modelIdx); - } + RadioData * simuData = new RadioData(radioData); + unsigned int flags = 0; - SimulatorMainWindow * dialog = new SimulatorMainWindow(parent, simulator, flags); - if (!dialog->setRadioData(simuData)) { - QMessageBox::critical(NULL, QObject::tr("Data Load Error"), QObject::tr("Error occurred while starting simulator.")); - delete dialog; - delete simuData; - return; - } + if (modelIdx >= 0) { + flags |= SIMULATOR_FLAGS_NOTX; + simuData->setCurrentModel(modelIdx); + } - dialog->setWindowModality(Qt::ApplicationModal); - dialog->setAttribute(Qt::WA_DeleteOnClose); + SimulatorMainWindow * dialog = new SimulatorMainWindow(parent, fwId, flags); + dialog->setWindowModality(Qt::ApplicationModal); + dialog->setAttribute(Qt::WA_DeleteOnClose); + + QObject::connect(dialog, &SimulatorMainWindow::destroyed, [simuData] (void) { + // TODO simuData and Horus tmp directory is deleted on simulator close OR we could use it to get back data from the simulation + delete simuData; + }); + + QString resultMsg; + if (dialog->getExitStatus(&resultMsg)) { + if (resultMsg.isEmpty()) + resultMsg = QObject::tr("Uknown error during Simulator startup."); + QMessageBox::critical(NULL, QObject::tr("Simulator Error"), resultMsg); + dialog->deleteLater(); + } + else if (dialog->setRadioData(simuData)) { dialog->start(); - - QObject::connect(dialog, &SimulatorMainWindow::destroyed, [simuData] (void) { - // TODO simuData and Horus tmp directory is deleted on simulator close OR we could use it to get back data from the simulation - delete simuData; - }); - dialog->show(); } else { - QMessageBox::warning(NULL, - QObject::tr("Warning"), - QObject::tr("Simulator for this firmware is not yet available")); + QMessageBox::critical(NULL, QObject::tr("Data Load Error"), QObject::tr("Error occurred while starting simulator.")); + dialog->deleteLater(); } } diff --git a/companion/src/simulation/simulatorinterface.cpp b/companion/src/simulation/simulatorinterface.cpp index 1f78b20aa..24919e055 100644 --- a/companion/src/simulation/simulatorinterface.cpp +++ b/companion/src/simulation/simulatorinterface.cpp @@ -19,38 +19,29 @@ */ #include "simulatorinterface.h" -#include -#include -#include -#include -#include -#include +#include "customdebug.h" #include "version.h" + +#include +#include + #if defined _MSC_VER || !defined __GNUC__ #include #endif -QMap registered_simulators; +#ifndef SIMULATOR_INTERFACE_LOADER_METHOD + #define SIMULATOR_INTERFACE_LOADER_DYNAMIC 1 // How to load simulator libraries: 1=dynamic load and unload; 0=load once (old way) +#endif -void registerSimulator(const QString & filename) +QMap SimulatorLoader::registeredSimulators; + +QStringList SimulatorLoader::getAvailableSimulators() { - QLibrary lib(filename); - typedef SimulatorFactory * (*RegisterSimulator)(); - qDebug() << "trying to register simulator in " << filename; - RegisterSimulator registerFunc = (RegisterSimulator)lib.resolve("registerSimu"); - if (registerFunc) { - SimulatorFactory * factory = registerFunc(); - registered_simulators[factory->name()] = factory; - qDebug() << "Registered" << factory->name() << "simulator"; - } - else { - qWarning() << "Library error" << filename << lib.errorString(); - } + return registeredSimulators.keys(); } -int registerSimulators(const QDir & dir) +int SimulatorLoader::registerSimulators(const QDir & dir) { - int noSimulatorsFound = 0; QStringList filters; #if defined(__APPLE__) filters << "*-simulator.dylib"; @@ -59,17 +50,41 @@ int registerSimulators(const QDir & dir) #else filters << "*-simulator.so"; #endif + registeredSimulators.clear(); + + qCDebug(simulatorInterfaceLoader) << "Searching for simulators in" << dir.path() << "matching pattern" << filters; - qDebug() << "Searching for simulators in" << dir.path(); foreach(QString filename, dir.entryList(filters, QDir::Files)) { - QString libraryFilename = dir.path() + "/" + filename; - registerSimulator(libraryFilename); - noSimulatorsFound++; + QLibrary * lib = new QLibrary( dir.path() + "/" + filename); + + qCDebug(simulatorInterfaceLoader) << "Trying to register simulator in " << filename; + + SimulatorFactory * factory; + RegisterSimulator registerFunc = (RegisterSimulator)lib->resolve("registerSimu"); + + if (registerFunc && (factory = registerFunc())) { + if (getAvailableSimulators().contains(factory->name())) + continue; + + lib->setProperty("instances_used", 0); + registeredSimulators.insert(factory->name(), lib); + delete factory; +#if SIMULATOR_INTERFACE_LOADER_DYNAMIC + lib->unload(); +#endif + qCDebug(simulatorInterfaceLoader) << "Registered" << registeredSimulators.lastKey() << "simulator in " << lib->fileName() << "and unloaded:" << !lib->isLoaded(); + } + else { + qWarning() << "Library error" << lib->fileName() << lib->errorString(); + delete lib; + } + } - return noSimulatorsFound; + qCDebug(simulatorInterfaceLoader) << "Found libraries:" << (registeredSimulators.size() ? registeredSimulators.keys() : QStringList() << "none"); + return registeredSimulators.size(); } -void registerSimulators() +void SimulatorLoader::registerSimulators() { QDir dir("."); if (registerSimulators(dir)) { @@ -90,31 +105,93 @@ void registerSimulators() registerSimulators(dir); } -SimulatorFactory * getSimulatorFactory(const QString & name) +void SimulatorLoader::unregisterSimulators() { + foreach(QLibrary * lib, registeredSimulators) + delete lib; +} + +QString SimulatorLoader::findSimulatorByFirmwareName(const QString & name) +{ + int pos; + QString ret; QString simuName = name; + while(1) { - qDebug() << "searching" << simuName << "simulator"; - foreach (QString name, registered_simulators.keys()) { - if (name.contains(simuName)) { - simuName = name; - qDebug() << "found" << simuName; - return registered_simulators[simuName]; - } + qCDebug(simulatorInterfaceLoader) << "searching" << simuName << "simulator"; + if (registeredSimulators.contains(simuName)) { + ret = simuName; + break; } - int pos = simuName.lastIndexOf('-'); - if (pos <= 0) + if ((pos = simuName.lastIndexOf('-')) <= 0) break; simuName = simuName.mid(0, pos); if (simuName.count('-') == 0) break; } - return NULL; + return ret; } -void unregisterSimulators() +SimulatorInterface * SimulatorLoader::loadSimulator(const QString & name) { - foreach(SimulatorFactory *factory, registered_simulators) { + SimulatorInterface * si = NULL; + QString libname = findSimulatorByFirmwareName(name); + + if (libname.isEmpty()) { + qWarning() << "Simulator" << name << "not found."; + return si; + } + + QLibrary * lib = registeredSimulators.value(libname, NULL); + if (!lib) { + qWarning() << "Simulator library is NULL"; + return si; + } + + qCDebug(simulatorInterfaceLoader) << "Trying to load simulator in " << lib->fileName(); + + SimulatorFactory * factory; + RegisterSimulator registerFunc = (RegisterSimulator)lib->resolve("registerSimu"); + if (registerFunc && (factory = registerFunc()) && (si = factory->create())) { + quint8 instance = lib->property("instances_used").toUInt(); + lib->setProperty("instances_used", ++instance); + qCDebug(simulatorInterfaceLoader) << "Loaded" << factory->name() << "simulator instance" << instance; delete factory; } + else { + qWarning() << "Library error" << lib->fileName() << lib->errorString(); + } + return si; +} + +bool SimulatorLoader::unloadSimulator(const QString & name) +{ + bool ret = false; +#if SIMULATOR_INTERFACE_LOADER_DYNAMIC + QString simuName = findSimulatorByFirmwareName(name); + if (simuName.isEmpty()) + return ret; + + QLibrary * lib = registeredSimulators.value(simuName, NULL); + + if (lib && lib->isLoaded()) { + quint8 instance = lib->property("instances_used").toUInt(); + lib->setProperty("instances_used", --instance); + if (!instance) { + ret = lib->unload(); + qCDebug(simulatorInterfaceLoader) << "Unloading" << simuName << "(" << lib->fileName() << ")" << "result:" << ret; + } + else { + ret = true; + qCDebug(simulatorInterfaceLoader) << "Simulator" << simuName << "instances remaining:" << instance; + } + } + else { + qCDebug(simulatorInterfaceLoader) << "Simulator library for " << simuName << "already unloaded."; + } +#else + qCDebug(simulatorInterfaceLoader) << "Keeping simulator library" << simuName << "loaded."; +#endif + + return ret; } diff --git a/companion/src/simulation/simulatorinterface.h b/companion/src/simulation/simulatorinterface.h index 42fef7557..faec70191 100644 --- a/companion/src/simulation/simulatorinterface.h +++ b/companion/src/simulation/simulatorinterface.h @@ -23,11 +23,16 @@ #include "boards.h" #include "constants.h" + +#include #include + +#include #include #include +#include +#include #include -#include struct TxInputs { @@ -122,9 +127,21 @@ class SimulatorFactory { virtual SimulatorInterface *create() = 0; }; -void registerSimulators(); -void unregisterSimulators(); -SimulatorFactory *getSimulatorFactory(const QString &name); -extern QMap registered_simulators; +class SimulatorLoader +{ + public: + static void registerSimulators(); + static void unregisterSimulators(); + static QStringList getAvailableSimulators(); + static QString findSimulatorByFirmwareName(const QString & name); + static SimulatorInterface * loadSimulator(const QString & name); + static bool unloadSimulator(const QString & name); + + protected: + typedef SimulatorFactory * (*RegisterSimulator)(); + + static int registerSimulators(const QDir & dir); + static QMap registeredSimulators; +}; #endif // _SIMULATORINTERFACE_H_ diff --git a/companion/src/simulation/simulatormainwindow.cpp b/companion/src/simulation/simulatormainwindow.cpp index a85f4b419..434ac429c 100644 --- a/companion/src/simulation/simulatormainwindow.cpp +++ b/companion/src/simulation/simulatormainwindow.cpp @@ -40,9 +40,8 @@ extern AppData g; // ensure what "g" means const quint16 SimulatorMainWindow::m_savedUiStateVersion = 2; -SimulatorMainWindow::SimulatorMainWindow(QWidget *parent, SimulatorInterface * simulator, quint8 flags, Qt::WindowFlags wflags) : +SimulatorMainWindow::SimulatorMainWindow(QWidget *parent, const QString & firmwareId, quint8 flags, Qt::WindowFlags wflags) : QMainWindow(parent, wflags), - m_simulator(simulator), ui(new Ui::SimulatorMainWindow), m_simulatorWidget(NULL), m_consoleWidget(NULL), @@ -52,12 +51,24 @@ SimulatorMainWindow::SimulatorMainWindow(QWidget *parent, SimulatorInterface * s m_telemetryDockWidget(NULL), m_trainerDockWidget(NULL), m_outputsDockWidget(NULL), + m_simulatorId(firmwareId), + m_exitStatusCode(0), m_radioProfileId(g.sessionId()), m_radioSizeConstraint(Qt::Horizontal | Qt::Vertical), m_firstShow(true), m_showRadioDocked(true), m_showMenubar(true) { + if (m_simulatorId.isEmpty()) { + m_simulatorId = SimulatorLoader::findSimulatorByFirmwareName(getCurrentFirmware()->getId()); + } + m_simulator = SimulatorLoader::loadSimulator(m_simulatorId); + if (!m_simulator) { + m_exitStatusMsg = tr("ERROR: Failed to create simulator interface, possibly missing or bad library."); + m_exitStatusCode = -1; + return; + } + ui->setupUi(this); setCorner(Qt::TopLeftCorner, Qt::LeftDockWidgetArea); @@ -128,25 +139,30 @@ SimulatorMainWindow::SimulatorMainWindow(QWidget *parent, SimulatorInterface * s SimulatorMainWindow::~SimulatorMainWindow() { - delete ui; -} - -void SimulatorMainWindow::closeEvent(QCloseEvent *) -{ - saveUiState(); - if (m_telemetryDockWidget) delete m_telemetryDockWidget; if (m_trainerDockWidget) delete m_trainerDockWidget; if (m_outputsDockWidget) delete m_outputsDockWidget; - if (m_consoleDockWidget) - delete m_consoleDockWidget; if (m_simulatorDockWidget) delete m_simulatorDockWidget; else if (m_simulatorWidget) delete m_simulatorWidget; + if (m_consoleDockWidget) + delete m_consoleDockWidget; + + delete ui; + + if (m_simulator) + delete m_simulator; + + SimulatorLoader::unloadSimulator(m_simulatorId); +} + +void SimulatorMainWindow::closeEvent(QCloseEvent *) +{ + saveUiState(); } void SimulatorMainWindow::show() @@ -173,7 +189,8 @@ void SimulatorMainWindow::changeEvent(QEvent *e) } } -QMenu * SimulatorMainWindow::createPopupMenu(){ +QMenu * SimulatorMainWindow::createPopupMenu() +{ QMenu * menu = QMainWindow::createPopupMenu(); menu->clear(); menu->addActions(ui->menuView->actions()); @@ -214,6 +231,13 @@ void SimulatorMainWindow::restoreUiState() restoreState(windowState, m_savedUiStateVersion); } +int SimulatorMainWindow::getExitStatus(QString * msg) +{ + if (msg) + *msg = m_exitStatusMsg; + return m_exitStatusCode; +} + bool SimulatorMainWindow::setRadioData(RadioData * radioData) { return m_simulatorWidget->setRadioData(radioData); diff --git a/companion/src/simulation/simulatormainwindow.h b/companion/src/simulation/simulatormainwindow.h index a63982bd6..4791cf0b4 100644 --- a/companion/src/simulation/simulatormainwindow.h +++ b/companion/src/simulation/simulatormainwindow.h @@ -25,7 +25,6 @@ #include #include -#include class DebugOutput; class RadioData; @@ -48,13 +47,14 @@ class SimulatorMainWindow : public QMainWindow Q_OBJECT public: - explicit SimulatorMainWindow(QWidget * parent, SimulatorInterface * simulator, quint8 flags=0, Qt::WindowFlags wflags = Qt::WindowFlags()); + explicit SimulatorMainWindow(QWidget * parent, const QString & firmwareId = "", quint8 flags=0, Qt::WindowFlags wflags = Qt::WindowFlags()); ~SimulatorMainWindow(); + int getExitStatus(QString * msg = Q_NULLPTR); bool setRadioData(RadioData * radioData); bool useTempDataPath(bool deleteOnClose = true); bool setOptions(SimulatorOptions & options, bool withSave = true); - QMenu * createPopupMenu(); + virtual QMenu * createPopupMenu(); public slots: virtual void show(); @@ -95,6 +95,9 @@ class SimulatorMainWindow : public QMainWindow QDockWidget * m_outputsDockWidget; QVector m_keymapHelp; + QString m_simulatorId; + QString m_exitStatusMsg; + int m_exitStatusCode; int m_radioProfileId; int m_radioSizeConstraint; bool m_firstShow; diff --git a/companion/src/simulation/simulatorstartupdialog.cpp b/companion/src/simulation/simulatorstartupdialog.cpp index b09d254e4..e232b36f9 100644 --- a/companion/src/simulation/simulatorstartupdialog.cpp +++ b/companion/src/simulation/simulatorstartupdialog.cpp @@ -23,13 +23,14 @@ #include "appdata.h" #include "constants.h" -#include "eeprominterface.h" +#include "simulatorinterface.h" #include "helpers.h" #include +using namespace Simulator; + extern AppData g; -extern QMap registered_simulators; SimulatorStartupDialog::SimulatorStartupDialog(SimulatorOptions * options, int * profId, QWidget *parent) : QDialog(parent), @@ -45,7 +46,7 @@ SimulatorStartupDialog::SimulatorStartupDialog(SimulatorOptions * options, int * ui->radioProfile->addItem(pi.value(), pi.key()); } - ui->radioType->addItems(registered_simulators.keys()); + ui->radioType->addItems(SimulatorLoader::getAvailableSimulators()); ui->optGrp_dataSource->setId(ui->optFile, SimulatorOptions::START_WITH_FILE); ui->optGrp_dataSource->setId(ui->optFolder, SimulatorOptions::START_WITH_FOLDER); @@ -151,7 +152,7 @@ void SimulatorStartupDialog::updateContainerTypes(void) void SimulatorStartupDialog::loadRadioProfile(int id) { - QString tmpstr; + QString tmpstr, tmpstr2; int i; if (id < 0 || !g.getActiveProfiles().contains(id)) @@ -166,8 +167,8 @@ void SimulatorStartupDialog::loadRadioProfile(int id) tmpstr = m_options->firmwareId; if (tmpstr.isEmpty() && !g.profile[id].fwType().isEmpty()) tmpstr = g.profile[id].fwType(); - else if (getSimulatorFactory(tmpstr)) - tmpstr = getSimulatorFactory(tmpstr)->name(); + else if (!(tmpstr2 = SimulatorLoader::findSimulatorByFirmwareName(m_options->firmwareId)).isEmpty()) + tmpstr = tmpstr2; i = ui->radioType->findText(findRadioId(tmpstr), Qt::MatchContains); if (i > -1) ui->radioType->setCurrentIndex(i); diff --git a/companion/src/simulation/simulatorstartupdialog.h b/companion/src/simulation/simulatorstartupdialog.h index dc5abcbea..ba5dc2f6a 100644 --- a/companion/src/simulation/simulatorstartupdialog.h +++ b/companion/src/simulation/simulatorstartupdialog.h @@ -28,8 +28,6 @@ namespace Ui { class SimulatorStartupDialog; } -using namespace Simulator; - class SimulatorStartupDialog : public QDialog { Q_OBJECT diff --git a/companion/src/simulator.cpp b/companion/src/simulator.cpp index 054c28179..ecd6a2556 100644 --- a/companion/src/simulator.cpp +++ b/companion/src/simulator.cpp @@ -19,13 +19,13 @@ */ #include -#include +#include #include #include -#include -#include -#include #include +#include +#include +#include #if defined(JOYSTICKS) || defined(SIMU_AUDIO) #include #undef main @@ -66,20 +66,11 @@ void sharedHelpText(QTextStream &stream) } // list all available radios stream << endl << QObject::tr("Available radios:") << endl; - foreach(QString name, registered_simulators.keys()) { + foreach(QString name, SimulatorLoader::getAvailableSimulators()) { stream << "\t" << name << endl; } } -QString findFirmwareId(int profileId) -{ - SimulatorFactory * sf = getSimulatorFactory(g.profile[profileId].fwType()); - if (sf) - return sf->name(); - else - return QString(); -} - int main(int argc, char *argv[]) { Q_INIT_RESOURCE(companion); @@ -100,6 +91,8 @@ int main(int argc, char *argv[]) g.init(); + QString resultMsg; + QTranslator companionTranslator; companionTranslator.load(":/companion_" + g.locale()); QTranslator qtTranslator; @@ -127,9 +120,9 @@ int main(int argc, char *argv[]) registerStorageFactories(); registerOpenTxFirmwares(); - registerSimulators(); + SimulatorLoader::registerSimulators(); - if (!registered_simulators.size()) { + if (!SimulatorLoader::getAvailableSimulators().size()) { showMessage(QObject::tr("ERROR: No simulator libraries available."), QMessageBox::Critical); return finish(3); } @@ -142,20 +135,19 @@ int main(int argc, char *argv[]) cliOptions.alias("help", "h"); cliOptions.parse(QCoreApplication::arguments()); if (cliOptions.count("help") || cliOptions.showUnrecognizedWarning()) { - QString msg; - QTextStream stream(&msg); + QTextStream stream(&resultMsg); stream << QObject::tr("Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] ") << endl << endl; stream << QObject::tr("Options:") << endl; cliOptions.showUsage(false, stream); sharedHelpText(stream); // display - showMessage(msg, QMessageBox::Information); + showMessage(resultMsg, QMessageBox::Information); return finish(1); } // TODO : defaults should be set in Profile::init() if (simOptions.firmwareId.isEmpty()) - simOptions.firmwareId = findFirmwareId(profileId); + simOptions.firmwareId = SimulatorLoader::findSimulatorByFirmwareName(g.profile[profileId].fwType()); if (simOptions.dataFolder.isEmpty()) simOptions.dataFolder = g.eepromDir(); if (simOptions.sdPath.isEmpty()) @@ -209,28 +201,16 @@ int main(int argc, char *argv[]) qDebug() << "profileId=" << profileId << simOptions; if (profileId < 0 || simOptions.firmwareId.isEmpty() || (simOptions.dataFile.isEmpty() && simOptions.dataFolder.isEmpty())) { - showMessage(QObject::tr("ERROR: Couldn't start simulator, missing radio/profile/data file/folder.\n Profile ID: [%1]; Radio ID: [%2];\nData File: [%3]") - .arg(profileId).arg(simOptions.firmwareId, simOptions.dataFile), QMessageBox::Critical); + resultMsg = QObject::tr("ERROR: Couldn't start simulator, missing radio/profile/data file/folder.\n Profile ID: [%1]; Radio ID: [%2];\nData File: [%3]"); + showMessage(resultMsg.arg(profileId).arg(simOptions.firmwareId, simOptions.dataFile), QMessageBox::Critical); return finish(1); } - if (!g.getActiveProfiles().contains(profileId) || !registered_simulators.keys().contains(simOptions.firmwareId)) { - QString msg; - QTextStream stream(&msg); + if (!g.getActiveProfiles().contains(profileId) || !SimulatorLoader::getAvailableSimulators().contains(simOptions.firmwareId)) { + QTextStream stream(&resultMsg); stream << QObject::tr("ERROR: Radio profile or simulator firmware not found.\nProfile ID: [%1]; Radio ID: [%2]") .arg(profileId).arg(simOptions.firmwareId); sharedHelpText(stream); - showMessage(msg, QMessageBox::Critical); - return finish(2); - } - - SimulatorFactory * factory = getSimulatorFactory(simOptions.firmwareId); - if (!factory) { - showMessage(QObject::tr("ERROR: Simulator %1 not found").arg(simOptions.firmwareId), QMessageBox::Critical); - return finish(2); - } - SimulatorInterface * simulator = factory->create(); - if (!simulator) { - showMessage(QObject::tr("ERROR: Failed to create simulator interface, possibly missing or bad library."), QMessageBox::Critical); + showMessage(resultMsg, QMessageBox::Critical); return finish(2); } @@ -239,26 +219,33 @@ int main(int argc, char *argv[]) g.sessionId(profileId); g.simuLastProfId(profileId); - int result = 1; - SimulatorMainWindow * mainWindow = new SimulatorMainWindow(NULL, simulator, SIMULATOR_FLAGS_STANDALONE); - if (mainWindow->setOptions(simOptions, true)) { + int result = 0; + SimulatorMainWindow * mainWindow = new SimulatorMainWindow(NULL, simOptions.firmwareId, SIMULATOR_FLAGS_STANDALONE); + if ((result = mainWindow->getExitStatus(&resultMsg))) { + if (resultMsg.isEmpty()) + resultMsg = QObject::tr("Uknown error during Simulator startup."); + showMessage(resultMsg, QMessageBox::Critical); + } + else if (mainWindow->setOptions(simOptions, true)) { mainWindow->start(); mainWindow->show(); result = app.exec(); + if (!result) { + if ((result = mainWindow->getExitStatus(&resultMsg)) && !resultMsg.isEmpty()) + qWarning() << "Exit message from SimulatorMainWindow:" << resultMsg; + } } else { result = 3; } - delete mainWindow; - delete simulator; + delete mainWindow; return finish(result); } int finish(int exitCode) { - qDebug() << "SIMULATOR EXIT" << exitCode; - unregisterSimulators(); + SimulatorLoader::unregisterSimulators(); unregisterOpenTxFirmwares(); unregisterStorageFactories(); @@ -266,5 +253,6 @@ int finish(int exitCode) SDL_Quit(); #endif + qDebug() << "SIMULATOR EXIT" << exitCode; return exitCode; } From e0022ac287c2d907dbf007854db29724cb17e61f Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Tue, 21 Mar 2017 19:49:58 +0100 Subject: [PATCH 013/203] Bitmaps with a too big filename were displayed in the selection popup (#4646) --- radio/src/gui/480x272/model_setup.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/gui/480x272/model_setup.cpp b/radio/src/gui/480x272/model_setup.cpp index 7737b91ea..4261cf6bf 100644 --- a/radio/src/gui/480x272/model_setup.cpp +++ b/radio/src/gui/480x272/model_setup.cpp @@ -97,7 +97,7 @@ enum MenuModelSetupItems { void onModelSetupBitmapMenu(const char * result) { if (result == STR_UPDATE_LIST) { - if (!sdListFiles(BITMAPS_PATH, BITMAPS_EXT, sizeof(g_model.header.bitmap), NULL)) { + if (!sdListFiles(BITMAPS_PATH, BITMAPS_EXT, sizeof(g_model.header.bitmap)-LEN_BITMAPS_EXT, NULL)) { POPUP_WARNING(STR_NO_BITMAPS_ON_SD); } } From b81c483be39ef5b0b9f3caf90090481f477db3fb Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Tue, 21 Mar 2017 20:11:48 +0100 Subject: [PATCH 014/203] Fixes #3795 (#4643) Multiple bugs found --- radio/src/gui/480x272/screens_setup.cpp | 31 +++++++++++++------------ 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/radio/src/gui/480x272/screens_setup.cpp b/radio/src/gui/480x272/screens_setup.cpp index 8a4523a56..627c7b090 100644 --- a/radio/src/gui/480x272/screens_setup.cpp +++ b/radio/src/gui/480x272/screens_setup.cpp @@ -68,6 +68,18 @@ uint8_t getZoneOptionColumns(const ZoneOption * option) } } +uint8_t editColorPart(coord_t x, coord_t y, event_t event, uint8_t part, uint8_t value, LcdFlags attr, uint32_t i_flags) +{ + const char * STR_COLOR_PARTS = "\002" "R:" "G:" "B:"; + uint8_t PART_BITS[] = { 5, 6, 5 }; + lcdDrawTextAtIndex(x, y, STR_COLOR_PARTS, part, (attr && menuHorizontalPosition < 0) ? TEXT_INVERTED_COLOR : TEXT_COLOR); + lcdDrawNumber(x + 20, y, value << (8-PART_BITS[part]), LEFT|TEXT_COLOR|((attr && (menuHorizontalPosition < 0 || menuHorizontalPosition == part)) ? attr : TEXT_COLOR)); + if (attr && menuHorizontalPosition == part) { + value = checkIncDec(event, value, 0, (1 << PART_BITS[part])-1, i_flags); + } + return value; +} + bool editZoneOption(coord_t y, const ZoneOption * option, ZoneOptionValue * value, LcdFlags attr, uint32_t i_flags, event_t event) { lcdDrawText(MENUS_MARGIN_LEFT, y, option->name); @@ -136,21 +148,10 @@ bool editZoneOption(coord_t y, const ZoneOption * option, ZoneOptionValue * valu lcdDrawSolidFilledRect(SCREENS_SETUP_2ND_COLUMN-1, y+1, 42, 17, TEXT_COLOR); lcdDrawSolidFilledRect(SCREENS_SETUP_2ND_COLUMN, y+2, 40, 15, CUSTOM_COLOR); - lcdDrawText(SCREENS_SETUP_2ND_COLUMN + 50, y, "R:", menuHorizontalPosition < 0 ? TEXT_INVERTED_COLOR : TEXT_COLOR); - lcdDrawNumber(SCREENS_SETUP_2ND_COLUMN + 70, y, r << 3, LEFT|TEXT_COLOR|((attr && menuHorizontalPosition <= 0) ? attr : 0)); - if (attr && menuHorizontalPosition == 0) { - r = checkIncDec(event, r, 0, (1<<5)-1, i_flags); - } - lcdDrawText(SCREENS_SETUP_2ND_COLUMN + 110, y, "G:", menuHorizontalPosition < 0 ? TEXT_INVERTED_COLOR : TEXT_COLOR); - lcdDrawNumber(SCREENS_SETUP_2ND_COLUMN + 130, y, g << 2, LEFT|TEXT_COLOR|((attr && (menuHorizontalPosition < 0 || menuHorizontalPosition == 1)) ? attr : 0)); - if (attr && menuHorizontalPosition == 1) { - g = checkIncDec(event, g, 0, (1<<6)-1, i_flags); - } - lcdDrawText(SCREENS_SETUP_2ND_COLUMN + 170, y, "B:", menuHorizontalPosition < 0 ? TEXT_INVERTED_COLOR : TEXT_COLOR); - lcdDrawNumber(SCREENS_SETUP_2ND_COLUMN + 190, y, b << 3, LEFT|TEXT_COLOR|((attr && (menuHorizontalPosition < 0 || menuHorizontalPosition == 2)) ? attr : 0)); - if (attr && menuHorizontalPosition == 2) { - b = checkIncDec(event, b, 0, (1<<5)-1, i_flags); - } + r = editColorPart(SCREENS_SETUP_2ND_COLUMN + 50, y, event, 0, r, attr, i_flags); + g = editColorPart(SCREENS_SETUP_2ND_COLUMN + 110, y, event, 1, g, attr, i_flags); + b = editColorPart(SCREENS_SETUP_2ND_COLUMN + 170, y, event, 2, b, attr, i_flags); + if (attr && checkIncDec_Ret) { value->unsignedValue = RGB_JOIN(r, g, b); } From 12d231443ce8af99b36c33717629ff87a5213424 Mon Sep 17 00:00:00 2001 From: Andre Bernet Date: Wed, 22 Mar 2017 08:38:23 +0100 Subject: [PATCH 015/203] Output reset wasn't saved (Fix #4662) Remove dead code --- radio/src/gui/128x64/model_outputs_arm.cpp | 8 +------- radio/src/gui/212x64/model_outputs.cpp | 8 +------- radio/src/gui/480x272/model_outputs.cpp | 8 +------- 3 files changed, 3 insertions(+), 21 deletions(-) diff --git a/radio/src/gui/128x64/model_outputs_arm.cpp b/radio/src/gui/128x64/model_outputs_arm.cpp index de52cea0c..e2b60bd17 100644 --- a/radio/src/gui/128x64/model_outputs_arm.cpp +++ b/radio/src/gui/128x64/model_outputs_arm.cpp @@ -207,6 +207,7 @@ void onLimitsMenu(const char *result) ld->ppmCenter = 0; ld->revert = false; ld->curve = 0; + storageDirty(EE_MODEL); } else if (result == STR_COPY_STICKS_TO_OFS) { copySticksToOffset(s_currIdx); @@ -230,13 +231,6 @@ void menuModelLimits(event_t event) SIMPLE_MENU(STR_MENULIMITS, menuTabModel, MENU_MODEL_OUTPUTS, HEADER_LINE+MAX_OUTPUT_CHANNELS+1); - if (warningResult) { - warningResult = 0; - LimitData * ld = limitAddress(sub); - ld->revert = !ld->revert; - storageDirty(EE_MODEL); - } - for (uint8_t i=0; ippmCenter = 0; ld->revert = false; ld->curve = 0; + storageDirty(EE_MODEL); } else if (result == STR_COPY_STICKS_TO_OFS) { copySticksToOffset(ch); @@ -116,13 +117,6 @@ void menuModelLimits(event_t event) drawColumnHeader(STR_LIMITS_HEADERS, menuHorizontalPosition); } - if (warningResult) { - warningResult = 0; - LimitData *ld = limitAddress(sub); - ld->revert = !ld->revert; - storageDirty(EE_MODEL); - } - for (int i=0; ippmCenter = 0; ld->revert = false; ld->curve = 0; + storageDirty(EE_MODEL); } else if (result == STR_COPY_STICKS_TO_OFS) { copySticksToOffset(ch); @@ -106,13 +107,6 @@ bool menuModelLimits(event_t event) drawColumnHeader(STR_LIMITS_HEADERS, NULL, menuHorizontalPosition); } - if (warningResult) { - warningResult = 0; - LimitData *ld = limitAddress(sub); - ld->revert = !ld->revert; - storageDirty(EE_MODEL); - } - for (int i=0; i Date: Wed, 22 Mar 2017 09:41:07 +0100 Subject: [PATCH 016/203] Fixes #4589 (#4644) Produces a segfault with the telenowa script (missing bitmap) --- radio/src/lua/api_lcd.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/radio/src/lua/api_lcd.cpp b/radio/src/lua/api_lcd.cpp index e399a2f53..16711a76c 100644 --- a/radio/src/lua/api_lcd.cpp +++ b/radio/src/lua/api_lcd.cpp @@ -422,7 +422,6 @@ static int luaOpenBitmap(lua_State * L) static BitmapBuffer * checkBitmap(lua_State * L, int index) { BitmapBuffer ** b = (BitmapBuffer **)luaL_checkudata(L, index, LUA_BITMAPHANDLE); - if (!*b) luaL_error(L, "null Image"); return *b; } From 76f5d029a0286964a2203b28babb2653f06db6d2 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Wed, 22 Mar 2017 11:39:09 +0100 Subject: [PATCH 017/203] Warning when Multiply used on first mix of a channel, fix #4525 (#4647) * Proposal to fix #4525 * Clearer text * Companion side * Translation not needed --- companion/src/modelprinter.cpp | 5 ++++- radio/src/gui/480x272/model_mixes.cpp | 5 ++++- radio/src/gui/common/stdlcd/model_mixes.cpp | 8 +++++++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/companion/src/modelprinter.cpp b/companion/src/modelprinter.cpp index 970b1ca57..1071311ce 100644 --- a/companion/src/modelprinter.cpp +++ b/companion/src/modelprinter.cpp @@ -429,7 +429,10 @@ QString ModelPrinter::printMixerLine(const MixData & mix, bool showMultiplex, in } str += " " + source; - str += " " + tr("Weight(%1)").arg(getGVarString(mix.weight, true)).toHtmlEscaped(); + if (mix.mltpx == MLTPX_MUL && !showMultiplex) + str += " " + QString("MULT!").toHtmlEscaped(); + else + str += " " + tr("Weight(%1)").arg(getGVarString(mix.weight, true)).toHtmlEscaped(); QString flightModesStr = printFlightModes(mix.flightModes); if (!flightModesStr.isEmpty()) diff --git a/radio/src/gui/480x272/model_mixes.cpp b/radio/src/gui/480x272/model_mixes.cpp index 71708d303..361ffa862 100644 --- a/radio/src/gui/480x272/model_mixes.cpp +++ b/radio/src/gui/480x272/model_mixes.cpp @@ -555,7 +555,10 @@ bool menuModelMixAll(event_t event) drawSource(MIX_LINE_SRC_POS, y, md->srcRaw); - gvarWeightItem(MIX_LINE_WEIGHT_POS, y, md, RIGHT | attr | (isMixActive(i) ? BOLD : 0), event); + if (mixCnt == 0 && md->mltpx == 1) + lcdDrawText(MIX_LINE_WEIGHT_POS, y, "MULT!", RIGHT | attr | (isMixActive(i) ? BOLD : 0)); + else + gvarWeightItem(MIX_LINE_WEIGHT_POS, y, md, RIGHT | attr | (isMixActive(i) ? BOLD : 0), event); displayMixLine(y, md); diff --git a/radio/src/gui/common/stdlcd/model_mixes.cpp b/radio/src/gui/common/stdlcd/model_mixes.cpp index 74e749748..40c8ad641 100644 --- a/radio/src/gui/common/stdlcd/model_mixes.cpp +++ b/radio/src/gui/common/stdlcd/model_mixes.cpp @@ -441,7 +441,13 @@ void menuModelMixAll(event_t event) drawSource(MIX_LINE_SRC_POS, y, md->srcRaw, 0); - gvarWeightItem(MIX_LINE_WEIGHT_POS, y, md, RIGHT | attr | (isMixActive(i) ? BOLD : 0), 0); + if (mixCnt == 0 && md->mltpx == 1) { + lcdDrawText(MIX_LINE_WEIGHT_POS, y, "MULT!", RIGHT | attr | (isMixActive(i) ? BOLD : 0)); + } + else { + gvarWeightItem(MIX_LINE_WEIGHT_POS, y, md, RIGHT | attr | (isMixActive(i) ? BOLD : 0), 0); + } + #if LCD_W >= 212 displayMixLine(y, md); #else From dc00757cd74983d9b96c3e24b444faa6ba8c7cc7 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Wed, 22 Mar 2017 07:39:02 -0400 Subject: [PATCH 018/203] [Simulator] New skin for channel output indicators. (Fix #4638 ) (#4669) --- companion/src/companion.qrc | 1 + .../images/simulator/icons/svg/line_horiz.svg | 5 +++ companion/src/themes/default/style.css | 37 +++++++++++++++++++ 3 files changed, 43 insertions(+) create mode 100644 companion/src/images/simulator/icons/svg/line_horiz.svg diff --git a/companion/src/companion.qrc b/companion/src/companion.qrc index 2c0d6986a..4a97f106c 100644 --- a/companion/src/companion.qrc +++ b/companion/src/companion.qrc @@ -21,6 +21,7 @@ images/simulator/icons/svg/info-active.svg images/simulator/icons/svg/joystick_settings.svg images/simulator/icons/svg/joystick_settings-active.svg + images/simulator/icons/svg/line_horiz.svg images/simulator/icons/svg/toggle_lock.svg images/simulator/icons/svg/toggle_lock-on.svg images/simulator/icons/svg/radio_outputs.svg diff --git a/companion/src/images/simulator/icons/svg/line_horiz.svg b/companion/src/images/simulator/icons/svg/line_horiz.svg new file mode 100644 index 000000000..56c97e5ea --- /dev/null +++ b/companion/src/images/simulator/icons/svg/line_horiz.svg @@ -0,0 +1,5 @@ + + + + + diff --git a/companion/src/themes/default/style.css b/companion/src/themes/default/style.css index c7548a661..5b018a1d0 100644 --- a/companion/src/themes/default/style.css +++ b/companion/src/themes/default/style.css @@ -55,6 +55,7 @@ QSplitter::handle:hover { SimulatorWidget > QWidget { background-color: qlineargradient(spread:reflect, x1:0, y1:0, x2:0, y2:1, stop:0 rgba(242, 242, 242, 255), stop:0.757062 rgba(222, 220, 220, 255), stop:1 rgba(232, 230, 230, 255)); } + /* radio LCD/controls area under "case" */ SimulatorWidget #radioUiWidget { background-color: qlineargradient(spread:reflect, x1:0.22, y1:0, x2:0.55065, y2:0.54, stop:0 rgba(7, 7, 7, 250), stop:0.864407 rgba(66, 66, 66, 255)); @@ -63,10 +64,13 @@ SimulatorWidget #radioUiWidget { } +/** RadioOutputsWidget **/ + /* outputs display splitter areas (channels, logical switches, global vars) */ RadioOutputsWidget > QSplitter > QWidget { border: 1px solid #a1a1a1; } + /* vertical headings with the area names */ RadioOutputsWidget QLabel[heading=true] { background-color: qlineargradient(spread:reflect, x1:0.22, y1:0, x2:0.5, y2:0.55, stop:0 rgba(20, 20, 20, 250), stop:0.85 rgba(86, 86, 86, 255)); @@ -75,3 +79,36 @@ RadioOutputsWidget QLabel[heading=true] { padding: 0.8em 0.45em; font-size: 8pt; } + +/* Channel output indicator sliders */ + +RadioOutputsWidget #channelsWidget QSlider::groove:vertical { + width: 18px; + background-color: transparent; + border-image: url(:/images/simulator/icons/svg/line_horiz.svg) 0 0 0 0 stretch round; +} + +RadioOutputsWidget #channelsWidget QSlider::add-page:vertical, +RadioOutputsWidget #channelsWidget QSlider::sub-page:vertical { + border: 1px solid #777; + margin: 0 5px; +} + +RadioOutputsWidget #channelsWidget QSlider::sub-page:vertical { + background: qlineargradient(x1: .4, y1: 0, x2: 1, y2: 1, stop: 0 #bbb, stop:1 #fff); + border-top-left-radius: 4px; + border-top-right-radius: 4px; +} + +RadioOutputsWidget #channelsWidget QSlider::add-page:vertical { + background: qlineargradient(x1: .6, y1: 1, x2: 0, y2: 0, stop:0 #55f, stop: 1 #eef); + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; +} + +RadioOutputsWidget #channelsWidget QSlider::handle:vertical:disabled { + background-color: darkgreen; + border: 1px solid #ccc; + border-radius: 1px; + height: 3px; +} From 4f6931faab66c6d8b83a3c41c827d0d9d93cec04 Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Wed, 22 Mar 2017 15:55:37 +0100 Subject: [PATCH 019/203] Fix typo in multi model name (H3 3D instead of H8 3D) --- companion/src/multiprotocols.cpp | 2 +- radio/src/gui/gui_common_arm.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/companion/src/multiprotocols.cpp b/companion/src/multiprotocols.cpp index ce2249f1c..1e8394044 100644 --- a/companion/src/multiprotocols.cpp +++ b/companion/src/multiprotocols.cpp @@ -36,7 +36,7 @@ static const QStringList STR_SUBTYPE_YD717 {"YD717", "Skywalker", "Syma X2", " static const QStringList STR_SUBTYPE_SYMAX {"Standard", "Syma X5C"}; static const QStringList STR_SUBTYPE_SLT {"SLT", "Vista"}; static const QStringList STR_SUBTYPE_CX10 {"Green", "Blue", "DM007", "-", "JC3015a", "JC3015b", "MK33041", "Q242"}; -static const QStringList STR_SUBTYPE_CG023 {"CG023", "YD829", "H3 3D"}; +static const QStringList STR_SUBTYPE_CG023 {"CG023", "YD829", "H8 3D"}; static const QStringList STR_SUBTYPE_BAYANG {"Bayang", "H8S3D"}; static const QStringList STR_SUBTYPE_KN {"WLtoys", "FeiLun"}; static const QStringList STR_SUBTYPE_MT99 {"MT99", "H7", "YZ", "LS", "FY805"}; diff --git a/radio/src/gui/gui_common_arm.cpp b/radio/src/gui/gui_common_arm.cpp index a1c787bdf..aaeba662c 100644 --- a/radio/src/gui/gui_common_arm.cpp +++ b/radio/src/gui/gui_common_arm.cpp @@ -625,7 +625,7 @@ const pm_char STR_SUBTYPE_SLT[] PROGMEM = "\005""SLT\0 ""Vista"; const pm_char STR_SUBTYPE_CX10[] PROGMEM = "\007""Green\0 ""Blue\0 ""DM007\0 ""-\0 ""JC3015a""JC3015b""MK33041""Q242\0 "; -const pm_char STR_SUBTYPE_CG023[] PROGMEM = "\005""CG023""YD829""H3 3d"; +const pm_char STR_SUBTYPE_CG023[] PROGMEM = "\005""CG023""YD829""H8 3d"; const pm_char STR_SUBTYPE_KN[] PROGMEM = "\006""WLtoys""FeiLun"; From 4faf323aed34e1f9775b1bd805d5adfb53936b6d Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Wed, 22 Mar 2017 16:02:04 -0400 Subject: [PATCH 020/203] [Simulator] Fix and refactor Joystick configuration dialog and internal stick-to-radio axis mapping system. Stick was not always showing active in config. dialog, and mappings were sometimes wrong. (#4672) --- companion/src/simulation/joystickdialog.cpp | 90 +++-- companion/src/simulation/joystickdialog.h | 3 +- companion/src/simulation/joystickdialog.ui | 364 +------------------ companion/src/simulation/simulatorwidget.cpp | 116 +++--- companion/src/simulation/simulatorwidget.h | 2 - 5 files changed, 111 insertions(+), 464 deletions(-) diff --git a/companion/src/simulation/joystickdialog.cpp b/companion/src/simulation/joystickdialog.cpp index 76a08e5c2..77cd14ef0 100644 --- a/companion/src/simulation/joystickdialog.cpp +++ b/companion/src/simulation/joystickdialog.cpp @@ -21,6 +21,8 @@ #include "joystickdialog.h" #include "ui_joystickdialog.h" +#include "constants.h" + joystickDialog::joystickDialog(QWidget *parent, int stick) : QDialog(parent), ui(new Ui::joystickDialog), @@ -43,6 +45,7 @@ joystickDialog::joystickDialog(QWidget *parent, int stick) : memcpy(jscal, jscaltmp, sizeof (jscal)); foreach(QComboBox *cb, findChildren(QRegExp("jsmapCB_[0-9]+"))) { + populateSourceCombo(cb); sticks[cb->property("channel").toUInt()] = cb; } foreach(QCheckBox *ib, findChildren(QRegExp("ChInv_[0-9]+"))) { @@ -62,7 +65,7 @@ joystickDialog::joystickDialog(QWidget *parent, int stick) : sliders[i]->setMinimum(jscal[i][0]); sliders[i]->setMaximum(jscal[i][2]); invert[i]->setChecked(g.joystick[i].stick_inv()); - sticks[i]->setCurrentIndex(g.joystick[i].stick_axe() + 1); + sticks[i]->setCurrentIndex(sticks[i]->findData(g.joystick[i].stick_axe())); } ui->backButton->setEnabled(false); @@ -72,7 +75,13 @@ joystickDialog::joystickDialog(QWidget *parent, int stick) : if (stick < 0) stick = g.jsCtrl(); - loadJoysticks(stick); + if (loadJoysticks(stick)) { + joystickSetEnabled(ui->joystickChkB->isChecked()); + joystickOpen(ui->joystickCB->currentIndex()); + } + else { + joystickSetEnabled(false); + } loadStep(); connect(joystick, SIGNAL(axisValueChanged(int, int)), this, SLOT(onjoystickAxisValueChanged(int, int))); @@ -85,7 +94,26 @@ joystickDialog::~joystickDialog() delete ui; } -void joystickDialog::loadJoysticks(int stick) +void joystickDialog::populateSourceCombo(QComboBox * cb) +{ + int i; + const QString axes[] = { + tr("Left Horizontal"), + tr("Left Vertical"), + tr("Right Vertical"), + tr("Right Horizontal") + }; + cb->clear(); + cb->addItem(tr("Not Assigned"), -1); + for (i=0; i < 4; ++i) { + cb->addItem(axes[i] % tr(" Stick"), i); + } + for (; i < CPN_MAX_STICKS + CPN_MAX_POTS; ++i) { + cb->addItem(tr("Knob/Slider %1").arg(i - CPN_MAX_STICKS + 1), i); + } +} + +bool joystickDialog::loadJoysticks(int stick) { QStringList joystickNames; bool found = false; @@ -101,23 +129,19 @@ void joystickDialog::loadJoysticks(int stick) joystick->close(); } ui->joystickCB->insertItems(0, joystickNames); - if (found && stick < joystickNames.size()) + if (found && stick < joystickNames.size()) { ui->joystickCB->setCurrentIndex(stick); - else if (!found) - ui->joystickCB->setCurrentIndex(0); - - joystickSetEnabled(found && ui->joystickChkB->isChecked()); + } + else if (!found) { + joystickSetEnabled(false); + } + return found; } void joystickDialog::joystickOpen(int stick) { - if (stick == -1 || !ui->joystickChkB->isChecked() || !ui->joystickCB->isEnabled()) { - ui->calibrationWidget->setDisabled(true); + if (stick < 0) return; - } - - ui->calibrationWidget->setEnabled(true); - ui->nextButton->setEnabled(true); joystick = new Joystick(this, 1, false, 0); if (joystick && joystick->open(stick)) { @@ -138,8 +162,6 @@ void joystickDialog::joystickSetEnabled(bool enable) ui->calibrationWidget->setEnabled(enable); ui->nextButton->setEnabled(enable && step < 4); ui->backButton->setEnabled(enable && step); - if (enable) - joystickOpen(ui->joystickCB->currentIndex()); } void joystickDialog::onjoystickAxisValueChanged(int axis, int value) @@ -229,6 +251,9 @@ void joystickDialog::on_okButton_clicked() g.jsSupport(ui->joystickChkB->isChecked()); g.jsCtrl(ui->joystickCB->currentIndex()); + if (joystick) + joystick->close(); + if (!g.jsSupport() || g.jsCtrl() < 0) { this->accept(); return; @@ -241,31 +266,20 @@ void joystickDialog::on_okButton_clicked() return; } - int stickAssignments[MAX_JOYSTICKS] = {0}; - for (int i = 0; i < MAX_JOYSTICKS; ++i) { - stick = sticks[i]->currentIndex() - 1; - if (stick >= 0 && stick < MAX_JOYSTICKS && ++stickAssignments[stick] > 1) { - QMessageBox::critical(this, tr("Error"), tr("Duplicated stick assignment!")); - return; + stick = sticks[i]->currentData().toInt(); + if (stick < 0) { + g.joystick[i].stick_axe(-1); + } + else { + g.joystick[i].stick_axe(stick); + g.joystick[i].stick_max(jscal[i][2]); + g.joystick[i].stick_med(jscal[i][1]); + g.joystick[i].stick_min(jscal[i][0]); + g.joystick[i].stick_inv(invert[i]->isChecked() ); + qDebug() << "joystick mapping " << sticks[i]->objectName() << "stick:" << i << "axe:" << stick; } } - joystick->close(); - - for (int i = 0; i < MAX_JOYSTICKS; ++i) - g.joystick[i].remove(); - - for (int i = 0; i < MAX_JOYSTICKS; ++i) { - stick = sticks[i]->currentIndex() - 1; - qDebug() << "joystick mapping " << sticks[i]->objectName() << "axe:" << i << "stick:" << stick; - if (stick >= 0 && stick < MAX_JOYSTICKS) { - g.joystick[stick].stick_axe( i ); - g.joystick[stick].stick_max( jscal[i][2] ); - g.joystick[stick].stick_med( jscal[i][1] ); - g.joystick[stick].stick_min( jscal[i][0] ); - g.joystick[stick].stick_inv( invert[i]->isChecked() ); - } - } this->accept(); } diff --git a/companion/src/simulation/joystickdialog.h b/companion/src/simulation/joystickdialog.h index 8c6fb5555..cdb85593a 100644 --- a/companion/src/simulation/joystickdialog.h +++ b/companion/src/simulation/joystickdialog.h @@ -53,7 +53,8 @@ class joystickDialog : public QDialog bool started; private slots: - void loadJoysticks(int stick = -1); + void populateSourceCombo(QComboBox * cb); + bool loadJoysticks(int stick = -1); void joystickOpen(int stick); void joystickSetEnabled(bool enable); void onjoystickAxisValueChanged(int axis, int value); diff --git a/companion/src/simulation/joystickdialog.ui b/companion/src/simulation/joystickdialog.ui index d52c6ceb5..eb2be2965 100644 --- a/companion/src/simulation/joystickdialog.ui +++ b/companion/src/simulation/joystickdialog.ui @@ -6,8 +6,8 @@ 0 0 - 473 - 335 + 554 + 351 @@ -90,51 +90,6 @@ 1 - - - Not Assigned - - - - - Right Vertical - - - - - Right Horizontal - - - - - Left Vertical - - - - - Left Horizontal - - - - - P1 - - - - - P2 - - - - - P3/LS - - - - - RS - - @@ -155,51 +110,6 @@ 2 - - - Not Assigned - - - - - Right Vertical - - - - - Right Horizontal - - - - - Left Vertical - - - - - Left Horizontal - - - - - P1 - - - - - P2 - - - - - P3/LS - - - - - RS - - @@ -241,51 +151,6 @@ 0 - - - Not Assigned - - - - - Right Vertical - - - - - Right Horizontal - - - - - Left Vertical - - - - - Left Horizontal - - - - - P1 - - - - - P2 - - - - - P3/LS - - - - - RS - - @@ -348,51 +213,6 @@ 4 - - - Not Assigned - - - - - Right Vertical - - - - - Right Horizontal - - - - - Left Vertical - - - - - Left Horizontal - - - - - P1 - - - - - P2 - - - - - P3/LS - - - - - RS - - @@ -434,51 +254,6 @@ 3 - - - Not Assigned - - - - - Right Vertical - - - - - Right Horizontal - - - - - Left Vertical - - - - - Left Horizontal - - - - - P1 - - - - - P2 - - - - - P3/LS - - - - - RS - - @@ -520,51 +295,6 @@ 5 - - - Not Assigned - - - - - Right Vertical - - - - - Right Horizontal - - - - - Left Vertical - - - - - Left Horizontal - - - - - P1 - - - - - P2 - - - - - P3/LS - - - - - RS - - @@ -620,51 +350,6 @@ 6 - - - Not Assigned - - - - - Right Vertical - - - - - Right Horizontal - - - - - Left Vertical - - - - - Left Horizontal - - - - - P1 - - - - - P2 - - - - - P3/LS - - - - - RS - - @@ -713,51 +398,6 @@ 7 - - - Not Assigned - - - - - Right Vertical - - - - - Right Horizontal - - - - - Left Vertical - - - - - Left Horizontal - - - - - P1 - - - - - P2 - - - - - P3/LS - - - - - RS - - diff --git a/companion/src/simulation/simulatorwidget.cpp b/companion/src/simulation/simulatorwidget.cpp index cdb23f3d9..0becb63e9 100644 --- a/companion/src/simulation/simulatorwidget.cpp +++ b/companion/src/simulation/simulatorwidget.cpp @@ -584,25 +584,9 @@ void SimulatorWidget::setupRadioWidgets() void SimulatorWidget::setupJoysticks() { #ifdef JOYSTICKS - static bool joysticksEnabled = false; - if (g.jsSupport() && g.jsCtrl() > -1) { - int count=0, axe; - for (int j=0; j < MAX_JOYSTICKS; j++){ - axe = g.joystick[j].stick_axe(); - if (axe >= 0 && axe < MAX_JOYSTICKS) { - jsmap[axe] = j + 1; - jscal[axe][0] = g.joystick[j].stick_min(); - jscal[axe][1] = g.joystick[j].stick_med(); - jscal[axe][2] = g.joystick[j].stick_max(); - jscal[axe][3] = g.joystick[j].stick_inv(); - count++; - } - } - if (count<3) { - QMessageBox::critical(this, tr("Warning"), tr("Joystick enabled but not configured correctly")); - return; - } + bool joysticksEnabled = false; + if (g.jsSupport() && g.jsCtrl() > -1) { if (!joystick) joystick = new Joystick(this); else @@ -614,24 +598,26 @@ void SimulatorWidget::setupJoysticks() joystick->sensitivities[j] = 0; joystick->deadzones[j] = 0; } - //mode 1,3 -> THR on right - vJoyRight->setStickConstraint(VirtualJoystickWidget::HOLD_Y, true); - vJoyRight->setStickConstraint(VirtualJoystickWidget::HOLD_X, true); - vJoyLeft->setStickConstraint(VirtualJoystickWidget::HOLD_Y, true); - vJoyLeft->setStickConstraint(VirtualJoystickWidget::HOLD_X, true); - connect(joystick, SIGNAL(axisValueChanged(int, int)), this, SLOT(onjoystickAxisValueChanged(int, int))); + connect(joystick, &Joystick::axisValueChanged, this, &SimulatorWidget::onjoystickAxisValueChanged); joysticksEnabled = true; } else { QMessageBox::critical(this, tr("Warning"), tr("Cannot open joystick, joystick disabled")); } } - else if (joysticksEnabled && joystick) { + else if (joystick) { + joystick->close(); disconnect(joystick, 0, this, 0); - vJoyRight->setStickConstraint(VirtualJoystickWidget::HOLD_Y, false); - vJoyRight->setStickConstraint(VirtualJoystickWidget::HOLD_X, false); - vJoyLeft->setStickConstraint(VirtualJoystickWidget::HOLD_Y, false); - vJoyLeft->setStickConstraint(VirtualJoystickWidget::HOLD_X, false); + joystick->deleteLater(); + joystick = NULL; + } + if (vJoyRight) { + vJoyRight->setStickConstraint(VirtualJoystickWidget::HOLD_X, joysticksEnabled); + vJoyRight->setStickConstraint(VirtualJoystickWidget::HOLD_Y, joysticksEnabled); + } + if (vJoyLeft) { + vJoyLeft->setStickConstraint(VirtualJoystickWidget::HOLD_X, joysticksEnabled); + vJoyLeft->setStickConstraint(VirtualJoystickWidget::HOLD_Y, joysticksEnabled); } #endif } @@ -860,38 +846,46 @@ void SimulatorWidget::centerSticks() void SimulatorWidget::onjoystickAxisValueChanged(int axis, int value) { #ifdef JOYSTICKS - int stick; - if (axis>=0 && axis<=8) { - stick=jsmap[axis]; - int stickval; - if (value>jscal[axis][1]) { - if ((jscal[axis][2]-jscal[axis][1])==0) - return; - stickval=(1024*(value-jscal[axis][1]))/(jscal[axis][2]-jscal[axis][1]); - } - else { - if ((jscal[axis][1]-jscal[axis][0])==0) - return; - stickval=(1024*(value-jscal[axis][1]))/(jscal[axis][1]-jscal[axis][0]); - } - if (jscal[axis][3]==1) { - stickval*=-1; - } - if (stick==1 ) { - vJoyRight->setStickY(-stickval/1024.0); - } - else if (stick==2) { - vJoyRight->setStickX(stickval/1024.0); - } - else if (stick==3) { - vJoyLeft->setStickY(-stickval/1024.0); - } - else if (stick==4) { - vJoyLeft->setStickX(stickval/1024.0); - } - else if (stick >= 5 && stick < 5 + analogs.count()) { - analogs[stick-5]->setValue(stickval); - } + static const int ttlSticks = CPN_MAX_STICKS; + static const int valueRange = 1024; + + if (!joystick || axis >= MAX_JOYSTICKS) + return; + + int dlta; + int stick = g.joystick[axis].stick_axe(); + + if (stick < 0 || stick >= ttlSticks + analogs.count()) + return; + + int stickval = valueRange * (value - g.joystick[axis].stick_med()); + + if (value > g.joystick[axis].stick_med()) { + if ((dlta = g.joystick[axis].stick_max() - g.joystick[axis].stick_med())) + stickval /= dlta; } + else if ((dlta = g.joystick[axis].stick_med() - g.joystick[axis].stick_min())) { + stickval /= dlta; + } + + if (g.joystick[axis].stick_inv()) + stickval *= -1; + + if (stick==1 ) { + vJoyRight->setStickY(-stickval/1024.0); + } + else if (stick==2) { + vJoyRight->setStickX(stickval/1024.0); + } + else if (stick==3) { + vJoyLeft->setStickY(-stickval/1024.0); + } + else if (stick==4) { + vJoyLeft->setStickX(stickval/1024.0); + } + else if (stick > ttlSticks) { + analogs[stick-ttlSticks-1]->setValue(stickval); + } + #endif } diff --git a/companion/src/simulation/simulatorwidget.h b/companion/src/simulation/simulatorwidget.h index 78c5d311b..727200252 100644 --- a/companion/src/simulation/simulatorwidget.h +++ b/companion/src/simulation/simulatorwidget.h @@ -137,8 +137,6 @@ class SimulatorWidget : public QWidget #ifdef JOYSTICKS Joystick *joystick; - int jscal[8][4]; - int jsmap[8]; #endif private slots: From 919e8eb9620b653ef0410bc9625bcc7a3dc2a547 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Wed, 22 Mar 2017 16:03:17 -0400 Subject: [PATCH 021/203] [build] Only build companion/simulator resources files once. (#4670) * [build] Only build companion/simulator resources files once and include in common lib; Consolidate/cosmetics. * [build] Fix "missing" translation resource files with some builds (since last commit); move resource file declarations to after app init as recommended; fix name of Qt translation file since v5.3 (this still only works on some systems with Qt installed and on the build machine). --- companion/src/CMakeLists.txt | 58 ++++++++++++++++-------------------- companion/src/companion.cpp | 19 +++++++----- companion/src/simulator.cpp | 18 +++++++---- 3 files changed, 50 insertions(+), 45 deletions(-) diff --git a/companion/src/CMakeLists.txt b/companion/src/CMakeLists.txt index 9233a1486..b63eb5edf 100644 --- a/companion/src/CMakeLists.txt +++ b/companion/src/CMakeLists.txt @@ -100,6 +100,7 @@ use_cxx11() # ensure gnu++11 in CXX_FLAGS with CMake < 3.1 include_directories( ${CMAKE_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_SOURCE_DIR} ${COMPANION_SRC_DIRECTORY} ${COMPANION_SRC_DIRECTORY}/shared ${SIMU_SRC_DIRECTORY} @@ -109,6 +110,11 @@ include_directories( ${COMPANION_SRC_DIRECTORY}/storage ) +configure_file(${COMPANION_SRC_DIRECTORY}/version.h.in ${CMAKE_BINARY_DIR}/version.h @ONLY) +configure_file(${COMPANION_SRC_DIRECTORY}/translations.qrc.in ${CMAKE_CURRENT_BINARY_DIR}/translations.qrc @ONLY) +configure_file(${COMPANION_SRC_DIRECTORY}/companion.desktop.in ${CMAKE_CURRENT_BINARY_DIR}/companion.desktop @ONLY) +configure_file(${COMPANION_SRC_DIRECTORY}/simulator.desktop.in ${CMAKE_CURRENT_BINARY_DIR}/simulator.desktop @ONLY) + ############# Supporting libraries ############### add_subdirectory(shared) @@ -144,11 +150,25 @@ set(common_MOC_HDRS modeledit/node.h ) -qt5_wrap_cpp(common_SRCS ${common_MOC_HDRS}) +set(common_RESOURCES + companion.qrc + ${CMAKE_CURRENT_BINARY_DIR}/translations.qrc + ) -add_library(common ${common_SRCS}) +set(LANGUAGES pl de fr es it sv cs fi zh) +foreach(language ${LANGUAGES}) + list(APPEND common_TS translations/companion_${language}.ts) +endforeach(language) + +qt5_wrap_cpp(common_SRCS ${common_MOC_HDRS}) +qt5_add_translation(common_QM ${common_TS}) +qt5_add_resources(common_RCC ${common_RESOURCES}) +add_custom_target(gen_qrc DEPENDS ${common_RCC} ${common_QM}) + +add_library(common ${common_SRCS} ${common_RCC}) qt5_use_modules(common Core Xml Widgets) -target_link_libraries(common simulation) +target_link_libraries(common PRIVATE simulation) +add_dependencies(common gen_qrc) ############# Companion ############### @@ -238,39 +258,15 @@ set(companion_UIS radionotfound.ui ) -set(companion_RESOURCES - companion.qrc - ${CMAKE_CURRENT_BINARY_DIR}/translations.qrc - ) - -configure_file(${COMPANION_SRC_DIRECTORY}/version.h.in ${CMAKE_BINARY_DIR}/version.h @ONLY) -configure_file(${COMPANION_SRC_DIRECTORY}/translations.qrc.in ${CMAKE_CURRENT_BINARY_DIR}/translations.qrc @ONLY) -configure_file(${COMPANION_SRC_DIRECTORY}/companion.desktop.in ${CMAKE_CURRENT_BINARY_DIR}/companion.desktop @ONLY) -configure_file(${COMPANION_SRC_DIRECTORY}/simulator.desktop.in ${CMAKE_CURRENT_BINARY_DIR}/simulator.desktop @ONLY) - if(WIN32) list(APPEND companion_SRCS icon.rc) endif() -include_directories(${CMAKE_BINARY_DIR}) -include_directories(${CMAKE_SOURCE_DIR}) - -set(LANGUAGES pl de fr es it sv cs fi zh) -foreach(language ${LANGUAGES}) - list(APPEND companion_TS translations/companion_${language}.ts) -endforeach(language) - qt5_wrap_ui(companion_SRCS ${companion_UIS}) qt5_wrap_cpp(companion_SRCS ${companion_MOC_HDRS}) -qt5_add_translation(companion_QM ${companion_TS}) -qt5_add_resources(companion_RCC ${companion_RESOURCES}) -add_custom_target(gen_qrc DEPENDS ${companion_RCC} ${companion_QM}) -add_executable(${COMPANION_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${companion_SRCS} ${companion_RCC}) - -add_dependencies(${COMPANION_NAME} gen_qrc) +add_executable(${COMPANION_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${companion_SRCS}) qt5_use_modules(${COMPANION_NAME} Core Widgets Network) - target_link_libraries(${COMPANION_NAME} PRIVATE generaledit modeledit simulation common qcustomplot shared storage ${PTHREAD_LIBRARY} ${SDL_LIBRARY} ${WIN_LINK_LIBRARIES}) PrintTargetReport("${COMPANION_NAME}") @@ -283,9 +279,7 @@ if(WIN32) list(APPEND simu_SRCS icon.rc) endif() -add_executable(${SIMULATOR_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${simu_SRCS} ${companion_RCC}) -add_dependencies(${SIMULATOR_NAME} gen_qrc) - +add_executable(${SIMULATOR_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${simu_SRCS}) target_link_libraries(${SIMULATOR_NAME} PRIVATE simulation common storage qxtcommandoptions ${PTHREAD_LIBRARY} ${SDL_LIBRARY} ${WIN_LINK_LIBRARIES}) ############# Translations #################### @@ -295,7 +289,7 @@ if(LUPDATE_FOUND) message(STATUS "Qt lupdate: " ${LUPDATE_EXECUTABLE}) add_custom_target(translations WORKING_DIRECTORY ${COMPANION_SRC_DIRECTORY} - COMMAND ${LUPDATE_EXECUTABLE} ${CMAKE_SOURCE_DIR} -no-obsolete -ts ${companion_TS} + COMMAND ${LUPDATE_EXECUTABLE} ${CMAKE_SOURCE_DIR} -no-obsolete -ts ${common_TS} ) else() message(STATUS "Qt lupdate not found, 'translations' target will not be availabe.") diff --git a/companion/src/companion.cpp b/companion/src/companion.cpp index 297b5613f..9bf411a48 100644 --- a/companion/src/companion.cpp +++ b/companion/src/companion.cpp @@ -51,17 +51,17 @@ class MyProxyStyle : public QProxyStyle int main(int argc, char *argv[]) { - Q_INIT_RESOURCE(companion); - -#if (QT_VERSION >= QT_VERSION_CHECK(5, 6, 0)) - QApplication::setAttribute(Qt::AA_EnableHighDpiScaling); -#endif - QApplication app(argc, argv); app.setApplicationName(APP_COMPANION); app.setOrganizationName(COMPANY); app.setOrganizationDomain(COMPANY_DOMAIN); app.setAttribute(Qt::AA_DontShowIconsInMenus, false); +#if (QT_VERSION >= QT_VERSION_CHECK(5, 6, 0)) + app.setAttribute(Qt::AA_EnableHighDpiScaling); +#endif + + Q_INIT_RESOURCE(companion); + Q_INIT_RESOURCE(translations); if (AppDebugMessageHandler::instance()) AppDebugMessageHandler::instance()->installAppMessageHandler(); @@ -84,7 +84,12 @@ int main(int argc, char *argv[]) QTranslator companionTranslator; companionTranslator.load(":/companion_" + g.locale()); QTranslator qtTranslator; - qtTranslator.load((QString)"qt_" + g.locale().left(2), QLibraryInfo::location(QLibraryInfo::TranslationsPath)); +#if (QT_VERSION >= QT_VERSION_CHECK(5, 3, 0)) + QString qtfile = "qtbase_"; +#else + QString qtfile = "qt_"; +#endif + qtTranslator.load(qtfile + g.locale().left(2), QLibraryInfo::location(QLibraryInfo::TranslationsPath)); app.installTranslator(&companionTranslator); app.installTranslator(&qtTranslator); diff --git a/companion/src/simulator.cpp b/companion/src/simulator.cpp index ecd6a2556..d99a06313 100644 --- a/companion/src/simulator.cpp +++ b/companion/src/simulator.cpp @@ -73,16 +73,17 @@ void sharedHelpText(QTextStream &stream) int main(int argc, char *argv[]) { - Q_INIT_RESOURCE(companion); - -#if (QT_VERSION >= QT_VERSION_CHECK(5, 6, 0)) - QApplication::setAttribute(Qt::AA_EnableHighDpiScaling); -#endif QApplication app(argc, argv); app.setApplicationName(APP_SIMULATOR); app.setOrganizationName(COMPANY); app.setOrganizationDomain(COMPANY_DOMAIN); +#if (QT_VERSION >= QT_VERSION_CHECK(5, 6, 0)) + app.setAttribute(Qt::AA_EnableHighDpiScaling); +#endif + + Q_INIT_RESOURCE(companion); + Q_INIT_RESOURCE(translations); if (AppDebugMessageHandler::instance()) AppDebugMessageHandler::instance()->installAppMessageHandler(); @@ -96,7 +97,12 @@ int main(int argc, char *argv[]) QTranslator companionTranslator; companionTranslator.load(":/companion_" + g.locale()); QTranslator qtTranslator; - qtTranslator.load((QString)"qt_" + g.locale().left(2), QLibraryInfo::location(QLibraryInfo::TranslationsPath)); +#if (QT_VERSION >= QT_VERSION_CHECK(5, 3, 0)) + QString qtfile = "qtbase_"; +#else + QString qtfile = "qt_"; +#endif + qtTranslator.load(qtfile + g.locale().left(2), QLibraryInfo::location(QLibraryInfo::TranslationsPath)); app.installTranslator(&companionTranslator); app.installTranslator(&qtTranslator); From d68778ec8150a8d10bf7da144bc3d8c4ff1bcdfa Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Wed, 22 Mar 2017 16:05:27 -0400 Subject: [PATCH 022/203] [Simulator] Virtual joystick tweaks. (#4666) * [Simulator] Create a reusable RadioTrimWidget; Move all trim-related enums to boards.h; Make sure aux trims are accounted for in SimulatorInterface; Trims now use toolbuttons with icons instead of pushbuttons with text. * [Simulator] New buttons & icons for virtual joystick axis hold/fix toggles; Joystick ball is now slightly scaled to stick area. * [Simulator] Virtual joystick now "follows" mouse clicks within the stick area (left-click on empty space will attract the control node). --- companion/src/boards.h | 45 ++- companion/src/companion.qrc | 8 + .../images/simulator/icons/svg/fixed_x-on.svg | 18 ++ .../images/simulator/icons/svg/fixed_x.svg | 18 ++ .../images/simulator/icons/svg/fixed_y-on.svg | 18 ++ .../images/simulator/icons/svg/fixed_y.svg | 18 ++ .../images/simulator/icons/svg/hold_x-on.svg | 19 ++ .../src/images/simulator/icons/svg/hold_x.svg | 19 ++ .../images/simulator/icons/svg/hold_y-on.svg | 19 ++ .../src/images/simulator/icons/svg/hold_y.svg | 19 ++ companion/src/modeledit/node.h | 25 +- companion/src/radiodata.h | 20 +- companion/src/simulation/CMakeLists.txt | 1 + companion/src/simulation/simulatorinterface.h | 2 +- companion/src/simulation/simulatorwidget.cpp | 63 ++-- companion/src/simulation/simulatorwidget.h | 8 +- .../src/simulation/widgets/radiotrimwidget.h | 134 +++++++++ .../src/simulation/widgets/radiowidget.cpp | 6 +- .../src/simulation/widgets/radiowidget.h | 6 +- .../src/simulation/widgets/sliderwidget.h | 1 + .../widgets/virtualjoystickwidget.cpp | 283 +++++++++--------- .../widgets/virtualjoystickwidget.h | 58 ++-- radio/src/targets/simu/opentxsimulator.cpp | 2 +- 23 files changed, 556 insertions(+), 254 deletions(-) create mode 100644 companion/src/images/simulator/icons/svg/fixed_x-on.svg create mode 100644 companion/src/images/simulator/icons/svg/fixed_x.svg create mode 100644 companion/src/images/simulator/icons/svg/fixed_y-on.svg create mode 100644 companion/src/images/simulator/icons/svg/fixed_y.svg create mode 100644 companion/src/images/simulator/icons/svg/hold_x-on.svg create mode 100644 companion/src/images/simulator/icons/svg/hold_x.svg create mode 100644 companion/src/images/simulator/icons/svg/hold_y-on.svg create mode 100644 companion/src/images/simulator/icons/svg/hold_y.svg create mode 100644 companion/src/simulation/widgets/radiotrimwidget.h diff --git a/companion/src/boards.h b/companion/src/boards.h index ab8ede1f2..96420498b 100644 --- a/companion/src/boards.h +++ b/companion/src/boards.h @@ -66,6 +66,42 @@ namespace Board { SWITCH_3POS }; + enum TrimAxes { + TRIM_AXIS_LH = 0, + TRIM_AXIS_LV, + TRIM_AXIS_RV, + TRIM_AXIS_RH, + TRIM_AXIS_T5, + TRIM_AXIS_T6, + }; + + enum TrimSwitchIndex + { + TRIM_SW_LH_DEC, + TRIM_SW_LH_INC, + TRIM_SW_LV_DEC, + TRIM_SW_LV_INC, + TRIM_SW_RV_DEC, + TRIM_SW_RV_INC, + TRIM_SW_RH_DEC, + TRIM_SW_RH_INC, + TRIM_SW_T5_DEC, + TRIM_SW_T5_INC, + TRIM_SW_T6_DEC, + TRIM_SW_T6_INC, + TRIM_SW_ENUM_END + }; + + enum Capability { + Pots, + Sliders, + MouseAnalogs, + Switches, + FactoryInstalledSwitches, + NumTrims, + NumTrimSwitches + }; + struct SwitchInfo { SwitchType config; @@ -82,15 +118,6 @@ namespace Board { unsigned int position; }; - enum Capability { - Pots, - Sliders, - MouseAnalogs, - Switches, - FactoryInstalledSwitches, - NumTrims, - NumTrimSwitches - }; } // TODO remove all those constants diff --git a/companion/src/companion.qrc b/companion/src/companion.qrc index 4a97f106c..cbd77a2d8 100644 --- a/companion/src/companion.qrc +++ b/companion/src/companion.qrc @@ -17,6 +17,14 @@ images/simulator/icons/svg/console.svg images/simulator/icons/svg/eraser.svg images/simulator/icons/svg/eraser-active.svg + images/simulator/icons/svg/fixed_x.svg + images/simulator/icons/svg/fixed_x-on.svg + images/simulator/icons/svg/fixed_y.svg + images/simulator/icons/svg/fixed_y-on.svg + images/simulator/icons/svg/hold_x.svg + images/simulator/icons/svg/hold_x-on.svg + images/simulator/icons/svg/hold_y.svg + images/simulator/icons/svg/hold_y-on.svg images/simulator/icons/svg/info.svg images/simulator/icons/svg/info-active.svg images/simulator/icons/svg/joystick_settings.svg diff --git a/companion/src/images/simulator/icons/svg/fixed_x-on.svg b/companion/src/images/simulator/icons/svg/fixed_x-on.svg new file mode 100644 index 000000000..3a9a7022b --- /dev/null +++ b/companion/src/images/simulator/icons/svg/fixed_x-on.svg @@ -0,0 +1,18 @@ + + + + + + + + image/svg+xml + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/fixed_x.svg b/companion/src/images/simulator/icons/svg/fixed_x.svg new file mode 100644 index 000000000..767a9a43a --- /dev/null +++ b/companion/src/images/simulator/icons/svg/fixed_x.svg @@ -0,0 +1,18 @@ + + + + + + + + image/svg+xml + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/fixed_y-on.svg b/companion/src/images/simulator/icons/svg/fixed_y-on.svg new file mode 100644 index 000000000..319b784ef --- /dev/null +++ b/companion/src/images/simulator/icons/svg/fixed_y-on.svg @@ -0,0 +1,18 @@ + + + + + + + + image/svg+xml + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/fixed_y.svg b/companion/src/images/simulator/icons/svg/fixed_y.svg new file mode 100644 index 000000000..e6b15140a --- /dev/null +++ b/companion/src/images/simulator/icons/svg/fixed_y.svg @@ -0,0 +1,18 @@ + + + + + + + + image/svg+xml + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/hold_x-on.svg b/companion/src/images/simulator/icons/svg/hold_x-on.svg new file mode 100644 index 000000000..81808417a --- /dev/null +++ b/companion/src/images/simulator/icons/svg/hold_x-on.svg @@ -0,0 +1,19 @@ + + + + + + + + image/svg+xml + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/hold_x.svg b/companion/src/images/simulator/icons/svg/hold_x.svg new file mode 100644 index 000000000..c65cf5514 --- /dev/null +++ b/companion/src/images/simulator/icons/svg/hold_x.svg @@ -0,0 +1,19 @@ + + + + + + + + image/svg+xml + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/hold_y-on.svg b/companion/src/images/simulator/icons/svg/hold_y-on.svg new file mode 100644 index 000000000..4058d326c --- /dev/null +++ b/companion/src/images/simulator/icons/svg/hold_y-on.svg @@ -0,0 +1,19 @@ + + + + + + + + image/svg+xml + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/hold_y.svg b/companion/src/images/simulator/icons/svg/hold_y.svg new file mode 100644 index 000000000..e620307b1 --- /dev/null +++ b/companion/src/images/simulator/icons/svg/hold_y.svg @@ -0,0 +1,19 @@ + + + + + + + + image/svg+xml + + + + + + + + + + + diff --git a/companion/src/modeledit/node.h b/companion/src/modeledit/node.h index b58437c01..b952a43e5 100644 --- a/companion/src/modeledit/node.h +++ b/companion/src/modeledit/node.h @@ -48,22 +48,25 @@ class Node : public QGraphicsObject void paint(QPainter *painter, const QStyleOptionGraphicsItem *option, QWidget *widget); void setBallSize(int size); void stepToCenter(qreal step=10); - int getBallSize() {return ballSize;} + int getBallSize() { return ballSize; } qreal getX(); qreal getY(); void setX(qreal newX); void setY(qreal newX); - void setCenteringX(bool val) {centerX = val;} - void setCenteringY(bool val) {centerY = val;} - void setFixedX(bool val) {fixedX = val;} - void setFixedY(bool val) {fixedY = val;} - bool getFixedX() {return fixedX;} - bool getFixedY() {return fixedY;} - void setMinX(int val) {minX = val;}; - void setMaxX(int val) {maxX = val;}; + void setCenteringX(bool val) { centerX = val; } + void setCenteringY(bool val) { centerY = val; } + void setFixedX(bool val) { fixedX = val; } + void setFixedY(bool val) { fixedY = val; } + bool getFixedX() { return fixedX; } + bool getFixedY() { return fixedY; } + void setMinX(int val) { minX = val; } + void setMaxX(int val) { maxX = val; } + void setPressed(bool pressed) { bPressed = pressed; } + bool isPressed() const { return bPressed; } + void setColor(const QColor & color); - + signals: void moved(int x, int y); void focus(); @@ -73,7 +76,7 @@ class Node : public QGraphicsObject QVariant itemChange(GraphicsItemChange change, const QVariant &value); void mousePressEvent(QGraphicsSceneMouseEvent *event); void mouseReleaseEvent(QGraphicsSceneMouseEvent *event); - + private: bool bPressed; bool centerX; diff --git a/companion/src/radiodata.h b/companion/src/radiodata.h index e5b8b8bc2..3c6b0af00 100644 --- a/companion/src/radiodata.h +++ b/companion/src/radiodata.h @@ -69,20 +69,6 @@ enum FailsafeModes { FAILSAFE_LAST = FAILSAFE_RECEIVER }; -#define TRIM_LH_L 0 -#define TRIM_LH_R 1 -#define TRIM_LV_DN 2 -#define TRIM_LV_UP 3 -#define TRIM_RV_DN 4 -#define TRIM_RV_UP 5 -#define TRIM_RH_L 6 -#define TRIM_RH_R 7 -#define TRIM_T5_DN 8 -#define TRIM_T5_UP 9 -#define TRIM_T6_DN 10 -#define TRIM_T6_UP 11 -#define TRIM_NONE 12 - #define CHAR_FOR_NAMES " ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789_-." #define CHAR_FOR_NAMES_REGEX "[ A-Za-z0-9_.-,]*" @@ -1010,9 +996,9 @@ class ModelData { ModelData(); ModelData(const ModelData & src); ModelData & operator = (const ModelData & src); - + void convert(Board::Type before, Board::Type after); - + ExpoData * insertInput(const int idx); void removeInput(const int idx); @@ -1248,7 +1234,7 @@ class RadioData { GeneralSettings generalSettings; std::vector categories; std::vector models; - + void convert(Board::Type before, Board::Type after); void setCurrentModel(unsigned int index); diff --git a/companion/src/simulation/CMakeLists.txt b/companion/src/simulation/CMakeLists.txt index ed9709e9b..d29ed78a9 100644 --- a/companion/src/simulation/CMakeLists.txt +++ b/companion/src/simulation/CMakeLists.txt @@ -51,6 +51,7 @@ set(simulation_HDRS widgets/radiofaderwidget.h widgets/radioknobwidget.h widgets/radioswitchwidget.h + widgets/radiotrimwidget.h widgets/sliderwidget.h widgets/virtualjoystickwidget.h ) diff --git a/companion/src/simulation/simulatorinterface.h b/companion/src/simulation/simulatorinterface.h index faec70191..7939f3715 100644 --- a/companion/src/simulation/simulatorinterface.h +++ b/companion/src/simulation/simulatorinterface.h @@ -57,7 +57,7 @@ class TxOutputs struct Trims { - int values[CPN_MAX_STICKS]; /* lh lv rv rh */ + int values[CPN_MAX_STICKS + CPN_MAX_AUX_TRIMS]; /* lh lv rv rh t5 t6 */ bool extended; }; diff --git a/companion/src/simulation/simulatorwidget.cpp b/companion/src/simulation/simulatorwidget.cpp index 0becb63e9..61e4d7bf9 100644 --- a/companion/src/simulation/simulatorwidget.cpp +++ b/companion/src/simulation/simulatorwidget.cpp @@ -55,7 +55,7 @@ SimulatorWidget::SimulatorWidget(QWidget * parent, SimulatorInterface *simulator flags(flags), lastPhase(-1), buttonPressed(0), - trimPressed(TRIM_NONE), + trimPressed(255), startupFromFile(false), deleteTempRadioData(false), saveTempRadioData(false), @@ -113,13 +113,13 @@ SimulatorWidget::SimulatorWidget(QWidget * parent, SimulatorInterface *simulator vJoyRight = new VirtualJoystickWidget(this, 'R'); ui->rightStickLayout->addWidget(vJoyRight); - connect(vJoyLeft, SIGNAL(trimButtonPressed(int)), this, SLOT(onTrimPressed(int))); - connect(vJoyLeft, SIGNAL(trimButtonReleased()), this, SLOT(onTrimReleased())); - connect(vJoyLeft, SIGNAL(trimSliderMoved(int,int)), this, SLOT(onTrimSliderMoved(int,int))); + connect(vJoyLeft, &VirtualJoystickWidget::trimButtonPressed, this, &SimulatorWidget::onTrimPressed); + connect(vJoyLeft, &VirtualJoystickWidget::trimButtonReleased, this, &SimulatorWidget::onTrimReleased); + connect(vJoyLeft, &VirtualJoystickWidget::trimSliderMoved, this, &SimulatorWidget::onTrimSliderMoved); - connect(vJoyRight, SIGNAL(trimButtonPressed(int)), this, SLOT(onTrimPressed(int))); - connect(vJoyRight, SIGNAL(trimButtonReleased()), this, SLOT(onTrimReleased())); - connect(vJoyRight, SIGNAL(trimSliderMoved(int,int)), this, SLOT(onTrimSliderMoved(int,int))); + connect(vJoyRight, &VirtualJoystickWidget::trimButtonPressed, this, &SimulatorWidget::onTrimPressed); + connect(vJoyRight, &VirtualJoystickWidget::trimButtonReleased, this, &SimulatorWidget::onTrimReleased); + connect(vJoyRight, &VirtualJoystickWidget::trimSliderMoved, this, &SimulatorWidget::onTrimSliderMoved); timer->setInterval(10); connect(timer, SIGNAL(timeout()), this, SLOT(onTimerEvent())); @@ -739,19 +739,19 @@ void SimulatorWidget::getValues() // Read stick trim values from firmware simulator and set joystick widgets as needed. void SimulatorWidget::setTrims() { - typedef VirtualJoystickWidget VJW; + using namespace Board; static Trims lastTrims; Trims trims; simulator->getTrims(trims); - if (trims.values[VJW::TRIM_AXIS_L_X] != lastTrims.values[VJW::TRIM_AXIS_L_X]) - vJoyLeft->setTrimValue(VJW::TRIM_AXIS_L_X, trims.values[VJW::TRIM_AXIS_L_X]); - if (trims.values[VJW::TRIM_AXIS_L_Y] != lastTrims.values[VJW::TRIM_AXIS_L_Y]) - vJoyLeft->setTrimValue(VJW::TRIM_AXIS_L_Y, trims.values[VJW::TRIM_AXIS_L_Y]); - if (trims.values[VJW::TRIM_AXIS_R_Y] != lastTrims.values[VJW::TRIM_AXIS_R_Y]) - vJoyRight->setTrimValue(VJW::TRIM_AXIS_R_Y, trims.values[VJW::TRIM_AXIS_R_Y]); - if (trims.values[VJW::TRIM_AXIS_R_X] != lastTrims.values[VJW::TRIM_AXIS_R_X]) - vJoyRight->setTrimValue(VJW::TRIM_AXIS_R_X, trims.values[VJW::TRIM_AXIS_R_X]); + if (trims.values[TRIM_AXIS_LH] != lastTrims.values[TRIM_AXIS_LH]) + vJoyLeft->setTrimValue(TRIM_AXIS_LH, trims.values[TRIM_AXIS_LH]); + if (trims.values[TRIM_AXIS_LV] != lastTrims.values[TRIM_AXIS_LV]) + vJoyLeft->setTrimValue(TRIM_AXIS_LV, trims.values[TRIM_AXIS_LV]); + if (trims.values[TRIM_AXIS_RV] != lastTrims.values[TRIM_AXIS_RV]) + vJoyRight->setTrimValue(TRIM_AXIS_RV, trims.values[TRIM_AXIS_RV]); + if (trims.values[TRIM_AXIS_RH] != lastTrims.values[TRIM_AXIS_RH]) + vJoyRight->setTrimValue(TRIM_AXIS_RH, trims.values[TRIM_AXIS_RH]); if (trims.extended != lastTrims.extended) { int trimMin = -125, trimMax = +125; @@ -759,10 +759,10 @@ void SimulatorWidget::setTrims() trimMin = -500; trimMax = +500; } - vJoyLeft->setTrimRange(VJW::TRIM_AXIS_L_X, trimMin, trimMax); - vJoyLeft->setTrimRange(VJW::TRIM_AXIS_L_Y, trimMin, trimMax); - vJoyRight->setTrimRange(VJW::TRIM_AXIS_R_Y, trimMin, trimMax); - vJoyRight->setTrimRange(VJW::TRIM_AXIS_R_X, trimMin, trimMax); + vJoyLeft->setTrimRange(TRIM_AXIS_LH, trimMin, trimMax); + vJoyLeft->setTrimRange(TRIM_AXIS_LV, trimMin, trimMax); + vJoyRight->setTrimRange(TRIM_AXIS_RV, trimMin, trimMax); + vJoyRight->setTrimRange(TRIM_AXIS_RH, trimMin, trimMax); } lastTrims = trims; } @@ -771,17 +771,6 @@ void SimulatorWidget::setTrims() * Event handlers/private slots */ -//void SimulatorDialog::showEvent(QShowEvent *) -//{ -// if (firstShow && isVisible()) { -// firstShow = false; -// } -//} - -//void SimulatorDialog::closeEvent(QCloseEvent *) -//{ -//} - void SimulatorWidget::mousePressEvent(QMouseEvent *event) { if (radioUiWidget) @@ -819,19 +808,19 @@ void SimulatorWidget::onTimerEvent() } } -void SimulatorWidget::onTrimPressed(int which) +void SimulatorWidget::onTrimPressed(int index) { - trimPressed = which; + trimPressed = index; } -void SimulatorWidget::onTrimReleased() +void SimulatorWidget::onTrimReleased(int) { - trimPressed = TRIM_NONE; + trimPressed = 255; } -void SimulatorWidget::onTrimSliderMoved(int which, int value) +void SimulatorWidget::onTrimSliderMoved(int index, int value) { - simulator->setTrim(which, value); + simulator->setTrim(index, value); } void SimulatorWidget::centerSticks() diff --git a/companion/src/simulation/simulatorwidget.h b/companion/src/simulation/simulatorwidget.h index 727200252..e7398039a 100644 --- a/companion/src/simulation/simulatorwidget.h +++ b/companion/src/simulation/simulatorwidget.h @@ -140,16 +140,14 @@ class SimulatorWidget : public QWidget #endif private slots: - //virtual void showEvent(QShowEvent *); - //virtual void closeEvent(QCloseEvent *); virtual void mousePressEvent(QMouseEvent *event); virtual void mouseReleaseEvent(QMouseEvent *event); virtual void wheelEvent(QWheelEvent *event); void onTimerEvent(); - void onTrimPressed(int which); - void onTrimReleased(); - void onTrimSliderMoved(int which, int value); + void onTrimPressed(int index); + void onTrimReleased(int); + void onTrimSliderMoved(int index, int value); void centerSticks(); void onjoystickAxisValueChanged(int axis, int value); diff --git a/companion/src/simulation/widgets/radiotrimwidget.h b/companion/src/simulation/widgets/radiotrimwidget.h new file mode 100644 index 000000000..a6f46bc89 --- /dev/null +++ b/companion/src/simulation/widgets/radiotrimwidget.h @@ -0,0 +1,134 @@ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _RADIOTRIMWIDGET_H_ +#define _RADIOTRIMWIDGET_H_ + +#include "radiowidget.h" +#include "sliderwidget.h" + +#include + +class RadioTrimWidget : public RadioWidget +{ + Q_OBJECT + + public: + + explicit RadioTrimWidget(Qt::Orientation orientation = Qt::Vertical, QWidget * parent = Q_NULLPTR, Qt::WindowFlags f = Qt::WindowFlags()) : + RadioWidget(parent, f), + m_slider(NULL) + { + init(orientation); + } + explicit RadioTrimWidget(const QString & labelText, Qt::Orientation orientation = Qt::Vertical, int value = 0, QWidget * parent = Q_NULLPTR, Qt::WindowFlags f = Qt::WindowFlags()) : + RadioWidget(labelText, value, parent, f), + m_slider(NULL) + { + init(orientation); + } + + void setIndices(int sliderIdx = -1, int decrBtnIdx = -1, int incrBtnIdx = -1) + { + setIndex(sliderIdx); + m_btnDecIndex = decrBtnIdx; + m_btnIncIndex = incrBtnIdx; + } + + void setTrimRange(int min, int max) + { + if (m_slider) + m_slider->setRange(min, max); + } + + signals: + + void trimButtonPressed(int index); + void trimButtonReleased(int index); + void trimSliderMoved(int index, int value); + + protected slots: + + void init(Qt::Orientation orientation) + { + m_type = RADIO_WIDGET_TRIM; + m_slider = new SliderWidget(this); + m_slider->setOrientation(orientation); + + setTrimRange(-125, 125); + setIndices(); + + QSize btnIcnSz(12, 12); + QWidget * trimWidget = new QWidget(this); + QBoxLayout * trimLayout = new QVBoxLayout(trimWidget); + trimLayout->setSpacing(5); + trimLayout->setContentsMargins(8, 8, 8, 8); + QToolButton * trimBtnInc = new QToolButton(trimWidget); + trimBtnInc->setIconSize(btnIcnSz); + QToolButton * trimBtnDec = new QToolButton(trimWidget); + trimBtnDec->setIconSize(btnIcnSz); + + Qt::Alignment algn; + if (orientation == Qt::Horizontal) { + trimWidget->setSizePolicy(QSizePolicy::Preferred, QSizePolicy::Fixed); + trimLayout->setDirection(QBoxLayout::RightToLeft); + trimBtnInc->setArrowType(Qt::RightArrow); + trimBtnDec->setArrowType(Qt::LeftArrow); + algn = Qt::AlignVCenter; + } + else { + trimWidget->setSizePolicy(QSizePolicy::Fixed, QSizePolicy::Preferred); + trimLayout->setDirection(QBoxLayout::TopToBottom); + trimBtnInc->setArrowType(Qt::UpArrow); + trimBtnDec->setArrowType(Qt::DownArrow); + algn = Qt::AlignHCenter; + } + + trimLayout->addWidget(trimBtnInc, 0, algn); + trimLayout->addWidget(m_slider, 1, algn); + trimLayout->addWidget(trimBtnDec, 0, algn); + + setWidget(trimWidget, algn); + + connect(m_slider, &SliderWidget::valueChanged, this, &RadioWidget::setValue); + connect(this, &RadioWidget::valueChanged, this, &RadioTrimWidget::onValueChanged); + + connect(trimBtnInc, &QToolButton::pressed, [this]() { emit trimButtonPressed(m_btnIncIndex); }); + connect(trimBtnInc, &QToolButton::released, [this]() { emit trimButtonReleased(m_btnIncIndex); }); + connect(trimBtnDec, &QToolButton::pressed, [this]() { emit trimButtonPressed(m_btnDecIndex); }); + connect(trimBtnDec, &QToolButton::released, [this]() { emit trimButtonReleased(m_btnDecIndex); }); + } + + void onValueChanged(int value) + { + m_slider->blockSignals(true); + m_slider->setValue(value); + m_slider->blockSignals(false); + emit trimSliderMoved(m_index, m_value); + } + + protected: + SliderWidget * m_slider; + int m_btnDecIndex; + int m_btnIncIndex; +}; + + +#endif // _RADIOTRIMWIDGET_H_ diff --git a/companion/src/simulation/widgets/radiowidget.cpp b/companion/src/simulation/widgets/radiowidget.cpp index f87522234..2e6d213dd 100644 --- a/companion/src/simulation/widgets/radiowidget.cpp +++ b/companion/src/simulation/widgets/radiowidget.cpp @@ -58,7 +58,7 @@ void RadioWidget::setValue(int value) { if (value != m_value) { m_value = value; - emit valueChanged(m_value); + emit valueChanged(value); } } @@ -166,7 +166,7 @@ void RadioWidget::addLabel() } } -void RadioWidget::setWidget(QWidget * widget) +void RadioWidget::setWidget(QWidget * widget, Qt::Alignment align) { if (m_controlWidget) { m_gridLayout->removeWidget(m_controlWidget); @@ -174,7 +174,7 @@ void RadioWidget::setWidget(QWidget * widget) } m_controlWidget = widget; if (widget) { - m_gridLayout->addWidget(widget, 0, 0, 1, 1, Qt::AlignHCenter); + m_gridLayout->addWidget(widget, 0, 0, 1, 1, align); m_gridLayout->setRowStretch(0, 1); } } diff --git a/companion/src/simulation/widgets/radiowidget.h b/companion/src/simulation/widgets/radiowidget.h index ad1b5bac7..aa9bb81ab 100644 --- a/companion/src/simulation/widgets/radiowidget.h +++ b/companion/src/simulation/widgets/radiowidget.h @@ -41,6 +41,7 @@ class RadioWidget : public QWidget RADIO_WIDGET_SWITCH, RADIO_WIDGET_KNOB, RADIO_WIDGET_FADER, + RADIO_WIDGET_TRIM, RADIO_WIDGET_STICK // actually one axis of a stick }; @@ -76,7 +77,6 @@ class RadioWidget : public QWidget void setStateData(const QByteArray & data); void changeVisibility(bool visible); - virtual int getValue() const; int getIndex() const; int getType() const; @@ -87,7 +87,7 @@ class RadioWidget : public QWidget void init(); void addLabel(); - void setWidget(QWidget * widget = NULL); + void setWidget(QWidget * widget = NULL, Qt::Alignment align = Qt::AlignHCenter); int m_value; int m_index; @@ -105,7 +105,7 @@ class RadioWidget : public QWidget signals: - void valueChanged(int m_value); + void valueChanged(int value); void flagsChanged(quint16 flags); }; diff --git a/companion/src/simulation/widgets/sliderwidget.h b/companion/src/simulation/widgets/sliderwidget.h index aa5140b82..f99ce570e 100644 --- a/companion/src/simulation/widgets/sliderwidget.h +++ b/companion/src/simulation/widgets/sliderwidget.h @@ -42,6 +42,7 @@ class SliderWidget : public QSlider { if (event->button() == Qt::RightButton && event->type() == QEvent::MouseButtonDblClick) { setValue(0); + emit sliderMoved(0); event->accept(); } QSlider::mousePressEvent(event); diff --git a/companion/src/simulation/widgets/virtualjoystickwidget.cpp b/companion/src/simulation/widgets/virtualjoystickwidget.cpp index 9242b01c4..dd250dcad 100644 --- a/companion/src/simulation/widgets/virtualjoystickwidget.cpp +++ b/companion/src/simulation/widgets/virtualjoystickwidget.cpp @@ -18,27 +18,32 @@ * GNU General Public License for more details. */ -#define GBALL_SIZE 20 -#define RESX 1024 +#define GBALL_SIZE 25 +#define GBALL_SIZE_MN 20 +#define GBALL_SIZE_MX 35 #include "virtualjoystickwidget.h" + +#include "boards.h" #include "constants.h" -#include "sliderwidget.h" #include "modeledit/node.h" #include "helpers.h" +#include "radiotrimwidget.h" +#include "simulator.h" VirtualJoystickWidget::VirtualJoystickWidget(QWidget *parent, QChar side, bool showTrims, bool showBtns, bool showValues, QSize size) : QWidget(parent), stickSide(side), prefSize(size), - hTrimSlider(NULL), - vTrimSlider(NULL), + hTrimWidget(NULL), + vTrimWidget(NULL), btnHoldX(NULL), btnHoldY(NULL), btnFixX(NULL), btnFixY(NULL), nodeLabelX(NULL), - nodeLabelY(NULL) + nodeLabelY(NULL), + m_stickPressed(false) { ar = (float)size.width() / size.height(); extraSize = QSize(0, 0); @@ -54,12 +59,11 @@ VirtualJoystickWidget::VirtualJoystickWidget(QWidget *parent, QChar side, bool s gv = new QGraphicsView(this); gv->setSizePolicy(sizePolicy); gv->setMinimumSize(size); -// gv->setMaximumSize(size + size * 3); -// gv->setFixedSize(prefSize); gv->setVerticalScrollBarPolicy(Qt::ScrollBarAlwaysOff); gv->setHorizontalScrollBarPolicy(Qt::ScrollBarAlwaysOff); + gv->setRenderHints(QPainter::Antialiasing); - scene = new QGraphicsScene(gv); + scene = new CustomGraphicsScene(gv); scene->setItemIndexMethod(QGraphicsScene::NoIndex); gv->setScene(scene); @@ -83,14 +87,12 @@ VirtualJoystickWidget::VirtualJoystickWidget(QWidget *parent, QChar side, bool s } if (showTrims) { - QWidget * hTrimWidget = createTrimWidget('H'); - QWidget * vTrimWidget = createTrimWidget('V'); + hTrimWidget = createTrimWidget('H'); + vTrimWidget = createTrimWidget('V'); layout->addWidget(vTrimWidget, 1, colvt, 1, 1); layout->addWidget(hTrimWidget, 2, 2, 1, 1); - hTrimSlider = hTrimWidget->findChild(); - vTrimSlider = vTrimWidget->findChild(); extraSize += QSize(vTrimWidget->sizeHint().width(), hTrimWidget->sizeHint().height()); } else { @@ -131,10 +133,12 @@ VirtualJoystickWidget::VirtualJoystickWidget(QWidget *parent, QChar side, bool s layout->addItem(new QSpacerItem(0, 0), 1, 0, 2, 1); // r1-2 c0: left h spacer layout->addWidget(gv, 1, 2, 1, 1); // r1 c2: stick widget layout->addItem(new QSpacerItem(0, 0), 1, 4, 2, 1); // r1-2 c4: right h spacer - layout->addItem(new QSpacerItem(0, 0), 3, 0, 1, 5); // r3 c0-4: bot v spacer + layout->addItem(new QSpacerItem(0, 0), 3, 0, 1, 5); // r4 c0-4: bot v spacer - connect(node, SIGNAL(xChanged()), this, SLOT(updateNodeValueLabels())); - connect(node, SIGNAL(yChanged()), this, SLOT(updateNodeValueLabels())); + connect(node, &Node::xChanged, this, &VirtualJoystickWidget::updateNodeValueLabels); + connect(node, &Node::yChanged, this, &VirtualJoystickWidget::updateNodeValueLabels); + + connect(scene, &CustomGraphicsScene::mouseEvent, this, &VirtualJoystickWidget::onGsMouseEvent); setSize(prefSize, frameSize()); } @@ -176,25 +180,25 @@ QPointF VirtualJoystickWidget::getStickPos() void VirtualJoystickWidget::setTrimValue(int which, int value) { - SliderWidget * slider = getTrimSlider(which); - if (slider) { - slider->setValue(value); + RadioTrimWidget * trim = getTrimWidget(which); + if (trim) { + trim->setValue(value); } } void VirtualJoystickWidget::setTrimRange(int which, int min, int max) { - SliderWidget * slider = getTrimSlider(which); - if (slider) { - slider->setRange(min, max); + RadioTrimWidget * trim = getTrimWidget(which); + if (trim) { + trim->setTrimRange(min, max); } } int VirtualJoystickWidget::getTrimValue(int which) { - SliderWidget * slider = getTrimSlider(which); - if (slider) { - return slider->value(); + RadioTrimWidget * trim = getTrimWidget(which); + if (trim) { + return trim->getValue(); } return 0; } @@ -269,13 +273,15 @@ void VirtualJoystickWidget::setSize(const QSize & size, const QSize &) layout->setColumnStretch(2, newGvSz); layout->setRowStretch(1, newGvSz); - //prefSize = QSize(newGvSz + extraSize.width(), newGvSz + extraSize.height()); gv->resize(newGvSz, newGvSz); gv->updateGeometry(); + int ballSize = (newGvSz * GBALL_SIZE * 0.005f); + ballSize = qMin(GBALL_SIZE_MX, qMax(ballSize, GBALL_SIZE_MN)); + QRectF qr = (QRectF)gv->contentsRect(); - qreal w = qr.width() - GBALL_SIZE; - qreal h = qr.height() - GBALL_SIZE; + qreal w = qr.width() - ballSize; + qreal h = qr.height() - ballSize; qreal cx = qr.width() / 2; qreal cy = qr.height() / 2; qreal nodeX = node->getX(); @@ -283,120 +289,64 @@ void VirtualJoystickWidget::setSize(const QSize & size, const QSize &) scene->setSceneRect(-cx,-cy,w,h); + node->setBallSize(ballSize); node->setX(nodeX); node->setY(nodeY); //qDebug() << thisAspectRatio << size << newGvSz << spacerSz << extraSize << gv->geometry() << gv->contentsRect() << gv->frameRect() << getStickPos(); } -QWidget *VirtualJoystickWidget::createTrimWidget(QChar type) +RadioTrimWidget * VirtualJoystickWidget::createTrimWidget(QChar type) { - QSizePolicy sp; - QString btnAlabel, btnBlabel; + RadioTrimWidget * trimWidget = new RadioTrimWidget(type == 'H' ? Qt::Horizontal : Qt::Vertical); + trimWidget->setIndices(getTrimSliderType(type), getTrimButtonType(type, 0), getTrimButtonType(type, 1)); - QString btnAname = QString("%1TrimBtnA_%2").arg(type.toLower()).arg(stickSide); - QString btnBname = QString("%1TrimBtnB_%2").arg(type.toLower()).arg(stickSide); - QString sliderName = QString("%1TrimAdj_%2").arg(type.toLower()).arg(stickSide); - - QWidget * trimWidget = new QWidget(this); - QBoxLayout * trimLayout = new QVBoxLayout(trimWidget); - SliderWidget * trimSlider = new SliderWidget(trimWidget); - QPushButton * trimBtnA = new QPushButton(trimWidget); - QPushButton * trimBtnB = new QPushButton(trimWidget); - - if (type == 'H') { - sp = QSizePolicy(QSizePolicy::Preferred, QSizePolicy::Fixed); - trimLayout->setDirection(QBoxLayout::LeftToRight); - trimSlider->setFixedHeight(23); - trimSlider->setOrientation(Qt::Horizontal); - trimBtnA->setText(ARROW_LEFT); - trimBtnB->setText(ARROW_RIGHT); - } - else { - sp = QSizePolicy(QSizePolicy::Fixed, QSizePolicy::Preferred); - trimLayout->setDirection(QBoxLayout::TopToBottom); - trimSlider->setFixedWidth(23); - trimSlider->setOrientation(Qt::Vertical); - trimBtnA->setText(ARROW_UP); - trimBtnB->setText(ARROW_DOWN); - } - - trimWidget->setSizePolicy(sp); - - trimSlider->setObjectName(sliderName); - trimSlider->setProperty("trimType", getTrimSliderType(type)); - trimSlider->setSizePolicy(sp); - trimSlider->setMinimum(-125); - trimSlider->setMaximum(125); - - trimBtnA->setObjectName(btnAname); - trimBtnA->setProperty("btnType", getTrimButtonType(type, 0)); - trimBtnA->setSizePolicy(QSizePolicy(QSizePolicy::Fixed, QSizePolicy::Fixed)); - trimBtnA->setMaximumSize(QSize(23, 23)); - trimBtnA->setAutoDefault(false); - - trimBtnB->setObjectName(btnBname); - trimBtnB->setProperty("btnType", getTrimButtonType(type, 1)); - trimBtnB->setSizePolicy(QSizePolicy(QSizePolicy::Fixed, QSizePolicy::Fixed)); - trimBtnB->setMaximumSize(QSize(23, 23)); - trimBtnB->setAutoDefault(false); - - trimLayout->setSpacing(6); - trimLayout->setContentsMargins(8, 9, 8, 9); - trimLayout->addWidget(trimBtnA); - trimLayout->addWidget(trimSlider); - trimLayout->addWidget(trimBtnB); - - connect(trimBtnA, SIGNAL(pressed()), SLOT(onTrimPressed())); - connect(trimBtnB, SIGNAL(pressed()), SLOT(onTrimPressed())); - connect(trimBtnA, SIGNAL(released()), SIGNAL(trimButtonReleased())); - connect(trimBtnB, SIGNAL(released()), SIGNAL(trimButtonReleased())); - connect(trimSlider, SIGNAL(valueChanged(int)), SLOT(onSliderChange(int))); + connect(trimWidget, &RadioTrimWidget::trimButtonPressed, this, &VirtualJoystickWidget::trimButtonPressed); + connect(trimWidget, &RadioTrimWidget::trimButtonReleased, this, &VirtualJoystickWidget::trimButtonReleased); + connect(trimWidget, &RadioTrimWidget::trimSliderMoved, this, &VirtualJoystickWidget::trimSliderMoved); return trimWidget; } -QPushButton * VirtualJoystickWidget::createButtonWidget(int type) +QToolButton * VirtualJoystickWidget::createButtonWidget(int type) { - QString btnRole, btnLabel; + QString btnLabel, tooltip; + QIcon icon; switch (type) { case HOLD_Y: - btnLabel = tr("Hold Y"); + btnLabel = tr("Hld Y"); + tooltip = tr("Hold Vertical stick position."); + icon = Simulator::SimulatorIcon("hold_y"); break; case FIX_Y: btnLabel = tr("Fix Y"); + tooltip = tr("Prevent Vertical movement of stick."); + icon = Simulator::SimulatorIcon("fixed_y"); break; case FIX_X: btnLabel = tr("Fix X"); + tooltip = tr("Prevent Horizontal movement of stick."); + icon = Simulator::SimulatorIcon("fixed_x"); break; case HOLD_X: - default: - btnLabel = tr("Hold X"); + btnLabel = tr("Hld X"); + tooltip = tr("Hold Horizontal stick position."); + icon = Simulator::SimulatorIcon("hold_x"); break; + default: + return NULL; } - QPushButton * btn = new QPushButton(this); - btn->setObjectName(QString("%1_%2").arg(btnLabel.replace(" ", "_")).arg(stickSide)); + QToolButton * btn = new QToolButton(this); btn->setProperty("btnType", type); + btn->setIcon(icon); + btn->setIconSize(QSize(20, 20)); + btn->setToolButtonStyle(Qt::ToolButtonIconOnly); btn->setText(btnLabel); - QFont font; - font.setPointSize(8); - btn->setFont(font); - btn->setStyleSheet(QLatin1String( \ - "QPushButton {" - " background-color: #EEEEEE;" - " border-style: outset;" - " border-width: 1px;" - " border-radius: 4px;" - " border-color: black;" - " padding: 2px;" - "}" - "QPushButton:checked {\n" - " background-color: #4CC417;\n" - " border-style: inset;\n" - "}" )); + btn->setToolTip(tooltip); btn->setCheckable(true); + btn->setAutoRaise(true); - connect(btn, SIGNAL(toggled(bool)), SLOT(onButtonChange(bool))); + connect(btn, &QToolButton::toggled, this, &VirtualJoystickWidget::onButtonChange); return btn; } @@ -423,76 +373,63 @@ QLayout *VirtualJoystickWidget::createNodeValueLayout(QChar type, QLabel *& valL int VirtualJoystickWidget::getTrimSliderType(QChar type) { + using namespace Board; + if (stickSide == 'L') { if (type == 'H') - return TRIM_AXIS_L_X; + return TRIM_AXIS_LH; else - return TRIM_AXIS_L_Y; + return TRIM_AXIS_LV; } else { if (type == 'H') - return TRIM_AXIS_R_X; + return TRIM_AXIS_RH; else - return TRIM_AXIS_R_Y; + return TRIM_AXIS_RV; } } int VirtualJoystickWidget::getTrimButtonType(QChar type, int pos) { + using namespace Board; + if (stickSide == 'L') { if (type == 'H') { if (pos == 0) - return TRIM_LH_L; + return TRIM_SW_LH_DEC; else - return TRIM_LH_R; + return TRIM_SW_LH_INC; } else { if (pos == 0) - return TRIM_LV_UP; + return TRIM_SW_LV_DEC; else - return TRIM_LV_DN; + return TRIM_SW_LV_INC; } } // right side else { if (type == 'H') { if (pos == 0) - return TRIM_RH_L; + return TRIM_SW_RH_DEC; else - return TRIM_RH_R; + return TRIM_SW_RH_INC; } else { if (pos == 0) - return TRIM_RV_UP; + return TRIM_SW_RV_DEC; else - return TRIM_RV_DN; + return TRIM_SW_RV_INC; } } } -SliderWidget *VirtualJoystickWidget::getTrimSlider(int which) +RadioTrimWidget * VirtualJoystickWidget::getTrimWidget(int which) { - if (which == TRIM_AXIS_L_X || which == TRIM_AXIS_R_X) - return hTrimSlider; + if (which == Board::TRIM_AXIS_LH || which == Board::TRIM_AXIS_RH) + return hTrimWidget; else - return vTrimSlider; -} - -void VirtualJoystickWidget::onTrimPressed() -{ - if (!sender() || !sender()->property("btnType").isValid()) - return; - - emit trimButtonPressed(sender()->property("btnType").toInt()); -} - -void VirtualJoystickWidget::onSliderChange(int value) -{ - if (!sender() || !sender()->property("trimType").isValid()) - return; - - emit trimSliderMoved(sender()->property("trimType").toInt(), value); - updateNodeValueLabels(); + return vTrimWidget; } void VirtualJoystickWidget::onButtonChange(bool checked) @@ -523,3 +460,57 @@ void VirtualJoystickWidget::updateNodeValueLabels() if (nodeLabelY) nodeLabelY->setText(QString("%1").arg((qreal)node->getY() * -100 + getTrimValue(1) / 5, 2, 'f', 0)); } + +void VirtualJoystickWidget::onGsMouseEvent(QGraphicsSceneMouseEvent * event) +{ + if (!node) + return; + + //qDebug() << event->type() << event->scenePos() << event->buttons() << event->isAccepted() << m_stickPressed; + if (event->type() == QEvent::GraphicsSceneMouseRelease && m_stickPressed) { + node->setPressed(false); + m_stickPressed = false; + return; + } + + if (!(event->buttons() & Qt::LeftButton)) + return; + + if (event->type() == QEvent::GraphicsSceneMousePress) { + node->setPressed(true); + m_stickPressed = true; + } + else if (!m_stickPressed || event->type() != QEvent::GraphicsSceneMouseMove) { + return; + } + node->setPos(event->scenePos()); +} + + +/* + * CustomGraphicsScene +*/ + +void CustomGraphicsScene::mousePressEvent(QGraphicsSceneMouseEvent * event) +{ + QGraphicsScene::mousePressEvent(event); + if (!event->isAccepted()) { + event->accept(); + emit mouseEvent(event); + } +} + +void CustomGraphicsScene::mouseReleaseEvent(QGraphicsSceneMouseEvent * event) +{ + QGraphicsScene::mouseReleaseEvent(event); + emit mouseEvent(event); +} + +void CustomGraphicsScene::mouseMoveEvent(QGraphicsSceneMouseEvent * event) +{ + QGraphicsScene::mouseMoveEvent(event); + if (!event->isAccepted() && (event->buttons() & Qt::LeftButton)) { + event->accept(); + emit mouseEvent(event); + } +} diff --git a/companion/src/simulation/widgets/virtualjoystickwidget.h b/companion/src/simulation/widgets/virtualjoystickwidget.h index 478f6398e..69faeddc1 100644 --- a/companion/src/simulation/widgets/virtualjoystickwidget.h +++ b/companion/src/simulation/widgets/virtualjoystickwidget.h @@ -27,24 +27,18 @@ #include #include #include -#include +#include #include +class CustomGraphicsScene; class Node; -class SliderWidget; +class RadioTrimWidget; class VirtualJoystickWidget : public QWidget { Q_OBJECT public: - enum TrimAxes { - TRIM_AXIS_L_X = 0, - TRIM_AXIS_L_Y, - TRIM_AXIS_R_Y, - TRIM_AXIS_R_X, - }; - enum ConstraintTypes { HOLD_X = 0, HOLD_Y, @@ -73,38 +67,60 @@ class VirtualJoystickWidget : public QWidget virtual void resizeEvent(QResizeEvent *event); signals: - void trimButtonPressed(int which); - void trimButtonReleased(); - void trimSliderMoved(int which, int value); + void trimButtonPressed(int index); + void trimButtonReleased(int index); + void trimSliderMoved(int index, int value); protected slots: - void onTrimPressed(); - void onSliderChange(int value); void onButtonChange(bool checked); void updateNodeValueLabels(); + void onGsMouseEvent(QGraphicsSceneMouseEvent * event); protected: void setSize(const QSize & size, const QSize &); - QWidget * createTrimWidget(QChar type); - QPushButton * createButtonWidget(int type); + RadioTrimWidget * createTrimWidget(QChar type); + QToolButton * createButtonWidget(int type); QLayout * createNodeValueLayout(QChar type, QLabel *& valLabel); int getTrimSliderType(QChar type); int getTrimButtonType(QChar type, int pos); - SliderWidget * getTrimSlider(int which); + RadioTrimWidget * getTrimWidget(int which); QChar stickSide; QSize prefSize; QGridLayout * layout; QGraphicsView * gv; - QGraphicsScene * scene; + CustomGraphicsScene * scene; Node * node; - SliderWidget * hTrimSlider, * vTrimSlider; - QPushButton * btnHoldX, * btnHoldY; - QPushButton * btnFixX, * btnFixY; + RadioTrimWidget * hTrimWidget; + RadioTrimWidget * vTrimWidget; + QToolButton * btnHoldX, * btnHoldY; + QToolButton * btnFixX, * btnFixY; QLabel * nodeLabelX, * nodeLabelY; QSize extraSize; float ar; // aspect ratio + bool m_stickPressed; +}; + +/* + * Custom GraphicsScene for mouse handling +*/ +class CustomGraphicsScene : public QGraphicsScene +{ + Q_OBJECT + + public: + CustomGraphicsScene(QObject *parent = Q_NULLPTR) : + QGraphicsScene(parent) + {} + + signals: + void mouseEvent(QGraphicsSceneMouseEvent * event); + + protected: + virtual void mousePressEvent(QGraphicsSceneMouseEvent * event); + virtual void mouseReleaseEvent(QGraphicsSceneMouseEvent * event); + virtual void mouseMoveEvent(QGraphicsSceneMouseEvent * event); }; #endif // VIRTUALJOYSTICKWIDGET_H diff --git a/radio/src/targets/simu/opentxsimulator.cpp b/radio/src/targets/simu/opentxsimulator.cpp index b0d1973de..2fd639e4d 100644 --- a/radio/src/targets/simu/opentxsimulator.cpp +++ b/radio/src/targets/simu/opentxsimulator.cpp @@ -134,7 +134,7 @@ void OpenTxSimulator::getTrims(Trims & trims) { uint8_t phase = getFlightMode(); trims.extended = hasExtendedTrims(); - for (uint8_t idx=0; idx<4; idx++) { + for (uint8_t idx=0; idx < CPN_MAX_STICKS + CPN_MAX_AUX_TRIMS; idx++) { trims.values[idx] = getTrimValue(getTrimFlightMode(phase, idx), idx); } From d586b7cd2bb4443f35b095bff96ef11a964d58fe Mon Sep 17 00:00:00 2001 From: 3djc Date: Wed, 22 Mar 2017 21:57:45 +0100 Subject: [PATCH 023/203] Allow neg value for telem comparison fonctions (#4667) * Allow neg value for telem comparison fonctions * Protect avr --- radio/src/gui/128x64/model_logical_switches.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/radio/src/gui/128x64/model_logical_switches.cpp b/radio/src/gui/128x64/model_logical_switches.cpp index ec5cd61ca..a41a89311 100644 --- a/radio/src/gui/128x64/model_logical_switches.cpp +++ b/radio/src/gui/128x64/model_logical_switches.cpp @@ -166,7 +166,11 @@ void menuModelLogicalSwitchOne(event_t event) else if (cs->func == LS_FUNC_ADIFFEGREATER) v2_min = 0; else +#if defined(CPUARM) + v2_min = -v2_max; +#else v2_min = minTelemValue(v1_val - MIXSRC_FIRST_TELEM + 1); +#endif INCDEC_SET_FLAG(EE_MODEL | INCDEC_REP10 | NO_INCDEC_MARKS); if (cs->v2 < v2_min || cs->v2 > v2_max) { cs->v2 = 0; From 3ddd809b2c58da18c5521ff188c821f169d6e818 Mon Sep 17 00:00:00 2001 From: 3djc Date: Thu, 23 Mar 2017 10:06:11 +0100 Subject: [PATCH 024/203] Skip building if nightly item already there --- tools/nightly22/build-nightly.sh | 37 +++++++++++++++++++------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/tools/nightly22/build-nightly.sh b/tools/nightly22/build-nightly.sh index e1d5494e0..f89880b52 100755 --- a/tools/nightly22/build-nightly.sh +++ b/tools/nightly22/build-nightly.sh @@ -27,25 +27,32 @@ docker rmi -f new-${docker} code/tools/nightly22/build-sdcard.sh # Build Linux companion -docker run -dit --name companion -v /home/opentx/${docker}:/opentx ${docker} -docker exec companion sh -c "mkdir -p build && cd build && cmake /opentx/code && cp radio/src/stamp.h /opentx/binaries/stamp-opentx.txt" -docker exec companion rm -rf build -docker exec companion /opentx/code/tools/build-companion.sh /opentx/code /opentx/binaries/ ${suffix} -docker stop companion -docker rm companion -cp -f binaries/*.deb ${output}/companion/linux/companion22_${version}${suffix}_amd64.deb +if [ ! -f ${output}/companion/linux/companion22_${version}${suffix}_amd64.deb]; then + docker run -dit --name companion -v /home/opentx/${docker}:/opentx ${docker} + docker exec companion sh -c "mkdir -p build && cd build && cmake /opentx/code && cp radio/src/stamp.h /opentx/binaries/stamp-opentx.txt" + docker exec companion rm -rf build + docker exec companion /opentx/code/tools/build-companion.sh /opentx/code /opentx/binaries/ ${suffix} + docker stop companion + docker rm companion + cp -f binaries/*.deb ${output}/companion/linux/companion22_${version}${suffix}_amd64.deb +fi # Request companion compilation on Windows -cd ${output}/companion/windows -wget -qO- http://winbox.open-tx.org/companion-builds/compile22.php?branch=$branch\&suffix=${suffix} -wget -O companion-windows-${version}${suffix}.exe http://winbox.open-tx.org/companion-builds/companion-windows-${version}${suffix}.exe -chmod -Rf g+w companion-windows-${version}${suffix}.exe +if [ ! -f ${output}/companion/windows/companion-windows-${version}${suffix}.exe]; then + cd ${output}/companion/windows + wget -qO- http://winbox.open-tx.org/companion-builds/compile22.php?branch=$branch\&suffix=${suffix} + wget -O companion-windows-${version}${suffix}.exe http://winbox.open-tx.org/companion-builds/companion-windows-${version}${suffix}.exe + chmod -Rf g+w companion-windows-${version}${suffix}.exe +fi + # Request companion compilation on Mac OS X -cd ${output}/companion/macosx -wget -qO- http://opentx.blinkt.de:8080/~opentx/build-opentx.py?branch=${branch}\&suffix=${suffix} -wget -O opentx-companion-${version}${suffix}.dmg http://opentx.blinkt.de:8080/~opentx/builds/opentx-companion-${version}${suffix}.dmg -chmod -Rf g+w opentx-companion-${version}${suffix}.dmg +if [ ! -f ${output}/companion/macosx/opentx-companion-${version}${suffix}.dmg]; then + cd ${output}/companion/macosx + wget -qO- http://opentx.blinkt.de:8080/~opentx/build-opentx.py?branch=${branch}\&suffix=${suffix} + wget -O opentx-companion-${version}${suffix}.dmg http://opentx.blinkt.de:8080/~opentx/builds/opentx-companion-${version}${suffix}.dmg + chmod -Rf g+w opentx-companion-${version}${suffix}.dmg +fi # Update stamps cp -f $workdir/binaries/stamp-opentx.txt ${output}/firmware From 99f1965aa6c03c1b59599884923101fbd0cdcb02 Mon Sep 17 00:00:00 2001 From: 3djc Date: Thu, 23 Mar 2017 10:09:27 +0100 Subject: [PATCH 025/203] fix typo --- tools/nightly22/build-nightly.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/nightly22/build-nightly.sh b/tools/nightly22/build-nightly.sh index f89880b52..c3656804f 100755 --- a/tools/nightly22/build-nightly.sh +++ b/tools/nightly22/build-nightly.sh @@ -27,7 +27,7 @@ docker rmi -f new-${docker} code/tools/nightly22/build-sdcard.sh # Build Linux companion -if [ ! -f ${output}/companion/linux/companion22_${version}${suffix}_amd64.deb]; then +if [ ! -f ${output}/companion/linux/companion22_${version}${suffix}_amd64.deb ]; then docker run -dit --name companion -v /home/opentx/${docker}:/opentx ${docker} docker exec companion sh -c "mkdir -p build && cd build && cmake /opentx/code && cp radio/src/stamp.h /opentx/binaries/stamp-opentx.txt" docker exec companion rm -rf build @@ -38,7 +38,7 @@ if [ ! -f ${output}/companion/linux/companion22_${version}${suffix}_amd64.deb]; fi # Request companion compilation on Windows -if [ ! -f ${output}/companion/windows/companion-windows-${version}${suffix}.exe]; then +if [ ! -f ${output}/companion/windows/companion-windows-${version}${suffix}.exe ]; then cd ${output}/companion/windows wget -qO- http://winbox.open-tx.org/companion-builds/compile22.php?branch=$branch\&suffix=${suffix} wget -O companion-windows-${version}${suffix}.exe http://winbox.open-tx.org/companion-builds/companion-windows-${version}${suffix}.exe @@ -47,7 +47,7 @@ fi # Request companion compilation on Mac OS X -if [ ! -f ${output}/companion/macosx/opentx-companion-${version}${suffix}.dmg]; then +if [ ! -f ${output}/companion/macosx/opentx-companion-${version}${suffix}.dmg ]; then cd ${output}/companion/macosx wget -qO- http://opentx.blinkt.de:8080/~opentx/build-opentx.py?branch=${branch}\&suffix=${suffix} wget -O opentx-companion-${version}${suffix}.dmg http://opentx.blinkt.de:8080/~opentx/builds/opentx-companion-${version}${suffix}.dmg From a7050e4b5162a5bc808035c83f56228089b95b50 Mon Sep 17 00:00:00 2001 From: 3djc Date: Thu, 23 Mar 2017 10:20:19 +0100 Subject: [PATCH 026/203] Allow 'pre put' of 'exe' for release too --- tools/release22/build-release.sh | 38 ++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tools/release22/build-release.sh b/tools/release22/build-release.sh index f069690c6..e58a14dc6 100755 --- a/tools/release22/build-release.sh +++ b/tools/release22/build-release.sh @@ -21,26 +21,32 @@ docker rmi -f new-${docker} code/tools/release22/build-sdcard.sh # Build Linux companion -docker run -dit --name companion -v /home/opentx/${docker}:/opentx ${docker} -docker exec companion sh -c "mkdir -p build && cd build && cmake /opentx/code && cp radio/src/stamp.h /opentx/binaries/stamp-opentx.txt" -docker exec companion rm -rf build -docker exec companion /opentx/code/tools/build-companion.sh /opentx/code /opentx/binaries/ -docker stop companion -docker rm companion -cp -f binaries/*.deb ${output}/companion/linux/companion22_${version}_amd64.deb -cp -f binaries/radio/src/lua/lua_fields_*.txt ${output}/firmware +if [ ! -f ${output}/companion/linux/companion22_${version}${suffix}_amd64.deb ]; then + docker run -dit --name companion -v /home/opentx/${docker}:/opentx ${docker} + docker exec companion sh -c "mkdir -p build && cd build && cmake /opentx/code && cp radio/src/stamp.h /opentx/binaries/stamp-opentx.txt" + docker exec companion rm -rf build + docker exec companion /opentx/code/tools/build-companion.sh /opentx/code /opentx/binaries/ + docker stop companion + docker rm companion + cp -f binaries/*.deb ${output}/companion/linux/companion22_${version}_amd64.deb + cp -f binaries/radio/src/lua/lua_fields_*.txt ${output}/firmware +fi # Request companion compilation on Windows -cd ${output}/companion/windows -wget -qO- http://winbox.open-tx.org/companion-builds/compile22.php?branch=$branch -wget -O companion-windows-${version}.exe http://winbox.open-tx.org/companion-builds/companion-windows-${version}.exe -chmod -f g+w companion-windows-${version.exe +if [ ! -f ${output}/companion/windows/companion-windows-${version}${suffix}.exe ]; then + cd ${output}/companion/windows + wget -qO- http://winbox.open-tx.org/companion-builds/compile22.php?branch=$branch + wget -O companion-windows-${version}.exe http://winbox.open-tx.org/companion-builds/companion-windows-${version}.exe + chmod -f g+w companion-windows-${version.exe +fi # Request companion compilation on Mac OS X -cd ${output}/companion/macosx -wget -qO- http://opentx.blinkt.de:8080/~opentx/build-opentx.py?branch=${branch} -wget -O opentx-companion-${version}.dmg http://opentx.blinkt.de:8080/~opentx/builds/opentx-companion-${version}.dmg -chmod -f g+w opentx-companion-${version}.dmg +if [ ! -f ${output}/companion/macosx/opentx-companion-${version}${suffix}.dmg ]; then + cd ${output}/companion/macosx + wget -qO- http://opentx.blinkt.de:8080/~opentx/build-opentx.py?branch=${branch} + wget -O opentx-companion-${version}.dmg http://opentx.blinkt.de:8080/~opentx/builds/opentx-companion-${version}.dmg + chmod -f g+w opentx-companion-${version}.dmg +fi # Update stamps cp -f $workdir/binaries/stamp-opentx.txt ${output}/firmware From 1856334e7e71b098e36475b193c90650cc2fa969 Mon Sep 17 00:00:00 2001 From: 3djc Date: Thu, 23 Mar 2017 10:36:06 +0100 Subject: [PATCH 027/203] Still build firmware stamps even if .deb binary is already there --- tools/nightly22/build-nightly.sh | 10 +++++----- tools/release22/build-release.sh | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/tools/nightly22/build-nightly.sh b/tools/nightly22/build-nightly.sh index c3656804f..20e35685a 100755 --- a/tools/nightly22/build-nightly.sh +++ b/tools/nightly22/build-nightly.sh @@ -27,15 +27,15 @@ docker rmi -f new-${docker} code/tools/nightly22/build-sdcard.sh # Build Linux companion +docker run -dit --name companion -v /home/opentx/${docker}:/opentx ${docker} +docker exec companion sh -c "mkdir -p build && cd build && cmake /opentx/code && cp radio/src/stamp.h /opentx/binaries/stamp-opentx.txt" +docker exec companion rm -rf build if [ ! -f ${output}/companion/linux/companion22_${version}${suffix}_amd64.deb ]; then - docker run -dit --name companion -v /home/opentx/${docker}:/opentx ${docker} - docker exec companion sh -c "mkdir -p build && cd build && cmake /opentx/code && cp radio/src/stamp.h /opentx/binaries/stamp-opentx.txt" - docker exec companion rm -rf build docker exec companion /opentx/code/tools/build-companion.sh /opentx/code /opentx/binaries/ ${suffix} - docker stop companion - docker rm companion cp -f binaries/*.deb ${output}/companion/linux/companion22_${version}${suffix}_amd64.deb fi +docker stop companion +docker rm companion # Request companion compilation on Windows if [ ! -f ${output}/companion/windows/companion-windows-${version}${suffix}.exe ]; then diff --git a/tools/release22/build-release.sh b/tools/release22/build-release.sh index e58a14dc6..efafeb8ea 100755 --- a/tools/release22/build-release.sh +++ b/tools/release22/build-release.sh @@ -21,16 +21,16 @@ docker rmi -f new-${docker} code/tools/release22/build-sdcard.sh # Build Linux companion +docker run -dit --name companion -v /home/opentx/${docker}:/opentx ${docker} +docker exec companion sh -c "mkdir -p build && cd build && cmake /opentx/code && cp radio/src/stamp.h /opentx/binaries/stamp-opentx.txt" +docker exec companion rm -rf build if [ ! -f ${output}/companion/linux/companion22_${version}${suffix}_amd64.deb ]; then - docker run -dit --name companion -v /home/opentx/${docker}:/opentx ${docker} - docker exec companion sh -c "mkdir -p build && cd build && cmake /opentx/code && cp radio/src/stamp.h /opentx/binaries/stamp-opentx.txt" - docker exec companion rm -rf build docker exec companion /opentx/code/tools/build-companion.sh /opentx/code /opentx/binaries/ - docker stop companion - docker rm companion cp -f binaries/*.deb ${output}/companion/linux/companion22_${version}_amd64.deb cp -f binaries/radio/src/lua/lua_fields_*.txt ${output}/firmware fi +docker stop companion +docker rm companion # Request companion compilation on Windows if [ ! -f ${output}/companion/windows/companion-windows-${version}${suffix}.exe ]; then From 7de823f140efeb5bf0c86f1d0c48baaa0f2787c9 Mon Sep 17 00:00:00 2001 From: 3djc Date: Thu, 23 Mar 2017 12:17:09 +0100 Subject: [PATCH 028/203] Only increment nightly index on successful processing --- tools/nightly22/build-nightly.sh | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tools/nightly22/build-nightly.sh b/tools/nightly22/build-nightly.sh index 20e35685a..489d653b0 100755 --- a/tools/nightly22/build-nightly.sh +++ b/tools/nightly22/build-nightly.sh @@ -11,7 +11,6 @@ version=2.2.0 # Incrementnightly index index=`cat index.txt` index=`expr $index + 1` -echo $index > index.txt suffix="N$index" cd ${workdir} @@ -55,12 +54,15 @@ if [ ! -f ${output}/companion/macosx/opentx-companion-${version}${suffix}.dmg ]; fi # Update stamps -cp -f $workdir/binaries/stamp-opentx.txt ${output}/firmware +cp -f ${workdir}/binaries/stamp-opentx.txt ${output}/firmware rm -f ${output}/companion/windows/companion-windows.stamp echo "#define VERSION "'"2.2.0'$suffix'"' >> ${output}/companion/windows/companion-windows.stamp cp -f ${output}/companion/windows/companion-windows.stamp ${output}/companion/linux/companion-windows.stamp cp -f ${output}/companion/windows/companion-windows.stamp ${output}/companion/linux/companion-macosx.stamp # Clean binaries It will be hosting built on demand firmware -rm -rf $workdir/binaries/* -rm -rf $workdir/binaries/.lock +rm -rf ${workdir}/binaries/* +rm -rf ${workdir}/binaries/.lock + +# Released is considered as valid if we get to that point +echo $index > ${workdir}/index.txt From e1dac6e58e3054dffdfd3158b3f58767988e8a91 Mon Sep 17 00:00:00 2001 From: Martin Hotar Date: Thu, 23 Mar 2017 18:22:32 +0100 Subject: [PATCH 029/203] cz translations - radio part (#4675) * cz translations * cz translations --- radio/src/translations/cz.h.txt | 119 +++++++++++++------------------- 1 file changed, 47 insertions(+), 72 deletions(-) diff --git a/radio/src/translations/cz.h.txt b/radio/src/translations/cz.h.txt index 7025dc2d4..6a027ff02 100644 --- a/radio/src/translations/cz.h.txt +++ b/radio/src/translations/cz.h.txt @@ -77,7 +77,7 @@ #define TR_SWTYPES "Žádný\0 ""Bez aretace""2-polohový\0""3-polohový\0" #define LEN_POTTYPES TR("\013","\016") -#define TR_POTTYPES TR("None\0 ""Pot w. det\0""Multipos\0 ""Pot\0 ", "Žádný\0 ""Pot s aretací\0""Vícepol. přep.""Potenciometr\0 ") +#define TR_POTTYPES TR("Žádný\0 ""Pot s aret.""Vícepol př.""Pot\0 ", "Žádný\0 ""Pot s aretací\0""Vícepol. přep.""Potenciometr\0 ") #define LEN_SLIDERTYPES "\006" #define TR_SLIDERTYPES "Žádný\0""Slider" @@ -208,7 +208,7 @@ #define TR_CSWSTAY "Edge\0" #else #define TR_CSWTIMER "Tim\0 " - #define TR_CSWSTICKY "Glue\0" + #define TR_CSWSTICKY "Stky\0" #if defined(CPUARM) #define TR_CSWRANGE "Rnge\0" #define TR_CSWSTAY "Edge\0" @@ -344,42 +344,6 @@ #define LEN_VTELEMCHNS TR("\004", "\005") -#if defined(CPUARM) - #define TR_TELEM_RESERVE TR("[--]", "[---]") - #define TR_TELEM_TIME TR("Time", "Time\0") - #define TR_SWR TR("SWR\0", "SWR\0 ") - #define TR_RX_BATT TR("[NA]", "[NA]\0") - #define TR_A3_A4 TR("A3\0 ""A4\0 ", "A3\0 ""A4\0 ") - #define TR_A3_A4_MIN TR("A3-\0""A4-\0", "A3-\0 ""A4-\0 ") -#else - #define TR_TELEM_RESERVE - #define TR_TELEM_TIME - #define TR_SWR - #define TR_RX_BATT - #define TR_A3_A4 - #define TR_A3_A4_MIN -#endif - -#define TR_ASPD_MAX TR("ASp+", "ASpd+") - -#if LCD_W >= 212 - #define TR_TELEM_RSSI_RX "RSSI\0" -#else - #define TR_TELEM_RSSI_RX TR("Rx\0 ", "Rx\0 ") -#endif - -#if defined(CPUARM) - #define TR_TELEM_TIMERS TR("Tmr1""Tmr2""Tmr3", "Tmr1\0""Tmr2\0""Tmr3\0") -#else - #define TR_TELEM_TIMERS TR("Tmr1""Tmr2", "Tmr1\0""Tmr2\0") -#endif - -#if LCD_W >= 212 - #define TR_VTELEMCHNS "---\0 ""Bat.\0" TR_TELEM_TIME TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_TIMERS TR_SWR "Tx\0 " TR_TELEM_RSSI_RX TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0 ""Rpm\0 ""Fuel\0""T1\0 ""T2\0 ""Spd\0 ""Dist\0""GAlt\0""Cell\0""Cells""Vfas\0""Curr\0""Cnsp\0""Powr\0""AccX\0""AccY\0""AccZ\0""Hdg\0 ""VSpd\0""ASpd\0""dTE\0 " TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0 ""A2-\0 " TR_A3_A4_MIN "Alt-\0""Alt+\0""Rpm+\0""T1+\0 ""T2+\0 ""Spd+\0""Dst+\0" TR_ASPD_MAX "Cell-""Cels-""Vfas-""Curr+""Powr+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Acc\0 ""Time\0" -#else - #define TR_VTELEMCHNS "---\0""Bat." TR_TELEM_TIME TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_TIMERS TR_SWR "Tx\0 " TR_TELEM_RSSI_RX TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0""Rpm\0""Fuel""T1\0 ""T2\0 ""Spd\0""Dist""GAlt""Cell""Cels""Vfas""Curr""Cnsp""Powr""AccX""AccY""AccZ""Hdg\0""VSpd""ASpd""dTE\0" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0""A2-\0" TR_A3_A4_MIN "Alt-""Alt+""Rpm+""T1+\0""T2+\0""Spd+""Dst+" TR_ASPD_MAX "Cel-""Cls-""Vfs-""Cur+""Pwr+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Acc\0""Time" -#endif - #define LENGTH_UNIT_IMP "ft\0" #define SPEED_UNIT_IMP "mph" #define LENGTH_UNIT_METR "m\0 " @@ -464,7 +428,11 @@ #endif #define LEN_VRENCODERS "\003" -#define TR_VRENCODERS "REa""REb" +#if defined(ROTARY_ENCODERS) + #define TR_VRENCODERS "REa""REb" +#else + #define TR_VRENCODERS "RE\0" +#endif #define LEN_VSWITCHES "\003" #define LEN_VSRCRAW "\004" @@ -480,13 +448,18 @@ #if defined(PCBHORUS) #define TR_TRIMS_VSRCRAW "\313Smě""\313Výš""\313Pln""\313Kři""\313T5\0""\313T6\0" +#elif defined(CPUARM) + #define TR_TRIMS_VSRCRAW "\313Smě""\313Výš""\313Pln""\313Kři" #else - #define TR_TRIMS_VSRCRAW TR("TrmS""TrmV""TrmP""TrmK", "\313Smě""\313Výš""\313Pln""\313Kři") + #define TR_TRIMS_VSRCRAW "TrmS""TrmV""TrmP""TrmK" #endif -#if defined(PCBHORUS) +#if defined(PCBX12S) #define TR_POTS_VSRCRAW "\310S1\0""\3106P\0""\310S2\0""\313L1\0""\313L2\0""\311LS\0""\311RS\0""\310JSx""\310JSy" #define TR_SW_VSRCRAW "\312SA\0""\312SB\0""\312SC\0""\312SD\0""\312SE\0""\312SF\0""\312SG\0""\312SH\0" +#elif defined(PCBX10) + #define TR_POTS_VSRCRAW "\310S1\0""\3106P\0""\310S2\0""\311LS\0""\311RS\0""None""None""\310EX1""\310EX2" + #define TR_SW_VSRCRAW "\312SA\0""\312SB\0""\312SC\0""\312SD\0""\312SE\0""\312SF\0""\312SG\0""\312SH\0" #elif defined(PCBFLAMENCO) #define TR_POTS_VSRCRAW "SD\0 ""LS\0 ""RS\0 " #define TR_SW_VSRCRAW "SA\0 ""SB\0 ""SC\0 ""SE\0 ""SF\0 " @@ -627,8 +600,10 @@ #define TR_EXIT "[EXIT]" #endif -#if defined(PCBTARANIS) - #define TR_POPUPS TR_EXIT "\010" "\010" "\010" "\010" TR_ENTER +#if defined(PCBFLAMENCO) + #define TR_POPUPS TR_EXIT "\010" TR_ENTER +#elif defined(PCBTARANIS) + #define TR_POPUPS TR(TR_EXIT "\010" TR_ENTER, TR_EXIT "\010" "\010" "\010" "\010" TR_ENTER) #else #define TR_POPUPS TR_ENTER "\010" TR_EXIT #define OFS_EXIT sizeof(TR_ENTER) @@ -641,7 +616,7 @@ #define TR_MOVINGMODEL "Přesouvám model." #define TR_LOADINGMODEL "Aktivuji model.." #define TR_NAME "Název" -#define TR_MODELNAME "Název modelu" +#define TR_MODELNAME TR("Model", "Název modelu") #define TR_PHASENAME "Název" #define TR_MIXNAME "Název" #define TR_INPUTNAME "Název" @@ -655,11 +630,11 @@ #define TR_ELIMITS TR("Limit +25%", "Kanál +/- 125%") #define TR_ETRIMS TR("širší Trim", "Široký trim") #define TR_TRIMINC TR("Krok Trimu", "Krok trimu") -#define TR_DISPLAY_TRIMS TR3("Zobr.hodnotu trimu", "Zobr.hodnotu trimu", "Číslo v liště trimu") +#define TR_DISPLAY_TRIMS TR3("Číslo v Trm", "Zobr.hodnotu trimu", "Číslo v liště trimu") #define TR_TTRACE TR("StopaPlynu", INDENT "Stopa plynu") #define TR_TTRIM TR3("TrimVolnob.", INDENT "Trim jen volnoběh", "Trim jen pro volnoběh") #define TR_BEEPCTR TR3("Středy \221\222", "Pípat středy \221\222", "Pípat středy") -#define TR_USE_GLOBAL_FUNCS "Použít Glob.Funkce" +#define TR_USE_GLOBAL_FUNCS TR("Glob.Funkce", "Použít Glob.Funkce") #if defined(PCBSKY9X) && defined(REVX) #define TR_OUTPUT_TYPE INDENT "Output" #endif @@ -746,11 +721,11 @@ #define TR_SPLASHSCREEN TR("úvodníLogo", "Zobrazit úvodní logo") #define TR_THROTTLEWARNING TR("* Plyn", INDENT "Kontrola plynu") #define TR_SWITCHWARNING TR("* Spínače", INDENT "Polohy spínačů") -#define TR_POTWARNINGSTATE TR(IF_CPUARM(INDENT) "Poty a Slidery", INDENT "Kontrola Pot. a Slid.") -#define TR_SLIDERWARNING TR(IF_CPUARM(INDENT) "Slidery", INDENT "Pozice sliderů") +#define TR_POTWARNINGSTATE TR("* Pot&Slid.", INDENT "Kontrola Pot&Slid.") +#define TR_SLIDERWARNING TR("* Slidery", INDENT "Pozice sliderů") #define TR_POTWARNING TR("* Potenc.", INDENT "Potenciometry") #define TR_TIMEZONE "Časové pásmo" -#define TR_ADJUST_RTC TR3(INDENT "Upravit RTC", INDENT "Upravit RTC", INDENT "Nastavit čas z GPS") +#define TR_ADJUST_RTC TR3("Čas z GPS", INDENT "Použít čas z GPS", INDENT "Použít čas z GPS") #define TR_GPS "GPS" #define TR_RXCHANNELORD TR("Pořadí kanálů", "Výchozí pořadí kanálů") #define TR_STICKS "Páky" @@ -827,8 +802,8 @@ #endif #define TR_MENUMODELSEL "MODEL" #define TR_MENUSETUP "NASTAVENÍ" -#define TR_MENUFLIGHTMODE "LETOVÝ REŽIM" -#define TR_MENUFLIGHTMODES "LETOVÉ REŽIMY" +#define TR_MENUFLIGHTMODE "LETOVÝ REŽIM" +#define TR_MENUFLIGHTMODES "LETOVÉ REŽIMY" #define TR_MENUHELISETUP "HELI" #define TR_MENULIMITS "SERVA" @@ -841,8 +816,8 @@ #define TR_MENUCURVES "KŘIVKY" #define TR_MENUCURVE "\002K" -#define TR_MENULOGICALSWITCH "LOG. SPÍNAč" -#define TR_MENULOGICALSWITCHES "LOGICKÉ SPÍNAčE" +#define TR_MENULOGICALSWITCH "LOG. SPÍNAČ" +#define TR_MENULOGICALSWITCHES "LOGICKÉ SPÍNAČE" #define TR_MENUCUSTOMFUNC "SPECIÁLNÍ FUNKCE" #define TR_MENUCUSTOMSCRIPTS "SKRIPTY LUA" #define TR_MENUTELEMETRY "TELEMETRIE" @@ -870,11 +845,11 @@ #define TR_MULTI_AUTOBIND TR(INDENT "Autobind",INDENT "Bind on powerup") #define TR_MULTI_DSM_AUTODTECT TR(INDENT "Autodetect", INDENT "Autodetect format") #define TR_MULTI_LOWPOWER TR(INDENT "Low power", INDENT "Low power mode") -#define TR_DISABLE_INTERNAL TR("Disable int. RF", "Disable internal RF") +#define TR_DISABLE_INTERNAL TR("Disable int.", "Disable internal RF") #define TR_MODULE_NO_SERIAL_MODE TR("!serial mode", "Not in serial mode") #define TR_MODULE_NO_INPUT TR("No input", "No serial input") -#define TR_MODULE_NO_TELEMETRY TR3( "No telmetry", "No MULTI_TELEMETRY", "No telemetry (enable MULTI_TELEMETRY)") -#define TR_MODULE_BINDING "Binding" +#define TR_MODULE_NO_TELEMETRY TR3( "No telemetry", "No MULTI_TELEMETRY", "No MULTI_TELEMETRY detected") +#define TR_MODULE_BINDING TR("Bind...","Binding") #define TR_PROTOCOL_INVALID TR("Prot. invalid", "Protocol invalid") #define TR_MODULE_STATUS TR(INDENT "Status", INDENT "Module Status") #define TR_MULTI_SERVOFREQ TR(INDENT "Servo rate", INDENT "Servo update rate") @@ -887,7 +862,7 @@ #define TR_VARIO "Vario" #define TR_PITCH_AT_ZERO INDENT "Tón na nule" #define TR_PITCH_AT_MAX INDENT "Tón na maximu" -#define TR_REPEAT_AT_ZERO INDENT "Opakování na nule" +#define TR_REPEAT_AT_ZERO TR(INDENT "Opak. na nule", INDENT "Opakování na nule") #define TR_POWEROFF "\027Power OFF..." #define TR_SHUTDOWN "Vypínání.." #define TR_SAVEMODEL "Ukládám nastavení modelu" @@ -906,8 +881,8 @@ #define TR_BACKUP_MODEL "Zálohovat na SD" #define TR_DELETE_MODEL "Smaž model" #define TR_RESTORE_MODEL "Obnov model z SD" -#define TR_DELETE_ERROR "Delete error" -#define TR_CAT_NOT_EMPTY "Category is not empty" +#define TR_DELETE_ERROR "Nelze odstranit" +#define TR_CAT_NOT_EMPTY "Kategorie není prázdná" #define TR_SDCARD_ERROR "Chyba SD karty" #define TR_NO_SDCARD "Není SD karta" #define TR_SDCARD_FULL "Plná SD karta" @@ -920,7 +895,7 @@ #define TR_ALARMSWARN "ALARMU" #define TR_SWITCHWARN "POZICE" #define TR_FAILSAFEWARN "FAILSAFE" -#define TR_WRONG_SDCARDVERSION "Doporučená ver.: " +#define TR_WRONG_SDCARDVERSION "Očekávaná ver.: " #define TR_WRONG_PCBREV "Jiná verze PCB/firmware" #define TR_EMERGENCY_MODE "NOUZOVÝ REŽIM" #define TR_PCBREV_ERROR "PCB error" @@ -986,14 +961,14 @@ #define TR_PATH_TOO_LONG "Cesta je moc dlouhá" #define TR_VIEW_TEXT "Zobrazit text" #define TR_FLASH_BOOTLOADER "Flash BootLoaderu" -#define TR_FLASH_EXTERNAL_DEVICE "Flash externího zařízení" -#define TR_FLASH_INTERNAL_MODULE "Flash vnitřního modulu" -#define TR_FIRMWARE_UPDATE_ERROR "Firmware update error" -#define TR_WRITING "\032Zapisuji.." +#define TR_FLASH_EXTERNAL_DEVICE TR("Flash ext. modulu", "Flash externího zařízení") +#define TR_FLASH_INTERNAL_MODULE TR("Flash vnitř. modulu", "Flash vnitřního modulu") +#define TR_FIRMWARE_UPDATE_ERROR TR("Chyba zápisu FW", "Chyba zápisu firmware") +#define TR_WRITING TR3("\14Zapisuji..", "\032Zapisuji..", "Zapisuji..") #define TR_CONFIRM_FORMAT "Provést Formát?" #define TR_INTERNALRF "Vnitřní RF modul" #define TR_EXTERNALRF "Externí RF modul" -#define TR_FAILSAFE "Mód Failsafe" +#define TR_FAILSAFE TR("Failsafe", "Mód Failsafe") #define TR_FAILSAFESET "NASTAVENÍ FAILSAFE" #define TR_HOLD "HOLD" #define TR_NONE "NONE" @@ -1039,8 +1014,8 @@ #define TR_TOPLCDTIMER "Stopky horního LCD" #define TR_UNIT "Jednotky" #define TR_TELEMETRY_NEWSENSOR INDENT "Přidat senzor ručně" -#define TR_CHANNELRANGE INDENT "Rozsah kanálů" -#define TR_ANTENNASELECTION INDENT "Antenna selection" +#define TR_CHANNELRANGE TR(INDENT "Kanály", INDENT "Rozsah kanálů") +#define TR_ANTENNASELECTION INDENT "Volba antény" #define TR_ANTENNACONFIRM1 "Opravdu přepnout?" #define TR_ANTENNACONFIRM2 "Ujisti se že je anténa připojena!" #define TR_LOWALARM INDENT "Nízký Alarm" @@ -1060,15 +1035,15 @@ #define TR_PT "č." #define TR_PTS " b." #define TR_SMOOTH "Hladká" -#define TR_COPY_STICKS_TO_OFS TR("Cpy stick->subtrim","Kopie pák do subtrimu") -#define TR_COPY_TRIMS_TO_OFS TR("Cpy trim->subtrim", "Kopíe trimů do subtrimu") +#define TR_COPY_STICKS_TO_OFS TR("Páky do subtrimu", "Kopie pák do subtrimu") +#define TR_COPY_TRIMS_TO_OFS TR("Trimy do subtrimu", "Kopíe trimů do subtrimu") #define TR_INCDEC "Zvěšit/Zmenšit" #define TR_GLOBALVAR "Glob. proměnná" #define TR_MIXSOURCE "Zdroje mixeru" #define TR_CONSTANT "Konstanta" #define TR_PERSISTENT_MAH TR(INDENT "Ulož mAh", INDENT "Ukládat mAh") #define TR_PREFLIGHT "Předletová kontrola" -#define TR_CHECKLIST INDENT "Zobrazit poznámky" +#define TR_CHECKLIST TR(INDENT "Poznámky", INDENT "Zobrazit poznámky") #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Ofset") #define TR_UART3MODE "Seriový port" #define TR_SCRIPT "Skript" @@ -1183,7 +1158,7 @@ #define TR_ABOUT_ROB_2 "openrcforums webmaster" #define TR_ABOUT_KJELL_1 "Kjell Kernen" -#define TR_ABOUT_KJELL_2 "www.open-tx.org main author" +#define TR_ABOUT_KJELL_2 "autor www.open-tx.org" #define TR_ABOUT_KJELL_3 "autor OpenTX Recorder" #define TR_ABOUT_KJELL_4 "Spoluautor Companion" @@ -1246,7 +1221,7 @@ #define TR_IGNORE_INSTANCE INDENT "Ignoruj chyby ID" #define TR_DISCOVER_SENSORS INDENT "Detekovat nové senzory" #define TR_STOP_DISCOVER_SENSORS INDENT "Zastavit autodetekci" -#define TR_DELETE_ALL_SENSORS INDENT "Odstranit všechny senzory" +#define TR_DELETE_ALL_SENSORS INDENT "Odebrat všechny senzory" #define TR_CONFIRMDELETE "Opravdu odstranit vše?" #define TR_SELECT_WIDGET "Zvolit widget" #define TR_REMOVE_WIDGET "Odstranit widget" From 93f6abd81a7017ce1fb2b091ef2a4153d8034361 Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Thu, 23 Mar 2017 19:48:13 +0100 Subject: [PATCH 030/203] Launchpad changelogs for 2.2.0 RC14 (and compilation fix for trusty) --- companion/src/modelprinter.cpp | 1 + launchpad/trusty/changelog | 6 ++++++ launchpad/xenial/changelog | 6 ++++++ launchpad/yakkety/changelog | 6 ++++++ 4 files changed, 19 insertions(+) diff --git a/companion/src/modelprinter.cpp b/companion/src/modelprinter.cpp index 1071311ce..0eec56eab 100644 --- a/companion/src/modelprinter.cpp +++ b/companion/src/modelprinter.cpp @@ -22,6 +22,7 @@ #include "modelprinter.h" #include #include +#include #include "multiprotocols.h" QString changeColor(const QString & input, const QString & to, const QString & from) diff --git a/launchpad/trusty/changelog b/launchpad/trusty/changelog index ff2470723..4c4d3a86f 100644 --- a/launchpad/trusty/changelog +++ b/launchpad/trusty/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N366.1~trusty) trusty; urgency=low + + * New release 2.2.0~N366 RC14 + + -- projectkk2glider Thu, 23 Mar 2017 19:02:56 +0100 + opentx-companion22 (2.2.0~N365~trusty) trusty; urgency=low * New release 2.2.0~N365 RC13 diff --git a/launchpad/xenial/changelog b/launchpad/xenial/changelog index 7fc34b594..5929c6e3b 100644 --- a/launchpad/xenial/changelog +++ b/launchpad/xenial/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N366~xenial) xenial; urgency=low + + * New release 2.2.0~N366 RC14 + + -- projectkk2glider Thu, 23 Mar 2017 19:02:52 +0100 + opentx-companion22 (2.2.0~N365~xenial) xenial; urgency=low * New release 2.2.0~N365 RC13 diff --git a/launchpad/yakkety/changelog b/launchpad/yakkety/changelog index 29cb75c70..230487cce 100644 --- a/launchpad/yakkety/changelog +++ b/launchpad/yakkety/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N366~yakkety) yakkety; urgency=low + + * New release 2.2.0~N366 RC14 + + -- projectkk2glider Thu, 23 Mar 2017 19:02:47 +0100 + opentx-companion22 (2.2.0~N365~yakkety) yakkety; urgency=low * New release 2.2.0~N365 RC13 From d82244adc0cdb9143a2d5a34a22822178a5ac8ee Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Thu, 23 Mar 2017 15:26:17 -0400 Subject: [PATCH 031/203] [Companion] Allow translating some "missing" strings (fixes lupdate warning in multiprotocols.cpp). --- companion/src/constants.h | 24 +++++++++++++----------- companion/src/flasheepromdialog.h | 5 +---- companion/src/multiprotocols.cpp | 24 +++++++++++++----------- 3 files changed, 27 insertions(+), 26 deletions(-) diff --git a/companion/src/constants.h b/companion/src/constants.h index 55638d5db..aa49091ca 100644 --- a/companion/src/constants.h +++ b/companion/src/constants.h @@ -43,17 +43,19 @@ #define CPN_MAX_KEYS 32 #define CPN_MAX_MOUSE_ANALOGS 2 -#define HEX_FILES_FILTER "HEX files (*.hex);;" -#define BIN_FILES_FILTER "BIN files (*.bin);;" -#define DFU_FILES_FILTER "DFU files (*.dfu);;" -#define EEPE_FILES_FILTER "EEPE files (*.eepe);;" -#define OTX_FILES_FILTER "OpenTX files (*.otx);;" -#define EEPROM_FILES_FILTER "Radio and Models settings files (*.otx *.eepe *.bin *.hex);;" OTX_FILES_FILTER EEPE_FILES_FILTER BIN_FILES_FILTER HEX_FILES_FILTER -#define FLASH_FILES_FILTER "FLASH files (*.bin *.hex *.dfu);;" BIN_FILES_FILTER HEX_FILES_FILTER DFU_FILES_FILTER -#define EXTERNAL_EEPROM_FILES_FILTER "EEPROM files (*.bin *.hex);;" BIN_FILES_FILTER HEX_FILES_FILTER -#define ER9X_EEPROM_FILE_TYPE "ER9X_EEPROM_FILE" -#define EEPE_EEPROM_FILE_HEADER "EEPE EEPROM FILE" -#define EEPE_MODEL_FILE_HEADER "EEPE MODEL FILE" +#define CPN_STR_FILES QT_TRANSLATE_NOOP("CompanionMacros", "files") +#define CPN_STR_RAD_MOD_SETTINGS QT_TRANSLATE_NOOP("CompanionMacros", "Radio and Models settings") +#define HEX_FILES_FILTER "HEX " CPN_STR_FILES " (*.hex);;" +#define BIN_FILES_FILTER "BIN " CPN_STR_FILES " (*.bin);;" +#define DFU_FILES_FILTER "DFU " CPN_STR_FILES " (*.dfu);;" +#define EEPE_FILES_FILTER "EEPE " CPN_STR_FILES " (*.eepe);;" +#define OTX_FILES_FILTER "OpenTX " CPN_STR_FILES " (*.otx);;" +#define EEPROM_FILES_FILTER CPN_STR_RAD_MOD_SETTINGS " " CPN_STR_FILES " (*.otx *.eepe *.bin *.hex);;" OTX_FILES_FILTER EEPE_FILES_FILTER BIN_FILES_FILTER HEX_FILES_FILTER +#define FLASH_FILES_FILTER "FLASH " CPN_STR_FILES " (*.bin *.hex *.dfu);;" BIN_FILES_FILTER HEX_FILES_FILTER DFU_FILES_FILTER +#define EXTERNAL_EEPROM_FILES_FILTER "EEPROM " CPN_STR_FILES " (*.bin *.hex);;" BIN_FILES_FILTER HEX_FILES_FILTER +#define ER9X_EEPROM_FILE_TYPE "ER9X_EEPROM_FILE" +#define EEPE_EEPROM_FILE_HEADER "EEPE EEPROM FILE" +#define EEPE_MODEL_FILE_HEADER "EEPE MODEL FILE" const char * const ARROW_LEFT = "\xE2\x86\x90"; const char * const ARROW_UP = "\xE2\x86\x91"; diff --git a/companion/src/flasheepromdialog.h b/companion/src/flasheepromdialog.h index 0cb2ae1d0..e7973bce6 100644 --- a/companion/src/flasheepromdialog.h +++ b/companion/src/flasheepromdialog.h @@ -21,12 +21,9 @@ #ifndef _FLASHEEPROMDIALOG_H_ #define _FLASHEEPROMDIALOG_H_ +#include #include -#define HEX_FILES_FILTER "HEX files (*.hex);;" -#define BIN_FILES_FILTER "BIN files (*.bin);;" -#define EXTERNAL_EEPROM_FILES_FILTER "EEPROM files (*.bin *.hex);;" BIN_FILES_FILTER HEX_FILES_FILTER - namespace Ui { class FlashEEpromDialog; diff --git a/companion/src/multiprotocols.cpp b/companion/src/multiprotocols.cpp index 1e8394044..502abeed2 100644 --- a/companion/src/multiprotocols.cpp +++ b/companion/src/multiprotocols.cpp @@ -23,10 +23,19 @@ #include "multiprotocols.h" #include "radiodata.h" -#define tr QObject::tr +#define STR_MULTI_SUBTYPE QT_TRANSLATE_NOOP("Multiprotocols", "Subtype") +#define STR_MULTI_VIDFREQ QT_TRANSLATE_NOOP("Multiprotocols", "Video TX frequency") +#define STR_MULTI_RFTUNE QT_TRANSLATE_NOOP("Multiprotocols", "C2500 frequency fine tune") +#define STR_MULTI_TELEMETRY QT_TRANSLATE_NOOP("Multiprotocols", "Telemetry") +#define STR_MULTI_RFPOWER QT_TRANSLATE_NOOP("Multiprotocols", "Radio output power") +#define STR_MULTI_SERVOFREQ QT_TRANSLATE_NOOP("Multiprotocols", "Servo output frequency") +#define STR_MULTI_OPTION QT_TRANSLATE_NOOP("Multiprotocols", "Option value") +#define STR_MULTI_DEFAULT QT_TRANSLATE_NOOP("Multiprotocols", "DEFAULT") -static const QStringList STR_SUBTYPE_CUSTOM ({tr("Subtype 0"), tr("Subtype 1"), tr("Subtype 2"), tr("Subtype 3"), - tr("Subtype 4"), tr("Subtype 5"), tr("Subtype 6"), tr("Subtype 7")}); +static const QStringList STR_SUBTYPE_CUSTOM ({ + STR_MULTI_SUBTYPE " 0", STR_MULTI_SUBTYPE " 1", STR_MULTI_SUBTYPE " 2", STR_MULTI_SUBTYPE " 3", + STR_MULTI_SUBTYPE " 4", STR_MULTI_SUBTYPE " 5", STR_MULTI_SUBTYPE " 6", STR_MULTI_SUBTYPE " 7" + }); static const QStringList STR_SUBTYPE_FLYSKY {"Standard", "V9x9", "V6x6", "V912", "CX20"}; static const QStringList STR_SUBTYPE_FRSKY {"D16", "D8", "D16 8ch", "V8", "D16 EU-LBT", "D16 EU-LBT 8ch"}; static const QStringList STR_SUBTYPE_HISKY {"HiSky", "HK310"}; @@ -47,14 +56,7 @@ static const QStringList STR_SUBTYPE_AFHDS2A {"PWM and IBUS", "PPM and IBUS", "P static const QStringList STR_SUBTYPE_Q2X2 {"Q222", "Q242", "Q282"}; static const QStringList STR_SUBTYPE_WK2x01 {"WK2801", "WK2401", "W6_5_1", "W6_6_1", "W6_HEL", "W6_HEL_I"}; static const QStringList STR_SUBTYPE_Q303 {"Q303", "CX35", "CX10D", "CX10WD"}; -static const QStringList NO_SUBTYPE {tr("DEFAULT")}; - -static const QString STR_MULTI_VIDFREQ = tr("Video TX frequency"); -static const QString STR_MULTI_RFTUNE = tr("C2500 frequency fine tune"); -static const QString STR_MULTI_TELEMETRY = tr("Telemetry"); -static const QString STR_MULTI_RFPOWER = tr("Radio output power"); -static const QString STR_MULTI_SERVOFREQ = tr("Servo output frequency"); -static const QString STR_MULTI_OPTION= tr("Option value"); +static const QStringList NO_SUBTYPE {STR_MULTI_DEFAULT}; // Table is designed to be shared with gui_common_arm.cpp From 64e960adc58ad299174a6686a5625b4ed74f1338 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Fri, 24 Mar 2017 03:39:43 -0400 Subject: [PATCH 032/203] [Simulator] Fix startup error in standalone mode when eeprom file does not exist (create file instead, as usual). --- companion/src/simulation/simulatorwidget.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/companion/src/simulation/simulatorwidget.cpp b/companion/src/simulation/simulatorwidget.cpp index 61e4d7bf9..058c3516a 100644 --- a/companion/src/simulation/simulatorwidget.cpp +++ b/companion/src/simulation/simulatorwidget.cpp @@ -225,6 +225,7 @@ bool SimulatorWidget::setStartupData(const QByteArray & dataSource, bool fromFil else { // the binary file will be read/written directly by the fw interface, save the file name for simulator->start() startupData = dataSource; + ret = 1; } } } From 1f7dd5a5bcbce29cbb99af193304f7cd7f216367 Mon Sep 17 00:00:00 2001 From: Thibault Jouan Date: Sat, 25 Mar 2017 12:03:52 +0000 Subject: [PATCH 033/203] Improve companion CMake programs name condition (#4684) * Refactor condition to avoid repeating the test in `else' and `endif'; * Suffix programs name with `${C9X_NAME_SUFFIX}' under FreeBSD, as for Linux build, else cmake build is failing because a `companion' directory already exist in the build directory. --- companion/src/CMakeLists.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/companion/src/CMakeLists.txt b/companion/src/CMakeLists.txt index b63eb5edf..65cfe06ba 100644 --- a/companion/src/CMakeLists.txt +++ b/companion/src/CMakeLists.txt @@ -1,6 +1,6 @@ set(SIMULATOR_INSTALL_PREFIX "" CACHE STRING "Alternative simulator library search path") -if(${CMAKE_SYSTEM_NAME} MATCHES "Linux") +if(${CMAKE_SYSTEM_NAME} MATCHES "(Linux|FreeBSD)") set(C9X_NAME_SUFFIX ${VERSION_MAJOR}${VERSION_MINOR}) set(COMPANION_NAME "companion${C9X_NAME_SUFFIX}") set(SIMULATOR_NAME "simulator${C9X_NAME_SUFFIX}") @@ -11,10 +11,10 @@ if(${CMAKE_SYSTEM_NAME} MATCHES "Linux") endif() message(STATUS "Simulators library search path: " ${SIMULATOR_LIB_PATH}) set(SIMULATOR_LIB_INSTALL_PATH ${CMAKE_INSTALL_PREFIX}/lib/companion${C9X_NAME_SUFFIX}) -else(${CMAKE_SYSTEM_NAME} MATCHES "Linux") +else() set(COMPANION_NAME "companion") set(SIMULATOR_NAME "simulator") -endif(${CMAKE_SYSTEM_NAME} MATCHES "Linux") +endif() # This the name that the user will see in the generated DMG and what the application # will be called under /Applications. We include the version string to make installing From 98388a7ec8d737b3faf37c9747fc428290546b94 Mon Sep 17 00:00:00 2001 From: 3djc Date: Sat, 25 Mar 2017 13:04:33 +0100 Subject: [PATCH 034/203] Used rouding like arm radios (#4683) --- companion/src/eeprominterface.h | 5 +++++ companion/src/simulation/radiooutputswidget.cpp | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/companion/src/eeprominterface.h b/companion/src/eeprominterface.h index 0589e294a..5b59c62cf 100644 --- a/companion/src/eeprominterface.h +++ b/companion/src/eeprominterface.h @@ -368,6 +368,11 @@ inline int divRoundClosest(const int n, const int d) return ((n < 0) ^ (d < 0)) ? ((n - d/2)/d) : ((n + d/2)/d); } +inline int calcRESXto100(int x) +{ + return divRoundClosest(x*100, 1024); +} + #define CHECK_IN_ARRAY(T, index) ((unsigned int)index < DIM(T) ? T[(unsigned int)index] : "???") extern QList eepromInterfaces; diff --git a/companion/src/simulation/radiooutputswidget.cpp b/companion/src/simulation/radiooutputswidget.cpp index 1721fb358..a7b06e7b9 100644 --- a/companion/src/simulation/radiooutputswidget.cpp +++ b/companion/src/simulation/radiooutputswidget.cpp @@ -313,7 +313,7 @@ void RadioOutputsWidget::setValues() for (ch = m_channelsMap.constBegin(); ch != m_channelsMap.constEnd(); ++ch) { if (ch.key() >= CPN_MAX_CHNOUT) continue; - ch.value().first->setText(QString("%1%").arg((outputs.chans[ch.key()] * 100 + 512) / 1024)); + ch.value().first->setText(QString("%1%").arg(calcRESXto100(outputs.chans[ch.key()]))); ch.value().second->setValue(qMin(1024, qMax(-1024, outputs.chans[ch.key()]))); } } From d5560d68f4a24e1c7465ad07f2dab30c6136a30a Mon Sep 17 00:00:00 2001 From: Martin Hotar Date: Sat, 25 Mar 2017 13:06:25 +0100 Subject: [PATCH 035/203] simuicons (#4677) * simuicons * exported as plainSVG * restart icons * some more of the -active ctates --- companion/src/companion.qrc | 6 +- .../simulator/icons/svg/camera-active.svg | 54 +++++++++- .../src/images/simulator/icons/svg/camera.svg | 58 +++++++++- .../simulator/icons/svg/console-active.svg | 49 +++++++++ .../images/simulator/icons/svg/console.svg | 57 ++++++++-- .../simulator/icons/svg/eraser-active.svg | 43 ++++++-- .../src/images/simulator/icons/svg/eraser.svg | 41 +++++-- .../images/simulator/icons/svg/fixed_x-on.svg | 49 +++++++-- .../images/simulator/icons/svg/fixed_x.svg | 49 +++++++-- .../images/simulator/icons/svg/fixed_y-on.svg | 49 +++++++-- .../images/simulator/icons/svg/fixed_y.svg | 49 +++++++-- .../images/simulator/icons/svg/hold_x-on.svg | 78 ++++++++++++-- .../src/images/simulator/icons/svg/hold_x.svg | 62 +++++++++-- .../images/simulator/icons/svg/hold_y-on.svg | 74 +++++++++++-- .../src/images/simulator/icons/svg/hold_y.svg | 62 +++++++++-- .../simulator/icons/svg/info-active.svg | 53 ++++++--- .../src/images/simulator/icons/svg/info.svg | 47 +++++--- .../icons/svg/joystick_settings-active.svg | 101 +++++++++++++++--- .../simulator/icons/svg/joystick_settings.svg | 99 ++++++++++++++--- .../icons/svg/radio_outputs-active.svg | 72 +++++++++++++ .../simulator/icons/svg/radio_outputs.svg | 101 ++++++++++++++---- .../icons/svg/reload_script-active.svg | 68 +++++++++--- .../simulator/icons/svg/reload_script.svg | 58 ++++++++-- .../simulator/icons/svg/restart-active.svg | 50 ++++++--- .../images/simulator/icons/svg/restart.svg | 44 +++++--- .../simulator/icons/svg/rf_out-active.svg | 61 +++++++++++ .../src/images/simulator/icons/svg/rf_out.svg | 82 ++++++++++++++ .../simulator/icons/svg/telemetry-active.svg | 69 ++++++++++++ .../images/simulator/icons/svg/telemetry.svg | 78 ++++++++++++-- .../simulator/icons/svg/trainer-active.svg | 46 ++++++++ .../images/simulator/icons/svg/trainer.svg | 70 +++++++----- .../simulator/icons/svg/word_wrap-active.svg | 11 -- .../simulator/icons/svg/word_wrap-on.svg | 77 +++++++++++++ .../images/simulator/icons/svg/word_wrap.svg | 77 +++++++++++-- 34 files changed, 1742 insertions(+), 302 deletions(-) create mode 100644 companion/src/images/simulator/icons/svg/console-active.svg create mode 100644 companion/src/images/simulator/icons/svg/radio_outputs-active.svg create mode 100644 companion/src/images/simulator/icons/svg/rf_out-active.svg create mode 100644 companion/src/images/simulator/icons/svg/rf_out.svg create mode 100644 companion/src/images/simulator/icons/svg/telemetry-active.svg create mode 100644 companion/src/images/simulator/icons/svg/trainer-active.svg delete mode 100644 companion/src/images/simulator/icons/svg/word_wrap-active.svg create mode 100644 companion/src/images/simulator/icons/svg/word_wrap-on.svg diff --git a/companion/src/companion.qrc b/companion/src/companion.qrc index cbd77a2d8..1ce2967b6 100644 --- a/companion/src/companion.qrc +++ b/companion/src/companion.qrc @@ -15,6 +15,7 @@ images/simulator/icons/svg/camera.svg images/simulator/icons/svg/camera-active.svg images/simulator/icons/svg/console.svg + images/simulator/icons/svg/console-active.svg images/simulator/icons/svg/eraser.svg images/simulator/icons/svg/eraser-active.svg images/simulator/icons/svg/fixed_x.svg @@ -33,14 +34,17 @@ images/simulator/icons/svg/toggle_lock.svg images/simulator/icons/svg/toggle_lock-on.svg images/simulator/icons/svg/radio_outputs.svg + images/simulator/icons/svg/radio_outputs-active.svg images/simulator/icons/svg/reload_script.svg images/simulator/icons/svg/reload_script-active.svg images/simulator/icons/svg/restart.svg images/simulator/icons/svg/restart-active.svg images/simulator/icons/svg/telemetry.svg + images/simulator/icons/svg/telemetry-active.svg images/simulator/icons/svg/trainer.svg + images/simulator/icons/svg/trainer-active.svg images/simulator/icons/svg/word_wrap.svg - images/simulator/icons/svg/word_wrap-active.svg + images/simulator/icons/svg/word_wrap-on.svg images/simulator/Horus/middle.png images/simulator/Horus/left.png images/simulator/Horus/right.png diff --git a/companion/src/images/simulator/icons/svg/camera-active.svg b/companion/src/images/simulator/icons/svg/camera-active.svg index 11858cd98..53db3bd93 100644 --- a/companion/src/images/simulator/icons/svg/camera-active.svg +++ b/companion/src/images/simulator/icons/svg/camera-active.svg @@ -1 +1,53 @@ - \ No newline at end of file + + + + + + + image/svg+xml + + + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/camera.svg b/companion/src/images/simulator/icons/svg/camera.svg index 24e159004..7a2d298d3 100644 --- a/companion/src/images/simulator/icons/svg/camera.svg +++ b/companion/src/images/simulator/icons/svg/camera.svg @@ -1 +1,57 @@ - \ No newline at end of file + + + + + + + image/svg+xml + + + + + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/console-active.svg b/companion/src/images/simulator/icons/svg/console-active.svg new file mode 100644 index 000000000..a60ccd064 --- /dev/null +++ b/companion/src/images/simulator/icons/svg/console-active.svg @@ -0,0 +1,49 @@ + + + + + + + image/svg+xml + + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/console.svg b/companion/src/images/simulator/icons/svg/console.svg index 9ce925a6e..5f42e9976 100644 --- a/companion/src/images/simulator/icons/svg/console.svg +++ b/companion/src/images/simulator/icons/svg/console.svg @@ -1,10 +1,49 @@ - - -image/svg+xml - - - - - - \ No newline at end of file + + + + + + image/svg+xml + + + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/eraser-active.svg b/companion/src/images/simulator/icons/svg/eraser-active.svg index 8b529097c..59ba7b0aa 100644 --- a/companion/src/images/simulator/icons/svg/eraser-active.svg +++ b/companion/src/images/simulator/icons/svg/eraser-active.svg @@ -1,12 +1,33 @@ - - -image/svg+xml - - - - - - - - \ No newline at end of file + + + + + + image/svg+xml + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/eraser.svg b/companion/src/images/simulator/icons/svg/eraser.svg index f7fe40f63..a056fcb3d 100644 --- a/companion/src/images/simulator/icons/svg/eraser.svg +++ b/companion/src/images/simulator/icons/svg/eraser.svg @@ -1,21 +1,40 @@ - - - - - + + + - + image/svg+xml - + - - - - + + + + diff --git a/companion/src/images/simulator/icons/svg/fixed_x-on.svg b/companion/src/images/simulator/icons/svg/fixed_x-on.svg index 3a9a7022b..4c824b71e 100644 --- a/companion/src/images/simulator/icons/svg/fixed_x-on.svg +++ b/companion/src/images/simulator/icons/svg/fixed_x-on.svg @@ -1,18 +1,47 @@ - - - - + + - + image/svg+xml - + - - - - + + + + + diff --git a/companion/src/images/simulator/icons/svg/fixed_x.svg b/companion/src/images/simulator/icons/svg/fixed_x.svg index 767a9a43a..fb0ce9ba3 100644 --- a/companion/src/images/simulator/icons/svg/fixed_x.svg +++ b/companion/src/images/simulator/icons/svg/fixed_x.svg @@ -1,18 +1,47 @@ - - - - + + - + image/svg+xml - + - - - - + + + + + diff --git a/companion/src/images/simulator/icons/svg/fixed_y-on.svg b/companion/src/images/simulator/icons/svg/fixed_y-on.svg index 319b784ef..6c95694ba 100644 --- a/companion/src/images/simulator/icons/svg/fixed_y-on.svg +++ b/companion/src/images/simulator/icons/svg/fixed_y-on.svg @@ -1,18 +1,47 @@ - - - - + + - + image/svg+xml - + - - - - + + + + + diff --git a/companion/src/images/simulator/icons/svg/fixed_y.svg b/companion/src/images/simulator/icons/svg/fixed_y.svg index e6b15140a..d80dba81b 100644 --- a/companion/src/images/simulator/icons/svg/fixed_y.svg +++ b/companion/src/images/simulator/icons/svg/fixed_y.svg @@ -1,18 +1,47 @@ - - - - + + - + image/svg+xml - + - - - - + + + + + diff --git a/companion/src/images/simulator/icons/svg/hold_x-on.svg b/companion/src/images/simulator/icons/svg/hold_x-on.svg index 81808417a..d9be149a5 100644 --- a/companion/src/images/simulator/icons/svg/hold_x-on.svg +++ b/companion/src/images/simulator/icons/svg/hold_x-on.svg @@ -1,19 +1,75 @@ - - - - + + - + image/svg+xml - + - - - - - + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/hold_x.svg b/companion/src/images/simulator/icons/svg/hold_x.svg index c65cf5514..4c9a292d1 100644 --- a/companion/src/images/simulator/icons/svg/hold_x.svg +++ b/companion/src/images/simulator/icons/svg/hold_x.svg @@ -1,19 +1,59 @@ - - - - + + - + image/svg+xml - + - - - - - + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/hold_y-on.svg b/companion/src/images/simulator/icons/svg/hold_y-on.svg index 4058d326c..5f5bbcce3 100644 --- a/companion/src/images/simulator/icons/svg/hold_y-on.svg +++ b/companion/src/images/simulator/icons/svg/hold_y-on.svg @@ -1,19 +1,71 @@ - - - - + + - + image/svg+xml - + - - - - - + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/hold_y.svg b/companion/src/images/simulator/icons/svg/hold_y.svg index e620307b1..6bbc69eaf 100644 --- a/companion/src/images/simulator/icons/svg/hold_y.svg +++ b/companion/src/images/simulator/icons/svg/hold_y.svg @@ -1,19 +1,59 @@ - - - - + + - + image/svg+xml - + - - - - - + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/info-active.svg b/companion/src/images/simulator/icons/svg/info-active.svg index 142f05adf..248968da3 100644 --- a/companion/src/images/simulator/icons/svg/info-active.svg +++ b/companion/src/images/simulator/icons/svg/info-active.svg @@ -1,15 +1,40 @@ - - -image/svg+xml - - - - - - - - - - - \ No newline at end of file + + + + + + image/svg+xml + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/info.svg b/companion/src/images/simulator/icons/svg/info.svg index 85f9f6e73..9a3c23d3c 100644 --- a/companion/src/images/simulator/icons/svg/info.svg +++ b/companion/src/images/simulator/icons/svg/info.svg @@ -1,23 +1,44 @@ - - - - - + + + - + image/svg+xml - + - - - - - - + + + + diff --git a/companion/src/images/simulator/icons/svg/joystick_settings-active.svg b/companion/src/images/simulator/icons/svg/joystick_settings-active.svg index 504b8d0a8..81f67903b 100644 --- a/companion/src/images/simulator/icons/svg/joystick_settings-active.svg +++ b/companion/src/images/simulator/icons/svg/joystick_settings-active.svg @@ -1,18 +1,85 @@ - - - - - - - - - - - - - - - - - \ No newline at end of file + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/joystick_settings.svg b/companion/src/images/simulator/icons/svg/joystick_settings.svg index 709113b4f..ed504de68 100644 --- a/companion/src/images/simulator/icons/svg/joystick_settings.svg +++ b/companion/src/images/simulator/icons/svg/joystick_settings.svg @@ -1,18 +1,89 @@ - - - - - - - - - - - - - - + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/radio_outputs-active.svg b/companion/src/images/simulator/icons/svg/radio_outputs-active.svg new file mode 100644 index 000000000..696dc6b6d --- /dev/null +++ b/companion/src/images/simulator/icons/svg/radio_outputs-active.svg @@ -0,0 +1,72 @@ + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/radio_outputs.svg b/companion/src/images/simulator/icons/svg/radio_outputs.svg index bba407aea..db467b8d5 100644 --- a/companion/src/images/simulator/icons/svg/radio_outputs.svg +++ b/companion/src/images/simulator/icons/svg/radio_outputs.svg @@ -1,33 +1,90 @@ - - - - - + + + - + image/svg+xml - + - - - - - - - + + + + + + + - - - - - - - - + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/reload_script-active.svg b/companion/src/images/simulator/icons/svg/reload_script-active.svg index cc8576d64..91eae3a1a 100644 --- a/companion/src/images/simulator/icons/svg/reload_script-active.svg +++ b/companion/src/images/simulator/icons/svg/reload_script-active.svg @@ -1,13 +1,57 @@ - - -image/svg+xml - - - - - - - - - \ No newline at end of file + + + + + + image/svg+xml + + + + + + + + + + </> + + + diff --git a/companion/src/images/simulator/icons/svg/reload_script.svg b/companion/src/images/simulator/icons/svg/reload_script.svg index c561fc4b0..f44816e90 100644 --- a/companion/src/images/simulator/icons/svg/reload_script.svg +++ b/companion/src/images/simulator/icons/svg/reload_script.svg @@ -1,21 +1,57 @@ - - - - - + + + - + image/svg+xml - + - - - - + + + + + </> diff --git a/companion/src/images/simulator/icons/svg/restart-active.svg b/companion/src/images/simulator/icons/svg/restart-active.svg index 031008c58..b825a62ae 100644 --- a/companion/src/images/simulator/icons/svg/restart-active.svg +++ b/companion/src/images/simulator/icons/svg/restart-active.svg @@ -1,13 +1,39 @@ - - -image/svg+xml - - - - - - - - - \ No newline at end of file + + + + + + image/svg+xml + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/restart.svg b/companion/src/images/simulator/icons/svg/restart.svg index 95ee5b5ca..268bfd407 100644 --- a/companion/src/images/simulator/icons/svg/restart.svg +++ b/companion/src/images/simulator/icons/svg/restart.svg @@ -1,21 +1,39 @@ - - - - - + + + - + image/svg+xml - + - - - - - - + + + diff --git a/companion/src/images/simulator/icons/svg/rf_out-active.svg b/companion/src/images/simulator/icons/svg/rf_out-active.svg new file mode 100644 index 000000000..0cf07b268 --- /dev/null +++ b/companion/src/images/simulator/icons/svg/rf_out-active.svg @@ -0,0 +1,61 @@ + + + + + + + image/svg+xml + + + + + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/rf_out.svg b/companion/src/images/simulator/icons/svg/rf_out.svg new file mode 100644 index 000000000..81fc7f9d6 --- /dev/null +++ b/companion/src/images/simulator/icons/svg/rf_out.svg @@ -0,0 +1,82 @@ + + + + + + + + + + image/svg+xml + + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/telemetry-active.svg b/companion/src/images/simulator/icons/svg/telemetry-active.svg new file mode 100644 index 000000000..1e803d922 --- /dev/null +++ b/companion/src/images/simulator/icons/svg/telemetry-active.svg @@ -0,0 +1,69 @@ + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/telemetry.svg b/companion/src/images/simulator/icons/svg/telemetry.svg index 6adfbeb07..c271c037e 100644 --- a/companion/src/images/simulator/icons/svg/telemetry.svg +++ b/companion/src/images/simulator/icons/svg/telemetry.svg @@ -1,21 +1,77 @@ - - - - - + + + - + image/svg+xml - + - - - - + + + + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/trainer-active.svg b/companion/src/images/simulator/icons/svg/trainer-active.svg new file mode 100644 index 000000000..4c97159c7 --- /dev/null +++ b/companion/src/images/simulator/icons/svg/trainer-active.svg @@ -0,0 +1,46 @@ + + + + + + + image/svg+xml + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/trainer.svg b/companion/src/images/simulator/icons/svg/trainer.svg index 3bb8e4d70..e0990b293 100644 --- a/companion/src/images/simulator/icons/svg/trainer.svg +++ b/companion/src/images/simulator/icons/svg/trainer.svg @@ -1,35 +1,57 @@ - - - - - + + + - + image/svg+xml - + - - - - - - - - + + + + + + + + - - - - - - - - - diff --git a/companion/src/images/simulator/icons/svg/word_wrap-active.svg b/companion/src/images/simulator/icons/svg/word_wrap-active.svg deleted file mode 100644 index 4a5fffbe2..000000000 --- a/companion/src/images/simulator/icons/svg/word_wrap-active.svg +++ /dev/null @@ -1,11 +0,0 @@ - - - -image/svg+xml - - - - - - - \ No newline at end of file diff --git a/companion/src/images/simulator/icons/svg/word_wrap-on.svg b/companion/src/images/simulator/icons/svg/word_wrap-on.svg new file mode 100644 index 000000000..2010c5714 --- /dev/null +++ b/companion/src/images/simulator/icons/svg/word_wrap-on.svg @@ -0,0 +1,77 @@ + + + + + + + + + + image/svg+xml + + + + + + + + + + + diff --git a/companion/src/images/simulator/icons/svg/word_wrap.svg b/companion/src/images/simulator/icons/svg/word_wrap.svg index a6abd2061..986080934 100644 --- a/companion/src/images/simulator/icons/svg/word_wrap.svg +++ b/companion/src/images/simulator/icons/svg/word_wrap.svg @@ -1,20 +1,77 @@ - - - + + + + - + image/svg+xml - + - - - - - + + + + + From dcdbff74b0fd5a5bd2642ac24d43dbcbacb34c2c Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sat, 25 Mar 2017 08:06:36 -0400 Subject: [PATCH 036/203] [Companion] Translation system improvements. (#4676) * [Companion] I18N: * Introduce new Translations class to centralize all related functionality; * Add ability to search multiple locations for .qm translation binaries (local folders, resources, system paths); * Add ability to reload translations dynamically w/out application restart; * Improve support for loading Qt translations (if available); * [build][i18n] Look for and include pre-built Qt translations with other translation resources; Generate translations.qrc dynamically with rest of build files; Add EN "translation" file (simpler UI string edits and possible abstractions); Rename ZH translation file to be country-specific. * [build] Centralize finding all the Qt bits into root CMakeLists; Make sure QT_QMAKE_EXECUTABLE is defined; Disable dysfunctional simulator installer script generation. * Cosmetics (unused includes). * [Companion] Make language options menu dynamic based on available translations, and always show native language name; Allow changing language of some elements w/out restarting (esp. menus/toolbar buttons); Simplify menus/actions/handlers for themes and icon sizes. * [build] Better way to generate translations.qrc using input file again (previous method was generating new qrc for each reconfig); Make sure common library is linked to other modules which may need it; Remove unused script. --- CMakeLists.txt | 39 +- cmake/FindLupdate.cmake | 17 - companion/src/CMakeLists.txt | 126 +- companion/src/companion.cpp | 16 +- companion/src/generaledit/CMakeLists.txt | 5 +- companion/src/mainwindow.cpp | 297 +- companion/src/mainwindow.h | 85 +- companion/src/modeledit/CMakeLists.txt | 1 + companion/src/simulator.cpp | 18 +- companion/src/storage/CMakeLists.txt | 3 +- companion/src/translations.cpp | 168 + companion/src/translations.h | 55 + companion/src/translations.qrc.in | 17 +- companion/src/translations/companion_en.ts | 12395 ++++++++++++++++ .../{companion_zh.ts => companion_zh_CN.ts} | 0 15 files changed, 12925 insertions(+), 317 deletions(-) delete mode 100644 cmake/FindLupdate.cmake create mode 100644 companion/src/translations.cpp create mode 100644 companion/src/translations.h create mode 100644 companion/src/translations/companion_en.ts rename companion/src/translations/{companion_zh.ts => companion_zh_CN.ts} (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 08f836bbe..274730a00 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -21,6 +21,9 @@ endif() if(POLICY CMP0054) cmake_policy(SET CMP0054 NEW) endif() +if(POLICY CMP0058) + cmake_policy(SET CMP0058 NEW) # for ninja +endif() set(CMAKE_COLOR_MAKEFILE ON) @@ -59,6 +62,7 @@ if(WIN32) list(APPEND CMAKE_PREFIX_PATH "${WIN_EXTRA_LIBS_PATH}" "${WIN_EXTRA_LIBS_PATH}/SDL") # hints for FindSDL endif() +find_package(Qt5Core) find_package(Qt5Widgets) find_package(Qt5Xml) find_package(Qt5LinguistTools) @@ -66,11 +70,37 @@ find_package(Qt5PrintSupport) find_package(Qt5Multimedia) find_package(Qt5Svg) -if(Qt5Widgets_FOUND) - message(STATUS "Qt Version: ${Qt5Widgets_VERSION}") +if(Qt5Core_FOUND) + message(STATUS "Qt Version: ${Qt5Core_VERSION}") + + ### Get locations of Qt binary executables & libs (libs are for distros, not for linking) + # first set up some hints + get_target_property(QtCore_LOCATION Qt5::Core LOCATION) + get_filename_component(qt_core_path ${QtCore_LOCATION} PATH) + if(APPLE) + get_filename_component(qt_core_path "${qt_core_path}/.." ABSOLUTE) + endif() + + set(QT_LIB_DIR ${qt_core_path} CACHE PATH "Path to Qt libraries (.dll|.framework|.so).") + find_path(QT_BIN_DIR NAMES "qmake" "qmake.exe" HINTS "${CMAKE_PREFIX_PATH}/bin" "${qt_core_path}/../bin" "${qt_core_path}" DOC "Path to Qt binaries (qmake, lupdate, etc.).") + find_program(QT_QMAKE_EXECUTABLE qmake HINTS "${QT_BIN_DIR}" DOC "Location of qmake program.") + find_program(QT_LUPDATE_EXECUTABLE lupdate HINTS "${QT_BIN_DIR}" DOC "Location of Qt's 'lupdate' program for updating translation files.") + + # Try to find Qt translations + if(QT_QMAKE_EXECUTABLE) + execute_process( + COMMAND ${QT_QMAKE_EXECUTABLE} -query QT_INSTALL_TRANSLATIONS + OUTPUT_VARIABLE qt_translations_hint + OUTPUT_STRIP_TRAILING_WHITESPACE + ) + endif() + find_path(QT_TRANSLATIONS_DIR NAMES "qt_en.qm" HINTS "${qt_translations_hint}" DOC "Path to prebuilt Qt translations (qt_*.qm).") + + ### Common definitions for the Qt-based apps list(APPEND APP_COMMON_DEFINES -DSIMU) list(APPEND APP_COMMON_DEFINES -DQXT_STATIC) list(APPEND APP_COMMON_DEFINES -DQT_USE_QSTRINGBUILDER) # more efficient QString construction using % operator + if(APP_CUSTOM_DBG_HANDLER) # provide full qDebug log context to our custom handler. This may also affect libsimulator, which is why it is here list(APPEND APP_COMMON_DEFINES -DQT_MESSAGELOGCONTEXT) @@ -84,6 +114,7 @@ if(Qt5Widgets_FOUND) else() list(APPEND APP_COMMON_DEFINES -DAPP_DBG_HANDLER_ENABLE=0) endif() + else() message(WARNING "Qt not found! Companion and Simulator builds disabled.") endif() @@ -97,7 +128,7 @@ if(NOT WIN32) endif() endif() -if(Qt5Widgets_FOUND OR FOX_FOUND) +if(Qt5Core_FOUND OR FOX_FOUND) set(SDL_BUILDING_LIBRARY YES) # this prevents FindSDL from appending SDLmain lib to the results, which we don't want find_package("SDL") if(SDL_FOUND) @@ -136,6 +167,6 @@ endif() add_subdirectory(${RADIO_SRC_DIRECTORY}) -if(Qt5Widgets_FOUND) +if(Qt5Core_FOUND) add_subdirectory(${COMPANION_SRC_DIRECTORY}) endif() diff --git a/cmake/FindLupdate.cmake b/cmake/FindLupdate.cmake deleted file mode 100644 index 0caf0ba30..000000000 --- a/cmake/FindLupdate.cmake +++ /dev/null @@ -1,17 +0,0 @@ -# Locate lupdate binary from QT - -# This module defines -# LUPDATE_EXECUTABLE, where is QT lupdate -# LUPDATE_FOUND, if false, don't try to use lupdate - -FIND_PROGRAM( LUPDATE_EXECUTABLE - NAMES - lupdate lupdate-qt4 -) - -# if the program is found then we have it -IF( LUPDATE_EXECUTABLE ) - SET( LUPDATE_FOUND "YES" ) -ENDIF( LUPDATE_EXECUTABLE ) - -MARK_AS_ADVANCED( LUPDATE_EXECUTABLE ) diff --git a/companion/src/CMakeLists.txt b/companion/src/CMakeLists.txt index 65cfe06ba..16432924a 100644 --- a/companion/src/CMakeLists.txt +++ b/companion/src/CMakeLists.txt @@ -110,20 +110,52 @@ include_directories( ${COMPANION_SRC_DIRECTORY}/storage ) +############# Do macro replacements on input files ############# configure_file(${COMPANION_SRC_DIRECTORY}/version.h.in ${CMAKE_BINARY_DIR}/version.h @ONLY) -configure_file(${COMPANION_SRC_DIRECTORY}/translations.qrc.in ${CMAKE_CURRENT_BINARY_DIR}/translations.qrc @ONLY) configure_file(${COMPANION_SRC_DIRECTORY}/companion.desktop.in ${CMAKE_CURRENT_BINARY_DIR}/companion.desktop @ONLY) configure_file(${COMPANION_SRC_DIRECTORY}/simulator.desktop.in ${CMAKE_CURRENT_BINARY_DIR}/simulator.desktop @ONLY) -############# Supporting libraries ############### +############# Translations ############### -add_subdirectory(shared) -add_subdirectory(modeledit) -add_subdirectory(generaledit) -add_subdirectory(simulation) -add_subdirectory(storage) -add_subdirectory(thirdparty/qcustomplot) -add_subdirectory(thirdparty/qxtcommandoptions) +### Generate .qm files and assemble resource (qrc) file. + +# available Companion translations (src/translations/*.ts) +set(LANGUAGES cs de en es fi fr it pl sv zh_CN) +foreach(language ${LANGUAGES}) + list(APPEND companion_TS translations/companion_${language}.ts) +endforeach(language) +# .ts -> .qm +qt5_add_translation(companion_QM ${companion_TS}) + +# add Qt translations if found +if(QT_TRANSLATIONS_DIR) + # Some languages have all translations in one qt_*.qm file and others break them up into modules, in which case we need qt_base_*.qm + file(GLOB qtbase_QM "${QT_TRANSLATIONS_DIR}/qtbase_*.qm") + file(GLOB qt_QM "${QT_TRANSLATIONS_DIR}/qt_??.qm") # don't want to match "qt_help_*.qm" + list(APPEND qt_QM "${QT_TRANSLATIONS_DIR}/qt_zh_CN.qm" "${QT_TRANSLATIONS_DIR}/qt_zh_TW.qm") # exceptions not matched by the GLOB +else() + message(STATUS "QT_TRANSLATIONS_DIR not found, unable to package pre-built Qt translations with application.") +endif() + +set(TRANSLATIONS_QRC "${CMAKE_CURRENT_BINARY_DIR}/translations.qrc") + +# Dynamically create translations.qrc file (XML) from all collected translation files. +foreach(qm_file ${companion_QM} ${qt_QM} ${qtbase_QM}) + get_filename_component(qm_file_name ${qm_file} NAME) + # Add file with full path and file name (w/out path) as alias to be used in actual code + set(TRANSLATION_FILES_LIST "${TRANSLATION_FILES_LIST} ${qm_file}\n") +endforeach() +configure_file(${COMPANION_SRC_DIRECTORY}/translations.qrc.in ${TRANSLATIONS_QRC} @ONLY) + +### Add optional "translations" target for updating .ts files +if(QT_LUPDATE_EXECUTABLE) + add_custom_target(translations + WORKING_DIRECTORY ${COMPANION_SRC_DIRECTORY} + COMMAND ${QT_LUPDATE_EXECUTABLE} ${CMAKE_SOURCE_DIR} -no-obsolete -ts ${companion_TS} + ) +else() + message(STATUS "Qt lupdate not found, 'translations' target will not be availabe.") +endif() ############# Common lib ############### @@ -134,6 +166,7 @@ set(common_SRCS eeprominterface.cpp helpers.cpp radiodata.cpp + translations.cpp firmwares/er9x/er9xeeprom.cpp firmwares/er9x/er9xinterface.cpp firmwares/ersky9x/ersky9xeeprom.cpp @@ -152,23 +185,29 @@ set(common_MOC_HDRS set(common_RESOURCES companion.qrc - ${CMAKE_CURRENT_BINARY_DIR}/translations.qrc + ${TRANSLATIONS_QRC} ) -set(LANGUAGES pl de fr es it sv cs fi zh) -foreach(language ${LANGUAGES}) - list(APPEND common_TS translations/companion_${language}.ts) -endforeach(language) - qt5_wrap_cpp(common_SRCS ${common_MOC_HDRS}) -qt5_add_translation(common_QM ${common_TS}) qt5_add_resources(common_RCC ${common_RESOURCES}) -add_custom_target(gen_qrc DEPENDS ${common_RCC} ${common_QM}) +#add_custom_target(gen_qrc DEPENDS ${common_RCC} ${companion_QM}) add_library(common ${common_SRCS} ${common_RCC}) qt5_use_modules(common Core Xml Widgets) target_link_libraries(common PRIVATE simulation) -add_dependencies(common gen_qrc) +#add_dependencies(common gen_qrc) + +set(CPN_COMMON_LIB common) + +############# Supporting libraries ############### + +add_subdirectory(shared) +add_subdirectory(modeledit) +add_subdirectory(generaledit) +add_subdirectory(simulation) +add_subdirectory(storage) +add_subdirectory(thirdparty/qcustomplot) +add_subdirectory(thirdparty/qxtcommandoptions) ############# Companion ############### @@ -259,15 +298,15 @@ set(companion_UIS ) if(WIN32) - list(APPEND companion_SRCS icon.rc) + set(icon_RC icon.rc) endif() qt5_wrap_ui(companion_SRCS ${companion_UIS}) qt5_wrap_cpp(companion_SRCS ${companion_MOC_HDRS}) -add_executable(${COMPANION_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${companion_SRCS}) +add_executable(${COMPANION_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${companion_SRCS} ${icon_RC}) qt5_use_modules(${COMPANION_NAME} Core Widgets Network) -target_link_libraries(${COMPANION_NAME} PRIVATE generaledit modeledit simulation common qcustomplot shared storage ${PTHREAD_LIBRARY} ${SDL_LIBRARY} ${WIN_LINK_LIBRARIES}) +target_link_libraries(${COMPANION_NAME} PRIVATE generaledit modeledit simulation ${CPN_COMMON_LIB} qcustomplot shared storage ${PTHREAD_LIBRARY} ${SDL_LIBRARY} ${WIN_LINK_LIBRARIES}) PrintTargetReport("${COMPANION_NAME}") @@ -275,25 +314,8 @@ PrintTargetReport("${COMPANION_NAME}") set(simu_SRCS simulator.cpp ) -if(WIN32) - list(APPEND simu_SRCS icon.rc) -endif() - -add_executable(${SIMULATOR_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${simu_SRCS}) -target_link_libraries(${SIMULATOR_NAME} PRIVATE simulation common storage qxtcommandoptions ${PTHREAD_LIBRARY} ${SDL_LIBRARY} ${WIN_LINK_LIBRARIES}) - -############# Translations #################### - -find_package(Lupdate) -if(LUPDATE_FOUND) - message(STATUS "Qt lupdate: " ${LUPDATE_EXECUTABLE}) - add_custom_target(translations - WORKING_DIRECTORY ${COMPANION_SRC_DIRECTORY} - COMMAND ${LUPDATE_EXECUTABLE} ${CMAKE_SOURCE_DIR} -no-obsolete -ts ${common_TS} - ) -else() - message(STATUS "Qt lupdate not found, 'translations' target will not be availabe.") -endif() +add_executable(${SIMULATOR_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${simu_SRCS} ${icon_RC}) +target_link_libraries(${SIMULATOR_NAME} PRIVATE simulation ${CPN_COMMON_LIB} storage qxtcommandoptions ${PTHREAD_LIBRARY} ${SDL_LIBRARY} ${WIN_LINK_LIBRARIES}) ############# Install #################### @@ -335,8 +357,7 @@ if(${CMAKE_SYSTEM_NAME} MATCHES "Linux") elseif(WIN32) - get_target_property(QtCore_LOCATION Qt5::Core LOCATION) - get_filename_component(QT_DLL_DIR ${QtCore_LOCATION} PATH) + set(QT_DLL_DIR ${QT_LIB_DIR}) set(INSTALL_TEMP_QTDLL_FILES Qt5Core Qt5Gui Qt5Widgets Qt5Xml Qt5Network Qt5PrintSupport Qt5Multimedia Qt5Svg) set(INSTALL_TEMP_ICUDLL_FILES icudt54.dll icuin54.dll icuuc54.dll) if(CMAKE_BUILD_TYPE STREQUAL "Debug") @@ -415,7 +436,7 @@ if(WIN32) set(SYSDIR "$ENV{windir}/system32") configure_file(${CMAKE_CURRENT_SOURCE_DIR}/../targets/windows/${COMPANION_NSI_IN_FILE} ${PROJECT_BINARY_DIR}/companion/companion.nsi @ONLY) - configure_file(${CMAKE_CURRENT_SOURCE_DIR}/../targets/windows/${SIMULATOR_NSI_IN_FILE} ${PROJECT_BINARY_DIR}/companion/simulator.nsi @ONLY) + #configure_file(${CMAKE_CURRENT_SOURCE_DIR}/../targets/windows/${SIMULATOR_NSI_IN_FILE} ${PROJECT_BINARY_DIR}/companion/simulator.nsi @ONLY) find_program(NSIS_EXE makensis.exe PATHS "C:/Program Files/NSIS" @@ -428,16 +449,16 @@ if(WIN32) DEPENDS companion simulator opentx-simulators ${PROJECT_BINARY_DIR}/companion/companion.nsi COMMENT "Companion Windows NSIS Installer") - add_custom_command(OUTPUT ${PROJECT_BINARY_DIR}/companion/simulator-install.exe - COMMAND "${NSIS_EXE}" ARGS ${PROJECT_BINARY_DIR}/companion/simulator.nsi - DEPENDS simulator ${PROJECT_BINARY_DIR}/companion/simulator.nsi - COMMENT "Simulator Windows NSIS Installer") +# add_custom_command(OUTPUT ${PROJECT_BINARY_DIR}/companion/simulator-install.exe +# COMMAND "${NSIS_EXE}" ARGS ${PROJECT_BINARY_DIR}/companion/simulator.nsi +# DEPENDS simulator ${PROJECT_BINARY_DIR}/companion/simulator.nsi +# COMMENT "Simulator Windows NSIS Installer") add_custom_target(installer DEPENDS ${PROJECT_BINARY_DIR}/companion/companion-windows.exe - DEPENDS ${PROJECT_BINARY_DIR}/companion/simulator-windows.exe +# DEPENDS ${PROJECT_BINARY_DIR}/companion/simulator-windows.exe SOURCES ${PROJECT_BINARY_DIR}/companion/companion.nsi - SOURCES ${PROJECT_BINARY_DIR}/companion/simulator.nsi +# SOURCES ${PROJECT_BINARY_DIR}/companion/simulator.nsi ) endif() @@ -507,11 +528,6 @@ IF(APPLE) install(PROGRAMS ${DFU_UTIL_ABSOLUTE_PATH} ${AVRDUDE_ABSOLUTE_PATH} DESTINATION ${companion_res_dir} COMPONENT Runtime) set(bundle_tools_path "\${CMAKE_INSTALL_PREFIX}/${companion_res_dir}/dfu-util;\${CMAKE_INSTALL_PREFIX}/${companion_res_dir}/avrdude") - # These needs to be relative to CMAKE_INSTALL_PREFIX - get_target_property(QT_LIBRARY_DIR Qt5::Core LOCATION) - get_filename_component(QT_LIBRARY_DIR ${QT_LIBRARY_DIR} PATH) - get_filename_component(QT_LIBRARY_DIR "${QT_LIBRARY_DIR}/.." ABSOLUTE) - # Include depencies (adding frameworks, fixing the embbeded libraries) # I get write errors without setting BU_CHMOD_BUNDLE_ITEMS even though it is # technically a hack (that is already is in the Bundle library ...) @@ -519,7 +535,7 @@ IF(APPLE) include(BundleUtilities) file(GLOB bundle_simulator_libs \"\${CMAKE_INSTALL_PREFIX}/${companion_res_dir}/libopentx-*${CMAKE_SHARED_LIBRARY_SUFFIX}\") set(BU_CHMOD_BUNDLE_ITEMS on) - fixup_bundle(\"${APPS}\" \"\${bundle_simulator_libs};${bundle_qt_libs};${bundle_tools_path}\" \"${QT_LIBRARY_DIR}\") + fixup_bundle(\"${APPS}\" \"\${bundle_simulator_libs};${bundle_qt_libs};${bundle_tools_path}\" \"${QT_LIB_DIR}\") file(RENAME \"\${CMAKE_INSTALL_PREFIX}/${COMPANION_NAME}.app\" \"\${CMAKE_INSTALL_PREFIX}/${COMPANION_OSX_APP_BUNDLE_NAME}.app\") " COMPONENT Runtime) endif() diff --git a/companion/src/companion.cpp b/companion/src/companion.cpp index 9bf411a48..d90e5d821 100644 --- a/companion/src/companion.cpp +++ b/companion/src/companion.cpp @@ -19,8 +19,6 @@ */ #include -#include -#include #include #if defined(JOYSTICKS) || defined(SIMU_AUDIO) #include @@ -33,6 +31,7 @@ #include "version.h" #include "appdata.h" #include "storage.h" +#include "translations.h" #ifdef __APPLE__ #include @@ -61,7 +60,6 @@ int main(int argc, char *argv[]) #endif Q_INIT_RESOURCE(companion); - Q_INIT_RESOURCE(translations); if (AppDebugMessageHandler::instance()) AppDebugMessageHandler::instance()->installAppMessageHandler(); @@ -81,17 +79,7 @@ int main(int argc, char *argv[]) app.setStyle(new MyProxyStyle); #endif - QTranslator companionTranslator; - companionTranslator.load(":/companion_" + g.locale()); - QTranslator qtTranslator; -#if (QT_VERSION >= QT_VERSION_CHECK(5, 3, 0)) - QString qtfile = "qtbase_"; -#else - QString qtfile = "qt_"; -#endif - qtTranslator.load(qtfile + g.locale().left(2), QLibraryInfo::location(QLibraryInfo::TranslationsPath)); - app.installTranslator(&companionTranslator); - app.installTranslator(&qtTranslator); + Translations::installTranslators(); // QTextCodec::setCodecForCStrings(QTextCodec::codecForName("UTF-8")); diff --git a/companion/src/generaledit/CMakeLists.txt b/companion/src/generaledit/CMakeLists.txt index 0b959c968..897fa4097 100644 --- a/companion/src/generaledit/CMakeLists.txt +++ b/companion/src/generaledit/CMakeLists.txt @@ -23,9 +23,10 @@ foreach(name ${generaledit_NAMES}) set(generaledit_HDRS ${generaledit_HDRS} ${name}.h) set(generaledit_UIS ${generaledit_UIS} ${name}.ui) endforeach() - + qt5_wrap_ui(generaledit_SRCS ${generaledit_UIS}) qt5_wrap_cpp(generaledit_SRCS ${generaledit_HDRS}) add_library(generaledit ${generaledit_SRCS}) -qt5_use_modules(generaledit Widgets Xml Multimedia) \ No newline at end of file +qt5_use_modules(generaledit Widgets Xml Multimedia) +target_link_libraries(generaledit PRIVATE ${CPN_COMMON_LIB}) diff --git a/companion/src/mainwindow.cpp b/companion/src/mainwindow.cpp index 0d4b5b9cd..5c8e40f7b 100644 --- a/companion/src/mainwindow.cpp +++ b/companion/src/mainwindow.cpp @@ -45,6 +45,8 @@ #include "radiointerface.h" #include "progressdialog.h" #include "storage.h" +#include "translations.h" + #include #include #include @@ -69,7 +71,16 @@ MainWindow::MainWindow(): downloadDialog_forWait(NULL), - checkForUpdatesState(0) + checkForUpdatesState(0), + fileMenu(NULL), + editMenu(NULL), + settingsMenu(NULL), + burnMenu(NULL), + helpMenu(NULL), + fileToolBar(NULL), + editToolBar(NULL), + burnToolBar(NULL), + helpToolBar(NULL) { mdiArea = new QMdiArea(this); mdiArea->setHorizontalScrollBarPolicy(Qt::ScrollBarAsNeeded); @@ -518,10 +529,37 @@ void MainWindow::closeEvent(QCloseEvent *event) } } +void MainWindow::changeEvent(QEvent * e) +{ + QMainWindow::changeEvent(e); + switch (e->type()) { + case QEvent::LanguageChange: + retranslateUi(); + break; + default: + break; + } +} + +void MainWindow::retranslateUi() +{ + createActions(); + createMenus(); + createToolBars(); + QMessageBox::information(this, tr("Companion"), tr("Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete.")); +} + void MainWindow::setLanguage(const QString & langString) { g.locale(langString); - QMessageBox::information(this, tr("Companion"), tr("The selected language will be used the next time you start Companion.")); + Translations::installTranslators(); +} + +void MainWindow::onLanguageChanged(QAction * act) +{ + QString lang = act->property("locale").toString(); + if (!lang.isNull()) + setLanguage(lang); } void MainWindow::setTheme(int index) @@ -530,20 +568,36 @@ void MainWindow::setTheme(int index) QMessageBox::information(this, tr("Companion"), tr("The new theme will be loaded the next time you start Companion.")); } +void MainWindow::onThemeChanged(QAction * act) +{ + bool ok; + int id = act->property("themeId").toInt(&ok); + if (ok && id >= 0 && id < 5) + setTheme(id); +} + void MainWindow::setIconThemeSize(int index) { g.iconSize(index); QMessageBox::information(this, tr("Companion"), tr("The icon size will be used the next time you start Companion.")); } +void MainWindow::onIconSizeChanged(QAction * act) +{ + bool ok; + int id = act->property("sizeId").toInt(&ok); + if (ok && id >= 0 && id < 4) + setIconThemeSize(id); +} + void MainWindow::newFile() { MdiChild * child = createMdiChild(); child->newFile(); - + if (IS_HORUS(getCurrentBoard())) { child->categoryAdd(); - } + } child->show(); } @@ -889,9 +943,6 @@ void MainWindow::updateMenus() compareAct->setEnabled(activeMdiChild()); updateRecentFileActions(); updateProfilesActions(); - updateLanguageActions(); - updateIconSizeActions(); - updateIconThemeActions(); setWindowTitle(tr("OpenTX Companion %1 - Radio: %2 - Profile: %3").arg(VERSION).arg(getCurrentFirmware()->getName()).arg(g.profile[g.id()].name())); } @@ -929,6 +980,7 @@ QAction * MainWindow::addAct(const QString & icon, const QString & sName, const if (slotObj == NULL) slotObj = this; connect(newAction, SIGNAL(triggered()), slotObj, slot); + actionsList.append(newAction); return newAction; } @@ -938,33 +990,46 @@ QAction * MainWindow::addAct(const QString & icon, const QString & sName, const return addAct(icon, sName, lName, QKeySequence::UnknownKey, slot); } -QAction * MainWindow::addAct(QActionGroup *aGroup, const QString & sName, const QString & lName, const char *slot) +QAction * MainWindow::addActToGroup(QActionGroup * aGroup, const QString & sName, const QString & lName, const char * propName, const QVariant & propValue, const QVariant & dfltValue) { - QAction *action = addAct("", sName, lName, QKeySequence::UnknownKey, slot); - action->setCheckable(true); - aGroup->addAction(action); - return action; + QAction * act = aGroup->addAction(sName); + act->setStatusTip(lName); + act->setCheckable(true); + if (propName) { + act->setProperty(propName, propValue); + if (propValue == dfltValue) + act->setChecked(true); + } + return act; } void MainWindow::createActions() { + foreach (QAction * act, actionsList) { + if (act) + act->deleteLater(); + } + actionsList.clear(); + separatorAct = new QAction(this); separatorAct->setSeparator(true); + actionsList.append(separatorAct); for (int i = 0; i < MAX_RECENT; ++i) { recentFileActs[i] = new QAction(this); recentFileActs[i]->setVisible(false); connect(recentFileActs[i], SIGNAL(triggered()), this, SLOT(openRecentFile())); + actionsList.append(recentFileActs[i]); } updateRecentFileActions(); QActionGroup *profilesAlignmentGroup = new QActionGroup(this); for (int i=0; isetVisible(false); profileActs[i]->setCheckable(true); - profilesAlignmentGroup->addAction(profileActs[i]); connect(profileActs[i], SIGNAL(triggered()), this, SLOT(loadProfile())); + actionsList.append(profileActs[i]); } updateProfilesActions(); @@ -977,36 +1042,6 @@ void MainWindow::createActions() copyAct = addAct("copy.png", tr("Copy Model"), tr("Copy current model to the clipboard"), QKeySequence::Copy, SLOT(copy())); pasteAct = addAct("paste.png", tr("Paste Model"), tr("Paste model from clipboard"), QKeySequence::Paste, SLOT(paste())); - QActionGroup *themeAlignGroup = new QActionGroup(this); - classicThemeAct = addAct( themeAlignGroup, tr("Classical"), tr("The classic companion9x icon theme"), SLOT(setClassicTheme())); - yericoThemeAct = addAct( themeAlignGroup, tr("Yerico"), tr("Yellow round honey sweet icon theme"), SLOT(setYericoTheme())); - monoThemeAct = addAct( themeAlignGroup, tr("Monochrome"), tr("A monochrome black icon theme"), SLOT(setMonochromeTheme())); - monoWhiteAct = addAct( themeAlignGroup, tr("MonoWhite"), tr("A monochrome white icon theme"), SLOT(setMonoWhiteTheme())); - monoBlueAct = addAct( themeAlignGroup, tr("MonoBlue"), tr("A monochrome blue icon theme"), SLOT(setMonoBlueTheme())); - - QActionGroup *iconAlignGroup = new QActionGroup(this); - smallIconAct = addAct( iconAlignGroup, tr("Small"), tr("Use small toolbar icons"), SLOT(setSmallIconThemeSize())); - normalIconAct = addAct( iconAlignGroup, tr("Normal"), tr("Use normal size toolbar icons"), SLOT(setNormalIconThemeSize())); - bigIconAct = addAct( iconAlignGroup, tr("Big"), tr("Use big toolbar icons"), SLOT(setBigIconThemeSize())); - hugeIconAct = addAct( iconAlignGroup, tr("Huge"), tr("Use huge toolbar icons"), SLOT(setHugeIconThemeSize())); - - QActionGroup *langAlignGroup = new QActionGroup(this); - sysLangAct = addAct( langAlignGroup, tr("System language"), tr("Use system language in menus"), SLOT(setSysLanguage())); - czechLangAct = addAct( langAlignGroup, tr("Czech"), tr("Use Czech in menus"), SLOT(setCZLanguage())); - germanLangAct = addAct( langAlignGroup, tr("German"), tr("Use German in menus"), SLOT(setDELanguage())); - englishLangAct = addAct( langAlignGroup, tr("English"), tr("Use English in menus"), SLOT(setENLanguage())); - finnishLangAct = addAct( langAlignGroup, tr("Finnish"), tr("Use Finnish in menus"), SLOT(setFILanguage())); - frenchLangAct = addAct( langAlignGroup, tr("French"), tr("Use French in menus"), SLOT(setFRLanguage())); - italianLangAct = addAct( langAlignGroup, tr("Italian"), tr("Use Italian in menus"), SLOT(setITLanguage())); -// hebrewLangAct = addAct( langAlignGroup, tr("Hebrew"), tr("Use Hebrew in menus"), SLOT(setHELanguage())); - polishLangAct = addAct( langAlignGroup, tr("Polish"), tr("Use Polish in menus"), SLOT(setPLLanguage())); -// portugueseLangAct = addAct( langAlignGroup, tr("Portuguese"), tr("Use Portuguese in menus"), SLOT(setPTLanguage())); - spanishLangAct = addAct( langAlignGroup, tr("Spanish"), tr("Use Spanish in menus"), SLOT(setESLanguage())); - swedishLangAct = addAct( langAlignGroup, tr("Swedish"), tr("Use Swedish in menus"), SLOT(setSELanguage())); -// russianLangAct = addAct( langAlignGroup, tr("Russian"), tr("Use Russian in menus"), SLOT(setRULanguage())); -// dutchLangAct = addAct( langAlignGroup, tr("Dutch"), tr("Use Dutch in menus"), SLOT(setNLLanguage())); - chineseLangAct = addAct( langAlignGroup, tr("Chinese"), tr("Use Chinese in menus"), SLOT(setCNLanguage())); - aboutAct = addAct("information.png", tr("About..."), tr("Show the application's About box"), SLOT(about())); printAct = addAct("print.png", tr("Print..."), tr("Print current model"), QKeySequence::Print, SLOT(print())); simulateAct = addAct("simulate.png", tr("Simulate..."), tr("Simulate current model"), QKeySequence(tr("Alt+S")), SLOT(simulate())); @@ -1038,23 +1073,42 @@ void MainWindow::createActions() printAct->setEnabled(false); } +QMenu * MainWindow::createLanguageMenu(QWidget * parent) +{ + QMenu * menu = new QMenu(tr("Set Menu Language"), parent); + QActionGroup * actGroup = new QActionGroup(menu); + QString lName; + + addActToGroup(actGroup, tr("System language"), tr("Use default system language."), "locale", QString(""), g.locale()); + foreach (const QString & lang, Translations::getAvailableTranslations()) { + QLocale locale(lang); + lName = locale.nativeLanguageName(); + addActToGroup(actGroup, lName.left(1).toUpper() % lName.mid(1), tr("Use %1 language (some translations may not be complete).").arg(lName), "locale", lang, g.locale()); + } + if (!actGroup->checkedAction()) + actGroup->actions().first()->setChecked(true); + + connect(actGroup, &QActionGroup::triggered, this, &MainWindow::onLanguageChanged); + menu->addActions(actGroup->actions()); + return menu; +} + void MainWindow::createMenus() { - QMenu *recentFileMenu = new QMenu(tr("Recent Files"), this); - QMenu *languageMenu = new QMenu(tr("Set Menu Language"), this); - QMenu *themeMenu = new QMenu(tr("Set Icon Theme"), this); - QMenu *iconThemeSizeMenu = new QMenu(tr("Set Icon Size"), this); + menuBar()->clear(); + if (fileMenu) { + fileMenu->deleteLater(); + } fileMenu = menuBar()->addMenu(tr("File")); - fileMenu->addAction(newAct); - fileMenu->addAction(openAct); - fileMenu->addAction(saveAct); - fileMenu->addAction(saveAsAct); - fileMenu->addMenu(recentFileMenu); + + QMenu *recentFileMenu = new QMenu(tr("Recent Files"), fileMenu); recentFileMenu->setIcon(CompanionIcon("recentdocument.png")); for (int i=0; iaddAction(recentFileActs[i]); } + + fileMenu->addMenu(recentFileMenu); fileMenu->addSeparator(); fileMenu->addAction(logsAct); fileMenu->addAction(fwPrefsAct); @@ -1066,46 +1120,50 @@ void MainWindow::createMenus() fileMenu->addSeparator(); fileMenu->addAction(exitAct); + if (editMenu) { + editMenu->deleteLater(); + } editMenu = menuBar()->addMenu(tr("Edit")); editMenu->addAction(cutAct); editMenu->addAction(copyAct); editMenu->addAction(pasteAct); + if (settingsMenu) { + settingsMenu->deleteLater(); + } settingsMenu = menuBar()->addMenu(tr("Settings")); - settingsMenu->addMenu(languageMenu); - languageMenu->addAction(sysLangAct); - languageMenu->addAction(englishLangAct); - languageMenu->addAction(czechLangAct); - languageMenu->addAction(germanLangAct); - languageMenu->addAction(finnishLangAct); - languageMenu->addAction(frenchLangAct); - languageMenu->addAction(italianLangAct); -// languageMenu->addAction(hebrewLangAct); - languageMenu->addAction(polishLangAct); -// languageMenu->addAction(portugueseLangAct); - languageMenu->addAction(spanishLangAct); - languageMenu->addAction(swedishLangAct); -// languageMenu->addAction(russianLangAct); -// languageMenu->addAction(dutchLangAct); - languageMenu->addAction(chineseLangAct); + QMenu *themeMenu = new QMenu(tr("Set Icon Theme"), settingsMenu); + QActionGroup * themeGroup = new QActionGroup(themeMenu); + addActToGroup(themeGroup, tr("Classical"), tr("The classic companion9x icon theme"), "themeId", 0, g.theme()); + addActToGroup(themeGroup, tr("Yerico"), tr("Yellow round honey sweet icon theme"), "themeId", 1, g.theme()); + addActToGroup(themeGroup, tr("Monochrome"), tr("A monochrome black icon theme"), "themeId", 3, g.theme()); + addActToGroup(themeGroup, tr("MonoBlue"), tr("A monochrome blue icon theme"), "themeId", 4, g.theme()); + addActToGroup(themeGroup, tr("MonoWhite"), tr("A monochrome white icon theme"), "themeId", 2, g.theme()); + connect(themeGroup, &QActionGroup::triggered, this, &MainWindow::onThemeChanged); + themeMenu->addActions(themeGroup->actions()); + + QMenu *iconThemeSizeMenu = new QMenu(tr("Set Icon Size"), settingsMenu); + QActionGroup * szGroup = new QActionGroup(iconThemeSizeMenu); + addActToGroup(szGroup, tr("Small"), tr("Use small toolbar icons"), "sizeId", 0, g.iconSize()); + addActToGroup(szGroup, tr("Normal"), tr("Use normal size toolbar icons"), "sizeId", 1, g.iconSize()); + addActToGroup(szGroup, tr("Big"), tr("Use big toolbar icons"), "sizeId", 2, g.iconSize()); + addActToGroup(szGroup, tr("Huge"), tr("Use huge toolbar icons"), "sizeId", 3, g.iconSize()); + connect(szGroup, &QActionGroup::triggered, this, &MainWindow::onIconSizeChanged); + iconThemeSizeMenu->addActions(szGroup->actions()); + + settingsMenu->addMenu(createLanguageMenu(settingsMenu)); settingsMenu->addMenu(themeMenu); - themeMenu->addAction(classicThemeAct); - themeMenu->addAction(yericoThemeAct); - themeMenu->addAction(monoThemeAct); - themeMenu->addAction(monoBlueAct); - themeMenu->addAction(monoWhiteAct); settingsMenu->addMenu(iconThemeSizeMenu); - iconThemeSizeMenu->addAction(smallIconAct); - iconThemeSizeMenu->addAction(normalIconAct); - iconThemeSizeMenu->addAction(bigIconAct); - iconThemeSizeMenu->addAction(hugeIconAct); settingsMenu->addSeparator(); settingsMenu->addAction(appPrefsAct); settingsMenu->addMenu(createProfilesMenu()); settingsMenu->addAction(editSplashAct); settingsMenu->addAction(burnConfigAct); + if (burnMenu) { + burnMenu->deleteLater(); + } burnMenu = menuBar()->addMenu(tr("Read/Write")); burnMenu->addAction(writeEepromAct); burnMenu->addAction(readEepromAct); @@ -1121,7 +1179,10 @@ void MainWindow::createMenus() burnMenu->addAction(burnFusesAct); burnMenu->addAction(burnListAct); } - menuBar()->addSeparator(); + + if (helpMenu) { + helpMenu->deleteLater(); + } helpMenu = menuBar()->addMenu(tr("Help")); helpMenu->addSeparator(); helpMenu->addAction(checkForUpdatesAct); @@ -1177,6 +1238,12 @@ void MainWindow::createToolBars() size=QSize(24,24); break; } + + if (fileToolBar) { + removeToolBar(fileToolBar); + fileToolBar->deleteLater(); + } + fileToolBar = addToolBar(tr("File")); fileToolBar->setIconSize(size); fileToolBar->setObjectName("File"); @@ -1215,6 +1282,11 @@ void MainWindow::createToolBars() fileToolBar->addAction(compareAct); fileToolBar->addAction(sdsyncAct); + if (editToolBar) { + removeToolBar(editToolBar); + editToolBar->deleteLater(); + } + editToolBar = addToolBar(tr("Edit")); editToolBar->setIconSize(size); editToolBar->setObjectName("Edit"); @@ -1222,6 +1294,11 @@ void MainWindow::createToolBars() editToolBar->addAction(copyAct); editToolBar->addAction(pasteAct); + if (burnToolBar) { + removeToolBar(burnToolBar); + burnToolBar->deleteLater(); + } + burnToolBar = new QToolBar(tr("Write")); addToolBar( Qt::LeftToolBarArea, burnToolBar ); burnToolBar->setIconSize(size); @@ -1237,6 +1314,11 @@ void MainWindow::createToolBars() burnToolBar->addSeparator(); burnToolBar->addAction(burnConfigAct); + if (helpToolBar) { + removeToolBar(helpToolBar); + helpToolBar->deleteLater(); + } + helpToolBar = addToolBar(tr("Help")); helpToolBar->setIconSize(size); helpToolBar->setObjectName("Help"); @@ -1295,63 +1377,6 @@ void MainWindow::updateRecentFileActions() } } -void MainWindow::updateIconSizeActions() -{ - switch (g.iconSize()) { - case 0: smallIconAct->setChecked(true); break; - case 1: normalIconAct->setChecked(true); break; - case 2: bigIconAct->setChecked(true); break; - case 3: hugeIconAct->setChecked(true); break; - } -} - -void MainWindow::updateLanguageActions() -{ - QString langId = g.locale(); - - if (langId=="") - sysLangAct->setChecked(true); - else if (langId=="cs_CZ") - czechLangAct->setChecked(true); - else if (langId=="de_DE") - germanLangAct->setChecked(true); - else if (langId=="en") - englishLangAct->setChecked(true); - else if (langId=="fi_FI") - finnishLangAct->setChecked(true); - else if (langId=="fr_FR") - frenchLangAct->setChecked(true); - else if (langId=="it_IT") - italianLangAct->setChecked(true); - // else if (langId=="he_IL") - // hebrewLangAct->setChecked(true); - else if (langId=="pl_PL") - polishLangAct->setChecked(true); - // else if (langId=="pt_PT") - // portugueseLangAct->setChecked(true); - else if (langId=="es_ES") - spanishLangAct->setChecked(true); - else if (langId=="sv_SE") - swedishLangAct->setChecked(true); - // else if (langId=="ru_RU") - // russianLangAct->setChecked(true); - // else if (langId=="nl_NL") - // dutchLangAct->setChecked(true); - else if (langId=="zh_CN") - chineseLangAct->setChecked(true); -} - -void MainWindow::updateIconThemeActions() -{ - switch (g.theme()) { - case 0: classicThemeAct->setChecked(true); break; - case 1: yericoThemeAct->setChecked(true); break; - case 2: monoWhiteAct->setChecked(true); break; - case 3: monoThemeAct->setChecked(true); break; - case 4: monoBlueAct->setChecked(true); break; - } -} - void MainWindow::updateProfilesActions() { for (int i=0; i actionsList; + QMenu *fileMenu; QMenu *editMenu; QMenu *settingsMenu; @@ -226,28 +213,6 @@ class MainWindow : public QMainWindow QAction *recentFileActs[MAX_RECENT]; QAction *profileActs[MAX_PROFILES]; QAction *createProfileAct; - QAction *classicThemeAct; - QAction *yericoThemeAct; - QAction *monoThemeAct; - QAction *monoBlueAct; - QAction *monoWhiteAct; - QAction *smallIconAct; - QAction *normalIconAct; - QAction *bigIconAct; - QAction *hugeIconAct; - - QAction *sysLangAct; - QAction *czechLangAct; - QAction *germanLangAct; - QAction *englishLangAct; - QAction *finnishLangAct; - QAction *frenchLangAct; - QAction *italianLangAct; - QAction *polishLangAct; - QAction *spanishLangAct; - QAction *swedishLangAct; - QAction *chineseLangAct; - QAction *openDocURLAct; }; diff --git a/companion/src/modeledit/CMakeLists.txt b/companion/src/modeledit/CMakeLists.txt index 20726bce9..73f9208e3 100644 --- a/companion/src/modeledit/CMakeLists.txt +++ b/companion/src/modeledit/CMakeLists.txt @@ -59,3 +59,4 @@ qt5_wrap_cpp(modeledit_SRCS ${modeledit_HDRS}) add_library(modeledit ${modeledit_SRCS}) qt5_use_modules(modeledit Widgets Xml Multimedia) +target_link_libraries(modeledit PRIVATE ${CPN_COMMON_LIB}) diff --git a/companion/src/simulator.cpp b/companion/src/simulator.cpp index d99a06313..b758bbff1 100644 --- a/companion/src/simulator.cpp +++ b/companion/src/simulator.cpp @@ -19,13 +19,9 @@ */ #include -#include -#include -#include #include #include #include -#include #if defined(JOYSTICKS) || defined(SIMU_AUDIO) #include #undef main @@ -41,6 +37,7 @@ #include "simulatorstartupdialog.h" #include "storage.h" #include "qxtcommandoptions.h" +#include "translations.h" #include "version.h" using namespace Simulator; @@ -83,7 +80,6 @@ int main(int argc, char *argv[]) #endif Q_INIT_RESOURCE(companion); - Q_INIT_RESOURCE(translations); if (AppDebugMessageHandler::instance()) AppDebugMessageHandler::instance()->installAppMessageHandler(); @@ -94,17 +90,7 @@ int main(int argc, char *argv[]) QString resultMsg; - QTranslator companionTranslator; - companionTranslator.load(":/companion_" + g.locale()); - QTranslator qtTranslator; -#if (QT_VERSION >= QT_VERSION_CHECK(5, 3, 0)) - QString qtfile = "qtbase_"; -#else - QString qtfile = "qt_"; -#endif - qtTranslator.load(qtfile + g.locale().left(2), QLibraryInfo::location(QLibraryInfo::TranslationsPath)); - app.installTranslator(&companionTranslator); - app.installTranslator(&qtTranslator); + Translations::installTranslators(); #if defined(JOYSTICKS) || defined(SIMU_AUDIO) uint32_t sdlFlags = 0; diff --git a/companion/src/storage/CMakeLists.txt b/companion/src/storage/CMakeLists.txt index 76f940881..5b1aefb20 100644 --- a/companion/src/storage/CMakeLists.txt +++ b/companion/src/storage/CMakeLists.txt @@ -27,4 +27,5 @@ foreach(name ${storage_NAMES}) endforeach() add_library(storage ${storage_SRCS}) -target_link_libraries(storage Qt5::Core Qt5::Gui Qt5::Xml Qt5::Widgets) \ No newline at end of file +qt5_use_modules(storage Core Xml Widgets) +target_link_libraries(storage PRIVATE ${CPN_COMMON_LIB}) diff --git a/companion/src/translations.cpp b/companion/src/translations.cpp new file mode 100644 index 000000000..2bd75881c --- /dev/null +++ b/companion/src/translations.cpp @@ -0,0 +1,168 @@ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "translations.h" +#include "appdata.h" + +#include +#include +#include +#include + +// List of available Companion translations +// todo: make dynamic eg. from directory listing +// todo: make locale name country-agnostic unless translation is specifically for a country (like zh_CN) +QStringList const Translations::getAvailableTranslations() +{ + static QStringList locales; + + if (!locales.size()) { + locales << "cs_CZ" + << "de_DE" + << "en" + << "es_ES" + << "fi_FI" + << "fr_FR" + //<< "he_IL" + << "it_IT" + //<< "nl_NL" + << "pl_PL" + //<< "pt_PT" + //<< "ru_RU" + << "sv_SE" + << "zh_CN" ; + } + return locales; +} + +QStringList const Translations::getAvailableLanguages() +{ + static QStringList languages; + if (!languages.size()) { + foreach (const QString & loc, getAvailableTranslations()) + languages.append(loc.left(2)); + } + return languages; +} + +QStringList const Translations::getTranslationPaths() +{ + // Look for translation files in the following locations, in order of priority + QStringList paths; + + // Prefer path set in environment variable, makes it possible to test/replace translations w/out rebuilding. + if (qEnvironmentVariableIsSet("OPENTX_APP_TRANSLATIONS_PATH") && QDir(qgetenv("OPENTX_APP_TRANSLATIONS_PATH").constData()).exists()) { + paths << qgetenv("OPENTX_APP_TRANSLATIONS_PATH").constData(); + } + // Try application subfolder first, also eg. to test/replace translations quickly. + paths << APP_TRANSLATIONS_FILE_PATH; + // Then the resource file + paths << APP_TRANSLATIONS_RESOURCE_PATH; + // Finally the system folder (more likely for Qt translations than Companion ones) + paths << QLibraryInfo::location(QLibraryInfo::TranslationsPath); + + return paths; +} + +void Translations::installTranslators() +{ + Q_INIT_RESOURCE(translations); + + static QList appTranslators; + + // Determine the locale + + QLocale locale; // defaults to system locale + if (!g.locale().isEmpty()) { + locale = QLocale(g.locale()); // reverts to "C" locale if invalid + if (locale.language() == QLocale::C) { + // reset + locale = QLocale::system(); + g.locale(""); + } + } + qDebug() << "Locale name:" << locale.name() << "language:" << locale.nativeLanguageName() << "country:" << locale.nativeCountryName(); + + // Remove any existing translators, this lets us re-translate w/out restart. + foreach (QTranslator * t, appTranslators) { + if (t) { + QCoreApplication::removeTranslator(t); + delete t; + } + } + appTranslators.clear(); + + /* Multiple translation files can be installed. + * Translations are searched for in the reverse order from which they were installed (last added is searched first). + * The search stops as soon as a translation containing a matching string is found. + */ + + // Look for translation files in several locations + QStringList tryPaths = getTranslationPaths(); + + // First try to install Qt translations for common GUI elements. + + QStringList qtFiles = QStringList() << "qt"; + // After Qt5.3 some translation files are broken up into modules. We only need "qtbase" for now. +#if (QT_VERSION >= QT_VERSION_CHECK(5, 3, 0)) + qtFiles << "qtbase"; +#endif + + foreach (const QString & qtfile, qtFiles) { + QTranslator * translator = new QTranslator(qApp); + if (tryLoadTranslator(translator, locale, qtfile, tryPaths)) { + appTranslators.append(translator); + } + else { + delete translator; + //qDebug() << "Could not find Qt translations for:" << locale.name() << "In file:" << qtfile << "Using paths:" << tryPaths; + } + } + + // Now try to install our custom translations if we support the current locale/language. + if (!getAvailableTranslations().contains(locale.name()) && !getAvailableLanguages().contains(locale.name().left(2))) + return; + + QTranslator * translator = new QTranslator(qApp); + if (tryLoadTranslator(translator, locale, "companion", tryPaths)) { + appTranslators.append(translator); + } + else { + delete translator; + qWarning() << "Could not find Companion translations for:" << locale.name() << "Using paths:" << tryPaths; + } +} + +bool Translations::tryLoadTranslator(QTranslator * t, const QLocale & locale, const QString & baseFile, const QStringList & paths) +{ + foreach (const QString & path, paths) { + if (t->load(locale, baseFile, "_", path)) { + if (QCoreApplication::installTranslator(t)) { + qDebug() << "Installed translation file" << baseFile << "from" << path << "for" << locale.name(); + return true; + } + else { + qWarning() << "Error installing translation file" << baseFile << "for:" << locale.name() << "from:" << path; + return false; + } + } + } + return false; +} diff --git a/companion/src/translations.h b/companion/src/translations.h new file mode 100644 index 000000000..0099317ed --- /dev/null +++ b/companion/src/translations.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef TRANSLATIONS_H +#define TRANSLATIONS_H + +#include + +// Where to find translation files? +// First any path in environment variable OPENTX_APP_TRANSLATIONS_PATH is used if it exists. + +// Default location for .qm files when NOT compiled into application (this is searched after OPENTX_APP_TRANSLATIONS_PATH). +#ifndef APP_TRANSLATIONS_FILE_PATH + #define APP_TRANSLATIONS_FILE_PATH QCoreApplication::applicationDirPath() % "/translations" +#endif +\ +// Default location for .qm files when compiled into application as a resource (this is searched after APP_TRANSLATIONS_FILE_PATH) . +#ifndef APP_TRANSLATIONS_RESOURCE_PATH + #define APP_TRANSLATIONS_RESOURCE_PATH ":/translations" +#endif + +class QLocale; +class QTranslator; + +class Translations +{ + public: + static QStringList const getTranslationPaths(); + static QStringList const getAvailableTranslations(); + static QStringList const getAvailableLanguages(); + + static void installTranslators(); + + protected: + static bool tryLoadTranslator(QTranslator * t, const QLocale & locale, const QString & baseFile, const QStringList & paths); +}; + +#endif // TRANSLATIONS_H diff --git a/companion/src/translations.qrc.in b/companion/src/translations.qrc.in index 975494eb8..6fc7f6a1f 100644 --- a/companion/src/translations.qrc.in +++ b/companion/src/translations.qrc.in @@ -1,13 +1,6 @@ - - - companion_cs.qm - companion_de.qm - companion_es.qm - companion_fi.qm - companion_fr.qm - companion_it.qm - companion_pl.qm - companion_sv.qm - companion_zh.qm - + + + +@TRANSLATION_FILES_LIST@ + diff --git a/companion/src/translations/companion_en.ts b/companion/src/translations/companion_en.ts new file mode 100644 index 000000000..e23bd7467 --- /dev/null +++ b/companion/src/translations/companion_en.ts @@ -0,0 +1,12395 @@ + + + + + AileronsPage + + + No + No + + + + Yes, controlled by a single channel + + + + + Yes, controlled by two channels + + + + + <br>First Aileron Channel: + + + + + Second Aileron Channel: + + + + + AirbrakesPage + + + No + + + + + Yes, controlled by a single channel + + + + + Yes, controlled by two channels + + + + + <br>First Airbrake Channel: + + + + + Second Airbrake Channel: + + + + + AppPreferencesDialog + + + Edit Settings + + + + + Radio Profile + + + + + Profile Name + + + + + Radio Type + + + + + Menu Language + + + + + Voice Language + + + + + Set voice language. +May be different from firmware language + + + + + Build Options + + + + + Splash Screen + + + + + Other Settings + + + + + SD Structure path + + + + + + The profile specific folder, if set, will override general Backup folder + + + + + Backup folder + + + + + If set it will override the application general setting + + + + + if set, will override general backup enable + + + + + + Enable automatic backup before writing firmware + + + + + General Settings + + + + + Default Stick Mode + + + + + Mode selection: + +Mode 1: + Left stick: Elevator, Rudder + Right stick: Throttle, Aileron + +Mode 2: + Left stick: Throttle, Rudder + Right stick: Elevator, Aileron + +Mode 3: + Left stick: Elevator, Aileron + Right stick: Throttle, Rudder + +Mode 4: + Left stick: Throttle, Aileron + Right stick: Elevator, Rudder + + + + + + + Mode 1 (RUD ELE THR AIL) + + + + + Mode 2 (RUD THR ELE AIL) + + + + + Mode 3 (AIL ELE THR RUD) + + + + + Mode 4 (AIL THR ELE RUD) + + + + + Default Channel Order + + + + + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> + + + + + R E T A + + + + + R E A T + + + + + R T E A + + + + + R T A E + + + + + R A E T + + + + + R A T E + + + + + E R T A + + + + + E R A T + + + + + E T R A + + + + + E T A R + + + + + E A R T + + + + + E A T R + + + + + T R E A + + + + + T R A E + + + + + T E R A + + + + + T E A R + + + + + T A R E + + + + + T A E R + + + + + A R E T + + + + + A R T E + + + + + A E R T + + + + + A E T R + + + + + A T R E + + + + + A T E R + + + + + Append version number to FW file name + + + + + Offer to write FW to Tx after download + + + + + Clear Image + + + + + Select Image + + + + + Remove Profile + + + + + + + + + Select Folder + + + + + Application Settings + + + + + Automatic check for Companion updates + + + + + Show splash screen when Companion starts + + + + + Automatic check for OpenTX firmware updates + + + + + Splash Screen Library + + + + + Files to keep + + + + + Google Earth Executable + + + + + User Splash Screens + + + + + Automatic Backup Folder + + + + + Use model wizard when creating a new model + + + + + Only show user splash images + + + + + Show user and companion splash images + + + + + Select Executable + + + + + Use OpenTX firmware nightly builds + + + + + Use Companion nightly builds + + + + + Simulator Settings + + + + + Calibrate + + + + + Blue + + + + + Green + + + + + Red + + + + + Orange + + + + + Yellow + + + + + Simulator capture folder + + + + + Only capture to clipboard + + + + + Enable + + + + + Joystick + + + + + Simulator BackLight + + + + + Remember simulator switch values + + + + + Simulator Volume Gain + + + + + My Radio + + + + + Select your snapshot folder + + + + + + No joysticks found + + + + + EMPTY: No radio settings stored in profile + + + + + AVAILABLE: Radio settings of unknown age + + + + + AVAILABLE: Radio settings stored %1 + + + + + Select your library folder + + + + + + Select your Models and Settings backup folder + + + + + Select Google Earth executable + + + + + Select the folder replicating your SD structure + + + + + Not possible to remove profile + + + + + The default profile can not be removed. + + + + + Open Image to load + + + + + Images (%1) + + + + + Channels + + + Name + + + + + Subtrim + + + + + Min + + + + + Max + + + + + Direction + + + + + Curve + + + + + PPM Center + + + + + Linear Subtrim + + + + + CH%1 + + + + + --- + + + + + INV + + + + + CompanionMacros + + + files + + + + + Radio and Models settings + + + + + CompareDialog + + + Compare Models + + + + + Drag first model here + + + + + Drag second model here + + + + + Close + + + + + Print + + + + + Print to file + + + + + No name + + + + + Print Document + + + + + Select PDF output file + + + + + ConclusionPage + + + OK, I understand. + + + + + ContributorsDialog + + + OpenTX Contributors + + + + + Main Developers + + + + + Other contributors + + + + + Companies and projects who have donated to OpenTX + + + + + People who have donated to OpenTX + + + + + Honors go to Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) + + + + + OpenTX Blacklist + + + + + monthly + + + + + CopyProcess + + + + + Error + + + + + Write error + + + + + Cannot write %1 (reason: %2) + + + + + Cannot open %1 (reason: %2) + + + + + CurveGroup + + + Diff + + + + + Expo + + + + + Func + + + + + Curve + + + + + Curves + + + Curve name + + + + + Fixed X + + + + + Custom X + + + + + Lines + + + + + Smooth + + + + + + Curve type + + + + + Curve Creator + + + + + Y at X=0 + + + + + Y at X=100 + + + + + Both + + + + + x>0 + + + + + x<0 + + + + + Apply + + + + + Side + + + + + Y at X=-100 + + + + + Coefficient + + + + + Curve %1 + + + + + %1 points + + + + + Linear + + + + + Single Expo + + + + + Symmetrical f(x)=-f(-x) + + + + + Symmetrical f(x)=f(-x) + + + + + Editing curve %1 + + + + + Not enough free points in EEPROM to store the curve. + + + + + Copy + + + + + Paste + + + + + Clear + + + + + Clear all curves + + + + + Are you sure you want to reset curve %1? + + + + + Are you sure you want to reset all curves? + + + + + CustomFunctionsPanel + + + Switch + + + + + Action + + + + + Parameters + + + + + Enable + + + + + SF%1 + + + + + GF%1 + + + + + ON + + + + + Error + + + + + Unable to find sound file %1! + + + + + &Copy + + + + + Ctrl+C + + + + + &Cut + + + + + Ctrl+X + + + + + &Paste + + + + + Ctrl+V + + + + + &Delete + + + + + Delete + + + + + CyclicPage + + + 90 + + + + + 120 + + + + + 120x + + + + + 140 + + + + + DebugOutput + + + Debug Output + + + + + <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> + + + + + Filter: + + + + + <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> +To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> + + + + + Buffer: + + + + + Number of lines to keep in display. + + + + + Filter &Help + + + + + Show information about using the filter. + + + + + Word &Wrap + + + + + Toggle word wrapping on/off. + + + + + &Clear + + + + + Clear the output window of all text. + + + + + Enable &Filter + + + + + Turn the filter on/off. + + + + + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> + + + + + Debug Console Filter Help + + + + + EepromInterface + + + Possible causes for this: + + + + + - Eeprom is from a newer version of OpenTX + + + + + - Eeprom is not from OpenTX + + + + + - Eeprom is not from Th9X + + + + + - Eeprom is not from Gruvin9X + + + + + - Eeprom is not from ErSky9X + + + + + - Eeprom is not from Er9X + + + + + - Eeprom size is invalid + + + + + - Eeprom file system is invalid + + + + + - Eeprom is from a unknown board + + + + + - Eeprom is from the wrong board + + + + + - Eeprom backup not supported + + + + + - Something that couldn't be guessed, sorry + + + + + Warning: + + + + + + - Your radio probably uses a wrong firmware, + eeprom size is 4096 but only the first 2048 are used + + + + + - Your eeprom is from an old version of OpenTX, upgrading! + You should 'save as' to keep the old file as a backup. + + + + + Warnings! + + + + + ElevonsPage + + + <br>First Elevon Channel: + + + + + Second Elevon Channel: + + + + + ExpoDialog + + + Flight modes + + + + + Input name + + + + + + + GV + + + + + Source for the mixer. + + + + + Weight + + + + + Switch + + + + + Switch used to enable the line. +If blank then the input is considered to be "ON" all the time. + + + + + Stick Side + + + + + NEG + + + + + POS + + + + + ALL + + + + + Scale + + + + + Include Trim + + + + + No + + + + + Yes + + + + + Curve + + + + + Curve applied to the source. + + + + + Source + + + + + Line name + + + + + Offset + + + + + The source for the mixer + + + + + Edit %1 + + + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + + + + FblPage + + + Throttle Channel: + + + + + Yaw Channel: + + + + + Pitch Channel: + + + + + Roll Channel: + + + + + FirmwarePreferencesDialog + + + Downloads + + + + + Check for updates + + + + + Voice + + + + + Set voice language. +May be different from firmware language + + + + + Download Voice + + + + + Download FW + + + + + Firmware + + + + + Latest Download + + + + + FlapsPage + + + No + + + + + Yes, controlled by a single channel + + + + + Yes, controlled by two channels + + + + + <br>First Flap Channel: + + + + + Second Flap Channel: + + + + + FlashEEpromDialog + + + + Write Models and Settings to Radio + + + + + Load... + + + + + Current Profile + + + + + Allows Companion to write to older version of the firmware + + + + + Check Firmware compatibility + + + + + <html><head/><body><p>Saves a dated copy of your eeprom to the backup folder you specified in the Companion settings before writing the current model to the radio.</p></body></html> + + + + + Backup before Write + + + + + <html><head/><body><p>Modify calibration parameters using settings from current profile</p></body></html> + + + + + Patch calibration setting from profile + + + + + <html><head/><body><p>Modify HW parameters using settings from current profile</p></body></html> + + + + + Patch HW settings from profile + + + + + Cancel + + + + + Write to TX + + + + + Current profile: %1 + + + + + Choose Radio Backup file + + + + + + + Error + + + + + + + + Warning + + + + + Wrong radio calibration data in profile, Settings not patched + + + + + Wrong radio setting data in profile, Settings not patched + + + + + Cannot write file %1: +%2. + + + + + Error writing file %1: +%2. + + + + + The radio firmware belongs to another product family, check file and preferences! + + + + + The radio firmware is outdated, please upgrade! + + + + + Cannot check Models and Settings compatibility! Continue anyway? + + + + + FlashFirmwareDialog + + + Flash Firmware + + + + + Load... + + + + + Date & Time + + + + + Variant + + + + + Version + + + + + Use profile start screen + + + + + Use firmware start screen + + + + + Use library start screen + + + + + Use another start screen + + + + + Allows Companion to write to older version of the firmware + + + + + Check Hardware compatibility + + + + + Backup and restore Models and Settings + + + + + Cancel + + + + + Write to TX + + + + + Open Firmware File + + + + + + + Warning + + + + + %1 may not be a valid firmware file + + + + + + + + + Error + + + + + The firmware file is not valid. + + + + + There is no start screen image in the firmware file. + + + + + Profile image %1 is invalid. + + + + + Open image file to use as radio start screen + + + + + Images (%1) + + + + + Image could not be loaded from %1 + + + + + The library image could not be loaded + + + + + Splash image not found + + + + + Cannot save customized firmware + + + + + Write Firmware to Radio + + + + + + Firmware check failed + + + + + Could not check firmware from radio + + + + + New firmware is not compatible with the one currently installed! + + + + + Conversion failed + + + + + Cannot convert Models and Settings for use with this firmware, original data will be used + + + + + Restore failed + + + + + Could not restore Models and Settings to Radio. The models and settings data file can be found at: %1 + + + + + Flashing done + + + + + FlashProcess + + + Executable %1 not found + + + + + Writing... + + + + + Reading... + + + + + Verifying... + + + + + unknown + + + + + ie: OpenTX for 9X board or OpenTX for 9XR board + + + + + ie: OpenTX for M128 / 9X board or OpenTX for 9XR board with M128 chip + + + + + ie: OpenTX for Gruvin9X board + + + + + Your radio uses a %1 CPU!!! + +Please check advanced burn options to set the correct cpu type. + + + + + Your radio uses a %1 CPU!!! + +Please select an appropriate firmware type to program it. + + + + + +You are currently using: + %1 + + + + + Your radio does not seem connected to USB or the driver is not installed!!! + +Please use ZADIG to properly install the driver. + + + + + Your radio does not seem connected to USB or the driver is not initialized!!!. + + + + + Flashing done (exit code = %1) + + + + + Flashing done with errors + + + + + FUSES: Low=%1 High=%2 Ext=%3 + + + + + FlightMode + + + Fade In + + + + + Fade Out + + + + + Name + + + + + Switch + + + + + FlightModePanel + + + Rotary Encoder %1 + + + + + GVAR%1 + + + + + Popup enabled + + + + + &Clear + + + + + Clear + + + + + Clear all current Flight Mode properties? + + + + + FlightModesPanel + + + Flight Mode %1 + + + + + (%1) + + + + + (default) + + + + + FlybarSelectionPage + + + Has Flybar + + + + + Flybarless + + + + + Flybar: + + + + + FusesDialog + + + Fuses + + + + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'Sans Serif'; font-size:9pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">Reads the current fuses in the AVR controller.</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg 2'; font-size:8pt;"><br /></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">Proper states for </span><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">AtMega 64 </span><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">:</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">EEPROM erase fuse not set: 0E, 81, FF</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">EEPROM erase fuse set: 0E, 89, FF</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg 2'; font-size:8pt;"><br /></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">Proper states for AtMega 2560 :</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">EEPROM erase fuse not set: D7, 11, FC</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">EEPROM erase fuse set: D7, 19, FC</span></p></body></html> + + + + + Read Fuses + + + + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'Sans Serif'; font-size:9pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt; font-weight:600; text-decoration: underline;">Reset Fuses</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">Fuses in the AVR tell it how to behave. Pressing this button sets the fuses to the default parameters needed in the FW. These parameters are different for stock and 4.1 MB, please verify you selected the appropriate processor type in preferences.</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg 2'; font-size:8pt;"><br /></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">This button also sets the &quot;EEPROM protect&quot; Fuse.</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">This prevents erasing of the EEPROM when the flash memory is written.</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg 2'; font-size:8pt;"><br /></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt; font-weight:600; text-decoration: underline;">WARNING</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">Setting fuses can lead to problems and even a total lockout from your controller. Do this only if you know what you are doing.</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg 2'; font-size:8pt;"><br /></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">When in doubt consult either the project's page or the 9xforum (http://9xforums.com/forum/)</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">If you do get locked out - google lookup for &quot;dealing with Fuse Bricks&quot;.</span></p></body></html> + + + + + Reset Fuses +EEPROM - PROTECT + + + + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'Sans Serif'; font-size:9pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt; font-weight:600; text-decoration: underline;">Reset Fuses</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">Fuses in the AVR tell it how to behave. Pressing this button sets the fuses to the default parameters needed in the </span><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">FW. These parameters are different for stock and 4.1 MB, please verify you selected the appropriate processor type in preferences.</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg 2'; font-size:8pt;"><br /></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">This button also clears the &quot;EEPROM protect&quot; Fuse.</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">This causes erasing of the EEPROM when the flash memory is written.</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg 2'; font-size:8pt;"><br /></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt; font-weight:600; text-decoration: underline;">WARNING</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">Setting fuses can lead to problems and even a total lockout from your controller. Do this only if you know what you are doing.</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg 2'; font-size:8pt;"><br /></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">When in doubt consult either the project's page or the 9xforum (http://9xforums.com/forum/)</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-family:'MS Shell Dlg 2'; font-size:8pt;">If you do get locked out - google lookup for &quot;dealing with Fuse Bricks&quot;.</span></p></body></html> + + + + + Reset Fuses +EEPROM - DELETE + + + + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'Ubuntu'; font-size:11pt; font-weight:400; font-style:normal;"> +<p align="center" style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-weight:600; text-decoration: underline;">WARNING</span></p> +<p align="center" style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-weight:600; text-decoration: underline;"></p> +<p align="center" style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Changing the fuses can mess up your radio.</p> +<p align="center" style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Proceed only if you know what you are doing.</p></body></html> + + + + + + Reset Radio Fuses + + + + + Read Fuses from Radio + + + + + GeneralEdit + + + Radio settings + + + + + Retrieve calib. and hw settings from profile + + + + + Store calib. and hw settings in selected profile + + + + + General settings used throught the transmitter. +These will be relevant for all models in the same EEPROM. + + + + + Setup + + + + + Global Functions + + + + + Trainer + + + + + Hardware + + + + + Calibration + + + + + + + Warning + + + + + Wrong data in profile, radio calibration was not retrieved + + + + + Wrong data in profile, Switch/pot config not retrieved + + + + + Wrong data in profile, hw related parameters were not retrieved + + + + + Do you want to store calibration in %1 profile<br>overwriting existing calibration? + + + + + Calibration and HW parameters saved. + + + + + GeneralSetup + + + Form + + + + + Readonly Unlock + + + + + SC + + + + + SE + + + + + SA + + + + + SF + + + + + SH + + + + + SD + + + + + SB + + + + + SG + + + + + Stick reverse + + + + + Country Code + + + + + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. + + + + + FAI Mode + + + + + Automatically adjust the radio's clock if a GPS is connected to telemetry. + + + + + Adjust RTC + + + + + Speaker Volume + + + + + + Hz + + + + + Vario pitch at max + + + + + Backlight Switch + + + + + Color 1 + + + + + Color 2 + + + + + Sound Mode + + + + + If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. + + + + + sec + + + + + Backlight color + + + + + Speaker Pitch (spkr only) + + + + + Beeper + + + + + Speaker + + + + + BeeperVoice + + + + + SpeakerVoice + + + + + Beep volume + + + + + Wav volume + + + + + Vario volume + + + + + Background volume + + + + + + ms + + + + + Backlight flash on alarm + + + + + Vario pitch at zero + + + + + Vario repeat at zero + + + + + Backlight Auto OFF after + + + + + This is the switch selectrion for turning on the backlight (if installed). + + + + + + + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">LCD Screen Contrast</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">Values can be 20-45</span></p></body></html> + + + + + RotEnc Navigation + + + + + Backlight Brightness + + + + + America + + + + + Japan + + + + + Europe + + + + + Voice Language + + + + + Timeshift from UTC + + + + + Backlight OFF Brightness + + + + + Mode selection: + +Mode 1: + Left stick: Elevator, Rudder + Right stick: Throttle, Aileron + +Mode 2: + Left stick: Throttle, Rudder + Right stick: Elevator, Aileron + +Mode 3: + Left stick: Elevator, Aileron + Right stick: Throttle, Rudder + +Mode 4: + Left stick: Throttle, Aileron + Right stick: Elevator, Rudder + + + + + + + Mode 1 (RUD ELE THR AIL) + + + + + Mode 2 (RUD THR ELE AIL) + + + + + Mode 3 (AIL ELE THR RUD) + + + + + Mode 4 (AIL THR ELE RUD) + + + + + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> + + + + + R E T A + + + + + R E A T + + + + + R T E A + + + + + R T A E + + + + + R A E T + + + + + R A T E + + + + + E R T A + + + + + E R A T + + + + + E T R A + + + + + E T A R + + + + + E A R T + + + + + E A T R + + + + + T R E A + + + + + T R A E + + + + + T E R A + + + + + T E A R + + + + + T A R E + + + + + T A E R + + + + + A R E T + + + + + A R T E + + + + + A E R T + + + + + A E T R + + + + + A T R E + + + + + A T E R + + + + + Stick Mode + + + + + Metric + + + + + Imperial + + + + + Default Channel Order + + + + + GPS Coordinates + + + + + Min + + + + + + v + + + + + Max + + + + + Low Memory Warning + + + + + Inactivity Timer + + + + + Show Splash Screen on Startup + + + + + Contrast + + + + + Battery Meter Range + + + + + Haptic Strength + + + + + LCD Display Type + + + + + "No Sound" Warning + + + + + Battery Warning + + + + + Haptic Length + + + + + MAVLink Baud Rate + + + + + + Quiet + + + + + Only Alarms + + + + + + No Keys + + + + + + All + + + + + Battery warning voltage. +This is the threashhold where the battery warning sounds. + +Acceptable values are 5v..10v + + + + + Standard + + + + + Optrex + + + + + If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. + + + + + min + + + + + + Show splash screen on startup + + + + + --- + + + + + 2s + + + + + 3s + + + + + 4s + + + + + 6s + + + + + 8s + + + + + 10s + + + + + 15s + + + + + 4800 Baud + + + + + 9600 Baud + + + + + 14400 Baud + + + + + 19200 Baud + + + + + 38400 Baud + + + + + 57600 Baud + + + + + 76800 Baud + + + + + 115200 Baud + + + + + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" text-decoration: underline;">Warnings</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">These will define startup warnings.</p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Throttle warning - will alert if the throttle is not at idle during startup</p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Switch warning - will alert if switches are not in their defaul position</p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Memory warning - will alert if there's not a lot of memory left</p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Silent mode warning - will alert you if the beeper is set to quiet (0)</p></body></html> + + + + + + X-Short + + + + + + Short + + + + + + Normal + + + + + + Long + + + + + + X-Long + + + + + hh° (N/S) mm' ss''.dd + + + + + NMEA + + + + + Play Delay (switch mid position) + + + + + Measurement Units + + + + + Haptic Mode + + + + + Beeper Length + + + + + Beeper Mode + + + + + Beeper volume + +0 - Quiet. No beeps at all. +1 - No Keys. Normal beeps but menu keys do not beep. +2 - Normal. +3 - Loud. +4 - Extra loud. + + + + + Alarms Only + + + + + GeneralSetupPanel + + + If you enable FAI, you loose the vario, the play functions, the telemetry screen. +This function cannot be disabled by the radio. +Are you sure ? + + + + + GyroPage + + + No + + + + + Yes, controled by a switch + + + + + Yes, controlled by a pot + + + + + Hardware + + + Form + + + + + SQ + + + + + SR + + + + + LS2 + + + + + SP + + + + + SO + + + + + S4 + + + + + RS + + + + + SB + + + + + PPM 2 + + + + + + + + + + + + + + Beeper volume + +0 - Quiet. No beeps at all. +1 - No Keys. Normal beeps but menu keys do not beep. +2 - Normal. +3 - Loud. +4 - Extra loud. + + + + + OFF + + + + + S-Port Mirror + + + + + Telemetry + + + + + SBUS Trainer + + + + + Debug + + + + + Rud + + + + + PPM 3 + + + + + S1 + + + + + S2 + + + + + S3 + + + + + PPM 1 + + + + + Serial Port + + + + + v + + + + + PPM Multiplier + + + + + Current Offset + + + + + PPM 4 + + + + + SA + + + + + Ele + + + + + Ail + + + + + Thr + + + + + SC + + + + + LS + + + + + SD + + + + + Battery Offset + + + + + SE + + + + + SF + + + + + SG + + + + + SH + + + + + SI + + + + + SJ + + + + + SK + + + + + SL + + + + + SM + + + + + SN + + + + + RS2 + + + + + Bluetooth + + + + + ADC Filter + + + + + HardwarePanel + + + + + None + + + + + 2 Positions Toggle + + + + + 2 Positions + + + + + 3 Positions + + + + + Pot with detent + + + + + Multipos switch + + + + + Pot without detent + + + + + Slider with detent + + + + + Heli + + + Off + + + + + 120 + + + + + 120X + + + + + 140 + + + + + 90 + + + + + Invert Elevator + + + + + Invert Aileron + + + + + Invert Collective + + + + + Long. cyc + + + + + Invert + + + + + Swash Ring + + + + + Swash Type + + + + + Lateral cyc + + + + + Collective + + + + + HeliPage + + + Throttle Channel: + + + + + Yaw Channel: + + + + + Pitch Channel: + + + + + Roll Channel: + + + + + InputsPanel + + + + Move Up + + + + + + Ctrl+Up + + + + + + Move Down + + + + + + Ctrl+Down + + + + + Clear All Inputs + + + + + Not enough available inputs! + + + + + Delete Selected Inputs? + + + + + &Add + + + + + Ctrl+A + + + + + &Edit + + + + + Enter + + + + + &Delete + + + + + Delete + + + + + &Copy + + + + + Ctrl+C + + + + + &Cut + + + + + Ctrl+X + + + + + &Paste + + + + + Ctrl+V + + + + + Du&plicate + + + + + Ctrl+U + + + + + Clear Inputs? + + + + + Really clear all the inputs? + + + + + LogicalSwitchesPanel + + + Function + + + + + V1 + + + + + V2 + + + + + AND Switch + + + + + Duration + + + + + Delay + + + + + L%1 + + + + + + (instant) + + + + + (infinite) + + + + + &Copy + + + + + Ctrl+C + + + + + &Cut + + + + + Ctrl+X + + + + + &Paste + + + + + Ctrl+V + + + + + &Delete + + + + + Delete + + + + + LogsDialog + + + Companion Log Viewer + + + + + Fly sessions + + + + + Zoom + + + + + X + + + + + Y + + + + + Reset + + + + + Filename + + + + + Open LogFile + + + + + Telemetry logs + + + + + Time (hh:mm:ss) + + + + + Plot Title Change + + + + + New plot title: + + + + + Axis Label Change + + + + + New axis label: + + + + + Graph Name Change + + + + + New graph name: + + + + + Error: no GPS data not found + + + + + The column containing GPS coordinates must be named "GPS". + +The columns for altitude "GAlt" and for speed "GSpd" are optional + + + + + Error + + + + + Cannot write file %1: +%2. + + + + + Cursor A: %1 m + + + + + Cursor B: %1 m + + + + + Time delta: %1 + + + + + Climb rate: %1 m/s + + + + + Select your log file + + + + + Available fields + + + + + The selected logfile contains %1 invalid lines out of %2 total lines + + + + + total duration + + + + + duration + + + + + (L1) + + + + + (R1) + + + + + (L2) + + + + + (R2) + + + + + MainWindow + + + + File loaded + + + + + Display previous warning again at startup ? + + + + + Checking for updates + + + + + Unable to check for updates. + + + + + A new version of Companion is available (version %1)<br>Would you like to download it? + + + + + + Save As + + + + + Executable (*.exe) + + + + + New release available + + + + + A new release of Companion is available, please check the OpenTX website! + + + + + + No updates available at this time. + + + + + Would you like to launch the installer? + + + + + + Error + + + + + Error opening file %1: +%2. + + + + + Not enough flash available on this board for all the selected options + + + + + Compilation server temporary failure, try later + + + + + Compilation server too busy, try later + + + + + Compilation error + + + + + Invalid firmware + + + + + Invalid board + + + + + Invalid language + + + + + Unknown server failure, try later + + + + + Do you want to write the firmware to the radio now ? + + + + + Firmware %1 does not seem to have ever been downloaded. +Release %2 is available. +Do you want to download it now? + +We recommend you view the release notes using the button below to learn about any changes that may be important to you. + + + + + + Yes + + + + + + No + + + + + + Release Notes + + + + + + Do you want to download release %1 now ? + + + + + A new version of %1 firmware is available: + - current is %2 + - newer is %3 + +Do you want to download it now? + +We recommend you view the release notes using the button below to learn about any changes that may be important to you. + + + + + Ignore this release %1? + + + + + + + Companion + + + + + The selected language will be used the next time you start Companion. + + + + + The new theme will be loaded the next time you start Companion. + + + + + The icon size will be used the next time you start Companion. + + + + + + Open Models and Settings file + + + + + + File saved + + + + + + Synchronize SD + + + + + Firmware updates + + + + + Current firmware does not provide release notes informations. + + + + + + Read Firmware from Radio + + + + + + Read Models and Settings from Radio + + + + + Models and Settings read + + + + + + This function is not yet implemented + + + + + Save Radio Backup to File + + + + + Read Radio Firmware to File + + + + + OpenTX Home Page: <a href='%1'>%1</a> + + + + + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> + + + + + If you've found this program useful, please support by <a href='%1'>donating</a> + + + + + Copyright OpenTX Team + + + + + About Companion + + + + + OpenTX Companion %1 - Radio: %2 - Profile: %3 + + + + + New + + + + + Create a new Models and Settings file + + + + + Open... + + + + + Save + + + + + + Save Models and Settings file + + + + + Save As... + + + + + Exit + + + + + Exit the application + + + + + Cut Model + + + + + Cut current model to the clipboard + + + + + Copy Model + + + + + Copy current model to the clipboard + + + + + Paste Model + + + + + Paste model from clipboard + + + + + Classical + + + + + The classic companion9x icon theme + + + + + Yerico + + + + + Yellow round honey sweet icon theme + + + + + Monochrome + + + + + A monochrome black icon theme + + + + + MonoWhite + + + + + A monochrome white icon theme + + + + + MonoBlue + + + + + A monochrome blue icon theme + + + + + Small + + + + + Use small toolbar icons + + + + + Normal + + + + + Use normal size toolbar icons + + + + + Big + + + + + Use big toolbar icons + + + + + Huge + + + + + Use huge toolbar icons + + + + + System language + + + + + Use system language in menus + + + + + Czech + + + + + Use Czech in menus + + + + + German + + + + + Use German in menus + + + + + English + + + + + Use English in menus + + + + + Finnish + + + + + Use Finnish in menus + + + + + French + + + + + Use French in menus + + + + + Italian + + + + + Use Italian in menus + + + + + Polish + + + + + Use Polish in menus + + + + + Spanish + + + + + Use Spanish in menus + + + + + Swedish + + + + + Use Swedish in menus + + + + + Chinese + + + + + Use Chinese in menus + + + + + About... + + + + + Show the application's About box + + + + + Print... + + + + + Print current model + + + + + Simulate... + + + + + Simulate current model + + + + + Alt+S + + + + + Load Backup... + + + + + Load backup from file + + + + + View Log File... + + + + + Open and view log file + + + + + Settings... + + + + + Edit Settings + + + + + Download... + + + + + Download firmware and voice files + + + + + Check for Updates... + + + + + Check OpenTX and Companion updates + + + + + Companion Changes... + + + + + Show Companion change log + + + + + Firmware Changes... + + + + + Show firmware change log + + + + + Compare Models... + + + + + Compare models + + + + + Edit Radio Splash Image... + + + + + Edit the splash image of your Radio + + + + + List programmers... + + + + + List available programmers + + + + + Fuses... + + + + + Show fuses dialog + + + + + Read firmware from Radio + + + + + Write Firmware to Radio + + + + + Write firmware to Radio + + + + + Add Radio Profile + + + + + Create a new Radio Setting Profile + + + + + Manuals and other Documents + + + + + Open the OpenTX document page in a web browser + + + + + Write Models and Settings To Radio + + + + + Write Models and Settings to Radio + + + + + Read Models and Settings From Radio + + + + + Configure Communications... + + + + + Configure software for communicating with the Radio + + + + + Write Backup to Radio + + + + + Write Backup from file to Radio + + + + + Backup Radio to File + + + + + Save a complete backup file of all settings and model data in the Radio + + + + + Contributors... + + + + + A tribute to those who have contributed to OpenTX and Companion + + + + + SD card synchronization + + + + + Recent Files + + + + + Set Menu Language + + + + + Set Icon Theme + + + + + Set Icon Size + + + + + + File + + + + + + Edit + + + + + Settings + + + + + Read/Write + + + + + + Help + + + + + + Radio Profile + + + + + Recent Models+Settings + + + + + Show recent Models+Settings documents + + + + + Show the list of radio profiles + + + + + Write + + + + + Ready + + + + + %2 + + + + + New Radio + + + + + MdiChild + + + Radio settings + + + + + Simulate Tx + + + + + Delete selected models? + + + + + Cannot delete default model. + + + + + &Edit + + + + + &Restore from backup + + + + + &Model Wizard + + + + + &Delete + + + + + Delete + + + + + &Copy + + + + + Ctrl+C + + + + + &Cut + + + + + Ctrl+X + + + + + + &Paste + + + + + + Ctrl+V + + + + + D&uplicate + + + + + Ctrl+U + + + + + Move to Category + + + + + &Use as default + + + + + P&rint model + + + + + Ctrl+P + + + + + &Simulate model + + + + + Alt+S + + + + + &Add model + + + + + &Rename category + + + + + &Delete category + + + + + &Add category + + + + + Models and settings will be automatically converted. +If that is not what you intended, please close the file +and choose the correct radio type/profile before reopening it. + + + + + Do you want to overwrite radio general settings? + + + + + You are pasting on an not empty model, are you sure? + + + + + free bytes + + + + + + Companion + + + + + This category is not empty! + + + + + New model + + + + + Editing model %1: + + + + + + + + + + + Error + + + + + + + + Save As + + + + + %1 has been modified. +Do you want to save your changes? + + + + + Unable to find Horus radio SD card! + + + + + Models and Settings written + + + + + Cannot write temporary file! + + + + + Open backup Models and Settings file + + + + + Unable to find file %1! + + + + + Error opening file %1: +%2. + + + + + Error reading file %1: +%2. + + + + + Invalid binary backup File %1 + + + + + Warning + + + + + MixerDialog + + + Dialog + + + + + Delay + + + + + Slow + + + + + Up + + + + + Down + + + + + + + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-weight:600; text-decoration: underline;">Delay ans Slow</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-weight:600; text-decoration: underline;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">These values control the speed and delay of the output of the mix. </p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Delay is not zero the actuation of the mix will be delayed by the specified amount of seconds.</p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Slow is not zero then the speed of the mix will be set by the value specified -&gt; the value states the number of seconds it takes to transit from -100 to 100.</p></body></html> + + + + + Include Trim + + + + + Offset + + + + + Weight + + + + + Name + + + + + Source + + + + + Multiplex + + + + + Warning + + + + + The curve used by the mix + + + + + Include DR/Expo + + + + + Flight modes + + + + + Switch + + + + + Mixer warning. +Setting this value will cause a beep to be emmitted when this value is active. + + + + + OFF + + + + + 1 Beep + + + + + 2 Beep + + + + + 3 Beep + + + + + No + + + + + Yes + + + + + + + GV + + + + + + + + The source for the mixer + + + + + Multiplexer + +This determines how mixer values are added. + +"+" means the value of the current mix is added to the previous mixes in the same channel. +"*" means the value of the current mix is amultiplied with the previous mixes in the same channel. +"R" means the value replaces the previous values. If the switch is off the value will be ignored. + + + + + ADD + + + + + MULTIPLY + + + + + REPLACE + + + + + Curve + + + + + Switch used by the mix. +If blank then the mix is considered to be "ON" all the time. + + + + + DEST -> CH%1 + + + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + + + + MixesPanel + + + + Move Up + + + + + + Ctrl+Up + + + + + + Move Down + + + + + + Ctrl+Down + + + + + Clear Mixes + + + + + Not enough available mixers! + + + + + Delete Selected Mixes? + + + + + &Add + + + + + Ctrl+A + + + + + &Edit + + + + + Enter + + + + + &Toggle highlight + + + + + Ctrl+T + + + + + &Delete + + + + + Delete + + + + + &Copy + + + + + Ctrl+C + + + + + C&ut + + + + + Ctrl+X + + + + + &Paste + + + + + Ctrl+V + + + + + Du&plicate + + + + + Ctrl+U + + + + + Clear Mixes? + + + + + Really clear all the mixes? + + + + + ModelEdit + + + Dialog + + + + + Simulate + + + + + Setup + + + + + Heli + + + + + Flight Modes + + + + + Inputs + + + + + Mixes + + + + + Outputs + + + + + Curves + + + + + Logical Switches + + + + + Special Functions + + + + + Telemetry + + + + + ModelPrinter + + + %1 bytes + + + + + CH%1 + + + + + Exponential + + + + + Extra Fine + + + + + Fine + + + + + Medium + + + + + Coarse + + + + + Unknown + + + + + Enabled + + + + + Disabled + + + + + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) + + + + + %1, Channels(%2-%3) + + + + + Receiver number(%1) + + + + + radio Protocol %1, subType %2, option value %3 + + + + + Slave/Jack + + + + + Master/SBUS Module + + + + + Master/CPPM Module + + + + + Master/SBUS in battery compartment + + + + + Master/Jack + + + + + 90 + + + + + 120 + + + + + 120X + + + + + 140 + + + + + + Off + + + + + Rudder + + + + + Elevator + + + + + Throttle + + + + + Aileron + + + + + Name(%1) + + + + + Persistent + + + + + MinuteBeep + + + + + CountDown(Beeps) + + + + + CountDown(Voice) + + + + + CountDown(Haptic) + + + + + + + + FM%1 + + + + + FM%1%2 + + + + + FM%1+%2 + + + + + [I%1] + + + + + Input%1 + + + + + Weight + + + + + Switch + + + + + + NoTrim + + + + + + Offset(%1) + + + + + Weight(%1) + + + + + Switch(%1) + + + + + No DR/Expo + + + + + Delay(u%1:d%2) + + + + + Slow(u%1:d%2) + + + + + Warn(%1) + + + + + Disabled in all flight modes + + + + + Flight modes(%1) + + + + + Flight mode(%1) + + + + + Edge(%1, [%2:%3]) + + + + + instant + + + + + Sticky(%1, %2) + + + + + Timer(%1, %2) + + + + + Duration(%1s) + + + + + Delay(%1s) + + + + + Custom + + + + + Standard + + + + + ModelSelectionPage + + + Plane + + + + + Multirotor + + + + + Helicopter + + + + + Model Name: + + + + + Model Type: + + + + + ModelsListWidget + + + No free slot available, cannot duplicate + + + + + Module + + + Start + + + + + CH + + + + + SubType + + + + + Polarity + + + + + Negative + + + + + Positive + + + + + Antenna + + + + + Internal + + + + + Ext. + Int. + + + + + Output type + + + + + Open Drain + + + + + Push Pull + + + + + Option value + + + + + Channels + + + + + Receiver No. + + + + + Bind on startup + + + + + Low Power + + + + + PPM delay + + + + + us + + + + + PPM Frame Length + + + + + ms + + + + + Protocol + + + + + Multi Radio Protocol + + + + + Failsafe Mode + + + + + Not set + + + + + Hold + + + + + Custom + + + + + No Pulses + + + + + Receiver + + + + + Trainer Mode + + + + + Master/Jack + + + + + Slave/Jack + + + + + Master/SBUS Module + + + + + Master/CPPM Module + + + + + Master/SBUS in battery compartment + + + + + Failsafe Positions + + + + + Show values in: + + + + + % + abbreviation for percent + + + + + μs + abbreviation for microseconds + + + + + ModulePanel + + + Trainer Port + + + + + Internal Radio System + + + + + External Radio Module + + + + + + Radio System + + + + + Extra Radio System + + + + + Value + + + + + Hold + + + + + No Pulse + + + + + MultiModelPrinter + + + General Model Settings + + + + + Name: + + + + + EEprom Size: + + + + + Timer%1: + + + + + Module%1: + + + + + Module: + + + + + Trainer port: + + + + + Throttle Trim: + + + + + Trim Increment: + + + + + Center Beep: + + + + + Helicopter Setup + + + + + Swash Type: + + + + + Swash Ring: + + + + + Input + + + + + Weight + + + + + Long. cyc + + + + + Lateral cyc + + + + + Collective + + + + + Flight modes + + + + + + Flight mode + + + + + Switch + + + + + Fade IN + + + + + Fade OUT + + + + + + FM%1 + + + + + + GV%1 + + + + + RE%1 + + + + + Limits + + + + + Channel + + + + + Name + + + + + + Offset + + + + + Min + + + + + Max + + + + + Invert + + + + + Global Variables + + + + + Inputs + + + + + Mixers + + + + + CV%1 + + + + + Curves + + + + + L%1 + + + + + Logical Switches + + + + + SF%1 + + + + + Special Functions + + + + + Telemetry Settings + + + + + Analogs + + + + + Unit + + + + + Scale + + + + + A%1 + + + + + RSSI Alarms + + + + + Low Alarm + + + + + Critical Alarm + + + + + MultirotorPage + + + Throttle Channel: + + + + + Yaw Channel: + + + + + Pitch Channel: + + + + + Roll Channel: + + + + + OptionsPage + + + Throttle Cut + + + + + Throttle Timer + + + + + Flight Timer + + + + + PrintDialog + + + Close + + + + + Print + + + + + Print to file + + + + + Print Document + + + + + Select PDF output file + + + + + ODF files (*.odt);;PDF Files(*.pdf);;HTML-Files (*.htm *.html);;All Files (*) + + + + + ProgressDialog + + + Flash Firmware + + + + + Close + + + + + ProgressWidget + + + Form + + + + + Show Details + + + + + QObject + + + Left Horizontal + + + + + Left Vertical + + + + + Right Vertical + + + + + Right Horizontal + + + + + Aux. 1 + + + + + Aux. 2 + + + + + + Unknown + + + + + FW: %1 + + + + + Pict: %1 + + + + + Profile image + + + + + Conversion error on field %1 + + + + + + -GV%1 + + + + + + + GV%1 + + + + + + + + + + + V + + + + + + A + + + + + mA + + + + + kts + + + + + + m/s + + + + + + + km/h + + + + + + + mph + + + + + + + m + + + + + f + + + + + + °C + + + + + °F + + + + + + % + + + + + + mAh + + + + + + W + + + + + mW + + + + + dB + + + + + rpms + + + + + + g + + + + + + ° + + + + + Rad + + + + + hours + + + + + minutes + + + + + seconds + + + + + + s + + + + + ft + + + + + h:m + + + + + m:s + + + + + h:m:s + + + + + + + REa + + + + + + + REb + + + + + TrmR + + + + + TrmE + + + + + TrmT + + + + + TrmA + + + + + Trm5 + + + + + Trm6 + + + + + + Batt + + + + + + Time + + + + + + + Timer1 + + + + + + + Timer2 + + + + + + + Timer3 + + + + + SWR + + + + + RSSI Tx + + + + + RSSI Rx + + + + + A1 + + + + + A2 + + + + + A3 + + + + + A4 + + + + + Alt + + + + + Rpm + + + + + Fuel + + + + + T1 + + + + + T2 + + + + + Speed + + + + + Dist + + + + + GPS Alt + + + + + Cell + + + + + Cells + + + + + Vfas + + + + + Curr + + + + + Cnsp + + + + + Powr + + + + + AccX + + + + + AccY + + + + + AccZ + + + + + Hdg + + + + + VSpd + + + + + AirSpeed + + + + + dTE + + + + + A1- + + + + + A2- + + + + + A3- + + + + + A4- + + + + + Alt- + + + + + Alt+ + + + + + Rpm+ + + + + + T1+ + + + + + T2+ + + + + + Speed+ + + + + + Dist+ + + + + + AirSpeed+ + + + + + Cell- + + + + + Cells- + + + + + Vfas- + + + + + Curr+ + + + + + Powr+ + + + + + ACC + + + + + GPS Time + + + + + + + + ---- + + + + + [I%1] + + + + + LUA%1%2 + + + + + MAX + + + + + + L%1 + + + + + CYC%1 + + + + + TR%1 + + + + + CH%1 + + + + + FM0 + + + + + FM1 + + + + + FM2 + + + + + FM3 + + + + + FM4 + + + + + FM5 + + + + + FM6 + + + + + FM7 + + + + + FM8 + + + + + RudTrim Left + + + + + RudTrim Right + + + + + EleTrim Down + + + + + EleTrim Up + + + + + ThrTrim Down + + + + + ThrTrim Up + + + + + AilTrim Left + + + + + AilTrim Right + + + + + Trim 5 Down + + + + + Trim 5 Up + + + + + Trim 6 Down + + + + + Trim 6 Up + + + + + + + OFF + + + + + + + ON + + + + + THs + + + + + TH% + + + + + THt + + + + + One + + + + + ??? + + + + + Diff(%1) + + + + + Expo(%1) + + + + + Function(%1) + + + + + Curve(%1) + + + + + !Curve(%1) + + + + + + + --- + + + + + a>x + + + + + a<x + + + + + |a|>x + + + + + |a|<x + + + + + AND + + + + + OR + + + + + XOR + + + + + a=b + + + + + a!=b + + + + + a>b + + + + + a<b + + + + + a>=b + + + + + a<=b + + + + + d>=x + + + + + |d|>=x + + + + + a=x + + + + + a~x + + + + + Timer + + + + + Sticky + + + + + Edge + + + + + Override %1 + + + + + Trainer + + + + + Trainer RUD + + + + + Trainer ELE + + + + + Trainer THR + + + + + Trainer AIL + + + + + Instant Trim + + + + + Play Sound + + + + + Haptic + + + + + Reset + + + + + Set Timer %1 + + + + + Vario + + + + + Play Track + + + + + Play Both + + + + + Play Value + + + + + Play Script + + + + + SD Logs + + + + + Volume + + + + + Backlight + + + + + Screenshot + + + + + Background Music + + + + + Background Music Pause + + + + + Adjust GV%1 + + + + + SetFailsafe Int. Module + + + + + SetFailsafe Ext. Module + + + + + RangeCheck Int. Module + + + + + RangeCheck Ext. Module + + + + + Bind Int. Module + + + + + Bind Ext. Module + + + + + Flight + + + + + Telemetry + + + + + Rotary Encoder + + + + + + + <font color=red><b>Inconsistent parameter</b></font> + + + + + Value + + + + + Decr: + + + + + Incr: + + + + + played once, not during startup + + + + + repeat(%1s) + + + + + DISABLED + + + + + INV + + + + + NOR + + + + + Switch + + + + + Switch + + + + + cannot be exported on this board! + + + + + Source %1 cannot be exported on this board! + + + + + OpenTX only accepts %1 points in all curves + + + + + OpenTx only accepts %1 points in all curves + + + + + + + + + + OpenTX on this board doesn't accept this function + + + + + OpenTX doesn't accept this telemetry protocol + + + + + OpenTX doesn't allow this number of channels + + + + + + + OpenTX doesn't accept this radio protocol + + + + + Unknown error + + + + + ... plus %1 errors + + + + + + + + + + + Error + + + + + Cannot write radio settings + + + + + Cannot write model %1 + + + + + + Rud + + + + + + Ele + + + + + + Thr + + + + + + Ail + + + + + + P1 + + + + + + P2 + + + + + + P3 + + + + + F1 + + + + + F2 + + + + + F3 + + + + + F4 + + + + + + + S1 + + + + + + + S2 + + + + + + + LS + + + + + + + RS + + + + + S3 + + + + + 6P + + + + + L1 + + + + + L2 + + + + + JSx + + + + + JSy + + + + + Channel values displayed in us + + + + + No OverrideCH functions available + + + + + Possibility to enable FAI MODE (no telemetry) at field + + + + + FAI MODE (no telemetry) always enabled + + + + + Support for the DIY-Multiprotocol-TX-Module + + + + + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 + + + + + Disable HELI menu and cyclic mix support + + + + + Disable Global variables + + + + + Support for Lua model scripts + + + + + Enable Lua compiler + + + + + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) + + + + + Instead of Joystick emulation, USB connection is Command Line Interface + + + + + + Adds mixers output view to the CHANNELS MONITOR screen, pressing [ENT] switches between the views + + + + + + Support for PPM internal module hack + + + + + + + + + + + + + + + Use alternative SQT5 font + + + + + ST7565P LCD or compatible + + + + + ST7565R LCD or compatible + + + + + ERC12864FSF LCD + + + + + ST7920 LCD + + + + + KS108 LCD + + + + + + Support for frsky telemetry mod + + + + + Support for telemetry easy board + + + + + + Support for jeti telemetry mod + + + + + + Support for receiving ardupilot data + + + + + + Support for receiving NMEA data + + + + + + Support for MAVLINK devices + + + + + Rotary Encoder use in menus navigation + + + + + + + + + + + Pots use in menus navigation + + + + + + + + + Support for DSM2 modules + + + + + Support for DSM2 modules using ppm instead of true serial + + + + + FrSky Taranis X9D+ + + + + + FrSky Taranis X9D + + + + + Haptic module installed + + + + + FrSky Taranis X9E + + + + + Confirmation before radio shutdown + + + + + Horus gimbals installed (Hall sensors) + + + + + FrSky Taranis X7 + + + + + FrSky Horus + + + + + Use ONLY with first DEV pcb version + + + + + Turnigy 9XR-PRO + + + + + + + Enable HELI menu and cyclic mix support + + + + + + + + + + + + + Enable TEMPLATES menu + + + + + + + + + + + + + No flight modes + + + + + + + + + + + + + Global variables + + + + + + + + + + + + + In model setup menus automatically set source by moving the control + + + + + + + + + + + + + In model setup menus automatically set switch by moving the control + + + + + + + + + + + + + No graphical check boxes and sliders + + + + + + + + + + + + + Battery graph + + + + + + + + + + + + + Don't use bold font for highlighting active items + + + + + + + Bluetooth interface + + + + + Turnigy 9XR with m128 chip + + + + + + + + + + Enable heli menu and cyclic mix support + + + + + + + + No splash screen + + + + + + + + + + Disable curves menus + + + + + + + + + Support for radio modified with regular speaker + + + + + + + + + + Used if you have modified your radio with voice mode + + + + + + + + + Used if you have modified your radio with haptic mode + + + + + + + + + + PPM center adjustment in limits + + + + + + + + + + Symetrical Limits + + + + + + + + Enable the throttle trace in Statistics + + + + + + + + + EEprom write Progress bar + + + + + + + + + + Imperial units + + + + + Turnigy 9XR + + + + + + No Winged Shadow How High support + + + + + + No vario support + + + + + + No GPS support + + + + + + No gauges in the custom telemetry screen + + + + + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) + + + + + 9X with stock board + + + + + + SmartieParts 2.2 Backlight support + + + + + + + + + + Enable resetting values by pressing up and down at the same time + + + + + EEprom write progress bar + + + + + Allow compensating for offset errors in FrSky FAS current sensors + + + + + 9X with stock board and m128 chip + + + + + 9X with AR9X board + + + + + 9X with Sky9x board + + + + + 9X with Gruvin9x board + + + + + + Support for SD memory card + + + + + + Support of FrSky PXX protocol + + + + + DIY MEGA2560 radio + + + + + Power management by soft-off circuitry + + + + + Negative span + + + + + Mid value + + + + + Positive span + + + + + Keys + + + + + Sticks + + + + + Keys + Sticks + + + + + English + + + + + Dutch + + + + + French + + + + + Italian + + + + + German + + + + + Czech + + + + + Slovak + + + + + Spanish + + + + + Polish + + + + + Portuguese + + + + + Swedish + + + + + Hungarian + + + + + No + + + + + RotEnc A + + + + + Rot Enc B + + + + + Rot Enc C + + + + + Rot Enc D + + + + + Rot Enc E + + + + + Rud Trim + + + + + Ele Trim + + + + + Thr Trim + + + + + Ail Trim + + + + + Rot Enc + + + + + !Flight mode %1 + + + + + Flight mode %1 + + + + + Own value + + + + + Flight mode %1 value + + + + + -GV%1 (%2) + + + + + GV%1 (%2) + + + + + Yellow + + + + + Orange + + + + + Red + + + + + Winged Shadow How High + + + + + Winged Shadow How High (not supported) + + + + + FrSky Sensor Hub + + + + + None + + + + + Imperial + + + + + Metric + + + + + Warning + + + + + Simulator for this firmware is not yet available + + + + + + Uknown error during Simulator startup. + + + + + Simulator Error + + + + + Data Load Error + + + + + Error occurred while starting simulator. + + + + + + + + + Synchronization error + + + + + No SD directory configured! + + + + + No Radio connected! + + + + + GV + + + + + Played once, not during startup + + + + + No repeat + + + + + %1s + + + + + Value + + + + + Source + + + + + GVAR + + + + + Increment + + + + + Trim disabled + + + + + Own Trim + + + + + Use Trim from Flight mode %1 + + + + + Use Trim from Flight mode %1 + Own Trim as an offset + + + + + THR + + + + + -%1 + + + + + + Models + + + + + + The directory '%1' doesn't exist! + + + + + Create '%1' failed + + + + + Copy '%1' to '%2' failed + + + + + Open '%1' failed + + + + + Write '%1' failed + + + + + Positive + + + + + Negative + + + + + Cannot write file %1: +%2. + + + + + Companion + + + + + <b><u>WARNING!</u></b><br>This will reset the fuses of %1 to the factory settings.<br>Writing fuses can mess up your radio.<br>Do this only if you are sure they are wrong!<br>Are you sure you want to continue? + + + + + + Could not delete temporary file: %1 + + + + + Unable to find Horus radio SD card! + + + + + Select a data file + + + + + Select Data Directory + + + + + Select SD Card Image Folder + + + + + Available profiles: + + + + + ID: + + + + + Name: + + + + + Available radios: + + + + + WARNING: couldn't initialize SDL: +%1 + + + + + ERROR: No simulator libraries available. + + + + + Radio profile ID or Name to use for simulator. + + + + + Radio type to simulate (usually defined in profile). + + + + + show this help text + + + + + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] + + + + + Options: + + + + + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. + Profile ID: [%1]; Radio ID: [%2]; +Data File: [%3] + + + + + ERROR: Radio profile or simulator firmware not found. +Profile ID: [%1]; Radio ID: [%2] + + + + + Error reading %1: %2 + + + + + Cannot save EEPROM + + + + + + Cannot open file %1: +%2. + + + + + + + Error writing file %1: +%2. + + + + + Invalid binary EEPROM file %1 + + + + + Can't extract RADIO/radio.bin + + + + + Can't extract RADIO/models.txt + + + + + Can't extract %1 + + + + + Unable to open %1: %2 + + + + + Invalid EEPROM file %1 + + + + + Invalid EEPROM File %1 + + + + + + Error opening file %1: +%2. + + + + + Error opening OTX archive %1 + + + + + Error initializing OTX archive writer + + + + + Error creating OTX file %1: +%2. + + + + + Error creating OTX archive + + + + + Error adding %1 to OTX archive + + + + + Error opening file %1 in write mode: +%2. + + + + + Unable to find file %1! + + + + + Thank you for upgrading to OpenTX 2.0. This is a major upgrade that adds and modifies a lot of things, so please make sure that you read release notes carefully to learn about the changes, and thoroughly check each of your models for proper function. + +The OpenTX Team. + + + + + QxtCommandOptions + + + sets the application GUI style + + + + + sets the application stylesheet + + + + + restores the application from an earlier session + + + + + displays debugging information about widgets + + + + + use right-to-left layout + + + + + never grab the mouse or keyboard + + + + + grab the mouse/keyboard even in a debugger + + + + + run in synchronous mode for debugging + + + + + use Direct3D by default + + + + + sets the X11 display + + + + + sets the geometry of the first window + + + + + sets the default font + + + + + sets the default background color + + + + + sets the default foreground color + + + + + sets the default button color + + + + + sets the application name + + + + + sets the application title + + + + + sets the X11 visual type + + + + + limit the number of colors on an 8-bit display + + + + + use a private color map + + + + + sets the input method server + + + + + disable the X Input Method + + + + + sets the style used by the input method + + + + + + option "%1" not found + + + + + Short options cannot have optional parameters + + + + + positional() called before parse() + + + + + unrecognized() called before parse() + + + + + count() called before parse() + + + + + value() called before parse() + + + + + parameters() called before parse() + + + + + unrecognized parameters: + + + + + %1 requires a parameter + + + + + RadioKnobWidget + + + Right-double-click to reset to center. + + + + + RadioNotFoundDialog + + + No Radio Found + + + + + <html><head/><body><p>No Radio was found!</p><p>Make sure that you hold the lower trim buttons towards the center while you turn it on.</p><p>Then connect the USB wire.</p><p><span style=" font-family:'arial,sans-serif'; font-size:13px; font-style:italic; color:#222222; background-color:#ffffff;">Note: if you have a Taranis that has not had the firmware upgraded to 2.0 then this version of Companion will not work.</span></p></body></html> + + + + + OK + + + + + RadioOutputsWidget + + + Form + + + + + View: + + + + + Logical Switches + + + + + Global Variables + + + + + Channel Outputs + + + + + L +o +g +i +c + + + + + G +l +o +b +a +l + + + + + C +h +a +n +n +e +l +s + + + + + RadioSwitchWidget + + + Latch/unlatch the momentary switch. + + + + + ReleaseNotesDialog + + + Companion Release Notes + + + + + ReleaseNotesFirmwareDialog + + + OpenTX Release Notes + + + + + RudderPage + + + No + + + + + Yes + + + + + <br>Rudder Channel: + + + + + Setup + + + Timer 1 + + + + + Top LCD Timer + + + + + Model Image + + + + + Warnings + + + + + Switch Warnings + + + + + Pot Warnings + + + + + OFF + + + + + Manual + + + + + Auto + + + + + Model + + + + + Center beep + + + + + Extended Trims + + + + + Display Checklist + + + + + Extended Limits + + + + + Reverse throttle operation. +If this is checked the throttle will be reversed. Idle will be forward, trim will also be reversed and the throttle warning will be reversed as well. + + + + + + + Reverse Throttle + + + + + Throttle Trim Idle Only + + + + + Throttle Warning + + + + + Exponential + + + + + Extra Fine + + + + + Fine + + + + + Medium + + + + + Coarse + + + + + Never + + + + + On change + + + + + Always + + + + + Global Functions + + + + + Throttle Source + + + + + Trim Step + + + + + Trims Display + + + + + Timer 2 + + + + + Timer 3 + + + + + SetupPanel + + + Timer %1 + + + + + SimpleTailPage + + + Elevator Channel: + + + + + SimulatedUIWidget + + + screenshot + Simulator LCD screenshot file name prefix + + + + + ENTER + + + + + PG-UP + + + + + PG-DN + + + + + DEL + + + + + BKSP + + + + + ESC + + + + + INS + + + + + <font size=+3>+</font> + + + + + <font size=+3>-</font> + + + + + <font size=+3>&larr;</font> + + + + + <font size=+3>&rarr;</font> + + + + + <font size=+3>&uarr;</font> + + + + + <font size=+3>&darr;</font> + + + + + <font size=+3>&#x2686;</font> + + + + + <font size=+3>&#x21b6;</font> + + + + + <font size=+3>&#x21b7;</font> + + + + + <font size=+3>&#x21c6;</font> + + + + + + <font size=+3>&#x21d3;</font> + + + + + <font size=+3>&#x21d1;</font> + + + + + <font size=+3>&#x21d5;</font> + + + + + <img src='qrc:/images/simulator/icons/svg/mouse.svg' width=20 height=18 /> + + + + + <img src='qrc:/images/simulator/icons/svg/arrow_click.svg' width=18 height=18 /> + + + + + <pre>[ MENU ]</pre> + + + + + <pre>[ PAGE ]</pre> + + + + + <pre>[ EXIT ]</pre> + + + + + <pre>[ ENT ]</pre> + + + + + <pre>[ UP ]</pre> + + + + + <pre>[ DN ]</pre> + + + + + <pre>[ <font size=+2>+</font> ]</pre> + + + + + <pre>[ <font size=+2>-</font> ]</pre> + + + + + <pre>[ PgUp ]</pre> + + + + + <pre>[ PgDn ]</pre> + + + + + <pre>[ MDL ]</pre> + + + + + <pre>[ RTN ]</pre> + + + + + <pre>[ SYS ]</pre> + + + + + <pre>[ TELE ]</pre> + + + + + <font size=+3>&#x2261;</font> + + + + + SimulatedUIWidget9X + + + + | + + + + + SimulatorMainWindow + + + OpenTx Simulator + + + + + View + + + + + Radio Window + + + + + Reload... + + + + + Tools + + + + + Toolbar + + + + + Reload Lua Scripts + + + + + Reload the Lua environment on the simulated radio. + + + + + F7 + + + + + Reload Radio Data + + + + + Reload all radio data without restarting the simulator. + + + + + F9 + + + + + Key Mapping + + + + + Show keyboard maping reference. + + + + + F1 + + + + + Joystick Settings + + + + + Open joystick configuration settings dialog. + + + + + F3 + + + + + LCD Screenshot + + + + + Save a screenshot of the current simulated LCD screen. + + + + + F8 + + + + + Dock In Main Window + + + + + Show the radio in the main window or as a separate "floating" window. + + + + + Menu Bar + + + + + Show or hide the top menu bar. + + + + + Alt+M + + + + + Constrain Width + + + + + Set radio widget width to be a fixed size. + + + + + Constrain Height + + + + + Set radio widget height to be a fixed size. + + + + + ERROR: Failed to create simulator interface, possibly missing or bad library. + + + + + Alt+T + + + + + Radio Outputs + + + + + F2 + + + + + Telemetry Simulator + + + + + F4 + + + + + Trainer Simulator + + + + + F5 + + + + + Debug Output + + + + + F6 + + + + + <b>Simulator Controls:</b> + + + + + <tr><th>Key/Mouse</th><th>Action</th></tr> + note: must match html layout of each table row (keyTemplate). + + + + + <tr><td><kbd>%1</kbd></td><td>%2</td></tr> + note: must match html layout of help text table header. + + + + + Simulator Help + + + + + SimulatorStartupDialog + + + OpenTX Simulator - Startup Options + + + + + Simulator Startup Options: + + + + + Radio Profile: + + + + + Existing radio profiles are shown here.<br /> +Create or edit profiles using the Companion application. + + + + + Radio Type: + + + + + Existing radio simulators are shown here.<br /> +The radio type specified in the selected profile is used by default. + + + + + Data Source: + + + + + Data File: + + + + + Data Folder: + + + + + SD Image Path: + + + + + Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> +<b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! + + + + + Select data file... + + + + + + + ... + + + + + Directory containing RADIO and MODELS folders to use.<br /> +New folder(s) with default radio/model will be created here if necessary. + + + + + Select data folder... + + + + + Directory containing the SD card image to use.<br/> +The default is configured in the chosen Radio Profile. + + + + + Select SD card image folder... + + + + + Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. + + + + + File + + + + + Folder + + + + + SD Path + + + + + All files (*.*) + + + + + SimulatorWidget + + + Companion Simulator + + + + + Radio Simulator (%1) + + + + + Could not determine startup data source. + + + + + Could not load data, possibly wrong format. + + + + + Data Load Error + + + + + Invalid startup data provided. Plese specify a proper file/path. + + + + + Simulator Startup Error + + + + + Error saving data: could open file for writing: '%1' + + + + + Error saving data: could not get data from simulator interface. + + + + + An unexpected error occurred while attempting to save radio data to file '%1'. + + + + + Data Save Error + + + + + Warning + + + + + Cannot open joystick, joystick disabled + + + + + Radio firmware error: %1 + + + + + - Flight Mode %1 (#%2) + + + + + SliderWidget + + + Right-double-click to reset to center. + + + + + SplashLibraryDialog + + + + ... + + + + + Splash Library - page %1 of %2 + + + + + Warning + + + + + Invalid image in library %1 + + + + + Information + + + + + No valid image found in library, check your settings + + + + + StandardPage + + + Channel %1 + + + + + SyncProcess + + + %1/%2 files + + + + + Create directory %1 + + + + + + Copy %1 to %2 + + + + + Write %1 + + + + + TailPage + + + Rudder Channel: + + + + + Elevator Channel: + + + + + Only one channel still available!<br>You probably should configure your model without using the wizard. + + + + + TailSelectionPage + + + Elevator and Rudder + + + + + Only Elevator + + + + + V-tail + + + + + Tail Type: + + + + + Telemetry + + + Protocol + + + + + Alarm 1 + + + + + + ---- + + + + + + Yellow + + + + + + Orange + + + + + + Red + + + + + Alarm 2 + + + + + RSSI + + + + + A1 + + + + + A2 + + + + + Sink Max + + + + + Climb Max + + + + + Sink Min + + + + + Climb Min + + + + + Center Silent + + + + + Vario limits + + + + + Vario source + + + + + Altimetry + + + + + Altitude source + + + + + Volts source + + + + + Top Bar + + + + + Volt source + + + + + Current source + + + + + Blades + + + + + mAh count + + + + + mAh + + + + + A + + + + + FAS Offset + + + + + Persistent mAh + + + + + Various + + + + + Serial Protocol + + + + + None + + + + + FrSky Sensor Hub + + + + + Sensors + + + + + Disable multi sensor handling + + + + + TelemetryAnalog + + + Unit + + + + + Max Value + + + + + Alarm 1 + + + + + + ---- + + + + + + Yellow + + + + + + Orange + + + + + + Red + + + + + + < + + + + + + > + + + + + Alarm 2 + + + + + Offset + + + + + Volts (V) + + + + + Amps (A) + + + + + Speed (m/s or ft/s) + + + + + Raw (-) + + + + + Speed (km/h or miles/h) + + + + + Meters (m or ft) + + + + + Temp (°) + + + + + Fuel (%) + + + + + mAmps (mA) + + + + + Range + + + + + TelemetryCustomScreen + + + Custom Screen Type + + + + + Min + + + + + Source + + + + + Gauge + + + + + Max + + + + + None + + + + + Numbers + + + + + Bars + + + + + Script + + + + + TelemetryPanel + + + Telemetry screen %1 + + + + + FrSky S.PORT + + + + + FrSky D + + + + + FrSky D (cable) + + + + + Low Alarm + + + + + Critical Alarm + + + + + Winged Shadow How High + + + + + Winged Shadow How High (not supported) + + + + + Alti + + + + + Alti+ + + + + + VSpeed + + + + + + + A1 + + + + + + + A2 + + + + + + A3 + + + + + + A4 + + + + + + FAS + + + + + Cells + + + + + --- + + + + + TelemetrySensor + + + Form + + + + + Custom + + + + + Calculated + + + + + Id + + + + + Instance + + + + + Add + + + + + Average + + + + + Min + + + + + Max + + + + + Multiply + + + + + Totalize + + + + + Cell + + + + + Consumption + + + + + Dist + + + + + Cells Sensor : + + + + + + + + + + + + --- + + + + + GPS Sensor : + + + + + Alt. Sensor : + + + + + Sensor : + + + + + Raw (-) + + + + + V + + + + + A + + + + + mA + + + + + kt + + + + + m/s + + + + + ft/s + + + + + km/h + + + + + mph + + + + + m + + + + + ft + + + + + °C + + + + + °F + + + + + % + + + + + mAh + + + + + W + + + + + mW + + + + + dBm + + + + + RPM + + + + + g + + + + + ° + + + + + Rad + + + + + mL + + + + + US fl.Oz. + + + + + Precision + + + + + Ratio + + + + + Blades + + + + + Offset + + + + + Multiplier + + + + + Auto Offset + + + + + Filter + + + + + Persistent + + + + + Positive + + + + + Logs + + + + + TelemetrySensorPanel + + + Lowest + + + + + Cell %1 + + + + + Highest + + + + + Delta + + + + + TelemetrySimulator + + + Telemetry Simulator + + + + + When enabled, sends any non-blank values as simulated telemetry data. + + + + + Simulate + + + + + Replay SD Log File + + + + + Replay rate + + + + + Load + + + + + |> + + + + + <| + + + + + > + + + + + <- + + + + + X + + + + + Row # +Timestamp + + + + + 1/5x + + + + + 5x + + + + + No Log File Currently Loaded + + + + + SWR + + + + + A2 + + + + + + + V / ratio + + + + + Db + + + + + RxBt + + + + + A1 + + + + + + + + + + + + + + + + + <html><head/><body><p><br/></p></body></html> + + + + + Tmp1 + + + + + A3 + + + + + A4 + + + + + RSSI + + + + + Tmp2 + + + + + + RPM + + + + + Fuel + + + + + °C + + + + + ml + + + + + Deg. C + + + + + % + + + + + + Meters + + + + + Alt + + + + + VSpd + + + + + m/s + + + + + Fuel Qty + + + + + + km/h + + + + + VFAS + + + + + Hdg + + + + + ASpd + + + + + + + G + + + + + GPS + + + + + Lat,Lon +(dec.deg.) + + + + + AccX + + + + + dd-MM-yyyy +hh:mm:ss + + + + + Date + + + + + Amps + + + + + AccZ + + + + + GAlt + + + + + + Volts + + + + + Cels + + + + + Curr + + + + + AccY + + + + + GSpd + + + + + Degrees + + + + + Log File + + + + + LOG Files (*.csv) + + + + + ERROR - invalid file + + + + + Templates + + + Simple 4-CH + + + + + T-Cut + + + + + Sticky T-Cut + + + + + V-Tail + + + + + Elevon\Delta + + + + + Heli Setup + + + + + Heli Setup with gyro gain control + + + + + Gyro gain control + + + + + Heli Setup (Futaba's channel assignment style) + + + + + Heli Setup with gyro gain control (Futaba's channel assignment style) + + + + + Gyro gain control (Futaba's channel assignment style) + + + + + Servo Test + + + + + MultiCopter + + + + + Use Model Config Wizard + + + + + Apply Template? + + + + + Apply template "%1"? + + + + + + + + + + + RUD + + + + + + + + + + + + + + ELE + + + + + + + THR + + + + + + + + + + + + AIL + + + + + + + + AIL2 + + + + + + + + ELE2 + + + + + + + + + + FLAPS + + + + + + + + + + FLAP%1 + + + + + + + + PITCH + + + + + + + + + + + + GYRO + + + + + + SPOIL + + + + + + SPOIL%1 + + + + + + RUD2 + + + + + + Clear Mixes? + + + + + Really clear existing mixes on CH6? + + + + + Really clear existing mixes on CH5? + + + + + ThrottlePage + + + Yes + + + + + No + + + + + <br>Throttle Channel: + + + + + Timer + + + Countdown + + + + + Minute Call + + + + + TimerPanel + + + Silent + + + + + Beeps + + + + + Voice + + + + + Haptic + + + + + Not persistent + + + + + Persistent (flight) + + + + + Persistent (manual reset) + + + + + Trainer + + + Form + + + + + Mode + + + + + Input + + + + + Weight + + + + + Rud + + + + + + + + + + + + Beeper volume + +0 - Quiet. No beeps at all. +1 - No Keys. Normal beeps but menu keys do not beep. +2 - Normal. +3 - Loud. +4 - Extra loud. + + + + + + + + Off + + + + + + + + += (Sum) + + + + + + + + := (Replace) + + + + + + + + chn1 + + + + + + + + chn2 + + + + + + + + chn3 + + + + + + + + chn4 + + + + + Ele + + + + + Thr + + + + + Ail + + + + + TrainerSimulator + + + Trainer simulator + + + + + TreeModel + + + Index + + + + + Name + + + + + Size + + + + + VTailPage + + + First Tail Channel: + + + + + Second Tail Channel: + + + + + VirtualJoystickWidget + + + Hld Y + + + + + Hold Vertical stick position. + + + + + Fix Y + + + + + Prevent Vertical movement of stick. + + + + + Fix X + + + + + Prevent Horizontal movement of stick. + + + + + Hld X + + + + + Hold Horizontal stick position. + + + + + WingtypeSelectionPage + + + Standard Wing + + + + + Flying Wing / Deltawing + + + + + WizardDialog + + + Model Wizard + + + + + Model Type + + + + + Enter model name and model type. + + + + + Throttle + + + + + Has your model got a motor or an engine? + + + + + Wing Type + + + + + Is your model a flying wing/deltawing or has it a standard wing configuration? + + + + + Ailerons + + + + + Has your model got ailerons? + + + + + Flaps + + + + + Has your model got flaps? + + + + + Airbrakes + + + + + Has your model got airbrakes? + + + + + Flying-wing / Delta-wing + + + + + Select the elevons channels + + + + + Rudder + + + + + Does your model have a rudder? + + + + + Tail Type + + + + + Select which type of tail your model is equiped with. + + + + + + Tail + + + + + + Select channels for tail control. + + + + + V-Tail + + + + + Select elevator channel. + + + + + Cyclic + + + + + Which type of swash control is installed in your helicopter? + + + + + Tail Gyro + + + + + Has your helicopter got an adjustable gyro for the tail? + + + + + Rotor Type + + + + + Has your helicopter got a flybar? + + + + + + Helicopter + + + + + + Select the controls for your helicopter + + + + + Multirotor + + + + + Select the control channels for your multirotor + + + + + Model Options + + + + + Select additional options + + + + + Save Changes + + + + + Manually check the direction of each control surface and reverse any channels that make controls move in the wrong direction. Remove the propeller/propellers before you try to control your model for the first time.<br>Please note that continuing removes all old model settings! + + + + + Enter a name for your model and select model type. + + + + + Select the receiver channel that is connected to your ESC or throttle servo.<br><br>Throttle - Spektrum: CH1, Futaba: CH3 + + + + + Most aircraft have a main wing and a tail with control surfaces. Flying wings and delta winged aircraft only have a single wing. The main control surface on a standard wing controls the roll of the aircraft. This surface is called an aileron.<br>The control surface of a delta wing controls both roll and pitch. This surface is called an elevon. + + + + + Models use one or two channels to control the ailerons.<br>A so called Y-cable can be used to connect a single receiver channel to two separate aileron servos. If your servos are connected by a Y-cable you should select the single-servo option.<br><br>Aileron - Spektrum: CH2, Futaba: CH1 + + + + + This wizard assumes that your flaps are controlled by a switch. If your flaps are controlled by a potentiometer you can change that manually later. + + + + + Air brakes are used to reduce the speed of advanced sail planes.<br>They are very uncommon on other types of planes. + + + + + Models use two channels to control the elevons.<br>Select these two channels + + + + + Select the receiver channel that is connected to your rudder.<br><br>Rudder - Spektrum: CH4, Futaba: CH4 + + + + + Select the tail type of your plane. + + + + + + Select the Rudder and Elevator channels.<br><br>Rudder - Spektrum: CH4, Futaba: CH4<br>Elevator - Spektrum: CH3, Futaba: CH2 + + + + + Select the Elevator channel.<br><br>Elevator - Spektrum: CH3, Futaba: CH2 + + + + + + + + + + + TBD. + + + + + Select the control channels for your multirotor.<br><br>Throttle - Spektrum: CH1, Futaba: CH3<br>Yaw - Spektrum: CH4, Futaba: CH4<br>Pitch - Spektrum: CH3, Futaba: CH2<br>Roll - Spektrum: CH2, Futaba: CH1 + + + + + There is no help available for the current page. + + + + + Model Wizard Help + + + + + WizardPrinter + + + Plane + + + + + Multicopter + + + + + Helicopter + + + + + Model Name: + + + + + Model Type: + + + + + Options: + + + + + Channel %1: + + + + + burnConfigDialog + + + Programmer Configuration + + + + + + Location of sam-ba executable + + + + + + + + The location of the AVRDUDE executable. + + + + + DFU-Util Location + + + + + Location of AVRDUDE executable + + + + + + + Use this button to browse and look for the AVRDUDE executable file. + + + + + + + Browse... + + + + + Programmer + + + + + Programmer used for communicating with the controller. +Please consult the programmer's documentation and the AVRDUDE documentation to select the appropriate programmer. + + + + + List all available programmers. + + + + + List Available + + + + + + Extra arguments that will be passed to AVRDUDE on every call + + + + + + Extra arguments used in AVRDUDE. +This can be used for providing extra information to AVRDUDE. + +Please only use this if you know what you are doing. There are no error checks and you could cripple your controller. + + + + + Extra Arguments + + + + + Show AVRDUDE help + + + + + Show Help + + + + + Communication port to the programmer. + + + + + + + Port + + + + + AVRDUDE Location + + + + + MCU + + + + + + CPU of your TX + + + + + + CPU present on your 9x radio +Should be m64 for stock radios +m2560 for v4.1 boards + + + + + at91sam3s8-9xr + + + + + SAM-BA Location + + + + + ARM MCU + + + + + sam-ba serial port + + + + + Alternate device + + + + + Use advanced controls + + + + + DFU-UTIL Configuration + + + + + SAM-BA Configuration + + + + + AVRDUDE Configuration + + + + + + + Select Location + + + + + List available programmers + + + + + Avrdude help + + + + + Companion + + + + + <b><u>WARNING!</u></b><br>Normally CPU type is automatically selected according to the chosen firmware.<br>If you change the CPU type the resulting eeprom could be inconsistent. + + + + + customizeSplashDialog + + + Transmitter Splash Screen Editor + + + + + + Invert + + + + + + Open Splash Library + + + + + + + + ... + + + + + + Load Profile + + + + + + Load FW + + + + + + Load Pict + + + + + + Save + + + + + Open Firmware File + + + + + + + + Error + + + + + Can not load embedded image from firmware file %1. + + + + + Open Image to load + + + + + Images (%1) + + + + + Cannot load the image file %1. + + + + + Cannot load profile image %1. + + + + + Cannot load the library image %1. + + + + + File Saved + + + + + The image was saved to the file %1 + + + + + Image Refresh Error + + + + + Failed to refresh image from file %1 + + + + + File Save Error + + + + + Failed to write image to %1 + + + + + downloadDialog + + + Downloading: + + + + + Unable to save the file %1: %2. + + + + + Companion + + + + + Download failed: %1. + + + + + joystickDialog + + + Configure Joystick + + + + + Ch2 + + + + + Ch1 + + + + + Ch4 + + + + + Ch6 + + + + + Ch3 + + + + + Ch5 + + + + + Ch7 + + + + + Ch8 + + + + + Instructions + + + + + Enable + + + + + Cancel + + + + + Back + + + + + Start + + + + + Ok + + + + + Not Assigned + + + + + Stick + + + + + Knob/Slider %1 + + + + + No joysticks found + + + + + Error + + + + + Cannot open joystick. + + + + + Press the Start button to start the stick range calibration procedure. +You may change the channel assignments or inversion at any time. + + + + + Move sticks and pots in every direction making full movement +Press Next when finished + + + + + Next + + + + + Place sticks and pots in middle position. +Press Next when done + + + + + Map joystick channels to controls using comboboxes. +Press Next when done. + + + + + Check inversion checkbox to if necessary to reverse direction. +Press Next when done. + + + + + Press OK to save configuration +Press Cancel to abort joystick calibration without saving. + + + + + Warning + + + + + Calibration not complete, save anyway? + + + + + preferencesDialog + + + Preferences + + + + + Simu BackLight + + + + + Simulator capture folder + + + + + Joystick + + + + + Remember simulator switches + + + + + Enable + + + + + Use clipboard only + + + + + Calibrate + + + + + Blue + + + + + Green + + + + + Red + + + + + Orange + + + + + Yellow + + + + + + Open Folder + + + + + Personal splash library + + + + + Include companion splashes + + + + + Only user defined splashes + + + + + Splash library behaviour + + + + + Custom TX splash screen + + + + + Open Image + + + + + + ... + + + + + Invert Pixels + + + + diff --git a/companion/src/translations/companion_zh.ts b/companion/src/translations/companion_zh_CN.ts similarity index 100% rename from companion/src/translations/companion_zh.ts rename to companion/src/translations/companion_zh_CN.ts From 0fa50df355e2280f62d47909b32fd6e4f653e4b6 Mon Sep 17 00:00:00 2001 From: LapinFou Date: Sat, 25 Mar 2017 13:27:28 +0100 Subject: [PATCH 037/203] Update French transation. --- companion/src/translations/companion_fr.ts | 2603 ++++---------------- 1 file changed, 515 insertions(+), 2088 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 71ce9a35f..2713d4559 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -61,49 +61,41 @@ AppPreferencesDialog - Edit Settings Modifier les réglages - Radio Profile Profil de radio - Default Channel Order Ordre des voies par défaut - Build Options Options de compilation - Menu Language Langue des menus - Default Stick Mode Mode par défaut - Select Image Sélectionner une image - Mode selection: Mode 1: @@ -145,207 +137,172 @@ Manche Droit: Profondeur, Direction - Mode 1 (RUD ELE THR AIL) Mode 1 (DIR PROF GAZ AIL) - Mode 2 (RUD THR ELE AIL) Mode 2 (DIR GAZ PROF AIL) - Mode 3 (AIL ELE THR RUD) Mode 3 (AIL PROF GAZ DIR) - Mode 4 (AIL THR ELE RUD) Mode 4 (AIL GAZ PROF DIR) - Splash Screen Ecran d'accueil - - The profile specific folder, if set, will override general Backup folder Dossier de sauvegarde spécifique au profil courant, si défini remplace le réglage de l'application - Backup folder Dossier de sauvegarde - If set it will override the application general setting Si défini, remplace le réglage de l'application pour ce profil - if set, will override general backup enable Si défini, remplace le réglage de l'application pour ce profil - <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> <html><head/><body><p>Ordre des voies</p><p><br/></p><p>Détermine l'ordre des mixages par défaut sur un nouveau modèle.</p></body></html> - R E T A D P G A - R E A T D P A G - R T E A D G P A - R T A E D G A P - R A E T D A P G - R A T E D A G P - E R T A P D G A - E R A T P D A G - E T R A P G D A - E T A R P G A D - E A R T P A D G - E A T R P A G D - T R E A G D P A - T R A E G D A P - T E R A G P D A - T E A R G P A D - T A R E G A D P - T A E R G A P D - A R E T A D P G - A R T E A D G P - A E R T A P D G - A E T R A P G D - A T R E A G D P - A T E R A G P D @@ -355,95 +312,76 @@ Manche Droit: Profondeur, Direction - - - - - Select Folder Sélectionner dossier - Select Executable Sélectionner exécutable - Use OpenTX firmware nightly builds Utlilser les nightly builds du firmware - Use Companion nightly builds Utlilser les nightly builds de Companion - Simulator Volume Gain Gain de volume du simulateur - Profile Name Nom du profil - Remove Profile Supprimer le profil - Clear Image Effacer l'image - Append version number to FW file name Ajouter le numéro de version au nom du fichier téléchargé - Offer to write FW to Tx after download Proposer de transférer le firmware à la radio après téléchargement - Radio Type Type de radio - Other Settings Autres réglages - General Settings Paramètres généraux - SD Structure path Chemin de la structure de la carte SD - Set voice language. May be different from firmware language Langue des voix. @@ -451,165 +389,137 @@ Peut être différente de la langue du firmware - Voice Language Langue des voix - Application Settings Réglages de l'application - Show splash screen when Companion starts Afficher l'écran d'accueil au lancement de Companion - Automatic check for Companion updates Vérifier la présence de mises à jour de Companion automatiquement - - Enable automatic backup before writing firmware Sauvegarder les réglages et modèles automatiquement lors des transferts - Automatic check for OpenTX firmware updates Vérifier la présence de mises à jour de firmware automatiquement - Splash Screen Library Bibliothèque d'écrans d'accueil - Files to keep Fichiers à conserver - Google Earth Executable Exécutable Google Earth - Only show user splash images Ne montrer que les images de l'utilisateur - Show user and companion splash images Montrer les images de Companion et de l'utilisateur - User Splash Screens Ecrans d'accueil personnalisés - Automatic Backup Folder Dossier de sauvegardes automatiques - Use model wizard when creating a new model Utiliser l'assistant à la création d'un nouveau modèle - Simulator Settings Paramètres du simulateur - Simulator BackLight Rétroéclairage du simulateur - Enable Actif - Blue Bleu - Green Vert - Red Rouge - Orange Orange - Yellow Jaune - Joystick - Calibrate Calibrer - Simulator capture folder Dossier des captures d'écran - Only capture to clipboard Capturer dans le presse-papiers uniquement - Remember simulator switch values Mémoriser les positions des inters du simulateur @@ -689,96 +599,103 @@ Peut être différente de la langue du firmware Channels - + Name Nom - + Min Min - + Max Max - + Subtrim Subtrim - + Direction Direction - + Curve Courbe - + PPM Center Neutre PPM - + Linear Subtrim Subtrim linéaire - + CH%1 VOIE%1 - + --- - + INV + + CompanionMacros + + + files + + + + + Radio and Models settings + + + CompareDialog - Compare Models Comparer les modèles - Drag first model here Glisser le premier modèle ici - Drag second model here Glisser le second modèle ici - Close Fermer - Print Imprimer - Print to file Imprimer vers un fichier @@ -877,22 +794,22 @@ Peut être différente de la langue du firmware CurveGroup - + Diff - + Expo - + Func Fonc - + Curve Courbe @@ -901,99 +818,82 @@ Peut être différente de la langue du firmware Curves - Fixed X X fixe - Custom X X configurable - Lines Linéaire - Smooth Adoucie - - Curve type Type de courbe - Curve Creator Créateur de courbe - Y at X=0 Y pour X=0 - Y at X=100 Y pour X=100 - Both Les 2 - x>0 - x<0 - Apply Appliquer - Side Côté - Y at X=-100 Y pour X=-100 - Coefficient - Curve name Nom de la courbe @@ -1183,29 +1083,21 @@ Peut être différente de la langue du firmware DebugOutput - - Debug Output Sortie débogage - - <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> <html><head/><body><p>Activer ou désactiver le filtre. Si le bouton ne reste pas actif, c'est qu'il y a probablement une erreur dans la <i>Regular Expression</i>.</p></body></html> - - Filter: Filtre: - - <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> <html><head/><body><p>Entrer le filtre ici. Cliquer sur le bouton d'aide/info pour plus de détails sur l'utilisation du filtre. </p><p> @@ -1213,81 +1105,61 @@ Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le - - Buffer: Tampon: - - Number of lines to keep in display. Nombre de lignes du tampon. - - Filter &Help Filtre &Aide - - Show information about using the filter. Affiche les informations concernant l'usage du filtre. - - Word &Wrap Renvoi &Ligne - - Toggle word wrapping on/off. Retour automatique à la ligne on/off. - - &Clear &Effacer - - Clear the output window of all text. Effacer tout le texte dans la fenêtre de sortie. - - Enable &Filter Activer &Filtre - - Turn the filter on/off. Basculer le filtre on/off. - + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>Le filtre supporte deux types de syntaxes: la recherche simple utilisant les métacaractères ou la recherche avancée utilisant les expressions régulières (<code>RegEx</code>) de type Perl.</p><p>Par défaut, un filtre ne montre que les lignes qui correspondent (<b>inclusif</b>). Pour faire un filtre <b>exclusif</b> qui supprime les lignes de correspondance, préfixez l'expression du filtre avec un <kbd>!</kbd> (point d'exclamation).</p><p>Pour utiliser les <b>Expressions Régulières</b> (RegEx), préfixez le texte du filtre avec un <kbd>/</kbd> (slash) ou <kbd>^</kbd> (accent circonflexe).<ul><li>Il faut mettre le <kbd>!</kbd> <u>avant</u> le <kbd>/</kbd> ou <kbd>^</kbd> dans le cas d'un filtre exclusif.</li><li>Par défaut, la correspondance est sensible à la casse (ex: a &ne; A). Pour la rendre insensible (ex: a = A), ajoutez l'opérateur typique <kbd>/i</kbd> (slash i) à la fin de votre RegEx.</li><li>Si vous utilisez un <kbd>^</kbd> pour désigner une RegEx, il deviendra une partie de la RegEx (<kbd>^</kbd> est le caractère de début de chaîne).</li><li>Si la RegEx n'est pas valide, le champ d'édition du filtre affichera une bordure rouge et vous ne pourrez pas activer le filtre.</li><li>Une ressource utile pour tester les RegExs (avec une référence complète) peut être trouvée sur le site <a href="http://www.regexr.com/">http://www.regexr.com/</a> (tutoriel en français: <a href="http://perl.mines-albi.fr/DocFr/perlretut.html">Expressions rationnelles/régulières en Perl</a>)</li></ul></p><p>Pour utiliser la <b>recherche simple</b>, tapez simplement le texte recherché.<ul><li>Métacaractères: le quantificateur <kbd>*</kbd> (astérisque) correspond à zéro ou plus de n'importe quel caractère, et le quantificateur <kbd>?</kbd> (point d'interrogation) correspond à un caractère unique.</li><li>La correspondance est toujours sensible à la casse.</li><li>La correspondance commence toujours au début du Log. Pour ignorer les caractères au début, utilisez le métacaractère <kbd>*</kbd>.</li><li>Un métacaractère <kbd>*</kbd> est implicitement ajouté à la fin (ainsi, toutes les correspondances valides soient bien affichées jusqu'à la fin du Log). Si vous voulez éviter ce métacaractère implicite, il faut utiliser une RegEx.</li><li>Pour rechercher un caractère qui est lui-même un métacaractère, il faut préfixer avec un <kbd>\</kbd> (backslash) (ex: "<i>toto\*titi</i>" correspond à "<i>toto*titi</i>").</li></ul></p><p>Quand l'<b>édition</b> est terminée, appuyez sur la touche ENTRER ou TAB (ou cliquez n'importe où à l'extérieur du champ du filtre) afin de mettre à jour le filtre.</p><p>Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le d'abord, puis faite le raccourci clavier <kbd>Shift-Supprimer</kbd> (ou <kbd>Shift-Retour Arrière</kbd>). Les filtres par défaut ne peuvent pas être effacés. Jusqu'à 50 filtres peuvent être mémorisés.</p></body></html> - + Debug Console Filter Help Aide sur les filtres pour la console de débogage @@ -1403,19 +1275,16 @@ Il est recommandé d'"Enregistrer Sous" au plus vite pour ne pas ExpoDialog - Weight Ratio - Flight modes Phases de vol - Input name Nom de l'entrée @@ -1423,51 +1292,41 @@ Il est recommandé d'"Enregistrer Sous" au plus vite pour ne pas - - - GV VG - Switch Interrupteur - Curve applied to the source. Courbe appliquée à la source. - Source - Line name Nom de la ligne - Stick Side Direction - Source for the mixer. La voie maître du mixage. - Switch used to enable the line. If blank then the input is considered to be "ON" all the time. Interrupteur utilisé pour activer la ligne. @@ -1475,61 +1334,51 @@ Si vide, la ligne est toujours active. - Scale Echelle - Include Trim Inclure Trim - No Non - Yes Oui - Curve Courbe - Offset Décalage - The source for the mixer La voie maître du mixage - NEG Négative - POS Positive - ALL Les 2 @@ -1586,25 +1435,21 @@ Si vide, la ligne est toujours active. FirmwarePreferencesDialog - Downloads Téléchargements - Check for updates Vérifier les mises à jour - Voice Voix - Set voice language. May be different from firmware language Langue des voix. @@ -1612,25 +1457,21 @@ Peut être différente de la langue du firmware - Download Voice Télécharger les fichiers son - Download FW Télécharger le firmware - Firmware - Latest Download Dernière version téléchargée @@ -1667,80 +1508,67 @@ Peut être différente de la langue du firmware FlashEEpromDialog - Write Models and Settings to Radio Transférer les réglages et modèles vers la radio - Load... Parcourir... - Current Profile Profil courant - Allows Companion to write to older version of the firmware Permet à Companion de transférer des réglages à une ancienne version de firmware - Check Firmware compatibility Vérifier la compatibilité du firmware - <html><head/><body><p>Saves a dated copy of your eeprom to the backup folder you specified in the Companion settings before writing the current model to the radio.</p></body></html> <html><head/><body><p>Enregistre une copie datée de votre eeprom actuelle dans le dossier de sauvegarde avant de transférer les modèles à la radio.</p></body></html> - Backup before Write Sauvegarder les réglages actuels avant d'écrire - <html><head/><body><p>Modify calibration parameters using settings from current profile</p></body></html> <html><head/><body><p>Charger l'étalonnage du profil courant</p></body></html> - Patch calibration setting from profile Patcher l'étalonnage du profil courant - <html><head/><body><p>Modify HW parameters using settings from current profile</p></body></html> <html><head/><body><p>Charger les paramètres hardware du profil courant</p></body></html> - Patch HW settings from profile Patcher les paramètres hardware du profil courant - Cancel Annuler - Write to TX Transférer @@ -1813,85 +1641,71 @@ Peut être différente de la langue du firmware FlashFirmwareDialog - Flash Firmware Programmer le firmware - Load... Parcourir... - Date & Time Date et heure - Variant Variante - Version - Use profile start screen Utiliser l'écran d'accueil du profil - Use firmware start screen Utiliser l'écran d'accueil du firmware - Use library start screen Utiliser un écran d'accueil de la bibliothèque - Use another start screen Utiliser un autre écran d'accueil - Allows Companion to write to older version of the firmware Permet à Companion de transférer des réglages à une ancienne version de firmware - Check Hardware compatibility Vérifier la compatibilité du hardware - Backup and restore Models and Settings Sauvegarder et restaurer les réglages et modèles - Cancel Annuler - Write to TX Transférer @@ -2116,25 +1930,21 @@ Veuillez utiliser Zadig pour installer le pilote. FlightMode - Fade In Fondu en entrée - Fade Out Fondu en sortie - Name Nom - Switch Interrupteur @@ -2212,13 +2022,11 @@ Veuillez utiliser Zadig pour installer le pilote. FusesDialog - Fuses Fusibles - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2248,13 +2056,11 @@ p, li { white-space: pre-wrap; } - Read Fuses Lire Fusibles - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2289,7 +2095,6 @@ p, li { white-space: pre-wrap; } - Reset Fuses EEPROM - PROTECT Réinitialiser Fusibles @@ -2297,7 +2102,6 @@ PROTECTION EEPROM - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2330,7 +2134,6 @@ p, li { white-space: pre-wrap; } - Reset Fuses EEPROM - DELETE Réinitialiser Fusibles @@ -2338,7 +2141,6 @@ EFFACEMENT EEPROM - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2377,13 +2179,11 @@ p, li { white-space: pre-wrap; } - Radio settings Réglages Radio - General settings used throught the transmitter. These will be relevant for all models in the same EEPROM. Paramètres généraux de l'émetteur. @@ -2396,13 +2196,11 @@ Communs à tous les modèles d'une même EEPROM. - Store calib. and hw settings in selected profile Sauver étalonnage et réglages hw dans profil - Retrieve calib. and hw settings from profile Lire étalonnage et réglages hw du profil @@ -2458,257 +2256,213 @@ Communs à tous les modèles d'une même EEPROM. GeneralSetup - Form Formulaire - Readonly Unlock Débloquage lecture seule - SC - SE - SA - SF - SH - SD - SB - SG - Timeshift from UTC Décalage horaire (UTC) - Voice Language Langue des voix - Country Code Zone géograhpique RF - Stick reverse Inversion des manches - FAI Mode Mode FAI - If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Lorsque le mode FAI est activé, le variomètre ainsi que l'écran et la lecture des valeurs de télémesure sont désactivés. Ce mode ne peut pas être désactivé sur la radio. - Adjust RTC Ajuster l'heure par GPS - Vario pitch at max Tonalité du vario au max - - Hz - Speaker Volume Volume haut-parleur - Backlight Switch Inter de rétroéclairage - Sound Mode Mode Son - Color 1 Couleur 1 - Color 2 Couleur 2 - Speaker Pitch (spkr only) Tonalité (HP uniquement) - If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. Si cette valeur est différente de 0, l'appui sur une touche de navigation déclenche le rétroéclairage qui s'éteint après la durée spécifiée (en secondes). - sec - Backlight color Couleur du rétroéclairage - Beeper Bipeur - Speaker Haut-parleur - BeeperVoice Bipeur/Voix - SpeakerVoice Haut-parleur/Voix - Beep volume Volume des bips - Wav volume Volume des fichiers audio - Vario volume Volume du variomètre - Background volume Volume de la musique d'ambiance - - ms - Backlight Auto OFF after Arrêt rétroéclairage après - Backlight flash on alarm Clignotement rétroécl. alarmes - Vario pitch at zero Tonalité du vario à 0 - Vario repeat at zero Répétition du vario à 0 - This is the switch selectrion for turning on the backlight (if installed). @@ -2717,8 +2471,6 @@ Communs à tous les modèles d'une même EEPROM. - - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2734,49 +2486,41 @@ p, li { white-space: pre-wrap; } - Backlight Brightness Luminosité du rétroéclairage - RotEnc Navigation Navigation sélecteur rotatif - Automatically adjust the radio's clock if a GPS is connected to telemetry. Régle automatique l'heure de la radio si un GPS est présent. - America Amérique - Japan Japon - Europe - Backlight OFF Brightness Luminosité écran éteint - Mode selection: Mode 1: @@ -2818,327 +2562,270 @@ Mode 4: - Mode 1 (RUD ELE THR AIL) Mode 1 (DIR PRF GAZ AIL) - Mode 2 (RUD THR ELE AIL) Mode 2 (DIR GAZ PRF AIL) - Mode 3 (AIL ELE THR RUD) Mode 3 (AIL PRF GAZ DIR) - Mode 4 (AIL THR ELE RUD) Mode 4 (AIL GAZ PRF DIR) - <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> <html><head/><body><p>Ordre des voies</p><p><br/></p><p>Détermine l'ordre des mixages par défaut sur un nouveau modèle.</p></body></html> - R E T A D P G A - R E A T D P A G - R T E A D G P A - R T A E D G A P - R A E T D A P G - R A T E D A G P - E R T A P D G A - E R A T P D A G - E T R A P G D A - E T A R P G A D - E A R T P A D G - E A T R P A G D - T R E A G D P A - T R A E G D A P - T E R A G P D A - T E A R G P A D - T A R E G A D P - T A E R G A P D - A R E T A D P G - A R T E A D G P - A E R T A P D G - A E T R A P G D - A T R E A G D P - A T E R A G P D - Stick Mode Mode - Metric Métrique - Imperial Impérial - Default Channel Order Ordre des voies par défaut - GPS Coordinates Coordonnées GPS - Min - - v - Max - Low Memory Warning Alerte mémoire pleine - Inactivity Timer Alerte d'inactivité - Show Splash Screen on Startup Afficher l'écran de démarrage - Contrast Contraste - Battery Meter Range Plage de l'indicateur de batterie - Haptic Strength Puissance vibreur - LCD Display Type Type de LCD - "No Sound" Warning Alerte "son coupé" - Battery Warning Alerte batterie - Haptic Length Durée vibreur - MAVLink Baud Rate Baudrate Mavlink - - Quiet Mode silencieux - Only Alarms Seulement les alarmes - - No Keys Touches silencieuses - - All Tous - Battery warning voltage. This is the threashhold where the battery warning sounds. @@ -3150,138 +2837,114 @@ Plage de valeurs: 5v...10v - Standard - Optrex - If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. Si différent de 0, émission d'un bip sonore régulier si aucune action n'a été effectuée sur l'émetteur depuis le temps spécifié (en minutes). Réinitialisation en agissant sur n'importe lequel des manches / touches de navigation. - min - - Show splash screen on startup Affiche l'écran d'accueil au démarrage - --- - 2s - 3s - 4s - 6s - 8s - 10s - 15s - 4800 Baud - 9600 Baud - 14400 Baud - 19200 Baud - 38400 Baud - 57600 Baud - 76800 Baud - 115200 Baud - - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -3308,88 +2971,70 @@ p, li { white-space: pre-wrap; } - - X-Short Très court - - Short Court - - Normal - - Long - - X-Long Très long - hh° (N/S) mm' ss''.dd - NMEA - Play Delay (switch mid position) Délai position centrale inters - Measurement Units Unités de mesure - Haptic Mode Mode du vibreur - Beeper Length Durée des bips - Beeper Mode Réglage des bips - Beeper volume 0 - Quiet. No beeps at all. @@ -3407,7 +3052,6 @@ Extra long : bips extra longs. - Alarms Only Seulement les Alarmes @@ -3444,61 +3088,51 @@ Are you sure ? Hardware - Form Formulaire - SQ - SR - LS2 - SP - SO - S4 - RS - SB - PPM 2 @@ -3513,16 +3147,6 @@ Are you sure ? - - - - - - - - - - Beeper volume 0 - Quiet. No beeps at all. @@ -3540,223 +3164,186 @@ Extra long : bips extra longs. - OFF Eteint - S-Port Mirror Recopie S. Port - Telemetry Télémetrie - SBUS Trainer Écolage SBUS - Debug Débogage - Rud Dir - PPM 3 - S1 - S2 - S3 - PPM 1 - Serial Port Port série - v - PPM Multiplier Coeff. multiplicateur PPM - Current Offset Correction courant - PPM 4 - SA - Ele Prf - Ail Ail - Thr Gaz - SC - LS - SD - Battery Offset Correction tension - SE - SF - SG - SH - SI - SJ - SK - SL - SM - SN - RS2 - Bluetooth - ADC Filter Filtre ADC @@ -3810,85 +3397,71 @@ Extra long : bips extra longs. Heli - Invert Elevator Profondeur - Invert Aileron Aileron - Invert Collective Pas collectif - Invert Inversion - Off Aucun - 120 - 120X - 140 - 90 - Long. cyc Cyc. longitudinal - Lateral cyc Cyc. latéral - Collective Source du pas collectif - Swash Type Type de plateau cyclique - Swash Ring Limite cyclique @@ -4131,49 +3704,41 @@ Extra long : bips extra longs. LogsDialog - Companion Log Viewer Visualiseur de Log - Filename Nom de fichier - Open LogFile Ouvrir fichier de Log - Zoom - X - Y - Reset Remise à zéro - Fly sessions Sessions de vol @@ -4312,111 +3877,111 @@ Les colonnes contenant l'altitude "GAlt" et la vitesse "GSpd MainWindow - - + + Edit Edition - - + + File Fichier - + Display previous warning again at startup ? Afficher les alertes précédentes lors du prochain démarrage ? - + New release available Nouvelle version disponible - - + + Error Erreur - + Error opening file %1: %2. Erreur à l'ouverture du fichier %1: %2. - + Compilation server too busy, try later Serveur de compilation surchargé, veuillez réessayer plus tard - + Unknown server failure, try later Erreur inconnue du serveur de compilation, veuillez réessayer plus tard - + Do you want to write the firmware to the radio now ? Voulez vous transférer le firmware à la radio maintenant ? - - + + Yes Oui - - + + No Non - - + + Release Notes Notes de version - - + + Do you want to download release %1 now ? Voulez-vous télécharger la version %1 maintenant ? - + Firmware updates Mises à jour de firmware - + Current firmware does not provide release notes informations. Le firmware actuel ne contient pas de notes de version. - + Load backup from file Charger une sauvegarde à partir du fichier - + Compare models Comparer les modèles - + Show fuses dialog Afficher les réglages des fusibles - + A monochrome black icon theme Thème avec icônes monochromes noires - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -4429,7 +3994,7 @@ Voulez-vous la télécharger maintenant ? Nous recommandons de lire attentivement les notes de version à l'aide du bouton ci-dessous, celles-ci peuvent contenir des infos importantes concernant les changements effectués depuis la version précédente. - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -4446,756 +4011,661 @@ Voulez vous la télécharger maintenant ? Nous recommandons de lire attentivement les notes de version à l'aide du bouton ci-dessous, celles-ci peuvent contenir des infos importantes concernant les changements effectués depuis la version précédente. - - + + Synchronize SD Synchroniser la carte SD - + New Nouveau - + Open... Ouvrir... - + Copy Model Copier le modèle - + A monochrome white icon theme Thème avec icônes monochromes blanches - + A monochrome blue icon theme Thème avec icônes monochromes bleues - + Small Petites - + Use small toolbar icons Petites icônes de barre d'outils - + Use normal size toolbar icons Icônes de barre d'outils normales - + Normal Normales - + Use big toolbar icons Grosses icônes de barre d'outils - + Big Grandes - + Use huge toolbar icons Immenses icônes de barre d'outils - + Huge Immenses - - Czech - Tchèque - - - - Use Czech in menus - Menus en Tchèque - - - - German - Allemand - - - - Use German in menus - Menus en Allemand - - - - English - Anglais - - - - Use English in menus - Menus en Anglais - - - - French - Français - - - - Use French in menus - Menus en Français - - - - Italian - Italien - - - - Use Italian in menus - Menus en Italien - - - - Polish - Polonais - - - - Use Polish in menus - Menus en Polonais - - - - Swedish - Suédois - - - - Use Swedish in menus - Menus en Suédois - - - + List programmers... Lister les programmateurs... - + Fuses... Fusibles... - - + + Read Firmware from Radio Lire le firmware de la radio - + Read firmware from Radio Lire le firmware de la radio - + Write Firmware to Radio Transférer le firmware à la radio - + Write firmware to Radio Transférer le firmware à la radio - + Add Radio Profile Ajouter un profil de radio - + Create a new Radio Setting Profile Créér un nouveau profil de radio - + Manuals and other Documents Manuels et documents - + Open the OpenTX document page in a web browser Ouvre la page de documentation d'OpenTX dans un navigateur - + Write Models and Settings To Radio Transférer les réglages et modèles vers la radio - + Write Models and Settings to Radio Transférer les réglages et modèles vers la radio - - - + + + Companion - - + + Read Models and Settings from Radio Lire les réglages et modèles depuis la radio - + OpenTX Companion %1 - Radio: %2 - Profile: %3 OpenTX Companion %1 - Radio: %2 - Profil: %3 - + Configure Communications... Configurer les communications... - + Configure software for communicating with the Radio Configurer le programme gérant les communications avec la radio - + Write Backup to Radio Transférer une sauvegarde à la radio - + Write Backup from file to Radio Transférer une sauvegarde à la radio - + Backup Radio to File Sauvegarder la radio - + Save a complete backup file of all settings and model data in the Radio Créer une copie de sauvegarde de tous les réglages et modèles de la radio - + Contributors... Contributeurs... - + A tribute to those who have contributed to OpenTX and Companion Remerciements à tout ceux qui ont contribué à OpenTX et Companion - + SD card synchronization Synchronisation de la carte SD - + Recent Files Fichiers récents - + Recent Models+Settings Fichiers de réglages et modèles récents - + Set Icon Theme Choisir le thème d'icônes - + Set Icon Size Choisir la taille des icônes - + Write Ecrire - + A new version of Companion is available (version %1)<br>Would you like to download it? Une nouvelle version de Companion est disponible (version %1)<br>Voulez-vous la télécharger ? - + OpenTX Home Page: <a href='%1'>%1</a> Page d'accueil d'OpenTX: <a href='%1'>%1</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> Si vous trouvez ce programme utile, merci de le supporter par une <a href='%1'>donation</a> - + Show the list of radio profiles Voir la liste des profils de radio - + Ready Prêt - + Show the application's About box Afficher la fenêtre "A propos" de l'application - - + + File loaded Fichier chargé - + A new release of Companion is available, please check the OpenTX website! Une nouvelle version de Companion est disponible, veuillez vous référer au site web d'OpenTX ! - - + + Open Models and Settings file Ouvrir un fichier de réglages et modèles - - + + File saved Fichier sauvegardé - + Read Models and Settings From Radio Lire les réglages et modèles depuis la radio - + Ignore this release %1? Ignorer la version %1 ? - + Not enough flash available on this board for all the selected options Pas assez de place disponible pour les options sélectionnées - + Compilation server temporary failure, try later Erreur de compilation sur le serveur, veuillez réessayer plus tard - + Compilation error Erreur de compilation - + Invalid firmware Firmware invalide - + Invalid board Carte non valide - + Invalid language Language non valide - + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + + + + Models and Settings read Lecture des modèles et réglages - - + + This function is not yet implemented Cette fonction n'est pas implémentée pour l'instant - + Save Radio Backup to File Sauvegarder la radio - + Read Radio Firmware to File Sauvegarder le firmware de la radio - + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> Le projet OpenTX Companion a été créé à partir d'<a href='%1'>eePe</a> - + Copyright OpenTX Team - + Create a new Models and Settings file Créer un nouveau fichier de réglages et modèles - - + + Save Models and Settings file Enregistrer le fichier de réglages et modèles - + Save Enregistrer - + Save As... Enregistrer sous... - + Exit the application Quitter l'application - + Exit Quitter - + Cut Model Couper le modèle - + Cut current model to the clipboard Couper le modèle courant dans le presse-papier - + Copy current model to the clipboard Copier le modèle courant dans le presse-papier - + Paste model from clipboard Coller le modèle depuis le presse-papier - + Paste Model Coller le modèle - + + Use default system language. + + + + + Use %1 language (some translations may not be complete). + + + + Classical Classique - + The classic companion9x icon theme Thème d'icônes classique de Companion - + Yerico - + Yellow round honey sweet icon theme Thème d'icônes rondes jaunes - + Monochrome - + MonoWhite Monochrome Blanc - + MonoBlue Monochrome Bleu - + System language Langue du système - - Use system language in menus - Utiliser la langue système dans les menus - - - - Finnish - Finlandais - - - - Use Finnish in menus - Menus en Finlandais - - - - Spanish - Espagnol - - - - Use Spanish in menus - Menus en espagnol - - - - Chinese - Chinois - - - - Use Chinese in menus - Utiliser les menus Chinois - - - + About... A propos... - + Print... Imprimer... - + Print current model Imprimer le modèle courant - + Simulate... Simuler... - + Simulate current model Simuler le modèle courant - + Alt+S - + Load Backup... Ouvrir la sauvegarde... - + View Log File... Ouvrir un Log... - + Open and view log file Ouvrir et visualiser un log - + Settings... Préférences... - + Edit Settings Modifier les réglages - + Download... Télécharger... - + Download firmware and voice files Télécharger firmware et fichiers son - + Check for Updates... Vérifier les mises à jour... - + Check OpenTX and Companion updates Vérifier les mises à jour d'OpenTX et Companion - + Companion Changes... Changements de Companion... - + Show Companion change log Voir l'historique des changements de Companion - + Firmware Changes... Changements du firmware... - + Show firmware change log Voir l'historique des changements du firmware - + Compare Models... Comparer 2 modèles... - + Edit Radio Splash Image... Modifier l'écran d'accueil de la radio... - + Edit the splash image of your Radio Modifier l'écran d'accueil de la radio - + List available programmers Lister les programmateurs supportés - - + + Save As Enregistrer Sous - + Executable (*.exe) Exécutable (*.exe) - - + + No updates available at this time. Aucune mise à jour disponible. - + Unable to check for updates. Impossible de rechercher des mises à jour. - + Would you like to launch the installer? Voulez-vous lancer l'installation ? - - + + Help Aide - + Checking for updates Recherche de mises à jour - - The selected language will be used the next time you start Companion. - La langue sélectionnée sera utilisée lors du prochain lancement de Companion. - - - + The new theme will be loaded the next time you start Companion. Le nouveau thème sera utilisé lors du prochain lancement de Companion. - + The icon size will be used the next time you start Companion. La nouvelle taille d'icônes sera utilisée lors du prochain lancement de Companion. - + About Companion A propos de Companion - + Set Menu Language Choisir la langue des menus - + Settings Réglages - + Read/Write Transfert - - + + Radio Profile Profil de radio - + Show recent Models+Settings documents Voir les fichiers récents - + %2 - + New Radio Nouvelle radio @@ -5451,13 +4921,11 @@ Enregistrer les changements ? - Radio settings Réglage Radio - Simulate Tx Simulation de l'émetteur @@ -5466,49 +4934,41 @@ Enregistrer les changements ? MixerDialog - Up Haut - ADD Ajouter - OFF - Down Bas - Slow Ralenti - Delay Délai - Curve Courbe - Multiplexer This determines how mixer values are added. @@ -5526,7 +4986,6 @@ Spécifie comment les valeurs de mixage sont interprétées. - The curve used by the mix Courbe utilisée par le mixage @@ -5534,27 +4993,21 @@ Spécifie comment les valeurs de mixage sont interprétées. - - - GV VG - Yes Oui - No Non - Mixer warning. Setting this value will cause a beep to be emmitted when this value is active. Alerte de mixage. @@ -5562,31 +5015,26 @@ Si activée, signale par des bips que le mixage est actif. - 1 Beep 1 Bip - 2 Beep 2 Bips - 3 Beep 3 Bips - Multiplex Multiplexage - Dialog Dialogue @@ -5595,10 +5043,6 @@ Si activée, signale par des bips que le mixage est actif. - - - - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -5624,31 +5068,26 @@ p, li { white-space: pre-wrap; } - Offset Décalage - Source Source - Switch Interrupteur - Weight Ratio - REPLACE Remplacer @@ -5657,22 +5096,16 @@ p, li { white-space: pre-wrap; } - - - - The source for the mixer La source du mixage - MULTIPLY Multiplier - Switch used by the mix. If blank then the mix is considered to be "ON" all the time. Interrupteur utilisé par le mixage. @@ -5680,13 +5113,11 @@ Mixage actif par défaut si non-renseigné. - Warning Avertissement - Name Nom @@ -5717,19 +5148,16 @@ Mixage actif par défaut si non-renseigné. - Include Trim Inclure Trim - Flight modes Phases de vol - Include DR/Expo Inclure DR/Expo @@ -5870,7 +5298,6 @@ Mixage actif par défaut si non-renseigné. ModelEdit - Simulate Simulation @@ -5906,7 +5333,6 @@ Mixage actif par défaut si non-renseigné. - Dialog Dialogue @@ -5934,308 +5360,308 @@ Mixage actif par défaut si non-renseigné. ModelPrinter - + %1 bytes %1 octets - + CH%1 VOIE%1 - + Exponential Exponentiel - + Extra Fine Extra fin - + Fine Fin - + Medium Moyen - + Coarse Grossier - + Unknown Inconnu - + Enabled Actif - + Disabled Inactif - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) %1, Voies(%2-%3), Impulsion(%4µs), Polarité(%5) - + %1, Channels(%2-%3) %1, Voies(%2-%3) - + Receiver number(%1) No. de récepteur(%1) - + radio Protocol %1, subType %2, option value %3 radio Protocol %1, sousType %2, option %3 - + Slave/Jack Elève/Jack - + Master/SBUS Module Maître/SBUS module - + Master/CPPM Module Maître/CPPM Module - + Master/SBUS in battery compartment Maître/SBUS compartiment batterie - + Master/Jack Maître/Jack - + 90 - + 120 - + 120X - + 140 - + Rudder Dérive - + Elevator Profondeur - + Throttle Gaz - + Aileron Ailerons - + Name(%1) Nom(%1) - + Persistent Persistant - + MinuteBeep Bip minutes - + CountDown(Beeps) Cpte à rebours(bips) - + CountDown(Voice) Cpte à rebours(voix) - + CountDown(Haptic) Cpte à rebours(vibreur) - - + + Off - - - - + + + + FM%1 PV%1 - + FM%1%2 PV%1%2 - + FM%1+%2 PV%1+%2 - + [I%1] [E%1] - + Input%1 Entrée%1 - + Weight Ratio - + Switch Inter - - + + NoTrim Pas de trim - + Weight(%1) Ratio(%1) - + Switch(%1) Inter(%1) - + No DR/Expo Pas d'expo/DR - - + + Offset(%1) Décalage(%1) - + Delay(u%1:d%2) Délai(h%1:b%2) - + Slow(u%1:d%2) Ralenti(h%1:b%2) - + Warn(%1) Alerte(%1) - + Disabled in all flight modes Désactivé pour toutes les phases de vol - + Flight modes(%1) Phases de vol(%1) - + Flight mode(%1) Phase de vol(%1) - + Edge(%1, [%2:%3]) Flanc(%1, [%2:%3]) - + instant - + Sticky(%1, %2) Bistable(%1, %2) - + Timer(%1, %2) Chrono(%1, %2) - + Duration(%1s) Durée(%1s) - + Delay(%1s) Délai(%1s) - + Custom Prédéfini - + Standard @@ -6280,237 +5706,198 @@ Mixage actif par défaut si non-renseigné. Module - Failsafe Mode Mode Failsafe - Start 1ère voie - PPM delay Impulsion - Negative Négative - Positive - Polarity Polarité - Trainer Mode Mode écolage - PPM Frame Length Longueur de trame PPM - CH VOIE - Antenna Antenne - Internal Interne - Ext. + Int. Ext. + Int. - Option value - us µs - Master/Jack Maître/Jack - Slave/Jack Elève/Jack - Master/SBUS Module Maître/SBUS module - Master/CPPM Module Maître/CPPM Module - Master/SBUS in battery compartment Maître/SBUS dans compartiment batterie - Show values in: Afficher les valeurs en: - % abbreviation for percent - μs abbreviation for microseconds - ms - Channels Nb de voies - Not set Non défini - Hold Maintien - Custom Prédéfini - No Pulses Pas d'impulsions - Receiver Récepteur - Failsafe Positions Positions - Protocol Protocole - Multi Radio Protocol Protocol Multi - Receiver No. Récepteur No. - Output type Type de sortie - Open Drain - Push Pull - SubType SousType - Bind on startup Bind au démarage - Low Power Puiss Réd @@ -6816,6 +6203,49 @@ Mixage actif par défaut si non-renseigné. Alarme critique + + Multiprotocols + + + Subtype + + + + + Video TX frequency + + + + + C2500 frequency fine tune + + + + + Telemetry + + + + + Radio output power + + + + + Servo output frequency + + + + + Option value + + + + + DEFAULT + + + MultirotorPage @@ -6861,19 +6291,16 @@ Mixage actif par défaut si non-renseigné. PrintDialog - Close Fermer - Print Imprimer - Print to file Imprimer vers un fichier @@ -6897,13 +6324,11 @@ Mixage actif par défaut si non-renseigné. ProgressDialog - Flash Firmware Flasher le firmware - Close Fermer @@ -6912,13 +6337,11 @@ Mixage actif par défaut si non-renseigné. ProgressWidget - Form Formulaire - Show Details Voir les détails @@ -7408,33 +6831,33 @@ Mixage actif par défaut si non-renseigné. - - + + --- - + Rud Trim Trim Dir - + Ele Trim Trim Prf - + Thr Trim Trim Gaz - + Ail Trim Trim Ail - + Rot Enc Mol Enc @@ -7596,22 +7019,22 @@ Mixage actif par défaut si non-renseigné. Vol - + !Flight mode %1 !Phase de vol %1 - + Flight mode %1 Phase de vol %1 - + Own value Valeur indépendante - + Flight mode %1 value Flight phase %1 value Valeur de la phase de vol %1 @@ -7633,7 +7056,7 @@ Mixage actif par défaut si non-renseigné. - + -GV%1 -VG%1 @@ -7678,74 +7101,85 @@ Mixage actif par défaut si non-renseigné. Sélecteur Rotatif - + -GV%1 (%2) -VG%1 (%2) - + GV%1 (%2) VG%1 (%2) - + Yellow Jaune - + Orange Orange - + Red Rouge - + Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (non supporté) - + FrSky Sensor Hub Sensor Hub FrSky - + None Aucun - + Imperial Impérial - + Metric Métrique - + + + Uknown error during Simulator startup. + + + + + Simulator Error + + + + Data Load Error Erreur de lecture des données - + Error occurred while starting simulator. Une erreur s'est produite lors du démarrage du simulateur. - + GV%1 VG%1 @@ -7753,7 +7187,7 @@ Mixage actif par défaut si non-renseigné. - + ---- @@ -7775,7 +7209,7 @@ Mixage actif par défaut si non-renseigné. - + P1 @@ -7877,13 +7311,13 @@ Mixage actif par défaut si non-renseigné. - + P2 - + P3 @@ -8039,25 +7473,25 @@ Mixage actif par défaut si non-renseigné. - + Rud Dir - + Ele Prf - + Thr Gaz - + Ail Ail @@ -8991,69 +8425,69 @@ Mixage actif par défaut si non-renseigné. - + Warning Avertissement - + Simulator for this firmware is not yet available Le simulateur n'est pas encore disponible pour ce firmware - + Switch Inter - + Switch L'inter - + cannot be exported on this board! n'est pas supporté sur cette carte ! - + Source %1 cannot be exported on this board! La source %1 n'est pas supportée sur cette plateforme ! - + OpenTX only accepts %1 points in all curves OpenTX n'accepte que %1 points au maximum entre toutes les courbes - + OpenTx only accepts %1 points in all curves OpenTX n'accepte que %1 points au maximum entre toutes les courbes - - - - - - + + + + + + OpenTX on this board doesn't accept this function OpenTX ne supporte pas cette fonction sur cette carte - + OpenTX doesn't accept this telemetry protocol OpenTX ne supporte pas ce protocole de télémesure - - - + + + OpenTX doesn't accept this radio protocol OpenTX ne supporte pas ce protocole radio - + OpenTX doesn't allow this number of channels OpenTX ne supporte pas ce nombre de voies @@ -9102,8 +8536,8 @@ The OpenTX Team. L'équipe OpenTX. - - + + @@ -9111,12 +8545,12 @@ L'équipe OpenTX. Erreur de synchronisation - + No SD directory configured! Aucun dossier SD configuré ! - + No Radio connected! Aucune radio connectée ! @@ -9196,12 +8630,12 @@ L'équipe OpenTX. Impossible de trouver la carte SD Horus ! - + Positive - + Negative Négative @@ -9227,79 +8661,79 @@ L'équipe OpenTX. Modèles - + Select a data file Sélectionnez un fichier - + Select Data Directory Slectionnez un répertoire - + Select SD Card Image Folder Slelectionnez le répertoire image carte SD - + Available profiles: Profils disponibles: - + ID: - + Name: Nom: - + Available radios: Radio disponibles: - + WARNING: couldn't initialize SDL: %1 ATTENTION: erreur initialisation SDL: %1 - + ERROR: No simulator libraries available. ERREUR: pas de simulateur disponible. - + Radio profile ID or Name to use for simulator. Nom du profil radio pour le simulateur. - + Radio type to simulate (usually defined in profile). Type de radio à simuler (souvent défini dans le profil). - + show this help text afficher ce texte d'aide - + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] Utilisation: simulator [OPTION]... [EEPROM.BIN FICHIER OUT REPERTOIRE DE DONNER] - + Options: - + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. Profile ID: [%1]; Radio ID: [%2]; Data File: [%3] @@ -9308,22 +8742,12 @@ Data File: [%3] Fichier de Données: [%3] - + ERROR: Radio profile or simulator firmware not found. Profile ID: [%1]; Radio ID: [%2] ERREUR: Profil radio ou firmware du simulateur non trouvé Profil ID: [%1]; Radio ID: [%2] - - - ERROR: Simulator %1 not found - ERREUR: Simulateur %1 non trouvé - - - - ERROR: Failed to create simulator interface, possibly missing or bad library. - ERREUR: Impossible de créer l'interface du simulateur, bibliothèque éventuellement manquante ou mauvaise. - Error reading %1: %2 @@ -9429,7 +8853,7 @@ Profil ID: [%1]; Radio ID: [%2] %2. - + Unable to find file %1! Fichier %1 introuvable ! @@ -9615,19 +9039,16 @@ Profil ID: [%1]; Radio ID: [%2] RadioNotFoundDialog - No Radio Found Radio non détectée - <html><head/><body><p>No Radio was found!</p><p>Make sure that you hold the lower trim buttons towards the center while you turn it on.</p><p>Then connect the USB wire.</p><p><span style=" font-family:'arial,sans-serif'; font-size:13px; font-style:italic; color:#222222; background-color:#ffffff;">Note: if you have a Taranis that has not had the firmware upgraded to 2.0 then this version of Companion will not work.</span></p></body></html> <html><head/><body><p>Aucune radio détectée !</p><p>Veuillez vous assurer de maintenir les 2 trims horizontaux vers l'intérieur lors de la mise sous tension de la radio.</p><p>Ensuite connecter le câble USB.</p><p><span style=" font-family:'arial,sans-serif'; font-size:13px; font-style:italic; color:#222222; background-color:#ffffff;">Note: Cette version de Companion ne doit être utilisée pour éditer des réglages que si la version du firmware de la radio est au moins 2.0.</span></p></body></html> - OK @@ -9636,43 +9057,31 @@ Profil ID: [%1]; Radio ID: [%2] RadioOutputsWidget - - Form Formulaire - - View: Vue: - - Logical Switches Inters Logiques - - Global Variables Variables Globales - - Channel Outputs Sorties Voies - - L o g @@ -9683,8 +9092,6 @@ L - - G l o @@ -9696,8 +9103,6 @@ G - - C h a @@ -9758,187 +9163,156 @@ E Setup - Center beep Bip de centrage - OFF - Model Image Image du modèle - Exponential Exponentiel - Throttle Trim Idle Only Trim ralenti uniquement - Timer 3 Chrono 3 - Extra Fine Extra fin - Fine Fin - Medium Moyen - Coarse Grossier - Display Checklist Afficher la checklist - Timer 2 Chrono 2 - Timer 1 Chrono 1 - Never Jamais - On change Au changement - Always Toujours - Global Functions Fonctions globales - Throttle Source Source des gaz - Trim Step Pas des trims - Trims Display Affichage des trims - Warnings Avertissements - Top LCD Timer Chrono LCD supérieur - Switch Warnings Positions des interrupteurs - Pot Warnings Positions des potentiomètres - Manual Manuel - Auto - Model Modèle - Extended Limits Débattements étendus - Extended Trims Trims étendus - Throttle Warning Alerte gaz - Reverse throttle operation. If this is checked the throttle will be reversed. Idle will be forward, trim will also be reversed and the throttle warning will be reversed as well. @@ -9950,7 +9324,6 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo - Reverse Throttle Gaz inversés @@ -10170,8 +9543,6 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo SimulatedUIWidgetX7 - - Taranis X7 Simulator Simulateur Taranis X7 @@ -10392,484 +9763,220 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo Appuyer Sel.Rot. - - SimulatorDialog - - - Companion Simulator - Simulateur Companion - - - - Radio Simulator - Simulateur radio - - - - Show Help/Keymap (F1) - Afficher Aide/Raccourci (F1) - - - - Show Help/Keymap - Afficher Aide/Raccourci - - - - Keymap - Raccourci - - - - F1 - - - - - help - aide - - - - Open the Joystick Settings window (F3) - Ouvrir la boite de dialogue de la configuration du Joystick (F3) - - - - Joystick Configuration - Configuration du Joystick - - - - Joystick Config. - Configuration Joy. - - - - F3 - - - - - joystick - - - - - Open Telemetry Simulator window (F4) - Ouvrir la boite de dialogue de la télémétrie (F4) - - - - Telemetry Simulator - Simulateur de télémesure - - - - Telemetry Sim. - Simulateur Telem. - - - - F4 - - - - - telemetry - télémétrie - - - - Open Trainer Simulator window (F5) - Ouvrir le simulateur d'écolage (F5) - - - - Trainer Simulator - Simulateur d'écolage - - - - Trainer Sim. - Simulateur Écol. - - - - F5 - - - - - trainer - écolage - - - - Open Debug Console window (F6) - Ouvrir la console de débogage (F6) - - - - - Debug Console - Console de débogage - - - - F6 - - - - - debug - débogage - - - - Reload Lua Scripts (F7) - Recharger le script Lua (F7) - - - - Reload Lua Scripts - Recharger le script Lua - - - - Reload Lua - Recharger Lua - - - - F7 - - - - - reloadLua - rechargeLua - - - - Save a screenshot of the radio LCD screen (F8) - Enregistrez une capture de l'écran LCD de la radio (F8) - - - - LCD Screenshot - Capture LCD - - - - Screenshot - Capture d'écran - - - - F8 - - - - - lcdScreenshot - captureLcd - - - - Reload all radio data (F9) - Recharger les données radio (F9) - - - - Reload Radio Data - Recharger les données radio - - - - Reload Radio - Recharger la radio - - - - F9 - - - - - reloadradio - rechargerRadio - - SimulatorMainWindow - - OpenTx Simulator Simulateur OpenTX - - View Vue - - Radio Window Fenêtre radio - - Reload... Recharger... - - Tools Outils - - Toolbar Barre d'outils - - Reload Lua Scripts Recharger le script Lua - - Reload the Lua environment on the simulated radio. Recharger l'environnement Lua dans le simulateur. - - F7 - - Reload Radio Data Recharger les données radio - - Reload all radio data without restarting the simulator. Recharger les données radio sans redémarrer le simulateur. - - F9 - - Key Mapping Raccourcis clavier - - Show keyboard maping reference. Afficher les raccourcis clavier. - - F1 - - Joystick Settings Paramètres Joystick - - Open joystick configuration settings dialog. Ouvrir la boite de dialogue de la configuration du Joystick. - - F3 - - LCD Screenshot Capture LCD - - Save a screenshot of the current simulated LCD screen. Enregistrez une capture de l'écran LCD actuellement simulé. - - F8 - - Dock In Main Window Ancrer dans la fenêtre principale - - Show the radio in the main window or as a separate "floating" window. Afficher la radio dans la fenêtre principale ou comme une fenêtre "flottante" séparée. - - Menu Bar Barre de menus - - Show or hide the top menu bar. Afficher ou masquer la barre de menus. - - Alt+M - - Constrain Width Contraindre la largeur - - Set radio widget width to be a fixed size. Défini la largeur du widget radio comme étant une taille fixe. - - Constrain Height Contraindre la hauteur - - Set radio widget height to be a fixed size. Défini la hauteur du widget radio comme étant une taille fixe. - + + ERROR: Failed to create simulator interface, possibly missing or bad library. + ERREUR: Impossible de créer l'interface du simulateur, bibliothèque éventuellement manquante ou mauvaise. + + + Alt+T - + Radio Outputs Sorties de la radio - + F2 - + Telemetry Simulator Simulateur de télémesure - + F4 - + Trainer Simulator Simulateur d'écolage - + F5 - + Debug Output Fenêtre de débogage - + F6 - + Simulator Controls: Contrôles du simulateur: - + <tr><th>Key/Mouse</td><th>Action</td></tr> <tr><th>Touche/Souris</td><th>Action</td></tr> - + Simulator Help Aide du simulateur @@ -10878,29 +9985,21 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo SimulatorStartupDialog - - OpenTX Simulator - Startup Options Simulateur OpenTX - Options de démarrage - - Simulator Startup Options: Options de démarrage: - - Radio Profile: Profil Radio: - - Existing radio profiles are shown here.<br /> Create or edit profiles using the Companion application. Les profils existants sont affichés ici.<br /> @@ -10908,15 +10007,11 @@ Créer ou éditer les profils avec l'application Companion. - - Radio Type: Type de Radio: - - Existing radio simulators are shown here.<br /> The radio type specified in the selected profile is used by default. Les simulateurs radios existants sont affichés ici.<br /> @@ -10924,36 +10019,26 @@ Le type de radio choisi par défaut est celui défini dans le profil selectionn - - Data Source: Source Données: - - Data File: Fichier Données: - - Data Folder: Répertoire Données: - - SD Image Path: Répertoire Image SD: - - Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> <b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! Fichier de données utilisé (.bin/.eeprom/.otx).Un nouveau fichier avec une nouvelle image sera créé si nécessaire.<br /> @@ -10961,8 +10046,6 @@ Le type de radio choisi par défaut est celui défini dans le profil selectionn - - Select data file... Choisir le fichier de données... @@ -10970,19 +10053,11 @@ Le type de radio choisi par défaut est celui défini dans le profil selectionn - - - - - - ... - - Directory containing RADIO and MODELS folders to use.<br /> New folder(s) with default radio/model will be created here if necessary. Chemin contenant les répertoires RADIO et MODELS à utiliser.<br /> @@ -10990,15 +10065,11 @@ Un (ou plusieurs) répertoire peut être créé ici si nécessaire. - - Select data folder... Sélectionner le répertoire de données... - - Directory containing the SD card image to use.<br/> The default is configured in the chosen Radio Profile. Répertoire contenant l'image de la carte SD.<br/> @@ -11006,41 +10077,31 @@ La valeur par défaut est configurée dans le profil radio sélectionné. - - Select SD card image folder... Choisir le répertoire contenant l'image de la carte SD... - - Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. Choisir la source (Fichier/Répertoire/Image SD) du type de donnée utilisé par le simulateur. - - File Fichier - - Folder Répertoire - - SD Path Image SD - + All files (*.*) Tous les fichiers (*.*) @@ -11049,79 +10110,71 @@ La valeur par défaut est configurée dans le profil radio sélectionné.SimulatorWidget - - Companion Simulator Simulateur Companion - + Radio Simulator (%1) Simulateur Radio (%1) - + Could not determine startup data source. Impossible de déterminer les données source. - + Could not load data, possibly wrong format. Impossible de charger les données, mauvais format. - + Data Load Error Erreur de lecture des données - + Invalid startup data provided. Plese specify a proper file/path. Données de démarrage fournies non valides. Veuillez spécifier un fichier/chemin approprié. - + Simulator Startup Error Erreur de démarrage du simulateur - + Error saving data: could open file for writing: '%1' Erreur de sauvegarde des données: impossible d'écrire le fichier '%1' - + Error saving data: could not get data from simulator interface. Erreur de sauvegarde des données: impossible de récupérer les données depuis l'interface de simulation. - + An unexpected error occurred while attempting to save radio data to file '%1'. Une erreur inattendue s'est produite lors de l'enregistrement des données radio dans le fichier '%1'. - + Data Save Error Erreur de sauvegarde des données - - + Warning Avertissement - - Joystick enabled but not configured correctly - Joystick activé mais non configuré correctement - - - + Cannot open joystick, joystick disabled Impossible d'accéder au Joystick, Joystick désactivé - + Firmware %1 error: %2 Firmware %1 erreur : %2 @@ -11139,8 +10192,6 @@ La valeur par défaut est configurée dans le profil radio sélectionné. - - ... @@ -11247,219 +10298,180 @@ La valeur par défaut est configurée dans le profil radio sélectionné.Telemetry - A1 - A2 - RSSI - Alarm 1 Alarme 1 - - ---- ---- - - Yellow Jaune - - Orange Orange - - Red Rouge - Alarm 2 Alarme 2 - Serial Protocol Protocole Série - Volt source Source de mesure de tension - Current source Source de mesure de courant - Protocol Protocole - None Aucun - FrSky Sensor Hub Sensor Hub FrSky - Blades Pales - Sink Max Chute max - Climb Max Montée max - Sink Min Chute min - Climb Min Montée min - Center Silent Neutre silencieux - Vario source Source vario - Vario limits Limites vario - Altimetry Altitude - Altitude source Source de l'altitude - Volts source Source de la tension - Top Bar Barre de titre de l'écran d'accueil - mAh - A - Various Divers - Sensors Capteurs - Disable multi sensor handling Désactiver la gestion des capteurs multiples - mAh count Valeur enregistrée - FAS Offset Décalage FAS - Persistent mAh Mémorisation des mAh @@ -11468,133 +10480,107 @@ La valeur par défaut est configurée dans le profil radio sélectionné.TelemetryAnalog - Unit Unité - Max Value Valeur Max - Alarm 1 Alarme 1 - - ---- - - Yellow Jaune - - Orange - - Red Rouge - - < - - > - Alarm 2 Alarme 2 - Offset Décalage - Volts (V) Tension (V) - Amps (A) Courant (A) - Speed (m/s or ft/s) Vitesse (m/s ou ft/s) - Raw (-) Chiffres bruts (-) - Speed (km/h or miles/h) Vitesse (km/h ou miles/h) - Meters (m or ft) Distance (m ou ft) - Temp (°) Température (°) - Fuel (%) Carburant (%) - mAmps (mA) Courant (mA) @@ -11608,7 +10594,6 @@ La valeur par défaut est configurée dans le profil radio sélectionné.TelemetryCustomScreen - Custom Screen Type Type d'écran personnalisé @@ -11634,25 +10619,21 @@ La valeur par défaut est configurée dans le profil radio sélectionné. - Min - Source - Gauge Jauge - Max @@ -11761,91 +10742,76 @@ La valeur par défaut est configurée dans le profil radio sélectionné.TelemetrySensor - Form Formulaire - Custom Prédéfini - Calculated Calculé - Id - Instance - Add Addition - Average Moyenne - Min - Max - Multiply Multiplication - Totalize Totalisation - Cell Element LiPo - Consumption Consommation - Dist Distance - Cells Sensor : Capteur d'éléments: @@ -11858,236 +10824,191 @@ La valeur par défaut est configurée dans le profil radio sélectionné. - - - - - - - - --- - GPS Sensor : Capteur GPS: - Alt. Sensor : Capteur d'altitude: - Sensor : Capteur: - V - A - mA - kt - m/s - ft/s - km/h - mph - m - ft - °C - °F - % - mAh - W - mW - dBm - g - ° - Rad - mL - US fl.Oz. - Raw (-) Chiffres bruts (-) - RPM Tours/minute - Precision Précision - Ratio - Blades Pales - Offset Décalage - Multiplier Multiplicateur - Auto Offset Offset auto - Filter Filtre - Persistent Persistant - Positive - Logs @@ -12119,120 +11040,86 @@ La valeur par défaut est configurée dans le profil radio sélectionné.TelemetrySimulator - - Telemetry Simulator Simulateur de télémesure - - VFAS - - RSSI - - SWR - - Simulate Simuler - - Replay SD Log File Rejouer le fichier de Log SD - - Replay rate Vitesse - - |> - - <| - - > - - <- - - X - - 1/5x - - 5x - - No Log File Currently Loaded Pas de fichier de Log chargé - - Load Charger - - Row # Timestamp Ligne # @@ -12240,8 +11127,6 @@ Horodatage - - RxBt @@ -12249,12 +11134,6 @@ Horodatage - - - - - - V / ratio @@ -12272,175 +11151,105 @@ Horodatage - - - - - - - - - - - - - - - - - - - - - - - - - - <html><head/><body><p><br/></p></body></html> - - - - Volts - - Db dB - - Curr Courant - - Amps - - Cels Elément - - A1 - - A2 - - ASpd - - - - km/h - - A3 - - GAlt - - - - Meters Mètres - - A4 - - GSpd - - Tmp1 - - Deg. C - - Hdg - - Lat,Lon (dec.deg.) - - dd-MM-yyyy hh:mm:ss jj-MM-aaaa @@ -12448,57 +11257,41 @@ hh:mm:ss - - Degrees - - Tmp2 - - °C - - Date - - GPS - - Fuel Carburant - - % - - AccX @@ -12506,93 +11299,67 @@ hh:mm:ss - - - - - - G - - Fuel Qty Qté Carburant - - ml - - AccY - - VSpd Vitesse Verticale - - m/s - - AccZ - - Alt Altitude - - - - RPM - - When enabled, sends any non-blank values as simulated telemetry data. Transmet les valeurs non vides au simulateur. - + Log File Fichier de Log - + LOG Files (*.csv) Fichier LOG (*.csv) - + ERROR - invalid file ERREUR - fichier non valide @@ -12836,13 +11603,11 @@ hh:mm:ss Timer - Countdown Compte à rebours - Minute Call Annonces minutes @@ -12889,31 +11654,26 @@ hh:mm:ss Trainer - Form Formulaire - Mode - Input Entrée - Weight Ratio - Rud Dir @@ -12926,14 +11686,6 @@ hh:mm:ss - - - - - - - - Beeper volume 0 - Quiet. No beeps at all. @@ -12954,10 +11706,6 @@ Extra long : bips extra longs. - - - - Off @@ -12966,10 +11714,6 @@ Extra long : bips extra longs. - - - - += (Sum) += (Additionner) @@ -12978,10 +11722,6 @@ Extra long : bips extra longs. - - - - := (Replace) := (Remplacer) @@ -12990,10 +11730,6 @@ Extra long : bips extra longs. - - - - chn1 VOIE1 @@ -13002,10 +11738,6 @@ Extra long : bips extra longs. - - - - chn2 VOIE2 @@ -13014,10 +11746,6 @@ Extra long : bips extra longs. - - - - chn3 VOIE3 @@ -13026,28 +11754,21 @@ Extra long : bips extra longs. - - - - chn4 VOIE4 - Ele Prf - Thr Gaz - Ail @@ -13056,8 +11777,6 @@ Extra long : bips extra longs. TrainerSimulator - - Trainer simulator Simulateur d'écolage @@ -13096,24 +11815,44 @@ Extra long : bips extra longs. VirtualJoystickWidget - - Hold Y - Retenir Y + + Hld Y + - + + Hold Vertical stick position. + + + + Fix Y Blocage Y - + + Prevent Vertical movement of stick. + + + + Fix X Blocage X - - Hold X - Retenir X + + Prevent Horizontal movement of stick. + + + + + Hld X + + + + + Hold Horizontal stick position. + @@ -13446,14 +12185,11 @@ Extra long : bips extra longs. - - Port - List all available programmers. Lister tous les programmateurs supportés. @@ -13462,17 +12198,12 @@ Extra long : bips extra longs. - - - - The location of the AVRDUDE executable. The location of the AVRDUDE.EXE executable. Chemin d'accès de l'exécutable AVRDUDE. - DFU-Util Location Chemin de DFU-UTIL @@ -13480,15 +12211,11 @@ Extra long : bips extra longs. - - - Use this button to browse and look for the AVRDUDE executable file. Utiliser ce bouton pour parcourir à la recherche du fichier exécutable AVRDUDE.EXE. - Programmer used for communicating with the controller. Please consult the programmer's documentation and the AVRDUDE documentation to select the appropriate programmer. Programmateur utilisé pour la communication avec le contrôleur. @@ -13496,7 +12223,6 @@ Consulter la documentation du programmateur utilisé et celle d'AVRDUDE pou - Communication port to the programmer. Port de communication pour le programmateur. @@ -13504,37 +12230,31 @@ Consulter la documentation du programmateur utilisé et celle d'AVRDUDE pou - MCU Processeur - at91sam3s8-9xr - Alternate device Dispositif alternatif - Use advanced controls Utiliser les contrôles avancés - Extra Arguments Paramètres supplémentaires - Show Help Aide @@ -13542,9 +12262,6 @@ Consulter la documentation du programmateur utilisé et celle d'AVRDUDE pou - - - Browse... Parcourir... @@ -13587,15 +12304,12 @@ Consulter la documentation du programmateur utilisé et celle d'AVRDUDE pou - List Available Affiche Liste - - Extra arguments used in AVRDUDE. This can be used for providing extra information to AVRDUDE. @@ -13607,19 +12321,16 @@ A n'utiliser qu'en connaissance de cause: il n'y a pas de contrô - AVRDUDE Location Emplacement d'AVRDUDE - Show AVRDUDE help Affiche l'aide d'AVRDUDE - Programmer Configuration Configuration AVRDUDE / SAM-BA Configuration du programmateur @@ -13627,8 +12338,6 @@ A n'utiliser qu'en connaissance de cause: il n'y a pas de contrô - - Extra arguments that will be passed to AVRDUDE on every call Paramètres complémentaires passés à chaque appel d'AVRDUDE @@ -13639,29 +12348,23 @@ A n'utiliser qu'en connaissance de cause: il n'y a pas de contrô - Location of AVRDUDE executable Chemin d'accès de l'exécutable AVRDUDE - Programmer Programmateur - - CPU of your TX CPU de l'émetteur - - CPU present on your 9x radio Should be m64 for stock radios m2560 for v4.1 boards @@ -13669,27 +12372,22 @@ m2560 for v4.1 boards - SAM-BA Location Emplacement de SAM-BA - - Location of sam-ba executable Emplacement de l'exécutable SAM-BA - ARM MCU Processeur ARM - sam-ba serial port Port série de SAM-BA @@ -13698,55 +12396,42 @@ m2560 for v4.1 boards customizeSplashDialog - Transmitter Splash Screen Editor Editeur d'écran d'accueil - - Invert Inverser - - Load FW Ouvrir le firmware - - Load Pict Ouvrir l'image - - Load Profile Charger le profil - - Save Sauvegarder - - Open Splash Library Ouvrir la bibliothèque des écrans d'accueil @@ -13755,10 +12440,6 @@ m2560 for v4.1 boards - - - - ... @@ -13840,7 +12521,6 @@ m2560 for v4.1 boards downloadDialog - Downloading: Téléchargement: @@ -13864,439 +12544,186 @@ m2560 for v4.1 boards joystickDialog - - Configure Joystick Configuration du Joystick - - Ch2 VOIE2 - - - - - - - - - - - - - - - - - - - - - - - - - Not Assigned - Non assignée - - - - - - - - - - - - - - - - - - - - - - - - - - + Right Vertical Droit Vertical - - - - - - - - - - - - - - - - - - - - - - - - + Right Horizontal Droit Horizontal - - - - - - - - - - - - - - - - - - - - - - - - + Left Vertical Gauche Vertical - - - - - - - - - - - - - - - - - - - - - - - - + Left Horizontal Gauche Horizontal - - - - - - - - - - - - - - - - - - - - - - - - - P1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - P2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - P3/LS - - - - - - - - - - - - - - - - - - - - - - - - - - - - RS - - - - - - + Ch1 VOIE1 - - - + Ch4 VOIE4 - - - + Ch6 VOIE6 - - - + Ch3 VOIE3 - - - + Ch5 VOIE5 - - - + Ch7 VOIE7 - - - + Ch8 VOIE8 - - - + Instructions - - - + Enable Actif - - - + Cancel Annuler - - - + Back Précédent - - - + Start Démarrer - + Next Suivant - - - + Ok OK - + + Not Assigned + + + + + Stick + + + + + Knob/Slider %1 + + + + No joysticks found Aucun Joystick trouvé - - + Error Erreur - + Cannot open joystick. Impossible d'accéder au Joystick. - + Press the Start button to start the stick range calibration procedure. You may change the channel assignments or inversion at any time. Appuyer sur le bouton Démarrer afin de lancer la procédure de calibration. Vous pouvez changer l'ordre et la direction des VOIES à n'importe quel moment. - + Move sticks and pots in every direction making full movement Press Next when finished Bouger les manches à fond dans toutes les directions. Cliquer sur Suivant lorsque vous avez terminé - + Place sticks and pots in middle position. Press Next when done Positionner les manches et pots en positon milieu. Cliquer sur Suivant lorsque vous êtes prêts - + Map joystick channels to controls using comboboxes. Press Next when done. Assigner les voies du Joystick en utilisant les boutons. Cliquer sur Suivant lorsque vous êtes prêts. - + Check inversion checkbox to if necessary to reverse direction. Press Next when done. Inverser la direction des VOIES si nécessaire. Cliquer sur Suivant lorsque vous êtes prêts. - + Press OK to save configuration Press Cancel to abort joystick calibration without saving. Cliquer sur OK pour sauvegarder. Cliquer sur Annuler pour interrompre la calibration sans sauvegarder. - + Warning Avertissement - + Calibration not complete, save anyway? Calibration incomplète, sauvegarder tout de même ? - - - Duplicated stick assignment! - Manche déjà assigné ! - preferencesDialog From 259f76e1b534c6cb535dc38ed1f7fc8e259d488b Mon Sep 17 00:00:00 2001 From: LapinFou Date: Sat, 25 Mar 2017 13:53:05 +0100 Subject: [PATCH 038/203] Updated French translation. --- companion/src/translations/companion_fr.ts | 54 +++++++++++----------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 2713d4559..82bdd4014 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -659,12 +659,12 @@ Peut être différente de la langue du firmware files - + fichiers Radio and Models settings - + Réglages Radio et Modèles @@ -4326,7 +4326,7 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. - + Certains textes ne seront pas traduits avant le prochain redémarrage de Companion. Veuillez noter que certaines traductions peuvent ne pas être complètes. @@ -4418,12 +4418,12 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Use default system language. - + Utiliser le langage système par défaut. Use %1 language (some translations may not be complete). - + Utiliser la langue %1 (certaines traductions peuvent être incomplètes). @@ -6208,42 +6208,42 @@ Mixage actif par défaut si non-renseigné. Subtype - + Sous-type Video TX frequency - + Fréquence vidéo TX C2500 frequency fine tune - + Affiner fréquence C2500 Telemetry - + Télémetrie Radio output power - + Puissance de sortie Servo output frequency - + Taux rafraichissement servo Option value - + Valeur optionnelle DEFAULT - + DÉFAUT @@ -7159,12 +7159,12 @@ Mixage actif par défaut si non-renseigné. Uknown error during Simulator startup. - + Erreur inconnue pendant le démarrage du simulateur. Simulator Error - + Erreur Simulateur @@ -9918,7 +9918,7 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo ERROR: Failed to create simulator interface, possibly missing or bad library. - ERREUR: Impossible de créer l'interface du simulateur, bibliothèque éventuellement manquante ou mauvaise. + ERREUR: Impossible de créer l'interface du simulateur, bibliothèque éventuellement manquante ou mauvaise. @@ -11817,42 +11817,42 @@ Extra long : bips extra longs. Hld Y - + Maintien Y Hold Vertical stick position. - + Maintien la position verticale du manche. Fix Y - Blocage Y + Bloque Y Prevent Vertical movement of stick. - + Empêche le mouvement vertical du manche. Fix X - Blocage X + Bloque X Prevent Horizontal movement of stick. - + Empêche le mouvement horizontal du manche. Hld X - + Maintien X Hold Horizontal stick position. - + Maintien la position horizontale du manche. @@ -12645,17 +12645,17 @@ m2560 for v4.1 boards Not Assigned - + Non assigné Stick - + Manche Knob/Slider %1 - + Potar/Slider %1 From 701125b0cac61d597836bc87d092022cf21edaa8 Mon Sep 17 00:00:00 2001 From: mhotar Date: Sat, 25 Mar 2017 15:11:29 +0100 Subject: [PATCH 039/203] Images converted to plain SVG #4677 --- .../src/images/simulator/icons/svg/rf_out.svg | 65 +++++------------ .../simulator/icons/svg/word_wrap-on.svg | 57 ++++----------- .../images/simulator/icons/svg/word_wrap.svg | 71 ++++++------------- 3 files changed, 49 insertions(+), 144 deletions(-) diff --git a/companion/src/images/simulator/icons/svg/rf_out.svg b/companion/src/images/simulator/icons/svg/rf_out.svg index 81fc7f9d6..cb0fe3955 100644 --- a/companion/src/images/simulator/icons/svg/rf_out.svg +++ b/companion/src/images/simulator/icons/svg/rf_out.svg @@ -1,44 +1,17 @@ - - + id="svg5332" + viewBox="0 0 64.000001 64.000001" + height="64" + width="64"> - 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- - + height="64" + width="64" + version="1.1"> - - - - + + + + From 5e55a3f5d30df6fa2a29be257fda73595fabf296 Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Sat, 25 Mar 2017 20:37:05 +0100 Subject: [PATCH 040/203] Lua killEvents() docs update --- radio/src/lua/api_general.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/radio/src/lua/api_general.cpp b/radio/src/lua/api_general.cpp index 1d69b2568..f9b933c75 100644 --- a/radio/src/lua/api_general.cpp +++ b/radio/src/lua/api_general.cpp @@ -796,13 +796,12 @@ static int luaPlayHaptic(lua_State * L) /*luadoc @function killEvents(key) -Stops key state machine. +Stops key state machine. See [Key Events](../key_events.md) for the detailed description. -@param key (number) key to be killed, can also include event type (only key part is used) +@param key (number) key to be killed, can also include event type (only the key part is used) @status current Introduced in 2.0.0 -TODO table of events/masks */ static int luaKillEvents(lua_State * L) { From 8c52e57c4654daba15f9664b635a484b9429cf47 Mon Sep 17 00:00:00 2001 From: 3djc Date: Sun, 26 Mar 2017 13:28:12 +0200 Subject: [PATCH 041/203] Eeprom upgrade checks tools --- tools/eeprom_upgd_check/check.lua | 29 +++++++++++++++++++ tools/eeprom_upgd_check/create.lua | 14 +++++++++ tools/eeprom_upgd_check/readme.txt | 46 ++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+) create mode 100644 tools/eeprom_upgd_check/check.lua create mode 100644 tools/eeprom_upgd_check/create.lua create mode 100644 tools/eeprom_upgd_check/readme.txt diff --git a/tools/eeprom_upgd_check/check.lua b/tools/eeprom_upgd_check/check.lua new file mode 100644 index 000000000..6a6ee194a --- /dev/null +++ b/tools/eeprom_upgd_check/check.lua @@ -0,0 +1,29 @@ +local function checktable(actual, reference) + for k, v in pairs( actual ) do + if v == reference[k] then + print("OK ", k, v, reference[k]) + else + print("ISSUE ", k, v, reference[k]) + end + end +end + +local function run(event) + inputt= {name = "In1", source = 1, weight = 50, offset = 10, switch = 3} + mixt= {name = "Mix1", source = 1, weight = 50, offset = 10, curveType = 1, curveValue = 50, flightModes = 3, delayUp = 5, speedDown = 5, speedUp = 2, delayDown = 5, mixWarn = 1 , carryTrim = true , multiplex = 1, switch = 3} + outputt = {name = "Out1", min = -800, max = 800, offset = 10, ppmCenter = 10, symetrical = 1, revert = 1, switch = 3} + timert = {mode = 4, start = 0, countdownBeep = 2, persistent = 1, minuteBeep = true, value = 10 } + lst = {func = 2, v1 = 2, v2 = 2, v3 = 2, duration = 3, delay = 2, ["and"] = 2} + input = model.getInput(4,0) + mix = model.getMix(4,0) + output = model.getOutput(4) + ls = model.getLogicalSwitch(0) + timer = model.getTimer(0) + checktable(input,inputt) + checktable(mix, mixt) + checktable(output, outputt) + checktable(ls, lst) + checktable(timer, timert) + return 2 +end +return {run=run} diff --git a/tools/eeprom_upgd_check/create.lua b/tools/eeprom_upgd_check/create.lua new file mode 100644 index 000000000..bbeff9ca9 --- /dev/null +++ b/tools/eeprom_upgd_check/create.lua @@ -0,0 +1,14 @@ +local function run(event) + inputt= {name = "In1", source = 1, weight = 50, offset = 10, switch = 3} + mixt= {name = "Mix1", source = 1, weight = 50, offset = 10, curveType = 1, curveValue = 50, flightModes = 3, delayUp = 5, speedDown = 5, speedUp = 2, delayDown = 5, mixWarn = 1 , carryTrim = true , multiplex = 1, switch = 3} + outputt = {name = "Out1", min = -800, max = 800, offset = 10, ppmCenter = 10, symetrical = 1, revert = 1, switch = 3} + timert = {mode = 4, start = 0, countdownBeep = 2, persistent = 1, minuteBeep = true, value = 10 } + lst = {func = 2, v1 = 2, v2 = 2, v3 = 2, duration = 3, delay = 2, ["and"] = 2} + model.insertInput(4,0,inputt) + model.insertMix(4,0,mixt) + model.setOutput(4, outputt) + model.setLogicalSwitch(0, lst) + model.setTimer(0, timert) + return 2 +end +return {run=run} diff --git a/tools/eeprom_upgd_check/readme.txt b/tools/eeprom_upgd_check/readme.txt new file mode 100644 index 000000000..822cd4776 --- /dev/null +++ b/tools/eeprom_upgd_check/readme.txt @@ -0,0 +1,46 @@ +Use this two scripts to check eeprom upgrade on lua capale radio. +Using create.lua on source version will create a predefined set of input, mixer, switche, timer and logical swictch +Perform the eeprom upgrade +On the target version, run check.lua, the debug output will give something like : +OK source 1 1 +OK switch 3 3 +OK offset 10 10 +OK weight 50 50 +OK name In1 In1 +OK weight 50 50 +OK speedDown 5 5 +OK curveValue 50 50 +OK speedUp 2 2 +OK delayDown 5 5 +OK carryTrim true true +OK mixWarn 1 1 +OK flightModes 3 3 +OK offset 10 10 +OK switch 3 3 +OK source 1 1 +OK curveType 1 1 +OK delayUp 5 5 +OK name Mix1 Mix1 +OK multiplex 1 1 +OK min -800 -800 +OK ppmCenter 10 10 +OK symetrical 1 1 +OK offset 10 10 +OK revert 1 1 +OK max 800 800 +OK name Out1 Out1 +OK v1 2 2 +OK delay 2 2 +OK func 2 2 +OK v3 2 2 +OK and 2 2 +OK v2 2 2 +OK duration 3 3 +OK minuteBeep true true +ISSUE value 43 10 +OK persistent 1 1 +OK start 0 0 +OK countdownBeep 2 2 +OK mode 4 4 + +The issue on 'value' for timer is normal and should be expected, but it should be the only one if eeprom upgrade was ok From 2bbb704c3e52610b4be194d112428ecda522a8ad Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Sun, 26 Mar 2017 19:16:08 +0200 Subject: [PATCH 042/203] Fixed: AudioQueue::playTone() with 0 frequency caused radio reboot (divide by zero) --- radio/src/audio_arm.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/radio/src/audio_arm.cpp b/radio/src/audio_arm.cpp index 305ecac3d..d5023ad2e 100644 --- a/radio/src/audio_arm.cpp +++ b/radio/src/audio_arm.cpp @@ -833,9 +833,7 @@ void AudioQueue::playTone(uint16_t freq, uint16_t len, uint16_t pause, uint8_t f CoEnterMutexSection(audioMutex); - if (freq && freq < BEEP_MIN_FREQ) { - freq = BEEP_MIN_FREQ; - } + freq = limit(BEEP_MIN_FREQ, freq, BEEP_MAX_FREQ); if (flags & PLAY_BACKGROUND) { varioContext.setFragment(freq, len, pause, 0, 0, (flags & PLAY_NOW)); From fc5835a327ab3ce59880b29cd516b517750b1ee1 Mon Sep 17 00:00:00 2001 From: Sebastien Charpentier Date: Sun, 26 Mar 2017 19:51:58 +0200 Subject: [PATCH 043/203] Added some tiny cosmetic changes in order to help user to make the link between Companion and the radio menu. (#4694) --- companion/src/translations/companion_fr.ts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 82bdd4014..100fcccd8 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -4940,7 +4940,7 @@ Enregistrer les changements ? ADD - Ajouter + += Ajouter @@ -5089,7 +5089,7 @@ p, li { white-space: pre-wrap; } REPLACE - Remplacer + := Remplacer @@ -5102,7 +5102,7 @@ p, li { white-space: pre-wrap; } MULTIPLY - Multiplier + *= Multiplier @@ -6772,7 +6772,7 @@ Mixage actif par défaut si non-renseigné. played once, not during startup - Lu une fois, mais pas à la mise en route + !1x Lu une fois, mais pas à la mise en route @@ -6919,7 +6919,7 @@ Mixage actif par défaut si non-renseigné. No repeat - Pas de rép. + 1x Lu une fois @@ -6986,7 +6986,7 @@ Mixage actif par défaut si non-renseigné. Played once, not during startup - Lu une fois, mais pas à la mise en route + 1x Lu une fois, mais pas à la mise en route From bed9f56b9d12ef5d84163826d53b3e743cc896a0 Mon Sep 17 00:00:00 2001 From: 3djc Date: Sun, 26 Mar 2017 20:04:49 +0200 Subject: [PATCH 044/203] Fix non overlapping text (#4691) --- radio/src/gui/common/stdlcd/model_mixes.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/gui/common/stdlcd/model_mixes.cpp b/radio/src/gui/common/stdlcd/model_mixes.cpp index 40c8ad641..37e884e40 100644 --- a/radio/src/gui/common/stdlcd/model_mixes.cpp +++ b/radio/src/gui/common/stdlcd/model_mixes.cpp @@ -231,7 +231,7 @@ void displayMixInfos(coord_t y, MixData * md) void displayMixLine(coord_t y, MixData * md, bool active) { if(active && md->name[0]) { - lcdDrawSizedText(FW*sizeof(TR_MIXER), 0, md->name, sizeof(md->name), ZCHAR); + lcdDrawSizedText(FW*sizeof(TR_MIXER)+FW/2, 0, md->name, sizeof(md->name), ZCHAR); if (!md->flightModes || ((md->curve.value || md->swtch) && ((get_tmr10ms() / 200) & 1))) displayMixInfos(y, md); else From 1d213099357211982074d61b74d9967f3902c190 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sun, 26 Mar 2017 14:06:55 -0400 Subject: [PATCH 045/203] [Companion] Speed up loading of model editor (#4689) * [Companion] Speed up loading of model editor by only displaying Logical Switches and Custom Functions which are actually used. * [Companion[ Constrain size of Repeat options combo box. * Missing indent. --- companion/src/modeledit/customfunctions.cpp | 301 +++++++++++--------- companion/src/modeledit/logicalswitches.cpp | 156 +++++----- companion/src/modeledit/logicalswitches.h | 2 +- 3 files changed, 248 insertions(+), 211 deletions(-) diff --git a/companion/src/modeledit/customfunctions.cpp b/companion/src/modeledit/customfunctions.cpp index fe5251a2c..36849cd18 100644 --- a/companion/src/modeledit/customfunctions.cpp +++ b/companion/src/modeledit/customfunctions.cpp @@ -29,6 +29,8 @@ RepeatComboBox::RepeatComboBox(QWidget *parent, int & repeatParam): unsigned int step = IS_ARM(getCurrentBoard()) ? 1 : 10; int value = repeatParam/step; + setSizePolicy(QSizePolicy::Maximum, QSizePolicy::Fixed); + if (step == 1) { addItem(QObject::tr("Played once, not during startup"), -1); value++; @@ -355,128 +357,149 @@ void CustomFunctionsPanel::onChildModified() void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) { CustomFunctionData & cfn = functions[i]; - AssignFunc func = (AssignFunc)fswtchFunc[i]->itemData(fswtchFunc[i]->currentIndex()).toInt(); + AssignFunc func = (AssignFunc)fswtchFunc[i]->currentData().toInt(); unsigned int widgetsMask = 0; if (modified) { - cfn.swtch = RawSwitch(fswtchSwtch[i]->itemData(fswtchSwtch[i]->currentIndex()).toInt()); + cfn.swtch = RawSwitch(fswtchSwtch[i]->currentData().toInt()); cfn.func = func; cfn.enabled = fswtchEnable[i]->isChecked(); cfn.adjustMode = (AssignFunc)fswtchGVmode[i]->currentIndex(); } - if (func>=FuncOverrideCH1 && func<=FuncOverrideCH32) { - if (model) { - int channelsMax = model->getChannelsMax(true); - fswtchParam[i]->setDecimals(0); - fswtchParam[i]->setSingleStep(1); - fswtchParam[i]->setMinimum(-channelsMax); - fswtchParam[i]->setMaximum(channelsMax); - if (modified) { - cfn.param = fswtchParam[i]->value(); - } - fswtchParam[i]->setValue(cfn.param); - widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM + CUSTOM_FUNCTION_ENABLE; - } - } - else if (func==FuncLogs) { - fswtchParam[i]->setDecimals(1); - fswtchParam[i]->setMinimum(0); - fswtchParam[i]->setMaximum(25.5); - fswtchParam[i]->setSingleStep(0.1); - if (modified) cfn.param = fswtchParam[i]->value()*10.0; - fswtchParam[i]->setValue(cfn.param/10.0); - widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM; - } - else if (func>=FuncAdjustGV1 && func<=FuncAdjustGVLast) { - if (modified) cfn.adjustMode = fswtchGVmode[i]->currentIndex(); - widgetsMask |= CUSTOM_FUNCTION_GV_MODE | CUSTOM_FUNCTION_ENABLE; - if (cfn.adjustMode==FUNC_ADJUST_GVAR_CONSTANT || cfn.adjustMode==FUNC_ADJUST_GVAR_INCDEC) { - if (modified) cfn.param = fswtchParam[i]->value(); - fswtchParam[i]->setDecimals(0); - fswtchParam[i]->setSingleStep(1); - if (IS_ARM(getCurrentBoard())) { - fswtchParam[i]->setMinimum(-500); - fswtchParam[i]->setMaximum(500); - } - else { - fswtchParam[i]->setMinimum(-125); - fswtchParam[i]->setMaximum(125); - } - fswtchParam[i]->setValue(cfn.param); - widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM; - } - else { - if (modified) cfn.param = fswtchParamT[i]->itemData(fswtchParamT[i]->currentIndex()).toInt(); - populateFuncParamCB(fswtchParamT[i], func, cfn.param, cfn.adjustMode); - widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM; - } - } - else if (func==FuncReset) { - if (modified) cfn.param = fswtchParamT[i]->itemData(fswtchParamT[i]->currentIndex()).toInt(); - populateFuncParamCB(fswtchParamT[i], func, cfn.param); - widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM | CUSTOM_FUNCTION_ENABLE; - } - else if (func>=FuncSetTimer1 && func<=FuncSetTimer3) { - if (modified) cfn.param = QTimeS(fswtchParamTime[i]->time()).seconds(); - fswtchParamTime[i]->setMinimumTime(QTime(0, 0, 0)); - fswtchParamTime[i]->setMaximumTime(firmware->getMaxTimerStart()); - fswtchParamTime[i]->setTime(QTimeS(cfn.param)); - widgetsMask |= CUSTOM_FUNCTION_TIME_PARAM + CUSTOM_FUNCTION_ENABLE; - } - else if (func>=FuncSetFailsafeInternalModule && func<=FuncBindExternalModule) { - widgetsMask |= CUSTOM_FUNCTION_ENABLE; - } - else if (func==FuncVolume) { - if (modified) cfn.param = fswtchParamT[i]->itemData(fswtchParamT[i]->currentIndex()).toInt(); - populateFuncParamCB(fswtchParamT[i], func, cfn.param); - widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM + CUSTOM_FUNCTION_ENABLE; - } - else if (func==FuncPlaySound || func==FuncPlayHaptic || func==FuncPlayValue || func==FuncPlayPrompt || func==FuncPlayBoth || func==FuncBackgroundMusic) { - if (func != FuncBackgroundMusic) { - widgetsMask |= CUSTOM_FUNCTION_REPEAT; - fswtchRepeat[i]->update(); - } - if (func==FuncPlayValue) { - if (modified) cfn.param = fswtchParamT[i]->itemData(fswtchParamT[i]->currentIndex()).toInt(); - populateFuncParamCB(fswtchParamT[i], func, cfn.param); - widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM + CUSTOM_FUNCTION_REPEAT; - } - else if (func==FuncPlayPrompt || func==FuncPlayBoth) { - if (firmware->getCapability(VoicesAsNumbers)) { + if (cfn.swtch.toValue()){ + + if (func>=FuncOverrideCH1 && func<=FuncOverrideCH32) { + if (model) { + int channelsMax = model->getChannelsMax(true); fswtchParam[i]->setDecimals(0); fswtchParam[i]->setSingleStep(1); - fswtchParam[i]->setMinimum(0); - if (func==FuncPlayPrompt) { - widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM + CUSTOM_FUNCTION_REPEAT + CUSTOM_FUNCTION_GV_TOOGLE; - } - else { - widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM + CUSTOM_FUNCTION_REPEAT; - fswtchParamGV[i]->setChecked(false); - } - fswtchParam[i]->setMaximum(func==FuncPlayBoth ? 254 : 255); + fswtchParam[i]->setMinimum(-channelsMax); + fswtchParam[i]->setMaximum(channelsMax); if (modified) { - if (fswtchParamGV[i]->isChecked()) { - fswtchParam[i]->setMinimum(1); - cfn.param = std::min(fswtchParam[i]->value(),5.0)+(fswtchParamGV[i]->isChecked() ? 250 : 0); - } - else { - cfn.param = fswtchParam[i]->value(); - } + cfn.param = fswtchParam[i]->value(); } - if (cfn.param>250 && (func!=FuncPlayBoth)) { - fswtchParamGV[i]->setChecked(true); - fswtchParam[i]->setValue(cfn.param-250); - fswtchParam[i]->setMaximum(5); + fswtchParam[i]->setValue(cfn.param); + widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM + CUSTOM_FUNCTION_ENABLE; + } + } + else if (func==FuncLogs) { + fswtchParam[i]->setDecimals(1); + fswtchParam[i]->setMinimum(0); + fswtchParam[i]->setMaximum(25.5); + fswtchParam[i]->setSingleStep(0.1); + if (modified) + cfn.param = fswtchParam[i]->value()*10.0; + fswtchParam[i]->setValue(cfn.param/10.0); + widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM; + } + else if (func>=FuncAdjustGV1 && func<=FuncAdjustGVLast) { + if (modified) + cfn.adjustMode = fswtchGVmode[i]->currentIndex(); + widgetsMask |= CUSTOM_FUNCTION_GV_MODE | CUSTOM_FUNCTION_ENABLE; + if (cfn.adjustMode==FUNC_ADJUST_GVAR_CONSTANT || cfn.adjustMode==FUNC_ADJUST_GVAR_INCDEC) { + if (modified) + cfn.param = fswtchParam[i]->value(); + fswtchParam[i]->setDecimals(0); + fswtchParam[i]->setSingleStep(1); + if (IS_ARM(getCurrentBoard())) { + fswtchParam[i]->setMinimum(-500); + fswtchParam[i]->setMaximum(500); } else { - fswtchParamGV[i]->setChecked(false); - fswtchParam[i]->setValue(cfn.param); + fswtchParam[i]->setMinimum(-125); + fswtchParam[i]->setMaximum(125); } - if (cfn.param < 251) - widgetsMask |= CUSTOM_FUNCTION_PLAY; + fswtchParam[i]->setValue(cfn.param); + widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM; } else { + if (modified) + cfn.param = fswtchParamT[i]->currentData().toInt(); + populateFuncParamCB(fswtchParamT[i], func, cfn.param, cfn.adjustMode); + widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM; + } + } + else if (func==FuncReset) { + if (modified) + cfn.param = fswtchParamT[i]->currentData().toInt(); + populateFuncParamCB(fswtchParamT[i], func, cfn.param); + widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM | CUSTOM_FUNCTION_ENABLE; + } + else if (func>=FuncSetTimer1 && func<=FuncSetTimer3) { + if (modified) + cfn.param = QTimeS(fswtchParamTime[i]->time()).seconds(); + fswtchParamTime[i]->setMinimumTime(QTime(0, 0, 0)); + fswtchParamTime[i]->setMaximumTime(firmware->getMaxTimerStart()); + fswtchParamTime[i]->setTime(QTimeS(cfn.param)); + widgetsMask |= CUSTOM_FUNCTION_TIME_PARAM + CUSTOM_FUNCTION_ENABLE; + } + else if (func>=FuncSetFailsafeInternalModule && func<=FuncBindExternalModule) { + widgetsMask |= CUSTOM_FUNCTION_ENABLE; + } + else if (func==FuncVolume) { + if (modified) + cfn.param = fswtchParamT[i]->currentData().toInt(); + populateFuncParamCB(fswtchParamT[i], func, cfn.param); + widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM + CUSTOM_FUNCTION_ENABLE; + } + else if (func==FuncPlaySound || func==FuncPlayHaptic || func==FuncPlayValue || func==FuncPlayPrompt || func==FuncPlayBoth || func==FuncBackgroundMusic) { + if (func != FuncBackgroundMusic) { + widgetsMask |= CUSTOM_FUNCTION_REPEAT; + fswtchRepeat[i]->update(); + } + if (func==FuncPlayValue) { + if (modified) + cfn.param = fswtchParamT[i]->currentData().toInt(); + populateFuncParamCB(fswtchParamT[i], func, cfn.param); + widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM + CUSTOM_FUNCTION_REPEAT; + } + else if (func==FuncPlayPrompt || func==FuncPlayBoth) { + if (firmware->getCapability(VoicesAsNumbers)) { + fswtchParam[i]->setDecimals(0); + fswtchParam[i]->setSingleStep(1); + fswtchParam[i]->setMinimum(0); + if (func==FuncPlayPrompt) { + widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM + CUSTOM_FUNCTION_REPEAT + CUSTOM_FUNCTION_GV_TOOGLE; + } + else { + widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM + CUSTOM_FUNCTION_REPEAT; + fswtchParamGV[i]->setChecked(false); + } + fswtchParam[i]->setMaximum(func==FuncPlayBoth ? 254 : 255); + if (modified) { + if (fswtchParamGV[i]->isChecked()) { + fswtchParam[i]->setMinimum(1); + cfn.param = std::min(fswtchParam[i]->value(),5.0)+(fswtchParamGV[i]->isChecked() ? 250 : 0); + } + else { + cfn.param = fswtchParam[i]->value(); + } + } + if (cfn.param>250 && (func!=FuncPlayBoth)) { + fswtchParamGV[i]->setChecked(true); + fswtchParam[i]->setValue(cfn.param-250); + fswtchParam[i]->setMaximum(5); + } + else { + fswtchParamGV[i]->setChecked(false); + fswtchParam[i]->setValue(cfn.param); + } + if (cfn.param < 251) + widgetsMask |= CUSTOM_FUNCTION_PLAY; + } + else { + widgetsMask |= CUSTOM_FUNCTION_FILE_PARAM; + if (modified) { + getFileComboBoxValue(fswtchParamArmT[i], cfn.paramarm, firmware->getCapability(VoicesMaxLength)); + } + populateFileComboBox(fswtchParamArmT[i], tracksSet, cfn.paramarm); + if (fswtchParamArmT[i]->currentText() != "----") { + widgetsMask |= CUSTOM_FUNCTION_PLAY; + } + } + } + else if (func==FuncBackgroundMusic) { widgetsMask |= CUSTOM_FUNCTION_FILE_PARAM; if (modified) { getFileComboBoxValue(fswtchParamArmT[i], cfn.paramarm, firmware->getCapability(VoicesMaxLength)); @@ -486,50 +509,46 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) widgetsMask |= CUSTOM_FUNCTION_PLAY; } } + else if (func==FuncPlaySound) { + if (modified) + cfn.param = (uint8_t)fswtchParamT[i]->currentIndex(); + populateFuncParamCB(fswtchParamT[i], func, cfn.param); + widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM; + } + else if (func==FuncPlayHaptic) { + if (modified) + cfn.param = (uint8_t)fswtchParamT[i]->currentIndex(); + populateFuncParamCB(fswtchParamT[i], func, cfn.param); + widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM; + } } - else if (func==FuncBackgroundMusic) { + else if (func==FuncPlayScript) { widgetsMask |= CUSTOM_FUNCTION_FILE_PARAM; if (modified) { - getFileComboBoxValue(fswtchParamArmT[i], cfn.paramarm, firmware->getCapability(VoicesMaxLength)); + getFileComboBoxValue(fswtchParamArmT[i], cfn.paramarm, 8); } - populateFileComboBox(fswtchParamArmT[i], tracksSet, cfn.paramarm); - if (fswtchParamArmT[i]->currentText() != "----") { - widgetsMask |= CUSTOM_FUNCTION_PLAY; + populateFileComboBox(fswtchParamArmT[i], scriptsSet, cfn.paramarm); + } + else if (func==FuncBacklight && IS_TARANIS_PLUS(getCurrentBoard())) { + if (modified) + cfn.param = (uint8_t)fswtchBLcolor[i]->value(); + fswtchBLcolor[i]->setValue(cfn.param); + widgetsMask |= CUSTOM_FUNCTION_BL_COLOR; + } + else { + if (modified) + cfn.param = fswtchParam[i]->value(); + fswtchParam[i]->setDecimals(0); + fswtchParam[i]->setSingleStep(1); + fswtchParam[i]->setValue(cfn.param); + if (func <= FuncInstantTrim) { + widgetsMask |= CUSTOM_FUNCTION_ENABLE; } } - else if (func==FuncPlaySound) { - if (modified) cfn.param = (uint8_t)fswtchParamT[i]->currentIndex(); - populateFuncParamCB(fswtchParamT[i], func, cfn.param); - widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM; - } - else if (func==FuncPlayHaptic) { - if (modified) cfn.param = (uint8_t)fswtchParamT[i]->currentIndex(); - populateFuncParamCB(fswtchParamT[i], func, cfn.param); - widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM; - } - } - else if (func==FuncPlayScript) { - widgetsMask |= CUSTOM_FUNCTION_FILE_PARAM; - if (modified) { - getFileComboBoxValue(fswtchParamArmT[i], cfn.paramarm, 8); - } - populateFileComboBox(fswtchParamArmT[i], scriptsSet, cfn.paramarm); - } - else if (func==FuncBacklight && IS_TARANIS_PLUS(getCurrentBoard())) { - if (modified) cfn.param = (uint8_t)fswtchBLcolor[i]->value(); - fswtchBLcolor[i]->setValue(cfn.param); - widgetsMask |= CUSTOM_FUNCTION_BL_COLOR; - } - else { - if (modified) cfn.param = fswtchParam[i]->value(); - fswtchParam[i]->setDecimals(0); - fswtchParam[i]->setSingleStep(1); - fswtchParam[i]->setValue(cfn.param); - if (func <= FuncInstantTrim) { - widgetsMask |= CUSTOM_FUNCTION_ENABLE; - } + } + fswtchFunc[i]->setVisible(widgetsMask); fswtchParam[i]->setVisible(widgetsMask & CUSTOM_FUNCTION_NUMERIC_PARAM); fswtchParamTime[i]->setVisible(widgetsMask & CUSTOM_FUNCTION_TIME_PARAM); fswtchParamGV[i]->setVisible(widgetsMask & CUSTOM_FUNCTION_GV_TOOGLE); diff --git a/companion/src/modeledit/logicalswitches.cpp b/companion/src/modeledit/logicalswitches.cpp index 0e81ae84e..44629ca18 100644 --- a/companion/src/modeledit/logicalswitches.cpp +++ b/companion/src/modeledit/logicalswitches.cpp @@ -214,7 +214,7 @@ void LogicalSwitchesPanel::edited() if (oldFuncFamily != newFuncFamily) { model->logicalSw[i].clear(); - model->logicalSw[i].func = csw[i]->itemData(csw[i]->currentIndex()).toInt(); + model->logicalSw[i].func = csw[i]->currentData().toInt(); if (newFuncFamily == LS_FAMILY_TIMER) { model->logicalSw[i].val1 = -119; model->logicalSw[i].val2 = -119; @@ -249,7 +249,7 @@ void LogicalSwitchesPanel::edited() updateTimerParam(cswitchOffset[i], model->logicalSw[i].val2, 0.1); break; case LS_FAMILY_EDGE: - cswitchOffset2[i]->setSpecialValueText(tr("(instant)")); + cswitchOffset2[i]->setSpecialValueText(" " + tr("(instant)")); if (sender() == cswitchOffset[i]) { model->logicalSw[i].val2 = TimToVal(cswitchOffset[i]->value()); updateTimerParam(cswitchOffset[i], model->logicalSw[i].val2, 0.0); @@ -259,7 +259,7 @@ void LogicalSwitchesPanel::edited() } updateTimerParam(cswitchOffset2[i], model->logicalSw[i].val2+model->logicalSw[i].val3, ValToTim(TimToVal(cswitchOffset[i]->value())-1)); if (model->logicalSw[i].val3 == 0) { - cswitchOffset2[i]->setSuffix("(infinite)"); + cswitchOffset2[i]->setSuffix(" " + tr("(infinite)")); } else { cswitchOffset2[i]->setSuffix(""); @@ -297,74 +297,83 @@ void LogicalSwitchesPanel::updateTimerParam(QDoubleSpinBox *sb, int timer, doubl #define VALUE3_VISIBLE 0x10 #define VALUE_TO_VISIBLE 0x20 #define DELAY_ENABLED 0x40 +#define DURATION_ENABLED 0x80 void LogicalSwitchesPanel::setSwitchWidgetVisibility(int i) { lock = true; + unsigned int mask; - unsigned int mask = DELAY_ENABLED; - RawSource source = RawSource(model->logicalSw[i].val1); - RawSourceRange range = source.getRange(model, generalSettings, model->logicalSw[i].getRangeFlags()); + if (!model->logicalSw[i].func) { + mask = 0; + } + else { + mask = DELAY_ENABLED | DURATION_ENABLED; - switch (model->logicalSw[i].getFunctionFamily()) - { - case LS_FAMILY_VOFS: - mask |= SOURCE1_VISIBLE; - populateSourceCB(cswitchSource1[i], source, generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | POPULATE_TELEMETRY | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0)); - cswitchOffset[i]->setDecimals(range.decimals); - cswitchOffset[i]->setSingleStep(range.step); - if (source.isTimeBased()) { - mask |= VALUE_TO_VISIBLE; - int maxTime = round(range.max); - int value = round(range.step*model->logicalSw[i].val2 + range.offset); - cswitchTOffset[i]->setMaximumTime(QTimeS(maxTime)); - QString format = (maxTime>=3600) ? "hh:mm:ss" : "mm:ss"; - if (!range.unit.isEmpty()) - format += QString("' [%1]'").arg(range.unit); - cswitchTOffset[i]->setDisplayFormat(format); - cswitchTOffset[i]->setTime(QTimeS(value)); + switch (model->logicalSw[i].getFunctionFamily()) + { + case LS_FAMILY_VOFS: + { + mask |= SOURCE1_VISIBLE; + RawSource source = RawSource(model->logicalSw[i].val1); + RawSourceRange range = source.getRange(model, generalSettings, model->logicalSw[i].getRangeFlags()); + populateSourceCB(cswitchSource1[i], source, generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | POPULATE_TELEMETRY | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0)); + cswitchOffset[i]->setDecimals(range.decimals); + cswitchOffset[i]->setSingleStep(range.step); + if (source.isTimeBased()) { + mask |= VALUE_TO_VISIBLE; + int maxTime = round(range.max); + int value = round(range.step*model->logicalSw[i].val2 + range.offset); + cswitchTOffset[i]->setMaximumTime(QTimeS(maxTime)); + QString format = (maxTime>=3600) ? "hh:mm:ss" : "mm:ss"; + if (!range.unit.isEmpty()) + format += QString("' [%1]'").arg(range.unit); + cswitchTOffset[i]->setDisplayFormat(format); + cswitchTOffset[i]->setTime(QTimeS(value)); + } + else { + mask |= VALUE2_VISIBLE; + if (range.unit.isEmpty()) + cswitchOffset[i]->setSuffix(""); + else + cswitchOffset[i]->setSuffix(" " + range.unit); + cswitchOffset[i]->setMinimum(range.min); + cswitchOffset[i]->setMaximum(range.max); + cswitchOffset[i]->setValue(range.step*(model->logicalSw[i].val2/* TODO+source.getRawOffset(model)*/)+range.offset); + } + break; } - else { - mask |= VALUE2_VISIBLE; - if (range.unit.isEmpty()) - cswitchOffset[i]->setSuffix(""); - else - cswitchOffset[i]->setSuffix(" " + range.unit); - cswitchOffset[i]->setMinimum(range.min); - cswitchOffset[i]->setMaximum(range.max); - cswitchOffset[i]->setValue(range.step*(model->logicalSw[i].val2/* TODO+source.getRawOffset(model)*/)+range.offset); - } - break; - case LS_FAMILY_STICKY: - // no break - case LS_FAMILY_VBOOL: - mask |= SOURCE1_VISIBLE | SOURCE2_VISIBLE; - populateSwitchCB(cswitchSource1[i], RawSwitch(model->logicalSw[i].val1), generalSettings, LogicalSwitchesContext); - populateSwitchCB(cswitchSource2[i], RawSwitch(model->logicalSw[i].val2), generalSettings, LogicalSwitchesContext); - break; - case LS_FAMILY_EDGE: - mask |= SOURCE1_VISIBLE | VALUE2_VISIBLE | VALUE3_VISIBLE; - mask &= ~DELAY_ENABLED; - populateSwitchCB(cswitchSource1[i], RawSwitch(model->logicalSw[i].val1), generalSettings, LogicalSwitchesContext); - updateTimerParam(cswitchOffset[i], model->logicalSw[i].val2, 0.0); - updateTimerParam(cswitchOffset2[i], model->logicalSw[i].val2+model->logicalSw[i].val3, ValToTim(TimToVal(cswitchOffset[i]->value())-1)); - cswitchOffset2[i]->setSpecialValueText(tr("(instant)")); - if (model->logicalSw[i].val3 == 0) { - cswitchOffset2[i]->setSuffix(tr("(infinite)")); - } - else { - cswitchOffset2[i]->setSuffix(""); - } - break; - case LS_FAMILY_VCOMP: - mask |= SOURCE1_VISIBLE | SOURCE2_VISIBLE; - populateSourceCB(cswitchSource1[i], RawSource(model->logicalSw[i].val1), generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | POPULATE_TELEMETRY | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0)); - populateSourceCB(cswitchSource2[i], RawSource(model->logicalSw[i].val2), generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | POPULATE_TELEMETRY | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0)); - break; - case LS_FAMILY_TIMER: - mask |= VALUE1_VISIBLE | VALUE2_VISIBLE; - updateTimerParam(cswitchValue[i], model->logicalSw[i].val1, 0.1); - updateTimerParam(cswitchOffset[i], model->logicalSw[i].val2, 0.1); + case LS_FAMILY_STICKY: + // no break + case LS_FAMILY_VBOOL: + mask |= SOURCE1_VISIBLE | SOURCE2_VISIBLE; + populateSwitchCB(cswitchSource1[i], RawSwitch(model->logicalSw[i].val1), generalSettings, LogicalSwitchesContext); + populateSwitchCB(cswitchSource2[i], RawSwitch(model->logicalSw[i].val2), generalSettings, LogicalSwitchesContext); + break; + case LS_FAMILY_EDGE: + mask |= SOURCE1_VISIBLE | VALUE2_VISIBLE | VALUE3_VISIBLE; + mask &= ~DELAY_ENABLED; + populateSwitchCB(cswitchSource1[i], RawSwitch(model->logicalSw[i].val1), generalSettings, LogicalSwitchesContext); + updateTimerParam(cswitchOffset[i], model->logicalSw[i].val2, 0.0); + updateTimerParam(cswitchOffset2[i], model->logicalSw[i].val2+model->logicalSw[i].val3, ValToTim(TimToVal(cswitchOffset[i]->value())-1)); + cswitchOffset2[i]->setSpecialValueText(tr("(instant)")); + if (model->logicalSw[i].val3 == 0) { + cswitchOffset2[i]->setSuffix(tr("(infinite)")); + } + else { + cswitchOffset2[i]->setSuffix(""); + } + break; + case LS_FAMILY_VCOMP: + mask |= SOURCE1_VISIBLE | SOURCE2_VISIBLE; + populateSourceCB(cswitchSource1[i], RawSource(model->logicalSw[i].val1), generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | POPULATE_TELEMETRY | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0)); + populateSourceCB(cswitchSource2[i], RawSource(model->logicalSw[i].val2), generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | POPULATE_TELEMETRY | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0)); + break; + case LS_FAMILY_TIMER: + mask |= VALUE1_VISIBLE | VALUE2_VISIBLE; + updateTimerParam(cswitchValue[i], model->logicalSw[i].val1, 0.1); + updateTimerParam(cswitchOffset[i], model->logicalSw[i].val2, 0.1); + } } cswitchSource1[i]->setVisible(mask & SOURCE1_VISIBLE); @@ -374,9 +383,12 @@ void LogicalSwitchesPanel::setSwitchWidgetVisibility(int i) cswitchOffset2[i]->setVisible(mask & VALUE3_VISIBLE); cswitchTOffset[i]->setVisible(mask & VALUE_TO_VISIBLE); if (firmware->getCapability(LogicalSwitchesExt)) { - cswitchDelay[i]->setEnabled(mask & DELAY_ENABLED); - cswitchDuration[i]->setValue(model->logicalSw[i].duration/10.0); - cswitchDelay[i]->setValue(model->logicalSw[i].delay/10.0); + cswitchDuration[i]->setVisible(mask & DURATION_ENABLED); + cswitchDelay[i]->setVisible(mask & DELAY_ENABLED); + if (mask & DURATION_ENABLED) + cswitchDuration[i]->setValue(model->logicalSw[i].duration/10.0); + if (mask & DELAY_ENABLED) + cswitchDelay[i]->setValue(model->logicalSw[i].delay/10.0); } lock = false; } @@ -425,8 +437,13 @@ void LogicalSwitchesPanel::populateCSWCB(QComboBox *b, int value) b->setMaxVisibleItems(10); } -void LogicalSwitchesPanel::populateAndSwitchCB(QComboBox *b, const RawSwitch & value) +void LogicalSwitchesPanel::populateAndSwitchCB(QComboBox *b, const RawSwitch & value, const int idx) { + if (!model->logicalSw[idx].func) { + b->setVisible(false); + return; + } + if (IS_ARM(firmware->getBoard())) { populateSwitchCB(b, value, generalSettings, LogicalSwitchesContext); } @@ -451,6 +468,7 @@ void LogicalSwitchesPanel::populateAndSwitchCB(QComboBox *b, const RawSwitch & v if (item == value) b->setCurrentIndex(b->count()-1); } } + b->setVisible(true); } void LogicalSwitchesPanel::updateLine(int i) @@ -460,7 +478,7 @@ void LogicalSwitchesPanel::updateLine(int i) lock = true; setSwitchWidgetVisibility(i); lock = true; - populateAndSwitchCB(cswitchAnd[i], RawSwitch(model->logicalSw[i].andsw)); + populateAndSwitchCB(cswitchAnd[i], RawSwitch(model->logicalSw[i].andsw), i); lock = false; } diff --git a/companion/src/modeledit/logicalswitches.h b/companion/src/modeledit/logicalswitches.h index 8ac3e3693..ea7ab1e56 100644 --- a/companion/src/modeledit/logicalswitches.h +++ b/companion/src/modeledit/logicalswitches.h @@ -62,7 +62,7 @@ class LogicalSwitchesPanel : public ModelPanel int selectedSwitch; void populateCSWCB(QComboBox *b, int value); - void populateAndSwitchCB(QComboBox *b, const RawSwitch & value); + void populateAndSwitchCB(QComboBox *b, const RawSwitch & value, const int idx); void updateLine(int index); void updateTimerParam(QDoubleSpinBox *sb, int timer, double minimum=0); From 36a6ba24b8f3e2131a0a94347822a7572b8389ad Mon Sep 17 00:00:00 2001 From: Thibault Jouan Date: Sun, 26 Mar 2017 18:07:35 +0000 Subject: [PATCH 046/203] Add firmware update tools location for FreeBSD (#4688) Add paths for avrdude and dfu-util programs under FreeBSD. SAM-BA does not exist yet in the FreeBSD port collection. --- companion/src/burnconfigdialog.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/companion/src/burnconfigdialog.cpp b/companion/src/burnconfigdialog.cpp index 2d7771006..400935573 100644 --- a/companion/src/burnconfigdialog.cpp +++ b/companion/src/burnconfigdialog.cpp @@ -125,6 +125,11 @@ void burnConfigDialog::getSettings() sambaLoc = "/usr/local/bin/sam-ba"; if ( dfuLoc.isEmpty()) dfuLoc = QFileInfo(QApplication::applicationDirPath() + "/../Resources/dfu-util").absoluteFilePath(); +#elif defined __FreeBSD__ + if (avrLoc.isEmpty()) + avrLoc = "/usr/local/bin/avrdude"; + if (dfuLoc.isEmpty()) + dfuLoc = "/usr/local/bin/dfu-util"; #else if ( avrLoc.isEmpty()) avrLoc = "/usr/bin/avrdude"; From 29018fae9c3d4d18e94317012e74596fdf607956 Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Sun, 26 Mar 2017 20:11:06 +0200 Subject: [PATCH 047/203] Keys code cleanup and documentation (#4692) --- radio/src/keys.cpp | 73 ++++++++++++++++++++++++++++++++++++---------- radio/src/keys.h | 34 +++++++-------------- 2 files changed, 67 insertions(+), 40 deletions(-) diff --git a/radio/src/keys.cpp b/radio/src/keys.cpp index 00ce73711..4c0580b06 100644 --- a/radio/src/keys.cpp +++ b/radio/src/keys.cpp @@ -2,7 +2,7 @@ * Copyright (C) OpenTX * * Based on code named - * th9x - http://code.google.com/p/th9x + * th9x - http://code.google.com/p/th9x * er9x - http://code.google.com/p/er9x * gruvin9x - http://code.google.com/p/gruvin9x * @@ -20,8 +20,27 @@ #include "opentx.h" +#define KEY_LONG_DELAY 32 // long key press minimum duration (x10ms), must be less than KEY_REPEAT_DELAY +#define KEY_REPEAT_DELAY 40 // press longer than this enables repeat (but does not fire it yet) +#define KEY_REPEAT_TRIGGER 48 // repeat trigger, used in combination with m_state to produce decreasing times between repeat events +#define KEY_REPEAT_PAUSE_DELAY 64 + +#ifdef SIMU + #define FILTERBITS 1 // defines how many bits are used for debounce +#else + #define FILTERBITS 4 // defines how many bits are used for debounce +#endif + +#define KSTATE_OFF 0 +#define KSTATE_RPTDELAY 95 +#define KSTATE_START 97 +#define KSTATE_PAUSE 98 +#define KSTATE_KILLED 99 + + event_t s_evt; struct t_inactivity inactivity = {0}; +Key keys[NUM_KEYS]; #if defined(CPUARM) event_t getEvent(bool trim) @@ -47,11 +66,9 @@ event_t getEvent() } #endif -#define KEY_LONG_DELAY 32 - -Key keys[NUM_KEYS]; void Key::input(bool val) { + // store new value in the bits that hold the key state history (used for debounce) uint8_t t_vals = m_vals ; t_vals <<= 1 ; if (val) t_vals |= 1; @@ -59,32 +76,39 @@ void Key::input(bool val) m_cnt++; - if (m_state && m_vals==0) { + if (m_state && m_vals == 0) { + // key is released if (m_state != KSTATE_KILLED) { + // TRACE("key %d BREAK", key()); putEvent(EVT_KEY_BREAK(key())); } - m_cnt = 0; m_state = KSTATE_OFF; + m_cnt = 0; + return; } + switch (m_state) { case KSTATE_OFF: - if (m_vals == FFVAL) { + if (m_vals == ((1<= 48) { //3 6 12 24 48 pulses in every 480ms + if (m_cnt >= KEY_REPEAT_TRIGGER) { //3 6 12 24 48 pulses in every 480ms m_state >>= 1; - m_cnt = 0; + m_cnt = 0; } // no break case 1: if ((m_cnt & (m_state-1)) == 0) { + // this produces repeat events that at first repeat slowly and then increase in speed + // TRACE("key %d REPEAT", key()); putEvent(EVT_KEY_REPT(key())); } break; - case KSTATE_PAUSE: //pause - if (m_cnt >= 64) { + case KSTATE_PAUSE: //pause repeat events + if (m_cnt >= KEY_REPEAT_PAUSE_DELAY) { m_state = 8; - m_cnt = 0; + m_cnt = 0; } break; @@ -117,17 +143,32 @@ void Key::input(bool val) } } +void Key::pauseEvents() +{ + m_state = KSTATE_PAUSE; + m_cnt = 0; +} + +void Key::killEvents() +{ + // TRACE("key %d killed", key()); + m_state = KSTATE_KILLED; +} + + uint8_t Key::key() const { return (this - keys); } +// Introduce a slight delay in the key repeat sequence void pauseEvents(event_t event) { event = EVT_KEY_MASK(event); if (event < (int)DIM(keys)) keys[event].pauseEvents(); } +// Disables any further event generation (BREAK and REPEAT) for this key, until the key is released void killEvents(event_t event) { #if defined(ROTARY_ENCODERS) diff --git a/radio/src/keys.h b/radio/src/keys.h index d7a7048c9..5475a7aed 100644 --- a/radio/src/keys.h +++ b/radio/src/keys.h @@ -41,15 +41,16 @@ #define EVT_ENTRY_UP 0xbe #endif -#define EVT_KEY_BREAK(key) ((key)|_MSK_KEY_BREAK) -#define EVT_KEY_FIRST(key) ((key)|_MSK_KEY_FIRST) -#define EVT_KEY_REPT(key) ((key)|_MSK_KEY_REPT) -#define EVT_KEY_LONG(key) ((key)|_MSK_KEY_LONG) +// normal order of events is: FIRST, LONG, REPEAT, REPEAT, ..., BREAK +#define EVT_KEY_FIRST(key) ((key)|_MSK_KEY_FIRST) // fired when key is pressed +#define EVT_KEY_LONG(key) ((key)|_MSK_KEY_LONG) // fired when key is held pressed for a while +#define EVT_KEY_REPT(key) ((key)|_MSK_KEY_REPT) // fired when key is held pressed long enough, fires multiple times with increasing speed +#define EVT_KEY_BREAK(key) ((key)|_MSK_KEY_BREAK) // fired when key is released (short or long), but only if the event was not killed -#define IS_KEY_BREAK(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_BREAK) #define IS_KEY_FIRST(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_FIRST) #define IS_KEY_LONG(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_LONG) #define IS_KEY_REPT(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_REPT) +#define IS_KEY_BREAK(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_BREAK) #if (defined(PCBHORUS) || defined(PCBFLAMENCO) || defined(PCBTARANIS)) && defined(ROTARY_ENCODER_NAVIGATION) typedef uint16_t event_t; @@ -79,34 +80,19 @@ class Key { -#define FILTERBITS 4 - -#ifdef SIMU - #define FFVAL 1 -#else - #define FFVAL ((1< 0; } - void pauseEvents() { m_state = KSTATE_PAUSE; m_cnt = 0; } - void killEvents() { m_state = KSTATE_KILLED; } + bool state() const { return m_vals > 0; } + void pauseEvents(); + void killEvents(); uint8_t key() const; }; extern Key keys[NUM_KEYS]; - extern event_t s_evt; #define putEvent(evt) s_evt = evt From 6c28efdd4fb5967b844ebcab8d9b0ce28bcc5de4 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Sun, 26 Mar 2017 20:39:59 +0200 Subject: [PATCH 048/203] Fixes #4695 --- radio/src/gui/gui_common_arm.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/radio/src/gui/gui_common_arm.cpp b/radio/src/gui/gui_common_arm.cpp index aaeba662c..8a252aa3f 100644 --- a/radio/src/gui/gui_common_arm.cpp +++ b/radio/src/gui/gui_common_arm.cpp @@ -131,6 +131,9 @@ int getChannelsUsed() bool isSourceAvailable(int source) { + if (source < 0) + return false; + if (source>=MIXSRC_FIRST_INPUT && source<=MIXSRC_LAST_INPUT) { return isInputAvailable(source - MIXSRC_FIRST_INPUT); } From aaaaf1a8068ba01f3246a744ef5b67ac60d51a60 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Mon, 27 Mar 2017 01:29:14 -0400 Subject: [PATCH 049/203] [simulation] Fix reported multi-position switch output being outside of normal range due to SIMU exception in mixer.cpp. --- radio/src/mixer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/mixer.cpp b/radio/src/mixer.cpp index ef4e226d2..d3ec9d021 100644 --- a/radio/src/mixer.cpp +++ b/radio/src/mixer.cpp @@ -428,10 +428,10 @@ void evalInputs(uint8_t mode) uint8_t ch = (i < NUM_STICKS ? CONVERT_MODE(i) : i); int16_t v = anaIn(i); -#if !defined(SIMU) if (IS_POT_MULTIPOS(i)) { v -= RESX; } +#if !defined(SIMU) else { CalibData * calib = &g_eeGeneral.calib[i]; v -= calib->mid; From 4086374249fc32fc6cffa3d72fc1b31dd24477e6 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Mon, 27 Mar 2017 18:43:23 +0200 Subject: [PATCH 050/203] Compilation fixes --- radio/src/translations/pl.h.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/radio/src/translations/pl.h.txt b/radio/src/translations/pl.h.txt index b77a1b874..59a6321cb 100644 --- a/radio/src/translations/pl.h.txt +++ b/radio/src/translations/pl.h.txt @@ -619,7 +619,7 @@ #define OFS_EXIT sizeof(TR_ENTER) #endif -#define TR_MENUWHENDONE CENTER "\006"TR_ENTER " > DALEJ " +#define TR_MENUWHENDONE CENTER "\006" TR_ENTER " > DALEJ" #define TR_FREE "woln" #define TR_DELETEMODEL "SKASUJ MODEL" #define TR_COPYINGMODEL "Kopiuj model.." @@ -1221,7 +1221,7 @@ #define TR_SERVOS_OK "Servos OK" #define TR_SERVOS_KO "Servos KO" //TODO: translation -#define TR_INVERTED SERIAL INDENT "Invert" +#define TR_INVERTED_SERIAL INDENT "Invert" #define TR_IGNORE_INSTANCE INDENT "Ignoruj przypadek" #define TR_DISCOVER_SENSORS INDENT "Znajdź nowe czujniki" #define TR_STOP_DISCOVER_SENSORS INDENT "Szukanie STOP " From 627347a48c591ee5532363f8d602a570fb11b03d Mon Sep 17 00:00:00 2001 From: 3djc Date: Mon, 27 Mar 2017 18:59:34 +0200 Subject: [PATCH 051/203] Horus as vario handling too (#4700) --- companion/src/modeledit/telemetry.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/companion/src/modeledit/telemetry.cpp b/companion/src/modeledit/telemetry.cpp index 3ef2dd185..7d932184f 100644 --- a/companion/src/modeledit/telemetry.cpp +++ b/companion/src/modeledit/telemetry.cpp @@ -758,7 +758,7 @@ TelemetryPanel::TelemetryPanel(QWidget *parent, ModelData & model, GeneralSettin connect(analogs[1], SIGNAL(modified()), this, SLOT(onModified())); } - if (IS_TARANIS(firmware->getBoard())) { + if (IS_HORUS_OR_TARANIS(firmware->getBoard())) { ui->voltsSource->setField(model.frsky.voltsSource, this); ui->altitudeSource->setField(model.frsky.altitudeSource, this); ui->varioSource->setField(model.frsky.varioSource, this); From f5ab145d2fc2bce96400eb0c8c58b1549cd8f9d2 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Mon, 27 Mar 2017 13:02:19 -0400 Subject: [PATCH 052/203] [Companion] Show custom control names throughout the UI (& internal refactoring) (#4693) * [Companion] Introduce new Boards class to further consolidate hardware metadata and remove some globals. * [Companion] * RawSource::toString() and RawSwitch::toString() can now return custom hardware names (if given a GeneralSettings object) for the following types (respectively): SOURCE_TYPE_STICK, SOURCE_TYPE_SWITCH, SWITCH_TYPE_SWITCH, & SWITCH_TYPE_MULTIPOS_POT; * RawSource::isPot() and isSlider() can now return their own index position in potConfig[]/sliderConfig[]; * Switch indicator strings can be localized if necessary. * [Companion] Refactor model printers to use new RawSource/RawSwitch capabilities; Simplify model-to-printer mapping scheme in multimodelprinter; Use const ModelData pointer. * [Companion] Refactor how RawSource and RawSwitch selection combo boxes are populated, using cache-able data models instead of direct manipulation; Refactor some other Helpers function into their own namespace. * Cosmetics & forgotten qualifier. --- companion/src/boards.cpp | 213 +++++-- companion/src/boards.h | 73 ++- companion/src/constants.h | 26 +- companion/src/eeprominterface.cpp | 197 +++---- companion/src/eeprominterface.h | 3 +- .../src/firmwares/er9x/er9xinterface.cpp | 10 +- .../firmwares/ersky9x/ersky9xinterface.cpp | 12 +- .../src/firmwares/opentx/opentxeeprom.cpp | 6 +- .../src/firmwares/opentx/opentxinterface.cpp | 22 +- companion/src/flasheepromdialog.cpp | 2 +- companion/src/helpers.cpp | 519 ++++++++---------- companion/src/helpers.h | 66 ++- companion/src/modeledit/customfunctions.cpp | 53 +- companion/src/modeledit/customfunctions.h | 3 + companion/src/modeledit/expodialog.cpp | 7 +- companion/src/modeledit/flightmodes.cpp | 17 +- companion/src/modeledit/heli.cpp | 12 +- companion/src/modeledit/heli.h | 1 + companion/src/modeledit/logicalswitches.cpp | 32 +- companion/src/modeledit/logicalswitches.h | 2 + companion/src/modeledit/mixerdialog.cpp | 7 +- companion/src/modeledit/setup.cpp | 40 +- companion/src/modeledit/telemetry.cpp | 13 +- companion/src/modelprinter.cpp | 66 +-- companion/src/modelprinter.h | 4 +- companion/src/modelslist.cpp | 2 +- companion/src/multimodelprinter.cpp | 108 ++-- companion/src/multimodelprinter.h | 6 +- companion/src/printdialog.cpp | 4 +- companion/src/radiodata.h | 32 +- companion/src/radiointerface.cpp | 18 +- companion/src/simulation/joystickdialog.cpp | 15 +- companion/src/simulation/simulatorinterface.h | 4 +- companion/src/storage/bineeprom.cpp | 2 +- companion/src/storage/eepe.cpp | 12 +- companion/src/storage/firmwareinterface.cpp | 1 + companion/src/storage/hexeeprom.cpp | 13 +- companion/src/storage/rlefile.cpp | 6 +- companion/src/storage/storage.cpp | 2 +- radio/src/targets/simu/opentxsimulator.cpp | 2 +- 40 files changed, 886 insertions(+), 747 deletions(-) diff --git a/companion/src/boards.cpp b/companion/src/boards.cpp index 92e8c1024..d5d885b6a 100644 --- a/companion/src/boards.cpp +++ b/companion/src/boards.cpp @@ -21,92 +21,156 @@ #include "boards.h" #include "macros.h" +// TODO remove all those constants +// Update: These are now all only used within this class. +// External access is only via getEEpromSize() and getFlashSize() + +#define EESIZE_STOCK 2048 +#define EESIZE_M128 4096 +#define EESIZE_GRUVIN9X 4096 +#define EESIZE_TARANIS (32*1024) +#define EESIZE_SKY9X (128*4096) +#define EESIZE_9XRPRO (128*4096) +#define EESIZE_MAX EESIZE_9XRPRO + +// getFlashSize() (and these macros) is only used by radiointerface::getDfuArgs (perhaps can find a better way?) +#define FSIZE_STOCK (64*1024) +#define FSIZE_M128 (128*1024) +#define FSIZE_GRUVIN9X (256*1024) +#define FSIZE_TARANIS (512*1024) +#define FSIZE_SKY9X (256*1024) +#define FSIZE_9XRPRO (512*1024) +#define FSIZE_HORUS (2048*1024) +#define FSIZE_MAX FSIZE_HORUS + using namespace Board; -int getEEpromSize(Board::Type board) +void Boards::setBoardType(const Type & board) +{ + if (board >= BOARD_UNKNOWN && board < BOARD_ENUM_COUNT) + m_boardType = board; + else + m_boardType = BOARD_UNKNOWN; +} + +const int Boards::getEEpromSize(Board::Type board) { switch (board) { - case Board::BOARD_STOCK: + case BOARD_STOCK: return EESIZE_STOCK; - case Board::BOARD_M128: + case BOARD_M128: return EESIZE_M128; - case Board::BOARD_MEGA2560: - case Board::BOARD_GRUVIN9X: + case BOARD_MEGA2560: + case BOARD_GRUVIN9X: return EESIZE_GRUVIN9X; - case Board::BOARD_SKY9X: + case BOARD_SKY9X: return EESIZE_SKY9X; - case Board::BOARD_9XRPRO: - case Board::BOARD_AR9X: + case BOARD_9XRPRO: + case BOARD_AR9X: return EESIZE_9XRPRO; - case Board::BOARD_TARANIS_X7: - case Board::BOARD_TARANIS_X9D: - case Board::BOARD_TARANIS_X9DP: - case Board::BOARD_TARANIS_X9E: - case Board::BOARD_FLAMENCO: + case BOARD_TARANIS_X7: + case BOARD_TARANIS_X9D: + case BOARD_TARANIS_X9DP: + case BOARD_TARANIS_X9E: + case BOARD_FLAMENCO: return EESIZE_TARANIS; + case BOARD_UNKNOWN: + return EESIZE_MAX; default: return 0; // unlimited } } -Board::SwitchInfo getSwitchInfo(Board::Type board, unsigned index) +const int Boards::getFlashSize(Type board) +{ + switch (board) { + case BOARD_STOCK: + return FSIZE_STOCK; + case BOARD_M128: + return FSIZE_M128; + case BOARD_MEGA2560: + case BOARD_GRUVIN9X: + return FSIZE_GRUVIN9X; + case BOARD_SKY9X: + return FSIZE_SKY9X; + case BOARD_9XRPRO: + case BOARD_AR9X: + return FSIZE_9XRPRO; + case BOARD_TARANIS_X9D: + case BOARD_TARANIS_X9DP: + case BOARD_TARANIS_X9E: + case BOARD_FLAMENCO: + return FSIZE_TARANIS; + case BOARD_X12S: + case BOARD_X10: + return FSIZE_HORUS; + case BOARD_UNKNOWN: + return FSIZE_MAX; + default: + return 0; + } +} + +const SwitchInfo Boards::getSwitchInfo(Board::Type board, unsigned index) { if (IS_TARANIS_X7(board)) { const Board::SwitchInfo switches[] = { - {Board::SWITCH_3POS, "SA"}, - {Board::SWITCH_3POS, "SB"}, - {Board::SWITCH_3POS, "SC"}, - {Board::SWITCH_3POS, "SD"}, - {Board::SWITCH_2POS, "SF"}, - {Board::SWITCH_TOGGLE, "SH"} + {SWITCH_3POS, "SA"}, + {SWITCH_3POS, "SB"}, + {SWITCH_3POS, "SC"}, + {SWITCH_3POS, "SD"}, + {SWITCH_2POS, "SF"}, + {SWITCH_TOGGLE, "SH"} }; if (index < DIM(switches)) return switches[index]; } else if (IS_HORUS_OR_TARANIS(board)) { const Board::SwitchInfo switches[] = { - {Board::SWITCH_3POS, "SA"}, - {Board::SWITCH_3POS, "SB"}, - {Board::SWITCH_3POS, "SC"}, - {Board::SWITCH_3POS, "SD"}, - {Board::SWITCH_3POS, "SE"}, - {Board::SWITCH_2POS, "SF"}, - {Board::SWITCH_3POS, "SG"}, - {Board::SWITCH_TOGGLE, "SH"}, - {Board::SWITCH_3POS, "SI"}, - {Board::SWITCH_3POS, "SJ"}, - {Board::SWITCH_3POS, "SK"}, - {Board::SWITCH_3POS, "SL"}, - {Board::SWITCH_3POS, "SM"}, - {Board::SWITCH_3POS, "SN"}, - {Board::SWITCH_3POS, "SO"}, - {Board::SWITCH_3POS, "SP"}, - {Board::SWITCH_3POS, "SQ"}, - {Board::SWITCH_3POS, "SR"} + {SWITCH_3POS, "SA"}, + {SWITCH_3POS, "SB"}, + {SWITCH_3POS, "SC"}, + {SWITCH_3POS, "SD"}, + {SWITCH_3POS, "SE"}, + {SWITCH_2POS, "SF"}, + {SWITCH_3POS, "SG"}, + {SWITCH_TOGGLE, "SH"}, + {SWITCH_3POS, "SI"}, + {SWITCH_3POS, "SJ"}, + {SWITCH_3POS, "SK"}, + {SWITCH_3POS, "SL"}, + {SWITCH_3POS, "SM"}, + {SWITCH_3POS, "SN"}, + {SWITCH_3POS, "SO"}, + {SWITCH_3POS, "SP"}, + {SWITCH_3POS, "SQ"}, + {SWITCH_3POS, "SR"} }; if (index < DIM(switches)) return switches[index]; } else { const Board::SwitchInfo switches[] = { - {Board::SWITCH_2POS, "THR"}, - {Board::SWITCH_2POS, "RUD"}, - {Board::SWITCH_2POS, "ELE"}, - {Board::SWITCH_3POS, "3POS"}, - {Board::SWITCH_2POS, "AIL"}, - {Board::SWITCH_2POS, "GEA"}, - {Board::SWITCH_TOGGLE, "TRN"} + {SWITCH_2POS, "THR"}, + {SWITCH_2POS, "RUD"}, + {SWITCH_2POS, "ELE"}, + {SWITCH_3POS, "3POS"}, + {SWITCH_2POS, "AIL"}, + {SWITCH_2POS, "GEA"}, + {SWITCH_TOGGLE, "TRN"} }; if (index < DIM(switches)) return switches[index]; } - return {Board::SWITCH_NOT_AVAILABLE, "???"}; + return {SWITCH_NOT_AVAILABLE, "???"}; } -int getBoardCapability(Board::Type board, Board::Capability capability) +const int Boards::getCapability(Board::Type board, Board::Capability capability) { switch (capability) { + case Sticks: + return 4; case Pots: if (IS_HORUS(board)) return 3; @@ -153,8 +217,61 @@ int getBoardCapability(Board::Type board, Board::Capability capability) else return 4; case NumTrimSwitches: - return getBoardCapability(board, NumTrims) * 2; + return getCapability(board, NumTrims) * 2; } return 0; } + +const QString Boards::getAxisName(int index) +{ + const QString axes[] = { + QObject::tr("Left Horizontal"), + QObject::tr("Left Vertical"), + QObject::tr("Right Vertical"), + QObject::tr("Right Horizontal"), + QObject::tr("Aux. 1"), + QObject::tr("Aux. 2"), + }; + if (index < (int)DIM(axes)) + return axes[index]; + else + return QObject::tr("Unknown"); +} + +/* Currently unused + +const QString Boards::getBoardName(Board::Type board) +{ + switch (board) { + case BOARD_STOCK: + return "9X"; + case BOARD_M128: + return "9X128"; + case BOARD_GRUVIN9X: + return "Gruvin9x"; + case BOARD_MEGA2560: + return "MEGA2560"; + case BOARD_TARANIS_X7: + return "Taranis X7"; + case BOARD_TARANIS_X9D: + return "Taranis X9D"; + case BOARD_TARANIS_X9DP: + return "Taranis X9D+"; + case BOARD_TARANIS_X9E: + return "Taranis X9E"; + case BOARD_SKY9X: + return "Sky9x"; + case BOARD_9XRPRO: + return "9XR-PRO"; + case BOARD_AR9X: + return "AR9X"; + case BOARD_X12S: + return "Horus"; + case BOARD_X10: + return "X10"; + default: + return QObject::tr("Unknown"); + } +} +*/ diff --git a/companion/src/boards.h b/companion/src/boards.h index 96420498b..d399b7a09 100644 --- a/companion/src/boards.h +++ b/companion/src/boards.h @@ -21,13 +21,17 @@ #ifndef _BOARDS_H_ #define _BOARDS_H_ +#include +#include + // TODO create a Board class with all these functions namespace Board { enum Type { - BOARD_STOCK, + BOARD_UNKNOWN = -1, + BOARD_STOCK = 0, BOARD_M128, BOARD_MEGA2560, BOARD_GRUVIN9X, @@ -41,7 +45,7 @@ namespace Board { BOARD_FLAMENCO, BOARD_X12S, BOARD_X10, - BOARD_UNKNOWN = -1 + BOARD_ENUM_COUNT }; enum PotType @@ -66,6 +70,14 @@ namespace Board { SWITCH_3POS }; + enum StickAxes { + STICK_AXIS_LH = 0, + STICK_AXIS_LV, + STICK_AXIS_RV, + STICK_AXIS_RH, + STICK_AXIS_COUNT + }; + enum TrimAxes { TRIM_AXIS_LH = 0, TRIM_AXIS_LV, @@ -73,9 +85,10 @@ namespace Board { TRIM_AXIS_RH, TRIM_AXIS_T5, TRIM_AXIS_T6, + TRIM_AXIS_COUNT }; - enum TrimSwitchIndex + enum TrimSwitches { TRIM_SW_LH_DEC, TRIM_SW_LH_INC, @@ -89,10 +102,11 @@ namespace Board { TRIM_SW_T5_INC, TRIM_SW_T6_DEC, TRIM_SW_T6_INC, - TRIM_SW_ENUM_END + TRIM_SW_COUNT }; enum Capability { + Sticks, Pots, Sliders, MouseAnalogs, @@ -105,7 +119,7 @@ namespace Board { struct SwitchInfo { SwitchType config; - const char * name; + QString name; }; struct SwitchPosition { @@ -120,29 +134,38 @@ namespace Board { } -// TODO remove all those constants -#define EESIZE_STOCK 2048 -#define EESIZE_M128 4096 -#define EESIZE_GRUVIN9X 4096 -#define EESIZE_TARANIS (32*1024) -#define EESIZE_SKY9X (128*4096) -#define EESIZE_9XRPRO (128*4096) -#define EESIZE_MAX EESIZE_9XRPRO +class Boards +{ + public: -// TODO remove all those constants -#define FSIZE_STOCK (64*1024) -#define FSIZE_M128 (128*1024) -#define FSIZE_GRUVIN9X (256*1024) -#define FSIZE_TARANIS (512*1024) -#define FSIZE_SKY9X (256*1024) -#define FSIZE_9XRPRO (512*1024) -#define FSIZE_HORUS (2048*1024) -#define FSIZE_MAX FSIZE_HORUS + Boards(Board::Type board) + { + setBoardType(board); + } -int getEEpromSize(Board::Type board); -Board::SwitchInfo getSwitchInfo(Board::Type board, unsigned index); + void setBoardType(const Board::Type & board); + Board::Type getBoardType() const { return m_boardType; } -int getBoardCapability(Board::Type board, Board::Capability capability); + const int getEEpromSize() { return getEEpromSize(m_boardType); } + const int getFlashSize() { return getFlashSize(m_boardType); } + const Board::SwitchInfo getSwitchInfo(unsigned index) { return getSwitchInfo(m_boardType, index); } + const int getCapability(Board::Capability capability) { return getCapability(m_boardType, capability); } + + static const int getEEpromSize(Board::Type board); + static const int getFlashSize(Board::Type board); + static const Board::SwitchInfo getSwitchInfo(Board::Type board, unsigned index); + static const int getCapability(Board::Type board, Board::Capability capability); + static const QString getAxisName(int index); + + protected: + + Board::Type m_boardType; +}; + +// temporary aliases for transition period, use Boards class instead. +#define getBoardCapability(b__, c__) Boards::getCapability(b__, c__) +#define getEEpromSize(b__) Boards::getEEpromSize(b__) +#define getSwitchInfo(b__, i__) Boards::getSwitchInfo(b__, i__) #define IS_9X(board) (board==Board::BOARD_STOCK || board==Board::BOARD_M128) #define IS_STOCK(board) (board==Board::BOARD_STOCK) diff --git a/companion/src/constants.h b/companion/src/constants.h index aa49091ca..c28e7a218 100644 --- a/companion/src/constants.h +++ b/companion/src/constants.h @@ -30,18 +30,22 @@ #define CPN_MAX_CURVES 32 #define CPN_MAX_POINTS 17 #define CPN_MAX_GVARS 9 -#define CPN_MAX_ENCODERS 2 -#define CPN_MAX_CHNOUT 32 // number of real output channels -#define CPN_MAX_CSW 64 // number of custom switches -#define CPN_MAX_CUSTOM_FUNCTIONS 64 // number of functions assigned to switches +#define CPN_MAX_ENCODERS 2 // rotary encoders +#define CPN_MAX_CHNOUT 32 // number of real output channels +#define CPN_MAX_CSW 64 // number of custom switches +#define CPN_MAX_CUSTOM_FUNCTIONS 64 // number of functions assigned to switches #define CPN_MAX_MODULES 2 -#define CPN_MAX_STICKS 4 -#define CPN_MAX_AUX_TRIMS 2 -#define CPN_MAX_POTS 8 +#define CPN_MAX_STICKS Board::STICK_AXIS_COUNT +#define CPN_MAX_TRIMS Board::TRIM_AXIS_COUNT +#define CPN_MAX_TRIM_SW Board::TRIM_SW_COUNT +#define CPN_MAX_KNOBS 4 +#define CPN_MAX_SLIDERS 4 +#define CPN_MAX_POTS (CPN_MAX_KNOBS + CPN_MAX_SLIDERS) #define CPN_MAX_CYC 3 #define CPN_MAX_SWITCHES 32 #define CPN_MAX_KEYS 32 #define CPN_MAX_MOUSE_ANALOGS 2 +#define CPN_MAX_ANALOGS (CPN_MAX_STICKS + CPN_MAX_POTS + CPN_MAX_MOUSE_ANALOGS) #define CPN_STR_FILES QT_TRANSLATE_NOOP("CompanionMacros", "files") #define CPN_STR_RAD_MOD_SETTINGS QT_TRANSLATE_NOOP("CompanionMacros", "Radio and Models settings") @@ -57,9 +61,9 @@ #define EEPE_EEPROM_FILE_HEADER "EEPE EEPROM FILE" #define EEPE_MODEL_FILE_HEADER "EEPE MODEL FILE" -const char * const ARROW_LEFT = "\xE2\x86\x90"; -const char * const ARROW_UP = "\xE2\x86\x91"; -const char * const ARROW_RIGHT = "\xE2\x86\x92"; -const char * const ARROW_DOWN = "\xE2\x86\x93"; +#define CPN_STR_SW_INDICATOR_UP QT_TRANSLATE_NOOP("RawSwitch", "\xE2\x86\x91") // Switch up position indicator: Up arrow, or similar. +#define CPN_STR_SW_INDICATOR_DN QT_TRANSLATE_NOOP("RawSwitch", "\xE2\x86\x93") // Switch down position indicator: Down arrow, or similar. +#define CPN_STR_SW_INDICATOR_NEUT QT_TRANSLATE_NOOP("RawSwitch", "-") // Switch neutral (middle) position indicator. +#define CPN_STR_SW_INDICATOR_REV QT_TRANSLATE_NOOP("RawSwitch", "!") // Switch reversed logic (NOT) indicator. #endif // _CONSTANTS_H_ diff --git a/companion/src/eeprominterface.cpp b/companion/src/eeprominterface.cpp index 073c8949f..15f834e12 100644 --- a/companion/src/eeprominterface.cpp +++ b/companion/src/eeprominterface.cpp @@ -500,7 +500,12 @@ QString RotaryEncoderString(int index) return CHECK_IN_ARRAY(rotary, index); } -QString RawSource::toString(const ModelData * model) const + +/* + * RawSource + */ + +QString RawSource::toString(const ModelData * model, const GeneralSettings * const generalSettings) const { static const QString trims[] = { QObject::tr("TrmR"), QObject::tr("TrmE"), QObject::tr("TrmT"), QObject::tr("TrmA"), QObject::tr("Trm5"), QObject::tr("Trm6") @@ -529,69 +534,109 @@ QString RawSource::toString(const ModelData * model) const return QObject::tr("----"); } + QString result; + int genAryIdx = 0; switch (type) { case SOURCE_TYPE_VIRTUAL_INPUT: - { - QString result = QObject::tr("[I%1]").arg(index+1); - if (model && strlen(model->inputNames[index]) > 0) { + result = QObject::tr("[I%1]").arg(index+1); + if (model) result += QString(model->inputNames[index]); - } return result; - } + case SOURCE_TYPE_LUA_OUTPUT: return QObject::tr("LUA%1%2").arg(index/16+1).arg(QChar('a'+index%16)); + case SOURCE_TYPE_STICK: - return getCurrentFirmware()->getAnalogInputName(index); + if (generalSettings) { + if (isPot(&genAryIdx)) + result = QString(generalSettings->potName[genAryIdx]); + else if (isSlider(&genAryIdx)) + result = QString(generalSettings->sliderName[genAryIdx]); + else + result = QString(generalSettings->stickName[index]); + } + if (result.isEmpty()) + result = getCurrentFirmware()->getAnalogInputName(index);; + return result; + case SOURCE_TYPE_TRIM: return CHECK_IN_ARRAY(trims, index); case SOURCE_TYPE_ROTARY_ENCODER: return RotaryEncoderString(index); case SOURCE_TYPE_MAX: return QObject::tr("MAX"); + case SOURCE_TYPE_SWITCH: - return getSwitchInfo(getCurrentBoard(), index).name; + if (generalSettings) + result = QString(generalSettings->switchName[index]); + if (result.isEmpty()) + result = getSwitchInfo(getCurrentBoard(), index).name; + return result; + case SOURCE_TYPE_CUSTOM_SWITCH: return QObject::tr("L%1").arg(index+1); + case SOURCE_TYPE_CYC: return QObject::tr("CYC%1").arg(index+1); + case SOURCE_TYPE_PPM: return QObject::tr("TR%1").arg(index+1); + case SOURCE_TYPE_CH: return QObject::tr("CH%1").arg(index+1); + case SOURCE_TYPE_SPECIAL: return CHECK_IN_ARRAY(special, index); + case SOURCE_TYPE_TELEMETRY: if (IS_ARM(getCurrentBoard())) { div_t qr = div(index, 3); - QString result = QString(model ? model->sensorData[qr.quot].label : QString("[T%1]").arg(qr.quot+1)); - if (qr.rem) result += qr.rem == 1 ? "-" : "+"; + result = model ? QString(model->sensorData[qr.quot].label) : QString("[T%1]").arg(qr.quot+1); + if (qr.rem) + result += (qr.rem == 1 ? "-" : "+"); return result; } else { return CHECK_IN_ARRAY(telemetry, index); } + case SOURCE_TYPE_GVAR: return QObject::tr("GV%1").arg(index+1); + default: return QObject::tr("----"); } } -bool RawSource::isPot() const +bool RawSource::isPot(int * potsIndex) const { - return (type == SOURCE_TYPE_STICK && - index >= CPN_MAX_STICKS && - index < CPN_MAX_STICKS + getBoardCapability(getCurrentBoard(), Board::Pots)); + if (type == SOURCE_TYPE_STICK && + index >= getBoardCapability(getCurrentBoard(), Board::Sticks) && + index < getBoardCapability(getCurrentBoard(), Board::Sticks) + getBoardCapability(getCurrentBoard(), Board::Pots)) { + if (potsIndex) + *potsIndex = index - getBoardCapability(getCurrentBoard(), Board::Sticks); + return true; + } + return false; } -bool RawSource::isSlider() const +bool RawSource::isSlider(int * sliderIndex) const { - return (type == SOURCE_TYPE_STICK && - index >= CPN_MAX_STICKS + getBoardCapability(getCurrentBoard(), Board::Pots) && - index < CPN_MAX_STICKS + getBoardCapability(getCurrentBoard(), Board::Pots) + getBoardCapability(getCurrentBoard(), Board::Sliders)); + if (type == SOURCE_TYPE_STICK && + index >= getBoardCapability(getCurrentBoard(), Board::Sticks) + getBoardCapability(getCurrentBoard(), Board::Pots) && + index < getBoardCapability(getCurrentBoard(), Board::Sticks) + getBoardCapability(getCurrentBoard(), Board::Pots) + getBoardCapability(getCurrentBoard(), Board::Sliders)) { + if (sliderIndex) + *sliderIndex = index - getBoardCapability(getCurrentBoard(), Board::Sticks) - getBoardCapability(getCurrentBoard(), Board::Pots); + return true; + } + return false; } -QString RawSwitch::toString(Board::Type board) const +/* + * RawSwitch + */ + +QString RawSwitch::toString(Board::Type board, const GeneralSettings * const generalSettings) const { if (board == Board::BOARD_UNKNOWN) { board = getCurrentBoard(); @@ -607,12 +652,6 @@ QString RawSwitch::toString(Board::Type board) const QObject::tr("FM0"), QObject::tr("FM1"), QObject::tr("FM2"), QObject::tr("FM3"), QObject::tr("FM4"), QObject::tr("FM5"), QObject::tr("FM6"), QObject::tr("FM7"), QObject::tr("FM8") }; - static const QString multiposPots[] = { - QObject::tr("S11"), QObject::tr("S12"), QObject::tr("S13"), QObject::tr("S14"), QObject::tr("S15"), QObject::tr("S16"), - QObject::tr("S21"), QObject::tr("S22"), QObject::tr("S23"), QObject::tr("S24"), QObject::tr("S25"), QObject::tr("S26"), - QObject::tr("S31"), QObject::tr("S32"), QObject::tr("S33"), QObject::tr("S34"), QObject::tr("S35"), QObject::tr("S36") - }; - static const QString trimsSwitches[] = { QObject::tr("RudTrim Left"), QObject::tr("RudTrim Right"), QObject::tr("EleTrim Down"), QObject::tr("EleTrim Up"), @@ -631,47 +670,77 @@ QString RawSwitch::toString(Board::Type board) const QObject::tr("THs"), QObject::tr("TH%"), QObject::tr("THt") }; + const QStringList directionIndicators = QStringList() + << CPN_STR_SW_INDICATOR_UP + << CPN_STR_SW_INDICATOR_NEUT + << CPN_STR_SW_INDICATOR_DN; + if (index < 0) { - return QString("!") + RawSwitch(type, -index).toString(); + return CPN_STR_SW_INDICATOR_REV % RawSwitch(type, -index).toString(board, generalSettings); } else { + QString swName; + div_t qr; switch(type) { case SWITCH_TYPE_SWITCH: if (IS_HORUS_OR_TARANIS(board)) { - div_t qr = div(index-1, 3); - Board::SwitchInfo switchInfo = getSwitchInfo(board, qr.quot); - const char * positions[] = { ARROW_UP, "-", ARROW_DOWN }; - return QString(switchInfo.name) + QString(positions[qr.rem]); + qr = div(index-1, 3); + if (generalSettings) + swName = QString(generalSettings->switchName[qr.quot]); + if (swName.isEmpty()) + swName = getSwitchInfo(board, qr.quot).name; + return swName + directionIndicators.at(qr.rem < directionIndicators.size() ? qr.rem : 1); } else { return CHECK_IN_ARRAY(switches9X, index - 1); } + case SWITCH_TYPE_VIRTUAL: return QObject::tr("L%1").arg(index); + case SWITCH_TYPE_MULTIPOS_POT: - return CHECK_IN_ARRAY(multiposPots, index-1); + qr = div(index - 1, getCurrentFirmware()->getCapability(MultiposPotsPositions)); + if (generalSettings && qr.quot < (int)DIM(generalSettings->potConfig)) + swName = QString(generalSettings->potName[qr.quot]); + if (swName.isEmpty()) + swName = getCurrentFirmware()->getAnalogInputName(qr.quot + getBoardCapability(board, Board::Sticks));; + return swName + "_" + QString::number(qr.rem + 1); + case SWITCH_TYPE_TRIM: return CHECK_IN_ARRAY(trimsSwitches, index-1); + case SWITCH_TYPE_ROTARY_ENCODER: return CHECK_IN_ARRAY(rotaryEncoders, index-1); + case SWITCH_TYPE_ON: return QObject::tr("ON"); + case SWITCH_TYPE_OFF: return QObject::tr("OFF"); + case SWITCH_TYPE_ONE: return QObject::tr("One"); + case SWITCH_TYPE_FLIGHT_MODE: return CHECK_IN_ARRAY(flightModes, index-1); + case SWITCH_TYPE_NONE: return QObject::tr("----"); + case SWITCH_TYPE_TIMER_MODE: return CHECK_IN_ARRAY(timerModes, index); + default: return QObject::tr("???"); } } } + +/* + * CurveReference + */ + QString CurveReference::toString() const { if (value == 0) { @@ -1063,7 +1132,7 @@ GeneralSettings::GeneralSettings() contrast = 25; vBatWarn = 90; - for (int i=0; igetBoard(); for (int i=0; i errors; - if (size != getEEpromSize(Board::BOARD_STOCK)) { + if (size != Boards::getEEpromSize(Board::BOARD_STOCK)) { std::cout << "wrong size\n"; errors.set(WRONG_SIZE); return errors.to_ulong(); @@ -127,7 +127,7 @@ unsigned long Er9xInterface::load(RadioData &radioData, const uint8_t *eeprom, i errors.set(WRONG_FILE_SYSTEM); return errors.to_ulong(); } - + efile->openRd(FILE_GENERAL); Er9xGeneral er9xGeneral; @@ -164,7 +164,7 @@ unsigned long Er9xInterface::load(RadioData &radioData, const uint8_t *eeprom, i } radioData.generalSettings = er9xGeneral; - + for (int i=0; iopenRd(FILE_MODEL(i)); @@ -174,7 +174,7 @@ unsigned long Er9xInterface::load(RadioData &radioData, const uint8_t *eeprom, i else { applyStickModeToModel(er9xModel, radioData.generalSettings.stickMode+1); radioData.models[i] = er9xModel; - } + } } std::cout << "ok\n"; @@ -329,4 +329,4 @@ int Er9xInterface::getCapability(Capability capability) default: return 0; } -} \ No newline at end of file +} diff --git a/companion/src/firmwares/ersky9x/ersky9xinterface.cpp b/companion/src/firmwares/ersky9x/ersky9xinterface.cpp index 8aefef92e..71e2555dc 100644 --- a/companion/src/firmwares/ersky9x/ersky9xinterface.cpp +++ b/companion/src/firmwares/ersky9x/ersky9xinterface.cpp @@ -158,7 +158,7 @@ unsigned long Ersky9xInterface::load(RadioData &radioData, const uint8_t *eeprom std::bitset errors; - if (size != EESIZE_SKY9X) { + if (size != Boards::getEEpromSize(Board::BOARD_SKY9X)) { std::cout << "wrong size\n"; errors.set(WRONG_SIZE); return errors.to_ulong(); @@ -169,7 +169,7 @@ unsigned long Ersky9xInterface::load(RadioData &radioData, const uint8_t *eeprom errors.set(WRONG_FILE_SYSTEM); return errors.to_ulong(); } - + efile->openRd(FILE_GENERAL); Ersky9xGeneral ersky9xGeneral; @@ -198,13 +198,13 @@ unsigned long Ersky9xInterface::load(RadioData &radioData, const uint8_t *eeprom return errors.to_ulong(); } radioData.generalSettings = ersky9xGeneral; - + for (int i=0; iopenRd(FILE_MODEL(i)); - + // if (!efile->readRlc2((uint8_t*)&ersky9xModel, sizeof(Ersky9xModelData))) { size = efile->readRlc2(buffer, 4096); if (!size) { @@ -222,7 +222,7 @@ unsigned long Ersky9xInterface::load(RadioData &radioData, const uint8_t *eeprom applyStickModeToModel(ersky9xModel, radioData.generalSettings.stickMode+1); radioData.models[i] = ersky9xModel; } - } + } } std::cout << "ok\n"; @@ -382,4 +382,4 @@ int Ersky9xInterface::getCapability(Capability capability) default: return 0; } -} \ No newline at end of file +} diff --git a/companion/src/firmwares/opentx/opentxeeprom.cpp b/companion/src/firmwares/opentx/opentxeeprom.cpp index 151d8b580..b72db253f 100644 --- a/companion/src/firmwares/opentx/opentxeeprom.cpp +++ b/companion/src/firmwares/opentx/opentxeeprom.cpp @@ -955,9 +955,9 @@ class FlightModeField: public TransformedField { Board::Type board; unsigned int version; int rotencCount; - int trimBase[CPN_MAX_STICKS+CPN_MAX_AUX_TRIMS]; - int trimExt[CPN_MAX_STICKS+CPN_MAX_AUX_TRIMS]; - unsigned int trimMode[CPN_MAX_STICKS+CPN_MAX_AUX_TRIMS]; + int trimBase[CPN_MAX_TRIMS]; + int trimExt[CPN_MAX_TRIMS]; + unsigned int trimMode[CPN_MAX_TRIMS]; }; class MixField: public TransformedField { diff --git a/companion/src/firmwares/opentx/opentxinterface.cpp b/companion/src/firmwares/opentx/opentxinterface.cpp index 0d916cc26..51eb51386 100644 --- a/companion/src/firmwares/opentx/opentxinterface.cpp +++ b/companion/src/firmwares/opentx/opentxinterface.cpp @@ -207,7 +207,7 @@ unsigned long OpenTxEepromInterface::load(RadioData &radioData, const uint8_t * std::bitset errors; - if (size != getEEpromSize(board)) { + if (size != Boards::getEEpromSize(board)) { if (size == 4096) { int notnull = false; for (int i = 2048; i < 4096; i++) { @@ -227,7 +227,7 @@ unsigned long OpenTxEepromInterface::load(RadioData &radioData, const uint8_t * } } else { - std::cout << " wrong size (" << size << "/" << getEEpromSize(board) << ")\n"; + std::cout << " wrong size (" << size << "/" << Boards::getEEpromSize(board) << ")\n"; errors.set(WRONG_SIZE); return errors.to_ulong(); } @@ -330,7 +330,7 @@ int OpenTxEepromInterface::save(uint8_t * eeprom, const RadioData & radioData, u version = getLastDataVersion(board); } - int size = getEEpromSize(board); + int size = Boards::getEEpromSize(board); efile->EeFsCreate(eeprom, size, board, version); @@ -379,8 +379,8 @@ int OpenTxEepromInterface::getSize(const ModelData &model) if (model.isEmpty()) return 0; - QByteArray tmp(EESIZE_MAX, 0); - efile->EeFsCreate((uint8_t *) tmp.data(), EESIZE_MAX, board, 255/*version max*/); + QByteArray tmp(Boards::getEEpromSize(Board::BOARD_UNKNOWN), 0); + efile->EeFsCreate((uint8_t *) tmp.data(), Boards::getEEpromSize(Board::BOARD_UNKNOWN), board, 255/*version max*/); OpenTxModelData open9xModel((ModelData &) model, board, 255/*version max*/, getCurrentFirmware()->getVariantNumber()); @@ -398,8 +398,8 @@ int OpenTxEepromInterface::getSize(const GeneralSettings &settings) if (IS_SKY9X(board)) return 0; - QByteArray tmp(EESIZE_MAX, 0); - efile->EeFsCreate((uint8_t *) tmp.data(), EESIZE_MAX, board, 255); + QByteArray tmp(Boards::getEEpromSize(Board::BOARD_UNKNOWN), 0); + efile->EeFsCreate((uint8_t *) tmp.data(), Boards::getEEpromSize(Board::BOARD_UNKNOWN), board, 255); OpenTxGeneralData open9xGeneral((GeneralSettings &) settings, board, 255, getCurrentFirmware()->getVariantNumber()); // open9xGeneral.Dump(); @@ -570,7 +570,9 @@ int OpenTxFirmware::getCapability(::Capability capability) return (IS_ARM(board) ? 1 : 0); case ExtraInputs: return 1; - case ExtendedTrims: + case TrimsRange: + return 125; + case ExtendedTrimsRange: return 500; case Simulation: return 1; @@ -727,7 +729,7 @@ int OpenTxFirmware::getCapability(::Capability capability) QString OpenTxFirmware::getAnalogInputName(unsigned int index) { - if (index < 4) { + if ((int)index < getBoardCapability(board, Board::Sticks)) { const QString sticks[] = { QObject::tr("Rud"), QObject::tr("Ele"), @@ -737,7 +739,7 @@ QString OpenTxFirmware::getAnalogInputName(unsigned int index) return sticks[index]; } - index -= 4; + index -= getBoardCapability(board, Board::Sticks); if (IS_9X(board) || IS_2560(board) || IS_SKY9X(board)) { const QString pots[] = { diff --git a/companion/src/flasheepromdialog.cpp b/companion/src/flasheepromdialog.cpp index 02c4571c7..4621e9e9f 100644 --- a/companion/src/flasheepromdialog.cpp +++ b/companion/src/flasheepromdialog.cpp @@ -227,7 +227,7 @@ void FlashEEpromDialog::on_burnButton_clicked() if (patch) { QString filename = generateProcessUniqueTempFileName("temp.bin"); QFile file(filename); - uint8_t *eeprom = (uint8_t*)malloc(getEEpromSize(getCurrentBoard())); + uint8_t *eeprom = (uint8_t*)malloc(Boards::getEEpromSize(getCurrentBoard())); int eeprom_size = getCurrentEEpromInterface()->save(eeprom, *radioData, 0, getCurrentFirmware()->getVariantNumber()); if (eeprom_size == 0) { return; diff --git a/companion/src/helpers.cpp b/companion/src/helpers.cpp index 3e3609ce9..0a22bd970 100644 --- a/companion/src/helpers.cpp +++ b/companion/src/helpers.cpp @@ -27,6 +27,7 @@ #endif #include "appdata.h" +#include "macros.h" #include "helpers.h" #include "simulatormainwindow.h" #include "storage/sdcard.h" @@ -34,6 +35,8 @@ #include #include +using namespace Helpers; + Stopwatch gStopwatch("global"); const QColor colors[CPN_MAX_CURVES] = { @@ -71,60 +74,6 @@ const QColor colors[CPN_MAX_CURVES] = { QColor(255,127,0), }; -void populateGvSourceCB(QComboBox *b, int value) -{ - QString strings[] = { QObject::tr("---"), QObject::tr("Rud Trim"), QObject::tr("Ele Trim"), QObject::tr("Thr Trim"), QObject::tr("Ail Trim"), QObject::tr("Rot Enc"), QObject::tr("Rud"), QObject::tr("Ele"), QObject::tr("Thr"), QObject::tr("Ail"), QObject::tr("P1"), QObject::tr("P2"), QObject::tr("P3")}; - b->clear(); - for (int i=0; i<= 12; i++) { - b->addItem(strings[i]); - } - b->setCurrentIndex(value); -} - -void populateFileComboBox(QComboBox * b, const QSet & set, const QString & current) -{ - b->clear(); - b->addItem("----"); - - bool added = false; - // Convert set into list and sort it alphabetically case insensitive - QStringList list = QStringList::fromSet(set); - qSort(list.begin(), list.end(), caseInsensitiveLessThan); - foreach (QString entry, list) { - b->addItem(entry); - if (entry == current) { - b->setCurrentIndex(b->count()-1); - added = true; - } - } - - if (!added && !current.isEmpty()) { - b->addItem(current); - b->setCurrentIndex(b->count()-1); - } -} - -void getFileComboBoxValue(QComboBox * b, char * dest, int length) -{ - memset(dest, 0, length+1); - if (b->currentText() != "----") { - strncpy(dest, b->currentText().toLatin1(), length); - } -} - -void populatePhasesCB(QComboBox *b, int value) -{ - for (int i=-getCurrentFirmware()->getCapability(FlightModes); i<=getCurrentFirmware()->getCapability(FlightModes); i++) { - if (i < 0) - b->addItem(QObject::tr("!Flight mode %1").arg(-i-1), i); - else if (i > 0) - b->addItem(QObject::tr("Flight mode %1").arg(i-1), i); - else - b->addItem(QObject::tr("----"), 0); - } - b->setCurrentIndex(value + getCurrentFirmware()->getCapability(FlightModes)); -} - /* * GVarGroup */ @@ -141,7 +90,7 @@ GVarGroup::GVarGroup(QCheckBox * weightGV, QAbstractSpinBox * weightSB, QComboBo lock(true) { if (allowGvars && getCurrentFirmware()->getCapability(Gvars)) { - populateGVCB(*weightCB, weight, model); + Helpers::populateGVCB(*weightCB, weight, model); connect(weightGV, SIGNAL(stateChanged(int)), this, SLOT(gvarCBChanged(int))); connect(weightCB, SIGNAL(currentIndexChanged(int)), this, SLOT(valuesChanged())); } @@ -252,7 +201,7 @@ void CurveGroup::update() curveGVarCB->setChecked(true); if (lastType != CurveReference::CURVE_REF_DIFF && lastType != CurveReference::CURVE_REF_EXPO) { lastType = curve.type; - populateGVCB(*curveValueCB, curve.value, model); + Helpers::populateGVCB(*curveValueCB, curve.value, model); } curveValueCB->show(); curveValueSB->hide(); @@ -370,145 +319,10 @@ void CurveGroup::valuesChanged() } /* - * Helpers + * Helpers namespace functions */ -void populateGvarUseCB(QComboBox *b, unsigned int phase) -{ - b->addItem(QObject::tr("Own value")); - for (int i=0; igetCapability(FlightModes); i++) { - if (i != (int)phase) { - b->addItem(QObject::tr("Flight mode %1 value").arg(i)); - } - } -} - -void populateSwitchCB(QComboBox * b, const RawSwitch & value, const GeneralSettings & generalSettings, SwitchContext context) -{ - Board::Type board = getCurrentBoard(); - RawSwitch item; - - b->clear(); - - if (context != MixesContext && context != GlobalFunctionsContext) { - // !FMx - if (IS_ARM(board)) { - for (int i=-getCurrentFirmware()->getCapability(FlightModes); i<0; i++) { - item = RawSwitch(SWITCH_TYPE_FLIGHT_MODE, i); - b->addItem(item.toString(), item.toValue()); - } - } - } - - if (context != GlobalFunctionsContext) { - for (int i=-getCurrentFirmware()->getCapability(LogicalSwitches); i<0; i++) { - item = RawSwitch(SWITCH_TYPE_VIRTUAL, i); - b->addItem(item.toString(), item.toValue()); - } - } - - for (int i=-getCurrentFirmware()->getCapability(RotaryEncoders); i<0; i++) { - item = RawSwitch(SWITCH_TYPE_ROTARY_ENCODER, i); - b->addItem(item.toString(), item.toValue()); - } - - for (int i = -getBoardCapability(board, Board::NumTrimSwitches); i < 0; i++) { - item = RawSwitch(SWITCH_TYPE_TRIM, i); - b->addItem(item.toString(), item.toValue()); - } - - for (int i=getCurrentFirmware()->getCapability(MultiposPots)-1; i>=0; i--) { - if (generalSettings.potConfig[i] == Board::POT_MULTIPOS_SWITCH) { - for (int j=-getCurrentFirmware()->getCapability(MultiposPotsPositions); j<0; j++) { - item = RawSwitch(SWITCH_TYPE_MULTIPOS_POT, -i*getCurrentFirmware()->getCapability(MultiposPotsPositions)+j); - b->addItem(item.toString(), item.toValue()); - } - } - } - - for (int i=-getCurrentFirmware()->getCapability(SwitchesPositions); i<0; i++) { - item = RawSwitch(SWITCH_TYPE_SWITCH, i); - if (IS_HORUS_OR_TARANIS(board) && !generalSettings.switchPositionAllowedTaranis(i)) { - continue; - } - b->addItem(item.toString(), item.toValue()); - } - - if (context == TimersContext) { - for (int i=0; i<5; i++) { - item = RawSwitch(SWITCH_TYPE_TIMER_MODE, i); - b->addItem(item.toString(), item.toValue()); - } - } - else { - item = RawSwitch(SWITCH_TYPE_NONE); - b->addItem(item.toString(), item.toValue()); - } - - for (int i=1; i<=getCurrentFirmware()->getCapability(SwitchesPositions); i++) { - item = RawSwitch(SWITCH_TYPE_SWITCH, i); - if (IS_HORUS_OR_TARANIS(board) && !generalSettings.switchPositionAllowedTaranis(i)) { - continue; - } - b->addItem(item.toString(), item.toValue()); - } - - for (int i=0; igetCapability(MultiposPots); i++) { - if (generalSettings.potConfig[i] == Board::POT_MULTIPOS_SWITCH) { - for (int j=1; j<=getCurrentFirmware()->getCapability(MultiposPotsPositions); j++) { - item = RawSwitch(SWITCH_TYPE_MULTIPOS_POT, i*getCurrentFirmware()->getCapability(MultiposPotsPositions)+j); - b->addItem(item.toString(), item.toValue()); - } - } - } - - for (int i=1; i <= getBoardCapability(board, Board::NumTrimSwitches); i++) { - item = RawSwitch(SWITCH_TYPE_TRIM, i); - b->addItem(item.toString(), item.toValue()); - } - - for (int i=1; i<=getCurrentFirmware()->getCapability(RotaryEncoders); i++) { - item = RawSwitch(SWITCH_TYPE_ROTARY_ENCODER, i); - b->addItem(item.toString(), item.toValue()); - } - - if (context != GlobalFunctionsContext) { - for (int i=1; i<=getCurrentFirmware()->getCapability(LogicalSwitches); i++) { - item = RawSwitch(SWITCH_TYPE_VIRTUAL, i); - b->addItem(item.toString(), item.toValue()); - } - } - - if (context == SpecialFunctionsContext || context == GlobalFunctionsContext) { - // ON - item = RawSwitch(SWITCH_TYPE_ON); - b->addItem(item.toString(), item.toValue()); - // One - item = RawSwitch(SWITCH_TYPE_ONE, 1); - b->addItem(item.toString(), item.toValue()); - } - - // FMx - if (context != MixesContext && context != GlobalFunctionsContext) { - if (IS_ARM(board)) { - for (int i=1; i<=getCurrentFirmware()->getCapability(FlightModes); i++) { - item = RawSwitch(SWITCH_TYPE_FLIGHT_MODE, i); - b->addItem(item.toString(), item.toValue()); - } - } - } - - for (int i=0; i < b->count(); ++i) { - if (RawSwitch(b->itemData(i).toInt()) == value) { - b->setCurrentIndex(i); - break; - } - } - - b->setMaxVisibleItems(10); -} - -void populateGVCB(QComboBox & b, int value, const ModelData & model) +void Helpers::populateGVCB(QComboBox & b, int value, const ModelData & model) { bool selected = false; @@ -544,146 +358,253 @@ void populateGVCB(QComboBox & b, int value, const ModelData & model) } } -void populateSourceCB(QComboBox * b, const RawSource & source, const GeneralSettings generalSettings, const ModelData * model, unsigned int flags) +void Helpers::populateGvarUseCB(QComboBox * b, unsigned int phase) { - Board::Type board = getCurrentBoard(); - RawSource item; + b->addItem(QObject::tr("Own value")); + for (int i=0; igetCapability(FlightModes); i++) { + if (i != (int)phase) { + b->addItem(QObject::tr("Flight mode %1 value").arg(i)); + } + } +} +void Helpers::populateGvSourceCB(QComboBox * b, int value) +{ + QString strings[] = { QObject::tr("---"), QObject::tr("Rud Trim"), QObject::tr("Ele Trim"), QObject::tr("Thr Trim"), QObject::tr("Ail Trim"), QObject::tr("Rot Enc"), QObject::tr("Rud"), QObject::tr("Ele"), QObject::tr("Thr"), QObject::tr("Ail"), QObject::tr("P1"), QObject::tr("P2"), QObject::tr("P3")}; b->clear(); + for (int i=0; i<= 12; i++) { + b->addItem(strings[i]); + } + b->setCurrentIndex(value); +} + +void Helpers::populatePhasesCB(QComboBox * b, int value) +{ + for (int i=-getCurrentFirmware()->getCapability(FlightModes); i<=getCurrentFirmware()->getCapability(FlightModes); i++) { + if (i < 0) + b->addItem(QObject::tr("!Flight mode %1").arg(-i-1), i); + else if (i > 0) + b->addItem(QObject::tr("Flight mode %1").arg(i-1), i); + else + b->addItem(QObject::tr("----"), 0); + } + b->setCurrentIndex(value + getCurrentFirmware()->getCapability(FlightModes)); +} + +void Helpers::populateFileComboBox(QComboBox * b, const QSet & set, const QString & current) +{ + b->clear(); + b->addItem("----"); + + bool added = false; + // Convert set into list and sort it alphabetically case insensitive + QStringList list = QStringList::fromSet(set); + qSort(list.begin(), list.end(), caseInsensitiveLessThan); + foreach (QString entry, list) { + b->addItem(entry); + if (entry == current) { + b->setCurrentIndex(b->count()-1); + added = true; + } + } + + if (!added && !current.isEmpty()) { + b->addItem(current); + b->setCurrentIndex(b->count()-1); + } +} + +void Helpers::getFileComboBoxValue(QComboBox * b, char * dest, int length) +{ + memset(dest, 0, length+1); + if (b->currentText() != "----") { + strncpy(dest, b->currentText().toLatin1(), length); + } +} + +void Helpers::addRawSwitchItems(QStandardItemModel * itemModel, const RawSwitchType & type, int count, const GeneralSettings * const generalSettings) +{ + // Most RawSwitch() indices are one-based (vs. typical zero); these are exceptions to the rule: + const static QVector rawSwitchIndexBaseZeroTypes = QVector() << SWITCH_TYPE_NONE << SWITCH_TYPE_ON << SWITCH_TYPE_OFF << SWITCH_TYPE_TIMER_MODE; + + int rawIdxAdj = 0; + const Board::Type board = getCurrentBoard(); + int i = (count < 0 ? count : 1); + const int maxCount = (i < 0 ? 0 : count + i); + + // handle exceptions in RawSwitch() index values + if (rawSwitchIndexBaseZeroTypes.contains(type)) + rawIdxAdj = -1; + + for ( ; i < maxCount; ++i) { + if (generalSettings) { + if (type == SWITCH_TYPE_SWITCH && IS_HORUS_OR_TARANIS(board) && !generalSettings->switchPositionAllowedTaranis(abs(i))) + continue; + if (type == SWITCH_TYPE_MULTIPOS_POT) { + int pot = div(abs(i) - 1, getCurrentFirmware()->getCapability(MultiposPotsPositions)).quot; + if (!generalSettings->isPotAvailable(pot) || generalSettings->potConfig[pot] != Board::POT_MULTIPOS_SWITCH) + continue; + } + } + RawSwitch rs(type, i + rawIdxAdj); + QStandardItem * modelItem = new QStandardItem(rs.toString(board, generalSettings)); + modelItem->setData(rs.toValue(), Qt::UserRole); + itemModel->appendRow(modelItem); + } +} + +QStandardItemModel * Helpers::getRawSwitchItemModel(const GeneralSettings * const generalSettings, SwitchContext context) +{ + QStandardItemModel * itemModel = new QStandardItemModel(); + Board::Type board = getCurrentBoard(); + Firmware * fw = getCurrentFirmware(); + + // Descending switch direction: NOT (!) switches + + if (context != MixesContext && context != GlobalFunctionsContext && IS_ARM(board)) { + addRawSwitchItems(itemModel, SWITCH_TYPE_FLIGHT_MODE, -fw->getCapability(FlightModes), generalSettings); + } + if (context != GlobalFunctionsContext) { + addRawSwitchItems(itemModel, SWITCH_TYPE_VIRTUAL, -fw->getCapability(LogicalSwitches), generalSettings); + } + addRawSwitchItems(itemModel, SWITCH_TYPE_ROTARY_ENCODER, -fw->getCapability(RotaryEncoders), generalSettings); + addRawSwitchItems(itemModel, SWITCH_TYPE_TRIM, -getBoardCapability(board, Board::NumTrimSwitches), generalSettings); + addRawSwitchItems(itemModel, SWITCH_TYPE_MULTIPOS_POT, -(fw->getCapability(MultiposPots) * fw->getCapability(MultiposPotsPositions)), generalSettings); + addRawSwitchItems(itemModel, SWITCH_TYPE_SWITCH, -fw->getCapability(SwitchesPositions), generalSettings); + + // Ascending switch direction (including zero) + + if (context == TimersContext) { + addRawSwitchItems(itemModel, SWITCH_TYPE_TIMER_MODE, 5, generalSettings); + } + else { + addRawSwitchItems(itemModel, SWITCH_TYPE_NONE, 1); + } + + addRawSwitchItems(itemModel, SWITCH_TYPE_SWITCH, fw->getCapability(SwitchesPositions), generalSettings); + addRawSwitchItems(itemModel, SWITCH_TYPE_MULTIPOS_POT, fw->getCapability(MultiposPots) * fw->getCapability(MultiposPotsPositions), generalSettings); + addRawSwitchItems(itemModel, SWITCH_TYPE_TRIM, getBoardCapability(board, Board::NumTrimSwitches), generalSettings); + addRawSwitchItems(itemModel, SWITCH_TYPE_ROTARY_ENCODER, fw->getCapability(RotaryEncoders), generalSettings); + if (context != GlobalFunctionsContext) { + addRawSwitchItems(itemModel, SWITCH_TYPE_VIRTUAL, fw->getCapability(LogicalSwitches), generalSettings); + } + if (context != MixesContext && context != GlobalFunctionsContext && IS_ARM(board)) { + addRawSwitchItems(itemModel, SWITCH_TYPE_FLIGHT_MODE, fw->getCapability(FlightModes), generalSettings); + } + if (context == SpecialFunctionsContext || context == GlobalFunctionsContext) { + addRawSwitchItems(itemModel, SWITCH_TYPE_ON, 1); + addRawSwitchItems(itemModel, SWITCH_TYPE_ONE, 1); + } + + return itemModel; +} + +void Helpers::addRawSourceItems(QStandardItemModel * itemModel, const RawSourceType & type, int count, const GeneralSettings * const generalSettings, + const ModelData * const model, const int start, const QList exclude) +{ + for (int i = start; i < start + count; i++) { + if (exclude.contains(i)) + continue; + + RawSource src = RawSource(type, i); + if (model) { + if (type == SOURCE_TYPE_VIRTUAL_INPUT && !model->isInputValid(i)) + continue; + } + if (generalSettings) { + int genAryIdx = 0; + if (type == SOURCE_TYPE_STICK && ((src.isPot(&genAryIdx) && !generalSettings->isPotAvailable(genAryIdx)) || (src.isSlider(&genAryIdx) && !generalSettings->isSliderAvailable(genAryIdx)))) + continue; + } + + QStandardItem * modelItem = new QStandardItem(src.toString(model, generalSettings)); + modelItem->setData(src.toValue(), Qt::UserRole); + itemModel->appendRow(modelItem); + + if (type == SOURCE_TYPE_SWITCH && generalSettings && IS_HORUS_OR_TARANIS(getCurrentBoard()) && !generalSettings->switchSourceAllowedTaranis(i)) { + modelItem->setData(0, Qt::UserRole - 1); // trick to disable an item + } + } +} + +QStandardItemModel * Helpers::getRawSourceItemModel(const GeneralSettings * const generalSettings, const ModelData * const model, unsigned int flags) +{ + QStandardItemModel * itemModel = new QStandardItemModel(); + Board::Type board = getCurrentBoard(); + Firmware * fw = getCurrentFirmware(); if (flags & POPULATE_NONE) { - item = RawSource(SOURCE_TYPE_NONE); - b->addItem(item.toString(model), item.toValue()); + addRawSourceItems(itemModel, SOURCE_TYPE_NONE, 1, generalSettings, model); } if (flags & POPULATE_SCRIPT_OUTPUTS) { - for (int i=0; igetCapability(LuaScripts); i++) { - for (int j=0; jgetCapability(LuaOutputsPerScript); j++) { - item = RawSource(SOURCE_TYPE_LUA_OUTPUT, i*16+j); - b->addItem(item.toString(model), item.toValue()); - } + for (int i=0; i < getCurrentFirmware()->getCapability(LuaScripts); i++) { + addRawSourceItems(itemModel, SOURCE_TYPE_LUA_OUTPUT, fw->getCapability(LuaOutputsPerScript), generalSettings, model, i * 16); } } if (model && (flags & POPULATE_VIRTUAL_INPUTS)) { - int virtualInputs = getCurrentFirmware()->getCapability(VirtualInputs); - for (int i=0; iisInputValid(i)) { - item = RawSource(SOURCE_TYPE_VIRTUAL_INPUT, i); - b->addItem(item.toString(model), item.toValue()); - } - } + addRawSourceItems(itemModel, SOURCE_TYPE_VIRTUAL_INPUT, fw->getCapability(VirtualInputs), generalSettings, model); } if (flags & POPULATE_SOURCES) { int totalSources = CPN_MAX_STICKS + getBoardCapability(board, Board::Pots) + getBoardCapability(board, Board::Sliders) + getBoardCapability(board, Board::MouseAnalogs); - for (int i=0; i < totalSources; i++) { - item = RawSource(SOURCE_TYPE_STICK, i); - // skip unavailable pots and sliders - if (item.isPot() && !generalSettings.isPotAvailable(i-CPN_MAX_STICKS)) - continue; - if (item.isSlider() && !generalSettings.isSliderAvailable(i-CPN_MAX_STICKS-getBoardCapability(board, Board::Pots))) - continue; - - b->addItem(item.toString(model), item.toValue()); - } - for (int i=0; igetCapability(RotaryEncoders); i++) { - item = RawSource(SOURCE_TYPE_ROTARY_ENCODER, i); - b->addItem(item.toString(model), item.toValue()); - } + addRawSourceItems(itemModel, SOURCE_TYPE_STICK, totalSources, generalSettings, model); + addRawSourceItems(itemModel, SOURCE_TYPE_ROTARY_ENCODER, fw->getCapability(RotaryEncoders), generalSettings, model); } if (flags & POPULATE_TRIMS) { - for (int i=0; i < getBoardCapability(board, Board::NumTrims); i++) { - item = RawSource(SOURCE_TYPE_TRIM, i); - b->addItem(item.toString(model), item.toValue()); - } + addRawSourceItems(itemModel, SOURCE_TYPE_TRIM, getBoardCapability(board, Board::NumTrims), generalSettings, model); } if (flags & POPULATE_SOURCES) { - item = RawSource(SOURCE_TYPE_MAX); - b->addItem(item.toString(model), item.toValue()); + addRawSourceItems(itemModel, SOURCE_TYPE_MAX, 1, generalSettings, model); } if (flags & POPULATE_SWITCHES) { - for (int i=0; iaddItem(item.toString(model), item.toValue()); - if (IS_HORUS_OR_TARANIS(board) && !generalSettings.switchSourceAllowedTaranis(i)) { - QModelIndex index = b->model()->index(b->count()-1, 0); - QVariant v(0); - b->model()->setData(index, v, Qt::UserRole - 1); - } - } - - for (int i=0; igetCapability(LogicalSwitches); i++) { - item = RawSource(SOURCE_TYPE_CUSTOM_SWITCH, i); - b->addItem(item.toString(model), item.toValue()); - } + addRawSourceItems(itemModel, SOURCE_TYPE_SWITCH, getBoardCapability(board, Board::Switches), generalSettings, model); + addRawSourceItems(itemModel, SOURCE_TYPE_CUSTOM_SWITCH, fw->getCapability(LogicalSwitches), generalSettings, model); } if (flags & POPULATE_SOURCES) { - for (int i=0; iaddItem(item.toString(model), item.toValue()); - } - - for (int i=0; igetCapability(TrainerInputs); i++) { - item = RawSource(SOURCE_TYPE_PPM, i); - b->addItem(item.toString(model), item.toValue()); - } - - for (int i=0; igetCapability(Outputs); i++) { - item = RawSource(SOURCE_TYPE_CH, i); - b->addItem(item.toString(model), item.toValue()); - } + addRawSourceItems(itemModel, SOURCE_TYPE_CYC, CPN_MAX_CYC, generalSettings, model); + addRawSourceItems(itemModel, SOURCE_TYPE_PPM, fw->getCapability(TrainerInputs), generalSettings, model); + addRawSourceItems(itemModel, SOURCE_TYPE_CH, fw->getCapability(Outputs), generalSettings, model); } if (flags & POPULATE_TELEMETRY) { if (IS_ARM(board)) { - for (int i=0; i<5; ++i) { - item = RawSource(SOURCE_TYPE_SPECIAL, i); - b->addItem(item.toString(model), item.toValue()); - } - for (int i=0; isensorData[i].isAvailable()) { //this conditon must be false if we populate Global Functions where model = 0 - for (int j=0; j<3; ++j) { - item = RawSource(SOURCE_TYPE_TELEMETRY, 3*i+j); - b->addItem(item.toString(model), item.toValue()); - // qDebug() << item.toString(model) << source.toString(model); - } + addRawSourceItems(itemModel, SOURCE_TYPE_SPECIAL, 5, generalSettings, model); + + if (model) { + QList exclude; + for (int i=0; i < CPN_MAX_SENSORS * 3; ++i) { + //this conditon must be false if we populate Global Functions where model = 0 + if (!model->sensorData[div(i, 3).quot].isAvailable()) + exclude << i; } + if (exclude.size() < CPN_MAX_SENSORS * 3) + addRawSourceItems(itemModel, SOURCE_TYPE_TELEMETRY, CPN_MAX_SENSORS * 3, generalSettings, model, 0, exclude); } } else { - for (int i=0; i<(flags & POPULATE_TELEMETRYEXT ? TELEMETRY_SOURCES_STATUS_COUNT : TELEMETRY_SOURCES_COUNT); i++) { - if (i==TELEMETRY_SOURCE_TX_TIME && !getCurrentFirmware()->getCapability(RtcTime)) - continue; - if (i==TELEMETRY_SOURCE_SWR && !getCurrentFirmware()->getCapability(SportTelemetry)) - continue; - if (i==TELEMETRY_SOURCE_TIMER3 && !IS_ARM(board)) - continue; - item = RawSource(SOURCE_TYPE_TELEMETRY, i); - b->addItem(item.toString(model), item.toValue()); - } + QList exclude; + if (!fw->getCapability(RtcTime)) + exclude << TELEMETRY_SOURCE_TX_TIME; + if (!fw->getCapability(SportTelemetry)) + exclude << TELEMETRY_SOURCE_SWR; + if (!IS_ARM(board)) + exclude << TELEMETRY_SOURCE_TIMER3; + int count = ((flags & POPULATE_TELEMETRYEXT) ? TELEMETRY_SOURCES_STATUS_COUNT : TELEMETRY_SOURCES_COUNT); + addRawSourceItems(itemModel, SOURCE_TYPE_TELEMETRY, count, generalSettings, model, 0, exclude); } } if (flags & POPULATE_GVARS) { - for (int i=0; igetCapability(Gvars); i++) { - item = RawSource(SOURCE_TYPE_GVAR, i); - b->addItem(item.toString(model), item.toValue()); - } + addRawSourceItems(itemModel, SOURCE_TYPE_GVAR, fw->getCapability(Gvars), generalSettings, model); } - for (int i=0; i < b->count(); ++i) { - if (RawSource(b->itemData(i).toInt()) == source) { - b->setCurrentIndex(i); - break; - } - } - - b->setMaxVisibleItems(10); + return itemModel; } QString image2qstring(QImage image) @@ -871,6 +792,7 @@ QPixmap makePixMap(const QImage & image) return QPixmap::fromImage(result); } + int version2index(const QString & version) { int result = 999; @@ -887,8 +809,10 @@ int version2index(const QString & version) return result; } -QString index2version(int index) +const QString index2version(int index) { + QString result; + QString templt("%1.%2.%3"); if (index >= 19900000) { int nightly = index % 1000; index /= 1000; @@ -896,22 +820,19 @@ QString index2version(int index) index /= 100; int minor = index % 100; int major = index / 100; - QString result = QString("%1.%2.%3").arg(major).arg(minor).arg(revision); + result = templt.arg(major).arg(minor).arg(revision); if (nightly > 0 && nightly < 999) { - result += QString("N%1").arg(nightly); + result += "N" + QString::number(nightly); } - return result; } else if (index >= 19900) { int revision = index % 100; index /= 100; int minor = index % 100; int major = index / 100; - return QString("%1.%2.%3").arg(major).arg(minor).arg(revision); - } - else { - return QString(); + result = templt.arg(major).arg(minor).arg(revision); } + return result; } bool qunlink(const QString & fileName) diff --git a/companion/src/helpers.h b/companion/src/helpers.h index c9a0b5170..24e2375b2 100644 --- a/companion/src/helpers.h +++ b/companion/src/helpers.h @@ -29,6 +29,7 @@ #include #include #include +#include extern const QColor colors[CPN_MAX_CURVES]; @@ -51,11 +52,6 @@ extern const QColor colors[CPN_MAX_CURVES]; #define TRIM_MODE_NONE 0x1F // 0b11111 -void populateGvSourceCB(QComboBox *b, int value); -void populateFileComboBox(QComboBox * b, const QSet & set, const QString & current); -void getFileComboBoxValue(QComboBox * b, char * dest, int length); -void populateRotEncCB(QComboBox *b, int value, int renumber); - QString getTheme(); class CompanionIcon: public QIcon { @@ -117,19 +113,6 @@ class CurveGroup : public QObject { int lastType; }; -enum SwitchContext -{ - LogicalSwitchesContext, - SpecialFunctionsContext, - GlobalFunctionsContext, - TimersContext, - MixesContext -}; - -void populateSwitchCB(QComboBox *b, const RawSwitch & value, const GeneralSettings & generalSettings, SwitchContext context); - -void populatePhasesCB(QComboBox *b, int value); -void populateGvarUseCB(QComboBox *b, unsigned int phase); #define POPULATE_NONE (1<<0) #define POPULATE_SOURCES (1<<1) @@ -144,8 +127,35 @@ void populateGvarUseCB(QComboBox *b, unsigned int phase); #define GVARS_VARIANT 0x0001 #define FRSKY_VARIANT 0x0002 -void populateGVCB(QComboBox & b, int value, const ModelData & model); -void populateSourceCB(QComboBox *b, const RawSource &source, const GeneralSettings generalSettings, const ModelData * model, unsigned int flags); +namespace Helpers +{ + enum SwitchContext + { + LogicalSwitchesContext, + SpecialFunctionsContext, + GlobalFunctionsContext, + TimersContext, + MixesContext + }; + + void addRawSwitchItems(QStandardItemModel * itemModel, const RawSwitchType & type, int count, const GeneralSettings * const generalSettings = NULL); + QStandardItemModel * getRawSwitchItemModel(const GeneralSettings * const generalSettings = NULL, SwitchContext context = LogicalSwitchesContext); + + void addRawSourceItems(QStandardItemModel * itemModel, const RawSourceType & type, int count, const GeneralSettings * const generalSettings = NULL, + const ModelData * const model = NULL, const int start = 0, const QList exclude = QList()); + QStandardItemModel * getRawSourceItemModel(const GeneralSettings * const generalSettings = NULL, const ModelData * const model = NULL, unsigned int flags = 0); + + void populateGvarUseCB(QComboBox *b, unsigned int phase); + void populateGvSourceCB(QComboBox *b, int value); + void populatePhasesCB(QComboBox *b, int value); + void populateGVCB(QComboBox & b, int value, const ModelData & model); + + void populateFileComboBox(QComboBox * b, const QSet & set, const QString & current); + void getFileComboBoxValue(QComboBox * b, char * dest, int length); +} // namespace Helpers + +// TODO : move to Helpers namespace + QString image2qstring(QImage image); int findmult(float value, float base); @@ -162,14 +172,14 @@ void startSimulation(QWidget * parent, RadioData & radioData, int modelIdx); QPixmap makePixMap(const QImage & image); int version2index(const QString & version); -QString index2version(int index); +const QString index2version(int index); class QTimeS : public QTime { public: - QTimeS(int s) { int h = s/3600; s %= 3600; int m = s/60; s %=60; setHMS(h, m, s); }; - QTimeS(const QTime & q) : QTime(q) {}; - int seconds() const { return hour()*3600 + minute()*60 + second(); }; + QTimeS(int s) { int h = s/3600; s %= 3600; int m = s/60; s %=60; setHMS(h, m, s); } + QTimeS(const QTime & q) : QTime(q) {} + int seconds() const { return hour()*3600 + minute()*60 + second(); } }; bool qunlink(const QString & fileName); @@ -186,7 +196,7 @@ bool caseInsensitiveLessThan(const QString &s1, const QString &s2); class GpsCoord { public: - GpsCoord(): latitude(0), longitude(0) {}; + GpsCoord(): latitude(0), longitude(0) {} double latitude; // Precede South latitudes and West longitudes with a minus sign. Latitudes range from -90 to 90. double longitude; // Longitudes range from -180 to 180. }; @@ -194,7 +204,7 @@ public: class GpsGlitchFilter { public: - GpsGlitchFilter() : lastValid(false), glitchCount(0) {}; + GpsGlitchFilter() : lastValid(false), glitchCount(0) {} bool isGlitch(GpsCoord coord); private: @@ -207,7 +217,7 @@ private: class GpsLatLonFilter { public: - GpsLatLonFilter() {}; + GpsLatLonFilter() {} bool isValid(GpsCoord coord); private: @@ -248,7 +258,7 @@ public: name(name), total(0) { timer.start(); }; - ~Stopwatch() {}; + ~Stopwatch() {} void restart() { total = 0; diff --git a/companion/src/modeledit/customfunctions.cpp b/companion/src/modeledit/customfunctions.cpp index 36849cd18..559b5a245 100644 --- a/companion/src/modeledit/customfunctions.cpp +++ b/companion/src/modeledit/customfunctions.cpp @@ -73,6 +73,13 @@ CustomFunctionsPanel::CustomFunctionsPanel(QWidget * parent, ModelData * model, lock = true; int num_fsw = model ? firmware->getCapability(CustomFunctions) : firmware->getCapability(GlobalFunctions); + rawSwitchItemModel = Helpers::getRawSwitchItemModel(&generalSettings, model ? Helpers::SpecialFunctionsContext : Helpers::GlobalFunctionsContext); + rawSwitchItemModel->setParent(this); + rawSrcInputsItemModel = Helpers::getRawSourceItemModel(&generalSettings, model, POPULATE_NONE|POPULATE_SOURCES|POPULATE_VIRTUAL_INPUTS|POPULATE_TRIMS|POPULATE_SWITCHES); + rawSrcInputsItemModel->setParent(this); + rawSrcAllItemModel = Helpers::getRawSourceItemModel(&generalSettings, model, POPULATE_NONE|POPULATE_SOURCES|POPULATE_VIRTUAL_INPUTS|POPULATE_SWITCHES|POPULATE_GVARS|POPULATE_TRIMS|POPULATE_TELEMETRY|POPULATE_TELEMETRYEXT|POPULATE_SCRIPT_OUTPUTS); + rawSrcAllItemModel->setParent(this); + if (!firmware->getCapability(VoicesAsNumbers)) { tracksSet = getFilesSet(getSoundsPath(generalSettings), QStringList() << "*.wav" << "*.WAV", firmware->getCapability(VoicesMaxLength)); for (int i=0; isetModel(rawSwitchItemModel); + fswtchSwtch[i]->setCurrentIndex(fswtchSwtch[i]->findData(functions[i].swtch.toValue())); fswtchSwtch[i]->setProperty("index", i); - populateSwitchCB(fswtchSwtch[i], functions[i].swtch, generalSettings, model ? SpecialFunctionsContext : GlobalFunctionsContext); fswtchSwtch[i]->setSizePolicy(QSizePolicy::Maximum, QSizePolicy::Minimum); fswtchSwtch[i]->setMaxVisibleItems(10); connect(fswtchSwtch[i], SIGNAL(currentIndexChanged(int)), this, SLOT(customFunctionEdited())); @@ -133,8 +141,14 @@ CustomFunctionsPanel::CustomFunctionsPanel(QWidget * parent, ModelData * model, // The function fswtchFunc[i] = new QComboBox(this); + if (!i) { + populateFuncCB(fswtchFunc[i], functions[i].func); + } + else { + fswtchFunc[i]->setModel(fswtchFunc[0]->model()); + fswtchFunc[i]->setCurrentIndex(fswtchFunc[i]->findData(functions[i].func)); + } fswtchFunc[i]->setProperty("index", i); - populateFuncCB(fswtchFunc[i], functions[i].func); connect(fswtchFunc[i], SIGNAL(currentIndexChanged(int)), this, SLOT(functionEdited())); tableLayout->addWidget(i, 2, fswtchFunc[i]); // s1.report("func"); @@ -216,6 +230,7 @@ CustomFunctionsPanel::CustomFunctionsPanel(QWidget * parent, ModelData * model, repeatLayout->addWidget(fswtchEnable[i], i+1); connect(fswtchEnable[i], SIGNAL(stateChanged(int)), this, SLOT(customFunctionEdited())); } + s1.report("add items"); disableMouseScrolling(); @@ -367,7 +382,7 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) cfn.adjustMode = (AssignFunc)fswtchGVmode[i]->currentIndex(); } - if (cfn.swtch.toValue()){ + if (cfn.swtch.toValue()) { if (func>=FuncOverrideCH1 && func<=FuncOverrideCH32) { if (model) { @@ -432,7 +447,7 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) fswtchParamTime[i]->setMinimumTime(QTime(0, 0, 0)); fswtchParamTime[i]->setMaximumTime(firmware->getMaxTimerStart()); fswtchParamTime[i]->setTime(QTimeS(cfn.param)); - widgetsMask |= CUSTOM_FUNCTION_TIME_PARAM + CUSTOM_FUNCTION_ENABLE; + widgetsMask |= CUSTOM_FUNCTION_TIME_PARAM | CUSTOM_FUNCTION_ENABLE; } else if (func>=FuncSetFailsafeInternalModule && func<=FuncBindExternalModule) { widgetsMask |= CUSTOM_FUNCTION_ENABLE; @@ -491,9 +506,9 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) else { widgetsMask |= CUSTOM_FUNCTION_FILE_PARAM; if (modified) { - getFileComboBoxValue(fswtchParamArmT[i], cfn.paramarm, firmware->getCapability(VoicesMaxLength)); + Helpers::getFileComboBoxValue(fswtchParamArmT[i], cfn.paramarm, firmware->getCapability(VoicesMaxLength)); } - populateFileComboBox(fswtchParamArmT[i], tracksSet, cfn.paramarm); + Helpers::populateFileComboBox(fswtchParamArmT[i], tracksSet, cfn.paramarm); if (fswtchParamArmT[i]->currentText() != "----") { widgetsMask |= CUSTOM_FUNCTION_PLAY; } @@ -502,9 +517,9 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) else if (func==FuncBackgroundMusic) { widgetsMask |= CUSTOM_FUNCTION_FILE_PARAM; if (modified) { - getFileComboBoxValue(fswtchParamArmT[i], cfn.paramarm, firmware->getCapability(VoicesMaxLength)); + Helpers::getFileComboBoxValue(fswtchParamArmT[i], cfn.paramarm, firmware->getCapability(VoicesMaxLength)); } - populateFileComboBox(fswtchParamArmT[i], tracksSet, cfn.paramarm); + Helpers::populateFileComboBox(fswtchParamArmT[i], tracksSet, cfn.paramarm); if (fswtchParamArmT[i]->currentText() != "----") { widgetsMask |= CUSTOM_FUNCTION_PLAY; } @@ -525,9 +540,9 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) else if (func==FuncPlayScript) { widgetsMask |= CUSTOM_FUNCTION_FILE_PARAM; if (modified) { - getFileComboBoxValue(fswtchParamArmT[i], cfn.paramarm, 8); + Helpers::getFileComboBoxValue(fswtchParamArmT[i], cfn.paramarm, 8); } - populateFileComboBox(fswtchParamArmT[i], scriptsSet, cfn.paramarm); + Helpers::populateFileComboBox(fswtchParamArmT[i], scriptsSet, cfn.paramarm); } else if (func==FuncBacklight && IS_TARANIS_PLUS(getCurrentBoard())) { if (modified) @@ -584,7 +599,8 @@ void CustomFunctionsPanel::fswPaste() CustomFunctionData *fsw = &functions[selectedFunction]; memcpy(fsw, fswData.constData(), sizeof(CustomFunctionData)); lock = true; - populateSwitchCB(fswtchSwtch[selectedFunction], functions[selectedFunction].swtch, generalSettings, model ? SpecialFunctionsContext : GlobalFunctionsContext); + fswtchSwtch[selectedFunction]->setModel(rawSwitchItemModel); + fswtchSwtch[selectedFunction]->setCurrentIndex(fswtchSwtch[selectedFunction]->findData(functions[selectedFunction].swtch.toValue())); populateFuncCB(fswtchFunc[selectedFunction], functions[selectedFunction].func); populateGVmodeCB(fswtchGVmode[selectedFunction], functions[selectedFunction].adjustMode); populateFuncParamCB(fswtchParamT[selectedFunction], functions[selectedFunction].func, functions[selectedFunction].param, functions[selectedFunction].adjustMode); @@ -599,7 +615,8 @@ void CustomFunctionsPanel::fswDelete() functions[selectedFunction].clear(); // TODO update switch and func lock = true; - populateSwitchCB(fswtchSwtch[selectedFunction], functions[selectedFunction].swtch, generalSettings, model ? SpecialFunctionsContext : GlobalFunctionsContext); + fswtchSwtch[selectedFunction]->setModel(rawSwitchItemModel); + fswtchSwtch[selectedFunction]->setCurrentIndex(fswtchSwtch[selectedFunction]->findData(functions[selectedFunction].swtch.toValue())); populateFuncCB(fswtchFunc[selectedFunction], functions[selectedFunction].func); refreshCustomFunction(selectedFunction); lock = false; @@ -699,18 +716,22 @@ void CustomFunctionsPanel::populateFuncParamCB(QComboBox *b, uint function, unsi CustomFunctionData::populateResetParams(model, b, value); } else if (function==FuncVolume) { - populateSourceCB(b, RawSource(value), generalSettings, model, POPULATE_NONE|POPULATE_SOURCES|POPULATE_VIRTUAL_INPUTS|POPULATE_TRIMS|POPULATE_SWITCHES); + b->setModel(rawSrcInputsItemModel); + b->setCurrentIndex(b->findData(value)); } else if (function==FuncPlayValue) { - populateSourceCB(b, RawSource(value), generalSettings, model, POPULATE_NONE|POPULATE_SOURCES|POPULATE_VIRTUAL_INPUTS|POPULATE_SWITCHES|POPULATE_GVARS|POPULATE_TRIMS|POPULATE_TELEMETRY|POPULATE_TELEMETRYEXT|POPULATE_SCRIPT_OUTPUTS); + b->setModel(rawSrcAllItemModel); + b->setCurrentIndex(b->findData(value)); } else if (function>=FuncAdjustGV1 && function<=FuncAdjustGVLast) { switch (adjustmode) { case 1: - populateSourceCB(b, RawSource(value), generalSettings, model, POPULATE_NONE|POPULATE_SOURCES|POPULATE_VIRTUAL_INPUTS|POPULATE_TRIMS|POPULATE_SWITCHES); + b->setModel(rawSrcInputsItemModel); + b->setCurrentIndex(b->findData(value)); break; case 2: - populateSourceCB(b, RawSource(value), generalSettings, model, POPULATE_GVARS); + b->setModel(Helpers::getRawSourceItemModel(&generalSettings, model, POPULATE_GVARS)); + b->setCurrentIndex(b->findData(value)); break; } } diff --git a/companion/src/modeledit/customfunctions.h b/companion/src/modeledit/customfunctions.h index 66f8e9229..98cf17e69 100644 --- a/companion/src/modeledit/customfunctions.h +++ b/companion/src/modeledit/customfunctions.h @@ -74,6 +74,9 @@ class CustomFunctionsPanel : public GenericPanel void populateFuncCB(QComboBox *b, unsigned int value); void populateGVmodeCB(QComboBox *b, unsigned int value); void populateFuncParamCB(QComboBox *b, uint function, unsigned int value, unsigned int adjustmode=0); + QStandardItemModel * rawSwitchItemModel; + QStandardItemModel * rawSrcInputsItemModel; + QStandardItemModel * rawSrcAllItemModel; QSet tracksSet; QSet scriptsSet; diff --git a/companion/src/modeledit/expodialog.cpp b/companion/src/modeledit/expodialog.cpp index 576558e72..3b56eee12 100644 --- a/companion/src/modeledit/expodialog.cpp +++ b/companion/src/modeledit/expodialog.cpp @@ -60,7 +60,8 @@ ExpoDialog::ExpoDialog(QWidget *parent, ModelData & model, ExpoData *expoData, G curveGroup = new CurveGroup(ui->curveTypeCB, ui->curveGVarCB, ui->curveValueCB, ui->curveValueSB, ed->curve, model, firmware->getCapability(HasInputDiff) ? 0 : (HIDE_DIFF | HIDE_NEGATIVE_CURVES)); - populateSwitchCB(ui->switchesCB, ed->swtch, generalSettings, MixesContext); + ui->switchesCB->setModel(Helpers::getRawSwitchItemModel(&generalSettings, Helpers::MixesContext)); + ui->switchesCB->setCurrentIndex(ui->switchesCB->findData(ed->swtch.toValue())); ui->sideCB->setCurrentIndex(ed->mode-1); @@ -90,8 +91,8 @@ ExpoDialog::ExpoDialog(QWidget *parent, ModelData & model, ExpoData *expoData, G if (firmware->getCapability(VirtualInputs)) { ui->inputName->setMaxLength(firmware->getCapability(InputsLength)); - populateSourceCB(ui->sourceCB, ed->srcRaw, generalSettings, &model, POPULATE_NONE | POPULATE_SOURCES | - POPULATE_SWITCHES | POPULATE_TRIMS | POPULATE_TELEMETRY); + ui->sourceCB->setModel(Helpers::getRawSourceItemModel(&generalSettings, &model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SWITCHES | POPULATE_TRIMS | POPULATE_TELEMETRY)); + ui->sourceCB->setCurrentIndex(ui->sourceCB->findData(ed->srcRaw.toValue())); ui->sourceCB->removeItem(0); ui->inputName->setValidator(new QRegExpValidator(rx, this)); ui->inputName->setText(inputName); diff --git a/companion/src/modeledit/flightmodes.cpp b/companion/src/modeledit/flightmodes.cpp index b956d51d5..d046f2aae 100644 --- a/companion/src/modeledit/flightmodes.cpp +++ b/companion/src/modeledit/flightmodes.cpp @@ -50,7 +50,8 @@ FlightModePanel::FlightModePanel(QWidget * parent, ModelData & model, int phaseI // Phase switch if (phaseIdx > 0) { - populateSwitchCB(ui->swtch, phase.swtch, generalSettings, MixesContext); + ui->swtch->setModel(Helpers::getRawSwitchItemModel(&generalSettings, Helpers::MixesContext)); + ui->swtch->setCurrentIndex(ui->swtch->findData(phase.swtch.toValue())); connect(ui->swtch, SIGNAL(currentIndexChanged(int)), this, SLOT(phaseSwitch_currentIndexChanged(int))); } else { @@ -74,7 +75,7 @@ FlightModePanel::FlightModePanel(QWidget * parent, ModelData & model, int phaseI ui->fadeIn->setDisabled(true); ui->fadeOut->setDisabled(true); } - + // The trims QString labels[CPN_MAX_STICKS]; for(int i=0; i < CPN_MAX_STICKS; i++) { @@ -129,7 +130,7 @@ FlightModePanel::FlightModePanel(QWidget * parent, ModelData & model, int phaseI // RE link to another RE reUse[i] = new QComboBox(ui->reGB); reUse[i]->setProperty("index", i); - populateGvarUseCB(reUse[i], phaseIdx); + Helpers::populateGvarUseCB(reUse[i], phaseIdx); if (phase.rotaryEncoders[i] > 1024) { reUse[i]->setCurrentIndex(phase.rotaryEncoders[i] - 1024); } @@ -171,7 +172,7 @@ FlightModePanel::FlightModePanel(QWidget * parent, ModelData & model, int phaseI // GVar link to another GVar gvUse[i] = new QComboBox(ui->gvGB); gvUse[i]->setProperty("index", i); - populateGvarUseCB(gvUse[i], phaseIdx); + Helpers::populateGvarUseCB(gvUse[i], phaseIdx); if (phase.gvars[i] > 1024) { gvUse[i]->setCurrentIndex(phase.gvars[i] - 1024); } @@ -185,7 +186,7 @@ FlightModePanel::FlightModePanel(QWidget * parent, ModelData & model, int phaseI gvValues[i]->setMinimum(-1024); gvValues[i]->setMaximum(1024); gvLayout->addWidget(gvValues[i], i, col++, 1, 1); - + // Popups if (IS_TARANIS(board) && phaseIdx == 0) { gvPopups[i] = new QCheckBox(ui->gvGB); @@ -219,9 +220,9 @@ void FlightModePanel::update() ui->fadeOut->setValue(float(phase.fadeOut)/scale); for (int i=0; i<4; i++) { - int trimsMax = firmware->getCapability(ExtendedTrims); + int trimsMax = firmware->getCapability(ExtendedTrimsRange); if (trimsMax == 0 || !model->extendedTrims) { - trimsMax = 125; + trimsMax = firmware->getCapability(TrimsRange); } trimsSlider[i]->setRange(-trimsMax, +trimsMax); trimsValue[i]->setRange(-trimsMax, +trimsMax); @@ -244,7 +245,7 @@ void FlightModePanel::update() } } - for (int i=0; isetDisabled(false); int idx = phase.rotaryEncoders[i]; FlightModeData *phasere = &phase; diff --git a/companion/src/modeledit/heli.cpp b/companion/src/modeledit/heli.cpp index 5b9f27399..dfcf32c0e 100644 --- a/companion/src/modeledit/heli.cpp +++ b/companion/src/modeledit/heli.cpp @@ -28,6 +28,9 @@ HeliPanel::HeliPanel(QWidget *parent, ModelData & model, GeneralSettings & gener { ui->setupUi(this); + rawSourceItemModel = Helpers::getRawSourceItemModel(&generalSettings, &model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_VIRTUAL_INPUTS | POPULATE_SWITCHES | POPULATE_TRIMS); + rawSourceItemModel->setParent(this); + connect(ui->swashType, SIGNAL(currentIndexChanged(int)), this, SLOT(edited())); connect(ui->swashRingVal, SIGNAL(editingFinished()), this, SLOT(edited())); connect(ui->swashCollectiveSource, SIGNAL(currentIndexChanged(int)), this, SLOT(edited())); @@ -68,11 +71,14 @@ void HeliPanel::update() lock = true; ui->swashType->setCurrentIndex(model->swashRingData.type); - populateSourceCB(ui->swashCollectiveSource, model->swashRingData.collectiveSource, generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_VIRTUAL_INPUTS | POPULATE_SWITCHES | POPULATE_TRIMS); + ui->swashCollectiveSource->setModel(rawSourceItemModel); + ui->swashCollectiveSource->setCurrentIndex(ui->swashCollectiveSource->findData(model->swashRingData.collectiveSource.toValue())); ui->swashRingVal->setValue(model->swashRingData.value); if (firmware->getCapability(VirtualInputs)) { - populateSourceCB(ui->swashElevatorSource, model->swashRingData.elevatorSource, generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_VIRTUAL_INPUTS | POPULATE_SWITCHES | POPULATE_TRIMS); - populateSourceCB(ui->swashAileronSource, model->swashRingData.aileronSource, generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_VIRTUAL_INPUTS | POPULATE_SWITCHES | POPULATE_TRIMS); + ui->swashElevatorSource->setModel(rawSourceItemModel); + ui->swashElevatorSource->setCurrentIndex(ui->swashElevatorSource->findData(model->swashRingData.elevatorSource.toValue())); + ui->swashAileronSource->setModel(rawSourceItemModel); + ui->swashAileronSource->setCurrentIndex(ui->swashAileronSource->findData(model->swashRingData.aileronSource.toValue())); ui->swashElevatorWeight->setValue(model->swashRingData.elevatorWeight); ui->swashAileronWeight->setValue(model->swashRingData.aileronWeight); ui->swashCollectiveWeight->setValue(model->swashRingData.collectiveWeight); diff --git a/companion/src/modeledit/heli.h b/companion/src/modeledit/heli.h index dfcb0a666..a6abb1d98 100644 --- a/companion/src/modeledit/heli.h +++ b/companion/src/modeledit/heli.h @@ -41,6 +41,7 @@ class HeliPanel : public ModelPanel private: Ui::Heli *ui; + QStandardItemModel * rawSourceItemModel; }; #endif // _HELI_H_ diff --git a/companion/src/modeledit/logicalswitches.cpp b/companion/src/modeledit/logicalswitches.cpp index 44629ca18..c60616633 100644 --- a/companion/src/modeledit/logicalswitches.cpp +++ b/companion/src/modeledit/logicalswitches.cpp @@ -28,6 +28,11 @@ LogicalSwitchesPanel::LogicalSwitchesPanel(QWidget * parent, ModelData & model, Stopwatch s1("LogicalSwitchesPanel"); int channelsMax = model.getChannelsMax(true); + rawSwitchItemModel = Helpers::getRawSwitchItemModel(&generalSettings, Helpers::LogicalSwitchesContext); + rawSwitchItemModel->setParent(this); + int srcFlags = POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | POPULATE_TELEMETRY | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0); + rawSourceItemModel = Helpers::getRawSourceItemModel(&generalSettings, &model, srcFlags); + rawSourceItemModel->setParent(this); QStringList headerLabels; headerLabels << "#" << tr("Function") << tr("V1") << tr("V2") << tr("AND Switch"); @@ -309,7 +314,6 @@ void LogicalSwitchesPanel::setSwitchWidgetVisibility(int i) } else { mask = DELAY_ENABLED | DURATION_ENABLED; - switch (model->logicalSw[i].getFunctionFamily()) { case LS_FAMILY_VOFS: @@ -317,7 +321,8 @@ void LogicalSwitchesPanel::setSwitchWidgetVisibility(int i) mask |= SOURCE1_VISIBLE; RawSource source = RawSource(model->logicalSw[i].val1); RawSourceRange range = source.getRange(model, generalSettings, model->logicalSw[i].getRangeFlags()); - populateSourceCB(cswitchSource1[i], source, generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | POPULATE_TELEMETRY | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0)); + cswitchSource1[i]->setModel(rawSourceItemModel); + cswitchSource1[i]->setCurrentIndex(cswitchSource1[i]->findData(source.toValue())); cswitchOffset[i]->setDecimals(range.decimals); cswitchOffset[i]->setSingleStep(range.step); if (source.isTimeBased()) { @@ -341,19 +346,22 @@ void LogicalSwitchesPanel::setSwitchWidgetVisibility(int i) cswitchOffset[i]->setMaximum(range.max); cswitchOffset[i]->setValue(range.step*(model->logicalSw[i].val2/* TODO+source.getRawOffset(model)*/)+range.offset); } + break; } - case LS_FAMILY_STICKY: - // no break + case LS_FAMILY_STICKY: // no break case LS_FAMILY_VBOOL: mask |= SOURCE1_VISIBLE | SOURCE2_VISIBLE; - populateSwitchCB(cswitchSource1[i], RawSwitch(model->logicalSw[i].val1), generalSettings, LogicalSwitchesContext); - populateSwitchCB(cswitchSource2[i], RawSwitch(model->logicalSw[i].val2), generalSettings, LogicalSwitchesContext); + cswitchSource1[i]->setModel(rawSwitchItemModel); + cswitchSource1[i]->setCurrentIndex(cswitchSource1[i]->findData(model->logicalSw[i].val1)); + cswitchSource2[i]->setModel(rawSwitchItemModel); + cswitchSource2[i]->setCurrentIndex(cswitchSource2[i]->findData(model->logicalSw[i].val2)); break; case LS_FAMILY_EDGE: mask |= SOURCE1_VISIBLE | VALUE2_VISIBLE | VALUE3_VISIBLE; mask &= ~DELAY_ENABLED; - populateSwitchCB(cswitchSource1[i], RawSwitch(model->logicalSw[i].val1), generalSettings, LogicalSwitchesContext); + cswitchSource1[i]->setModel(rawSwitchItemModel); + cswitchSource1[i]->setCurrentIndex(cswitchSource1[i]->findData(model->logicalSw[i].val1)); updateTimerParam(cswitchOffset[i], model->logicalSw[i].val2, 0.0); updateTimerParam(cswitchOffset2[i], model->logicalSw[i].val2+model->logicalSw[i].val3, ValToTim(TimToVal(cswitchOffset[i]->value())-1)); cswitchOffset2[i]->setSpecialValueText(tr("(instant)")); @@ -366,13 +374,16 @@ void LogicalSwitchesPanel::setSwitchWidgetVisibility(int i) break; case LS_FAMILY_VCOMP: mask |= SOURCE1_VISIBLE | SOURCE2_VISIBLE; - populateSourceCB(cswitchSource1[i], RawSource(model->logicalSw[i].val1), generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | POPULATE_TELEMETRY | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0)); - populateSourceCB(cswitchSource2[i], RawSource(model->logicalSw[i].val2), generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | POPULATE_TELEMETRY | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0)); + cswitchSource1[i]->setModel(rawSourceItemModel); + cswitchSource1[i]->setCurrentIndex(cswitchSource1[i]->findData(model->logicalSw[i].val1)); + cswitchSource2[i]->setModel(rawSourceItemModel); + cswitchSource2[i]->setCurrentIndex(cswitchSource2[i]->findData(model->logicalSw[i].val2)); break; case LS_FAMILY_TIMER: mask |= VALUE1_VISIBLE | VALUE2_VISIBLE; updateTimerParam(cswitchValue[i], model->logicalSw[i].val1, 0.1); updateTimerParam(cswitchOffset[i], model->logicalSw[i].val2, 0.1); + break; } } @@ -445,7 +456,8 @@ void LogicalSwitchesPanel::populateAndSwitchCB(QComboBox *b, const RawSwitch & v } if (IS_ARM(firmware->getBoard())) { - populateSwitchCB(b, value, generalSettings, LogicalSwitchesContext); + b->setModel(rawSwitchItemModel); + b->setCurrentIndex(b->findData(value.toValue())); } else { RawSwitch item; diff --git a/companion/src/modeledit/logicalswitches.h b/companion/src/modeledit/logicalswitches.h index ea7ab1e56..32464dbaf 100644 --- a/companion/src/modeledit/logicalswitches.h +++ b/companion/src/modeledit/logicalswitches.h @@ -58,6 +58,8 @@ class LogicalSwitchesPanel : public ModelPanel QDoubleSpinBox * cswitchDelay[CPN_MAX_CSW]; QComboBox * cswitchSource1[CPN_MAX_CSW]; QComboBox * cswitchSource2[CPN_MAX_CSW]; + QStandardItemModel * rawSwitchItemModel; + QStandardItemModel * rawSourceItemModel; void setSwitchWidgetVisibility(int i); int selectedSwitch; diff --git a/companion/src/modeledit/mixerdialog.cpp b/companion/src/modeledit/mixerdialog.cpp index e061b74de..635e7cc43 100644 --- a/companion/src/modeledit/mixerdialog.cpp +++ b/companion/src/modeledit/mixerdialog.cpp @@ -42,8 +42,8 @@ MixerDialog::MixerDialog(QWidget *parent, ModelData & model, MixData *mixdata, G this->setWindowTitle(tr("DEST -> CH%1").arg(md->destCh)); - populateSourceCB(ui->sourceCB, md->srcRaw, generalSettings, &model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | - POPULATE_VIRTUAL_INPUTS | POPULATE_SWITCHES | POPULATE_TRIMS); + ui->sourceCB->setModel(Helpers::getRawSourceItemModel(&generalSettings, &model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_SWITCHES | POPULATE_TRIMS)); + ui->sourceCB->setCurrentIndex(ui->sourceCB->findData(md->srcRaw.toValue())); ui->sourceCB->removeItem(0); int limit = firmware->getCapability(OffsetWeight); @@ -103,7 +103,8 @@ MixerDialog::MixerDialog(QWidget *parent, ModelData & model, MixData *mixdata, G } } - populateSwitchCB(ui->switchesCB, md->swtch, generalSettings, MixesContext); + ui->switchesCB->setModel(Helpers::getRawSwitchItemModel(&generalSettings, Helpers::MixesContext)); + ui->switchesCB->setCurrentIndex(ui->switchesCB->findData(md->swtch.toValue())); ui->warningCB->setCurrentIndex(md->mixWarn); ui->mltpxCB->setCurrentIndex(md->mltpx); int scale=firmware->getCapability(SlowScale); diff --git a/companion/src/modeledit/setup.cpp b/companion/src/modeledit/setup.cpp index 803cbb1e6..b24a9d3a4 100644 --- a/companion/src/modeledit/setup.cpp +++ b/companion/src/modeledit/setup.cpp @@ -49,7 +49,9 @@ TimerPanel::TimerPanel(QWidget *parent, ModelData & model, TimerData & timer, Ge } // Mode - populateSwitchCB(ui->mode, timer.mode, generalSettings, TimersContext); + ui->mode->setModel(Helpers::getRawSwitchItemModel(&generalSettings, Helpers::TimersContext)); + ui->mode->setCurrentIndex(ui->mode->findData(timer.mode.toValue())); + //Helpers::populateSwitchCB(ui->mode, timer.mode, generalSettings, Helpers::TimersContext); if (!firmware->getCapability(PermTimers)) { ui->persistent->hide(); @@ -887,19 +889,20 @@ SetupPanel::SetupPanel(QWidget * parent, ModelData & model, GeneralSettings & ge // Beep Center checkboxes prevFocus = ui->trimsDisplay; int analogs = CPN_MAX_STICKS + getBoardCapability(board, Board::Pots) + getBoardCapability(board, Board::Sliders); - for (int i=0; igetCapability(RotaryEncoders); i++) { + int genAryIdx = 0; + for (int i=0; i < analogs + firmware->getCapability(RotaryEncoders); i++) { + RawSource src((i < analogs) ? SOURCE_TYPE_STICK : SOURCE_TYPE_ROTARY_ENCODER, (i < analogs) ? i : analogs - i); QCheckBox * checkbox = new QCheckBox(this); checkbox->setProperty("index", i); - checkbox->setText(igetAnalogInputName(i) : RotaryEncoderString(i-analogs)); + checkbox->setText(src.toString(&model, &generalSettings)); ui->centerBeepLayout->addWidget(checkbox, 0, i+1); connect(checkbox, SIGNAL(toggled(bool)), this, SLOT(onBeepCenterToggled(bool))); centerBeepCheckboxes << checkbox; if (IS_HORUS_OR_TARANIS(board)) { - RawSource src(SOURCE_TYPE_STICK, i); - if (src.isPot() && !generalSettings.isPotAvailable(i-CPN_MAX_STICKS)) { + if (src.isPot(&genAryIdx) && !generalSettings.isPotAvailable(genAryIdx)) { checkbox->hide(); } - else if (src.isSlider() && !generalSettings.isSliderAvailable(i-CPN_MAX_STICKS-getBoardCapability(board, Board::Pots))) { + else if (src.isSlider(&genAryIdx) && !generalSettings.isSliderAvailable(genAryIdx)) { checkbox->hide(); } } @@ -909,13 +912,12 @@ SetupPanel::SetupPanel(QWidget * parent, ModelData & model, GeneralSettings & ge // Startup switches warnings for (int i=0; isetOrientation(Qt::Vertical); slider->setMinimum(0); slider->setInvertedAppearance(true); + slider->setInvertedControls(true); slider->setTickPosition(QSlider::TicksBothSides); slider->setMinimumSize(QSize(30, 50)); slider->setMaximumSize(QSize(50, 50)); slider->setSingleStep(1); slider->setPageStep(1); slider->setTickInterval(1); - label->setText(switchInfo.name); + label->setText(src.toString(&model, &generalSettings)); slider->setMaximum(switchInfo.config == Board::SWITCH_3POS ? 2 : 1); cb->setProperty("index", i); ui->switchesStartupLayout->addWidget(label, 0, i+1); @@ -951,21 +954,18 @@ SetupPanel::SetupPanel(QWidget * parent, ModelData & model, GeneralSettings & ge prevFocus = ui->potWarningMode; if (IS_HORUS_OR_TARANIS(board)) { for (int i=0; isetProperty("index", i); - cb->setText(firmware->getAnalogInputName(i+4)); + cb->setText(src.toString(&model, &generalSettings)); ui->potWarningLayout->addWidget(cb, 0, i+1); connect(cb, SIGNAL(toggled(bool)), this, SLOT(potWarningToggled(bool))); potWarningCheckboxes << cb; - if (RawSource(SOURCE_TYPE_STICK, CPN_MAX_STICKS+i).isPot()) { - if (!generalSettings.isPotAvailable(i)) { - cb->hide(); - } + if (src.isPot(&genAryIdx) && !generalSettings.isPotAvailable(genAryIdx)) { + cb->hide(); } - else { - if (!generalSettings.isSliderAvailable(i-getBoardCapability(board, Board::Pots))) { - cb->hide(); - } + else if (src.isSlider(&genAryIdx) && !generalSettings.isSliderAvailable(genAryIdx)) { + cb->hide(); } QWidget::setTabOrder(prevFocus, cb); prevFocus = cb; diff --git a/companion/src/modeledit/telemetry.cpp b/companion/src/modeledit/telemetry.cpp index 7d932184f..58c6e38d6 100644 --- a/companion/src/modeledit/telemetry.cpp +++ b/companion/src/modeledit/telemetry.cpp @@ -352,7 +352,7 @@ TelemetryCustomScreen::TelemetryCustomScreen(QWidget *parent, ModelData & model, if (IS_TARANIS(firmware->getBoard())) { QSet scriptsSet = getFilesSet(g.profile[g.id()].sdPath() + "/SCRIPTS/TELEMETRY", QStringList() << "*.lua", 8); - populateFileComboBox(ui->scriptName, scriptsSet, screen.body.script.filename); + Helpers::populateFileComboBox(ui->scriptName, scriptsSet, screen.body.script.filename); connect(ui->scriptName, SIGNAL(currentIndexChanged(int)), this, SLOT(scriptNameEdited())); connect(ui->scriptName, SIGNAL(editTextChanged ( const QString)), this, SLOT(scriptNameEdited())); } @@ -362,12 +362,15 @@ TelemetryCustomScreen::TelemetryCustomScreen(QWidget *parent, ModelData & model, void TelemetryCustomScreen::populateTelemetrySourceCB(QComboBox * b, RawSource & source, bool last) { + int flags = POPULATE_NONE | POPULATE_TELEMETRY; if (IS_ARM(firmware->getBoard())) { - populateSourceCB(b, source, generalSettings, model, POPULATE_NONE | POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | POPULATE_TELEMETRY | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0)); + flags |= POPULATE_SOURCES | POPULATE_SCRIPT_OUTPUTS | POPULATE_VIRTUAL_INPUTS | POPULATE_TRIMS | POPULATE_SWITCHES | (firmware->getCapability(GvarsInCS) ? POPULATE_GVARS : 0); } - else { - populateSourceCB(b, source, generalSettings, model, POPULATE_NONE | POPULATE_TELEMETRY | (last ? POPULATE_TELEMETRYEXT : 0)); + else if (last) { + flags |= POPULATE_TELEMETRYEXT; } + b->setModel(Helpers::getRawSourceItemModel(&generalSettings, model, flags)); + b->setCurrentIndex(b->findData(source.toValue())); } TelemetryCustomScreen::~TelemetryCustomScreen() @@ -454,7 +457,7 @@ void TelemetryCustomScreen::scriptNameEdited() { if (!lock) { lock = true; - getFileComboBoxValue(ui->scriptName, screen.body.script.filename, 8); + Helpers::getFileComboBoxValue(ui->scriptName, screen.body.script.filename, 8); emit modified(); lock = false; } diff --git a/companion/src/modelprinter.cpp b/companion/src/modelprinter.cpp index 0eec56eab..a24cabb11 100644 --- a/companion/src/modelprinter.cpp +++ b/companion/src/modelprinter.cpp @@ -20,6 +20,8 @@ #include "helpers.h" #include "modelprinter.h" +#include "multiprotocols.h" + #include #include #include @@ -342,7 +344,7 @@ QString ModelPrinter::printInputName(int idx) } } else { - result = RawSource(SOURCE_TYPE_STICK, idx).toString(&model); + result = RawSource(SOURCE_TYPE_STICK, idx).toString(&model, &generalSettings); } return result.toHtmlEscaped(); } @@ -363,22 +365,26 @@ QString ModelPrinter::printInputLine(const ExpoData & input) } if (firmware->getCapability(VirtualInputs)) { - str += input.srcRaw.toString(&model).toHtmlEscaped(); + str += input.srcRaw.toString(&model, &generalSettings).toHtmlEscaped(); } str += " " + tr("Weight").toHtmlEscaped() + QString("(%1)").arg(getGVarString(input.weight,true).toHtmlEscaped()); - if (input.curve.value) str += " " + input.curve.toString().toHtmlEscaped(); + if (input.curve.value) + str += " " + input.curve.toString().toHtmlEscaped(); QString flightModesStr = printFlightModes(input.flightModes); - if (!flightModesStr.isEmpty()) str += " " + flightModesStr.toHtmlEscaped(); + if (!flightModesStr.isEmpty()) + str += " " + flightModesStr.toHtmlEscaped(); if (input.swtch.type != SWITCH_TYPE_NONE) - str += " " + tr("Switch").toHtmlEscaped() + QString("(%1)").arg(input.swtch.toString().toHtmlEscaped()); + str += " " + tr("Switch").toHtmlEscaped() + QString("(%1)").arg(input.swtch.toString(getCurrentBoard(), &generalSettings)).toHtmlEscaped(); if (firmware->getCapability(VirtualInputs)) { - if (input.carryTrim>0) str += " " + tr("NoTrim").toHtmlEscaped(); - else if (input.carryTrim<0) str += " " + RawSource(SOURCE_TYPE_TRIM, (-(input.carryTrim)-1)).toString(&model).toHtmlEscaped(); + if (input.carryTrim>0) + str += " " + tr("NoTrim").toHtmlEscaped(); + else if (input.carryTrim<0) + str += " " + RawSource(SOURCE_TYPE_TRIM, (-(input.carryTrim)-1)).toString(&model, &generalSettings).toHtmlEscaped(); } if (input.offset) @@ -424,7 +430,7 @@ QString ModelPrinter::printMixerLine(const MixData & mix, bool showMultiplex, in str += "  "; } // highlight source if needed - QString source = mix.srcRaw.toString(&model).toHtmlEscaped(); + QString source = mix.srcRaw.toString(&model, &generalSettings).toHtmlEscaped(); if ( (mix.srcRaw.type == SOURCE_TYPE_CH) && (mix.srcRaw.index+1 == (int)highlightedSource) ) { source = "" + source + ""; } @@ -440,12 +446,12 @@ QString ModelPrinter::printMixerLine(const MixData & mix, bool showMultiplex, in str += " " + flightModesStr.toHtmlEscaped(); if (mix.swtch.type != SWITCH_TYPE_NONE) - str += " " + tr("Switch(%1)").arg(mix.swtch.toString()).toHtmlEscaped(); + str += " " + tr("Switch(%1)").arg(mix.swtch.toString(getCurrentBoard(), &generalSettings)).toHtmlEscaped(); if (mix.carryTrim > 0) str += " " + tr("NoTrim").toHtmlEscaped(); else if (mix.carryTrim < 0) - str += " " + RawSource(SOURCE_TYPE_TRIM, (-(mix.carryTrim)-1)).toString(&model); + str += " " + RawSource(SOURCE_TYPE_TRIM, (-(mix.carryTrim)-1)).toString(&model, &generalSettings); if (firmware->getCapability(HasNoExpo) && mix.noExpo) str += " " + tr("No DR/Expo").toHtmlEscaped(); @@ -467,16 +473,9 @@ QString ModelPrinter::printMixerLine(const MixData & mix, bool showMultiplex, in return str; } -QString ModelPrinter::printFlightModeSwitch(int index) +QString ModelPrinter::printFlightModeSwitch(const RawSwitch & swtch) { - if (index == 0) - return "---"; - else if (index > 0) { - return printFlightModeName(index-1); - } - else { - return "!" + printFlightModeName(-index-1); - } + return swtch.toString(getCurrentBoard(), &generalSettings); } QString ModelPrinter::printFlightModeName(int index) @@ -517,6 +516,8 @@ QString ModelPrinter::printLogicalSwitchLine(int idx) { QString result = ""; const LogicalSwitchData & ls = model.logicalSw[idx]; + const QString sw1Name = RawSwitch(ls.val1).toString(getCurrentBoard(), &generalSettings); + const QString sw2Name = RawSwitch(ls.val2).toString(getCurrentBoard(), &generalSettings); if (!ls.func) return result; @@ -526,10 +527,10 @@ QString ModelPrinter::printLogicalSwitchLine(int idx) } switch (ls.getFunctionFamily()) { case LS_FAMILY_EDGE: - result += tr("Edge(%1, [%2:%3])").arg(RawSwitch(ls.val1).toString()).arg(ValToTim(ls.val2)).arg(ls.val3<0 ? tr("instant") : QString("%1").arg(ValToTim(ls.val2+ls.val3))); + result += tr("Edge(%1, [%2:%3])").arg(sw1Name).arg(ValToTim(ls.val2)).arg(ls.val3<0 ? tr("instant") : QString("%1").arg(ValToTim(ls.val2+ls.val3))); break; case LS_FAMILY_STICKY: - result += tr("Sticky(%1, %2)").arg(RawSwitch(ls.val1).toString()).arg(RawSwitch(ls.val2).toString()); + result += tr("Sticky(%1, %2)").arg(sw1Name).arg(sw2Name); break; case LS_FAMILY_TIMER: result += tr("Timer(%1, %2)").arg(ValToTim(ls.val1)).arg(ValToTim(ls.val2)); @@ -539,7 +540,7 @@ QString ModelPrinter::printLogicalSwitchLine(int idx) RawSourceRange range = source.getRange(&model, generalSettings); QString res; if (ls.val1) - res += source.toString(&model); + res += source.toString(&model, &generalSettings); else res += "0"; res.remove(" "); @@ -564,7 +565,7 @@ QString ModelPrinter::printLogicalSwitchLine(int idx) break; } case LS_FAMILY_VBOOL: - result += RawSwitch(ls.val1).toString(); + result += sw1Name; switch (ls.func) { case LS_FN_AND: result += " AND "; @@ -579,12 +580,12 @@ QString ModelPrinter::printLogicalSwitchLine(int idx) result += " bar "; break; } - result += RawSwitch(ls.val2).toString(); + result += sw2Name; break; case LS_FAMILY_VCOMP: if (ls.val1) - result += RawSource(ls.val1).toString(&model); + result += RawSource(ls.val1).toString(&model, &generalSettings); else result += "0"; switch (ls.func) { @@ -612,7 +613,7 @@ QString ModelPrinter::printLogicalSwitchLine(int idx) break; } if (ls.val2) - result += RawSource(ls.val2).toString(&model); + result += RawSource(ls.val2).toString(&model, &generalSettings); else result += "0"; break; @@ -620,7 +621,7 @@ QString ModelPrinter::printLogicalSwitchLine(int idx) if (ls.andsw != 0) { result +=" ) AND "; - result += RawSwitch(ls.andsw).toString(); + result += RawSwitch(ls.andsw).toString(getCurrentBoard(), &generalSettings); } if (firmware->getCapability(LogicalSwitchesExt)) { @@ -637,13 +638,16 @@ QString ModelPrinter::printCustomFunctionLine(int idx) { QString result; const CustomFunctionData & cf = model.customFn[idx]; - if (cf.swtch.type == SWITCH_TYPE_NONE) return result; + if (cf.swtch.type == SWITCH_TYPE_NONE) + return result; - result += cf.swtch.toString() + " - "; + result += cf.swtch.toString(getCurrentBoard(), &generalSettings) + " - "; result += cf.funcToString() + "("; result += cf.paramToString(&model) + ")"; - if (!cf.repeatToString().isEmpty()) result += " " + cf.repeatToString(); - if (!cf.enabledToString().isEmpty()) result += " " + cf.enabledToString(); + if (!cf.repeatToString().isEmpty()) + result += " " + cf.repeatToString(); + if (!cf.enabledToString().isEmpty()) + result += " " + cf.enabledToString(); return result; } diff --git a/companion/src/modelprinter.h b/companion/src/modelprinter.h index aa02e9585..68c38105a 100644 --- a/companion/src/modelprinter.h +++ b/companion/src/modelprinter.h @@ -53,14 +53,14 @@ class ModelPrinter: public QObject public: ModelPrinter(Firmware * firmware, const GeneralSettings & generalSettings, const ModelData & model); virtual ~ModelPrinter(); - + QString printEEpromSize(); QString printTrimIncrementMode(); QString printThrottleTrimMode(); static QString printModuleProtocol(unsigned int protocol); static QString printMultiRfProtocol(int rfProtocol, bool custom); static QString printMultiSubType(int rfProtocol, bool custom, unsigned int subType); - QString printFlightModeSwitch(int index); + QString printFlightModeSwitch(const RawSwitch & swtch); QString printFlightModeName(int index); QString printFlightModes(unsigned int flightModes); QString printModule(int idx); diff --git a/companion/src/modelslist.cpp b/companion/src/modelslist.cpp index ab0f227a7..c29b24bfc 100644 --- a/companion/src/modelslist.cpp +++ b/companion/src/modelslist.cpp @@ -247,7 +247,7 @@ void TreeModel::refresh() Board::Type board = eepromInterface->getBoard(); if (!IS_SKY9X(board) && !IS_HORUS(board)) { - availableEEpromSize = getEEpromSize(board) - 64; // let's consider fat + availableEEpromSize = Boards::getEEpromSize(board) - 64; // let's consider fat availableEEpromSize -= 16 * ((eepromInterface->getSize(radioData->generalSettings) + 14) / 15); } diff --git a/companion/src/multimodelprinter.cpp b/companion/src/multimodelprinter.cpp index 56e80f760..858664609 100644 --- a/companion/src/multimodelprinter.cpp +++ b/companion/src/multimodelprinter.cpp @@ -101,9 +101,9 @@ bool MultiModelPrinter::MultiColumns::isEmpty() #define COMPARE(what) \ columns.beginCompare(); \ - for (int cc=0; cc

").arg(modelPrinters.count()) + label + "

"; + return QString("

").arg(modelPrinterMap.count()) + label + "

"; } MultiModelPrinter::MultiModelPrinter(Firmware * firmware): @@ -121,25 +121,27 @@ MultiModelPrinter::MultiModelPrinter(Firmware * firmware): MultiModelPrinter::~MultiModelPrinter() { - for(int i=0; i pair(&model, new ModelPrinter(firmware, generalSettings, model)); + modelPrinterMap.insert(idx, pair); // QMap.insert will replace any existing key +} + void MultiModelPrinter::setModel(int idx, const ModelData & model) { - int count = std::max(models.size(), idx+1); - models.resize(count); - modelPrinters.resize(count); - - if (modelPrinters[idx]) { - // free existing model printer - delete modelPrinters[idx]; - modelPrinters[idx] = 0; - } - - models[idx] = (ModelData *)&model; // TODO remove cast - modelPrinters[idx] = new ModelPrinter(firmware, defaultSettings, model); + setModel(idx, model, defaultSettings); } QString MultiModelPrinter::print(QTextDocument * document) @@ -169,7 +171,7 @@ QString MultiModelPrinter::printSetup() { QString str = printTitle(tr("General Model Settings")); - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); columns.appendTitle(tr("Name:")); COMPARE(model->name); columns.append("
"); @@ -207,15 +209,15 @@ QString MultiModelPrinter::printSetup() QString MultiModelPrinter::printHeliSetup() { bool heliEnabled = false; - for (int k=0; kswashRingData.type != HELI_SWASH_TYPE_NONE; + for (int k=0; k < modelPrinterMap.size(); k++) { + heliEnabled = heliEnabled || modelPrinterMap.value(k).first->swashRingData.type != HELI_SWASH_TYPE_NONE; } if (!heliEnabled) return ""; QString str = printTitle(tr("Helicopter Setup")); - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); columns.appendTitle (tr("Swash Type:")); COMPARE(modelPrinter->printHeliSwashType()); columns.append ("
"); @@ -260,15 +262,15 @@ QString MultiModelPrinter::printFlightModes() // Trims { - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); columns.append(""); columns.append(""); columns.append(""); columns.append(""); columns.append(""); columns.append(""); - for (int i=0; i<4; i++) { - columns.append(""); + for (int i=0; i < getBoardCapability(getCurrentBoard(), Board::NumTrims); i++) { + columns.append(""); } columns.append(""); @@ -276,13 +278,13 @@ QString MultiModelPrinter::printFlightModes() columns.append(""); - for (int k=0; k"); COMPARE(modelPrinter->printTrim(i, k)); columns.append(""); @@ -297,7 +299,7 @@ QString MultiModelPrinter::printFlightModes() // GVars and Rotary Encoders int gvars = firmware->getCapability(Gvars); if ((gvars && firmware->getCapability(GvarsFlightModes)) || firmware->getCapability(RotaryEncoders)) { - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); columns.append("
" + tr("Flight mode") + "" + tr("Switch") + "" + tr("Fade IN") + "" + tr("Fade OUT") + "" + getCurrentFirmware()->getAnalogInputName(i) + " trim" + RawSource(SOURCE_TYPE_TRIM, i).toString() + "
" + tr("FM%1").arg(i) + " "); COMPARE(model->flightModeData[i].name); columns.append(""); - COMPARE(model->flightModeData[i].swtch.toString()); + COMPARE(modelPrinter->printFlightModeSwitch(model->flightModeData[i].swtch)); columns.append(""); COMPARE(model->flightModeData[i].fadeIn); columns.append(""); COMPARE(model->flightModeData[i].fadeOut); columns.append("
"); columns.append(""); if (firmware->getCapability(GvarsFlightModes)) { @@ -339,7 +341,7 @@ QString MultiModelPrinter::printFlightModes() QString MultiModelPrinter::printLimits() { QString str = printTitle(tr("Limits")); - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); columns.append("
" + tr("Flight mode") + "
" \ "" \ " " \ @@ -350,6 +352,11 @@ QString MultiModelPrinter::printLimits() " " \ ""); for (int i=0; igetCapability(Outputs); i++) { + int count = 0; + for (int k=0; k < modelPrinterMap.size(); k++) + count = std::max(count, modelPrinterMap.value(k).first->mixes(i).size()); + if (!count) + continue; columns.append(""); + } columns.append("
" + tr("Channel") + "" + tr("Invert") + "
"); COMPARE(modelPrinter->printChannelName(i)); columns.append(""); @@ -363,6 +370,7 @@ QString MultiModelPrinter::printLimits() columns.append(""); COMPARE(model->limitData[i].revertToString()); columns.append("
"); str.append(columns.print()); @@ -373,7 +381,7 @@ QString MultiModelPrinter::printGvars() { QString str = printTitle(tr("Global Variables")); int gvars = firmware->getCapability(Gvars); - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); columns.append(""); for (int i=0; i") + tr("GV%1").arg(i+1) + ""); @@ -392,12 +400,12 @@ QString MultiModelPrinter::printGvars() QString MultiModelPrinter::printInputs() { QString str = printTitle(tr("Inputs")); - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); columns.append("
"); for (int i=0; igetCapability(VirtualInputs)); i++) { int count = 0; - for (int k=0; kexpos(i).size()); + for (int k=0; k < modelPrinterMap.size(); k++) { + count = std::max(count, modelPrinterMap.value(k).first->expos(i).size()); } if (count > 0) { columns.append("
"); @@ -418,12 +426,12 @@ QString MultiModelPrinter::printInputs() QString MultiModelPrinter::printMixers() { QString str = printTitle(tr("Mixers")); - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); columns.append(""); for (int i=0; igetCapability(Outputs); i++) { int count = 0; - for (int k=0; kmixes(i).size()); + for (int k=0; k < modelPrinterMap.size(); k++) { + count = std::max(count, modelPrinterMap.value(k).first->mixes(i).size()); } if (count > 0) { columns.append("
"); @@ -444,13 +452,13 @@ QString MultiModelPrinter::printMixers() QString MultiModelPrinter::printCurves(QTextDocument * document) { QString str; - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); int count = 0; columns.append(""); for (int i=0; igetCapability(NumCurves); i++) { bool curveEmpty = true; - for (int k=0; kcurves[i].isEmpty()) { + for (int k=0; k < modelPrinterMap.size(); k++) { + if (!modelPrinterMap.value(k).first->curves[i].isEmpty()) { curveEmpty = false; break; } @@ -459,8 +467,8 @@ QString MultiModelPrinter::printCurves(QTextDocument * document) count++; columns.append(""); } } @@ -475,13 +483,13 @@ QString MultiModelPrinter::printCurves(QTextDocument * document) QString MultiModelPrinter::printLogicalSwitches() { QString str; - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); int count = 0; columns.append("
" + tr("CV%1").arg(i+1) + ""); COMPARE(modelPrinter->printCurve(i)); - for (int k=0; k").arg(modelPrinters[k]->createCurveImage(i, document))); + for (int k=0; k < modelPrinterMap.size(); k++) + columns.append(k, QString("
").arg(modelPrinterMap.value(k).second->createCurveImage(i, document))); columns.append("
"); for (int i=0; igetCapability(LogicalSwitches); i++) { bool lsEmpty = true; - for (int k=0; kprintLogicalSwitchLine(i).isEmpty()) { + for (int k=0; k < modelPrinterMap.size(); k++) { + if (!modelPrinterMap.value(k).second->printLogicalSwitchLine(i).isEmpty()) { lsEmpty = false; break; } @@ -504,13 +512,13 @@ QString MultiModelPrinter::printLogicalSwitches() QString MultiModelPrinter::printCustomFunctions() { QString str; - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); int count = 0; columns.append("
"); - for (int i=0; igetCapability(CustomFunctions); i++) { + for (int i=0; i < firmware->getCapability(CustomFunctions); i++) { bool sfEmpty = true; - for (int k=0; kprintCustomFunctionLine(i).isEmpty()) { + for (int k=0; k < modelPrinterMap.size(); k++) { + if (modelPrinterMap.value(k).first->customFn[i].swtch.type != SWITCH_TYPE_NONE) { sfEmpty = false; break; } @@ -536,7 +544,7 @@ QString MultiModelPrinter::printTelemetry() // Analogs on non ARM boards if (!IS_ARM(firmware->getBoard())) { - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); columns.append("
" \ ""); for (int i=0; i<2; i++) { @@ -555,7 +563,7 @@ QString MultiModelPrinter::printTelemetry() // RSSI alarms { - MultiColumns columns(models.size()); + MultiColumns columns(modelPrinterMap.size()); columns.append("
" + tr("Analogs") + "" + tr("Unit") + "" + tr("Scale") + "" + tr("Offset") + "
"); for (int i=0; i<2; i++) { columns.append("
" + QString(i==0 ? tr("RSSI Alarms") : "") + ""); diff --git a/companion/src/multimodelprinter.h b/companion/src/multimodelprinter.h index 31c807e54..97332691a 100644 --- a/companion/src/multimodelprinter.h +++ b/companion/src/multimodelprinter.h @@ -33,7 +33,8 @@ class MultiModelPrinter: public QObject public: MultiModelPrinter(Firmware * firmware); virtual ~MultiModelPrinter(); - + + void setModel(int idx, const ModelData & model, const GeneralSettings & generalSettings); void setModel(int idx, const ModelData & model); QString print(QTextDocument * document); @@ -58,8 +59,7 @@ class MultiModelPrinter: public QObject Firmware * firmware; GeneralSettings defaultSettings; - QVector models; // TODO const - QVector modelPrinters; + QMap > modelPrinterMap; QString printTitle(const QString & label); QString printSetup(); diff --git a/companion/src/printdialog.cpp b/companion/src/printdialog.cpp index 082785e71..6f403dfb9 100644 --- a/companion/src/printdialog.cpp +++ b/companion/src/printdialog.cpp @@ -36,7 +36,7 @@ PrintDialog::PrintDialog(QWidget *parent, Firmware * firmware, GeneralSettings & ui->setupUi(this); setWindowIcon(CompanionIcon("print.png")); setWindowTitle(model.name); - multimodelprinter.setModel(0, model); + multimodelprinter.setModel(0, model, generalSettings); ui->textEdit->setHtml(multimodelprinter.print(ui->textEdit->document())); if (!printfilename.isEmpty()) { printToFile(); @@ -44,7 +44,7 @@ PrintDialog::PrintDialog(QWidget *parent, Firmware * firmware, GeneralSettings & } } -void PrintDialog::closeEvent(QCloseEvent *event) +void PrintDialog::closeEvent(QCloseEvent *event) { } diff --git a/companion/src/radiodata.h b/companion/src/radiodata.h index 3c6b0af00..480d99012 100644 --- a/companion/src/radiodata.h +++ b/companion/src/radiodata.h @@ -218,7 +218,7 @@ class RawSource { return index >= 0 ? (type * 65536 + index) : -(type * 65536 - index); } - QString toString(const ModelData * model = NULL) const; + QString toString(const ModelData * model = NULL, const GeneralSettings * const generalSettings = NULL) const; RawSourceRange getRange(const ModelData * model, const GeneralSettings & settings, unsigned int flags=0) const; @@ -231,8 +231,8 @@ class RawSource { } bool isTimeBased() const; - bool isPot() const; - bool isSlider() const; + bool isPot(int * potsIndex = NULL) const; + bool isSlider(int * sliderIndex = NULL) const; RawSourceType type; int index; @@ -277,7 +277,7 @@ class RawSwitch { return index >= 0 ? (type * 256 + index) : -(type * 256 - index); } - QString toString(Board::Type board = Board::BOARD_UNKNOWN) const; + QString toString(Board::Type board = Board::BOARD_UNKNOWN, const GeneralSettings * const generalSettings = NULL) const; bool operator== ( const RawSwitch& other) { return (this->type == other.type) && (this->index == other.index); @@ -541,9 +541,9 @@ class CustomFunctionData { // Function Switches data class FlightModeData { public: FlightModeData() { clear(0); } - int trimMode[CPN_MAX_STICKS+CPN_MAX_AUX_TRIMS]; - int trimRef[CPN_MAX_STICKS+CPN_MAX_AUX_TRIMS]; - int trim[CPN_MAX_STICKS+CPN_MAX_AUX_TRIMS]; + int trimMode[CPN_MAX_TRIMS]; + int trimRef[CPN_MAX_TRIMS]; + int trim[CPN_MAX_TRIMS]; RawSwitch swtch; char name[10+1]; unsigned int fadeIn; @@ -1127,9 +1127,9 @@ class GeneralSettings { unsigned int version; unsigned int variant; - int calibMid[CPN_MAX_STICKS+CPN_MAX_POTS+CPN_MAX_MOUSE_ANALOGS]; - int calibSpanNeg[CPN_MAX_STICKS+CPN_MAX_POTS+CPN_MAX_MOUSE_ANALOGS]; - int calibSpanPos[CPN_MAX_STICKS+CPN_MAX_POTS+CPN_MAX_MOUSE_ANALOGS]; + int calibMid[CPN_MAX_ANALOGS]; + int calibSpanNeg[CPN_MAX_ANALOGS]; + int calibSpanPos[CPN_MAX_ANALOGS]; unsigned int currModelIndex; char currModelFilename[16+1]; unsigned int contrast; @@ -1201,13 +1201,13 @@ class GeneralSettings { unsigned int hw_uartMode; unsigned int backlightColor; CustomFunctionData customFn[CPN_MAX_CUSTOM_FUNCTIONS]; - char switchName[18][3+1]; + char switchName[CPN_MAX_SWITCHES][3+1]; unsigned int switchConfig[CPN_MAX_SWITCHES]; - char stickName[4][3+1]; - char potName[4][3+1]; - unsigned int potConfig[4]; - char sliderName[4][3+1]; - unsigned int sliderConfig[4]; + char stickName[CPN_MAX_STICKS][3+1]; + char potName[CPN_MAX_KNOBS][3+1]; + unsigned int potConfig[CPN_MAX_KNOBS]; + char sliderName[CPN_MAX_SLIDERS][3+1]; + unsigned int sliderConfig[CPN_MAX_SLIDERS]; char themeName[8+1]; typedef uint8_t ThemeOptionData[8+1]; diff --git a/companion/src/radiointerface.cpp b/companion/src/radiointerface.cpp index 58654e673..cf6a0e2c0 100644 --- a/companion/src/radiointerface.cpp +++ b/companion/src/radiointerface.cpp @@ -84,17 +84,13 @@ QStringList getDfuArgs(const QString & cmd, const QString & filename) { QStringList args; burnConfigDialog bcd; - QString memory = "0x08000000"; - if (cmd == "-U") { - memory.append(QString(":%1").arg(getCurrentFirmware()->getFlashSize())); - } args << bcd.getDFUArgs(); - if (!filename.endsWith(".dfu")) { - args << "--dfuse-address" << memory; - } - args << "-d" << "0483:df11"; - QString fullcmd = cmd + filename; - args << "" << fullcmd; + if (!filename.endsWith(".dfu")) + args << "--dfuse-address" << "0x08000000"; + if (cmd == "-U") + args.last().append(":" % QString::number(Boards::getFlashSize(getCurrentBoard()))); + args << "--device" << "0483:df11"; + args << "" << cmd % filename; return args; } @@ -467,7 +463,7 @@ QString findMassstoragePath(const QString & filename, bool onlyPath) #if !defined __APPLE__ QString fstype = entry->me_type; // qDebug() << eepromfile; - + if (fstype.contains("fat") && QFile::exists(eepromfile)) { #else if (QFile::exists(eepromfile)) { diff --git a/companion/src/simulation/joystickdialog.cpp b/companion/src/simulation/joystickdialog.cpp index 77cd14ef0..d2c87b2d6 100644 --- a/companion/src/simulation/joystickdialog.cpp +++ b/companion/src/simulation/joystickdialog.cpp @@ -21,6 +21,7 @@ #include "joystickdialog.h" #include "ui_joystickdialog.h" +#include "boards.h" #include "constants.h" joystickDialog::joystickDialog(QWidget *parent, int stick) : @@ -97,19 +98,13 @@ joystickDialog::~joystickDialog() void joystickDialog::populateSourceCombo(QComboBox * cb) { int i; - const QString axes[] = { - tr("Left Horizontal"), - tr("Left Vertical"), - tr("Right Vertical"), - tr("Right Horizontal") - }; cb->clear(); cb->addItem(tr("Not Assigned"), -1); - for (i=0; i < 4; ++i) { - cb->addItem(axes[i] % tr(" Stick"), i); + for (i=0; i < Board::STICK_AXIS_COUNT; ++i) { + cb->addItem(Boards::getAxisName(i) % tr(" Stick"), i); } - for (; i < CPN_MAX_STICKS + CPN_MAX_POTS; ++i) { - cb->addItem(tr("Knob/Slider %1").arg(i - CPN_MAX_STICKS + 1), i); + for (; i < Board::STICK_AXIS_COUNT + CPN_MAX_POTS; ++i) { + cb->addItem(tr("Knob/Slider %1").arg(i - Board::STICK_AXIS_COUNT + 1), i); } } diff --git a/companion/src/simulation/simulatorinterface.h b/companion/src/simulation/simulatorinterface.h index 7939f3715..834d33746 100644 --- a/companion/src/simulation/simulatorinterface.h +++ b/companion/src/simulation/simulatorinterface.h @@ -41,7 +41,7 @@ struct TxInputs int switches[CPN_MAX_SWITCHES]; bool keys[CPN_MAX_KEYS]; bool rotenc; - bool trims[(CPN_MAX_STICKS + CPN_MAX_AUX_TRIMS) * 2]; + bool trims[CPN_MAX_TRIM_SW]; }; class TxOutputs @@ -57,7 +57,7 @@ class TxOutputs struct Trims { - int values[CPN_MAX_STICKS + CPN_MAX_AUX_TRIMS]; /* lh lv rv rh t5 t6 */ + int values[CPN_MAX_TRIMS]; /* lh lv rv rh t5 t6 */ bool extended; }; diff --git a/companion/src/storage/bineeprom.cpp b/companion/src/storage/bineeprom.cpp index ffbebdcab..c27d5681c 100644 --- a/companion/src/storage/bineeprom.cpp +++ b/companion/src/storage/bineeprom.cpp @@ -50,7 +50,7 @@ bool BinEepromFormat::write(const RadioData & radioData) { bool result; EEPROMInterface * eepromInterface = getCurrentEEpromInterface(); - int size = getEEpromSize(eepromInterface->getBoard()); + int size = Boards::getEEpromSize(eepromInterface->getBoard()); if (size == 0) { return false; } diff --git a/companion/src/storage/eepe.cpp b/companion/src/storage/eepe.cpp index a1e399d61..b7c7f218c 100644 --- a/companion/src/storage/eepe.cpp +++ b/companion/src/storage/eepe.cpp @@ -31,23 +31,23 @@ bool EepeFormat::load(RadioData & radioData) setError(QObject::tr("Unable to open %1: %2").arg(filename).arg(file.errorString())); return false; } - + QTextStream inputStream(&file); QString hline = inputStream.readLine(); if (hline != EEPE_EEPROM_FILE_HEADER) { qDebug() << qPrintable("[eepe] No EEPE header"); return false; } - + qDebug() << qPrintable("[eepe] EEPE header found"); - - QByteArray eeprom(EESIZE_MAX, 0); - int eeprom_size = HexInterface(inputStream).load((uint8_t *)eeprom.data(), EESIZE_MAX); + + QByteArray eeprom(Boards::getEEpromSize(Board::BOARD_UNKNOWN), 0); + int eeprom_size = HexInterface(inputStream).load((uint8_t *)eeprom.data(), Boards::getEEpromSize(Board::BOARD_UNKNOWN)); if (!eeprom_size) { setError(QObject::tr("Invalid EEPROM file %1").arg(filename)); return false; } eeprom.resize(eeprom_size); - + return extract(radioData, eeprom); } diff --git a/companion/src/storage/firmwareinterface.cpp b/companion/src/storage/firmwareinterface.cpp index 2ba04471a..369af6504 100644 --- a/companion/src/storage/firmwareinterface.cpp +++ b/companion/src/storage/firmwareinterface.cpp @@ -31,6 +31,7 @@ #define DATE_MARK "DATE" #define TIME_MARK "TIME" #define EEPR_MARK "EEPR" +#define FSIZE_MAX Boards::getFlashSize(Board::BOARD_UNKNOWN) FirmwareInterface::FirmwareInterface(const QString & filename): flash(FSIZE_MAX, 0), diff --git a/companion/src/storage/hexeeprom.cpp b/companion/src/storage/hexeeprom.cpp index e49230be9..a0ecc33ae 100644 --- a/companion/src/storage/hexeeprom.cpp +++ b/companion/src/storage/hexeeprom.cpp @@ -31,17 +31,16 @@ bool HexEepromFormat::load(RadioData & radioData) qDebug() << "Unable to open" << filename << file.errorString(); return false; } - + QTextStream inputStream(&file); - // TODO remove EESIZE_MAX - QByteArray eeprom(EESIZE_MAX, 0); - int eeprom_size = HexInterface(inputStream).load((uint8_t *)eeprom.data(), EESIZE_MAX); + QByteArray eeprom(Boards::getEEpromSize(Board::BOARD_UNKNOWN), 0); + int eeprom_size = HexInterface(inputStream).load((uint8_t *)eeprom.data(), Boards::getEEpromSize(Board::BOARD_UNKNOWN)); if (!eeprom_size) { setError(QObject::tr("Invalid EEPROM File %1").arg(filename)); return false; } eeprom.resize(eeprom_size); - + return extract(radioData, eeprom); } @@ -52,12 +51,12 @@ bool HexEepromFormat::writeToFile(const uint8_t * eeprom, uint32_t size) setError(QObject::tr("Cannot open file %1:\n%2.").arg(filename).arg(file.errorString())); return false; } - + QTextStream outputStream(&file); if (!HexInterface(outputStream).save(eeprom, size)) { setError(QObject::tr("Error writing file %1:\n%2.").arg(filename).arg(file.errorString())); return false; } - + return true; } diff --git a/companion/src/storage/rlefile.cpp b/companion/src/storage/rlefile.cpp index c19723d2a..82cbf5bbf 100644 --- a/companion/src/storage/rlefile.cpp +++ b/companion/src/storage/rlefile.cpp @@ -71,7 +71,7 @@ void RleFile::EeFsCreate(uint8_t *eeprom, int size, Board::Type board, unsigned eeFsBlockSize = 64; eeFsFirstBlock = 1; eeFsBlocksOffset = eeFsSize - eeFsBlockSize; - eeFsBlocksMax = 1 + (EESIZE_TARANIS-eeFsSize)/eeFsBlockSize; + eeFsBlocksMax = 1 + (Boards::getEEpromSize(board)-eeFsSize) / eeFsBlockSize; eeFsLinkSize = sizeof(int16_t); memset(eeprom, 0, size); eeFsArm->version = eeFsVersion; @@ -154,7 +154,7 @@ bool RleFile::EeFsOpen(uint8_t *eeprom, int size, Board::Type board) eeFsLinkSize = sizeof(int16_t); eeFsFirstBlock = 1; eeFsBlocksOffset = eeFsSize - eeFsBlockSize; - eeFsBlocksMax = 1 + (EESIZE_TARANIS-eeFsSize)/eeFsBlockSize; + eeFsBlocksMax = 1 + (Boards::getEEpromSize(board)-eeFsSize) / eeFsBlockSize; return eeFsArm->mySize == eeFsSize; } else { @@ -406,7 +406,7 @@ unsigned int RleFile::readRlc12(uint8_t *buf, unsigned int i_len, bool rlc2) qDebug() << "RLC decoding error!"; return 0; } - + if (rlc2) { if(m_bRlc&0x80){ // if contains high byte m_zeroes =(m_bRlc>>4) & 0x7; diff --git a/companion/src/storage/storage.cpp b/companion/src/storage/storage.cpp index 0d19e1396..cd9b5bac6 100644 --- a/companion/src/storage/storage.cpp +++ b/companion/src/storage/storage.cpp @@ -124,7 +124,7 @@ bool convertEEprom(const QString & sourceEEprom, const QString & destinationEEpr if (!storage.load(*radioData)) return false; - QByteArray eeprom(EESIZE_MAX, 0); + QByteArray eeprom(Boards::getEEpromSize(Board::BOARD_UNKNOWN), 0); int size = getCurrentEEpromInterface()->save((uint8_t *)eeprom.data(), *radioData, version, variant); if (size == 0) { return false; diff --git a/radio/src/targets/simu/opentxsimulator.cpp b/radio/src/targets/simu/opentxsimulator.cpp index 2fd639e4d..c84ee7260 100644 --- a/radio/src/targets/simu/opentxsimulator.cpp +++ b/radio/src/targets/simu/opentxsimulator.cpp @@ -134,7 +134,7 @@ void OpenTxSimulator::getTrims(Trims & trims) { uint8_t phase = getFlightMode(); trims.extended = hasExtendedTrims(); - for (uint8_t idx=0; idx < CPN_MAX_STICKS + CPN_MAX_AUX_TRIMS; idx++) { + for (uint8_t idx=0; idx < CPN_MAX_TRIMS; idx++) { trims.values[idx] = getTrimValue(getTrimFlightMode(phase, idx), idx); } From c9df941ee6ec6ee71f1abea1fc3011eb020c68c1 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Mon, 27 Mar 2017 19:52:22 +0200 Subject: [PATCH 053/203] Conversion issues #4570 and #4264 --- companion/src/constants.h | 8 +- companion/src/eeprominterface.cpp | 4 +- companion/src/modeledit/customfunctions.h | 24 ++--- companion/src/modeledit/logicalswitches.h | 20 ++-- companion/src/radiodata.cpp | 96 ++++++++++++++++++- companion/src/radiodata.h | 15 ++- .../src/simulation/radiooutputswidget.cpp | 2 +- companion/src/simulation/simulatorinterface.h | 2 +- 8 files changed, 136 insertions(+), 35 deletions(-) diff --git a/companion/src/constants.h b/companion/src/constants.h index c28e7a218..322b016a1 100644 --- a/companion/src/constants.h +++ b/companion/src/constants.h @@ -30,10 +30,10 @@ #define CPN_MAX_CURVES 32 #define CPN_MAX_POINTS 17 #define CPN_MAX_GVARS 9 -#define CPN_MAX_ENCODERS 2 // rotary encoders -#define CPN_MAX_CHNOUT 32 // number of real output channels -#define CPN_MAX_CSW 64 // number of custom switches -#define CPN_MAX_CUSTOM_FUNCTIONS 64 // number of functions assigned to switches +#define CPN_MAX_ENCODERS 2 // rotary encoders +#define CPN_MAX_CHNOUT 32 // number of real output channels +#define CPN_MAX_LOGICAL_SWITCHES 64 // number of custom switches +#define CPN_MAX_SPECIAL_FUNCTIONS 64 // number of functions assigned to switches #define CPN_MAX_MODULES 2 #define CPN_MAX_STICKS Board::STICK_AXIS_COUNT #define CPN_MAX_TRIMS Board::TRIM_AXIS_COUNT diff --git a/companion/src/eeprominterface.cpp b/companion/src/eeprominterface.cpp index 15f834e12..6e62b51f5 100644 --- a/companion/src/eeprominterface.cpp +++ b/companion/src/eeprominterface.cpp @@ -1528,9 +1528,9 @@ void ModelData::clear() limitData[i].clear(); for (int i=0; i tracksSet; QSet scriptsSet; int mediaPlayerCurrent; - QComboBox * fswtchSwtch[CPN_MAX_CUSTOM_FUNCTIONS]; - QComboBox * fswtchFunc[CPN_MAX_CUSTOM_FUNCTIONS]; - QCheckBox * fswtchParamGV[CPN_MAX_CUSTOM_FUNCTIONS]; - QDoubleSpinBox * fswtchParam[CPN_MAX_CUSTOM_FUNCTIONS]; - QTimeEdit * fswtchParamTime[CPN_MAX_CUSTOM_FUNCTIONS]; - QPushButton * playBT[CPN_MAX_CUSTOM_FUNCTIONS]; - QComboBox * fswtchParamT[CPN_MAX_CUSTOM_FUNCTIONS]; - QComboBox * fswtchParamArmT[CPN_MAX_CUSTOM_FUNCTIONS]; - QCheckBox * fswtchEnable[CPN_MAX_CUSTOM_FUNCTIONS]; - RepeatComboBox * fswtchRepeat[CPN_MAX_CUSTOM_FUNCTIONS]; - QComboBox * fswtchGVmode[CPN_MAX_CUSTOM_FUNCTIONS]; - QSlider * fswtchBLcolor[CPN_MAX_CUSTOM_FUNCTIONS]; + QComboBox * fswtchSwtch[CPN_MAX_SPECIAL_FUNCTIONS]; + QComboBox * fswtchFunc[CPN_MAX_SPECIAL_FUNCTIONS]; + QCheckBox * fswtchParamGV[CPN_MAX_SPECIAL_FUNCTIONS]; + QDoubleSpinBox * fswtchParam[CPN_MAX_SPECIAL_FUNCTIONS]; + QTimeEdit * fswtchParamTime[CPN_MAX_SPECIAL_FUNCTIONS]; + QPushButton * playBT[CPN_MAX_SPECIAL_FUNCTIONS]; + QComboBox * fswtchParamT[CPN_MAX_SPECIAL_FUNCTIONS]; + QComboBox * fswtchParamArmT[CPN_MAX_SPECIAL_FUNCTIONS]; + QCheckBox * fswtchEnable[CPN_MAX_SPECIAL_FUNCTIONS]; + RepeatComboBox * fswtchRepeat[CPN_MAX_SPECIAL_FUNCTIONS]; + QComboBox * fswtchGVmode[CPN_MAX_SPECIAL_FUNCTIONS]; + QSlider * fswtchBLcolor[CPN_MAX_SPECIAL_FUNCTIONS]; QMediaPlayer * mediaPlayer; int selectedFunction; diff --git a/companion/src/modeledit/logicalswitches.h b/companion/src/modeledit/logicalswitches.h index 32464dbaf..70342898a 100644 --- a/companion/src/modeledit/logicalswitches.h +++ b/companion/src/modeledit/logicalswitches.h @@ -48,16 +48,16 @@ class LogicalSwitchesPanel : public ModelPanel void cswCut(); private: - QComboBox * csw[CPN_MAX_CSW]; - QDoubleSpinBox * cswitchValue[CPN_MAX_CSW]; - QDoubleSpinBox * cswitchOffset[CPN_MAX_CSW]; - QDoubleSpinBox * cswitchOffset2[CPN_MAX_CSW]; - QTimeEdit * cswitchTOffset[CPN_MAX_CSW]; - QComboBox * cswitchAnd[CPN_MAX_CSW]; - QDoubleSpinBox * cswitchDuration[CPN_MAX_CSW]; - QDoubleSpinBox * cswitchDelay[CPN_MAX_CSW]; - QComboBox * cswitchSource1[CPN_MAX_CSW]; - QComboBox * cswitchSource2[CPN_MAX_CSW]; + QComboBox * csw[CPN_MAX_LOGICAL_SWITCHES]; + QDoubleSpinBox * cswitchValue[CPN_MAX_LOGICAL_SWITCHES]; + QDoubleSpinBox * cswitchOffset[CPN_MAX_LOGICAL_SWITCHES]; + QDoubleSpinBox * cswitchOffset2[CPN_MAX_LOGICAL_SWITCHES]; + QTimeEdit * cswitchTOffset[CPN_MAX_LOGICAL_SWITCHES]; + QComboBox * cswitchAnd[CPN_MAX_LOGICAL_SWITCHES]; + QDoubleSpinBox * cswitchDuration[CPN_MAX_LOGICAL_SWITCHES]; + QDoubleSpinBox * cswitchDelay[CPN_MAX_LOGICAL_SWITCHES]; + QComboBox * cswitchSource1[CPN_MAX_LOGICAL_SWITCHES]; + QComboBox * cswitchSource2[CPN_MAX_LOGICAL_SWITCHES]; QStandardItemModel * rawSwitchItemModel; QStandardItemModel * rawSourceItemModel; void setSwitchWidgetVisibility(int i); diff --git a/companion/src/radiodata.cpp b/companion/src/radiodata.cpp index 4d09f71b9..6a284b5c5 100644 --- a/companion/src/radiodata.cpp +++ b/companion/src/radiodata.cpp @@ -23,7 +23,7 @@ // TODO here we will move a lot of functions from eeprominterface.cpp when no merge risk -void RawSource::convert(Board::Type before, Board::Type after) +RawSource RawSource::convert(Board::Type before, Board::Type after) { if (type == SOURCE_TYPE_STICK && index >= 4 + getBoardCapability(before, Board::Pots)) { // 1st slider alignment @@ -57,11 +57,79 @@ void RawSource::convert(Board::Type before, Board::Type after) } } } + + return *this; +} + +RawSwitch RawSwitch::convert(Board::Type before, Board::Type after) +{ + // SWI to SWR don't exist on !X9E board + if (!IS_TARANIS_X9E(after) && IS_TARANIS_X9E(before)) { + if (type == SWITCH_TYPE_SWITCH && index >= 24) { + index = index % 24; + } + } + + // No SE and SG on X7 board + if (IS_TARANIS_X7(after)) { + if (IS_TARANIS_X9(before) || IS_HORUS(before)) { + if (type == SWITCH_TYPE_SWITCH && index >= 18) { + index -= 6; + } + else if (type == SWITCH_TYPE_SWITCH && index >= 12) { + index -= 3; + } + } + } + + return *this; +} + +void ExpoData::convert(Board::Type before, Board::Type after) +{ + swtch.convert(before, after); } void MixData::convert(Board::Type before, Board::Type after) { srcRaw.convert(before, after); + swtch.convert(before, after); +} + +void LogicalSwitchData::convert(Board::Type before, Board::Type after) +{ + CSFunctionFamily family = getFunctionFamily(); + switch(family) { + case LS_FAMILY_VOFS: + val1 = RawSource(val1).convert(before, after).toValue(); + break; + case LS_FAMILY_STICKY: + case LS_FAMILY_VBOOL: + val1 = RawSwitch(val1).convert(before, after).toValue(); + val2 = RawSwitch(val2).convert(before, after).toValue(); + break; + case LS_FAMILY_EDGE: + val1 = RawSwitch(val1).convert(before, after).toValue(); + break; + case LS_FAMILY_VCOMP: + val1 = RawSource(val1).convert(before, after).toValue(); + val2 = RawSource(val2).convert(before, after).toValue(); + break; + default: + break; + } + + andsw = RawSwitch(andsw).convert(before, after).toValue(); +} + +void CustomFunctionData::convert(Board::Type before, Board::Type after) +{ + swtch.convert(before, after); +} + +void FlightModeData::convert(Board::Type before, Board::Type after) +{ + swtch.convert(before, after); } void ModelData::convert(Board::Type before, Board::Type after) @@ -70,11 +138,37 @@ void ModelData::convert(Board::Type before, Board::Type after) for (int i=0; itype != other.type) || (this->index != other.index); } + RawSwitch convert(Board::Type before, Board::Type after); + RawSwitchType type; int index; }; @@ -338,6 +340,7 @@ class ExpoData { int carryTrim; char name[10+1]; void clear() { memset(this, 0, sizeof(ExpoData)); } + void convert(Board::Type before, Board::Type after); }; class CurvePoint { @@ -468,6 +471,7 @@ class LogicalSwitchData { // Logical Switches data CSFunctionFamily getFunctionFamily() const; unsigned int getRangeFlags() const; QString funcToString() const; + void convert(Board::Type before, Board::Type after); }; enum AssignFunc { @@ -536,6 +540,8 @@ class CustomFunctionData { // Function Switches data static void populatePlaySoundParams(QStringList & qs); static void populateHapticParams(QStringList & qs); + void convert(Board::Type before, Board::Type after); + }; class FlightModeData { @@ -551,6 +557,7 @@ class FlightModeData { int rotaryEncoders[CPN_MAX_ENCODERS]; int gvars[CPN_MAX_GVARS]; void clear(const int phase); + void convert(Board::Type before, Board::Type after); }; class SwashRingData { // Swash Ring data @@ -1033,8 +1040,8 @@ class ModelData { ExpoData expoData[CPN_MAX_EXPOS]; CurveData curves[CPN_MAX_CURVES]; - LogicalSwitchData logicalSw[CPN_MAX_CSW]; - CustomFunctionData customFn[CPN_MAX_CUSTOM_FUNCTIONS]; + LogicalSwitchData logicalSw[CPN_MAX_LOGICAL_SWITCHES]; + CustomFunctionData customFn[CPN_MAX_SPECIAL_FUNCTIONS]; SwashRingData swashRingData; unsigned int thrTraceSrc; uint64_t switchWarningStates; @@ -1200,7 +1207,7 @@ class GeneralSettings { unsigned int switchUnlockStates; unsigned int hw_uartMode; unsigned int backlightColor; - CustomFunctionData customFn[CPN_MAX_CUSTOM_FUNCTIONS]; + CustomFunctionData customFn[CPN_MAX_SPECIAL_FUNCTIONS]; char switchName[CPN_MAX_SWITCHES][3+1]; unsigned int switchConfig[CPN_MAX_SWITCHES]; char stickName[CPN_MAX_STICKS][3+1]; diff --git a/companion/src/simulation/radiooutputswidget.cpp b/companion/src/simulation/radiooutputswidget.cpp index a7b06e7b9..d2cdd686d 100644 --- a/companion/src/simulation/radiooutputswidget.cpp +++ b/companion/src/simulation/radiooutputswidget.cpp @@ -321,7 +321,7 @@ void RadioOutputsWidget::setValues() if (ui->logicalSwitchesWidget->isVisible()) { QHash::const_iterator ls; for (ls = m_logicSwitchMap.constBegin(); ls != m_logicSwitchMap.constEnd(); ++ls) { - if (ls.key() >= CPN_MAX_CSW || (prevOutputs.vsw[ls.key()] == outputs.vsw[ls.key()] && m_lastFlightPhase > -1)) + if (ls.key() >= CPN_MAX_LOGICAL_SWITCHES || (prevOutputs.vsw[ls.key()] == outputs.vsw[ls.key()] && m_lastFlightPhase > -1)) continue; ls.value()->setBackgroundRole(outputs.vsw[ls.key()] ? QPalette::Dark : QPalette::Background); ls.value()->setForegroundRole(outputs.vsw[ls.key()] ? QPalette::BrightText : QPalette::WindowText); diff --git a/companion/src/simulation/simulatorinterface.h b/companion/src/simulation/simulatorinterface.h index 834d33746..deeaa687d 100644 --- a/companion/src/simulation/simulatorinterface.h +++ b/companion/src/simulation/simulatorinterface.h @@ -49,7 +49,7 @@ class TxOutputs public: TxOutputs() { memset(this, 0, sizeof(TxOutputs)); } int chans[CPN_MAX_CHNOUT]; - bool vsw[CPN_MAX_CSW]; + bool vsw[CPN_MAX_LOGICAL_SWITCHES]; int gvars[CPN_MAX_FLIGHT_MODES][CPN_MAX_GVARS]; unsigned int beep; // uint8_t phase; From c8be6d406da1e51ab344fa521e7f225d23cacf81 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Mon, 27 Mar 2017 23:01:51 -0400 Subject: [PATCH 054/203] [Companion] Replace erroneously removed File menu items (closes #4708). --- companion/src/mainwindow.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/companion/src/mainwindow.cpp b/companion/src/mainwindow.cpp index 5c8e40f7b..c857a86fe 100644 --- a/companion/src/mainwindow.cpp +++ b/companion/src/mainwindow.cpp @@ -1101,6 +1101,10 @@ void MainWindow::createMenus() fileMenu->deleteLater(); } fileMenu = menuBar()->addMenu(tr("File")); + fileMenu->addAction(newAct); + fileMenu->addAction(openAct); + fileMenu->addAction(saveAct); + fileMenu->addAction(saveAsAct); QMenu *recentFileMenu = new QMenu(tr("Recent Files"), fileMenu); recentFileMenu->setIcon(CompanionIcon("recentdocument.png")); From 19688ff924a756c709720cad156ec8e050696a79 Mon Sep 17 00:00:00 2001 From: 3djc Date: Tue, 28 Mar 2017 09:38:40 +0200 Subject: [PATCH 055/203] Add warning for translators --- companion/src/modelslist.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/companion/src/modelslist.cpp b/companion/src/modelslist.cpp index c29b24bfc..ff9940841 100644 --- a/companion/src/modelslist.cpp +++ b/companion/src/modelslist.cpp @@ -277,6 +277,7 @@ void TreeModel::refresh() model.category = 0; if (!defaultCategoryItem) { defaultCategoryItem = rootItem->appendChild(0, -1); + /*: Translators do NOT use accent for this, this is the default category name on Horus. */ defaultCategoryItem->setData(0, QObject::tr("Models")); } categoryItem = defaultCategoryItem; @@ -495,4 +496,4 @@ void ModelsListWidget::onCurrentItemChanged(QTreeWidgetItem * current, QTreeWidg else ((MdiChild*)parent())->viableModelSelected(!radioData->models[currentRow()-1].isEmpty()); */ } -#endif \ No newline at end of file +#endif From 02c7ef70ea9cfab45b5844def1551282c0cd492d Mon Sep 17 00:00:00 2001 From: Andre Bernet Date: Tue, 28 Mar 2017 09:49:24 +0200 Subject: [PATCH 056/203] Add headers to GVAR grid... (Re #4707) --- companion/src/modeledit/flightmodes.cpp | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/companion/src/modeledit/flightmodes.cpp b/companion/src/modeledit/flightmodes.cpp index d046f2aae..cc35ce7bc 100644 --- a/companion/src/modeledit/flightmodes.cpp +++ b/companion/src/modeledit/flightmodes.cpp @@ -153,12 +153,27 @@ FlightModePanel::FlightModePanel(QWidget * parent, ModelData & model, int phaseI // GVars if (gvCount > 0 && (firmware->getCapability(GvarsFlightModes) || phaseIdx == 0) ) { QGridLayout *gvLayout = new QGridLayout(ui->gvGB); + + // Column headers + int headerCol = 1; + QLabel *nameLabel = new QLabel(ui->gvGB); + nameLabel->setText(tr("Name")); + gvLayout->addWidget(nameLabel, 0, headerCol++, 1, 1); + if (phaseIdx > 0) { + QLabel *sourceLabel = new QLabel(ui->gvGB); + sourceLabel->setText(tr("Value source")); + gvLayout->addWidget(sourceLabel, 0, headerCol++, 1, 1); + } + QLabel *valueLabel = new QLabel(ui->gvGB); + valueLabel->setText(tr("Value")); + gvLayout->addWidget(valueLabel, 0, headerCol++, 1, 1); + for (int i=0; igvGB); label->setText(tr("GVAR%1").arg(i+1)); - gvLayout->addWidget(label, i, col++, 1, 1); + gvLayout->addWidget(label, i+1, col++, 1, 1); // GVar name int nameLen = firmware->getCapability(GvarsName); if (nameLen > 0) { @@ -166,7 +181,7 @@ FlightModePanel::FlightModePanel(QWidget * parent, ModelData & model, int phaseI gvNames[i]->setProperty("index", i); gvNames[i]->setMaxLength(nameLen); connect(gvNames[i], SIGNAL(editingFinished()), this, SLOT(GVName_editingFinished())); - gvLayout->addWidget(gvNames[i], i, col++, 1, 1); + gvLayout->addWidget(gvNames[i], i+1, col++, 1, 1); } if (phaseIdx > 0) { // GVar link to another GVar @@ -177,7 +192,7 @@ FlightModePanel::FlightModePanel(QWidget * parent, ModelData & model, int phaseI gvUse[i]->setCurrentIndex(phase.gvars[i] - 1024); } connect(gvUse[i], SIGNAL(currentIndexChanged(int)), this, SLOT(phaseGVUse_currentIndexChanged(int))); - gvLayout->addWidget(gvUse[i], i, col++, 1, 1); + gvLayout->addWidget(gvUse[i], i+1, col++, 1, 1); } // GVar value gvValues[i] = new QSpinBox(ui->gvGB); @@ -185,7 +200,7 @@ FlightModePanel::FlightModePanel(QWidget * parent, ModelData & model, int phaseI connect(gvValues[i], SIGNAL(editingFinished()), this, SLOT(phaseGVValue_editingFinished())); gvValues[i]->setMinimum(-1024); gvValues[i]->setMaximum(1024); - gvLayout->addWidget(gvValues[i], i, col++, 1, 1); + gvLayout->addWidget(gvValues[i], i+1, col++, 1, 1); // Popups if (IS_TARANIS(board) && phaseIdx == 0) { @@ -193,7 +208,7 @@ FlightModePanel::FlightModePanel(QWidget * parent, ModelData & model, int phaseI gvPopups[i]->setProperty("index", i); gvPopups[i]->setText(tr("Popup enabled")); connect(gvPopups[i], SIGNAL(toggled(bool)), this, SLOT(phaseGVPopupToggled(bool))); - gvLayout->addWidget(gvPopups[i], i, col++, 1, 1); + gvLayout->addWidget(gvPopups[i], i+1, col++, 1, 1); } } } From 061297e9b5266e4c56c54bcf6eea73d2bf0e4b6d Mon Sep 17 00:00:00 2001 From: Andre Bernet Date: Tue, 28 Mar 2017 10:51:09 +0200 Subject: [PATCH 057/203] Harmonize play delay across radios --- radio/src/gui/128x64/radio_setup.cpp | 2 +- radio/src/gui/480x272/radio_setup.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/radio/src/gui/128x64/radio_setup.cpp b/radio/src/gui/128x64/radio_setup.cpp index b6a8ded59..9c6c6d429 100644 --- a/radio/src/gui/128x64/radio_setup.cpp +++ b/radio/src/gui/128x64/radio_setup.cpp @@ -538,7 +538,7 @@ void menuRadioSetup(event_t event) lcdDrawTextAlignedLeft(y, STR_SWITCHES_DELAY); lcdDrawNumber(RADIO_SETUP_2ND_COLUMN, y, 10*SWITCHES_DELAY(), attr|LEFT); lcdDrawText(lcdLastRightPos, y, STR_MS, attr); - if (attr) CHECK_INCDEC_GENVAR(event, g_eeGeneral.switchesDelay, -15, +15); + if (attr) CHECK_INCDEC_GENVAR(event, g_eeGeneral.switchesDelay, -15, 100-15); break; #endif diff --git a/radio/src/gui/480x272/radio_setup.cpp b/radio/src/gui/480x272/radio_setup.cpp index 866b2c3e8..a2fb882d9 100644 --- a/radio/src/gui/480x272/radio_setup.cpp +++ b/radio/src/gui/480x272/radio_setup.cpp @@ -451,7 +451,7 @@ bool menuRadioSetup(event_t event) case ITEM_SETUP_SWITCHES_DELAY: lcdDrawText(MENUS_MARGIN_LEFT, y, STR_SWITCHES_DELAY); lcdDrawNumber(RADIO_SETUP_2ND_COLUMN, y, 10*SWITCHES_DELAY(), attr|LEFT, 0, NULL, STR_MS); - if (attr) CHECK_INCDEC_GENVAR(event, g_eeGeneral.switchesDelay, -15, +15); + if (attr) CHECK_INCDEC_GENVAR(event, g_eeGeneral.switchesDelay, -15, 100-15); break; case ITEM_SETUP_RX_CHANNEL_ORD: From 19e3fba836148af3b34a9679cdf4f7c8df94e294 Mon Sep 17 00:00:00 2001 From: Andre Bernet Date: Tue, 28 Mar 2017 11:16:07 +0200 Subject: [PATCH 058/203] [companion] Update all translation files --- companion/src/translations/companion_cs.ts | 7851 +++++++++------- companion/src/translations/companion_de.ts | 7992 +++++++++------- companion/src/translations/companion_en.ts | 2465 ++--- companion/src/translations/companion_es.ts | 8016 +++++++++------- companion/src/translations/companion_fi.ts | 7952 +++++++++------- companion/src/translations/companion_fr.ts | 2057 ++--- companion/src/translations/companion_it.ts | 8030 +++++++++------- companion/src/translations/companion_pl.ts | 8120 ++++++++++------- companion/src/translations/companion_sv.ts | 3623 +++++--- companion/src/translations/companion_zh_CN.ts | 5561 ++++++----- 10 files changed, 36519 insertions(+), 25148 deletions(-) diff --git a/companion/src/translations/companion_cs.ts b/companion/src/translations/companion_cs.ts index e283c6cfe..5b790bcbb 100644 --- a/companion/src/translations/companion_cs.ts +++ b/companion/src/translations/companion_cs.ts @@ -1,30 +1,30 @@ - + AileronsPage - + No Ne - + Yes, controlled by a single channel Ano, ovládané jedním kanálem - + Yes, controlled by two channels Ano, ovládané dvěma kanály - + <br>First Aileron Channel: <br>První kanál křidélek: - + Second Aileron Channel: <br>Druhý kanál křidélek: @@ -32,27 +32,27 @@ AirbrakesPage - + No Ne - + Yes, controlled by a single channel Ano, ovládané jedním kanálem - + Yes, controlled by two channels Ano, ovládané dvěma kanály - + <br>First Airbrake Channel: <br>První kanál brzdících klapek: - + Second Airbrake Channel: <br>Druhý kanál brzdících klapek: @@ -524,498 +524,149 @@ Může být jiná než verze firmwaru Pamatovat si polohy přepínačů v simulátoru - + My Radio Moje rádio - + Select your snapshot folder Vyberat složku pro snímky obrazovky simulátoru - - + + No joysticks found Joystick nenalezen - + EMPTY: No radio settings stored in profile PRÁZDNÉ: V profilu nejsou uložena žádná nastavení rádia - + AVAILABLE: Radio settings of unknown age DOSTUPNÉ: Nastavení rádia jsou neznámého stáří - + AVAILABLE: Radio settings stored %1 DOSTUPNÉ: Nastavení rádia jsou uložena %1 - + Select your library folder Vyberat složkus s logy - - + + Select your Models and Settings backup folder Zvolit složku pro automatické zálohy modelů a nastavení - + Select Google Earth executable Zvolit spustitelnou binárku aplikace Google Earth - + Select the folder replicating your SD structure Vyberat složku která představuje obsah SD karty rádia - + Not possible to remove profile Není možné odebrat profil - + The default profile can not be removed. Výchozí profil nemůže být odstraněn. - + Open Image to load Otevřít soubor s logem - + Images (%1) Obrázky (%1) - - Calibration - - - Form - - - - - SQ - - - - - SR - - - - - LS2 - - - - - SP - - - - - SO - - - - - S4 - - - - - RS - - - - - SB - - - - - Serial Port - Seriový port - - - - - - - - - - - - - Beeper volume - -0 - Quiet. No beeps at all. -1 - No Keys. Normal beeps but menu keys do not beep. -2 - Normal. -3 - Loud. -4 - Extra loud. - Hlasitost Bzučáku - -0 - Tichý. No beeps at all. -1 - Bez kláves. Normal beeps but menu keys do not beep. -2 - Normální. -3 - Hlasitý. -4 - Extra Hlasitý. - - - - OFF - Vypnuto - - - - S-Port Mirror - Zrcadlit S-Port - - - - Telemetry - Telemetrie - - - - SBUS Trainer - SBUS trenér - - - - Debug - - - - - Rud - Směrovka - - - - - Mid value - Střed - - - - Pot. 4 - - - - - Pot. 3 - - - - - Pot. 2 - - - - - Pot. 1 - - - - - PPM 1 - - - - - Stick 3 - Páka 3 - - - - - Negative span - Negativní - - - - - Positive span - Pozitivní - - - - Stick 1 - Páka 1 - - - - PPM 2 - - - - - Stick 2 - Páka 2 - - - - Stick 4 - Páka 4 - - - - v - V - - - - PPM Multiplier - PPM Násobič - - - - PPM 3 - - - - - PPM 4 - - - - - Battery Offset - Ofset baterie - - - - Current Offset - Ofset proudu - - - - S1 - - - - - S2 - - - - - S3 - - - - - SA - - - - - Ele - Výškovka - - - - Ail - Křidélka - - - - Thr - Plyn - - - - SC - - - - - LS - - - - - SD - - - - - SE - - - - - SF - - - - - SG - - - - - SH - - - - - SI - - - - - SJ - - - - - SK - - - - - SL - - - - - SM - - - - - SN - - - - - RS2 - - - - - Bluetooth - - - - - CalibrationPanel - - - - - None - Žádný - - - - 2 Positions Toggle - 2 pozice bez aretace - - - - 2 Positions - 2 pozice - - - - 3 Positions - 3 pozice - - - - Pot with detent - Pot s aretací - - - - Multipos switch - Vícepolohový přepínač - - - - Pot without detent - Pot bez aretace - - - - Slider with detent - Jezdec s aretací - - Channels - + Name Název - + Min - + Max - + Subtrim - + Direction Invertovat - + Curve Křivka - + PPM Center Střed - + Linear Subtrim Symetrický - - Channel %1 - Kanál %1 + + CH%1 + - + --- - + INV + + CompanionMacros + + + files + + + + + Radio and Models settings + + + CompareDialog @@ -1049,17 +700,17 @@ Může být jiná než verze firmwaru Tisk do souboru - + No name Model nepojmenován - + Print Document Vytisknout dokument - + Select PDF output file Vyberte cílový PDF soubor @@ -1067,7 +718,7 @@ Může být jiná než verze firmwaru ConclusionPage - + OK, I understand. OK, rozuměl jsem. @@ -1075,43 +726,43 @@ Může být jiná než verze firmwaru ContributorsDialog - + OpenTX Contributors Přispěvatelé OpenTX - + Main Developers Vývojáři - + Other contributors Ostatní přispěvatelé - + Companies and projects who have donated to OpenTX Společnosti a projekty které přispěly OpenTx - + People who have donated to OpenTX Lidé kteří přispěli projektu OpenTx - + Honors go to Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) Speciální poděkování patří Rafalu Tomczakovi (RadioClone), Thomasi Hustererovi (th9x) a také Erazovi Ravivovi(er9x a eePe) - + OpenTX Blacklist - + monthly měsíčně @@ -1119,24 +770,24 @@ Thomasi Hustererovi (th9x) a také Erazovi Ravivovi(er9x a eePe) CopyProcess - - - + + + Error Chyba - + Write error Chyba zápisu - + Cannot write %1 (reason: %2) Nelze zapsat %1 (důvod: %2) - + Cannot open %1 (reason: %2) Nelze otevřít %1 (důvod: %2) @@ -1144,22 +795,22 @@ Thomasi Hustererovi (th9x) a také Erazovi Ravivovi(er9x a eePe) CurveGroup - + Diff Diferenciace - + Expo Exponenciála - + Func Funkce - + Curve Křivka @@ -1248,72 +899,72 @@ Thomasi Hustererovi (th9x) a také Erazovi Ravivovi(er9x a eePe) Název křivky - + Curve %1 Křivka %1 - + %1 points %1 bodů - + Linear Lineární - + Single Expo Expo - + Symmetrical f(x)=-f(-x) Symetrická f(x)=-f(-x) - + Symmetrical f(x)=f(-x) Symetrická f(x)=f(-x) - + Copy Kopírovat - + Paste Vložit - + Clear Vymazat - + Clear all curves Vymazat všechny křivky - + Are you sure you want to reset curve %1? Opravdu chcete vymazat křivku %1? - + Are you sure you want to reset all curves? Opravdu chcete vymazat všechny křivky? - + Editing curve %1 Upravit křivku k%1 - + Not enough free points in EEPROM to store the curve. V nastavení modelu již nejsou volné body k uložení této křivky. @@ -1321,88 +972,88 @@ Thomasi Hustererovi (th9x) a také Erazovi Ravivovi(er9x a eePe) CustomFunctionsPanel - + Switch Spínač - + Action Akce - + Parameters Hodnota - + Enable Povolit - + SF%1 - + GF%1 - + ON Překlad se do formuláře nevejde. Zap - + Error Chyba - + Unable to find sound file %1! Nemohu nalézt zvukový soubor %1! - + &Delete &Odstranit - + Delete - + &Copy &Kopírovat - + Ctrl+C - + &Cut V&yjmout - + Ctrl+X - + &Paste &Vložit - + Ctrl+V @@ -1410,22 +1061,22 @@ Thomasi Hustererovi (th9x) a také Erazovi Ravivovi(er9x a eePe) CyclicPage - + 90 - + 120 - + 120x - + 140 @@ -1433,99 +1084,175 @@ Thomasi Hustererovi (th9x) a také Erazovi Ravivovi(er9x a eePe) DebugOutput - + Debug Output + + + <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> + + + + + Filter: + + + + + <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> +To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> + + + + + Buffer: + + + + + Number of lines to keep in display. + + + + + Filter &Help + + + + + Show information about using the filter. + + + + + Word &Wrap + + + + + Toggle word wrapping on/off. + + + + + &Clear + + + + + Clear the output window of all text. + + + + + Enable &Filter + + + + + Turn the filter on/off. + + + + + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> + + + + + Debug Console Filter Help + + EepromInterface - + Possible causes for this: Možné příčiny: - + - Eeprom is from a newer version of OpenTX - eeprom pochází z novější verze OpenTX - + - Eeprom is not from OpenTX - eeprom nepochází z OpenTX - + - Eeprom is not from Th9X - eeprom nepochází z Th9X - + - Eeprom is not from Gruvin9X - eeprom nepochází z Gruvin9X - + - Eeprom is not from ErSky9X - eeprom nepochází z Ersky9X - + - Eeprom is not from Er9X - eeprom nepochází z Er9X - + - Eeprom size is invalid - velikost eeprom není platná - + - Eeprom file system is invalid - eeprom struktura souboru je poškozená - + - Eeprom is from a unknown board - eeprom pochází z neznámé hw platformy - + - Eeprom is from the wrong board - eeprom pochází z jiné desky - + - Eeprom backup not supported - záloha eeprom není podporována - + - Something that couldn't be guessed, sorry - problém který neumíme určit, bohužel - + Warning: Varování: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used Vaše rádio možná používá jiný firmware než by mělo, velikost eeprom je 4096, ale jen polovina je používána - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - Vaše eeprom pochází ze starší verze openTX, aktualizuji! Měl byste ji 'Uložit jako' pro uchování starší verze jako zálohy. - + Warnings! Pozor! @@ -1533,12 +1260,12 @@ Měl byste ji 'Uložit jako' pro uchování starší verze jako záloh ElevonsPage - + <br>First Elevon Channel: <br>První kanál elevonů: - + Second Elevon Channel: <br>Druhý kanál elevonů: @@ -1655,30 +1382,50 @@ Pokud není použito, vstup je AKTIVNÍ stále. Křivka která se aplikuje na zdroj. - + Edit %1 Upravit %1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + FblPage - + Throttle Channel: Kanál plynu: - + Yaw Channel: Kanál bočení: - + Pitch Channel: Kanál klopení: - + Roll Channel: Kanál klonění: @@ -1731,27 +1478,27 @@ Může být jiná než verze firmwaru FlapsPage - + No Ne - + Yes, controlled by a single channel Ano, ovládané jedním kanálem - + Yes, controlled by two channels Ano, ovládané dvěma kanály - + <br>First Flap Channel: <br>První kanál klapek: - + Second Flap Channel: <br>Druhý kanál klapek: @@ -1760,7 +1507,7 @@ Může být jiná než verze firmwaru FlashEEpromDialog - + Write Models and Settings to Radio Zapsat modely a nastavení do rádia @@ -1776,7 +1523,6 @@ Může být jiná než verze firmwaru - Allows Companion to write to older version of the firmware Umožní Companion zapisovat do starší verze firmware @@ -1785,6 +1531,11 @@ Může být jiná než verze firmwaru Check Firmware compatibility Zkontrolovat kompatibilitu firmware + + + <html><head/><body><p>Saves a dated copy of your eeprom to the backup folder you specified in the Companion settings before writing the current model to the radio.</p></body></html> + + Backup before Write @@ -1821,107 +1572,66 @@ Může být jiná než verze firmwaru Zapsat do rádia - + Current profile: %1 Současný profil: %1 - + Choose Radio Backup file Vyberte soubor se zálohou rádia - - - - - - - - - - + + Error Chyba - - - Unable to find file %1! - Nemohu nalézt soubor %1! - - - - - - Error opening file %1: -%2. - Chyba při otevírání souboru %1: -%2. - - - - - Invalid Models and Settings File %1 - Neplatný soubor modelů a nastavení %1 - - - - Error reading file %1: -%2. - Chyba při otevírání souboru %1: -%2. - - Invalid Models and Settings file %1 - Neplatný soubor modelů a nastavení %1 - - - - - - + + + Warning Pozor - + Wrong radio calibration data in profile, Settings not patched Profil neobsahuje platná kalibrační data, nastavení nebyla upravena - + Wrong radio setting data in profile, Settings not patched Profil neobsahuje platná data nastavení rádia, nastavení nebyla upravena - - + Cannot write file %1: %2. Nelze zapsat soubor %1: %2. - + Error writing file %1: %2. Chyba při zápisu souboru %1: %2. - + The radio firmware belongs to another product family, check file and preferences! Firmware rádia je z jiné rodiny produktů , zkontrolujte nastavení předvoleb! - + The radio firmware is outdated, please upgrade! Firmware rádia je zastaralý, aktualizujte ho prosím! - + Cannot check Models and Settings compatibility! Continue anyway? Nelze ověřit kompatibilitu dat modelů a nastavení! Chcete přesto pokračovat? @@ -1999,119 +1709,119 @@ Může být jiná než verze firmwaru Zapsat do rádia - + Open Firmware File Otevřít soubor firmwaru - - - + + + Warning Pozor - + %1 may not be a valid firmware file %1 nemusí být platný soubor firmwaru - - - - + + + + Error Chyba - + The firmware file is not valid. Soubor firmwaru není platný. - + There is no start screen image in the firmware file. Soubor firmware neobsahuje žádné logo. - + Profile image %1 is invalid. Obrázek profilu %1 není platný. - + Open image file to use as radio start screen Otevřít soubor obrázku pro použití jako úvodní logo - + Images (%1) Obrázky (%1) - + Image could not be loaded from %1 Nelze načíst obrázek z %1 - + The library image could not be loaded Nelze načíst obrázek z knihovny - + Splash image not found Obrázek loga nebyl nalezen - + Cannot save customized firmware Nelze uložit upravený firmware - + Write Firmware to Radio Zapsat firmware do rádia - - + + Firmware check failed Kontrola firmwaru selhala - + Could not check firmware from radio Nelze ověřit firmware v rádiu - + New firmware is not compatible with the one currently installed! Nový firmware není kompatibilní s verzí instalovanou v rádiu! - + Conversion failed Převod selhal - + Cannot convert Models and Settings for use with this firmware, original data will be used Nemohu převést modely a nastavení pro použití s tímto firmwarem, budou použita původní data - + Restore failed Obnovení selhalo - + Could not restore Models and Settings to Radio. The models and settings data file can be found at: %1 Nelze obnovit modely a nastavení rádia. Data modelů a nastavení naleznete v %1 - + Flashing done Zápis firmware je dokončen @@ -2119,47 +1829,47 @@ Může být jiná než verze firmwaru FlashProcess - + Executable %1 not found Spustitelný soubor %1 nebyl nalezen - + Writing... Zápis... - + Reading... Načítání... - + Verifying... Ověřování... - + unknown neznámý - + ie: OpenTX for 9X board or OpenTX for 9XR board ie: OpenTX pro desku 9X nebo OpenTX pro 9XR - + ie: OpenTX for M128 / 9X board or OpenTX for 9XR board with M128 chip ie: OpenTX pro M128 / 9X nebo OpenTX pro 9XR s čipem M128 - + ie: OpenTX for Gruvin9X board ie: OpenTX pro desku Gruvin9X - + Your radio uses a %1 CPU!!! Please check advanced burn options to set the correct cpu type. @@ -2168,7 +1878,7 @@ Please check advanced burn options to set the correct cpu type. Zkontrolujte prosím rozšířená nastavení programátoru a nastavte správný typ CPU. - + Your radio uses a %1 CPU!!! Please select an appropriate firmware type to program it. @@ -2177,7 +1887,7 @@ Please select an appropriate firmware type to program it. Vyberte prosím správný typ firmwaru. - + You are currently using: %1 @@ -2186,7 +1896,7 @@ Nyní používáte: %1 - + Your radio does not seem connected to USB or the driver is not installed!!! Please use ZADIG to properly install the driver. @@ -2195,22 +1905,22 @@ Please use ZADIG to properly install the driver. Prosím, použijte program Zadig pro správnou instalaci ovladače. - + Your radio does not seem connected to USB or the driver is not initialized!!!. Vaše rádio není připojeno k USB nebo není inicializován ovladač!. - + Flashing done (exit code = %1) Zápis je dokončen (exit code = %1) - + Flashing done with errors Zápis byl dokončen s chybami - + FUSES: Low=%1 High=%2 Ext=%3 POJISTKY MCU: Low=%1 High=%2 Ext=%3 @@ -2241,35 +1951,65 @@ Prosím, použijte program Zadig pro správnou instalaci ovladače. FlightModePanel - + Rotary Encoder %1 Otočný enkodér %1 - + + Name + Název + + + + Value source + + + + + Value + Hodnota + + + GVAR%1 GP%1 - + Popup enabled Vyskakovací okno povoleno + + + &Clear + + + + + Clear + Vymazat + + + + Clear all current Flight Mode properties? + + FlightModesPanel - + Flight Mode %1 Letový režim %1 - + (%1) - + (default) (výchozí) @@ -2277,17 +2017,17 @@ Prosím, použijte program Zadig pro správnou instalaci ovladače. FlybarSelectionPage - + Has Flybar Má stabilizátor(Flybar) - + Flybarless Bez stabilizátoru (Flybarless) - + Flybar: Stabilizátor: @@ -2393,24 +2133,19 @@ p, li { white-space: pre-wrap; } <p align="center" style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Provádějte pouze pokud opravdu víte co děláte.</p></body></html> - - + + Reset Radio Fuses - + Read Fuses from Radio GeneralEdit - - - General Edit - Obecná nastavení - Store calib. and hw settings in selected profile @@ -2421,6 +2156,11 @@ p, li { white-space: pre-wrap; } Retrieve calib. and hw settings from profile Získat kalibraci a HW nastavení z profilu + + + Radio settings + + General settings used throught the transmitter. @@ -2429,48 +2169,59 @@ These will be relevant for all models in the same EEPROM. Tyto volby jsou platné pro všechny modely v jedné EEPROM. - + Setup Nastevní - + Trainer Trenér - + Global Functions Globální funkce - - Hardware / Calibration - Hardware / Kalibrace + + Hardware + - - + + Calibration + + + + + + Warning Pozor - + Wrong data in profile, radio calibration was not retrieved Špatná data v profilu, není možné získat parametry kalibrace - + + Wrong data in profile, Switch/pot config not retrieved + + + + Wrong data in profile, hw related parameters were not retrieved Špatná data v profilu, není možné získat HW parametry - + Do you want to store calibration in %1 profile<br>overwriting existing calibration? Chcete uložit kalibraci do profilu %1<br>Přepsat existující kalibraci? - + Calibration and HW parameters saved. Kalibrace a HW parametry byly uloženy. @@ -2528,173 +2279,172 @@ Tyto volby jsou platné pro všechny modely v jedné EEPROM. - + Timeshift from UTC Časový posun od UTC - + Voice Language Jazyk hlasových zpráv - + Country Code Kód země - + Stick reverse Revers os kniplů - + FAI Mode FAI mód - - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. FAI je soutéžní mód (www.fai.org), zablokuje vario, zobrazení telemetrie a funkce hlasového hlášení. Tuto funkci nelze vypnout v menu rádia. - + Adjust RTC Nastavit RTC - + Vario pitch at max Tón varia na maximu - - + + Hz - + Speaker Volume Hlasitost reproduktoru - + Backlight Switch Spínač podsvětlení - + Sound Mode Mód zvuku - + Color 1 Barva 1 - + Color 2 Barva 2 - + Speaker Pitch (spkr only) Tón zvuku (pouze spkr) - + If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. Pokud tato hodnota není nula, každé stisknutí klávesy zapne podsvétlení a vypne ho až po uplynutí nastaveného počtu sekund. - + sec s - + Backlight color Barva podsvětlení - + Beeper Bzučák - + Speaker Reproduktor - + BeeperVoice Bzučák+Hlas - + SpeakerVoice Repro+Hlas - + Beep volume Upozornění - + Wav volume Wav soubor - + Vario volume Vario - + Background volume Zvuk v pozadí - - + + ms - + Backlight Auto OFF after Auto. vypnutí podsvětlení po - + Backlight flash on alarm Blik. podsvětlením při alarmu - + Vario pitch at zero Tón varia na nule - + Vario repeat at zero Opakování varia na nule - + This is the switch selectrion for turning on the backlight (if installed). Toto je volba spínače který zapne podsvětlení (pokud je nainstalováno). - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2709,32 +2459,42 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">Hodnoty mohou být 20-45</span></p></body></html> - + Backlight Brightness Jas podsvětlení - + RotEnc Navigation Navigace otočným enkodérem - + + Automatically adjust the radio's clock if a GPS is connected to telemetry. + + + + America Amerika - + Japan Japonsko - + Europe Evropa - + + Backlight OFF Brightness + + + + Mode selection: Mode 1: @@ -2775,271 +2535,271 @@ Mode 4: - + Mode 1 (RUD ELE THR AIL) Mód1 (Směr.Výšk.Plyn.Křid) - + Mode 2 (RUD THR ELE AIL) Mód2 (Směr.Plyn.Výšk.Křid) - + Mode 3 (AIL ELE THR RUD) Mód3 (Křid.Výšk.Plyn.Směr) - + Mode 4 (AIL THR ELE RUD) Mód4 (Křid.Plyn.Výšk.Směr) - + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> <html><head/><body><p>Pořadí kanálů</p><p><br/></p><p>Definuje výchozí pořadí kanálů použité při vytvoření nového modelu.</p></body></html> - + R E T A S V P K - + R E A T S V K P - + R T E A S P V K - + R T A E S P K V - + R A E T S K V P - + R A T E S K P V - + E R T A V S P K - + E R A T V S K P - + E T R A V P S K - + E T A R V P K S - + E A R T V K S P - + E A T R V K P S - + T R E A P S V K - + T R A E P S K V - + T E R A P V S K - + T E A R P V K S - + T A R E P K S V - + T A E R P K V S - + A R E T K S V P - + A R T E K S P V - + A E R T K V S P - + A E T R K V P S - + A T R E K P S V - + A T E R K P V S - + Stick Mode Výchozí mód vysílačky - + Metric Metrické - + Imperial Imperiální - + Default Channel Order Výchozí pořadí kanálů - + GPS Coordinates Souřadnice GPS - + Min - - + + v V - + Max - + Low Memory Warning Upozornit na nedostatek paměti - + Inactivity Timer Časovač nečinnosti - + Show Splash Screen on Startup Zobrazit úvodní logo - + Contrast Kontrast - + Battery Meter Range Rozsah ukazatele baterie - + Haptic Strength Síla vibrací - + LCD Display Type Typ LCD zobrazovače - + "No Sound" Warning Upozornění na vypnutý zvuk - + Battery Warning Alarm baterie - + Haptic Length Délka vibrací - + MAVLink Baud Rate - - + + Quiet Tichý - + Only Alarms Jen alarm - - + + No Keys Bez kláves - - + + All Vše - + Battery warning voltage. This is the threashhold where the battery warning sounds. @@ -3048,114 +2808,114 @@ Acceptable values are 5v..10v Použitelné hodnoty jsou 5v..10v - + Standard - + Optrex - + If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. Pokud není nastaveno na nulu, bude zapnuto zvukové upozornění, že jste rádio nechali bez povšimnutí nastavený počet minut. - + min - - + + Show splash screen on startup Zobrazit úvodní logo při zapnutí vysílčky - + --- - + 2s - + 3s - + 4s - + 6s - + 8s - + 10s - + 15s - + 4800 Baud - + 9600 Baud - + 14400 Baud - + 19200 Baud - + 38400 Baud - + 57600 Baud - + 76800 Baud - + 115200 Baud - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -3170,72 +2930,72 @@ p, li { white-space: pre-wrap; } - - + + X-Short Extra krátký - - + + Short Krátký - - + + Normal Normální - - + + Long Dlouhý - - + + X-Long Extra dlouhý - - + + hh° (N/S) mm' ss''.dd - + NMEA - + Play Delay (switch mid position) Přechod střední polohy přepínače - + Measurement Units Měrné jednotky - + Haptic Mode Mód vibrací - + Beeper Length Délka zvuku - + Beeper Mode Mód zvuku - + Beeper volume 0 - Quiet. No beeps at all. @@ -3252,7 +3012,7 @@ p, li { white-space: pre-wrap; } 4 - Extra Hlasitý. - + Alarms Only Jen alarmy @@ -3260,7 +3020,7 @@ p, li { white-space: pre-wrap; } GeneralSetupPanel - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Are you sure ? @@ -3273,21 +3033,324 @@ Opravdu to takto chcete ? GyroPage - + No Ne - + Yes, controled by a switch Ano, ovládané spínačem - + Yes, controlled by a pot Ano, ovládané potenciomerem + + Hardware + + + Form + + + + + SQ + + + + + SR + + + + + LS2 + + + + + SP + + + + + SO + + + + + S4 + S4 + + + + RS + + + + + SB + + + + + PPM 2 + + + + + + + + + + + + + + Beeper volume + +0 - Quiet. No beeps at all. +1 - No Keys. Normal beeps but menu keys do not beep. +2 - Normal. +3 - Loud. +4 - Extra loud. + + + + + OFF + + + + + S-Port Mirror + Zrcadlit S-Port + + + + Telemetry + Telemetrie + + + + SBUS Trainer + SBUS trenér + + + + Debug + + + + + Rud + Směrovka + + + + PPM 3 + + + + + S1 + S1 + + + + S2 + S2 + + + + S3 + S3 + + + + PPM 1 + + + + + Serial Port + Seriový port + + + + v + V + + + + PPM Multiplier + PPM Násobič + + + + Current Offset + Ofset proudu + + + + PPM 4 + + + + + SA + + + + + Ele + Výškovka + + + + Ail + Křidélka + + + + Thr + + + + + SC + + + + + LS + + + + + SD + + + + + Battery Offset + Ofset baterie + + + + SE + + + + + SF + + + + + SG + + + + + SH + + + + + SI + + + + + SJ + + + + + SK + + + + + SL + + + + + SM + + + + + SN + + + + + RS2 + + + + + Bluetooth + + + + + ADC Filter + + + + + HardwarePanel + + + + + None + Žádný + + + + 2 Positions Toggle + 2 pozice bez aretace + + + + 2 Positions + 2 pozice + + + + 3 Positions + 3 pozice + + + + Pot with detent + Pot s aretací + + + + Multipos switch + Vícepolohový přepínač + + + + Pot without detent + Pot bez aretace + + + + Slider with detent + Jezdec s aretací + + Heli @@ -3364,22 +3427,22 @@ Opravdu to takto chcete ? HeliPage - + Throttle Channel: Kanál plynu: - + Yaw Channel: Kanál bočení: - + Pitch Channel: Kanál klopení: - + Roll Channel: Kanál klonění: @@ -3387,122 +3450,122 @@ Opravdu to takto chcete ? InputsPanel - - + + Move Up Posunout nahoru - - + + Ctrl+Up Ctrl+Nahoru Ctrl+Up - - + + Move Down Posunout dolů - - + + Ctrl+Down Ctrl+Dolů - + Clear All Inputs Vymazat všechny vstupy - + Not enough available inputs! Již nejsou další volné vstupy! - + Delete Selected Inputs? Vymazat vybrané vstupy? - + &Add &Přidat - + Ctrl+A - + &Edit &Upravit - + Enter - + &Delete V&ymazat - + Delete - + &Copy &Kopírovat - + Ctrl+C - + &Cut Vyj&mout - + Ctrl+X - + &Paste &Vložit - + Ctrl+V - + Du&plicate &Duplikovat - + Ctrl+U - + Clear Inputs? Vymazat vstupy? - + Really clear all the inputs? Opravdu chcete vymazat všechny vstupy? @@ -3510,88 +3573,89 @@ Opravdu to takto chcete ? LogicalSwitchesPanel - + V1 - + V2 - + Duration Trvání - + Delay Zpoždění - + Function Funkce - + AND Switch AND spínač - + L%1 - - + + (instant) - + &Delete Vy&mazat - + Delete - + &Copy &Kopírovat - + + (infinite) - + Ctrl+C - + &Cut V&yjmout - + Ctrl+X - + &Paste &Vložit - + Ctrl+V @@ -3604,146 +3668,166 @@ Opravdu to takto chcete ? Prohlížeč logu - + Filename Soubor - + Open LogFile Otevřít - + Zoom - + X - + Y - + Reset - + Fly sessions Lety - + Telemetry logs Logy telemetrie - + Time (hh:mm:ss) Čas (hh:mm:ss) - + Plot Title Change - + New plot title: - + Axis Label Change - + New axis label: - + Graph Name Change - + New graph name: - + Error: no GPS data not found - + The column containing GPS coordinates must be named "GPS". The columns for altitude "GAlt" and for speed "GSpd" are optional - + Error Chyba - + Cannot write file %1: %2. Nelze zapsat soubor %1: %2. - + + Cursor A: %1 m + + + + + Cursor B: %1 m + + + + + Time delta: %1 + + + + + Climb rate: %1 m/s + + + + Select your log file Vyberte soubor s logy - + Available fields Dostupná pole - + The selected logfile contains %1 invalid lines out of %2 total lines Zvolený soubor logu obsahuje %1neplatných řádků z celkových %2 - + total duration - + duration - + (L1) - + (R1) - + (L2) - + (R2) @@ -3751,261 +3835,239 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt MainWindow - - - - + + File loaded Soubor byl načten - + Display previous warning again at startup ? Chcete zobrazit předchozí upozornění i příště ? - + Checking for updates Kontroluji aktualizace - + Unable to check for updates. Nelze ověřit aktualizace. - - + + Save As Uložit jako - + Executable (*.exe) Spustitelný (*.exe) - + New release available Je dostupné nové vydání - - + + No updates available at this time. Žádné aktualizace nejsou nyní dostupné. - + Would you like to launch the installer? Chcete spustit instalátor? - - + + Error Chyba - + Error opening file %1: %2. Chyba při otevírání souboru %1: %2. - - Compilation server termporary failure, try later - Server companion je dočasně nedostupný, zkuste to později - - - + A new release of Companion is available, please check the OpenTX website! Je dostupná nová verze Companion, prosím navštivte internetové stránky OpenTX! - - Not enough memory for all the selected firmware options - Není dostatek paměti pro všechny zvolené vlastnosti firmwaru - - - + Compilation server too busy, try later Server companion je zaneprázdněn, zkuste to později - + Unknown server failure, try later Neznámá chyba serveru, zkuste to později - + Do you want to write the firmware to the radio now ? Chcete zapsat firmware do rádia nyní? - - + + Yes Ano - - + + No Ne - - + + Release Notes Poznámky k vydání - - + + Do you want to download release %1 now ? Chcete nyní stáhnout vydání %1 ? - - + + File saved Soubor byl uložen - + Firmware updates Aktualizace firmwaru - + Current firmware does not provide release notes informations. K tomuto firmwaru nejsou poznámky k vydání. - + A new version of Companion is available (version %1)<br>Would you like to download it? Je dostupná nová verze Companion (verze %1)<br>Chcete ji nyní stáhnout? - - Compilation server requires registration, please check OpenTX web site - Kompilační server vyžaduje registraci, prosím navštivte internetové stránky OpenTX - - - + Ignore this release %1? Ignorovat tuto verzi %1? - - The selected language will be used the next time you start Companion. - Zvolený jazyk bude použit při příštím spuštění Companion. - - - + The new theme will be loaded the next time you start Companion. Nové téma bude použito při příštím spuštění Companion. - + The icon size will be used the next time you start Companion. Zvolená velikost ikon bude použita při příštím spuštění Companion. - + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> Projekt OpenTX Companion vznikl oddělením z <a href='%1'>eePe</a> - + Load backup from file Načíst zálohu ze souboru - - + + Open Models and Settings file Otevřít soubor modelů a nastavení - + Read Models and Settings From Radio Načíst modely a nastavení z rádia - + Save Radio Backup to File Uložit zálohu rádia do souboru - + Read Radio Firmware to File Načíst firmware rádia do souboru - + OpenTX Home Page: <a href='%1'>%1</a> Internetová stránka OpenTX : <a href='%1'>%1</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> Pokud vám byl tento program užitečný, podpořte jej <a href='%1'>darem</a> - + Copyright OpenTX Team - + About Companion O aplikaci Companion - + New Nový - + Open... Otevřít - + Save Uložit - + Save As... Uložit jako... - + Copy Model Kopírovat model - + Paste Model Vložit model - + Compare models Porovnat modely - + Exit the application Ukončit aplikaci - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -4018,7 +4080,7 @@ Chcete ho stáhnout nyní? Doporučujeme prohlédnout poznámky k vydání, pomocí tlačítka níže se dozvíte o případných změnách, které mohou být pro vás důležité. - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -4035,574 +4097,533 @@ Chcete firmware stáhnout nyní? Doporučujeme prohlédnout poznámky k vydání, pomocí tlačítka níže se dozvíte o případných změnách, které mohou být pro vás důležité. - - + + Synchronize SD Synchronizace SD - + A monochrome black icon theme Černé mono téma - + A monochrome white icon theme Bílé mono téma - + A monochrome blue icon theme Modré mono téma - + Small Malá - + Use small toolbar icons Použít malé ikony nástrojové lišty - + Use normal size toolbar icons Použít normální velikost ikon nástrojové lišty - + Normal Normální - + Use big toolbar icons Použít velké ikony nástrojové lišty - + Big Velká - + Use huge toolbar icons Použít největší ikony nástrojové lišty - + Huge Největší - + Create a new Models and Settings file Vytvořit nový soubor modelů a nastavení - - + + Save Models and Settings file Uložit soubor modelů a nastavení - + Exit Ukončit - + Cut Model Vyjmout model - + Cut current model to the clipboard Vyjmout aktuální model a uložit do schránky - + Copy current model to the clipboard Kopírovat aktuální model do schránky - + Paste model from clipboard Vložit obsah schránky na aktuální pozici - + Classical Klasik9x - + The classic companion9x icon theme Původní téma companion9x - + Yerico - + Yellow round honey sweet icon theme Žluté medové téma - + Monochrome Mono - + MonoWhite Mono-bílé - + MonoBlue Mono-modré - + System language Výchozí jazyk prostředí - - Use system language in menus - Použít systémový jazyk - - - - Czech - Čeština - - - - Use Czech in menus - Aplikace v českém jazyce - - - - German - - - - - Use German in menus - - - - - English - - - - - Use English in menus - - - - - Finnish - - - - - Use Finnish in menus - - - - - French - - - - - Use French in menus - - - - - Italian - - - - - Use Italian in menus - - - - - Polish - - - - - Use Polish in menus - - - - - Spanish - - - - - Use Spanish in menus - - - - - Swedish - - - - - Use Swedish in menus - - - - + About... O aplikaci - + Print... Tisk - + Print current model Vytisknout zvolený model - + Simulate... Simulace - + Simulate current model Simulace vybraného modelu - + Alt+S - + Load Backup... Načíst zálohu... - + View Log File... Zobrazit Log - + Open and view log file Otevře a zobrazí soubor logu rádia - + Settings... Předvolby... - + Edit Settings Upravit nastavení předvoleb - + Download... Stáhnout - + Download firmware and voice files Stáhnout firmware a hlasové soubory - + Check for Updates... Zkontrolovat aktualizace - + Check OpenTX and Companion updates Zkontrolovat aktualizace OpenTX a Companion - + Companion Changes... Změny Companion - + Show Companion change log Zobrazí seznam změn jednotlivých vydání Companion - + Firmware Changes... Změny Firmwaru - + Show firmware change log Zobrazí seznam změn jednotlivých vydání Firmware - + Compare Models... Porovnat modely... - + Edit Radio Splash Image... Upravit úvodní logo rádia... - + Edit the splash image of your Radio Upravit úvodní grafické logo rádia - + List programmers... Seznam programátorů... - + Fuses... Pojistky mikrokontroléru... - - + + Read Firmware from Radio Načíst firmware z rádia - + Read firmware from Radio Načíst firmware z rádia - - + Write Firmware to Radio Zapsat firmware do rádia - + Write firmware to Radio Zapsat firmware do rádia - + Add Radio Profile Nový profil rádia - + Create a new Radio Setting Profile Vytvořit nový profil nastavení rádia - + Manuals and other Documents Manuály a jiné dokumenty - + Open the OpenTX document page in a web browser Otevřít stránku s dokumenty OpenTX v prohlížeči - + Write Models and Settings To Radio Zapsat modely a nastavení do rádia - - + Write Models and Settings to Radio Zapsat modely a nastavení do rádia - - - + + + Companion - - + + Not enough flash available on this board for all the selected options + + + + + Compilation server temporary failure, try later + + + + + Compilation error + + + + + Invalid firmware + + + + + Invalid board + + + + + Invalid language + + + + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + + + + + Read Models and Settings from Radio Načíst modely a nastavení z rádia - + + Models and Settings read + + + + + + This function is not yet implemented + + + + OpenTX Companion %1 - Radio: %2 - Profile: %3 OpenTX Companion %1 - Rádio: %2 - Profil: %3 - + Configure Communications... Nastavení propojení - + Configure software for communicating with the Radio Nastavení softwaru pro komunikaci s rádiem - + Write Backup to Radio Zapsat zálohu do rádia - + Write Backup from file to Radio Zapsat zálohu ze souboru do rádia - + Backup Radio to File Zálohovat rádio do souboru - + Save a complete backup file of all settings and model data in the Radio Uložit kompletní zálohu modelů a nastavení rádia - + Contributors... Přispěvatelé - + A tribute to those who have contributed to OpenTX and Companion Hold těm, kteří přispěli k OpenTX a Companion - + SD card synchronization Syncronizace SD karty se složkou s daty - + + Use default system language. + + + + + Use %1 language (some translations may not be complete). + + + + Recent Files Nedávné soubory - + Recent Models+Settings Nedávné modely a nastavení - + Set Icon Theme Téma ikon - + Set Icon Size Velikost ikon - + Show the list of radio profiles Výběr profilů rádia - + Write Zápis - + New Radio Nové rádio - + List available programmers Seznam použitelných programátorů - + Show fuses dialog Zobrazit dialog nastavení pojistek mikrokontroléru - + Show the application's About box O aplikaci Companion - + Set Menu Language Nastavení jazyka - - + + File Soubor - - + + Edit Úpravy - + Settings Nastavení - + Read/Write Čtení/Zápis - - + + Help Nápověda - - + + Radio Profile Profil rádia - + Show recent Models+Settings documents Nedávné dokumenty modelů a nastavení rádia - + Ready Připraven - + %2 @@ -4610,134 +4631,260 @@ Doporučujeme prohlédnout poznámky k vydání, pomocí tlačítka níže se do MdiChild - + free bytes volné[B] - + Editing model %1: Editace modelu %1: - - - - - - - - - - - - - - - - - - + + + + + + Error Chyba - - + Unable to find file %1! Nemohu nalézt soubor %1! - - - - + Error opening file %1: %2. Chyba při otevírání souboru %1: %2. - - - Invalid EEPROM File %1 - Neplatný soubor EEPROM %1 - - - - + Error reading file %1: %2. Chyba při otevírání souboru %1: %2. - - Invalid binary EEPROM File %1 - Neplatný binární soubor EEPROM %1 - - - - - - + + + + Save As Uložit jako - - - - - Cannot write file %1: -%2. - Nelze zapsat soubor %1: -%2. - - - - - Error writing file %1: -%2. - Chyba při zápisuí souboru %1: -%2. - - - + Open backup Models and Settings file Otevřít zálohu modelů a nastavení rádia - + + Companion + + + Delete selected models? + + + + + Cannot delete default model. + Nelze odstranit výchozí model. + + + + &Edit + &Upravit + + + + &Restore from backup + &Obnovit ze zálohy + + + + &Model Wizard + &Průvodce nastavením modelu + + + + &Delete + + + + + Delete + + + + + &Copy + &Kopírovat + + + + Ctrl+C + + + + + &Cut + + + + + Ctrl+X + + + + + + &Paste + &Vložit + + + + + Ctrl+V + + + + + D&uplicate + &Duplikovat + + + + Ctrl+U + + + + + Move to Category + + + + + &Use as default + &Použít jako výchozí + + + + P&rint model + Vy&tisknout model + + + + Ctrl+P + + + + + &Simulate model + &Simulovat model + + + + Alt+S + + + + + &Add model + + + + + &Rename category + + + + + &Delete category + + + + + &Add category + + + + + Models and settings will be automatically converted. +If that is not what you intended, please close the file +and choose the correct radio type/profile before reopening it. + + + + + Do you want to overwrite radio general settings? + Chcete přepsat obecná nastavení rádia? + + + + You are pasting on an not empty model, are you sure? + Vkládáte do modelu který není prázdný, jste si jist? + + + + This category is not empty! + + + New model + + + + %1 has been modified. Do you want to save your changes? %1 byl změněn. Chcete ho uložit? - + + Unable to find Horus radio SD card! + + + + + Models and Settings written + + + + Cannot write temporary file! Nelze zapsat dočasný soubor! - - - - + Warning Varování - + Invalid binary backup File %1 Neplatný binární soubor zálohy %1 + + + Radio settings + + + + + Simulate Tx + Simulace Rádia + MixerDialog @@ -4946,139 +5093,159 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Pokud je nastaveno zpomalení, nastavená hodnota udává rychlost mixu -&gt; hodnota udává počet sekund které trvá změna hodnoty z -100 na 100.</p></body></html> - + DEST -> CH%1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + MixesPanel - - + + Move Up Posunout nahoru - - + + Ctrl+Up Ctrl+Nahoru - - + + Move Down Posunout dolů - - + + Ctrl+Down Ctrl+Dolů - + Clear Mixes Vymazat všechny mixy - + Not enough available mixers! Není k dispozici dostatek mixů! - + Delete Selected Mixes? Odstranit vybrané mixy? - + &Add &Přidat - + Ctrl+A - + &Edit &Upravit - + Enter - + &Toggle highlight Přepnout &zvýraznění - + Ctrl+T - + &Delete &Odstranit - + Delete - + &Copy &Kopírovat - + Ctrl+C - + Ctrl+X - + C&ut &Vyjmout - + &Paste &Vložit - + Ctrl+V - + Du&plicate &Duplikovat - + Ctrl+U - + Clear Mixes? Vymazat mixy? - + Really clear all the mixes? Opravdu vymazat všechny mixy? @@ -5096,52 +5263,52 @@ p, li { white-space: pre-wrap; } Simulace - + Setup Nastevní - + Heli - + Inputs Vstupy(DR/Expo) - + Logical Switches Logické spínače - + Mixes Mixer - + Flight Modes Letové režimy - + Outputs Výstupy - + Curves Křivky - + Special Functions Speciální funkce - + Telemetry Telemetrie @@ -5149,281 +5316,308 @@ p, li { white-space: pre-wrap; } ModelPrinter - + %1 bytes %1 bajtů - + CH%1 - + Exponential Exponenciální - + Extra Fine Extra jemný - + Fine Jemný - + Medium Střední - + Coarse Hrubý - + Unknown Neznámý - + Enabled Povoleno - + Disabled Zakázáno - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) %1, Kanály(%2-%3), PPM pauza(%4usec), Polarita pulzů(%5) - + %1, Channels(%2-%3) %1, Kanály(%2-%3) - + Receiver number(%1) Přijímač číslo(%1) - + + radio Protocol %1, subType %2, option value %3 + + + + Slave/Jack Žák/Jack konektor - + Master/SBUS Module Učitel/SBUS modul - + Master/CPPM Module Učitel/CPPM modul - + Master/SBUS in battery compartment Učitel/SBUS konektor v šachtě baterie - + Master/Jack Učitel/Jack konektor - + + 90 + CH9X {90?} + + + + 120 + CH9X {120?} + + + + 120X + CH9X {120X?} + + + + 140 + CH9X {140?} + + + Rudder Směrovka - + Elevator Výškovka - + Throttle Plyn - + Aileron Křidélka - + Name(%1) Název(%1) - + Persistent Trvalé - + MinuteBeep Oznamovat minuty - + CountDown(Beeps) Odečítat (Zvuk) - + CountDown(Voice) Odečítat (Hlas) - + CountDown(Haptic) Odečítat (Vibrace) - + + Off Vypnuto - - - - + + + + FM%1 LR%1 - + FM%1%2 LR%1%2 - + FM%1+%2 LR%1+%2 - + [I%1] - + Input%1 Vstup%1 - + Weight Váha - + Switch Spínač - - + + NoTrim Žádný trim - + Weight(%1) Váha(%1) - + Switch(%1) Spínač(%1) - + No DR/Expo Bez DR/Expo - + + Offset(%1) Ofset(%1) - + Delay(u%1:d%2) Zpoždění(u%1:d%2) - + Slow(u%1:d%2) Zpomalení(u%1:d%2) - + Warn(%1) Varování(%1) - + Disabled in all flight modes Zakázáno ve všech letových režimech - + Flight modes(%1) Letové režimy(%1) - + Flight mode(%1) Letový režim(%1) - + Edge(%1, [%2:%3]) - + instant - + Sticky(%1, %2) - + Timer(%1, %2) - + Duration(%1s) Trvání(%1s) - + Delay(%1s) Zpoždění(%1s) - + Custom Volná-XY - + Standard Rastr-X @@ -5431,27 +5625,27 @@ p, li { white-space: pre-wrap; } ModelSelectionPage - + Plane Letadlo - + Multirotor - + Helicopter Helikoptéra - + Model Name: Název modelu: - + Model Type: Typ modelu: @@ -5459,129 +5653,7 @@ p, li { white-space: pre-wrap; } ModelsListWidget - - - &Edit - &Upravit - - - - &Restore from backup - &Obnovit ze zálohy - - - - &Model Wizard - &Průvodce nastavením modelu - - - - &Delete - &Odstranit - - - - Delete - - - - - &Copy - &Kopírovat - - - - Ctrl+C - - - - - &Cut - &Vyjmout - - - - Ctrl+X - - - - - &Paste - &Vložit - - - - Ctrl+V - - - - - D&uplicate - &Duplikovat - - - - Ctrl+U - - - - - &Use as default - &Použít jako výchozí - - - - P&rint model - Vy&tisknout model - - - - Ctrl+P - - - - - &Simulate model - &Simulovat model - - - - Alt+S - - - - - General Settings - Obecná nastavení - - - - Delete Selected Models? - Odstranit vybrané modely? - - - - - Cannot delete default model. - Nelze odstranit výchozí model. - - - - Cannot cut default model. - Nelze přesunout výchozí model. - - - - Do you want to overwrite radio general settings? - Chcete přepsat obecná nastavení rádia? - - - - You are pasting on an not empty model, are you sure? - Vkládáte do modelu který není prázdný, jste si jist? - - - + No free slot available, cannot duplicate Není už volný slot, nelze duplikovat @@ -5589,142 +5661,199 @@ p, li { white-space: pre-wrap; } Module - + Failsafe Mode Režim Failsafe - + Start První kanál - + PPM delay PPM zpoždění - + Negative Negativní - + Positive Pozitivní - + Polarity Polarita - + Trainer Mode Mód trenér - + PPM Frame Length Délka PPM rámce - + CH - + + SubType + + + + + Antenna + + + + + Internal + + + + + Ext. + Int. + + + + + Option value + + + + + Bind on startup + + + + + Low Power + + + + us - + + Multi Radio Protocol + + + + Master/Jack Učitel/Jack konektor - + Slave/Jack Žák/Jack konektor - + Master/SBUS Module Učitel/SBUS modul - + Master/CPPM Module Učitel/CPPM modul - + Master/SBUS in battery compartment Učitel/SBUS konektor v šachtě baterie - + + Show values in: + + + + + % + abbreviation for percent + + + + + μs + abbreviation for microseconds + + + + ms - + Channels Počet kanálů - + Not set Nenastaveno - + Hold Držet hodnotu - + Custom Vlastní - + No Pulses Žádné pulzy - + Receiver Dle nastavení přijímače - + Failsafe Positions Pozice Failsafe - + Protocol Protokol - + Receiver No. Číslo přijímače - + Output type Typ řízení výstupu - + Open Drain - + Push Pull @@ -5732,43 +5861,43 @@ p, li { white-space: pre-wrap; } ModulePanel - + Trainer Port Port Trenér - + Internal Radio System Interní vysílací modul - + External Radio Module Externí vysílací modul - - + + Radio System Vysílací modul - + Extra Radio System Extra modul - + Value Hodnota - + Hold Držet hodnotu - + No Pulse Žádné pulzy @@ -5776,229 +5905,322 @@ p, li { white-space: pre-wrap; } MultiModelPrinter - + General Model Settings Obecná nastavení modelu - + Name: Název: - + EEprom Size: Velikost EEPROM: - + Timer%1: Stopky%1: - + Module%1: Modul%1: - + Module: Modul: - + Trainer port: Port Trenér: - + Throttle Trim: Trim plynu: - + Trim Increment: Krok trimu: - + Center Beep: Zvuk ve středové poloze: - + + Helicopter Setup + + + + + Swash Type: + + + + + Swash Ring: + + + + + Input + Vstup + + + + Weight + Váha + + + + Long. cyc + + + + + Lateral cyc + + + + + Collective + Kolektiv + + + Flight modes Letové režimy - - + + Flight mode Letový režim - + Switch Spínač - + Fade IN Přechod při aktivaci - + Fade OUT Přechod při deaktivaci - - + + FM%1 LR%1 - - + + GV%1 GP%1 - + RE%1 - + Limits Limity - + Channel Kanál - + Name Název - - + + Offset Subtrim - + Min - + Max - + Invert Invertovat - + Global Variables Globální proměnné - + Inputs Vstupy(DR/Expo) - + Mixers Mixy - + CV%1 K%1 - + Curves Křivky - + L%1 - + Logical Switches Logické spínače - + SF%1 - + Special Functions Speciální funkce - + Telemetry Settings Nastavení telemetrie - + Analogs Analogy - + Unit Jednotky - + Scale Rozsah - + A%1 - + RSSI Alarms RSSI Alarmy + + + Low Alarm + Nízký alarm + + + + Critical Alarm + Kriticky alarm + + + + Multiprotocols + + + Subtype + + + + + Video TX frequency + + + + + C2500 frequency fine tune + + + + + Telemetry + Telemetrie + + + + Radio output power + + + + + Servo output frequency + + + + + Option value + + + + + DEFAULT + + MultirotorPage - + Throttle Channel: Kanál plynu: - + Yaw Channel: Kanál bočení: - + Pitch Channel: Kanál klopení: - + Roll Channel: Kanál klonění: @@ -6006,17 +6228,17 @@ p, li { white-space: pre-wrap; } OptionsPage - + Throttle Cut Zámek plynu (spínač THR) - + Throttle Timer Stopky na plynu - + Flight Timer Letové stopky @@ -6039,17 +6261,17 @@ p, li { white-space: pre-wrap; } Tisk do souboru - + Print Document Vytisknout dokument - + Select PDF output file Vyberte cílový PDF soubor - + ODF files (*.odt);;PDF Files(*.pdf);;HTML-Files (*.htm *.html);;All Files (*) soubor ODF (*.odt);;soubor PDF (*.pdf);;soubor HTML (*.htm *.html);;Všechny (*) @@ -6083,681 +6305,731 @@ p, li { white-space: pre-wrap; } QObject - - + + Rud Směrovka - - + + Ele Výškovka - - + + Thr Plyn - - + + Ail Křidélka - - - + + P1 Potenciometr P1 - - - + + P2 Potenciometr P2 - - - + + P3 Potenciometr P3 - - - - + + + S1 - - - - + + + S2 - - - - + + + LS - - - - + + + RS - + TrmR Trim směrovky - + TrmE Trim výškovky - + TrmT Trim plynu - + TrmA Trim křidélek - - - + + + REa Otočný enkodér REa - - - + + + REb Otočný enkodér REb - - + + Batt - + A1 Telem. vstup A1 - + A2 Telem. vstup A2 - + Alt Výška - + Rpm Otáčky - + Fuel Palivo - + T1 - + SWR - - + + °F - + + mW + + + + + Rad + + + + + Trm5 + + + + + Trm6 + + + + T2 - + Speed Rychlost - + Dist Vzdálenost - + GPS Alt Výška GPS - + Cell Článek - + Vfas - + Curr Proud - + Cnsp - + Powr Výkon - + AccX - + AccY - + AccZ - + VSpd - + A1- - + A2- - + Alt- - + Alt+ - + Rpm+ - + T1+ - + T2+ - - + + Time - + MAX - - S11 - S11 (multipos1_poloha1) - - - - S12 - S12 (multipos1_poloha2) - - - - S13 - S13 (multipos1_poloha3) - - - - S14 - S14 (multipos1_poloha4) - - - - S15 - S15 (multipos1_poloha5) - - - - S16 - S16 (multipos1_poloha6) - - - - S21 - S21 (multipos2_poloha1) - - - - S22 - S22 (multipos2_poloha2) - - - - S23 - S23 (multipos2_poloha3) - - - - S24 - S24 (multipos2_poloha4) - - - - S25 - S25 (multipos2_poloha5) - - - - S26 - S26 (multipos2_poloha6) - - - + CYC%1 - - - - + + + + ---- - + THR Plyn - - - + + + ON ZAPNUTO - - - + + + OFF VYPNUTO - + Diff(%1) Dif(%1) - + Expo(%1) - + Function(%1) Funkce(%1) - + Curve(%1) Křivka(%1) - + !Curve(%1) !Křivka(%1) - - + + Support for frsky telemetry mod Podpora frsky telemetrie tj. zobrazení telemetrických dat na displeji rádia (je potřeba upravit HW, bez této úpravy nebudou fungovat dva přepínače! a pochopitelně nebudou zobrazena žádná telem. data.) - - + + Support for jeti telemetry mod Podpora telemetrie JETI - - + + Support for receiving ardupilot data telemetrie - podpora pro příjem ardupilot dat - - + + Support for receiving NMEA data telemetrie - podpora pro příjem NMEA dat - + Support for telemetry easy board Podpora pro desku TelemetrEZ - - + + Support for MAVLINK devices Podpora pro zařízení s MAVLINK - + Rotary Encoder use in menus navigation Použít Rotary Encoder pro navigaci v menu - + No OverrideCH functions available Funkce Zámek kanálu není dostupná - - - - - - + + + + + + Enable heli menu and cyclic mix support Funkce pro heli, nastavení typu mechaniky - - - - - - - - - + + + + + + Enable TEMPLATES menu Přidá menu s jednoduchými šablonami modelu - - - - + + + + No splash screen Bez úvodního loga Firmware nebude obsahovat žádné logo, ani podporu pro něj. Toto se hodí pokud je potřeba ušetřit místo v paměti FLASH pro jiné funkce - - - - - - - - - + + + + + + + + + No flight modes Firmware nebude obsahovat podporu Letových Režimů - + Support for Lua model scripts Podpora pro Lua skripty. -miniaplikace spustitelné z SD karty - + + + + + + + + + + + Use alternative SQT5 font Použít alternativní znakovou sadu písma (jiný font) - - (displaying only first 10 warnings) - (zobrazeno pouze prvních 10 varování) - - - + Possibility to enable FAI MODE (no telemetry) at field Možnost povolit FAI MODE v menu rádia. FAI je soutěžní mód (www.fai.org), zablokuje vario, zobrazení telemetrie a funkce hlasového hlášení. - + FAI MODE (no telemetry) always enabled FAI MODE vždy aktivní (nelze vypnout v menu rádia) FAI je soutěžní mód (www.fai.org), zablokuje vario, zobrazení telemetrie a funkce hlasového hlášení. - - - - - Support for a third timer - Přidá třetí stopky - - - + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) Místo emulace joisticku je USB připojeno v režimu přenosu souborů (jako v Bootloaderu) - + Instead of Joystick emulation, USB connection is Command Line Interface Místo emulace joisticku je USB připojeno v režimu CLI (textová konzole) - - Removes D8 and LR12 FrSky protocols that are not legal for use in the EU on radios sold after Jan 1st, 2015 - Odstraní volby pro Frsky protokoly D8 a LR12 která nejsou legální pro rádia zakoupená po 1.1.2015 - - - + + Support for PPM internal module hack Podpora pro upravený vnitřní modul v režimu PPM - + ST7565P LCD or compatible ST7565P LCD a kompatibilní - + ST7565R LCD or compatible ST7565R LCD a kompatibilní - + ERC12864FSF LCD - + ST7920 LCD - - 9X board - 9X základní deska - - - + EEprom write progress bar Progresbar zobrazující zápis do EEPROM (tj. ukládání nastavení) - - + + No Winged Shadow How High support Bez podpory - Winged Shadow How High - - + + Turnigy 9XR + + + + + No vario support Bez podpory varia - - + + No GPS support Bez podpory GPS - - + + No gauges in the custom telemetry screen Bez grafických ukazatelů hodnoty na obrazovkách telemetrie - + + 9X with stock board + + + + Allow compensating for offset errors in FrSky FAS current sensors Povolit možnost kompenzace chyby ofsetu u Frsky FAS proudového senzoru, pokud je to potřeba - - + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) Přidá podporu pro revers os kniplů. To je nutné zejména pro osazení FrSky kniplů do 9X. - + + 9X with stock board and m128 chip + + + + + 9X with AR9X board + + + + + 9X with Sky9x board + + + + + 9X with Gruvin9x board + + + + + DIY MEGA2560 radio + + + + Power management by soft-off circuitry Ovládání napájení pomocí soft-off obvodu - - ar9x board / 9X - ar9x deska / 9X - - - - 9XR-PRO - - - - - FrSky Taranis - - - - - FrSky Taranis Plus - - - - + FrSky Taranis X9E - + Confirmation before radio shutdown Přidá potvrzování před vypnutím rádia - - - Adds mixers output view to the CHANNELS MONITOR screen, pressing [ENT] switches between the views - Přidá monitor výstupu mixů k monitoru kanálů, stiskem [ENT] přepnete z jednoho do druhého - - - + Haptic module installed Podpora pro vibrační modul - + Disable HELI menu and cyclic mix support Odstranit funkce pro heli a nastavení typu mechaniky - + + Unknown error + + + + + ... plus %1 errors + + + + + Cannot write radio settings + + + + + Cannot write model %1 + + + + + 6P + CH9X {6P?} + + + + JSx + + + + + JSy + + + + + Support for the DIY-Multiprotocol-TX-Module + + + + + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 + + + + Disable Global variables Odstranit Globální proměnné - - + + Enable Lua compiler + + + + + KS108 LCD + + + + + WTV20 voice module + + + + + JQ6500 voice module + + + + + FrSky Taranis X9D+ + + + + + FrSky Taranis X9D + + + - - - - - - + Horus gimbals installed (Hall sensors) + + + + + FrSky Taranis X7 + + + + + FrSky Horus + + + + + Use ONLY with first DEV pcb version + + + + + Turnigy 9XR-PRO + + + + + Turnigy 9XR with m128 chip + + + + + + + + + Disable curves menus Bez uživatelsky definovatelných křivek - - - - + + + + + Support for radio modified with regular speaker Vylepšený zvukový výstup, funkční i s origo pípákem, @@ -6765,137 +7037,111 @@ ale doporučuje se provést instalaci reproduktoru - - - - - + + + + + Used if you have modified your radio with voice mode Hlasový výstup pro telemetrii, nutno zastavět hlasový modul - - - - - + + + + + Used if you have modified your radio with haptic mode Výstrahy pomocí vibračního motoru (je třeba osadit) - + Channel values displayed in us Hodnoty kanálů budou zobrazeny v us (mikrosekundy) místo procent - - - - - - - - - + + + + + + + + + In model setup menus automatically set source by moving the control Výběr spínače v mixu atd. se provádí jeho sepnutím - - - - - - - - - + + + + + + + + + In model setup menus automatically set switch by moving the control Výběr spínače v mixu atd. se provádí jeho sepnutím - - - - - - - - - + + + + + + + + + Battery graph Grafické znázornění stavu baterie - - - - + + + + Enable the throttle trace in Statistics Přidat Stopu Plynu (Throttle-trace) v panelu STATISTIKA - - M128 / 9X board - M128 / 9X základní deska - - - - 9XR - - - - - 9XR with M128 chip - 9XR s čipem M128 - - - - Gruvin9x board / 9X - Gruvin9x deska / 9X - - - - + + Support of FrSky PXX protocol Podpora pro Frsky PXX protokol - - - - - + + + + + Support for DSM2 modules Podpora DSM2 modulů - - - - - - - - - + + + + + + PPM center adjustment in limits Možnost nastavovat střed serva šířkou pulzu - - - - - - - - - + + + + + + Symetrical Limits Symetrické limity Přidá možnost volby mezi @@ -6906,33 +7152,33 @@ Přidá možnost volby mezi nastavené limity tedy nemusí být rovny hodnotě -100% a 100%, ale budou pouze maximem výchylky) - - - - - - - + + + + + + + Pots use in menus navigation Moznost zadávat hodnoty a pohybovat se v menu pomocí potenciometrů - - + + SmartieParts 2.2 Backlight support Podpora pro modul SmartieParts 2.2 (programátor/podsvícení) Není určeno pro starší verze Smartie Parts - - - - - - + + + + + + Enable resetting values by pressing up and down at the same time Rychlé nastavení hodnoty současným stiskem dvou tlačítek. (+) a (-) invertuje hodnotu @@ -6941,28 +7187,28 @@ Není určeno pro starší verze Smartie Parts (UP) a (DN) vastaví výchozí hodnotu - - - - - - - - - + + + + + + + + + No graphical check boxes and sliders Nahrazeni posuvníku a zatržítek (checkboxu) textem - - - - - - - - - + + + + + + + + + Don't use bold font for highlighting active items Vypnout zvýraznění aktivních mixů/spínačů tučným písmem. Pokud není tato volby vybrána, @@ -6971,53 +7217,43 @@ zobrazovány tučným pismem. Neaktivní mixy/spínače budou zobrazeny normálním písmem - - - - - + + + + + EEprom write Progress bar Progresbar zobrazující zápis do EEPROM (tj. ukládání nastavení) - - - - - - + + + + + + Imperial units Imerialní jednotky pro telemetrii (stopy, palce, míle atd.) - - MEGA2560 board - MEGA2560 deska - - - - Sky9x board / 9X - Sky9x deska / 9X - - - - - + + + Bluetooth interface - - - - - - - - - + + + + + + + + + Global variables Aktivuje Globální Proměnné Jsou to proměnné, které lze použít pro konfiguraci místo některých pevných číselných hodnot. @@ -7026,1355 +7262,1210 @@ Jejich hodnoty naleznete u originální 9x desky v seznamu křivek. U ostatních Nastavení hodnoty se provádí přímo v seznamu proměnných, nebo pomocí Funkce - - + + Support for SD memory card Podpora paměťové karty SD - + Support for DSM2 modules using ppm instead of true serial Podpora DSM2 modulů s použitím PPM místo sériového protokolu - - - + + + Enable HELI menu and cyclic mix support Funkce pro heli, nastavení typu mechaniky - - + Warning Varování - - EEPROM saved with these warnings: - EEPROM uložena s těmito varováními: - - - + English - + French - + Italian - + German - + Czech - + Slovak - + Spanish - + Portuguese - + Swedish - - Finnish - + + Dutch + - + + Hungarian + + + + No Žádný - + RotEnc A Otočný enkodér :A - + Rot Enc B Otočný enkodér :B - + Rot Enc C Otočný enkodér :C - + Rot Enc D Otočný enkodér :D - + Rot Enc E Otočný enkodér :E - + No repeat Neopakovat - - - - - - - + + + + + + + V - - + + s - + ft - - - + + + m - - - + + + °C - - - + + + ° - - + + % - - - + + + mph - - - + + + km/h - - + + m/s - - + + A - + mA - + kts - + f - - + + mAh - - + + W - + dB - + rpms - - + + g - + hours - + minutes - + seconds - + h:m - + m:s - + h:m:s - - + F1 - - + F2 - - + F3 - - + F4 - - + S3 - - - + + + Timer3 Stopky3 - + RSSI Tx - + RSSI Rx - + A3 Telem. vstup A3 - + A4 Telem. vstup A4 - + Cells - + dTE - + Hdg - + AirSpeed - + A3- Telem. vstup A3- - + A4- Telem. vstup A4- - + Speed+ - + Dist+ - + AirSpeed+ - + Cell- - + Cells- - + Vfas- - + Curr+ - + Powr+ - + ACC - + GPS Time - - + L1 - - + L2 - - - L3 - - - - - - L4 - - - - - - L5 - - - - - - L6 - - - - - - L7 - - - - - - L8 - - - - - - L9 - - - - - - L10 - - - - - - L11 - - - - - - L12 - - - - - - L13 - - - - - - L14 - - - - - - L15 - - - - - - L16 - - - - - - L17 - - - - - - L18 - - - - - - L19 - - - - - - L20 - - - - - - L21 - - - - - - L22 - - - - - - L23 - - - - - - L24 - - - - - - L25 - - - - - - L26 - - - - - - L27 - - - - - - L28 - - - - - - L29 - - - - - - L30 - - - - - - L31 - - - - - - L32 - - - - + [I%1] - + LUA%1%2 - + + + L%1 + + + + TR%1 - + FM0 LR0 - + FM1 LR1 - + FM2 LR2 - + FM3 LR3 - + FM4 LR4 - + FM5 LR5 - + FM6 LR6 - + FM7 LR7 - + FM8 LR8 - - S31 - S31 (multipos3_poloha1) - - - - S32 - S32 (multipos3_poloha2) - - - - S33 - S33 (multipos3_poloha3) - - - - S34 - S34 (multipos3_poloha4) - - - - S35 - S35 (multipos3_poloha5) - - - - S36 - S36 (multipos3_poloha6) - - - + RudTrim Left TrimSmě.r-Vlevo - + RudTrim Right TrimSměr.-Vpravo - + EleTrim Down TrimVýšk.-Dolů - + EleTrim Up TrimVýšk.-Nahoru - + ThrTrim Down TrimPlyn-Dolů - + ThrTrim Up TrimPlyn-Nahoru - + AilTrim Left Trimkřid.-Vlevo - + AilTrim Right TrimKřid-Vpravo - + + Trim 5 Down + + + + + Trim 5 Up + + + + + Trim 6 Down + + + + + Trim 6 Up + + + + THs Pln> - + TH% Pln% - + THt Pln* - + One One(výběr modelu) - + ??? - + a>x - + a<x - + |a|>x - + |a|<x - + AND - + OR - + XOR - + a=b - + a!=b - + a>b - + a<b - + a>=b - + a<=b - + d>=x - + |d|>=x - + a=x - + a~x - + Timer - + Sticky - + + Left Horizontal + Levá horizontální + + + + Left Vertical + Levá vertikální + + + + Right Vertical + Pravá vertikální + + + + Right Horizontal + Pravá horizontální + + + + Aux. 1 + + + + + Aux. 2 + + + + + Unknown Neznámý - + Override %1 Zámek %1 - + Trainer Trenér - + Trainer RUD Trenér - směrovka - + Trainer ELE Trenér - výškovka - + Trainer THR Trenér - plyn - + Trainer AIL Trenér - křidélka - + Instant Trim - + Play Sound Přehrát zvuk - + Haptic Vibrovat - + Reset - + Set Timer %1 Nastav Timer %1 - + Vario - + Play Both Přehrát pár - + Play Value Přehrát hodnotu - + Play Script Spustit skript - + Volume Hlasitost - + Backlight Podsvětlení - + Screenshot Snímek LCD - + Adjust GV%1 Upravit GP%1 - + SetFailsafe Int. Module Nastavit Failsafe vnitř. modulu - + SetFailsafe Ext. Module Nastavit Failsafe ext. modulu - + RangeCheck Int. Module Test dosahu vnitř. modulu - + RangeCheck Ext. Module Test dosahu ext. modulu - + Bind Int. Module Bind vnitř. modulu - + Bind Ext. Module Bind ext. modulu - - - + + + <font color=red><b>Inconsistent parameter</b></font> <font color=red><b>parametr není konzistentní</b></font> - + played once, not during startup přehrát jednou, ale ne po startu - + repeat(%1s) opakovat(%1s) - + DISABLED ZAKÁZÁN - + INV - + NOR --- - + Rotary Encoder Rotační enkodér - + + -GV%1 (%2) + + + + + GV%1 (%2) + + + + !Flight mode %1 !Letový režim %1 - + Flight mode %1 Letový režim %1 - + Yellow Žlutá - + Orange Oranžová - + Red Červená - + Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (nepodporován) - + FrSky Sensor Hub FrSky Senzor Hub - + None Žádný - + Imperial Imperiální - + Metric Metrické - + + + Uknown error during Simulator startup. + + + + + Simulator Error + + + + + Data Load Error + + + + + Error occurred while starting simulator. + + + + Play Track Hrát stopu - - - + + + --- - + Rud Trim Trim směrovky - + Ele Trim Trim výškovky - + Thr Trim Trim plynu - + Ail Trim Trim křidélek - + Rot Enc - + Polish - + CH%1 - + Background Music Hudba na pozadí - + Background Music Pause Hudba na pozadí -pozastavit - - - + + + Timer1 Stopky1 - - - + + + Timer2 Stopky2 - + Edge - + SD Logs SD logy - + Telemetry Telemetrie - + Value Hodnota - + Decr: Zmenšit: - + Incr: Zvětšit: - + Played once, not during startup Hrát jednou, ne při výběru modelu - + %1s - + Value Hodnota - + Source Zdroj - + GVAR Proměnná - + Increment Upravit - + Flight Let - + Own value Vlastní hodnota - + Flight mode %1 value Flight phase %1 value Hodnota režimu LR%1 - + Keys Klávesy - + Sticks Páky - + Keys + Sticks Klávesy i páky - - + + -GV%1 -GP%1 - - - + + + GV%1 GP%1 - + Simulator for this firmware is not yet available Simulátor pro tuto verzi firmware zatím není dostupný - - - Simultaneous usage of expo and curves is no longer supported - Současné použití expa a křivek již není podporováno - - - + Switch Spínač - + Switch Spínač - + cannot be exported on this board! -na této desce nelze exportovat! - + Source %1 cannot be exported on this board! Zdroj %1 nelze na této desce exportovat! - + OpenTX only accepts %1 points in all curves V OpenTX je možné zadat pouze %1 bodů dohromady ve všech křivkách - + OpenTx only accepts %1 points in all curves V OpenTX je možné zadat pouze %1 bodů dohromady ve všech křivkách - - - - - + + + + + + OpenTX on this board doesn't accept this function OpenTX nepodporuje tuto funkci na této zákl. desce - + OpenTX doesn't accept this telemetry protocol OpenTX nepodporuje tento protokol - - - + + + OpenTX doesn't accept this radio protocol OpenTX nepodporuje tento protokol - + OpenTX doesn't allow this number of channels V OpenTX nelze použít tento počet kanálů - - th9x on this board doesn't have Rotary Encoders - v th9x na této desce nelze použít rotační enkodéry - - - + Trim disabled Trim zakázán - + Own Trim Vlastní trim - + Use Trim from Flight mode %1 Použít trim z letového režimu %1 - + Use Trim from Flight mode %1 + Own Trim as an offset Použít hodnotu trimu z letového režimu %1 + vlastní trim jako ofset - + FW: %1 - + Pict: %1 Obr: %1 - + Profile image Obrázek profilu - - Simultaneous usage of expo and curves is no longer supported in OpenTX - Současné použití expa a křivky již není podporováno - - - + Thank you for upgrading to OpenTX 2.0. This is a major upgrade that adds and modifies a lot of things, so please make sure that you read release notes carefully to learn about the changes, and thoroughly check each of your models for proper function. The OpenTX Team. @@ -8383,99 +8474,496 @@ The OpenTX Team. Tým OpenTX. - + GV GP - - - - - + + + + + Synchronization error Chyba synchronizace - + No SD directory configured! Složka SD karty nebyla nastavena! - + No Radio connected! Není připojeno rádio! - + -%1 - - + + The directory '%1' doesn't exist! Složka '%1' neexistuje! - + Create '%1' failed Vytvoření '%1' selhalo - + Copy '%1' to '%2' failed Kopírování '%1' do '%2' selhalo - + Open '%1' failed Otevření '%1' selhalo - + Write '%1' failed Zápis '%1' selhal - - - + + + + + + + Error Chyba - + Cannot write file %1: %2. Nelze zapsat soubor %1: %2. - + Companion - + <b><u>WARNING!</u></b><br>This will reset the fuses of %1 to the factory settings.<br>Writing fuses can mess up your radio.<br>Do this only if you are sure they are wrong!<br>Are you sure you want to continue? <b><u>POZOR!</u></b><br>Toto nastaví pojistky %1 do továrního nastavení.<br>Zápis pojistek může poškodit vaše rádio.<br>Proveďte pouze pokud jste si jist že jsou nastaveny špatně!<br>Jste si opravdu jist, že chcete pokračovat? - - + + Could not delete temporary file: %1 Nelze odstarnit dočasný soubor: %1 - - Radio type - Typ rádia + + Unable to find Horus radio SD card! + - - Which radio type do you want to simulate? - Jaký typ rádia chcete simulovat? + + Conversion error on field %1 + + + + + Negative span + Negativní + + + + Mid value + Střed + + + + Positive span + Pozitivní + + + + + Models + Translators do NOT use accent for this, this is the default category name on Horus. + + + + + Positive + Pozitivní + + + + Negative + Negativní + + + + Select a data file + + + + + Select Data Directory + + + + + Select SD Card Image Folder + + + + + Available profiles: + + + + + ID: + + + + + Name: + + + + + Available radios: + + + + + WARNING: couldn't initialize SDL: +%1 + + + + + ERROR: No simulator libraries available. + + + + + Radio profile ID or Name to use for simulator. + + + + + Radio type to simulate (usually defined in profile). + + + + + show this help text + + + + + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] + + + + + Options: + + + + + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. + Profile ID: [%1]; Radio ID: [%2]; +Data File: [%3] + + + + + ERROR: Radio profile or simulator firmware not found. +Profile ID: [%1]; Radio ID: [%2] + + + + + Error reading %1: %2 + + + + + Cannot save EEPROM + + + + + + Cannot open file %1: +%2. + + + + + + + Error writing file %1: +%2. + + + + + Invalid binary EEPROM file %1 + + + + + Can't extract RADIO/radio.bin + + + + + Can't extract RADIO/models.txt + + + + + Can't extract %1 + + + + + Unable to open %1: %2 + + + + + Invalid EEPROM file %1 + + + + + Invalid EEPROM File %1 + Neplatný soubor EEPROM %1 + + + + + Error opening file %1: +%2. + Chyba při otevírání souboru %1: +%2. + + + + Error opening OTX archive %1 + + + + + Error initializing OTX archive writer + + + + + Error creating OTX file %1: +%2. + + + + + Error creating OTX archive + + + + + Error adding %1 to OTX archive + + + + + Error opening file %1 in write mode: +%2. + + + + + Unable to find file %1! + Nemohu nalézt soubor %1! + + + + QxtCommandOptions + + + sets the application GUI style + + + + + sets the application stylesheet + + + + + restores the application from an earlier session + + + + + displays debugging information about widgets + + + + + use right-to-left layout + + + + + never grab the mouse or keyboard + + + + + grab the mouse/keyboard even in a debugger + + + + + run in synchronous mode for debugging + + + + + use Direct3D by default + + + + + sets the X11 display + + + + + sets the geometry of the first window + + + + + sets the default font + + + + + sets the default background color + + + + + sets the default foreground color + + + + + sets the default button color + + + + + sets the application name + + + + + sets the application title + + + + + sets the X11 visual type + + + + + limit the number of colors on an 8-bit display + + + + + use a private color map + + + + + sets the input method server + + + + + disable the X Input Method + + + + + sets the style used by the input method + + + + + + option "%1" not found + + + + + Short options cannot have optional parameters + + + + + positional() called before parse() + + + + + unrecognized() called before parse() + + + + + count() called before parse() + + + + + value() called before parse() + + + + + parameters() called before parse() + + + + + unrecognized parameters: + + + + + %1 requires a parameter + + + + + RadioKnobWidget + + + Right-double-click to reset to center. + @@ -8496,10 +8984,100 @@ Tým OpenTX. + + RadioOutputsWidget + + + Form + + + + + View: + + + + + Logical Switches + Logické spínače + + + + Global Variables + Globální proměnné + + + + Channel Outputs + + + + + L +o +g +i +c + + + + + G +l +o +b +a +l + + + + + C +h +a +n +n +e +l +s + + + + + RadioSwitchWidget + + + Latch/unlatch the momentary switch. + + + + + RawSwitch + + + ↑ + + + + + ↓ + + + + + - + + + + + ! + + + ReleaseNotesDialog - + Companion Release Notes Poznámky k vydání Companion @@ -8507,7 +9085,7 @@ Tým OpenTX. ReleaseNotesFirmwareDialog - + OpenTX Release Notes Poznámky k vydání OpenTX @@ -8515,17 +9093,17 @@ Tým OpenTX. RudderPage - + No Ne - + Yes Ano - + <br>Rudder Channel: <br>Kanál směrovky: @@ -8703,7 +9281,7 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. SetupPanel - + Timer %1 @@ -8711,179 +9289,847 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. SimpleTailPage - + Elevator Channel: Kanál výškovky: - SimulatorDialog + SimulatedUIWidget - - + + Rotary encoder click + + + + + Take Screenshot + + + + + screenshot + Simulator LCD screenshot file name prefix + + + + + SimulatedUIWidget9X + + + UP/PG-UP + + + + + [ UP ] + + + + + DN/PG-DN + + + + + [ DN ] + + + + + RIGHT/+ + + + + + [ + ] + + + + + LEFT/- + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + [ UP ]/[ DN ] or Rotary Sel. + + + + + SimulatedUIWidgetX12 + + + PG-UP + + + + + [ PgUp ] + + + + + PG-DN + + + + + [ PgDn ] + + + + + UP + + + + + [ MDL ] + + + + + DN/DEL/BKSP + + + + + [ RTN ] + + + + + LEFT + + + + + [ SYS ] + + + + + RIGHT + + + + + [ TELE ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/X + + + + + Rotary UP + + + + + +/C + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX7 + + + Taranis X7 Simulator + + + + + PG-UP + + + + + [ PAGE ] + + + + + PG-DN + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX9 + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + +/UP + + + + + [ + ] + + + + + -/DN + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ ENT ] + + + + + WHEEL/PAD SCRL + + + + + [ + ]/[ - ] + + + + + SimulatedUIWidgetX9E + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatorMainWindow + + + OpenTx Simulator + + + + + View + + + + + Radio Window + + + + + Reload... + + + + + Tools + + + + + Toolbar + + + + + Reload Lua Scripts + + + + + Reload the Lua environment on the simulated radio. + + + + + F7 + + + + + Reload Radio Data + + + + + Reload all radio data without restarting the simulator. + + + + + F9 + + + + + Key Mapping + + + + + Show keyboard maping reference. + + + + + F1 + + + + + Joystick Settings + + + + + Open joystick configuration settings dialog. + + + + + F3 + + + + + LCD Screenshot + + + + + Save a screenshot of the current simulated LCD screen. + + + + + F8 + + + + + Dock In Main Window + + + + + Show the radio in the main window or as a separate "floating" window. + + + + + Menu Bar + + + + + Show or hide the top menu bar. + + + + + Alt+M + + + + + Constrain Width + + + + + Set radio widget width to be a fixed size. + + + + + Constrain Height + + + + + Set radio widget height to be a fixed size. + + + + + ERROR: Failed to create simulator interface, possibly missing or bad library. + + + + + Alt+T + + + + + Radio Outputs + + + + + F2 + + + + + Telemetry Simulator + + + + + F4 + + + + + Trainer Simulator + + + + + F5 + + + + + Debug Output + + + + + F6 + + + + + Simulator Controls: + + + + + <tr><th>Key/Mouse</td><th>Action</td></tr> + + + + + Simulator Help + + + + + SimulatorStartupDialog + + + OpenTX Simulator - Startup Options + + + + + Simulator Startup Options: + + + + + Radio Profile: + + + + + Existing radio profiles are shown here.<br /> +Create or edit profiles using the Companion application. + + + + + Radio Type: + + + + + Existing radio simulators are shown here.<br /> +The radio type specified in the selected profile is used by default. + + + + + Data Source: + + + + + Data File: + + + + + Data Folder: + + + + + SD Image Path: + + + + + Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> +<b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! + + + + + Select data file... + + + + + + + ... + + + + + Directory containing RADIO and MODELS folders to use.<br /> +New folder(s) with default radio/model will be created here if necessary. + + + + + Select data folder... + + + + + Directory containing the SD card image to use.<br/> +The default is configured in the chosen Radio Profile. + + + + + Select SD card image folder... + + + + + Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. + + + + + File + Soubor + + + + Folder + + + + + SD Path + + + + + All files (*.*) + + + + + SimulatorWidget + + + Companion Simulator + Companion Simulátor + + + + Radio Simulator (%1) + + + + + Could not determine startup data source. + + + + + Could not load data, possibly wrong format. + + + + + Data Load Error + + + + + Invalid startup data provided. Plese specify a proper file/path. + + + + + Simulator Startup Error + + + + + Error saving data: could open file for writing: '%1' + + + + + Error saving data: could not get data from simulator interface. + + + + + An unexpected error occurred while attempting to save radio data to file '%1'. + + + + + Data Save Error + + + + Warning - Varování + - - Joystick enabled but not configured correctly - Joystick je povolen, ale není nakonfigurován - - - + Cannot open joystick, joystick disabled - Nelze otevřít joystick, není povolený + Nelze otevřít joystick, není povolený - - Simulating Radio (%1) - Simulace rádia (%1) - - - - - Outputs - Výstupy - - - + Firmware %1 error: %2 - Firmware %1 chyba: %2 + Firmware %1 chyba: %2 - SimulatorDialog9X + SliderWidget - - Companion Simulator - Companion Simulátor - - - - - - - Right Double Click to Reset - Dvojité kliknutí pravým tlačítkem myši nastaví na střed - - - - - Hold X - Držet X - - - - - Fix X - Fixovat X - - - - - Fix Y - Fixovat Y - - - - - Hold Y - Držet Y - - - - BEEP - Zvuk - - - - Outputs2 - Výstupy 2 - - - - Gvars - GP - - - - 9x Simulator - 9x Simulátor - - - - Outputs - Výstupy - - - - SimulatorDialogTaranis - - - Companion Simulator - Companion Simulátor - - - - Outputs2 - Výstupy 2 - - - - Gvars - Globální proměnné - - - - S3 - S3 - - - - S4 - S4 - - - - - Hold Y - Držet Y - - - - - Fix Y - Fixovat Y - - - - - Fix X - Fixovat X - - - - - Hold X - Držet X - - - - - - - Right Double Click to Reset - Dvojité kliknutí pravým tlačítkem myši nastaví na střed - - - - Taranis Simulator - Taranis Simulátor - - - - Outputs - Výstupy + + Right-double-click to reset to center. + @@ -8895,27 +10141,27 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. - + Splash Library - page %1 of %2 Knihovna s logy - strana %1 z %2 - + Warning Varování - + Invalid image in library %1 Neplatné logo v knihovně %1 - + Information - + No valid image found in library, check your settings Nebylo nalezenožádné použitelné logo v knihovně, zkontrolujte nastavení @@ -8923,7 +10169,7 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. StandardPage - + Channel %1 Kanál %1 @@ -8931,43 +10177,41 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. SyncProcess - + %1/%2 files - + Create directory %1 - - Copy %1 to %2 - + + Copy %1 to %2 - - Write %1 - + + Write %1 TailPage - + Rudder Channel: Kanál směrovky: - + Elevator Channel: Kanál výškovky: - + Only one channel still available!<br>You probably should configure your model without using the wizard. Pouze jeden kanál je k dispozici ! <br> Pravděpodobně budete muset nastavit model bez použití průvodce. @@ -8975,22 +10219,22 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. TailSelectionPage - + Elevator and Rudder Výškovka a směrovka - + Only Elevator Jen výškovka - + V-tail Ocas - V - + Tail Type: Typ ocasu: @@ -9270,7 +10514,7 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. Meters (m or ft) Vzdálenost (m nebo ft) - + Temp (°) Teplota (°) @@ -9286,7 +10530,7 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. MiliAmpéry (mA) - + Range Rozsah @@ -9299,22 +10543,22 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. Typ panelu - + None Žádný - + Numbers Hodnoty - + Bars Ukazatele - + Script Skript @@ -9342,99 +10586,99 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. TelemetryPanel - + Telemetry screen %1 Stránka telemetrie %1 - + Low Alarm Nízký alarm - + Critical Alarm Kriticky alarm - + Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (nepodporován) - - - + + + A1 Telem. vstup A1 - + Alti - + FrSky S.PORT - + FrSky D - + FrSky D (cable) FrSky D (kabel) - + Alti+ - + VSpeed - - - + + + A2 Telem. vstup A2 - - + + A3 Telem. vstup A3 - - + + A4 Telem. vstup A4 - - + + FAS - + Cells - + --- @@ -9593,12 +10837,12 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. ft - + °C - + °F @@ -9620,26 +10864,36 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. + mW + + + + dBm - - g - - - - ° + g - mL + ° + Rad + + + + + mL + + + + US fl.Oz. @@ -9649,57 +10903,57 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. Jednotky (-) - + RPM Otáčky (ot/min) - + Precision Přesnost - + Ratio - + Blades Listy vrtule - + Offset Ofset - + Multiplier Násobitel - + Auto Offset Auto ofset - + Filter Filtr - + Persistent Trvalé - + Positive Pozitivní - + Logs Logovat @@ -9707,22 +10961,22 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. TelemetrySensorPanel - + Lowest Nejnižší - + Cell %1 Článek %1 - + Highest Nejvyšší - + Delta @@ -9730,240 +10984,560 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. TelemetrySimulator - + Telemetry Simulator - - Vario Altitude - - - - - V-ALT - - - - - Vario Vertical Speed - - - - - V-VSPD - - - - - ACCZ - - - - - GPS Time - - - - - GPS-T - - - - - ACCX - - - - - GPS Lat/Lon - - - - - GPS-LL - - - - + VFAS - - FAS-V - - - - - GPS Speed - - - - - GPS-S - - - - - CELLS - - - - - ACCY - - - - - GPS Course - - - - - GPS-C - - - - - GPS Altitude - - - - - GPS-A - - - - - CURRENT - - - - - FAS-C - - - - - 30 - - - - + RSSI - - 75 - - - - + SWR - - FR_ID_AIR_SPEED - - - - - ASPD - - - - + A1 Telem. vstup A1 - + A2 Telem. vstup A2 - - A3 - Telem. vstup A3 + + Simulate + Simulace - - A4 - Telem. vstup A4 - - - - Temperature 1 + + Replay SD Log File - - T1 + + Replay rate + + + + + Load + + + + + |> + + + + + <| + + + + + > + + + + + <- - Temperature 2 + X - - T2 + + Row # +Timestamp - + + 1/5x + CH9X {1/5x?} + + + + 5x + CH9X {5x?} + + + + No Log File Currently Loaded + + + + + + + V / ratio + + + + + Db + + + + + RxBt + + + + + + + + + + + + + + + + + <html><head/><body><p><br/></p></body></html> + + + + + Tmp1 + + + + + A3 + Telem. vstup A3 + + + + A4 + Telem. vstup A4 + + + + Tmp2 + + + + + Fuel + Palivo + + + + °C + + + + + ml + + + + + Deg. C + + + + + % + + + + + + Meters + + + + + Alt + Výška + + + + VSpd + + + + + m/s + + + + + Fuel Qty + + + + + + km/h + + + + + Hdg + + + + + ASpd + + + + + + + G + + + + + GPS + + + + + Lat,Lon +(dec.deg.) + + + + + AccX + + + + + dd-MM-yyyy +hh:mm:ss + + + + + Date + + + + + Amps + + + + + AccZ + + + + + GAlt + + + + + + Volts + + + + + Cels + + + + + Curr + Proud + + + + AccY + + + + + GSpd + + + + + Degrees + + + + + RPM Otáčky (ot/min) - - FUEL - - - - + When enabled, sends any non-blank values as simulated telemetry data. - - simulate + + Log File - - Instance + + LOG Files (*.csv) - - 2 - CH9X {2?} + + ERROR - invalid file + + + + + Templates + + + Simple 4-CH + - - <html><head/><body><p>Start with <span style=" font-style:italic;">0x</span> for hex, <span style=" font-style:italic;">0</span> for octal, otherwise decimal.<br/>Numeric entry only. Blank values are not sent.</p></body></html> + + T-Cut + + + + + Sticky T-Cut + + + + + V-Tail + Ocas typu V + + + + Elevon\Delta + + + + + Heli Setup + + + + + Heli Setup with gyro gain control + + + + + Gyro gain control + + + + + Heli Setup (Futaba's channel assignment style) + + + + + Heli Setup with gyro gain control (Futaba's channel assignment style) + + + + + Gyro gain control (Futaba's channel assignment style) + + + + + Servo Test + + + + + MultiCopter + + + + + Use Model Config Wizard + + + + + Apply Template? + + + + + Apply template "%1"? + + + + + + + + + + + RUD + + + + + + + + + + + + + + ELE + + + + + + + THR + Plyn + + + + + + + + + + + AIL + + + + + + + + AIL2 + + + + + + + + ELE2 + + + + + + + + + + FLAPS + + + + + + + + + + FLAP%1 + + + + + + + + PITCH + + + + + + + + + + + + GYRO + + + + + + SPOIL + + + + + + SPOIL%1 + + + + + + RUD2 + + + + + + Clear Mixes? + Vymazat mixy? + + + + Really clear existing mixes on CH6? + + + + + Really clear existing mixes on CH5? ThrottlePage - + Yes Ano - + No Ne - + <br>Throttle Channel: <br>Kanál plynu: @@ -9984,37 +11558,37 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. TimerPanel - + Silent Tichý - + Beeps Zvuk - + Voice Hlas - + Haptic Vibrovat - + Not persistent Neukládat - + Persistent (flight) Trvalý (v rámci letu) - + Persistent (manual reset) Trvalý (reset ručně) @@ -10145,33 +11719,94 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. TrainerSimulator - + Trainer simulator + + TreeModel + + + Index + + + + + Name + Název + + + + Size + + + VTailPage - + First Tail Channel: První kanál: - + Second Tail Channel: Druhý kanál: + + VirtualJoystickWidget + + + Hld Y + + + + + Hold Vertical stick position. + + + + + Fix Y + Fixovat Y + + + + Prevent Vertical movement of stick. + + + + + Fix X + Fixovat X + + + + Prevent Horizontal movement of stick. + + + + + Hld X + + + + + Hold Horizontal stick position. + + + WingtypeSelectionPage - + Standard Wing Běžné křídlo - + Flying Wing / Deltawing Samokřídlo / Delta @@ -10179,273 +11814,273 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. WizardDialog - + Model Wizard Průvodce nastavením modelu - + Model Type Typ modelu - + Enter model name and model type. Zvolte název a typ modelu. - + Throttle Plyn - + Has your model got a motor or an engine? Má váš model motorový pohon? - + Wing Type Typ křídla - + Is your model a flying wing/deltawing or has it a standard wing configuration? Je váš model samokřídlo/delta, nebo má běžnou konfiguraci křídla? - + Ailerons Křidélka - + Has your model got ailerons? Má váš model křidélka? - + Flaps Klapky - + Has your model got flaps? Má váš model vztlakové klapky? - + Airbrakes Brzdy - + Has your model got airbrakes? Má váš model brzdící klapky? - + Flying-wing / Delta-wing Samokřídlo / Delta křídlo - + Select the elevons channels Zvolte kanál elevonů - + Rudder Směrovka - + Does your model have a rudder? Má váš model ovládanou směrovku? - + Tail Type Typ ocasu - + Select which type of tail your model is equiped with. Vyberte jaký typ ocasu má váš model. - - + + Tail Ocas - - + + Select channels for tail control. Zvolte kanály pro ovládání ocasních ploch. - + V-Tail Ocas typu V - + Select elevator channel. Zvolte kanál výškovky. - + Cyclic Cyklika - + Which type of swash control is installed in your helicopter? Jaký typ desky cykliky je instalován? - + Tail Gyro Gyro ocasu - + Has your helicopter got an adjustable gyro for the tail? Má vaše heli gyro ocasu s nastavitelným ziskem? - + Rotor Type Typ rotoru - + Has your helicopter got a flybar? Má vaše heli flybar(pádla na hlavě)? - - + + Helicopter Helikoptéra - - + + Select the controls for your helicopter - + Multirotor - + Select the control channels for your multirotor Zvolte ovládací kanály vaší multikoptéry - + Model Options Užitečné funkce - + Select additional options Vyberte další položky - + Save Changes Uložit změny - + Manually check the direction of each control surface and reverse any channels that make controls move in the wrong direction. Remove the propeller/propellers before you try to control your model for the first time.<br>Please note that continuing removes all old model settings! Ručně zkontrolujte směr každé řídicí plochy a nastavte revers těch co se pohybují v opačném směru. Raději odstraňte vrtuli / vrtule, než se poprvé pokusíte ovládat svůj model.<br>Vezměte prosím na vědomí, že pokud budete pokračovat, dojde k odstranění všech starých nastavení tohoto modelu! - + Enter a name for your model and select model type. Zvolte název a typ modelu. - + Select the receiver channel that is connected to your ESC or throttle servo.<br><br>Throttle - Spektrum: CH1, Futaba: CH3 Zvolte kanál přijímače, který je připojen k ESC, nebo servu plynu.<br><br>Spektrum: CH1, Futaba: CH3 - + Most aircraft have a main wing and a tail with control surfaces. Flying wings and delta winged aircraft only have a single wing. The main control surface on a standard wing controls the roll of the aircraft. This surface is called an aileron.<br>The control surface of a delta wing controls both roll and pitch. This surface is called an elevon. Většina letadel má hlavní křídlo a ocas s ovládacími plochami. Samokřídla a delty mají jen jedno křídlo. Hlavní řídicí plochy na standardním křídle ovládájí klonění letadla. Tyto plochy se nazývají křidélka. <br> Ovládací plochy delta křídla řídí podélný i příčný náklon. Tyto plochy se nazývají elevony. - + Models use one or two channels to control the ailerons.<br>A so called Y-cable can be used to connect a single receiver channel to two separate aileron servos. If your servos are connected by a Y-cable you should select the single-servo option.<br><br>Aileron - Spektrum: CH2, Futaba: CH1 Modely používají jeden, nebo dva kanály pro ovládání křidélek.<br>Tzv. Y-kabel lze použít pro připojení dvou samostatných serv křidélek do jednoho kanálu přijímače. Pokud jsou vaše serva spojeny Y-kabelem, měli byste zvolit možnost "jeden kanál"<br><br>Spektrum: CH2, Futaba: CH1 - + This wizard assumes that your flaps are controlled by a switch. If your flaps are controlled by a potentiometer you can change that manually later. Tento průvodce předpokládá, že vaše klapky jsou ovládány spínačem. Pokud jsou vaše klapky řízeny potenciometrem můžete toto změnit později ručně. - + Air brakes are used to reduce the speed of advanced sail planes.<br>They are very uncommon on other types of planes. Vzduchové brzdy se používají ke snížení rychlosti moderních kluzáků.<br>Na jiných typech letadel nejsou příliš obvyklé. - + Models use two channels to control the elevons.<br>Select these two channels Modely používají dva kanály pro ovládání elevonů.<br>Vyberte je - + Select the receiver channel that is connected to your rudder.<br><br>Rudder - Spektrum: CH4, Futaba: CH4 Zvolte kanál přijímače, který je připojen k vaší směrovce.<br>Spektrum:. CH4, Futaba: CH4 - + Select the tail type of your plane. Zvolte typ ocasu vašeho modelu. - + Select the Rudder and Elevator channels.<br><br>Rudder - Spektrum: CH4, Futaba: CH4<br>Elevator - Spektrum: CH3, Futaba: CH2 Zvolte kanály směrovky a výškovky.<br><br>Směrovka - Spektrum: CH4, Futaba: CH4<br>Výškovka - Spektrum: CH3, Futaba: CH2 - + Select the Elevator channel.<br><br>Elevator - Spektrum: CH3, Futaba: CH2 Zvolte kanál výškovky.<br><br>Spektrum: CH3, Futaba: CH2 - - - - - - - + + + + + + + TBD. - + Select the control channels for your multirotor.<br><br>Throttle - Spektrum: CH1, Futaba: CH3<br>Yaw - Spektrum: CH4, Futaba: CH4<br>Pitch - Spektrum: CH3, Futaba: CH2<br>Roll - Spektrum: CH2, Futaba: CH1 Zvolte ovládací kanály vaší multikoptéry.<br><br>Plyn - Spektrum: CH1, Futaba: CH3<br>Bočení - Spektrum: CH4, Futaba: CH4<br>Klopení - Spektrum: CH3, Futaba: CH2<br>Klonění - Spektrum: CH2, Futaba: CH1 - + There is no help available for the current page. Pro tuto stránku není dostupná žádná nápověda. - + Model Wizard Help Nápověda průvodce nastavením modelu @@ -10453,37 +12088,37 @@ Funkce trimu bude opačná, stejně tak i varování polohy páky plynu. WizardPrinter - + Plane Letadlo - + Multicopter Multikoptéra - + Helicopter Helikoptéra - + Model Name: Název modelu: - + Model Type: Typ modelu: - + Options: Volby: - + Channel %1: Kanál %1: @@ -10659,44 +12294,44 @@ m2560 pro V4 desky sériový port sam-ba - + DFU-UTIL Configuration Konfigurace DFU-UTIL - + SAM-BA Configuration Konfigurace SAM-BA - + AVRDUDE Configuration Konfigurace AVRDUDE - - - + + + Select Location Procházet umístění - + List available programmers Seznam použitelných programátorů - + Avrdude help - + Companion - + <b><u>WARNING!</u></b><br>Normally CPU type is automatically selected according to the chosen firmware.<br>If you change the CPU type the resulting eeprom could be inconsistent. <b><u>VAROVÁNÍ!</u></b><br>Běžně je typ CPU vybrán podle typu zvoleného firmware.<br>Pokud změníte typ CPU, výsledná eeprom nemusí být platná. @@ -10753,75 +12388,75 @@ m2560 pro V4 desky - - - - + + + + Error Chyba - + Open Firmware File Otevřít soubor firmwaru - + Can not load embedded image from firmware file %1. Nelze načíst vložený obrázek ze souboru firmwaru %1. - + Open Image to load Otevřít soubor s logem - + Images (%1) obrázky (%1) - + Cannot load the image file %1. Nelze načíst obrázek %1. - + Cannot load profile image %1. Nelze načíst obrázek profilu %1. - + Cannot load the library image %1. Nelze načíst obrázek z knihovny %1. - + File Saved Soubor byl uložen - + The image was saved to the file %1 Obrázek byl uložen do souboru %1 - + Image Refresh Error Chyba čtení obrázku - + Failed to refresh image from file %1 Nelze číst obrázek ze souboru %1 - + File Save Error Nelze uložit - + Failed to write image to %1 Nelze uložit obrázek do %1 @@ -10834,17 +12469,17 @@ m2560 pro V4 desky Stahuji: - + Unable to save the file %1: %2. Nelze uložit soubor %1: %2. - + Companion - + Download failed: %1. Stažení se nezdařilo: %1. @@ -10857,231 +12492,155 @@ m2560 pro V4 desky Nastavte joystick - + Ch2 - - - - - - - - - Not Assigned - Nepřiřazeno - - - - - - - - - - - Right Vertical - Pravá vertikální - - - - - - - - - - - Right Horizontal - Pravá horizontální - - - - - - - - - - - Left Vertical - Levá vertikální - - - - - - - - - - - Left Horizontal - Levá horizontální - - - - - - - - - - - P1 - Potenciometr 1 - - - - - - - - - - - P2 - Potenciometr 2 - - - - - - - - - - - P3/LS - Potenciometr 3 /LS - - - - - - - - - - - RS - - - - + Ch1 - + Ch4 - + Ch6 - + Ch3 - + Ch5 - + Ch7 - + Ch8 - + Instructions Instrukce - + + Enable + Povolit + + + Cancel Zrušit - + + Back + + + + + Start + První kanál + + + Next Další - + Ok OK - - Move sticks and pots in every direction making full movement -Press next when finished - Hýbejte pákami a potenciometry ve všech směrech až do krajních poloh. -Potom stiskněte tlačítko Další + + Not Assigned + - - + + Stick + + + + + Knob/Slider %1 + + + + + No joysticks found + Joystick nenalezen + + + Error Chyba - + Cannot open joystick. Nemohu otevřít joystick. - + + Press the Start button to start the stick range calibration procedure. +You may change the channel assignments or inversion at any time. + + + + + Move sticks and pots in every direction making full movement +Press Next when finished + + + + Place sticks and pots in middle position. -Press next when done - Umístěte páky a potenciometry do střední polohy. -Potom stiskněte tlačítko Další +Press Next when done + - + Map joystick channels to controls using comboboxes. -Press next when done - Přiřaďte kanály joysticku k ovládání funkcí. -Potom stiskněte tlačítko Další +Press Next when done. + - - Check inversion checkbox to get maximum at top-right position. -Press next when done - Zkontroluj invertovací políčka k nastavení maxima v pravé horní pozici. -Potom stiskněte tlačítko Další + + Check inversion checkbox to if necessary to reverse direction. +Press Next when done. + - - Press ok to save configuration -Press cancel to abort joystick calibration - Stiskem tlačítka OK uložíte konfiguraci. -Tlačítkem Zrušit přerušíte kalibraci + + Press OK to save configuration +Press Cancel to abort joystick calibration without saving. + - - Duplicated stick assignment - Duplicitní přiřazení páky + + Warning + - - - mdiChild - - Simulate Tx - Simulace Rádia + + Calibration not complete, save anyway? + diff --git a/companion/src/translations/companion_de.ts b/companion/src/translations/companion_de.ts index 88c703579..507812dc9 100644 --- a/companion/src/translations/companion_de.ts +++ b/companion/src/translations/companion_de.ts @@ -1,30 +1,30 @@ - + AileronsPage - + No Nein - + Yes, controlled by a single channel Ja, mit einem Kanal - + Yes, controlled by two channels Ja, mit 2 Kanälen - + <br>First Aileron Channel: <br> Erster, rechter Querruder Kanal - + Second Aileron Channel: Zweiter, linker Querruder Kanal @@ -32,27 +32,27 @@ AirbrakesPage - + No Nein - + Yes, controlled by a single channel Ja, mit 1 Servo - + Yes, controlled by two channels Ja, mit 2 Servos - + <br>First Airbrake Channel: <br> Erster, rechter Airbrake Kanal - + Second Airbrake Channel: Zweiter, linker Airbrake Kanal @@ -69,15 +69,6 @@ Radio Profile Sender Profil - - - - - - - Open Folder - Verzeichnis öffnen - Default Channel Order @@ -315,6 +306,20 @@ Mode 4: A T E R Q G H S + + + + + + + Select Folder + + + + + Select Executable + + Use OpenTX firmware nightly builds @@ -422,11 +427,6 @@ May be different from firmware language Files to keep Dateien - - - Find Executable - Ausführbare Datei auswählen - Google Earth Executable @@ -523,498 +523,149 @@ May be different from firmware language Schalterstellungen im Simulator merken - + My Radio Mein Sender - + Select your snapshot folder Auswahl des Snapshot Verzeichnis - - + + No joysticks found Kein Joystick gefunden - + EMPTY: No radio settings stored in profile LEER: Keine Sender-Einstellungen im Profil gespeichert - + AVAILABLE: Radio settings of unknown age Verüfgbar: Sender-Einstellungen mit unklarem Alter - + AVAILABLE: Radio settings stored %1 Verfügbar: Sender-Einstellungen gespeichert %1 - + Select your library folder Auswahl des Bibliotheks-Verzeichnis - - + + Select your Models and Settings backup folder Auswahl der Modell-und Einstellungs-Verzeichnisse - + Select Google Earth executable Wähle Google Earth exe - + Select the folder replicating your SD structure - + Not possible to remove profile - + The default profile can not be removed. - + Open Image to load Öffne Bild zum laden - + Images (%1) Bilder (%1) - - Calibration - - - Form - Form - - - - SQ - SQ - - - - SR - SR - - - - LS2 - LS2 - - - - SP - SP - - - - SO - SO - - - - S4 - S4 - - - - RS - RS - - - - SB - SB - - - - Serial Port - Serielle Schnittstelle - - - - - - - - - - - - - Beeper volume - -0 - Quiet. No beeps at all. -1 - No Keys. Normal beeps but menu keys do not beep. -2 - Normal. -3 - Loud. -4 - Extra loud. - Lautstärke Piepser - -0 - Leise. Kein Piepston -1 - Kein Tastaturpieps. Normale Piepstöne aber kein Tastaturpieps -2 - Normal -3 - Laut -4 - Sehr laut. - - - - OFF - AUS - - - - S-Port Mirror - S_Port Ausgang - - - - Telemetry - Telemetrie - - - - SBUS Trainer - SBus Schüler - - - - Debug - Debugmode - - - - Rud - Sei - - - - - Mid value - Mitte Wert - - - - Pot. 4 - Poti 4 - - - - Pot. 3 - Poti 3 - - - - Pot. 2 - Poti 2 - - - - Pot. 1 - Poti 1 - - - - PPM 1 - PPM 1 - - - - Stick 3 - Knüppel 3 - - - - - Negative span - Neg Bereich - - - - - Positive span - Pos Bereich - - - - Stick 1 - Knüppel 1 - - - - PPM 2 - PPM 2 - - - - Stick 2 - Knüppel 2 - - - - Stick 4 - Knüppel 4 - - - - v - V - - - - PPM Multiplier - PPM Multiplikator - - - - PPM 3 - PPM 3 - - - - PPM 4 - PPM 4 - - - - Battery Offset - - - - - Current Offset - - - - - S1 - S1 - - - - S2 - S2 - - - - S3 - S3 - - - - SA - SA - - - - Ele - Höh - - - - Ail - Qur - - - - Thr - Gas - - - - SC - SC - - - - LS - LS - - - - SD - SD - - - - SE - SE - - - - SF - SF - - - - SG - SG - - - - SH - SH - - - - SI - SI - - - - SJ - SJ - - - - SK - SK - - - - SL - SL - - - - SM - SM - - - - SN - SN - - - - RS2 - RS2 - - - - Bluetooth - - - - - CalibrationPanel - - - - - None - Kein - - - - 2 Positions Toggle - 2 Position Taster - - - - 2 Positions - 2 Positionen - - - - 3 Positions - 3 Positionen - - - - Pot with detent - Poti mit Raste - - - - Multipos switch - Stufenschalter - - - - Pot without detent - Poti ohne Raste - - - - Slider with detent - Schieber mit Raste - - Channels - + Name Name - + Min Min - + Max Max - + Subtrim Mitte - + Direction Richtung - + Curve Kurve - + PPM Center PPM Mitte - + Linear Subtrim Lineare Mitte - - Channel %1 - Kanal %1 + + CH%1 + CH%1 - + --- --- - + INV INV + + CompanionMacros + + + files + + + + + Radio and Models settings + + + CompareDialog @@ -1048,17 +699,17 @@ May be different from firmware language Druck in Datei - + No name Kein Namen - + Print Document Drucke Dokument - + Select PDF output file PDF Output Datei wählen @@ -1066,7 +717,7 @@ May be different from firmware language ConclusionPage - + OK, I understand. OK verstanden @@ -1074,42 +725,42 @@ May be different from firmware language ContributorsDialog - + OpenTX Contributors - + Main Developers - + Other contributors - + Companies and projects who have donated to OpenTX - + People who have donated to OpenTX - + Honors go to Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) - + OpenTX Blacklist - + monthly @@ -1117,24 +768,24 @@ May be different from firmware language CopyProcess - - - + + + Error Fehler - + Write error Schreibfehler - + Cannot write %1 (reason: %2) - + Cannot open %1 (reason: %2) @@ -1142,22 +793,22 @@ May be different from firmware language CurveGroup - + Diff Diff - + Expo Expo - + Func Funktion - + Curve Kurve @@ -1246,72 +897,72 @@ May be different from firmware language Kurven Name - + Curve %1 Kurve %1 - + %1 points %1 Punkte - + Linear Linear - + Single Expo Enfache Expo - + Symmetrical f(x)=-f(-x) Punktsym. Expo - + Symmetrical f(x)=f(-x) Achsensym. Expo - + Copy Kopieren - + Paste Einfügen - + Clear Löschen - + Clear all curves Lösche alle Kurven - + Are you sure you want to reset curve %1? Die Kurve %1 wirklich löschen? - + Are you sure you want to reset all curves? Wirklich alle Kurven löschen? - + Editing curve %1 Kurve %1 bearbeiten - + Not enough free points in EEPROM to store the curve. Nicht genug freie Punkte im EEPROM um die Kurve zu speichern @@ -1319,88 +970,88 @@ May be different from firmware language CustomFunctionsPanel - + Switch Schalter - + Action Aktion - + Parameters Parameter - + Enable Aktivieren - + SF%1 SF%1 - + GF%1 GF%1 - + ON EIN - + Error Fehler - + Unable to find sound file %1! Kann das Soundfile %1 nicht finden - + &Delete &Löschen - + Delete Löschen - + &Copy &Kopieren - + Ctrl+C Ctrl+C - + &Cut &Ausschneiden - + Ctrl+X Ctrl+X - + &Paste Ein&fügen - + Ctrl+V Ctrl+V @@ -1408,22 +1059,22 @@ May be different from firmware language CyclicPage - + 90 90 - + 120 120 - + 120x 120x - + 140 140 @@ -1431,98 +1082,174 @@ May be different from firmware language DebugOutput - + Debug Output Debug Ausgabe + + + <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> + + + + + Filter: + + + + + <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> +To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> + + + + + Buffer: + + + + + Number of lines to keep in display. + + + + + Filter &Help + + + + + Show information about using the filter. + + + + + Word &Wrap + + + + + Toggle word wrapping on/off. + + + + + &Clear + + + + + Clear the output window of all text. + + + + + Enable &Filter + + + + + Turn the filter on/off. + + + + + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> + + + + + Debug Console Filter Help + + EepromInterface - + Possible causes for this: - + - Eeprom is from a newer version of OpenTX - + - Eeprom is not from OpenTX - + - Eeprom is not from Th9X - + - Eeprom is not from Gruvin9X - + - Eeprom is not from ErSky9X - + - Eeprom is not from Er9X - + - Eeprom size is invalid - + - Eeprom file system is invalid - + - Eeprom is from a unknown board - + - Eeprom is from the wrong board - + - Eeprom backup not supported - + - Something that couldn't be guessed, sorry - + Warning: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - + Warnings! @@ -1530,12 +1257,12 @@ May be different from firmware language ElevonsPage - + <br>First Elevon Channel: <br>Erster Rechter Höhenruder Kanal - + Second Elevon Channel: Zweiter Linker Höhenruder Kanal @@ -1651,30 +1378,50 @@ If blank then the input is considered to be "ON" all the time.BEIDE - + Edit %1 Edit %1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + FblPage - + Throttle Channel: Gas Kanal - + Yaw Channel: Yaw Heck Kanal - + Pitch Channel: Pitch Kanal - + Roll Channel: Roll Kanal @@ -1726,27 +1473,27 @@ May be different from firmware language FlapsPage - + No Nein - + Yes, controlled by a single channel Ja mit einem Kanal - + Yes, controlled by two channels Ja, mit 2 Kanälen - + <br>First Flap Channel: <br> Erster, rechter Flap Kanal - + Second Flap Channel: Zweiter, linker Flap Kanal @@ -1755,7 +1502,7 @@ May be different from firmware language FlashEEpromDialog - + Write Models and Settings to Radio Schreibe Modelle und Einstellungen in den Sender @@ -1771,7 +1518,6 @@ May be different from firmware language - Allows Companion to write to older version of the firmware @@ -1780,6 +1526,11 @@ May be different from firmware language Check Firmware compatibility Firmware Kompatibilität prüfen + + + <html><head/><body><p>Saves a dated copy of your eeprom to the backup folder you specified in the Companion settings before writing the current model to the radio.</p></body></html> + + Backup before Write @@ -1816,105 +1567,66 @@ May be different from firmware language Schreibe in Sender - + Current profile: %1 - + Choose Radio Backup file - - - - - - - - - - + + Error Fehler - - - Unable to find file %1! - Kann die Datei %1 nicht finden ! - - - - - - Error opening file %1: -%2. - Fehler beim Öffnen der Datei %1: -%2. - - - - - Invalid Models and Settings File %1 - Ungültige Modell- und Einstellungsdatei %1 - - - - Error reading file %1: -%2. - - - Invalid Models and Settings file %1 - - - - - - - + + + Warning Warnung - + Wrong radio calibration data in profile, Settings not patched - + Wrong radio setting data in profile, Settings not patched - - + Cannot write file %1: %2. - + Kann Datei %1: +%2 nicht schreiben. - + Error writing file %1: %2. Fehler beim Schreiben der Datei %1: %2. - + The radio firmware belongs to another product family, check file and preferences! - + The radio firmware is outdated, please upgrade! Die Sender Firmware ist überholt, bitte updaten! - + Cannot check Models and Settings compatibility! Continue anyway? @@ -1992,119 +1704,119 @@ May be different from firmware language Schreibe in Sender - + Open Firmware File - + Öffne Firmware Datei - - - + + + Warning Warnung - + %1 may not be a valid firmware file - - - - + + + + Error Fehler - + The firmware file is not valid. - + There is no start screen image in the firmware file. - + Profile image %1 is invalid. - + Open image file to use as radio start screen - + Images (%1) Bilder (%1) - + Image could not be loaded from %1 - + The library image could not be loaded - + Splash image not found - + Cannot save customized firmware Kann benutzerspezifische Firmware nicht speichern - + Write Firmware to Radio Schreibe Firmware in den Sender - - + + Firmware check failed - + Could not check firmware from radio - + New firmware is not compatible with the one currently installed! - + Conversion failed Umwandlung gescheitert - + Cannot convert Models and Settings for use with this firmware, original data will be used - + Restore failed Wiederherstellung gescheitert - + Could not restore Models and Settings to Radio. The models and settings data file can be found at: %1 - + Flashing done @@ -2112,47 +1824,47 @@ May be different from firmware language FlashProcess - + Executable %1 not found - + Writing... Schreiben - + Reading... Lesen - + Verifying... Vergleichen - + unknown unbekannt - + ie: OpenTX for 9X board or OpenTX for 9XR board ie: OpenTX für das 9X Board oder OpenTX für das 9XR Board - + ie: OpenTX for M128 / 9X board or OpenTX for 9XR board with M128 chip ie: OpenTX für das M128 / 9X Board oder OpenTX für das 9XR Board mit dem M128 chip - + ie: OpenTX for Gruvin9X board ie: OpenTX für das Gruvin9X Board - + Your radio uses a %1 CPU!!! Please check advanced burn options to set the correct cpu type. @@ -2161,7 +1873,7 @@ Please check advanced burn options to set the correct cpu type. Bitte die weiteren Brenn-Optionen prüfen und den CPU Typ correct setzen - + Your radio uses a %1 CPU!!! Please select an appropriate firmware type to program it. @@ -2170,7 +1882,7 @@ Please select an appropriate firmware type to program it. Bitte dazu eine passende Firmware zum programmieren auswählen - + You are currently using: %1 @@ -2178,29 +1890,29 @@ You are currently using: %1 - + Your radio does not seem connected to USB or the driver is not installed!!! Please use ZADIG to properly install the driver. - + Your radio does not seem connected to USB or the driver is not initialized!!!. - + Flashing done (exit code = %1) - + Flashing done with errors - + FUSES: Low=%1 High=%2 Ext=%3 FUSES: Low=%1 High=%2 Ext=%3 @@ -2231,35 +1943,65 @@ Please use ZADIG to properly install the driver. FlightModePanel - + Rotary Encoder %1 Drehgeber %1 - + + Name + Name + + + + Value source + + + + + Value + Wert + + + GVAR%1 GVAR%1 - + Popup enabled Anzeige im Popupfenster freigeben + + + &Clear + + + + + Clear + Löschen + + + + Clear all current Flight Mode properties? + + FlightModesPanel - + Flight Mode %1 Flugphase %1 - + (%1) (%1) - + (default) (normal) @@ -2267,17 +2009,17 @@ Please use ZADIG to properly install the driver. FlybarSelectionPage - + Has Flybar Has Flybar - + Flybarless Flybarless - + Flybar: Flybar: @@ -2374,13 +2116,13 @@ p, li { white-space: pre-wrap; } Das Ändern der Fuses kann Deine Fernsteuerung unbrauchbar machen. Mache nur weiter, wenn Du weißt was Du machst - - + + Reset Radio Fuses - + Read Fuses from Radio @@ -2389,8 +2131,8 @@ p, li { white-space: pre-wrap; } GeneralEdit - General Edit - Sender Grundeinstellungen + Radio settings + @@ -2400,12 +2142,12 @@ These will be relevant for all models in the same EEPROM. Dieses sind für alle Modelle im gleichen EEPROM gültig. - + Setup Einstellungen - + Trainer Schüler Signaleingang @@ -2420,38 +2162,49 @@ Dieses sind für alle Modelle im gleichen EEPROM gültig. Verwende Kal-und HW Einstellungen aus dem Profil - + Global Functions Globale Funktionen - - Hardware / Calibration - Hardware Kalibrierung + + Hardware + - - + + Calibration + + + + + + Warning Warnung - + Wrong data in profile, radio calibration was not retrieved Falsche Werte im Profil, Sender-Kalibireierung wurde nicht ausgeführt - + + Wrong data in profile, Switch/pot config not retrieved + + + + Wrong data in profile, hw related parameters were not retrieved Falsche Werte im Profil, HW Parameter wurden nicht verwendet - + Do you want to store calibration in %1 profile<br>overwriting existing calibration? Wollen Sie die Kalibrierwete im %1 Profil speichern<br>und die vorhandenen Kalibrierwerte überschreiben? - + Calibration and HW parameters saved. Kalibrierung und HW Parameter gesichert @@ -2509,166 +2262,165 @@ Dieses sind für alle Modelle im gleichen EEPROM gültig. SG - + Timeshift from UTC Zeitverschiebung von UTC - + Voice Language Ansagesprache - + Country Code Ländercode - + Stick reverse Knüppel umkehren - + FAI Mode FAI Modus - - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Achutng Bei FAI-Mode gibt es keine Vario, keine Ansage und Telemetrie. Diese Funktionen können dann nicht mehr am Sender aktivert werden - + Adjust RTC Uhr einstellen - + Vario pitch at max Vario Tonhöhe bei Max-Steig - - + + Hz Hz - + Speaker Volume Lautstärke Gesamt - + Backlight Switch LCD Beleuchtung EIN mit - + Sound Mode Sound Modus - + Color 1 Farbe 1 - + Color 2 Farbe2 - + Speaker Pitch (spkr only) Lautstärke (Spkr Mod) - + If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. Wenn dieser Wert ungleich 0 ist, wird die Hintergrundbeleuchtung nach irgendeinem Tastendruck eingeschaltet und nach einer eingestellten Zeit in Sekunden ausgeschaltet. - + sec sek - + Backlight color LCD Beleuchtung Farbe - + Beeper Piepser - + Speaker Lautsprecher - + BeeperVoice Beeper Sound - + SpeakerVoice Sprecher Stimme - + Beep volume Piepser Lautstärke - + Wav volume Wav Lautstärke - + Vario volume Vario Lautstärke - + Background volume Hintergrundlautstärke - - + + ms ms - + Backlight Auto OFF after LCD Beleuchtung AUS nach - + Backlight flash on alarm LCD Beleucht. an bei Alarm - + Vario pitch at zero Vario Tonhöhe bei Min-Sink - + Vario repeat at zero Vario Ton Wiederholrate - + This is the switch selectrion for turning on the backlight (if installed). @@ -2677,8 +2429,8 @@ und nach einer eingestellten Zeit in Sekunden ausgeschaltet. - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2689,32 +2441,42 @@ p, li { white-space: pre-wrap; } Die Werte können sein - + Backlight Brightness LCD Beleuchtung Helligkeit - + RotEnc Navigation Drehgeber Navigation - + + Automatically adjust the radio's clock if a GPS is connected to telemetry. + + + + America Amerika - + Japan Japan - + Europe Europa - + + Backlight OFF Brightness + + + + Mode selection: Mode 1: @@ -2755,271 +2517,271 @@ Mode 4: - + Mode 1 (RUD ELE THR AIL) Mode 1 (Sei Höh Gas Qur) - + Mode 2 (RUD THR ELE AIL) Mode 2 (Sei Gas Höh Qur) - + Mode 3 (AIL ELE THR RUD) Mode 3 (Qur Höh Gas Sei) - + Mode 4 (AIL THR ELE RUD) Mode 4 (Qur Gas Höh Sei) - + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> - + R E T A S H G Q - + R E A T S H Q G - + R T E A S G H Q - + R T A E S G Q H - + R A E T S Q H G - + R A T E S Q G H - + E R T A H S G Q - + E R A T H S Q G - + E T R A H G S Q - + E T A R H G Q S - + E A R T H Q S G - + E A T R H Q G S - + T R E A G S H Q - + T R A E G S Q H - + T E R A G H S Q - + T E A R G H Q S - + T A R E G Q S H - + T A E R G Q H S - + A R E T Q S H G - + A R T E Q S G H - + A E R T Q H S G - + A E T R Q H G S - + A T R E Q G S H - + A T E R Q G H S - + Stick Mode Knüppelmodus - + Metric Metrisch - + Imperial Zöllig - + Default Channel Order Voreingest. Kanalordnung - + GPS Coordinates GPS Koordinaten - + Min Min - - + + v V - + Max Max - + Low Memory Warning Low Memory Warnung - + Inactivity Timer Inaktivitätstimer - + Show Splash Screen on Startup Zeige Startbild an - + Contrast LCD Kontrast - + Battery Meter Range Akku Ladestand - + Haptic Strength Haptik Stärke - + LCD Display Type LCD Display Typ - + "No Sound" Warning Keine Sound Warnung - + Battery Warning Sender Akkuwarnung - + Haptic Length Haptik Länge - + MAVLink Baud Rate Mav Link Baudrate - - + + Quiet Stumm - + Only Alarms Nur Alarme - - + + No Keys Kein Tastenpieps - - + + All Alles - + Battery warning voltage. This is the threashhold where the battery warning sounds. @@ -3030,114 +2792,114 @@ Legt die Schaltschwelle fest wann die Warnung für die Akku-Unterspannungmeldung Werte liegen zwischen 5-10V - + Standard Standard - + Optrex Optrex LCD - + If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. Falls ungleich 0 ertönt ein Piepston wenn der Sender für eine bestimmte Anzahl Minuten nicht bedient wurde. - + min Min - - + + Show splash screen on startup Zeige Startbild an - + --- --- - + 2s 2s - + 3s 3s - + 4s 4s - + 6s 6s - + 8s 8s - + 10s 10s - + 15s 15s - + 4800 Baud 4800 Baud - + 9600 Baud 115200 Baud {9600 ?} - + 14400 Baud 14400 Baud - + 19200 Baud 19200 Baud - + 38400 Baud 38400 Baud - + 57600 Baud 57600 Baud - + 76800 Baud 76800 Baud - + 115200 Baud 115200 Baud - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -3158,72 +2920,72 @@ Warnung stummer Betrieb - Wird angezeigt, wenn der Piepser komplett ausgeschalte - - + + X-Short X-kurz - - + + Short Kurz - - + + Normal Normal - - + + Long Lang - - + + X-Long X-lang - - + + hh° (N/S) mm' ss''.dd GMS hh° (N/S) mm' ss''.dd - + NMEA NMEA - + Play Delay (switch mid position) Schalter Mittenpos. verzögern - + Measurement Units Maßeinheiten - + Haptic Mode Haptik Modus - + Beeper Length Piepser Länge - + Beeper Mode Modus Piepser - + Beeper volume 0 - Quiet. No beeps at all. @@ -3240,7 +3002,7 @@ Warnung stummer Betrieb - Wird angezeigt, wenn der Piepser komplett ausgeschalte 4 - Sehr laut. - + Alarms Only Nur Alarme @@ -3248,7 +3010,7 @@ Warnung stummer Betrieb - Wird angezeigt, wenn der Piepser komplett ausgeschalte GeneralSetupPanel - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Are you sure ? @@ -3260,21 +3022,330 @@ Sind Sie sicher, dass sie das so wollen? GyroPage - + No Nein - + Yes, controled by a switch Ja, mit Schalter gesteuert - + Yes, controlled by a pot Ja, mit Poti gesteuert + + Hardware + + + Form + Form + + + + SQ + SQ + + + + SR + SR + + + + LS2 + LS2 + + + + SP + SP + + + + SO + SO + + + + S4 + S4 + + + + RS + RS + + + + SB + SB + + + + PPM 2 + PPM 2 + + + + + + + + + + + + + Beeper volume + +0 - Quiet. No beeps at all. +1 - No Keys. Normal beeps but menu keys do not beep. +2 - Normal. +3 - Loud. +4 - Extra loud. + Lautstärke Piepser + +0 - Leise. Kein Piepston +1 - Kein Tastaturpieps. Normale Piepstöne aber kein Tastaturpieps +2 - Normal +3 - Laut +4 - Sehr laut. + + + + OFF + AUS + + + + S-Port Mirror + S_Port Ausgang + + + + Telemetry + Telemetrie + + + + SBUS Trainer + SBus Schüler + + + + Debug + Debugmode + + + + Rud + Sei + + + + PPM 3 + PPM 3 + + + + S1 + S1 + + + + S2 + S2 + + + + S3 + S3 + + + + PPM 1 + PPM 1 + + + + Serial Port + Serielle Schnittstelle + + + + v + V + + + + PPM Multiplier + PPM Multiplikator + + + + Current Offset + + + + + PPM 4 + PPM 4 + + + + SA + SA + + + + Ele + Höh + + + + Ail + + + + + Thr + Gas + + + + SC + SC + + + + LS + LS + + + + SD + SD + + + + Battery Offset + + + + + SE + SE + + + + SF + SF + + + + SG + SG + + + + SH + SH + + + + SI + SI + + + + SJ + SJ + + + + SK + SK + + + + SL + SL + + + + SM + SM + + + + SN + SN + + + + RS2 + RS2 + + + + Bluetooth + + + + + ADC Filter + + + + + HardwarePanel + + + + + None + Kein + + + + 2 Positions Toggle + 2 Position Taster + + + + 2 Positions + 2 Positionen + + + + 3 Positions + 3 Positionen + + + + Pot with detent + Poti mit Raste + + + + Multipos switch + Stufenschalter + + + + Pot without detent + Poti ohne Raste + + + + Slider with detent + Schieber mit Raste + + Heli @@ -3351,22 +3422,22 @@ Sind Sie sicher, dass sie das so wollen? HeliPage - + Throttle Channel: Gas Kanal - + Yaw Channel: Yaw (Heck) Kanal - + Pitch Channel: Pitch Kanal - + Roll Channel: Roll Kanal @@ -3374,121 +3445,121 @@ Sind Sie sicher, dass sie das so wollen? InputsPanel - - + + Move Up Nach oben - - + + Ctrl+Up Ctrl+Up - - + + Move Down Nach unten - - + + Ctrl+Down Ctrl+Down - + Clear All Inputs Alle Inputs löschen - + Not enough available inputs! Nicht genügend freie Eingänge - + Delete Selected Inputs? Lösche ausgewählte Inputs? - + &Add &Addieren - + Ctrl+A Ctrl+a - + &Edit &Editieren - + Enter Eingabe - + &Delete &Löschen - + Delete Löschen - + &Copy &Kopieren - + Ctrl+C Ctrl+C - + &Cut &Ausschneiden - + Ctrl+X Ctrl+X - + &Paste Ein&fügen - + Ctrl+V Ctrl+V - + Du&plicate D&uplizieren - + Ctrl+U Ctrl+U - + Clear Inputs? Eingänge Löschen? - + Really clear all the inputs? wirklich alle Eingänge löschen? @@ -3496,88 +3567,89 @@ Sind Sie sicher, dass sie das so wollen? LogicalSwitchesPanel - + V1 V1 - + V2 V2 - + Duration Dauer - + Delay Verzögerung - + Function Funktion - + AND Switch UND Schalter - + L%1 L%1 - + + + (instant) + + + + &Delete &Löschen - + Delete Löschen - + &Copy &Kopieren - - - (no release) - - - - + + (infinite) (unendlich) - + Ctrl+C Ctrl+C - + &Cut &Ausschneiden - + Ctrl+X Ctrl+X - + &Paste Ein&fügen - + Ctrl+V Ctrl+V @@ -3590,145 +3662,166 @@ Sind Sie sicher, dass sie das so wollen? Companion Log ansehen - + Filename Dateiname - + Open LogFile Öffne LogDatei - + Zoom Zoom - + X X - + Y Y - + Reset Reset - + Fly sessions Flugdaten - + Telemetry logs Telemetrie Logs - + Time (hh:mm:ss) Zeit - + Plot Title Change - + New plot title: - + Axis Label Change - + New axis label: - + Graph Name Change - + New graph name: - + Error: no GPS data not found - + The column containing GPS coordinates must be named "GPS". The columns for altitude "GAlt" and for speed "GSpd" are optional - + Error Fehler - + Cannot write file %1: %2. + Kann Datei %1: +%2 nicht schreiben. + + + + Cursor A: %1 m - + + Cursor B: %1 m + + + + + Time delta: %1 + + + + + Climb rate: %1 m/s + + + + Select your log file Wähle die Log Datei aus - + Available fields Verfügbare Felder - + The selected logfile contains %1 invalid lines out of %2 total lines Die ausgewählte Log-Datei enthält %1 ungültige Zeilen von %2 Gesamtzeilen - + total duration - + duration - + (L1) - + (R1) - + (L2) - + (R2) @@ -3736,657 +3829,537 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt MainWindow - - - - + + File loaded Datei geladen - - - + + Save As Speichern unter - - + + No updates available at this time. Kein Update vorhanden. - + Unable to check for updates. Kann nicht auf Updates überprüfen. - + Executable (*.exe) Anwendung (*.exe) - + Would you like to launch the installer? Möchtest Du das Installationsprogramm starten ? - - Compilation server requires registration, please check OpenTX web site - Der Compiler-Server benötigt eine Registration, bitte auf der OpenTX-Webseite prüfen - - - + Do you want to write the firmware to the radio now ? Wollen sie die Firmware jetzt in den Sender schreiben - - + + File saved Datei gespeichert - + Read Models and Settings From Radio Lese Modell und Einstellungen vom Sender - + Save Radio Backup to File Speichere Sender Backup in Datei - + Read Radio Firmware to File Lese Sender Firmware in Datei - + Display previous warning again at startup ? - + New release available Neuer Softwarestand verfügbar - - + + Error Fehler - + Error opening file %1: %2. Fehler beim Öffnen der Datei %1: %2. - - Compilation server termporary failure, try later - Compiler Server hat einen temporärer Fehler , später nochmal versuchen - - - + A new version of Companion is available (version %1)<br>Would you like to download it? Eine neue Version von Companion ist verfügbar (version%1)<br>Wollen Sie die jetzt Donwloaden? - + A new release of Companion is available, please check the OpenTX website! Eine neue Version von Companion ist verfügbar, bitte auf der opentx webseite nachsehen! - - Not enough memory for all the selected firmware options - Nicht genügend Speicher für all die ausgewählen Optionen - - - + Compilation server too busy, try later Compilation-Server ist ausgelastet, Bitte später nochmal versuchen - + Unknown server failure, try later Unbekannter Server Fehler, Bitte später nochmal versuchen - - + + Yes Ja - - + + No Nein - - + + Release Notes Softwarestände - - + + Do you want to download release %1 now ? Wollen sie jetzt das Release %1 downloaden? - - The selected language will be used the next time you start Companion. - Sprache beim Start von Companion auswählen - - - + The new theme will be loaded the next time you start Companion. - + The icon size will be used the next time you start Companion. - - + + Open Models and Settings file Öffne Modelle und Einstellungs Datei - + Firmware updates Firmware updates - + Current firmware does not provide release notes informations. - + Load backup from file Lade Backup von Datei - + OpenTX Home Page: <a href='%1'>%1</a> OpenTX Home Page: <a href='%1'>%1</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> - + About Companion Über Companion - + Compare models Vergleiche Modelle - + Exit the application Beendet die Anwendung - + Ignore this release %1? - + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> - + Copyright OpenTX Team - + New Neu - + Open... Öffnen - + Save Speichern - + Save As... Speichern als - + Copy Model Kopiere Modell - + A monochrome black icon theme - + A monochrome white icon theme - + A monochrome blue icon theme - + Small Klein - + Use small toolbar icons - + Use normal size toolbar icons - + Normal Normal - + Use big toolbar icons - + Big Groß - + Use huge toolbar icons - + Huge Riesig - + Create a new Models and Settings file Erzeuge eine neue Modell-und Einstellungen-Datei - - + + Save Models and Settings file Speichere Modell und Einstellungen in Datei - + Exit Fertig - + Cut Model Ausschneiden Modell - + Cut current model to the clipboard Ausschneiden aktuelles Modell und in Zwischenablage - + Copy current model to the clipboard Kopiere Modell in die Zwischenablage - + Paste model from clipboard Einfügen Modell aus Zwischenablage - + Paste Model Einfüge Modell - + Classical Klassisch - + The classic companion9x icon theme - + Yerico Yerico - + Yellow round honey sweet icon theme - + Monochrome Monochrom - + MonoWhite Weiß - + MonoBlue Blau - + System language Systemsprache - - - Use system language in menus - Systemsprache in den Menüs - - - - Czech - Czech - - - - Use Czech in menus - Use Czech in menus - - - - German - Deutch - - - - Use German in menus - Deutsch für die Menüs - - - - English - English - - - - Use English in menus - Englisch für die Menüs - - - - Finnish - Finish - - - - Use Finnish in menus - - - - - French - French - - - - Use French in menus - - - - - Italian - Italien - - - - Use Italian in menus - - - - - Polish - Polish - - - - Use Polish in menus - Use Polish in menus - - Spanish - Spanish - - - - Use Spanish in menus - - - - - Swedish - Swedish - - - - Use Swedish in menus - - - - About... Über - + Print... Drucken - + Print current model Drucke aktuelles Modell - + Simulate... Simulation... - + Simulate current model Simulation aktuelles Modell - + Alt+S Alt+S - + Load Backup... Lade Backup - + View Log File... Anzeige Log Datei... - + Open and view log file Öffne und zeige Log Datei an - + Settings... Einstellungen - + Edit Settings Editiere Einstellungen - + Download... Download... - + Download firmware and voice files Download Firmware und Sprechdateien - + Check for Updates... Prüfe auf Update - + Check OpenTX and Companion updates Prüfe Opentx und Companion auf Updates - + Companion Changes... Companion Änderungen... - + Show Companion change log - + Firmware Changes... Firmware Änderungen... - + Show firmware change log - + Compare Models... Vergleiche Modelle - + Edit Radio Splash Image... Editiere Sender Start Bild... - + Edit the splash image of your Radio Editiere das Starthbild für den Sender - + List programmers... Liste der Programmiergeräte... - + Fuses... Fuses - - + + Read Firmware from Radio Lese Firmware aus dem Sender - + Read firmware from Radio Lese Firmware aus dem Sender - - + Write Firmware to Radio Schreibe Firmware in den Sender - + Write firmware to Radio Schreibe Firmware in den Sender - + Add Radio Profile Füge Senderprofil hinzu - + Create a new Radio Setting Profile Erstelle neues Sender Profil - + Manuals and other Documents Handbücher und andere Dokumente - + Open the OpenTX document page in a web browser - + Write Models and Settings To Radio Schreibe Modelle und Einstellungen in den Sender - - + Write Models and Settings to Radio Schreibe Modelle und Einstellungen in den Sender - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -4395,7 +4368,37 @@ We recommend you view the release notes using the button below to learn about an - + + Not enough flash available on this board for all the selected options + + + + + Compilation server temporary failure, try later + + + + + Compilation error + + + + + Invalid firmware + + + + + Invalid board + + + + + Invalid language + + + + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -4406,180 +4409,206 @@ We recommend you view the release notes using the button below to learn about an - - - + + + Companion Companion - - + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + + + + + Synchronize SD Synchronisiere mit SD-Karte - - + + Read Models and Settings from Radio Lese Modelle und Einstellungen aus dem Sender - + + Models and Settings read + + + + + + This function is not yet implemented + + + + OpenTX Companion %1 - Radio: %2 - Profile: %3 - + Configure Communications... Konfiguriere Kommunikation - + Configure software for communicating with the Radio - + Write Backup to Radio Schreibe Backup in den Sender - + Write Backup from file to Radio Schreibe Backup aus Datei in den Sender - + Backup Radio to File Mach Backup von Sender in Datei - + Save a complete backup file of all settings and model data in the Radio - + Contributors... Vergleichen... - + A tribute to those who have contributed to OpenTX and Companion - + SD card synchronization - + + Use default system language. + + + + + Use %1 language (some translations may not be complete). + + + + Recent Files Kürzlich verw. Dateien - + Recent Models+Settings Kürzlich verwendete Modelle+Einstellungen - + Set Icon Theme Icon setzen - + Set Icon Size Icon Größen - + List available programmers Liste der möglichen Programmiergeräte - + Show fuses dialog Zeige Fuses Einstellungen - + Show the application's About box Zeige das Infofenster - + Set Menu Language Menüsprache einstellen - + Show recent Models+Settings documents - + Show the list of radio profiles Anzeige der Sender Profil-Liste - + Write Schreibe - + %2 %2 - + New Radio Neuer Sender - + Checking for updates Überprüfe auf Updates - - + + File Datei - - + + Edit Bearbeiten - + Settings Einstellungen - + Read/Write Lesen/Schreiben - - + + Help Hilfe - - + + Radio Profile Sender Profil - + Ready Fertig @@ -4587,134 +4616,260 @@ We recommend you view the release notes using the button below to learn about an MdiChild - - - - - - - - - - - - - - - - - - + + + + + + Error Fehler - + Editing model %1: Modell %1 bearbeiten : - - + + Delete selected models? + + + + + Cannot delete default model. + Kann das aktive Modell nicht löschen + + + + &Edit + &Editieren + + + + &Restore from backup + Wiederherstellung aus dem Backup + + + + &Model Wizard + &Modell Wizard + + + + &Delete + &Löschen + + + + Delete + Löschen + + + + &Copy + &Kopieren + + + + Ctrl+C + Ctrl+C + + + + &Cut + &Ausschneiden + + + + Ctrl+X + Ctrl+X + + + + + &Paste + Ein&fügen + + + + + Ctrl+V + Ctrl+V + + + + D&uplicate + D&uplizieren + + + + Ctrl+U + Ctrl+U + + + + Move to Category + + + + + &Use as default + setze &Standard + + + + P&rint model + Modell &drucken + + + + Ctrl+P + Ctrl+P + + + + &Simulate model + &Simulation + + + + Alt+S + Alt+S + + + + &Add model + + + + + &Rename category + + + + + &Delete category + + + + + &Add category + + + + + Models and settings will be automatically converted. +If that is not what you intended, please close the file +and choose the correct radio type/profile before reopening it. + + + + + Do you want to overwrite radio general settings? + Wollen sie wirklich die Sender Grundeinstellungen überschreiben? + + + + You are pasting on an not empty model, are you sure? + Sie kopieren in ein nicht leeres Modell, fortfahren? + + + + This category is not empty! + + + + + New model + + + + + Unable to find Horus radio SD card! + + + + + Models and Settings written + + + + Unable to find file %1! Kann die Datei %1 nicht finden ! - - - - + + + + Save As Speichern unter - + Open backup Models and Settings file Öffne Backup Modelle-und Einstellungs Datei - + free bytes Freie Bytes - + + Companion Companion - - - Invalid EEPROM File %1 - Ungültige EEPROM Datei %1 - - - - - - + Error opening file %1: %2. Fehler beim Öffnen der Datei %1: %2. - - + Error reading file %1: %2. Fehler beim Lesen der Datei%1: %2. - - Invalid binary EEPROM File %1 - Ungültige EEPROM Programmdatei %1 - - - - - - - Cannot write file %1: -%2. - Kann Datei %1: -%2 nicht schreiben. - - - - - Error writing file %1: -%2. - Fehler beim Schreiben der Datei %1: -%2. - - - + %1 has been modified. Do you want to save your changes? %1 wurde verändert. Sollen die Änderungen gespeichert werden? - - - - + Warning Warnung - + Invalid binary backup File %1 Ungültige Binär Backup Datei %1 - + Cannot write temporary file! Kann temporäre Datei nicht schreiben! + + + Radio settings + + + + + Simulate Tx + Sender Simulation + MixerDialog @@ -4911,139 +5066,159 @@ If blank then the mix is considered to be "ON" all the time. Nach unten - + DEST -> CH%1 DEST -> CH%1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + MixesPanel - - + + Move Up Nach oben - - + + Ctrl+Up Ctrl+Up - - + + Move Down Nach unten - - + + Ctrl+Down Ctrl+Down - + Clear Mixes Mischer löschen - + Not enough available mixers! Nicht genügend Mischer verfügbar! - + Delete Selected Mixes? Lösche ausgewählte Mischer? - + &Add &Addieren - + Ctrl+A Ctrl+a - + &Edit &Editieren - + Enter Eingabe - + &Toggle highlight - + Ctrl+T Ctrl+T - + &Delete &Löschen - + Delete Löschen - + &Copy &Kopieren - + Ctrl+C Ctrl+C - + Ctrl+X Ctrl+X - + C&ut &Ausschneiden - + &Paste Ein&fügen - + Ctrl+V Ctrl+V - + Du&plicate Du&plizieren - + Ctrl+U Ctrl+U - + Clear Mixes? Mischer löschen? - + Really clear all the mixes? Wirklich alle Mischer löschen ? @@ -5056,32 +5231,32 @@ If blank then the mix is considered to be "ON" all the time. Dialog - + Heli Heli TS-Mischer - + Inputs Inputs - + Logical Switches Logische Schalter - + Special Functions Spezial Funktionen - + Telemetry Telemetrie - + Flight Modes Flugphasen @@ -5091,22 +5266,22 @@ If blank then the mix is considered to be "ON" all the time. Simulation - + Setup Konfiguration - + Mixes Mischer - + Outputs Ausgaben - + Curves Kurven @@ -5114,304 +5289,336 @@ If blank then the mix is considered to be "ON" all the time. ModelPrinter - + %1 bytes - + CH%1 CH%1 - + Exponential Exponential - + Extra Fine Sehr fein - + Fine Fein - + Medium Mittel - + Coarse Grob - + Unknown Unbekannt - + Enabled - + Disabled Inaktiv - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) - + %1, Channels(%2-%3) - + Receiver number(%1) - + + radio Protocol %1, subType %2, option value %3 + + + + Slave/Jack Schüler/Buchse - + Master/SBUS Module - + Lehrer/SBus Module - + Master/CPPM Module Lehrer/CPPM Module - + Master/SBUS in battery compartment - + Lehrer/SBus im Akkufach - + Master/Jack Lehrer/Buchse - + + 90 + 90 + + + + 120 + 120 + + + + 120X + 120X + + + + 140 + 140 + + + Rudder Seitenruder - + Elevator - + Throttle Gas - + Aileron - + Name(%1) - + Slow(u%1:d%2) - + Persistent Dauerhaft - + MinuteBeep - + CountDown(Beeps) - + CountDown(Voice) - + CountDown(Haptic) - + + Off Aus - - - - + + + + FM%1 FM%1 - + FM%1%2 FM%1%2 - + FM%1+%2 - + [I%1] [I%1] - + Input%1 Input%1 - + Weight Gewichtung - + Switch Schalter - - + + NoTrim - + Weight(%1) Gewichtung(%1) - + Switch(%1) Schalter(%1) - + No DR/Expo Kein DR/Expo - + + Offset(%1) Offset(%1) - + Delay(u%1:d%2) - + Warn(%1) - + Disabled in all flight modes - + Flight modes(%1) Flugphasen(%1) - + Flight mode(%1) Flugphase(%1) - + Edge(%1, [%2:%3]) Puls(%1, [%2:%3]) - + + instant + + + + Sticky(%1, %2) SRFF(%1, %2) - + Timer(%1, %2) Takt(%1, %2) - + Duration(%1s) - + Delay(%1s) - + Custom - + Standard - + Standard ModelSelectionPage - + Plane Flugmodell - + Multirotor Multicopter - + Helicopter Hubschrauber - + Model Name: Model Name: - + Model Type: Model Typ: @@ -5419,130 +5626,7 @@ If blank then the mix is considered to be "ON" all the time. ModelsListWidget - - - &Edit - &Editieren - - - - &Restore from backup - Wiederherstellung aus dem Backup - - - - &Model Wizard - &Modell Wizard - - - - &Delete - &Löschen - - - - Delete - Löschen - - - - &Copy - &Kopieren - - - - Ctrl+C - Ctrl+C - - - - &Cut - &Ausschneiden - - - - Ctrl+X - Ctrl+X - - - - &Paste - Ein&fügen - - - - Ctrl+V - Ctrl+V - - - - D&uplicate - D&uplizieren - - - - Ctrl+U - Ctrl+U - - - - &Use as default - setze &Standard - - - - P&rint model - Modell &drucken - - - - Ctrl+P - Ctrl+P - - - - Alt+S - Alt+S - - - - &Simulate model - &Simulation - - - - General Settings - Sender Grundeinstellungen - - - - Delete Selected Models? - Gewähltes Modell löschen ? - - - - - Cannot delete default model. - Kann das aktive Modell nicht löschen - - - - Cannot cut default model. - Kann das aktive Modell nicht ausschneiden - - - - Do you want to overwrite radio general settings? - Wollen sie wirklich die Sender Grundeinstellungen überschreiben? - - - - You are pasting on an not empty model, are you sure? - You are pasting on an not empty model, are you sure ? - Sie kopieren in ein nicht leeres Modell, fortfahren? - - - + No free slot available, cannot duplicate Kein freier Modellspeicherplatz, kann nicht kopieren @@ -5550,142 +5634,199 @@ If blank then the mix is considered to be "ON" all the time. Module - + Failsafe Mode Failsafe Mode - + Start Start - + PPM delay PPM Puls - + Negative Negativ - + Positive Positiv - + Polarity Polarität - + Trainer Mode Trainer Mode - + PPM Frame Length PPM Frame Länge - + CH CH - + + SubType + + + + + Antenna + + + + + Internal + + + + + Ext. + Int. + + + + + Option value + + + + + Bind on startup + + + + + Low Power + + + + us us - + + Multi Radio Protocol + + + + Master/Jack Lehrer/Buchse - + Slave/Jack Schüler/Buchse - + Master/SBUS Module Lehrer/SBus Module - + Master/CPPM Module Lehrer/CPPM Module - + Master/SBUS in battery compartment Lehrer/SBus im Akkufach - + + Show values in: + + + + + % + abbreviation for percent + % + + + + μs + abbreviation for microseconds + + + + ms ms - + Channels Kanäle - + Not set Nicht eingestellt - + Hold Halte Servopos. - + Custom Frei einstellbar - + No Pulses Keine PPM Pulse - + Receiver Empfänger gesp. - + Failsafe Positions Failsafe Positionen - + Protocol Protokoll - + Receiver No. Empfänger Nr. - + Output type - + Open Drain - + Push Pull @@ -5693,43 +5834,43 @@ If blank then the mix is considered to be "ON" all the time. ModulePanel - + Trainer Port Trainer Port - + Internal Radio System Internes HF Modul - + External Radio Module Externes HF Modul - - + + Radio System Sender System - + Extra Radio System - + Value Wert - + Hold Halte Servopos. - + No Pulse keine Pulse @@ -5737,229 +5878,322 @@ If blank then the mix is considered to be "ON" all the time. MultiModelPrinter - + General Model Settings Allgemeine Modell Einstellungen - + Name: - + EEprom Size: - + Timer%1: - + Module%1: - + Module: - + Trainer port: - + Throttle Trim: - + Trim Increment: - + Center Beep: - + + Helicopter Setup + + + + + Swash Type: + + + + + Swash Ring: + + + + + Input + Eingang + + + + Weight + Gewichtung + + + + Long. cyc + + + + + Lateral cyc + + + + + Collective + Kollektiv Pitch-Quelle u. Gew. + + + Flight modes Flugphasen - - + + Flight mode - + Switch Schalter - + Fade IN - + Fade OUT - - + + FM%1 FM%1 - - + + GV%1 GV%1 - + RE%1 - + Limits Grenzen - + Channel - + Name Name - - + + Offset Offset - + Min Min - + Max Max - + Invert Invertieren - + Global Variables - + Inputs Inputs - + Mixers Mischer - + CV%1 - + Curves Kurven - + L%1 L%1 - + Logical Switches Logische Schalter - + SF%1 SF%1 - + Special Functions Spezial Funktionen - + Telemetry Settings Telemetrie Einstellungen - + Analogs - + Unit Einheit - + Scale - + Gewichtung - + A%1 A%1 - + RSSI Alarms + + + Low Alarm + Voralarm + + + + Critical Alarm + Kritischer Alarm + + + + Multiprotocols + + + Subtype + + + + + Video TX frequency + + + + + C2500 frequency fine tune + + + + + Telemetry + Telemetrie + + + + Radio output power + + + + + Servo output frequency + + + + + Option value + + + + + DEFAULT + + MultirotorPage - + Throttle Channel: Gas Kanal - + Yaw Channel: Yaw (Heck) Kanal - + Pitch Channel: Pitch Kanal - + Roll Channel: Roll Kanal @@ -5967,17 +6201,17 @@ If blank then the mix is considered to be "ON" all the time. OptionsPage - + Throttle Cut Gas Freigabe Schalter - + Throttle Timer Gas Timer starten - + Flight Timer Flug Timer starten @@ -6000,17 +6234,17 @@ If blank then the mix is considered to be "ON" all the time. Druck in Datei - + Print Document Drucke Dokument - + Select PDF output file PDF Output Datei wählen - + ODF files (*.odt);;PDF Files(*.pdf);;HTML-Files (*.htm *.html);;All Files (*) ODF files (*.odt);;PDF Files(*.pdf);;HTML-Files (*.htm *.html);;All Files (*) @@ -6044,2339 +6278,2622 @@ If blank then the mix is considered to be "ON" all the time. QObject - + Polish Polish - + CH%1 CH%1 - + No Nein - + RotEnc A Drehgeber A - + Rot Enc B Drehgebeer B - + Rot Enc C Drehgeber C - + Rot Enc D Drehgeber D - + Rot Enc E Drehgeber E - + Trainer Trainer SHGQ - + Trainer RUD Trainer Sei - + Trainer ELE Trainer Höh - + Trainer THR Trainer Gas - + Trainer AIL Trainer Que - + Instant Trim Instant Trim - + Play Sound Audio abspielen - - Start Logs - Start Datenlogger - - - + Haptic Play Haptik - - - + + + --- --- - + Rud Trim Sei Trim - + Ele Trim Höh Trim - + Thr Trim Gas Trim - + Ail Trim Que Trim - + Rot Enc Dreh Geb - + English English - + French French - + Italian Italien - + German Deutch - + Czech Czech - + Slovak Slovak - + Spanish Spanish - + Portuguese Portuguese - + Swedish Swedish - + + Dutch + + + + + Hungarian + + + + No repeat Keine Wiederholung - + Reset Reset - - + S3 S3 - + RSSI Tx RSSI Tx - + RSSI Rx RSSI RX - + A3 A3 - + A4 A4 - + Cells Zellen - + AirSpeed AirSpeed - + dTE dTE - + Hdg Hdg - + A3- A3- - + A4- A4- - + Speed+ Geschw+ - + Dist+ Dist+ - + AirSpeed+ Airspeed+ - + Cell- Zelle- - + Cells- Zellen- - + Vfas- Vfas- - + Curr+ Strom+ - + Powr+ Leistung+ - + ACC ACC - + GPS Time GPS Zeit - - + L1 L1 - - + L2 L2 - - - L3 - L3 - - - - - L4 - L4 - - - - - L5 - L5 - - - - - L6 - L6 - - - - - L7 - L7 - - - - - L8 - L8 - - - - - L9 - L9 - - - - - L10 - L10 - - - - - L11 - L11 - - - - - L12 - L12 - - - - - L13 - L13 - - - - - L14 - L14 - - - - - L15 - L15 - - - - - L16 - L16 - - - - - L17 - L17 - - - - - L18 - L18 - - - - - L19 - L19 - - - - - L20 - L20 - - - - - L21 - L21 - - - - - L22 - L22 - - - - - L23 - L23 - - - - - L24 - L24 - - - - - L25 - L25 - - - - - L26 - L26 - - - - - L27 - L27 - - - - - L28 - L28 - - - - - L29 - L29 - - - - - L30 - L30 - - - - - L31 - L31 - - - - - L32 - L32 - - - + [I%1] [I%1] - + LUA%1%2 LUA%1%2 - + + + L%1 + L%1 + + + TR%1 TR%1 - + FM0 FM0 - + FM1 FM1 - + FM2 FM2 - + FM3 FM3 - + FM4 FM4 - + FM5 FM5 - + FM6 FM6 - + FM7 FM7 - + FM8 FM8 - - S31 - S31 - - - - S32 - S32 - - - - S33 - S33 - - - - S34 - S34 - - - - S35 - S35 - - - - S36 - S36 - - - + One Einmal - + a>x a>x - + a<x a<x - + |a|>x |a|>x - + |a|<x |a|<x - + AND AND - + OR OR - + XOR XOR - + a=b a=b - + a!=b a!=b - + a>b a>b - + a<b a<b - + a>=b a>=b - + a<=b a<=b - + d>=x d>=x - + |d|>=x |d|>=x - + a=x a=x - + a~x a~x - + Timer Takt - + Sticky SRFF - + + Left Horizontal + Links Horizontal + + + + Left Vertical + Links Vertikal + + + + Right Vertical + Rechts Vertikal + + + + Right Horizontal + Rechts Horizontal + + + + Aux. 1 + + + + + Aux. 2 + + + + + Unknown Unbekannt - + played once, not during startup - + repeat(%1s) - + DISABLED Gesperrt - + INV INV - + NOR NOR - + Override %1 Überschreibe %1 - + Set Timer %1 Set Timer %1 - + Vario Varioton Ein/Aus - + Play Track Spiel Sound - + Play Both Sag Beides - + Play Value Sag Wert - + Play Script - + + SD Logs + + + + Volume Lautstärke Gesamt - + Backlight LCD Beleuchtung - + Screenshot LCD Screenshot - + Background Music Hintergrund Musik - + Background Music Pause Hintergrund Musik Pause - + Edge Puls - - - + + + <font color=red><b>Inconsistent parameter</b></font> - + Telemetry Telemetrie - + Value Wert - + Decr: Decr: - + Incr: Incr: - + Played once, not during startup Kommt einmal, aber nicht beim Start - + %1s %1s - + Adjust GV%1 Adjust GV %1 - + SetFailsafe Int. Module - + SetFailsafe Ext. Module - + RangeCheck Int. Module - + RangeCheck Ext. Module - + Bind Int. Module - + Bind Ext. Module - + Rotary Encoder Drehgeber - + Value Wert - + Source Quelle - + GVAR GVAR - + Increment Increment - + Flight - + !Flight mode %1 !Flugphase %1 - + Flight mode %1 Flugphase %1 - + Flight mode %1 value Flugphase %1 Wert - + + -GV%1 (%2) + + + + + GV%1 (%2) + + + + Yellow Gelb - + Orange Orange - + Red Rot - + Winged Shadow How High Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (nicht unterstützt) - + FrSky Sensor Hub FrSky Sensor Hub - + None Kein - + Imperial Imperial - + Metric Metrisch - + + + Uknown error during Simulator startup. + + + + + Simulator Error + + + + + Data Load Error + + + + + Error occurred while starting simulator. + + + + Own value Eigener Wert - - Finnish - Finnish - - - + Keys Tasten - + Sticks Knüppel - + Keys + Sticks Taste+Knüppel - - + + -GV%1 -GV%1 - - - + + + GV%1 GV%1 - - - - + + + + ---- ---- - + THR Gas - - - + + P1 P1 - - - + + P2 P2 - - - + + P3 P3 - - + + Batt TX-Akku - + SWR SWR - + MAX MAX - - S11 - S11 - - - - S12 - S12 - - - - S13 - S13 - - - - S14 - S14 - - - - S15 - S15 - - - - S16 - S16 - - - - S21 - S21 - - - - S22 - S22 - - - - S23 - S23 - - - - S24 - S24 - - - - S25 - S25 - - - - S26 - S26 - - - + RudTrim Left SeiteTrim links - + RudTrim Right SeiteTrim rechts - + EleTrim Down HöheTrim ab - + EleTrim Up HöheTrim auf - + ThrTrim Down GasTrim ab - + ThrTrim Up GasTrim auf - + AilTrim Left QuerTrim links - + AilTrim Right QuerTrim rechts - + + Trim 5 Down + + + + + Trim 5 Up + + + + + Trim 6 Down + + + + + Trim 6 Up + + + + THs GSs - + TH% GS% - + THt GSt - + ??? ??? - + Diff(%1) Diff(%1) - + Expo(%1) Expo(%1) - + Function(%1) Funktion(%1) - + Curve(%1) Kurve(%1) - + !Curve(%1) !Kurve(%1) - - + + Rud Sei - - + + °F - - + + Ele Höh - - + + Thr Gas - - + + Ail unsure Que - + TrmR TrmS - + TrmE TrmH - + TrmT TrmG - + TrmA TrmQ - - - - + + + S1 S1 - - - - - - - + + + + + + + V V - - + + s s - + ft ft - - - + + + m m - - - + + + °C °C - - - + + + ° ° - - + + % % - - - + + + mph mph - - - + + + km/h km/h - - + + m/s m/s - - + + A A - + mA mA - + kts kts - + f f - - + + mAh mAh - - + + W W - + + mW + + + + dB dB - + rpms rpm - - + + g g - + + Rad + + + + hours Std - + minutes min - + seconds sec - + h:m h:m - + m:s m:s - + h:m:s h:m:s - - - - + + + S2 S2 - - - - + + + LS LS - - - - + + + RS RS - - + F1 F1 - - + F2 F2 - - + F3 F3 - - + F4 F4 - - - + + + REa DGa - - - + + + REb DGb - - - + + Trm5 + + + + + Trm6 + + + + + + Timer3 Stoppuhr3 - + Alt Alt - + Rpm Rpm - + Fuel Fuel - + Speed Geschw - + Dist Dist - + GPS Alt GPS Alt - + Cell Zelle - + Vfas Vfas - + Curr Strom - + Cnsp Verbrauch - + Powr Leistung - + AccX AccX - + AccY AccY - + AccZ AccZ - + VSpd V-Speed - + A1- A1- - + A2- A2- - + Alt- Alt- - + Alt+ Alt+ - + Rpm+ Rpm+ - + T1+ T1+ - + T2+ T2+ - - + + Time Zeit - - + + Support for frsky telemetry mod Ünterstützt Frsky Telemetry Mod - - + + Support for jeti telemetry mod Ünterstützt Jeti Telemetry Mod - - + + Support for receiving ardupilot data - - + + Support for receiving NMEA data - + Support for telemetry easy board - - - Support for MAVLINK devices + + Unknown error - - Rotary Encoder use in menus navigation - nutze den Drehgeber für Menü Navigation - - - - - - - - - Enable heli menu and cyclic mix support - Freigabe Helimenü und zykl. Mischer - - - - - - - - - - - - Enable TEMPLATES menu - Freigabe Tamplaptes Menü - - - - - - - No splash screen - Kein Startbild - - - - - - - - - - - - Disable curves menus - Kein Kurvenmenü - - - - - - - Support for radio modified with regular speaker + + ... plus %1 errors - - - - - - Used if you have modified your radio with voice mode + + Cannot write radio settings - - - - - - Used if you have modified your radio with haptic mode + + Cannot write model %1 - - Channel values displayed in us - Kanalwerte Anzeige in us statt % + + 6P + 6P - - - - - - - - - - In model setup menus automatically set source by moving the control + + JSx - - - - - - - - - - In model setup menus automatically set switch by moving the control - - - - - Use alternative SQT5 font - Alternative SQT5 Schrift verw. - - - - (displaying only first 10 warnings) - - - - - Possibility to enable FAI MODE (no telemetry) at field - - - - - FAI MODE (no telemetry) always enabled - - - - - - - - Support for a third timer - - - - - Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) - - - - - Instead of Joystick emulation, USB connection is Command Line Interface - - - - - Removes D8 and LR12 FrSky protocols that are not legal for use in the EU on radios sold after Jan 1st, 2015 + + JSy + Support for the DIY-Multiprotocol-TX-Module + + + + + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 + + + + + Enable Lua compiler + + + + + KS108 LCD + + + + + WTV20 voice module + + + + + JQ6500 voice module + + + + + + Support for MAVLINK devices + + + + + Rotary Encoder use in menus navigation + nutze den Drehgeber für Menü Navigation + + + + FrSky Taranis X9D+ + + + + + FrSky Taranis X9D + + + + + Horus gimbals installed (Hall sensors) + + + + + FrSky Taranis X7 + + + + + FrSky Horus + + + + + Use ONLY with first DEV pcb version + + + + + Turnigy 9XR-PRO + + + + + Turnigy 9XR with m128 chip + + + + + + + + + + Enable heli menu and cyclic mix support + Freigabe Helimenü und zykl. Mischer + + + + + + + + + Enable TEMPLATES menu + Freigabe Tamplaptes Menü + + + + + + + No splash screen + Kein Startbild + + + + + + + + + Disable curves menus + Kein Kurvenmenü + + + + + + + + Support for radio modified with regular speaker + + + + + + + + + Used if you have modified your radio with voice mode + + + + + + + + + Used if you have modified your radio with haptic mode + + + + + Channel values displayed in us + Kanalwerte Anzeige in us statt % + + + + + + + + + + + + In model setup menus automatically set source by moving the control + + + + + + + + + + + + + In model setup menus automatically set switch by moving the control + + + + + + + + + + + + + + + Use alternative SQT5 font + Alternative SQT5 Schrift verw. + + + + Possibility to enable FAI MODE (no telemetry) at field + + + + + FAI MODE (no telemetry) always enabled + + + + + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) + + + + + Instead of Joystick emulation, USB connection is Command Line Interface + + + + + Support for PPM internal module hack - + ST7565P LCD or compatible - + ST7565R LCD or compatible - + ERC12864FSF LCD - + ST7920 LCD - - 9X board - - - - - - - + + + + Enable the throttle trace in Statistics - + EEprom write progress bar EEprom Schreib-Balken - - + + No Winged Shadow How High support - - + + Turnigy 9XR + + + + + No vario support Kein Vario - - + + No GPS support Kein GPS - - + + No gauges in the custom telemetry screen - + + 9X with stock board + + + + Allow compensating for offset errors in FrSky FAS current sensors - - + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) - - Power management by soft-off circuitry - - - - - ar9x board / 9X - - - - - 9XR-PRO + + 9X with stock board and m128 chip - FrSky Taranis + 9X with AR9X board - - FrSky Taranis Plus + + 9X with Sky9x board - + + 9X with Gruvin9x board + + + + + DIY MEGA2560 radio + + + + + Power management by soft-off circuitry + + + + FrSky Taranis X9E - + Confirmation before radio shutdown - - - Adds mixers output view to the CHANNELS MONITOR screen, pressing [ENT] switches between the views - - - - + Haptic module installed Haptikmodul installiert - + Support for Lua model scripts Lua Model-Spriptsprache unterstützen - - + + Support of FrSky PXX protocol Unterstützung von FrSky PXX Protokol - + Disable HELI menu and cyclic mix support Kein Helimenü und zykl. Mischer - + Disable Global variables Keine Globale Variablen - - - - - + + + + + Support for DSM2 modules Ünterstützung für DSM2-Module - - - - - - - - - + + + + + + PPM center adjustment in limits PPM Mitten-Einstellung bei Servo Limits - - - - - - - - - + + + + + + Symetrical Limits Symmetrische Grenzen - - - - - - - + + + + + + + Pots use in menus navigation Potis als Menü Navigation benutzen - + No OverrideCH functions available - - - - - - - - - + + + + + + + + + No flight modes Keine Flugphasen - - + + SmartieParts 2.2 Backlight support - - - - - - + + + + + + Enable resetting values by pressing up and down at the same time - - - - - - - - - + + + + + + + + + No graphical check boxes and sliders - - - - - - - - - + + + + + + + + + Battery graph Akku Ladezustand - - - - - - - - - + + + + + + + + + Don't use bold font for highlighting active items - - - - - + + + + + EEprom write Progress bar EEprom Schreib-Balken - - - - - - + + + + + + Imperial units Zöllige Einheiten - - M128 / 9X board - - - - - 9XR - 9XR - - - - 9XR with M128 chip - - - - - Gruvin9x board / 9X - - - - - MEGA2560 board - - - - - Sky9x board / 9X - - - - - - + + + Bluetooth interface Bluetooth Schnittstelle - - - - - - - - - + + + + + + + + + Global variables Globale Variablen - - + + Support for SD memory card Unterstützung für SD-Speicherkarte - + Support for DSM2 modules using ppm instead of true serial Unterstüzung für DSM2 Modul mit PPM-Signal anstatt echtem seriellem Signal - - - + + + Enable HELI menu and cyclic mix support Freigabe von Heli-Menüs und zyklischer Mischer Unterstützung - - - + + + Timer1 Stoppuhr1 - - - + + + Timer2 Stoppuhr2 - + A1 A1 - + A2 A2 - + T1 T1 - + T2 T2 - - - Simultaneous usage of expo and curves is no longer supported - Gleichzeitiger Gebrauch von Expo und Kurven ist nicht mehr möglich - - - + CYC%1 CYC%1 - - - + + + ON EIN - - - + + + OFF AUS - - + Warning Warnung - - EEPROM saved with these warnings: - EEPROM gespeichert mit diesen Warnungen: - - - + Simulator for this firmware is not yet available - - th9x on this board doesn't have Rotary Encoders + + Switch + Schalter + + + + Switch - + + cannot be exported on this board! + + + + Source %1 cannot be exported on this board! - + OpenTX only accepts %1 points in all curves OpenTX kann nur max %1 Punkte für alle Kurven - + OpenTx only accepts %1 points in all curves - - - - - + + + + + + OpenTX on this board doesn't accept this function OpenTX unterstützt diese Funktion für diese Board nicht - + OpenTX doesn't accept this telemetry protocol - - - + + + OpenTX doesn't accept this radio protocol - + OpenTX doesn't allow this number of channels Opentx kann nicht diese Anzahl von Kanälen - + Trim disabled Trim ausgeschaltet - + Own Trim Eigene Trim - + Use Trim from Flight mode %1 Trim von Flugphase %1 - + Use Trim from Flight mode %1 + Own Trim as an offset Trim von Flugphase %1 + Eigene Trim als Offset - + FW: %1 FW %1 - + Pict: %1 Bild: %1 - + Profile image Profil Bild - - Simultaneous usage of expo and curves is no longer supported in OpenTX - Gleichzeitiger Gebrauch von Expo und Kurven ist in open9x nicht mehr möglich - - - + Thank you for upgrading to OpenTX 2.0. This is a major upgrade that adds and modifies a lot of things, so please make sure that you read release notes carefully to learn about the changes, and thoroughly check each of your models for proper function. The OpenTX Team. - - - - - + + + + + Synchronization error - + No SD directory configured! - + No Radio connected! - + GV GV - + -%1 - - + + The directory '%1' doesn't exist! - + Create '%1' failed - + Copy '%1' to '%2' failed - + Open '%1' failed - + Write '%1' failed - - - + + + + + + + Error Fehler - + Cannot write file %1: %2. - + Kann Datei %1: +%2 nicht schreiben. - + Companion Companion - + <b><u>WARNING!</u></b><br>This will reset the fuses of %1 to the factory settings.<br>Writing fuses can mess up your radio.<br>Do this only if you are sure they are wrong!<br>Are you sure you want to continue? - - + + Could not delete temporary file: %1 - - Radio type + + Unable to find Horus radio SD card! - - Which radio type do you want to simulate? + + Conversion error on field %1 + + + + + Negative span + Neg Bereich + + + + Mid value + Mitte Wert + + + + Positive span + Pos Bereich + + + + + Models + Translators do NOT use accent for this, this is the default category name on Horus. + + + + + Positive + Positiv + + + + Negative + Negativ + + + + Select a data file + + + + + Select Data Directory + + + + + Select SD Card Image Folder + + + + + Available profiles: + + + + + ID: + + + + + Name: + + + + + Available radios: + + + + + WARNING: couldn't initialize SDL: +%1 + + + + + ERROR: No simulator libraries available. + + + + + Radio profile ID or Name to use for simulator. + + + + + Radio type to simulate (usually defined in profile). + + + + + show this help text + + + + + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] + + + + + Options: + + + + + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. + Profile ID: [%1]; Radio ID: [%2]; +Data File: [%3] + + + + + ERROR: Radio profile or simulator firmware not found. +Profile ID: [%1]; Radio ID: [%2] + + + + + Error reading %1: %2 + + + + + Cannot save EEPROM + + + + + + Cannot open file %1: +%2. + + + + + + + Error writing file %1: +%2. + Fehler beim Schreiben der Datei %1: +%2. + + + + Invalid binary EEPROM file %1 + + + + + Can't extract RADIO/radio.bin + + + + + Can't extract RADIO/models.txt + + + + + Can't extract %1 + + + + + Unable to open %1: %2 + + + + + Invalid EEPROM file %1 + + + + + Invalid EEPROM File %1 + Ungültige EEPROM Datei %1 + + + + + Error opening file %1: +%2. + Fehler beim Öffnen der Datei %1: +%2. + + + + Error opening OTX archive %1 + + + + + Error initializing OTX archive writer + + + + + Error creating OTX file %1: +%2. + + + + + Error creating OTX archive + + + + + Error adding %1 to OTX archive + + + + + Error opening file %1 in write mode: +%2. + + + + + Unable to find file %1! + Kann die Datei %1 nicht finden ! + + + + QxtCommandOptions + + + sets the application GUI style + + + + + sets the application stylesheet + + + + + restores the application from an earlier session + + + + + displays debugging information about widgets + + + + + use right-to-left layout + + + + + never grab the mouse or keyboard + + + + + grab the mouse/keyboard even in a debugger + + + + + run in synchronous mode for debugging + + + + + use Direct3D by default + + + + + sets the X11 display + + + + + sets the geometry of the first window + + + + + sets the default font + + + + + sets the default background color + + + + + sets the default foreground color + + + + + sets the default button color + + + + + sets the application name + + + + + sets the application title + + + + + sets the X11 visual type + + + + + limit the number of colors on an 8-bit display + + + + + use a private color map + + + + + sets the input method server + + + + + disable the X Input Method + + + + + sets the style used by the input method + + + + + + option "%1" not found + + + + + Short options cannot have optional parameters + + + + + positional() called before parse() + + + + + unrecognized() called before parse() + + + + + count() called before parse() + + + + + value() called before parse() + + + + + parameters() called before parse() + + + + + unrecognized parameters: + + + + + %1 requires a parameter + + + + + RadioKnobWidget + + + Right-double-click to reset to center. @@ -8398,10 +8915,100 @@ The OpenTX Team. OK + + RadioOutputsWidget + + + Form + Form + + + + View: + + + + + Logical Switches + Logische Schalter + + + + Global Variables + + + + + Channel Outputs + + + + + L +o +g +i +c + + + + + G +l +o +b +a +l + + + + + C +h +a +n +n +e +l +s + + + + + RadioSwitchWidget + + + Latch/unlatch the momentary switch. + + + + + RawSwitch + + + ↑ + + + + + ↓ + + + + + - + + + + + ! + + + ReleaseNotesDialog - + Companion Release Notes Companion Software Stände @@ -8409,7 +9016,7 @@ The OpenTX Team. ReleaseNotesFirmwareDialog - + OpenTX Release Notes Opentx Release Notes @@ -8417,17 +9024,17 @@ The OpenTX Team. RudderPage - + No Nein - + Yes Ja - + <br>Rudder Channel: <br> Seite Kanal: @@ -8604,7 +9211,7 @@ umgedreht und ist dann vorne SetupPanel - + Timer %1 @@ -8612,180 +9219,847 @@ umgedreht und ist dann vorne SimpleTailPage - + Elevator Channel: Höhe Kanal: - SimulatorDialog + SimulatedUIWidget - - + + Rotary encoder click + + + + + Take Screenshot + + + + + screenshot + Simulator LCD screenshot file name prefix + + + + + SimulatedUIWidget9X + + + UP/PG-UP + + + + + [ UP ] + + + + + DN/PG-DN + + + + + [ DN ] + + + + + RIGHT/+ + + + + + [ + ] + + + + + LEFT/- + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + [ UP ]/[ DN ] or Rotary Sel. + + + + + SimulatedUIWidgetX12 + + + PG-UP + + + + + [ PgUp ] + + + + + PG-DN + + + + + [ PgDn ] + + + + + UP + + + + + [ MDL ] + + + + + DN/DEL/BKSP + + + + + [ RTN ] + + + + + LEFT + + + + + [ SYS ] + + + + + RIGHT + + + + + [ TELE ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/X + + + + + Rotary UP + + + + + +/C + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX7 + + + Taranis X7 Simulator + + + + + PG-UP + + + + + [ PAGE ] + + + + + PG-DN + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX9 + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + +/UP + + + + + [ + ] + + + + + -/DN + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ ENT ] + + + + + WHEEL/PAD SCRL + + + + + [ + ]/[ - ] + + + + + SimulatedUIWidgetX9E + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatorMainWindow + + + OpenTx Simulator + + + + + View + + + + + Radio Window + + + + + Reload... + + + + + Tools + + + + + Toolbar + + + + + Reload Lua Scripts + + + + + Reload the Lua environment on the simulated radio. + + + + + F7 + F7 + + + + Reload Radio Data + + + + + Reload all radio data without restarting the simulator. + + + + + F9 + F9 + + + + Key Mapping + + + + + Show keyboard maping reference. + + + + + F1 + F1 + + + + Joystick Settings + + + + + Open joystick configuration settings dialog. + + + + + F3 + F3 + + + + LCD Screenshot + + + + + Save a screenshot of the current simulated LCD screen. + + + + + F8 + F8 + + + + Dock In Main Window + + + + + Show the radio in the main window or as a separate "floating" window. + + + + + Menu Bar + + + + + Show or hide the top menu bar. + + + + + Alt+M + + + + + Constrain Width + + + + + Set radio widget width to be a fixed size. + + + + + Constrain Height + + + + + Set radio widget height to be a fixed size. + + + + + ERROR: Failed to create simulator interface, possibly missing or bad library. + + + + + Alt+T + + + + + Radio Outputs + + + + + F2 + F2 + + + + Telemetry Simulator + Telemetrie Simulator + + + + F4 + F4 + + + + Trainer Simulator + + + + + F5 + F5 + + + + Debug Output + Debug Ausgabe + + + + F6 + F6 + + + + Simulator Controls: + + + + + <tr><th>Key/Mouse</td><th>Action</td></tr> + + + + + Simulator Help + + + + + SimulatorStartupDialog + + + OpenTX Simulator - Startup Options + + + + + Simulator Startup Options: + + + + + Radio Profile: + + + + + Existing radio profiles are shown here.<br /> +Create or edit profiles using the Companion application. + + + + + Radio Type: + + + + + Existing radio simulators are shown here.<br /> +The radio type specified in the selected profile is used by default. + + + + + Data Source: + + + + + Data File: + + + + + Data Folder: + + + + + SD Image Path: + + + + + Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> +<b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! + + + + + Select data file... + + + + + + + ... + ... + + + + Directory containing RADIO and MODELS folders to use.<br /> +New folder(s) with default radio/model will be created here if necessary. + + + + + Select data folder... + + + + + Directory containing the SD card image to use.<br/> +The default is configured in the chosen Radio Profile. + + + + + Select SD card image folder... + + + + + Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. + + + + + File + Datei + + + + Folder + + + + + SD Path + + + + + All files (*.*) + + + + + SimulatorWidget + + + Companion Simulator + Companion Simulator + + + + Radio Simulator (%1) + + + + + Could not determine startup data source. + + + + + Could not load data, possibly wrong format. + + + + + Data Load Error + + + + + Invalid startup data provided. Plese specify a proper file/path. + + + + + Simulator Startup Error + + + + + Error saving data: could open file for writing: '%1' + + + + + Error saving data: could not get data from simulator interface. + + + + + An unexpected error occurred while attempting to save radio data to file '%1'. + + + + + Data Save Error + + + + Warning - Warnung + Warnung - - Joystick enabled but not configured correctly - Joystick eingeschaltet, aber nicht korrekt eingestellt - - - + Cannot open joystick, joystick disabled - Kann joystick nicht öffnen, joystick ausgeschaltet + Kann joystick nicht öffnen, joystick ausgeschaltet - - Simulating Radio (%1) - Simulation Sender (%1) - - - - - - Outputs - Ausgaben - - - + Firmware %1 error: %2 - Firmware %1 Fehler: %2 + Firmware %1 Fehler: %2 - SimulatorDialog9X + SliderWidget - - Companion Simulator - Companion Simulator - - - - - Hold X - Halte X - - - - - Fix X - Fixiere X - - - - - Fix Y - Fixiere Y - - - - - Hold Y - Halte Y - - - - Outputs2 - Ausgang2 - - - - Gvars - Gvars - - - - - - - Right Double Click to Reset - Zurücksetzen mit rechtem Doppelklick - - - - BEEP - Piepston - - - - 9x Simulator - 9x Simulator - - - - Outputs - Ausgaben - - - - SimulatorDialogTaranis - - - Companion Simulator - Companion Simulator - - - - Taranis Simulator - Taranis Simulator - - - - Outputs - Ausgaben - - - - Outputs2 - Ausgang2 - - - - Gvars - Gvars - - - - S3 - S3 - - - - S4 - S4 - - - - - - - Right Double Click to Reset - Zurücksetzen mit rechtem Doppelklick - - - - - Hold Y - Halte Y - - - - - Fix Y - Fixiere Y - - - - - Fix X - Fixiere X - - - - - Hold X - Halte X + + Right-double-click to reset to center. + @@ -8797,27 +10071,27 @@ umgedreht und ist dann vorne ... - + Splash Library - page %1 of %2 Startbild Bibliothek - Seite %1 von %2 - + Warning Warnung - + Invalid image in library %1 ungültige Bilddatei in Bibliothek %1 - + Information Information - + No valid image found in library, check your settings keine gültige Bilddatei gefunden in Bibliothek, bitte Einstellungen prüfen @@ -8825,7 +10099,7 @@ umgedreht und ist dann vorne StandardPage - + Channel %1 Kanal %1 @@ -8833,43 +10107,41 @@ umgedreht und ist dann vorne SyncProcess - + %1/%2 files - + Create directory %1 - - Copy %1 to %2 - + + Copy %1 to %2 - - Write %1 - + + Write %1 TailPage - + Rudder Channel: Seitenruder Kanal - + Elevator Channel: Höhenruder Kanal - + Only one channel still available!<br>You probably should configure your model without using the wizard. @@ -8877,22 +10149,22 @@ umgedreht und ist dann vorne TailSelectionPage - + Elevator and Rudder Höhe und Seite - + Only Elevator Nur Höhe - + V-tail V Leitwerk - + Tail Type: Leitwerk Typ: @@ -9172,7 +10444,7 @@ umgedreht und ist dann vorne Meters (m or ft) Meter (m or ft) - + Temp (°) Temp(°) @@ -9188,7 +10460,7 @@ umgedreht und ist dann vorne mAmp (mA) - + Range Bereich @@ -9201,22 +10473,22 @@ umgedreht und ist dann vorne Telemetrie Anzeige als - + None Kein - + Numbers Nummern - + Bars Balken - + Script Script @@ -9244,99 +10516,99 @@ umgedreht und ist dann vorne TelemetryPanel - + Telemetry screen %1 Telemetrie Bild %1 - + Low Alarm Voralarm - + Critical Alarm Kritischer Alarm - + Winged Shadow How High Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (nicht unterstützt) - - - + + + A1 A1 - + Alti Höhe - + FrSky S.PORT FrSky S.PORT - + FrSky D FrSky D - + FrSky D (cable) FrSky D (Kabel) - + Alti+ Höhe+ - + VSpeed VSpeed - - - + + + A2 A2 - - + + A3 A3 - - + + A4 A4 - - + + FAS FAS - + Cells Zellen - + --- --- @@ -9495,12 +10767,12 @@ umgedreht und ist dann vorne ft ft - + °C °C - + °F @@ -9522,26 +10794,36 @@ umgedreht und ist dann vorne + mW + + + + dBm - + g g - - + + ° ° - + + Rad + + + + mL - + US fl.Oz. @@ -9551,57 +10833,57 @@ umgedreht und ist dann vorne Roh (-) - + RPM Drehz - + Precision Precision - + Ratio - + Blades Rotorblätter - + Offset Offset - + Multiplier Muliplikator - + Auto Offset Auto Offset - + Filter Filter - + Persistent Dauerhaft - + Positive Positiv - + Logs Log Daten @@ -9609,22 +10891,22 @@ umgedreht und ist dann vorne TelemetrySensorPanel - + Lowest Niedrigster - + Cell %1 Zelle %1 - + Highest Höchster - + Delta Differenz @@ -9632,240 +10914,560 @@ umgedreht und ist dann vorne TelemetrySimulator - + Telemetry Simulator Telemetrie Simulator - - Vario Altitude - Vario Höhe - - - - V-ALT - V-Höhe - - - - Vario Vertical Speed - Vario Vertikal Geschw - - - - V-VSPD - V-Spd - - - - ACCZ - ACCZ - - - - GPS Time - GPS Zeit - - - - GPS-T - GPS-T - - - - ACCX - ACCX - - - - GPS Lat/Lon - GPS Länge/Breite - - - - GPS-LL - GPS-LB - - - + VFAS VFAS - - FAS-V - FAS-V - - - - GPS Speed - GPS-Speed - - - - GPS-S - GPS-S - - - - CELLS - Zellen - - - - ACCY - ACCY - - - - GPS Course - GPS Kurs - - - - GPS-C - GPS-K - - - - GPS Altitude - GPS Höhe - - - - GPS-A - GPS-H - - - - CURRENT - Strom - - - - FAS-C - FAS-S - - - - 30 - 30 - - - + RSSI RSSI - - 75 - 75 - - - + SWR SWR - - FR_ID_AIR_SPEED - - - - - ASPD - ASPD - - - + A1 A1 - + A2 A2 - + + Simulate + Simulation + + + + Replay SD Log File + + + + + Replay rate + + + + + Load + + + + + |> + + + + + <| + + + + + > + > + + + + <- + + + + + X + X + + + + Row # +Timestamp + + + + + 1/5x + 1/5x + + + + 5x + 5x + + + + No Log File Currently Loaded + + + + + + + V / ratio + + + + + Db + + + + + RxBt + + + + + + + + + + + + + + + + + <html><head/><body><p><br/></p></body></html> + + + + + Tmp1 + + + + A3 A3 - + A4 A4 - - Temperature 1 - Temperatur 1 + + Tmp2 + - - T1 - T1 + + Fuel + Fuel - - Temperature 2 - Temperatur 2 + + °C + °C - - T2 - T2 + + ml + - + + Deg. C + + + + + % + % + + + + + Meters + + + + + Alt + Alt + + + + VSpd + V-Speed + + + + m/s + m/s + + + + Fuel Qty + + + + + + km/h + km/h + + + + Hdg + + + + + ASpd + + + + + + + G + + + + + GPS + + + + + Lat,Lon +(dec.deg.) + + + + + AccX + AccX + + + + dd-MM-yyyy +hh:mm:ss + + + + + Date + + + + + Amps + + + + + AccZ + AccZ + + + + GAlt + + + + + + Volts + + + + + Cels + + + + + Curr + Strom + + + + AccY + AccY + + + + GSpd + + + + + Degrees + + + + + RPM RPM - - FUEL - - - - + When enabled, sends any non-blank values as simulated telemetry data. - - simulate - simuliere + + Log File + - - Instance - SubID + + LOG Files (*.csv) + - - 2 - 2 + + ERROR - invalid file + + + + + Templates + + + Simple 4-CH + - - <html><head/><body><p>Start with <span style=" font-style:italic;">0x</span> for hex, <span style=" font-style:italic;">0</span> for octal, otherwise decimal.<br/>Numeric entry only. Blank values are not sent.</p></body></html> + + T-Cut + + + + + Sticky T-Cut + + + + + V-Tail + V-Leitwerk + + + + Elevon\Delta + + + + + Heli Setup + + + + + Heli Setup with gyro gain control + + + + + Gyro gain control + + + + + Heli Setup (Futaba's channel assignment style) + + + + + Heli Setup with gyro gain control (Futaba's channel assignment style) + + + + + Gyro gain control (Futaba's channel assignment style) + + + + + Servo Test + + + + + MultiCopter + + + + + Use Model Config Wizard + + + + + Apply Template? + + + + + Apply template "%1"? + + + + + + + + + + + RUD + + + + + + + + + + + + + + ELE + + + + + + + THR + Gas + + + + + + + + + + + AIL + + + + + + + + AIL2 + + + + + + + + ELE2 + + + + + + + + + + FLAPS + + + + + + + + + + FLAP%1 + + + + + + + + PITCH + + + + + + + + + + + + GYRO + + + + + + SPOIL + + + + + + SPOIL%1 + + + + + + RUD2 + + + + + + Clear Mixes? + Mischer löschen? + + + + Really clear existing mixes on CH6? + + + + + Really clear existing mixes on CH5? ThrottlePage - + Yes Ja - + No Nein - + <br>Throttle Channel: <br>Gas Kanal: @@ -9886,37 +11488,37 @@ umgedreht und ist dann vorne TimerPanel - + Silent Kein - + Beeps Pieps - + Voice Stimme - + Haptic Play Haptik - + Not persistent Nicht dauerhaft - + Persistent (flight) Dauerhaft für Flug - + Persistent (manual reset) Dauerhaft (per Hand reset) @@ -10047,33 +11649,94 @@ umgedreht und ist dann vorne TrainerSimulator - + Trainer simulator Trainer Simulator + + TreeModel + + + Index + + + + + Name + Name + + + + Size + + + VTailPage - + First Tail Channel: Erster rRechter Leitwerk Kanal - + Second Tail Channel: Zweiter, linker Leitwerk Kanal + + VirtualJoystickWidget + + + Hld Y + + + + + Hold Vertical stick position. + + + + + Fix Y + Fixiere Y + + + + Prevent Vertical movement of stick. + + + + + Fix X + Fixiere X + + + + Prevent Horizontal movement of stick. + + + + + Hld X + + + + + Hold Horizontal stick position. + + + WingtypeSelectionPage - + Standard Wing Normaler Flügel - + Flying Wing / Deltawing Nurflügler / Deltaflügel @@ -10081,273 +11744,273 @@ umgedreht und ist dann vorne WizardDialog - + Model Wizard Modell Wizard - + Model Type Model Type - + Enter model name and model type. Modellname und Modelltyp eingeben - + Throttle Gas - + Has your model got a motor or an engine? Hat das Modell einen Antriebsmotor (Elektro oder Verbrenner) - + Wing Type Flächen Typ - + Is your model a flying wing/deltawing or has it a standard wing configuration? Ist das Modell ein Nurflügel/Delta oder hat es eine normale Fläche - + Ailerons Querruder - + Has your model got ailerons? Hat das Modell Querruder - + Flaps Landeklappen - + Has your model got flaps? Hat das Modell Landeklappen - + Airbrakes Bremsklappen - + Has your model got airbrakes? Hat das Modell Bremsklappen - + Flying-wing / Delta-wing Nurflügler / Deltaflügel - + Select the elevons channels - + Rudder Seitenruder - + Does your model have a rudder? Hat das Modell ein Seitenruder - + Tail Type Leitwerkstyp - + Select which type of tail your model is equiped with. Welchen Hecktyp hat das Modell - - + + Tail Leitwerk - - + + Select channels for tail control. Wähle die Kanäle für das Leitwerk - + V-Tail V-Leitwerk - + Select elevator channel. Wähle den Höhenruder Kanal - + Cyclic Zyklisch - + Which type of swash control is installed in your helicopter? Welchen Typ an Taumelscheibe hat der Heli - + Tail Gyro Heck Kreisel - + Has your helicopter got an adjustable gyro for the tail? Hat der Heli einen einstellbaren Heckkreisel - + Rotor Type Rotorkopf-Typ - + Has your helicopter got a flybar? - - + + Helicopter Hubschrauber - - + + Select the controls for your helicopter - + Multirotor MultiCopter - + Select the control channels for your multirotor - + Model Options Modell Optionen - + Select additional options Auswahl von zusätzlichen Optionen - + Save Changes Speichere die Kanäle - + Manually check the direction of each control surface and reverse any channels that make controls move in the wrong direction. Remove the propeller/propellers before you try to control your model for the first time.<br>Please note that continuing removes all old model settings! - + Enter a name for your model and select model type. Modellname eingeben und Modelltype auswählen - + Select the receiver channel that is connected to your ESC or throttle servo.<br><br>Throttle - Spektrum: CH1, Futaba: CH3 - + Most aircraft have a main wing and a tail with control surfaces. Flying wings and delta winged aircraft only have a single wing. The main control surface on a standard wing controls the roll of the aircraft. This surface is called an aileron.<br>The control surface of a delta wing controls both roll and pitch. This surface is called an elevon. - + Models use one or two channels to control the ailerons.<br>A so called Y-cable can be used to connect a single receiver channel to two separate aileron servos. If your servos are connected by a Y-cable you should select the single-servo option.<br><br>Aileron - Spektrum: CH2, Futaba: CH1 - + This wizard assumes that your flaps are controlled by a switch. If your flaps are controlled by a potentiometer you can change that manually later. - + Air brakes are used to reduce the speed of advanced sail planes.<br>They are very uncommon on other types of planes. - + Models use two channels to control the elevons.<br>Select these two channels - + Select the receiver channel that is connected to your rudder.<br><br>Rudder - Spektrum: CH4, Futaba: CH4 - + Select the tail type of your plane. - + Select the Rudder and Elevator channels.<br><br>Rudder - Spektrum: CH4, Futaba: CH4<br>Elevator - Spektrum: CH3, Futaba: CH2 - + Select the Elevator channel.<br><br>Elevator - Spektrum: CH3, Futaba: CH2 - - - - - - - + + + + + + + TBD. TBS. - + Select the control channels for your multirotor.<br><br>Throttle - Spektrum: CH1, Futaba: CH3<br>Yaw - Spektrum: CH4, Futaba: CH4<br>Pitch - Spektrum: CH3, Futaba: CH2<br>Roll - Spektrum: CH2, Futaba: CH1 - + There is no help available for the current page. - + Model Wizard Help Modell Wizard Hilfe @@ -10355,37 +12018,37 @@ umgedreht und ist dann vorne WizardPrinter - + Plane Flugmodell - + Multicopter Multikopter - + Helicopter Hubschrauber - + Model Name: Model Name: - + Model Type: Model Typ: - + Options: Optionen: - + Channel %1: Kanal %1: @@ -10393,7 +12056,7 @@ umgedreht und ist dann vorne burnConfigDialog - + AVRDUDE Configuration Einstellung AVRDUDE @@ -10555,39 +12218,39 @@ Please only use this if you know what you are doing. There are no error checks sam-ba serialer port - + DFU-UTIL Configuration DFU-UTIL Konfiguration - + SAM-BA Configuration SAM-BA Konfiguration - - - + + + Select Location Wähle Speicherort - + List available programmers Liste der möglichen Programmiergeräte - + Avrdude help AVRDude Hilfe - + Companion Companion - + <b><u>WARNING!</u></b><br>Normally CPU type is automatically selected according to the chosen firmware.<br>If you change the CPU type the resulting eeprom could be inconsistent. @@ -10650,75 +12313,75 @@ Please only use this if you know what you are doing. There are no error checks ... - - - - + + + + Error Fehler - + Open Firmware File Öffne Firmware Datei - + Can not load embedded image from firmware file %1. - + Open Image to load Bilddatei öffnen - + Images (%1) Bilder (%1) - + Cannot load the image file %1. - + Cannot load profile image %1. - + Cannot load the library image %1. - + File Saved Datei gespeichert - + The image was saved to the file %1 - + Image Refresh Error - + Failed to refresh image from file %1 - + File Save Error Datei speichern fehlerhaft - + Failed to write image to %1 @@ -10731,17 +12394,17 @@ Please only use this if you know what you are doing. There are no error checks Herunterladen: - + Unable to save the file %1: %2. Kann Datei %1:%2 nicht abspeichern. - + Companion Companion - + Download failed: %1. Herunterladen fehlgeschlagen: %1. @@ -10754,226 +12417,155 @@ Please only use this if you know what you are doing. There are no error checks Joystick konfigurieren - + Ch2 Ch2 - - - - - - - - - Not Assigned - Nicht zugewiesen - - - - - - - - - - - Right Vertical - Rechts Vertikal - - - - - - - - - - - Right Horizontal - Rechts Horizontal - - - - - - - - - - - Left Vertical - Links Vertikal - - - - - - - - - - - Left Horizontal - Links Horizontal - - - - - - - - - - - P1 - P1 - - - - - - - - - - - P2 - P2 - - - - - - - - - - - P3/LS - P3/LS - - - - - - - - - - - RS - RS - - - + Ch1 Ch1 - + Ch4 Ch4 - + Ch6 Ch6 - + Ch3 Ch3 - + Ch5 Ch5 - + Ch7 Ch7 - + Ch8 Ch8 - + Instructions Anweisungen - + + Enable + + + + Cancel abbrechen - + + Back + + + + + Start + Start + + + Next weiter - + Ok Ok - - Move sticks and pots in every direction making full movement -Press next when finished - Bewege Knüppel und Potis bis zu den Anschlägen in jeweils beide Richtungen. Wähle weiter wenn fertig + + Not Assigned + - - + + Stick + + + + + Knob/Slider %1 + + + + + No joysticks found + Kein Joystick gefunden + + + Error Fehler - + Cannot open joystick. kann Joystick nicht öffnen. - + + Press the Start button to start the stick range calibration procedure. +You may change the channel assignments or inversion at any time. + + + + + Move sticks and pots in every direction making full movement +Press Next when finished + + + + Place sticks and pots in middle position. -Press next when done - Stelle alle Knüppel und Potis in die Mitte. Wähle weiter wenn fertig +Press Next when done + - + Map joystick channels to controls using comboboxes. -Press next when done +Press Next when done. - - Check inversion checkbox to get maximum at top-right position. -Press next when done + + Check inversion checkbox to if necessary to reverse direction. +Press Next when done. - - Press ok to save configuration -Press cancel to abort joystick calibration + + Press OK to save configuration +Press Cancel to abort joystick calibration without saving. - - Duplicated stick assignment - + + Warning + Warnung - - - mdiChild - - Simulate Tx - Sender Simulation + + Calibration not complete, save anyway? + diff --git a/companion/src/translations/companion_en.ts b/companion/src/translations/companion_en.ts index e23bd7467..a1b639e8b 100644 --- a/companion/src/translations/companion_en.ts +++ b/companion/src/translations/companion_en.ts @@ -34,7 +34,7 @@ No - + No @@ -775,22 +775,22 @@ Mode 4: CurveGroup - + Diff - + Expo - + Func - + Curve @@ -952,87 +952,87 @@ Mode 4: CustomFunctionsPanel - + Switch - + Action - + Parameters - + Enable - + SF%1 - + GF%1 - + ON - + Error - + Unable to find sound file %1! - + &Copy - + Ctrl+C - + &Cut - + Ctrl+X - + &Paste - + Ctrl+V - + &Delete - + Delete @@ -1321,7 +1321,7 @@ If blank then the input is considered to be "ON" all the time. No - + No @@ -1364,22 +1364,22 @@ If blank then the input is considered to be "ON" all the time. - + Click to access popup menu - + Clear All - + Set All - + Invert All @@ -1456,7 +1456,7 @@ May be different from firmware language No - + No @@ -1917,32 +1917,47 @@ Please use ZADIG to properly install the driver. FlightModePanel - + Rotary Encoder %1 - + + Name + + + + + Value source + + + + + Value + + + + GVAR%1 - + Popup enabled - + &Clear - + Clear - + Clear all current Flight Mode properties? @@ -1950,17 +1965,17 @@ Please use ZADIG to properly install the driver. FlightModesPanel - + Flight Mode %1 - + (%1) - + (default) @@ -2943,7 +2958,7 @@ Are you sure ? No - + No @@ -3480,88 +3495,89 @@ Are you sure ? LogicalSwitchesPanel - + Function - + V1 - + V2 - + AND Switch - + Duration - + Delay - + L%1 - - + + (instant) - + + (infinite) - + &Copy - + Ctrl+C - + &Cut - + Ctrl+X - + &Paste - + Ctrl+V - + &Delete - + Delete @@ -3740,122 +3756,122 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt MainWindow - - + + File loaded - + Display previous warning again at startup ? - + Checking for updates - + Unable to check for updates. - + A new version of Companion is available (version %1)<br>Would you like to download it? - - + + Save As - + Executable (*.exe) - + New release available - + A new release of Companion is available, please check the OpenTX website! - - + + No updates available at this time. - + Would you like to launch the installer? - - + + Error - + Error opening file %1: %2. - + Not enough flash available on this board for all the selected options - + Compilation server temporary failure, try later - + Compilation server too busy, try later - + Compilation error - + Invalid firmware - + Invalid board - + Invalid language - + Unknown server failure, try later - + Do you want to write the firmware to the radio now ? - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -3864,31 +3880,31 @@ We recommend you view the release notes using the button below to learn about an - - + + Yes - - + + No - - - - - - Release Notes - + No + Release Notes + + + + + Do you want to download release %1 now ? - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -3899,720 +3915,625 @@ We recommend you view the release notes using the button below to learn about an - + Ignore this release %1? - - - + + + Companion - - The selected language will be used the next time you start Companion. - - - - + The new theme will be loaded the next time you start Companion. - + The icon size will be used the next time you start Companion. - - + + Open Models and Settings file - - + + File saved - - + + Synchronize SD - + Firmware updates - + Current firmware does not provide release notes informations. - - + + Read Firmware from Radio - - + + Read Models and Settings from Radio - + Models and Settings read - - + + This function is not yet implemented - + Save Radio Backup to File - + Read Radio Firmware to File - + OpenTX Home Page: <a href='%1'>%1</a> - + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> - + Copyright OpenTX Team - + About Companion - + OpenTX Companion %1 - Radio: %2 - Profile: %3 - + New - + Create a new Models and Settings file - + Open... - + Save - - + + Save Models and Settings file - + Save As... - + Exit - + Exit the application - + Cut Model - + Cut current model to the clipboard - + Copy Model - + Copy current model to the clipboard - + Paste Model - + Paste model from clipboard - + Classical - + The classic companion9x icon theme - + Yerico - + Yellow round honey sweet icon theme - + Monochrome - + A monochrome black icon theme - + MonoWhite - + A monochrome white icon theme - + MonoBlue - + A monochrome blue icon theme - + Small - + Use small toolbar icons - + Normal - + Use normal size toolbar icons - + Big - + Use big toolbar icons - + Huge - + Use huge toolbar icons - + System language - - Use system language in menus - - - - - Czech - - - - - Use Czech in menus - - - - - German - - - - - Use German in menus - - - - - English - - - - - Use English in menus - - - - - Finnish - - - - - Use Finnish in menus - - - - - French - - - - - Use French in menus - - - - - Italian - - - - - Use Italian in menus - - - - - Polish - - - - - Use Polish in menus - - - - - Spanish - - - - - Use Spanish in menus - - - - - Swedish - - - - - Use Swedish in menus - - - - - Chinese - - - - - Use Chinese in menus - - - - + About... - + Show the application's About box - + Print... - + Print current model - + Simulate... - + Simulate current model - + Alt+S - + Load Backup... - + Load backup from file - + View Log File... - + Open and view log file - + Settings... - + Edit Settings - + Download... - + Download firmware and voice files - + Check for Updates... - + Check OpenTX and Companion updates - + Companion Changes... - + Show Companion change log - + Firmware Changes... - + Show firmware change log - + Compare Models... - + Compare models - + Edit Radio Splash Image... - + Edit the splash image of your Radio - + List programmers... - + List available programmers - + Fuses... - + Show fuses dialog - + Read firmware from Radio - + Write Firmware to Radio - + Write firmware to Radio - + Add Radio Profile - + Create a new Radio Setting Profile - + Manuals and other Documents - + Open the OpenTX document page in a web browser - + Write Models and Settings To Radio - + Write Models and Settings to Radio - + Read Models and Settings From Radio - + Configure Communications... - + Configure software for communicating with the Radio - + Write Backup to Radio - + Write Backup from file to Radio - + Backup Radio to File - + Save a complete backup file of all settings and model data in the Radio - + Contributors... - + A tribute to those who have contributed to OpenTX and Companion - + SD card synchronization - + + Use default system language. + + + + + Use %1 language (some translations may not be complete). + + + + Recent Files - + Set Menu Language - + Set Icon Theme - + Set Icon Size - - + + File - - + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + + + + + Edit - + Settings - + Read/Write - - + + Help - - + + Radio Profile - + Recent Models+Settings - + Show recent Models+Settings documents - + Show the list of radio profiles - + Write - + Ready - + %2 - + New Radio @@ -5001,7 +4922,7 @@ Setting this value will cause a beep to be emmitted when this value is active. No - + No @@ -5071,17 +4992,17 @@ If blank then the mix is considered to be "ON" all the time. - + Clear All - + Set All - + Invert All @@ -5284,308 +5205,308 @@ If blank then the mix is considered to be "ON" all the time. ModelPrinter - + %1 bytes - + CH%1 - + Exponential - + Extra Fine - + Fine - + Medium - + Coarse - + Unknown - + Enabled - + Disabled - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) - + %1, Channels(%2-%3) - + Receiver number(%1) - + radio Protocol %1, subType %2, option value %3 - + Slave/Jack - + Master/SBUS Module - + Master/CPPM Module - + Master/SBUS in battery compartment - + Master/Jack - + 90 - + 120 - + 120X - + 140 - - + + Off - + Rudder - + Elevator - + Throttle - + Aileron - + Name(%1) - + Persistent - + MinuteBeep - + CountDown(Beeps) - + CountDown(Voice) - + CountDown(Haptic) - - - - + + + + FM%1 - + FM%1%2 - + FM%1+%2 - + [I%1] - + Input%1 - + Weight - + Switch - - + + NoTrim - - + + Offset(%1) - + Weight(%1) - + Switch(%1) - + No DR/Expo - + Delay(u%1:d%2) - + Slow(u%1:d%2) - + Warn(%1) - + Disabled in all flight modes - + Flight modes(%1) - + Flight mode(%1) - + Edge(%1, [%2:%3]) - + instant - + Sticky(%1, %2) - + Timer(%1, %2) - + Duration(%1s) - + Delay(%1s) - + Custom - + Standard @@ -5621,7 +5542,7 @@ If blank then the mix is considered to be "ON" all the time. ModelsListWidget - + No free slot available, cannot duplicate @@ -5829,43 +5750,43 @@ If blank then the mix is considered to be "ON" all the time. ModulePanel - + Trainer Port - + Internal Radio System - + External Radio Module - - + + Radio System - + Extra Radio System - + Value - + Hold - + No Pulse @@ -6127,6 +6048,49 @@ If blank then the mix is considered to be "ON" all the time. + + Multiprotocols + + + Subtype + + + + + Video TX frequency + + + + + C2500 frequency fine tune + + + + + Telemetry + + + + + Radio output power + + + + + Servo output frequency + + + + + Option value + + + + + DEFAULT + + + MultirotorPage @@ -6287,14 +6251,14 @@ If blank then the mix is considered to be "ON" all the time. - + -GV%1 - + GV%1 @@ -6461,14 +6425,14 @@ If blank then the mix is considered to be "ON" all the time. - + REa - + REb @@ -6775,7 +6739,7 @@ If blank then the mix is considered to be "ON" all the time. - + ---- @@ -6816,136 +6780,136 @@ If blank then the mix is considered to be "ON" all the time. - + FM0 - + FM1 - + FM2 - + FM3 - + FM4 - + FM5 - + FM6 - + FM7 - + FM8 - + RudTrim Left - + RudTrim Right - + EleTrim Down - + EleTrim Up - + ThrTrim Down - + ThrTrim Up - + AilTrim Left - + AilTrim Right - + Trim 5 Down - + Trim 5 Up - + Trim 6 Down - + Trim 6 Up - + OFF - + ON - + THs - + TH% - + THt @@ -6986,8 +6950,8 @@ If blank then the mix is considered to be "ON" all the time. - - + + --- @@ -7387,520 +7351,351 @@ If blank then the mix is considered to be "ON" all the time. - - + + Rud - - + + Ele - - + + Thr - - + + Ail - - + + P1 - - + + P2 - - + + P3 - + F1 - + F2 - + F3 - + F4 - - - + + + S1 - - - + + + S2 - - - + + + LS - - - + + + RS - + S3 - + 6P - + L1 - + L2 - + JSx - + JSy - + Channel values displayed in us - + No OverrideCH functions available - + Possibility to enable FAI MODE (no telemetry) at field - + FAI MODE (no telemetry) always enabled - + Support for the DIY-Multiprotocol-TX-Module - + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 - + Disable HELI menu and cyclic mix support - + Disable Global variables - + Support for Lua model scripts - + Enable Lua compiler - + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) - + Instead of Joystick emulation, USB connection is Command Line Interface - - - Adds mixers output view to the CHANNELS MONITOR screen, pressing [ENT] switches between the views - - - - - + + Support for PPM internal module hack - - - - - - - - - - - + + + + + + + + + + + Use alternative SQT5 font - + ST7565P LCD or compatible - + ST7565R LCD or compatible - + ERC12864FSF LCD - + ST7920 LCD - + KS108 LCD - + Support for frsky telemetry mod - + Support for telemetry easy board - - + + Support for jeti telemetry mod - - + + Support for receiving ardupilot data - - + + Support for receiving NMEA data - - + + Support for MAVLINK devices - + Rotary Encoder use in menus navigation - - - - - - - + + + + + + + Pots use in menus navigation - - - - - + + + + + Support for DSM2 modules - + Support for DSM2 modules using ppm instead of true serial - + FrSky Taranis X9D+ - + FrSky Taranis X9D - + Haptic module installed - + FrSky Taranis X9E - + Confirmation before radio shutdown - + Horus gimbals installed (Hall sensors) - + FrSky Taranis X7 - + FrSky Horus - + Use ONLY with first DEV pcb version - + Turnigy 9XR-PRO - - - - - Enable HELI menu and cyclic mix support - - - - - - - - - - - - - Enable TEMPLATES menu - - - - - - - - - - - - - No flight modes - - - - - - - - - - - - - Global variables - - - - - - - - - - - - - In model setup menus automatically set source by moving the control - - - - - - - - - - - - - In model setup menus automatically set switch by moving the control - - - - - - - - - - - No graphical check boxes and sliders - - - - - - - - - - - - - Battery graph - - - - - - - - - - - - - Don't use bold font for highlighting active items - - - - - - - Bluetooth interface - - - - - Turnigy 9XR with m128 chip - - - - - - - - - - Enable heli menu and cyclic mix support - - - - - - - - No splash screen - - - - - - - - - - Disable curves menus - - - - - - - - - Support for radio modified with regular speaker - - - - - - - - - - Used if you have modified your radio with voice mode + + + Enable HELI menu and cyclic mix support @@ -7908,8 +7703,140 @@ If blank then the mix is considered to be "ON" all the time. - - Used if you have modified your radio with haptic mode + + + Enable TEMPLATES menu + + + + + + + + + + + + + No flight modes + + + + + WTV20 voice module + + + + + JQ6500 voice module + + + + + + + + + + + + + Global variables + + + + + + + + + + + + + In model setup menus automatically set source by moving the control + + + + + + + + + + + + + In model setup menus automatically set switch by moving the control + + + + + + + + + + + + + No graphical check boxes and sliders + + + + + + + + + + + + + Battery graph + + + + + + + + + + + + + Don't use bold font for highlighting active items + + + + + + + Bluetooth interface + + + + + Turnigy 9XR with m128 chip + + + + + + + + + + Enable heli menu and cyclic mix support + + + + + + + + No splash screen @@ -7917,9 +7844,18 @@ If blank then the mix is considered to be "ON" all the time. - - - PPM center adjustment in limits + + + Disable curves menus + + + + + + + + + Support for radio modified with regular speaker @@ -7927,143 +7863,171 @@ If blank then the mix is considered to be "ON" all the time. - - + + Used if you have modified your radio with voice mode + + + + + + + + + Used if you have modified your radio with haptic mode + + + + + + + + + + PPM center adjustment in limits + + + + + + + + + Symetrical Limits - - - - + + + + Enable the throttle trace in Statistics - - - - - + + + + + EEprom write Progress bar - - - - - - + + + + + + Imperial units - + Turnigy 9XR - - + + No Winged Shadow How High support - - + + No vario support - - + + No GPS support - - + + No gauges in the custom telemetry screen - - + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) - + 9X with stock board - - + + SmartieParts 2.2 Backlight support - - - - - - + + + + + + Enable resetting values by pressing up and down at the same time - + EEprom write progress bar - + Allow compensating for offset errors in FrSky FAS current sensors - + 9X with stock board and m128 chip - + 9X with AR9X board - + 9X with Sky9x board - + 9X with Gruvin9x board - - + + Support for SD memory card - - + + Support of FrSky PXX protocol - + DIY MEGA2560 radio - + Power management by soft-off circuitry @@ -8160,7 +8124,7 @@ If blank then the mix is considered to be "ON" all the time. No - + No @@ -8188,139 +8152,139 @@ If blank then the mix is considered to be "ON" all the time. - + Rud Trim - + Ele Trim - + Thr Trim - + Ail Trim - + Rot Enc - + !Flight mode %1 - + Flight mode %1 - + Own value - + Flight mode %1 value - + -GV%1 (%2) - + GV%1 (%2) - + Yellow - + Orange - + Red - + Winged Shadow How High - + Winged Shadow How High (not supported) - + FrSky Sensor Hub - + None - + Imperial - + Metric - + Warning - + Simulator for this firmware is not yet available - - + + Uknown error during Simulator startup. - + Simulator Error - + Data Load Error - + Error occurred while starting simulator. - - + + @@ -8328,12 +8292,12 @@ If blank then the mix is considered to be "ON" all the time. - + No SD directory configured! - + No Radio connected! @@ -8343,74 +8307,75 @@ If blank then the mix is considered to be "ON" all the time. - + Played once, not during startup - + No repeat - + %1s - + Value - + Source - + GVAR - + Increment - + Trim disabled - + Own Trim - + Use Trim from Flight mode %1 - + Use Trim from Flight mode %1 + Own Trim as an offset - + THR - + -%1 - - + + Models + Translators do NOT use accent for this, this is the default category name on Horus. @@ -8440,12 +8405,12 @@ If blank then the mix is considered to be "ON" all the time. - + Positive - + Negative @@ -8477,85 +8442,85 @@ If blank then the mix is considered to be "ON" all the time. - + Select a data file - + Select Data Directory - + Select SD Card Image Folder - + Available profiles: - + ID: - + Name: - + Available radios: - + WARNING: couldn't initialize SDL: %1 - + ERROR: No simulator libraries available. - + Radio profile ID or Name to use for simulator. - + Radio type to simulate (usually defined in profile). - + show this help text - + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] - + Options: - + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. Profile ID: [%1]; Radio ID: [%2]; Data File: [%3] - + ERROR: Radio profile or simulator firmware not found. Profile ID: [%1]; Radio ID: [%2] @@ -8929,6 +8894,29 @@ s + + RawSwitch + + + ↑ + + + + + ↓ + + + + + - + + + + + ! + + + ReleaseNotesDialog @@ -8950,7 +8938,7 @@ s No - + No @@ -9132,7 +9120,7 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi SetupPanel - + Timer %1 @@ -9148,204 +9136,419 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi SimulatedUIWidget - + + Rotary encoder click + + + + + Take Screenshot + + + + screenshot Simulator LCD screenshot file name prefix - - - ENTER - - - - - PG-UP - - - - - PG-DN - - - - - DEL - - - - - BKSP - - - - - ESC - - - - - INS - - - - - <font size=+3>+</font> - - - - - <font size=+3>-</font> - - - - - <font size=+3>&larr;</font> - - - - - <font size=+3>&rarr;</font> - - - - - <font size=+3>&uarr;</font> - - - - - <font size=+3>&darr;</font> - - - - - <font size=+3>&#x2686;</font> - - - - - <font size=+3>&#x21b6;</font> - - - - - <font size=+3>&#x21b7;</font> - - - - - <font size=+3>&#x21c6;</font> - - - - - - <font size=+3>&#x21d3;</font> - - - - - <font size=+3>&#x21d1;</font> - - - - - <font size=+3>&#x21d5;</font> - - - - - <img src='qrc:/images/simulator/icons/svg/mouse.svg' width=20 height=18 /> - - - - - <img src='qrc:/images/simulator/icons/svg/arrow_click.svg' width=18 height=18 /> - - - - - <pre>[ MENU ]</pre> - - - - - <pre>[ PAGE ]</pre> - - - - - <pre>[ EXIT ]</pre> - - - - - <pre>[ ENT ]</pre> - - - - - <pre>[ UP ]</pre> - - - - - <pre>[ DN ]</pre> - - - - - <pre>[ <font size=+2>+</font> ]</pre> - - - - - <pre>[ <font size=+2>-</font> ]</pre> - - - - - <pre>[ PgUp ]</pre> - - - - - <pre>[ PgDn ]</pre> - - - - - <pre>[ MDL ]</pre> - - - - - <pre>[ RTN ]</pre> - - - - - <pre>[ SYS ]</pre> - - - - - <pre>[ TELE ]</pre> - - - - - <font size=+3>&#x2261;</font> - - SimulatedUIWidget9X - - - | + + UP/PG-UP + + + + + [ UP ] + + + + + DN/PG-DN + + + + + [ DN ] + + + + + RIGHT/+ + + + + + [ + ] + + + + + LEFT/- + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + [ UP ]/[ DN ] or Rotary Sel. + + + + + SimulatedUIWidgetX12 + + + PG-UP + + + + + [ PgUp ] + + + + + PG-DN + + + + + [ PgDn ] + + + + + UP + + + + + [ MDL ] + + + + + DN/DEL/BKSP + + + + + [ RTN ] + + + + + LEFT + + + + + [ SYS ] + + + + + RIGHT + + + + + [ TELE ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/X + + + + + Rotary UP + + + + + +/C + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX7 + + + Taranis X7 Simulator + + + + + PG-UP + + + + + [ PAGE ] + + + + + PG-DN + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX9 + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + +/UP + + + + + [ + ] + + + + + -/DN + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ ENT ] + + + + + WHEEL/PAD SCRL + + + + + [ + ]/[ - ] + + + + + SimulatedUIWidgetX9E + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press @@ -9502,74 +9705,67 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi - + ERROR: Failed to create simulator interface, possibly missing or bad library. - + Alt+T - + Radio Outputs - + F2 - + Telemetry Simulator - + F4 - + Trainer Simulator - + F5 - + Debug Output - + F6 - - <b>Simulator Controls:</b> + + Simulator Controls: + + + + + <tr><th>Key/Mouse</td><th>Action</td></tr> - <tr><th>Key/Mouse</th><th>Action</th></tr> - note: must match html layout of each table row (keyTemplate). - - - - - <tr><td><kbd>%1</kbd></td><td>%2</td></tr> - note: must match html layout of help text table header. - - - - Simulator Help @@ -9689,7 +9885,7 @@ The default is configured in the chosen Radio Profile. - + All files (*.*) @@ -9702,73 +9898,68 @@ The default is configured in the chosen Radio Profile. - + Radio Simulator (%1) - + Could not determine startup data source. - + Could not load data, possibly wrong format. - + Data Load Error - + Invalid startup data provided. Plese specify a proper file/path. - + Simulator Startup Error - + Error saving data: could open file for writing: '%1' - + Error saving data: could not get data from simulator interface. - + An unexpected error occurred while attempting to save radio data to file '%1'. - + Data Save Error - + Warning - + Cannot open joystick, joystick disabled - - Radio firmware error: %1 - - - - - - Flight Mode %1 (#%2) + + Firmware %1 error: %2 @@ -10234,99 +10425,99 @@ The default is configured in the chosen Radio Profile. TelemetryPanel - + Telemetry screen %1 - + FrSky S.PORT - + FrSky D - + FrSky D (cable) - + Low Alarm - + Critical Alarm - + Winged Shadow How High - + Winged Shadow How High (not supported) - + Alti - + Alti+ - + VSpeed - - - + + + A1 - - - - A2 - - - - - - A3 - - - + - A4 + A2 - FAS + A3 + + A4 + + + + + + FAS + + + + Cells - + --- @@ -10609,22 +10800,22 @@ The default is configured in the chosen Radio Profile. TelemetrySensorPanel - + Lowest - + Cell %1 - + Highest - + Delta @@ -10940,17 +11131,17 @@ hh:mm:ss - + Log File - + LOG Files (*.csv) - + ERROR - invalid file @@ -11182,7 +11373,7 @@ hh:mm:ss No - + No @@ -11206,37 +11397,37 @@ hh:mm:ss TimerPanel - + Silent - + Beeps - + Voice - + Haptic - + Not persistent - + Persistent (flight) - + Persistent (manual reset) @@ -11400,42 +11591,42 @@ hh:mm:ss VirtualJoystickWidget - + Hld Y - + Hold Vertical stick position. - + Fix Y - + Prevent Vertical movement of stick. - + Fix X - + Prevent Horizontal movement of stick. - + Hld X - + Hold Horizontal stick position. @@ -11943,29 +12134,29 @@ m2560 for v4.1 boards - - - + + + Select Location - + List available programmers - + Avrdude help - + Companion - + <b><u>WARNING!</u></b><br>Normally CPU type is automatically selected according to the chosen firmware.<br>If you change the CPU type the resulting eeprom could be inconsistent. diff --git a/companion/src/translations/companion_es.ts b/companion/src/translations/companion_es.ts index 423fc5640..93f12875d 100644 --- a/companion/src/translations/companion_es.ts +++ b/companion/src/translations/companion_es.ts @@ -1,30 +1,30 @@ - + AileronsPage - + No No - + Yes, controlled by a single channel Si, controlado por un único canal - + Yes, controlled by two channels Si, controlado por dos canales - + <br>First Aileron Channel: <br>Canal Primer Alerón: - + Second Aileron Channel: Canal Segundo Alerón: @@ -32,27 +32,27 @@ AirbrakesPage - + No No - + Yes, controlled by a single channel Si, controlado por un único canal - + Yes, controlled by two channels Si, controlado por dos canales - + <br>First Airbrake Channel: <br>Primer Canal Aerofreno: - + Second Airbrake Channel: Segundo Canal Aerofreno: @@ -69,15 +69,6 @@ Radio Profile Perfil de Radio - - - - - - - Open Folder - Abrir Carpeta - Default Channel Order @@ -315,6 +306,20 @@ Modo 4: A T E R A T E R + + + + + + + Select Folder + + + + + Select Executable + + Use OpenTX firmware nightly builds @@ -423,11 +428,6 @@ Puede ser diferente del lenguaje del firmware Files to keep Archivos a mantener - - - Find Executable - Encontrar ejecutable - Google Earth Executable @@ -524,498 +524,149 @@ Puede ser diferente del lenguaje del firmware Recordar los valores de los switch en el simulador - + My Radio Mi Radio - + Select your snapshot folder Selecciona tu carpeta de capturas - - + + No joysticks found No se han encopntrado joysticks - + EMPTY: No radio settings stored in profile VACIO: No se han guardado ajustes en el perfil de tu radio - + AVAILABLE: Radio settings of unknown age DISPONIBLE:Ajustes de radio de tiempo desconocido - + AVAILABLE: Radio settings stored %1 DISPONIBLE: Ajustes de radio guardados %1 - + Select your library folder Selecciona tu carpeta de una carpeta - - + + Select your Models and Settings backup folder Selecciona la carpeta de seguridad de tus modelos y ajustes - + Select Google Earth executable Selecciona el ejecutable de Google Earth - + Select the folder replicating your SD structure Selecciona la carpeta que replica la structura de tu tarjeta SD - + Not possible to remove profile No es posible eliminar el perfil - + The default profile can not be removed. El perfil prederterminado no se puede eliminar. - + Open Image to load Abrir imagen para cargar - + Images (%1) Imagenes (%1) - - Calibration - - - Form - - - - - SQ - - - - - SR - - - - - LS2 - - - - - SP - - - - - SO - - - - - S4 - - - - - RS - - - - - SB - - - - - Serial Port - Puerto Serie - - - - - - - - - - - - - Beeper volume - -0 - Quiet. No beeps at all. -1 - No Keys. Normal beeps but menu keys do not beep. -2 - Normal. -3 - Loud. -4 - Extra loud. - Volumen Beeper - -0 - Silencio. Ningun tipo de beep. -1 - Sin teclas. Los beeps suenan normal pero las teclas de menu no sonarán. -2 - Normal. -3 - Alto. -4 - Extra Alto. - - - - OFF - - - - - S-Port Mirror - S-Port Espejo - - - - Telemetry - Telemetría - - - - SBUS Trainer - - - - - Debug - Depurar - - - - Rud - Rud - - - - - Mid value - Valor medio - - - - Pot. 4 - - - - - Pot. 3 - - - - - Pot. 2 - - - - - Pot. 1 - - - - - PPM 1 - PPM 1 - - - - Stick 3 - - - - - - Negative span - Amplitud negativa - - - - - Positive span - Amplitud positiva - - - - Stick 1 - - - - - PPM 2 - PPM 2 - - - - Stick 2 - - - - - Stick 4 - - - - - v - - - - - PPM Multiplier - Multiplicador PPM - - - - PPM 3 - PPM 3 - - - - PPM 4 - PPM 4 - - - - Battery Offset - - - - - Current Offset - - - - - S1 - - - - - S2 - - - - - S3 - - - - - SA - - - - - Ele - Ele - - - - Ail - Ail - - - - Thr - Thr - - - - SC - - - - - LS - LS - - - - SD - - - - - SE - - - - - SF - SF - - - - SG - - - - - SH - - - - - SI - - - - - SJ - - - - - SK - - - - - SL - - - - - SM - - - - - SN - - - - - RS2 - - - - - Bluetooth - - - - - CalibrationPanel - - - - - None - Ninguno - - - - 2 Positions Toggle - - - - - 2 Positions - - - - - 3 Positions - - - - - Pot with detent - - - - - Multipos switch - - - - - Pot without detent - - - - - Slider with detent - - - Channels - + Name Nombre - + Min Min - + Max Max - + Subtrim Subtrim - + Direction Dirección - + Curve Curva - + PPM Center Centro PPM - + Linear Subtrim Subtrim lineal - - Channel %1 - Canal %1 + + CH%1 + - + --- --- - + INV INV + + CompanionMacros + + + files + + + + + Radio and Models settings + + + CompareDialog @@ -1049,17 +700,17 @@ Puede ser diferente del lenguaje del firmware Imprimir a archivo - + No name Sin nombre - + Print Document Imprimir documento - + Select PDF output file Seleccionar archivo de salida PDF @@ -1067,7 +718,7 @@ Puede ser diferente del lenguaje del firmware ConclusionPage - + OK, I understand. OK, Entiendo. @@ -1075,42 +726,42 @@ Puede ser diferente del lenguaje del firmware ContributorsDialog - + OpenTX Contributors - + Main Developers - + Other contributors - + Companies and projects who have donated to OpenTX - + People who have donated to OpenTX - + Honors go to Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) Los honores van a Rafal Tomczak (RadioClone), Thomas Husterer (th9x) y Erez Raviv (er9x y eePe) - + OpenTX Blacklist - + monthly @@ -1118,24 +769,24 @@ Puede ser diferente del lenguaje del firmware CopyProcess - - - + + + Error Error - + Write error Error escritura - + Cannot write %1 (reason: %2) - + Cannot open %1 (reason: %2) @@ -1143,22 +794,22 @@ Puede ser diferente del lenguaje del firmware CurveGroup - + Diff Diff - + Expo Expo - + Func Func - + Curve Curva @@ -1247,72 +898,72 @@ Puede ser diferente del lenguaje del firmware Nombre de la curva - + Curve %1 Curva %1 - + %1 points %1 puntos - + Linear Lineal - + Single Expo Expo Unico - + Symmetrical f(x)=-f(-x) Simetricas f(x)=-f(-x) - + Symmetrical f(x)=f(-x) Simetricas f(x)=f(-x) - + Copy - + Paste - + Clear - + Clear all curves - + Are you sure you want to reset curve %1? - + Are you sure you want to reset all curves? - + Editing curve %1 Edición de curva %1 - + Not enough free points in EEPROM to store the curve. No hay suficientes puntos en el EEPROM para guardar la curva. @@ -1320,87 +971,87 @@ Puede ser diferente del lenguaje del firmware CustomFunctionsPanel - + Switch Cambiar - + Action Acción - + Parameters Parámetros - + Enable Activar - + SF%1 SF%1 - + GF%1 - + ON ON - + Error Error - + Unable to find sound file %1! ¡No se ha encontrado el archivo de sonido %1! - + &Delete &Borrar - + Delete Borrar - + &Copy &Copiar - + Ctrl+C Ctrl+C - + &Cut C&ortar - + Ctrl+X Ctrl+X - + &Paste &Pegar - + Ctrl+V Ctrl+V @@ -1408,22 +1059,22 @@ Puede ser diferente del lenguaje del firmware CyclicPage - + 90 90 - + 120 120 - + 120x 120x - + 140 140 @@ -1431,98 +1082,174 @@ Puede ser diferente del lenguaje del firmware DebugOutput - + Debug Output + + + <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> + + + + + Filter: + + + + + <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> +To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> + + + + + Buffer: + + + + + Number of lines to keep in display. + + + + + Filter &Help + + + + + Show information about using the filter. + + + + + Word &Wrap + + + + + Toggle word wrapping on/off. + + + + + &Clear + + + + + Clear the output window of all text. + + + + + Enable &Filter + + + + + Turn the filter on/off. + + + + + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> + + + + + Debug Console Filter Help + + EepromInterface - + Possible causes for this: - + - Eeprom is from a newer version of OpenTX - + - Eeprom is not from OpenTX - + - Eeprom is not from Th9X - + - Eeprom is not from Gruvin9X - + - Eeprom is not from ErSky9X - + - Eeprom is not from Er9X - + - Eeprom size is invalid - + - Eeprom file system is invalid - + - Eeprom is from a unknown board - + - Eeprom is from the wrong board - + - Eeprom backup not supported - + - Something that couldn't be guessed, sorry - + Warning: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - + Warnings! @@ -1530,12 +1257,12 @@ Puede ser diferente del lenguaje del firmware ElevonsPage - + <br>First Elevon Channel: <br>Primer canal de Elevon: - + Second Elevon Channel: Segundo canal de Elevon: @@ -1652,30 +1379,50 @@ Si está en blanco entonces las entradas son consideradas como ON todo el tiempo TODO - + Edit %1 Editar %1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + FblPage - + Throttle Channel: Canal de Acelerador: - + Yaw Channel: Canal de Yaw: - + Pitch Channel: Canal de pitch: - + Roll Channel: Canal de roll: @@ -1728,27 +1475,27 @@ Puede ser diferente del lenguaje del firmware FlapsPage - + No No - + Yes, controlled by a single channel Si, controlado por un único canal - + Yes, controlled by two channels Si, controlado por dos canales - + <br>First Flap Channel: <br>Canal del primer Flap: - + Second Flap Channel: Canal del segundo Flap: @@ -1757,7 +1504,7 @@ Puede ser diferente del lenguaje del firmware FlashEEpromDialog - + Write Models and Settings to Radio Escribir Modelos y Ajustes a la Radio @@ -1773,7 +1520,6 @@ Puede ser diferente del lenguaje del firmware - Allows Companion to write to older version of the firmware Permitir a Companion escribir a las versiones viejas de firmware @@ -1782,6 +1528,11 @@ Puede ser diferente del lenguaje del firmware Check Firmware compatibility Comprobar la compatibilidad del firmware + + + <html><head/><body><p>Saves a dated copy of your eeprom to the backup folder you specified in the Companion settings before writing the current model to the radio.</p></body></html> + + Backup before Write @@ -1818,107 +1569,66 @@ Puede ser diferente del lenguaje del firmware Escribir al TX - + Current profile: %1 - + Choose Radio Backup file Elegir archivo de copia de seguridad de la radio - - - - - - - - - - + + Error Error - - Unable to find file %1! - - - - - - - Error opening file %1: -%2. - Error abriendo el archivo %1: -%2. - - - - - Invalid Models and Settings File %1 - Archivo de Modelos y Ajustes inválido %1 - - - - Error reading file %1: -%2. - Error leyendo el archivo %1: -%2. + + + + + Warning + Aviso - Invalid Models and Settings file %1 - - - - - - - - Warning - - - - Wrong radio calibration data in profile, Settings not patched Datos de calibración de radio incorrectos en el perfil, ajustes no corregidos - + Wrong radio setting data in profile, Settings not patched Datos de ajustes de radio incorrectos en el perfil, ajustes no corregidos - - + Cannot write file %1: %2. No se puede escribir el archivo %1: %2. - + Error writing file %1: %2. Error escribiendo el archivo %1: %2. - + The radio firmware belongs to another product family, check file and preferences! El firmware de la radio pertenece a otro producto, ¡comprueba el archivo y las preferencias! - + The radio firmware is outdated, please upgrade! El firmware de la radio está obsoleto, ¡por favor actializalo! - + Cannot check Models and Settings compatibility! Continue anyway? ¡No se pueden comprobar la compatibilidad de Modelos y Ajustes! ¿Continuar de todas maneras? @@ -1996,119 +1706,119 @@ Puede ser diferente del lenguaje del firmware Escribir al TX - + Open Firmware File Abrir archivo de Firmware - - - + + + Warning - + Aviso - + %1 may not be a valid firmware file %1 puede no ser un archivo de firmware válido - - - - + + + + Error Error - + The firmware file is not valid. El archivo de firmware no es válido. - + There is no start screen image in the firmware file. No hay imagen de pantalla de inicio en el archivo de firmware. - + Profile image %1 is invalid. El perfil de imagen %1 es inválido. - + Open image file to use as radio start screen Abir archivo de imagen para usar de pantalla de inicio de la radio - + Images (%1) Imagenes (%1) - + Image could not be loaded from %1 La imagen no puede ser cargada desde %1 - + The library image could not be loaded La librería de imágen no puede ser cargada - + Splash image not found - + Cannot save customized firmware No se puede guardar el firmware personalizado - + Write Firmware to Radio Escribir Firmware a la Radio - - + + Firmware check failed - + Could not check firmware from radio - + New firmware is not compatible with the one currently installed! - + Conversion failed Coversion fallida - + Cannot convert Models and Settings for use with this firmware, original data will be used No se pueden convertir los Modelos y Ajustes para usar con este firmware, se usarán los datos originales - + Restore failed Restauración fallida - + Could not restore Models and Settings to Radio. The models and settings data file can be found at: %1 No se ha podido restaurar los Modelos y Ajustes a la Radio. Los datos de los modelos y ajustes se pueden encontrar en: %1 - + Flashing done @@ -2116,47 +1826,47 @@ Puede ser diferente del lenguaje del firmware FlashProcess - + Executable %1 not found - + Writing... - + Reading... - + Verifying... - + unknown - + ie: OpenTX for 9X board or OpenTX for 9XR board Esto es: OpenTX para placas 9x o OpenTX para placas 9XR - + ie: OpenTX for M128 / 9X board or OpenTX for 9XR board with M128 chip Esto es: OpenTX para placas M128 / 9x o OpenTX para placas 9XR con el chip M128 - + ie: OpenTX for Gruvin9X board Esto es: OpenTX para placas Gruvin9x - + Your radio uses a %1 CPU!!! Please check advanced burn options to set the correct cpu type. @@ -2165,7 +1875,7 @@ Please check advanced burn options to set the correct cpu type. Por favor comprueba en las opciones avanzadas de gravado el tipo correcto de cpu. - + Your radio uses a %1 CPU!!! Please select an appropriate firmware type to program it. @@ -2174,7 +1884,7 @@ Please select an appropriate firmware type to program it. Por favor elige el tipo de firmware apropiado para programarlo. - + You are currently using: %1 @@ -2183,29 +1893,29 @@ Actualmente estás usando: %1 - + Your radio does not seem connected to USB or the driver is not installed!!! Please use ZADIG to properly install the driver. - + Your radio does not seem connected to USB or the driver is not initialized!!!. - + Flashing done (exit code = %1) - + Flashing done with errors - + FUSES: Low=%1 High=%2 Ext=%3 @@ -2236,35 +1946,65 @@ Please use ZADIG to properly install the driver. FlightModePanel - + Rotary Encoder %1 Codificador Rotativo %1 - + + Name + Nombre + + + + Value source + + + + + Value + Valor + + + GVAR%1 GVAR%1 - + Popup enabled Popup activado + + + &Clear + + + + + Clear + + + + + Clear all current Flight Mode properties? + + FlightModesPanel - + Flight Mode %1 Modo de vuelo%1 - + (%1) (%1) - + (default) (Predeterminado) @@ -2272,17 +2012,17 @@ Please use ZADIG to properly install the driver. FlybarSelectionPage - + Has Flybar Tiene Flybar - + Flybarless Flybarless - + Flybar: Flybar: @@ -2380,13 +2120,13 @@ p, li { white-space: pre-wrap; } - - + + Reset Radio Fuses - + Read Fuses from Radio @@ -2395,8 +2135,8 @@ p, li { white-space: pre-wrap; } GeneralEdit - General Edit - Edición General + Radio settings + @@ -2406,12 +2146,12 @@ These will be relevant for all models in the same EEPROM. Estos puede ser relevantes para todos los modelos en el mismo EEPROM. - + Setup Configuración - + Trainer Trainer @@ -2426,38 +2166,49 @@ Estos puede ser relevantes para todos los modelos en el mismo EEPROM.Recuperar calib. y los ajustes de hw de un perfil - + Global Functions - - Hardware / Calibration + + Hardware - - + + Calibration + + + + + + Warning Aviso - + Wrong data in profile, radio calibration was not retrieved Datos incorrectos en el perfil, la cablibración de la radio no se ha recuperado - + + Wrong data in profile, Switch/pot config not retrieved + + + + Wrong data in profile, hw related parameters were not retrieved Datos incorrectos en el perfil,los parámetros de hw no se ha recuperado - + Do you want to store calibration in %1 profile<br>overwriting existing calibration? ¿Quieres guardar la calibración en el perfil %1<br>¿Sobreescribir la calibración existente? - + Calibration and HW parameters saved. Calibración y parámetros de HW guardados. @@ -2515,165 +2266,164 @@ Estos puede ser relevantes para todos los modelos en el mismo EEPROM. - + Timeshift from UTC Zona horaria UTC - + Voice Language - + Lenguaje de las Voces - + Country Code Codigo País - + Stick reverse - + FAI Mode Modo FAI - - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Si activas FAI, perderás el vario, las funciones de reproducción, la pantalla de telemetría. Esta función no se puede desactivar en la radio. - + Adjust RTC - + Vario pitch at max Tono de vario al max - - + + Hz - + Speaker Volume Volumen Altavoz - + Backlight Switch Switch de pantalla - + Sound Mode Modo sonido - + Color 1 - + Color 2 - + Speaker Pitch (spkr only) Tono del altavoz (solo altavoz) - + If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. Si este valor no es 0, cualquier pulsación encenderá la pantalla y se apagará despues de un número determinado de segundos. - + sec seg - + Backlight color Color de pantalla - + Beeper - + Speaker Altavoz - + BeeperVoice BeeperVoz - + SpeakerVoice VozAltavoz - + Beep volume Volumen Beep - + Wav volume Volumen Wav - + Vario volume Volumen Vario - + Background volume Volumen de Fondo - - + + ms - + Backlight Auto OFF after Apagado automático de pantalla después - + Backlight flash on alarm Pantalla parpadea con una alarma - + Vario pitch at zero Tono de vario a cero - + Vario repeat at zero Vario repite a cero - + This is the switch selectrion for turning on the backlight (if installed). @@ -2682,8 +2432,8 @@ Estos puede ser relevantes para todos los modelos en el mismo EEPROM. - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2698,32 +2448,42 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">Los valores pueden ser 20-45</span></p></body></html> - + Backlight Brightness Brillo pantalla - + RotEnc Navigation Navegación RotEnc - + + Automatically adjust the radio's clock if a GPS is connected to telemetry. + + + + America - + Japan Japón - + Europe Europa - + + Backlight OFF Brightness + + + + Mode selection: Mode 1: @@ -2764,271 +2524,271 @@ Modo 4: - + Mode 1 (RUD ELE THR AIL) Modo 1 (RUD ELE THR AIL) - + Mode 2 (RUD THR ELE AIL) Modo 2 (RUD THR ELE AIL) - + Mode 3 (AIL ELE THR RUD) Modo 3 (AIL ELE THR RUD) - + Mode 4 (AIL THR ELE RUD) Modo 4 (AIL THR ELE RUD) - + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> - + <html><head/><body><p>Orden de los canales</p><p><br/></p><p>Define el orden por defecto de las mezclas en un nuevo modelo</p></body></html> - + R E T A R E T A - + R E A T R E A T - + R T E A R T E A - + R T A E R T A E - + R A E T R A E T - + R A T E R A T E - + E R T A E R T A - + E R A T E R A T - + E T R A E T R A - + E T A R E T A R - + E A R T E A R T - + E A T R E A T R - + T R E A T R E A - + T R A E T R A E - + T E R A T E R A - + T E A R T E A R - + T A R E T A R E - + T A E R T A E R - + A R E T A R E T - + A R T E A R T E - + A E R T A E R T - + A E T R A E T R - + A T R E A T R E - + A T E R A T E R - + Stick Mode Modo Stick - + Metric Métrico - + Imperial - + Default Channel Order - + Orden Prederterminado Canales - + GPS Coordinates Coordenadas GPS - + Min - - + + v - + Max - + Low Memory Warning Aviso Memoria Baja - + Inactivity Timer Tiempo de inactividad - + Show Splash Screen on Startup Mostrar Pantalla de Inicio al Enceder - + Contrast Contraste - + Battery Meter Range - + Haptic Strength Fuerza de Haptic - + LCD Display Type Tipo de Pantalla LCD - + "No Sound" Warning Aviso "Sin Sonido" - + Battery Warning Aviso de Bateria - + Haptic Length Longitud Haptic - + MAVLink Baud Rate Transferencia Baud MAVLink - - + + Quiet Silencio - + Only Alarms Solo Alarmas - - + + No Keys Sin teclas - - + + All Todo - + Battery warning voltage. This is the threashhold where the battery warning sounds. @@ -3039,114 +2799,114 @@ Este es el umbral cuando la batería emite sonidos de aviso. Los valores aceptables son 5v..10v - + Standard Estandar - + Optrex - + If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. Si no es cero emitirá sonidos si el transmisor de deja sin pulsaciones surante el numero específico de minutos. - + min min - - + + Show splash screen on startup Mostrar pantalla de inicio al encender - + --- --- - + 2s 2s - + 3s 3s - + 4s 4s - + 6s 6s - + 8s 8s - + 10s 10s - + 15s 15s - + 4800 Baud - + 9600 Baud - + 14400 Baud - + 19200 Baud - + 38400 Baud - + 57600 Baud - + 76800 Baud - + 115200 Baud - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -3171,72 +2931,72 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Aviso de silencio - te alertará si el beeper está en modo silencio (0)</p></body></html> - - + + X-Short X-Corto - - + + Short Corto - - + + Normal - - + + Long Largo - - + + X-Long X-Largo - - + + hh° (N/S) mm' ss''.dd - + NMEA - + Play Delay (switch mid position) Retardo de Play (switch en posición media) - + Measurement Units Unidades de Medida - + Haptic Mode Modo Haptic - + Beeper Length Longitud del beeper - + Beeper Mode Modo Beeper - + Beeper volume 0 - Quiet. No beeps at all. @@ -3253,7 +3013,7 @@ p, li { white-space: pre-wrap; } 4 - Extra Alto. - + Alarms Only Solo Alarmas @@ -3261,7 +3021,7 @@ p, li { white-space: pre-wrap; } GeneralSetupPanel - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Are you sure ? @@ -3273,21 +3033,330 @@ Esta función no se puede desactivar en la radio. GyroPage - + No No - + Yes, controled by a switch Si, controlado por un switch - + Yes, controlled by a pot Si, controlado por un potenciómetro + + Hardware + + + Form + + + + + SQ + + + + + SR + + + + + LS2 + + + + + SP + + + + + SO + + + + + S4 + + + + + RS + + + + + SB + + + + + PPM 2 + PPM 2 + + + + + + + + + + + + + Beeper volume + +0 - Quiet. No beeps at all. +1 - No Keys. Normal beeps but menu keys do not beep. +2 - Normal. +3 - Loud. +4 - Extra loud. + Volumen Beeper + +0 - Silencio. Ningun tipo de beep. +1 - Sin teclas. Los beeps suenan normal pero las teclas de menu no sonarán. +2 - Normal. +3 - Alto. +4 - Extra Alto. + + + + OFF + + + + + S-Port Mirror + S-Port Espejo + + + + Telemetry + Telemetría + + + + SBUS Trainer + + + + + Debug + Depurar + + + + Rud + Rud + + + + PPM 3 + PPM 3 + + + + S1 + + + + + S2 + + + + + S3 + + + + + PPM 1 + PPM 1 + + + + Serial Port + Puerto Serie + + + + v + + + + + PPM Multiplier + Multiplicador PPM + + + + Current Offset + + + + + PPM 4 + PPM 4 + + + + SA + + + + + Ele + Ele + + + + Ail + Ail + + + + Thr + Thr + + + + SC + + + + + LS + LS + + + + SD + + + + + Battery Offset + + + + + SE + + + + + SF + SF + + + + SG + + + + + SH + + + + + SI + + + + + SJ + + + + + SK + + + + + SL + + + + + SM + + + + + SN + + + + + RS2 + + + + + Bluetooth + + + + + ADC Filter + + + + + HardwarePanel + + + + + None + Ninguno + + + + 2 Positions Toggle + + + + + 2 Positions + + + + + 3 Positions + + + + + Pot with detent + + + + + Multipos switch + + + + + Pot without detent + + + + + Slider with detent + + + Heli @@ -3364,22 +3433,22 @@ Esta función no se puede desactivar en la radio. HeliPage - + Throttle Channel: Canal de Acelerador: - + Yaw Channel: Canal de Yaw: - + Pitch Channel: Canal de pitch: - + Roll Channel: Canal de roll: @@ -3387,121 +3456,121 @@ Esta función no se puede desactivar en la radio. InputsPanel - - + + Move Up Mover Arriba - - + + Ctrl+Up - - + + Move Down Mover Abajo - - + + Ctrl+Down - + Clear All Inputs Limpiar Todas las entradas - + Not enough available inputs! ¡No hay disponibles suficientes entradas! - + Delete Selected Inputs? ¿Borrar las Entradas Seleccionadas? - + &Add &Añadir - + Ctrl+A - + &Edit &Editar - + Enter - + &Delete &Borrar - + Delete Borrar - + &Copy &Copiar - + Ctrl+C Ctrl+C - + &Cut C&ortar - + Ctrl+X Ctrl+X - + &Paste &Pegar - + Ctrl+V - + Du&plicate &Duplicar - + Ctrl+U - + Clear Inputs? ¿Limpiar entradas? - + Really clear all the inputs? ¿Seguro que quieres limpiar todas las entradas? @@ -3509,88 +3578,89 @@ Esta función no se puede desactivar en la radio. LogicalSwitchesPanel - + V1 - + V2 - + Duration Duración - + Delay Retardo - + Function Función - + AND Switch - + L%1 - + + + (instant) + + + + &Delete &Borrar - + Delete Borrar - + &Copy &Copiar - - - (no release) - - - - + + (infinite) - + Ctrl+C - + &Cut C&ortar - + Ctrl+X - + &Paste &Pegar - + Ctrl+V @@ -3603,146 +3673,166 @@ Esta función no se puede desactivar en la radio. Visor de registros de Companion - + Filename Nombre Archivo - + Open LogFile Abrir archivo Registros - + Zoom - + X - + Y - + Reset Resetear - + Fly sessions Sesiones de vuelo - + Telemetry logs Registros de telemetría - + Time (hh:mm:ss) Hora (hh:mm:ss) - + Plot Title Change - + New plot title: - + Axis Label Change - + New axis label: - + Graph Name Change - + New graph name: - + Error: no GPS data not found - + The column containing GPS coordinates must be named "GPS". The columns for altitude "GAlt" and for speed "GSpd" are optional - + Error Error - + Cannot write file %1: %2. No se puede escribir el archivo %1: %2. - + + Cursor A: %1 m + + + + + Cursor B: %1 m + + + + + Time delta: %1 + + + + + Climb rate: %1 m/s + + + + Select your log file Selecciona tu archivo de registros - + Available fields Campos disponibles - + The selected logfile contains %1 invalid lines out of %2 total lines El archivo de registros elegido contiene %1 lineas inválidas de un total de %2 lineas - + total duration - + duration - + (L1) - + (R1) - + (L2) - + (R2) @@ -3750,523 +3840,466 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt MainWindow - - - - + + File loaded Archivo Cargado - - - + + Save As Guardar Como - - + + No updates available at this time. No hay actualizaciones disponibles ahora. - + Unable to check for updates. Imposible comprobar actualizaciones. - + Checking for updates Comprobando actualizaciones - + Executable (*.exe) Ejecutable (*.exe) - + A new release of Companion is available, please check the OpenTX website! ¡Una nueva versión de Companion está disponible, por favor comprueba la web de OpenTX! - + Would you like to launch the installer? ¿Quieres ejecutar el instalador? - - Not enough memory for all the selected firmware options - No hay memoria suficiente para todas las opciones de firmware seleccionadas - - - - + + File saved Archivo guardado - + Read Models and Settings From Radio Leer los Modelos y Ajustes de la Radio - + Save Radio Backup to File Guardar Copia deSeguridad de la Radio a un Archivo - + Read Radio Firmware to File Leer el Firmware de la Radio a un Archivo - + OpenTX Home Page: <a href='%1'>%1</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> Si has encontrado este programa útl, por favor ayuda con una <a href='%1'>donación</a> - + Display previous warning again at startup ? ¿Volver a mostrar el aviso previo de nuevo a comenzar? - + New release available Nueva versión disponible - - + + Error - + Error opening file %1: %2. Error abriendo el archivo %1: %2. - - Compilation server termporary failure, try later - Fallo temporal en el servidor de compilación, intentalo mas tarde - - - + Compilation server too busy, try later Servidor de compilación demasiado ocupado, inténtalo mas tarde - + Unknown server failure, try later Fallo desconocido de servidor, inténtalo mas tarde - - + + Yes Si - - + + No - - + + Release Notes Notas de la Versión - - + + Do you want to download release %1 now ? ¿Quieres descargar la versión %1 ahora? - - + + Open Models and Settings file Abrir archivo de Modelos y Ajustes - + Firmware updates Actualizaciones de firmware - + Current firmware does not provide release notes informations. EL firmware actual no proporciona notas de la versión. - + New Nuevo - + Open... Abrir... - + Save Guardar - + Save As... Guardar Como... - + Copy Model Copiar Modelo - + Paste Model Pegar Modelo - + Load backup from file Cargar copia de seguridad desde un archivo - + Compare models Comparar modelos - + Exit the application Salir de la aplicación - + List available programmers Lista de programadores disponibles - + Show fuses dialog - + Show the application's About box Mostrar la ventana de aplicación Acerca de - + Set Menu Language Menú Ajuste Lenguaje - + Show the list of radio profiles Mostrar la lsita de los perfiles de radio - + Write Escribir - + %2 %2 - + New Radio Nueva Radio - + A new version of Companion is available (version %1)<br>Would you like to download it? Una nueva versión de Companion está disponible (versión %1),<br>¿Te gustaría descargarla? - - Compilation server requires registration, please check OpenTX web site - El servidor de compilación requiere registro, por favor comprueba la pagina web de OpenTX - - - + Do you want to write the firmware to the radio now ? ¿Te gustaría escribir el firmware a la radio ahora? - - The selected language will be used the next time you start Companion. - El lenguaje seleccionado podrá ser usado la próxima vez que inicies Companion. - - - + The new theme will be loaded the next time you start Companion. El nuevo tema será cargado la próxima vez que inicies Companion. - + The icon size will be used the next time you start Companion. El tamaño de los iconos será usado la próxima vez que inicies Companion. - + About Companion Acerca de Companion - + A monochrome black icon theme Tema de icono monocromo negro - + A monochrome white icon theme Tema de icono monocromo blanco - + A monochrome blue icon theme Tema de icono monocromo azul - + Small Pequeño - + Use small toolbar icons Usar iconos pequeños en la barra de herramientas - + Use normal size toolbar icons Usar iconos normales en la barra de herramientas - + Normal - + Use big toolbar icons Usar iconos grandes en la barra de herramientas - + Big Grande - + Use huge toolbar icons Usar iconos extra grandes en la barra de herramientas - + Huge Extra Grande - + Ignore this release %1? ¿Ignorar esta versión %1? - + + Not enough flash available on this board for all the selected options + + + + + Compilation server temporary failure, try later + + + + + Compilation error + + + + + Invalid firmware + + + + + Invalid board + + + + + Invalid language + + + + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + + + + + Models and Settings read + + + + + + This function is not yet implemented + + + + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> El proyecto OpenTX Companion se ha bifurcado originalmente desde <a href='%1'>eePe</a> - + Copyright OpenTX Team Derechos de autor del equipo OpenTX - + Create a new Models and Settings file Crear un nuevo archivo de Modelos y Ajustes - - + + Save Models and Settings file Guardar el archivo de Modelos y Ajustes - + Exit Salir - + Cut Model Cortar Modelo - + Cut current model to the clipboard Cortar el modelo actual al portapapeles - + Copy current model to the clipboard Copiar el modelo actual al portapapeles - + Paste model from clipboard Pegar modelo desde el portapapeles - + + Use default system language. + + + + + Use %1 language (some translations may not be complete). + + + + Classical Clasico - + The classic companion9x icon theme Tema de iconos clasicos de companion9x - + Yerico - + Yellow round honey sweet icon theme Tema de iconos amarillo miel redondo - + Monochrome Monocromo - + MonoWhite MonoBlanco - + MonoBlue MonoAzul - + System language Lenguaje del sistema - - Use system language in menus - Usar elnguaje del sistema en los menús - - - - Czech - Checo - - - - Use Czech in menus - Usar Checo en los menús - - - - German - Alemán - - - - Use German in menus - Usar Alemán en los menús - - - - English - Inglés - - - - Use English in menus - Usar Inglés en los menús - - - - Finnish - Finlandés - - - - Use Finnish in menus - Usar Finlandés en los menús - - - - French - Francés - - - - Use French in menus - Usar Francés en los menús - - - - Italian - Italiano - - - - Use Italian in menus - Usar Italiano en los menús - - - - Polish - Polaco - - - - Use Polish in menus - Usar Polaco en los menús - - - - Swedish - Sueco - - - - Use Swedish in menus - Usar Sueco en los menús - - - - Spanish - Español - - - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -4275,7 +4308,7 @@ We recommend you view the release notes using the button below to learn about an - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -4286,313 +4319,306 @@ We recommend you view the release notes using the button below to learn about an - - - + + + Companion Companion - - + + Synchronize SD - + OpenTX Companion %1 - Radio: %2 - Profile: %3 - Use Spanish in menus - Usar Español en los menús - - - About... Acerca de... - + Print... Imprimir... - + Print current model Imprimir el modelo actual - + Simulate... Simular... - + Simulate current model Simular el modelo actual - + Alt+S - + Load Backup... Cargar Copia de Seguridad... - + View Log File... Ver Archivo de Registro... - + Open and view log file Abrir y ver el archivo de registro - + Settings... Ajustes... - + Edit Settings Editar Ajustes - + Download... Descargar... - + Download firmware and voice files Descargar los archivos de firmware y voces - + Check for Updates... Comprobar Actualizaciones... - + Check OpenTX and Companion updates Comprobar la actualizaciones de OpenTX y Companion - + Companion Changes... Cambios Companion... - + Show Companion change log Mostrar el registro de cambios de Companion - + Firmware Changes... Cambios de Firmware... - + Show firmware change log Mostrar el registro de cambios de firmware - + Compare Models... Comparar Modelos... - + Edit Radio Splash Image... Editar Imagen de Inicio de la Radio... - + Edit the splash image of your Radio Editar la imagen de inicio de tu radio - + List programmers... Lista de programadores... - + Fuses... - - + + Read Firmware from Radio Leer Firmware desde la Radio - + Read firmware from Radio Leer firmware desde la Radio - - + Write Firmware to Radio Escribir Firmware a la Radio - + Write firmware to Radio Escribir firmware a la Radio - + Add Radio Profile Añadir perfil de Radio - + Create a new Radio Setting Profile Crear un nuevo Perfil de Ajuste de Radio - + Manuals and other Documents Manuales y otros Documentos - + Open the OpenTX document page in a web browser Abrir la página de documentación de OpenTX en un navegador - + Write Models and Settings To Radio Escribir Modelos y Ajustes a la Radio - - + Write Models and Settings to Radio Escribir Modelos y Ajustes a la Radio - - + + Read Models and Settings from Radio Leer los Modelos y Ajustes de la Radio - + Configure Communications... Configurar Comunicaciones... - + Configure software for communicating with the Radio Configurar software para la comunicación con la Radio - + Write Backup to Radio Escribir Copia de Seguridad a la Radio - + Write Backup from file to Radio Escribir Copia de Seguridad desde un archivo a la Radio - + Backup Radio to File Copia de Seguridad de la Radio a un Archivo - + Save a complete backup file of all settings and model data in the Radio Guardar una copia de seguridad completa de todos los datos de ajustes y modelos en la Radio - + Contributors... Contribuidores... - + A tribute to those who have contributed to OpenTX and Companion Un tributo a aquellos que han contribuido en OpenTX y Companion - + SD card synchronization - + Recent Files Archivos Recientes - + Recent Models+Settings Recientes Modelos+Ajustes - + Set Icon Theme Selecciona el Tema de Iconos - + Set Icon Size Selecciona el Tamaño de Iconos - - + + File Archivo - - + + Edit Editar - + Settings Ajustes - + Read/Write Leer/Escribir - - + + Help Ayuda - - + + Radio Profile Perfil de Radio - + Show recent Models+Settings documents Mostrar los documentos recientes de Modelos +Ajustes - + Ready Listo @@ -4600,134 +4626,260 @@ We recommend you view the release notes using the button below to learn about an MdiChild - - - - - - - - - - - - - - - - - - + + + + + + Error Error - + Editing model %1: Editando modelo %1: - - + + Delete selected models? + + + + + Cannot delete default model. + No se puede borrar el modelo predeterminado. + + + + &Edit + &Editar + + + + &Restore from backup + &Restaurar desde copia de seguridad + + + + &Model Wizard + Asistente &Modelos + + + + &Delete + &Borrar + + + + Delete + Borrar + + + + &Copy + &Copiar + + + + Ctrl+C + Ctrl+C + + + + &Cut + C&ortar + + + + Ctrl+X + Ctrl+X + + + + + &Paste + &Pegar + + + + + Ctrl+V + Ctrl+V + + + + D&uplicate + &Duplicar + + + + Ctrl+U + + + + + Move to Category + + + + + &Use as default + &Usar como valor predeterminado + + + + P&rint model + Imp&rimir modelo + + + + Ctrl+P + + + + + &Simulate model + &Simular modelo + + + + Alt+S + + + + + &Add model + + + + + &Rename category + + + + + &Delete category + + + + + &Add category + + + + + Models and settings will be automatically converted. +If that is not what you intended, please close the file +and choose the correct radio type/profile before reopening it. + + + + + Do you want to overwrite radio general settings? + ¿Quieres sobreescribir los ajustes generales de la radio? + + + + You are pasting on an not empty model, are you sure? + Estas pegando en un modelo que no está vacio, ¿estas seguro? + + + + This category is not empty! + + + + + New model + + + + + Unable to find Horus radio SD card! + + + + + Models and Settings written + + + + Unable to find file %1! ¡No es posible encontrar el archivo %1! - - + Error reading file %1: %2. Error leyendo el archivo %1: %2. - + free bytes Bytes libres - - - - + Error opening file %1: %2. Error abriendo el archivo %1: %2. - - - Invalid EEPROM File %1 - Archivo EEPROM inválido %1 - - - - Invalid binary EEPROM File %1 - Archivo binario EEPROM inválido %1 - - - - - - + + + + Save As Guardar Como - - - - - Cannot write file %1: -%2. - No se puede escribir el archivo %1: -%2. - - - + Open backup Models and Settings file Abrir archivo de copia de seguridad de Modelos y Ajustes - + + Companion Companion - + %1 has been modified. Do you want to save your changes? %1 ha sido modificado. ¿Quieres guardar los cambios? - - - - + Warning Aviso - + Invalid binary backup File %1 Archivo binariode copia de seguridad inválido %1 - - - Error writing file %1: -%2. - Error escribiendo el archivo %1: -%2. - - - + Cannot write temporary file! ¡No se puede escribir el archivo temporal! + + + Radio settings + + + + + Simulate Tx + Simular TX + MixerDialog @@ -4929,139 +5081,159 @@ Esto determina como los valores de mezcla son añadidos. Abajo - + DEST -> CH%1 DEST ->CH%1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + MixesPanel - - + + Move Up Mover Arriba - - + + Ctrl+Up Ctrl+Arriba - - + + Move Down Mover Abajo - - + + Ctrl+Down Ctrl+Abajo - + Clear Mixes Limpiar mezclas - + Not enough available mixers! ¡No hay suficientes mezclas disponibles! - + Delete Selected Mixes? ¿Borrar las mezclas seleccionadas? - + &Add &Añadir - + Ctrl+A - + &Edit &Editar - + Enter Enter - + &Toggle highlight &Seleccionar Palanca - + Ctrl+T - + &Delete &Borrar - + Delete Borrar - + &Copy &Copiar - + Ctrl+C - + Ctrl+X - + C&ut C&ortar - + &Paste &Pegar - + Ctrl+V - + Du&plicate &Duplicar - + Ctrl+U - + Clear Mixes? ¿Limpiar mezclas? - + Really clear all the mixes? ¿Seguro que quieres limpiar todas las mezclas? @@ -5074,52 +5246,52 @@ Esto determina como los valores de mezcla son añadidos. Mensaje - + Setup Ajustes - + Heli - + Inputs Entradas - + Logical Switches Switches lógicos - + Mixes Mezclas - + Outputs Salidas - + Curves Curvas - + Special Functions Funciones especiales - + Telemetry Telemetría - + Flight Modes Fases de vuelo @@ -5132,276 +5304,308 @@ Esto determina como los valores de mezcla son añadidos. ModelPrinter - + %1 bytes - + CH%1 - + Exponential Exponencial - + Extra Fine Extra Fino - + Fine Fino - + Medium Medio - + Coarse Duro - + Unknown Desconocido - + Enabled Activado - + Disabled Desactivado - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) - + %1, Channels(%2-%3) - + Receiver number(%1) - + + radio Protocol %1, subType %2, option value %3 + + + + Slave/Jack - + Master/SBUS Module - + Master/CPPM Module - + Master/SBUS in battery compartment - + Master/Jack - + + 90 + 90 + + + + 120 + 120 + + + + 120X + 120X + + + + 140 + 140 + + + Rudder Timón - + Elevator Profundidad - + Throttle Acelerador - + Aileron Aleron - + Name(%1) - + Slow(u%1:d%2) - + Persistent - + MinuteBeep - + CountDown(Beeps) - + CountDown(Voice) - + CountDown(Haptic) - + + Off Apagado - - - - + + + + FM%1 - + FM%1%2 - + FM%1+%2 - + [I%1] - + Input%1 Entrada%1 - + Weight - + Switch - - + + NoTrim - + Weight(%1) - + Switch(%1) Switch(%1) - + No DR/Expo - + + Offset(%1) - + Delay(u%1:d%2) - + Warn(%1) - + Disabled in all flight modes - + Flight modes(%1) Modos de vuelo(%1) - + Flight mode(%1) Modo de vuelo(%1) - + Edge(%1, [%2:%3]) - + + instant + + + + Sticky(%1, %2) - + Timer(%1, %2) Temporizador (%1, %2) - + Duration(%1s) - + Delay(%1s) - + Custom A medida - + Standard Estandar @@ -5409,27 +5613,27 @@ Esto determina como los valores de mezcla son añadidos. ModelSelectionPage - + Plane Avión - + Multirotor - + Helicopter Helicóptero - + Model Name: Nombre Modelo: - + Model Type: Tipo Modelo: @@ -5437,130 +5641,7 @@ Esto determina como los valores de mezcla son añadidos. ModelsListWidget - - - &Edit - &Editar - - - - &Restore from backup - &Restaurar desde copia de seguridad - - - - &Model Wizard - Asistente &Modelos - - - - &Delete - &Borrar - - - - Delete - Borrar - - - - &Copy - &Copiar - - - - Ctrl+C - Ctrl+C - - - - &Cut - C&ortar - - - - Ctrl+X - Ctrl+X - - - - &Paste - &Pegar - - - - Ctrl+V - Ctrl+V - - - - D&uplicate - &Duplicar - - - - Ctrl+U - - - - - &Use as default - &Usar como valor predeterminado - - - - P&rint model - Imp&rimir modelo - - - - Ctrl+P - - - - - Alt+S - - - - - &Simulate model - &Simular modelo - - - - General Settings - Ajustes Generales - - - - Delete Selected Models? - ¿Borrar los modelos seleccionados? - - - - - Cannot delete default model. - No se puede borrar el modelo predeterminado. - - - - Cannot cut default model. - No se puede cortar el valor predeterminado. - - - - Do you want to overwrite radio general settings? - ¿Quieres sobreescribir los ajustes generales de la radio? - - - - You are pasting on an not empty model, are you sure? - You are pasting on an not empty model, are you sure ? - Estas pegando en un modelo que no está vacio, ¿estas seguro? - - - + No free slot available, cannot duplicate No hay ranuras disponibles, no se puede duplicar @@ -5568,142 +5649,199 @@ Esto determina como los valores de mezcla son añadidos. Module - + Failsafe Mode Modo Failsafe - + Start Comenzar - + PPM delay Retardo PPM - + Negative Negativo - + Positive Positivo - + Polarity Polaridad - + Trainer Mode Modo Entrenador - + PPM Frame Length Longitud Trama PPM - + CH - + + SubType + + + + + Antenna + + + + + Internal + + + + + Ext. + Int. + + + + + Option value + + + + + Bind on startup + + + + + Low Power + + + + us - + + Multi Radio Protocol + + + + Master/Jack - + Slave/Jack - + Master/SBUS Module - + Master/CPPM Module - + Master/SBUS in battery compartment - + + Show values in: + + + + + % + abbreviation for percent + + + + + μs + abbreviation for microseconds + + + + ms - + Channels Canales - + Not set - + Hold Esperar - + Custom A medida - + No Pulses Sin Pulsos - + Receiver Receptor - + Failsafe Positions Posiciones Failsafe - + Protocol Protocolo - + Receiver No. Receptor Nº. - + Output type - + Open Drain - + Push Pull @@ -5711,43 +5849,43 @@ Esto determina como los valores de mezcla son añadidos. ModulePanel - + Trainer Port Puerto Entrenador - + Internal Radio System Sistema Interno de Radio - + External Radio Module Modulo externo de Radio - - + + Radio System Sistema de Radio - + Extra Radio System Extra Sistema de Radio - + Value Valor - + Hold Esperar - + No Pulse @@ -5755,229 +5893,322 @@ Esto determina como los valores de mezcla son añadidos. MultiModelPrinter - + General Model Settings - + Name: - + EEprom Size: - + Timer%1: - + Module%1: - + Module: - + Trainer port: - + Throttle Trim: - + Trim Increment: - + Center Beep: - + + Helicopter Setup + + + + + Swash Type: + + + + + Swash Ring: + + + + + Input + Entrada + + + + Weight + + + + + Long. cyc + + + + + Lateral cyc + + + + + Collective + Colectivo + + + Flight modes Modos de vuelo - - + + Flight mode Modo de vuelo - + Switch - + Fade IN - + Fade OUT - - + + FM%1 - - + + GV%1 - + RE%1 - + Limits Limites - + Channel - + Name Nombre - - + + Offset Offset - + Min - + Max - + Invert Invertir - + Global Variables Variables globales - + Inputs Entradas - + Mixers Mezclas - + CV%1 - + Curves Curvas - + L%1 - + Logical Switches - + Switches lógicos - + SF%1 SF%1 - + Special Functions - + Funciones especiales - + Telemetry Settings Ajustes Telemetría - + Analogs - + Unit Unidad - + Scale Escala - + A%1 A%1 - + RSSI Alarms + + + Low Alarm + Alarma Baja + + + + Critical Alarm + Alarma crítica + + + + Multiprotocols + + + Subtype + + + + + Video TX frequency + + + + + C2500 frequency fine tune + + + + + Telemetry + Telemetría + + + + Radio output power + + + + + Servo output frequency + + + + + Option value + + + + + DEFAULT + + MultirotorPage - + Throttle Channel: Canal Throttle: - + Yaw Channel: Canal Yaw: - + Pitch Channel: Canal Pitch: - + Roll Channel: Canal Roll: @@ -5985,17 +6216,17 @@ Esto determina como los valores de mezcla son añadidos. OptionsPage - + Throttle Cut Corte de Gas - + Throttle Timer Temporizador de Gas - + Flight Timer Temporizador de vuelo @@ -6018,17 +6249,17 @@ Esto determina como los valores de mezcla son añadidos. Imprimir a archivo - + Print Document Imprimir documento - + Select PDF output file Seleccionar archivo de salida PDF - + ODF files (*.odt);;PDF Files(*.pdf);;HTML-Files (*.htm *.html);;All Files (*) Archivos ODF (*.odt);;Archivos PDF (*.pdf);;Archivos HTML(*.htm *.html);;Todos los Archivos (*) @@ -6062,2241 +6293,2125 @@ Esto determina como los valores de mezcla son añadidos. QObject - + Polish Polaco - + CH%1 - + No No - + RotEnc A - + Rot Enc B - + Rot Enc C - + Rot Enc D - + Rot Enc E - + Trainer Entrenador - + Trainer RUD Entrenador RUD - + Trainer ELE Entrenador ELE - + Trainer THR Entrenador THR - + Trainer AIL Entrenador AIL - + Instant Trim Trim Instantáneo - + Play Sound Reproducir Sonido - - Start Logs - Comenzar Registro - - - + Haptic Reproducir Haptic - - - + + + --- - + Rud Trim - + Ele Trim - + Thr Trim - + Ail Trim - + Rot Enc - + English Inglés - + French Francés - + Italian Italiano - + German Alemán - + Czech Checo - + Slovak Eslovaco - + Spanish Español - + Portuguese Portugués - + Swedish Sueco - + + Dutch + + + + + Hungarian + + + + No repeat No Repetir - + Reset Resetear - + mA - + kts - + f - + + mW + + + + dB - + rpms - + + Rad + + + + hours - + minutes - + seconds - + h:m - + m:s - + h:m:s - - + F1 - - + F2 - - + F3 - - + F4 - - + S3 - - - + + + Timer3 Temporizador 3 - + RSSI Tx - + RSSI Rx - + A3 - + A4 - + Cells - + dTE - + Hdg - + AirSpeed - + A3- - + A4- - + Speed+ Velocidad+ - + Dist+ - + AirSpeed+ - + Cell- - + Cells- - + Vfas- - + Curr+ - + Powr+ - + ACC - + GPS Time Hora GPS - - + L1 - - + L2 - - - L3 - - - - - - L4 - - - - - - L5 - - - - - - L6 - - - - - - L7 - - - - - - L8 - - - - - - L9 - - - - - - L10 - - - - - - L11 - - - - - - L12 - - - - - - L13 - - - - - - L14 - - - - - - L15 - - - - - - L16 - - - - - - L17 - - - - - - L18 - - - - - - L19 - - - - - - L20 - - - - - - L21 - - - - - - L22 - - - - - - L23 - - - - - - L24 - - - - - - L25 - - - - - - L26 - - - - - - L27 - - - - - - L28 - - - - - - L29 - - - - - - L30 - - - - - - L31 - - - - - - L32 - - - - + [I%1] - + LUA%1%2 - + TR%1 - + FM0 - + FM1 - + FM2 - + FM3 - + FM4 - + FM5 - + FM6 - + FM7 - + FM8 - - S31 - - - - - S32 - - - - - S33 - - - - - S34 - - - - - S35 - - - - - S36 - - - - + RudTrim Left RudTrim Izquierda - + RudTrim Right RudTrim Derecha - + EleTrim Down EleTrim Abajo - + EleTrim Up EleTrim Arriba - + ThrTrim Down ThrTrim Abajo - + ThrTrim Up ThrTrim Arriba - + AilTrim Left AilTrim Izquierda - + AilTrim Right AilTrim Derecha - + + Trim 5 Down + + + + + Trim 5 Up + + + + + Trim 6 Down + + + + + Trim 6 Up + + + + THs - + TH% - + THt - + One Uno - + ??? ??? - + a>x - + a<x - + |a|>x - + |a|<x - + AND - + OR - + XOR - + a=b - + a!=b - + a>b - + a<b - + a>=b - + a<=b - + d>=x - + |d|>=x - + a=x - + a~x - + Timer Temporizador - + Sticky - + + Left Horizontal + Izquierda Hrizontal + + + + Left Vertical + Izquierda Vertical + + + + Right Vertical + Derecha Vertical + + + + Right Horizontal + Derecha Horizontal + + + + Aux. 1 + + + + + Aux. 2 + + + + + Unknown Desconocido - + Override %1 Invalidar %1 - + Set Timer %1 Ajustar temporizador %1 - + Vario - + Play Track Reproducir Pista - + Play Both Reproducir Ambos - + Play Value Reproducir Valor - + Play Script - + + SD Logs + + + + Volume Volumen - + Backlight Luz de Fondo - + Screenshot - + Background Music Música de Fondo - + Background Music Pause Pausar Música de Fondo - + played once, not during startup - + repeat(%1s) - + DISABLED - + INV INV - + NOR NOR - + Edge - + + Trm5 + + + + + Trm6 + + + + + + L%1 + + + + SetFailsafe Int. Module - + SetFailsafe Ext. Module - + RangeCheck Int. Module - + RangeCheck Ext. Module - + Bind Int. Module - + Bind Ext. Module - - - + + + <font color=red><b>Inconsistent parameter</b></font> <font color=red><b>Parámetro Inconsistente</b></font> - + Value Valor - + Decr: - + Incr: - + Played once, not during startup Reproducir una vez, no en el inicio - + %1s - + Adjust GV%1 Ajustar GV%1 - + Rotary Encoder Codificador Rotativo - + Value Valor - + Source Origen - + GVAR GVAR - + Increment Incremento - + Flight - - Finnish - Finlandés - - - + !Flight mode %1 !Modo de vuelo%1 - + Flight mode %1 Modo de vuelo%1 - + Flight mode %1 value Valor modo de vuelo%1 - + + -GV%1 (%2) + + + + + GV%1 (%2) + + + + Yellow Amarillo - + Orange Naranja - + Red Rojo - + Winged Shadow How High - + Winged Shadow How High (not supported) - + FrSky Sensor Hub - + None Ninguno - + Imperial - + Metric Métrico - - - + + + Uknown error during Simulator startup. + + + + + Simulator Error + + + + + Data Load Error + + + + + Error occurred while starting simulator. + + + + + + Timer1 Temporizador1 - - - + + + Timer2 Temporizador 2 - + Telemetry Telemetría - + Own value Valor propio - + Keys Teclas - + Sticks - + Keys + Sticks Teclas + Sticks - - + + -GV%1 - - - - + + + + ---- - - - + + P1 - - - + + P2 - - - + + P3 - + MAX - - + + Rud - - - - - - - + + + + + + + V - - + + s - + ft - - - + + + m - - - + + + °C - - - + + + ° - - + + % - - - + + + mph - - - + + + km/h - - + + m/s - - + + A - - + + °F - - + + mAh - - + + W - - + + g - - + + Ele - - + + Thr - - + + Ail - - - + + + REa - - - + + + REb - - S11 - - - - - S12 - - - - - S13 - - - - - S14 - - - - - S15 - - - - - S16 - - - - - S21 - - - - - S22 - - - - - S23 - - - - - S24 - - - - - S25 - - - - - S26 - - - - + Diff(%1) - + Expo(%1) - + Function(%1) Función(%1) - + Curve(%1) Curva(%1) - + !Curve(%1) !Curva(%1) - + Alt - + Rpm - + Fuel Combustible - + Speed Velocidad - + Dist - + GPS Alt - + Cell - + A1 - + A2 - + T1 - + T2 - - - Simultaneous usage of expo and curves is no longer supported - El uso simultáneo de exponenciales y curvas no está soportado - - - + TrmR - + TrmE - + TrmT - + TrmA - - - - + + + S1 - - - - + + + S2 - - - - + + + LS - - - - + + + RS - - + + Batt Batería - + SWR - + Vfas - + Curr - + Cnsp - + Powr - + AccX - + AccY - + AccZ - + VSpd - + A1- - + A2- - + Alt- - + Alt+ - + Rpm+ - + T1+ - + T2+ - - + + Time Hora - + CYC%1 - - - + + + GV%1 - + THR - - - + + + ON - - - + + + OFF - - + + Support for frsky telemetry mod Mod de soporte para telemetría frsky - - + + Support for jeti telemetry mod Mod de soporte para tele,etría jeti - - + + Support for receiving ardupilot data Soporte para recepción de datos ardupilot - - + + Support for receiving NMEA data Soporte para recepción de datos NMEA - + Support for telemetry easy board Soporte para para placa sencilla de telemetría - - - Support for MAVLINK devices - Soporte para dispositivos MAVLINK - - - - Rotary Encoder use in menus navigation - Uso de codificador rotativo en los menús de navegación - - - - - - - - - Enable heli menu and cyclic mix support - Activar menú Heli y el soporte de mezcla de cíclico - - - - - - - - - - - - Enable TEMPLATES menu - Activar menú PLANTILLAS - - - - - - - No splash screen - Sin pantalla de inicio - - - - - - - - - - - - Disable curves menus - Desctivar el menú curvas - - - - - - - Support for radio modified with regular speaker - Soporte para radio modificada con altavoz normal - - - - - - - - Used if you have modified your radio with voice mode - Usado si tienes modificada tu radio con modo voz - - - - - - - - Used if you have modified your radio with haptic mode - Usado si tienes tu radio modificada con el modo haptic - - - - Channel values displayed in us - Visualizar los valores de canal en us - - - - - - - - - - - - In model setup menus automatically set source by moving the control - En el menú de ajuste de modelo se selecciona automáticamente el origen del control moviendolo - - - - - - - - - - - - In model setup menus automatically set switch by moving the control - En el menú de ajuste de modelo se selecciona automáticamente el switch de control moviendolo - - - - Use alternative SQT5 font - Usar fuente alternativa SQT5 - - - - (displaying only first 10 warnings) - (visualizar solo los 10 primero avisos) - - - - Possibility to enable FAI MODE (no telemetry) at field + + Unknown error - - FAI MODE (no telemetry) always enabled + + ... plus %1 errors - - - - - Support for a third timer + + Cannot write radio settings - - Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) + + Cannot write model %1 - - Instead of Joystick emulation, USB connection is Command Line Interface + + 6P + 6P + + + + JSx - - Removes D8 and LR12 FrSky protocols that are not legal for use in the EU on radios sold after Jan 1st, 2015 + + JSy + Support for the DIY-Multiprotocol-TX-Module + + + + + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 + + + + + Enable Lua compiler + + + + + KS108 LCD + + + + + WTV20 voice module + + + + + JQ6500 voice module + + + + + + Support for MAVLINK devices + Soporte para dispositivos MAVLINK + + + + Rotary Encoder use in menus navigation + Uso de codificador rotativo en los menús de navegación + + + + FrSky Taranis X9D+ + + + + + FrSky Taranis X9D + + + + + Horus gimbals installed (Hall sensors) + + + + + FrSky Taranis X7 + + + + + FrSky Horus + + + + + Use ONLY with first DEV pcb version + + + + + Turnigy 9XR-PRO + + + + + Turnigy 9XR with m128 chip + + + + + + + + + + Enable heli menu and cyclic mix support + Activar menú Heli y el soporte de mezcla de cíclico + + + + + + + + + Enable TEMPLATES menu + Activar menú PLANTILLAS + + + + + + + No splash screen + Sin pantalla de inicio + + + + + + + + + Disable curves menus + Desctivar el menú curvas + + + + + + + + Support for radio modified with regular speaker + Soporte para radio modificada con altavoz normal + + + + + + + + Used if you have modified your radio with voice mode + Usado si tienes modificada tu radio con modo voz + + + + + + + + Used if you have modified your radio with haptic mode + Usado si tienes tu radio modificada con el modo haptic + + + + Channel values displayed in us + Visualizar los valores de canal en us + + + + + + + + + + + + In model setup menus automatically set source by moving the control + En el menú de ajuste de modelo se selecciona automáticamente el origen del control moviendolo + + + + + + + + + + + + In model setup menus automatically set switch by moving the control + En el menú de ajuste de modelo se selecciona automáticamente el switch de control moviendolo + + + + + + + + + + + + + + Use alternative SQT5 font + Usar fuente alternativa SQT5 + + + + Possibility to enable FAI MODE (no telemetry) at field + + + + + FAI MODE (no telemetry) always enabled + + + + + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) + + + + + Instead of Joystick emulation, USB connection is Command Line Interface + + + + + Support for PPM internal module hack - + ST7565P LCD or compatible - + ST7565R LCD or compatible - + ERC12864FSF LCD - + ST7920 LCD - - 9X board - - - - - - - + + + + Enable the throttle trace in Statistics Activar el recorrido del acelerador en las Estadísticas - + EEprom write progress bar Barra de progreso de escritura EEPROM - - + + No Winged Shadow How High support - - + + Turnigy 9XR + + + + + No vario support No hay soporte de variómetro - - + + No GPS support No hay soporte para GPS - - + + No gauges in the custom telemetry screen No hay indicadores en la pantalla de telemetría personalizada - + + 9X with stock board + + + + Allow compensating for offset errors in FrSky FAS current sensors Permitir la compensación de los errores de offset en los sensores FrSky FAS actuales - - + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) Añadir soporte para invertir las entradas de sticks (ejem. neseraio para los gimbals FrSky) - - Power management by soft-off circuitry - - - - - ar9x board / 9X - - - - - 9XR-PRO + + 9X with stock board and m128 chip - FrSky Taranis + 9X with AR9X board - - FrSky Taranis Plus + + 9X with Sky9x board - + + 9X with Gruvin9x board + + + + + DIY MEGA2560 radio + + + + + Power management by soft-off circuitry + + + + FrSky Taranis X9E - + Confirmation before radio shutdown - - - Adds mixers output view to the CHANNELS MONITOR screen, pressing [ENT] switches between the views - - - - + Haptic module installed Módulo Haptic instalado - + Support for Lua model scripts Soporte para los modelos de scripts Lua - - + + Support of FrSky PXX protocol Soporte para protocolo FrSky PXX - + Disable HELI menu and cyclic mix support Desactivar el menú de HELI y el soporte de mezcla de cíclico - + Disable Global variables Desactivar las variables Globales - - - - - + + + + + Support for DSM2 modules Soporte para los módulos DSM2 - - - - - - - - - + + + + + + PPM center adjustment in limits Ajuste del centro PPM en los limites - - - - - - - - - + + + + + + Symetrical Limits Límites simétricos - - - - - - - + + + + + + + Pots use in menus navigation Usar potenciómetros en los menús de navegación - + No OverrideCH functions available No hay funciones OverrideCH disponibles - - - - - - - - - + + + + + + + + + No flight modes Sin modos de vuelo - - + + SmartieParts 2.2 Backlight support Soporte de retroiluminación para SmartieParts 2.2 - - - - - - + + + + + + Enable resetting values by pressing up and down at the same time Activar el reseteo de valores presionando up y down al mismo tiempo - - - - - - - - - + + + + + + + + + No graphical check boxes and sliders Sin casillas de verificación ni sliders gráficos - - - - - - - - - + + + + + + + + + Battery graph Gráfico batería - - - - - - - - - + + + + + + + + + Don't use bold font for highlighting active items No usar la fuente negrita para destacar elementos activos - - - - - + + + + + EEprom write Progress bar Barra de progreso de escriture de EEprom - - - - - - + + + + + + Imperial units Unidades Imperiales - - M128 / 9X board - - - - - 9XR - - - - - 9XR with M128 chip - - - - - Gruvin9x board / 9X - - - - - MEGA2560 board - - - - - Sky9x board / 9X - - - - - - + + + Bluetooth interface Interfaz Bluetooth - - - - - - - - - + + + + + + + + + Global variables Variables globales - - + + Support for SD memory card Soporte para tarjetas de memoria SD - + Support for DSM2 modules using ppm instead of true serial Soporte para módulos DSM2 que usan PPM en lugar de true serial - - - + + + Enable HELI menu and cyclic mix support Activar menú HELI y el soporte de mezcla de cíclico - - + Warning Aviso - - EEPROM saved with these warnings: - EEPROM guardado con estos avisos: - - - + Simulator for this firmware is not yet available El simulador para este firmware ya no está disponible - - th9x on this board doesn't have Rotary Encoders - th9x en esta placa no tiene Rotary Encoders + + Switch + - + + Switch + + + + + cannot be exported on this board! + + + + Source %1 cannot be exported on this board! - + OpenTX only accepts %1 points in all curves OpenTx solo aceta %1 puntos en todas las curvas - + OpenTx only accepts %1 points in all curves OpenTx solo aceta %1 puntos en todas las curvas - - - - - + + + + + + OpenTX on this board doesn't accept this function OpenTX en esta placa no acepta esa función - + OpenTX doesn't accept this telemetry protocol OpenTX en esta placa no acepta este protocolo de telemetría - - - + + + OpenTX doesn't accept this radio protocol OpenTX en esta placa no acepta este protocolo de radio - + OpenTX doesn't allow this number of channels OpenTX en esta placa no acepta este número de canales - + Trim disabled Trim desactivado - + Own Trim Trim propio - + Use Trim from Flight mode %1 Usar Trim para el modo de vuelo %1 - + Use Trim from Flight mode %1 + Own Trim as an offset Usar Trim para el modo de vuelo %1 + Trim propio com un compensador - + FW: %1 - + Pict: %1 - + Profile image Nombre de Perfil - - Simultaneous usage of expo and curves is no longer supported in OpenTX - El uso simultáneo de exponenciales y curvas no está soportado en OpenTX - - - + Thank you for upgrading to OpenTX 2.0. This is a major upgrade that adds and modifies a lot of things, so please make sure that you read release notes carefully to learn about the changes, and thoroughly check each of your models for proper function. The OpenTX Team. @@ -8305,98 +8420,496 @@ The OpenTX Team. El equipo OpenTX. - - - - - + + + + + Synchronization error - + No SD directory configured! - + No Radio connected! - + GV GV - + -%1 - - + + The directory '%1' doesn't exist! - + Create '%1' failed - + Copy '%1' to '%2' failed - + Open '%1' failed - + Write '%1' failed - - - + + + + + + + Error Error - + Cannot write file %1: %2. No se puede escribir el archivo %1: %2. - + Companion Companion - + <b><u>WARNING!</u></b><br>This will reset the fuses of %1 to the factory settings.<br>Writing fuses can mess up your radio.<br>Do this only if you are sure they are wrong!<br>Are you sure you want to continue? <b><u>¡AVISO!</u></b><br>Esto reseteará los fuses de %1 a los ajustes de fábrica.<br>Escribir fuses puede estropear tu radio.<br>¡Haz esto sólo si estás seguro que están mal!<br>¿Estás seguro de continuar? - - + + Could not delete temporary file: %1 - - Radio type + + Unable to find Horus radio SD card! - - Which radio type do you want to simulate? + + Conversion error on field %1 + + + + + Negative span + Amplitud negativa + + + + Mid value + Valor medio + + + + Positive span + Amplitud positiva + + + + + Models + Translators do NOT use accent for this, this is the default category name on Horus. + + + + + Positive + Positivo + + + + Negative + Negativo + + + + Select a data file + + + + + Select Data Directory + + + + + Select SD Card Image Folder + + + + + Available profiles: + + + + + ID: + + + + + Name: + + + + + Available radios: + + + + + WARNING: couldn't initialize SDL: +%1 + + + + + ERROR: No simulator libraries available. + + + + + Radio profile ID or Name to use for simulator. + + + + + Radio type to simulate (usually defined in profile). + + + + + show this help text + + + + + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] + + + + + Options: + + + + + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. + Profile ID: [%1]; Radio ID: [%2]; +Data File: [%3] + + + + + ERROR: Radio profile or simulator firmware not found. +Profile ID: [%1]; Radio ID: [%2] + + + + + Error reading %1: %2 + + + + + Cannot save EEPROM + + + + + + Cannot open file %1: +%2. + + + + + + + Error writing file %1: +%2. + Error escribiendo el archivo %1: +%2. + + + + Invalid binary EEPROM file %1 + + + + + Can't extract RADIO/radio.bin + + + + + Can't extract RADIO/models.txt + + + + + Can't extract %1 + + + + + Unable to open %1: %2 + + + + + Invalid EEPROM file %1 + + + + + Invalid EEPROM File %1 + Archivo EEPROM inválido %1 + + + + + Error opening file %1: +%2. + Error abriendo el archivo %1: +%2. + + + + Error opening OTX archive %1 + + + + + Error initializing OTX archive writer + + + + + Error creating OTX file %1: +%2. + + + + + Error creating OTX archive + + + + + Error adding %1 to OTX archive + + + + + Error opening file %1 in write mode: +%2. + + + + + Unable to find file %1! + ¡No es posible encontrar el archivo %1! + + + + QxtCommandOptions + + + sets the application GUI style + + + + + sets the application stylesheet + + + + + restores the application from an earlier session + + + + + displays debugging information about widgets + + + + + use right-to-left layout + + + + + never grab the mouse or keyboard + + + + + grab the mouse/keyboard even in a debugger + + + + + run in synchronous mode for debugging + + + + + use Direct3D by default + + + + + sets the X11 display + + + + + sets the geometry of the first window + + + + + sets the default font + + + + + sets the default background color + + + + + sets the default foreground color + + + + + sets the default button color + + + + + sets the application name + + + + + sets the application title + + + + + sets the X11 visual type + + + + + limit the number of colors on an 8-bit display + + + + + use a private color map + + + + + sets the input method server + + + + + disable the X Input Method + + + + + sets the style used by the input method + + + + + + option "%1" not found + + + + + Short options cannot have optional parameters + + + + + positional() called before parse() + + + + + unrecognized() called before parse() + + + + + count() called before parse() + + + + + value() called before parse() + + + + + parameters() called before parse() + + + + + unrecognized parameters: + + + + + %1 requires a parameter + + + + + RadioKnobWidget + + + Right-double-click to reset to center. @@ -8418,10 +8931,100 @@ El equipo OpenTX. + + RadioOutputsWidget + + + Form + + + + + View: + + + + + Logical Switches + Switches lógicos + + + + Global Variables + Variables globales + + + + Channel Outputs + + + + + L +o +g +i +c + + + + + G +l +o +b +a +l + + + + + C +h +a +n +n +e +l +s + + + + + RadioSwitchWidget + + + Latch/unlatch the momentary switch. + + + + + RawSwitch + + + ↑ + + + + + ↓ + + + + + - + + + + + ! + + + ReleaseNotesDialog - + Companion Release Notes Notas de la versión Companion @@ -8429,7 +9032,7 @@ El equipo OpenTX. ReleaseNotesFirmwareDialog - + OpenTX Release Notes Notas de la versión OpenTX @@ -8437,17 +9040,17 @@ El equipo OpenTX. RudderPage - + No - + Yes Si - + <br>Rudder Channel: <br>Canal del timón (Rudder): @@ -8624,7 +9227,7 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t SetupPanel - + Timer %1 @@ -8632,180 +9235,848 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t SimpleTailPage - + Elevator Channel: Canal Profundidad (Elevator): - SimulatorDialog + SimulatedUIWidget - - + + Rotary encoder click + + + + + Take Screenshot + + + + + screenshot + Simulator LCD screenshot file name prefix + + + + + SimulatedUIWidget9X + + + UP/PG-UP + + + + + [ UP ] + + + + + DN/PG-DN + + + + + [ DN ] + + + + + RIGHT/+ + + + + + [ + ] + + + + + LEFT/- + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + [ UP ]/[ DN ] or Rotary Sel. + + + + + SimulatedUIWidgetX12 + + + PG-UP + + + + + [ PgUp ] + + + + + PG-DN + + + + + [ PgDn ] + + + + + UP + + + + + [ MDL ] + + + + + DN/DEL/BKSP + + + + + [ RTN ] + + + + + LEFT + + + + + [ SYS ] + + + + + RIGHT + + + + + [ TELE ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/X + + + + + Rotary UP + + + + + +/C + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX7 + + + Taranis X7 Simulator + + + + + PG-UP + + + + + [ PAGE ] + + + + + PG-DN + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX9 + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + +/UP + + + + + [ + ] + + + + + -/DN + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ ENT ] + + + + + WHEEL/PAD SCRL + + + + + [ + ]/[ - ] + + + + + SimulatedUIWidgetX9E + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatorMainWindow + + + OpenTx Simulator + + + + + View + + + + + Radio Window + + + + + Reload... + + + + + Tools + + + + + Toolbar + + + + + Reload Lua Scripts + + + + + Reload the Lua environment on the simulated radio. + + + + + F7 + + + + + Reload Radio Data + + + + + Reload all radio data without restarting the simulator. + + + + + F9 + + + + + Key Mapping + + + + + Show keyboard maping reference. + + + + + F1 + + + + + Joystick Settings + + + + + Open joystick configuration settings dialog. + + + + + F3 + + + + + LCD Screenshot + + + + + Save a screenshot of the current simulated LCD screen. + + + + + F8 + + + + + Dock In Main Window + + + + + Show the radio in the main window or as a separate "floating" window. + + + + + Menu Bar + + + + + Show or hide the top menu bar. + + + + + Alt+M + + + + + Constrain Width + + + + + Set radio widget width to be a fixed size. + + + + + Constrain Height + + + + + Set radio widget height to be a fixed size. + + + + + ERROR: Failed to create simulator interface, possibly missing or bad library. + + + + + Alt+T + + + + + Radio Outputs + + + + + F2 + + + + + Telemetry Simulator + + + + + F4 + + + + + Trainer Simulator + + + + + F5 + + + + + Debug Output + + + + + F6 + + + + + Simulator Controls: + + + + + <tr><th>Key/Mouse</td><th>Action</td></tr> + + + + + Simulator Help + + + + + SimulatorStartupDialog + + + OpenTX Simulator - Startup Options + + + + + Simulator Startup Options: + + + + + Radio Profile: + + + + + Existing radio profiles are shown here.<br /> +Create or edit profiles using the Companion application. + + + + + Radio Type: + + + + + Existing radio simulators are shown here.<br /> +The radio type specified in the selected profile is used by default. + + + + + Data Source: + + + + + Data File: + + + + + Data Folder: + + + + + SD Image Path: + + + + + Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> +<b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! + + + + + Select data file... + + + + + + + ... + + + + + Directory containing RADIO and MODELS folders to use.<br /> +New folder(s) with default radio/model will be created here if necessary. + + + + + Select data folder... + + + + + Directory containing the SD card image to use.<br/> +The default is configured in the chosen Radio Profile. + + + + + Select SD card image folder... + + + + + Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. + + + + + File + Archivo + + + + Folder + + + + + SD Path + + + + + All files (*.*) + + + + + SimulatorWidget + + + Companion Simulator + Simulador Companion + + + + Radio Simulator (%1) + + + + + Could not determine startup data source. + + + + + Could not load data, possibly wrong format. + + + + + Data Load Error + + + + + Invalid startup data provided. Plese specify a proper file/path. + + + + + Simulator Startup Error + + + + + Error saving data: could open file for writing: '%1' + + + + + Error saving data: could not get data from simulator interface. + + + + + An unexpected error occurred while attempting to save radio data to file '%1'. + + + + + Data Save Error + + + + Warning - Aviso + Aviso - - Joystick enabled but not configured correctly - El joystick está activado con no está correctamente configurado - - - + Cannot open joystick, joystick disabled - No se puede abrir el joystick, joystick desactivado + No se puede abrir el joystick, joystick desactivado - - Simulating Radio (%1) - Simulación de Radio (%1) - - - - - Outputs - Salidas - - - + Firmware %1 error: %2 - Firmware %1 error: %2 + Firmware %1 error: %2 - SimulatorDialog9X + SliderWidget - - Companion Simulator - Simulador Companion - - - - - - - Right Double Click to Reset - Doble click derecho para Resetear - - - - - Hold X - Mantener X - - - - - Fix X - Fijar X - - - - - Fix Y - Fijar Y - - - - - Hold Y - Mantener Y - - - - BEEP - BEEP - - - - 9x Simulator - Simulador 9x - - - - Outputs - Salidas - - - - Outputs2 - Salidas2 - - - - Gvars - - - - - SimulatorDialogTaranis - - - Companion Simulator - Simulador Companion - - - - Outputs2 - Salidas2 - - - - Gvars - Gvars - - - - S3 + + Right-double-click to reset to center. - - - S4 - - - - - - Hold Y - Mantener Y - - - - - Fix Y - Fijar Y - - - - - Fix X - Fijar X - - - - - Hold X - Mantener X - - - - - - - Right Double Click to Reset - Doble click derecho para Resetear - - - - Taranis Simulator - SimuladorTaranis - - - - Outputs - Salidas - SplashLibraryDialog @@ -8816,27 +10087,27 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t - + Splash Library - page %1 of %2 LIbreria de pantallas de inicio - página %1 de %2 - + Warning Aviso - + Invalid image in library %1 Imagen inválida en la librería %1 - + Information Información - + No valid image found in library, check your settings No se ha encontrado una imagen válida en la librería, comprueba tus ajustes @@ -8844,7 +10115,7 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t StandardPage - + Channel %1 Canal %1 @@ -8852,43 +10123,41 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t SyncProcess - + %1/%2 files - + Create directory %1 - - Copy %1 to %2 - + + Copy %1 to %2 - - Write %1 - + + Write %1 TailPage - + Rudder Channel: <br>Canal del timón (Rudder): - + Elevator Channel: Canal Profundidad (Elevator): - + Only one channel still available!<br>You probably should configure your model without using the wizard. @@ -8896,22 +10165,22 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t TailSelectionPage - + Elevator and Rudder Profundidad y timón - + Only Elevator Solo profundidad - + V-tail Cola-V - + Tail Type: Tipo de cola: @@ -9191,7 +10460,7 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t Meters (m or ft) Metros (m o pies) - + Temp (°) Temp (°) @@ -9207,7 +10476,7 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t miliAmperios (mA) - + Range Rango @@ -9220,22 +10489,22 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t Personalizar tipo pantalla - + None Ninguno - + Numbers - + Bars Barras - + Script @@ -9263,99 +10532,99 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t TelemetryPanel - + FrSky S.PORT - + FrSky D - + FrSky D (cable) - + Telemetry screen %1 Pantalla telemetría %1 - + Low Alarm Alarma Baja - + Critical Alarm Alarma crítica - + Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (no soportado) - + Alti - + Alti+ - + VSpeed - - - + + + A1 - - - + + + A2 - - + + A3 - - + + A4 - - + + FAS - + Cells - + --- @@ -9514,12 +10783,12 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t ft - + °C - + °F @@ -9541,26 +10810,36 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t + mW + + + + dBm - - g - - - - ° + g - mL + ° + Rad + + + + + mL + + + + US fl.Oz. @@ -9570,57 +10849,57 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t - + RPM - + Precision - + Ratio - + Blades Palas - + Offset Offset - + Multiplier - + Auto Offset - + Filter - + Persistent - + Positive Positivo - + Logs @@ -9628,22 +10907,22 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t TelemetrySensorPanel - + Lowest - + Cell %1 - + Highest - + Delta @@ -9651,240 +10930,560 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t TelemetrySimulator - + Telemetry Simulator - - Vario Altitude - - - - - V-ALT - - - - - Vario Vertical Speed - - - - - V-VSPD - - - - - ACCZ - - - - - GPS Time - Hora GPS - - - - GPS-T - - - - - ACCX - - - - - GPS Lat/Lon - - - - - GPS-LL - - - - + VFAS - - FAS-V - - - - - GPS Speed - - - - - GPS-S - - - - - CELLS - - - - - ACCY - - - - - GPS Course - - - - - GPS-C - - - - - GPS Altitude - - - - - GPS-A - - - - - CURRENT - - - - - FAS-C - - - - - 30 - 30 - - - + RSSI - - 75 - 75 - - - + SWR - - FR_ID_AIR_SPEED - - - - - ASPD - - - - + A1 - + A2 - - A3 + + Simulate + Simular + + + + Replay SD Log File - - A4 + + Replay rate - - Temperature 1 + + Load - - T1 + + |> + + + + + <| + + + + + > + + + + + <- - Temperature 2 + X - - T2 + + Row # +Timestamp - + + 1/5x + 1/5x + + + + 5x + 5x + + + + No Log File Currently Loaded + + + + + + + V / ratio + + + + + Db + + + + + RxBt + + + + + + + + + + + + + + + + + <html><head/><body><p><br/></p></body></html> + + + + + Tmp1 + + + + + A3 + + + + + A4 + + + + + Tmp2 + + + + + Fuel + Combustible + + + + °C + + + + + ml + + + + + Deg. C + + + + + % + + + + + + Meters + + + + + Alt + + + + + VSpd + + + + + m/s + + + + + Fuel Qty + + + + + + km/h + + + + + Hdg + + + + + ASpd + + + + + + + G + + + + + GPS + + + + + Lat,Lon +(dec.deg.) + + + + + AccX + + + + + dd-MM-yyyy +hh:mm:ss + + + + + Date + + + + + Amps + + + + + AccZ + + + + + GAlt + + + + + + Volts + + + + + Cels + + + + + Curr + + + + + AccY + + + + + GSpd + + + + + Degrees + + + + + RPM - - FUEL - - - - + When enabled, sends any non-blank values as simulated telemetry data. - - simulate + + Log File - - Instance + + LOG Files (*.csv) - - 2 - 2 + + ERROR - invalid file + + + + + Templates + + + Simple 4-CH + - - <html><head/><body><p>Start with <span style=" font-style:italic;">0x</span> for hex, <span style=" font-style:italic;">0</span> for octal, otherwise decimal.<br/>Numeric entry only. Blank values are not sent.</p></body></html> + + T-Cut + + + + + Sticky T-Cut + + + + + V-Tail + Cola-V + + + + Elevon\Delta + + + + + Heli Setup + + + + + Heli Setup with gyro gain control + + + + + Gyro gain control + + + + + Heli Setup (Futaba's channel assignment style) + + + + + Heli Setup with gyro gain control (Futaba's channel assignment style) + + + + + Gyro gain control (Futaba's channel assignment style) + + + + + Servo Test + + + + + MultiCopter + + + + + Use Model Config Wizard + + + + + Apply Template? + + + + + Apply template "%1"? + + + + + + + + + + + RUD + + + + + + + + + + + + + + ELE + + + + + + + THR + + + + + + + + + + + + AIL + + + + + + + + AIL2 + + + + + + + + ELE2 + + + + + + + + + + FLAPS + + + + + + + + + + FLAP%1 + + + + + + + + PITCH + + + + + + + + + + + + GYRO + + + + + + SPOIL + + + + + + SPOIL%1 + + + + + + RUD2 + + + + + + Clear Mixes? + ¿Limpiar mezclas? + + + + Really clear existing mixes on CH6? + + + + + Really clear existing mixes on CH5? ThrottlePage - + Yes Si - + No No - + <br>Throttle Channel: <br>Canal de Acelerador: @@ -9905,37 +11504,37 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t TimerPanel - + Silent Silencio - + Beeps - + Voice Voz - + Haptic Reproducir Haptic - + Not persistent No persistente - + Persistent (flight) Persistente (vuelo) - + Persistent (manual reset) Persistente (reset manual) @@ -10066,33 +11665,94 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t TrainerSimulator - + Trainer simulator + + TreeModel + + + Index + + + + + Name + Nombre + + + + Size + + + VTailPage - + First Tail Channel: Primer Canal de cola: - + Second Tail Channel: Segundo Canal de cola: + + VirtualJoystickWidget + + + Hld Y + + + + + Hold Vertical stick position. + + + + + Fix Y + Fijar Y + + + + Prevent Vertical movement of stick. + + + + + Fix X + Fijar X + + + + Prevent Horizontal movement of stick. + + + + + Hld X + + + + + Hold Horizontal stick position. + + + WingtypeSelectionPage - + Standard Wing Ala estandar - + Flying Wing / Deltawing Ala volante/Ala delta @@ -10100,273 +11760,273 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t WizardDialog - + Model Wizard Asistente Modelos - + Model Type Tipo Modelo - + Enter model name and model type. Introduce nombre de modelo y tipo de modelo. - + Throttle Acelerador - + Has your model got a motor or an engine? ¿Tiene tu modelo motor? - + Wing Type Tipo de Ala - + Is your model a flying wing/deltawing or has it a standard wing configuration? ¿Es tu modelo un ala volante/ala delta o tiene una configuración estándar de ala? - + Ailerons Alerones - + Has your model got ailerons? ¿Tiene tu modelo alerones? - + Flaps - + Has your model got flaps? ¿Tiene tu modelo flaps? - + Airbrakes Aerofrenos - + Has your model got airbrakes? ¿Tiene tu modelo aerofrenos? - + Flying-wing / Delta-wing Ala volante / Ala delta - + Select the elevons channels Selecciona los canales de los elevones - + Rudder Timón - + Does your model have a rudder? ¿Tiene tu modelo timón? - + Tail Type Tipo de cola - + Select which type of tail your model is equiped with. Selecciona el tipo de cola que lleva tu modelo. - - + + Tail Cola - - + + Select channels for tail control. Seleciona los canales para el control de cola. - + V-Tail Cola-V - + Select elevator channel. Selecciona el canal de profundidad. - + Cyclic Cíclico - + Which type of swash control is installed in your helicopter? ¿Que tipo de plato está instalado en tu helicóptero? - + Tail Gyro Giróscopo cola - + Has your helicopter got an adjustable gyro for the tail? ¿Tiene tu helicóptero giróscopo ajustable para la cola? - + Rotor Type Tipo Rotor - + Has your helicopter got a flybar? ¿Tiene tu helicóptero flybars? - - + + Helicopter Helicóptero - - + + Select the controls for your helicopter Selecciona los controles de tu helicóptero - + Multirotor - + Select the control channels for your multirotor Selecciona los canales para tu multirotor - + Model Options Opciones Modelo - + Select additional options Selecciona opciones adicionales - + Save Changes Guardar Cambios - + Manually check the direction of each control surface and reverse any channels that make controls move in the wrong direction. Remove the propeller/propellers before you try to control your model for the first time.<br>Please note that continuing removes all old model settings! Comprobar manualmente la dirección de cada control de superficie y los reversos de cualquier canal para que el control de movimiento no se erroneo. Saca la hélice/hélices antes de intentar controlar tu modelo por primera vez.<br> ¡Por favor tenga en cuenta eliminar los ajustes viejos! - + Enter a name for your model and select model type. Introduce un nombre para tu modelo y selecciona el tipo de modelo. - + Select the receiver channel that is connected to your ESC or throttle servo.<br><br>Throttle - Spektrum: CH1, Futaba: CH3 Selecciona el canal del receptor que está conectado a tu ESC o servo de acelerador.<br><br>Acelerador - Spektrum: CH1, Futaba: CH3 - + Most aircraft have a main wing and a tail with control surfaces. Flying wings and delta winged aircraft only have a single wing. The main control surface on a standard wing controls the roll of the aircraft. This surface is called an aileron.<br>The control surface of a delta wing controls both roll and pitch. This surface is called an elevon. La mayoría de los aviones tienen un ala principal y una cola con controles de superficie. Volando alas y alas delta solo hay un ala simple. El control principal de superficie en un ala estandar controla el alabeo del avión. Esta superficie se llama alerón.<br> El control de superficie de un ala delta controla ambos alabeo y cabeceo. Esta superficie se llama elevon. - + Models use one or two channels to control the ailerons.<br>A so called Y-cable can be used to connect a single receiver channel to two separate aileron servos. If your servos are connected by a Y-cable you should select the single-servo option.<br><br>Aileron - Spektrum: CH2, Futaba: CH1 Los modelos usan 1 o 2 canales para controlar los alerones.<br>Un cable en Y se puede usar para conectar un solo canal del receptor a dos servos separados de los alerones. Si usas servos conectados por un cable Y debes seleccionar la opcion de servo único.<br><br> Alerón Spektrum: CH2, Futaba CH1 - + This wizard assumes that your flaps are controlled by a switch. If your flaps are controlled by a potentiometer you can change that manually later. Este asistente asume que tus flaps estan controlados por un switch. Si tus flaps están controlados por un potenciómetro lo puedes cambiar manualmente mas tarde. - + Air brakes are used to reduce the speed of advanced sail planes.<br>They are very uncommon on other types of planes. Los aerofrenos son usados para reducir la velocidad de avance en los veleros.<br>No son muy comunes en otro tipo de aviones. - + Models use two channels to control the elevons.<br>Select these two channels Los modelos usan dos canales para controlar los elevones.<br>Selecciona esos dos canales - + Select the receiver channel that is connected to your rudder.<br><br>Rudder - Spektrum: CH4, Futaba: CH4 Selecciona el canal del receptor que está conectado al timón.<br><br>Timón - Spektrum: CH4, Futaba: CH4 - + Select the tail type of your plane. Selecciona el tipo de cola de tu avión. - + Select the Rudder and Elevator channels.<br><br>Rudder - Spektrum: CH4, Futaba: CH4<br>Elevator - Spektrum: CH3, Futaba: CH2 Selecciona los canales de timón y de profundidad.<br><br>Timón - Spektrum: CH4, Futaba: CH4<br>Profundidad - Spektrum: CH3, Futaba: CH2 - + Select the Elevator channel.<br><br>Elevator - Spektrum: CH3, Futaba: CH2 Selecciona el canal de profundidad<br><br>Profundidad - Spektrum: CH3, Futaba: CH2 - - - - - - - + + + + + + + TBD. - + Select the control channels for your multirotor.<br><br>Throttle - Spektrum: CH1, Futaba: CH3<br>Yaw - Spektrum: CH4, Futaba: CH4<br>Pitch - Spektrum: CH3, Futaba: CH2<br>Roll - Spektrum: CH2, Futaba: CH1 Selecciona el control de canales de tu multirotor.<br><br>Gas - Spektrum: CH1, Futaba: CH3<br>Yaw - Spektrum: CH4, Futaba: CH4<br>Pitch - Spektrum: CH3, Futaba: CH2<br>Roll - Spektrum: CH2, Futaba: CH1 - + There is no help available for the current page. No hay ayuda disponible en la página actual. - + Model Wizard Help Ayuda asistente de modelo @@ -10374,37 +12034,37 @@ Si está marcado el acelerador será invertido. El ralentí será delante, el t WizardPrinter - + Plane Avión - + Multicopter Multicóptero - + Helicopter Helicóptero - + Model Name: Nombre Modelo: - + Model Type: Tipo Modelo: - + Options: Opciones: - + Channel %1: Canal %1: @@ -10565,44 +12225,44 @@ Por favor solamente usa esto si sabes lo que estás haciendo. No hay control de Puerto serie sam-ba - + DFU-UTIL Configuration Configuración DFU-UTIL - + SAM-BA Configuration Configuración SAM-BA - + AVRDUDE Configuration Configuración AVRDUDE - - - + + + Select Location Seleccionar localización - + List available programmers Lista de programadores disponibles - + Avrdude help - + Companion - + <b><u>WARNING!</u></b><br>Normally CPU type is automatically selected according to the chosen firmware.<br>If you change the CPU type the resulting eeprom could be inconsistent. <b><u>¡AVISO!</u></b><br>Normalmente el tipo de CPU ees automáticamente elegida para el tipo de firmware.<br>Si cambias el tipo de CPU el eeprom resultante podria ser inconsistente. @@ -10675,75 +12335,75 @@ m2560 para las placas v4.1 - - - - + + + + Error - + Open Firmware File Abrir archivo de Firmware - + Can not load embedded image from firmware file %1. No se pueden cargar la imagen incrustada el archivo de firmware %1. - + Open Image to load Abrir imagen para cargar - + Images (%1) Imagenes (%1) - + Cannot load the image file %1. No se puede cargar el archivo de imagen %1. - + Cannot load profile image %1. No se puede cargar el archivo de perfil %1. - + Cannot load the library image %1. No se puede cargar la librería de imagen %1. - + File Saved Archivo Guardado - + The image was saved to the file %1 La imagen ha sido guardada al archivo %1 - + Image Refresh Error Error en el refresco de Imagen - + Failed to refresh image from file %1 Fallo al refrescar la imagen del archivo %1 - + File Save Error Error Guardado de Archivo - + Failed to write image to %1 Fallo al escribir la imagen a %1 @@ -10756,17 +12416,17 @@ m2560 para las placas v4.1 Descargando: - + Unable to save the file %1: %2. No se puede guardar el archivo %1: %2. - + Companion Companion - + Download failed: %1. Descarga fallida: %1. @@ -10779,231 +12439,155 @@ m2560 para las placas v4.1 Configurar Joystick - + Ch2 - - - - - - - - - Not Assigned - No Asignado - - - - - - - - - - - Right Vertical - Derecha Vertical - - - - - - - - - - - Right Horizontal - Derecha Horizontal - - - - - - - - - - - Left Vertical - Izquierda Vertical - - - - - - - - - - - Left Horizontal - Izquierda Hrizontal - - - - - - - - - - - P1 - - - - - - - - - - - - P2 - - - - - - - - - - - - P3/LS - - - - - - - - - - - - RS - - - - + Ch1 - + Ch4 - + Ch6 - + Ch3 - + Ch5 - + Ch7 - + Ch8 - + Instructions Instrucciones - + + Enable + + + + Cancel Cancelar - + + Back + + + + + Start + Comenzar + + + Next Siguiente - + Ok - - Move sticks and pots in every direction making full movement -Press next when finished - Mueve los sticks y los potenciómetros en cada dirección haciendo movientos completos -Presiona siguiente cuando finalices + + Not Assigned + - - + + Stick + + + + + Knob/Slider %1 + + + + + No joysticks found + No se han encopntrado joysticks + + + Error - + Cannot open joystick. No se puede abrir el joystick. - - Place sticks and pots in middle position. -Press next when done - Sitúa los sticks y los potenciómetros en la posición media. -Presiona siguiente cuando esté hecho - - - - Map joystick channels to controls using comboboxes. -Press next when done - Mapa de canales de joystick a controles utilizando comboxes. -Presiona siguiente cuando esté hecho - - - - Check inversion checkbox to get maximum at top-right position. -Press next when done - Marca la casilla de inversión para obtener la posición superior derecha máxima. -Presiona siguiente cuando esté hecho - - - - Press ok to save configuration -Press cancel to abort joystick calibration - Presiona ok para guardar la configuración -Presiona cancelar para abortar la calibración del joystick - - - - Duplicated stick assignment + + Press the Start button to start the stick range calibration procedure. +You may change the channel assignments or inversion at any time. - - - mdiChild - - Simulate Tx - Simular TX + + Move sticks and pots in every direction making full movement +Press Next when finished + + + + + Place sticks and pots in middle position. +Press Next when done + + + + + Map joystick channels to controls using comboboxes. +Press Next when done. + + + + + Check inversion checkbox to if necessary to reverse direction. +Press Next when done. + + + + + Press OK to save configuration +Press Cancel to abort joystick calibration without saving. + + + + + Warning + Aviso + + + + Calibration not complete, save anyway? + diff --git a/companion/src/translations/companion_fi.ts b/companion/src/translations/companion_fi.ts index 391c02bc4..ed14c66b1 100644 --- a/companion/src/translations/companion_fi.ts +++ b/companion/src/translations/companion_fi.ts @@ -1,30 +1,30 @@ - + AileronsPage - + No Ei - + Yes, controlled by a single channel Kyllä, ohjataan yhdellä kanavalla - + Yes, controlled by two channels Kyllä, ohjataan kahdella kanavalla - + <br>First Aileron Channel: <br>1. siiveke kanava: - + Second Aileron Channel: 2. siiveke kanava: @@ -32,27 +32,27 @@ AirbrakesPage - + No Ei - + Yes, controlled by a single channel Kyllä, ohjataan yhdellä kanavalla - + Yes, controlled by two channels Kyllä, ohjataan kahdella kanavalla - + <br>First Airbrake Channel: <br>1. lentojarru kanava: - + Second Airbrake Channel: 2. lentojarru kanava: @@ -69,15 +69,6 @@ Radio Profile Radio profiili - - - - - - - Open Folder - Avaa kansio - Default Channel Order @@ -323,6 +314,20 @@ Tila 4: A T E R S Ka Ko P + + + + + + + Select Folder + + + + + Select Executable + + Use OpenTX firmware nightly builds @@ -426,11 +431,6 @@ Voi olla eri kun firmwaren kieli Files to keep Tiedostoja - - - Find Executable - Avaa tiedosto - Google Earth Executable @@ -527,498 +527,149 @@ Voi olla eri kun firmwaren kieli Muista simulaattorin kytkimien asennot - + My Radio Minun radio - + Select your snapshot folder Valitse kansioi kuville - - + + No joysticks found Joystickia ei löydy - + EMPTY: No radio settings stored in profile TYHJÄ: Ei radion asetuksia tallennettu profiiliin - + AVAILABLE: Radio settings of unknown age TARJOLLA: Radion asetukset, voi olla vanhoja - + AVAILABLE: Radio settings stored %1 TARJOLLA: Radion asetukset %1 - + Select your library folder Valitse kansio kirjastolle - - + + Select your Models and Settings backup folder Valitse kansio mallien ja asetusten varmuuskopioille - + Select Google Earth executable Valitse Google Earth tiedosto - + Select the folder replicating your SD structure Valitse kansio mihin "monistetaan" SD muistikortin kansio - + Not possible to remove profile Profiilia ei voida poistaa - + The default profile can not be removed. Nykyistä profiilia ei voida poistaa. - + Open Image to load Avaa kuva latausta varten - + Images (%1) Kuvia (%1) - - Calibration - - - Form - - - - - SQ - - - - - SR - - - - - LS2 - LS2 - - - - SP - - - - - SO - - - - - S4 - S4 - - - - RS - RS - - - - SB - SB - - - - Serial Port - Sarja portti - - - - - - - - - - - - - Beeper volume - -0 - Quiet. No beeps at all. -1 - No Keys. Normal beeps but menu keys do not beep. -2 - Normal. -3 - Loud. -4 - Extra loud. - Piipperin voluumi - -0 -Äänetön ( ei piippaa ). -1 -Ei nap ( normaalisti mutta ei menun napeista). -2 -Normaalisti. -3 -Voimakas. -4 -Erittäin voimakas. - - - - OFF - Pois - - - - S-Port Mirror - S-Portti peilik - - - - Telemetry - Telemetria - - - - SBUS Trainer - - - - - Debug - Korjaus - - - - Rud - PER - - - - - Mid value - Keski alue - - - - Pot. 4 - Pot- 4 - - - - Pot. 3 - Pot. 3 - - - - Pot. 2 - Pot. 2 - - - - Pot. 1 - Pot. 1 - - - - PPM 1 - PPM 1 - - - - Stick 3 - Tikku 3 - - - - - Negative span - Negatiivinen liike - - - - - Positive span - Positiivinen liike - - - - Stick 1 - Tikku 1 - - - - PPM 2 - PPM 2 - - - - Stick 2 - Tikku 2 - - - - Stick 4 - Tikku 4 - - - - v - v - - - - PPM Multiplier - PPM Kerroin - - - - PPM 3 - PPM 3 - - - - PPM 4 - PPM 4 - - - - Battery Offset - - - - - Current Offset - - - - - S1 - S1 - - - - S2 - S2 - - - - S3 - S3 - - - - SA - SA - - - - Ele - KOR - - - - Ail - SII - - - - Thr - KAA - - - - SC - SC - - - - LS - LS - - - - SD - SD - - - - SE - SE - - - - SF - SF - - - - SG - SG - - - - SH - SH - - - - SI - - - - - SJ - - - - - SK - - - - - SL - - - - - SM - - - - - SN - - - - - RS2 - - - - - Bluetooth - - - - - CalibrationPanel - - - - - None - Ei mitään - - - - 2 Positions Toggle - - - - - 2 Positions - - - - - 3 Positions - - - - - Pot with detent - - - - - Multipos switch - - - - - Pot without detent - - - - - Slider with detent - - - Channels - + Name Nimi - + Min Min - + Max Max - + Subtrim Alitrimmi - + Direction Suunta - + Curve Käyrä - + PPM Center PPM keski - + Linear Subtrim Lineaarinen alitrimmi - - Channel %1 - Kanava %1 + + CH%1 + CH%1 - + --- --- - + INV KÄÄNT + + CompanionMacros + + + files + + + + + Radio and Models settings + + + CompareDialog @@ -1052,17 +703,17 @@ Voi olla eri kun firmwaren kieli Tulosta tiedostoon - + No name Ei nimeä - + Print Document Tulosta dokumentti - + Select PDF output file Valitse PDF tiedosto @@ -1070,7 +721,7 @@ Voi olla eri kun firmwaren kieli ConclusionPage - + OK, I understand. OK, Ymmärrän. @@ -1078,42 +729,42 @@ Voi olla eri kun firmwaren kieli ContributorsDialog - + OpenTX Contributors - + Main Developers - + Other contributors - + Companies and projects who have donated to OpenTX - + People who have donated to OpenTX - + Honors go to Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) Kiitokset: Rafal Tomczak(RadioClone), Thomas Husterer (th9x) sekä Eriz Raviv (er9x ja eePe) - + OpenTX Blacklist - + monthly @@ -1121,24 +772,24 @@ Voi olla eri kun firmwaren kieli CopyProcess - - - + + + Error Virhe - + Write error Kirjoitus virhe - + Cannot write %1 (reason: %2) - + Cannot open %1 (reason: %2) @@ -1146,22 +797,22 @@ Voi olla eri kun firmwaren kieli CurveGroup - + Diff Ero - + Expo Expo - + Func Toiminto - + Curve Käyrä @@ -1250,72 +901,72 @@ Voi olla eri kun firmwaren kieli Käyrän nimi - + Curve %1 Käyräi %1 - + %1 points %1 pisteet - + Linear Suora - + Single Expo yks expo - + Symmetrical f(x)=-f(-x) Symmetrinen f(x)=-f(-x) - + Symmetrical f(x)=f(-x) Symmetrinen f(x)=f(-x) - + Copy - + Paste - + Clear - + Clear all curves - + Are you sure you want to reset curve %1? - + Are you sure you want to reset all curves? - + Editing curve %1 Muutetaan käyrää %1 - + Not enough free points in EEPROM to store the curve. Ei vapaata tilaa EEPROMissa tallentaa käyrää. @@ -1323,87 +974,87 @@ Voi olla eri kun firmwaren kieli CustomFunctionsPanel - + Switch Kytkin - + Action Toiminto - + Parameters Parametrit - + Enable Päälle - + SF%1 SF%1 - + GF%1 - + ON ON - + Error Virhe - + Unable to find sound file %1! Äänitiedostoa ei löydy %1! - + &Delete &Poista - + Delete Poista - + &Copy &Kopio - + Ctrl+C Ctrl+C - + &Cut &Leikkaa - + Ctrl+X Ctrl+X - + &Paste &Liitä - + Ctrl+V Ctrl+V @@ -1411,22 +1062,22 @@ Voi olla eri kun firmwaren kieli CyclicPage - + 90 90 - + 120 120 - + 120x 120x - + 140 140 @@ -1434,98 +1085,174 @@ Voi olla eri kun firmwaren kieli DebugOutput - + Debug Output + + + <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> + + + + + Filter: + + + + + <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> +To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> + + + + + Buffer: + + + + + Number of lines to keep in display. + + + + + Filter &Help + + + + + Show information about using the filter. + + + + + Word &Wrap + + + + + Toggle word wrapping on/off. + + + + + &Clear + + + + + Clear the output window of all text. + + + + + Enable &Filter + + + + + Turn the filter on/off. + + + + + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> + + + + + Debug Console Filter Help + + EepromInterface - + Possible causes for this: - + - Eeprom is from a newer version of OpenTX - + - Eeprom is not from OpenTX - + - Eeprom is not from Th9X - + - Eeprom is not from Gruvin9X - + - Eeprom is not from ErSky9X - + - Eeprom is not from Er9X - + - Eeprom size is invalid - + - Eeprom file system is invalid - + - Eeprom is from a unknown board - + - Eeprom is from the wrong board - + - Eeprom backup not supported - + - Something that couldn't be guessed, sorry - + Warning: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - + Warnings! @@ -1533,12 +1260,12 @@ Voi olla eri kun firmwaren kieli ElevonsPage - + <br>First Elevon Channel: <br>1. korkeusper kanava: - + Second Elevon Channel: 2. korkeusper kanava: @@ -1655,30 +1382,50 @@ Jos on tyhjä, katsotaan tulon olen ON tilassa kokoajan. Nimi - + Edit %1 Muuta %1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + FblPage - + Throttle Channel: Kaasun kanava: - + Yaw Channel: Yaw kanava: - + Pitch Channel: Pitch kanava: - + Roll Channel: Roll kanava: @@ -1731,27 +1478,27 @@ Voi olla eri kun firmwaren kieli FlapsPage - + No Ei - + Yes, controlled by a single channel Kyllä, ohjataan yhdellä kanavalla - + Yes, controlled by two channels Kyllä, ohjataan kahdella kanavalla - + <br>First Flap Channel: <br>1. laippojen kanava: - + Second Flap Channel: 2. laippojen kanava: @@ -1760,7 +1507,7 @@ Voi olla eri kun firmwaren kieli FlashEEpromDialog - + Write Models and Settings to Radio Kirjoita mallit ja asetukset lähettimeen @@ -1776,7 +1523,6 @@ Voi olla eri kun firmwaren kieli - Allows Companion to write to older version of the firmware Anna Companionin kirjoittaa myös vanhaan firmwareen @@ -1785,6 +1531,11 @@ Voi olla eri kun firmwaren kieli Check Firmware compatibility Tarkista firmwaren yhteensopivuus + + + <html><head/><body><p>Saves a dated copy of your eeprom to the backup folder you specified in the Companion settings before writing the current model to the radio.</p></body></html> + + Backup before Write @@ -1821,106 +1572,66 @@ Voi olla eri kun firmwaren kieli Kirjoita lähettimeen - + Current profile: %1 - + Choose Radio Backup file Valitse Lähettimen varmuuskopio tiedosto - - - - - - - - - - + + Error Virhe - - - Unable to find file %1! - Ei löydy tiedostoa %1! - - - - - - Error opening file %1: -%2. - Virhe avattaessa tiedostoa %1: -%2. - - - - - Invalid Models and Settings File %1 - Huono malli ja asetus tiedosto %1 - - - - Error reading file %1: -%2. - Virhe luettaessa tiedostoa %1: -%2. - - Invalid Models and Settings file %1 - - - - - - - + + + Warning Varoitus - + Wrong radio calibration data in profile, Settings not patched Väärä radion kalibraatio data profiilissa, asetuksia ei ole korjattu - + Wrong radio setting data in profile, Settings not patched Väärä radion asetus data profiilissa, asetuksia ei ole korjattu - - + Cannot write file %1: %2. - + Ei voi kirjoittaa tiedostoa %1: +%2. - + Error writing file %1: %2. Virhe kirjottaessa tiedostoa %1: %2. - + The radio firmware belongs to another product family, check file and preferences! Lähettimen firmware kuuluu toiselle lähettin mallille, tarkista oikea tiedosto ja asetukset! - + The radio firmware is outdated, please upgrade! Firware on vanhaa versio, päivitä se uudempaan! - + Cannot check Models and Settings compatibility! Continue anyway? Ei voi varmistaa että mallit ja asetukset täsmää laitteistoon. Jatketaanko silti ? @@ -1998,119 +1709,119 @@ Voi olla eri kun firmwaren kieli Kirjoita lähettimeen - + Open Firmware File Avaa firmware tiedosto - - - + + + Warning Varoitus - + %1 may not be a valid firmware file %1 ei ehkä ole oikea firmware tiedosto - - - - + + + + Error Virhe - + The firmware file is not valid. Tämä ei ole oikea firmware tiedosto. - + There is no start screen image in the firmware file. Tälle firmwarelle ei ole alku ruutu kuvaa. - + Profile image %1 is invalid. Profiilin kuva %1 on väärä. - + Open image file to use as radio start screen Avaa kuva ja käytä sitä alku ruutu kuvana - + Images (%1) Kuvia (%1) - + Image could not be loaded from %1 Kuvaa ei voi ladata %1 - + The library image could not be loaded Kuvaa ei voi ladata - + Splash image not found - + Cannot save customized firmware Muutettua firmwarea ei voi tallentaa - + Write Firmware to Radio Kirjoita firmware lähettimeen - - + + Firmware check failed - + Could not check firmware from radio - + New firmware is not compatible with the one currently installed! - + Conversion failed Muutos virheellinen - + Cannot convert Models and Settings for use with this firmware, original data will be used Ei voida muuttaa malli ja asetus tietoja käymään uuteen firmwareen, alkuperäiset tiedot otetaan käyttöön - + Restore failed Palautus epäonnistui - + Could not restore Models and Settings to Radio. The models and settings data file can be found at: %1 Ei voi palauttaa malli ja asetus tietoja lähettimestä. Mallit ja asetukset löytyy tiedostosta: %1 - + Flashing done @@ -2118,47 +1829,47 @@ Voi olla eri kun firmwaren kieli FlashProcess - + Executable %1 not found - + Writing... - + Reading... - + Verifying... - + unknown - + ie: OpenTX for 9X board or OpenTX for 9XR board ie: OpenTX 9X tai OpenTX 9XR - + ie: OpenTX for M128 / 9X board or OpenTX for 9XR board with M128 chip ie: OpenTX M128 / 9X tai OpenTX 9XR M128 sirulla - + ie: OpenTX for Gruvin9X board ie: OpenTX Gruvin9X - + Your radio uses a %1 CPU!!! Please check advanced burn options to set the correct cpu type. @@ -2167,7 +1878,7 @@ Please check advanced burn options to set the correct cpu type. Tarkasta asetuksista CPU:n oikea tyyppi. - + Your radio uses a %1 CPU!!! Please select an appropriate firmware type to program it. @@ -2176,7 +1887,7 @@ Please select an appropriate firmware type to program it. Valitse oikea firmware jonka ohjelmoit. - + You are currently using: %1 @@ -2185,29 +1896,29 @@ Käytät nyt: %1 - + Your radio does not seem connected to USB or the driver is not installed!!! Please use ZADIG to properly install the driver. - + Your radio does not seem connected to USB or the driver is not initialized!!!. - + Flashing done (exit code = %1) - + Flashing done with errors - + FUSES: Low=%1 High=%2 Ext=%3 SULAKKEET: Ala=%1 Kork=%2 Lis=%3 @@ -2238,35 +1949,65 @@ Please use ZADIG to properly install the driver. FlightModePanel - + Rotary Encoder %1 ??Rotary Encoder?? %1 - + + Name + Nimi + + + + Value source + + + + + Value + Arvo + + + GVAR%1 GVAR%1 - + Popup enabled Popupit sallittu + + + &Clear + + + + + Clear + + + + + Clear all current Flight Mode properties? + + FlightModesPanel - + Flight Mode %1 Lentotila %1 - + (%1) (%1) - + (default) (oletus) @@ -2274,17 +2015,17 @@ Please use ZADIG to properly install the driver. FlybarSelectionPage - + Has Flybar ON flybar - + Flybarless EI flybar - + Flybar: Flybar: @@ -2430,13 +2171,13 @@ p, li { white-space: pre-wrap; } <p align="center" style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Proceed only if you know what you are doing.</p></body></html> - - + + Reset Radio Fuses - + Read Fuses from Radio @@ -2445,8 +2186,8 @@ p, li { white-space: pre-wrap; } GeneralEdit - General Edit - Yleiset muutokset + Radio settings + @@ -2466,48 +2207,59 @@ These will be relevant for all models in the same EEPROM. Nämä vaikuttaa kaikkiin malleihin jotka on EEPROMilla. - + Setup Asetukset - + Trainer Traineri - + Global Functions - - Hardware / Calibration + + Hardware - - + + Calibration + + + + + + Warning Varoitus - + Wrong data in profile, radio calibration was not retrieved Väärää dataa profiilissa, radion kalibraatio tietoja ei noudettu - + + Wrong data in profile, Switch/pot config not retrieved + + + + Wrong data in profile, hw related parameters were not retrieved Väärää dataa profiilissa, HW parametreja ei noudettu - + Do you want to store calibration in %1 profile<br>overwriting existing calibration? Haluatko tallentaa kalibraation %1 profiiliin<br>Vanha kalibraatio poistetaan ? - + Calibration and HW parameters saved. Kalibraatio ja HW parametrit tallennettu. @@ -2565,165 +2317,164 @@ Nämä vaikuttaa kaikkiin malleihin jotka on EEPROMilla. SG - + Timeshift from UTC Ajansiirto UTC:stä - + Voice Language Äänen kieli - + Country Code Maa koodi - + Stick reverse - + FAI Mode FAI tila - - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. FAI tilassa ei toimi: Vario, äänten toistaminen, telemetria ruutu. Tätä ei saa pois päältä radiosta. - + Adjust RTC - + Vario pitch at max Vario ääni kun max - - + + Hz Hz - + Speaker Volume Äänen voimakkuus - + Backlight Switch Taustavalon kytkin - + Sound Mode Ääni tila - + Color 1 Väri 1 - + Color 2 Väri 2 - + Speaker Pitch (spkr only) Äänen korkeus (vain kaj.) - + If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. Jos tämä arvo ei ole 0, jokainen painallus sytyttää taustavalon, sammuu valitun ajan jälkeen ( SEK). - + sec sec - + Backlight color Taustavalon väri - + Beeper Piipperi - + Speaker Kaiutin - + BeeperVoice Piippausääni - + SpeakerVoice Kaiutinääni - + Beep volume Piippaus voluumi - + Wav volume Wav voluumi - + Vario volume Vario voluumi - + Background volume Taustan voluumi - - + + ms ms - + Backlight Auto OFF after Taustavalo pois automaattisesti - + Backlight flash on alarm Taustavalo vilkkuu hälytyksenä - + Vario pitch at zero Vario ääni kun nolla - + Vario repeat at zero Varion toisto nollassa - + This is the switch selectrion for turning on the backlight (if installed). @@ -2732,8 +2483,8 @@ Nämä vaikuttaa kaikkiin malleihin jotka on EEPROMilla. - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2748,32 +2499,42 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">Values can be 20-45</span></p></body></html> - + Backlight Brightness Taustavalon kirkkaus - + RotEnc Navigation RotEnc navigaatio - + + Automatically adjust the radio's clock if a GPS is connected to telemetry. + + + + America Amerikka - + Japan Japani - + Europe Eurooppa - + + Backlight OFF Brightness + + + + Mode selection: Mode 1: @@ -2817,271 +2578,271 @@ Tila 4: - + Mode 1 (RUD ELE THR AIL) Mode 1 (PER KOR KAA SII) - + Mode 2 (RUD THR ELE AIL) Mode 2 (PER KAA KOR SII) - + Mode 3 (AIL ELE THR RUD) Mode 3 (SII KOR KAA PER) - + Mode 4 (AIL THR ELE RUD) Mode 4 (SII KAA KOR PER) - + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> <html><head/><body><p>Kanava järjestys</p><p><br/></p><p>Määrittelee miksereiden perusasetukset uuteen malliin.</p></body></html> - + R E T A P Ko Ka S - + R E A T P Ko S Ka - + R T E A P Ka Ko S - + R T A E P Ka S Ko - + R A E T P S Ko Ka - + R A T E P S Ka Ko - + E R T A Ko P Ka S - + E R A T Ko P S Ka - + E T R A Ko Ka P S - + E T A R Ko Ka S P - + E A R T Ko S P Ka - + E A T R Ko S Ka P - + T R E A Ka P Ko S - + T R A E Ka P S Ko - + T E R A Ka Ko P S - + T E A R Ka Ko S P - + T A R E Ka S P Ko - + T A E R Ka S Ko P - + A R E T S P Ko Ka - + A R T E S P Ka Ko - + A E R T S Ko P Ka - + A E T R S Ko Ka P - + A T R E S Ka P Ko - + A T E R S Ka Ko P - + Stick Mode Tikku tila - + Metric Metrit - + Imperial Imperiaali - + Default Channel Order Kanavien järjestys - + GPS Coordinates GPS koordinaatit - + Min Min - - + + v v - + Max Max - + Low Memory Warning Muisti vähissä hälytys - + Inactivity Timer Käyttämättömyys ajastin - + Show Splash Screen on Startup Näytä alkuruutu käynnistyksessä - + Contrast Kontrasti - + Battery Meter Range - + Haptic Strength Värinän voimakkuus - + LCD Display Type LCD näytön tyyppi - + "No Sound" Warning "Ei ääniä" hälytys - + Battery Warning Akun varoitin - + Haptic Length Värinän pituus - + MAVLink Baud Rate MAV linkki baudit - - + + Quiet Äänetön - + Only Alarms Vain hälyt - - + + No Keys Ei nap - - + + All Kaikki - + Battery warning voltage. This is the threashhold where the battery warning sounds. @@ -3092,114 +2853,114 @@ Tämä on jännitealue jolloin akun varoitus ääni annetaan. Hyväksytty arvo: 5v - 10v - + Standard Vakio - + Optrex Optrex - + If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. Jos tämä arvo ei ole 0, piipataan valitun ajan jos mitään käskyjä ei tule ( MIN ). - + min Min - - + + Show splash screen on startup Näytä alkuruutu käynnistyksessä - + --- --- - + 2s 2s - + 3s 3s - + 4s 4s - + 6s 6s - + 8s 8s - + 10s 10s - + 15s 15s - + 4800 Baud 4800 Baudia - + 9600 Baud 9600 Baudia - + 14400 Baud 14400 Baudia - + 19200 Baud 19200 Baudia - + 38400 Baud 38400 Baudia - + 57600 Baud 57600 Baudia - + 76800 Baud 76800 Baudia - + 115200 Baud 115200 Baudia - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -3224,72 +2985,72 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Silent mode warning - will alert you if the beeper is set to quiet (0)</p></body></html> - - + + X-Short X-lyhyt - - + + Short Lyhyt - - + + Normal Normaali - - + + Long Pitkä - - + + X-Long X-Pitkä - - + + hh° (N/S) mm' ss''.dd hh° (N/S) mm' ss''.dd - + NMEA NMEA - + Play Delay (switch mid position) Toista viive (kytkin keskiasennossa) - + Measurement Units Mittayksiköt - + Haptic Mode Värinä tila - + Beeper Length Piippaus pituus - + Beeper Mode Piipperin moodi - + Beeper volume 0 - Quiet. No beeps at all. @@ -3306,7 +3067,7 @@ p, li { white-space: pre-wrap; } 4 -Erittäin voimakas. - + Alarms Only Vain hälyt @@ -3314,7 +3075,7 @@ p, li { white-space: pre-wrap; } GeneralSetupPanel - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Are you sure ? @@ -3326,21 +3087,330 @@ Oletko varma ? GyroPage - + No Ei - + Yes, controled by a switch Kyllä, ohjataan kytkimellä - + Yes, controlled by a pot Kyllä, ohjataan potikalla + + Hardware + + + Form + + + + + SQ + + + + + SR + + + + + LS2 + LS2 + + + + SP + + + + + SO + + + + + S4 + S4 + + + + RS + RS + + + + SB + SB + + + + PPM 2 + PPM 2 + + + + + + + + + + + + + Beeper volume + +0 - Quiet. No beeps at all. +1 - No Keys. Normal beeps but menu keys do not beep. +2 - Normal. +3 - Loud. +4 - Extra loud. + Piipperin voluumi + +0 -Äänetön ( ei piippaa ). +1 -Ei nap ( normaalisti mutta ei menun napeista). +2 -Normaalisti. +3 -Voimakas. +4 -Erittäin voimakas. + + + + OFF + Pois + + + + S-Port Mirror + S-Portti peilik + + + + Telemetry + Telemetria + + + + SBUS Trainer + + + + + Debug + Korjaus + + + + Rud + PER + + + + PPM 3 + PPM 3 + + + + S1 + S1 + + + + S2 + S2 + + + + S3 + S3 + + + + PPM 1 + PPM 1 + + + + Serial Port + Sarja portti + + + + v + v + + + + PPM Multiplier + PPM Kerroin + + + + Current Offset + + + + + PPM 4 + PPM 4 + + + + SA + SA + + + + Ele + KOR + + + + Ail + SII + + + + Thr + KAA + + + + SC + SC + + + + LS + LS + + + + SD + SD + + + + Battery Offset + + + + + SE + SE + + + + SF + SF + + + + SG + SG + + + + SH + SH + + + + SI + + + + + SJ + + + + + SK + + + + + SL + + + + + SM + + + + + SN + + + + + RS2 + + + + + Bluetooth + + + + + ADC Filter + + + + + HardwarePanel + + + + + None + Ei mitään + + + + 2 Positions Toggle + + + + + 2 Positions + + + + + 3 Positions + + + + + Pot with detent + + + + + Multipos switch + + + + + Pot without detent + + + + + Slider with detent + + + Heli @@ -3417,22 +3487,22 @@ Oletko varma ? HeliPage - + Throttle Channel: Kaasu kanava: - + Yaw Channel: Yaw kanava: - + Pitch Channel: Pitch kanava: - + Roll Channel: Roll kanava: @@ -3440,121 +3510,121 @@ Oletko varma ? InputsPanel - - + + Move Up Siirrä ylös - - + + Ctrl+Up Ctrl+Ylös - - + + Move Down Siirrä alas - - + + Ctrl+Down Ctrl+Alas - + Clear All Inputs Tyhjennä kaikki tulot - + Not enough available inputs! Ei vapaita tuloja vapaana! - + Delete Selected Inputs? Poista valitut tulot? - + &Add &Lisää - + Ctrl+A Ctrl+A - + &Edit &Muuta - + Enter Entteri - + &Delete &Poista - + Delete Poista - + &Copy &Kopio - + Ctrl+C Ctrl+C - + &Cut &Leikkaa - + Ctrl+X Ctrl+X - + &Paste &Liitä - + Ctrl+V Ctrl+V - + Du&plicate Jäl&jennä - + Ctrl+U Ctrl+U - + Clear Inputs? Tyhjennä tulot? - + Really clear all the inputs? Varmasti tyhjennä kaikki tulot? @@ -3562,88 +3632,89 @@ Oletko varma ? LogicalSwitchesPanel - + V1 V1 - + V2 V2 - + Duration Kesto - + Delay Viive - + Function Toiminto - + AND Switch JA kytkin - + L%1 L%1 - + + + (instant) + + + + &Delete &Poista - + Delete Poista - + &Copy &Kopio - - - (no release) - - - - + + (infinite) (ääretön) - + Ctrl+C Ctrl+C - + &Cut &Leikkaa - + Ctrl+X Ctrl+X - + &Paste &Liitä - + Ctrl+V Ctrl+V @@ -3656,145 +3727,166 @@ Oletko varma ? Companion logit - + Filename Tiedoston nimi - + Open LogFile Avaa logi - + Zoom Zuumaa - + X X - + Y Y - + Reset Resetti - + Fly sessions Lento jakso - + Telemetry logs Telemetria logit - + Time (hh:mm:ss) Aika - + Plot Title Change - + New plot title: - + Axis Label Change - + New axis label: - + Graph Name Change - + New graph name: - + Error: no GPS data not found - + The column containing GPS coordinates must be named "GPS". The columns for altitude "GAlt" and for speed "GSpd" are optional - + Error Virhe - + Cannot write file %1: %2. + Ei voi kirjoittaa tiedostoa %1: +%2. + + + + Cursor A: %1 m - + + Cursor B: %1 m + + + + + Time delta: %1 + + + + + Climb rate: %1 m/s + + + + Select your log file Valitse logi tiedosto - + Available fields Valittavana olevat kentät - + The selected logfile contains %1 invalid lines out of %2 total lines Valittu logi sisältää: %1 virhe riviä, kokomäärästä %2 riviä - + total duration - + duration - + (L1) - + (R1) - + (L2) - + (R2) @@ -3802,586 +3894,471 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt MainWindow - - - - + + File loaded Tiedosto ladattu - + Display previous warning again at startup ? Näytä edellinen varoitus uudelleen kun radio käynnistetään ? - + Checking for updates Tarkistetaan päivityksiä - + Unable to check for updates. Ei voi tarkistaa päivityksiä. - + A new version of Companion is available (version %1)<br>Would you like to download it? Uusi versio Companionista on saatavilla (versio %1)<br>Haluatko ladata sen nyt ? - - - + + Save As Tallenna nimellä - + Executable (*.exe) Suoritettava (*.exe) - + New release available Uusi julkaisu saatavilla - - + + No updates available at this time. Ei päivityksiä saatavilla tälläkertaa. - + Would you like to launch the installer? Haluatko suorittaa asennus ohjelman? - - + + Error Virhe - + Error opening file %1: %2. Virhe avattaessa tiedostoa %1: %2. - + Compilation server too busy, try later Kääntäjä palvelin liian kiireinen, yritä kohta uudelleen - - Compilation server requires registration, please check OpenTX web site - Kääntäjä palvelin tarvii rekisteröitymisen, käy OpenTX sivuilla katsomassa lisää - - - + Unknown server failure, try later Tuntematon palvelin virhe, yritä kohta uudelleen - - Compilation server termporary failure, try later - Companion palvelin tilapäisesti tiltissä, yritä kohta uudelleen - - - - + + Yes Kyllä - - + + No Ei - - + + Release Notes Julkaisuun liittyviä dokuja - - + + Do you want to download release %1 now ? Haluatko ladata julkaisun %1 nyt ? - - The selected language will be used the next time you start Companion. - Valittu kieli otetaan käyttöön Companionissa kun se käynnistettään seuraavan kerran. - - - + The new theme will be loaded the next time you start Companion. Uusi teema otetaan käyttöön Companionissa kun se käynnistettään seuraavan kerran. - + The icon size will be used the next time you start Companion. Uusi ikonienkoko otetaan käyttöön Companionissa kun se käynnistettään seuraavan kerran. - - + + File saved Tiedosto tallennettu - + Firmware updates Firmware päivityksiä - + Current firmware does not provide release notes informations. Nykyinen firmware ei sisällä julkaisu dokuja. - + OpenTX Home Page: <a href='%1'>%1</a> OpenTX Kotisivut: <a href='%1'>%1</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> Jos meinaat että tämä ohjelma on hyvä. Teeppä hyvä teko ja: <a href='%1'>Lahjoita</a> - + About Companion Tietoja Companionista - + New Uusi - + Open... Avaa... - + Save As... Tallenna nimellä... - + Exit Poistu - + Exit the application Poistu ohjelmasta - + Classical Klassinen - + Do you want to write the firmware to the radio now ? Haluatko kirjoittaa firmwaren lähettimen muistiin ? - + Ignore this release %1? Ohita tämä versio (r%1)? - - + + Open Models and Settings file Avaa mallit ja asetukset - + Read Models and Settings From Radio Lue mallit ja asetukset lähettimestä - + Save Radio Backup to File Tallenna lähettimen varmuuskopio tiedostoon - + Read Radio Firmware to File Lue firmware tiedostosta - + Create a new Models and Settings file Luo uusi mallit ja asetukset tiedosto - - + + Save Models and Settings file Tallenna mallit ja asetukset tiedostoon - + Cut Model Leikkaa malli - + Cut current model to the clipboard Leikka nykyinen malli leikepöydälle - + Copy current model to the clipboard Kopio nykyinen malli leikepöydälle - + Paste model from clipboard Liitä nykyinen malli leikepöydälle - + Paste Model Liitä malli - + The classic companion9x icon theme Klassiset Companion iconit teema - + Yerico Yerico - + Yellow round honey sweet icon theme Hunajan keltaiset ikonit teema - + Monochrome Yksivärinen - + A monochrome black icon theme Yksivärisen teeman musta ikoni tyyli - + MonoWhite Simppeli valkoinen - + A monochrome white icon theme Yksivärisen teeman valkoinen ikoni tyyli - + MonoBlue Simppeli sininen - + A monochrome blue icon theme Yksivärisen teeman sininen ikoni tyyli - + Small Pieni - + Use small toolbar icons Käytä pieniä ikoneita työkalupalkissa - + Normal Normaali - + Use normal size toolbar icons Käytä normaaleita ikoneita työkalupalkissa - + Big Iso - + Use big toolbar icons Käytä isoja ikoneita työkalupalkissa - + Huge Valtava - + Use huge toolbar icons Käytä valtavia ikoneita työkalupalkissa - + System language Järjestelmän kieli - - Use system language in menus - Käytä järjestelmän kieltä valikoihin - - - - Czech - Tsekki - - - - Use Czech in menus - Käytä tsekki valikoita - - - - German - Saksa - - - - Use German in menus - Käytä saksa valikoita - - - - English - Englanti - - - - Use English in menus - Käytä englanti valikoita - - - - Finnish - Suomi - - - - Use Finnish in menus - Käytä suomi valikoita - - - - French - Ranska - - - - Use French in menus - Käytä ranska valikoita - - - - Italian - Italia - - - - Use Italian in menus - Käytä italia valikoita - - - - Spanish - Espanja - - - - Use Spanish in menus - - - - + Alt+S Alt+S - + SD card synchronization - + Show the list of radio profiles - + New Radio Uusi Radio - - Polish - Puola - - - - Use Polish in menus - Käytä puola valikoita - - - - Swedish - Ruotsi - - - - Use Swedish in menus - Käytä ruotsi valikoita - - - + About... Tietoja... - + Print... Tulosta... - + Simulate... Simuloi... - + Simulate current model Simuloi nykyinen malli - + Load Backup... Lataa varmuuskopio... - + View Log File... Näytä logi tiedosto... - + Open and view log file Avaa ja näytä logi tiedosto - + Settings... Asetukset... - + Download... Ladattu... - + Check for Updates... Tarkistetaan päivityksiä... - + Companion Changes... Companionin muutokset... - + Show Companion change log Näytä Companionin muutos logi - + Firmware Changes... Firmwaren muutokset... - + Show firmware change log Näytä firmwaren muutos logi - + Compare Models... Vertaa malleja... - + Edit Radio Splash Image... Muuta lähettimen alkuruutu kuvaa... - + Edit the splash image of your Radio Muuta alkuruutua omaan lähettimeen - - + + Read Firmware from Radio Lue firmware lähettimestä - + Read firmware from Radio Lue firmware lähettimestä - - + Write Firmware to Radio Kirjoita firmware lähettimeen - + Write firmware to Radio Kirjoita firmware lähettimeen - + Write Models and Settings To Radio Kirjoita mallit ja asetukset lähettimeen - - + Write Models and Settings to Radio Kirjoita mallit ja asetukset lähettimeen - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -4390,7 +4367,7 @@ We recommend you view the release notes using the button below to learn about an - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -4401,385 +4378,562 @@ We recommend you view the release notes using the button below to learn about an - - + + Synchronize SD - - + + Read Models and Settings from Radio Lue mallit ja asetukset lähettimestä - + Configure Communications... Määrittele yhteydet... - + Configure software for communicating with the Radio Asetetaan ohjelma joka lukee ja kirjoittaa tiedot lähettimeen - + Write Backup to Radio Kirjoita varmuuskiop lähettimeen - + Write Backup from file to Radio Kirjoita varmuuskopio tiedosto lähettimeen - + Backup Radio to File Varmuuskopio lähetin tiedostoon - + Save a complete backup file of all settings and model data in the Radio Tallenna täydellinen varmuuskopio kaikista malleista ja asetuksista lähettimeen - + Contributors... Avustajat... - + Recent Models+Settings Viimeisimmät mallit ja asetukset - - + + Radio Profile Radio profiili - + A new release of Companion is available, please check the OpenTX website! Uusi versio Companionista on saatavilla. Käy OpenTX sivuilla katsomassa lisää! - - Not enough memory for all the selected firmware options - Ei tarpeeksi vapaata muistia valituille toiminnoille - - - - - + + + Companion Companion - + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> OpenTX Companion projektin on aloittanut alunperin: <a href='%1'>eePe</a> {1'?} - + Copyright OpenTX Team Tekijänoikeus: OpenTX tiimi - + OpenTX Companion %1 - Radio: %2 - Profile: %3 - + Save Tallenna - + Copy Model Kopio malli - + Show recent Models+Settings documents Näytä lista viimeaikaisista mallit ja asetukset dokuista - + %2 %2 - + Show the application's About box Näytä sovelluksen tietoja ikkuna - + + Not enough flash available on this board for all the selected options + + + + + Compilation server temporary failure, try later + + + + + Compilation error + + + + + Invalid firmware + + + + + Invalid board + + + + + Invalid language + + + + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + + + + + Models and Settings read + + + + + + This function is not yet implemented + + + + Print current model Tulosta nykyinen malli - + Load backup from file Lataa varmuuskipio tiedostosta - + Edit Settings Muuta asetuksia - + Download firmware and voice files Lataa firmware ja ääni tiedostot - + Check OpenTX and Companion updates Tarkista OpenTX ja Companion päivitykset - + Compare models Vertaa malleja - + List available programmers Lista vapaista ohjelmointilaitteista - + List programmers... Lista ohjelmointilaitteista... - + Fuses... Sulakkeet... - + Show fuses dialog Näytä sulake dialogi - + Create a new Radio Setting Profile Luo uusi radio asetus profiili - + Add Radio Profile Lisää lähettimen profiili - + Manuals and other Documents Manuaalit ja muut dokut - + Open the OpenTX document page in a web browser Avaa OpenTX dokut webbi selaimen sivulle - + A tribute to those who have contributed to OpenTX and Companion Hatunnosto niille jotka on tukenut OpenTX ja Companion projektia - + + Use default system language. + + + + + Use %1 language (some translations may not be complete). + + + + Recent Files Viimeisimmät tiedostot - + Set Menu Language Aseta valikon kieli - + Set Icon Theme Aseta ikonien teema - + Set Icon Size Aseta ikonien koko - - + + File Tiedosto - - + + Edit Muuta - + Settings Asetukset - + Read/Write Lue/Kirjoita - - + + Help Apu - + Write Kirjoita - + Ready Valmis MdiChild + + + Delete selected models? + + + + + Cannot delete default model. + Valittuna ollutta mallia ei voida poistaa. + + &Edit + &Muuta + + + + &Restore from backup + &Palauta varmuuskopiosta + + + + &Model Wizard + &Malli apuri + + + + &Delete + &Poista + + + + Delete + Poista + + + + &Copy + &Kopio + + + + Ctrl+C + Ctrl+C + + + + &Cut + &Leikkaa + + + + Ctrl+X + Ctrl+X + + + + + &Paste + &Liitä + + + + + Ctrl+V + Ctrl+V + + + + D&uplicate + Jäl&jennä + + + + Ctrl+U + Ctrl+U + + + + Move to Category + + + + + &Use as default + &Käytä perus asetuksena + + + + P&rint model + Tu&losta malli + + + + Ctrl+P + Ctrl+P + + + + &Simulate model + &Simuloi malli + + + + Alt+S + Alt+S + + + + &Add model + + + + + &Rename category + + + + + &Delete category + + + + + &Add category + + + + + Models and settings will be automatically converted. +If that is not what you intended, please close the file +and choose the correct radio type/profile before reopening it. + + + + + Do you want to overwrite radio general settings? + Haluatko päällekirjoittaa radion yleiset asetukset ? + + + + You are pasting on an not empty model, are you sure? + Yrität liittää tietoja ei tyhjän mallin tietoihin, haluatko varmasti jatkaa ? + + + free bytes Vapaata tilaa - + + Companion Companion - + + This category is not empty! + + + + + New model + + + + Editing model %1: Muutetaan mallia %1: - - - - - - - - - - - - - - - - - - + + + + + + Error Virhe - - + + Unable to find Horus radio SD card! + + + + + Models and Settings written + + + + Unable to find file %1! Ei löydy tiedostoa %1! - - - - + Error opening file %1: %2. Virhe avattaessa tiedostoa %1: %2. - - - Invalid EEPROM File %1 - Väärä EEPROM tiedosto %1 - - - - + Error reading file %1: %2. Virhe luettaessa tiedostoa %1: %2. - - Invalid binary EEPROM File %1 - Väärää tietoa EEPROM tiedostossa %1 - - - - - - + + + + Save As Tallenna nimellä - - - - - Cannot write file %1: -%2. - Ei voi kirjoittaa tiedostoa %1: -%2. - - - - - Error writing file %1: -%2. - Virhe kirjottaessa tiedostoa %1: -%2. - - - + %1 has been modified. Do you want to save your changes? %1 on modifoitu. Haluatko tallentaa muutokset ? - + Cannot write temporary file! Väliaikaiseen tiedostoon ei voida kirjoittaa! - + Open backup Models and Settings file Avaa varmuuskopio mallit ja asetukset - - - - + Warning Varoitus - + Invalid binary backup File %1 Väärää tietoa varmuuskopio tiedostossa %1 + + + Radio settings + + + + + Simulate Tx + Simuloi Tx + MixerDialog @@ -4978,139 +5132,159 @@ If blank then the mix is considered to be "ON" all the time. Jos tyhjä mikserin katsotaan olevan "ON" kokoajan. - + DEST -> CH%1 KOHD -> CH%1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + MixesPanel - - + + Move Up Siirrä ylös - - + + Ctrl+Up Ctrl+Ylös - - + + Move Down Siirrä alas - - + + Ctrl+Down Ctrl+Alas - + Clear Mixes Tyhjennä mikserit - + Not enough available mixers! Ei enempää vapaita miksereitä! - + Delete Selected Mixes? Poista valitut mikserit? - + &Add &Lisää - + Ctrl+A Ctrl+A - + &Edit &Muuta - + Enter Entteri - + &Toggle highlight &valitse korostettu - + Ctrl+T Ctrl+T - + &Delete &Poista - + Delete Poista - + &Copy &Kopio - + Ctrl+C Ctrl+C - + Ctrl+X Ctrl+X - + C&ut C&ut - + &Paste &Liitä - + Ctrl+V Ctrl+V - + Du&plicate Jäl&jennä - + Ctrl+U Ctrl+U - + Clear Mixes? Tyhjennä mikserit? - + Really clear all the mixes? Varmasti tyhjennä kaikki mikserit? @@ -5128,52 +5302,52 @@ Jos tyhjä mikserin katsotaan olevan "ON" kokoajan. Simuloi - + Setup Asetukset - + Heli Kopteri - + Flight Modes Lento tilat - + Inputs Tulot - + Mixes Mikserit - + Outputs - + Logical Switches Loogiset kytkimet - + Curves Käyrät - + Special Functions Spesiaali toiminnot - + Telemetry Telemetria @@ -5181,276 +5355,308 @@ Jos tyhjä mikserin katsotaan olevan "ON" kokoajan. ModelPrinter - + %1 bytes - + CH%1 CH%1 - + Exponential Expo - + Extra Fine Eri hieno - + Fine Hieno - + Medium Keski - + Coarse Karkea - + Unknown Tuntematon - + Enabled Päälle - + Disabled Pois - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) - + %1, Channels(%2-%3) - + Receiver number(%1) - + + radio Protocol %1, subType %2, option value %3 + + + + Slave/Jack - + Master/SBUS Module - + Master/CPPM Module - + Master/SBUS in battery compartment - + Master/Jack - + + 90 + 90 + + + + 120 + 120 + + + + 120X + 120X + + + + 140 + 140 + + + Rudder Sivuperäsin - + Elevator Korkeusperäsin - + Throttle Kaasu - + Aileron Siivekkeet - + Name(%1) - + Slow(u%1:d%2) - + Persistent Yhtämittainen - + MinuteBeep Minutti piippaus - + CountDown(Beeps) - + CountDown(Voice) - + CountDown(Haptic) - + + Off Pois - - - - + + + + FM%1 FM%1 - + FM%1%2 FM%1%2 - + FM%1+%2 - + [I%1] [I%1] - + Input%1 Tulo%1 - + Weight Paino - + Switch Kytkin - - + + NoTrim Ei trimmiä - + Weight(%1) Paino(%1) - + Switch(%1) Kytkin(%1) - + No DR/Expo Ei DR / Expoja - + + Offset(%1) Tasoitus(%1) - + Delay(u%1:d%2) - + Warn(%1) - + Disabled in all flight modes - + Flight modes(%1) Lentotilat(%1) - + Flight mode(%1) Lentotila(%1) - + Edge(%1, [%2:%3]) reuna(%1, [%2:%3]) - + + instant + + + + Sticky(%1, %2) Jähmeä(%1, %2) - + Timer(%1, %2) Ajastin(%1, %2) - + Duration(%1s) - + Delay(%1s) - + Custom Omat - + Standard Vakio @@ -5458,27 +5664,27 @@ Jos tyhjä mikserin katsotaan olevan "ON" kokoajan. ModelSelectionPage - + Plane Lentokone - + Multirotor Moniroottori / autogiro - + Helicopter Helikopteri - + Model Name: Mallin nimi: - + Model Type: Mallin tyyppi: @@ -5486,129 +5692,7 @@ Jos tyhjä mikserin katsotaan olevan "ON" kokoajan. ModelsListWidget - - - &Edit - &Muuta - - - - &Restore from backup - &Palauta varmuuskopiosta - - - - &Model Wizard - &Malli apuri - - - - &Delete - &Poista - - - - Delete - Poista - - - - &Copy - &Kopio - - - - Ctrl+C - Ctrl+C - - - - &Cut - &Leikkaa - - - - Ctrl+X - Ctrl+X - - - - &Paste - &Liitä - - - - Ctrl+V - Ctrl+V - - - - D&uplicate - Jäl&jennä - - - - Ctrl+U - Ctrl+U - - - - &Use as default - &Käytä perus asetuksena - - - - P&rint model - Tu&losta malli - - - - Ctrl+P - Ctrl+P - - - - &Simulate model - &Simuloi malli - - - - Alt+S - Alt+S - - - - General Settings - Yleiset asetukset - - - - Delete Selected Models? - Poista valitut mallit? - - - - - Cannot delete default model. - Valittuna ollutta mallia ei voida poistaa. - - - - Cannot cut default model. - Valittua mallia ei voi leikata. - - - - Do you want to overwrite radio general settings? - Haluatko päällekirjoittaa radion yleiset asetukset ? - - - - You are pasting on an not empty model, are you sure? - Yrität liittää tietoja ei tyhjän mallin tietoihin, haluatko varmasti jatkaa ? - - - + No free slot available, cannot duplicate Ei vapaata tilaa, ei voida monistaa @@ -5616,142 +5700,199 @@ Jos tyhjä mikserin katsotaan olevan "ON" kokoajan. Module - + Failsafe Mode Turvatila - + Start Aloitus - + PPM delay PPM viive - + Negative Negatiivinen - + Positive Positiivinen - + Polarity Napaisuus - + Trainer Mode Harjoitus tila - + PPM Frame Length PPM läh pituus - + CH CH - + + SubType + + + + + Antenna + + + + + Internal + + + + + Ext. + Int. + + + + + Option value + + + + + Bind on startup + + + + + Low Power + + + + us us - + + Multi Radio Protocol + + + + Master/Jack - + Slave/Jack - + Master/SBUS Module - + Master/CPPM Module - + Master/SBUS in battery compartment - + + Show values in: + + + + + % + abbreviation for percent + % + + + + μs + abbreviation for microseconds + + + + ms ms - + Channels Kanavat - + Not set - + Hold Pidä - + Custom Omat - + No Pulses Ei pulsseja - + Receiver Vastaanotin - + Failsafe Positions Turvatila asennot - + Protocol Protokolla - + Receiver No. Vastaanotin No. - + Output type - + Open Drain - + Push Pull @@ -5759,43 +5900,43 @@ Jos tyhjä mikserin katsotaan olevan "ON" kokoajan. ModulePanel - + Trainer Port Trainerin portti - + Internal Radio System Sisäinen radio systeemi - + External Radio Module Ulkoinen radio systeemi - - + + Radio System Radio systeemi - + Extra Radio System Extra Radio järjestelmä - + Value Arvo - + Hold Pidä - + No Pulse @@ -5803,229 +5944,322 @@ Jos tyhjä mikserin katsotaan olevan "ON" kokoajan. MultiModelPrinter - + General Model Settings Yleiset mallin asetukset - + Name: - + EEprom Size: - + Timer%1: - + Module%1: - + Module: - + Trainer port: - + Throttle Trim: - + Trim Increment: - + Center Beep: - + + Helicopter Setup + + + + + Swash Type: + + + + + Swash Ring: + + + + + Input + Tulo + + + + Weight + Paino + + + + Long. cyc + + + + + Lateral cyc + + + + + Collective + Kopt Collective + + + Flight modes Lento tilat - - + + Flight mode Lento tila - + Switch Kytkin - + Fade IN - + Fade OUT - - + + FM%1 FM%1 - - + + GV%1 GV%1 - + RE%1 - + Limits Rajat - + Channel - + Name Nimi - - + + Offset Tasoitus - + Min Min - + Max Max - + Invert Käänteinen - + Global Variables Globaalit muuttujat - + Inputs Tulot - + Mixers Mikserit - + CV%1 - + Curves Käyrät - + L%1 L%1 - + Logical Switches Loogiset kytkimet - + SF%1 SF%1 - + Special Functions Spesiaali toiminnot - + Telemetry Settings Telemetria asetukset - + Analogs - + Unit Yksikkö - + Scale Skaala - + A%1 A%1 - + RSSI Alarms + + + Low Alarm + Ala hälytys + + + + Critical Alarm + Kriittinen hälytys + + + + Multiprotocols + + + Subtype + + + + + Video TX frequency + + + + + C2500 frequency fine tune + + + + + Telemetry + Telemetria + + + + Radio output power + + + + + Servo output frequency + + + + + Option value + + + + + DEFAULT + + MultirotorPage - + Throttle Channel: Kaasun kanava: - + Yaw Channel: Yaw kanava: - + Pitch Channel: Pitch kanava: - + Roll Channel: Roll kanava: @@ -6033,17 +6267,17 @@ Jos tyhjä mikserin katsotaan olevan "ON" kokoajan. OptionsPage - + Throttle Cut Kaasu pakko pois - + Throttle Timer Kaasu ajastin - + Flight Timer Lento ajastin @@ -6066,17 +6300,17 @@ Jos tyhjä mikserin katsotaan olevan "ON" kokoajan. Tulosta tiedostoon - + Print Document Tulosta dokumentti - + Select PDF output file Valitse PDF tiedosto - + ODF files (*.odt);;PDF Files(*.pdf);;HTML-Files (*.htm *.html);;All Files (*) ODF tiedosto (*.odt);;PDF tiedosto (*.pdf);;HTML-tiedosto (*.htm *.html);;Kaikki tiedostot (*) @@ -6110,2241 +6344,2125 @@ Jos tyhjä mikserin katsotaan olevan "ON" kokoajan. QObject - + FW: %1 FW: %1 - + Pict: %1 Pict: %1 - + Profile image Profiili kuva - - + + Rud PER - - + + Ele KOR - - + + Thr KAA - - + + Ail SII - - - + + P1 P1 - - - + + P2 P2 - - - + + P3 P3 - - - - + + + S1 S1 - - - - + + + S2 S2 - - - - + + + LS LS - - - - + + + RS RS - - - + + + REa REa - - - + + + REb REb - + TrmR tPER - + TrmE tKOR - + TrmT tKAA - + TrmA tSII - - + + Trm5 + + + + + Trm6 + + + + + Batt Batt - - - + + + Timer1 Ajastin 1 - - - + + + Timer2 Ajastin 2 - + SWR SWR - + A1 A1 - + A2 A2 - + Alt Kork - + Rpm Kier - + Fuel Bensa - + T1 T1 - + T2 T2 - + Speed Nopeus - + Dist Etäisyys - + GPS Alt GPS kork - + Cell Kenno - + Vfas Vfas - + Curr Virta - + Cnsp Cnsp - + Powr Powr - + AccX AccX - + AccY AccY - + AccZ AccZ - + VSpd Vspd - + dTE dTE - + A1- A1- - + A2- A2- - + Alt- Kork- - + Alt+ Kork+ - + Rpm+ Kier+ - + T1+ T1+ - + T2+ T2+ - - + + Time Aika - - - - + + + + ---- ---- - + MAX MAX - + CYC%1 CYC%1 - - - + + + GV%1 GV%1 - - + S3 S3 - + RSSI Tx RSSI TX - + RSSI Rx RSSI RX - + A3 A3 - + A4 A4 - + Cells Kennoja - + AirSpeed Ilman nopeus - + Hdg Hdg - + A3- A3- - + A4- A4- - + Speed+ Nopeus + - + Dist+ Etäisyys + - + AirSpeed+ Ilman nopeus + - + Cell- Kenno- - + Cells- Kennoja- - + Vfas- Vfas- - + Curr+ Virta + - + Powr+ Powr + - + ACC ACC - + GPS Time GPS aika - - + L1 L1 - - + L2 L2 - - - L3 - L3 - - - - - L4 - L4 - - - - - L5 - L5 - - - - - L6 - L6 - - - - - L7 - L7 - - - - - L8 - L8 - - - - - L9 - L9 - - - - - L10 - L10 - - - - - L11 - L11 - - - - - L12 - L12 - - - - - L13 - L13 - - - - - L14 - L14 - - - - - L15 - L15 - - - - - L16 - L16 - - - - - L17 - L17 - - - - - L18 - L18 - - - - - L19 - L19 - - - - - L20 - L20 - - - - - L21 - L21 - - - - - L22 - L22 - - - - - L23 - L23 - - - - - L24 - L24 - - - - - L25 - L25 - - - - - L26 - L26 - - - - - L27 - L27 - - - - - L28 - L28 - - - - - L29 - L29 - - - - - L30 - L30 - - - - - L31 - L31 - - - - - L32 - L32 - - - + [I%1] [I%1] - + LUA%1%2 LUA%1%2 - + TR%1 TR%1 - + FM0 FM0 - + FM1 FM1 - + FM2 FM2 - + FM3 FM3 - + FM4 FM4 - + FM5 FM5 - + FM6 FM6 - + FM7 FM7 - + FM8 FM8 - - S11 - S11 - - - - S12 - S12 - - - - S13 - S13 - - - - S14 - S14 - - - - S15 - S15 - - - - S16 - S16 - - - - S21 - S21 - - - - S22 - S22 - - - - S23 - S23 - - - - S24 - S24 - - - - S25 - S25 - - - - S26 - 26 - - - - S31 - S31 - - - - S32 - S32 - - - - S33 - S33 - - - - S34 - S34 - - - - S35 - S35 - - - - S36 - S36 - - - + RudTrim Left PER trimmi vasen - + RudTrim Right PER trimmi oikea - + EleTrim Down KOR trimmi alas - + EleTrim Up KOR trimmi ylös - + ThrTrim Down KAA trimmi alas - + ThrTrim Up KAA trimmi ylös - + AilTrim Left SII trimmi vasen - + AilTrim Right SII trimmi oikea - - - + + + OFF Pois - + + SD Logs + + + + SetFailsafe Int. Module - + SetFailsafe Ext. Module - + RangeCheck Int. Module - + RangeCheck Ext. Module - + Bind Int. Module - + Bind Ext. Module - + played once, not during startup - + repeat(%1s) - + DISABLED Pois - + INV KÄÄNT - + NOR NOR - + THs THs - + TH% TH% - + THt THt - - - + + + ON ON - - + + °F - + + mW + + + + + Rad + + + + + + L%1 + L%1 + + + + Trim 5 Down + + + + + Trim 5 Up + + + + + Trim 6 Down + + + + + Trim 6 Up + + + + One Yksi - + ??? ??? - + Diff(%1) Ero(%1) - + Expo(%1) Expo(%1) - + Function(%1) Toiminto(%1) - + Curve(%1) Käyrä(%1) - + !Curve(%1) !Käyrä(%1) - - - + + + --- --- - + a>x a>x - + a<x a<x - + |a|>x |a|>x - + |a|<x |a|<x - + AND JA - + OR TAI - + XOR KÄÄNT TAI - + a=b a=b - + a!=b a!=b - + a>b a>b - + a<b a<b - + a>=b a>=b - + a<=b a<=b - + d>=x d>=x - + |d|>=x |d|>=x - + a=x a=x - + a~x a~x - + Timer Ajastin - + Sticky Lukko - + Edge Reuna - + + Left Horizontal + Vasen vaaka + + + + Left Vertical + Vasen pysty + + + + Right Vertical + Oikea pysty + + + + Right Horizontal + Oikea vaaka + + + + Aux. 1 + + + + + Aux. 2 + + + + + Unknown Tuntematon - - - + + + <font color=red><b>Inconsistent parameter</b></font> <font color=red><b>epäjohdonmukainen arvo</b></font> - + Telemetry Telemetria - + Value Arvo - + Decr: Väh: - + Incr: Lis: - - - - - - - + + + + + + + V V - - + + s s - + ft jalka - - - + + + m metri - - - + + + °C °C - - - + + + ° ° - - + + % % - - - + + + mph mph - - - + + + km/h km/h - - + + m/s m/s - - + + A A - + mA - + kts - + f - - + + mAh mAh - - + + W W - + dB - + rpms - - + + g g - + hours - + minutes - + seconds - + h:m - + m:s - + h:m:s - - + F1 - - + F2 - - + F3 - - + F4 - - - + + + Timer3 Ajastin 3 - + Override %1 Ohitus %1 - + Trainer Traineri - + Trainer RUD Trainerin PER - + Trainer ELE Trainerin KOR - + Trainer THR Trainerin KAA - + Trainer AIL Trainerin SII - + Instant Trim Välitön trimmi - + Play Sound Toista ääni - + Haptic Toista värinä - + Reset Resetti - + Set Timer %1 Aseta ajastin %1 - + Vario Variom - + Play Track Toista raita - + Play Both Toista molemmat - + Play Value Toista arvo - + Play Script - - Start Logs - Aloita login tallennus - - - + Volume Voluumi - + Backlight Taustavalo - + Screenshot - + Background Music Tausta musiikki - + Background Music Pause Tausta musiikki tauko - + Adjust GV%1 Muuta GV%1 - + No repeat Ei toistoa - - - Simultaneous usage of expo and curves is no longer supported - Samanaikainen käyttö expolla ja käyrällä ei ole enää tuettu + + Switch + Kytkin - + + Switch + + + + + cannot be exported on this board! + + + + Source %1 cannot be exported on this board! - + OpenTX only accepts %1 points in all curves OpenTX vastaanottaa vain %1 pistettä kaikkiin käyriin - + OpenTx only accepts %1 points in all curves OpenTX vastaanottaa vain %1 pistettä kaikkiin käyriin - - - - - + + + + + + OpenTX on this board doesn't accept this function OpenTX ja tämä funktio ei onnistu tässä radiossa - + OpenTX doesn't accept this telemetry protocol OpenTX ei hyväksy tätä telemetria protokollaa - - - + + + OpenTX doesn't accept this radio protocol OpenTX ei hyväksy tätä radio protokollaa - + OpenTX doesn't allow this number of channels OpenTX ei hyväksy näin montaa kanavaa - - + Warning Varoitus - - EEPROM saved with these warnings: - EEPROM tallennettiin seuraavin varoituksin: - - - - + + Support for frsky telemetry mod Tuki FrSky telemetria moduulille - + Support for telemetry easy board Tuki telemetrialle ( easy board ) - - + + Support for jeti telemetry mod Tuki Jeti telemetria moduulille - - + + Support for receiving ardupilot data Tuki vastaanottaa ardupilot dataa - - + + Support for receiving NMEA data Tuki vastaanottaa NMEA dataa - - + + Support for MAVLINK devices Tuki MAVLINK laitteille - + Rotary Encoder use in menus navigation Rotary encoder käyttö valikon navigoinnissa - - - - - - - + + + + + + + Pots use in menus navigation Potikoiden käyttö valikko navigoinnissa - + No OverrideCH functions available Ei ohituskanava funkitoita saatavissa - - - - - - + + + + + + Enable heli menu and cyclic mix support HELI valikko päälle ,cyclic mix tuella - - - - - - - - - + + + + + + Enable TEMPLATES menu Mallit valikko käyttöön - - - - + + + + No splash screen Ei alkuruutua - - - - - - - - - + + + + + + + + + No flight modes Ei lentotiloja - - - - - - - - - + + + + + + Disable curves menus Käyrät valikko pois - - - - + + + + + Support for radio modified with regular speaker Tuki radioille johon viritetty normaali kaiutin - - - - - + + + + + Used if you have modified your radio with voice mode Käytetään jos radioon on viritetty ääni moduuli - - - - - + + + + + Used if you have modified your radio with haptic mode Käytetään jos radioon on viritetty värinä moduuli - - - - - + + + + + Support for DSM2 modules Tuki DSM2 moduleille - - - - - - - - - + + + + + + PPM center adjustment in limits PPM keskitys arvojen mukaan - - - - - - - - - + + + + + + + + + Global variables Globaalit muuttujat - - - - - - - - - + + + + + + Symetrical Limits Symmetriset rajat - - + + SmartieParts 2.2 Backlight support "Smartie parts 2.2" taustavalo tuki - + Channel values displayed in us Kavanien arvot näytetään us mallissa - - - - - - - - - + + + + + + + + + In model setup menus automatically set source by moving the control Mallien asetukset asetetaan automaattisesti kun ohjaimia käänellään - - - - - - - - - + + + + + + + + + In model setup menus automatically set switch by moving the control Mallien asetukset asetetaan automaattisesti kun nappeja käänellään - - - - - - + + + + + + Enable resetting values by pressing up and down at the same time Asetuksien poisto: Paina ylös ja alas samanaikaisesti - - - - - - - - - + + + + + + + + + No graphical check boxes and sliders Ei graaffisia valintalaatikoita ja liukuja - - - - - - - - - + + + + + + + + + Battery graph Akun grafiikka - - - - - - - - - + + + + + + + + + Don't use bold font for highlighting active items Älä käytä lihavointua fonttia korostamaan aktiivisia asioita - + + + + + + + + + + + Use alternative SQT5 font Käytä vaihtoehtoista SQT5 fonttia - - (displaying only first 10 warnings) - (näytetään vain ensimmäiset10 varoitusta) - - - + Possibility to enable FAI MODE (no telemetry) at field - + FAI MODE (no telemetry) always enabled - - - - - Support for a third timer - - - - + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) - + Instead of Joystick emulation, USB connection is Command Line Interface - - Removes D8 and LR12 FrSky protocols that are not legal for use in the EU on radios sold after Jan 1st, 2015 - - - - + + Support for PPM internal module hack - + ST7565P LCD or compatible - + ST7565R LCD or compatible - + ERC12864FSF LCD - + ST7920 LCD - - 9X board - - - - - - - + + + + Enable the throttle trace in Statistics Salli kaasun seuranta statistiikassa - + EEprom write progress bar EEprom tallennus palkki - - - - - - + + + + + + Imperial units Imperiaali yksiköt - - + + Unknown error + + + + + ... plus %1 errors + + + + + Cannot write radio settings + + + + + Cannot write model %1 + + + + + 6P + 6P + + + + JSx + + + + + JSy + + + + + Support for the DIY-Multiprotocol-TX-Module + + + + + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 + + + + + Enable Lua compiler + + + + + KS108 LCD + + + + + WTV20 voice module + + + + + JQ6500 voice module + + + + + FrSky Taranis X9D+ + + + + + FrSky Taranis X9D + + + + + Horus gimbals installed (Hall sensors) + + + + + FrSky Taranis X7 + + + + + FrSky Horus + + + + + Use ONLY with first DEV pcb version + + + + + Turnigy 9XR-PRO + + + + + Turnigy 9XR with m128 chip + + + + + Turnigy 9XR + + + + + No Winged Shadow How High support erikoistoiminto korkea (ei tuettu) - - + + No vario support Ei vario tukea - - + + No GPS support Ei GPS tukea - - + + No gauges in the custom telemetry screen Ei mittareita "omassa" telemetria ruudussa - + + 9X with stock board + + + + Allow compensating for offset errors in FrSky FAS current sensors Salli virheiden kompensoiti FrSkyn FAS virta sensorille - - + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) Lisää tuki käänteisille tikkujen tuloille ( esim taraniksen gimbaalit) - - M128 / 9X board - - - - - 9XR - 9XR - - - - 9XR with M128 chip - - - - - Gruvin9x board / 9X - - - - - MEGA2560 board - - - - - Sky9x board / 9X - - - - - ar9x board / 9X - - - - - FrSky Taranis Plus - - - - + FrSky Taranis X9E - - - - - + + + + + EEprom write Progress bar EEprom tallennus palkki - - - Support for SD memory card - Tuki SD Muistikortille - - - - - Support of FrSky PXX protocol - Tuli FrSky PXX protokollalle - - - - Confirmation before radio shutdown - - - - - Support for DSM2 modules using ppm instead of true serial - Tuki DSM2 moduuleille käyttäen PPM, eikä oikeaa sarjaliikennettä - - - - Power management by soft-off circuitry - - - - - - Adds mixers output view to the CHANNELS MONITOR screen, pressing [ENT] switches between the views - - - - - - - Enable HELI menu and cyclic mix support - HELI valikko päälle ,cyclic mix tuella - - - - 9XR-PRO + + 9X with stock board and m128 chip - FrSky Taranis + 9X with AR9X board + + 9X with Sky9x board + + + + + 9X with Gruvin9x board + + + + + + Support for SD memory card + Tuki SD Muistikortille + + + + + Support of FrSky PXX protocol + Tuli FrSky PXX protokollalle + + + + Confirmation before radio shutdown + + + + + Support for DSM2 modules using ppm instead of true serial + Tuki DSM2 moduuleille käyttäen PPM, eikä oikeaa sarjaliikennettä + + + + DIY MEGA2560 radio + + + + + Power management by soft-off circuitry + + + + + + Enable HELI menu and cyclic mix support + HELI valikko päälle ,cyclic mix tuella + + + Haptic module installed Värinä moduli asennettu - + Support for Lua model scripts Tuki LUA mallien skripteille - - - + + + Bluetooth interface Bluetooth liintäntä - + Disable HELI menu and cyclic mix support HELI valikko pois ,myös cyclic mix tuki - + Disable Global variables Globaalit muuttujat pois päältä - - th9x on this board doesn't have Rotary Encoders - th9x radiossa ei ole Rot Enc - - - + Rud Trim PER trim - + Ele Trim KOR trim - + Thr Trim KAA trim - + Ail Trim SII trim - + Rot Enc Rot Enc - + English Englanti - + French Ranska - + Italian Italia - + German Saksa - + Czech Tsekki - + Slovak Slovakia - + Spanish Espanja - + Polish Puola - + Portuguese Portugali - + Swedish Ruotsi - + + Dutch + + + + + Hungarian + + + + THR KAA - + CH%1 CH%1 - + No Ei - + RotEnc A RotEnc A - + Rot Enc B RotEnc B - + Rot Enc C RotEnc C - + Rot Enc D RotEnc D - + Rot Enc E RotEnc E - + !Flight mode %1 !Lento tila %1 - + Flight mode %1 Lento tila %1 - + Own value Oma arvo - + + -GV%1 (%2) + + + + + GV%1 (%2) + + + + Flight mode %1 value Lento tila %1 arvo - + Keys Napit - + Sticks Tikut - + Keys + Sticks Napit + Tikut - - + + -GV%1 -GV%1 - - Finnish - Suomi - - - + Yellow Keltainen - + Orange Oranssi - + Red Punainen - + Winged Shadow How High erikoistoiminto korkea - + Winged Shadow How High (not supported) erikoistoiminto korkea (ei tuettu) - + FrSky Sensor Hub FrSky:n hubi - + None Ei mitään - + Imperial Imperiaali - + Metric Metrit - + Simulator for this firmware is not yet available Tämän firmwaren simulointi ei ole vielä mahdollista - + + + Uknown error during Simulator startup. + + + + + Simulator Error + + + + + Data Load Error + + + + + Error occurred while starting simulator. + + + + Played once, not during startup Toistettu kerran, ei aloituksessa - + %1s %1s - + Value Arvo - + Source Lähde - + GVAR Gvarit - + Increment Säätö - + Flight - + Rotary Encoder Rotary encoderi - + Trim disabled Trimmi pois - + Own Trim Oma trimmi - + Use Trim from Flight mode %1 Käytä trimmiä lentotilaan %1 - + Use Trim from Flight mode %1 + Own Trim as an offset Käytä trimmiä lentotilaan %1 + Oma trimmi asetuksena - - Simultaneous usage of expo and curves is no longer supported in OpenTX - Molempien käyttö yhtäaikaa ( expot ja käyrät) ei ole enää tuettu OpenTX:llä - - - + Thank you for upgrading to OpenTX 2.0. This is a major upgrade that adds and modifies a lot of things, so please make sure that you read release notes carefully to learn about the changes, and thoroughly check each of your models for proper function. The OpenTX Team. @@ -8353,97 +8471,496 @@ The OpenTX Team. OpenTX Tiimi. - - - - - + + + + + Synchronization error - + No SD directory configured! - + No Radio connected! - + GV GV - + -%1 - - + + The directory '%1' doesn't exist! - + Create '%1' failed - + Copy '%1' to '%2' failed - + Open '%1' failed - + Write '%1' failed - - - + + + + + + + Error Virhe - + Cannot write file %1: %2. - + Ei voi kirjoittaa tiedostoa %1: +%2. - + Companion Companion - + <b><u>WARNING!</u></b><br>This will reset the fuses of %1 to the factory settings.<br>Writing fuses can mess up your radio.<br>Do this only if you are sure they are wrong!<br>Are you sure you want to continue? <b><u>VAROITUS!</u></b><br>Tämä nollaa sulakkeet %1 tehdas asetuksille.<br>Sulakkeiden kirjoittaminen voi sekoittaa lähettimeno.<br>Muuta vain jos tiedät että nykyiset on väärin!<br>Haluatko varmasti jatkaa ? - - + + Could not delete temporary file: %1 - - Radio type + + Unable to find Horus radio SD card! - - Which radio type do you want to simulate? + + Conversion error on field %1 + + + + + Negative span + Negatiivinen liike + + + + Mid value + Keski alue + + + + Positive span + Positiivinen liike + + + + + Models + Translators do NOT use accent for this, this is the default category name on Horus. + + + + + Positive + Positiivinen + + + + Negative + Negatiivinen + + + + Select a data file + + + + + Select Data Directory + + + + + Select SD Card Image Folder + + + + + Available profiles: + + + + + ID: + + + + + Name: + + + + + Available radios: + + + + + WARNING: couldn't initialize SDL: +%1 + + + + + ERROR: No simulator libraries available. + + + + + Radio profile ID or Name to use for simulator. + + + + + Radio type to simulate (usually defined in profile). + + + + + show this help text + + + + + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] + + + + + Options: + + + + + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. + Profile ID: [%1]; Radio ID: [%2]; +Data File: [%3] + + + + + ERROR: Radio profile or simulator firmware not found. +Profile ID: [%1]; Radio ID: [%2] + + + + + Error reading %1: %2 + + + + + Cannot save EEPROM + + + + + + Cannot open file %1: +%2. + + + + + + + Error writing file %1: +%2. + Virhe kirjottaessa tiedostoa %1: +%2. + + + + Invalid binary EEPROM file %1 + + + + + Can't extract RADIO/radio.bin + + + + + Can't extract RADIO/models.txt + + + + + Can't extract %1 + + + + + Unable to open %1: %2 + + + + + Invalid EEPROM file %1 + + + + + Invalid EEPROM File %1 + Väärä EEPROM tiedosto %1 + + + + + Error opening file %1: +%2. + Virhe avattaessa tiedostoa %1: +%2. + + + + Error opening OTX archive %1 + + + + + Error initializing OTX archive writer + + + + + Error creating OTX file %1: +%2. + + + + + Error creating OTX archive + + + + + Error adding %1 to OTX archive + + + + + Error opening file %1 in write mode: +%2. + + + + + Unable to find file %1! + Ei löydy tiedostoa %1! + + + + QxtCommandOptions + + + sets the application GUI style + + + + + sets the application stylesheet + + + + + restores the application from an earlier session + + + + + displays debugging information about widgets + + + + + use right-to-left layout + + + + + never grab the mouse or keyboard + + + + + grab the mouse/keyboard even in a debugger + + + + + run in synchronous mode for debugging + + + + + use Direct3D by default + + + + + sets the X11 display + + + + + sets the geometry of the first window + + + + + sets the default font + + + + + sets the default background color + + + + + sets the default foreground color + + + + + sets the default button color + + + + + sets the application name + + + + + sets the application title + + + + + sets the X11 visual type + + + + + limit the number of colors on an 8-bit display + + + + + use a private color map + + + + + sets the input method server + + + + + disable the X Input Method + + + + + sets the style used by the input method + + + + + + option "%1" not found + + + + + Short options cannot have optional parameters + + + + + positional() called before parse() + + + + + unrecognized() called before parse() + + + + + count() called before parse() + + + + + value() called before parse() + + + + + parameters() called before parse() + + + + + unrecognized parameters: + + + + + %1 requires a parameter + + + + + RadioKnobWidget + + + Right-double-click to reset to center. @@ -8465,10 +8982,100 @@ OpenTX Tiimi. Ok + + RadioOutputsWidget + + + Form + + + + + View: + + + + + Logical Switches + Loogiset kytkimet + + + + Global Variables + Globaalit muuttujat + + + + Channel Outputs + + + + + L +o +g +i +c + + + + + G +l +o +b +a +l + + + + + C +h +a +n +n +e +l +s + + + + + RadioSwitchWidget + + + Latch/unlatch the momentary switch. + + + + + RawSwitch + + + ↑ + + + + + ↓ + + + + + - + + + + + ! + + + ReleaseNotesDialog - + Companion Release Notes Companion muistiinpanot @@ -8476,7 +9083,7 @@ OpenTX Tiimi. ReleaseNotesFirmwareDialog - + OpenTX Release Notes OpenTX muistiinpanot @@ -8484,17 +9091,17 @@ OpenTX Tiimi. RudderPage - + No Ei - + Yes Kyllä - + <br>Rudder Channel: <br>Peräsin kanava: @@ -8670,7 +9277,7 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, SetupPanel - + Timer %1 @@ -8678,179 +9285,847 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, SimpleTailPage - + Elevator Channel: Korkeusper kanava: - SimulatorDialog + SimulatedUIWidget - - + + Rotary encoder click + + + + + Take Screenshot + + + + + screenshot + Simulator LCD screenshot file name prefix + + + + + SimulatedUIWidget9X + + + UP/PG-UP + + + + + [ UP ] + + + + + DN/PG-DN + + + + + [ DN ] + + + + + RIGHT/+ + + + + + [ + ] + + + + + LEFT/- + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + [ UP ]/[ DN ] or Rotary Sel. + + + + + SimulatedUIWidgetX12 + + + PG-UP + + + + + [ PgUp ] + + + + + PG-DN + + + + + [ PgDn ] + + + + + UP + + + + + [ MDL ] + + + + + DN/DEL/BKSP + + + + + [ RTN ] + + + + + LEFT + + + + + [ SYS ] + + + + + RIGHT + + + + + [ TELE ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/X + + + + + Rotary UP + + + + + +/C + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX7 + + + Taranis X7 Simulator + + + + + PG-UP + + + + + [ PAGE ] + + + + + PG-DN + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX9 + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + +/UP + + + + + [ + ] + + + + + -/DN + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ ENT ] + + + + + WHEEL/PAD SCRL + + + + + [ + ]/[ - ] + + + + + SimulatedUIWidgetX9E + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatorMainWindow + + + OpenTx Simulator + + + + + View + + + + + Radio Window + + + + + Reload... + + + + + Tools + + + + + Toolbar + + + + + Reload Lua Scripts + + + + + Reload the Lua environment on the simulated radio. + + + + + F7 + + + + + Reload Radio Data + + + + + Reload all radio data without restarting the simulator. + + + + + F9 + + + + + Key Mapping + + + + + Show keyboard maping reference. + + + + + F1 + + + + + Joystick Settings + + + + + Open joystick configuration settings dialog. + + + + + F3 + + + + + LCD Screenshot + + + + + Save a screenshot of the current simulated LCD screen. + + + + + F8 + + + + + Dock In Main Window + + + + + Show the radio in the main window or as a separate "floating" window. + + + + + Menu Bar + + + + + Show or hide the top menu bar. + + + + + Alt+M + + + + + Constrain Width + + + + + Set radio widget width to be a fixed size. + + + + + Constrain Height + + + + + Set radio widget height to be a fixed size. + + + + + ERROR: Failed to create simulator interface, possibly missing or bad library. + + + + + Alt+T + + + + + Radio Outputs + + + + + F2 + + + + + Telemetry Simulator + + + + + F4 + + + + + Trainer Simulator + + + + + F5 + + + + + Debug Output + + + + + F6 + + + + + Simulator Controls: + + + + + <tr><th>Key/Mouse</td><th>Action</td></tr> + + + + + Simulator Help + + + + + SimulatorStartupDialog + + + OpenTX Simulator - Startup Options + + + + + Simulator Startup Options: + + + + + Radio Profile: + + + + + Existing radio profiles are shown here.<br /> +Create or edit profiles using the Companion application. + + + + + Radio Type: + + + + + Existing radio simulators are shown here.<br /> +The radio type specified in the selected profile is used by default. + + + + + Data Source: + + + + + Data File: + + + + + Data Folder: + + + + + SD Image Path: + + + + + Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> +<b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! + + + + + Select data file... + + + + + + + ... + ... + + + + Directory containing RADIO and MODELS folders to use.<br /> +New folder(s) with default radio/model will be created here if necessary. + + + + + Select data folder... + + + + + Directory containing the SD card image to use.<br/> +The default is configured in the chosen Radio Profile. + + + + + Select SD card image folder... + + + + + Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. + + + + + File + Tiedosto + + + + Folder + + + + + SD Path + + + + + All files (*.*) + + + + + SimulatorWidget + + + Companion Simulator + Companion simulaattori + + + + Radio Simulator (%1) + + + + + Could not determine startup data source. + + + + + Could not load data, possibly wrong format. + + + + + Data Load Error + + + + + Invalid startup data provided. Plese specify a proper file/path. + + + + + Simulator Startup Error + + + + + Error saving data: could open file for writing: '%1' + + + + + Error saving data: could not get data from simulator interface. + + + + + An unexpected error occurred while attempting to save radio data to file '%1'. + + + + + Data Save Error + + + + Warning - Varoitus + Varoitus - - Joystick enabled but not configured correctly - Joystick päällä mutta väärin aseteltu - - - + Cannot open joystick, joystick disabled - Ei voi avata joystickia, joystick pois käytöstä + Ei voi avata joystickia, joystick pois käytöstä - - Simulating Radio (%1) - Simuloi radio (%1) - - - - - Outputs - Lähdöt - - - + Firmware %1 error: %2 - Firmware %1 virhe: %2 + Firmware %1 virhe: %2 - SimulatorDialog9X + SliderWidget - - Companion Simulator - Companion simulaattori - - - - - Hold X - Pidä X - - - - - Fix X - Kesk X - - - - - Fix Y - Kesk Y - - - - - Hold Y - Pidä Y - - - - Outputs2 - Lähdöt2 - - - - Gvars - Gvarit - - - - - - - Right Double Click to Reset - Tuplaklikkaa oikea -> resetoi - - - - BEEP - PIIP - - - - 9x Simulator - 9x simulaattori - - - - Outputs - Ulostulot - - - - SimulatorDialogTaranis - - - Companion Simulator - Companion simulaattori - - - - Taranis Simulator - Taranis simulaattori - - - - Outputs - Ulostulot - - - - Outputs2 - Lähdöt2 - - - - Gvars - Gvarit - - - - S3 - S3 - - - - S4 - S4 - - - - - - - Right Double Click to Reset - Tuplaklikkaa oikea -> resetoi - - - - - Hold Y - Pidä Y - - - - - Fix Y - Kesk Y - - - - - Fix X - Kesk X - - - - - Hold X - Pidä X + + Right-double-click to reset to center. + @@ -8862,27 +10137,27 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, ... - + Splash Library - page %1 of %2 Kuvakirjasto - sivu %1 tai %2 - + Warning Varoitus - + Invalid image in library %1 Väärä kuva kirjastossa %1 - + Information Info - + No valid image found in library, check your settings Yhtään kuvaa ei löydy kuva kirjastosta, tarkista asetukset @@ -8890,7 +10165,7 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, StandardPage - + Channel %1 Kanava %1 @@ -8898,43 +10173,41 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, SyncProcess - + %1/%2 files - + Create directory %1 - - Copy %1 to %2 - + + Copy %1 to %2 - - Write %1 - + + Write %1 TailPage - + Rudder Channel: Peräsin kanava: - + Elevator Channel: Korkeusper kanava: - + Only one channel still available!<br>You probably should configure your model without using the wizard. @@ -8942,22 +10215,22 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, TailSelectionPage - + Elevator and Rudder Korkeusper ja peräsin - + Only Elevator Vain korkeusper - + V-tail V-Peräsin - + Tail Type: Perän tyyppi: @@ -9237,7 +10510,7 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, Meters (m or ft) Metrit (m tai jalkaa ) - + Temp (°) Lämpöt (c) @@ -9253,7 +10526,7 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, mAmp (mA) - + Range Matka @@ -9266,22 +10539,22 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, Oman ruudun tyyppi - + None Ei mitään - + Numbers - + Bars Palkit - + Script @@ -9309,99 +10582,99 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, TelemetryPanel - + FrSky S.PORT FrSky S.PORT - + FrSky D FrSky D - + FrSky D (cable) FrSky D (kaapeli) - + Telemetry screen %1 Telemetria ruutu %1 - + Low Alarm Ala hälytys - + Critical Alarm Kriittinen hälytys - + Winged Shadow How High erikoistoiminto korkea - + Winged Shadow How High (not supported) erikoistoiminto korkea (ei tuettu) - + Alti Kork - + Alti+ Kork+ - + VSpeed Vnopeus - - - + + + A1 A1 - - - + + + A2 A2 - - + + A3 A3 - - + + A4 A4 - - + + FAS FAS - + Cells Kennoja - + --- --- @@ -9560,12 +10833,12 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, ft jalka - + °C °C - + °F @@ -9587,26 +10860,36 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, + mW + + + + dBm - + g g - - + + ° ° - + + Rad + + + + mL - + US fl.Oz. @@ -9616,57 +10899,57 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, Raaka ( - ) - + RPM - + Precision - + Ratio - + Blades Prop lavat - + Offset Tasoitus - + Multiplier - + Auto Offset - + Filter Filtteri - + Persistent Yhtämittainen - + Positive Positiivinen - + Logs Logit @@ -9674,22 +10957,22 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, TelemetrySensorPanel - + Lowest - + Cell %1 - + Highest - + Delta @@ -9697,240 +10980,560 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, TelemetrySimulator - + Telemetry Simulator - - Vario Altitude - - - - - V-ALT - - - - - Vario Vertical Speed - - - - - V-VSPD - - - - - ACCZ - - - - - GPS Time - GPS aika - - - - GPS-T - - - - - ACCX - - - - - GPS Lat/Lon - - - - - GPS-LL - - - - + VFAS - - FAS-V - - - - - GPS Speed - - - - - GPS-S - - - - - CELLS - - - - - ACCY - - - - - GPS Course - - - - - GPS-C - - - - - GPS Altitude - - - - - GPS-A - - - - - CURRENT - - - - - FAS-C - - - - - 30 - 9X {30?} - - - + RSSI RSSI - - 75 - 9X {75?} - - - + SWR SWR - - FR_ID_AIR_SPEED - - - - - ASPD - - - - + A1 A1 - + A2 A2 - + + Simulate + Simuloi + + + + Replay SD Log File + + + + + Replay rate + + + + + Load + + + + + |> + + + + + <| + + + + + > + > + + + + <- + + + + + X + X + + + + Row # +Timestamp + + + + + 1/5x + 1/5x + + + + 5x + 5x + + + + No Log File Currently Loaded + + + + + + + V / ratio + + + + + Db + + + + + RxBt + + + + + + + + + + + + + + + + + <html><head/><body><p><br/></p></body></html> + + + + + Tmp1 + + + + A3 A3 - + A4 A4 - - Temperature 1 + + Tmp2 - - T1 - T1 + + Fuel + Bensa - - Temperature 2 + + °C + °C + + + + ml - - T2 - T2 + + Deg. C + - + + % + % + + + + + Meters + + + + + Alt + Kork + + + + VSpd + Vspd + + + + m/s + m/s + + + + Fuel Qty + + + + + + km/h + km/h + + + + Hdg + + + + + ASpd + + + + + + + G + + + + + GPS + + + + + Lat,Lon +(dec.deg.) + + + + + AccX + AccX + + + + dd-MM-yyyy +hh:mm:ss + + + + + Date + + + + + Amps + + + + + AccZ + AccZ + + + + GAlt + + + + + + Volts + + + + + Cels + + + + + Curr + Virta + + + + AccY + AccY + + + + GSpd + + + + + Degrees + + + + + RPM - - FUEL - - - - + When enabled, sends any non-blank values as simulated telemetry data. - - simulate + + Log File - - Instance + + LOG Files (*.csv) - - 2 - 2 + + ERROR - invalid file + + + + + Templates + + + Simple 4-CH + - - <html><head/><body><p>Start with <span style=" font-style:italic;">0x</span> for hex, <span style=" font-style:italic;">0</span> for octal, otherwise decimal.<br/>Numeric entry only. Blank values are not sent.</p></body></html> + + T-Cut + + + + + Sticky T-Cut + + + + + V-Tail + V-Peräsin + + + + Elevon\Delta + + + + + Heli Setup + + + + + Heli Setup with gyro gain control + + + + + Gyro gain control + + + + + Heli Setup (Futaba's channel assignment style) + + + + + Heli Setup with gyro gain control (Futaba's channel assignment style) + + + + + Gyro gain control (Futaba's channel assignment style) + + + + + Servo Test + + + + + MultiCopter + + + + + Use Model Config Wizard + + + + + Apply Template? + + + + + Apply template "%1"? + + + + + + + + + + + RUD + + + + + + + + + + + + + + ELE + + + + + + + THR + KAA + + + + + + + + + + + AIL + + + + + + + + AIL2 + + + + + + + + ELE2 + + + + + + + + + + FLAPS + + + + + + + + + + FLAP%1 + + + + + + + + PITCH + + + + + + + + + + + + GYRO + + + + + + SPOIL + + + + + + SPOIL%1 + + + + + + RUD2 + + + + + + Clear Mixes? + Tyhjennä mikserit? + + + + Really clear existing mixes on CH6? + + + + + Really clear existing mixes on CH5? ThrottlePage - + Yes Kyllä - + No Ei - + <br>Throttle Channel: <br>Kaasu kanava: @@ -9951,37 +11554,37 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, TimerPanel - + Silent Äänetön - + Beeps Piipit - + Voice Ääni - + Haptic Toista värinä - + Not persistent Ei yhtämittainen - + Persistent (flight) Jatkuva (lento) - + Persistent (manual reset) Jatkuva (manuaalinen nollaus) @@ -10112,33 +11715,94 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, TrainerSimulator - + Trainer simulator + + TreeModel + + + Index + + + + + Name + Nimi + + + + Size + + + VTailPage - + First Tail Channel: 1. V-per kanava: - + Second Tail Channel: 2. V-per kanava: + + VirtualJoystickWidget + + + Hld Y + + + + + Hold Vertical stick position. + + + + + Fix Y + Kesk Y + + + + Prevent Vertical movement of stick. + + + + + Fix X + Kesk X + + + + Prevent Horizontal movement of stick. + + + + + Hld X + + + + + Hold Horizontal stick position. + + + WingtypeSelectionPage - + Standard Wing Normaali siipi - + Flying Wing / Deltawing Lentävä siipi / Delta siipi @@ -10146,273 +11810,273 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, WizardDialog - + Model Wizard Apuri - + Model Type Mallin tyyppi - + Enter model name and model type. Anna mallille nimi ja tyyppi. - + Throttle Kaasu - + Has your model got a motor or an engine? Onko mallissa moottoria ? - + Wing Type Siiven tyyppi - + Is your model a flying wing/deltawing or has it a standard wing configuration? Onko malli: Lentäväsiipi / Deltasiipi vai ihan perus siipi ? - + Ailerons Siivekkeet - + Has your model got ailerons? Onko mallissa siivekkeet ? - + Flaps Laipat - + Has your model got flaps? Onko mallissa laipat ? - + Airbrakes Lentojarrut - + Has your model got airbrakes? Onko mallissa lentojarruja ? - + Flying-wing / Delta-wing Lentäväsiipi / Deltasiipi - + Select the elevons channels Valitse elevonien kanavat - + Rudder Sivuperäsin - + Does your model have a rudder? Onko mallissa peräsin ? - + Tail Type Perän tyyppi - + Select which type of tail your model is equiped with. Valitse minkä tyyppinen perä mallissa on. - - + + Tail Perä - - + + Select channels for tail control. Valitse kanava perän ohjaamiseen. - + V-Tail V-Peräsin - + Select elevator channel. Korkeusper kanava. - + Cyclic Sarjoissa - + Which type of swash control is installed in your helicopter? Minkä tyypin "Swash" ohjaus kopterissa on ? - + Tail Gyro Perän gyro - + Has your helicopter got an adjustable gyro for the tail? Onko kopterissa säädettävä gyro perän ohjaamiseen ? - + Rotor Type Roottorin tyyppi - + Has your helicopter got a flybar? Onko kopterissa flybar ? - - + + Helicopter Helikopteri - - + + Select the controls for your helicopter Valitse kopterin ojaimet - + Multirotor Moniroottori - + Select the control channels for your multirotor Valitse moniroottorin ohjain kanavat - + Model Options Mallin valinnat - + Select additional options Vaitse lisävalinnat - + Save Changes Talenna muutokset - + Manually check the direction of each control surface and reverse any channels that make controls move in the wrong direction. Remove the propeller/propellers before you try to control your model for the first time.<br>Please note that continuing removes all old model settings! Tarkasta kaikki ohjain pinnat että ne toimii oikeaan suuntaa! Muista irroittaa propelli kun testaat asetuksia ensimmäistä kertaa. <br> Muista että jos jatkat kaikki vanhat asetukset kyseiseeen malliin poistetaan ! - + Enter a name for your model and select model type. Anna mallille nimi sekä tyyppi. - + Select the receiver channel that is connected to your ESC or throttle servo.<br><br>Throttle - Spektrum: CH1, Futaba: CH3 Valitse vastaanottimen kanava joka on kytketti ESCiin / Kaasun servoon.<br><br>Kaasu - Spektrum: CH1, Futama: CH3 - + Most aircraft have a main wing and a tail with control surfaces. Flying wings and delta winged aircraft only have a single wing. The main control surface on a standard wing controls the roll of the aircraft. This surface is called an aileron.<br>The control surface of a delta wing controls both roll and pitch. This surface is called an elevon. Yleisesti lentokoneissa on siipi ja peräsimet, joissa on ohjainpinnat. Lentäväsiipi ja deltasiipi koneissa on yksi siipi. Siiven ohjainpintoja kutsutaan siivekkeiksi jolla konetta kallistetaan.<br>Lentävänsiiven ja deltasiiven ohjaus tapahtuu siivenohjainpinnalla jolla kone kallistuu sekä nousee tai laskee. - + Models use one or two channels to control the ailerons.<br>A so called Y-cable can be used to connect a single receiver channel to two separate aileron servos. If your servos are connected by a Y-cable you should select the single-servo option.<br><br>Aileron - Spektrum: CH2, Futaba: CH1 Mallit käyttää siivekkeisiin joko yhtä tai kahta kanavaa.<br> Niin kutsuttu Y-kaapeli yhdistää molemmat siiveke servot yhteen kanavaan. Jos yhdistät käyttäen Y-kaapelia niin valitse yhden servon valinta.<br><br>Siiveke -Spektrum: CH2, Futaba: CH:1 - + Models use two channels to control the elevons.<br>Select these two channels Malli käyttää kahta kanavaa elevonien käyttämiseen. <br>Valitse nämä kaksi kanavaa - + This wizard assumes that your flaps are controlled by a switch. If your flaps are controlled by a potentiometer you can change that manually later. Tämä apuri olettaa että laippoja ohjataan kytkimellä. Jos laippoja ohjataan potikalla, voit muuttaa sen myöhemmin valikosta. - + Air brakes are used to reduce the speed of advanced sail planes.<br>They are very uncommon on other types of planes. Lentojarruja käytetään vähentämään lentonopeutta isommissa liidokeissa/ Purjekoneissa.<br> Ne ovat aika harvinaisia muun tyyppisissä koneissa. - + Select the receiver channel that is connected to your rudder.<br><br>Rudder - Spektrum: CH4, Futaba: CH4 Valitse vastaanottimen kanava joka kytketty peräsimeen.<br><br>Peräsin - Spektrum: CH4, Futaba: CH4 - + Select the tail type of your plane. Valitse mallin perän tyyppi. - + Select the Rudder and Elevator channels.<br><br>Rudder - Spektrum: CH4, Futaba: CH4<br>Elevator - Spektrum: CH3, Futaba: CH2 Valitse peräsimen ja korkkarin kanavat.<br><br>Peräsin - Spektrum:CH4, Futaba: CH4<br>Korkkari -Spektrum:CH3, Futaba:CH2 - + Select the Elevator channel.<br><br>Elevator - Spektrum: CH3, Futaba: CH2 Valitse korkkarin kanava.<br><br>Korkkari -Spektrum: CH3, Futaba: CH2 - - - - - - - + + + + + + + TBD. TBD. - + Select the control channels for your multirotor.<br><br>Throttle - Spektrum: CH1, Futaba: CH3<br>Yaw - Spektrum: CH4, Futaba: CH4<br>Pitch - Spektrum: CH3, Futaba: CH2<br>Roll - Spektrum: CH2, Futaba: CH1 Valitse kanavat monimoottorille.<br><br>Kaasu -Spektrum: CH1, Futaba: CH3<br>Yaw - Spektrum: CH4, Futaba: CH4<br>Pitch - Spektrum: CH3, Futaba: CH2<br>Roll - Spektrum: CH2, Futaba: CH1 - + There is no help available for the current page. Tähän kohtaan ei ole tarjolla apu sivua. - + Model Wizard Help Malli apurin ohje @@ -10420,37 +12084,37 @@ Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, WizardPrinter - + Plane Lentokone - + Multicopter Multikopteri - + Helicopter Helikopteri - + Model Name: Mallin nimi: - + Model Type: Mallin tyyppi: - + Options: Valinnat: - + Channel %1: Kanava %1: @@ -10625,44 +12289,44 @@ m2560 joka on v4.1 lähettimessä Käytä lisä toimintoja - + DFU-UTIL Configuration DFU-UTIL määrittely - + SAM-BA Configuration SAM-BA määrittely - + AVRDUDE Configuration AVRDUDE määrittely - - - + + + Select Location Valitse kohde - + List available programmers Lista vapaista ohjelmointilaitteista - + Avrdude help - + Companion Companion - + <b><u>WARNING!</u></b><br>Normally CPU type is automatically selected according to the chosen firmware.<br>If you change the CPU type the resulting eeprom could be inconsistent. <b><u>VAROITUS!</u></b><br>CPU Tyyppi valitaan yleensä valitun firmwaren mukaan.<br>Jos vaihdat CPU Tyyppiä eeprom ei välttämättä toimi oikein. @@ -10719,75 +12383,75 @@ m2560 joka on v4.1 lähettimessä Tallenna - - - - + + + + Error Virhe - + Open Firmware File Avaa firmware tiedosto - + Can not load embedded image from firmware file %1. Ei voi ladata liitettyä kuvaa firmware tiedostosta %1. - + Open Image to load Avaa kuva latausta varten - + Images (%1) Kuvia (%1) - + Cannot load the image file %1. Ei voi ladata kuvaa tiedostosta %1. - + Cannot load profile image %1. Ei voi ladata profiilikuvaa %1. - + Cannot load the library image %1. Ei voi ladata kirjasto kuvaa %1. - + File Saved Tiedosto tallennettu - + The image was saved to the file %1 Kuva on tallennettu tiedostoksi %1 - + Image Refresh Error Kuvan päivitys virhe - + Failed to refresh image from file %1 Ei voi päivitää kuvaa tiedostosta %1 - + File Save Error Tiedoston tallennus virhe - + Failed to write image to %1 Virhe kuvan kirjoituksessa tiedostoon %1 @@ -10800,17 +12464,17 @@ m2560 joka on v4.1 lähettimessä Ladataan: - + Unable to save the file %1: %2. Ei voida tallentaa tiedstoa %1: %2. - + Companion Companion - + Download failed: %1. Lataus epäonnistui %1. @@ -10823,231 +12487,155 @@ m2560 joka on v4.1 lähettimessä Määrittele joystick - + Ch2 CH2 - - - - - - - - - Not Assigned - Ei valittua toimintoa - - - - - - - - - - - Right Vertical - Oikea pysty - - - - - - - - - - - Right Horizontal - Oikea vaaka - - - - - - - - - - - Left Vertical - Vasen pysty - - - - - - - - - - - Left Horizontal - Vasen vaaka - - - - - - - - - - - P1 - P1 - - - - - - - - - - - P2 - P2 - - - - - - - - - - - P3/LS - P3/LS - - - - - - - - - - - RS - RS - - - + Ch1 CH1 - + Ch4 CH4 - + Ch6 CH6 - + Ch3 CH3 - + Ch5 CH5 - + Ch7 CH7 - + Ch8 CH8 - + Instructions Ohjeita - + + Enable + Päälle + + + Cancel Peruuta - + + Back + + + + + Start + Aloitus + + + Next Seuraava - + Ok Ok - - Move sticks and pots in every direction making full movement -Press next when finished - Liikuta tikkuja ja potikoita joka suuntaan, tehden täydet liikeradat -Paina seuraava kun olet valmis + + Not Assigned + - - + + Stick + + + + + Knob/Slider %1 + + + + + No joysticks found + Joystickia ei löydy + + + Error Virhe - + Cannot open joystick. Ei voi avata joystickia. - - Place sticks and pots in middle position. -Press next when done - Laita tikut ja potikat keskiasentoon -Ja paina seuraava kun olet valmis - - - - Map joystick channels to controls using comboboxes. -Press next when done - Liitä joystickin kanavat ohjaimiin käytäen "comboboxeja". -Paina seuraava kun olet valmis - - - - Check inversion checkbox to get maximum at top-right position. -Press next when done - Tarkasta "kääntö ruutu" että saat maksit ylä-oikea asentoon. -Paina seuraava kun olet valmis - - - - Press ok to save configuration -Press cancel to abort joystick calibration - Paina" ok" niin asetukset tallennetaan -Paina "peruuta" niin joystickin kalibrointi perutetaan - - - - Duplicated stick assignment + + Press the Start button to start the stick range calibration procedure. +You may change the channel assignments or inversion at any time. - - - mdiChild - - Simulate Tx - Simuloi Tx + + Move sticks and pots in every direction making full movement +Press Next when finished + + + + + Place sticks and pots in middle position. +Press Next when done + + + + + Map joystick channels to controls using comboboxes. +Press Next when done. + + + + + Check inversion checkbox to if necessary to reverse direction. +Press Next when done. + + + + + Press OK to save configuration +Press Cancel to abort joystick calibration without saving. + + + + + Warning + Varoitus + + + + Calibration not complete, save anyway? + diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 100fcccd8..3d89d602a 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -657,12 +657,12 @@ Peut être différente de la langue du firmware CompanionMacros - + files fichiers - + Radio and Models settings Réglages Radio et Modèles @@ -794,22 +794,22 @@ Peut être différente de la langue du firmware CurveGroup - + Diff - + Expo - + Func Fonc - + Curve Courbe @@ -971,87 +971,87 @@ Peut être différente de la langue du firmware CustomFunctionsPanel - + Switch Interrupteur - + Action - + Parameters Paramètres - + Enable Actif - + SF%1 FS%1 - + GF%1 FG%1 - + ON - + Error Erreur - + Unable to find sound file %1! Impossible de trouver le fichier son %1 ! - + &Delete &Supprimer - + Delete Supprimer - + &Copy &Copier - + Ctrl+C - + &Cut &Couper - + Ctrl+X - + &Paste &Coller - + Ctrl+V @@ -1167,78 +1167,78 @@ Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le EepromInterface - + Possible causes for this: Causes possibles: - + - Eeprom is from a newer version of OpenTX - L'EEPROM peut avoir été créée avec une version d'OpenTX plus récente - + - Eeprom is not from OpenTX - L'EEPROM peut avoir été créée avec un firmware autre qu'OpenTX - + - Eeprom is not from Th9X - L'EEPROM n'est pas une EEPROM TX9X - + - Eeprom is not from Gruvin9X - L'EEPROM n'est pas une EEPROM Gruvin9X - + - Eeprom is not from ErSky9X - L'EEPROM n'est pas une EEPROM ErSky9X - + - Eeprom is not from Er9X - L'EEPROM n'est pas une EEPROM ER9X - + - Eeprom size is invalid - La taille de l'EEPROM est invalide - + - Eeprom file system is invalid - Le système de fichier de l'EEPROM est invalide - + - Eeprom is from a unknown board - L'EEPROM ne correspond à aucune carte supportée - + - Eeprom is from the wrong board - L'EEPROM ne correspond pas au type de radio sélectionné - + - Eeprom backup not supported - Sauvegarde d'EEPROM non supportée - + - Something that couldn't be guessed, sorry - Erreur inconnue - + Warning: Avertissement: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - Le firmware de la radio est probablement incorrect, @@ -1246,14 +1246,14 @@ la taille de l'EEPROM est de 4096 mais seulement 2048 bytes sont utilisés. Vérifier la sélection (M64/M128) - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - Le fichier qui vient d'être ouvert provient d'une ancienne verison d'OpenTX et a été converti. Il est recommandé d'"Enregistrer Sous" au plus vite pour ne pas risquer d'écraser votre ancien fichier. - + Warnings! Avertissements ! @@ -1388,22 +1388,22 @@ Si vide, la ligne est toujours active. Editer %1 - + Click to access popup menu Cliquez pour accéder au menu contextuel - + Clear All Effacer Tout - + Set All Définir Tout - + Invert All Inverser Tout @@ -1952,32 +1952,47 @@ Veuillez utiliser Zadig pour installer le pilote. FlightModePanel - + Rotary Encoder %1 Sélecteur Rotatif %1 - + + Name + Nom + + + + Value source + Source valeur + + + + Value + Valeur + + + GVAR%1 VG%1 - + Popup enabled Indication activée - + &Clear &Effacer - + Clear Effacer - + Clear all current Flight Mode properties? Effacer tout les modes de vols ? @@ -1985,17 +2000,17 @@ Veuillez utiliser Zadig pour installer le pilote. FlightModesPanel - + Flight Mode %1 Phase de vol %1 - + (%1) - + (default) (par défaut) @@ -3614,88 +3629,89 @@ Extra long : bips extra longs. LogicalSwitchesPanel - + V1 - + V2 - + Duration Durée - + Delay Délai - + Function Fonction - + AND Switch ET supplémentaire - + L%1 - - + + (instant) - + &Delete &Supprimer - + Delete Supprimer - + &Copy &Copier - + + (infinite) (infini) - + Ctrl+C - + &Cut &Couper - + Ctrl+X - + &Paste &Coller - + Ctrl+V @@ -3877,14 +3893,14 @@ Les colonnes contenant l'altitude "GAlt" et la vitesse "GSpd MainWindow - - + + Edit Edition - + File Fichier @@ -3976,7 +3992,7 @@ Les colonnes contenant l'altitude "GAlt" et la vitesse "GSpd Afficher les réglages des fusibles - + A monochrome black icon theme Thème avec icônes monochromes noires @@ -4032,52 +4048,52 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Copier le modèle - + A monochrome white icon theme Thème avec icônes monochromes blanches - + A monochrome blue icon theme Thème avec icônes monochromes bleues - + Small Petites - + Use small toolbar icons Petites icônes de barre d'outils - + Use normal size toolbar icons Icônes de barre d'outils normales - + Normal Normales - + Use big toolbar icons Grosses icônes de barre d'outils - + Big Grandes - + Use huge toolbar icons Immenses icônes de barre d'outils - + Huge Immenses @@ -4206,27 +4222,27 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Synchronisation de la carte SD - + Recent Files Fichiers récents - + Recent Models+Settings Fichiers de réglages et modèles récents - + Set Icon Theme Choisir le thème d'icônes - + Set Icon Size Choisir la taille des icônes - + Write Ecrire @@ -4246,12 +4262,12 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Si vous trouvez ce programme utile, merci de le supporter par une <a href='%1'>donation</a> - + Show the list of radio profiles Voir la liste des profils de radio - + Ready Prêt @@ -4426,37 +4442,37 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Utiliser la langue %1 (certaines traductions peuvent être incomplètes). - + Classical Classique - + The classic companion9x icon theme Thème d'icônes classique de Companion - + Yerico - + Yellow round honey sweet icon theme Thème d'icônes rondes jaunes - + Monochrome - + MonoWhite Monochrome Blanc - + MonoBlue Monochrome Bleu @@ -4608,8 +4624,8 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Voulez-vous lancer l'installation ? - - + + Help Aide @@ -4639,33 +4655,33 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Choisir la langue des menus - + Settings Réglages - + Read/Write Transfert - - + + Radio Profile Profil de radio - + Show recent Models+Settings documents Voir les fichiers récents - + %2 - + New Radio Nouvelle radio @@ -4922,7 +4938,7 @@ Enregistrer les changements ? Radio settings - Réglage Radio + Réglages Radio @@ -5132,17 +5148,17 @@ Mixage actif par défaut si non-renseigné. Cliquez pour accéder au menu contextuel - + Clear All Effacer Tout - + Set All Définir Tout - + Invert All Inverser Tout @@ -5360,308 +5376,308 @@ Mixage actif par défaut si non-renseigné. ModelPrinter - + %1 bytes %1 octets - + CH%1 VOIE%1 - + Exponential Exponentiel - + Extra Fine Extra fin - + Fine Fin - + Medium Moyen - + Coarse Grossier - + Unknown Inconnu - + Enabled Actif - + Disabled Inactif - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) %1, Voies(%2-%3), Impulsion(%4µs), Polarité(%5) - + %1, Channels(%2-%3) %1, Voies(%2-%3) - + Receiver number(%1) No. de récepteur(%1) - + radio Protocol %1, subType %2, option value %3 radio Protocol %1, sousType %2, option %3 - + Slave/Jack Elève/Jack - + Master/SBUS Module Maître/SBUS module - + Master/CPPM Module Maître/CPPM Module - + Master/SBUS in battery compartment Maître/SBUS compartiment batterie - + Master/Jack Maître/Jack - + 90 - + 120 - + 120X - + 140 - + Rudder Dérive - + Elevator Profondeur - + Throttle Gaz - + Aileron Ailerons - + Name(%1) Nom(%1) - + Persistent Persistant - + MinuteBeep Bip minutes - + CountDown(Beeps) Cpte à rebours(bips) - + CountDown(Voice) Cpte à rebours(voix) - + CountDown(Haptic) Cpte à rebours(vibreur) - - + + Off - - - - + + + + FM%1 PV%1 - + FM%1%2 PV%1%2 - + FM%1+%2 PV%1+%2 - + [I%1] [E%1] - + Input%1 Entrée%1 - + Weight Ratio - + Switch Inter - - + + NoTrim Pas de trim - + Weight(%1) Ratio(%1) - + Switch(%1) Inter(%1) - + No DR/Expo Pas d'expo/DR - - + + Offset(%1) Décalage(%1) - + Delay(u%1:d%2) Délai(h%1:b%2) - + Slow(u%1:d%2) Ralenti(h%1:b%2) - + Warn(%1) Alerte(%1) - + Disabled in all flight modes Désactivé pour toutes les phases de vol - + Flight modes(%1) Phases de vol(%1) - + Flight mode(%1) Phase de vol(%1) - + Edge(%1, [%2:%3]) Flanc(%1, [%2:%3]) - + instant - + Sticky(%1, %2) Bistable(%1, %2) - + Timer(%1, %2) Chrono(%1, %2) - + Duration(%1s) Durée(%1s) - + Delay(%1s) Délai(%1s) - + Custom Prédéfini - + Standard @@ -5697,7 +5713,7 @@ Mixage actif par défaut si non-renseigné. ModelsListWidget - + No free slot available, cannot duplicate Pas d'emplacement libre, impossible de dupliquer @@ -5905,43 +5921,43 @@ Mixage actif par défaut si non-renseigné. ModulePanel - + Trainer Port Port écolage - + Internal Radio System Module HF interne - + External Radio Module Module HF externe - - + + Radio System Module HF - + Extra Radio System Module HF supplémentaire - + Value Valeur - + Hold Maintien - + No Pulse Pas d'impulsion @@ -5949,256 +5965,256 @@ Mixage actif par défaut si non-renseigné. MultiModelPrinter - + General Model Settings Paramètres généraux - + Name: Nom: - + EEprom Size: Taille d'EEPROM: - + Timer%1: Chrono%1: - + Module%1: - + Module: - + Trainer port: Port écolage: - + Throttle Trim: Trim gaz: - + Trim Increment: Pas des trims: - + Center Beep: Bip de centrage: - + Helicopter Setup Réglage hélicoptère - + Swash Type: Type Cyclique: - + Swash Ring: Anneau Cyclique: - + Input Entrée - + Weight Ratio - + Long. cyc Cyc. longitudinal - + Lateral cyc Cyc. latéral - + Collective Source du pas collectif - + Flight modes Phases de vol - - + + Flight mode Phase de vol - + Switch Inter - + Fade IN Fondu en entrée - + Fade OUT Fondu en sortie - - + + FM%1 PV%1 - - + + GV%1 VG%1 - + RE%1 - + Limits Limites - + Channel Voie - + Name Nom - - + + Offset Décalage - + Min - + Max - + Invert Inversé - + Global Variables Variables globales - + Inputs Entrées - + Mixers Mixages - + CV%1 CB%1 - + Curves Courbes - + L%1 - + Logical Switches Inters logiques - + SF%1 FS%1 - + Special Functions Fonctions spéciales - + Telemetry Settings Paramètres de télémesure - + Analogs Analogiques - + Unit Unité - + Scale Echelle - + A%1 - + RSSI Alarms Alarmes RSSI - + Low Alarm Alarme basse - + Critical Alarm Alarme critique @@ -6354,7 +6370,7 @@ Mixage actif par défaut si non-renseigné. Polonais - + CH%1 VOIE%1 @@ -6389,475 +6405,476 @@ Mixage actif par défaut si non-renseigné. Sel.Rot. E - + Trainer Écolage - + Trainer RUD Écolage Direction - + Trainer ELE Écolage Profondeur - + Trainer THR Écolage Gaz - + Trainer AIL Écolage Ailerons - + Instant Trim Trims instantanés - + Play Sound Jouer Son - + Haptic Vibreur - + S3 - + RSSI Tx - + RSSI Rx - + A3 - + A4 - + Cells Velm - + dTE - + Hdg Cap - + AirSpeed Vitesse Air - + A3- - + A4- - + Speed+ Vit+ - + Dist+ - + AirSpeed+ VitA+ - + Cell- Elem- - + Cells- Velm- - + Vfas- - + Curr+ Cour+ - + Powr+ Puis+ - + ACC - + GPS Time Heure GPS - + L1 - + L2 - + [I%1] [E%1] - + LUA%1%2 - - + + L%1 - + TR%1 - + FM0 PV0 - + FM1 PV1 - + FM2 PV2 - + FM3 PV3 - + FM4 PV4 - + FM5 PV5 - + FM6 PV6 - + FM7 PV7 - + FM8 PV8 - - S31 - - - - - S32 - - - - - S33 - - - - - S34 - - - - - S35 - - - - - S36 - - - - + Trim 5 Down Trim 5 Bas - + Trim 5 Up Trim 5 Haut - + Trim 6 Down Trim 6 Bas - + Trim 6 Up Trim 6 Haut - + One Un - + a>x - + a<x - + |a|>x - + |a|<x - + AND ET - + OR OU - + XOR OUX - + a=b - + a!=b - + a>b - + a<b - + a>=b - + a<=b - + d>=x - + |d|>=x - + a=x - + a~x - + Timer Chrono - + Sticky Bistable - + + Left Horizontal + Gauche Horizontal + + + + Left Vertical + Gauche Vertical + + + + Right Vertical + Droit Vertical + + + + Right Horizontal + Droit Horizontal + + + + Aux. 1 + + + + + Aux. 2 + + + + + Unknown Inconnu - + SD Logs Logs SD - + played once, not during startup !1x Lu une fois, mais pas à la mise en route - + repeat(%1s) Répéter chaque %1s - + DISABLED DESACTIVE - + INV - + NOR - + Reset Remise à zéro - + Set Timer %1 Définir chrono %1 - + Vario - + Volume - + Play Value Lire valeur - + Backlight Rétroéclairage - + Play Track Jouer fichier - - - + + + --- - + Rud Trim Trim Dir - + Ele Trim Trim Prf - + Thr Trim Trim Gaz - + Ail Trim Trim Ail - + Rot Enc Mol Enc @@ -6917,124 +6934,124 @@ Mixage actif par défaut si non-renseigné. Hongrois - + No repeat 1x Lu une fois - + Play Both Jouer les 2 - + Override %1 Remplacer %1 - + Play Script Exécuter script - + Screenshot Capture d'écran - + Background Music Musique de fond - + Background Music Pause Pause musique de fond - + Edge Flanc - - - + + + <font color=red><b>Inconsistent parameter</b></font> <font color=red><b>Paramètre inconsistant</b></font> - + Telemetry Télémesure - + Value Valeur - + Decr: Décr: - + Incr: Incr: - + Played once, not during startup 1x Lu une fois, mais pas à la mise en route - + %1s - + Value Valeur - + Source - + GVAR VG - + Increment Incrément - + Flight Vol - + !Flight mode %1 !Phase de vol %1 - + Flight mode %1 Phase de vol %1 - + Own value Valeur indépendante - + Flight mode %1 value Flight phase %1 value Valeur de la phase de vol %1 @@ -7056,138 +7073,138 @@ Mixage actif par défaut si non-renseigné. - + -GV%1 -VG%1 - + Adjust GV%1 Ajuster VG%1 - + SetFailsafe Int. Module Déf. failsafe module interne - + SetFailsafe Ext. Module Déf. failsafe module externe - + RangeCheck Int. Module Test portée module interne - + RangeCheck Ext. Module Test portée module externe - + Bind Int. Module Bind module interne - + Bind Ext. Module Bind module externe - + Rotary Encoder Sélecteur Rotatif - + -GV%1 (%2) -VG%1 (%2) - + GV%1 (%2) VG%1 (%2) - + Yellow Jaune - + Orange Orange - + Red Rouge - + Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (non supporté) - + FrSky Sensor Hub Sensor Hub FrSky - + None Aucun - + Imperial Impérial - + Metric Métrique - + Uknown error during Simulator startup. Erreur inconnue pendant le démarrage du simulateur. - + Simulator Error Erreur Simulateur - + Data Load Error Erreur de lecture des données - + Error occurred while starting simulator. Une erreur s'est produite lors du démarrage du simulateur. - - + + GV%1 VG%1 - - - - + + + + ---- @@ -7197,19 +7214,19 @@ Mixage actif par défaut si non-renseigné. GAZ - - + + Batt - + SWR - - + + P1 @@ -7220,13 +7237,13 @@ Mixage actif par défaut si non-renseigné. - + V - + s @@ -7310,215 +7327,155 @@ Mixage actif par défaut si non-renseigné. - - + + P2 - - + + P3 - + MAX - - S11 - - - - - S12 - - - - - S13 - - - - - S14 - - - - - S15 - - - - - S16 - - - - - S21 - - - - - S22 - - - - - S23 - - - - - S24 - - - - - S25 - - - - - S26 - - - - + RudTrim Left TrmD Gauche - + RudTrim Right TrmD Droite - + EleTrim Down TrmP Bas - + EleTrim Up TrmP Haut - + ThrTrim Down TrmG Bas - + ThrTrim Up TrmG Haut - + AilTrim Left TrmA Gauche - + AilTrim Right TrmA Droite - + THs GZs - + TH% GZ% - + THt GZt - + ??? - + Diff(%1) - + Expo(%1) - + Function(%1) Fonction(%1) - + Curve(%1) Courbe(%1) - + !Curve(%1) !Courbe(%1) - - + + Rud Dir - - + + Ele Prf - - + + Thr Gaz - - + + Ail Ail - + TrmR TrmD - + TrmE TrmP - + TrmT TrmG - + TrmA TrmA - - - + + + S1 @@ -7588,284 +7545,284 @@ Mixage actif par défaut si non-renseigné. - - - + + + S2 - - - + + + LS - - - + + + RS - + F1 - + F2 - + F3 - + F4 - - + + REa - - + + REb - + Trm5 - + Trm6 - - - + + + Timer3 Chrono 3 - + Alt Altitude - + Rpm - + Fuel Carburant - + Speed Vitesse - + Dist Distance - + GPS Alt Altitude GPS - + Cell Element LiPo - + Vfas Vfas - + Curr Courant - + Cnsp Consommation - + Powr Puissance - + AccX - + AccY - + AccZ - + VSpd Vitesse Verticale - + A1- - + A2- - + Alt- - + Alt+ - + Rpm+ - + T1+ - + T2+ - - + + Time Temps - + CYC%1 - - + + ON - - + + OFF - - + + Support for frsky telemetry mod Support de la télémétrie FrSky - - + + Support for jeti telemetry mod Support de la télémétrie JETI - - + + Support for receiving ardupilot data Support de la télémétrie ARDUPILOT - - + + Support for receiving NMEA data Support de la télémétrie NMEA - + Support for telemetry easy board Support de la carte TelemetrEZ - - + + Support for MAVLINK devices Support du protocole MAVLINK - + Rotary Encoder use in menus navigation Utiliser le sélecteur rotatif pour la navigation - - - - - - + + + + + + Enable heli menu and cyclic mix support Activer le menu hélico et les mixages CCPM - - - - - - + + + + + + Enable TEMPLATES menu Inclure les gabarits - + 6P - + Enable Lua compiler Active le compilateur Lua - + Support for the DIY-Multiprotocol-TX-Module Support du module Multiprotocol @@ -7890,96 +7847,77 @@ Mixage actif par défaut si non-renseigné. Impossible d'écrire le modèle %1 - + JSx - + JSy - + KS108 LCD - + WTV20 voice module Module voix WTV20 - + JQ6500 voice module Module voix JQ6500 - + FrSky Taranis X9D+ - + FrSky Taranis X9D - + Horus gimbals installed (Hall sensors) Manches à effet HALL de Horus installés - + FrSky Taranis X7 - + FrSky Horus - + Use ONLY with first DEV pcb version Exclusivement pour les Horus DEV - + Turnigy 9XR-PRO - + Turnigy 9XR with m128 chip Turnigy 9XR avec une puce m128 - - - - - - No splash screen - Pas d'écran de démarrage - - - - Disable curves menus - Désactiver le menu des courbes - - - - - - - - Support for radio modified with regular speaker - Haut-parleur au lieu du buzzer d'origine + No splash screen + Pas d'écran de démarrage @@ -7987,224 +7925,233 @@ Mixage actif par défaut si non-renseigné. - Used if you have modified your radio with voice mode - Support du module vocal + + Disable curves menus + Désactiver le menu des courbes - - Used if you have modified your radio with haptic mode - Support du vibreur + + Support for radio modified with regular speaker + Haut-parleur au lieu du buzzer d'origine - - Channel values displayed in us - Positions de voies affichées en µs + + + + + + Used if you have modified your radio with voice mode + Support du module vocal - - - - - - - - - - Battery graph - Graphique de batterie - - - - - - - - - - - - - - Use alternative SQT5 font - Utiliser la police alternative SQT5 - - - - Possibility to enable FAI MODE (no telemetry) at field - Possibilité d'activer le mode FAI (télémétrie désactivée) sur le terrain - - - - FAI MODE (no telemetry) always enabled - Mode FAI (télémétrie désactivée) toujours actif - - - - Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) - Le port USB connecte les disques virtuels au lieu du Joystick (comme dans le bootloader) - - - - Instead of Joystick emulation, USB connection is Command Line Interface - Le port USB est utilisé pour un port série avec interface par ligne de commande au lieu du Joystick - - - - Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 - Masque le protocole D8. Légalement obligatoire sur les radios Européennes importées après le 1er janvier 2015 - - - - - Support for PPM internal module hack - Support du remplacement du module interne par un module PPM - - - - ST7565P LCD or compatible - ST7565P LCD ou compatible - - - - ST7565R LCD or compatible - ST7565R LCD ou compatible - - - - ERC12864FSF LCD - LCD ERC12864FSF - - - - ST7920 LCD - LCD ST7920 - - - - - - - Enable the throttle trace in Statistics - Activer l'historique du manche des gaz dans les statistiques - - - - EEprom write progress bar - Barre de progression pour l'écriture de l'EEPROM - - - - - No Winged Shadow How High support - Supprimer le support du variomètre Winged Shadow How High - - - - Turnigy 9XR - - - - - - No vario support - Supprimer la fonction variomètre audio - - - - - No GPS support - Supprimer le support du GPS - - - - - No gauges in the custom telemetry screen - Supprimer l'affichage des valeurs de télémesure par barres - - - - 9X with stock board - 9X avec carte mère d'origine - - - - Allow compensating for offset errors in FrSky FAS current sensors - Permettre la compensation d'un décalage des capteurs de courant FASxx FrSky - - - - - Add support for reversing stick inputs (e.g. needed for FrSky gimbals) - Ajoute le support de l'inversion des manches (nécessaire pour l'utilisation de manches FrSky) - - - - DIY MEGA2560 radio - - - - - Power management by soft-off circuitry - Gestion alim. par software - - - - FrSky Taranis X9E - - - - - Confirmation before radio shutdown - Confirmation avant l'arrêt de la radio - - - - Haptic module installed - Module vibreur installé - - - - Support for Lua model scripts - Support des scripts Lua - - - - - Support of FrSky PXX protocol - Support du protocole PXX FrSky - - - - Disable HELI menu and cyclic mix support - Supprimer le menu HELICO et les mixages cycliques - - - - Disable Global variables - Supprimer le support des variables globales - - - - Support for DSM2 modules - Support du protocole DSM2 + + Used if you have modified your radio with haptic mode + Support du vibreur + + + + Channel values displayed in us + Positions de voies affichées en µs + + + + + + + + + + + + Battery graph + Graphique de batterie + + + + + + + + + + + + + + Use alternative SQT5 font + Utiliser la police alternative SQT5 + + + + Possibility to enable FAI MODE (no telemetry) at field + Possibilité d'activer le mode FAI (télémétrie désactivée) sur le terrain + + + + FAI MODE (no telemetry) always enabled + Mode FAI (télémétrie désactivée) toujours actif + + + + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) + Le port USB connecte les disques virtuels au lieu du Joystick (comme dans le bootloader) + + + + Instead of Joystick emulation, USB connection is Command Line Interface + Le port USB est utilisé pour un port série avec interface par ligne de commande au lieu du Joystick + + + + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 + Masque le protocole D8. Légalement obligatoire sur les radios Européennes importées après le 1er janvier 2015 + + + + + Support for PPM internal module hack + Support du remplacement du module interne par un module PPM + + + + ST7565P LCD or compatible + ST7565P LCD ou compatible + + + + ST7565R LCD or compatible + ST7565R LCD ou compatible + + + + ERC12864FSF LCD + LCD ERC12864FSF + + + + ST7920 LCD + LCD ST7920 + + + + + + + Enable the throttle trace in Statistics + Activer l'historique du manche des gaz dans les statistiques + + + + EEprom write progress bar + Barre de progression pour l'écriture de l'EEPROM + + + + + No Winged Shadow How High support + Supprimer le support du variomètre Winged Shadow How High + + + + Turnigy 9XR + + + + + + No vario support + Supprimer la fonction variomètre audio + + + + + No GPS support + Supprimer le support du GPS + + + + + No gauges in the custom telemetry screen + Supprimer l'affichage des valeurs de télémesure par barres + + + + 9X with stock board + 9X avec carte mère d'origine + + + + Allow compensating for offset errors in FrSky FAS current sensors + Permettre la compensation d'un décalage des capteurs de courant FASxx FrSky + + + + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) + Ajoute le support de l'inversion des manches (nécessaire pour l'utilisation de manches FrSky) + + + + DIY MEGA2560 radio + + + + + Power management by soft-off circuitry + Gestion alim. par software + + + + FrSky Taranis X9E + + + + + Confirmation before radio shutdown + Confirmation avant l'arrêt de la radio + + + + Haptic module installed + Module vibreur installé + + + + Support for Lua model scripts + Support des scripts Lua - - - - - - PPM center adjustment in limits - Neutres PPM ajustables + + Support of FrSky PXX protocol + Support du protocole PXX FrSky + + + + Disable HELI menu and cyclic mix support + Supprimer le menu HELICO et les mixages cycliques + + + + Disable Global variables + Supprimer le support des variables globales + + + + + + + + Support for DSM2 modules + Support du protocole DSM2 @@ -8213,67 +8160,64 @@ Mixage actif par défaut si non-renseigné. + PPM center adjustment in limits + Neutres PPM ajustables + + + + + + + + Symetrical Limits Limites symétriques - - - - - - - + + + + + + + Pots use in menus navigation Support de la navigation dans les menus avec les POTS - + No OverrideCH functions available Désactive la fonction spéciale "Remplacer VOIEx" - - - - - - - - - + + + + + + + + + No flight modes Pas de phases de vol - - + + SmartieParts 2.2 Backlight support Support du rétroéclairage pour la carte SmartieParts 2.2 - - - - - - + + + + + + Enable resetting values by pressing up and down at the same time Permet la remise à zéro des valeurs en pressant haut-bas en même temps, valeur min avec gauche/bas, valeur max avec haut/droite, inversion avec gauche/droite - - - - - - - - - - - No graphical check boxes and sliders - Pas de cases à cocher et de curseurs graphiques - @@ -8284,153 +8228,166 @@ Mixage actif par défaut si non-renseigné. + No graphical check boxes and sliders + Pas de cases à cocher et de curseurs graphiques + + + + + + + + + + + Don't use bold font for highlighting active items Ne pas mettre les lignes actives en gras - - - - - + + + + + EEprom write Progress bar Barre de progression affichée lors des écritures EEPROM - - - - - - + + + + + + Imperial units Unités Impériales - - - + + + Bluetooth interface Interface Bluetooth - - - - - - - - - + + + + + + + + + Global variables Variables globales - - - - - - - - - + + + + + + + + + In model setup menus automatically set source by moving the control Sélectionner les sources des mixeurs en bougeant le contrôle désiré - - - - - - - - - + + + + + + + + + In model setup menus automatically set switch by moving the control Sélectionner les interrupteurs en bougeant le contrôle désiré - + 9X with stock board and m128 chip Carte 9x avec un chip m128 - + 9X with AR9X board 9X avec carte AR9X - + 9X with Sky9x board 9X avec carte Sky9x - + 9X with Gruvin9x board 9X avec carte Gruvin9x - - + + Support for SD memory card Support de la carte SD - + Support for DSM2 modules using ppm instead of true serial Support pour les modules DSM2 par le signal PPM - - - + + + Enable HELI menu and cyclic mix support Activer le menu hélico et les mixages CCPM - - - + + + Timer1 Chrono 1 - - - + + + Timer2 Chrono 2 - + A1 - + A2 - + T1 - + T2 - + Warning Avertissement - + Simulator for this firmware is not yet available Le simulateur n'est pas encore disponible pour ce firmware @@ -8492,22 +8449,22 @@ Mixage actif par défaut si non-renseigné. OpenTX ne supporte pas ce nombre de voies - + Trim disabled Trim désactivé - + Own Trim Valeur indépendante - + Use Trim from Flight mode %1 Utiliser le trim de la phase de vol %1 - + Use Trim from Flight mode %1 + Own Trim as an offset Utiliser le trim de la phase de vol %1 + une valeur indépendante additionnée @@ -8560,7 +8517,7 @@ L'équipe OpenTX. VG - + -%1 @@ -8592,50 +8549,50 @@ L'équipe OpenTX. - - - - - - + + + + + + Error Erreur - + Cannot write file %1: %2. Ecriture fichier %1 impossible: %2. - + Companion - + <b><u>WARNING!</u></b><br>This will reset the fuses of %1 to the factory settings.<br>Writing fuses can mess up your radio.<br>Do this only if you are sure they are wrong!<br>Are you sure you want to continue? <b><u>AVERTISSEMENT !</u></b><br>Ceci réinitialisera les fusibles %1 à leur valeur par défaut.<br>Modifier les fusibles peut entraîner le blocage de votre émetteur.<br>Ne l'effectuer que si vous êtes certain qu'ils sont incorrects !<br>Etes-vous sûr de vouloir continuer ? - - + + Could not delete temporary file: %1 Impossible d'effacer le fichier temporaire %1 - + Unable to find Horus radio SD card! Impossible de trouver la carte SD Horus ! - + Positive - + Negative Négative @@ -8655,10 +8612,11 @@ L'équipe OpenTX. Amp. Positive - - + + Models - Modèles + Translators do NOT use accent for this, this is the default category name on Horus. + Modeles @@ -8760,7 +8718,7 @@ Profil ID: [%1]; Radio ID: [%2] - + Cannot open file %1: %2. Lecture fichier impossible %1: @@ -8768,7 +8726,7 @@ Profil ID: [%1]; Radio ID: [%2] - + Error writing file %1: %2. @@ -8806,7 +8764,7 @@ Profil ID: [%1]; Radio ID: [%2] Fichier EEPROM invalide %1 - + Invalid EEPROM File %1 Fichier EEPROM invalide %1 @@ -9125,6 +9083,29 @@ E Verrouiller/déverrouiller l'inter momentané. + + RawSwitch + + + ↑ + + + + + ↓ + + + + + - + + + + + ! + + + ReleaseNotesDialog @@ -9331,7 +9312,7 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo SetupPanel - + Timer %1 Chrono %1 @@ -10641,99 +10622,99 @@ La valeur par défaut est configurée dans le profil radio sélectionné. TelemetryPanel - + FrSky S.PORT - + FrSky D - + FrSky D (cable) FrSky D (câble) - + Telemetry screen %1 Ecran de télémesure %1 - + Low Alarm Alarme basse - + Critical Alarm Alarme critique - + Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (non supporté) - + Alti Alt - + Alti+ Alt+ - + VSpeed Vitesse verticale - - - + + + A1 - - - - A2 - - - - - - A3 - - - + - A4 + A2 - FAS + A3 + + A4 + + + + + + FAS + + + + Cells Velm - + --- @@ -11016,22 +10997,22 @@ La valeur par défaut est configurée dans le profil radio sélectionné. TelemetrySensorPanel - + Lowest Min - + Cell %1 Elém. %1 - + Highest Max - + Delta @@ -11615,37 +11596,37 @@ hh:mm:ss TimerPanel - + Silent Aucun - + Beeps Bips - + Voice Voix - + Haptic Vibreur - + Not persistent Non persistant - + Persistent (flight) Persistant (vol) - + Persistent (manual reset) Persistant (RAZ manuelle) @@ -12276,29 +12257,29 @@ Consulter la documentation du programmateur utilisé et celle d'AVRDUDE pou Configuration de SAM-BA - - - + + + Select Location Choisir l'emplacement - + List available programmers Lister les programmateurs supportés - + Avrdude help Aide d'AVRDUDE - + Companion - + <b><u>WARNING!</u></b><br>Normally CPU type is automatically selected according to the chosen firmware.<br>If you change the CPU type the resulting eeprom could be inconsistent. <b><u>ATTENTION !</u></b><br>Le type de processeur est normalement choisi automatiquement pour le firmware sélectionné.<br>Si vous le changez, l'EEPROM peut être corrompue lors du transfert. @@ -12552,26 +12533,6 @@ m2560 for v4.1 boards Ch2 VOIE2 - - - Right Vertical - Droit Vertical - - - - Right Horizontal - Droit Horizontal - - - - Left Vertical - Gauche Vertical - - - - Left Horizontal - Gauche Horizontal - Ch1 @@ -12633,7 +12594,7 @@ m2560 for v4.1 boards Démarrer - + Next Suivant @@ -12643,84 +12604,84 @@ m2560 for v4.1 boards OK - + Not Assigned Non assigné - + Stick Manche - + Knob/Slider %1 Potar/Slider %1 - + No joysticks found Aucun Joystick trouvé - + Error Erreur - + Cannot open joystick. Impossible d'accéder au Joystick. - + Press the Start button to start the stick range calibration procedure. You may change the channel assignments or inversion at any time. Appuyer sur le bouton Démarrer afin de lancer la procédure de calibration. Vous pouvez changer l'ordre et la direction des VOIES à n'importe quel moment. - + Move sticks and pots in every direction making full movement Press Next when finished Bouger les manches à fond dans toutes les directions. Cliquer sur Suivant lorsque vous avez terminé - + Place sticks and pots in middle position. Press Next when done Positionner les manches et pots en positon milieu. Cliquer sur Suivant lorsque vous êtes prêts - + Map joystick channels to controls using comboboxes. Press Next when done. Assigner les voies du Joystick en utilisant les boutons. Cliquer sur Suivant lorsque vous êtes prêts. - + Check inversion checkbox to if necessary to reverse direction. Press Next when done. Inverser la direction des VOIES si nécessaire. Cliquer sur Suivant lorsque vous êtes prêts. - + Press OK to save configuration Press Cancel to abort joystick calibration without saving. Cliquer sur OK pour sauvegarder. Cliquer sur Annuler pour interrompre la calibration sans sauvegarder. - + Warning Avertissement - + Calibration not complete, save anyway? Calibration incomplète, sauvegarder tout de même ? diff --git a/companion/src/translations/companion_it.ts b/companion/src/translations/companion_it.ts index 34607c949..cf8f56fc0 100644 --- a/companion/src/translations/companion_it.ts +++ b/companion/src/translations/companion_it.ts @@ -1,30 +1,30 @@ - + AileronsPage - + No No - + Yes, controlled by a single channel Si, controllato da un singolo canale - + Yes, controlled by two channels Si, controllati da due canali - + <br>First Aileron Channel: <br>Canale del primo alettone: - + Second Aileron Channel: Canale del secondo alettone: @@ -32,27 +32,27 @@ AirbrakesPage - + No No - + Yes, controlled by a single channel Si, controllato da un singolo canale - + Yes, controlled by two channels Si, controllati da due canali - + <br>First Airbrake Channel: Canale del primo diruttore: - + Second Airbrake Channel: Canale del secondo diruttore: @@ -69,15 +69,6 @@ Radio Profile Profilo Radio - - - - - - - Open Folder - Apri Cartella - Default Channel Order @@ -315,6 +306,20 @@ Mode 4: A T E R A M E D + + + + + + + Select Folder + + + + + Select Executable + + Use OpenTX firmware nightly builds @@ -423,11 +428,6 @@ Può essere differente dalla lingua del firmware Files to keep Numero di file recenti - - - Find Executable - Cerca eseguibile - Google Earth Executable @@ -524,498 +524,149 @@ Può essere differente dalla lingua del firmware Ricorda la posizione degli switches nel simulatore - + My Radio La mia radio - + Select your snapshot folder Selezionare la cartella per le schermate del simulatore - - + + No joysticks found Nessun joystick trovato - + EMPTY: No radio settings stored in profile VUOTO: Nessuna impostazione radio nel profilo - + AVAILABLE: Radio settings of unknown age DISPONIBILE: Impostazioni di data sconosciuta - + AVAILABLE: Radio settings stored %1 DISPONIBILE: Impostazioni memorizzate %1 - + Select your library folder Selezionare la cartella degli sfondi - - + + Select your Models and Settings backup folder Selezionare la cartella per i backup - + Select Google Earth executable Trova l'eseguibile di Google Earth - + Select the folder replicating your SD structure Selezionare la cartella contenente la struttura della scheda SD - + Not possible to remove profile Non è possibile rimuover il profilo - + The default profile can not be removed. Il profilo predefinito non può essere rimosso. - + Open Image to load Apri l'immagine da caricare - + Images (%1) Immagini (%1) - - Calibration - - - Form - - - - - SQ - - - - - SR - - - - - LS2 - - - - - SP - - - - - SO - - - - - S4 - S4 - - - - RS - RS - - - - SB - SB - - - - Serial Port - Porta Seriale - - - - - - - - - - - - - Beeper volume - -0 - Quiet. No beeps at all. -1 - No Keys. Normal beeps but menu keys do not beep. -2 - Normal. -3 - Loud. -4 - Extra loud. - Volume allarmi - -0 - Silenzioso, nessun beep. -1 - No tastiera. Nessun suono viene generato alla pressione dei rasti. -2 - Normale. -3 - Forte. -4 - Fortissimo. - - - - OFF - Spento - - - - S-Port Mirror - Replica dati S-Port - - - - Telemetry - Telemetria - - - - SBUS Trainer - Maestro/Allievo SBUS - - - - Debug - Debug - - - - Rud - Dir - - - - - Mid value - Valore intermedio - - - - Pot. 4 - Pot. 4 - - - - Pot. 3 - Pot.3 - - - - Pot. 2 - Pot. 2 - - - - Pot. 1 - Pot. 1 - - - - PPM 1 - PPM 1 - - - - Stick 3 - Sick 3 - - - - - Negative span - Corsa negativa - - - - - Positive span - Corsa positiva - - - - Stick 1 - Stick 1 - - - - PPM 2 - PPM 2 - - - - Stick 2 - Stick 2 - - - - Stick 4 - Stick 4 - - - - v - v - - - - PPM Multiplier - Moltiplicatore PPM - - - - PPM 3 - PPM 3 - - - - PPM 4 - PPM 4 - - - - Battery Offset - - - - - Current Offset - - - - - S1 - S1 - - - - S2 - S2 - - - - S3 - S3 - - - - SA - SA - - - - Ele - Ele - - - - Ail - Ale - - - - Thr - Mot - - - - SC - SC - - - - LS - LS - - - - SD - SD - - - - SE - SE - - - - SF - SF - - - - SG - SG - - - - SH - SH - - - - SI - SI - - - - SJ - SJ - - - - SK - SK - - - - SL - SL - - - - SM - SM - - - - SN - SN - - - - RS2 - RS2 - - - - Bluetooth - - - - - CalibrationPanel - - - - - None - Nessuno - - - - 2 Positions Toggle - Momentaneo 2 posizioni - - - - 2 Positions - 2 Posizioni - - - - 3 Positions - 3 Posizioni - - - - Pot with detent - Pot con fermo centrale - - - - Multipos switch - Interruttore Multiposizione - - - - Pot without detent - Potenziometro - - - - Slider with detent - Slider con fermo centrale - - Channels - + Name Nome - + Min Min - + Max Max - + Subtrim Subtrim - + Direction Direzione - + Curve Curva - + PPM Center Centro PPM - + Linear Subtrim Subtrim lineare - - Channel %1 - Canale %1 + + CH%1 + CH%1 - + --- --- - + INV INV + + CompanionMacros + + + files + + + + + Radio and Models settings + + + CompareDialog @@ -1049,17 +700,17 @@ Può essere differente dalla lingua del firmware Stampa su file - + No name Modello senza nome - + Print Document Stampa documento - + Select PDF output file Scegliere il nome del file PDF @@ -1067,7 +718,7 @@ Può essere differente dalla lingua del firmware ConclusionPage - + OK, I understand. Va bene, ho capito. @@ -1075,42 +726,42 @@ Può essere differente dalla lingua del firmware ContributorsDialog - + OpenTX Contributors - + Main Developers - + Other contributors - + Companies and projects who have donated to OpenTX - + People who have donated to OpenTX - + Honors go to Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) Un sentito ringraziamento è dovuto a Rafal Tomczak (RadioClone), Thomas Husterer (th9x) e Erez Raviv (er9x e eePe) - + OpenTX Blacklist - + monthly @@ -1118,24 +769,24 @@ Può essere differente dalla lingua del firmware CopyProcess - - - + + + Error Errore - + Write error Errore di scrittura - + Cannot write %1 (reason: %2) Non posso scrivere %1 (motivo: %2) - + Cannot open %1 (reason: %2) Non posso aprire %1 (motivo: %2) @@ -1143,22 +794,22 @@ Può essere differente dalla lingua del firmware CurveGroup - + Diff Diff - + Expo Espo - + Func Funz - + Curve Curva @@ -1247,72 +898,72 @@ Può essere differente dalla lingua del firmware Nome curva - + Curve %1 Curva %1 - + %1 points punti %1 - + Linear Lineare - + Single Expo Esponenziale singola - + Symmetrical f(x)=-f(-x) Curva simmetrica f(x)=-f(-x) - + Symmetrical f(x)=f(-x) Curva simmetrica f(x)=f(-x) - + Copy Copia - + Paste Incolla - + Clear Cancella - + Clear all curves Cancella tutte le curve - + Are you sure you want to reset curve %1? Volete veramente cancellare la curva %1 ? - + Are you sure you want to reset all curves? Volete veramente cancellare tutte le curve ? - + Editing curve %1 Modifica curva %1 - + Not enough free points in EEPROM to store the curve. Non ci sono abbastanza punti liberi in memoria per salvare la curva. @@ -1320,87 +971,87 @@ Può essere differente dalla lingua del firmware CustomFunctionsPanel - + Switch Interruttore - + Action Azione - + Parameters Parametri - + Enable Abilita - + SF%1 FS%1 - + GF%1 GF%1 - + ON Acceso - + Error Errore - + Unable to find sound file %1! Impossibile trovare il file sonoro %1! - + &Delete &Elimina - + Delete Elimina - + &Copy &Copia - + Ctrl+C Ctrl+C - + &Cut &Taglia - + Ctrl+X Ctrl+X - + &Paste &Incolla - + Ctrl+V Ctrl+V @@ -1408,22 +1059,22 @@ Può essere differente dalla lingua del firmware CyclicPage - + 90 90 - + 120 120 - + 120x 120x - + 140 140 @@ -1431,98 +1082,174 @@ Può essere differente dalla lingua del firmware DebugOutput - + Debug Output Uscita diagnostica + + + <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> + + + + + Filter: + + + + + <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> +To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> + + + + + Buffer: + + + + + Number of lines to keep in display. + + + + + Filter &Help + + + + + Show information about using the filter. + + + + + Word &Wrap + + + + + Toggle word wrapping on/off. + + + + + &Clear + + + + + Clear the output window of all text. + + + + + Enable &Filter + + + + + Turn the filter on/off. + + + + + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> + + + + + Debug Console Filter Help + + EepromInterface - + Possible causes for this: - + - Eeprom is from a newer version of OpenTX - + - Eeprom is not from OpenTX - + - Eeprom is not from Th9X - + - Eeprom is not from Gruvin9X - + - Eeprom is not from ErSky9X - + - Eeprom is not from Er9X - + - Eeprom size is invalid - + - Eeprom file system is invalid - + - Eeprom is from a unknown board - + - Eeprom is from the wrong board - + - Eeprom backup not supported - + - Something that couldn't be guessed, sorry - + Warning: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - + Warnings! @@ -1530,12 +1257,12 @@ Può essere differente dalla lingua del firmware ElevonsPage - + <br>First Elevon Channel: <br>Canale primo Elevone: - + Second Elevon Channel: Canale secondo Elevone: @@ -1652,32 +1379,52 @@ Se vuoto verrà sempre considerata "Attiva". TUTTI - + Edit %1 Modifica %1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + FblPage - + Throttle Channel: Canale motore: - + Yaw Channel: TODO Canale imbardata: - + Pitch Channel: TODO Canale Beccheggio: - + Roll Channel: TODO Canale Rollio: @@ -1731,27 +1478,27 @@ Può essere differente dalla lingua del firmware FlapsPage - + No No - + Yes, controlled by a single channel Si, controllato da un singolo canale - + Yes, controlled by two channels Si, controllati da due canali - + <br>First Flap Channel: <br>Canale primo Flap: - + Second Flap Channel: Canale secondo Flap: @@ -1760,7 +1507,7 @@ Può essere differente dalla lingua del firmware FlashEEpromDialog - + Write Models and Settings to Radio Scrivi Modelli e Impostazioni sulla Radio @@ -1776,7 +1523,6 @@ Può essere differente dalla lingua del firmware - Allows Companion to write to older version of the firmware Consenti a Companion di scrivere a versioni precedenti del firmware @@ -1785,6 +1531,11 @@ Può essere differente dalla lingua del firmware Check Firmware compatibility Verifica compatibilità firmware + + + <html><head/><body><p>Saves a dated copy of your eeprom to the backup folder you specified in the Companion settings before writing the current model to the radio.</p></body></html> + + Backup before Write @@ -1821,107 +1572,66 @@ Può essere differente dalla lingua del firmware Scrivi sulla radio - + Current profile: %1 Profilo attuale: %1 - + Choose Radio Backup file Scegli il file di salvataggio della radio - - - - - - - - - - + + Error Errore - - - Unable to find file %1! - Impossibile trovare il file %1! - - - - - - Error opening file %1: -%2. - Errore durante l'apertura del file %1: -%2. - - - - - Invalid Models and Settings File %1 - File impostazioni non valido %1 - - - - Error reading file %1: -%2. - Error durante la lettura del file %1: -%2. - - Invalid Models and Settings file %1 - File impostazioni e modelli non valido %1 - - - - - - + + + Warning Avviso - + Wrong radio calibration data in profile, Settings not patched Dati errati nel profilo, la calibrazione della radio non è stata sostituita - + Wrong radio setting data in profile, Settings not patched Dati errati nel profilo, i settaggi HW della radio non sono stati sostituiti - - + Cannot write file %1: %2. Non posso scrivere il file %1: %2. - + Error writing file %1: %2. Errore durante la scrittura del file %1: %2. - + The radio firmware belongs to another product family, check file and preferences! Il Firmware appartiene ad un'altra famiglia di prodotti, controllare il file e le preferenze! - + The radio firmware is outdated, please upgrade! Il firmware della radio è obsoleto, per favore aggiornare! - + Cannot check Models and Settings compatibility! Continue anyway? Non posso controllare la compatibilità delle impostazioni! Continuare ugualmente ? @@ -1999,119 +1709,119 @@ Può essere differente dalla lingua del firmware Scrivi sulla radio - + Open Firmware File Apri file del Firmware - - - + + + Warning Avviso - + %1 may not be a valid firmware file %1 potrebbe non essere un file di firmware valido - - - - + + + + Error Errore - + The firmware file is not valid. Il file del firmware non è valido. - + There is no start screen image in the firmware file. Non c'è nessuna immagine di avvio nel firmware selezionato. - + Profile image %1 is invalid. L'immagine del profilo %1 non è valida. - + Open image file to use as radio start screen Apri immagine da utilizzare come sfondo di avvio della radio - + Images (%1) Immagini (%1) - + Image could not be loaded from %1 Impossibile caricare l'immagine da %1 - + The library image could not be loaded L'immagine della libreria non può essere caricata - + Splash image not found Immagine di avvio non trovata - + Cannot save customized firmware Errore durante la scrittura del firmware personalizzato - + Write Firmware to Radio Scrivi Firmware sulla Radio - - + + Firmware check failed Controllo firmware fallito - + Could not check firmware from radio Non posso controllare il firmware dallaradio - + New firmware is not compatible with the one currently installed! Il nuovo firmware non è compatibile con quello attualmente installato! - + Conversion failed Conversione fallita - + Cannot convert Models and Settings for use with this firmware, original data will be used Non posso convertire le impostazioni per questo firmware, verranno usate le impostazioni originali - + Restore failed Ripristino fallito - + Could not restore Models and Settings to Radio. The models and settings data file can be found at: %1 Non è possibile ripristinare Modelli e impostazioni sulla radio. Il file di Modelli e impostazioni può essere trovato in: %1 - + Flashing done Scrittura effettuata @@ -2119,47 +1829,47 @@ Può essere differente dalla lingua del firmware FlashProcess - + Executable %1 not found Eseguibile %1 non trovato - + Writing... Scrittura in corso... - + Reading... Lettura in corso... - + Verifying... Verifica in corso... - + unknown Sconosciuto - + ie: OpenTX for 9X board or OpenTX for 9XR board ad esempio: OpenTX per 9X o OpenTX per 9XR - + ie: OpenTX for M128 / 9X board or OpenTX for 9XR board with M128 chip ad esempio: OpenTX per M128 9X o OpenTX per 9XR con M128 - + ie: OpenTX for Gruvin9X board ad esempio: OpenTX per piastra Gruivin9X - + Your radio uses a %1 CPU!!! Please check advanced burn options to set the correct cpu type. @@ -2168,7 +1878,7 @@ Please check advanced burn options to set the correct cpu type. Per cortesia controllate le opzioni avanzate e impostate il tipo corretto. - + Your radio uses a %1 CPU!!! Please select an appropriate firmware type to program it. @@ -2177,7 +1887,7 @@ Please select an appropriate firmware type to program it. Per cortesia selezionate un firmware corretto per programmarla. - + You are currently using: %1 @@ -2186,7 +1896,7 @@ state attualmente utilizzando: %1 - + Your radio does not seem connected to USB or the driver is not installed!!! Please use ZADIG to properly install the driver. @@ -2195,22 +1905,22 @@ Please use ZADIG to properly install the driver. Usate ZADIG per installare correttamente il driver. - + Your radio does not seem connected to USB or the driver is not initialized!!!. La vostra radio non sembra connessa alla USB o il driver non è inizializzato!!!. - + Flashing done (exit code = %1) Scrittura effettuata (codice di uscita = %1) - + Flashing done with errors Scrittura effettuata con errori - + FUSES: Low=%1 High=%2 Ext=%3 @@ -2241,35 +1951,65 @@ Usate ZADIG per installare correttamente il driver. FlightModePanel - + Rotary Encoder %1 Encoder rotativo %1 - + + Name + Nome + + + + Value source + + + + + Value + Valore + + + GVAR%1 VAR.GLOB%1 - + Popup enabled Popup abilitato + + + &Clear + + + + + Clear + Cancella + + + + Clear all current Flight Mode properties? + + FlightModesPanel - + Flight Mode %1 Fase di volo %1 - + (%1) (%1) - + (default) (Predefinita) @@ -2277,17 +2017,17 @@ Usate ZADIG per installare correttamente il driver. FlybarSelectionPage - + Has Flybar Con Flybar - + Flybarless Senza Flybar - + Flybar: Flybar: @@ -2433,13 +2173,13 @@ p, li { white-space: pre-wrap; } <p align="center" style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Proseguire solo se si sa cosa si sta facendo.</p></body></html> - - + + Reset Radio Fuses Reimposta FUSES della radio - + Read Fuses from Radio Leggi impostazioni FUSES dalla Radio @@ -2448,8 +2188,8 @@ p, li { white-space: pre-wrap; } GeneralEdit - General Edit - Impostazioni generali + Radio settings + @@ -2459,12 +2199,12 @@ These will be relevant for all models in the same EEPROM. Queste impostazioni sono comuni a tutti i modelli nella stessa EEPROM. - + Setup Impostazioni - + Trainer Maestro/Allievo @@ -2479,38 +2219,49 @@ Queste impostazioni sono comuni a tutti i modelli nella stessa EEPROM.Recupera calib. e settaggi HW dal profilo scelto - + Global Functions Funzioni Globali - - Hardware / Calibration - Hardware / Calibrazione + + Hardware + - - + + Calibration + + + + + + Warning Avviso - + Wrong data in profile, radio calibration was not retrieved Dati errati nel profilo, la calibrazione della radio non è stata ripristinata - + + Wrong data in profile, Switch/pot config not retrieved + + + + Wrong data in profile, hw related parameters were not retrieved Dati errati nel profilo, i settaggi HW della radio non sono stati ripristinati - + Do you want to store calibration in %1 profile<br>overwriting existing calibration? Volete salvare la calibrazione e i settaggi nel profilo %1<br>sovrascrivendo i settaggi esistenti ? - + Calibration and HW parameters saved. Dati di calibrazione e settaggi HW salvati. @@ -2568,173 +2319,172 @@ Queste impostazioni sono comuni a tutti i modelli nella stessa EEPROM.SG - + Timeshift from UTC Differenza in ore da GMT - + Voice Language Lingua per le voci - + Country Code Codice paese - + Stick reverse Inverti Stick - + FAI Mode Modalità FAI - - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Se abilitate la modalità FAI, il variometro, le funzioni di lettura della telemetria e gli schermi telemetrici verrano disabilitati. Questa funzione non è disattivabile dalla radio. - + Adjust RTC Aggiusta Orologio - + Vario pitch at max Tono del vario al massimo - - + + Hz Hz - + Speaker Volume Volume altoparlante - + Backlight Switch Interruttore retroilluminazione - + Sound Mode Modalità audio - + Color 1 Colore 1 - + Color 2 Colore 2 - + Speaker Pitch (spkr only) Tonalità suono (modifica HW) - + If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. Se questo valore non è 0, ogni pressione di tasto provocherà l'accensione della luce e questa verrà spenta dopo il numero di secondi specificato. - + sec sec - + Backlight color Colore retroilluminazione - + Beeper Cicalino - + Speaker Altoparlante - + BeeperVoice Cicalino e voce - + SpeakerVoice Altoparlante e Voce - + Beep volume Volume cicalino - + Wav volume Volume file Wav - + Vario volume Volume per vario - + Background volume Volume sottofondo - - + + ms ms - + Backlight Auto OFF after Auto spegnimento luce dopo - + Backlight flash on alarm Retroilluminazione su allarme - + Vario pitch at zero Tono del vario a zero - + Vario repeat at zero Ripetizione vario a zero - + This is the switch selectrion for turning on the backlight (if installed). Questo è l'interruttore selezionato per l'accensione della retroilluminazione (se installata). - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2749,157 +2499,157 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">I valori possono andare da 20 a 45</span></p></body></html> - + Backlight Brightness Luminosità retroilluminazione - + RotEnc Navigation Navigazione con Encoder - + America America - + Japan Giappone - + Europe Europa - + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> <html><head/><body><p>Ordine dei canali</p><p><br/></p><p>Definisce l'ordine delle miscelazioni predefinite durante la creazione di un modello.</p></body></html> - + R E T A D E M A - + R E A T D E A M - + R T E A D M E A - + R T A E D M A E - + R A E T D A E M - + R A T E D A M E - + E R T A E D M A - + E R A T E D A M - + E T R A E M D A - + E T A R E M A D - + E A R T E A D M - + E A T R E A M D - + T R E A M D E A - + T R A E M D A E - + T E R A M E D A - + T E A R M E A D - + T A R E M A D E - + T A E R M A E D - + A R E T A D E M - + A R T E A D M E - + A E R T A E D M - + A E T R A E M D - + A T R E A M D E - + A T E R A M E D - + Mode selection: Mode 1: @@ -2940,138 +2690,138 @@ Mode 4: - + Mode 1 (RUD ELE THR AIL) Modo 1 (DIR ELE MOT ALE) - + Mode 2 (RUD THR ELE AIL) Modo 2 (DIR MOTO ELE ALE) - + Mode 3 (AIL ELE THR RUD) Modo 3 (ALE ELE MOT DIR) - + Mode 4 (AIL THR ELE RUD) Modo 4 (ALE MOT ELE DIR) - + Stick Mode Modo Stick - + Metric Sistema Metrico - + Imperial Imperiale - + Default Channel Order Ordine canali predefinito - + GPS Coordinates Coordinate GPS - + Min Min - - + + v v - + Max Max - + Beeper Mode Modalità suono beeper - + Low Memory Warning Avviso memoria in esaurimento - + Inactivity Timer Temporizzatore di inattività - + Beeper Length Lunghezza suono - + Show Splash Screen on Startup Mostra schermata all'avvio - + Contrast Contrasto - + Battery Meter Range Campo misuratore batteria - + Haptic Strength Intensità vibrazione (mod. HW) - + LCD Display Type Tipo display LCD - + "No Sound" Warning Avviso "nessun suono" - + Battery Warning Allarme batteria scarica - + Haptic Length Lunghezza vibrazione - + MAVLink Baud Rate Baud rate MAVLink - + Haptic Mode Modalità vibrazione - + Beeper volume 0 - Quiet. No beeps at all. @@ -3088,35 +2838,45 @@ Mode 4: 4 - Fortissimo. - - + + Quiet Silenzioso - + Alarms Only Solo allarmi - - + + No Keys No Tasti - - + + All Tutti - + Only Alarms Solo allarmi - + + Automatically adjust the radio's clock if a GPS is connected to telemetry. + + + + + Backlight OFF Brightness + + + + Battery warning voltage. This is the threashhold where the battery warning sounds. @@ -3127,114 +2887,114 @@ Al di sotto di questo valore verrà generato un seganle di allarme. Valori accettabili da 5v a 10v - + Standard Standard - + Optrex Optrex - + If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. Se non è zero, verrà fatto suonare l'allarme se la radio non è utilizzata per il numero di minuti specificato. - + min min - - + + Show splash screen on startup Mostra schermata all'avvio - + --- --- - + 2s 2s - + 3s 3s - + 4s 4s - + 6s 6s - + 8s 8s - + 10s 10s - + 15s 15s - + 4800 Baud 4800 Baud - + 9600 Baud 9600 Baud - + 14400 Baud 14400 Baud - + 19200 Baud 19200 Baud - + 38400 Baud 38400 Baud - + 57600 Baud 57600 Baud - + 76800 Baud 76800 Baud - + 115200 Baud 115200 Baud - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -3259,52 +3019,52 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Suoni disabilitati - avvisa se i suoni sono disabilitati (0)</p></body></html> - - + + X-Short Extra Corto - - + + Short Corto - - + + Normal Normale - - + + Long Lungo - - + + X-Long Extra Lungo - - + + hh° (N/S) mm' ss''.dd hh° (N/S) mm' ss" .dd - + NMEA NMEA - + Play Delay (switch mid position) Ritardo esecuzione(posizione intermedia) - + Measurement Units Unità di misura @@ -3312,7 +3072,7 @@ p, li { white-space: pre-wrap; } GeneralSetupPanel - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Are you sure ? @@ -3325,21 +3085,330 @@ Siete sicuri ? GyroPage - + No No - + Yes, controled by a switch Si, controllato da un interruttore - + Yes, controlled by a pot Si, controllato da un potenziometro + + Hardware + + + Form + + + + + SQ + + + + + SR + + + + + LS2 + + + + + SP + + + + + SO + + + + + S4 + S4 + + + + RS + RS + + + + SB + SB + + + + PPM 2 + PPM 2 + + + + + + + + + + + + + Beeper volume + +0 - Quiet. No beeps at all. +1 - No Keys. Normal beeps but menu keys do not beep. +2 - Normal. +3 - Loud. +4 - Extra loud. + Volume allarmi + +0 - Silenzioso, nessun beep. +1 - No tastiera. Nessun suono viene generato alla pressione dei rasti. +2 - Normale. +3 - Forte. +4 - Fortissimo. + + + + OFF + Spento + + + + S-Port Mirror + Replica dati S-Port + + + + Telemetry + Telemetria + + + + SBUS Trainer + Maestro/Allievo SBUS + + + + Debug + Debug + + + + Rud + Dir + + + + PPM 3 + PPM 3 + + + + S1 + S1 + + + + S2 + S2 + + + + S3 + S3 + + + + PPM 1 + PPM 1 + + + + Serial Port + Porta Seriale + + + + v + v + + + + PPM Multiplier + Moltiplicatore PPM + + + + Current Offset + + + + + PPM 4 + PPM 4 + + + + SA + SA + + + + Ele + Ele + + + + Ail + Ale + + + + Thr + Mot + + + + SC + SC + + + + LS + LS + + + + SD + SD + + + + Battery Offset + + + + + SE + SE + + + + SF + SF + + + + SG + SG + + + + SH + SH + + + + SI + SI + + + + SJ + SJ + + + + SK + SK + + + + SL + SL + + + + SM + SM + + + + SN + SN + + + + RS2 + RS2 + + + + Bluetooth + + + + + ADC Filter + + + + + HardwarePanel + + + + + None + Nessuno + + + + 2 Positions Toggle + Momentaneo 2 posizioni + + + + 2 Positions + 2 Posizioni + + + + 3 Positions + 3 Posizioni + + + + Pot with detent + Pot con fermo centrale + + + + Multipos switch + Interruttore Multiposizione + + + + Pot without detent + Potenziometro + + + + Slider with detent + Slider con fermo centrale + + Heli @@ -3416,22 +3485,22 @@ Siete sicuri ? HeliPage - + Throttle Channel: Canale motore: - + Yaw Channel: Canale imbardata: - + Pitch Channel: Canale Beccheggio: - + Roll Channel: Canale Rollio: @@ -3439,121 +3508,121 @@ Siete sicuri ? InputsPanel - - + + Move Up Muovi Su - - + + Ctrl+Up Ctrl+Up - - + + Move Down Muovi Giù - - + + Ctrl+Down Ctrl+Down - + Clear All Inputs Cancella tutti gli ingressi - + Not enough available inputs! Nessun ulteriore ingresso disponibile! - + Delete Selected Inputs? Cancellare gli ingressi selezionati? - + &Add &Aggiungi - + Ctrl+A Ctrl+A - + &Edit &Modifica - + Enter Invio - + &Delete &Elimina - + Delete Elimina - + &Copy &Copia - + Ctrl+C Ctrl+C - + &Cut &Taglia - + Ctrl+X Ctrl+X - + &Paste &Incolla - + Ctrl+V Ctrl+V - + Du&plicate Dup&lica - + Ctrl+U Ctrl+U - + Clear Inputs? Cancellare gli ingressi? - + Really clear all the inputs? Volete veramente cancellare gli ingressi? @@ -3561,88 +3630,89 @@ Siete sicuri ? LogicalSwitchesPanel - + V1 V1 - + V2 V2 - + Duration Durata - + Delay Ritardo - + Function Funzione - + AND Switch Interruttore AND - + L%1 L%1 - + + + (instant) + + + + &Delete &Elimina - + Delete Elimina - + &Copy &Copia - - - (no release) - (no rilascio) - - - + + (infinite) (infinito) - + Ctrl+C Ctrl+C - + &Cut &Taglia - + Ctrl+X Ctrl+X - + &Paste &Incolla - + Ctrl+V Ctrl+V @@ -3655,146 +3725,166 @@ Siete sicuri ? Visualizzatore di Log di Companion - + Filename Nome file - + Open LogFile Apri file di log - + Zoom Ingrandimento - + X X - + Y Y - + Reset Ripristina - + Fly sessions Sessioni di volo - + Telemetry logs Log telemetrici - + Time (hh:mm:ss) Tempo - + Plot Title Change Cambia titolo del grafico - + New plot title: Nuovo titolo del grafico: - + Axis Label Change Cambia etichetta asse - + New axis label: Nuova etichetta: - + Graph Name Change Cambia nome del grafico - + New graph name: Nuovo nome del grafico: - + Error: no GPS data not found - + The column containing GPS coordinates must be named "GPS". The columns for altitude "GAlt" and for speed "GSpd" are optional - + Error Errore - + Cannot write file %1: %2. Non posso scrivere il file %1: %2. - + + Cursor A: %1 m + + + + + Cursor B: %1 m + + + + + Time delta: %1 + + + + + Climb rate: %1 m/s + + + + Select your log file Selezionare il file di log - + Available fields Campi disponibili - + The selected logfile contains %1 invalid lines out of %2 total lines Il file di log selezionato contiene %1 righe errate su un totale di %2 righe - + total duration durata totale - + duration durata - + (L1) - + (R1) - + (L2) - + (R2) @@ -3802,752 +3892,688 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt MainWindow - - - - + + File loaded Documento caricato - + Display previous warning again at startup ? Mostrare il precedente avviso all'avvio ? - + Checking for updates Controllo aggiornamenti in corso - + Unable to check for updates. Impossibile controllare gli aggiornamenti. - - - + + Save As Salva come - + Executable (*.exe) Eseguibili (*.exe) - + New release available Nuova versione disponibile - - + + No updates available at this time. Nessun aggiornamento disponibile. - + Would you like to launch the installer? Desiderate eseguire l'aggiornamento ? - + Error opening file %1: %2. Errore durante l'apertura del file %1: %2. - - Compilation server termporary failure, try later - Guasto temporaneo del server di compilazione, riprovate più tardi - - - + Compilation server too busy, try later Il server di compilazione è occupato, provate più tardi - + Unknown server failure, try later Errore del server sconosciuto, provare più tardi - + Do you want to write the firmware to the radio now ? Volete scrivere il firmware sulla radio? - - + + File saved Documento salvato - - + + Error Errore - - + + Yes Si - - + + No No - - + + Release Notes Note di aggiornamento - - + + Do you want to download release %1 now ? Volete scaricare la versione %1 adesso ? - - + + Open Models and Settings file Apri modelli e file impostazioni - + Firmware updates Aggiornamenti firmware - + Current firmware does not provide release notes informations. Il firmware selezionato non fornisce note di aggiornamento. - - The selected language will be used the next time you start Companion. - Il linguaggio selezionato sarà usato al prossimo riavvio di Companion. - - - + A new release of Companion is available, please check the OpenTX website! Una nuova versione di Companion è disponibile, visitate il sito Web di OpenTx! - - Not enough memory for all the selected firmware options - Memoria insufficente per tutte le opzioni firmware selezionate - - - + The new theme will be loaded the next time you start Companion. Il nuovo tema sarà caricato al prossimo riavvio di Companion. - + The icon size will be used the next time you start Companion. La dimensione delle icone sarà usata al prossimo riavvio di Companion. - + OpenTX Companion %1 - Radio: %2 - Profile: %3 - + New Nuovo - + Open... Apri... - + Save Salva - + Save As... Salva come... - + Copy Model Copia Modello - + Paste Model Incolla Modello - + A monochrome black icon theme Tema icone monocromatico nero - + A monochrome white icon theme Tema icone monocromatico bianco - + A monochrome blue icon theme tema icone monocromatico blu - + Small Piccole - + Use small toolbar icons Usa icone piccole barra strumenti - + Use normal size toolbar icons Usa icone normali nell barra strumenti - + Normal Normali - + Use big toolbar icons Usa icone grandi barra strumenti - + Big Grandi - + Use huge toolbar icons Usa icone giganti barra strumenti - + Huge Giganti - + Ignore this release %1? Ignorare questa versione %1? - + + Not enough flash available on this board for all the selected options + + + + + Compilation server temporary failure, try later + + + + + Compilation error + + + + + Invalid firmware + + + + + Invalid board + + + + + Invalid language + + + + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + + + + + Models and Settings read + + + + + + This function is not yet implemented + + + + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> Il progetto OpenTx-Companion è originariamente derivato da <a href='%1'>eePe</a> - + Copyright OpenTX Team Copyright OpenTX Team - + Create a new Models and Settings file Crea nuovo modello e file di impostazioni - - + + Save Models and Settings file Salva Modello e file impostazioni - + Exit Esci - + Cut Model Taglia Modello - + Cut current model to the clipboard Taglia e inserisci modello nella clipboard - + Copy current model to the clipboard Copia modello nella clipboard - + Paste model from clipboard Incolla Modello dalla clipboard - + + Use default system language. + + + + + Use %1 language (some translations may not be complete). + + + + Classical Classica - + The classic companion9x icon theme Tema classico icone Companion - + Yerico Yerico - + Yellow round honey sweet icon theme Tema di icone giallo dolce miele rotondo - + Monochrome Monocromatico - + MonoWhite Monocolore Bianco - + MonoBlue Monocolore Blu - + System language Lingua di sistema - - - Use system language in menus - Usa la lingua di sistema - - - - Czech - Ceco - - - - Use Czech in menus - Usa il Ceco nei menu - - - - German - Tedesco - - - - Use German in menus - Usa il Tedesco nei menu - - - - English - Inglese - - - - Use English in menus - Usa l'inglese nei menu - - - - Finnish - Finlandese - - - - Use Finnish in menus - Usa il Fillandese nei menu - - - - French - Francese - - - - Use French in menus - Usa il Francese nei menu - - - - Italian - Italiano - - - - Use Italian in menus - Usa l'Italiano nei menu - - - - Polish - Polacco - - - - Use Polish in menus - Usa il polacco nei menu - - Spanish - Spagnolo - - - - Use Spanish in menus - UtUsa lo spagnolo nei menu - - - - Swedish - Svedese - - - - Use Swedish in menus - Usa lo svedese nei menu - - - About... Informa su... - + Print... Stampa... - + Print current model Stampa il modello corrente - + Simulate... Simula... - + Simulate current model Simula il modello corrente - + Alt+S Alt+S - + Load Backup... Carica salvataggio... - + View Log File... Visualizza file di Log... - + Open and view log file Apri e visualizza file di log - + Settings... Impostazioni... - + Edit Settings Edita Impostazioni - + Download... Scarica... - + Download firmware and voice files Scarica Firmware e file voce - + Check for Updates... Controllo aggiornamenti... - + Check OpenTX and Companion updates Controllo degli aggiornamenti di openTx e Companion - + Companion Changes... Cambiamenti in Companion... - + Show Companion change log Mostra i cambiamenti in Companion - + Firmware Changes... Cambiamenti nel Firmware... - + Show firmware change log Mostra i cambiamenti nel Firmware - + Compare Models... Confronta due modelli... - + Edit Radio Splash Image... Edita immagine Splah della radio... - + Edit the splash image of your Radio Edita immagine splash della tua radio - + List programmers... Lista programmatori... - + Fuses... Fuses... - - + + Read Firmware from Radio Leggi il Firmware dalla Radio - + Read firmware from Radio Leggi firmware dalla Radio - - + Write Firmware to Radio Scrivi Firmware sulla Radio - + Write firmware to Radio Scrivi firmware sulla Radio - + Add Radio Profile Aggiungi profilo Radio - + Create a new Radio Setting Profile Crea un nuovo profilo Radio - + Manuals and other Documents Manuali e altri documenti - + Open the OpenTX document page in a web browser Apri la pagina documenti di OpenTx in un browser web - + Write Models and Settings To Radio Scrivi modello e impostazioni sulla Radio - - + Write Models and Settings to Radio Scrivi Modeli e Impostazioni sulla Radio - - + + Read Models and Settings from Radio Leggi Modelli e Impostazioni dalla Radio - + Configure Communications... Configura Comunicazioni... - + Configure software for communicating with the Radio Configura il software per comunicare con la Radio - + Write Backup to Radio Scrivi salvataggio sulla Radio - + Write Backup from file to Radio Scrivi salvataggio dal file sulla Radio - + Backup Radio to File Salvataggio Radio su File - + Save a complete backup file of all settings and model data in the Radio Salvataggio completo di Impostazioni e Modelli nella Radio - + Contributors... Contributori.... - + A tribute to those who have contributed to OpenTX and Companion Un ringraziamento a tutti coloro che hanno contribuito a OpenTx e Companion - + Recent Files File recenti - + Recent Models+Settings Modelli e Impostazioni recenti - + Set Menu Language Inposta Menu Lingua - + Load backup from file Carica salvataggio da file - + Read Models and Settings From Radio Leggi Modelli e impostazioni dalla Radio - + Save Radio Backup to File Salvataggio Radio su file - + Read Radio Firmware to File Leggi firmware radio su File - + OpenTX Home Page: <a href='%1'>%1</a> OpenTX Home Page: <a href='%1'>%1</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> Se avete trovato utile questo programma prego supportatelo con <a href='%1'>una donazione</a> - + Compare models Confronta due modelli - + Exit the application Esci dall'applicazione - + Show the list of radio profiles Mostra la lista dei profili radio - + Write Scrivi - + A new version of Companion is available (version %1)<br>Would you like to download it? Una nuova versione di Companion è disponibile (versione %1)<br> Vuoi scaricarla? - - Compilation server requires registration, please check OpenTX web site - Server di compilazione richiede la registrazione, prego controllare sul sito web di OpenTx - - - + About Companion Informazioni su Companion - + List available programmers Lista dei programmatori supportati - + Show fuses dialog Mostra finestra di dialogo Fuses - + Show the application's About box Mostra la finestra Informazioni Su - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -4560,7 +4586,7 @@ Volete scaricarla adesso ? Vi raccomandiamo di leggere le note di rilascio sottostanti per vedere se ci siano cambiamenti che possano essere ritenuti da Voi rilevanti. - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -4577,84 +4603,84 @@ Do you want to download it now? We recommend you view the release notes using the button below to learn about any changes that may be important to you. - - - + + + Companion Companion - - + + Synchronize SD Sincronizza SD - + SD card synchronization Sincronizzazione scheda SD - + Set Icon Theme Scegliere il tema di icone - + Set Icon Size Impostazione dimensione icone - - + + File Documento - - + + Edit Modifica - + Settings Impostazioni - + Read/Write Leggi/Scrivi - - + + Help Aiuto - - + + Radio Profile Profilo Radio - + Show recent Models+Settings documents Mostra modell e impostazioni recenti - + Ready Pronto - + %2 %2 - + New Radio Nuova radio @@ -4662,134 +4688,260 @@ We recommend you view the release notes using the button below to learn about an MdiChild - + free bytes byte liberi - + + Companion Companion - + Editing model %1: Modifica modello %1: - - - - - - - - - - - - - - - - - - + + + + + + Error Errore - - + Unable to find file %1! Impossibile trovare il file %1! - - - - + Error opening file %1: %2. Errore durante l'apertura del file %1: %2. - - - Invalid EEPROM File %1 - File impostazioni non valido %1 - - - - - - + Warning Avviso - - + Error reading file %1: %2. Error durante la lettura del file %1: %2. - - Invalid binary EEPROM File %1 - File binario delle impostazioni non valido %1 - - - - - - + + + + Save As Salva Come - - - - - Cannot write file %1: -%2. - Non posso scrivere il file %1: -%2. - - - - - Error writing file %1: -%2. - Errore durante la scrittura del file %1: -%2. - - - + Open backup Models and Settings file Apri salvataggio modelli e impostazioni - + Invalid binary backup File %1 File di backup binario non valido %1 - + %1 has been modified. Do you want to save your changes? %1 è stato modificato. Salvare le modifiche ? - + + Delete selected models? + + + + + Cannot delete default model. + Non posso cancellare il modello predefinito. + + + + &Edit + &Modifica + + + + &Restore from backup + &Ripristina da backup + + + + &Model Wizard + &Assistente di configurazione + + + + &Delete + &Elimina + + + + Delete + Elimina + + + + &Copy + &Copia + + + + Ctrl+C + Ctrl+C + + + + &Cut + &Taglia + + + + Ctrl+X + Ctrl+X + + + + + &Paste + &Incolla + + + + + Ctrl+V + Ctrl+V + + + + D&uplicate + D&uplica + + + + Ctrl+U + Ctrl+U + + + + Move to Category + + + + + &Use as default + &Predefinito + + + + P&rint model + S&tampa modello + + + + Ctrl+P + Ctrl+P + + + + &Simulate model + Sim&ula modello + + + + Alt+S + Alt+S + + + + &Add model + + + + + &Rename category + + + + + &Delete category + + + + + &Add category + + + + + Models and settings will be automatically converted. +If that is not what you intended, please close the file +and choose the correct radio type/profile before reopening it. + + + + + Do you want to overwrite radio general settings? + Vuoi sovrascrivere le impostazioni generali della radio? + + + + You are pasting on an not empty model, are you sure? + State copiando su un modello non vuoto, siete sicuri ? + + + + This category is not empty! + + + + + New model + + + + + Unable to find Horus radio SD card! + + + + + Models and Settings written + + + + Cannot write temporary file! Errore durante la scittura del file temporaneo! + + + Radio settings + + + + + Simulate Tx + Simula TX + MixerDialog @@ -4998,139 +5150,159 @@ Determina come il valore viene aggiunto alla miscelazione. Giù - + DEST -> CH%1 DEST -> CH%1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + MixesPanel - - + + Move Up Muovi in Su - - + + Ctrl+Up Ctrl+Up - - + + Move Down Muovi in Giù - - + + Ctrl+Down Ctrl+Down - + Clear Mixes Cancella Miscelazioni - + Not enough available mixers! Non ci sono più miscelazioni disponibili! - + Delete Selected Mixes? Cancellare le miscelazioni selezionate ? - + &Add &Aggiungi - + Ctrl+A Ctrl+A - + &Edit &Modifica - + Enter Invio - + &Toggle highlight Al&terna evidenziazione - + Ctrl+T Ctrl+T - + &Delete &Elimina - + Delete Elimina - + &Copy &Copia - + Ctrl+C Ctrl+C - + Ctrl+X Ctrl+X - + C&ut Ta&glia - + &Paste &Incolla - + Ctrl+V Ctrl+V - + Du&plicate Du&plica - + Ctrl+U Ctrl+U - + Clear Mixes? Cancellare le miscelazioni ? - + Really clear all the mixes? Sicuri di voler cancellare le miscelazioni ? @@ -5148,52 +5320,52 @@ Determina come il valore viene aggiunto alla miscelazione. Simula Modello - + Setup Impostazioni - + Heli Heli - + Inputs Ingressi - + Logical Switches Interruttori logici - + Mixes Miscelazioni - + Curves Curve - + Flight Modes Fasi di volo - + Outputs Uscite - + Special Functions Funzioni speciali - + Telemetry Telemetria @@ -5201,276 +5373,308 @@ Determina come il valore viene aggiunto alla miscelazione. ModelPrinter - + %1 bytes - + CH%1 CH%1 - + Exponential Esponenziale - + Extra Fine Extra Fine - + Fine Fine - + Medium Medio - + Coarse Ampio - + Unknown Sconosciuto - + Enabled Abilitato - + Disabled Disabilitato - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) - + %1, Channels(%2-%3) - + Receiver number(%1) - + + radio Protocol %1, subType %2, option value %3 + + + + Slave/Jack Allievo/(Presa) - + Master/SBUS Module Maestro/Modulo SBUS - + Master/CPPM Module Maestro/Modulo CPPM - + Master/SBUS in battery compartment Maestro/SBUS nel compartimento batteria - + Master/Jack Maestro/(presa) - + + 90 + 90 + + + + 120 + 120 + + + + 120X + 120X + + + + 140 + 140 + + + Rudder Direzionale - + Elevator Elevatore - + Throttle Motore - + Aileron Alettoni - + Name(%1) - + Slow(u%1:d%2) - + Persistent Persistente - + MinuteBeep - + CountDown(Beeps) - + CountDown(Voice) - + CountDown(Haptic) - + + Off - + NO - - - - + + + + FM%1 FV %1 - + FM%1%2 FV %1%2 - + FM%1+%2 - + [I%1] [I%1] - + Input%1 Ingresso%1 - + Weight Peso - + Switch - + Interruttore - - + + NoTrim NoTrim - + Weight(%1) Peso(%1) - + Switch(%1) Interruttore(%1) - + No DR/Expo No DR/Espo - + + Offset(%1) Spostamento(%1) - + Delay(u%1:d%2) - + Warn(%1) - + Disabled in all flight modes - + Flight modes(%1) Fasi di volo(%1) - + Flight mode(%1) Fase di volo(%1) - + Edge(%1, [%2:%3]) Soglia(%1, [%2:%3]) - + + instant + + + + Sticky(%1, %2) Bloccato(%1, %2) - + Timer(%1, %2) Temporizzatore(%1, %2) - + Duration(%1s) - + Delay(%1s) - + Custom Personalizzato - + Standard Standard @@ -5478,27 +5682,27 @@ Determina come il valore viene aggiunto alla miscelazione. ModelSelectionPage - + Plane Aereo - + Multirotor Multirotore - + Helicopter Elicottero - + Model Name: Nome Modello: - + Model Type: Tipo di modello: @@ -5506,129 +5710,7 @@ Determina come il valore viene aggiunto alla miscelazione. ModelsListWidget - - - &Edit - &Modifica - - - - &Restore from backup - &Ripristina da backup - - - - &Model Wizard - &Assistente di configurazione - - - - &Delete - &Elimina - - - - Delete - Elimina - - - - &Copy - &Copia - - - - Ctrl+C - Ctrl+C - - - - &Cut - &Taglia - - - - Ctrl+X - Ctrl+X - - - - &Paste - &Incolla - - - - Ctrl+V - Ctrl+V - - - - D&uplicate - D&uplica - - - - Ctrl+U - Ctrl+U - - - - &Use as default - &Predefinito - - - - P&rint model - S&tampa modello - - - - Ctrl+P - Ctrl+P - - - - Alt+S - Alt+S - - - - &Simulate model - Sim&ula modello - - - - General Settings - Impostazioni generali radio - - - - Delete Selected Models? - Cancellare i modelli selezionati ? - - - - - Cannot delete default model. - Non posso cancellare il modello predefinito. - - - - Cannot cut default model. - Non posso tagliare il modello predefinito. - - - - Do you want to overwrite radio general settings? - Vuoi sovrascrivere le impostazioni generali della radio? - - - - You are pasting on an not empty model, are you sure? - State copiando su un modello non vuoto, siete sicuri ? - - - + No free slot available, cannot duplicate Nussun spazio di memoria libero, non posso duplicare @@ -5636,142 +5718,199 @@ Determina come il valore viene aggiunto alla miscelazione. Module - + Failsafe Mode Modalità FailSafe - + Start Inizio - + PPM delay Pausa PPM - + Negative Negativo - + Positive Positivo - + Polarity Polarità - + Trainer Mode Modalità maestro allievo - + PPM Frame Length Durata segnale PPM - + CH CH - + + SubType + + + + + Antenna + + + + + Internal + + + + + Ext. + Int. + + + + + Option value + + + + + Bind on startup + + + + + Low Power + + + + us us - + + Multi Radio Protocol + + + + Master/Jack Maestro/(presa) - + Slave/Jack Allievo/(Presa) - + Master/SBUS Module Maestro/Modulo SBUS - + Master/CPPM Module Maestro/Modulo CPPM - + Master/SBUS in battery compartment Maestro/SBUS nel compartimento batteria - + + Show values in: + + + + + % + abbreviation for percent + + + + + μs + abbreviation for microseconds + + + + ms ms - + Channels Canali - + Not set Non impostato - + Hold Mantieni - + Custom Personalizzato - + No Pulses No impulsi - + Receiver Ricevitore - + Failsafe Positions Posizioni Failsafe - + Protocol Protocollo - + Receiver No. Numero Ricev. - + Output type Tipo uscita - + Open Drain - + Push Pull @@ -5779,43 +5918,43 @@ Determina come il valore viene aggiunto alla miscelazione. ModulePanel - + Trainer Port Porta Allievo - + Internal Radio System Sistema Radio interno - + External Radio Module Modulo radio Esterno - - + + Radio System Sistema Radio - + Extra Radio System Sistema radio esteso - + Value Valore - + Hold Mantieni - + No Pulse No impulsi @@ -5823,229 +5962,322 @@ Determina come il valore viene aggiunto alla miscelazione. MultiModelPrinter - + General Model Settings Impostazioni generali del modello - + Name: - + EEprom Size: - + Timer%1: - + Module%1: - + Module: - + Trainer port: - + Throttle Trim: - + Trim Increment: - + Center Beep: - + + Helicopter Setup + + + + + Swash Type: + + + + + Swash Ring: + + + + + Input + Ingresso + + + + Weight + Peso + + + + Long. cyc + + + + + Lateral cyc + + + + + Collective + Collettivo + + + Flight modes Fasi di volo - - + + Flight mode Fase di volo - + Switch - + Interruttore - + Fade IN - + Fade OUT - - + + FM%1 FV %1 - - + + GV%1 VG%1 - + RE%1 - + Limits Limiti - + Channel - + Name Nome - - + + Offset Spostamento - + Min Min - + Max Max - + Invert - + Global Variables Variabili Globali - + Inputs Ingressi - + Mixers Miscelazioni - + CV%1 - + Curves Curve - + L%1 L%1 - + Logical Switches Interruttori logici - + SF%1 FS%1 - + Special Functions Funzioni speciali - + Telemetry Settings Impostazioni telemetria - + Analogs - + Unit Unità - + Scale Campo di misura - + A%1 A%1 - + RSSI Alarms + + + Low Alarm + Allarme basso + + + + Critical Alarm + Allarme critico + + + + Multiprotocols + + + Subtype + + + + + Video TX frequency + + + + + C2500 frequency fine tune + + + + + Telemetry + Telemetria + + + + Radio output power + + + + + Servo output frequency + + + + + Option value + + + + + DEFAULT + + MultirotorPage - + Throttle Channel: Canale Motore: - + Yaw Channel: Canale Imbardata: - + Pitch Channel: Canale Beccheggio: - + Roll Channel: Canale Rollio: @@ -6053,17 +6285,17 @@ Determina come il valore viene aggiunto alla miscelazione. OptionsPage - + Throttle Cut Blocco motore - + Throttle Timer Temporizzatore motore - + Flight Timer Temporizzatore volo @@ -6086,17 +6318,17 @@ Determina come il valore viene aggiunto alla miscelazione. Stampa su file - + Print Document Stampa documento - + Select PDF output file Scegliere il nome del file PDF - + ODF files (*.odt);;PDF Files(*.pdf);;HTML-Files (*.htm *.html);;All Files (*) Documenti ODF (*.odt);;Documenti PDF (*.pdf);;Documenti HTML (*.htm *.html);;Tutti i documenti (*) @@ -6130,2241 +6362,2125 @@ Determina come il valore viene aggiunto alla miscelazione. QObject - + Polish Polacco - + CH%1 CH%1 - + No No - + RotEnc A EncRot A - + Rot Enc B EncRot B - + Rot Enc C EncRot C - + Rot Enc D EncRot D - + Rot Enc E EncRot E - + Trainer Allievo - + Trainer RUD Allievo DIR - + Trainer ELE Allievo ELE - + Trainer THR Allievo MOT - + Trainer AIL Allievo ALE - + Instant Trim Trim Istantanei - + Play Sound Suona - + Play Track Suona Traccia - - Start Logs - Avvia Log - - - + Haptic Vibrazione - - + + °F - + h:m - + m:s - + h:m:s - - + F1 - - + F2 - - + F3 - - + F4 - - + S3 S3 - + RSSI Tx - + RSSI Rx - + A3 A3 - + A4 A4 - + Cells Celle - + dTE - + Hdg - + AirSpeed - + A3- A2- {3-?} - + A4- A2- {4-?} - + Speed+ Velocità+ - + Dist+ - + AirSpeed+ - + Cell- Cella- - + Cells- - + Vfas- - + Curr+ Corr- - + Powr+ - + ACC - + GPS Time Ora GPS - - + L1 - - + L2 - - - L3 - - - - - - L4 - - - - - - L5 - - - - - - L6 - - - - - - L7 - - - - - - L8 - - - - - - L9 - - - - - - L10 - - - - - - L11 - - - - - - L12 - - - - - - L13 - - - - - - L14 - - - - - - L15 - - - - - - L16 - - - - - - L17 - - - - - - L18 - - - - - - L19 - - - - - - L20 - - - - - - L21 - - - - - - L22 - - - - - - L23 - - - - - - L24 - - - - - - L25 - - - - - - L26 - - - - - - L27 - - - - - - L28 - - - - - - L29 - - - - - - L30 - - - - - - L31 - - - - - - L32 - - - - + [I%1] [I%1] - + LUA%1%2 - + + + L%1 + L%1 + + + TR%1 - + FM0 FV0 - + FM1 FV1 - + FM2 FV2 - + FM3 FV3 - + FM4 FV4 - + FM5 FV5 - + FM6 FV6 - + FM7 FV7 - + FM8 FV8 - - S31 - - - - - S32 - - - - - S33 - - - - - S34 - - - - - S35 - - - - - S36 - - - - + One Uno - + a>x - + a<x - + |a|>x - + |a|<x - + AND AND - + OR - + XOR - + a=b - + a!=b - + a>b - + a<b - + a>=b - + a<=b - + d>=x - + |d|>=x - + a=x - + a~x - + Timer Tempo - + Sticky Bloccato - + + Left Horizontal + Orizzontale Sinistro + + + + Left Vertical + Verticale Sinistro + + + + Right Vertical + Verticale Destro + + + + Right Horizontal + Orizzontale Destro + + + + Aux. 1 + + + + + Aux. 2 + + + + + Unknown Sconosciuto - + Override %1 Imposta %1 - + Reset Ripristina - + Set Timer %1 Imposta temporizzatore %1 - + Vario Variometro - + Play Script Esegui Script - + + SD Logs + + + + Volume Volume - + Backlight Retroilluminazione - + played once, not during startup - + repeat(%1s) - + DISABLED DISABILITATO - + INV INV - + NOR NOR - + Play Value Suona valore - - - + + + --- --- - + Rud Trim Trim Dir - + Ele Trim Trim Ele - + Thr Trim Trim Mot - + Ail Trim Trim Ale - + Rot Enc Enc Rot - + English Inglese - + French Francese - + Italian Italiano - + German Tedesco - + Czech Ceco - + Slovak Slovacco - + Spanish Spagnolo - + Portuguese Portoghese - + Swedish Svedese - + + Dutch + + + + + Hungarian + + + + No repeat Non ripetere - + Play Both Suana Entrambi - + Screenshot Cattura schermo - + Background Music Musica di sottofondo - + Background Music Pause Pausa musica di sottofondo - + Edge Soglia - - - + + + <font color=red><b>Inconsistent parameter</b></font> <font color=red><b>Parametro inconsistente</b></font> - + Telemetry Telemetria - + + Trm5 + + + + + Trm6 + + + + SetFailsafe Int. Module - + SetFailsafe Ext. Module - + RangeCheck Int. Module - + RangeCheck Ext. Module - + Bind Int. Module - + Bind Ext. Module - + Value Valore - + Decr: Decr: - + Incr: Incr: - + Played once, not during startup Suona una sola volta, non durante l'avvio - + %1s %1s - + Value Valore - + Source Sorgente - + GVAR VARG - + Increment Incremento - + Flight - + !Flight mode %1 !Fase di volo %1 - + Flight mode %1 Fase di volo %1 - + Own value Legato alla fase - + + -GV%1 (%2) + + + + + GV%1 (%2) + + + + Flight mode %1 value Valore Fase di Volo %1 - + Keys Tasti - + Sticks Leve - + Keys + Sticks Tasti + Leve - - + + -GV%1 -VG%1 - + Adjust GV%1 Regola VG%1 - + Rotary Encoder Encoder rotativo - - Finnish - Finlandese - - - + Yellow Giallo - + Orange Arancione - + Red Rosso - + Winged Shadow How High Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (non supportato) - + FrSky Sensor Hub FrSky Sensor Hub - + None Nessuno - + Imperial Imperiale - + Metric Sistema Metrico - - - + + + Uknown error during Simulator startup. + + + + + Simulator Error + + + + + Data Load Error + + + + + Error occurred while starting simulator. + + + + + + GV%1 VG%1 - - - - + + + + ---- ---- - + THR MOT - - - + + P1 P1 - - - + + P2 P2 - - - + + P3 P3 - - - + + + REa REa - - - + + + REb REb - + Alt Alt - + Rpm - + Fuel - + Speed - + Dist - + GPS Alt - + Cell - + MAX - - + + Rud - - + + Ele - - + + Thr - - + + Ail - - - + + + Timer1 - - - + + + Timer2 - + A1 A1 - + A2 A2 - + T1 - + T2 - - - Simultaneous usage of expo and curves is no longer supported - L'uso simultaneo degli esponenziali e delle curve non è più supportato + + Switch + Interruttore - + + Switch + + + + + cannot be exported on this board! + + + + Source %1 cannot be exported on this board! La sorgente %1 non può essere esportata su questa radio! - + OpenTX only accepts %1 points in all curves OpenTX accetta solamente %1 punti in tutte le curve - + OpenTx only accepts %1 points in all curves OpenTx accetta solamente %1 punti in tutte le curve - - - - - + + + + + + OpenTX on this board doesn't accept this function OpenTX in questa piattaforma non accetta la funzione - + OpenTX doesn't accept this telemetry protocol OpenTX non accetta questo protocollo di telemetria - - - + + + OpenTX doesn't accept this radio protocol OpenTX non accetta questo protocollo di trasmissione - + OpenTX doesn't allow this number of channels OpenTX non consente questo numero di canali - - + + Support for frsky telemetry mod Supporto per la modifica per la telemetria FrSky - - + + Support for jeti telemetry mod Supporto per la modifica per la telemetria Jeti - - + + Support for receiving ardupilot data Supporto per la modifica per la ricezione dati ardupilot - - + + Support for receiving NMEA data Supporto per la modifica per la ricezione dati NMEA - + Support for telemetry easy board Supporto per la scheda Telemetrez - - + + Support for MAVLINK devices Supporto per dispositivi MAVLINK - + Rotary Encoder use in menus navigation Utilizzo dell'encoder rotativo nella navigazione dei menù - - (displaying only first 10 warnings) - (elenco dei primi 10 avvisi) - - - - - - - - + + + + + + Enable heli menu and cyclic mix support Abilita supporto menù elicotteri e miscelazione ciclico - - - - - - - - - + + + + + + Enable TEMPLATES menu Abilita menù dei MODELLI - - - - + + + + No splash screen Disabilita schermata di avvio - - - - - - - - - + + + + + + + + + No flight modes Disabilita supporto fasi di volo - - - - - - - - - - Disable curves menus - Disabilita il menu delle curve - - - - - - - Support for radio modified with regular speaker - Supporto per modifica con altoparlante - - - - - - - - Used if you have modified your radio with voice mode - Utilizzato per la gestione del modulo audio - - - - - - - - Used if you have modified your radio with haptic mode - Abilita supporto vibrazione - - - - Channel values displayed in us - Posizione canali visualizzata in us - - - - - Add support for reversing stick inputs (e.g. needed for FrSky gimbals) - Aggiungi il supporto per l'inversione degli stick (Ad es. necessario per l'utilizzo degli stick FrSky) - - - - M128 / 9X board + + Unknown error - - 9XR + + ... plus %1 errors - - 9XR with M128 chip + + Cannot write radio settings - - Gruvin9x board / 9X + + Cannot write model %1 - - MEGA2560 board + + 6P + 9X {6P?} + + + + JSx - - Power management by soft-off circuitry - Gestione dell'alimentazione mediante pulsante soft-off - - - - Haptic module installed - Modulo vibrazione installato - - - - Support for Lua model scripts - Supporto degli script LUA - - - - - - - - - - - - Battery graph - Grafico della batteria - - - - Use alternative SQT5 font - Usa font alternativo SQT5 (Leggermente quadrato) - - - - No OverrideCH functions available - Nessuna funzione di forzatura CH disponibile - - - - Possibility to enable FAI MODE (no telemetry) at field - Impostazione della modalità FAI (no telemetria) da radio - - - - FAI MODE (no telemetry) always enabled - Modalità FAI (no telemetria) sempre attiva - - - - - - - Support for a third timer - - - - - Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) - - - - - Instead of Joystick emulation, USB connection is Command Line Interface - - - - - Removes D8 and LR12 FrSky protocols that are not legal for use in the EU on radios sold after Jan 1st, 2015 + + JSy + Support for the DIY-Multiprotocol-TX-Module + + + + + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 + + + + + Enable Lua compiler + + + + + KS108 LCD + + + + + WTV20 voice module + + + + + JQ6500 voice module + + + + + FrSky Taranis X9D+ + + + + + FrSky Taranis X9D + + + + + Horus gimbals installed (Hall sensors) + + + + + FrSky Taranis X7 + + + + + FrSky Horus + + + + + Use ONLY with first DEV pcb version + + + + + Turnigy 9XR-PRO + + + + + Turnigy 9XR with m128 chip + + + + + + + + + + Disable curves menus + Disabilita il menu delle curve + + + + + + + + Support for radio modified with regular speaker + Supporto per modifica con altoparlante + + + + + + + + Used if you have modified your radio with voice mode + Utilizzato per la gestione del modulo audio + + + + + + + + Used if you have modified your radio with haptic mode + Abilita supporto vibrazione + + + + DIY MEGA2560 radio + + + + + Channel values displayed in us + Posizione canali visualizzata in us + + + + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) + Aggiungi il supporto per l'inversione degli stick (Ad es. necessario per l'utilizzo degli stick FrSky) + + + + Power management by soft-off circuitry + Gestione dell'alimentazione mediante pulsante soft-off + + + + Haptic module installed + Modulo vibrazione installato + + + + Support for Lua model scripts + Supporto degli script LUA + + + + + + + + + + + + Battery graph + Grafico della batteria + + + + + + + + + + + + + + Use alternative SQT5 font + Usa font alternativo SQT5 (Leggermente quadrato) + + + + No OverrideCH functions available + Nessuna funzione di forzatura CH disponibile + + + + Possibility to enable FAI MODE (no telemetry) at field + Impostazione della modalità FAI (no telemetria) da radio + + + + FAI MODE (no telemetry) always enabled + Modalità FAI (no telemetria) sempre attiva + + + + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) + + + + + Instead of Joystick emulation, USB connection is Command Line Interface + + + + + Support for PPM internal module hack - + ST7565P LCD or compatible Display LCD ST7565R o compatibile - + ERC12864FSF LCD - + ST7920 LCD - - 9X board - - - - - - - + + + + Enable the throttle trace in Statistics Abilita il grafico utilizzo motore nelle statistiche - + EEprom write progress bar Barra di avanzamento durante la scrittura della eeprom - - + + No Winged Shadow How High support Disabilita supporto Winged Shadow How High - - + + Turnigy 9XR + + + + + No vario support Nessun Variometro - - + + No GPS support Disabilita supporto GPS - - + + No gauges in the custom telemetry screen Disabilita schermate telemetriche a barre - + + 9X with stock board + + + + Allow compensating for offset errors in FrSky FAS current sensors Abilita compensazione per errore offset in sensore di corrente FAS FrSky - - ar9x board / 9X - - - - - 9XR-PRO - - - - - FrSky Taranis - - - - - FrSky Taranis Plus - - - - + FrSky Taranis X9E - + Confirmation before radio shutdown - + ST7565R LCD or compatible Display LCD ST7565R o compatibile - - - Adds mixers output view to the CHANNELS MONITOR screen, pressing [ENT] switches between the views - Aggiungi la vista delle uscite dei mixer alla schermata Monitor Canali, premendo [ENT] si intervallano le viste - - - - + + Support of FrSky PXX protocol Supporto del protocollo PXX FrSky - + Disable HELI menu and cyclic mix support Disabilita il menù HELI e le funzioni del piatto ciclico - + Disable Global variables Disabilita variabili globali - - - - - + + + + + Support for DSM2 modules Supporto per moduli DSM2 - - - - - - - - - + + + + + + PPM center adjustment in limits Regolazione del centro PPM nel menù limiti - - - - - - - - - + + + + + + Symetrical Limits Limiti Simmetrici - - - - - - - + + + + + + + Pots use in menus navigation Utilizzo dei potenziometri per la navigazione nei menù - - + + SmartieParts 2.2 Backlight support Abilita il supporto per la scheda SmartiePart versione 2.2 - - - - - - + + + + + + Enable resetting values by pressing up and down at the same time Abilita l'azzeramento di un valore mediante pressione contemporanea di tasti - - - - - - - - - + + + + + + + + + No graphical check boxes and sliders Disabilita grafica per caselle di spunta e cursori - - - - - - - - - + + + + + + + + + Don't use bold font for highlighting active items Non utilizzare font in grassetto per evidenziare le voci attive - - - - - + + + + + EEprom write Progress bar Barra di avanzamento durante la scrittura della eeprom - - - - - - + + + + + + Imperial units Unità Imperiali nella telemetria - - Sky9x board / 9X - - - - - - + + + Bluetooth interface Interfaccia bluetooth - - - - - - - - - + + + + + + + + + Global variables Variabili Globali - - - - - - - - - + + + + + + + + + In model setup menus automatically set source by moving the control Nel menu settaggio modelli selezionare automaticamente la sorgente muovendo il controllo - - - - - - - - - + + + + + + + + + In model setup menus automatically set switch by moving the control Nel menu settaggio modelli selezionare automaticamente l'interruttore muovendo il controllo - - + + 9X with stock board and m128 chip + + + + + 9X with AR9X board + + + + + 9X with Sky9x board + + + + + 9X with Gruvin9x board + + + + + Support for SD memory card Supporto memorie SD - + Support for DSM2 modules using ppm instead of true serial Supporto per moduli DSM2 usando il ppm invece della seriale - - - + + + Enable HELI menu and cyclic mix support Abilita il menù HELI e le funzioni del piatto ciclico - + TrmR - + TrmE - + TrmT - + TrmA - - - - + + + S1 - - - - - - - + + + + + + + V - - + + s - + ft - - - + + + m - - - + + + °C - - - + + + ° - - + + % - - - + + + mph - - - + + + km/h - - + + m/s - - + + A - + mA - + kts - + f - - + + mAh - - + + W - + + mW + + + + dB - + rpms - - + + g - + + Rad + + + + hours - + minutes - + seconds - - - - + + + S2 - - - - + + + LS - - - - + + + RS - - + + Batt Batt - - - + + + Timer3 Tempo3 - + Vfas - + Curr - + Cnsp - + Powr - + AccX - + AccY - + AccZ - + VSpd - + A1- A1- - + A2- A2- - + Alt- - + Alt+ - + Rpm+ - + T1+ - + T2+ - - + + Time Tempo - + CYC%1 - - S11 - - - - - S12 - - - - - S13 - - - - - S14 - - - - - S15 - - - - - S16 - - - - - S21 - - - - - S22 - - - - - S23 - - - - - S24 - - - - - S25 - - - - - S26 - - - - + RudTrim Left Trim Dir Sinistro - + RudTrim Right Trim Dir Destro - + EleTrim Down Trim Ele Giù - + EleTrim Up Trim Ele Su - + ThrTrim Down Trim Mot Giù - + ThrTrim Up Trim Mot Su - + AilTrim Left Trim Ale Sinistro - + AilTrim Right Trim Ale Destro - + + Trim 5 Down + + + + + Trim 5 Up + + + + + Trim 6 Down + + + + + Trim 6 Up + + + + THs MOs - + TH% MO% - + THt MOt - + ??? - + Diff(%1) Diff(%1) - + Expo(%1) Espo(%1) - + Function(%1) funzione(%1) - + Curve(%1) Curva(%1) - + !Curve(%1) !Curva(%1) - + SWR - - - + + + ON - - - + + + OFF - - + Warning Avviso - - EEPROM saved with these warnings: - EEPROM salvata con questi avvisi: - - - + Simulator for this firmware is not yet available Il simulatore per questo firmware non è ancora disponibile - - th9x on this board doesn't have Rotary Encoders - th9x non ha gli Encoder Rotativi - - - + Trim disabled Trim disabilitato - + Own Trim Trim proprio - + Use Trim from Flight mode %1 Usa Trim della Fase di volo %1 - + Use Trim from Flight mode %1 + Own Trim as an offset Usa Trim della Fase di volo %1 + Trim proprio come offset - + FW: %1 FW: %1 - + Pict: %1 immag: %1 - + Profile image Immagine profilo - - Simultaneous usage of expo and curves is no longer supported in OpenTX - L'uso simultaneo di esponeziali e curve non è più supportato in OpenTX - - - + Thank you for upgrading to OpenTX 2.0. This is a major upgrade that adds and modifies a lot of things, so please make sure that you read release notes carefully to learn about the changes, and thoroughly check each of your models for proper function. The OpenTX Team. @@ -8373,98 +8489,496 @@ The OpenTX Team. Il Team di OpenTX. - - - - - + + + + + Synchronization error Errore di sincronizzazione - + No SD directory configured! - + No Radio connected! Radio non connessa! - + GV VG - + -%1 - - + + The directory '%1' doesn't exist! la cartella '%1' non esiste! - + Create '%1' failed Creazione di '%1' fallita - + Copy '%1' to '%2' failed Copia di '%1' in '%2' fallita - + Open '%1' failed Apertura di '%1' fallita - + Write '%1' failed Scrittura di '%1' fallita - - - + + + + + + + Error Errore - + Cannot write file %1: %2. Non posso scrivere il file %1: %2. - + Companion Companion - + <b><u>WARNING!</u></b><br>This will reset the fuses of %1 to the factory settings.<br>Writing fuses can mess up your radio.<br>Do this only if you are sure they are wrong!<br>Are you sure you want to continue? <b><u>ATTENZIONE!</u></b><br>Questa operazione ripristinerà i fuse del processore %1 ai valori di fabbrica.<br>Modificare i fuse pruo bloccare la radio.<br>Fatelo solo se siete assolutamente sicuri che siano sbagliati<br>sicuri di voler continuare ? - - + + Could not delete temporary file: %1 Non posso cancellare il file temporaneo: %1 - - Radio type + + Unable to find Horus radio SD card! - - Which radio type do you want to simulate? + + Conversion error on field %1 + + + + + Negative span + Corsa negativa + + + + Mid value + Valore intermedio + + + + Positive span + Corsa positiva + + + + + Models + Translators do NOT use accent for this, this is the default category name on Horus. + + + + + Positive + Positivo + + + + Negative + Negativo + + + + Select a data file + + + + + Select Data Directory + + + + + Select SD Card Image Folder + + + + + Available profiles: + + + + + ID: + + + + + Name: + + + + + Available radios: + + + + + WARNING: couldn't initialize SDL: +%1 + + + + + ERROR: No simulator libraries available. + + + + + Radio profile ID or Name to use for simulator. + + + + + Radio type to simulate (usually defined in profile). + + + + + show this help text + + + + + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] + + + + + Options: + + + + + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. + Profile ID: [%1]; Radio ID: [%2]; +Data File: [%3] + + + + + ERROR: Radio profile or simulator firmware not found. +Profile ID: [%1]; Radio ID: [%2] + + + + + Error reading %1: %2 + + + + + Cannot save EEPROM + + + + + + Cannot open file %1: +%2. + + + + + + + Error writing file %1: +%2. + Errore durante la scrittura del file %1: +%2. + + + + Invalid binary EEPROM file %1 + + + + + Can't extract RADIO/radio.bin + + + + + Can't extract RADIO/models.txt + + + + + Can't extract %1 + + + + + Unable to open %1: %2 + + + + + Invalid EEPROM file %1 + + + + + Invalid EEPROM File %1 + File impostazioni non valido %1 + + + + + Error opening file %1: +%2. + Errore durante l'apertura del file %1: +%2. + + + + Error opening OTX archive %1 + + + + + Error initializing OTX archive writer + + + + + Error creating OTX file %1: +%2. + + + + + Error creating OTX archive + + + + + Error adding %1 to OTX archive + + + + + Error opening file %1 in write mode: +%2. + + + + + Unable to find file %1! + Impossibile trovare il file %1! + + + + QxtCommandOptions + + + sets the application GUI style + + + + + sets the application stylesheet + + + + + restores the application from an earlier session + + + + + displays debugging information about widgets + + + + + use right-to-left layout + + + + + never grab the mouse or keyboard + + + + + grab the mouse/keyboard even in a debugger + + + + + run in synchronous mode for debugging + + + + + use Direct3D by default + + + + + sets the X11 display + + + + + sets the geometry of the first window + + + + + sets the default font + + + + + sets the default background color + + + + + sets the default foreground color + + + + + sets the default button color + + + + + sets the application name + + + + + sets the application title + + + + + sets the X11 visual type + + + + + limit the number of colors on an 8-bit display + + + + + use a private color map + + + + + sets the input method server + + + + + disable the X Input Method + + + + + sets the style used by the input method + + + + + + option "%1" not found + + + + + Short options cannot have optional parameters + + + + + positional() called before parse() + + + + + unrecognized() called before parse() + + + + + count() called before parse() + + + + + value() called before parse() + + + + + parameters() called before parse() + + + + + unrecognized parameters: + + + + + %1 requires a parameter + + + + + RadioKnobWidget + + + Right-double-click to reset to center. @@ -8486,10 +9000,100 @@ Il Team di OpenTX. OK + + RadioOutputsWidget + + + Form + + + + + View: + + + + + Logical Switches + Interruttori logici + + + + Global Variables + Variabili Globali + + + + Channel Outputs + + + + + L +o +g +i +c + + + + + G +l +o +b +a +l + + + + + C +h +a +n +n +e +l +s + + + + + RadioSwitchWidget + + + Latch/unlatch the momentary switch. + + + + + RawSwitch + + + ↑ + + + + + ↓ + + + + + - + + + + + ! + + + ReleaseNotesDialog - + Companion Release Notes Note di aggiornamento di Companion @@ -8497,7 +9101,7 @@ Il Team di OpenTX. ReleaseNotesFirmwareDialog - + OpenTX Release Notes informazioni su aggiornamenti OpenTX @@ -8505,17 +9109,17 @@ Il Team di OpenTX. RudderPage - + No No - + Yes Si - + <br>Rudder Channel: <br>Canale Direzionale: @@ -8692,7 +9296,7 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà SetupPanel - + Timer %1 @@ -8700,179 +9304,847 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà SimpleTailPage - + Elevator Channel: Canale dell'Elevatore: - SimulatorDialog + SimulatedUIWidget - - + + Rotary encoder click + + + + + Take Screenshot + + + + + screenshot + Simulator LCD screenshot file name prefix + + + + + SimulatedUIWidget9X + + + UP/PG-UP + + + + + [ UP ] + + + + + DN/PG-DN + + + + + [ DN ] + + + + + RIGHT/+ + + + + + [ + ] + + + + + LEFT/- + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + [ UP ]/[ DN ] or Rotary Sel. + + + + + SimulatedUIWidgetX12 + + + PG-UP + + + + + [ PgUp ] + + + + + PG-DN + + + + + [ PgDn ] + + + + + UP + + + + + [ MDL ] + + + + + DN/DEL/BKSP + + + + + [ RTN ] + + + + + LEFT + + + + + [ SYS ] + + + + + RIGHT + + + + + [ TELE ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/X + + + + + Rotary UP + + + + + +/C + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX7 + + + Taranis X7 Simulator + + + + + PG-UP + + + + + [ PAGE ] + + + + + PG-DN + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX9 + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + +/UP + + + + + [ + ] + + + + + -/DN + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ ENT ] + + + + + WHEEL/PAD SCRL + + + + + [ + ]/[ - ] + + + + + SimulatedUIWidgetX9E + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatorMainWindow + + + OpenTx Simulator + + + + + View + + + + + Radio Window + + + + + Reload... + + + + + Tools + + + + + Toolbar + + + + + Reload Lua Scripts + + + + + Reload the Lua environment on the simulated radio. + + + + + F7 + + + + + Reload Radio Data + + + + + Reload all radio data without restarting the simulator. + + + + + F9 + + + + + Key Mapping + + + + + Show keyboard maping reference. + + + + + F1 + + + + + Joystick Settings + + + + + Open joystick configuration settings dialog. + + + + + F3 + + + + + LCD Screenshot + + + + + Save a screenshot of the current simulated LCD screen. + + + + + F8 + + + + + Dock In Main Window + + + + + Show the radio in the main window or as a separate "floating" window. + + + + + Menu Bar + + + + + Show or hide the top menu bar. + + + + + Alt+M + + + + + Constrain Width + + + + + Set radio widget width to be a fixed size. + + + + + Constrain Height + + + + + Set radio widget height to be a fixed size. + + + + + ERROR: Failed to create simulator interface, possibly missing or bad library. + + + + + Alt+T + + + + + Radio Outputs + + + + + F2 + + + + + Telemetry Simulator + Simulatore Telemetria + + + + F4 + + + + + Trainer Simulator + + + + + F5 + + + + + Debug Output + Uscita diagnostica + + + + F6 + + + + + Simulator Controls: + + + + + <tr><th>Key/Mouse</td><th>Action</td></tr> + + + + + Simulator Help + + + + + SimulatorStartupDialog + + + OpenTX Simulator - Startup Options + + + + + Simulator Startup Options: + + + + + Radio Profile: + + + + + Existing radio profiles are shown here.<br /> +Create or edit profiles using the Companion application. + + + + + Radio Type: + + + + + Existing radio simulators are shown here.<br /> +The radio type specified in the selected profile is used by default. + + + + + Data Source: + + + + + Data File: + + + + + Data Folder: + + + + + SD Image Path: + + + + + Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> +<b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! + + + + + Select data file... + + + + + + + ... + ... + + + + Directory containing RADIO and MODELS folders to use.<br /> +New folder(s) with default radio/model will be created here if necessary. + + + + + Select data folder... + + + + + Directory containing the SD card image to use.<br/> +The default is configured in the chosen Radio Profile. + + + + + Select SD card image folder... + + + + + Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. + + + + + File + Documento + + + + Folder + + + + + SD Path + + + + + All files (*.*) + + + + + SimulatorWidget + + + Companion Simulator + Simulatore di Companion + + + + Radio Simulator (%1) + + + + + Could not determine startup data source. + + + + + Could not load data, possibly wrong format. + + + + + Data Load Error + + + + + Invalid startup data provided. Plese specify a proper file/path. + + + + + Simulator Startup Error + + + + + Error saving data: could open file for writing: '%1' + + + + + Error saving data: could not get data from simulator interface. + + + + + An unexpected error occurred while attempting to save radio data to file '%1'. + + + + + Data Save Error + + + + Warning - Avviso + Avviso - - Joystick enabled but not configured correctly - Joystick abilitato ma non configurato correttamente - - - + Cannot open joystick, joystick disabled - Non riesco ad aprire il joystick, supporto joystick disabilitato + Non riesco ad aprire il joystick, supporto joystick disabilitato - - Simulating Radio (%1) - Simulazione Radio (%1) - - - - - Outputs - Uscite - - - + Firmware %1 error: %2 - Firmware %1 errore: %2 + Firmware %1 errore: %2 - SimulatorDialog9X + SliderWidget - - Companion Simulator - Simulatore di Companion - - - - - - - Right Double Click to Reset - Doppio click con il destro per portare a 0 - - - - - Hold X - Mantieni X - - - - - Fix X - Blocca X - - - - - Fix Y - Blocca Y - - - - - Hold Y - Mantieni Y - - - - Outputs2 - Uscite2 - - - - Gvars - Var Glob - - - - BEEP - SUONO - - - - 9x Simulator - Simulatore 9x - - - - Outputs - Uscite - - - - SimulatorDialogTaranis - - - Companion Simulator - Simulatore di Companion - - - - Outputs2 - Uscite2 - - - - Gvars - Var Glob - - - - S3 - S3 - - - - S4 - S4 - - - - - Hold Y - Mantieni Y - - - - - Fix Y - Blocca Y - - - - - Fix X - Blocca X - - - - - Hold X - Mantieni X - - - - - - - Right Double Click to Reset - Doppio click con il destro per portare a 0 - - - - Taranis Simulator - Simulatore Taranis - - - - Outputs - Uscite + + Right-double-click to reset to center. + @@ -8884,27 +10156,27 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà - + Splash Library - page %1 of %2 Libreria sfondi - pagina %1 di %2 - + Warning Avviso - + Invalid image in library %1 Immagine corrotta nella libreria %1 - + Information Informazione - + No valid image found in library, check your settings Nessuna immagine trovata nella libreria, controllate le impostazioni @@ -8912,7 +10184,7 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà StandardPage - + Channel %1 Canale %1 @@ -8920,43 +10192,41 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà SyncProcess - + %1/%2 files - + Create directory %1 Crea directory %1 - - Copy %1 to %2 - - Copia %1 su %2 + + Copy %1 to %2 + Copia %1 su %2 {1 ?} {2?} - - Write %1 - - Scrivi %1 + + Write %1 + Scrivi %1 {1?} TailPage - + Rudder Channel: Canale Direzionale: - + Elevator Channel: Canale Elevatore: - + Only one channel still available!<br>You probably should configure your model without using the wizard. @@ -8964,22 +10234,22 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà TailSelectionPage - + Elevator and Rudder Elevatore e Deriva - + Only Elevator Solo Elevatore - + V-tail Coda a V - + Tail Type: Tipo di coda: @@ -9259,7 +10529,7 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà Meters (m or ft) Metri (m o ft) - + Temp (°) Temperatura (°) @@ -9275,7 +10545,7 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà Corrente (mA) - + Range Intervallo @@ -9288,22 +10558,22 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà Tipo schermo personalizzato - + None Nessuno - + Numbers Numeri - + Bars Barre - + Script Script @@ -9331,99 +10601,99 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà TelemetryPanel - + FrSky S.PORT FrSky S.PORT - + FrSky D FrSky D - + FrSky D (cable) FrSky D (su cavo) - + Telemetry screen %1 Schermo telemetria %1 - + Low Alarm Allarme basso - + Critical Alarm Allarme critico - + Winged Shadow How High Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (non supportato) - + Alti - + Alti+ - + VSpeed - - - + + + A1 A1 - - - + + + A2 A2 - - + + A3 A3 - - + + A4 A4 - - + + FAS FAS - + Cells Celle - + --- --- @@ -9582,12 +10852,12 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà ft - + °C - + °F @@ -9609,26 +10879,36 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà + mW + + + + dBm - - g - - - - ° + g - mL + ° + Rad + + + + + mL + + + + US fl.Oz. @@ -9638,57 +10918,57 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà Grezza (-) - + RPM - + Precision Precisione - + Ratio - + Blades Pale dell'elica - + Offset Spostamento - + Multiplier Moltiplicatore - + Auto Offset - + Filter Filtra - + Positive Positivo - + Logs Registra - + Persistent Persistente @@ -9696,22 +10976,22 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà TelemetrySensorPanel - + Lowest Minore - + Cell %1 Cella %1 - + Highest Maggiore - + Delta Diff @@ -9719,240 +10999,560 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà TelemetrySimulator - + Telemetry Simulator Simulatore Telemetria - - Vario Altitude - Altitudine Vario - - - - V-ALT - - - - - Vario Vertical Speed - Velocità verticale Vario - - - - V-VSPD - - - - - ACCZ - - - - - GPS Time - Ora GPS - - - - GPS-T - - - - - ACCX - - - - - GPS Lat/Lon - - - - - GPS-LL - - - - + VFAS - - FAS-V - - - - - GPS Speed - - - - - GPS-S - - - - - CELLS - CELLE - - - - ACCY - - - - - GPS Course - Rotta GPS - - - - GPS-C - - - - - GPS Altitude - Altitudine GPS - - - - GPS-A - - - - - CURRENT - CORRENTE - - - - FAS-C - - - - - 30 - 9X {30?} - - - + RSSI RSSI - - 75 - 9X {75?} - - - + SWR - - FR_ID_AIR_SPEED - - - - - ASPD - - - - + A1 A1 - + A2 A2 - + + Simulate + Simula Modello + + + + Replay SD Log File + + + + + Replay rate + + + + + Load + + + + + |> + + + + + <| + + + + + > + > + + + + <- + + + + + X + X + + + + Row # +Timestamp + + + + + 1/5x + 9X {1/5x?} + + + + 5x + 9X {5x?} + + + + No Log File Currently Loaded + + + + + + + V / ratio + + + + + Db + + + + + RxBt + + + + + + + + + + + + + + + + + <html><head/><body><p><br/></p></body></html> + + + + + Tmp1 + + + + A3 A3 - + A4 A4 - - Temperature 1 - Temperatura 1 + + Tmp2 + - - T1 - + + Fuel + - - Temperature 2 - Temperatura 2 + + °C + - - T2 - + + ml + - + + Deg. C + + + + + % + + + + + + Meters + + + + + Alt + Alt + + + + VSpd + + + + + m/s + + + + + Fuel Qty + + + + + + km/h + + + + + Hdg + + + + + ASpd + + + + + + + G + + + + + GPS + + + + + Lat,Lon +(dec.deg.) + + + + + AccX + + + + + dd-MM-yyyy +hh:mm:ss + + + + + Date + + + + + Amps + + + + + AccZ + + + + + GAlt + + + + + + Volts + + + + + Cels + + + + + Curr + + + + + AccY + + + + + GSpd + + + + + Degrees + + + + + RPM - - FUEL - CARBURANTE - - - + When enabled, sends any non-blank values as simulated telemetry data. Quando abilitato invia i valori non nulli come dati telemetrici simulati. - - simulate - simula + + Log File + - - Instance - Istanza + + LOG Files (*.csv) + - - 2 - 9X {2?} + + ERROR - invalid file + + + + + Templates + + + Simple 4-CH + - - <html><head/><body><p>Start with <span style=" font-style:italic;">0x</span> for hex, <span style=" font-style:italic;">0</span> for octal, otherwise decimal.<br/>Numeric entry only. Blank values are not sent.</p></body></html> - <html><head/><body><p>Inserite i numeri iniziando con <span style=" font-style:italic;">0x</span> per hex, <span style=" font-style:italic;">0</span> per ottali, altrimenti decimali.<br/>Solo valori numerici. I valori non compilati non vengono inviati.</p></body></html> + + T-Cut + + + + + Sticky T-Cut + + + + + V-Tail + Coda a V + + + + Elevon\Delta + + + + + Heli Setup + + + + + Heli Setup with gyro gain control + + + + + Gyro gain control + + + + + Heli Setup (Futaba's channel assignment style) + + + + + Heli Setup with gyro gain control (Futaba's channel assignment style) + + + + + Gyro gain control (Futaba's channel assignment style) + + + + + Servo Test + + + + + MultiCopter + + + + + Use Model Config Wizard + + + + + Apply Template? + + + + + Apply template "%1"? + + + + + + + + + + + RUD + + + + + + + + + + + + + + ELE + + + + + + + THR + MOT + + + + + + + + + + + AIL + + + + + + + + AIL2 + + + + + + + + ELE2 + + + + + + + + + + FLAPS + + + + + + + + + + FLAP%1 + + + + + + + + PITCH + + + + + + + + + + + + GYRO + + + + + + SPOIL + + + + + + SPOIL%1 + + + + + + RUD2 + + + + + + Clear Mixes? + Cancellare le miscelazioni ? + + + + Really clear existing mixes on CH6? + + + + + Really clear existing mixes on CH5? + ThrottlePage - + Yes Si - + No No - + <br>Throttle Channel: <br>Canale Motore: @@ -9973,37 +11573,37 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà TimerPanel - + Silent Silenzioso - + Beeps Suoni - + Voice Voce - + Haptic Vibrazione - + Not persistent Non persistente - + Persistent (flight) Persistente (volo) - + Persistent (manual reset) Persistente (reset manuale) @@ -10134,33 +11734,94 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà TrainerSimulator - + Trainer simulator Simulatore allievo + + TreeModel + + + Index + + + + + Name + Nome + + + + Size + + + VTailPage - + First Tail Channel: Canale primo servo di coda: - + Second Tail Channel: Canale secondo servo di coda: + + VirtualJoystickWidget + + + Hld Y + + + + + Hold Vertical stick position. + + + + + Fix Y + Blocca Y + + + + Prevent Vertical movement of stick. + + + + + Fix X + Blocca X + + + + Prevent Horizontal movement of stick. + + + + + Hld X + + + + + Hold Horizontal stick position. + + + WingtypeSelectionPage - + Standard Wing Ali normali - + Flying Wing / Deltawing Tuttala / Ala a Delta @@ -10168,273 +11829,273 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà WizardDialog - + Model Wizard Assistente di configurazione - + Model Type Tipologia modello - + Enter model name and model type. Inserire nome e tipo di modello. - + Throttle Motore - + Has your model got a motor or an engine? Il modello ha un motore a scoppio o elettrico? - + Wing Type Tipo di ala - + Is your model a flying wing/deltawing or has it a standard wing configuration? Il modello è un tuttala / ala a delta o ha una configurazione standard? - + Ailerons Alettoni - + Has your model got ailerons? Il modello ha gli alettoni? - + Flaps Flap - + Has your model got flaps? Il modello ha i flap? - + Airbrakes Diruttori - + Has your model got airbrakes? Il modello ha i diruttori? - + Flying-wing / Delta-wing Tuttala / Ala a delta - + Select the elevons channels Selezionare in canali degli elevoni - + Rudder Direzionale - + Does your model have a rudder? Il modello ha un direzionale? - + Tail Type Tipo di coda - + Select which type of tail your model is equiped with. Selezionare quale tipo di coda ha il modello. - - + + Tail Coda - - + + Select channels for tail control. Selezionare i canali che controllano la coda. - + V-Tail Coda a V - + Select elevator channel. Selezionare il canale dell'elevatore. - + Cyclic Ciclico - + Which type of swash control is installed in your helicopter? Quale tipo di anello è installato sul vostro elicottero? - + Tail Gyro Giroscopio di coda - + Has your helicopter got an adjustable gyro for the tail? L' elicottero ha un giroscopio per la coda? - + Rotor Type Tipo di rotore - + Has your helicopter got a flybar? L'elicottero ha una Flybar ? - - + + Helicopter Elicottero - - + + Select the controls for your helicopter Selezionare i controlli per l'elicottero - + Multirotor Multirotore - + Select the control channels for your multirotor Selezionare i canali di controllo per il multirotore - + Model Options Opzioni del modello - + Select additional options Selezionarefunzionalità aggiuntive - + Save Changes Salva cambiamenti - + Manually check the direction of each control surface and reverse any channels that make controls move in the wrong direction. Remove the propeller/propellers before you try to control your model for the first time.<br>Please note that continuing removes all old model settings! Controllare manualmente la direzione di ogni superfice di controllo e invertire ogni canale che si sposta nella direzione errata. Rimuovere l'elica/eliche prima di controllare per la prima volta il modello.<br>Attenzione: continuando verranno rimosse tutte le impostazioni dei vecchi modelli! - + Enter a name for your model and select model type. Inserire il nome per il vostro modello e selezionare il tipo di modello. - + Select the receiver channel that is connected to your ESC or throttle servo.<br><br>Throttle - Spektrum: CH1, Futaba: CH3 Selezionare il canale della ricevente al quale è connesso l'ESC o il servo del gas.<br><br>Es. Spectrum: CH1, Futaba:.CH3 - + Most aircraft have a main wing and a tail with control surfaces. Flying wings and delta winged aircraft only have a single wing. The main control surface on a standard wing controls the roll of the aircraft. This surface is called an aileron.<br>The control surface of a delta wing controls both roll and pitch. This surface is called an elevon. Molti aeromobili hanno l'ala principale e la coda con superfici di controllo. I veivoli tuttala e le ali a delta ne hanno una sola. In un ala tradizionale le superfici di controllo principali provocano il rollio del veivolo e si chiamano Alettoni.<br>In un'ala a delta le superfici di controllo provocano contemporaneamente rollio e beccheggio e si chiamano Elevoni. - + Models use one or two channels to control the ailerons.<br>A so called Y-cable can be used to connect a single receiver channel to two separate aileron servos. If your servos are connected by a Y-cable you should select the single-servo option.<br><br>Aileron - Spektrum: CH2, Futaba: CH1 - + This wizard assumes that your flaps are controlled by a switch. If your flaps are controlled by a potentiometer you can change that manually later. Questo assistente configura l'azionamento dei flap tramite switch. Potete associare un potenziometro in seguito. - + Air brakes are used to reduce the speed of advanced sail planes.<br>They are very uncommon on other types of planes. I diruttori sono utilizzati per rdurre la velocità degli alianti.<br>Non sono molto comuni in altri tipi di modelli. - + Models use two channels to control the elevons.<br>Select these two channels I modelli usano due canali per il controllo degli elevoni.<br>Selezionare i canali appropriati - + Select the receiver channel that is connected to your rudder.<br><br>Rudder - Spektrum: CH4, Futaba: CH4 Selezionare il canale della ricevente al quale è connesso il direzionale.<br><br>Es. Spectrum: CH4, Futaba:.CH4 - + Select the tail type of your plane. Slezionare il tipo di coda dell'aereo. - + Select the Rudder and Elevator channels.<br><br>Rudder - Spektrum: CH4, Futaba: CH4<br>Elevator - Spektrum: CH3, Futaba: CH2 Selezionare il canale del direzionale e dell'elevatore.<br><br>Direzionale - Spectrum: CH4, Futaba:.CH4<br>Elevatore - Spektrum: CH3, Futaba: CH2 - + Select the Elevator channel.<br><br>Elevator - Spektrum: CH3, Futaba: CH2 Selezionare il canale della ricevente al quale è connesso l'elevatore.<br><br>Es. Spectrum: CH3, Futaba:.CH2 - - - - - - - + + + + + + + TBD. - + Select the control channels for your multirotor.<br><br>Throttle - Spektrum: CH1, Futaba: CH3<br>Yaw - Spektrum: CH4, Futaba: CH4<br>Pitch - Spektrum: CH3, Futaba: CH2<br>Roll - Spektrum: CH2, Futaba: CH1 Selezionare i canali per il vostro multirotore.<br><br>Motore - Spektrum: CH1, Futaba: CH3<br>Imbardata - Spektrum: CH4, Futaba: CH4<br>Beccheggio - Spektrum: CH3, Futaba: CH2<br>Rollio - Spektrum: CH2, Futaba: CH1 - + There is no help available for the current page. Nessun aiuto disponibile per questa pagina. - + Model Wizard Help Aiuto dell'assistente di configurazione @@ -10442,37 +12103,37 @@ Se l'opzione selezionata lo stick motore verrà rovesciato. Il minimo sarà WizardPrinter - + Plane Aereo - + Multicopter Multirotore - + Helicopter Elicottero - + Model Name: Nome Modello: - + Model Type: Tipo Modello: - + Options: Opzioni: - + Channel %1: Canale %1: @@ -10631,47 +12292,47 @@ utilizzatelo solo se sapete cosa state facendo. Non viene fatto alcun controllo Porta seriale per sam-ba - + DFU-UTIL Configuration DFU-UTIL Cconfiguration Configurazione DFU-UTIL - + SAM-BA Configuration SAM-BA Cconfiguration Configurazione SAM-BA - + AVRDUDE Configuration AVRDUDE Cconfiguration Configurazione AVRDUDE - - - + + + Select Location Seleziona eseguibile - + List available programmers Lista dei programmatori supportati - + Avrdude help Aiuto su AVRDUDE - + Companion Companion - + <b><u>WARNING!</u></b><br>Normally CPU type is automatically selected according to the chosen firmware.<br>If you change the CPU type the resulting eeprom could be inconsistent. <b><u>Attenzione!</u></b><br>Normalmente il processore viene selezionato automaticamente in base al firmware scelto.<br>Se cambiate il tipo di processore la EEPROM potrebbe risultare incoerente. @@ -10744,75 +12405,75 @@ m2560 per le schede v4.1 ... - - - - + + + + Error Errore - + Open Firmware File Apri file Firmware - + Can not load embedded image from firmware file %1. Impossibile caricare immagine dal file di Firmware %1. - + Open Image to load Apri l'immagine da caricare - + Images (%1) Immagini (%1) - + Cannot load the image file %1. Impossibile caricare il file immagine %1. - + Cannot load profile image %1. Impossibile caricarel'immagine dal profilo %1. - + Cannot load the library image %1. Impossibile caricare l'immagine di libreria %1. - + File Saved File salvato - + The image was saved to the file %1 L'immagine è stata salvata nel file %1 - + Image Refresh Error Errore aggiornamento immagine - + Failed to refresh image from file %1 Errore durante l'aggiornamento dell'immagine dal file %1 - + File Save Error Errore salvataggio file - + Failed to write image to %1 Errore di scittura dell'mmagine nel file %1 @@ -10825,17 +12486,17 @@ m2560 per le schede v4.1 Scaricamento in corso: - + Unable to save the file %1: %2. Impossibile salvare il file: %1: %2. - + Companion Companion - + Download failed: %1. Scaricamento fallito: %1. @@ -10848,232 +12509,155 @@ m2560 per le schede v4.1 Configurazione Joystick - + Ch2 Ch2 - - - - - - - - - Not Assigned - Non assegnato - - - - - - - - - - - Right Vertical - Verticale Destro - - - - - - - - - - - Right Horizontal - Orizzontale Destro - - - - - - - - - - - Left Vertical - Verticale Sinistro - - - - - - - - - - - Left Horizontal - Orizzontale Sinistro - - - - - - - - - - - P1 - P1 - - - - - - - - - - - P2 - P2 - - - - - - - - - - - P3/LS - P3/LS - - - - - - - - - - - RS - RS - - - + Ch1 Ch1 - + Ch4 Ch4 - + Ch6 Ch6 - + Ch3 Ch3 - + Ch5 Ch5 - + Ch7 Ch7 - + Ch8 Ch8 - + Instructions Istruzioni - + + Enable + Abilita + + + Cancel Annulla - + + Back + + + + + Start + Inizio + + + Next Successivo - + Ok Ok - - Move sticks and pots in every direction making full movement -Press next when finished - Muovere gli stick e i potenziometri in tutte le direzioni fino a fine corsa -Premere "Successivo" quando avete terminato + + Not Assigned + - - + + Stick + + + + + Knob/Slider %1 + + + + + No joysticks found + Nessun joystick trovato + + + Error Errore - + Cannot open joystick. Non riesco ad aprire il joystick. - - Place sticks and pots in middle position. -Press next when done - Posizionare gli stick e i potenziometri al centro. -Premere "Successivo" quando avete terminato - - - - Map joystick channels to controls using comboboxes. -Press next when done - Identificare i canali con gli stick usando gli elenchi a discesa. -Premere "Successivo" quando avete terminato - - - - Check inversion checkbox to get maximum at top-right position. -Press next when done - Controllare l'inversione dei canali, i canali devono essere -al massimo quando lo stick è in alto a destra. -Premere "Successivo" quando avete terminato - - - - Press ok to save configuration -Press cancel to abort joystick calibration - Premere ok per salvare la configurazione -Premere annulla per cancellare l'operazione - - - - Duplicated stick assignment + + Press the Start button to start the stick range calibration procedure. +You may change the channel assignments or inversion at any time. - - - mdiChild - - Simulate Tx - Simula TX + + Move sticks and pots in every direction making full movement +Press Next when finished + + + + + Place sticks and pots in middle position. +Press Next when done + + + + + Map joystick channels to controls using comboboxes. +Press Next when done. + + + + + Check inversion checkbox to if necessary to reverse direction. +Press Next when done. + + + + + Press OK to save configuration +Press Cancel to abort joystick calibration without saving. + + + + + Warning + Avviso + + + + Calibration not complete, save anyway? + diff --git a/companion/src/translations/companion_pl.ts b/companion/src/translations/companion_pl.ts index e6a09149d..29dcfcba5 100644 --- a/companion/src/translations/companion_pl.ts +++ b/companion/src/translations/companion_pl.ts @@ -1,30 +1,30 @@ - + AileronsPage - + No Nie - + Yes, controlled by a single channel Tak, kontrolowane przez 1 kanał - + Yes, controlled by two channels Tak, kontrolowane przez 2 kanały - + <br>First Aileron Channel: <br> Pierwszy kanał lotek: - + Second Aileron Channel: Drugi kanał lotek: @@ -32,27 +32,27 @@ AirbrakesPage - + No Nie - + Yes, controlled by a single channel Tak, kontrolowane przez 1 kanał - + Yes, controlled by two channels Tak, kontrolowane przez 2 kanały - + <br>First Airbrake Channel: <br> Pierwszy kanał hamulców: - + Second Airbrake Channel: Drugi kanał hamulców: @@ -69,15 +69,6 @@ Radio Profile Profil radia - - - - - - - Open Folder - Otwórz katalog - Default Channel Order @@ -297,6 +288,20 @@ Mode 4: A T E R L G W K + + + + + + + Select Folder + + + + + Select Executable + + Use OpenTX firmware nightly builds @@ -405,11 +410,6 @@ Może być różny od języka firmware Files to keep Pliki do zapamiętania - - - Find Executable - Wskaż plik wykonywalny - Google Earth Executable @@ -506,498 +506,149 @@ Może być różny od języka firmware Zapamiętaj ustawienia przełączników w symulatorze - + My Radio Moje Radio - + Select your snapshot folder Katalog zrzutów - - + + No joysticks found Brak joysticka - + EMPTY: No radio settings stored in profile PUSTY:Brak ustawień radia w profilu - + AVAILABLE: Radio settings of unknown age DOSTĘPNY:Nieznany wiek ustawień radia - + AVAILABLE: Radio settings stored %1 DOSTĘPNY:Zapamiętane ustawienia radia %1 - + Select your library folder Wybierz katalog biblioteki - - + + Select your Models and Settings backup folder Wybierz folder do backupowania Modeli i Ustawień - + Select Google Earth executable Wybierz wykonywalny plik Google Earth - + Select the folder replicating your SD structure Wybierz folder do zreplikowania struktury Twojej karty SD - + Not possible to remove profile Usunięcie profilu jest niemożliwe - + The default profile can not be removed. Podstawowy profil nie może być usunięty. - + Open Image to load Otwórz obrazek do załadowania - + Images (%1) Obrazki (%1) - - Calibration - - - Form - Formularz - - - - RS - Prawy Suwak - - - - SB - SB - - - - Rud - SK - - - - Pot. 4 - Potencj. 4 - - - - Pot. 3 - Potencj. 3 - - - - Pot. 2 - Potencj. 2 - - - - Pot. 1 - Potencj. 1 - - - - PPM 1 - PPM 1 - - - - Stick 3 - Drążek 3 - - - - - Negative span - Ujemny zakres - - - - - Mid value - Wartość środkowa - - - - SQ - SQ - - - - SR - SR - - - - LS2 - LS2 - - - - SP - SP - - - - SO - SO - - - - S4 - S4 - - - - - Positive span - Dodatni zakres - - - - Stick 1 - Drążek 1 - - - - Stick 2 - Drążek 2 - - - - Stick 4 - Drążek 4 - - - - v - V - - - - PPM Multiplier - Mnożnik PPM - - - - Current Offset - Aktuany ofset - - - - S1 - Potencjometr 1 - - - - S2 - Potencjometr 2 - - - - S3 - Potencjometr 3 - - - - SA - SA - - - - Ele - SW - - - - Ail - Lotki - - - - Thr - Gaz - - - - SC - SC - - - - LS - Lewy Suwak - - - - SD - SD - - - - SE - SE - - - - SF - SF - - - - SG - SG - - - - SH - SH - - - - SI - SI - - - - SJ - SJ - - - - SK - SK - - - - SL - SL - - - - SM - SM - - - - SN - SN - - - - RS2 - RS2 - - - - Bluetooth - Bluetooth - - - - PPM 2 - PPM 2 - - - - Battery Offset - Ofset baterii - - - - PPM 3 - PPM 3 - - - - PPM 4 - PPM 4 - - - - - - - - - - - - - Beeper volume - -0 - Quiet. No beeps at all. -1 - No Keys. Normal beeps but menu keys do not beep. -2 - Normal. -3 - Loud. -4 - Extra loud. - Głośność piknięć - -0 -Cicho. Żadnych piknięć. -1 - Bez przycisków. Normalne piknięcia ale bez pikania dla przycisków menu. -2 - Normalna. -3 - Głośna. -4 - Bardzo głośna. - - - - OFF - Wyłącz - - - - S-Port Mirror - Kopia S-Port - - - - Telemetry - Telemetria - - - - SBUS Trainer - Trener SBUS - - - - Debug - Debugowanie - - - - Serial Port - Port szeregowy - - - - CalibrationPanel - - - - - None - Brak - - - - 2 Positions Toggle - 2 Poz. Przełącznik chwilowy - - - - 2 Positions - 2 Pozycje - - - - 3 Positions - 3 Pozycje - - - - Pot with detent - Potencj. z zapadką - - - - Multipos switch - Przeł. wielopoz - - - - Pot without detent - Potencjometr bez zapadki - - - - Slider with detent - Suwak z zapadką - - Channels - + Name Nazwa - + Min Min - + Max Maks - + Curve Krzywa - + + CH%1 + Kan %1 + + + Subtrim Subtrim - + Direction Kierunek - + PPM Center Środek PPM - + Linear Subtrim Liniowy Subtrim - - Channel %1 - Kanał %1 - - - + --- --- - + INV Odwr + + CompanionMacros + + + files + + + + + Radio and Models settings + + + CompareDialog @@ -1031,17 +682,17 @@ Może być różny od języka firmware Drukuj do pliku - + No name Model bez nazwy - + Print Document Drukuj dokument - + Select PDF output file Wybierz plik docelowy PDF @@ -1049,7 +700,7 @@ Może być różny od języka firmware ConclusionPage - + OK, I understand. OK, Rozumiem. @@ -1057,42 +708,42 @@ Może być różny od języka firmware ContributorsDialog - + OpenTX Contributors Współpracownicy OpenTX - + Main Developers Główni Developerzy - + Other contributors Inni współpracownicy - + Companies and projects who have donated to OpenTX Firmy i projekty, które wsparły OpenTX - + People who have donated to OpenTX Ludzie, którzy wsparli OpenTX - + Honors go to Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) Specjalne podziękowania Rafałowi Tomczakowi (RadioClone), Thomasowi Husteterowi (th9x) a także Erazowi Ravivowi(er9x i eePe) - + OpenTX Blacklist Indeks (zakaz) OpenTX - + monthly miesięcznie @@ -1100,24 +751,24 @@ Może być różny od języka firmware CopyProcess - - - + + + Error Błąd - + Write error Błąd Zapisu - + Cannot write %1 (reason: %2) Nie mogę zapisać %1 (powód %2) - + Cannot open %1 (reason: %2) Nie mogę otworzyć %1 (powód %2) @@ -1125,22 +776,22 @@ Może być różny od języka firmware CurveGroup - + Diff Różnicowość - + Expo Expo - + Func Funkcja - + Curve Krzywa @@ -1229,72 +880,72 @@ Może być różny od języka firmware Nazwa krzywej - + Curve %1 Krzywa %1 - + %1 points %1 punktowa - + Linear Liniowa - + Single Expo Pojedyncze expo (wykładnicza) - + Symmetrical f(x)=-f(-x) Symetryczna (nieparzysta) f(x)=-f(-x) - + Symmetrical f(x)=f(-x) Symetryczna (parzysta) f(x)=f(-x) - + Copy Skopiuj - + Paste Wklej - + Clear Wyczyść - + Clear all curves Wyczyść wszystkie krzywe - + Are you sure you want to reset curve %1? Czy na pewno chcesz wyczyścić krzywą %1? - + Are you sure you want to reset all curves? Czy na pewno chcesz wyczyścić krzywe? - + Editing curve %1 Edycja krzywej k%1 - + Not enough free points in EEPROM to store the curve. Za mało wolnych punktów w eepromie by zapamiętać krzywą. @@ -1302,87 +953,87 @@ Może być różny od języka firmware CustomFunctionsPanel - + Switch Przełącznik - + Action Akcja - + Parameters Parametry - + Enable Włączone - + SF%1 SF%1 - + GF%1 FG%1 - + ON Włącz - + Error Błąd - + Unable to find sound file %1! Nie mogę odnaleźć pliku dźwiękowego %1! - + &Delete &Wykasuj - + Delete Wykasuj - + &Copy &Kopiuj - + Ctrl+C Ctrl+C - + &Cut W&ytnij - + Ctrl+X Ctrl+X - + &Paste W&klej - + Ctrl+V Ctrl+V @@ -1390,22 +1041,22 @@ Może być różny od języka firmware CyclicPage - + 90 90 - + 120 120 - + 120x 120x - + 140 140 @@ -1413,100 +1064,176 @@ Może być różny od języka firmware DebugOutput - + Debug Output Wyjście debugera + + + <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> + + + + + Filter: + + + + + <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> +To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> + + + + + Buffer: + + + + + Number of lines to keep in display. + + + + + Filter &Help + + + + + Show information about using the filter. + + + + + Word &Wrap + + + + + Toggle word wrapping on/off. + + + + + &Clear + + + + + Clear the output window of all text. + + + + + Enable &Filter + + + + + Turn the filter on/off. + + + + + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> + + + + + Debug Console Filter Help + + EepromInterface - + Possible causes for this: Możliwe przyczyny tego: - + - Eeprom is from a newer version of OpenTX - Eeprom jest z nowszej wersji OpenTX - + - Eeprom is not from OpenTX - Eeprom nie jest z OpenTX - + - Eeprom is not from Th9X - Eeprom nie jest z Th9X - + - Eeprom is not from Gruvin9X - Eeprom nie jest z Gruvin9X - + - Eeprom is not from ErSky9X - Eeprom nie jest z ErSky9X - + - Eeprom is not from Er9X - Eeprom nie jest z Er9X - + - Eeprom size is invalid - Nieprawidłowa wielkość Eeproma - + - Eeprom file system is invalid - Błedny system plików Eeproma - + - Eeprom is from a unknown board - Eeprom z nieznanej płyty - + - Eeprom is from the wrong board - Eeprom ze złej płyty - + - Eeprom backup not supported - Backup Eepromu nieobsługiwany - + - Something that couldn't be guessed, sorry - Coś czego nie można odgadnąć, przepraszam - + Warning: Ostrzeżenie: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - Twoje radio prawdopodobnie używa złego firmware, wielkość eepromu to 4096 ale tylko pierwsze 2048 jest użyte - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - Twój eeprom jest ze starej wersji OpenTX, Zupgraduj! Powinieneś 'zapisać jako' stary plik jako kopię zapasową. - + Warnings! Ostrzeżenia! @@ -1514,233 +1241,16 @@ Powinieneś 'zapisać jako' stary plik jako kopię zapasową. ElevonsPage - + <br>First Elevon Channel: <br> Pierwszy Kanał Sterolotek: - + Second Elevon Channel: Drugi Kanał Sterolotek: - - Er9x::Templates - - - Simple 4-CH - Proste 4 kanały - - - - T-Cut - Wył Gazu - - - - Sticky T-Cut - Stały wyłącznik Gazu - - - - V-Tail - Motylkowy - - - - Elevon\Delta - Elevon/Delta - - - - Heli Setup - Ustawienie Heli - - - - Heli Setup with gyro gain control - Ustawienie heli ze stabilizacją Żyro - - - - Gyro gain control - Stabilizacja Żyro - - - - Heli Setup (Futaba's channel assignment style) - Ustawienie heli (Ustawienie kanałów w stylu Futaby) - - - - Heli Setup with gyro gain control (Futaba's channel assignment style) - Ustawienie heli ze stabilizacją Żyro(Ustawienie kanałów w stylu Futaby) - - - - Gyro gain control (Futaba's channel assignment style) - Stabilizacja Żyro(Ustawienie kanałów w stylu Futaby) - - - - Servo Test - Test Serwa - - - - MultiCopter - Wielowirnikowiec - - - - Use Model Config Wizard - Użyj konfiguratora modelu - - - - Apply Template? - Dodać szablon ? - - - - Apply template "%1"? - Dodać szablon "%1"? - - - - - - - - - - RUD - SK - - - - - - - - - - - - - ELE - SW - - - - - - THR - Gaz - - - - - - - - - - - AIL - Lotki - - - - - - - AIL2 - Lotka2 - - - - - - - ELE2 - SW2 - - - - - - - - - FLAPS - Klapy - - - - - - - - - FLAP%1 - Klapy %1 - - - - - - - PITCH - Pochylenie - - - - - - - - - - - GYRO - ŻYRO - - - - - SPOIL - Spoiler - - - - - SPOIL%1 - Spoiler%1 - - - - - RUD2 - SK2 - - - - - Clear Mixes? - Wyczyść miksery? - - - - Really clear existing mixes on CH6? - Na pewno wyczyścić mikser na kanale 6? - - - - Really clear existing mixes on CH5? - Na pewno wyczyścić mikser na kanale 5? - - ExpoDialog @@ -1853,30 +1363,50 @@ Jeśli puste linia jest uznawana za aktywną cały czas. Krzywa załączona do źródła. - + Edit %1 Edycja %1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + FblPage - + Throttle Channel: Kanał gazu: - + Yaw Channel: Kanał odchylenia: - + Pitch Channel: Kanał pochylenia: - + Roll Channel: Kanał przechylenia: @@ -1929,27 +1459,27 @@ Może być różny od języka firmware FlapsPage - + No Nie - + Yes, controlled by a single channel Tak, kontrolowane przez 1 kanał - + Yes, controlled by two channels Tak, kontrolowane przez 2 kanały - + <br>First Flap Channel: <br> Pierwszy kanał klap: - + Second Flap Channel: Drugi kanał Klap: @@ -1958,7 +1488,7 @@ Może być różny od języka firmware FlashEEpromDialog - + Write Models and Settings to Radio Zapisz Modele i Ustawienia do radia @@ -1974,7 +1504,6 @@ Może być różny od języka firmware - Allows Companion to write to older version of the firmware Pozwól Companion na zapis do starszej wersji firmware @@ -1983,6 +1512,11 @@ Może być różny od języka firmware Check Firmware compatibility Sprawdź kompatybilność firmware + + + <html><head/><body><p>Saves a dated copy of your eeprom to the backup folder you specified in the Companion settings before writing the current model to the radio.</p></body></html> + + Backup before Write @@ -2019,107 +1553,66 @@ Może być różny od języka firmware Zapisz do radia - + Current profile: %1 Aktualny profil %1 - + Choose Radio Backup file Wybierz plik Backupu radia - - - - - - - - - - + + Error Błąd - - - Unable to find file %1! - Nie mogę odnaleźć pliku %1! - - - - - - Error opening file %1: -%2. - Błąd otwarcia pliku %1: -%2. - - - - - Invalid Models and Settings File %1 - Błędny plik %1 Modeli i Ustawień - - - - Error reading file %1: -%2. - Błąd odczytu pliku %1: -%2. - - Invalid Models and Settings file %1 - Błędny plik %1 Modeli i Ustawień - - - - - - + + + Warning Ostrzeżenie - + Wrong radio calibration data in profile, Settings not patched Błędna kalibracja radia w profilu, Ustawienia nie spatchowane - + Wrong radio setting data in profile, Settings not patched Błędne ustawienia radia w profilu, Ustawienia nie spatchowane - - + Cannot write file %1: %2. Nie mogę zapisać pliku %1: %2. - + Error writing file %1: %2. Błąd zapisu pliku %1: %2. - + The radio firmware belongs to another product family, check file and preferences! Firmware radia należy do innej rodziny produktów, sprawdź plik i preferencje ! - + The radio firmware is outdated, please upgrade! Firmware w radiu jest przestarzały. Proszę zaktualizować! - + Cannot check Models and Settings compatibility! Continue anyway? Nie mogę potwierdzić kompatybilności Modeli i Ustawień. Kontynuować? @@ -2197,119 +1690,119 @@ Może być różny od języka firmware Zapisz do radia - + Open Firmware File Otwórz plik Firmware - - - + + + Warning Ostrzeżenie - + %1 may not be a valid firmware file %1 może nie być prawidłowym plikiem firmware - - - - + + + + Error Błąd - + The firmware file is not valid. Plik firmware jest błędny. - + There is no start screen image in the firmware file. Brak obrazka ekranu startowego w firmware. - + Profile image %1 is invalid. Obraz profilu %1 nieprawidłowy. - + Open image file to use as radio start screen Otwórz plik obrazka by użyć go jako ekran startowy radia - + Images (%1) Obrazki (%1) - + Image could not be loaded from %1 Obrazek nie może być załadowany z %1 - + The library image could not be loaded Obrazek z biblioteki nie może być załadowany - + Splash image not found Obrazek startowy nie znaleziony - + Cannot save customized firmware Nie mogę zapisać przystosowanego firmware - + Write Firmware to Radio Zapisz firmware do radia - - + + Firmware check failed Sprawdzenie firmawe nieudane - + Could not check firmware from radio Nie mogę sprawdzić firmware w radiu - + New firmware is not compatible with the one currently installed! Nowe firmware niekompatybilne z aktualnie zainstalowanym! - + Conversion failed Konwersja nieudana - + Cannot convert Models and Settings for use with this firmware, original data will be used Nie mogę skonwertować Modeli i Ustawień na ten rodzaj firmware, zostaną użyte oryginalne dane - + Restore failed Zapis nieudany - + Could not restore Models and Settings to Radio. The models and settings data file can be found at: %1 Nie mogę odtworzyć Modeli i Ustawień do radia. Plik modeli i ustawień można znaleźć w: %1 - + Flashing done Sflashowanie zakończone @@ -2317,47 +1810,47 @@ Może być różny od języka firmware FlashProcess - + Executable %1 not found Plik wykonywany %1 nie znaleziony - + Writing... Zapis... - + Reading... Czytanie... - + Verifying... Weryfikacja... - + unknown nieznany - + ie: OpenTX for 9X board or OpenTX for 9XR board ie: OpenTX dal platformy 9X lub OpenTX lub 9XR - + ie: OpenTX for M128 / 9X board or OpenTX for 9XR board with M128 chip ie: OpenTX dla platformy M128 / 9X lub OpenTX dla platformy 9XR z chipem M128 - + ie: OpenTX for Gruvin9X board ie: OpenTX dla platformy Gruvin9X - + Your radio uses a %1 CPU!!! Please check advanced burn options to set the correct cpu type. @@ -2366,7 +1859,7 @@ Please check advanced burn options to set the correct cpu type. Sprawdź zaawansowane opcje aby ustalić prawidłowy procesor. - + Your radio uses a %1 CPU!!! Please select an appropriate firmware type to program it. @@ -2375,7 +1868,7 @@ Please select an appropriate firmware type to program it. Proszę wybrać poprany rodzaj firmware. - + You are currently using: %1 @@ -2384,7 +1877,7 @@ Aktualnie używasz: %1 - + Your radio does not seem connected to USB or the driver is not installed!!! Please use ZADIG to properly install the driver. @@ -2393,22 +1886,22 @@ Please use ZADIG to properly install the driver. W celu instalacji drivera użyj ZADIG. - + Your radio does not seem connected to USB or the driver is not initialized!!!. Radio nie jest podłączone do USB lub driver nie został zainicjalizowany!!!. - + Flashing done (exit code = %1) Flaszowanie zakończone( z kodem %1) - + Flashing done with errors Flashowanie zakończone z Błędami - + FUSES: Low=%1 High=%2 Ext=%3 Bezpieczniki: Low=%1 High=%2 Ext=%3 @@ -2439,35 +1932,65 @@ W celu instalacji drivera użyj ZADIG. FlightModePanel - + Rotary Encoder %1 Pokrętło %1 - + + Name + Nazwa + + + + Value source + + + + + Value + Wartość + + + GVAR%1 ZmGl%1 - + Popup enabled Wyskakujące okna aktywne + + + &Clear + + + + + Clear + Wyczyść + + + + Clear all current Flight Mode properties? + + FlightModesPanel - + Flight Mode %1 Faza lotu %1 - + (%1) (%1) - + (default) (bazowa) @@ -2475,17 +1998,17 @@ W celu instalacji drivera użyj ZADIG. FlybarSelectionPage - + Has Flybar Posiada flaybar - + Flybarless Bez flybara - + Flybar: Flaybar: @@ -2631,24 +2154,19 @@ p, li { white-space: pre-wrap; } <p align="center" style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Rób to tylko wtedy gdy masz absolutną pewność i wiedzę.</p></body></html> - - + + Reset Radio Fuses Zresetuj bezpieczniki radia - + Read Fuses from Radio Odczytaj bezpieczniki radia GeneralEdit - - - General Edit - Główne ustawienia - Store calib. and hw settings in selected profile @@ -2659,6 +2177,11 @@ p, li { white-space: pre-wrap; } Retrieve calib. and hw settings from profile Odtworzenie kalibracji i ustawień HW z profilu + + + Radio settings + + General settings used throught the transmitter. @@ -2667,48 +2190,59 @@ These will be relevant for all models in the same EEPROM. Będą one obowiązywać dla wszystkich modeli w tym samym EEPROM-ie. - + Setup Ustawienia - + Trainer Trener - + Global Functions Funkcje Globalne - - Hardware / Calibration - Kalibracja sprzętu + + Hardware + - - + + Calibration + + + + + + Warning Ostrzeżenie - + Wrong data in profile, radio calibration was not retrieved Błędne dane w profilu, kalibracja nie została odzyskana - + + Wrong data in profile, Switch/pot config not retrieved + + + + Wrong data in profile, hw related parameters were not retrieved Błędne dane w profilu, parametry HW nie zostały odzyskana - + Do you want to store calibration in %1 profile<br>overwriting existing calibration? Chcesz zapamiętać dane kalibracji profilu %1<br> Zastąpią one aktualne dane kalibracji? - + Calibration and HW parameters saved. Kalibracja i parametry HW zapamiętane. @@ -2721,137 +2255,137 @@ Będą one obowiązywać dla wszystkich modeli w tym samym EEPROM-ie.Formularz - + GPS Coordinates Koordynaty GPS - + Speaker Pitch (spkr only) Wysokość tonów (tylko dźwięki) - + Measurement Units Jednostki miar - - + + hh° (N/S) mm' ss''.dd hh° (N/S) mm' ss''.dd - + NMEA NMEA - + Voice Language Język komunikatów - + Timeshift from UTC Strefa czasowa względem UTC - + Metric Metryczne - + Imperial Imperialne - + Country Code Kod kraju - + America Ameryka - + Japan Japonia - + Europe Europa - - + + X-Short Bardzo krótka - - + + Short Krótka - - + + Normal Normalna - - + + Long Długa - - + + X-Long Bardzo długa - + Color 1 Kolor 1 - + Color 2 Kolor 2 - + Beeper Length Długość piknięcia - + RotEnc Navigation Nawigacja pokrętłem - + Beeper Mode Tryb pikania - + Vario pitch at zero Ton Wario dla zera - + Standard Standard - + Optrex Optrex @@ -2861,12 +2395,12 @@ Będą one obowiązywać dla wszystkich modeli w tym samym EEPROM-ie.Odblokuj "Tylko do odczytu" - + Sound Mode Tryb dźwiękowy - + Beeper volume 0 - Quiet. No beeps at all. @@ -2883,61 +2417,61 @@ Będą one obowiązywać dla wszystkich modeli w tym samym EEPROM-ie. - - + + Quiet Cichy - + Alarms Only Tylko alarmy - - + + No Keys Bez przycisków - - + + All Wszystkie - + Only Alarms Tylko Alarmy - + Haptic Mode Tryb wibracji - + Beeper Pikanie - + Speaker Głośnik - + BeeperVoice Pikanie i głosy - + SpeakerVoice Głośnik i głosy - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2992,18 +2526,18 @@ p, li { white-space: pre-wrap; } SG - - + + Hz Hz - + Battery Warning Ostrzeżenie o zasilaniu - + Battery warning voltage. This is the threashhold where the battery warning sounds. @@ -3014,152 +2548,152 @@ Ustala próg ostrzeżenia. Dopuszczalne wartości 5v-10v - + Vario pitch at max Ton Wario dla Maks - + If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. Jeśli ta wartość jest różna od 0, każde naciśnięcie klawisza włączy podświetlenie, które zgaśnie po ustalonej liczbie sekund. - + sec s - - + + ms ms - + Backlight Brightness Jasność Podświetlenia - + Vario repeat at zero Powtarzanie dla Wario zero - + Backlight Auto OFF after Wyłącz podświetlenie po - + Backlight color Kolor Podświetlenia - + Min Min - - + + v V - + Max Maks - + Contrast Kontrast - + Battery Meter Range Zakres Pomiaru Baterii - + If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. Radio zasygnalizuje dźwiękiem brak aktywności po określonej liczbie minut. 0- wyłącza tę funkcję. - + min Min - + 4800 Baud 4800 bps - + 9600 Baud 9600 bps - + 14400 Baud 14400 bps - + 19200 Baud 19200 bps - + 38400 Baud 38400 bps - + 57600 Baud 57600 bps - + 76800 Baud 76800 bps - + 115200 Baud 115200 bps - + Backlight Switch Przełącznik Podświetlenia - + Show Splash Screen on Startup Pokazuj ekran startowy z logo - + This is the switch selectrion for turning on the backlight (if installed). To jest przełącznik do włączenia podświetlenia (jeśli zainstalowane). - + LCD Display Type Typ ekranu LCD - + Adjust RTC Dostosuj Zegar - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -3184,123 +2718,133 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Ostrzeżenie cichej pracy - będzie ostrzegało gdy pikanie jest ustawione na cicho(0)</p></body></html> - + MAVLink Baud Rate Prędkość przesyłu MAVLink - + Speaker Volume Głośność dźwięków - + Haptic Length Długość wibracji - + Inactivity Timer Timer bezczynności - - + + Show splash screen on startup Pokazuj ekran startowy z logo - + --- --- - + 2s 2s - + 3s 3s - + 4s 4s - + 6s 6s - + 8s 8s - + 10s 10s - + 15s 15s - + "No Sound" Warning Ostrzeżenie "Brak Dźwięku" - + Low Memory Warning Ostrzeżenie niski stan Pamięci - + Haptic Strength Siła wibracji - + Beep volume Głośność sygnałów - + Wav volume Głośność WAV - + Vario volume Głośność wariometru - + Background volume Głośność tła - + Stick Mode Mod drążków - + Default Channel Order Bazowa kolejność kanałów - + FAI Mode Tryb FAI - + + Automatically adjust the radio's clock if a GPS is connected to telemetry. + + + + + Backlight OFF Brightness + + + + Mode selection: Mode 1: @@ -3341,168 +2885,167 @@ Mode 4: - + Mode 1 (RUD ELE THR AIL) Mod 1 (SK.SW.Gaz.Lot) - + Mode 2 (RUD THR ELE AIL) Mod 2 (SK.Gaz.SW.Lot) - + Mode 3 (AIL ELE THR RUD) - + Mode 4 (AIL THR ELE RUD) Mod 4 (Lot.Gaz.SW.SK) - + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> <html><head/><body><p>Kolejność kanałów</p><p><br/></p><p>Definiuje kolejność standardowych mikserów dla nowego modelu.</p></body></html> - + R E T A K W G L - + R E A T K W L G - + R T E A K G W L - + R T A E K G L W - + R A E T K L W G - + R A T E K L G W - + E R T A W K G L - + E R A T W K L G - + E T R A W G K L - + E T A R W G L K - + E A R T W L K G - + E A T R W L G K - + T R E A G K W L - + T R A E G K L W - + T E R A G W K L - + T E A R G W L K - + T A R E G L K W - + T A E R G L W K - + A R E T L K W G - + A R T E L R G W - + A E R T L W K G - + A E T R L W G K - + A T R E L G K W - + A T E R L G W K - + Stick reverse Rewers drążków - - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Jeśli uaktywnisz tryb FAI, utracisz informacje o wariometrze, funkcje odtwarzania i ekrany telemetrii. Ten tryb nie może być dezaktywowany. - + Play Delay (switch mid position) Opóźnienie odtwarzania (pozycja środkowa przełącznika) - + Backlight flash on alarm Błyskanie podświetleniem przy alarmie @@ -3510,7 +3053,7 @@ Mode 4: GeneralSetupPanel - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Are you sure ? @@ -3522,21 +3065,330 @@ Jesteś pewien ? GyroPage - + No Nie - + Yes, controled by a switch Tak, kontrolowane przez przełącznik - + Yes, controlled by a pot Tak, kontrolowane przez potencjometr + + Hardware + + + Form + Formularz + + + + SQ + SQ + + + + SR + SR + + + + LS2 + LS2 + + + + SP + SP + + + + SO + SO + + + + S4 + S4 + + + + RS + + + + + SB + SB + + + + PPM 2 + PPM 2 + + + + + + + + + + + + + Beeper volume + +0 - Quiet. No beeps at all. +1 - No Keys. Normal beeps but menu keys do not beep. +2 - Normal. +3 - Loud. +4 - Extra loud. + Głośność piknięć + +0 -Cicho. Żadnych piknięć. +1 - Bez przycisków. Normalne piknięcia ale bez pikania dla przycisków menu. +2 - Normalna. +3 - Głośna. +4 - Bardzo głośna. + + + + OFF + Wyłącz + + + + S-Port Mirror + Kopia S-Port + + + + Telemetry + Telemetria + + + + SBUS Trainer + Trener SBUS + + + + Debug + Debugowanie + + + + Rud + SK + + + + PPM 3 + PPM 3 + + + + S1 + Potencjometr 1 + + + + S2 + Potencjometr 2 + + + + S3 + S3 + + + + PPM 1 + PPM 1 + + + + Serial Port + Port szeregowy + + + + v + V + + + + PPM Multiplier + Mnożnik PPM + + + + Current Offset + Aktuany ofset + + + + PPM 4 + PPM 4 + + + + SA + SA + + + + Ele + SW + + + + Ail + Lotki + + + + Thr + Gaz + + + + SC + SC + + + + LS + + + + + SD + SD + + + + Battery Offset + Ofset baterii + + + + SE + SE + + + + SF + SF + + + + SG + SG + + + + SH + SH + + + + SI + SI + + + + SJ + SJ + + + + SK + SK + + + + SL + SL + + + + SM + SM + + + + SN + SN + + + + RS2 + RS2 + + + + Bluetooth + Bluetooth + + + + ADC Filter + + + + + HardwarePanel + + + + + None + + + + + 2 Positions Toggle + 2 Poz. Przełącznik chwilowy + + + + 2 Positions + 2 Pozycje + + + + 3 Positions + 3 Pozycje + + + + Pot with detent + Potencj. z zapadką + + + + Multipos switch + Przeł. wielopoz + + + + Pot without detent + Potencjometr bez zapadki + + + + Slider with detent + Suwak z zapadką + + Heli @@ -3613,22 +3465,22 @@ Jesteś pewien ? HeliPage - + Throttle Channel: Kanał gazu: - + Yaw Channel: Kanał odchylenia: - + Pitch Channel: Kanał pochylenia: - + Roll Channel: Kanał przechylenia: @@ -3636,121 +3488,121 @@ Jesteś pewien ? InputsPanel - - + + Move Up W górę - - + + Ctrl+Up Ctrl+Up - - + + Move Down W dół - - + + Ctrl+Down Ctrl+Down - + Clear All Inputs Wyczyść wszystkie wejścia - + Not enough available inputs! Za mało dostępnych wejść! - + Delete Selected Inputs? Skasować Wybrane Wejścia? - + &Add &Dodaj - + Ctrl+A Ctrl+A - + &Edit &Edycja - + Enter Enter - + &Delete &Wykasuj - + Delete Wykasuj - + &Copy &Kopiuj - + Ctrl+C Ctrl+C - + &Cut W&ytnij - + Ctrl+X Ctrl+X - + &Paste W&klej - + Ctrl+V Ctrl+V - + Du&plicate &Zduplikuj - + Ctrl+U Ctrl+U - + Clear Inputs? Wyczyść Wejścia? - + Really clear all the inputs? Czy na pewno wyczyścić wszystkie wejścia? @@ -3758,88 +3610,89 @@ Jesteś pewien ? LogicalSwitchesPanel - + V1 Wartość 1 - + V2 Wartość 2 - + Function Funkcja - + AND Switch Przełącznik "I" - + Duration Czas trwania - + Delay Opóźnienie - + L%1 L%1 - + + (infinite) (nieskończony) - + &Delete &Wykasuj - + Delete Wykasuj - + &Copy &Kopiuj - - + + (instant) (natychmistowy) - + Ctrl+C Ctrl+C - + &Cut W&ytnij - + Ctrl+X Ctrl+X - + &Paste W&klej - + Ctrl+V Ctrl+V @@ -3852,87 +3705,87 @@ Jesteś pewien ? Companion przegląd logów - + Filename Nazwa pliku - + Open LogFile Otwórz plik logów - + Zoom Przybliżenie - + X X - + Y Y - + Reset Reset - + Fly sessions Sesja lotów - + Telemetry logs Logi Telemetrii - + Time (hh:mm:ss) Czas (hh:mm:ss) - + Plot Title Change Zmiana tytułu pilota - + New plot title: Nowy tytuł pilota: - + Axis Label Change Zmiana oznaczenia osi - + New axis label: Nowe oznaczenie osi: - + Graph Name Change Zmiana nazwy wykresu - + New graph name: Nowa nazwa wykresu: - + Error: no GPS data not found Błąd: Brak danych GPS - + The column containing GPS coordinates must be named "GPS". The columns for altitude "GAlt" and for speed "GSpd" are optional @@ -3941,59 +3794,79 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt Kolumny wysokości "GAlt" i prędkości "GSpd" są opcjonalne - + Error Błąd - + Cannot write file %1: %2. Nie mogę zapisać pliku %1: %2. - + + Cursor A: %1 m + + + + + Cursor B: %1 m + + + + + Time delta: %1 + + + + + Climb rate: %1 m/s + + + + Select your log file Wybierz plik logów - + Available fields Dostępne pola - + The selected logfile contains %1 invalid lines out of %2 total lines Wybrany plik zawiera %1 błędnych linii z %2 wszystkich linii - + total duration Całkowity czas trwania - + duration Czas trwania - + (L1) (L1) - + (R1) (R1) - + (L2) (L2) - + (R2) (R2) @@ -4001,621 +3874,553 @@ Kolumny wysokości "GAlt" i prędkości "GSpd" są opcjonaln MainWindow - - - - + + File loaded Plik załadowany - + Display previous warning again at startup ? Wyświetlić poprzednie ostrzeżenie przy uruchomieniu? - + Checking for updates Sprawdź aktualizacje - + Unable to check for updates. Nie mogę sprawdzić aktualizacji. - - + + Save As Zapisz jako - + Executable (*.exe) Wykonywalny (*.exe) - + New release available Dostępne jest nowe wydanie - - + + No updates available at this time. Brak aktualizacji dostępnych teraz. - + Would you like to launch the installer? Chcesz uruchomić instalator? - - + + Error Błąd - + Error opening file %1: %2. Błąd otwarcia pliku %1: %2. - - Compilation server termporary failure, try later - Serwer kompilacji chwilowo nieczynny, spróbuj później - - - + A new release of Companion is available, please check the OpenTX website! Nowe wydanie Companion jest dostępne, proszę sprawdzić stronę OpenTX! - - Not enough memory for all the selected firmware options - Za mało pamięci dla wybranej konfiguracji firmware - - - + Compilation server too busy, try later Serwer kompilacji zbyt zajęty, spróbuj później - + + Compilation error + + + + + Invalid firmware + + + + + Invalid board + + + + + Invalid language + + + + Unknown server failure, try later Nieznany błąd serwera, spróbuj później - - + + Yes Tak - - + + No Nie - - + + Release Notes Informacje o wydaniu - - + + Do you want to download release %1 now ? Chcesz pobrać wydanie %1 teraz? - - + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + + + + + File saved Plik zapisany - + Firmware updates Aktualizacja firmware - + Current firmware does not provide release notes informations. Aktualny firmware nie zawiera opisu wydania. - + + Models and Settings read + + + + + + This function is not yet implemented + + + + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> Projekt Companion odłączony z oryginalnego <a href='%1'>eePe</a> - + New Nowy - + Open... Otwórz... - + Save Zapisz - + Save As... Zapisz jako... - + Copy Model Kopiuj Model - + Paste Model Wklej Model - + About... O aplikacji... - + Print... Drukuj... - + Simulate... Symulacja... - + Simulate current model Symulacja aktualnego modelu - + Alt+S Alt+S - + Load Backup... Załaduj backup... - + View Log File... Obejrzyj plik logów... - + Open and view log file Otwórz i obejrzyj plik logów - + Edit Settings Edycja Ustawień - + Settings... Ustawienia... - + Download firmware and voice files Pobierz firmware i pliki dźwiękowe - + Create a new Radio Setting Profile Utwórz nowy Profil Ustawień Radia - + + Use default system language. + + + + + Use %1 language (some translations may not be complete). + + + + A monochrome black icon theme Monochromatyczny czarny wygląd ikon - + Do you want to write the firmware to the radio now ? Chcesz wgrać firmware do radia teraz? - + Ignore this release %1? Zignorować to wydanie %1? - - + + Open Models and Settings file Otwórz plik Modeli i Ustawień - + Read Models and Settings From Radio Wczytaj Modele i Ustawienia z radia - + Save Radio Backup to File Zapisz Backup radia do pliku - + Read Radio Firmware to File Odczytaj Firmware radia do pliku - + Create a new Models and Settings file Utwórz nowy plik Modeli i Ustawień - - + + Save Models and Settings file Zapisz plik Modeli i Ustawień - + Cut Model Wytnij Model - + Cut current model to the clipboard Wytnij aktualny model do schowka - + Copy current model to the clipboard Wytnij aktualny model do schowka - + Paste model from clipboard Wklej Model ze schowka - + The classic companion9x icon theme Klasyczny zestaw ikon Companion - + A monochrome white icon theme Monochromatyczny biały wygląd ikon - + A monochrome blue icon theme Monochromatyczny niebieski wygląd ikon - + Small Małe - + Use small toolbar icons Użyj małych ikon paska narzędzi - + Use normal size toolbar icons Użyj normalnych ikon paska narzędzi - + Normal Normalne - + Use big toolbar icons Użyj dużych ikon paska narzędzi - + Big Duże - + Use huge toolbar icons Użyj olbrzymich ikon paska narzędzi - + Huge Olbrzymie - - Czech - Czeski - - - - Use Czech in menus - Użyj Czeskiego w menu - - - - German - Niemiecki - - - - Use German in menus - Użyj Niemieckiego w menu - - - - English - Angielski - - - - Use English in menus - Użyj Angielskiego w menu - - - - Finnish - Fiński - - - - Use Finnish in menus - Użyj Fińskiego w menu - - - - French - Francuski - - - - Use French in menus - Użyj Francuskiego w menu - - - - Italian - Włoski - - - - Use Italian in menus - Użyj Włoskiego w menu - - - - Polish - Polski - - - - Use Polish in menus - Użyj Polskiego w menu - - - - Spanish - Hiszpański - - - - Use Spanish in menus - Użyj hiszpańskiego w menu - - - - Swedish - Szwedzki - - - - Use Swedish in menus - Użyj Szwedzkiego w menu - - - + Edit Radio Splash Image... Edytor ekranu startowego radia... - + Edit the splash image of your Radio Edytuj ekran startowy swojego radia - - + + Read Firmware from Radio Odczytaj Firmware z radia - + Read firmware from Radio Odczytaj Firmware z radia - - + Write Firmware to Radio Zapisz firmware do radia - + Write firmware to Radio Zapisz firmware do radia - + Write Models and Settings To Radio Zapisz Modele i Ustawienia do radia - - + Write Models and Settings to Radio Zapisz Modele i Ustawienia do radia - - + + Read Models and Settings from Radio Wczytaj Modele i Ustawienia z radia - + Configure software for communicating with the Radio Ustaw oprogramowanie komunikacyjne z radiem - + Write Backup to Radio Zapisz Backup do radia - + Backup Radio to File Zbackupuj radio do pliku - + Save a complete backup file of all settings and model data in the Radio Zachowaj kompletny plik backup wszystkich ustawień i danych modeli z radia - + Recent Files Ostatnie Pliki - + Show recent Models+Settings documents Pokaż ostatnie dokumenty Modeli i Ustawień - + Print current model Drukuj aktualny model - + Check OpenTX and Companion updates Sprawdź aktualizacje OpenTX i Companion - + Fuses... Bezpieczniki... - + Manuals and other Documents Podręcznik i dokumentacja - + Open the OpenTX document page in a web browser Otwórz stronę dokumentacji OpenTX w przeglądarce - + A tribute to those who have contributed to OpenTX and Companion Hołd dla tych, którzy przyczynili się do rozwoju OpenTX i Companion - + Contributors... Współpracownicy... - + Recent Models+Settings Ostatnie Modele+Ustawienia - + Set Icon Theme Ustaw wygląd ikon - + Set Icon Size Ustaw wielkość ikon - + A new version of Companion is available (version %1)<br>Would you like to download it? Dostępna jest nowy Companion (wersja %1)<br>Chcesz ją pobrać ? - - Compilation server requires registration, please check OpenTX web site - Serwer kompilacji wymaga rejestracji, proszę odwiedzić stronę OpenTX - - - - The selected language will be used the next time you start Companion. - Wybrany język będzie użyty po ponownym uruchomieniu Comapnion. - - - + The new theme will be loaded the next time you start Companion. Wybrany wygląd będzie użyty po ponownym uruchomieniu Comapnion. - + The icon size will be used the next time you start Companion. Wybrana wielkość ikon będzie użyta po ponownym uruchomieniu Comapnion. - + OpenTX Home Page: <a href='%1'>%1</a> Strona domowa OpenTX: <a href='%1'>%1</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> Jeśli uważasz, że ten program jest użyteczny, wesprzyj poprzez <a href='%1'>donację</a> - + About Companion O aplikacji Companion - + Load backup from file Załaduj backup z pliku - + Exit Zakończ - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -4628,7 +4433,7 @@ Czy chcesz teraz je pobrać? Zalecamy przeczytanie informacji o wydaniu (przycisk poniżej) w celu poznania zmian które mogą być istotne dla Ciebie. - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -4644,214 +4449,219 @@ Czy chcesz teraz pobrać ? Zalecamy przeczytanie informacji o wydaniu (przycisk poniżej) w celu poznania zmian które mogą być istotne dla Ciebie. - - - + + + Companion Companion - - + + Synchronize SD Zsynchronizuj kartę pamięci - + OpenTX Companion %1 - Radio: %2 - Profile: %3 OpenTX Companion %1 - Radio: %2 - Profil: %3 - + Monochrome Monochromatyczny - + MonoWhite Mono-Biały - + MonoBlue Mono-Niebieski - + System language Język systemu - - Use system language in menus - Użyj języka systemu w menu - - - + Download... Pobieranie... - + Check for Updates... Sprawdź aktualizacje... - + Companion Changes... Zmiany w Companion... - + Show Companion change log Pokaż log zmian Companion - + Firmware Changes... Zmiany w Firmware... - + Show firmware change log Pokaż log zmian Firmware - + Compare Models... Porównaj modele... - + List programmers... Lista programistów... - + Add Radio Profile Dodaj profil radia - + Configure Communications... Ustaw komunikację... - + Yerico - + Yellow round honey sweet icon theme Żółty zaokrąglony miodowy motyw ikon - - + + Radio Profile Profil radia - + Write Zapis - + %2 %2 - + Compare models Porównaj modele - + Exit the application Zakończ aplikację companion9x - + List available programmers Lista dostępnych programatorów - + Show fuses dialog Pokaż okno ustawień mikro-kontrolera - + Show the application's About box O aplikacji companion9x - + Copyright OpenTX Team Prawa Zespół OpenTX - + Classical Klasyczny - + Write Backup from file to Radio Zapisz Backup z pliku do radia - + + Not enough flash available on this board for all the selected options + + + + + Compilation server temporary failure, try later + + + + SD card synchronization Synchronizacja karty SD - + Set Menu Language Ustaw język menu - - + + File Plik - - + + Edit Edycja - + Settings Ustawienia - + Read/Write Odczyt/Zapis - - + + Help Pomoc - + Show the list of radio profiles Pokaż listę profili radia - + Ready Gotowe - + New Radio Nowe Radio @@ -4859,134 +4669,260 @@ Zalecamy przeczytanie informacji o wydaniu (przycisk poniżej) w celu poznania z MdiChild - + free bytes wolna pamięć[B] - + Editing model %1: Edycja modelu %1: - - - - - - - - - - - - - - - - - - + + + + + + Error Błąd - - + Unable to find file %1! Nie mogę odnaleźć pliku %1! - - - - + Error opening file %1: %2. Błąd otwarcia pliku %1: %2. - - - Invalid EEPROM File %1 - Zły plik EEPROM %1 - - - - - - + Warning Ostrzeżenie - - Invalid binary EEPROM File %1 - Nieprawidłowy plik binarny EEPROM %1 - - - - - - + + + + Save As Zapisz jako - - - - - Cannot write file %1: -%2. - Nie mogę zapisać pliku %1: -%2. - - - - - Error writing file %1: -%2. - Błąd zapisu pliku %1: -%2. - - - + + Companion Companion - - + Error reading file %1: %2. Błąd odczytu pliku %1: %2. - + %1 has been modified. Do you want to save your changes? %1 został zmieniony. Zapisać? - + + Delete selected models? + + + + + Cannot delete default model. + Nie mogę wykasować bazowego modelu. + + + + &Edit + &Edycja + + + + &Restore from backup + &Odtworzyć z backupu + + + + &Model Wizard + &Kreator ustawień modelu + + + + &Delete + &Wykasuj + + + + Delete + Wykasuj + + + + &Copy + &Kopiuj + + + + Ctrl+C + + + + + &Cut + + + + + Ctrl+X + Ctrl+X + + + + + &Paste + + + + + + Ctrl+V + Ctrl+V + + + + D&uplicate + &Zduplikuj + + + + Ctrl+U + Ctrl+U + + + + Move to Category + + + + + &Use as default + &Użyj jako bazowy + + + + P&rint model + Wy&drukuj model + + + + Ctrl+P + Ctrl+P + + + + &Simulate model + &Zasymuluj model + + + + Alt+S + Alt+S + + + + &Add model + + + + + &Rename category + + + + + &Delete category + + + + + &Add category + + + + + Models and settings will be automatically converted. +If that is not what you intended, please close the file +and choose the correct radio type/profile before reopening it. + + + + + Do you want to overwrite radio general settings? + Czy chcesz nadpisać główne ustawienia radia? + + + + You are pasting on an not empty model, are you sure? + Wklejasz na niepustym modelu, jesteś pewien? + + + + This category is not empty! + + + + + New model + + + + + Unable to find Horus radio SD card! + + + + + Models and Settings written + + + + Cannot write temporary file! Nie mogę zapisać pliku tymczasowego! - + Open backup Models and Settings file Otwórz plik backupu Modeli i Ustawień - + Invalid binary backup File %1 nieprawidłowy binarny plik %1 + + + Radio settings + + + + + Simulate Tx + Symulacja radia + MixerDialog @@ -5195,139 +5131,159 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Jeśli spowolnienie nie jest równe 0 wtedy prędkość miksera zostanie ustawiona na podaną wartość-&gt; wartość oznacza liczbę sekund jaką mikser potrzebuje by pokonać drogę od -100 do 100.</p></body></html> - + DEST -> CH%1 Cel -> KAN%1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + MixesPanel - - + + Move Up W górę - - + + Ctrl+Up Ctrl+Up - - + + Move Down W dół - - + + Ctrl+Down Ctrl+Down - + Clear Mixes Wyczyść miksery - + Not enough available mixers! Za mało dostępnych mikserów! - + Delete Selected Mixes? Skasować wybrane miksery? - + &Add &Dodaj - + Ctrl+A Ctrl+A - + &Edit &Edycja - + Enter Enter - + &Toggle highlight &Przełącz podświetlenie - + Ctrl+T Ctrl+T - + &Delete &Wykasuj - + Delete Wykasuj - + &Copy &Kopiuj - + Ctrl+C Ctrl+C - + Ctrl+X Ctrl+X - + C&ut &Wytnij - + &Paste &Wklej - + Ctrl+V Ctrl+V - + Du&plicate &Zduplikuj - + Ctrl+U Ctrl+U - + Clear Mixes? Wyczyść miksery? - + Really clear all the mixes? Czy na pewno wyczyścić wszystkie miksery? @@ -5345,52 +5301,52 @@ p, li { white-space: pre-wrap; } Symulacja - + Setup Ustawienia - + Heli Heli - + Inputs Wejścia - + Logical Switches Przełączniki logiczne - + Mixes Miksery - + Flight Modes Fazy lotu - + Outputs Wyjścia - + Special Functions Funkcje Specjalne - + Curves Krzywe - + Telemetry Telemetria @@ -5398,281 +5354,308 @@ p, li { white-space: pre-wrap; } ModelPrinter - + %1 bytes %1 bajtów - + CH%1 Kan %1 - + Exponential Exponential - + Extra Fine Bardzo dokładny - + Fine Dokładny - + Medium Średni - + Coarse Zgrubny - + Unknown Nieznany - + Enabled Włączone - + Disabled Wyłączone - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) %1, Kanałów(%2-%3), Opóżnienie PPM(%4usec), Polaryzacja impulsu(%5) - + %1, Channels(%2-%3) %1, Kanały(%2-%3) - + Receiver number(%1) Numer Odbiornika(%1) - + + radio Protocol %1, subType %2, option value %3 + + + + Slave/Jack Uczeń/Jack - + Master/SBUS Module Trener/SBUS Moduł - + Master/CPPM Module Trener/CPPM Moduł - + Master/SBUS in battery compartment Trener/SBUS w kieszeni baterii - + Master/Jack Trener/Jack - + + 90 + 90 + + + + 120 + 120 + + + + 120X + 120X + + + + 140 + 140 + + + Rudder SK - + Elevator SW - + Throttle Gaz - + Aileron Lotki - + Name(%1) Nazwa(%1) - + + Offset(%1) Wyrównanie(%1) - + Delay(u%1:d%2) Opóźnienie(u%1:d%2) - + Persistent Stały - + MinuteBeep Dźwięk minutowy - + CountDown(Beeps) Odlicznie (Pikniecie) - + CountDown(Voice) Odlicznie (Głos) - + CountDown(Haptic) Odlicznie (Wibracje) - + + Off Wyłącz - - - - + + + + FM%1 FM%1 - + FM%1%2 FM%1%2 - + FM%1+%2 FM%1+%2 - + [I%1] [W%1] - + Input%1 Wejście %1 - + Weight Waga - + Switch Przełącznik - - + + NoTrim Bez Trymera - + Weight(%1) Waga(%1) - + Switch(%1) Przełącznik(%1) - + No DR/Expo Bez DR/Expo - + Slow(u%1:d%2) Spowolnienie(u%1:d%2) - + Warn(%1) (%1)Ostrzeżenie - + Disabled in all flight modes Wyłaczone we wszystkich fazach lotu - + Flight modes(%1) Fazy lotu(%1) - + Flight mode(%1) Faza lotu (%1) - + Edge(%1, [%2:%3]) Brzeg(%1, [%2:%3]) - + instant natychmiastowy - + Sticky(%1, %2) Stały(%1, %2) - + Timer(%1, %2) Timer(%1, %2) - + Duration(%1s) Trwanie(%1s) - + Delay(%1s) Opóznienie(%1) - + Custom Własny - + Standard Standard @@ -5680,27 +5663,27 @@ p, li { white-space: pre-wrap; } ModelSelectionPage - + Plane Samolot - + Multirotor Multikopter - + Helicopter Śmigłowiec - + Model Name: Nazwa Modelu: - + Model Type: Typ Modelu: @@ -5708,129 +5691,7 @@ p, li { white-space: pre-wrap; } ModelsListWidget - - - &Edit - &Edycja - - - - &Restore from backup - &Odtworzyć z backupu - - - - &Model Wizard - &Kreator ustawień modelu - - - - &Delete - &Wykasuj - - - - Delete - Wykasuj - - - - &Copy - &Kopiuj - - - - Ctrl+C - Ctrl-C - - - - &Cut - &Wytnij - - - - Ctrl+X - - - - - &Paste - &Wklej - - - - Ctrl+V - Ctrl+V - - - - D&uplicate - &Zduplikuj - - - - Ctrl+U - Ctrl+U - - - - &Use as default - &Użyj jako bazowy - - - - P&rint model - Wy&drukuj model - - - - Ctrl+P - Ctrl+P - - - - &Simulate model - &Zasymuluj model - - - - Alt+S - Alt+S - - - - General Settings - Główne ustawienia - - - - Delete Selected Models? - Skasować wybrane modele? - - - - - Cannot delete default model. - Nie mogę wykasować bazowego modelu. - - - - Cannot cut default model. - Nie mogę wyciąć bazowego modelu. - - - - Do you want to overwrite radio general settings? - Czy chcesz nadpisać główne ustawienia radia? - - - - You are pasting on an not empty model, are you sure? - Wklejasz na niepustym modelu, jesteś pewien? - - - + No free slot available, cannot duplicate Brak wolnych miejsc, nie mogę zduplikować @@ -5838,142 +5699,199 @@ p, li { white-space: pre-wrap; } Module - + Failsafe Mode Tryb Failsafe - + Start Start - + PPM delay Opóźnienie PPM - + Negative Ujemna - + Positive Dodatnia - + Polarity Polaryzacja - + Trainer Mode Tryb trenera - + PPM Frame Length Długość ramki PPM - + CH Kan - + + SubType + + + + + Antenna + + + + + Internal + + + + + Ext. + Int. + + + + + Option value + + + + + Bind on startup + + + + + Low Power + + + + us us - + + Multi Radio Protocol + + + + Master/Jack Trener/Jack - + Slave/Jack Uczeń/Jack - + Master/SBUS Module Trener/SBUS Moduł - + Master/CPPM Module Trener/CPPM Moduł - + Master/SBUS in battery compartment Trener/SBUS w kieszeni baterii - + + Show values in: + + + + + % + abbreviation for percent + % + + + + μs + abbreviation for microseconds + + + + ms ms - + Channels Kanały - + Not set BRAK - + Hold Utrzymuj - + Custom Ustawienia Własne - + No Pulses Brak sygnałów - + Receiver Odbiornik - + Failsafe Positions Pozycja Failsave - + Protocol Protokół - + Receiver No. Nr odbiornika. - + Output type Typ wyjścia - + Open Drain Otwarty dren - + Push Pull Push Pull @@ -5981,45 +5899,45 @@ p, li { white-space: pre-wrap; } ModulePanel - + Trainer Port Port trenera - + Internal Radio System Wewnętrzny moduł radiowy - + External Radio Module External Radio Module - Internal Radio System - zaznaczyć by opisać spójność nazw angielskich Zewnętrzny moduł radiowy - - + + Radio System System radia - + Extra Radio System System Radiowy Ekstra - + Value Wartość - + Hold Utrzymuj - + No Pulse Brak impulsu @@ -6027,229 +5945,322 @@ p, li { white-space: pre-wrap; } MultiModelPrinter - + General Model Settings Główne ustawienia modelu - + Name: Nazwa: - + EEprom Size: Wielkosć EEPROMu: - + Timer%1: Timer%1: - + Module%1: Moduł%1: - + Module: Moduł: - + Trainer port: Port trenera: - + Throttle Trim: Trymer gazu: - + Trim Increment: Zwiększanie trymera: - + Center Beep: Dźwięk środka: - + + Helicopter Setup + + + + + Swash Type: + + + + + Swash Ring: + + + + + Input + Wejście + + + + Weight + Waga + + + + Long. cyc + Długi cykl + + + + Lateral cyc + Boczny cykl + + + + Collective + Pochylenie (Collective) + + + Flight modes Fazy lotu - - + + Flight mode Faza lotu - + Switch Przełącznik - + Fade IN Pojawianie - + Fade OUT Zanikanie - - + + FM%1 FM%1 - - + + GV%1 ZG%1 - + RE%1 RE%1 - + Limits Limity - + Channel Kanał - + Name Nazwa - - + + Offset Wyrównanie - + Min Min - + Max Maks - + Invert Odwróć - + Global Variables Zmienne globalne - + Inputs Wejścia - + Mixers Miksery - + CV%1 CV%1 - + Curves Krzywe - + L%1 L%1 - + Logical Switches Przełączniki logiczne - + SF%1 SF%1 - + Special Functions Funkcje Specjalne - + Telemetry Settings Ustawienia telemetrii - + Analogs Analogowe - + Unit Jednostka - + Scale Skala - + A%1 A%1 - + RSSI Alarms Alarmy RSSI + + + Low Alarm + Alarm niski + + + + Critical Alarm + Alarm krytyczny + + + + Multiprotocols + + + Subtype + + + + + Video TX frequency + + + + + C2500 frequency fine tune + + + + + Telemetry + Telemetria + + + + Radio output power + + + + + Servo output frequency + + + + + Option value + + + + + DEFAULT + + MultirotorPage - + Throttle Channel: Kanał gazu: - + Yaw Channel: Kanał odchylenia: - + Pitch Channel: Kanał kąta: - + Roll Channel: Kanał rotacji: @@ -6257,17 +6268,17 @@ p, li { white-space: pre-wrap; } OptionsPage - + Throttle Cut Odcięcie Gazu - + Throttle Timer Timer Gazu - + Flight Timer Timer Lotu @@ -6290,17 +6301,17 @@ p, li { white-space: pre-wrap; } Drukuj do pliku - + Print Document Drukuj dokument - + Select PDF output file Wybierz plik docelowy PDF - + ODF files (*.odt);;PDF Files(*.pdf);;HTML-Files (*.htm *.html);;All Files (*) pliki ODF (*.odt);;pliki PDF (*.pdf);;pliki HTML (*.htm *.html);;Wszystkie pliki (*) @@ -6334,972 +6345,952 @@ p, li { white-space: pre-wrap; } QObject - - + + Rud SK - - + + Ele SW - - + + Thr Gaz - - + + Ail Lotki - - - + + P1 Potencjometr 1 - - - + + P2 Potencjometr 2 - - - + + P3 Potencjometr 3 - - - - + + + S1 Potencjometr 1 - - - - + + + S2 Potencjometr 2 - - - - + + + LS Lewy suwak - - - - + + + RS Prawy suwak - + TrmR Trymer SK - + TrmE Trymer SW - + TrmT Trymer gazu - + TrmA Trymer lotek - - - + + + REa Pokrętło :a - - - + + + REb Pokrętło :b - - + + Batt Bateria - + A1 Sygnał telemetrii A1 - + A2 Sygnał telemetrii A2 - + Alt Wysokość - + Rpm Obroty - + Fuel Paliwo - + T1 - + SWR SWR - - - - - - - + + + + + + + V V - - + + s s - + ft ft - - - + + + m b - - + + % % - - - + + + km/h km/h - - + + m/s m/s - - + + A A - + mA mA - + kts kts - + f f - - + + mAh mAh - - + + W W - + + mW + + + + dB dB - + rpms rpms - - + + g g - + + Rad + + + + hours godziny - + minutes minuty - + seconds sekundy - + h:m h:m - + m:s m:s - + h:m:s h:m:s - - + F1 F1 - - + F2 F2 - - + F3 F3 - - + F4 F4 - + T2 - + Speed Prędkość - + Dist Odległość - + GPS Alt Wysokość GPS - + Cell Cela - + Vfas - + Curr Natężenie - + Cnsp - + Powr Moc - + Cells Cele - + AccX - + AccY - + AccZ - + VSpd - + A1- - + A2- - + Alt- - + Alt+ - + Rpm+ - + T1+ - + T2+ - - + + Time Czas - - - + + + °C °C - - - + + + ° ° - - - + + + mph mph - - + + °F °F - + MAX - - S11 - P11 - - - - S12 - P12 - - - - S13 - P13 - - - - S14 - P14 - - - - S15 - P15 - - - - S16 - P16 - - - - S21 - P21 - - - - S22 - P22 - - - - S23 - P23 - - - - S24 - P24 - - - - S25 - P25 - - - - S26 - P26 - - - + CYC%1 - - - - + + + + ---- - + THR THR - - - + + + ON Włącz - - - + + + OFF Wyłącz - + Diff(%1) Różnicowość(%1) - + Expo(%1) Expo(%1) - + Function(%1) Funkcja(%1) - + Curve(%1) Krzywa(%1) - + !Curve(%1) !Krzywa(%1) - - + + Support for frsky telemetry mod Wsparcie dla telemetrii FrSky - - + + Support for jeti telemetry mod Wsparcie telemetrii JETI - - + + Support for receiving ardupilot data Wsparcie dla otrzymywania danych ardupilota - - + + Support for receiving NMEA data Wsparcie dla otrzymywania danych NMEA - + Support for telemetry easy board Wsparcie dla platformy TelemetrEZ - - + + Support for MAVLINK devices Wsparcie urządzeń MAVLINK - + Rotary Encoder use in menus navigation Użycie pokrętła do nawigacji w menu - - - - - - + + + + + + Enable heli menu and cyclic mix support Uaktywnione menu Heli i wsparcie dla cyklicznych mikserów - - - - - - - - - + + + + + + Enable TEMPLATES menu Uaktywnienie menu szablonów - - - - + + + + No splash screen Bez loga na ekranie - - - - - - - - - + + + + + + + + + No flight modes Firmware bez menu faz lotu - + Channel values displayed in us Wartości kanałów wyświetlone w us - + + + + + + + + + + + Use alternative SQT5 font Użyj alternatywnego fontu SQT5 - + No OverrideCH functions available Brak dostępnych Funkcji Nadpisania Kanału - + Possibility to enable FAI MODE (no telemetry) at field Umożliwienie uaktywniania trybu FAI(brak telemetrii) w menu na lotnisku - + FAI MODE (no telemetry) always enabled Tryb FAI (brak telemetrii) zawsze aktywny - - - - - Support for a third timer - Wsparcie dla 3ciego Timera - - - + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) Zamiast emulacji joysticka, podłaczenie USB działa jako dysk zewnętrzny (jak w Bootloaderze) - + Instead of Joystick emulation, USB connection is Command Line Interface Zamiast emulacji joysticka, podłaczenie USB działa jako interface linii komend - - Removes D8 and LR12 FrSky protocols that are not legal for use in the EU on radios sold after Jan 1st, 2015 - Usuwa protokoły FrSky D8 i LR12,które są nielegalne na terenie UE w radiach sprzedawanych po 01-01-2015 - - - + + Support for PPM internal module hack Wsparcie dla shakowania wewnętrznego modułu PPM - + ERC12864FSF LCD LCD: ERC12864FSF - + ST7920 LCD LCD: ST7920 - - 9X board - Płyta 9X - - - + EEprom write progress bar Pasek postępu wgrywania EEPROMu - - + + No Winged Shadow How High support Bez wsparcia - Winged Shadow How High - - + + Turnigy 9XR + + + + + No vario support Bez wsparcia wario - - + + No GPS support Bez wsparcia GPS - - + + No gauges in the custom telemetry screen Bez graficznych wskazań telemetrii - + + 9X with stock board + + + + Allow compensating for offset errors in FrSky FAS current sensors Pozwolenie na kompensację błędów w czujnikach natężenia FrSky FAS - - ar9x board / 9X - płyta ar9x / 9X - - - - FrSky Taranis Plus - FrSky Taranis Plus - - - + FrSky Taranis X9E FrSky Taranis X9E - + Confirmation before radio shutdown Potwierdzenie przez wyłączeniem radia - + ST7565P LCD or compatible LCD ST7565P lub kompatybilny - + ST7565R LCD or compatible LCD ST7565R lub kompatybilny - - - Adds mixers output view to the CHANNELS MONITOR screen, pressing [ENT] switches between the views - Dodaje widok wyjścia mikserów do ekrany MONITORA KANAŁÓW, wciśnięcie [ENT] przełącza pomiędzy widokami - - - - MEGA2560 board - Płyta MEGA2560 - - - - Sky9x board / 9X - Płyta Sky9x / 9X - - - - 9XR-PRO - 9XR-PRO - - - - FrSky Taranis - FrSky Taranis - - - + Haptic module installed Moduł wibracji zainstalowany - + Support for Lua model scripts Wsparcie dla skryptów LUA - + + Unknown error + + + + + ... plus %1 errors + + + + + Cannot write radio settings + + + + + Cannot write model %1 + + + + + 6P + 6P + + + + JSx + + + + + JSy + + + + + Support for the DIY-Multiprotocol-TX-Module + + + + + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 + + + + Disable HELI menu and cyclic mix support Dezaktywowane menu Heli i wsparcie dla cyklicznych mikserów - + Disable Global variables dezaktywowane zmienne globalne - - + + Enable Lua compiler + + + + + KS108 LCD + + + + + WTV20 voice module + + + + + JQ6500 voice module + + + + + FrSky Taranis X9D+ + + + + + FrSky Taranis X9D + FrSky Taranis X9E {9D?} + + - - - - - - + Horus gimbals installed (Hall sensors) + + + + + FrSky Taranis X7 + FrSky Taranis X9E {7?} + + + + FrSky Horus + + + + + Use ONLY with first DEV pcb version + + + + + Turnigy 9XR-PRO + + + + + Turnigy 9XR with m128 chip + + + + + + + + + Disable curves menus Bez menu krzywych - - - - + + + + + Support for radio modified with regular speaker Wsparcie dla modyfikacji radia zwykłym głośnikiem - - - - - + + + + + Used if you have modified your radio with voice mode Używane jeśli radio jest zmodyfikowane w calu użycia komunikatów głosowych - - - - - + + + + + Used if you have modified your radio with haptic mode Używane jeśli radio jest zmodyfikowane do użycia wibracji - - - - - - - - - + + + + + + + + + Battery graph Grafika baterii - - - - + + + + Enable the throttle trace in Statistics Uaktywnić śledzenie gazu w statystykach - - M128 / 9X board - Płyta M128 / 9X - - - - 9XR - 9XR - - - - 9XR with M128 chip - 9XR z kością M128 - - - - Gruvin9x board / 9X - Płyta Gruvin9x / 9X - - - - + + Support of FrSky PXX protocol Wsparcie dla protokołu Frsky PXX - - - - - + + + + + Support for DSM2 modules wsparcie modułu DSM2 - - - - - - - - - + + + + + + PPM center adjustment in limits Limit dostrojenia centrowania PPM - - - - - - - - - + + + + + + Symetrical Limits Limity symetryczne - - - - - - - + + + + + + + Pots use in menus navigation Użycie potencjometrów do nawigacji w menu - - + + SmartieParts 2.2 Backlight support Wsparcie podświetlenia SmartieParts 2.2 - - - - - - + + + + + + Enable resetting values by pressing up and down at the same time Szybkie nastawianie wartości (+) a (-) neguje wartość @@ -7308,1273 +7299,1177 @@ p, li { white-space: pre-wrap; } (UP) a (DN) ustawia 0 - - - - - - - - - + + + + + + + + + No graphical check boxes and sliders Brak graficznych pol wyboru i suwaków - - - - - - - - - + + + + + + + + + Don't use bold font for highlighting active items Nie używaj podświetlenia dla wybranych aktywnych elementów, mikserów, krzywych, expo, etc - - - - - + + + + + EEprom write Progress bar Pasek postępu zapisywania EEPROM - - - - - - + + + + + + Imperial units Imperialne jednostki w telemetrii - - - + + + Bluetooth interface Interface Bluetooth - - - - - - - - - + + + + + + + + + Global variables Globalne zmienne - - (displaying only first 10 warnings) - (wyświetlanie tylko pierwszych 10 ostrzeżeń) - - - - - - - - - - - + + + + + + + + + In model setup menus automatically set source by moving the control W menu ustawień modelu automatycznie wybierz źródło poprzez poruszenie nim - - - - - - - - - + + + + + + + + + In model setup menus automatically set switch by moving the control W menu ustawień modelu automatycznie wybierz źródło poprzez poruszenie nim - - + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) Dodanie wsparcia dla odwracania wejścia drążków (np. potrzebne dla gimbali FrSky) - - + + 9X with stock board and m128 chip + + + + + 9X with AR9X board + + + + + 9X with Sky9x board + + + + + 9X with Gruvin9x board + + + + + Support for SD memory card Wsparcie karty SD - + Support for DSM2 modules using ppm instead of true serial Wsparcie modułu DSM2 przez użycie PPM zamiast prawdziwego szeregowego - + + DIY MEGA2560 radio + + + + Power management by soft-off circuitry Zarządzanie zasilaniem przez obwód Soft-Off - - - + + + Enable HELI menu and cyclic mix support Uaktywnij menu HELI i cyklicznych mikserów - - + Warning Ostrzeżenie - - EEPROM saved with these warnings: - EEPROM zapisany z tymi ostrzeżeniami: - - - + English Angielski - + French Francuski - + Italian Włoski - + German Niemiecki - + Czech Czeski - + Slovak Słowacki - + Spanish Hiszpański - + Portuguese Portugalski - + Polish Polski - - Finnish - Fiński + + Dutch + - + + Hungarian + + + + No Nie - + RotEnc A Pokrętło :A - + Rot Enc B Pokrętło :B - + Rot Enc C Pokrętło :C - + Rot Enc D Pokrętło :D - + Rot Enc E Pokrętło :E - + No repeat Bez powtórzeń - - + S3 S3 - - - + + + Timer3 Timer3 - + RSSI Tx RSSI Tx - + RSSI Rx RSSI Rx - + A3 A3 - + A4 A4 - + dTE dTE - + AirSpeed Prędkość wzgl. Powierza - + Hdg Kier - + A3- A3- - + A4- A4- - + AirSpeed+ Prędkość wzgl. Powierza+ - + ACC ACC - + GPS Time Czas GPS - - + L1 L1 - - + L2 L2 - - - L3 - L3 - - - - - L4 - L4 - - - - - L5 - L5 - - - - - L6 - L6 - - - - - L7 - L7 - - - - - L8 - L8 - - - - - L9 - L9 - - - - - L10 - L10 - - - - - L11 - L11 - - - - - L12 - L12 - - - - - L13 - L13 - - - - - L14 - L14 - - - - - L15 - L15 - - - - - L16 - L16 - - - - - L17 - L17 - - - - - L18 - L18 - - - - - L19 - L19 - - - - - L20 - L20 - - - - - L21 - L21 - - - - - L22 - L22 - - - - - L23 - L23 - - - - - L24 - L24 - - - - - L25 - L25 - - - - - L26 - L26 - - - - - L27 - L27 - - - - - L28 - L28 - - - - - L29 - L29 - - - - - L30 - L30 - - - - - L31 - L31 - - - - - L32 - L32 - - - + [I%1] [W%1] - + LUA%1%2 LUA%1%2 - + TR%1 TR%1 - + FM0 TL0 - + FM1 TL1 - + FM2 TL2 - + FM3 TL3 - + FM4 TL4 - + FM5 TL5 - + FM6 TL6 - + FM7 TL7 - + FM8 TL8 - - S31 - S31 - - - - S32 - S32 - - - - S33 - S33 - - - - S34 - S34 - - - - S35 - S35 - - - - S36 - S36 - - - + RudTrim Left SK Trymer lewy - + RudTrim Right SK Trymer prawy - + EleTrim Down SW Trymer w dół - + EleTrim Up SW Trymer w górę - + ThrTrim Down Gaz Trymer w dół - + ThrTrim Up Gaz Trymer w gorę - + AilTrim Left Lotki trymer w lewo - + AilTrim Right Lotki trymer w prawo - + + Trim 5 Down + + + + + Trim 5 Up + + + + + Trim 6 Down + + + + + Trim 6 Up + + + + THs THs - + TH% TH% - + THt THt - + One Jeden - + ??? ??? - + a>x a>x - + a<x a<x - + |a|>x |a|>x - + |a|<x |a|<x - + AND I (logiczne) - + OR Lub (logiczne) - + XOR XOR (Logiczne) - + a=b a=b - + a!=b a!=b - + a>b a>b - + a<b a<b - + a>=b a>=b - + a<=b a<=b - + d>=x d>=x - + |d|>=x |d|>=x - + a=x a=x - + a~x a~x - + Timer Timer - + Sticky Trwałe przełączenie - + + Left Horizontal + Lewy poziomy + + + + Left Vertical + Lewy pionowy + + + + Right Vertical + Prawy pionowy + + + + Right Horizontal + Prawy poziomy + + + + Aux. 1 + + + + + Aux. 2 + + + + + Unknown Nieznane - + Override %1 Nadpisanie %1 - + Trainer Trener - + Trainer RUD Trener - SK - + Trainer ELE Trener - SW - + Trainer THR Trener - Gaz - + Trainer AIL Trener - Lotki - + Instant Trim Natychmiastowe trymowanie - + Play Sound Odtwórz dźwięk - + Reset Zresetuj - + Set Timer %1 Ustaw Timer %1 - + Vario Wariometr - + Play Both Odtwórz oba - + Play Value Odtwórz wartość - + Play Script Odtwórz Skrypt - - Start Logs - Start logowania - - - + Volume Głośność - + Backlight Podświetlenie - + Screenshot Zrzut ekranu - + Adjust GV%1 Ustaw ZG%1 - + SetFailsafe Int. Module Ustaw FailSafe Wew. Modułu - + SetFailsafe Ext. Module Ustaw FailSafe Zew. Modułu - + RangeCheck Int. Module Sprawdzenie Zasiegu Wew. Modułu - + RangeCheck Ext. Module Sprawdzenie Zasiegu Zew. Modułu - + Bind Int. Module Bindowanie Wew. Modułu - + Bind Ext. Module Bindowanie Zew. Modułu - + Flight Lot - + Rotary Encoder Pokrętło - - - + + + <font color=red><b>Inconsistent parameter</b></font> Niespójny parametr <font color=red><b>Niespójny parametr</b></font> - + played once, not during startup Odtworzone raz, nie w czasie startu - + repeat(%1s) powtórz(%1s) - + DISABLED Wyłączone - + INV Odwróć - + NOR NormalnyNOR - + + -GV%1 (%2) + + + + + GV%1 (%2) + + + + !Flight mode %1 !Faza lotu %1 - + Flight mode %1 Faza lotu %1 - + Yellow Żółty - + Orange Pomarańczowy - + Red Czerwony - + Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (nie obsługiwane) - + FrSky Sensor Hub Hub sensora FrSky - + None Żaden - + Imperial Imperialne - + Metric Metryczne - + + + Uknown error during Simulator startup. + + + + + Simulator Error + + + + + Data Load Error + + + + + Error occurred while starting simulator. + + + + Play Track Odtwórz ścieżkę - - - + + + --- - + Rud Trim Trymer SK - + Ele Trim Trymer SW - + Thr Trim Trymer gazu - + Ail Trim Trymer lotek - + Rot Enc Pokrętło - + Swedish Szwedzki - + CH%1 Kan %1 - + Haptic Wibracje - + Background Music Muzyka tła - + Background Music Pause Muzyka tła - pauza - - - + + + Timer1 Timer1 - - - + + Trm5 + + + + + Trm6 + + + + + + Timer2 Timer2 - + Speed+ Prędkość+ - + Dist+ Dyst+ - + Cell- Cela- - + Cells- Cele- - + Vfas- Vfat- - + Curr+ Natęż+ - + Powr+ Moc+ - + + + L%1 + L%1 + + + Edge Brzeg - + + SD Logs + + + + Telemetry Telemetria - + Value Wartość - + Decr: Zmniejsz: - + Incr: Zwiększ: - + Played once, not during startup Odtwarzaj raz, nie w trakcie uruchomienia - + %1s - + Value Wartość - + Source Źródło - + GVAR Zmienna - + Increment Zwiększanie - + Own value Własna Wartość - + Flight mode %1 value Flight phase %1 value Wartość Fazy lotu FL%1 - + Keys Przyciski - + Sticks Drążki - + Keys + Sticks Przyciski i Drążki - - + + -GV%1 -ZG%1 - - - + + + GV%1 ZG%1 - + Simulator for this firmware is not yet available Nie jest dostępny symulator dla tego firmware - - - Simultaneous usage of expo and curves is no longer supported - Równoległe użycie expo i krzywych nie jest dłużej wspierane + + Switch + Przełącznik - + + Switch + + + + + cannot be exported on this board! + + + + Source %1 cannot be exported on this board! Źródło %1 nie może być wyeksportowane na tę płytę! - + OpenTX only accepts %1 points in all curves OpenTX zezwala tylko na %1 punktów we wszystkich krzywych - + OpenTx only accepts %1 points in all curves OpenTX zezwala tylko na %1 punktów we wszystkich krzywych - - - - - + + + + + + OpenTX on this board doesn't accept this function OpenTX na tej platformie nie dopuszcza tej funkcji - + OpenTX doesn't accept this telemetry protocol OpenTX nie obsługuje tego protokołu telemetrii - - - + + + OpenTX doesn't accept this radio protocol OpenTX nie obsługuje tego protokołu radiowego - + OpenTX doesn't allow this number of channels OpenTX nie obsługuje tej ilości kanałów - - th9x on this board doesn't have Rotary Encoders - th9x nie posiada pokręteł na tej platformie - - - + Trim disabled Trymery wyłączone - + Own Trim Własne trymery - + Use Trim from Flight mode %1 Użyj trymerów dla Fazy Lotu %1 - + Use Trim from Flight mode %1 + Own Trim as an offset Użyj trymerów dla Fazy Lotu %1 + Własne trymery jako wyrównania - + FW: %1 FW:%1 - + Pict: %1 Obrazek:%1 - + Profile image Obrazek Profilu - - Simultaneous usage of expo and curves is no longer supported in OpenTX - Jednoczesne użycie expo i krzywych nie jest dłużej wspierane w OpenTX - - - + Thank you for upgrading to OpenTX 2.0. This is a major upgrade that adds and modifies a lot of things, so please make sure that you read release notes carefully to learn about the changes, and thoroughly check each of your models for proper function. The OpenTX Team. @@ -8583,109 +8478,497 @@ The OpenTX Team. Zespół OpenTX. - + GV ZG - - - - - + + + + + Synchronization error Błąd synchronizacji - + No SD directory configured! Nieskonfigurowany katalog karty SD! - + No Radio connected! Radio niepodłączone! - - + + The directory '%1' doesn't exist! Katalog '%1' nie istnieje! - + Create '%1' failed Utworzenie '%1' nieudane - + Copy '%1' to '%2' failed Skopiowanie '%1' do '%2' nieudane - + Open '%1' failed Otwarcie '%1' nieudane - + Write '%1' failed Zapis '%1' nieudany - + -%1 -%1 - + Positive Dodatni - + Negative Ujemny - - - + + + + + + + Error Błąd - + Cannot write file %1: %2. Nie mogę zapisać pliku %1: %2. - + Companion Companion - + <b><u>WARNING!</u></b><br>This will reset the fuses of %1 to the factory settings.<br>Writing fuses can mess up your radio.<br>Do this only if you are sure they are wrong!<br>Are you sure you want to continue? <b><u>UWAGA!</u></b><br>U zresetuje bezpieczniki %1 do fabrycznych ustawień.<br>Zapis bezpieczników może uszkodzić twoje radio.<br>Zrób to tylko jeśli jesteś pewien że są złe!<br>Jesteś pewien by kontynuować? - - + + Could not delete temporary file: %1 Nie mogę skasować pliku tymczasowego: %1 - - Radio type - Typ radia + + Unable to find Horus radio SD card! + - - Which radio type do you want to simulate? - Które radio chcesz zasymulować ? + + Conversion error on field %1 + + + + + Negative span + Ujemny zakres + + + + Mid value + Wartość środkowa + + + + Positive span + Dodatni zakres + + + + + Models + Translators do NOT use accent for this, this is the default category name on Horus. + + + + + Select a data file + + + + + Select Data Directory + + + + + Select SD Card Image Folder + + + + + Available profiles: + + + + + ID: + + + + + Name: + + + + + Available radios: + + + + + WARNING: couldn't initialize SDL: +%1 + + + + + ERROR: No simulator libraries available. + + + + + Radio profile ID or Name to use for simulator. + + + + + Radio type to simulate (usually defined in profile). + + + + + show this help text + + + + + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] + + + + + Options: + + + + + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. + Profile ID: [%1]; Radio ID: [%2]; +Data File: [%3] + + + + + ERROR: Radio profile or simulator firmware not found. +Profile ID: [%1]; Radio ID: [%2] + + + + + Error reading %1: %2 + + + + + Cannot save EEPROM + + + + + + Cannot open file %1: +%2. + + + + + + + Error writing file %1: +%2. + Błąd zapisu pliku %1: +%2. + + + + Invalid binary EEPROM file %1 + + + + + Can't extract RADIO/radio.bin + + + + + Can't extract RADIO/models.txt + + + + + Can't extract %1 + + + + + Unable to open %1: %2 + + + + + Invalid EEPROM file %1 + + + + + Invalid EEPROM File %1 + Zły plik EEPROM %1 + + + + + Error opening file %1: +%2. + Błąd otwarcia pliku %1: +%2. + + + + Error opening OTX archive %1 + + + + + Error initializing OTX archive writer + + + + + Error creating OTX file %1: +%2. + + + + + Error creating OTX archive + + + + + Error adding %1 to OTX archive + + + + + Error opening file %1 in write mode: +%2. + + + + + Unable to find file %1! + Nie mogę odnaleźć pliku %1! + + + + QxtCommandOptions + + + sets the application GUI style + + + + + sets the application stylesheet + + + + + restores the application from an earlier session + + + + + displays debugging information about widgets + + + + + use right-to-left layout + + + + + never grab the mouse or keyboard + + + + + grab the mouse/keyboard even in a debugger + + + + + run in synchronous mode for debugging + + + + + use Direct3D by default + + + + + sets the X11 display + + + + + sets the geometry of the first window + + + + + sets the default font + + + + + sets the default background color + + + + + sets the default foreground color + + + + + sets the default button color + + + + + sets the application name + + + + + sets the application title + + + + + sets the X11 visual type + + + + + limit the number of colors on an 8-bit display + + + + + use a private color map + + + + + sets the input method server + + + + + disable the X Input Method + + + + + sets the style used by the input method + + + + + + option "%1" not found + + + + + Short options cannot have optional parameters + + + + + positional() called before parse() + + + + + unrecognized() called before parse() + + + + + count() called before parse() + + + + + value() called before parse() + + + + + parameters() called before parse() + + + + + unrecognized parameters: + + + + + %1 requires a parameter + + + + + RadioKnobWidget + + + Right-double-click to reset to center. + @@ -8706,10 +8989,100 @@ Zespół OpenTX. OK + + RadioOutputsWidget + + + Form + Formularz + + + + View: + + + + + Logical Switches + Przełączniki logiczne + + + + Global Variables + Zmienne globalne + + + + Channel Outputs + + + + + L +o +g +i +c + + + + + G +l +o +b +a +l + + + + + C +h +a +n +n +e +l +s + + + + + RadioSwitchWidget + + + Latch/unlatch the momentary switch. + + + + + RawSwitch + + + ↑ + + + + + ↓ + + + + + - + + + + + ! + + + ReleaseNotesDialog - + Companion Release Notes Informacje o wydaniu Companion @@ -8717,7 +9090,7 @@ Zespół OpenTX. ReleaseNotesFirmwareDialog - + OpenTX Release Notes Informacje o wydaniu OpenTX @@ -8725,17 +9098,17 @@ Zespół OpenTX. RudderPage - + No Nie - + Yes Tak - + <br>Rudder Channel: <br> Kanał Steru Kierunku: @@ -8911,7 +9284,7 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również SetupPanel - + Timer %1 Timer %1 @@ -8919,179 +9292,847 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również SimpleTailPage - + Elevator Channel: Kanał Steru Wysokości: - SimulatorDialog + SimulatedUIWidget - - + + Rotary encoder click + + + + + Take Screenshot + + + + + screenshot + Simulator LCD screenshot file name prefix + + + + + SimulatedUIWidget9X + + + UP/PG-UP + + + + + [ UP ] + + + + + DN/PG-DN + + + + + [ DN ] + + + + + RIGHT/+ + + + + + [ + ] + + + + + LEFT/- + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + [ UP ]/[ DN ] or Rotary Sel. + + + + + SimulatedUIWidgetX12 + + + PG-UP + + + + + [ PgUp ] + + + + + PG-DN + + + + + [ PgDn ] + + + + + UP + + + + + [ MDL ] + + + + + DN/DEL/BKSP + + + + + [ RTN ] + + + + + LEFT + + + + + [ SYS ] + + + + + RIGHT + + + + + [ TELE ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/X + + + + + Rotary UP + + + + + +/C + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX7 + + + Taranis X7 Simulator + + + + + PG-UP + + + + + [ PAGE ] + + + + + PG-DN + + + + + [ MENU ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatedUIWidgetX9 + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + +/UP + + + + + [ + ] + + + + + -/DN + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ ENT ] + + + + + WHEEL/PAD SCRL + + + + + [ + ]/[ - ] + + + + + SimulatedUIWidgetX9E + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + + + + + Rotary Selector + + + + + -/UP + + + + + Rotary UP + + + + + +/DN + + + + + Rotary DOWN + + + + + ENTER/MOUSE-MID + + + + + Selector Press + + + + + SimulatorMainWindow + + + OpenTx Simulator + + + + + View + + + + + Radio Window + + + + + Reload... + + + + + Tools + + + + + Toolbar + + + + + Reload Lua Scripts + + + + + Reload the Lua environment on the simulated radio. + + + + + F7 + F7 + + + + Reload Radio Data + + + + + Reload all radio data without restarting the simulator. + + + + + F9 + F9 + + + + Key Mapping + + + + + Show keyboard maping reference. + + + + + F1 + F1 + + + + Joystick Settings + + + + + Open joystick configuration settings dialog. + + + + + F3 + F3 + + + + LCD Screenshot + + + + + Save a screenshot of the current simulated LCD screen. + + + + + F8 + F8 + + + + Dock In Main Window + + + + + Show the radio in the main window or as a separate "floating" window. + + + + + Menu Bar + + + + + Show or hide the top menu bar. + + + + + Alt+M + + + + + Constrain Width + + + + + Set radio widget width to be a fixed size. + + + + + Constrain Height + + + + + Set radio widget height to be a fixed size. + + + + + ERROR: Failed to create simulator interface, possibly missing or bad library. + + + + + Alt+T + + + + + Radio Outputs + + + + + F2 + F2 + + + + Telemetry Simulator + Symulator telemetrii + + + + F4 + F4 + + + + Trainer Simulator + + + + + F5 + F5 + + + + Debug Output + Wyjście debugera + + + + F6 + F6 + + + + Simulator Controls: + + + + + <tr><th>Key/Mouse</td><th>Action</td></tr> + + + + + Simulator Help + + + + + SimulatorStartupDialog + + + OpenTX Simulator - Startup Options + + + + + Simulator Startup Options: + + + + + Radio Profile: + + + + + Existing radio profiles are shown here.<br /> +Create or edit profiles using the Companion application. + + + + + Radio Type: + + + + + Existing radio simulators are shown here.<br /> +The radio type specified in the selected profile is used by default. + + + + + Data Source: + + + + + Data File: + + + + + Data Folder: + + + + + SD Image Path: + + + + + Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> +<b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! + + + + + Select data file... + + + + + + + ... + ... + + + + Directory containing RADIO and MODELS folders to use.<br /> +New folder(s) with default radio/model will be created here if necessary. + + + + + Select data folder... + + + + + Directory containing the SD card image to use.<br/> +The default is configured in the chosen Radio Profile. + + + + + Select SD card image folder... + + + + + Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. + + + + + File + Plik + + + + Folder + + + + + SD Path + + + + + All files (*.*) + + + + + SimulatorWidget + + + Companion Simulator + Symulator Companion + + + + Radio Simulator (%1) + + + + + Could not determine startup data source. + + + + + Could not load data, possibly wrong format. + + + + + Data Load Error + + + + + Invalid startup data provided. Plese specify a proper file/path. + + + + + Simulator Startup Error + + + + + Error saving data: could open file for writing: '%1' + + + + + Error saving data: could not get data from simulator interface. + + + + + An unexpected error occurred while attempting to save radio data to file '%1'. + + + + + Data Save Error + + + + Warning - Ostrzeżenie + Ostrzeżenie - - Joystick enabled but not configured correctly - Joystick uaktywniony ale nieprawidłowo skonfigurowany - - - + Cannot open joystick, joystick disabled - Nie mogę otworzyć joysticka, dezaktywowany + Nie mogę otworzyć joysticka, dezaktywowany - - Simulating Radio (%1) - Symulacja Radia (%1) - - - - - Outputs - Wyjścia - - - + Firmware %1 error: %2 - Firmware %1 błąd: %2 + Firmware %1 błąd: %2 - SimulatorDialog9X + SliderWidget - - Companion Simulator - Symulator Companion - - - - - - - Right Double Click to Reset - Podwójne kliknięcie PPM w celu zresetowania - - - - - Hold X - Przytrzymaj X - - - - - Fix X - Zablokuj X - - - - - Fix Y - Zablokuj Y - - - - - Hold Y - Przytrzymaj Y - - - - Outputs2 - Wyjścia2 - - - - Gvars - Zm-Gl - - - - BEEP - Dźwięk - - - - 9x Simulator - Symulator 9x - - - - Outputs - Wyjścia - - - - SimulatorDialogTaranis - - - Companion Simulator - Symulator Companion - - - - Outputs2 - Wyjścia2 - - - - Gvars - Zm-Gl - - - - S3 - S3 - - - - S4 - S4 - - - - - Hold Y - Przytrzymaj Y - - - - - Fix Y - Zablokuj Y - - - - - Fix X - Zablokuj X - - - - - Hold X - Przytrzymaj X - - - - - - - Right Double Click to Reset - Podwójne kliknięcie PPM w celu zresetowania - - - - Taranis Simulator - Symulator Taranis - - - - Outputs - Wyjścia + + Right-double-click to reset to center. + @@ -9103,27 +10144,27 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również ... - + Splash Library - page %1 of %2 Biblioteka obrazków - strona %1 z %2 - + Warning Ostrzeżenie - + Invalid image in library %1 Nieprawidłowy obrazek w bibliotece %1 - + Information Informacja - + No valid image found in library, check your settings Nie znaleziono prawidłowego obrazka w bibliotece, sprawdź ustawienia @@ -9131,7 +10172,7 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również StandardPage - + Channel %1 Kanał %1 @@ -9139,43 +10180,41 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również SyncProcess - + %1/%2 files Pliki %1/%2 - + Create directory %1 Utwórz katalog %1 - - Copy %1 to %2 - - Skopuj %1 do %2 + + Copy %1 to %2 + Skopuj %1 do %2 {1 ?} {2?} - - Write %1 - - Zapisz %1 + + Write %1 + Zapisz %1 {1?} TailPage - + Rudder Channel: Kanał Steru Kierunku: - + Elevator Channel: Kanał Steru Wysokości: - + Only one channel still available!<br>You probably should configure your model without using the wizard. TYlko jeden kanał jest dostepny!<br>Prawdopoobnie musisz skonfigurować swój model bez użycia konfiguratora. @@ -9183,22 +10222,22 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również TailSelectionPage - + Elevator and Rudder Ster Wysokości i Ster Kierunku - + Only Elevator Tylko Ster Wysokości - + V-tail Usterzenie motylkowe - + Tail Type: Typ ogona: @@ -9478,7 +10517,7 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również Meters (m or ft) Wysokość (m albo ft) - + Temp (°) Temp (°) @@ -9494,7 +10533,7 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również miliAmpery (mA) - + Range Zasięg @@ -9507,22 +10546,22 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również Typ panelu - + None Żaden - + Numbers Liczby - + Bars Paski - + Script Skrypt @@ -9550,99 +10589,99 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również TelemetryPanel - + Telemetry screen %1 Panel Telemetrii %1 - + Low Alarm Alarm niski - + Critical Alarm Alarm krytyczny - + Winged Shadow How High Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (Nie obsługiwane) - - - + + + A1 A1 - + Alti Wysokościomierz - + FrSky S.PORT - + FrSky D FrSky D - + FrSky D (cable) FrSky D (kabel) - + Alti+ Wysokościomierz+ - + VSpeed Prędkość Pionowa - - - + + + A2 A2 - - + + A3 A3 - - + + A4 A4 - - + + FAS FAS - + Cells Cele - + --- --- @@ -9801,12 +10840,12 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również ft ft - + °C °C - + °F °F @@ -9828,26 +10867,36 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również + mW + + + + dBm dBm - + g g - - + + ° ° - + + Rad + + + + mL ml - + US fl.Oz. US fl.Oz. @@ -9857,57 +10906,57 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również Bezwymiarowe (-) - + Ratio Współczynnik - + Positive Dodatni - + RPM RPM - + Precision Precyzja - + Blades Łopaty - + Offset Wyrównanie - + Multiplier Mnożnik - + Auto Offset Wyrównanie automatyczne - + Filter Filtr - + Logs Logi - + Persistent Stały @@ -9915,22 +10964,22 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również TelemetrySensorPanel - + Lowest Najniższy - + Cell %1 Cela %1 - + Highest Najwyższy - + Delta Delta @@ -9938,240 +10987,560 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również TelemetrySimulator - + Telemetry Simulator Symulator telemetrii - - Vario Altitude - Wysokość z wariometru - - - - V-ALT - W-Wys - - - - Vario Vertical Speed - Prędkość pionowa z wario - - - - V-VSPD - W-Prędk - - - - ACCZ - Przysp.Z - - - - GPS Time - Czas GPS - - - - GPS-T - CZ-GPS - - - - ACCX - Przysp.X - - - - GPS Lat/Lon - Poz. GPS - - - - GPS-LL - P-GPS - - - + VFAS Napięcie - - FAS-V - Napięcie - - - - GPS Speed - Prędk GPS - - - - GPS-S - P-GPS - - - - CELLS - Ogniwa - - - - ACCY - Przysp.Y - - - - GPS Course - Kurs GPS - - - - GPS-C - K-GPS - - - - GPS Altitude - Wys. GPS - - - - GPS-A - W-GPS - - - - CURRENT - Natężenie - - - - FAS-C - Natężenie - - - - 30 - 30 - - - + RSSI RSSI - - 75 - 75 - - - + SWR SWR - - FR_ID_AIR_SPEED - FR_ID_Predk_Powietrza - - - - ASPD - ASIR - - - + A1 A1 - + A2 A2 - + + Simulate + Symulacja + + + + Replay SD Log File + + + + + Replay rate + + + + + Load + + + + + |> + + + + + <| + + + + + > + > + + + + <- + + + + + X + X + + + + Row # +Timestamp + + + + + 1/5x + 1/5x + + + + 5x + 5x + + + + No Log File Currently Loaded + + + + + + + V / ratio + + + + + Db + + + + + RxBt + + + + + + + + + + + + + + + + + <html><head/><body><p><br/></p></body></html> + + + + + Tmp1 + + + + A3 A3 - + A4 A4 - - Temperature 1 - Temp 1 + + Tmp2 + - - T1 - T1 + + Fuel + Paliwo - - Temperature 2 - Temp 2 + + °C + °C - - T2 - T2 + + ml + - + + Deg. C + + + + + % + % + + + + + Meters + + + + + Alt + Wysokość + + + + VSpd + + + + + m/s + m/s + + + + Fuel Qty + + + + + + km/h + km/h + + + + Hdg + + + + + ASpd + + + + + + + G + + + + + GPS + + + + + Lat,Lon +(dec.deg.) + + + + + AccX + + + + + dd-MM-yyyy +hh:mm:ss + + + + + Date + + + + + Amps + + + + + AccZ + + + + + GAlt + + + + + + Volts + + + + + Cels + + + + + Curr + Natężenie + + + + AccY + + + + + GSpd + + + + + Degrees + + + + + RPM RPM - - FUEL - Paliwo - - - + When enabled, sends any non-blank values as simulated telemetry data. Kiedy aktywne, wysyła jakiekolwiek dane jako symulację danych telemetrii. - - simulate - symulacja + + Log File + - - Instance - Wystąpienie + + LOG Files (*.csv) + - - 2 - 2 + + ERROR - invalid file + + + + + Templates + + + Simple 4-CH + Proste 4 kanały - - <html><head/><body><p>Start with <span style=" font-style:italic;">0x</span> for hex, <span style=" font-style:italic;">0</span> for octal, otherwise decimal.<br/>Numeric entry only. Blank values are not sent.</p></body></html> - <html><head/><body><p>Start with <span style=" font-style:italic;">0x</span> Dla HEX, <span style=" font-style:italic;">0</span> dla OCTAL, inaczej decymalnie.<br/>Wejscie tylko numeryczne puste dane nie będą wysyłane.</p></body></html> + + T-Cut + Wył Gazu + + + + Sticky T-Cut + Stały wyłącznik Gazu + + + + V-Tail + Motylkowy + + + + Elevon\Delta + Elevon/Delta + + + + Heli Setup + Ustawienie Heli + + + + Heli Setup with gyro gain control + Ustawienie heli ze stabilizacją Żyro + + + + Gyro gain control + Stabilizacja Żyro + + + + Heli Setup (Futaba's channel assignment style) + Ustawienie heli (Ustawienie kanałów w stylu Futaby) + + + + Heli Setup with gyro gain control (Futaba's channel assignment style) + Ustawienie heli ze stabilizacją Żyro(Ustawienie kanałów w stylu Futaby) + + + + Gyro gain control (Futaba's channel assignment style) + Stabilizacja Żyro(Ustawienie kanałów w stylu Futaby) + + + + Servo Test + Test Serwa + + + + MultiCopter + Wielowirnikowiec + + + + Use Model Config Wizard + Użyj konfiguratora modelu + + + + Apply Template? + Dodać szablon ? + + + + Apply template "%1"? + Dodać szablon "%1"? + + + + + + + + + + RUD + SK + + + + + + + + + + + + + ELE + SW + + + + + + THR + + + + + + + + + + + + AIL + Lotki + + + + + + + AIL2 + Lotka2 + + + + + + + ELE2 + SW2 + + + + + + + + + FLAPS + Klapy + + + + + + + + + FLAP%1 + Klapy %1 + + + + + + + PITCH + Pochylenie + + + + + + + + + + + GYRO + ŻYRO + + + + + SPOIL + Spoiler + + + + + SPOIL%1 + Spoiler%1 + + + + + RUD2 + SK2 + + + + + Clear Mixes? + Wyczyść miksery? + + + + Really clear existing mixes on CH6? + Na pewno wyczyścić mikser na kanale 6? + + + + Really clear existing mixes on CH5? + Na pewno wyczyścić mikser na kanale 5? ThrottlePage - + Yes Tak - + No Nie - + <br>Throttle Channel: <br>Kanał gazu: @@ -10192,37 +11561,37 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również TimerPanel - + Silent Cisza - + Beeps Dźwięk - + Voice Komunikaty głosowe - + Haptic Wibracje - + Not persistent Niestałe - + Persistent (flight) Stałe (lot) - + Persistent (manual reset) Stałe (Ręczny reset) @@ -10353,33 +11722,94 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również TrainerSimulator - + Trainer simulator Symulator trenera + + TreeModel + + + Index + + + + + Name + Nazwa + + + + Size + + + VTailPage - + First Tail Channel: Pierwszy Kanał Ogona: - + Second Tail Channel: Drugi Kanał Ogona: + + VirtualJoystickWidget + + + Hld Y + + + + + Hold Vertical stick position. + + + + + Fix Y + Zablokuj Y + + + + Prevent Vertical movement of stick. + + + + + Fix X + Zablokuj X + + + + Prevent Horizontal movement of stick. + + + + + Hld X + + + + + Hold Horizontal stick position. + + + WingtypeSelectionPage - + Standard Wing Standardowe Skrzydło - + Flying Wing / Deltawing Latające skrzydło / Delta @@ -10387,273 +11817,273 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również WizardDialog - + Model Wizard Kreator ustawień modelu - + Model Type Typ modelu - + Enter model name and model type. Wprowadź nazwę modelu i typ. - + Throttle Gaz - + Has your model got a motor or an engine? Czy Twój model posiada silnik? - + Wing Type Rodzaj Skrzydeł - + Is your model a flying wing/deltawing or has it a standard wing configuration? Czy Twój model jest latającym skrzydłem/deltą czy posiada standardowe skrzydła? - + Ailerons Lotki - + Has your model got ailerons? Czy Twój model posiada lotki? - + Flaps Klapy - + Has your model got flaps? Czy Twój model posiada klapy? - + Airbrakes Hamulce aerodynamiczne - + Has your model got airbrakes? Czy Twój model posiada hamulce aerodynamiczne? - + Flying-wing / Delta-wing Latające skrzydło / Delta - + Select the elevons channels Wybierz kanały Elevon - + Rudder Ster Kierunku - + Does your model have a rudder? Czy Twój model posiada ster kierunku? - + Tail Type Typ Ogona - + Select which type of tail your model is equiped with. Wybierz typ ogona Twojego modelu. - - + + Tail Ogon - - + + Select channels for tail control. Wybierz kanały kontrolujące ogon. - + V-Tail Motylkowy - + Select elevator channel. Wybierz kanał Steru Wysokości. - + Cyclic Okresowy - + Which type of swash control is installed in your helicopter? Jaki typ sterowania tarczy ma Twój śmigłowiec? - + Tail Gyro Gyro ogonowe - + Has your helicopter got an adjustable gyro for the tail? Czy Twój śmigłowiec posiada regulowane Gyro ogonowe? - + Rotor Type Typ Wirnika - + Has your helicopter got a flybar? Czy Twój model posiada flybar? - - + + Helicopter Śmigłowiec - - + + Select the controls for your helicopter Wybierz sterowanie Twojego śmigłowca - + Multirotor Wielowirnikowiec - + Select the control channels for your multirotor Wybierz sterowanie Twojego wielowirnikowca - + Model Options Opcje Modelu - + Select additional options Wybierz dodatkowe opcje - + Save Changes Zapisz Zmiany - + Manually check the direction of each control surface and reverse any channels that make controls move in the wrong direction. Remove the propeller/propellers before you try to control your model for the first time.<br>Please note that continuing removes all old model settings! Ręcznie sprawdź kierunki działania płaszczyzn sterowych i odwróć kanał którego kontrola działa w nieprawidłowym kierunku. Zdemontuj śmigło(a) przed sprawdzeniem pierwszy rac Twojego modelu.<br> Uwaga: kontynuacja usunie stare ustawienia modelu! - + Enter a name for your model and select model type. Wprowadź nazwę modelu i typ. - + Select the receiver channel that is connected to your ESC or throttle servo.<br><br>Throttle - Spektrum: CH1, Futaba: CH3 Wybierz kanał odbiornika który kontroluje ESC/serwo gazu.<br><br>Gaz - Spektrum: Kn1, Futaba: Kn3 - + Most aircraft have a main wing and a tail with control surfaces. Flying wings and delta winged aircraft only have a single wing. The main control surface on a standard wing controls the roll of the aircraft. This surface is called an aileron.<br>The control surface of a delta wing controls both roll and pitch. This surface is called an elevon. Większość samolotów posiada powierzchnie sterowe na skrzydłach i ogonie. Latające skrzydło oraz delta posada tylko sterowanie na skrzydłach. Główne powierzchnie sterowe standardowych skrzydeł powodują obrót samolotu w osi podłużnej. Są to lotki.<br> Powierzchnie sterowe na skrzydle w delcie i latającym skrzydle działają jako lotki i ster wysokości. Są to sterolotki. - + Models use one or two channels to control the ailerons.<br>A so called Y-cable can be used to connect a single receiver channel to two separate aileron servos. If your servos are connected by a Y-cable you should select the single-servo option.<br><br>Aileron - Spektrum: CH2, Futaba: CH1 Większość modelu używa jednego lub 2ch kanałów do sterowania lotkami.<br><br>Przez tzw. Y-kabel mogą być kontrolowane 2 serwa na jednym kanale. Jeśli używasz Y-kabla wybierz opcję z jednym serwem.<br><br> Lotki - Spektrum: Kan2, Futaba: Kan1 - + Models use two channels to control the elevons.<br>Select these two channels Modele używają dwóch kanałów do kontrolowania sterolotek.<br>Wybierz dwa kanały - + This wizard assumes that your flaps are controlled by a switch. If your flaps are controlled by a potentiometer you can change that manually later. Kreator uznaje że kontroluje klapy tylko przełącznikiem. Jeśli chcesz kontrolować klapy potencjometrem możesz zmienić to ręcznie później. - + Air brakes are used to reduce the speed of advanced sail planes.<br>They are very uncommon on other types of planes. Hamulce aerodynamiczne są używane do zmniejszenia prędkości szybowca.<br> Sa bardzo rzadko używane w innych typach samolotów. - + Select the receiver channel that is connected to your rudder.<br><br>Rudder - Spektrum: CH4, Futaba: CH4 Wybierz kanał odbiornika który kontroluje Ster Kierunku.<br><br>Ster Kierunku - Spektrum: Kn4, Futaba: Kn4 - + Select the tail type of your plane. Wybierz typ ogona Twojego modelu. - + Select the Rudder and Elevator channels.<br><br>Rudder - Spektrum: CH4, Futaba: CH4<br>Elevator - Spektrum: CH3, Futaba: CH2 Wybierz kanały sterów wysokości i kierunku.<br><br>Ster Kierunku - Spektrum: Kn4, Futaba: Kn4<br>Ster Wysokości - Spektrum: Kn3, Futaba: Kn2 - + Select the Elevator channel.<br><br>Elevator - Spektrum: CH3, Futaba: CH2 Wybierz kanał Steru wysokości.<br><br>Ster Wysokości - Spektrum: Kn3, Futaba: Kn2 - - - - - - - + + + + + + + TBD. TBD. - + Select the control channels for your multirotor.<br><br>Throttle - Spektrum: CH1, Futaba: CH3<br>Yaw - Spektrum: CH4, Futaba: CH4<br>Pitch - Spektrum: CH3, Futaba: CH2<br>Roll - Spektrum: CH2, Futaba: CH1 Wybierz kanały kontroli Twojego wielowirnikowca.<br><br>Gaz - Spektrum: Kn1, Futaba: Kn3<br>>Odchylenie - Spektrum: Kn4, Futaba: Kn4<br>Kąt - Spektrum: Kn3, Futaba: Kn2<br>Rotacja - Spektrum: Kn2, Futaba: Kn1 - + There is no help available for the current page. Brak pomocy dla aktualnej strony. - + Model Wizard Help Pomoc kreatora modelu @@ -10661,37 +12091,37 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również WizardPrinter - + Plane Samolot - + Multicopter Multikopter - + Helicopter Śmigłowiec - + Model Name: Nazwa Modelu: - + Model Type: Typ Modelu: - + Options: Opcje: - + Channel %1: Kanał %1: @@ -10867,44 +12297,44 @@ m2560 dla platformy V4 Port szeregowy sam-ba - + DFU-UTIL Configuration Konfiguracja DFU-UTIL - + SAM-BA Configuration Konfiguracja SAM-BA - + AVRDUDE Configuration Konfiguracja AVRDUDE - - - + + + Select Location Wybierz położenie - + List available programmers Lista dostępnych programatorów - + Avrdude help Pomoc dla Averdude - + Companion Companion - + <b><u>WARNING!</u></b><br>Normally CPU type is automatically selected according to the chosen firmware.<br>If you change the CPU type the resulting eeprom could be inconsistent. <b><u>Ostrzeżenie!</u></b><br>Normalnie typ procesora jest wybierany automatycznie zgodnie z wybranym firmware.<br>Jeśli zmienisz typ procesora dla EEpromu rezultaty mogą być nieprzewidywalne. @@ -10961,75 +12391,75 @@ m2560 dla platformy V4 ... - - - - + + + + Error Błąd - + Cannot load the image file %1. Nie mogę załadować pliku obrazka %1. - + Cannot load profile image %1. Nie mogę załadować obrazu Profilu %1. - + Cannot load the library image %1. Nie mogę załadować obrazu biblioteki %1. - + File Saved Plik Zapisany - + The image was saved to the file %1 Obraz został zapisany do pliku %1 - + Image Refresh Error Błąd odświeżenia obrazka - + Failed to refresh image from file %1 Nieudane odświeżenie obrazka z pliku %1 - + File Save Error Błąd zapisu pliku - + Failed to write image to %1 Nieudany zapis obrazka do %1 - + Open Image to load Otwórz obrazek do załadowania - + Open Firmware File Otwórz plik Firmware - + Can not load embedded image from firmware file %1. Nie mogę załadować wbudowanego obrazka z pliku Firmware %1. - + Images (%1) Obrazki (%1) @@ -11042,17 +12472,17 @@ m2560 dla platformy V4 Pobierz: - + Unable to save the file %1: %2. Nie mogę zapisać pliku %1: %2. - + Companion Companion - + Download failed: %1. Pobieranie nieudane: %1. @@ -11065,231 +12495,155 @@ m2560 dla platformy V4 Ustaw joystick - + Ch2 Kanał 02 - - - - - - - - - Not Assigned - Nie przydzielono - - - - - - - - - - - Right Vertical - Prawy pionowy - - - - - - - - - - - Right Horizontal - Prawy poziomy - - - - - - - - - - - Left Vertical - Lewy pionowy - - - - - - - - - - - Left Horizontal - Lewy poziomy - - - - - - - - - - - P1 - Potencjometr 1 - - - - - - - - - - - P2 - Potencjometr 2 - - - - - - - - - - - P3/LS - Potencjometr 3 /Lewy suwak - - - - - - - - - - - RS - Prawy suwak - - - + Ch1 Kanał 01 - + Ch4 Kanał 04 - + Ch6 Kanał 06 - + Ch3 Kanał 03 - + Ch5 Kanał 05 - + Ch7 Kanał 07 - + Ch8 Kanał 08 - + Instructions Instrukcje - + + Enable + + + + Cancel Przerwij - + + Back + + + + + Start + Start + + + Next Następny - + Ok OK - - Move sticks and pots in every direction making full movement -Press next when finished - Poruszaj drążkami i potencjometrami w pełnym możliwym zakresie. -Naciśnij Dalej po wykonaniu + + Not Assigned + - - + + Stick + + + + + Knob/Slider %1 + + + + + No joysticks found + Brak joysticka + + + Error Błąd - + Cannot open joystick. Nie mogę otworzyć joysticka. - + + Press the Start button to start the stick range calibration procedure. +You may change the channel assignments or inversion at any time. + + + + + Move sticks and pots in every direction making full movement +Press Next when finished + + + + Place sticks and pots in middle position. -Press next when done - Ustaw drążki i potencjometry w środku. -Naciśnij Dalej po wykonaniu +Press Next when done + - + Map joystick channels to controls using comboboxes. -Press next when done - Zmapuj kanały joysticka używając pól kombi. -Naciśnij Dalej po wykonaniu +Press Next when done. + - - Check inversion checkbox to get maximum at top-right position. -Press next when done - Sprawdź Pole Wyboru rewersu w celu uzyskania maksimum w górnej prawej pozycji. -Naciśnij Dalej po wykonaniu + + Check inversion checkbox to if necessary to reverse direction. +Press Next when done. + - - Press ok to save configuration -Press cancel to abort joystick calibration - Naciśnij OK w celu zapisu -Anuluj w celu przerwania kalibracji joysticka + + Press OK to save configuration +Press Cancel to abort joystick calibration without saving. + - - Duplicated stick assignment - Zduplikowane przypisanie drążków + + Warning + Ostrzeżenie - - - mdiChild - - Simulate Tx - Symulacja radia + + Calibration not complete, save anyway? + diff --git a/companion/src/translations/companion_sv.ts b/companion/src/translations/companion_sv.ts index 56e6b5141..ce8b77d04 100644 --- a/companion/src/translations/companion_sv.ts +++ b/companion/src/translations/companion_sv.ts @@ -1,6 +1,6 @@ - + AileronsPage @@ -57,10 +57,6 @@ Radio Profile Radioprofil - - Open Folder - Öppna katalog - Default Channel Order Kanalordning @@ -315,10 +311,6 @@ Behöver inte vara samma som menyspråk Files to keep Behåll filer - - Find Executable - Sök Program - Google Earth Executable Sökväg till Google Earth @@ -479,289 +471,15 @@ Behöver inte vara samma som menyspråk Use Companion nightly builds Använd Companions nattliga byggningar - - - Calibration - Form - Form - - - Beeper volume - -0 - Quiet. No beeps at all. -1 - No Keys. Normal beeps but menu keys do not beep. -2 - Normal. -3 - Loud. -4 - Extra loud. - Summervolym - -0 - Tyst. Inga pip alls. -1 - Ej vid knapptryck. Normala pip, men inte vid knapptryckningar. -2 - Normalt. -3 - Högt. -4 - Extra högt. - - - RS - RS - - - SB - SB - - - Serial Port - Serieport - - - OFF - Av - - - S-Port Mirror - Speglad Serieport - - - Telemetry - Telemetri - - - SBUS Trainer - SBUS-Lärare - - - Debug - Debug - - - Rud - Rod - - - Pot. 4 - Pot. 4 - - - Pot. 3 - Pot. 3 - - - Pot. 2 - Pot. 2 - - - Pot. 1 - Pot. 1 - - - PPM 1 - PPM 1 - - - Stick 3 - Spak 3 - - - Negative span - Negativa värden - - - Mid value - Centrumvärde - - - Positive span - Positiva värden - - - Stick 1 - Spak 1 - - - PPM 2 - PPM 2 - - - Stick 2 - Spak 2 - - - Stick 4 - Spak 4 - - - v - v - - - PPM Multiplier - PPM Multiplikator - - - PPM 3 - PPM 3 - - - PPM 4 - PPM 4 - - - S1 - S1 - - - S2 - S2 - - - S3 - S3 - - - SA - SA - - - Ele - Hjd - - - Ail - Ske - - - Thr - Gas - - - SC - SC - - - LS - LS - - - SD - SD - - - SE - SE - - - SF - SF - - - SG - SG - - - SH - SH - - - SI - SI - - - SJ - SJ - - - SK - SK - - - SL - SL - - - SM - SM - - - SN - SN - - - SQ - SQ - - - SR - SR - - - LS2 - LS2 - - - SP - SP - - - SO - SO - - - S4 - S4 - - - RS2 - RS2 - - - Bluetooth - Blåtand - - - Battery Offset + Select Folder - Current Offset + Select Executable - - CalibrationPanel - - None - Ingen - - - 2 Positions Toggle - 2-Läges-brytare - - - 2 Positions - 2 Lägen - - - 3 Positions - 3 Lägen - - - Pot with detent - Ratt med mittklick - - - Multipos switch - Flerlägesväljare - - - Pot without detent - Ratt utan mittklick - - - Slider with detent - Skjutpot med mittklick - - Channels @@ -796,10 +514,6 @@ Behöver inte vara samma som menyspråk Linear Subtrim Linjärt Subtrim - - Channel %1 - Kanal %1 - --- ---- @@ -808,6 +522,21 @@ Behöver inte vara samma som menyspråk INV INV + + CH%1 + KN%1 + + + + CompanionMacros + + files + + + + Radio and Models settings + + CompareDialog @@ -1147,6 +876,67 @@ Behöver inte vara samma som menyspråk Debug Output Debugutgång + + <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> + + + + Filter: + + + + <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> +To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> + + + + Buffer: + + + + Number of lines to keep in display. + + + + Filter &Help + + + + Show information about using the filter. + + + + Word &Wrap + + + + Toggle word wrapping on/off. + + + + &Clear + + + + Clear the output window of all text. + + + + Enable &Filter + + + + Turn the filter on/off. + + + + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> + + + + Debug Console Filter Help + + EepromInterface @@ -1324,6 +1114,22 @@ Om fältet lämnas tomt så är raden aktivt hela tiden. Edit %1 Redigera %1 + + Click to access popup menu + + + + Clear All + + + + Set All + + + + Invert All + + FblPage @@ -1466,26 +1272,6 @@ Behöver inte vara samma som menyspråk Error Fel - - Unable to find file %1! - Kan inte hitta filen %1 ! - - - Error opening file %1: -%2. - Fel vid öppning av filen %1: -%2. - - - Invalid Models and Settings File %1 - Filen innehåller inte Modeller och Inställningar: %1 - - - Error reading file %1: -%2. - Fel vid inläsning från filen %1: -%2. - Warning Varning @@ -1523,8 +1309,8 @@ Behöver inte vara samma som menyspråk Det går inte att verifiera att Modeller och Inställningar är kompatibla. Fortsätt i alla fall? - Invalid Models and Settings file %1 - Filen innehåller inte Modeller och Inställningar: %1 + <html><head/><body><p>Saves a dated copy of your eeprom to the backup folder you specified in the Companion settings before writing the current model to the radio.</p></body></html> + @@ -1790,6 +1576,30 @@ Använd Zadig för att installera drivrutinen. Popup enabled Popup aktiv + + Name + Namn + + + Value source + + + + Value + Värde + + + &Clear + + + + Clear + Ta Bort + + + Clear all current Flight Mode properties? + + FlightModesPanel @@ -1964,10 +1774,6 @@ p, li { white-space: pre-wrap; } GeneralEdit - - General Edit - Allmänna inställningar - General settings used throught the transmitter. These will be relevant for all models in the same EEPROM. @@ -2015,8 +1821,20 @@ Dessa inställningar gäller för alla modeller. Globala Funktioner - Hardware / Calibration - Hårdvara / Kalibrering + Radio settings + + + + Hardware + + + + Calibration + + + + Wrong data in profile, Switch/pot config not retrieved + @@ -2037,7 +1855,7 @@ Dessa inställningar gäller för alla modeller. Measurement Units Måttenheter - + hh° (N/S) mm' ss''.dd hh° (N/S) mm' ss''.dd @@ -2662,6 +2480,14 @@ brytare Battery Meter Range Batterimätarens Mätområde + + Automatically adjust the radio's clock if a GPS is connected to telemetry. + + + + Backlight OFF Brightness + + GeneralSetupPanel @@ -2689,6 +2515,248 @@ FAI-funktionen kan inte slås av i sändaren. Ja, styrd via en potentiometer + + Hardware + + Form + Form + + + SQ + SQ + + + SR + SR + + + LS2 + LS2 + + + SP + SP + + + SO + SO + + + S4 + S4 + + + RS + RS + + + SB + SB + + + PPM 2 + PPM 2 + + + Beeper volume + +0 - Quiet. No beeps at all. +1 - No Keys. Normal beeps but menu keys do not beep. +2 - Normal. +3 - Loud. +4 - Extra loud. + Summervolym + +0 - Tyst. Inga pip alls. +1 - Ej vid knapptryck. Normala pip, men inte vid knapptryckningar. +2 - Normalt. +3 - Högt. +4 - Extra högt. + + + OFF + Av + + + S-Port Mirror + Speglad Serieport + + + Telemetry + Telemetri + + + SBUS Trainer + SBUS-Lärare + + + Debug + Debug + + + Rud + Rod + + + PPM 3 + PPM 3 + + + S1 + S1 + + + S2 + S2 + + + S3 + S3 + + + PPM 1 + PPM 1 + + + Serial Port + Serieport + + + v + v + + + PPM Multiplier + PPM Multiplikator + + + Current Offset + + + + PPM 4 + PPM 4 + + + SA + SA + + + Ele + Hjd + + + Ail + Ske + + + Thr + Gas + + + SC + SC + + + LS + LS + + + SD + SD + + + Battery Offset + + + + SE + SE + + + SF + SF + + + SG + SG + + + SH + SH + + + SI + SI + + + SJ + SJ + + + SK + SK + + + SL + SL + + + SM + SM + + + SN + SN + + + RS2 + RS2 + + + Bluetooth + Blåtand + + + ADC Filter + + + + + HardwarePanel + + None + Ingen + + + 2 Positions Toggle + 2-Läges-brytare + + + 2 Positions + 2 Lägen + + + 3 Positions + 3 Lägen + + + Pot with detent + Ratt med mittklick + + + Multipos switch + Flerlägesväljare + + + Pot without detent + Ratt utan mittklick + + + Slider with detent + Skjutpot med mittklick + + Heli @@ -2929,8 +2997,8 @@ FAI-funktionen kan inte slås av i sändaren. Ctrl+V - (no release) - (release saknas) + (instant) + @@ -3055,6 +3123,22 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt (R2) (R2) + + Cursor A: %1 m + + + + Cursor B: %1 m + + + + Time delta: %1 + + + + Climb rate: %1 m/s + + MainWindow @@ -3110,10 +3194,6 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt System language Systemspråk - - Use system language in menus - Använd systemspråket i menyerna - Print current model Skriv ut modell @@ -3248,10 +3328,6 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt Fel vid öppning av filen %1: %2. - - Compilation server termporary failure, try later - Tillfälligt fel i byggservern. Försök igen senare - Compilation server too busy, try later Byggservern är upptagen. Försök igen senare @@ -3268,10 +3344,6 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt A new release of Companion is available, please check the OpenTX website! En ny version av Companion finns tillgänglig. Var god kontrollera OpenTX webbsida! - - Not enough memory for all the selected firmware options - Firmware får inte plats i radion eftersom alltför många funktioner är valda samtidigt - Alt+S Alt+S @@ -3365,10 +3437,6 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt A new version of Companion is available (version %1)<br>Would you like to download it? An ny version av Companion finns tillgänglig (version %1)<br>Vill du ladda ned den? - - Compilation server requires registration, please check OpenTX web site - Byggservern kräver registrering. Var god kontrollera OpenTX webbsida - No Nej @@ -3381,10 +3449,6 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt Do you want to download release %1 now ? Vill du ladda ned firmware %1 nu ? - - The selected language will be used the next time you start Companion. - Språket som valts kommer att användas nästa gång Companion startas. - The new theme will be loaded the next time you start Companion. De nya ikonerna kommer att användas nästa gång Companion startas. @@ -3509,70 +3573,6 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt Huge Mycket Stor - - Czech - Czeckiska - - - Use Czech in menus - Använd Tjeckiska i menyerna - - - German - Tyska - - - Use German in menus - Använd Tyska i menyerna - - - English - Engelska - - - Use English in menus - Använd Engelska i menyerna - - - Finnish - Finska - - - Use Finnish in menus - Använd Finska i menyerna - - - French - Franska - - - Use French in menus - Använd Franska i menyerna - - - Italian - Italienska - - - Use Italian in menus - Använd Italienska i menyerna - - - Polish - Polska - - - Use Polish in menus - Använd Polska i menyerna - - - Swedish - Svenska - - - Use Swedish in menus - Använd Svenska i menyerna - About... Om... @@ -3713,14 +3713,6 @@ Vill du ladda ned den nya versionen nu? Vi rekommenderar att du använder knappen nedan för att ta del av de senaste förändringarna och bedöma om de är viktiga för dig. - - Spanish - Spanska - - - Use Spanish in menus - Använd Spanska i menyerna - Companion Companion @@ -3729,6 +3721,50 @@ Vi rekommenderar att du använder knappen nedan för att ta del av de senaste f OpenTX Companion %1 - Radio: %2 - Profile: %3 OpenTX Companion %1 - Radio: %2 - Profil: %3 + + Not enough flash available on this board for all the selected options + + + + Compilation server temporary failure, try later + + + + Compilation error + + + + Invalid firmware + + + + Invalid board + + + + Invalid language + + + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + + + + Models and Settings read + + + + This function is not yet implemented + + + + Use default system language. + + + + Use %1 language (some translations may not be complete). + + MdiChild @@ -3760,30 +3796,10 @@ Vi rekommenderar att du använder knappen nedan för att ta del av de senaste f Save As Spara som - - Cannot write file %1: -%2. - Filen %1 kunde inte skrivas: -%2. - - - Error writing file %1: -%2. - Fel vid skrivning av filen %1: -%2. - free bytes bytes lediga - - Invalid EEPROM File %1 - Ogiltig modelldatafil %1 - - - Invalid binary EEPROM File %1 - Ogiltig binär modelldatafil %1 - %1 has been modified. Do you want to save your changes? @@ -3810,6 +3826,144 @@ Vill du spara förändringarna? Invalid binary backup File %1 Den binära backupfilen är felaktig %1 + + Radio settings + + + + Simulate Tx + Simulera sändare + + + Delete selected models? + + + + Cannot delete default model. + Det går inte att ta bort standard-modellen. + + + &Edit + &Redigera + + + &Restore from backup + &Återställ från säkerhetskopia + + + &Model Wizard + &Modellguide + + + &Delete + + + + Delete + Ta bort + + + &Copy + &Kopiera + + + Ctrl+C + Ctrl+C + + + &Cut + Klipp &Ut + + + Ctrl+X + Ctrl+X + + + &Paste + Klistra &In + + + Ctrl+V + Ctrl+V + + + D&uplicate + &Duplicera + + + Ctrl+U + Ctrl+U + + + Move to Category + + + + &Use as default + A&nvänd som standard + + + P&rint model + Skriv &ut modell + + + Ctrl+P + Ctrl+P + + + &Simulate model + S&imulera modell + + + Alt+S + Alt+S + + + &Add model + + + + &Rename category + + + + &Delete category + + + + &Add category + + + + Models and settings will be automatically converted. +If that is not what you intended, please close the file +and choose the correct radio type/profile before reopening it. + + + + Do you want to overwrite radio general settings? + Vill du skriva över radioinställningarna? + + + You are pasting on an not empty model, are you sure? + Du skriver över en modell som redan har inställningar. Är du säker? + + + This category is not empty! + + + + New model + + + + Unable to find Horus radio SD card! + + + + Models and Settings written + + MixerDialog @@ -3982,6 +4136,22 @@ p, li { white-space: pre-wrap; } <p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Om Tröghet inte är noll kommer hastigheten i förändringar att begränsas av det angivna värdet -&gt; värdet specificerar det antal sekunder det tar att gå från fullt negativt utslag (-100) till fullt positivt utslag(100).</p></body></html> + + Click to access popup menu + + + + Clear All + + + + Set All + + + + Invert All + + MixesPanel @@ -4149,15 +4319,15 @@ p, li { white-space: pre-wrap; } Exponential - + Exponentiella Extra Fine - + Extrafina Fine - + Fina Medium @@ -4165,7 +4335,7 @@ p, li { white-space: pre-wrap; } Coarse - + Grova Unknown @@ -4355,6 +4525,30 @@ p, li { white-space: pre-wrap; } Slow(u%1:d%2) + + radio Protocol %1, subType %2, option value %3 + + + + 90 + 90 + + + 120 + 120 + + + 120X + 120X + + + 140 + 140 + + + instant + + ModelSelectionPage @@ -4381,107 +4575,10 @@ p, li { white-space: pre-wrap; } ModelsListWidget - - &Edit - &Redigera - - - &Delete - Ta &Bort - - - Delete - Ta bort - - - &Copy - &Kopiera - - - Ctrl+C - Ctrl+C - - - &Cut - Klipp &Ut - - - Ctrl+X - Ctrl+X - - - &Paste - Klistra &In - - - Ctrl+V - Ctrl+V - - - D&uplicate - &Duplicera - - - Ctrl+U - Ctrl+U - - - &Use as default - A&nvänd som standard - - - P&rint model - Skriv &ut modell - - - Alt+S - Alt+S - - - &Simulate model - S&imulera modell - - - General Settings - Sändarens inställningar - - - Delete Selected Models? - Radera valda modeller? - - - Do you want to overwrite radio general settings? - Vill du skriva över radioinställningarna? - - - You are pasting on an not empty model, are you sure? - You are pasting on an not empty model, are you sure ? - Du skriver över en modell som redan har inställningar. Är du säker? - No free slot available, cannot duplicate Det finns ingen ledig plats för en kopia - - &Restore from backup - &Återställ från säkerhetskopia - - - &Model Wizard - &Modellguide - - - Ctrl+P - Ctrl+P - - - Cannot delete default model. - Det går inte att ta bort standard-modellen. - - - Cannot cut default model. - Det går inte att klippa ut standard-modellen. - Module @@ -4597,6 +4694,52 @@ p, li { white-space: pre-wrap; } Push Pull + + SubType + + + + Antenna + + + + Internal + + + + Ext. + Int. + + + + Option value + + + + Bind on startup + + + + Low Power + + + + Multi Radio Protocol + + + + Show values in: + + + + % + abbreviation for percent + % + + + μs + abbreviation for microseconds + + ModulePanel @@ -4795,6 +4938,81 @@ p, li { white-space: pre-wrap; } RSSI Alarms + + Helicopter Setup + + + + Swash Type: + + + + Swash Ring: + + + + Input + Indata + + + Weight + Vikt + + + Long. cyc + Long. cyc + + + Lateral cyc + Lateral cyc + + + Collective + Collective + + + Low Alarm + Låg Alarmnivå + + + Critical Alarm + Kritisk Alarmnivå + + + + Multiprotocols + + Subtype + + + + Video TX frequency + + + + C2500 frequency fine tune + + + + Telemetry + Telemetri + + + Radio output power + + + + Servo output frequency + + + + Option value + + + + DEFAULT + + MultirotorPage @@ -4917,11 +5135,11 @@ p, li { white-space: pre-wrap; } m m - + °C °C - + ° ° @@ -5001,10 +5219,6 @@ p, li { white-space: pre-wrap; } Play Sound Spela ljud - - Start Logs - Starta loggning - ---- ---- @@ -5037,10 +5251,6 @@ p, li { white-space: pre-wrap; } Warning Varning - - EEPROM saved with these warnings: - Modelldata sparades, men med dessa varningar: - Simulator for this firmware is not yet available Det finns ännu ingen simulator för denna typ av firmware @@ -5113,10 +5323,6 @@ p, li { white-space: pre-wrap; } OFF Av - - th9x on this board doesn't have Rotary Encoders - th9x stödjer inte inställningshjul för detta sändarkort - TrmR TrmR @@ -5253,10 +5459,6 @@ p, li { white-space: pre-wrap; } Keys + Sticks Knappar + Spakar - - Simultaneous usage of expo and curves is no longer supported - Expo och pspecialkurva kan inte längre kombineras - Support for frsky telemetry mod Stöd för FrSky telemeri @@ -5305,10 +5507,6 @@ p, li { white-space: pre-wrap; } Channel values displayed in us Kanal-värden visade i us - - (displaying only first 10 warnings) - (enbart de 10 första varningarna visas) - In model setup menus automatically set source by moving the control Välj automatisk kontroller i menyn för modelinställningar genom att använda dem @@ -5517,126 +5715,6 @@ p, li { white-space: pre-wrap; } L2 LB2 - - L3 - LB3 - - - L4 - LB4 - - - L5 - LB5 - - - L6 - LB6 - - - L7 - LB7 - - - L8 - LB8 - - - L9 - LB9 - - - L10 - LB10 - - - L11 - LB11 - - - L12 - LB12 - - - L13 - LB13 - - - L14 - LB14 - - - L15 - LB15 - - - L16 - LB16 - - - L17 - LB17 - - - L18 - LB18 - - - L19 - LB19 - - - L20 - LB20 - - - L21 - LB21 - - - L22 - LB22 - - - L23 - LB23 - - - L24 - LB24 - - - L25 - LB25 - - - L26 - LB26 - - - L27 - LB27 - - - L28 - LB28 - - - L29 - LB29 - - - L30 - LB30 - - - L31 - LB31 - - - L32 - LB32 - [I%1] [I%1] @@ -5677,30 +5755,6 @@ p, li { white-space: pre-wrap; } FM8 FM8 - - S31 - S31 - - - S32 - S32 - - - S33 - S33 - - - S34 - S34 - - - S35 - S35 - - - S36 - S36 - RudTrim Left RoderTrim Vänster @@ -5925,54 +5979,6 @@ p, li { white-space: pre-wrap; } SWR SWR - - S11 - S11 - - - S12 - S12 - - - S13 - S13 - - - S14 - S14 - - - S15 - S15 - - - S16 - S16 - - - S21 - S21 - - - S22 - S22 - - - S23 - S23 - - - S24 - S24 - - - S25 - S25 - - - S26 - S26 - Diff(%1) Diff(%1) @@ -6025,10 +6031,6 @@ p, li { white-space: pre-wrap; } Portuguese Portugisiska - - Finnish - Finska - !Flight mode %1 !Flygläge %1 @@ -6145,10 +6147,6 @@ p, li { white-space: pre-wrap; } Profile image Profilbild - - Simultaneous usage of expo and curves is no longer supported in OpenTX - Det går inte att använda Expo på en specialkurva i OpenTX - Thank you for upgrading to OpenTX 2.0. This is a major upgrade that adds and modifies a lot of things, so please make sure that you read release notes carefully to learn about the changes, and thoroughly check each of your models for proper function. @@ -6313,10 +6311,6 @@ OpenTX-gruppen. ST7565R LCD or compatible ST7565R LCD eller kompatibel - - Adds mixers output view to the CHANNELS MONITOR screen, pressing [ENT] switches between the views - Lägger till mixerutdata-vy till KANALER-skärmen, tryck [ENT] för at växla mellan vyerna - Synchronization error Synkroniseringsfel @@ -6395,10 +6389,6 @@ OpenTX-gruppen. Power management by soft-off circuitry Strömbrytare styrd av mjukvara - - Support for a third timer - Stöd för en tredje timer - Support for PPM internal module hack Stöd för hårdvaruhack med intern PPM-modul @@ -6411,7 +6401,7 @@ OpenTX-gruppen. Flight Flygning - + °F °F @@ -6419,62 +6409,10 @@ OpenTX-gruppen. DISABLED INAKTIV - - Removes D8 and LR12 FrSky protocols that are not legal for use in the EU on radios sold after Jan 1st, 2015 - Ta bort FrSkys radioprotokoll D8 och R12,l som inte är lagliga i EU för sändare sålda efter 2015-01-01 - - - 9X board - 9X-kort - - - M128 / 9X board - M128 / 9X kort - - - 9XR - 9XR - - - 9XR with M128 chip - 9XR med M128-CPU - - - Gruvin9x board / 9X - 9X med Gruvin9X-kort - - - MEGA2560 board - MEGA2560-kort - - - Sky9x board / 9X - 9X med Sky9X-kort - - - 9XR-PRO - 9XR-PRO - - - FrSky Taranis - FrSky Taranis - - - FrSky Taranis Plus - FrSky Taranis Plus - FrSky Taranis X9E FrSky Taranis X9E - - Radio type - Radiotyp - - - Which radio type do you want to simulate? - Vilken typ av radio vill du simulera? - INV INV @@ -6495,10 +6433,6 @@ OpenTX-gruppen. Instead of Joystick emulation, USB connection is Command Line Interface - - ar9x board / 9X - - SetFailsafe Int. Module @@ -6531,6 +6465,548 @@ OpenTX-gruppen. repeat(%1s) + + Left Horizontal + Vänster Horisontal + + + Left Vertical + Vänster Vertikal + + + Right Vertical + Höger Vertikal + + + Right Horizontal + Höger Horisontal + + + Aux. 1 + + + + Aux. 2 + + + + Conversion error on field %1 + + + + mW + + + + Rad + + + + Trm5 + + + + Trm6 + + + + L%1 + LB%1 + + + Trim 5 Down + + + + Trim 5 Up + + + + Trim 6 Down + + + + Trim 6 Up + + + + SD Logs + + + + Switch + Brytare + + + Switch + + + + cannot be exported on this board! + + + + Unknown error + + + + ... plus %1 errors + + + + Cannot write radio settings + + + + Cannot write model %1 + + + + 6P + 6P + + + JSx + + + + JSy + + + + Support for the DIY-Multiprotocol-TX-Module + + + + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 + + + + Enable Lua compiler + + + + KS108 LCD + + + + WTV20 voice module + + + + JQ6500 voice module + + + + FrSky Taranis X9D+ + + + + FrSky Taranis X9D + FrSky Taranis X9E {9D?} + + + Horus gimbals installed (Hall sensors) + + + + FrSky Taranis X7 + FrSky Taranis X9E {7?} + + + FrSky Horus + + + + Use ONLY with first DEV pcb version + + + + Turnigy 9XR-PRO + + + + Turnigy 9XR with m128 chip + + + + Turnigy 9XR + + + + 9X with stock board + + + + 9X with stock board and m128 chip + + + + 9X with AR9X board + + + + 9X with Sky9x board + + + + 9X with Gruvin9x board + + + + DIY MEGA2560 radio + + + + Negative span + Negativa värden + + + Mid value + Centrumvärde + + + Positive span + Positiva värden + + + Dutch + + + + Hungarian + + + + -GV%1 (%2) + + + + GV%1 (%2) + + + + Uknown error during Simulator startup. + + + + Simulator Error + + + + Data Load Error + + + + Error occurred while starting simulator. + + + + Models + Translators do NOT use accent for this, this is the default category name on Horus. + + + + Positive + Positiv + + + Negative + Negativ + + + Unable to find Horus radio SD card! + + + + Select a data file + + + + Select Data Directory + + + + Select SD Card Image Folder + + + + Available profiles: + + + + ID: + + + + Name: + + + + Available radios: + + + + WARNING: couldn't initialize SDL: +%1 + + + + ERROR: No simulator libraries available. + + + + Radio profile ID or Name to use for simulator. + + + + Radio type to simulate (usually defined in profile). + + + + show this help text + + + + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] + + + + Options: + + + + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. + Profile ID: [%1]; Radio ID: [%2]; +Data File: [%3] + + + + ERROR: Radio profile or simulator firmware not found. +Profile ID: [%1]; Radio ID: [%2] + + + + Error reading %1: %2 + + + + Cannot save EEPROM + + + + Cannot open file %1: +%2. + + + + Error writing file %1: +%2. + Fel vid skrivning av filen %1: +%2. + + + Invalid binary EEPROM file %1 + + + + Can't extract RADIO/radio.bin + + + + Can't extract RADIO/models.txt + + + + Can't extract %1 + + + + Unable to open %1: %2 + + + + Invalid EEPROM file %1 + + + + Invalid EEPROM File %1 + Ogiltig modelldatafil %1 + + + Error opening file %1: +%2. + Fel vid öppning av filen %1: +%2. + + + Error opening OTX archive %1 + + + + Error initializing OTX archive writer + + + + Error creating OTX file %1: +%2. + + + + Error creating OTX archive + + + + Error adding %1 to OTX archive + + + + Error opening file %1 in write mode: +%2. + + + + Unable to find file %1! + Kan inte hitta filen %1 ! + + + + QxtCommandOptions + + sets the application GUI style + + + + sets the application stylesheet + + + + restores the application from an earlier session + + + + displays debugging information about widgets + + + + use right-to-left layout + + + + never grab the mouse or keyboard + + + + grab the mouse/keyboard even in a debugger + + + + run in synchronous mode for debugging + + + + use Direct3D by default + + + + sets the X11 display + + + + sets the geometry of the first window + + + + sets the default font + + + + sets the default background color + + + + sets the default foreground color + + + + sets the default button color + + + + sets the application name + + + + sets the application title + + + + sets the X11 visual type + + + + limit the number of colors on an 8-bit display + + + + use a private color map + + + + sets the input method server + + + + disable the X Input Method + + + + sets the style used by the input method + + + + option "%1" not found + + + + Short options cannot have optional parameters + + + + positional() called before parse() + + + + unrecognized() called before parse() + + + + count() called before parse() + + + + value() called before parse() + + + + parameters() called before parse() + + + + unrecognized parameters: + + + + %1 requires a parameter + + + + + RadioKnobWidget + + Right-double-click to reset to center. + + RadioNotFoundDialog @@ -6547,6 +7023,83 @@ OpenTX-gruppen. <html><head/><body><p>Ingen radio hittades!</p><p>Se till att du håller de båda nedre trimknappana mot centrum när du slår på radion.</p><p>Anslut sedan USB-kabeln.</p><p><span style=" font-family:'arial,sans-serif'; font-size:13px; font-style:italic; color:#222222; background-color:#ffffff;">OBS: Denna version av Companion kräver att programvaran i din Taranis är av version 2.0 eller senare. Programmet fungerar INTE med Taranis-sändare med äldre programvaruversioner.</span></p></body></html> + + RadioOutputsWidget + + Form + Form + + + View: + + + + Logical Switches + Logiska Brytare + + + Global Variables + Globala Variabler + + + Channel Outputs + + + + L +o +g +i +c + + + + G +l +o +b +a +l + + + + C +h +a +n +n +e +l +s + + + + + RadioSwitchWidget + + Latch/unlatch the momentary switch. + + + + + RawSwitch + + ↑ + + + + ↓ + + + + - + + + + ! + + + ReleaseNotesDialog @@ -6728,128 +7281,679 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga - SimulatorDialog + SimulatedUIWidget - Warning - Varning + Rotary encoder click + - Joystick enabled but not configured correctly - Joysticken påslagen, men ej rätt inställd + Take Screenshot + + + + screenshot + Simulator LCD screenshot file name prefix + + + + + SimulatedUIWidget9X + + UP/PG-UP + + + + [ UP ] + + + + DN/PG-DN + + + + [ DN ] + + + + RIGHT/+ + + + + [ + ] + + + + LEFT/- + + + + [ - ] + + + + ENTER/MOUSE-MID + + + + [ MENU ] + + + + DEL/BKSP/ESC + + + + [ EXIT ] + + + + WHEEL/PAD SCRL + + + + [ UP ]/[ DN ] or Rotary Sel. + + + + + SimulatedUIWidgetX12 + + PG-UP + + + + [ PgUp ] + + + + PG-DN + + + + [ PgDn ] + + + + UP + + + + [ MDL ] + + + + DN/DEL/BKSP + + + + [ RTN ] + + + + LEFT + + + + [ SYS ] + + + + RIGHT + + + + [ TELE ] + + + + WHEEL/PAD SCRL + + + + Rotary Selector + + + + -/X + + + + Rotary UP + + + + +/C + + + + Rotary DOWN + + + + ENTER/MOUSE-MID + + + + Selector Press + + + + + SimulatedUIWidgetX7 + + Taranis X7 Simulator + + + + PG-UP + + + + [ PAGE ] + + + + PG-DN + + + + [ MENU ] + + + + DEL/BKSP/ESC + + + + [ EXIT ] + + + + WHEEL/PAD SCRL + + + + Rotary Selector + + + + -/UP + + + + Rotary UP + + + + +/DN + + + + Rotary DOWN + + + + ENTER/MOUSE-MID + + + + Selector Press + + + + + SimulatedUIWidgetX9 + + PG-UP + + + + [ MENU ] + + + + PG-DN + + + + [ PAGE ] + + + + DEL/BKSP/ESC + + + + [ EXIT ] + + + + +/UP + + + + [ + ] + + + + -/DN + + + + [ - ] + + + + ENTER/MOUSE-MID + + + + [ ENT ] + + + + WHEEL/PAD SCRL + + + + [ + ]/[ - ] + + + + + SimulatedUIWidgetX9E + + PG-UP + + + + [ MENU ] + + + + PG-DN + + + + [ PAGE ] + + + + DEL/BKSP/ESC + + + + [ EXIT ] + + + + WHEEL/PAD SCRL + + + + Rotary Selector + + + + -/UP + + + + Rotary UP + + + + +/DN + + + + Rotary DOWN + + + + ENTER/MOUSE-MID + + + + Selector Press + + + + + SimulatorMainWindow + + OpenTx Simulator + + + + View + + + + Radio Window + + + + Reload... + + + + Tools + + + + Toolbar + + + + Reload Lua Scripts + + + + Reload the Lua environment on the simulated radio. + + + + F7 + F7 + + + Reload Radio Data + + + + Reload all radio data without restarting the simulator. + + + + F9 + F9 + + + Key Mapping + + + + Show keyboard maping reference. + + + + F1 + F1 + + + Joystick Settings + + + + Open joystick configuration settings dialog. + + + + F3 + F3 + + + LCD Screenshot + + + + Save a screenshot of the current simulated LCD screen. + + + + F8 + F8 + + + Dock In Main Window + + + + Show the radio in the main window or as a separate "floating" window. + + + + Menu Bar + + + + Show or hide the top menu bar. + + + + Alt+M + + + + Constrain Width + + + + Set radio widget width to be a fixed size. + + + + Constrain Height + + + + Set radio widget height to be a fixed size. + + + + ERROR: Failed to create simulator interface, possibly missing or bad library. + + + + Alt+T + + + + Radio Outputs + + + + F2 + F2 + + + Telemetry Simulator + Telemetri-simulator + + + F4 + F4 + + + Trainer Simulator + + + + F5 + F5 + + + Debug Output + Debugutgång + + + F6 + F6 + + + Simulator Controls: + + + + <tr><th>Key/Mouse</td><th>Action</td></tr> + + + + Simulator Help + + + + + SimulatorStartupDialog + + OpenTX Simulator - Startup Options + + + + Simulator Startup Options: + + + + Radio Profile: + + + + Existing radio profiles are shown here.<br /> +Create or edit profiles using the Companion application. + + + + Radio Type: + + + + Existing radio simulators are shown here.<br /> +The radio type specified in the selected profile is used by default. + + + + Data Source: + + + + Data File: + + + + Data Folder: + + + + SD Image Path: + + + + Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> +<b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! + + + + Select data file... + + + + ... + ... + + + Directory containing RADIO and MODELS folders to use.<br /> +New folder(s) with default radio/model will be created here if necessary. + + + + Select data folder... + + + + Directory containing the SD card image to use.<br/> +The default is configured in the chosen Radio Profile. + + + + Select SD card image folder... + + + + Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. + + + + File + Arkiv + + + Folder + + + + SD Path + + + + All files (*.*) + + + + + SimulatorWidget + + Companion Simulator + Companion Simulator + + + Radio Simulator (%1) + + + + Could not determine startup data source. + + + + Could not load data, possibly wrong format. + + + + Data Load Error + + + + Invalid startup data provided. Plese specify a proper file/path. + + + + Simulator Startup Error + + + + Error saving data: could open file for writing: '%1' + + + + Error saving data: could not get data from simulator interface. + + + + An unexpected error occurred while attempting to save radio data to file '%1'. + + + + Data Save Error + + + + Warning + Varning Cannot open joystick, joystick disabled - Joysticken kan inte hittas. Joysticken stängs av - - - Simulating Radio (%1) - Simulerar Radio (%1) - - - Outputs - Utgångar + Joysticken kan inte hittas. Joysticken stängs av Firmware %1 error: %2 - Firmware %1 fel: %2 + Firmware %1 fel: %2 - SimulatorDialog9X + SliderWidget - Companion Simulator - Companion Simulator - - - Right Double Click to Reset - Höger dubbelklick nollställer - - - Hold X - Håll X - - - Fix X - Fixera X - - - Fix Y - Fixera Y - - - Hold Y - Håll Y - - - Outputs2 - Outputs2 - - - Gvars - Gvars - - - BEEP - Summer - - - 9x Simulator - Simulator för 9x - - - Outputs - Utgångar - - - - SimulatorDialogTaranis - - Companion Simulator - Companion Simulator - - - Outputs2 - Outputs2 - - - Gvars - Gvars - - - Hold Y - Håll Y - - - Fix Y - Fixera Y - - - Fix X - Fixera X - - - Hold X - Håll X - - - Right Double Click to Reset - Höger dubbelklick nollställer - - - Taranis Simulator - Taranissimulator - - - Outputs - Utgångar - - - S3 - S3 - - - S4 - S4 + Right-double-click to reset to center. + @@ -6892,24 +7996,22 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga Create directory %1 Skapa folder %1 - - - - Copy %1 to %2 - - Kopiera %1 till %2 - - - - Write %1 - - Skriv %1 %1/%2 files + + Copy %1 to %2 + Kopiera %1 till %2 + {1 ?} {2?} + + + Write %1 + Skriv %1 + {1?} + TailPage @@ -7158,7 +8260,7 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga Meters (m or ft) Meter (m eller ft) - + Temp (°) Temp (°) @@ -7455,11 +8557,11 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga ft ft - + °C °C - + °F °F @@ -7483,7 +8585,7 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga g g - + ° ° @@ -7495,6 +8597,14 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga US fl.Oz. + + mW + + + + Rad + + TelemetrySensorPanel @@ -7533,118 +8643,14 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga SWR SWR - - simulate - simulera - A2 A2 - - Vario Altitude - Variohöjd - - - V-ALT - V-ALT - - - Vario Vertical Speed - Vertikal hastighet från vario - - - V-VSPD - V-VSPD - - - ACCZ - ACCZ - - - GPS Time - GPS-tid - - - GPS-T - GPS-T - - - ACCX - ACCX - - - GPS Lat/Lon - - - - GPS-LL - GPS-LL - VFAS VFAS - - FAS-V - FAS-V - - - GPS Speed - GPS-hastighet - - - GPS-S - GPS-S - - - CELLS - CELLS - - - ACCY - ACCY - - - GPS Course - GPS-kurs - - - GPS-C - GPS-C - - - GPS Altitude - GPS Höjd - - - GPS-A - GPS-A - - - CURRENT - CURRENT - - - FAS-C - FAS-C - - - 30 - 30 - - - 75 - 75 - - - FR_ID_AIR_SPEED - - - - ASPD - ASPD - A3 A3 @@ -7653,45 +8659,347 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga A4 A4 - - Temperature 1 - Temperatur 1 - - - T1 - T1 - - - Temperature 2 - Temperatur 2 - - - T2 - T2 - RPM RPM - - FUEL - FUEL - When enabled, sends any non-blank values as simulated telemetry data. - <html><head/><body><p>Start with <span style=" font-style:italic;">0x</span> for hex, <span style=" font-style:italic;">0</span> for octal, otherwise decimal.<br/>Numeric entry only. Blank values are not sent.</p></body></html> - <html><head/><body><p>Inled hextal med <span style=" font-style:italic;">0x</span>. Inled octaltal med <span style=" font-style:italic;">0</span>. Alla andra tal antas vara decimala.<br/>Enbart numeriska tecken. Tomma tal skickas ej.</p></body></html> + Simulate + Simulera - Instance - Instans + Replay SD Log File + - 2 - 2 + Replay rate + + + + Load + + + + |> + + + + <| + + + + > + > + + + <- + + + + X + X + + + Row # +Timestamp + + + + 1/5x + 1/5x + + + 5x + 5x + + + No Log File Currently Loaded + + + + V / ratio + + + + Db + + + + RxBt + + + + <html><head/><body><p><br/></p></body></html> + + + + Tmp1 + + + + Tmp2 + + + + Fuel + Tank + + + °C + °C + + + ml + + + + Deg. C + + + + % + % + + + Meters + + + + Alt + Höj + + + VSpd + VHastighet + + + m/s + m/s + + + Fuel Qty + + + + km/h + km/h + + + Hdg + + + + ASpd + + + + G + + + + GPS + + + + Lat,Lon +(dec.deg.) + + + + AccX + AccX + + + dd-MM-yyyy +hh:mm:ss + + + + Date + + + + Amps + + + + AccZ + AccZ + + + GAlt + + + + Volts + + + + Cels + + + + Curr + Ström + + + AccY + AccY + + + GSpd + + + + Degrees + + + + Log File + + + + LOG Files (*.csv) + + + + ERROR - invalid file + + + + + Templates + + Simple 4-CH + + + + T-Cut + + + + Sticky T-Cut + + + + V-Tail + V-stjärt + + + Elevon\Delta + + + + Heli Setup + + + + Heli Setup with gyro gain control + + + + Gyro gain control + + + + Heli Setup (Futaba's channel assignment style) + + + + Heli Setup with gyro gain control (Futaba's channel assignment style) + + + + Gyro gain control (Futaba's channel assignment style) + + + + Servo Test + + + + MultiCopter + + + + Use Model Config Wizard + + + + Apply Template? + + + + Apply template "%1"? + + + + RUD + + + + ELE + + + + THR + GAS + + + AIL + + + + AIL2 + + + + ELE2 + + + + FLAPS + + + + FLAP%1 + + + + PITCH + + + + GYRO + + + + SPOIL + + + + SPOIL%1 + + + + RUD2 + + + + Clear Mixes? + Ta bort mixarna? + + + Really clear existing mixes on CH6? + + + + Really clear existing mixes on CH5? + @@ -7837,6 +9145,21 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga Trainer-simulator + + TreeModel + + Index + + + + Name + Namn + + + Size + + + VTailPage @@ -7848,6 +9171,41 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga Andra stjärtkanalen: + + VirtualJoystickWidget + + Hld Y + + + + Hold Vertical stick position. + + + + Fix Y + Fixera Y + + + Prevent Vertical movement of stick. + + + + Fix X + Fixera X + + + Prevent Horizontal movement of stick. + + + + Hld X + + + + Hold Horizontal stick position. + + + WingtypeSelectionPage @@ -8383,34 +9741,6 @@ m2560 för v4.1-kort Ch2 Kn2 - - Not Assigned - Ej tilldelad - - - Right Vertical - Höger Vertikal - - - Right Horizontal - Höger Horisontal - - - Left Vertical - Vänster Vertikal - - - Left Horizontal - Vänster Horisontal - - - P1 - P1 - - - P2 - P2 - Ch1 Kn1 @@ -8455,12 +9785,6 @@ m2560 för v4.1-kort Ok OK - - Move sticks and pots in every direction making full movement -Press next when finished - Rör spakar och pottentiometrar. Ge fulla utslag. -Tryck på Nästa när du är klar - Error Fel @@ -8469,48 +9793,71 @@ Tryck på Nästa när du är klar Cannot open joystick. Kan inte öppna joystick. + + Enable + + + + Back + + + + Start + Start + + + Not Assigned + + + + Stick + + + + Knob/Slider %1 + + + + No joysticks found + Ingen joystick hittades + + + Press the Start button to start the stick range calibration procedure. +You may change the channel assignments or inversion at any time. + + + + Move sticks and pots in every direction making full movement +Press Next when finished + + Place sticks and pots in middle position. -Press next when done - Centrera spakar och potentiometrar. -Tryck på Nästa när du är klar +Press Next when done + Map joystick channels to controls using comboboxes. -Press next when done - Koppla joystick-kanaler till kontroller. -Tryck på Nästa när du är klar +Press Next when done. + - Check inversion checkbox to get maximum at top-right position. -Press next when done - Klicka på inverterings-kryssrutan för att lägga max i den högra, vre positionen -Tryck på Nästa när du är klar + Check inversion checkbox to if necessary to reverse direction. +Press Next when done. + - Press ok to save configuration -Press cancel to abort joystick calibration - Tryck på OK för att spara inställningarna -Tryck på Avbryt för att avburyta kalibreringen + Press OK to save configuration +Press Cancel to abort joystick calibration without saving. + - P3/LS - P3/LS + Warning + Varning - RS - RS - - - Duplicated stick assignment - Dubblerad koppling av spak - - - - mdiChild - - Simulate Tx - Simulera sändare + Calibration not complete, save anyway? + diff --git a/companion/src/translations/companion_zh_CN.ts b/companion/src/translations/companion_zh_CN.ts index b50545625..61a2d4b99 100644 --- a/companion/src/translations/companion_zh_CN.ts +++ b/companion/src/translations/companion_zh_CN.ts @@ -1,6 +1,6 @@ - + AileronsPage @@ -535,67 +535,67 @@ Mode 4: - + No joysticks found 找不到游戏杆 - + EMPTY: No radio settings stored in profile 空白:在遥控器档案中找不到遥控器设定 - + AVAILABLE: Radio settings of unknown age 允许:不明日期的遥控器设定 - + AVAILABLE: Radio settings stored %1 允许:遥控器设定保存到 %1 - + Select your library folder 对话框标题栏 选择你的图片库文件夹 - - + + Select your Models and Settings backup folder 对话框标题栏 选择你的模型和设定备份文件夹 - + Select Google Earth executable 对话框标题栏 选择 Google Earth 可执行文件 - + Select the folder replicating your SD structure 对话框标题栏 选择模拟SD卡目录结构的电脑文件夹 - + Not possible to remove profile 不能移除遥控器档案 - + The default profile can not be removed. 默认遥控器档案无法被移除. - + Open Image to load 打开图片并载入 - + Images (%1) 图片 (%1) @@ -603,72 +603,85 @@ Mode 4: Channels - + Name 在舵机设置页面中 通道名称 [Name] - + Subtrim 在舵机设置页面中 舵机中位 [Subtrim] - + Min 在舵机设置页面中 舵机下限 [Min] - + Max 在舵机设置页面中 舵机上限 [Max] - + Direction 在舵机设置页面中 舵机反向 [Dir] - + Curve 在舵机设置页面中 舵机曲线 [Curve] - + PPM Center 在舵机设置页面中 PPM中位脉宽 - + Linear Subtrim 在舵机设置页面中 线性微调 [Linear] - + CH%1 在舵机设置页面中 通道%1 - + --- 在舵机设置页面中 表示舵机正向 正向 [→] - + INV 在舵机设置页面中 反向 [←] + + CompanionMacros + + + files + + + + + Radio and Models settings + + + CompareDialog @@ -738,42 +751,42 @@ Mode 4: ContributorsDialog - + OpenTX Contributors OpenTX 贡献者 - + Main Developers 主要开发者 - + Other contributors 其他贡献者 - + Companies and projects who have donated to OpenTX 曾经给予OpenTX捐赠的公司和项目 - + People who have donated to OpenTX 曾经给予OpenTX捐赠的个人 - + Honors go to Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) 荣誉给予 Rafal Tomczak (RadioClone), Thomas Husterer (th9x) 和 Erez Raviv (er9x and eePe) - + OpenTX Blacklist OpenTX 黑名单 - + monthly 每月 @@ -810,25 +823,25 @@ Mode 4: CurveGroup - + Diff 用于INPUT和MIXER曲线选择项 差动曲线 [Diff] - + Expo 用于INPUT和MIXER曲线选择项 指数曲线 [Expo] - + Func 用于INPUT和MIXER曲线选择项 其他曲线 [Func] - + Curve 用于INPUT和MIXER曲线选择项 多点曲线 [Cstm] @@ -992,102 +1005,102 @@ Mode 4: CustomFunctionsPanel - + Switch CustomFunctionPanel 启动开关 - + Action CustomFunctionPanel 功能 - + Parameters CustomFunctionPanel 参数 - + Enable CustomFunctionPanel 是否启用 - + SF%1 CustomFunctionPanel SF%1 - + GF%1 CustomFunctionPanel GF%1 - + ON CustomFunctionPanel 启用 - + Error CustomFunctionPanel 错误 - + Unable to find sound file %1! 找不到声音文件 %1! - + &Copy CustomFunctionPanel 复制 (&C) - + Ctrl+C CustomFunctionPanel Ctrl+C - + &Cut CustomFunctionPanel 剪切 (&C) - + Ctrl+X CustomFunctionPanel Ctrl+X - + &Paste CustomFunctionPanel 粘贴 (&P) - + Ctrl+V CustomFunctionPanel Ctrl+V - + &Delete CustomFunctionPanel 删除 (&D) - + Delete CustomFunctionPanel 删除 @@ -1119,100 +1132,176 @@ Mode 4: DebugOutput - + Debug Output Debug 输出 + + + <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> + + + + + Filter: + + + + + <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> +To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> + + + + + Buffer: + + + + + Number of lines to keep in display. + + + + + Filter &Help + + + + + Show information about using the filter. + + + + + Word &Wrap + + + + + Toggle word wrapping on/off. + + + + + &Clear + (&C)清除 + + + + Clear the output window of all text. + + + + + Enable &Filter + + + + + Turn the filter on/off. + + + + + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> + + + + + Debug Console Filter Help + + EepromInterface - + Possible causes for this: 可能导致这样的原因: - + - Eeprom is from a newer version of OpenTX - Eeprom 来自 OpenTX 的新版本 - + - Eeprom is not from OpenTX - Eeprom 不是来自 OpenTX - + - Eeprom is not from Th9X - Eeprom 不是来自 Th9x - + - Eeprom is not from Gruvin9X - Eeprom 不是来自 Gruvin9x - + - Eeprom is not from ErSky9X - Eeprom 不是来自 ErSky9X - + - Eeprom is not from Er9X - Eeprom 不是来自 Er9x - + - Eeprom size is invalid - Eeprom 文件大小非法 - + - Eeprom file system is invalid - Eeprom 文件系统非法 - + - Eeprom is from a unknown board - Eeprom 来自未知的主板 - + - Eeprom is from the wrong board - Eeprom 来自错误的主板 - + - Eeprom backup not supported - 不支持 Eeprom 备份 - + - Something that couldn't be guessed, sorry - 抱歉，无法找出确定原因 - + Warning: 警告： - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - 你的遥控器可能使用了错误的固件， eeprom 大小为4096但仅前半部分的2048被使用 - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - 你的eeprom来自旧版本的OpenTX，请升级！ 你应该使用 '存储为' 将旧版本作为备份保存. - + Warnings! 警告！ @@ -1363,11 +1452,31 @@ If blank then the input is considered to be "ON" all the time.混控的输入源 - + Edit %1 Inputs对话框 编辑 %1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + FblPage @@ -1478,7 +1587,7 @@ May be different from firmware language FlashEEpromDialog - + Write Models and Settings to Radio 将模型和设置写入到遥控器 @@ -1543,107 +1652,66 @@ May be different from firmware language 写入到遥控器 - + Current profile: %1 当前档案: %1 - + Choose Radio Backup file 选择遥控器备份文件 - - - - - - - - - - + + Error 错误 - - Unable to find file %1! - 无法找到文件 %1! - - - - - - Error opening file %1: -%2. - 打开文件错误 %1: -%2. - - - - - Invalid Models and Settings File %1 - 无效的模型和设置文件 %1 - - - - Error reading file %1: -%2. - 打开文件错误 %1: -%2. - - - - Invalid Models and Settings file %1 - 无效的模型和设置文件 %1 - - - + + - - + Warning 警告 - + Wrong radio calibration data in profile, Settings not patched 此文档包含错误的遥控器校准数据.设置没有修改 - + Wrong radio setting data in profile, Settings not patched 此文档包含错误的遥控器设置数据.设置没有修改 - - + Cannot write file %1: %2. 无法写入文件 %1: %2. - + Error writing file %1: %2. 写入文件错误 %1: %2. - + The radio firmware belongs to another product family, check file and preferences! 这个遥控器固件属于其他产品，检查文件和配置! - + The radio firmware is outdated, please upgrade! 这个遥控器固件已经过期, 请升级! - + Cannot check Models and Settings compatibility! Continue anyway? 无法检查模型和设置兼容性! 仍然继续么? @@ -1721,119 +1789,119 @@ May be different from firmware language 写入到遥控器 - + Open Firmware File 打开固件文件 - - - + + + Warning 警告 - + %1 may not be a valid firmware file %1 可能是非法的固件文件 + - - - - + + + Error 错误 - + The firmware file is not valid. 固件文件非法. - + There is no start screen image in the firmware file. 固件中没有开机画面. - + Profile image %1 is invalid. 档案图片 %1 无效. - + Open image file to use as radio start screen 打开图片文件用作遥控器开机画面 - + Images (%1) 图片 (%1) - + Image could not be loaded from %1 图片无法从 %1 中加载 - + The library image could not be loaded 图片库中的图片无法被加载 - + Splash image not found 无法找到开机画面图片 - + Cannot save customized firmware 无法保存定制固件 - + Write Firmware to Radio 写入固件到遥控器 - - + + Firmware check failed 固件检查失败 - + Could not check firmware from radio 无法检查遥控器中的固件 - + New firmware is not compatible with the one currently installed! 新的固件于当前安装的固件不兼容! - + Conversion failed 转换失败 - + Cannot convert Models and Settings for use with this firmware, original data will be used 无法转换此固件中的模型和设置, 将使用原始数据 - + Restore failed 恢复失败 - + Could not restore Models and Settings to Radio. The models and settings data file can be found at: %1 无法将模型和设置恢复到遥控器. 模型和设置数据可以在 %1 中找到 - + Flashing done 烧录完成 @@ -1841,7 +1909,7 @@ May be different from firmware language FlashProcess - + Executable %1 not found FlashProcess 未找到可执行文件 %1 @@ -1972,32 +2040,47 @@ Please use ZADIG to properly install the driver. FlightModePanel - + Rotary Encoder %1 - + + Name + + + + + Value source + + + + + Value + + + + GVAR%1 全局变量[GV] %1 - + Popup enabled 屏幕弹窗提示 - + &Clear (&C)清除 - + Clear 清除 - + Clear all current Flight Mode properties? 是否清除所有的飞行模式属性? @@ -2005,19 +2088,19 @@ Please use ZADIG to properly install the driver. FlightModesPanel - + Flight Mode %1 用于FM设定 飞行模式[FM] %1 - + (%1) FlightModePanel (%1) - + (default) FlightModePanel (默认) @@ -2197,9 +2280,8 @@ p, li { white-space: pre-wrap; } GeneralEdit - General Edit - General Edit ???? - 一般选项 + Radio settings + @@ -2249,35 +2331,35 @@ These will be relevant for all models in the same EEPROM. 校准 - - - + + + Warning General Edit 警告 - + Wrong data in profile, radio calibration was not retrieved 此文档包含错误的数据. 未读取遥控器校准数据 - + Wrong data in profile, Switch/pot config not retrieved 此文档包含错误的数据. 未读取开关/旋钮配置 - + Wrong data in profile, hw related parameters were not retrieved 此文档包含错误的数据. 未读取硬件相关参数 - + Do you want to store calibration in %1 profile<br>overwriting existing calibration? 你想要存储校准数据到 %1 档案<br>覆盖当前已经存在的校准数据么? - + Calibration and HW parameters saved. 校准数据和硬件参数已经存储. @@ -2336,169 +2418,169 @@ These will be relevant for all models in the same EEPROM. - + Timeshift from UTC 依照UTC调整时间 [From UTC] - + Voice Language 语音语言 [Voice Language] - + Country Code 国家代码 [Country Code] - + Stick reverse 反向摇杆 [Stick Reverse] - + FAI Mode FAI 模式 [FAI Mode] - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. 如果开启FAI模式, 你将会失去Vario功能, 播放音频功能和回传显示功能. 此模式不能使用遥控器按键关闭. - + Automatically adjust the radio's clock if a GPS is connected to telemetry. 如果安装有GPS回传则自动调整遥控器时钟. - + Adjust RTC 自动调整时钟 - + Vario pitch at max 最大上升率时Vario音调 [Max] - - + + Hz - + Speaker Volume 喇叭音量 [Volume] - + Backlight Switch 背光开关 [Switch] - + Sound Mode 声音模式 [Sound Mode] - + Color 1 颜色 1 - + Color 2 颜色 2 - + Speaker Pitch (spkr only) 喇叭音调 (仅喇叭) [Pitch] - + If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. 如果值非0, 任何按键将会开启背光, 并在所设定秒数后关闭. - + sec 秒 - + Backlight color 背光颜色 [Color] - + Beeper 蜂鸣器 - + Speaker 喇叭 - + BeeperVoice 蜂鸣器和语音 - + SpeakerVoice 喇叭和语音 - + Beep volume 蜂鸣器音量 - + Wav volume WAV播放音量 - + Vario volume Vario音量 - + Background volume 背景音乐音量 - - + + ms 毫秒 - + Backlight Auto OFF after 背光自动关闭时间 [Duration] - + Backlight flash on alarm 告警时背光闪烁 [Alarm] - + Vario pitch at zero 升降率为0时Vario音调 [Zero] - + Vario repeat at zero 升降率0时Vario重复率 [Repeat] - + This is the switch selectrion for turning on the backlight (if installed). @@ -2508,8 +2590,8 @@ These will be relevant for all models in the same EEPROM. - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -2524,32 +2606,37 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">取值范围 20-45</span></p></body></html> - + Backlight Brightness 背光亮度 [Brightness] - + RotEnc Navigation 旋转编码器导航 [RotEnc] - + America 美国 - + Japan 日本 - + Europe 欧洲 - + + Backlight OFF Brightness + + + + Mode selection: Mode 1: @@ -2590,278 +2677,278 @@ MODE4 模式4: - + Mode 1 (RUD ELE THR AIL) MODE1 日本手↕升降↔方向 ↕油门↔副翼 - + Mode 2 (RUD THR ELE AIL) MODE2 美国手↕油门↔方向 ↕升降↔副翼 - + Mode 3 (AIL ELE THR RUD) MODE3 中国手↕升降↔副翼 ↕油门↔方向 - + Mode 4 (AIL THR ELE RUD) MODE4 模式4 ↕油门↔副翼 ↕升降↔方向 - + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> <html><head/><body><p>通道顺序</p><p><br/></p><p>定义了当新的混控创建时默认的通道顺序.</p></body></html> - + R E T A 方向 升降 油门 副翼 [R E T A] - + R E A T 方向 升降 副翼 油门 [R E A T] - + R T E A 方向 油门 升降 副翼 [R T E A] - + R T A E 方向 油门 副翼 升降 [R T A E] - + R A E T 方向 副翼 升降 油门 [R A E T] - + R A T E 方向 副翼 油门 升降 [R A T E] - + E R T A 升降 方向 油门 副翼 [E R T A] - + E R A T 升降 方向 副翼 油门 [E R A T] - + E T R A 升降 油门 方向 副翼 [E T R A] - + E T A R 升降 油门 副翼 方向 [E T A R] - + E A R T 升降 副翼 方向 油门 [E A R T] - + E A T R 升降 副翼 油门 方向 [E A T R] - + T R E A 油门 方向 升降 副翼 [T R E A] - + T R A E 油门 方向 副翼 升降 [T R A E] - + T E R A 油门 升降 方向 副翼 [T E R A] - + T E A R 油门 升降 副翼 方向 [T E A R] - + T A R E 油门 副翼 方向 升降 [T A R E] - + T A E R 油门 副翼 升降 方向 [T A E R] - + A R E T 副翼 方向 升降 油门 [A R E T] - + A R T E 副翼 方向 油门 升降 [A R T E] - + A E R T 副翼 升降 方向 油门 [A E R T] - + A E T R 副翼 升降 油门 方向 [A E T R] - + A T R E 副翼 油门 方向 升降 [A T R E] - + A T E R 副翼 油门 升降 方向 [A T E R] - + Stick Mode 摇杆模式 [MODE] - + Metric 公制 [Metric] - + Imperial 英制 [Imperial] - + Default Channel Order 默认通道顺序[Default Ch Order] - + GPS Coordinates GPS坐标格式 [GPS Coordinates] - + Min GeneralEdit 最小 - - + + v GeneralEdit v - + Max GeneralEdit 最大 - + Low Memory Warning 内存低时开机告警 [Memory Low] - + Inactivity Timer 忘记关机定时器 [Inactivity] - + Show Splash Screen on Startup 显示开机画面 [Splash Screen] - + Contrast 显示屏对比度 [Contrast] - + Battery Meter Range 遥控器电池图标范围 [Range] - + Haptic Strength 振动强度 [Haptic Strength] - + LCD Display Type LCD显示屏类型 [LCD Disp Type] - + "No Sound" Warning 当静音时 开机告警 [Sound Off] - + Battery Warning 遥控器电量警告 [Battery Low] - + Haptic Length 振动时长 [Haptic Length] - + MAVLink Baud Rate MAVLink 波特率 [Baud Rate] - - + + Quiet GeneralEdit 禁用 [Quiet] - + Only Alarms GeneralEdit 只有告警 [Alarm] - - + + No Keys GeneralEdit 忽略按键 [NoKey] - - + + All GeneralEdit 开启 [All] - + Battery warning voltage. This is the threashhold where the battery warning sounds. @@ -2872,121 +2959,121 @@ Acceptable values are 5v..10v 允许值是5V - 10V - + Standard 标准LCD [Standard] - + Optrex GeneralEdit 光王LCD [Optrex] - + If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. - + min - - + + Show splash screen on startup - + --- GeneralEdit - + 2s GeneralEdit - + 3s GeneralEdit - + 4s GeneralEdit - + 6s GeneralEdit - + 8s - + 10s - + 15s - + 4800 Baud GeneralEdit - + 9600 Baud - + 14400 Baud - + 19200 Baud - + 38400 Baud - + 57600 Baud - + 76800 Baud - + 115200 Baud - - + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -3001,77 +3088,77 @@ p, li { white-space: pre-wrap; } - - + + X-Short GeneralEdit 极短 - - + + Short GeneralEdit 较短 - - + + Normal 正常 - - + + Long GeneralEdit 较长 - - + + X-Long 极长 - + hh° (N/S) mm' ss''.dd - + NMEA GeneralEdit - + Play Delay (switch mid position) 开关拨过中档时播音延迟 [Delay] - + Measurement Units 单位制 [Units] - + Haptic Mode GeneralEdit 振动 [Haptic Mode] - + Beeper Length 蜂鸣时长 [Beep Length] - + Beeper Mode 蜂鸣音 [Beep Mode] - + Beeper volume 0 - Quiet. No beeps at all. @@ -3082,7 +3169,7 @@ p, li { white-space: pre-wrap; } - + Alarms Only GeneralEdit 只有告警 [Alarm] @@ -3091,7 +3178,7 @@ p, li { white-space: pre-wrap; } GeneralSetupPanel - + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. Are you sure ? @@ -3378,48 +3465,53 @@ Are you sure ? Bluetooth 蓝牙 [Bluetooth] + + + ADC Filter + + HardwarePanel - - - + + + None 无 - + 2 Positions Toggle 2位弹簧开关 - + 2 Positions 2位开关 - + 3 Positions 3位开关 - + Pot with detent 有中位旋钮 - + Multipos switch 多位开关 - + Pot without detent 无中位旋钮 - + Slider with detent 有中位滑杆 @@ -3646,102 +3738,103 @@ Are you sure ? LogicalSwitchesPanel - + Function LogicalSwitchPanel 运算方式 [Function] - + V1 LogicalSwitchPanel 数值1 [V1] - + V2 LogicalSwitchPanel 数值2 [V2] - + AND Switch 与开关 [AND Sw] - + Duration LogicalSwitchPanel 持续时间 [Duration] - + Delay LogicalSwitchPanel 延迟 [Delay] - + L%1 LogicalSwitchPanel - - + + (instant) LogicalSwitchPanel 边沿触发使用 (立刻 [instant]) - + + (infinite) LogicalSwitchPanel 边沿触发使用 (无限 [infinite]) - + &Copy 复制 (&C) - + Ctrl+C LogicalSwitchPanel - + &Cut LogicalSwitchPanel 剪切 (&C) - + Ctrl+X LogicalSwitchPanel - + &Paste LogicalSwitchPanel 粘贴 (&P) - + Ctrl+V LogicalSwitchPanel - + &Delete LogicalSwitchPanel 删除 (&D) - + Delete LogicalSwitchPanel 删除 @@ -3925,125 +4018,123 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt MainWindow - - - - + + File loaded 文件已载入 - + Display previous warning again at startup ? 在启动时重新显示先前的警告? - + Checking for updates 检查更新中 - + Unable to check for updates. 无法检查更新. - + A new version of Companion is available (version %1)<br>Would you like to download it? 有新版本的 Companion 可用. (版本号 %1)<br>你希望现在就下载么? - - + + Save As 另存为 - + Executable (*.exe) 可执行文件 (*.exe) - + New release available 有新版本发布 - + A new release of Companion is available, please check the OpenTX website! 有新版本的 Companion 可用, 请查看OpenTX网站! - - + + No updates available at this time. 目前没有更新的固件版本发布. - + Would you like to launch the installer? 你希望打开安装程序么? - - + + Error 错误 - + Error opening file %1: %2. 打开文件错误 %1: %2. - + Not enough flash available on this board for all the selected options 此主板上没有足够的Flash用来存储所有所选选项 - + Compilation server temporary failure, try later 编译服务器临时不可用, 请稍后再试 - + Compilation server too busy, try later 编译服务器太忙, 请稍后再试 - + Compilation error 编译错误 - + Invalid firmware 无效的固件 - + Invalid board 无效的主板 - + Invalid language 无效的语言 - + Unknown server failure, try later 未知服务器失效, 请稍后再试 - + Do you want to write the firmware to the radio now ? 你希望现在就将固件写入到遥控器么? - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -4056,33 +4147,33 @@ We recommend you view the release notes using the button below to learn about an 我们建议你使用下面的按钮查看版本说明, 以便了解对你来说重要的更新项目. - - + + Yes MainWindow 是 - - + + No MainWindow 否 - - + + Release Notes 版本发布说明 - - + + Do you want to download release %1 now ? 你希望现在就下载版本 %1 么? - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -4099,713 +4190,627 @@ We recommend you view the release notes using the button below to learn about an 我们建议你使用下面的按钮查看版本发布说明, 以便了解对你来说重要的更新项目. - + Ignore this release %1? 忽略此版本 %1? - - - + + + Companion - - The selected language will be used the next time you start Companion. - 选择的语言将在重新打开程序后使用. - - - + The new theme will be loaded the next time you start Companion. 新的主题将在重新打开程序后使用. - + The icon size will be used the next time you start Companion. 新的图标大小将在重新打开程序后使用. - - + + Open Models and Settings file 打开模型和配置文件 - - + + File saved 文件已保存 - - + + Synchronize SD 同步SD卡 - + Firmware updates 固件升级 - + Current firmware does not provide release notes informations. 目前的固件没有提供版本发布说明信息. - - + + Read Firmware from Radio 从遥控器中读取固件 - - + Write Firmware to Radio 将固件写入遥控器 - - + + Read Models and Settings from Radio 从遥控器中读取模型和配置 - - + Write Models and Settings to Radio 将模型和配置写入遥控器 - + Save Radio Backup to File 保存遥控器备份到文件 - + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + + + + + Models and Settings read + + + + + + This function is not yet implemented + + + + Read Radio Firmware to File 读取遥控器固件并保存到文件 - + OpenTX Home Page: <a href='%1'>%1</a> OpenTX 网站主页: <a href='%1'>%1</a> - + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> OpenTX Companion项目起初分支于 <a href='%1'>eePe</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> 如果你觉得此程序有用, 请通过<a href='%1'>捐赠</a>支持 - + Copyright OpenTX Team 版权所有 OpenTX Team - + About Companion 关于 Companion - + OpenTX Companion %1 - Radio: %2 - Profile: %3 OpenTX Companion %1 - 遥控器: %2 - 档案: %3 - + New MainWindow 新建配置文件 - + Create a new Models and Settings file 建立新的模型和设置文件 - + Open... 打开... - + Save 保存 - - + + Save Models and Settings file 保存模型和配置文件 - + Save As... 另存为... - + Exit 退出 - + Exit the application 退出程序 - + Cut Model 剪切模型 - + Cut current model to the clipboard 剪切当前模型到剪贴板 - + Copy Model 复制模型 - + Copy current model to the clipboard 复制当前模型到剪贴板 - + Paste Model 粘贴模型 - + Paste model from clipboard 从剪贴板中粘贴当前模型 - + Classical 经典 - + The classic companion9x icon theme 经典 companion9x 图标主题 - + Yerico Yerico图标主题 - + Yellow round honey sweet icon theme 黄色圆润甜蜜图标主题 - + Monochrome 单色黑白 - + A monochrome black icon theme 黑色图标的黑白主题 - + MonoWhite 单色白色 - + A monochrome white icon theme 白色图标的黑白主题 - + MonoBlue 单色蓝色 - + A monochrome blue icon theme 蓝色图标的黑白主题 - + Small 小 - + Use small toolbar icons 使用小的工具栏图标 - + Normal MainWindow 普通 - + Use normal size toolbar icons 使用普通大小的工具栏图标 - + Big 大 - + Use big toolbar icons 使用大工具栏图标 - + Huge 超大 - + Use huge toolbar icons 使用特大的工具栏图标 - + System language 使用系统语言 - - Use system language in menus - 使用系统语言菜单 - - - - Czech - 捷克语 - - - - Use Czech in menus - 使用捷克语菜单 - - - - German - 德语 - - - - Use German in menus - 使用德语菜单 - - - - English - 英语 - - - - Use English in menus - 使用英语菜单 - - - - Finnish - 芬兰语 - - - - Use Finnish in menus - 使用芬兰语菜单 - - - - French - 法语 - - - - Use French in menus - 使用法语菜单 - - - - Italian - 意大利语 - - - - Use Italian in menus - 使用意大利语菜单 - - - - Polish - 波兰语 - - - - Use Polish in menus - 使用波兰语菜单 - - - - Spanish - 西班牙语 - - - - Use Spanish in menus - 使用西班牙语菜单 - - - - Swedish - 瑞典语 - - - - Use Swedish in menus - 使用瑞典语菜单 - - - - Chinese - 中文 - - - - Use Chinese in menus - 使用中文菜单 - - - + About... 关于... - + Show the application's About box 显示程序的关于对话框 - + Print... 打印... - + Print current model 打印当前模型配置 - + Simulate... 模拟... - + Simulate current model 模拟当前模型 - + Alt+S - + Load Backup... 载入备份... - + Load backup from file 从文件中载入备份 - + View Log File... 查看 Log 文件... - + Open and view log file 打开和查看 Log 文件 - + Settings... 设置... - + Edit Settings 编辑设定 - + Download... 下载... - + Download firmware and voice files 下载固件和语音文件 - + Check for Updates... 检查更新... - + Check OpenTX and Companion updates 检查 OpenTX 和 Companion 更新 - + Companion Changes... Companion 更新记录... - + Show Companion change log 显示 Companion 更新记录 - + Firmware Changes... OpenTX固件 更新记录... - + Show firmware change log 显示固件更新记录 - + Compare Models... 比较模型... - + Compare models 比较模型参数 - + Edit Radio Splash Image... 编辑遥控器开机画面... - + Edit the splash image of your Radio 编辑你的遥控器的开机画面 - + List programmers... 列出编程器... - + List available programmers 列出可用的编程器 - + Fuses... 熔丝位... - + Show fuses dialog 显示熔丝位对话框 - + Read firmware from Radio 从遥控器中读取固件 - + Write firmware to Radio 将固件写入遥控器 - + Add Radio Profile 添加遥控器档案 - + Create a new Radio Setting Profile 建立新的遥控器设置档案 - + Manuals and other Documents 使用说明书和其他文档 - + Open the OpenTX document page in a web browser 在网络浏览器中打开OpenTX文档主页 - + Write Models and Settings To Radio 将模型和配置写入遥控器 - + Read Models and Settings From Radio 从遥控器中读取模型和配置 - + Configure Communications... 配置通讯... - + Configure software for communicating with the Radio 配置与遥控器通讯的软件 - + Write Backup to Radio 将备份写入遥控器 - + Write Backup from file to Radio 将备份文件写入到遥控器 - + Backup Radio to File 备份遥控器到文件 - + Save a complete backup file of all settings and model data in the Radio 保存一个包含所有遥控器设置和模型数据的备份文件 - + Contributors... 贡献者... - + A tribute to those who have contributed to OpenTX and Companion 向所有对OpenTX和Companion做出过贡献的人致敬 - + SD card synchronization 同步SD卡 - + + Use default system language. + + + + + Use %1 language (some translations may not be complete). + + + + Recent Files 最近使用的文件 - + Set Menu Language 设置菜单语言 - + Set Icon Theme 设置程序图标 - + Set Icon Size 设置图标大小 - - + + File 文件 - - + + Edit 编辑 - + Settings 设置 - + Read/Write 读/写 - - + + Help 帮助 - - + + Radio Profile 遥控器档案 - + Recent Models+Settings 最近使用的模型和设置 - + Show recent Models+Settings documents 显示最近使用的模型和设置文件 - + Show the list of radio profiles 显示遥控器文档列表 - + Write 写入 - + Ready 已准备好 - + %2 - + New Radio 新的遥控器 @@ -4813,135 +4818,257 @@ We recommend you view the release notes using the button below to learn about an MdiChild - + + Radio settings + + + + Simulate Tx 模拟遥控器 - + + Delete selected models? + + + + + Cannot delete default model. + 无法删除默认模型. + + + + &Edit + 编辑 (&E) + + + + &Restore from backup + 载入备份 (&R) + + + + &Model Wizard + 模型向导 (&M) + + + + &Delete + 删除 (&D) + + + + Delete + 删除 + + + + &Copy + + + + + Ctrl+C + Ctrl+C + + + + &Cut + 剪切 (&C) + + + + Ctrl+X + Ctrl+X + + + + + &Paste + 粘贴 (&P) + + + + + Ctrl+V + Ctrl+V + + + + D&uplicate + 克隆 (&P) + + + + Ctrl+U + + + + + Move to Category + + + + + &Use as default + 用作默认模型 (&U) + + + + P&rint model + 打印模型配置 (&P) + + + + Ctrl+P + + + + + &Simulate model + 模拟当前模型 (&S) + + + + Alt+S + + + + + &Add model + + + + + &Rename category + + + + + &Delete category + + + + + &Add category + + + + + Models and settings will be automatically converted. +If that is not what you intended, please close the file +and choose the correct radio type/profile before reopening it. + + + + + Do you want to overwrite radio general settings? + 你希望覆盖遥控器一般设定么？ + + + + You are pasting on an not empty model, are you sure? + 你正在粘贴到的模型中已经有内容, 确认要覆盖么? + + + free bytes 剩余空间 (Bytes) - + + This category is not empty! + + + + + New model + + + + Editing model %1: 编辑模型 %1: - - - - - - - - - - - - - - - - - - - + + + + + + + Error 错误 - - + + Unable to find Horus radio SD card! + + + + + Models and Settings written + + + + Unable to find file %1! 无法找到文件 %1! - - - - + Error opening file %1: %2. 打开文件错误 %1: %2. - - - Invalid EEPROM File %1 - 无效的 EEPROM 文件 %1 - - - - - - + Warning 警告 - - + Error reading file %1: %2. 打开文件错误 %1: %2. - - Invalid binary EEPROM File %1 - 无效的二进制 EEPROM 文件 %1 - - - - - - + + + + Save As 另存为 - - - - - Cannot write file %1: -%2. - - - - - - Error writing file %1: -%2. - 写入文件错误 %1: -%2. - - - + + Companion Companion - + %1 has been modified. Do you want to save your changes? %1已经修改. 想要保存修改么? - + Cannot write temporary file! - + Open backup Models and Settings file 打开备份的模型和设置文件 - + Invalid binary backup File %1 无效的二进制备份文件 %1 @@ -5161,34 +5288,54 @@ If blank then the mix is considered to be "ON" all the time. 如果不设定开启开关则默认此条混控一直启用. - + DEST -> CH%1 目标 -> 通道%1 + + + Click to access popup menu + + + + + Clear All + + + + + Set All + + + + + Invert All + + MixesPanel - + Move Up 向上移动此行 - + Ctrl+Up - + Move Down 向下移动此行 - + Ctrl+Down Ctrl+Dn @@ -5198,102 +5345,102 @@ If blank then the mix is considered to be "ON" all the time. 清除本页所有混控 - + Not enough available mixers! 无空白混控存储位置! - + Delete Selected Mixes? 是否删除选择的混控? - + &Add 添加 (&A) - + Ctrl+A - + &Edit 编辑 (&E) - + Enter 确定 - + &Toggle highlight 切换高亮 (&T) - + Ctrl+T - + &Delete 删除 (&D) - + Delete 删除 - + &Copy 复制 (&C) - + Ctrl+C - + C&ut 剪切 (&C) - + Ctrl+X - + &Paste 粘贴 (&P) - + Ctrl+V - + Du&plicate 克隆 (&P) - + Ctrl+U - + Clear Mixes? 清除混控? - + Really clear all the mixes? 是否真的删除所有混控? @@ -5311,54 +5458,54 @@ If blank then the mix is considered to be "ON" all the time. 遥控器模拟器 - + Setup 设置 Setup - + Heli 直升机 Heli - + Flight Modes 飞行模式 FM - + Inputs 输入 Inputs - + Mixes !!!! mixes-->mixer 混控 Mixer - + Outputs 输出 Outputs - + Curves ModelEdit 曲线 Curves - + Logical Switches 逻辑开关 Logical Sw - + Special Functions 特殊功能 Special Func - + Telemetry 回传设置 Tele @@ -5366,316 +5513,316 @@ If blank then the mix is considered to be "ON" all the time. ModelPrinter - + %1 bytes - + CH%1 - + Exponential 指微调的步长 先小后大 [Exp] - + Extra Fine 很小 [Extra Fine] - + Fine 小 [Fine] - + Medium 中等 [Medium] - + Coarse 大 [Coarse] - + Unknown Model Printer 未知[Unknown] - + Enabled 启用[Enabled] - + Disabled 禁用[Disabled] - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) %1, 通道(%2-%3), PPM 延迟(%4微秒), Pulse 极性(%5) - + %1, Channels(%2-%3) %1, 通道[CH](%2-%3) - + Receiver number(%1) 接收机编号[Receiver num](%1) - + radio Protocol %1, subType %2, option value %3 遥控器协议 %1, 子协议 %2, 可选值 %3 - + Slave/Jack 教练从机/教练线插口 [Slave/Jack] - + Master/SBUS Module 教练主机/SBUS 模块 [Master/SBUS] - + Master/CPPM Module 教练主机/CPPM 模块 [Master/CPPM] - + Master/SBUS in battery compartment 教练主机/SBUS 电池盒中插座 - + Master/Jack 教练主机/教练线插口 [Master/Jack] - + 90 - + 120 - + 120X - + 140 - - + + Off Model Printer 关闭 - + Rudder Model Printer 方向[Rudder] - + Elevator Model Printer 升降[Elevator] - + Throttle Model Printer 油门[Throttle] - + Aileron Model Printer 副翼[Aileron] - + Name(%1) 名称(%1) - + Persistent 保持[Persistent] - + MinuteBeep 分钟提示[MinuteBeep] - + CountDown(Beeps) 倒数报数(蜂鸣[Beeps]) - + CountDown(Voice) 倒数报数(语音[Voice]) - + CountDown(Haptic) 倒数报数(振动[Haptic]) - - - - + + + + FM%1 - + FM%1%2 - + FM%1+%2 - + [I%1] - + Input%1 !!!!此处似乎应该是[I%1] (用在INPUT列表页面中) I%1 - + Weight 比例 [Weight] - + Switch 启用开关[Switch] - - + + NoTrim 不使用微调[Notrim] - - + + Offset(%1) 偏移[Offse](%1) - + Weight(%1) 比例 [Weight](%1) - + Switch(%1) 启用开关[Switch](%1) - + No DR/Expo 不使用 DR/Expo - + Delay(u%1:d%2) 延迟(u%1:d%2) - + Slow(u%1:d%2) 慢动作u(u%1:d%2) - + Warn(%1) 启用时蜂鸣提示[Warn](%1) - + Disabled in all flight modes 在所有飞行模式中禁用 - + Flight modes(%1) 飞行模式 [FM](%1) - + Flight mode(%1) 飞行模式 [FM](%1) - + Edge(%1, [%2:%3]) 边沿触发[Edge](%1, [%2:%3]) - + instant 立刻执行[instant] - + Sticky(%1, %2) 粘滞键[Sticky](%1, %2) - + Timer(%1, %2) 定时[Timer](%1, %2) - + Duration(%1s) 持续[Duration](%1秒) - + Delay(%1s) 延迟[Delay](%1s) - + Custom 自定义[Custom] - + Standard 标准[Standard] @@ -5711,146 +5858,7 @@ If blank then the mix is considered to be "ON" all the time. ModelsListWidget - - Index - ModelList 后面加了多个空格 为了排版美观 SPACES ADDED FOR LAYOUT - 模型编号 - - - - Name - 模型名称 - - - - Size - Model List Widget - 占用内存 - - - - - &Edit - 编辑 (&E) - - - - &Restore from backup - 载入备份 (&R) - - - - &Model Wizard - 模型向导 (&M) - - - - &Delete - 删除 (&D) - - - - Delete - 删除 - - - - &Copy - 复制 (&C) - - - - Ctrl+C - - - - - &Cut - 剪切 (&C) - - - - Ctrl+X - - - - - &Paste - 粘贴 (&P) - - - - Ctrl+V - - - - - D&uplicate - 克隆 (&P) - - - - Ctrl+U - - - - - &Use as default - 用作默认模型 (&U) - - - - P&rint model - 打印模型配置 (&P) - - - - Ctrl+P - - - - - &Simulate model - 模拟当前模型 (&S) - - - - Alt+S - - - - - General Settings - 遥控器一般设定 - - - - Delete Selected Models? - 是否删除选择的模型? - - - - - Cannot delete default model. - 无法删除默认模型. - - - - Cannot cut default model. - 无法剪切默认模型. - - - - Do you want to overwrite radio general settings? - 你希望覆盖遥控器一般设定么？ - - - - You are pasting on an not empty model, are you sure? - 你正在粘贴到的模型中已经有内容, 确认要覆盖么? - - - + No free slot available, cannot duplicate 没有空余的模型存储空间, 无法克隆 @@ -5858,166 +5866,203 @@ If blank then the mix is considered to be "ON" all the time. Module - + CH 通道 - + Failsafe Mode 失控保护方式 [Failsafe Mode] - + Start 开始通道 [CH] - + PPM delay PPM 延迟 [Delay] - + us 微秒 - + Negative 负 [Negative] - + Positive 正 [Positive] - + + Antenna + + + + + Internal + + + + + Ext. + Int. + + + + + Option value + + + + Master/Jack 教练主机/教练线插口 [Master/Jack] - + Slave/Jack 教练从机/教练线插口 [Slave/Jack] - + Master/SBUS Module 教练主机/SBUS 模块 [Master/SBUS] - + Master/CPPM Module 教练主机/CPPM 模块 [Master/CPPM] - + Master/SBUS in battery compartment 教练主机/SBUS 电池盒中插座 - + + Show values in: + + + + + % + abbreviation for percent + + + + + μs + abbreviation for microseconds + + + + Polarity 极性 [Polarity] - + Trainer Mode 教练功能模式 [Trainer Mode] - + ms 毫秒 - + PPM Frame Length PPM帧长 [Frame Length] - + Channels 通道数 [Channels] - + Not set 未设置 - + Hold 自定义 [Custom]]]]] 保持 [Hold] - + Custom 自定义 [Custom]]]]] 自定义 [Custom] - + No Pulses 自定义 [Custom]]]]] 不输出脉冲 [No Puls] - + Receiver 自定义 [Custom]]]]] 接收机设置[Reciever] - + Failsafe Positions 失控保护位置 [F.s. Positons] - + Protocol 遥控器射频协议 [Protocol] - + Multi Radio Protocol 多遥控协议 [Multi Protocal] - + Receiver No. 接收机编号 [Receiver No.]. - + Output type 输出类型 [Output type] - + Open Drain 开漏输出 [Open Drain] - + Push Pull 推挽输出 [Push Pull] - + SubType 子协议 - + Bind on startup 开机时对频[Bind] - + Low Power 低功率[Range] @@ -6025,44 +6070,44 @@ If blank then the mix is considered to be "ON" all the time. ModulePanel - + Trainer Port 教练功能 [Trainer Port] - + Internal Radio System 内置高频头 [Internal RF] - + External Radio Module 外置高频头 [External RF] - - + + Radio System 高频头 [Radio System] - + Extra Radio System 附加高频头 [Extra RF] - + Value 自定义回传中使用 设为 - + Hold 保持 [Hold] - + No Pulse 不输出脉冲 [No Pulse] @@ -6070,249 +6115,302 @@ If blank then the mix is considered to be "ON" all the time. MultiModelPrinter - + General Model Settings 一般模型设定 - + Name: 名称 [Name]: - + EEprom Size: EEprom 大小: - + Timer%1: 计时器[Timer] %1: - + Module%1: 模块%1: - + Module: 模块: - + Trainer port: 教练功能 [教练功能]: - + Throttle Trim: 油门微调 [Thr Trim]: - + Trim Increment: 微调步幅 [Trim Increment]: - + Center Beep: 中位蜂鸣: - + Helicopter Setup 直升机设定 - + Swash Type: 斜盘类型 [Swach Type]: - + Swash Ring: 斜盘限位 [Swach RIng]: - + Input 输入 - + Weight 比例 [Weight] - + Long. cyc 纵向循环螺距 [Long] - + Lateral cyc 横向循环螺距 [Lateral] - + Collective 总距 [Collective] - + Flight modes 飞行模式 [Modes] - - + + Flight mode 飞行模式 [Modes] - + Switch 启用开关 [Switch] - + Fade IN 淡入 - + Fade OUT 淡出 - - + + FM%1 - - + + GV%1 - + RE%1 - + Limits 极限 - + Channel 通道 - + Name 名称 [Name] - - + + Offset 偏移 [Offset] - + Min 舵机下限 [Min] - + Max 舵机上限 [Max] - + Invert 反向 - + Global Variables 全局变量 [Global Variables] - + Inputs 输入 - + Mixers 混控 [Mixers] - + CV%1 - + Curves 多点曲线 [Curves] - + L%1 - + Logical Switches 逻辑开关 [Logical Sw] - + SF%1 - + Special Functions 特殊功能 [Special Func] - + Telemetry Settings 回传设定 [Telemetry] - + Analogs 模拟量 [Analogs] - + Unit 单位 [Unit] - + Scale 缩放 [Scale] - + A%1 - + RSSI Alarms RSSI 告警 [RSSI Alarms] + + + Low Alarm + 低告警 + + + + Critical Alarm + 紧急告警 + + + + Multiprotocols + + + Subtype + + + + + Video TX frequency + + + + + C2500 frequency fine tune + + + + + Telemetry + + + + + Radio output power + + + + + Servo output frequency + + + + + Option value + + + + + DEFAULT + + MultirotorPage @@ -6432,1897 +6530,1894 @@ If blank then the mix is considered to be "ON" all the time. 档案图片 - - + + -GV%1 - - - + + + GV%1 - - - - - - - + + + + + + + V - - + + A - + mA - + kts - - + + m/s - - - + + + km/h - - - + + + mph - - - + + + m - + f - - + + °C - + °F - - + + % - - + + mAh - - + + W - + + mW + + + + dB - + rpms - - + + g - - + + ° - + + Rad + + + + hours 小时 - + minutes 分 - + seconds 秒 - - + + s - + ft - + h:m 小时:分钟 - + m:s 分钟:秒数 - + h:m:s 小时:分钟:秒数 - - - + + + REa - - - + + + REb - + TrmR TrmR 方向微调 - + TrmE TrmE 升降微调 - + TrmT TrmT 油门微调 - + TrmA TrmA 副翼微调 - - + + Trm5 + + + + + Trm6 + + + + + Batt Batt 控电电压 - - + + Time Time 当前时间 - - - + + + Timer1 重设计时器中会用到 RESET 计时器1 [Timer1] - - - + + + Timer2 重设计时器中会用到 RESET 计时器2 [Timer2] - - - + + + Timer3 重设计时器中会用到 RESET 计时器3 [Timer3] - + SWR SWR 天线健康值 - + RSSI Tx RSSI Tx 发射机RSSI - + RSSI Rx RSSI Rx 接收机RSSI - + A1 A1 模拟值1 - + A2 A2 模拟值2 - + A3 A3 模拟值3 - + A4 A4 模拟值4 - + Alt Alt 高度 - + Rpm Rpm 转速 - + Fuel Fuel 油量 - + T1 T1 温度1 - + T2 T2 温度2 - + Speed Speed 速度 - + Dist Dist 距离 - + GPS Alt GPS Alt GPS高度 - + Cell Cell 锂电单片电压 - + Cells Cells 锂电总电压 - + Vfas Vfas FAS传感器电压 - + Curr Curr 电流 - + Cnsp Cnsp 电池使用mAh - + Powr Powr 功率 - + AccX AccX X轴加速度 - + AccY AccY Y轴加速度 - + AccZ AccZ Z轴加速度 - + Hdg !!!!英文中多了个空格? Hdg 航向角 - + VSpd VSpd 垂直速度 - + AirSpeed AirSpeed 空速 - + dTE dTE 总能量变化 - + A1- - + A2- - + A3- - + A4- - + Alt- Alt- 最小高度 - + Alt+ Alt+ 最大高度 - + Rpm+ - + T1+ - + T2+ - + Speed+ - + Dist+ - + AirSpeed+ - + Cell- - + Cells- - + Vfas- - + Curr+ - + Powr+ - + ACC ACC 加速度 - + GPS Time GPS Time GPS时间 - - - - + + + + ---- - + [I%1] - + LUA%1%2 - + MAX MAX 最大 - - + + L%1 - + CYC%1 CYC%1 循环螺距 - + TR%1 TR%1 教练口通道 - + CH%1 - + FM0 - + FM1 - + FM2 - + FM3 - + FM4 - + FM5 - + FM6 - + FM7 - + FM8 - - S11 - - - - - S12 - - - - - S13 - - - - - S14 - - - - - S15 - - - - - S16 - - - - - S21 - - - - - S22 - - - - - S23 - - - - - S24 - - - - - S25 - - - - - S26 - - - - - S31 - - - - - S32 - - - - - S33 - - - - - S34 - - - - - S35 - - - - - S36 - - - - + RudTrim Left ThrTrim Down 油门微调↓ RudTrim Left 方向微调← - + RudTrim Right ThrTrim Down 油门微调↓ RudTrim Right 方向微调→ - + EleTrim Down ThrTrim Down 油门微调↓ EleTrim Down 升降微调↓ - + EleTrim Up ThrTrim Down 油门微调↓ EleTrim Up 升降微调↑ - + ThrTrim Down ThrTrim Down 油门微调↓ ThrTrim Down 油门微调↓ - + ThrTrim Up ThrTrim Down 油门微调↓ ThrTrim Up 油门微调↑ - + AilTrim Left ThrTrim Down 油门微调↓ AilTrim Left 副翼微调← - + AilTrim Right ThrTrim Down 油门微调↓ AilTrim Right 副翼微调→ - - - + + Trim 5 Down + + + + + Trim 5 Up + + + + + Trim 6 Down + + + + + Trim 6 Up + + + + + + OFF 计时器设置 Timer OFF 关闭 - - - + + + ON OFF 关闭 ON 开启 - + THs OFF 关闭 THs 油门激活 - + TH% OFF 关闭 TH% 油门比例 - + THt OFF 关闭 THt 油门计时 - + One One 单次 - + ??? - + Diff(%1) - + Expo(%1) - + Function(%1) - + Curve(%1) - + !Curve(%1) - - - + + + --- - + a>x 数值1 ＝ 数值2 a=x 数值1 ＞ 数值2 a>x - + a<x 数值1 ＝ 数值2 a=x 数值1 ＜ 数值2 a<x - + |a|>x 数值1 ＝ 数值2 a=x |数值1| ＞ 数值2 |a|>x - + |a|<x 数值1 ＝ 数值2 a=x |数值1| ＜ 数值 2 |a|<x - + AND 数值1 ＝ 数值2 a=x 与运算 AND - + OR 数值1 ＝ 数值2 a=x 或运算 OR - + XOR 数值1 ＝ 数值2 a=x 异或运算 XOR - + a=b 数值1 ＝ 数值2 a=x 数值1 ＝ 数值2 a=b - + a!=b 数值1 ＝ 数值2 a=x 数值1 !＝ 数值2 a!=b - + a>b 数值1 ＝ 数值2 a=x 数值1 ＞ 数值2 a>b - + a<b 数值1 ＝ 数值2 a=x 数值1 ＜ 数值2 a<b - + a>=b 数值1 ＝ 数值2 a=x 数值1 ≥ 数值2 a>=b - + a<=b 数值1 ＝ 数值2 a=x 数值1 ≤ 数值2 a<=b - + d>=x 数值1 ＝ 数值2 a=x 数值1变动 ≥ 数值2 d>=x - + |d|>=x 数值1 ＝ 数值2 a=x |数值1变动| ≥ 数值2 d>=x - + a=x 数值1 ＝ 数值2 a=x 数值1 ＝ 数值2 a=x - + a~x 数值1 ＝ 数值2 a=x 数值1 ≈ 数值2 a~x - + Timer 数值1 ＝ 数值2 a=x 定时开关 Timer - + Sticky 数值1 ＝ 数值2 a=x 粘滞键 Sticky - + Edge 数值1 ＝ 数值2 a=x 边沿触发 EDGE - - + + Left Horizontal + 左摇杆水平方向 + + + + Left Vertical + 左摇杆垂直方向 + + + + Right Vertical + 右摇杆上下方向 + + + + Right Horizontal + 右摇杆水平方向 + + + + Aux. 1 + + + + + Aux. 2 + + + + + Unknown 未知 - + Override %1 操纵杆位变微调 [Instant Trim] 锁定通道值 %1 [Override] - + Trainer 操纵杆位变微调 [Instant Trim] 教练开关 [Trainer] - + Trainer RUD 操纵杆位变微调 [Instant Trim] 教练开关 方向 [Trainer RUD] - + Trainer ELE 操纵杆位变微调 [Instant Trim] 教练开关 升降 [Trainer ELE] - + Trainer THR 操纵杆位变微调 [Instant Trim] 教练开关 油门 [Trainer THR] - + Trainer AIL 操纵杆位变微调 [Instant Trim] 教练开关 副翼 [Trainer AIL] - + Instant Trim 操纵杆位变微调 [Instant Trim] 操纵杆位变微调 [Instant Trim] - + Play Sound 操纵杆位变微调 [Instant Trim] 播放蜂鸣 [Play Sound] - + Haptic 操纵杆位变微调 [Instant Trim] 振动 [Haptic] - + Reset 操纵杆位变微调 [Instant Trim] 重设 [Reset] - + Set Timer %1 操纵杆位变微调 [Instant Trim] 设定计时器%1 [Set Timer] - + Vario 操纵杆位变微调 [Instant Trim] 开启 Vario 声音 [Vario] - + Play Track 操纵杆位变微调 [Instant Trim] 播放声音文件 [Play Track] - + Play Both 操纵杆位变微调 [Instant Trim] 播放同时振动 [Play Both] - + Play Value 操纵杆位变微调 [Instant Trim] 播放数值 [Play Value] - + Play Script 操纵杆位变微调 [Instant Trim] 运行脚本 [Play Script] - + SD Logs 操纵杆位变微调 [Instant Trim] SD Log 记录 [SD Logs] - + Volume 操纵杆位变微调 [Instant Trim] 音量 [Volume] - + Backlight 操纵杆位变微调 [Instant Trim] 背光 [Backlight] - + Screenshot 操纵杆位变微调 [Instant Trim] 截屏 [Screenshot] - + Background Music 操纵杆位变微调 [Instant Trim] 背景音乐播放 [Bg Music] - + Background Music Pause 操纵杆位变微调 [Instant Trim] 背景音乐暂停 [Bg Music Pause] - + Adjust GV%1 操纵杆位变微调 [Instant Trim] 设定GV%1 [Adjust GV] - + SetFailsafe Int. Module 操纵杆位变微调 [Instant Trim] 启动内置高频头失控保护 [SetFailsafe Int] - + SetFailsafe Ext. Module 操纵杆位变微调 [Instant Trim] 启动外置高频头失控保护 [SetFailsafe Ext] - + RangeCheck Int. Module 操纵杆位变微调 [Instant Trim] 内置高频头拉距测试 - + RangeCheck Ext. Module 操纵杆位变微调 [Instant Trim] 外置高频头拉距测试 - + Bind Int. Module 操纵杆位变微调 [Instant Trim] 内置高频头对频 - + Bind Ext. Module 操纵杆位变微调 [Instant Trim] 外置高频头对频 - + Flight 操纵杆位变微调 [Instant Trim] 飞行 [Flight] - + Telemetry 操纵杆位变微调 [Instant Trim] 回传值 [Telemetry] - + Rotary Encoder 操纵杆位变微调 [Instant Trim] 旋转编码器 [Rotary Encoder] - - - + + + <font color=red><b>Inconsistent parameter</b></font> <font color=red><b>不一致的参数</b></font> - + Value 值 - + Decr: 减少: - + Incr: 增加: - + played once, not during startup 播放一次但开机时不播放 - + repeat(%1s) 每%1秒重复 - + DISABLED 禁用 - + INV 反向 - + NOR ???? 或非 - + Positive 正向 - + Negative 负 - + Switch 启动开关 - + Switch 启动开关 - + cannot be exported on this board! 无法输出到这个主板! - + Source %1 cannot be exported on this board! 源 %1 无法输出到这个主板! - + OpenTX only accepts %1 points in all curves OpenTX只允许最大%1点曲线 - + OpenTx only accepts %1 points in all curves OpenTX只允许最大%1点曲线 - - - - + + + + OpenTX on this board doesn't accept this function OpenTX在这个主板上不支持此项功能 - + OpenTX doesn't accept this telemetry protocol OpenTX 不接受此回传协议 - + OpenTX doesn't allow this number of channels OpenTX 不允许此通道数量 - - - + + + OpenTX doesn't accept this radio protocol OpenTX 不接受此遥控器协议 - - (displaying only first 10 warnings) - (仅显示前10个警告) - - - - + Warning 警告 - - EEPROM saved with these warnings: - EEPROM已保存, 带有下列警告: - - - - + + Rud - - + + Ele - - + + Thr - - + + Ail - - + + P1 P1 - - + + P2 P2 - - + + P3 - + F1 - + F2 - + F3 - + F4 - - - + + + S1 - - - + + + S2 - - - + + + LS - - - + + + RS - + S3 - + 6P - + L1 - + L2 - + Channel values displayed in us 通道值显示为微秒 - + No OverrideCH functions available 不允许锁定通道值功能 - + Possibility to enable FAI MODE (no telemetry) at field 可选择启用 FAI 模式 (没有回传) - + FAI MODE (no telemetry) always enabled 一直启用 FAI 模式 (没有回传) - + Disable HELI menu and cyclic mix support 禁用直升机菜单和CCPM混控菜单 - + Disable Global variables 禁用GV[Global variables]功能 - + Support for Lua model scripts 支持Lua模型脚本 - + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) 当用USB连接到电脑时,启用U盘功能而不是游戏杆功能 (与在 Bootloader 中一样) - + Instead of Joystick emulation, USB connection is Command Line Interface 当用USB连接到电脑时,启用命令行界面功能而不是游戏杆功能 - + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 移除 D8 FrSky 协议支持,因为在20151月1日后在欧洲销售的遥控器中使用此协议是不合法的 - + Support for the DIY-Multiprotocol-TX-Module 支持 DIY-Multiprotocol-TX-Module - - - Adds mixers output view to the CHANNELS MONITOR screen, pressing [ENT] switches between the views - 加入混控输出查看 [mixers output view] 到通道查看页面, 按[ENT]键切换视图 - - - + + Support for PPM internal module hack 支持 hack PPM内置高频头 - - - - - - - - - - + + + + + + + + + + + Use alternative SQT5 font 使用 另一个 SQT5 font - + ST7565P LCD or compatible ST7565P LCD或兼容型号 - + ST7565R LCD or compatible ST7565R LCD或兼容型号 - + ERC12864FSF LCD ERC12864FSF LCD - + ST7920 LCD ST7920 LCD - + KS108 LCD KS108 LCD - - + + Support for frsky telemetry mod 支持 Frsky 回传模块 - + Support for telemetry easy board 支持 telemetry easy board - - + + Support for jeti telemetry mod 支持J JETI 回传mod - - + + Support for receiving ardupilot data 支持接收 ardupilot 数据 - - + + Support for receiving NMEA data 支持接收 NMEA 数据 - - + + Support for MAVLINK devices 支持 MAVLINK 设备 - + Rotary Encoder use in menus navigation 使用旋转编码器 进行菜单导航 - - - - - - - + + + + + + + Pots use in menus navigation 使用旋钮进行菜单导航 - - - - - + + + + + Support for DSM2 modules 支持DSM2高频头 - + Support for DSM2 modules using ppm instead of true serial 通过PPM而非真串行支持DSM2高频头 - + FrSky Taranis X9D+ FrSky Taranis X9D+ - + FrSky Taranis X9D FrSky Taranis X9D - + Haptic module installed 振动模块已经安装 - + FrSky Taranis X9E FrSky Taranis X9E - + Confirmation before radio shutdown 遥控器关机前确认 - + Horus gimbals installed (Hall sensors) Horus 摇杆已安装 (霍尔传感器) - + FrSky Taranis X7 FrSky Taranis X7 - + FrSky Horus FrSky Horus - + Use ONLY with first DEV pcb version 只用与 DEV pcb 版本 - + Turnigy 9XR-PRO Turnigy 9XR-PRO - - - + + + Enable HELI menu and cyclic mix support 允许直升机菜单和斜盘混控支持 - - - - - - - - - + + + + + + Enable TEMPLATES menu 允许模板菜单 - - - - - - - - - + + + + + + + + + No flight modes - - - - - - - - - + + + + + + Disable curves menus 禁用曲线菜单 - - - - - - - - - + + + + + + PPM center adjustment in limits 限值中调整PPM中位 - - - - - - - - - + + + + + + + + + Global variables GV [Global variables] - - - - - - - - - + + + + + + Symetrical Limits 对称的舵机上下限 - - - - - - - - - + + + + + + + + + In model setup menus automatically set source by moving the control 在模型配置菜单通过移动摇杆自动设置源 - - - - - - - - - + + Unknown error + + + + + ... plus %1 errors + + + + + Cannot write radio settings + + + + + Cannot write model %1 + + + + + JSx + + + + + JSy + + + + + Enable Lua compiler + + + + + WTV20 voice module + + + + + JQ6500 voice module + + + + + + + + + + + + In model setup menus automatically set switch by moving the control 在模型配置菜单通过拨动开关自动设置源 - - - - - - - - - + + + + + + + + + No graphical check boxes and sliders 无图形选择框和滑杆 - - - - - - - - - + + + + + + + + + Battery graph 电池图标 - - - - - - - - - + + + + + + + + + Don't use bold font for highlighting active items 不使用粗体高亮活动项目 - - - + + + Bluetooth interface 蓝牙界面 - + Turnigy 9XR with m128 chip Turnigy 9XR (m128芯片) - - - - - - + + + + + + Enable heli menu and cyclic mix support 允许直升机菜单和斜盘混控支持 - - - - + + + + No splash screen 不使用开机画面 - - - - - + + + + + Support for radio modified with regular speaker 支持改装过普通扬声器的遥控器 - - - - - - + + + + + Used if you have modified your radio with voice mode 使用, 如果你的遥控器加入语音板 - - - - - + + + + + Used if you have modified your radio with haptic mode 使用, 如果你的遥控器改装过振动 - - - - + + + + Enable the throttle trace in Statistics 允许记录油门信息 ,以便在遥控器Statistics菜单中显示 - - - - - + + + + + EEprom write Progress bar EEPROM写入进度条 - - - - - - + + + + + + Imperial units 英制单位 - + Turnigy 9XR Turnigy 9XR - - + + No Winged Shadow How High support 不支持 Winged Shadow How High - - + + No vario support 不支持Vario - - + + No GPS support 不支持 GPS - - + + No gauges in the custom telemetry screen 在自定义回传屏幕中没有仪表盘 - - + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) 增添了摇杆输入反向功能 (例如Frsky的摇杆组件需要此功能) - + 9X with stock board 9X (原装主板) - - + + SmartieParts 2.2 Backlight support 支持 SmartieParts 2.2 - - - - - - + + + + + + Enable resetting values by pressing up and down at the same time 允许通过同时按上下键重设数值 - + EEprom write progress bar EEPROM写入进度条 - + Allow compensating for offset errors in FrSky FAS current sensors 允许补偿Frsky FAS电流传感器的偏移误差 - + 9X with stock board and m128 chip 9X (原装主板和m128芯片) - + 9X with AR9X board 9X (AR9X主板) - + 9X with Sky9x board 9X (Sky9x主板) - + 9X with Gruvin9x board 9X (Gruvin9x主板) - - + + Support for SD memory card 支持SD卡 - - + + Support of FrSky PXX protocol 支持 FrSky PXX 高频头协议 - + DIY MEGA2560 radio DIY的 MEGA2560 遥控器 - + Power management by soft-off circuitry 使用软关机电路控制电源 @@ -8342,219 +8437,240 @@ If blank then the mix is considered to be "ON" all the time. 正范围 - + Keys 按键 [Keys] - + Sticks 摇杆 [Sticks] - + Keys + Sticks 按键和摇杆 [Keys + Sticks] - + English 英语 - + Dutch 荷兰语 - + French 法语 - + Italian 意大利语 - + German 德语 - + Czech 捷克语 - + Slovak 慢动作 [Slow] - + Spanish 西班牙语 - + Polish 波兰语 - + Portuguese 葡萄牙语 - + Swedish 瑞典语 - + Hungarian 匈牙利语 - + No QObject中 否 - + RotEnc A 旋转编码器A - + Rot Enc B 旋转编码器B - + Rot Enc C 旋转编码器C - + Rot Enc D 旋转编码器D - + Rot Enc E 旋转编码器E - + Rud Trim 微调Rud - + Ele Trim 微调Ele - + Thr Trim 微调Thr - + Ail Trim 微调Ail - + Rot Enc 旋转编码器 - + !Flight mode %1 !Flight mode %1 - + Flight mode %1 Flight mode %1 - + Own value 使用单独的取值 - + Flight mode %1 value 使用FM%1值 - + -GV%1 (%2) -GV%1 (%2) - + GV%1 (%2) GV%1 (%2) - + Yellow 黄色警告 - + Orange 橙色警告 - + Red 红色警告 - + Winged Shadow How High Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (不再支持) - + FrSky Sensor Hub FrSky Sensor Hub - + None 无 - + Imperial 英制 [Imperial] - + Metric 公制 [Metric] - + Simulator for this firmware is not yet available 模拟器现在还不支持此版固件 - - + + + Uknown error during Simulator startup. + + + + + Simulator Error + + + + + Data Load Error + + + + + Error occurred while starting simulator. + + + + + @@ -8562,12 +8678,12 @@ If blank then the mix is considered to be "ON" all the time. 同步错误 - + No SD directory configured! SD卡目录没有配置! - + No Radio connected! 遥控器未连接! @@ -8577,70 +8693,70 @@ If blank then the mix is considered to be "ON" all the time. GV - + Played once, not during startup 播放一次但开机时不播放 [!1x] - + No repeat 播放一次 [1x] - + %1s 每%1秒播放一次 - + Value 值 - + Source 出现在INPUT主界面的条目概览中? 输入源 - + GVAR GVAR - + Increment 增加 - + Trim disabled QQ Object 出现在INPUT主界面的条目概览中? 不使用微调 - + Own Trim 使用单独的微调值 - + Use Trim from Flight mode %1 使用 FM%1 的微调值 - + Use Trim from Flight mode %1 + Own Trim as an offset 使用 FM%1 的微调值 + 单独的微调偏移值 - + THR QObject THR THR - + -%1 @@ -8671,227 +8787,181 @@ If blank then the mix is considered to be "ON" all the time. 写入 '%1' 失败 - - - + + + + + + + Error 错误 - + Cannot write file %1: %2. 无法写入文件 %1: %2. - + Companion Companion - + <b><u>WARNING!</u></b><br>This will reset the fuses of %1 to the factory settings.<br>Writing fuses can mess up your radio.<br>Do this only if you are sure they are wrong!<br>Are you sure you want to continue? <b><u>警告!</u></b><br>这将把 %1 的熔丝位恢复工厂设置<br>改变熔丝位可能使你的遥控器变砖.<br>只有当你确定它们是错误的时候才能进行此操作!<br>你确认要继续么? - - + + Could not delete temporary file: %1 无法删除临时文件: %1 - - Simulator Startup Options: - 模拟器启动选项: + + Unable to find Horus radio SD card! + - - Profile: - 档案: - - - - Existing radio profiles are shown here.<br/>Create or edit profiles using the Companion application. - 已有的遥控器档案显示在这里.<br/>使用 Companion 程序来创建或编辑档案. - - - - Radio Type: - 遥控器型号: - - - - Existing radio simulators are shown here.<br/>The radio type specified in the selected profile is used by default. - 已有的遥控器模拟器显示在这里.<br/>默认使用档案中的遥控器型号. - - - - EEPROM Image: - EEPROM 镜像文件: - - - - EEPROM image file to use. A new file with a default image will be created if necessary.<br /><b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! - 使用的 EEPROM 镜像文件.如果需要,新的包含默认镜像的文件将被创建<br /><b>注意</b>: 任何与当前选择的遥控器型号不同的已有的 EEPROM 数据将会被覆盖! - - - - Select EEPROM image file... - 选择 EEPROM 镜像文件... - - - - All files (*.*) - 所有文件 (*.*) - - - - Select EEPROM image - 选择 EEPROM 镜像文件 - - - + Available profiles: 可用档案: - + ID: - + Name: 名称: - + Available radios: 可用的遥控器: - + WARNING: couldn't initialize SDL: %1 警告: 无法初始化 SDL: %1 - - WARNING: couldn't create directory for EEPROM: -%1 - 警告:无法位EEPROM建立目录: -%1 + + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] + - + + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. + Profile ID: [%1]; Radio ID: [%2]; +Data File: [%3] + + + + ERROR: No simulator libraries available. 错误:没有可用的模拟器库. - + Radio profile ID or Name to use for simulator. 用于模拟器的遥控器档案 ID 或名称. - + Radio type to simulate (usually defined in profile). 模拟的遥控器类型 (一般在遥控器档案中定义). - + show this help text 显示这个帮助文字 - - Usage: simulator [OPTION]... [EEPROM.BIN FILE] - 使用方法: simulator [OPTION]... [EEPROM.BIN FILE] - - - + Options: 选项: - - ERROR: Couldn't start simulator, missing radio/profile/EEPROM file. -Profile ID: [%1]; Radio ID: [%2] -EEPROM File: [%3] - 错误: 无法打开模拟器, 缺失遥控器/档案/EEPROM 文件. -档案 ID: [%1]; 遥控器 ID: [%2] -EEPROM 文件: [%3] - - - + ERROR: Radio profile or simulator firmware not found. Profile ID: [%1]; Radio ID: [%2] 错误: 未找到遥控器档案或模拟器固件. 档案 ID: [%1]; 遥控器 ID: [%2] - - ERROR: Simulator %1 not found - 错误: 未找到模拟器 %1 - - - - - + + Error opening file %1: %2. 打开文件错误 %1: %2. - - Error opening OTX archive %1. - 打开 OTX 存档错误 %1. - - - - mz_zip_reader_file_stat() failed! - mz_zip_reader_file_stat() 失败! - - - - - - Can't extract file %1 - 无法解压文件 %1 - - - + Error initializing OTX archive writer OTX 存档写入器初始化错误 - - - + Error adding %1 to OTX archive 将 %1 加入到 OTX 存档时出错 - + Error creating OTX archive 创建 OTX 存档时出错 - + + Error opening OTX archive %1 + 打开 OTX 存档错误 %1. {1?} + + + Error creating OTX file %1: %2. 创建 OTX 存档 %1时出错: %2. - + + Error reading %1: %2 + + + + + Cannot save EEPROM + + + + + + Cannot open file %1: +%2. + + + + + + Error writing file %1: %2. 写入文件错误 %1: %2. + + + Invalid binary EEPROM file %1 + + Thank you for upgrading to OpenTX 2.0. This is a major upgrade that adds and modifies a lot of things, so please make sure that you read release notes carefully to learn about the changes, and thoroughly check each of your models for proper function. @@ -8899,6 +8969,74 @@ Profile ID: [%1]; Radio ID: [%2] The OpenTX Team. 感谢你升级到OpenTX 2.0. 这是一个主要更新,新加入和修正了许多方面, 所以请确定你仔细阅读了版本发布说明来了解这些变化. 并且逐个检查每个模型都可以工作正常. + + + Conversion error on field %1 + + + + + + Models + Translators do NOT use accent for this, this is the default category name on Horus. + + + + + Select a data file + + + + + Select Data Directory + + + + + Select SD Card Image Folder + + + + + Can't extract RADIO/radio.bin + + + + + Can't extract RADIO/models.txt + + + + + Can't extract %1 + + + + + Unable to open %1: %2 + + + + + Invalid EEPROM file %1 + + + + + Invalid EEPROM File %1 + 无效的 EEPROM 文件 %1 + + + + Error opening file %1 in write mode: +%2. + + + + + Unable to find file %1! + 无法找到文件 %1! + QxtCommandOptions @@ -9064,6 +9202,14 @@ The OpenTX Team. + + RadioKnobWidget + + + Right-double-click to reset to center. + + + RadioNotFoundDialog @@ -9082,10 +9228,100 @@ The OpenTX Team. + + RadioOutputsWidget + + + Form + 表单 + + + + View: + + + + + Logical Switches + + + + + Global Variables + 全局变量 [Global Variables] + + + + Channel Outputs + + + + + L +o +g +i +c + + + + + G +l +o +b +a +l + + + + + C +h +a +n +n +e +l +s + + + + + RadioSwitchWidget + + + Latch/unlatch the momentary switch. + + + + + RawSwitch + + + ↑ + + + + + ↓ + + + + + - + + + + + ! + + + ReleaseNotesDialog - + Companion Release Notes Companion 版本发布说明 @@ -9300,7 +9536,7 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi SetupPanel - + Timer %1 计时器[Timer] %1 @@ -9314,433 +9550,841 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi - SimulatorDialog + SimulatedUIWidget - - F1 - + + Rotary encoder click + - - Show Help/Keymap - 显示帮助/快捷键 + + Take Screenshot + - - F4 - - - - - Open Telemetry Simulator - 启用回传模拟 - - - - F5 - - - - - Open Trainer Simulator - 启用教练功能模拟 - - - - F6 - - - - - Open Debug Output - 启用Debug输出 - - - - F7 - - - - - Reload Lua Scripts - 载入 Lua 脚本 - - - - Simulator Controls: - 模拟器控制: - - - - <tr><th>Key/Mouse</td><th>Action</td></tr> - - - - - Simulator Help - 模拟器帮助 - - - - Outputs - 输出 - - - - GVars - - - - - Firmware %1 error: %2 - 固件 %1 错误: %2 + + screenshot + Simulator LCD screenshot file name prefix + - SimulatorDialog9X + SimulatedUIWidget9X - - Companion Simulator - Companion 模拟器 - - - - BEEP - 蜂鸣 - - - - 9x Simulator - 9x 模拟器 - - - + UP/PG-UP - + - + [ UP ] - + - + DN/PG-DN - + - + [ DN ] - + - - LEFT/+ - + + RIGHT/+ + - + [ + ] - + - - RIGHT/- - + + LEFT/- + - + [ - ] - + - + ENTER/MOUSE-MID - + - + [ MENU ] - + - + DEL/BKSP/ESC - + - + [ EXIT ] - + - + WHEEL/PAD SCRL - + WHEEL/PAD SCRL - + [ UP ]/[ DN ] or Rotary Sel. - [ UP ]/[ DN ] 或转盘选择. + [ UP ]/[ DN ] 或转盘选择. - SimulatorDialogFlamenco + SimulatedUIWidgetX12 - - Companion Simulator - Companion 模拟器 - - - - Flamenco Simulator - Flamenco 模拟器 - - - - SimulatorDialogHorus - - - Companion Simulator - Companion 模拟器 - - - - PF4 - Telemetry Simulator - PF4 - 回传模拟 - - - - PF5 - Trainer Simulator - PF5 - 教练功能模拟 - - - - PF6 - Debug Console Window - PF6 - Debug终端窗口 - - - - PF7 - Reload Lua Scripts - PF7 重新载入 Lua 脚本 - - - - Horus Simulator - Horus 模拟器 - - - + PG-UP - + - + [ PgUp ] - + - + PG-DN - + - + [ PgDn ] - + - + UP - + - + [ MDL ] - + - + DN/DEL/BKSP - + - + [ RTN ] - + - + LEFT - + - + [ SYS ] - + - + RIGHT - + - + [ TELE ] - + - + WHEEL/PAD SCRL - + WHEEL/PAD SCRL - + Rotary Selector - 转盘按钮 + 转盘按钮 - + -/X - + - + Rotary UP - 转盘上 + 转盘上 - + +/C - + - + Rotary DOWN - 转盘下 + 转盘下 - + ENTER/MOUSE-MID - + - + Selector Press - 按下转盘按钮 + 按下转盘按钮 - SimulatorDialogTaranis + SimulatedUIWidgetX7 - - Companion Simulator - Companion 模拟器 + + Taranis X7 Simulator + - - S3 - - - - - S4 - - - - - Taranis Simulator - Taranis 模拟器 - - - - PF4 - Telemetry Simulator - PF4 - 回传模拟 - - - - PF5 - Trainer Simulator - PF5 - 教练功能模拟 - - - - PF6 - Debug Console Output - PF6 - Debug终端窗口 - - - - PF7 - Reload Lua Scripts - PF7 重新载入 Lua 脚本 - - - + PG-UP - + - - [ MENU ] - - - - - PG-DN - - - - + [ PAGE ] - + - + + PG-DN + + + + + [ MENU ] + + + + DEL/BKSP/ESC - + - + [ EXIT ] - + - - +/UP - - - - - [ + ] - - - - - -/DN - - - - - [ - ] - - - - - ENTER/MOUSE-MID - - - - - [ ENT ] - - - - + WHEEL/PAD SCRL - WHEEL/PAD SCRL + WHEEL/PAD SCRL - - [ + ]/[ - ] or Rotary Sel. - [ UP ]/[ DN ] 或转盘选择. + + Rotary Selector + 转盘按钮 + + + + -/UP + + + + + Rotary UP + 转盘上 + + + + +/DN + + + + + Rotary DOWN + 转盘下 + + + + ENTER/MOUSE-MID + + + + + Selector Press + 按下转盘按钮 + + + + SimulatedUIWidgetX9 + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + +/UP + + + + + [ + ] + + + + + -/DN + + + + + [ - ] + + + + + ENTER/MOUSE-MID + + + + + [ ENT ] + + + + + WHEEL/PAD SCRL + WHEEL/PAD SCRL + + + + [ + ]/[ - ] + + + + + SimulatedUIWidgetX9E + + + PG-UP + + + + + [ MENU ] + + + + + PG-DN + + + + + [ PAGE ] + + + + + DEL/BKSP/ESC + + + + + [ EXIT ] + + + + + WHEEL/PAD SCRL + WHEEL/PAD SCRL + + + + Rotary Selector + 转盘按钮 + + + + -/UP + + + + + Rotary UP + 转盘上 + + + + +/DN + + + + + Rotary DOWN + 转盘下 + + + + ENTER/MOUSE-MID + + + + + Selector Press + 按下转盘按钮 + + + + SimulatorMainWindow + + + OpenTx Simulator + + + + + View + + + + + Radio Window + + + + + Reload... + + + + + Tools + + + + + Toolbar + + + + + Reload Lua Scripts + 载入 Lua 脚本 + + + + Reload the Lua environment on the simulated radio. + + + + + F7 + + + + + Reload Radio Data + + + + + Reload all radio data without restarting the simulator. + + + + + F9 + + + + + Key Mapping + + + + + Show keyboard maping reference. + + + + + F1 + + + + + Joystick Settings + + + + + Open joystick configuration settings dialog. + + + + + F3 + + + + + LCD Screenshot + + + + + Save a screenshot of the current simulated LCD screen. + + + + + F8 + + + + + Dock In Main Window + + + + + Show the radio in the main window or as a separate "floating" window. + + + + + Menu Bar + + + + + Show or hide the top menu bar. + + + + + Alt+M + + + + + Constrain Width + + + + + Set radio widget width to be a fixed size. + + + + + Constrain Height + + + + + Set radio widget height to be a fixed size. + + + + + ERROR: Failed to create simulator interface, possibly missing or bad library. + + + + + Alt+T + + + + + Radio Outputs + + + + + F2 + + + + + Telemetry Simulator + 回传模拟器 + + + + F4 + + + + + Trainer Simulator + + + + + F5 + + + + + Debug Output + Debug 输出 + + + + F6 + + + + + Simulator Controls: + 模拟器控制: + + + + <tr><th>Key/Mouse</td><th>Action</td></tr> + + + + + Simulator Help + 模拟器帮助 + + + + SimulatorStartupDialog + + + OpenTX Simulator - Startup Options + + + + + Simulator Startup Options: + 模拟器启动选项: + + + + Radio Profile: + + + + + Existing radio profiles are shown here.<br /> +Create or edit profiles using the Companion application. + + + + + Radio Type: + 遥控器型号: + + + + Existing radio simulators are shown here.<br /> +The radio type specified in the selected profile is used by default. + + + + + Data Source: + + + + + Data File: + + + + + Data Folder: + + + + + SD Image Path: + + + + + Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> +<b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! + + + + + Select data file... + + + + + + + ... + + + + + Directory containing RADIO and MODELS folders to use.<br /> +New folder(s) with default radio/model will be created here if necessary. + + + + + Select data folder... + + + + + Directory containing the SD card image to use.<br/> +The default is configured in the chosen Radio Profile. + + + + + Select SD card image folder... + + + + + Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. + + + + + File + 文件 + + + + Folder + + + + + SD Path + + + + + All files (*.*) + 所有文件 (*.*) + + + + SimulatorWidget + + + Companion Simulator + Companion 模拟器 + + + + Radio Simulator (%1) + + + + + Could not determine startup data source. + + + + + Could not load data, possibly wrong format. + + + + + Data Load Error + + + + + Invalid startup data provided. Plese specify a proper file/path. + + + + + Simulator Startup Error + + + + + Error saving data: could open file for writing: '%1' + + + + + Error saving data: could not get data from simulator interface. + + + + + An unexpected error occurred while attempting to save radio data to file '%1'. + + + + + Data Save Error + + + + + Warning + + + + + Cannot open joystick, joystick disabled + 无法打开游戏杆, 游戏杆功能禁用 + + + + Firmware %1 error: %2 + 固件 %1 错误: %2 + + + + SliderWidget + + + Right-double-click to reset to center. + @@ -9810,30 +10454,6 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi 写入 %1 - - T - - - Simulating Radio (%1) - 模拟遥控器 (%1) - - - - - Warning - 警告 - - - - Joystick enabled but not configured correctly - 游戏杆功能启用, 但尚未正确配置 - - - - Cannot open joystick, joystick disabled - 无法打开游戏杆, 游戏杆功能禁用 - - TailPage @@ -10224,99 +10844,99 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi TelemetryPanel - + Telemetry screen %1 回传屏幕 %1 - + FrSky S.PORT - + FrSky D - + FrSky D (cable) - + Low Alarm 低告警 - + Critical Alarm 紧急告警 - + Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (不支持) - + Alti 高度 - + Alti+ 最大高度 - + VSpeed 垂直速度 - - - + + + A1 A1 模拟值1 - - - + + + A2 A2 模拟值2 - - + + A3 A3 模拟值3 - - + + A4 A4 模拟值4 - - + + FAS FAS - + Cells 锂电总电压 - + --- @@ -10507,81 +11127,91 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi + mW + + + + dBm - + RPM - + g - + ° - + + Rad + + + + mL - + US fl.Oz. - + Precision 精确度 - + Ratio 比例 - + Blades 旋翼数 - + Offset 偏移 - + Multiplier 系数 - + Auto Offset 自动偏移 - + Filter 过滤器 - + Persistent 保持 - + Positive 正向 - + Logs LOG记录 @@ -10589,22 +11219,22 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi TelemetrySensorPanel - + Lowest 最低 - + Cell %1 第%1片 - + Highest 最高 - + Delta 每片电压差 @@ -10617,309 +11247,321 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi 回传模拟器 - + When enabled, sends any non-blank values as simulated telemetry data. 如果允许 =, 发送任何非空值作为回传模拟数据. - + Simulate 模拟 - + Replay SD Log File 重播 SD Log 文件 - + + Replay rate + + + + |> - + <| - + > - + <- - + X - + + 1/5x + 1/5x + + + + 5x + 5x + + + No Log File Currently Loaded 现在没有载入任何 log 文件 - + Load 载入 - - Replay rate (1/5 -> 5x) - 播放速度 (1/5 -> 5x) - - - + Row # Timestamp 行数 时间戳 - + RxBt RxBt 接收机电压 - - - + + + V / ratio 伏 / 比值 - - - - - - - - - - - - - + + + + + + + + + + + + + <html><head/><body><p><br/></p></body></html> - + VFAS VFAS FAS传感器电压 - - + + Lat,Lon +(dec.deg.) + + + + + dd-MM-yyyy +hh:mm:ss + + + + + Volts V - + RSSI RSSI 信号强度 - + Db - + Curr Curr 电流 - + Amps A - + SWR SWR 天线健康值 - + Cels Cells 锂电电压 - + A1 A1 模拟值1 - + A2 A2 模拟值2 - + ASpd ASpd 空速 - - + + km/h - + A3 A3 模拟值3 - + GAlt GALT GPS高度 - - + + Meters m - + A4 A4 模拟值4 - + GSpd GSpd GPS速度 - + Tmp1 Tmp1 温度1 - + Deg. C ℃ - + Hdg Hdg 航向角 - + Degrees ° - + Tmp2 Tmp2 温度2 - + °C - + Date Date 日期 - - dd-MM-yyyy hh:mm:ss - - - - - + + RPM Rpm - + GPS - - Lat,Lon (dec.deg.) - 纬度,经度 (用小数表示) - - - + Fuel Fule 燃油 - + % - + AccX AccX X轴加速度 - - - + + + G G - + Fuel Qty Fule Qty 油量 - + ml - + AccY AccY Y轴加速度 - + VSpd VSpd 垂直速度 - + m/s - + AccZ AccZ Z轴加速度 - + Alt Alt 高度 - + Log File Log 文件 - + LOG Files (*.csv) LOG文件 (*.csv) - + ERROR - invalid file 错误 无效的文件 @@ -11175,37 +11817,37 @@ Timestamp TimerPanel - + Silent 静音 [Silent] - + Beeps 蜂鸣 [Beeps] - + Voice 语音 [Voice] - + Haptic 振动 [Haptic] - + Not persistent 关机不记忆 [Not persistent] - + Persistent (flight) 关机记忆 随Flight重设 [Flight] - + Persistent (manual reset) 关机记忆 手动重设 [manual reset] @@ -11336,11 +11978,29 @@ Timestamp TrainerSimulator - + Trainer simulator 教练功能模拟 + + TreeModel + + + Index + 模型编号 + + + + Name + + + + + Size + 占用内存 + + VTailPage @@ -11357,24 +12017,44 @@ Timestamp VirtualJoystickWidget - - Hold Y - 保持 Y + + Hld Y + - + + Hold Vertical stick position. + + + + Fix Y 固定 Y - + + Prevent Vertical movement of stick. + + + + Fix X 固定 X - - Hold X - 保持 X + + Prevent Horizontal movement of stick. + + + + + Hld X + + + + + Hold Horizontal stick position. + @@ -11887,29 +12567,29 @@ v4.1版电路板应为m2560 AVRDUDE 配置 - - - + + + Select Location 选择位置 - + List available programmers 列出可用的编程器 - + Avrdude help AVRDUDE 帮助 - + Companion Companion - + <b><u>WARNING!</u></b><br>Normally CPU type is automatically selected according to the chosen firmware.<br>If you change the CPU type the resulting eeprom could be inconsistent. <b><u>警告</u></b><br>一般来说CPU类型将会根据固件文件自动选择<br>如果你更改CPU类型, EEPROM可能会不兼容. @@ -12071,224 +12751,155 @@ v4.1版电路板应为m2560 配置游戏杆 - + Ch2 游戏杆通道2 - - - - - - - - - Not Assigned - 没有指定 - - - - - - - - - - - Right Vertical - 右摇杆上下方向 - - - - - - - - - - - Right Horizontal - 右摇杆水平方向 - - - - - - - - - - - Left Vertical - 左摇杆垂直方向 - - - - - - - - - - - Left Horizontal - 左摇杆水平方向 - - - - - - - - - - - P1 - - - - - - - - - - - - P2 - - - - - - - - - - - - P3/LS - - - - - - - - - - - - RS - - - - + Ch1 游戏杆通道1 - + Ch4 游戏杆通道4 - + Ch6 游戏杆通道6 - + Ch3 游戏杆通道3 - + Ch5 游戏杆通道5 - + Ch7 游戏杆通道7 - + Ch8 游戏杆通道8 - + Instructions 指令 - + + Enable + + + + Cancel 取消 - + + Back + + + + + Start + 开始通道 [CH] + + + Next 下一步 - + Ok 确定 - - Move sticks and pots in every direction making full movement -Press next when finished - 移动每个摇杆和旋钮到极限位置 -完成后按"下一步"按钮 + + Not Assigned + + + + + Stick + + + + + Knob/Slider %1 + + + + + No joysticks found + 找不到游戏杆 - Error 错误 - + Cannot open joystick. 找不到游戏杆. - + + Press the Start button to start the stick range calibration procedure. +You may change the channel assignments or inversion at any time. + + + + + Move sticks and pots in every direction making full movement +Press Next when finished + + + + Place sticks and pots in middle position. -Press next when done - 将摇杆和旋钮置于中间位置. -完成后按"下一步"按钮 +Press Next when done + - + Map joystick channels to controls using comboboxes. -Press next when done - 使用选框将游戏杆通道映射到摇杆. -完成后按"下一步"按钮 +Press Next when done. + - - Check inversion checkbox to get maximum at top-right position. -Press next when done - 勾选反向选框以便达到右上方最大值. -完成后按"下一步"按钮 + + Check inversion checkbox to if necessary to reverse direction. +Press Next when done. + - - Press ok to save configuration -Press cancel to abort joystick calibration - 按"确定"按钮保存游戏杆校准 -按"取消"按钮取消游戏杆校准 -完成后按"下一步"按钮 + + Press OK to save configuration +Press Cancel to abort joystick calibration without saving. + - - Duplicated stick assignment - 复制游戏杆设定 + + Warning + + + + + Calibration not complete, save anyway? + From 10c6c9a1ece0c8414b66f42fb5e4dcf350382e5f Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Wed, 29 Mar 2017 15:43:16 +0200 Subject: [PATCH 059/203] Add DM002 multipl protocol (#4716) --- companion/src/modelprinter.cpp | 2 +- companion/src/multiprotocols.cpp | 1 - companion/src/radiodata.h | 5 +++-- radio/src/gui/gui_common_arm.cpp | 1 - radio/src/myeeprom.h | 5 +++-- radio/src/translations/cz.h.txt | 2 +- radio/src/translations/de.h.txt | 2 +- radio/src/translations/en.h.txt | 2 +- radio/src/translations/es.h.txt | 2 +- radio/src/translations/fi.h.txt | 2 +- radio/src/translations/fr.h.txt | 2 +- radio/src/translations/it.h.txt | 2 +- radio/src/translations/nl.h.txt | 2 +- radio/src/translations/pl.h.txt | 2 +- radio/src/translations/pt.h.txt | 2 +- radio/src/translations/se.h.txt | 2 +- 16 files changed, 18 insertions(+), 18 deletions(-) diff --git a/companion/src/modelprinter.cpp b/companion/src/modelprinter.cpp index a24cabb11..79d26dbd0 100644 --- a/companion/src/modelprinter.cpp +++ b/companion/src/modelprinter.cpp @@ -135,7 +135,7 @@ QString ModelPrinter::printMultiRfProtocol(int rfProtocol, bool custom) static const char *strings[] = { "FlySky", "Hubsan", "FrSky", "Hisky", "V2x2", "DSM", "Devo", "YD717", "KN", "SymaX", "SLT", "CX10", "CG023", "Bayang", "ESky", "MT99XX", "MJXQ", "Shenqi", "FY326", "SFHSS", "J6 PRO","FQ777","Assan","Hontai","OLRS", - "FlySky AFHDS2A", "Q2x2", "Walkera", "Q303", "GW008" + "FlySky AFHDS2A", "Q2x2", "Walkera", "Q303", "GW008", "DM002" }; if (custom) return "Custom - proto " + QString::number(rfProtocol); diff --git a/companion/src/multiprotocols.cpp b/companion/src/multiprotocols.cpp index 502abeed2..980ce5fa7 100644 --- a/companion/src/multiprotocols.cpp +++ b/companion/src/multiprotocols.cpp @@ -85,7 +85,6 @@ const Multiprotocols multiProtocols { { MM_RF_PROTO_Q2X2, STR_SUBTYPE_Q2X2, 2, nullptr }, { MM_RF_PROTO_WK_2X01, STR_SUBTYPE_WK2x01, 5, nullptr }, { MM_RF_PROTO_Q303, STR_SUBTYPE_Q303, 3, nullptr }, - { MM_RF_PROTO_GW08, NO_SUBTYPE, 0, nullptr }, { MM_RF_CUSTOM_SELECTED, STR_SUBTYPE_CUSTOM, 7, STR_MULTI_OPTION }, //Sential and default for protocols not listed above (MM_RF_CUSTOM is 0xff() diff --git a/companion/src/radiodata.h b/companion/src/radiodata.h index acf5f35fd..7a099220f 100644 --- a/companion/src/radiodata.h +++ b/companion/src/radiodata.h @@ -792,8 +792,9 @@ enum MultiModuleRFProtocols { MM_RF_PROTO_Q2X2, MM_RF_PROTO_WK_2X01, MM_RF_PROTO_Q303, - MM_RF_PROTO_GW08, - MM_RF_PROTO_LAST=MM_RF_PROTO_GW08 + MM_RF_PROTO_GW008, + MM_RF_PROTO_DM002, + MM_RF_PROTO_LAST=MM_RF_PROTO_DM002 }; enum TrainerProtocol { diff --git a/radio/src/gui/gui_common_arm.cpp b/radio/src/gui/gui_common_arm.cpp index 8a252aa3f..02f18579d 100644 --- a/radio/src/gui/gui_common_arm.cpp +++ b/radio/src/gui/gui_common_arm.cpp @@ -674,7 +674,6 @@ const mm_protocol_definition multi_protocols[] = { { MM_RF_PROTO_Q2X2, STR_SUBTYPE_Q2X2, 2, nullptr }, { MM_RF_PROTO_WK_2X01, STR_SUBTYPE_WK2x01, 5, nullptr }, { MM_RF_PROTO_Q303, STR_SUBTYPE_Q303, 3, nullptr }, - { MM_RF_PROTO_GW08, NO_SUBTYPE, 0, nullptr }, { MM_RF_CUSTOM_SELECTED, NO_SUBTYPE, 7, STR_MULTI_OPTION }, //Sential and default for protocols not listed above (MM_RF_CUSTOM is 0xff() diff --git a/radio/src/myeeprom.h b/radio/src/myeeprom.h index 904941b44..1466557e2 100644 --- a/radio/src/myeeprom.h +++ b/radio/src/myeeprom.h @@ -531,8 +531,9 @@ enum MultiModuleRFProtocols { MM_RF_PROTO_Q2X2, MM_RF_PROTO_WK_2X01, MM_RF_PROTO_Q303, - MM_RF_PROTO_GW08, - MM_RF_PROTO_LAST= MM_RF_PROTO_GW08 + MM_RF_PROTO_GW008, + MM_RF_PROTO_DM002, + MM_RF_PROTO_LAST= MM_RF_PROTO_DM002 }; enum MMDSM2Subtypes { diff --git a/radio/src/translations/cz.h.txt b/radio/src/translations/cz.h.txt index 6a027ff02..de38bbd6f 100644 --- a/radio/src/translations/cz.h.txt +++ b/radio/src/translations/cz.h.txt @@ -107,7 +107,7 @@ #define TR_DSM_PROTOCOLS "LP45""DSM2""DSMX" #define LEN_MULTI_PROTOCOLS "\006" -#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0" +#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0""DM002\0" #define TR_MULTI_CUSTOM "Custom" diff --git a/radio/src/translations/de.h.txt b/radio/src/translations/de.h.txt index 4ff09ae5b..1c392d226 100644 --- a/radio/src/translations/de.h.txt +++ b/radio/src/translations/de.h.txt @@ -112,7 +112,7 @@ #define TR_DSM_PROTOCOLS "LP45""DSM2""DSMX" //LP45 =Low Power 4 und 5 Kanal #define LEN_MULTI_PROTOCOLS "\006" -#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2""Walk.\0""Q303\0 ""GW008\0" +#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2""Walk.\0""Q303\0 ""GW008\0""DM002\0" #define TR_MULTI_CUSTOM "Custom" diff --git a/radio/src/translations/en.h.txt b/radio/src/translations/en.h.txt index 0640bef7b..96ef02ade 100644 --- a/radio/src/translations/en.h.txt +++ b/radio/src/translations/en.h.txt @@ -111,7 +111,7 @@ #define TR_DSM_PROTOCOLS "LP45""DSM2""DSMX" #define LEN_MULTI_PROTOCOLS "\006" -#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0" +#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0""DM002\0" #define TR_MULTI_CUSTOM "Custom" diff --git a/radio/src/translations/es.h.txt b/radio/src/translations/es.h.txt index ffe32abd1..fdef4d0b8 100644 --- a/radio/src/translations/es.h.txt +++ b/radio/src/translations/es.h.txt @@ -107,7 +107,7 @@ #define TR_DSM_PROTOCOLS "LP45""DSM2""DSMX" #define LEN_MULTI_PROTOCOLS "\006" -#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0" +#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0""DM002\0" #define TR_MULTI_CUSTOM "Custom" diff --git a/radio/src/translations/fi.h.txt b/radio/src/translations/fi.h.txt index 9bccb0ba2..61b6c7596 100644 --- a/radio/src/translations/fi.h.txt +++ b/radio/src/translations/fi.h.txt @@ -107,7 +107,7 @@ #define TR_DSM_PROTOCOLS "LP45""DSM2""DSMX" #define LEN_MULTI_PROTOCOLS "\006" -#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0" +#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0""DM002\0" #define TR_MULTI_CUSTOM "Custom" diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index a208b4dd3..23fd21b1b 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -107,7 +107,7 @@ #define TR_DSM_PROTOCOLS "LP45""DSM2""DSMX" #define LEN_MULTI_PROTOCOLS "\006" -#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0" +#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0""DM002\0" #define TR_MULTI_CUSTOM "Perso" diff --git a/radio/src/translations/it.h.txt b/radio/src/translations/it.h.txt index 413eac8b4..044b9f484 100644 --- a/radio/src/translations/it.h.txt +++ b/radio/src/translations/it.h.txt @@ -107,7 +107,7 @@ #define TR_DSM_PROTOCOLS "LP45""DSM2""DSMX" #define LEN_MULTI_PROTOCOLS "\006" -#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0" +#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0""DM002\0" #define TR_MULTI_CUSTOM "Custom" diff --git a/radio/src/translations/nl.h.txt b/radio/src/translations/nl.h.txt index 2a8cb55a5..b061bc961 100644 --- a/radio/src/translations/nl.h.txt +++ b/radio/src/translations/nl.h.txt @@ -112,7 +112,7 @@ #define TR_DSM_PROTOCOLS "LP45""DSM2""DSMX" #define LEN_MULTI_PROTOCOLS "\006" -#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0" +#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0""DM002\0" #define TR_MULTI_CUSTOM "Custom" diff --git a/radio/src/translations/pl.h.txt b/radio/src/translations/pl.h.txt index 59a6321cb..3f6514fb8 100644 --- a/radio/src/translations/pl.h.txt +++ b/radio/src/translations/pl.h.txt @@ -108,7 +108,7 @@ #define TR_DSM_PROTOCOLS "LP45""DSM2""DSMX" #define LEN_MULTI_PROTOCOLS "\006" -#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0" +#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0""DM002\0" #define TR_MULTI_CUSTOM "Custom" diff --git a/radio/src/translations/pt.h.txt b/radio/src/translations/pt.h.txt index 5ebf9cb70..ee124581e 100644 --- a/radio/src/translations/pt.h.txt +++ b/radio/src/translations/pt.h.txt @@ -107,7 +107,7 @@ #define TR_DSM_PROTOCOLS "LP45""DSM2""DSMX" #define LEN_MULTI_PROTOCOLS "\006" -#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0" +#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0""DM002\0" #define TR_MULTI_CUSTOM "Custom" diff --git a/radio/src/translations/se.h.txt b/radio/src/translations/se.h.txt index 28ea212da..622e94763 100644 --- a/radio/src/translations/se.h.txt +++ b/radio/src/translations/se.h.txt @@ -107,7 +107,7 @@ #define TR_DSM_PROTOCOLS "LP45""DSM2""DSMX" #define LEN_MULTI_PROTOCOLS "\006" -#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0" +#define TR_MULTI_PROTOCOLS "FlySky""Hubsan""FrSky\0""Hisky\0""V2x2\0 ""DSM\0 ""Devo\0 ""YD717\0""KN\0 ""SymaX\0""SLT\0 ""CX10\0 ""CG023\0""Bayang""ESky\0 ""MT99XX""MJXQ\0 ""Shenqi""FY326\0""SFHSS\0""J6 PRO""FQ777\0""Assan\0""Hontai""OLRS\0 ""FS 2A\0""Q2x2\0 ""Walk.\0""Q303\0 ""GW008\0""DM002\0" #define TR_MULTI_CUSTOM "Custom" From 6709c55fea5b9459dab5dc485e755ba1a3bbcdc1 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Wed, 29 Mar 2017 09:44:51 -0400 Subject: [PATCH 060/203] [Simulator] Fix timing issues in all AVR simulators on Windows (MSVC) (#4709) * [simpgmspace] Fix 2MHz and 16KHz timers on MSVC builds (fixes LCD/key/switch response delay on all AVR simulators); Introduce experimental use of Qt to simplify x-platform code (disabled by default). * Qt timer scaling fix. --- radio/src/targets/simu/simpgmspace.cpp | 76 +++++++++++++++----------- 1 file changed, 43 insertions(+), 33 deletions(-) diff --git a/radio/src/targets/simu/simpgmspace.cpp b/radio/src/targets/simu/simpgmspace.cpp index c53ec2dd1..c9ad8b0d3 100644 --- a/radio/src/targets/simu/simpgmspace.cpp +++ b/radio/src/targets/simu/simpgmspace.cpp @@ -18,6 +18,13 @@ * GNU General Public License for more details. */ +#if defined(QT_CORE_LIB) && 0 // experimental + #define SIMPGMSPC_USE_QT 1 + #include +#else + #define SIMPGMSPC_USE_QT 0 +#endif + #include "opentx.h" #include #include @@ -74,32 +81,17 @@ void toplcdOff() { } -uint16_t getTmr16KHz() +U64 microsTimer(void) { -#if defined(_MSC_VER) - return get_tmr10ms() * 16; -#else - struct timeval tv; - gettimeofday(&tv, NULL); - return tv.tv_usec * 2 / 125; -#endif -} +#if SIMPGMSPC_USE_QT -uint16_t getTmr2MHz() -{ -#if defined(_MSC_VER) - return get_tmr10ms() * 125; -#else - struct timeval tv; - gettimeofday(&tv, NULL); - return tv.tv_usec * 2; -#endif -} + static QElapsedTimer ticker; + if (!ticker.isValid()) + ticker.start(); + return ticker.nsecsElapsed() / 1000; + +#elif defined(_MSC_VER) -// return 2ms resolution to match CoOS settings -U64 CoGetOSTime(void) -{ -#if defined(_MSC_VER) static double freqScale = 0.0; static LARGE_INTEGER firstTick; LARGE_INTEGER newTick; @@ -108,23 +100,41 @@ U64 CoGetOSTime(void) LARGE_INTEGER frequency; // get ticks per second QueryPerformanceFrequency(&frequency); - // 2ms resolution - freqScale = 500.0 / frequency.QuadPart; + // 1us resolution + freqScale = 1e6 / frequency.QuadPart; // init timer QueryPerformanceCounter(&firstTick); - TRACE_SIMPGMSPACE("CoGetOSTime() init: first tick = %llu @ %llu Hz", firstTick.QuadPart, frequency.QuadPart); + TRACE_SIMPGMSPACE("microsTimer() init: first tick = %llu @ %llu Hz: %g", firstTick.QuadPart, frequency.QuadPart); } // read the timer QueryPerformanceCounter(&newTick); // compute the elapsed time return U64((newTick.QuadPart - firstTick.QuadPart) * freqScale); - //return GetTickCount64() / 2; // only 10-16ms typical resolution -#else + +#else // GNUC + auto now = std::chrono::steady_clock::now(); - return (U64) std::chrono::duration_cast(now.time_since_epoch()).count() / 2; + return (U64) std::chrono::duration_cast(now.time_since_epoch()).count(); + #endif } +uint16_t getTmr16KHz() +{ + return microsTimer() * 2 / 125; +} + +uint16_t getTmr2MHz() +{ + return microsTimer() * 2; +} + +// return 2ms resolution to match CoOS settings +U64 CoGetOSTime(void) +{ + return microsTimer() * 500; +} + void simuInit() { #if defined(STM32) @@ -135,11 +145,11 @@ void simuInit() simuSetSwitch(i, 0); simuSetKey(i, false); // a little dirty, but setting keys that don't exist is perfectly OK here } - for (int i=0; i<(NUM_STICKS+NUM_AUX_TRIMS)*2; i++) + for (int i=0; i < (NUM_STICKS+NUM_AUX_TRIMS)*2; i++) simuSetTrim(i, false); -#if defined(ROTARY_ENCODER_NAVIGATION) - for (uint8_t i=0; i Date: Wed, 29 Mar 2017 09:46:48 -0400 Subject: [PATCH 061/203] [build] Add "all-libsimulators" target to build all simulator flavors at once. (#4710) * [build] Add "all-libsimulators" target to build all simulator flavors at once. * [build] Refine the "all simulators" target setup and deal with GNU 'make' parallelism issue (ninja=faster); rename to "all-simu-libs". --- radio/src/CMakeLists.txt | 1 + radio/src/targets/9x/CMakeLists.txt | 1 + radio/src/targets/gruvin9x/CMakeLists.txt | 1 + radio/src/targets/simu/CMakeLists.txt | 22 ++++++++++++++++++++++ 4 files changed, 25 insertions(+) diff --git a/radio/src/CMakeLists.txt b/radio/src/CMakeLists.txt index f2a7f145c..f8b1773e3 100644 --- a/radio/src/CMakeLists.txt +++ b/radio/src/CMakeLists.txt @@ -96,6 +96,7 @@ elseif(PCB STREQUAL 9X2561) set(MCU atmega2561) string(TOLOWER ${PCB} FLAVOUR) set(EEPROM EEPROM_RLC) + set(SDCARD NO) add_definitions(-DEEPROM_VARIANT=${M2561_VARIANT}) set(GUI_DIR 128x64) set(TARGET_DIR 9x) diff --git a/radio/src/targets/9x/CMakeLists.txt b/radio/src/targets/9x/CMakeLists.txt index 1e0a99b70..67131794c 100644 --- a/radio/src/targets/9x/CMakeLists.txt +++ b/radio/src/targets/9x/CMakeLists.txt @@ -6,6 +6,7 @@ set(AVRDUDE_MCU m64) string(TOLOWER ${PCB} FLAVOUR) set(EEPROM_VARIANT_NEEDED ON) set(EEPROM EEPROM_RLC) +set(SDCARD NO) set(GUI_DIR 128x64) set(TARGET_DIR 9x) set(FIRMWARE_DEPENDENCIES ${FIRMWARE_DEPENDENCIES} 9x_bitmaps) diff --git a/radio/src/targets/gruvin9x/CMakeLists.txt b/radio/src/targets/gruvin9x/CMakeLists.txt index 311b7685d..158cba68f 100644 --- a/radio/src/targets/gruvin9x/CMakeLists.txt +++ b/radio/src/targets/gruvin9x/CMakeLists.txt @@ -4,6 +4,7 @@ set(AVRDUDE_MCU m2560) string(TOLOWER ${PCB} FLAVOUR) set(EEPROM EEPROM_RLC) add_definitions(-DEEPROM_VARIANT=0) +set(SDCARD NO) set(GUI_DIR 128x64) set(TARGET_DIR gruvin9x) set(FIRMWARE_DEPENDENCIES ${FIRMWARE_DEPENDENCIES} 9x_bitmaps) diff --git a/radio/src/targets/simu/CMakeLists.txt b/radio/src/targets/simu/CMakeLists.txt index c72cdb85e..5c5ea5234 100644 --- a/radio/src/targets/simu/CMakeLists.txt +++ b/radio/src/targets/simu/CMakeLists.txt @@ -32,6 +32,28 @@ if(Qt5Widgets_FOUND) target_link_libraries(${SIMULATOR_TARGET} ${SDL_LIBRARY}) qt5_use_modules(${SIMULATOR_TARGET} Core) add_custom_target(libsimulator DEPENDS ${SIMULATOR_TARGET}) + + # Prepare the "all-simu-libs" target to build simulator libraries for *every* supported PCB type (PCB_TYPES list) + # (a fast build machine or corresponding amount of patience is recommended for this target). + if(${CMAKE_GENERATOR} MATCHES ".*Unix Makefiles$") + # Ensure parallel builds with GCC make (try with MAKEFLAGS but this seems to be getting clobbered somewhere). + # otherwise 'make' may complain: "warning: jobserver unavailable: using -j1..." and build single-threaded. (Ninja always rocks this.) + set(mkflags "$ENV{MAKEFLAGS}") + if (mkflags STREQUAL "") + set(mkflags "-j") + endif() + endif() + set(all_libs_cmd ${CMAKE_COMMAND} -E echo "Building all simulator libraries") + foreach(pcb ${PCB_TYPES}) + set(pcbrev "") + if(pcb STREQUAL SKY9X) + set(pcbrev "-DPCBREV=REVC") + elseif(pcb STREQUAL X12S) + set(pcbrev "-DPCBREV=13") + endif() + set(all_libs_cmd ${all_libs_cmd} && ${CMAKE_COMMAND} -DPCB=${pcb} ${pcbrev} -Wno-dev ${CMAKE_SOURCE_DIR} ${CMAKE_BINARY_DIR} && ${CMAKE_COMMAND} --build . --target libsimulator -- ${mkflags}) + endforeach() + add_custom_target(all-simu-libs COMMAND ${all_libs_cmd} USES_TERMINAL WORKING_DIRECTORY ${CMAKE_BINARY_DIR}) endif() if(WIN32) From 443d75c0ac92d3db809b8c1ed55df3977e64961c Mon Sep 17 00:00:00 2001 From: 3djc Date: Wed, 29 Mar 2017 21:10:29 +0200 Subject: [PATCH 062/203] Make default category translatable (with dev warning) (#4712) --- companion/src/mdichild.cpp | 3 ++- companion/src/modeledit/modeledit.cpp | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/companion/src/mdichild.cpp b/companion/src/mdichild.cpp index 8b8eb00f1..b64492a20 100644 --- a/companion/src/mdichild.cpp +++ b/companion/src/mdichild.cpp @@ -415,7 +415,8 @@ void MdiChild::generalEdit() void MdiChild::categoryAdd() { - CategoryData category("New category"); + /*: Translators do NOT use accent for this, this is the default category name on Horus. */ + CategoryData category(qPrintable(tr("New category"))); radioData.categories.push_back(category); setModified(); emit copyAvailable(false); // workaround : nothing is selected after model creation diff --git a/companion/src/modeledit/modeledit.cpp b/companion/src/modeledit/modeledit.cpp index 8edae5a27..4e2791211 100644 --- a/companion/src/modeledit/modeledit.cpp +++ b/companion/src/modeledit/modeledit.cpp @@ -114,7 +114,8 @@ void ModelEdit::launchSimulation() { RadioData * simuData = new RadioData(); simuData->generalSettings = generalSettings; - CategoryData category("Models"); + /*: Translators do NOT use accent for this, this is the default category name on Horus. */ + CategoryData category(qPrintable(tr("Models"))); simuData->categories.push_back(category); if (simuData->models.size() == 0) { simuData->models.push_back(model); From 361b2b707ff6df0fbc8a09df5d546d067f1827af Mon Sep 17 00:00:00 2001 From: 3djc Date: Thu, 30 Mar 2017 08:15:58 +0200 Subject: [PATCH 063/203] Do not recompile if firmware is already there Always print filename on compile error so that the email handler can attach the error log --- radio/util/build-firmware.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/radio/util/build-firmware.py b/radio/util/build-firmware.py index d73d1d67e..86d5bf64b 100755 --- a/radio/util/build-firmware.py +++ b/radio/util/build-firmware.py @@ -202,6 +202,7 @@ def build_firmware(path): file(outpath, "a").write("\n".join(cmd) + output + error) else: file(errpath, "w").write(output + error) + print filename exit(COMPILATION_ERROR) # Launch make @@ -212,6 +213,7 @@ def build_firmware(path): file(outpath, "a").write(output + error) else: file(errpath, "w").write(output + error) + print filename exit(COMPILATION_ERROR) if what == "firmware": @@ -228,6 +230,7 @@ def build_firmware(path): shutil.move(target, path) if os.path.isfile(errpath): + print filename exit(COMPILATION_ERROR) lockpath = path + ".lock" @@ -236,7 +239,11 @@ try: with lock.acquire(timeout = 60*60): if not os.path.isfile(path): build_firmware(path) + else: + print filename + exit(0) except filelock.Timeout: + print filename exit(COMPILATION_ERROR) print filename From 89bfd6dcf4e12917336807df31bc80bd9ef0f46b Mon Sep 17 00:00:00 2001 From: 3djc Date: Thu, 30 Mar 2017 08:43:50 +0200 Subject: [PATCH 064/203] Earlier is better --- radio/util/build-firmware.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/radio/util/build-firmware.py b/radio/util/build-firmware.py index 86d5bf64b..da3da657c 100755 --- a/radio/util/build-firmware.py +++ b/radio/util/build-firmware.py @@ -233,15 +233,16 @@ if os.path.isfile(errpath): print filename exit(COMPILATION_ERROR) +if os.path.isfile(path): + print filename + exit(0) + lockpath = path + ".lock" lock = filelock.FileLock(lockpath) try: with lock.acquire(timeout = 60*60): if not os.path.isfile(path): build_firmware(path) - else: - print filename - exit(0) except filelock.Timeout: print filename exit(COMPILATION_ERROR) From 965849ee41755fc2c6ef77d458212f72aa0b47bd Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Fri, 31 Mar 2017 07:53:40 +0200 Subject: [PATCH 065/203] Small progress on German translations (#4719) --- companion/src/multiprotocols.cpp | 2 +- companion/src/translations/companion_de.ts | 336 +++++++++++---------- 2 files changed, 170 insertions(+), 168 deletions(-) diff --git a/companion/src/multiprotocols.cpp b/companion/src/multiprotocols.cpp index 980ce5fa7..602075284 100644 --- a/companion/src/multiprotocols.cpp +++ b/companion/src/multiprotocols.cpp @@ -25,7 +25,7 @@ #define STR_MULTI_SUBTYPE QT_TRANSLATE_NOOP("Multiprotocols", "Subtype") #define STR_MULTI_VIDFREQ QT_TRANSLATE_NOOP("Multiprotocols", "Video TX frequency") -#define STR_MULTI_RFTUNE QT_TRANSLATE_NOOP("Multiprotocols", "C2500 frequency fine tune") +#define STR_MULTI_RFTUNE QT_TRANSLATE_NOOP("Multiprotocols", "CC2500 frequency fine tune") #define STR_MULTI_TELEMETRY QT_TRANSLATE_NOOP("Multiprotocols", "Telemetry") #define STR_MULTI_RFPOWER QT_TRANSLATE_NOOP("Multiprotocols", "Radio output power") #define STR_MULTI_SERVOFREQ QT_TRANSLATE_NOOP("Multiprotocols", "Servo output frequency") diff --git a/companion/src/translations/companion_de.ts b/companion/src/translations/companion_de.ts index 507812dc9..c47361872 100644 --- a/companion/src/translations/companion_de.ts +++ b/companion/src/translations/companion_de.ts @@ -4111,6 +4111,52 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt Create a new Models and Settings file Erzeuge eine neue Modell-und Einstellungen-Datei + + + Not enough flash available on this board for all the selected options + + + + + Compilation server temporary failure, try later + + + + + Compilation error + + + + + Invalid firmware + + + + + Invalid board + + + + + Invalid language + + + + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + + + + + Models and Settings read + + + + + + This function is not yet implemented + + @@ -4147,6 +4193,16 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt Paste Model Einfüge Modell + + + Use default system language. + + + + + Use %1 language (some translations may not be complete). + + Classical @@ -4367,36 +4423,6 @@ Do you want to download it now? We recommend you view the release notes using the button below to learn about any changes that may be important to you. - - - Not enough flash available on this board for all the selected options - - - - - Compilation server temporary failure, try later - - - - - Compilation error - - - - - Invalid firmware - - - - - Invalid board - - - - - Invalid language - - A new version of %1 firmware is available: @@ -4415,11 +4441,6 @@ We recommend you view the release notes using the button below to learn about an Companion Companion - - - Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. - - @@ -4432,17 +4453,6 @@ We recommend you view the release notes using the button below to learn about an Read Models and Settings from Radio Lese Modelle und Einstellungen aus dem Sender - - - Models and Settings read - - - - - - This function is not yet implemented - - OpenTX Companion %1 - Radio: %2 - Profile: %3 @@ -4493,16 +4503,6 @@ We recommend you view the release notes using the button below to learn about an SD card synchronization - - - Use default system language. - - - - - Use %1 language (some translations may not be complete). - - Recent Files @@ -6137,42 +6137,44 @@ If blank then the mix is considered to be "ON" all the time. Subtype - + Subtyp + Video TX frequency - + Videosender Frequenz + C2500 frequency fine tune - + Frequenzfeineinstellung CC2500 Telemetry - Telemetrie + Telemetrie Radio output power - + Sender-Sendeleistung Servo output frequency - + Ausgabefrequenz des Servosignals Option value - + Optionswert DEFAULT - + Standard @@ -6254,7 +6256,7 @@ If blank then the mix is considered to be "ON" all the time. Flash Firmware - + Flashe Firmware @@ -6392,57 +6394,57 @@ If blank then the mix is considered to be "ON" all the time. English - English + Englisch French - French + Französisch Italian - Italien + Italienisch German - Deutch + Deutsch Czech - Czech + Tschechisch Slovak - Slovak + Slowakisch Spanish - Spanish + Spanisch Portuguese - Portuguese + Portogiesisch Swedish - Swedish + Schwedisch Dutch - + Niederländisch Hungarian - + Ungarisch @@ -6635,6 +6637,26 @@ If blank then the mix is considered to be "ON" all the time. FM8 FM8 + + + Trim 5 Down + + + + + Trim 5 Up + + + + + Trim 6 Down + + + + + Trim 6 Up + + One @@ -6771,6 +6793,11 @@ If blank then the mix is considered to be "ON" all the time. Unknown Unbekannt + + + SD Logs + + played once, not during startup @@ -6831,11 +6858,6 @@ If blank then the mix is considered to be "ON" all the time. Play Script - - - SD Logs - - Volume @@ -7179,26 +7201,6 @@ If blank then the mix is considered to be "ON" all the time. AilTrim Right QuerTrim rechts - - - Trim 5 Down - - - - - Trim 5 Up - - - - - Trim 6 Down - - - - - Trim 6 Up - - THs @@ -12421,6 +12423,72 @@ Please only use this if you know what you are doing. There are no error checks Ch2 Ch2 + + + Not Assigned + + + + + Stick + + + + + Knob/Slider %1 + + + + + No joysticks found + Kein Joystick gefunden + + + + Press the Start button to start the stick range calibration procedure. +You may change the channel assignments or inversion at any time. + + + + + Move sticks and pots in every direction making full movement +Press Next when finished + + + + + Place sticks and pots in middle position. +Press Next when done + + + + + Map joystick channels to controls using comboboxes. +Press Next when done. + + + + + Check inversion checkbox to if necessary to reverse direction. +Press Next when done. + + + + + Press OK to save configuration +Press Cancel to abort joystick calibration without saving. + + + + + Warning + Warnung + + + + Calibration not complete, save anyway? + + Ch1 @@ -12491,26 +12559,6 @@ Please only use this if you know what you are doing. There are no error checks Ok Ok - - - Not Assigned - - - - - Stick - - - - - Knob/Slider %1 - - - - - No joysticks found - Kein Joystick gefunden - Error @@ -12521,52 +12569,6 @@ Please only use this if you know what you are doing. There are no error checks Cannot open joystick. kann Joystick nicht öffnen. - - - Press the Start button to start the stick range calibration procedure. -You may change the channel assignments or inversion at any time. - - - - - Move sticks and pots in every direction making full movement -Press Next when finished - - - - - Place sticks and pots in middle position. -Press Next when done - - - - - Map joystick channels to controls using comboboxes. -Press Next when done. - - - - - Check inversion checkbox to if necessary to reverse direction. -Press Next when done. - - - - - Press OK to save configuration -Press Cancel to abort joystick calibration without saving. - - - - - Warning - Warnung - - - - Calibration not complete, save anyway? - - preferencesDialog From 4c0dbfcb6c7e27937e04dc27ce505621bdfaba09 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Fri, 31 Mar 2017 01:55:25 -0400 Subject: [PATCH 066/203] [Companion] Make simulator startup from ModelEdit panel act the same as simulating a model from the models list widget (that is, including the other radio data as well); Simplify some code, remove automatic signal connections and use new syntax. (#4721) --- companion/src/modeledit/modeledit.cpp | 60 +++++++++------------------ companion/src/modeledit/modeledit.h | 9 ++-- 2 files changed, 23 insertions(+), 46 deletions(-) diff --git a/companion/src/modeledit/modeledit.cpp b/companion/src/modeledit/modeledit.cpp index 4e2791211..6ba56e4d5 100644 --- a/companion/src/modeledit/modeledit.cpp +++ b/companion/src/modeledit/modeledit.cpp @@ -38,8 +38,7 @@ ModelEdit::ModelEdit(QWidget * parent, RadioData & radioData, int modelId, Firmw QDialog(parent), ui(new Ui::ModelEdit), modelId(modelId), - model(radioData.models[modelId]), - generalSettings(radioData.generalSettings), + radioData(radioData), firmware(firmware) { Stopwatch s1("ModelEdit"); @@ -49,27 +48,30 @@ ModelEdit::ModelEdit(QWidget * parent, RadioData & radioData, int modelId, Firmw setWindowIcon(CompanionIcon("edit.png")); restoreGeometry(g.modelEditGeo()); ui->pushButton->setIcon(CompanionIcon("simulate.png")); - SetupPanel * setupPanel = new SetupPanel(this, model, generalSettings, firmware); + SetupPanel * setupPanel = new SetupPanel(this, radioData.models[modelId], radioData.generalSettings, firmware); addTab(setupPanel, tr("Setup")); if (firmware->getCapability(Heli)) - addTab(new HeliPanel(this, model, generalSettings, firmware), tr("Heli")); - addTab(new FlightModesPanel(this, model, generalSettings, firmware), tr("Flight Modes")); - addTab(new InputsPanel(this, model, generalSettings, firmware), tr("Inputs")); + addTab(new HeliPanel(this, radioData.models[modelId], radioData.generalSettings, firmware), tr("Heli")); + addTab(new FlightModesPanel(this, radioData.models[modelId], radioData.generalSettings, firmware), tr("Flight Modes")); + addTab(new InputsPanel(this, radioData.models[modelId], radioData.generalSettings, firmware), tr("Inputs")); s1.report("inputs"); - addTab(new MixesPanel(this, model, generalSettings, firmware), tr("Mixes")); + addTab(new MixesPanel(this, radioData.models[modelId], radioData.generalSettings, firmware), tr("Mixes")); s1.report("Mixes"); - Channels * chnPanel = new Channels(this, model, generalSettings, firmware); + Channels * chnPanel = new Channels(this, radioData.models[modelId], radioData.generalSettings, firmware); addTab(chnPanel, tr("Outputs")); s1.report("Outputs"); - addTab(new Curves(this, model, generalSettings, firmware), tr("Curves")); - addTab(new LogicalSwitchesPanel(this, model, generalSettings, firmware), tr("Logical Switches")); + addTab(new Curves(this, radioData.models[modelId], radioData.generalSettings, firmware), tr("Curves")); + addTab(new LogicalSwitchesPanel(this, radioData.models[modelId], radioData.generalSettings, firmware), tr("Logical Switches")); s1.report("LS"); - addTab(new CustomFunctionsPanel(this, &model, generalSettings, firmware), tr("Special Functions")); + addTab(new CustomFunctionsPanel(this, &radioData.models[modelId], radioData.generalSettings, firmware), tr("Special Functions")); s1.report("CF"); if (firmware->getCapability(Telemetry) & TM_HASTELEMETRY) - addTab(new TelemetryPanel(this, model, generalSettings, firmware), tr("Telemetry")); + addTab(new TelemetryPanel(this, radioData.models[modelId], radioData.generalSettings, firmware), tr("Telemetry")); + + connect(setupPanel, &SetupPanel::extendedLimitsToggled, chnPanel, &Channels::refreshExtendedLimits); + connect(ui->tabWidget, &QTabWidget::currentChanged, this, &ModelEdit::onTabIndexChanged); + connect(ui->pushButton, &QPushButton::clicked, this, &ModelEdit::launchSimulation); - connect(setupPanel, SIGNAL(extendedLimitsToggled()), chnPanel, SLOT(refreshExtendedLimits())); s1.report("end"); gStopwatch.report("ModelEdit end constructor"); } @@ -92,38 +94,16 @@ void ModelEdit::addTab(GenericPanel *panel, QString text) VerticalScrollArea * area = new VerticalScrollArea(widget, panel); baseLayout->addWidget(area); ui->tabWidget->addTab(widget, text); - connect(panel, SIGNAL(modified()), this, SLOT(onTabModified())); + connect(panel, &GenericPanel::modified, this, &ModelEdit::modified); } -void ModelEdit::onTabModified() +void ModelEdit::onTabIndexChanged(int index) { - emit modified(); -} - -void ModelEdit::on_tabWidget_currentChanged(int index) -{ - panels[index]->update(); -} - -void ModelEdit::on_pushButton_clicked() -{ - launchSimulation(); + if (index < panels.size()) + panels.at(index)->update(); } void ModelEdit::launchSimulation() { - RadioData * simuData = new RadioData(); - simuData->generalSettings = generalSettings; - /*: Translators do NOT use accent for this, this is the default category name on Horus. */ - CategoryData category(qPrintable(tr("Models"))); - simuData->categories.push_back(category); - if (simuData->models.size() == 0) { - simuData->models.push_back(model); - } - else { - simuData->models[0] = model; - } - simuData->models[0].category = 0; - startSimulation(this, *simuData, 0); - delete simuData; + startSimulation(this, radioData, modelId); } diff --git a/companion/src/modeledit/modeledit.h b/companion/src/modeledit/modeledit.h index 9571536f3..969ae85d7 100644 --- a/companion/src/modeledit/modeledit.h +++ b/companion/src/modeledit/modeledit.h @@ -46,7 +46,7 @@ class ModelEdit : public QDialog public: ModelEdit(QWidget * parent, RadioData & radioData, int modelId, Firmware * firmware); ~ModelEdit(); - + protected: void closeEvent(QCloseEvent *event); @@ -54,15 +54,12 @@ class ModelEdit : public QDialog void modified(); private slots: - void onTabModified(); - void on_pushButton_clicked(); - void on_tabWidget_currentChanged(int index); + void onTabIndexChanged(int index); private: Ui::ModelEdit *ui; int modelId; - ModelData & model; - GeneralSettings & generalSettings; + RadioData & radioData; Firmware * firmware; QVector panels; From 369bac9950f1127c7de279c49b81d45bab31a318 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Fri, 31 Mar 2017 01:56:22 -0400 Subject: [PATCH 067/203] [Companion] Improve handling of non-supported splash image (Horus) in radio profile settings page. (#4720) --- companion/src/apppreferencesdialog.cpp | 51 +++-- companion/src/apppreferencesdialog.ui | 282 +++++++++++++------------ 2 files changed, 173 insertions(+), 160 deletions(-) diff --git a/companion/src/apppreferencesdialog.cpp b/companion/src/apppreferencesdialog.cpp index 8b46cd41e..acc03dd0b 100644 --- a/companion/src/apppreferencesdialog.cpp +++ b/companion/src/apppreferencesdialog.cpp @@ -77,7 +77,7 @@ void AppPreferencesDialog::writeValues() g.enableBackup(ui->backupEnable->isChecked()); if (ui->joystickChkB ->isChecked() && ui->joystickCB->isEnabled()) { - g.jsSupport(ui->joystickChkB ->isChecked()); + g.jsSupport(ui->joystickChkB ->isChecked()); g.jsCtrl(ui->joystickCB ->currentIndex()); } else { @@ -193,7 +193,7 @@ void AppPreferencesDialog::initSettings() ui->joystickCB->setDisabled(true); ui->joystickcalButton->setDisabled(true); } -#endif +#endif // Profile Tab Inits ui->channelorderCB->setCurrentIndex(g.profile[g.id()].channelOrder()); ui->stickmodeCB->setCurrentIndex(g.profile[g.id()].defaultMode()); @@ -213,7 +213,6 @@ void AppPreferencesDialog::initSettings() } ui->profileNameLE->setText(g.profile[g.id()].name()); - ui->SplashFileName->setText(g.profile[g.id()].splashFile()); QString hwSettings; if (g.profile[g.id()].stickPotCalib() == "" ) { @@ -229,30 +228,13 @@ void AppPreferencesDialog::initSettings() ui->lblGeneralSettings->setText(hwSettings); Firmware * current_firmware = getCurrentFirmware(); - - if (!IS_HORUS(current_firmware->getBoard())) { - displayImage(g.profile[g.id()].splashFile()); - } - // TODO: Remove once splash replacement supported on Horus - // NOTE: 480x272 image causes issues on screens <800px high, needs a solution like scrolling once reinstated - else { - ui->imageLabel->hide(); - ui->splashLabel->hide(); - ui->SplashFileName->hide(); - ui->SplashSelect->hide(); - ui->SplashSelect->setEnabled(false); - ui->clearImageButton->hide(); - ui->clearImageButton->setEnabled(false); - ui->splashSeparator->hide(); - } - foreach(Firmware * firmware, firmwares) { ui->downloadVerCB->addItem(firmware->getName(), firmware->getId()); if (current_firmware->getFirmwareBase() == firmware) { ui->downloadVerCB->setCurrentIndex(ui->downloadVerCB->count() - 1); } } - + baseFirmwareChanged(); } @@ -306,7 +288,7 @@ void AppPreferencesDialog::on_ge_pathButton_clicked() ui->ge_lineedit->setText(fileName); } } - + #if defined(JOYSTICKS) void AppPreferencesDialog::on_joystickChkB_clicked() { if (ui->joystickChkB->isChecked()) { @@ -367,10 +349,13 @@ bool AppPreferencesDialog::displayImage(const QString & fileName) // Start by clearing the label ui->imageLabel->clear(); - QImage image(fileName); - if (image.isNull()) + if (fileName.isEmpty()) return false; - + + QImage image(fileName); + if (image.isNull()) + return false; + ui->imageLabel->setPixmap(makePixMap(image)); ui->imageLabel->setFixedSize(getCurrentFirmware()->getCapability(LcdWidth), getCurrentFirmware()->getCapability(LcdHeight)); return true; @@ -388,7 +373,7 @@ void AppPreferencesDialog::on_SplashSelect_clicked() if (!fileName.isEmpty()){ g.imagesDir(QFileInfo(fileName).dir().absolutePath()); - + displayImage(fileName); ui->SplashFileName->setText(fileName); } @@ -478,7 +463,7 @@ void AppPreferencesDialog::firmwareOptionChanged(bool state) } } } - } + } } void AppPreferencesDialog::populateFirmwareOptions(const Firmware * firmware) @@ -542,6 +527,18 @@ void AppPreferencesDialog::populateFirmwareOptions(const Firmware * firmware) showVoice(voice && voice->isChecked()); + // TODO: Remove once splash replacement supported on Horus + // NOTE: 480x272 image causes issues on screens <800px high, needs a solution like scrolling once reinstated + if (IS_HORUS(parent->getBoard())) { + ui->widget_splashImage->hide(); + ui->SplashFileName->setText(""); + } + else { + ui->widget_splashImage->show(); + ui->SplashFileName->setText(g.profile[g.id()].splashFile()); + displayImage(g.profile[g.id()].splashFile()); + } + updateLock = false; QTimer::singleShot(0, this, SLOT(shrink())); } diff --git a/companion/src/apppreferencesdialog.ui b/companion/src/apppreferencesdialog.ui index 3c668b2c3..1898fb56b 100644 --- a/companion/src/apppreferencesdialog.ui +++ b/companion/src/apppreferencesdialog.ui @@ -45,7 +45,139 @@ Radio Profile - + + + + + Remove Profile + + + + + + + Select Folder + + + + + + + The profile specific folder, if set, will override general Backup folder + + + Select Folder + + + + + + + + 0 + + + 0 + + + 0 + + + 0 + + + 6 + + + + + + 0 + 0 + + + + + 75 + true + + + + Splash Screen + + + + + + + true + + + true + + + + + + + Select Image + + + + + + + + 0 + 0 + + + + + 128 + 64 + + + + + 212 + 64 + + + + QFrame::StyledPanel + + + QFrame::Plain + + + 1 + + + + + + true + + + + + + + Clear Image + + + + + + + Qt::Horizontal + + + + + + @@ -183,80 +315,7 @@ May be different from firmware language - - - - - 0 - 0 - - - - - 75 - true - - - - Splash Screen - - - - - - - true - - - true - - - - - - - - 0 - 0 - - - - - 128 - 64 - - - - - 212 - 64 - - - - QFrame::StyledPanel - - - QFrame::Plain - - - 1 - - - - - - true - - - - - - - Qt::Horizontal - - - - + @@ -269,7 +328,7 @@ May be different from firmware language - + @@ -285,7 +344,7 @@ May be different from firmware language - + true @@ -298,7 +357,7 @@ May be different from firmware language - + The profile specific folder, if set, will override general Backup folder @@ -308,7 +367,7 @@ May be different from firmware language - + If set it will override the application general setting @@ -318,7 +377,7 @@ May be different from firmware language - + if set, will override general backup enable @@ -328,14 +387,14 @@ May be different from firmware language - + General Settings - + true @@ -345,7 +404,7 @@ May be different from firmware language - + @@ -358,7 +417,7 @@ May be different from firmware language - + @@ -412,7 +471,7 @@ Mode 4: - + @@ -428,7 +487,7 @@ Mode 4: - + @@ -576,21 +635,21 @@ Mode 4: - + Append version number to FW file name - + Offer to write FW to Tx after download - + Qt::Vertical @@ -603,44 +662,6 @@ Mode 4: - - - - Clear Image - - - - - - - Select Image - - - - - - - Remove Profile - - - - - - - Select Folder - - - - - - - The profile specific folder, if set, will override general Backup folder - - - Select Folder - - - @@ -1111,9 +1132,6 @@ Mode 4: downloadVerCB langCombo voiceCombo - SplashFileName - SplashSelect - clearImageButton sdPath sdPathButton profilebackupPath @@ -1147,9 +1165,7 @@ Mode 4: volumeGain buttonBox - - - + buttonBox From 9ff1dab6b83b15e30aafda03b70732c20b91b54d Mon Sep 17 00:00:00 2001 From: 3djc Date: Fri, 31 Mar 2017 10:06:34 +0200 Subject: [PATCH 068/203] Hide non working serial2 for Horus --- radio/src/gui/480x272/radio_hardware.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/radio/src/gui/480x272/radio_hardware.cpp b/radio/src/gui/480x272/radio_hardware.cpp index a2b81ed94..c46960d2a 100644 --- a/radio/src/gui/480x272/radio_hardware.cpp +++ b/radio/src/gui/480x272/radio_hardware.cpp @@ -47,7 +47,7 @@ enum MenuRadioHardwareItems { ITEM_RADIO_HARDWARE_SG, ITEM_RADIO_HARDWARE_SH, ITEM_RADIO_HARDWARE_BLUETOOTH, -#if defined(SERIAL2) +#if defined(SERIAL2) && defined(DEBUG) ITEM_RADIO_HARDWARE_UART3_MODE, #endif ITEM_RADIO_HARDWARE_JITTER_FILTER, @@ -176,7 +176,7 @@ bool menuRadioHardware(event_t event) editName(HW_SETTINGS_COLUMN+50, y, g_eeGeneral.bluetoothName, LEN_BLUETOOTH_NAME, event, menuHorizontalPosition == 1 ? attr : 0); break; -#if defined(SERIAL2) +#if defined(SERIAL2) && defined(DEBUG) case ITEM_RADIO_HARDWARE_UART3_MODE: lcdDrawText(MENUS_MARGIN_LEFT, y, STR_UART3MODE); g_eeGeneral.serial2Mode = editChoice(HW_SETTINGS_COLUMN+50, y, STR_UART3MODES, g_eeGeneral.serial2Mode, 0, UART_MODE_MAX, attr, event); From d1cacc2f0f14393913d44e0bb6a3bfd7a33e25bd Mon Sep 17 00:00:00 2001 From: 3djc Date: Fri, 31 Mar 2017 16:12:43 +0200 Subject: [PATCH 069/203] Use filename when no name is defined (#4726) --- radio/src/storage/modelslist.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/radio/src/storage/modelslist.h b/radio/src/storage/modelslist.h index e920d70b4..5b496bebd 100644 --- a/radio/src/storage/modelslist.h +++ b/radio/src/storage/modelslist.h @@ -74,8 +74,15 @@ class ModelCell } else { zchar2str(modelName, header.name, LEN_MODEL_NAME); + if (modelName[0] == 0) { + char * tmp; + strncpy(modelName, modelFilename, LEN_MODEL_NAME); + tmp = (char *) memchr(modelName, '.', LEN_MODEL_NAME); + if (tmp != NULL) + *tmp = 0; + } char timer[LEN_TIMER_STRING]; - buffer->drawSizedText(5, 2, header.name, LEN_MODEL_NAME, SMLSIZE|ZCHAR|TEXT_COLOR); + buffer->drawSizedText(5, 2, modelName, LEN_MODEL_NAME, SMLSIZE|TEXT_COLOR); getTimerString(timer, 0); buffer->drawText(101, 40, timer, TEXT_COLOR); for (int i=0; i<4; i++) { From b17a6d470f986cd6bc8a96213761b1af8b361560 Mon Sep 17 00:00:00 2001 From: 3djc Date: Fri, 31 Mar 2017 16:13:36 +0200 Subject: [PATCH 070/203] Only allow saving to OTX format (#4727) --- companion/src/mdichild.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/companion/src/mdichild.cpp b/companion/src/mdichild.cpp index b64492a20..ac94dbdde 100644 --- a/companion/src/mdichild.cpp +++ b/companion/src/mdichild.cpp @@ -652,7 +652,7 @@ bool MdiChild::saveAs(bool isNew) #ifdef __APPLE__ fileName = QFileDialog::getSaveFileName(this, tr("Save As"), g.eepromDir() + "/" +fi.fileName()); #else - fileName = QFileDialog::getSaveFileName(this, tr("Save As"), g.eepromDir() + "/" +fi.fileName(), tr(EEPROM_FILES_FILTER)); + fileName = QFileDialog::getSaveFileName(this, tr("Save As"), g.eepromDir() + "/" +fi.fileName(), tr(OTX_FILES_FILTER)); #endif } if (fileName.isEmpty()) From e2722509f70fd4d27db3c7514d9b2fdbeee5e82d Mon Sep 17 00:00:00 2001 From: 3djc Date: Fri, 31 Mar 2017 16:14:00 +0200 Subject: [PATCH 071/203] Instead of copying current profile, start from a blank one (#4714) * Instead of copying current profile, start from a blank one * Handle both add profile (which add a new (ie blank) one) and copy current profile which behaves like before (but says it) * Avoid duplicate code --- companion/src/mainwindow.cpp | 17 +++++++++++++++-- companion/src/mainwindow.h | 2 ++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/companion/src/mainwindow.cpp b/companion/src/mainwindow.cpp index c857a86fe..36e0286ba 100644 --- a/companion/src/mainwindow.cpp +++ b/companion/src/mainwindow.cpp @@ -1059,6 +1059,7 @@ void MainWindow::createActions() readFlashAct = addAct("read_flash.png", tr("Read Firmware from Radio"),tr("Read firmware from Radio"), SLOT(readFlash())); writeFlashAct = addAct("write_flash.png", tr("Write Firmware to Radio"), tr("Write firmware to Radio"), SLOT(writeFlash())); createProfileAct = addAct("", tr("Add Radio Profile"), tr("Create a new Radio Setting Profile"), SLOT(createProfile())); + copyProfileAct = addAct("", tr("Copy Current Radio Profile"), tr("Duplicate current Radio Setting Profile"), SLOT(copyProfile())); openDocURLAct = addAct("", tr("Manuals and other Documents"), tr("Open the OpenTX document page in a web browser"), SLOT(openDocURL())); writeEepromAct = addAct("write_eeprom.png", tr("Write Models and Settings To Radio"), tr("Write Models and Settings to Radio"), SLOT(writeEeprom())); readEepromAct = addAct("read_eeprom.png", tr("Read Models and Settings From Radio"), tr("Read Models and Settings from Radio"), SLOT(readEeprom())); @@ -1218,6 +1219,7 @@ QMenu *MainWindow::createProfilesMenu() profilesMenu->addSeparator(); profilesMenu->addAction(createProfileAct); + profilesMenu->addAction(copyProfileAct); profilesMenu->setIcon(CompanionIcon("profiles.png")); return profilesMenu; } @@ -1398,6 +1400,18 @@ void MainWindow::updateProfilesActions() } } + +void MainWindow::copyProfile() +{ + int previous = g.id(); + + createProfile(); + if (g.id() == previous) //Failed to find free slot + return; + g.profile[g.id()] = g.profile[previous]; + updateMenus(); +} + void MainWindow::createProfile() { int i; @@ -1405,8 +1419,7 @@ void MainWindow::createProfile() if (i==MAX_PROFILES) //Failed to find free slot return; - // Copy current profile to new and give it a new name - g.profile[i] = g.profile[g.id()]; + g.profile[i].init(i); g.profile[i].name(tr("New Radio")); g.id(i); diff --git a/companion/src/mainwindow.h b/companion/src/mainwindow.h index fa43cdb6a..90b199887 100644 --- a/companion/src/mainwindow.h +++ b/companion/src/mainwindow.h @@ -123,6 +123,7 @@ class MainWindow : public QMainWindow void fwPrefs(); void updateMenus(); void createProfile(); + void copyProfile(); void setActiveSubWindow(QWidget *window); void autoClose(); @@ -213,6 +214,7 @@ class MainWindow : public QMainWindow QAction *recentFileActs[MAX_RECENT]; QAction *profileActs[MAX_PROFILES]; QAction *createProfileAct; + QAction *copyProfileAct; QAction *openDocURLAct; }; From 2aebcb842a9874af4d1ce7fe4561ce5a3ac6b93d Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Fri, 31 Mar 2017 18:33:48 +0200 Subject: [PATCH 072/203] Lua docs update: lcd.drawText() added link to fonts --- radio/src/lua/api_lcd.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/lua/api_lcd.cpp b/radio/src/lua/api_lcd.cpp index 16711a76c..0f4ae04b8 100644 --- a/radio/src/lua/api_lcd.cpp +++ b/radio/src/lua/api_lcd.cpp @@ -197,7 +197,7 @@ Draw a text beginning at (x,y) @param flags (unsigned number) drawing flags. All values can be combined together using the + character. ie BLINK + DBLSIZE. -See the Appendix for available characters in each font set. +See the [Appendix](../appendix/fonts.md) for available characters in each font set. * `0 or not specified` normal font * `XXLSIZE` jumbo sized font * `DBLSIZE` double size font From 9d3960f0f5220aff905cfe43a56f1ef4bf31f3a7 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Fri, 31 Mar 2017 13:19:12 -0400 Subject: [PATCH 073/203] [Simulator] TelemetrySimulator: Fix instance values not being populated with radio settings (also now reloads instance values with rest of radio data). (closes #4711) --- companion/src/simulation/simulatormainwindow.cpp | 4 ++++ companion/src/simulation/simulatormainwindow.h | 3 +++ companion/src/simulation/telemetrysimu.cpp | 7 +++++-- companion/src/simulation/telemetrysimu.h | 1 + 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/companion/src/simulation/simulatormainwindow.cpp b/companion/src/simulation/simulatormainwindow.cpp index 434ac429c..9f7a0cb5a 100644 --- a/companion/src/simulation/simulatormainwindow.cpp +++ b/companion/src/simulation/simulatormainwindow.cpp @@ -259,6 +259,8 @@ void SimulatorMainWindow::start() m_simulatorWidget->start(); if (m_outputsWidget) m_outputsWidget->start(); + + emit simulatorStart(); } void SimulatorMainWindow::createDockWidgets() @@ -279,6 +281,8 @@ void SimulatorMainWindow::createDockWidgets() m_telemetryDockWidget->setWidget(telem); m_telemetryDockWidget->setObjectName("TELEMETRY_SIMULATOR"); addTool(m_telemetryDockWidget, Qt::LeftDockWidgetArea, icon, QKeySequence(tr("F4"))); + connect(this, &SimulatorMainWindow::simulatorStart, telem, &TelemetrySimulator::onSimulatorStarted); + connect(ui->actionReloadRadioData, &QAction::triggered, telem, &TelemetrySimulator::onSimulatorStarted); } if (!m_trainerDockWidget) { diff --git a/companion/src/simulation/simulatormainwindow.h b/companion/src/simulation/simulatormainwindow.h index 4791cf0b4..5e9da9a3f 100644 --- a/companion/src/simulation/simulatormainwindow.h +++ b/companion/src/simulation/simulatormainwindow.h @@ -65,6 +65,9 @@ class SimulatorMainWindow : public QMainWindow void showRadioFixedHeight(bool fixed); void showRadioDocked(bool dock); + signals: + void simulatorStart(); + protected slots: virtual void closeEvent(QCloseEvent *); virtual void changeEvent(QEvent *e); diff --git a/companion/src/simulation/telemetrysimu.cpp b/companion/src/simulation/telemetrysimu.cpp index fb85ad25e..258b6cee0 100644 --- a/companion/src/simulation/telemetrysimu.cpp +++ b/companion/src/simulation/telemetrysimu.cpp @@ -31,8 +31,6 @@ TelemetrySimulator::TelemetrySimulator(QWidget * parent, SimulatorInterface * si { ui->setupUi(this); - setupDataFields(); - timer.setInterval(10); connect(&timer, &QTimer::timeout, this, &TelemetrySimulator::generateTelemetryFrame); @@ -70,6 +68,11 @@ TelemetrySimulator::~TelemetrySimulator() delete ui; } +void TelemetrySimulator::onSimulatorStarted() +{ + setupDataFields(); +} + void TelemetrySimulator::onSimulateToggled(bool isChecked) { if (isChecked) { diff --git a/companion/src/simulation/telemetrysimu.h b/companion/src/simulation/telemetrysimu.h index 42e63296f..5c1af2e42 100644 --- a/companion/src/simulation/telemetrysimu.h +++ b/companion/src/simulation/telemetrysimu.h @@ -45,6 +45,7 @@ class TelemetrySimulator : public QWidget explicit TelemetrySimulator(QWidget * parent, SimulatorInterface * simulator); virtual ~TelemetrySimulator(); + void onSimulatorStarted(); protected slots: From fa275793adfc486ab1f9f33ba75420c218efd403 Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Fri, 31 Mar 2017 19:52:20 +0200 Subject: [PATCH 074/203] simpgmspace CoGetOSTime() was returning wrong values (too big) --- radio/src/targets/simu/simpgmspace.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/targets/simu/simpgmspace.cpp b/radio/src/targets/simu/simpgmspace.cpp index c9ad8b0d3..dcf0c6f01 100644 --- a/radio/src/targets/simu/simpgmspace.cpp +++ b/radio/src/targets/simu/simpgmspace.cpp @@ -132,7 +132,7 @@ uint16_t getTmr2MHz() // return 2ms resolution to match CoOS settings U64 CoGetOSTime(void) { - return microsTimer() * 500; + return microsTimer() / 2000; } void simuInit() From b22e45cf18282fc8529d7b8f92347110db24f7ae Mon Sep 17 00:00:00 2001 From: 3djc Date: Sat, 1 Apr 2017 08:10:46 +0200 Subject: [PATCH 075/203] Companion : display warning on eeprom upgrade (#4724) * Display warning on eeprom upgrade * Use existing function --- companion/src/firmwares/opentx/opentxinterface.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/companion/src/firmwares/opentx/opentxinterface.cpp b/companion/src/firmwares/opentx/opentxinterface.cpp index 51eb51386..246fe1237 100644 --- a/companion/src/firmwares/opentx/opentxinterface.cpp +++ b/companion/src/firmwares/opentx/opentxinterface.cpp @@ -254,6 +254,7 @@ unsigned long OpenTxEepromInterface::load(RadioData &radioData, const uint8_t * if (version_error == OLD_VERSION) { errors.set(version_error); errors.set(HAS_WARNINGS); + ShowEepromWarnings(NULL, QObject::tr("Warning"), errors.to_ulong()); } else if (version_error == NOT_OPENTX) { std::cout << " not open9x\n"; @@ -281,7 +282,6 @@ unsigned long OpenTxEepromInterface::load(RadioData &radioData, const uint8_t * return errors.to_ulong(); } } - std::cout << " ok\n"; errors.set(ALL_OK); return errors.to_ulong(); From 9c7c8244f42c7dbe9371ee3c6f8694fdca20cd18 Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Sat, 1 Apr 2017 08:11:16 +0200 Subject: [PATCH 076/203] Fixes #4715: model notes were read from the settings path, but should be read from SD card path (#4728) --- radio/src/targets/simu/simufatfs.cpp | 38 +++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/radio/src/targets/simu/simufatfs.cpp b/radio/src/targets/simu/simufatfs.cpp index 40c49d154..7e6c1a4a6 100644 --- a/radio/src/targets/simu/simufatfs.cpp +++ b/radio/src/targets/simu/simufatfs.cpp @@ -101,16 +101,46 @@ void simuFatfsSetPaths(const char * sdPath, const char * settingsPath) TRACE_SIMPGMSPACE("simuFatfsSetPaths(): simuSettingsDirectory: \"%s\"", simuSettingsDirectory.c_str()); } -bool startsWith(const char *path, const char * start) +bool startsWith(const std::string & str, const std::string & prefix) { - return strncasecmp(path, start, strlen(start)) == 0; + return str.length() >= prefix.length() && + str.compare(0, prefix.length(), prefix) == 0; +} + +bool endsWith(const std::string & str, const std::string & suffix) +{ + return str.length() >= suffix.length() && + str.compare(str.length() - suffix.length(), suffix.length(), suffix) == 0; +} + +bool redirectToSettingsDirectory(const std::string & path) +{ + /* + Decide if we use special simuSettingsDirectory path or normal path + + We use special path for: + * radio settings and models list in /RADIO directory + * model (*.bin) files in /MODELS directory + */ + if (!simuSettingsDirectory.empty()) { +#if defined(COLORLCD) + if (path == RADIO_MODELSLIST_PATH || path == RADIO_SETTINGS_PATH) { + return true; + } +#endif + if (startsWith(path, "/MODELS") && endsWith(path, MODELS_EXT)) { + return true; + } + } + return false; } std::string convertToSimuPath(const char * path) { std::string result; if (isPathDelimiter(path[0])) { - if (!simuSettingsDirectory.empty() && (startsWith(path, "/MODELS") || startsWith(path, "/RADIO"))) { + if (redirectToSettingsDirectory(path)) { + // TRACE("REDIRECT ********************************************"); result = simuSettingsDirectory + std::string(path); } else { @@ -127,7 +157,7 @@ std::string convertToSimuPath(const char * path) std::string convertFromSimuPath(const char * path) { std::string result; - if (startsWith(path, simuSdDirectory.c_str())) { + if (startsWith(path, simuSdDirectory)) { result = std::string(path).substr(simuSdDirectory.length(), std::string::npos); if (result.empty()) { result = "/"; From 5dabe53af4f929153495f5598d675d1706e1a420 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sat, 1 Apr 2017 02:13:24 -0400 Subject: [PATCH 077/203] Minor misc. fixes (#4729) * [Simulator] Remove extraneous format value in microsTimer; Better way to delete SimulatorStartupDialog (in case no event loop starts). * [Simulator] No helpers dependency for SimulatorStartupDialog. * [simpgmspace] Rename micros timer function and make externally available. * [Companion] Fix possible uninitialized value in TreeModel (compiler warning). * [multi_arm] Fix minor compiler warning (MSVC: "unsafe mix of type 'uint8_t' and type 'bool' in operation"). * [lua] Fix compiler warning ("'data' may be used uninitialized in this function"). * [OpenTxSimulator] Fix analogs array range. * [Simulator] Auto-start simulator when SimulatorMainWindow is first shown (vs. before it was shown). * [Simulator] DebugOutput: prevent possible mutex deadlock on buffer overflow (force queued connection for Qt < 5.3). * [Companion] Display calibration data for Horus joysticks (MOUSE1/MOUSE2) --- companion/src/companion.qrc | 1 + companion/src/generaledit/calibration.cpp | 6 +++--- companion/src/helpers.cpp | 1 - .../src/images/simulator/icons/svg/folder_open.svg | 7 +++++++ companion/src/modelslist.cpp | 4 ++-- companion/src/simulation/debugoutput.cpp | 4 ++-- companion/src/simulation/simulatormainwindow.cpp | 9 +++++---- companion/src/simulation/simulatorstartupdialog.cpp | 3 +-- companion/src/simulator.cpp | 3 +-- radio/src/lua/api_general.cpp | 2 +- radio/src/pulses/multi_arm.cpp | 2 +- radio/src/targets/simu/opentxsimulator.cpp | 2 +- radio/src/targets/simu/simpgmspace.cpp | 10 +++++----- radio/src/targets/simu/simpgmspace.h | 8 +++++--- 14 files changed, 35 insertions(+), 27 deletions(-) create mode 100644 companion/src/images/simulator/icons/svg/folder_open.svg diff --git a/companion/src/companion.qrc b/companion/src/companion.qrc index 1ce2967b6..5b68fcd0b 100644 --- a/companion/src/companion.qrc +++ b/companion/src/companion.qrc @@ -22,6 +22,7 @@ images/simulator/icons/svg/fixed_x-on.svg images/simulator/icons/svg/fixed_y.svg images/simulator/icons/svg/fixed_y-on.svg + images/simulator/icons/svg/folder_open.svg images/simulator/icons/svg/hold_x.svg images/simulator/icons/svg/hold_x-on.svg images/simulator/icons/svg/hold_y.svg diff --git a/companion/src/generaledit/calibration.cpp b/companion/src/generaledit/calibration.cpp index 44bda3141..e07a874b1 100644 --- a/companion/src/generaledit/calibration.cpp +++ b/companion/src/generaledit/calibration.cpp @@ -41,10 +41,10 @@ CalibrationPanel::CalibrationPanel(QWidget * parent, GeneralSettings & generalSe tableWidget->setFrameStyle(QFrame::NoFrame | QFrame::Plain); tableWidget->setStyleSheet("QTableWidget {background-color: transparent;}"); QStringList headerLabels; - headerLabels << QObject::tr("Negative span") << QObject::tr("Mid value") << QObject::tr("Positive span"); + headerLabels << QObject::tr("Negative span") << QObject::tr("Mid value") << QObject::tr("Positive span"); tableWidget->setHorizontalHeaderLabels(headerLabels); - int rows = CPN_MAX_STICKS + getBoardCapability(getCurrentBoard(), Board::Pots) + getBoardCapability(getCurrentBoard(), Board::Sliders); + int rows = CPN_MAX_STICKS + getBoardCapability(getCurrentBoard(), Board::Pots) + getBoardCapability(getCurrentBoard(), Board::Sliders) + getBoardCapability(getCurrentBoard(), Board::MouseAnalogs); tableWidget->setRowCount(rows); for(int i = 0; i < rows; ++i) { @@ -80,7 +80,7 @@ void CalibrationPanel::onCellChanged(int value) emit modified(); } } - + int CalibrationPanel::getCalibrationValue(int row, int column) { switch(column) { diff --git a/companion/src/helpers.cpp b/companion/src/helpers.cpp index 0a22bd970..68afcc79d 100644 --- a/companion/src/helpers.cpp +++ b/companion/src/helpers.cpp @@ -762,7 +762,6 @@ void startSimulation(QWidget * parent, RadioData & radioData, int modelIdx) dialog->deleteLater(); } else if (dialog->setRadioData(simuData)) { - dialog->start(); dialog->show(); } else { diff --git a/companion/src/images/simulator/icons/svg/folder_open.svg b/companion/src/images/simulator/icons/svg/folder_open.svg new file mode 100644 index 000000000..768169f8c --- /dev/null +++ b/companion/src/images/simulator/icons/svg/folder_open.svg @@ -0,0 +1,7 @@ + + + + + + + diff --git a/companion/src/modelslist.cpp b/companion/src/modelslist.cpp index ff9940841..19ffff11a 100644 --- a/companion/src/modelslist.cpp +++ b/companion/src/modelslist.cpp @@ -265,7 +265,7 @@ void TreeModel::refresh() for (unsigned i=0; imodels.size(); i++) { ModelData & model = radioData->models[i]; int currentColumn = 0; - TreeItem * current; + TreeItem * current = NULL; if (IS_HORUS(board)) { if (!model.isEmpty()) { TreeItem * categoryItem; @@ -290,7 +290,7 @@ void TreeModel::refresh() current->setData(currentColumn++, QString().sprintf("%02d", i + 1)); } - if (!model.isEmpty()) { + if (!model.isEmpty() && current) { QString modelName; if (strlen(model.name) > 0) modelName = model.name; diff --git a/companion/src/simulation/debugoutput.cpp b/companion/src/simulation/debugoutput.cpp index 0cb582fb1..2bba42b9f 100644 --- a/companion/src/simulation/debugoutput.cpp +++ b/companion/src/simulation/debugoutput.cpp @@ -87,8 +87,8 @@ DebugOutput::DebugOutput(QWidget * parent, SimulatorInterface *simulator): m_dataBufferDevice->setInputBufferMaxSize(DEBUG_OUTPUT_WIDGET_INP_BUFF_SIZE); m_dataBufferDevice->open(QIODevice::ReadWrite | QIODevice::Text); - connect(m_dataBufferDevice, &FilteredTextBuffer::readyRead, this, &DebugOutput::processBytesReceived); - connect(m_dataBufferDevice, &FilteredTextBuffer::bufferOverflow, this, &DebugOutput::onDataBufferOverflow); + connect(m_dataBufferDevice, &FilteredTextBuffer::readyRead, this, &DebugOutput::processBytesReceived, Qt::QueuedConnection); + connect(m_dataBufferDevice, &FilteredTextBuffer::bufferOverflow, this, &DebugOutput::onDataBufferOverflow, Qt::QueuedConnection); connect(this, &DebugOutput::filterChanged, m_dataBufferDevice, &FilteredTextBuffer::setLineFilter); connect(this, &DebugOutput::filterEnabledChanged, m_dataBufferDevice, &FilteredTextBuffer::setLineFilterEnabled); connect(this, &DebugOutput::filterExprChanged, m_dataBufferDevice, &FilteredTextBuffer::setLineFilterExpr); diff --git a/companion/src/simulation/simulatormainwindow.cpp b/companion/src/simulation/simulatormainwindow.cpp index 9f7a0cb5a..41a708e5c 100644 --- a/companion/src/simulation/simulatormainwindow.cpp +++ b/companion/src/simulation/simulatormainwindow.cpp @@ -168,13 +168,14 @@ void SimulatorMainWindow::closeEvent(QCloseEvent *) void SimulatorMainWindow::show() { QMainWindow::show(); -#ifdef Q_OS_LINUX - // for whatever reason, w/out this workaround any floating docks may appear and get "stuck" behind other windows, eg. Terminal or Companion. if (m_firstShow) { - restoreUiState(); m_firstShow = false; + #ifdef Q_OS_LINUX + // for whatever reason, w/out this workaround any floating docks may appear and get "stuck" behind other windows, eg. Terminal or Companion. + restoreUiState(); + #endif + start(); } -#endif } void SimulatorMainWindow::changeEvent(QEvent *e) diff --git a/companion/src/simulation/simulatorstartupdialog.cpp b/companion/src/simulation/simulatorstartupdialog.cpp index e232b36f9..be67d7a90 100644 --- a/companion/src/simulation/simulatorstartupdialog.cpp +++ b/companion/src/simulation/simulatorstartupdialog.cpp @@ -24,7 +24,6 @@ #include "appdata.h" #include "constants.h" #include "simulatorinterface.h" -#include "helpers.h" #include @@ -52,7 +51,7 @@ SimulatorStartupDialog::SimulatorStartupDialog(SimulatorOptions * options, int * ui->optGrp_dataSource->setId(ui->optFolder, SimulatorOptions::START_WITH_FOLDER); ui->optGrp_dataSource->setId(ui->optSdPath, SimulatorOptions::START_WITH_SDPATH); - CompanionIcon icon("open.png"); + SimulatorIcon icon("folder_open"); ui->btnSelectDataFile->setIcon(icon); ui->btnSelectDataFolder->setIcon(icon); ui->btnSelectSdPath->setIcon(icon); diff --git a/companion/src/simulator.cpp b/companion/src/simulator.cpp index b758bbff1..bbfac692b 100644 --- a/companion/src/simulator.cpp +++ b/companion/src/simulator.cpp @@ -185,7 +185,7 @@ int main(int argc, char *argv[]) if (!cliOptsFound || profileId == -1 || simOptions.firmwareId.isEmpty() || (simOptions.dataFile.isEmpty() && simOptions.dataFolder.isEmpty())) { SimulatorStartupDialog * dlg = new SimulatorStartupDialog(&simOptions, &profileId); int ret = dlg->exec(); - dlg->deleteLater(); + delete dlg; if (ret != QDialog::Accepted) { return finish(0); } @@ -219,7 +219,6 @@ int main(int argc, char *argv[]) showMessage(resultMsg, QMessageBox::Critical); } else if (mainWindow->setOptions(simOptions, true)) { - mainWindow->start(); mainWindow->show(); result = app.exec(); if (!result) { diff --git a/radio/src/lua/api_general.cpp b/radio/src/lua/api_general.cpp index f9b933c75..67a0553f9 100644 --- a/radio/src/lua/api_general.cpp +++ b/radio/src/lua/api_general.cpp @@ -408,7 +408,7 @@ static int luaCrossfireTelemetryPop(lua_State * L) } } - uint8_t length, data; + uint8_t length = 0, data = 0; if (luaInputTelemetryFifo->probe(length) && luaInputTelemetryFifo->size() >= uint32_t(length)) { // length value includes the length field luaInputTelemetryFifo->pop(length); diff --git a/radio/src/pulses/multi_arm.cpp b/radio/src/pulses/multi_arm.cpp index a4781ad22..a3d4045a0 100644 --- a/radio/src/pulses/multi_arm.cpp +++ b/radio/src/pulses/multi_arm.cpp @@ -74,7 +74,7 @@ static void sendByteMulti(uint8_t b) //max 11 changes 0 10 10 10 10 P 1 uint8_t len = BITLEN_MULTI; //max val: 10*20 < 256 for (uint8_t i=0; i<=9; i++) { //8Bits + 1Parity + Stop=1 bool nlev = b & 1; //lsb first - parity = parity ^ nlev; + parity = parity ^ (uint8_t)nlev; if (lev == nlev) { len += BITLEN_MULTI; } diff --git a/radio/src/targets/simu/opentxsimulator.cpp b/radio/src/targets/simu/opentxsimulator.cpp index c84ee7260..f85be7b9e 100644 --- a/radio/src/targets/simu/opentxsimulator.cpp +++ b/radio/src/targets/simu/opentxsimulator.cpp @@ -18,7 +18,7 @@ #include "opentx.h" #include "simulcd.h" -int16_t g_anas[NUM_STICKS+NUM_POTS+NUM_SLIDERS]; +int16_t g_anas[Analogs::NUM_ANALOGS]; uint16_t anaIn(uint8_t chan) { diff --git a/radio/src/targets/simu/simpgmspace.cpp b/radio/src/targets/simu/simpgmspace.cpp index dcf0c6f01..23ba0aa09 100644 --- a/radio/src/targets/simu/simpgmspace.cpp +++ b/radio/src/targets/simu/simpgmspace.cpp @@ -81,7 +81,7 @@ void toplcdOff() { } -U64 microsTimer(void) +uint64_t simuTimerMicros(void) { #if SIMPGMSPC_USE_QT @@ -104,7 +104,7 @@ U64 microsTimer(void) freqScale = 1e6 / frequency.QuadPart; // init timer QueryPerformanceCounter(&firstTick); - TRACE_SIMPGMSPACE("microsTimer() init: first tick = %llu @ %llu Hz: %g", firstTick.QuadPart, frequency.QuadPart); + TRACE_SIMPGMSPACE("microsTimer() init: first tick = %llu @ %llu Hz", firstTick.QuadPart, frequency.QuadPart); } // read the timer QueryPerformanceCounter(&newTick); @@ -121,18 +121,18 @@ U64 microsTimer(void) uint16_t getTmr16KHz() { - return microsTimer() * 2 / 125; + return simuTimerMicros() * 2 / 125; } uint16_t getTmr2MHz() { - return microsTimer() * 2; + return simuTimerMicros() * 2; } // return 2ms resolution to match CoOS settings U64 CoGetOSTime(void) { - return microsTimer() / 2000; + return simuTimerMicros() / 2000; } void simuInit() diff --git a/radio/src/targets/simu/simpgmspace.h b/radio/src/targets/simu/simpgmspace.h index a5cdd1e90..d1edfe084 100644 --- a/radio/src/targets/simu/simpgmspace.h +++ b/radio/src/targets/simu/simpgmspace.h @@ -356,15 +356,16 @@ extern char * main_thread_error; #define SIMU_SLEEP(x) do { if (!main_thread_running) return; sleep(x/*ms*/); } while (0) #define SIMU_SLEEP_NORET(x) do { sleep(x/*ms*/); } while (0) +uint64_t simuTimerMicros(void); + void simuInit(); +void StartSimu(bool tests=true, const char * sdPath = 0, const char * settingsPath = 0); +void StopSimu(); void simuSetKey(uint8_t key, bool state); void simuSetTrim(uint8_t trim, bool state); void simuSetSwitch(uint8_t swtch, int8_t state); -void StartSimu(bool tests=true, const char * sdPath = 0, const char * settingsPath = 0); -void StopSimu(); - void StartEepromThread(const char *filename="eeprom.bin"); void StopEepromThread(); #if defined(SIMU_AUDIO) && defined(CPUARM) @@ -419,6 +420,7 @@ OS_TID CoCreateTask(FUNCPtr task, void *argv, uint32_t parameter, void * stk, ui #define CoTickDelay(x) sleep(2*(x)) #define CoCreateFlag(...) 0 U64 CoGetOSTime(void); + #define UART_Stop(...) #define UART3_Stop(...) #define USART_GetITStatus(...) 0 From 8b61cd56bc38ff262303e44c40cba28013f83e65 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sat, 1 Apr 2017 20:48:55 -0400 Subject: [PATCH 078/203] [Simulator] Prevent two possible concurrency issues with FIFOBufferDevice/FilteredTextBuffer. --- companion/src/simulation/filteredtextbuffer.cpp | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/companion/src/simulation/filteredtextbuffer.cpp b/companion/src/simulation/filteredtextbuffer.cpp index 75f50cd51..61d30d911 100644 --- a/companion/src/simulation/filteredtextbuffer.cpp +++ b/companion/src/simulation/filteredtextbuffer.cpp @@ -115,7 +115,9 @@ qint64 FIFOBufferDevice::readData(char * data, qint64 len) qint64 FIFOBufferDevice::readLine(char * data, qint64 maxSize) { + m_dataRWLock.lockForRead(); qint64 len = buffer().indexOf('\n', 0); + m_dataRWLock.unlock(); if (len < 0 || maxSize <= 0) return 0; @@ -128,7 +130,9 @@ qint64 FIFOBufferDevice::readLine(char * data, qint64 maxSize) QByteArray FIFOBufferDevice::readLine(qint64 maxSize) { QByteArray ba; + m_dataRWLock.lockForRead(); qint64 len = buffer().indexOf('\n', 0); + m_dataRWLock.unlock(); if (len < 0) return ba; @@ -169,9 +173,9 @@ FilteredTextBuffer::FilteredTextBuffer(QObject * parent) : setInputBufferMaxSize(m_inBuffMaxSize); setInputBufferTimeout(m_inBuffFlushTimeout); - connect(m_inBuffer, &FIFOBufferDevice::readyRead, this, &FilteredTextBuffer::processInputBuffer); - connect(m_inBuffer, &FIFOBufferDevice::bytesWritten, this, &FilteredTextBuffer::onInputBufferWrite); - connect(m_inBuffer, &FIFOBufferDevice::bufferOverflow, this, &FilteredTextBuffer::onInputBufferOverflow); + connect(m_inBuffer, &FIFOBufferDevice::readyRead, this, &FilteredTextBuffer::processInputBuffer, Qt::QueuedConnection); + connect(m_inBuffer, &FIFOBufferDevice::bytesWritten, this, &FilteredTextBuffer::onInputBufferWrite, Qt::QueuedConnection); + connect(m_inBuffer, &FIFOBufferDevice::bufferOverflow, this, &FilteredTextBuffer::onInputBufferOverflow, Qt::QueuedConnection); connect(m_bufferFlushTimer, &QTimer::timeout, this, &FilteredTextBuffer::processInputBuffer); connect(this, &FilteredTextBuffer::timerStart, m_bufferFlushTimer, static_cast(&QTimer::start)); connect(this, &FilteredTextBuffer::timerStop, m_bufferFlushTimer, &QTimer::stop); From 8d0db05e78e266b363e4388730fd81b47e6e7e2b Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Sun, 2 Apr 2017 12:16:12 +0200 Subject: [PATCH 079/203] Copy useful links from 2.1 to 2.2 (#4732) --- README.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index b217e85fe..3572396fa 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -##OpenTX 2.2 Branch +##OpenTX 2.2 Branch [![Build Status](https://travis-ci.org/opentx/opentx.svg?branch=next)](https://travis-ci.org/opentx/opentx) [![Coverity Scan Build Status](https://scan.coverity.com/projects/11787/badge.svg)](https://scan.coverity.com/projects/opentx-opentx) @@ -7,4 +7,11 @@ The ongoing development on 2.2.x is done in this branch. -Refer to the opentx.wiki for information about setting up the tool chains for building OpenTX and OpenTX Companion as well as other development related issues. +Refer to the [OpenTX wiki](https://github.com/opentx/opentx/wiki) for information about setting up the tool chains for building OpenTX and OpenTX Companion as well as other development related issues. + +Useful links: + * OpenTX Blog http://blog.open-tx.org/ + * OpenTX Main Site http://www.open-tx.org/ + * OpenTx University http://open-txu.org/ + * OpenTX User Manual https://www.gitbook.com/book/opentx/opentx-taranis-manual/details + * OpenTX Lua Reference Guide https://www.gitbook.com/book/opentx/opentx-lua-reference-guide/details From 36bb9513147cd5e25427af5687057d9c79251455 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sun, 2 Apr 2017 06:17:06 -0400 Subject: [PATCH 080/203] [Companion] Radio profile/current firmware handling: (#4737) * Fix possible confusion/data corruption when deleting radio profile (closes #4734, ref: #4686); * Add Delete Profile action to Radio Profiles menu (closes #4736) (but remove from from app prefs. panel); * Add confirmation prompt before deleting profile; * Open profile settings dialog when creating/copying a profile (closes #4735); * Make sure current (global) firmware flavor is properly updated when changing fw type/options in profile; * Append "-Copy" to name of copied profile; * Factor out Firmware global vars/functions in favor of static members. --- companion/src/apppreferencesdialog.cpp | 47 +++---- companion/src/apppreferencesdialog.h | 4 +- companion/src/apppreferencesdialog.ui | 8 -- companion/src/companion.cpp | 4 +- companion/src/eeprominterface.cpp | 22 ++-- companion/src/eeprominterface.h | 46 +++++-- .../src/firmwares/opentx/opentxinterface.cpp | 8 +- companion/src/fwpreferencesdialog.cpp | 2 +- companion/src/mainwindow.cpp | 124 +++++++++++++----- companion/src/mainwindow.h | 5 + companion/src/simulator.cpp | 2 +- 11 files changed, 172 insertions(+), 100 deletions(-) diff --git a/companion/src/apppreferencesdialog.cpp b/companion/src/apppreferencesdialog.cpp index acc03dd0b..871064cf4 100644 --- a/companion/src/apppreferencesdialog.cpp +++ b/companion/src/apppreferencesdialog.cpp @@ -100,12 +100,13 @@ void AppPreferencesDialog::writeValues() g.profile[g.id()].name(ui->profileNameLE->text()); // If a new fw type has been choosen, several things need to reset - current_firmware_variant = getFirmwareVariant(); - QString id = current_firmware_variant->getId(); + Firmware::setCurrentVariant(getFirmwareVariant()); + QString id = Firmware::getCurrentVariant()->getId(); if (g.profile[g.id()].fwType() != id) { g.profile[g.id()].fwName(""); g.profile[g.id()].initFwVariables(); g.profile[g.id()].fwType(id); + emit firmwareProfileChanged(g.id()); } } @@ -227,10 +228,10 @@ void AppPreferencesDialog::initSettings() } ui->lblGeneralSettings->setText(hwSettings); - Firmware * current_firmware = getCurrentFirmware(); - foreach(Firmware * firmware, firmwares) { + QString currType = QStringList(g.profile[g.id()].fwType().split('-').mid(0, 2)).join('-'); + foreach(Firmware * firmware, Firmware::getRegisteredFirmwares()) { ui->downloadVerCB->addItem(firmware->getName(), firmware->getId()); - if (current_firmware->getFirmwareBase() == firmware) { + if (currType == firmware->getId()) { ui->downloadVerCB->setCurrentIndex(ui->downloadVerCB->count() - 1); } } @@ -332,18 +333,6 @@ void AppPreferencesDialog::on_sdPathButton_clicked() } } -void AppPreferencesDialog::on_removeProfileButton_clicked() -{ - if ( g.id() == 0 ) { - QMessageBox::information(this, tr("Not possible to remove profile"), tr("The default profile can not be removed.")); - } - else { - g.profile[g.id()].remove(); - g.id( 0 ); - initSettings(); - } -} - bool AppPreferencesDialog::displayImage(const QString & fileName) { // Start by clearing the label @@ -395,9 +384,9 @@ void AppPreferencesDialog::showVoice(bool show) void AppPreferencesDialog::baseFirmwareChanged() { - QVariant selected_firmware = ui->downloadVerCB->itemData(ui->downloadVerCB->currentIndex()); + QString selected_firmware = ui->downloadVerCB->currentData().toString(); - foreach(Firmware * firmware, firmwares) { + foreach(Firmware * firmware, Firmware::getRegisteredFirmwares()) { if (firmware->getId() == selected_firmware) { populateFirmwareOptions(firmware); break; @@ -407,31 +396,31 @@ void AppPreferencesDialog::baseFirmwareChanged() Firmware * AppPreferencesDialog::getFirmwareVariant() { - QVariant selected_firmware = ui->downloadVerCB->itemData(ui->downloadVerCB->currentIndex()); + QString selected_firmware = ui->downloadVerCB->currentData().toString(); - foreach(Firmware * firmware, firmwares) { + foreach(Firmware * firmware, Firmware::getRegisteredFirmwares()) { QString id = firmware->getId(); if (id == selected_firmware) { foreach(QCheckBox *cb, optionsCheckBoxes) { if (cb->isChecked()) { - id += QString("-") + cb->text(); + id += "-" + cb->text(); } } if (voice && voice->isChecked()) { - id += QString("-tts") + ui->voiceCombo->currentText(); + id += "-tts" + ui->voiceCombo->currentText(); } if (ui->langCombo->count()) { - id += QString("-") + ui->langCombo->currentText(); + id += "-" + ui->langCombo->currentText(); } - return getFirmware(id); + return Firmware::getFirmwareForId(id); } } // Should never occur... - return default_firmware_variant; + return Firmware::getDefaultVariant(); } void AppPreferencesDialog::firmwareOptionChanged(bool state) @@ -442,8 +431,8 @@ void AppPreferencesDialog::firmwareOptionChanged(bool state) } Firmware * firmware=NULL; if (cb && state) { - QVariant selected_firmware = ui->downloadVerCB->itemData(ui->downloadVerCB->currentIndex()); - foreach(firmware, firmwares) { + QVariant selected_firmware = ui->downloadVerCB->currentData(); + foreach(firmware, Firmware::getRegisteredFirmwares()) { if (firmware->getId() == selected_firmware) { foreach(QList + + + diff --git a/companion/src/companion.qrc b/companion/src/companion.qrc index 26c8f57d2..18b46f26a 100644 --- a/companion/src/companion.qrc +++ b/companion/src/companion.qrc @@ -620,6 +620,7 @@ themes/monoblue/16/contributors.png themes/monoblue/16/stop.png themes/monoblue/16/write_eeprom.png + themes/monoblue/16/sdsync.png themes/monoblue/24/paintbrush.png themes/monoblue/24/open.png themes/monoblue/24/edit.png @@ -663,6 +664,7 @@ themes/monoblue/24/contributors.png themes/monoblue/24/stop.png themes/monoblue/24/write_eeprom.png + themes/monoblue/24/sdsync.png themes/monoblue/32/paintbrush.png themes/monoblue/32/open.png themes/monoblue/32/edit.png @@ -706,6 +708,7 @@ themes/monoblue/32/contributors.png themes/monoblue/32/stop.png themes/monoblue/32/write_eeprom.png + themes/monoblue/32/sdsync.png themes/monoblue/48/paintbrush.png themes/monoblue/48/open.png themes/monoblue/48/edit.png @@ -749,6 +752,7 @@ themes/monoblue/48/contributors.png themes/monoblue/48/stop.png themes/monoblue/48/write_eeprom.png + themes/monoblue/48/sdsync.png themes/monowhite/16/paintbrush.png themes/monowhite/16/open.png themes/monowhite/16/edit.png @@ -792,6 +796,7 @@ themes/monowhite/16/contributors.png themes/monowhite/16/stop.png themes/monowhite/16/write_eeprom.png + themes/monowhite/16/sdsync.png themes/monowhite/24/paintbrush.png themes/monowhite/24/open.png themes/monowhite/24/edit.png @@ -835,6 +840,7 @@ themes/monowhite/24/contributors.png themes/monowhite/24/stop.png themes/monowhite/24/write_eeprom.png + themes/monowhite/24/sdsync.png themes/monowhite/32/paintbrush.png themes/monowhite/32/open.png themes/monowhite/32/edit.png @@ -878,6 +884,7 @@ themes/monowhite/32/contributors.png themes/monowhite/32/stop.png themes/monowhite/32/write_eeprom.png + themes/monowhite/32/sdsync.png themes/monowhite/48/paintbrush.png themes/monowhite/48/open.png themes/monowhite/48/edit.png @@ -921,6 +928,7 @@ themes/monowhite/48/contributors.png themes/monowhite/48/stop.png themes/monowhite/48/write_eeprom.png + themes/monowhite/48/sdsync.png themes/yerico/16/paintbrush.png themes/yerico/16/open.png themes/yerico/16/edit.png diff --git a/companion/src/comparedialog.cpp b/companion/src/comparedialog.cpp index 12e154572..1fc7a743d 100644 --- a/companion/src/comparedialog.cpp +++ b/companion/src/comparedialog.cpp @@ -20,42 +20,46 @@ #include "comparedialog.h" #include "ui_comparedialog.h" +#include "appdata.h" #include "helpers.h" +#include "modelslist.h" #include #include -class DragDropHeader { - public: - DragDropHeader(): - general_settings(false), - models_count(0) - { - } - bool general_settings; - uint8_t models_count; - uint8_t models[CPN_MAX_MODELS]; -}; +//class DragDropHeader { +// public: +// DragDropHeader(): +// general_settings(false), +// models_count(0) +// { +// } +// bool general_settings; +// uint8_t models_count; +// uint8_t models[CPN_MAX_MODELS]; +//}; CompareDialog::CompareDialog(QWidget * parent, Firmware * firmware): - QDialog(parent, Qt::WindowTitleHint | Qt::WindowSystemMenuHint), - multimodelprinter(firmware), - model1Valid(false), - model2Valid(false), + QDialog(parent, Qt::Window), + multimodelprinter(new MultiModelPrinter(firmware)), ui(new Ui::CompareDialog) { ui->setupUi(this); - setWindowIcon(CompanionIcon("compare.png")); setAcceptDrops(true); + if (!g.compareWinGeo().isEmpty()) { + restoreGeometry(g.compareWinGeo()); + } +} - //setDragDropOverwriteMode(true); - //setDropIndicatorShown(true); - // TODO scroll to top ... ui->textEdit->scrollToAnchor("1"); +CompareDialog::~CompareDialog() +{ + delete multimodelprinter; + delete ui; } void CompareDialog::dragMoveEvent(QDragMoveEvent * event) { - if (event->mimeData()->hasFormat("application/x-companion")) { + if (event->mimeData()->hasFormat("application/x-companion-modeldata")) { event->acceptProposedAction(); } else { @@ -65,8 +69,7 @@ void CompareDialog::dragMoveEvent(QDragMoveEvent * event) void CompareDialog::dragEnterEvent(QDragEnterEvent * event) { - // accept just text/uri-list mime format - if (event->mimeData()->hasFormat("application/x-companion")) { + if (event->mimeData()->hasFormat("application/x-companion-modeldata")) { event->acceptProposedAction(); } else { @@ -79,55 +82,85 @@ void CompareDialog::dragLeaveEvent(QDragLeaveEvent * event) event->accept(); } -bool CompareDialog::handleDroppedModel(const QMimeData * mimeData, ModelData & model, QLabel * label) +bool CompareDialog::handleMimeData(const QMimeData * mimeData) { - if (mimeData->hasFormat("application/x-companion")) { - QByteArray gmData = mimeData->data("application/x-companion"); - DragDropHeader * header = (DragDropHeader *)gmData.data(); - if (!header->general_settings) { - char * gData = gmData.data() + sizeof(DragDropHeader); - if (gData[0] == 'M') { - ModelData * modeltemp = (ModelData *)(gData + 1); - if (modeltemp->used) { - memcpy(&model, modeltemp, sizeof(ModelData)); - QString name(model.name); - if (!name.isEmpty()) - label->setText(name); - else - label->setText(tr("No name")); - return true; - } - } - } + QVector mList; + GeneralSettings gs; + if (!TreeModel::decodeMimeData(mimeData, &mList, &gs) || mList.isEmpty()) + return false; + for (int i=0; i < mList.size(); ++i) { + GMData data; + data.model = mList[i]; + data.gs = gs; + modelsList.append(data); } - return false; + return true; +} + +void CompareDialog::closeEvent(QCloseEvent * event) +{ + g.compareWinGeo(saveGeometry()); } void CompareDialog::dropEvent(QDropEvent *event) { - QLabel * child = qobject_cast(childAt(event->pos())); - if (!child) return; - if (child->objectName().contains("label_1")) { - model1Valid = handleDroppedModel(event->mimeData(), model1, ui->label_1); - } - else if (child->objectName().contains("label_2")) { - model2Valid = handleDroppedModel(event->mimeData(), model2, ui->label_2); - } - event->accept(); - if (model1Valid && model2Valid) { - multimodelprinter.setModel(0, model1); - multimodelprinter.setModel(1, model2); - ui->textEdit->setHtml(multimodelprinter.print(ui->textEdit->document())); + if (handleMimeData(event->mimeData())) { + event->accept(); + compare(); } } -void CompareDialog::closeEvent(QCloseEvent *event) +void CompareDialog::compare() { + QLayoutItem *child; + while ((child = ui->layout_modelNames->takeAt(0))) { + if (child->widget()) + delete child->widget(); + delete child; + } + + multimodelprinter->clearModels(); + ui->textEdit->clear(); + + for (int i=0; i < modelsList.size(); ++i) { + multimodelprinter->setModel(i, &modelsList[i].model, &modelsList[i].gs); + QString name(modelsList.at(i).model.name); + if (name.isEmpty()) + name = tr("Unnamed Model %1").arg(i+1); + + QWidget * hdr = new QWidget(this); + hdr->setLayout(new QHBoxLayout()); + hdr->layout()->setContentsMargins(0, 0, 0, 0); + hdr->layout()->setSpacing(2); + QToolButton * btn = new QToolButton(hdr); + btn->setIcon(CompanionIcon("clear.png")); + btn->setProperty("index", i); + btn->setFixedSize(18, 18); + btn->setToolTip(tr("Click to remove this model.")); + hdr->layout()->addWidget(btn); + QLabel * lbl = new QLabel(name, this); + lbl->setStyleSheet("font-weight: bold;"); + hdr->layout()->addWidget(lbl); + connect(btn, &QToolButton::clicked, this, &CompareDialog::removeModelBtnClicked); + + ui->layout_modelNames->addWidget(hdr); + } + if (modelsList.size()) + ui->textEdit->setHtml(multimodelprinter->print(ui->textEdit->document())); } -CompareDialog::~CompareDialog() +void CompareDialog::removeModel(int idx) { - delete ui; + if (idx < modelsList.size()) { + modelsList.remove(idx); + compare(); + } +} + +void CompareDialog::removeModelBtnClicked() +{ + if (sender() && sender()->property("index").isValid()) + removeModel(sender()->property("index").toInt()); } void CompareDialog::on_printButton_clicked() diff --git a/companion/src/comparedialog.h b/companion/src/comparedialog.h index ca6d2e0b6..03e709360 100644 --- a/companion/src/comparedialog.h +++ b/companion/src/comparedialog.h @@ -35,27 +35,32 @@ class CompareDialog : public QDialog public: CompareDialog(QWidget *parent, Firmware * firmware); ~CompareDialog(); - + protected: - MultiModelPrinter multimodelprinter; - ModelData model1; - ModelData model2; - bool model1Valid; - bool model2Valid; + struct GMData { + ModelData model; + GeneralSettings gs; + }; + + MultiModelPrinter * multimodelprinter; + QVector modelsList; + QMap modelsMap; Ui::CompareDialog * ui; - + protected slots: + void removeModelBtnClicked(); void on_printButton_clicked(); void on_printFileButton_clicked(); - + protected: - void closeEvent(QCloseEvent * event); - bool handleDroppedModel(const QMimeData * mimeData, ModelData & model, QLabel * label); - void dropEvent(QDropEvent *event); - void dragMoveEvent(QDragMoveEvent *event); - void dragEnterEvent(QDragEnterEvent *event); - void dragLeaveEvent(QDragLeaveEvent *event); - void printDiff(); + virtual void closeEvent(QCloseEvent * event); + virtual void dragMoveEvent(QDragMoveEvent *event); + virtual void dragEnterEvent(QDragEnterEvent *event); + virtual void dragLeaveEvent(QDragLeaveEvent *event); + virtual void dropEvent(QDropEvent *event); + bool handleMimeData(const QMimeData * mimeData); + void compare(); + void removeModel(int idx); }; #endif // _COMPAREDIALOG_H_ diff --git a/companion/src/comparedialog.ui b/companion/src/comparedialog.ui index d56701196..ba4d24c81 100644 --- a/companion/src/comparedialog.ui +++ b/companion/src/comparedialog.ui @@ -29,63 +29,22 @@ Compare Models - - - - - - - 75 - true - - - - true - - - color:green; - - - Drag first model here - - - Qt::AlignCenter - - - - - - - - 75 - true - - - - true - - - color:red; - - - Drag second model here - - - Qt::AlignCenter - - - - - - + true - + + + + + To compare models, drag and drop them anywhere in this window. + + + @@ -122,11 +81,28 @@ + + + + 6 + + + 0 + + + 0 + + + 0 + + + 0 + + + - - - + closeButton diff --git a/companion/src/eeprominterface.cpp b/companion/src/eeprominterface.cpp index ccfe39d4d..d13b0e108 100644 --- a/companion/src/eeprominterface.cpp +++ b/companion/src/eeprominterface.cpp @@ -1502,6 +1502,7 @@ RadioData::RadioData() void ModelData::clear() { memset(this, 0, sizeof(ModelData)); + modelIndex = -1; // an invalid index, this is managed by the TreeView data model moduleData[0].channelsCount = 8; moduleData[1].channelsStart = 0; moduleData[1].channelsCount = 8; diff --git a/companion/src/mainwindow.cpp b/companion/src/mainwindow.cpp index 2544913c2..c7fb519e4 100644 --- a/companion/src/mainwindow.cpp +++ b/companion/src/mainwindow.cpp @@ -72,38 +72,35 @@ MainWindow::MainWindow(): downloadDialog_forWait(NULL), checkForUpdatesState(0), - fileMenu(NULL), - editMenu(NULL), - settingsMenu(NULL), - burnMenu(NULL), - helpMenu(NULL), - fileToolBar(NULL), - editToolBar(NULL), - burnToolBar(NULL), - helpToolBar(NULL) + windowsListActions(new QActionGroup(this)) { + // setUnifiedTitleAndToolBarOnMac(true); + this->setWindowIcon(QIcon(":/icon.png")); + QNetworkProxyFactory::setUseSystemConfiguration(true); + setAcceptDrops(true); + mdiArea = new QMdiArea(this); mdiArea->setHorizontalScrollBarPolicy(Qt::ScrollBarAsNeeded); mdiArea->setVerticalScrollBarPolicy(Qt::ScrollBarAsNeeded); + mdiArea->setTabsClosable(true); + mdiArea->setTabsMovable(true); + mdiArea->setDocumentMode(true); + connect(mdiArea, &QMdiArea::subWindowActivated, this, &MainWindow::updateMenus); + setCentralWidget(mdiArea); - connect(mdiArea, SIGNAL(subWindowActivated(QMdiSubWindow*)), this, SLOT(updateMenus())); - windowMapper = new QSignalMapper(this); - connect(windowMapper, SIGNAL(mapped(QWidget*)), this, SLOT(setActiveSubWindow(QWidget*))); createActions(); createMenus(); createToolBars(); - createStatusBar(); + retranslateUi(); updateMenus(); - restoreState(g.mainWinState()); + setIconThemeSize(g.iconSize()); restoreGeometry(g.mainWinGeo()); + restoreState(g.mainWinState()); + setTabbedWindows(g.tabbedMdi()); - // setUnifiedTitleAndToolBarOnMac(true); - this->setWindowIcon(QIcon(":/icon.png")); - this->setIconSize(QSize(32, 32)); - QNetworkProxyFactory::setUseSystemConfiguration(true); - setAcceptDrops(true); + connect(windowsListActions, &QActionGroup::triggered, this, &MainWindow::onChangeWindowAction); // give time to the splash to disappear and main window to open before starting updates int updateDelay = 1000; @@ -129,7 +126,8 @@ MainWindow::MainWindow(): printfilename = strl[count]; } } - if (strl.count()>1) str = strl[1]; + if (strl.count() > 1) + str = strl[1]; if (!str.isEmpty()) { int fileType = getStorageType(str); @@ -153,6 +151,14 @@ MainWindow::MainWindow(): } } +MainWindow::~MainWindow() +{ + if (windowsListActions) { + delete windowsListActions; + windowsListActions = NULL; + } +} + void MainWindow::displayWarnings() { int warnId = g.warningId(); @@ -522,6 +528,7 @@ void MainWindow::closeEvent(QCloseEvent *event) { g.mainWinGeo(saveGeometry()); g.mainWinState(saveState()); + g.tabbedMdi(actTabbedWindows->isChecked()); mdiArea->closeAllSubWindows(); if (mdiArea->currentSubWindow()) { event->ignore(); @@ -536,21 +543,13 @@ void MainWindow::changeEvent(QEvent * e) QMainWindow::changeEvent(e); switch (e->type()) { case QEvent::LanguageChange: - retranslateUi(); + retranslateUi(true); break; default: break; } } -void MainWindow::retranslateUi() -{ - createActions(); - createMenus(); - createToolBars(); - QMessageBox::information(this, tr("Companion"), tr("Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete.")); -} - void MainWindow::setLanguage(const QString & langString) { g.locale(langString); @@ -580,8 +579,26 @@ void MainWindow::onThemeChanged(QAction * act) void MainWindow::setIconThemeSize(int index) { - g.iconSize(index); - QMessageBox::information(this, tr("Companion"), tr("The icon size will be used the next time you start Companion.")); + if (index != g.iconSize()) + g.iconSize(index); + + QSize size; + switch(g.iconSize()) { + case 0: + size=QSize(16,16); + break; + case 2: + size=QSize(32,32); + break; + case 3: + size=QSize(48,48); + break; + case 1: + default: + size=QSize(24,24); + break; + } + this->setIconSize(size); } void MainWindow::onIconSizeChanged(QAction * act) @@ -592,14 +609,22 @@ void MainWindow::onIconSizeChanged(QAction * act) setIconThemeSize(id); } +void MainWindow::setTabbedWindows(bool on) +{ + mdiArea->setViewMode(on ? QMdiArea::TabbedView : QMdiArea::SubWindowView); + if (actTileWindows) + actTileWindows->setDisabled(on); + if (actCascadeWindows) + actCascadeWindows->setDisabled(on); + + if (actTabbedWindows->isChecked() != on) + actTabbedWindows->setChecked(on); +} + void MainWindow::newFile() { MdiChild * child = createMdiChild(); child->newFile(); - - if (IS_HORUS(getCurrentBoard())) { - child->categoryAdd(); - } child->show(); } @@ -652,6 +677,12 @@ void MainWindow::saveAs() } } +void MainWindow::closeFile() +{ + if (mdiArea->activeSubWindow()) + mdiArea->activeSubWindow()->close(); +} + void MainWindow::openRecentFile() { QAction *action = qobject_cast(sender()); @@ -669,7 +700,7 @@ void MainWindow::loadProfileId(const unsigned pid) // TODO Load all variables - // Set the new profile number g.id(pid); Firmware::setCurrentVariant(Firmware::getFirmwareForId(g.profile[pid].fwType())); - emit FirmwareChanged(); + emit firmwareChanged(); updateMenus(); } @@ -754,47 +785,11 @@ void MainWindow::customizeSplash() dialog->deleteLater(); } -void MainWindow::cut() -{ - if (activeMdiChild()) { - activeMdiChild()->cut(); - updateMenus(); - } -} - -void MainWindow::copy() -{ - if (activeMdiChild()) { - activeMdiChild()->copy(); - updateMenus(); - } -} - -void MainWindow::paste() -{ - if (activeMdiChild()) activeMdiChild()->paste(); -} - void MainWindow::writeEeprom() { if (activeMdiChild()) activeMdiChild()->writeEeprom(); } -void MainWindow::simulate() -{ - if (activeMdiChild()) activeMdiChild()->radioSimulate(); -} - -void MainWindow::print() -{ - if (activeMdiChild()) activeMdiChild()->print(); -} - -void MainWindow::loadBackup() -{ - if (activeMdiChild()) activeMdiChild()->loadBackup(); -} - void MainWindow::readEeprom() { Board::Type board = getCurrentBoard(); @@ -937,28 +932,68 @@ void MainWindow::about() void MainWindow::updateMenus() { - bool hasMdiChild = (activeMdiChild() != 0); - bool hasModelSelected = (activeMdiChild() && activeMdiChild()->hasModelSelected()); + QMdiSubWindow * activeChild = mdiArea->activeSubWindow(); newAct->setEnabled(true); openAct->setEnabled(true); - saveAct->setEnabled(hasMdiChild); - saveAsAct->setEnabled(hasMdiChild); - cutAct->setEnabled(hasModelSelected); - copyAct->setEnabled(hasModelSelected); - pasteAct->setEnabled(hasMdiChild ? activeMdiChild()->hasPasteData() : false); - writeEepromAct->setEnabled(hasMdiChild); + saveAct->setEnabled(activeChild); + saveAsAct->setEnabled(activeChild); + closeAct->setEnabled(activeChild); + compareAct->setEnabled(activeChild); + writeEepromAct->setEnabled(activeChild); readEepromAct->setEnabled(true); - writeBackupToRadioAct->setEnabled(true); - readBackupToFileAct->setEnabled(true); - for (int i=0; isetEnabled(true); + writeBUToRadioAct->setEnabled(true); + readBUToFileAct->setEnabled(true); + + foreach (QAction * act, fileWindowActions) { + if (!act) + continue; + if (fileMenu && fileMenu->actions().contains(act)) + fileMenu->removeAction(act); + if (fileToolBar && fileToolBar->actions().contains(act)) { + fileToolBar->removeAction(act); + } + if (act->isSeparator() && act->parent() == this) + delete act; } - separatorAct->setVisible(hasMdiChild); - simulateAct->setEnabled(hasMdiChild); - printAct->setEnabled(hasModelSelected); - loadbackupAct->setEnabled(hasMdiChild); - compareAct->setEnabled(activeMdiChild()); + fileWindowActions.clear(); + if (activeChild) { + editMenu->clear(); + editMenu->addActions(activeMdiChild()->getEditActions()); + editMenu->addSeparator(); + editMenu->addActions(activeMdiChild()->getModelActions()); // maybe separate menu/toolbar? + editMenu->setEnabled(true); + + editToolBar->clear(); + editToolBar->addActions(activeMdiChild()->getEditActions()); + editToolBar->setEnabled(true); + if (activeMdiChild()->getAction(MdiChild::ACT_MDL_MOV)) { + // workaround for default split button appearance of action with menu :-/ + QToolButton * btn; + if ((btn = qobject_cast(editToolBar->widgetForAction(activeMdiChild()->getAction(MdiChild::ACT_MDL_MOV))))) + btn->setPopupMode(QToolButton::InstantPopup); + } + + fileWindowActions = activeMdiChild()->getGeneralActions(); + QAction *sep = new QAction(this); + sep->setSeparator(true); + fileWindowActions.append(sep); + fileMenu->insertActions(logsAct, fileWindowActions); + fileToolBar->insertActions(logsAct, fileWindowActions); + } + else { + editToolBar->setDisabled(true); + editMenu->setDisabled(true); + } + + foreach (QAction * act, windowsListActions->actions()) { + if (act->property("window_ptr").canConvert() && + act->property("window_ptr").value() == activeChild) { + act->setChecked(true); + break; + } + } + updateRecentFileActions(); updateProfilesActions(); setWindowTitle(tr("OpenTX Companion %1 - Radio: %2 - Profile: %3").arg(VERSION).arg(getCurrentFirmware()->getName()).arg(g.profile[g.id()].name())); @@ -966,53 +1001,51 @@ void MainWindow::updateMenus() MdiChild * MainWindow::createMdiChild() { - MdiChild * child = new MdiChild(this); - mdiArea->addSubWindow(child); - if (!child->parentWidget()->isMaximized() && !child->parentWidget()->isMinimized()) { - child->parentWidget()->resize(400, 400); - } + QMdiSubWindow * win = new QMdiSubWindow(); + MdiChild * child = new MdiChild(this, win); + win->setAttribute(Qt::WA_DeleteOnClose); + win->setWidget(child); + mdiArea->addSubWindow(win); + if (g.mdiWinGeo().size() < 10 && g.mdiWinGeo() == "maximized") + win->showMaximized(); - connect(child, SIGNAL(copyAvailable(bool)),cutAct, SLOT(setEnabled(bool))); - connect(child, SIGNAL(copyAvailable(bool)),copyAct, SLOT(setEnabled(bool))); - connect(child, SIGNAL(copyAvailable(bool)),simulateAct, SLOT(setEnabled(bool))); - connect(child, SIGNAL(copyAvailable(bool)),printAct, SLOT(setEnabled(bool))); + connect(this, &MainWindow::firmwareChanged, child, &MdiChild::onFirmwareChanged); + connect(child, &MdiChild::windowTitleChanged, this, &MainWindow::onSubwindowTitleChanged); + connect(child, &MdiChild::modified, this, &MainWindow::onSubwindowModified); + connect(child, &MdiChild::newStatusMessage, statusBar(), &QStatusBar::showMessage); + connect(win, &QMdiSubWindow::destroyed, this, &MainWindow::updateWindowActions); + updateWindowActions(); return child; } -QAction * MainWindow::addAct(const QString & icon, const QString & sName, const QString & lName, enum QKeySequence::StandardKey shortcut, const char *slot, QObject *slotObj) -{ - return addAct(icon, sName, lName, QKeySequence(shortcut), slot, slotObj); -} - -QAction * MainWindow::addAct(const QString & icon, const QString & sName, const QString & lName, const QKeySequence & shortcut, const char *slot, QObject *slotObj) +QAction * MainWindow::addAct(const QString & icon, const char *slot, const QKeySequence & shortcut, QObject *slotObj, const char * signal) { QAction * newAction = new QAction( this ); + newAction->setMenuRole(QAction::NoRole); if (!icon.isEmpty()) newAction->setIcon(CompanionIcon(icon)); - if (!sName.isEmpty()) - newAction->setText(sName); - if (!lName.isEmpty()) - newAction->setStatusTip(lName); - newAction->setShortcut(shortcut); - if (slotObj == NULL) - slotObj = this; - connect(newAction, SIGNAL(triggered()), slotObj, slot); - actionsList.append(newAction); + if (!shortcut.isEmpty()) + newAction->setShortcut(shortcut); + if (slot) { + if (!slotObj) + slotObj = this; + if (!signal) + connect(newAction, SIGNAL(triggered()), slotObj, slot); + else + connect(newAction, signal, slotObj, slot); + } return newAction; } - -QAction * MainWindow::addAct(const QString & icon, const QString & sName, const QString & lName, const char *slot) -{ - return addAct(icon, sName, lName, QKeySequence::UnknownKey, slot); -} - -QAction * MainWindow::addActToGroup(QActionGroup * aGroup, const QString & sName, const QString & lName, const char * propName, const QVariant & propValue, const QVariant & dfltValue) +QAction * MainWindow::addActToGroup(QActionGroup * aGroup, const QString & sName, const QString & lName, const char * propName, const QVariant & propValue, const QVariant & dfltValue, const QKeySequence & shortcut) { QAction * act = aGroup->addAction(sName); + act->setMenuRole(QAction::NoRole); act->setStatusTip(lName); act->setCheckable(true); + if (!shortcut.isEmpty()) + act->setShortcut(shortcut); if (propName) { act->setProperty(propName, propValue); if (propValue == dfltValue) @@ -1021,77 +1054,292 @@ QAction * MainWindow::addActToGroup(QActionGroup * aGroup, const QString & sName return act; } +void MainWindow::trAct(QAction * act, const QString & text, const QString & descript) +{ + if (!text.isEmpty()) + act->setText(text); + if (!descript.isEmpty()) + act->setStatusTip(descript); +} + +void MainWindow::retranslateUi(bool showMsg) +{ + trAct(newAct, tr("New"), tr("Create a new Models and Settings file")); + trAct(openAct, tr("Open..."), tr("Open Models and Settings file")); + trAct(saveAct, tr("Save"), tr("Save Models and Settings file")); + trAct(saveAsAct, tr("Save As..."), tr("Save Models and Settings file")); + trAct(closeAct, tr("Close"), tr("Close Models and Settings file")); + trAct(exitAct, tr("Exit"), tr("Exit the application")); + trAct(aboutAct, tr("About..."), tr("Show the application's About box")); + + trAct(recentFilesAct, tr("Recent Files"), tr("List of recently used files")); + trAct(profilesMenuAct, tr("Radio Profiles"), tr("Create or Select Radio Profiles")); + trAct(logsAct, tr("View Log File..."), tr("Open and view log file")); + trAct(appPrefsAct, tr("Settings..."), tr("Edit Settings")); + trAct(fwPrefsAct, tr("Download..."), tr("Download firmware and voice files")); + trAct(checkForUpdatesAct, tr("Check for Updates..."), tr("Check OpenTX and Companion updates")); + trAct(changelogAct, tr("Companion Changes..."), tr("Show Companion change log")); + trAct(fwchangelogAct, tr("Firmware Changes..."), tr("Show firmware change log")); + trAct(compareAct, tr("Compare Models..."), tr("Compare models")); + trAct(editSplashAct, tr("Edit Radio Splash Image..."), tr("Edit the splash image of your Radio")); + trAct(burnListAct, tr("List programmers..."), tr("List available programmers")); + trAct(burnFusesAct, tr("Fuses..."), tr("Show fuses dialog")); + trAct(readFlashAct, tr("Read Firmware from Radio"), tr("Read firmware from Radio")); + trAct(writeFlashAct, tr("Write Firmware to Radio"), tr("Write firmware to Radio")); + trAct(sdsyncAct, tr("Synchronize SD"), tr("SD card synchronization")); + + trAct(openDocURLAct, tr("Manuals and other Documents"), tr("Open the OpenTX document page in a web browser")); + trAct(writeEepromAct, tr("Write Models and Settings To Radio"), tr("Write Models and Settings to Radio")); + trAct(readEepromAct, tr("Read Models and Settings From Radio"), tr("Read Models and Settings from Radio")); + trAct(burnConfigAct, tr("Configure Communications..."), tr("Configure software for communicating with the Radio")); + trAct(writeBUToRadioAct, tr("Write Backup to Radio"), tr("Write Backup from file to Radio")); + trAct(readBUToFileAct, tr("Backup Radio to File"), tr("Save a complete backup file of all settings and model data in the Radio")); + trAct(contributorsAct, tr("Contributors..."), tr("A tribute to those who have contributed to OpenTX and Companion")); + + trAct(createProfileAct, tr("Add Radio Profile"), tr("Create a new Radio Settings Profile")); + trAct(copyProfileAct, tr("Copy Current Radio Profile"), tr("Duplicate current Radio Settings Profile")); + trAct(deleteProfileAct, tr("Delete Current Radio Profile..."), tr("Delete the current Radio Settings Profile")); + + trAct(actTabbedWindows, tr("Tabbed Windows"), tr("Use tabs to arrange open windows.")); + trAct(actTileWindows, tr("Tile Windows"), tr("Arrange open windows across all the available space.")); + trAct(actCascadeWindows, tr("Cascade Windows"), tr("Arrange all open windows in a stack.")); + trAct(actCloseAllWindows, tr("Close All Windows"), tr("Closes all open files (prompts to save if necessary.")); + + editMenu->setTitle(tr("Edit")); + fileMenu->setTitle(tr("File")); + settingsMenu->setTitle(tr("Settings")); + themeMenu->setTitle(tr("Set Icon Theme")); + iconThemeSizeMenu->setTitle(tr("Set Icon Size")); + burnMenu->setTitle(tr("Read/Write")); + windowMenu->setTitle(tr("Window")); + helpMenu->setTitle(tr("Help")); + + fileToolBar->setWindowTitle(tr("File")); + editToolBar->setWindowTitle(tr("Edit")); + burnToolBar->setWindowTitle(tr("Write")); + helpToolBar->setWindowTitle(tr("Help")); + + showReadyStatus(); + + if (showMsg) + QMessageBox::information(this, tr("Companion"), tr("Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete.")); +} + void MainWindow::createActions() { - foreach (QAction * act, actionsList) { - if (act) - act->deleteLater(); + newAct = addAct("new.png", SLOT(newFile()), QKeySequence::New); + openAct = addAct("open.png", SLOT(openFile()), QKeySequence::Open); + saveAct = addAct("save.png", SLOT(save()), QKeySequence::Save); + saveAsAct = addAct("saveas.png", SLOT(saveAs()), tr("Ctrl+Shift+S")); // Windows doesn't have "native" save-as key, Lin/OSX both use this one anyway + closeAct = addAct("clear.png", SLOT(closeFile()) /*, QKeySequence::Close*/); // setting/showing this shortcut interferes with the system one (Ctrl+W/Ctrl-F4) + exitAct = addAct("exit.png", SLOT(closeAllWindows()), QKeySequence::Quit, qApp); + + logsAct = addAct("logs.png", SLOT(logFile()), tr("Ctrl+Alt+L")); + appPrefsAct = addAct("apppreferences.png", SLOT(appPrefs()), QKeySequence::Preferences); + fwPrefsAct = addAct("fwpreferences.png", SLOT(fwPrefs()), tr("Ctrl+Alt+D")); + compareAct = addAct("compare.png", SLOT(compare()), tr("Ctrl+Alt+R")); + sdsyncAct = addAct("sdsync.png", SLOT(sdsync())); + + editSplashAct = addAct("paintbrush.png", SLOT(customizeSplash())); + burnListAct = addAct("list.png", SLOT(burnList())); + burnFusesAct = addAct("fuses.png", SLOT(burnFuses())); + readFlashAct = addAct("read_flash.png", SLOT(readFlash())); + writeFlashAct = addAct("write_flash.png", SLOT(writeFlash())); + writeEepromAct = addAct("write_eeprom.png", SLOT(writeEeprom())); + readEepromAct = addAct("read_eeprom.png", SLOT(readEeprom())); + burnConfigAct = addAct("configure.png", SLOT(burnConfig())); + writeBUToRadioAct = addAct("write_eeprom_file.png", SLOT(writeBackup())); + readBUToFileAct = addAct("read_eeprom_file.png", SLOT(readBackup())); + + createProfileAct = addAct("new.png", SLOT(createProfile())); + copyProfileAct = addAct("copy.png", SLOT(copyProfile())); + deleteProfileAct = addAct("clear.png", SLOT(deleteCurrentProfile())); + + actTabbedWindows = addAct("", SLOT(setTabbedWindows(bool)), 0, this, SIGNAL(triggered(bool))); + actTileWindows = addAct("", SLOT(tileSubWindows()), 0, mdiArea); + actCascadeWindows = addAct("", SLOT(cascadeSubWindows()), 0, mdiArea); + actCloseAllWindows = addAct("", SLOT(closeAllSubWindows()), 0, mdiArea); + + checkForUpdatesAct = addAct("update.png", SLOT(doUpdates())); + aboutAct = addAct("information.png", SLOT(about())); + openDocURLAct = addAct("changelog.png", SLOT(openDocURL())); + changelogAct = addAct("changelog.png", SLOT(changelog())); + fwchangelogAct = addAct("changelog.png", SLOT(fwchangelog())); + contributorsAct = addAct("contributors.png", SLOT(contributors())); + + // these two get assigned menus in createMenus() + recentFilesAct = addAct("recentdocument.png"); + profilesMenuAct = addAct("profiles.png"); + + exitAct->setMenuRole(QAction::QuitRole); + aboutAct->setMenuRole(QAction::AboutRole); + appPrefsAct->setMenuRole(QAction::PreferencesRole); + contributorsAct->setMenuRole(QAction::ApplicationSpecificRole); + openDocURLAct->setMenuRole(QAction::ApplicationSpecificRole); + checkForUpdatesAct->setMenuRole(QAction::ApplicationSpecificRole); + changelogAct->setMenuRole(QAction::ApplicationSpecificRole); + fwchangelogAct->setMenuRole(QAction::ApplicationSpecificRole); + + actTabbedWindows->setCheckable(true); + compareAct->setEnabled(false); +} + +void MainWindow::createMenus() +{ + fileMenu = menuBar()->addMenu(""); + fileMenu->addAction(newAct); + fileMenu->addAction(openAct); + fileMenu->addAction(saveAct); + fileMenu->addAction(saveAsAct); + fileMenu->addAction(closeAct); + fileMenu->addAction(recentFilesAct); + fileMenu->addSeparator(); + fileMenu->addAction(logsAct); + fileMenu->addAction(fwPrefsAct); + fileMenu->addAction(compareAct); + fileMenu->addAction(sdsyncAct); + fileMenu->addSeparator(); + fileMenu->addAction(exitAct); + + editMenu = menuBar()->addMenu(""); + + settingsMenu = menuBar()->addMenu(""); + settingsMenu->addMenu(createLanguageMenu(settingsMenu)); + + themeMenu = settingsMenu->addMenu(""); + QActionGroup * themeGroup = new QActionGroup(themeMenu); + addActToGroup(themeGroup, tr("Classical"), tr("The classic companion9x icon theme"), "themeId", 0, g.theme()); + addActToGroup(themeGroup, tr("Yerico"), tr("Yellow round honey sweet icon theme"), "themeId", 1, g.theme()); + addActToGroup(themeGroup, tr("Monochrome"), tr("A monochrome black icon theme"), "themeId", 3, g.theme()); + addActToGroup(themeGroup, tr("MonoBlue"), tr("A monochrome blue icon theme"), "themeId", 4, g.theme()); + addActToGroup(themeGroup, tr("MonoWhite"), tr("A monochrome white icon theme"), "themeId", 2, g.theme()); + connect(themeGroup, &QActionGroup::triggered, this, &MainWindow::onThemeChanged); + themeMenu->addActions(themeGroup->actions()); + + iconThemeSizeMenu = settingsMenu->addMenu(""); + QActionGroup * szGroup = new QActionGroup(iconThemeSizeMenu); + addActToGroup(szGroup, tr("Small"), tr("Use small toolbar icons"), "sizeId", 0, g.iconSize()); + addActToGroup(szGroup, tr("Normal"), tr("Use normal size toolbar icons"), "sizeId", 1, g.iconSize()); + addActToGroup(szGroup, tr("Big"), tr("Use big toolbar icons"), "sizeId", 2, g.iconSize()); + addActToGroup(szGroup, tr("Huge"), tr("Use huge toolbar icons"), "sizeId", 3, g.iconSize()); + connect(szGroup, &QActionGroup::triggered, this, &MainWindow::onIconSizeChanged); + iconThemeSizeMenu->addActions(szGroup->actions()); + + settingsMenu->addSeparator(); + settingsMenu->addAction(appPrefsAct); + settingsMenu->addAction(profilesMenuAct); + settingsMenu->addAction(editSplashAct); + settingsMenu->addAction(burnConfigAct); + + burnMenu = menuBar()->addMenu(""); + burnMenu->addAction(writeEepromAct); + burnMenu->addAction(readEepromAct); + burnMenu->addSeparator(); + burnMenu->addAction(writeBUToRadioAct); + burnMenu->addAction(readBUToFileAct); + burnMenu->addSeparator(); + burnMenu->addAction(writeFlashAct); + burnMenu->addAction(readFlashAct); + burnMenu->addSeparator(); + burnMenu->addSeparator(); + if (!IS_ARM(getCurrentBoard())) { + burnMenu->addAction(burnFusesAct); + burnMenu->addAction(burnListAct); } - actionsList.clear(); - separatorAct = new QAction(this); - separatorAct->setSeparator(true); - actionsList.append(separatorAct); + windowMenu = menuBar()->addMenu(""); + windowMenu->addAction(actTabbedWindows); + windowMenu->addAction(actTileWindows); + windowMenu->addAction(actCascadeWindows); + windowMenu->addAction(actCloseAllWindows); + windowMenu->addSeparator(); - for (int i = 0; i < MAX_RECENT; ++i) { - recentFileActs[i] = new QAction(this); + helpMenu = menuBar()->addMenu(""); + helpMenu->addSeparator(); + helpMenu->addAction(checkForUpdatesAct); + helpMenu->addSeparator(); + helpMenu->addAction(aboutAct); + helpMenu->addAction(openDocURLAct); + helpMenu->addSeparator(); + helpMenu->addAction(changelogAct); + helpMenu->addAction(fwchangelogAct); + helpMenu->addSeparator(); + helpMenu->addAction(contributorsAct); + + recentFilesMenu = new QMenu(this); + for ( int i = 0; i < g.historySize(); ++i) { + recentFileActs.append(recentFilesMenu->addAction("")); recentFileActs[i]->setVisible(false); connect(recentFileActs[i], SIGNAL(triggered()), this, SLOT(openRecentFile())); - actionsList.append(recentFileActs[i]); } - updateRecentFileActions(); + recentFilesAct->setMenu(recentFilesMenu); - QActionGroup *profilesAlignmentGroup = new QActionGroup(this); - for (int i=0; iaddAction("")); profileActs[i]->setVisible(false); profileActs[i]->setCheckable(true); connect(profileActs[i], SIGNAL(triggered()), this, SLOT(loadProfile())); - actionsList.append(profileActs[i]); + profilesGroup->addAction(profileActs[i]); } - updateProfilesActions(); + profilesMenu->addSeparator(); + profilesMenu->addAction(createProfileAct); + profilesMenu->addAction(copyProfileAct); + profilesMenu->addAction(deleteProfileAct); + profilesMenuAct->setMenu(profilesMenu); +} - newAct = addAct("new.png", tr("New"), tr("Create a new Models and Settings file"), QKeySequence::New, SLOT(newFile())); - openAct = addAct("open.png", tr("Open..."), tr("Open Models and Settings file"), QKeySequence::Open, SLOT(openFile())); - saveAct = addAct("save.png", tr("Save"), tr("Save Models and Settings file"), QKeySequence::Save, SLOT(save())); - saveAsAct = addAct("saveas.png", tr("Save As..."), tr("Save Models and Settings file"), QKeySequence::SaveAs, SLOT(saveAs())); - exitAct = addAct("exit.png", tr("Exit"), tr("Exit the application"), QKeySequence::Quit, SLOT(closeAllWindows()), qApp); - cutAct = addAct("cut.png", tr("Cut Model"), tr("Cut current model to the clipboard"), QKeySequence::Cut, SLOT(cut())); - copyAct = addAct("copy.png", tr("Copy Model"), tr("Copy current model to the clipboard"), QKeySequence::Copy, SLOT(copy())); - pasteAct = addAct("paste.png", tr("Paste Model"), tr("Paste model from clipboard"), QKeySequence::Paste, SLOT(paste())); +void MainWindow::createToolBars() +{ + fileToolBar = addToolBar(""); + fileToolBar->setObjectName("File"); + fileToolBar->addAction(newAct); + fileToolBar->addAction(openAct); + fileToolBar->addAction(recentFilesAct); + fileToolBar->addAction(saveAct); + fileToolBar->addAction(closeAct); + fileToolBar->addSeparator(); + fileToolBar->addAction(logsAct); + fileToolBar->addAction(fwPrefsAct); + fileToolBar->addSeparator(); + fileToolBar->addAction(appPrefsAct); + fileToolBar->addAction(profilesMenuAct); + fileToolBar->addAction(editSplashAct); + fileToolBar->addAction(editSplashAct); + fileToolBar->addSeparator(); + fileToolBar->addAction(compareAct); + fileToolBar->addAction(sdsyncAct); - aboutAct = addAct("information.png", tr("About..."), tr("Show the application's About box"), SLOT(about())); - printAct = addAct("print.png", tr("Print..."), tr("Print current model"), QKeySequence::Print, SLOT(print())); - simulateAct = addAct("simulate.png", tr("Simulate..."), tr("Simulate current model"), QKeySequence(tr("Alt+S")), SLOT(simulate())); - loadbackupAct = addAct("open.png", tr("Load Backup..."), tr("Load backup from file"), SLOT(loadBackup())); - logsAct = addAct("logs.png", tr("View Log File..."), tr("Open and view log file"), SLOT(logFile())); - appPrefsAct = addAct("apppreferences.png",tr("Settings..."), tr("Edit Settings"), SLOT(appPrefs())); - fwPrefsAct = addAct("fwpreferences.png", tr("Download..."), tr("Download firmware and voice files"), SLOT(fwPrefs())); - checkForUpdatesAct = addAct("update.png", tr("Check for Updates..."), tr("Check OpenTX and Companion updates"), SLOT(doUpdates())); - changelogAct = addAct("changelog.png", tr("Companion Changes..."), tr("Show Companion change log"), SLOT(changelog())); - fwchangelogAct = addAct("changelog.png", tr("Firmware Changes..."), tr("Show firmware change log"), SLOT(fwchangelog())); - compareAct = addAct("compare.png", tr("Compare Models..."), tr("Compare models"), SLOT(compare())); - editSplashAct = addAct("paintbrush.png", tr("Edit Radio Splash Image..."), tr("Edit the splash image of your Radio"), SLOT(customizeSplash())); - burnListAct = addAct("list.png", tr("List programmers..."), tr("List available programmers"), SLOT(burnList())); - burnFusesAct = addAct("fuses.png", tr("Fuses..."), tr("Show fuses dialog"), SLOT(burnFuses())); - readFlashAct = addAct("read_flash.png", tr("Read Firmware from Radio"),tr("Read firmware from Radio"), SLOT(readFlash())); - writeFlashAct = addAct("write_flash.png", tr("Write Firmware to Radio"), tr("Write firmware to Radio"), SLOT(writeFlash())); - openDocURLAct = addAct("", tr("Manuals and other Documents"), tr("Open the OpenTX document page in a web browser"), SLOT(openDocURL())); - writeEepromAct = addAct("write_eeprom.png", tr("Write Models and Settings To Radio"), tr("Write Models and Settings to Radio"), SLOT(writeEeprom())); - readEepromAct = addAct("read_eeprom.png", tr("Read Models and Settings From Radio"), tr("Read Models and Settings from Radio"), SLOT(readEeprom())); - burnConfigAct = addAct("configure.png", tr("Configure Communications..."), tr("Configure software for communicating with the Radio"), SLOT(burnConfig())); - writeBackupToRadioAct = addAct("write_eeprom_file.png", tr("Write Backup to Radio"), tr("Write Backup from file to Radio"), SLOT(writeBackup())); - readBackupToFileAct = addAct("read_eeprom_file.png", tr("Backup Radio to File"), tr("Save a complete backup file of all settings and model data in the Radio"), SLOT(readBackup())); - contributorsAct = addAct("contributors.png", tr("Contributors..."), tr("A tribute to those who have contributed to OpenTX and Companion"), SLOT(contributors())); - sdsyncAct = addAct("sdsync.png", tr("Synchronize SD"), tr("SD card synchronization"), SLOT(sdsync())); + // workaround for default split button appearance of action with menu :-/ + QToolButton * btn; + if ((btn = qobject_cast(fileToolBar->widgetForAction(recentFilesAct)))) + btn->setPopupMode(QToolButton::InstantPopup); + if ((btn = qobject_cast(fileToolBar->widgetForAction(profilesMenuAct)))) + btn->setPopupMode(QToolButton::InstantPopup); - createProfileAct = addAct("new.png", tr("Add Radio Profile"), tr("Create a new Radio Settings Profile"), SLOT(createProfile())); - copyProfileAct = addAct("copy.png", tr("Copy Current Radio Profile"), tr("Duplicate current Radio Settings Profile"), SLOT(copyProfile())); - deleteProfileAct = addAct("clear.png", tr("Delete Current Radio Profile"), tr("Delete the current Radio Settings Profile"), SLOT(deleteCurrentProfile())); + // gets populated later + editToolBar = addToolBar(""); + editToolBar->setObjectName("Edit"); - compareAct->setEnabled(false); - simulateAct->setEnabled(false); - printAct->setEnabled(false); + burnToolBar = new QToolBar(this); + addToolBar( Qt::LeftToolBarArea, burnToolBar ); + burnToolBar->setObjectName("Write"); + burnToolBar->addAction(writeEepromAct); + burnToolBar->addAction(readEepromAct); + burnToolBar->addSeparator(); + burnToolBar->addAction(writeBUToRadioAct); + burnToolBar->addAction(readBUToFileAct); + burnToolBar->addSeparator(); + burnToolBar->addAction(writeFlashAct); + burnToolBar->addAction(readFlashAct); + burnToolBar->addSeparator(); + burnToolBar->addAction(burnConfigAct); + + helpToolBar = addToolBar(""); + helpToolBar->setObjectName("Help"); + helpToolBar->addAction(checkForUpdatesAct); + helpToolBar->addAction(aboutAct); } QMenu * MainWindow::createLanguageMenu(QWidget * parent) @@ -1114,246 +1362,7 @@ QMenu * MainWindow::createLanguageMenu(QWidget * parent) return menu; } -void MainWindow::createMenus() -{ - menuBar()->clear(); - - if (fileMenu) { - fileMenu->deleteLater(); - } - fileMenu = menuBar()->addMenu(tr("File")); - fileMenu->addAction(newAct); - fileMenu->addAction(openAct); - fileMenu->addAction(saveAct); - fileMenu->addAction(saveAsAct); - - QMenu *recentFileMenu = new QMenu(tr("Recent Files"), fileMenu); - recentFileMenu->setIcon(CompanionIcon("recentdocument.png")); - for (int i=0; iaddAction(recentFileActs[i]); - } - - fileMenu->addMenu(recentFileMenu); - fileMenu->addSeparator(); - fileMenu->addAction(logsAct); - fileMenu->addAction(fwPrefsAct); - fileMenu->addSeparator(); - fileMenu->addAction(simulateAct); - fileMenu->addAction(printAct); - fileMenu->addAction(compareAct); - fileMenu->addAction(sdsyncAct); - fileMenu->addSeparator(); - fileMenu->addAction(exitAct); - - if (editMenu) { - editMenu->deleteLater(); - } - editMenu = menuBar()->addMenu(tr("Edit")); - editMenu->addAction(cutAct); - editMenu->addAction(copyAct); - editMenu->addAction(pasteAct); - - if (settingsMenu) { - settingsMenu->deleteLater(); - } - settingsMenu = menuBar()->addMenu(tr("Settings")); - - QMenu *themeMenu = new QMenu(tr("Set Icon Theme"), settingsMenu); - QActionGroup * themeGroup = new QActionGroup(themeMenu); - addActToGroup(themeGroup, tr("Classical"), tr("The classic companion9x icon theme"), "themeId", 0, g.theme()); - addActToGroup(themeGroup, tr("Yerico"), tr("Yellow round honey sweet icon theme"), "themeId", 1, g.theme()); - addActToGroup(themeGroup, tr("Monochrome"), tr("A monochrome black icon theme"), "themeId", 3, g.theme()); - addActToGroup(themeGroup, tr("MonoBlue"), tr("A monochrome blue icon theme"), "themeId", 4, g.theme()); - addActToGroup(themeGroup, tr("MonoWhite"), tr("A monochrome white icon theme"), "themeId", 2, g.theme()); - connect(themeGroup, &QActionGroup::triggered, this, &MainWindow::onThemeChanged); - themeMenu->addActions(themeGroup->actions()); - - QMenu *iconThemeSizeMenu = new QMenu(tr("Set Icon Size"), settingsMenu); - QActionGroup * szGroup = new QActionGroup(iconThemeSizeMenu); - addActToGroup(szGroup, tr("Small"), tr("Use small toolbar icons"), "sizeId", 0, g.iconSize()); - addActToGroup(szGroup, tr("Normal"), tr("Use normal size toolbar icons"), "sizeId", 1, g.iconSize()); - addActToGroup(szGroup, tr("Big"), tr("Use big toolbar icons"), "sizeId", 2, g.iconSize()); - addActToGroup(szGroup, tr("Huge"), tr("Use huge toolbar icons"), "sizeId", 3, g.iconSize()); - connect(szGroup, &QActionGroup::triggered, this, &MainWindow::onIconSizeChanged); - iconThemeSizeMenu->addActions(szGroup->actions()); - - settingsMenu->addMenu(createLanguageMenu(settingsMenu)); - settingsMenu->addMenu(themeMenu); - settingsMenu->addMenu(iconThemeSizeMenu); - settingsMenu->addSeparator(); - settingsMenu->addAction(appPrefsAct); - settingsMenu->addMenu(createProfilesMenu()); - settingsMenu->addAction(editSplashAct); - settingsMenu->addAction(burnConfigAct); - - if (burnMenu) { - burnMenu->deleteLater(); - } - burnMenu = menuBar()->addMenu(tr("Read/Write")); - burnMenu->addAction(writeEepromAct); - burnMenu->addAction(readEepromAct); - burnMenu->addSeparator(); - burnMenu->addAction(writeBackupToRadioAct); - burnMenu->addAction(readBackupToFileAct); - burnMenu->addSeparator(); - burnMenu->addAction(writeFlashAct); - burnMenu->addAction(readFlashAct); - burnMenu->addSeparator(); - burnMenu->addSeparator(); - if (!IS_ARM(getCurrentBoard())) { - burnMenu->addAction(burnFusesAct); - burnMenu->addAction(burnListAct); - } - - if (helpMenu) { - helpMenu->deleteLater(); - } - helpMenu = menuBar()->addMenu(tr("Help")); - helpMenu->addSeparator(); - helpMenu->addAction(checkForUpdatesAct); - helpMenu->addSeparator(); - helpMenu->addAction(aboutAct); - helpMenu->addAction(openDocURLAct); - helpMenu->addSeparator(); - helpMenu->addAction(changelogAct); - helpMenu->addAction(fwchangelogAct); - helpMenu->addSeparator(); - helpMenu->addAction(contributorsAct); -} - -QMenu *MainWindow::createRecentFileMenu() -{ - QMenu *recentFileMenu = new QMenu(this); - for ( int i = 0; i < MAX_RECENT; ++i) { - recentFileMenu->addAction(recentFileActs[i]); - } - return recentFileMenu; -} - -QMenu *MainWindow::createProfilesMenu() -{ - QMenu *profilesMenu=new QMenu(tr("Radio Profile"), this); - for (int i = 0; i < MAX_PROFILES; ++i) { - profilesMenu->addAction(profileActs[i]); - } - profilesMenu->addSeparator(); - - profilesMenu->addAction(createProfileAct); - profilesMenu->addAction(copyProfileAct); - profilesMenu->addAction(deleteProfileAct); - profilesMenu->setIcon(CompanionIcon("profiles.png")); - return profilesMenu; -} - -void MainWindow::createToolBars() -{ - QSize size; - switch(g.iconSize()) { - case 0: - size=QSize(16,16); - break; - case 1: - size=QSize(24,24); - break; - case 2: - size=QSize(32,32); - break; - case 3: - size=QSize(48,48); - break; - default: - size=QSize(24,24); - break; - } - - if (fileToolBar) { - removeToolBar(fileToolBar); - fileToolBar->deleteLater(); - } - - fileToolBar = addToolBar(tr("File")); - fileToolBar->setIconSize(size); - fileToolBar->setObjectName("File"); - fileToolBar->addAction(newAct); - fileToolBar->addAction(openAct); - - QToolButton * recentToolButton = new QToolButton; - recentToolButton->setPopupMode(QToolButton::InstantPopup); - recentToolButton->setFocusPolicy(Qt::NoFocus); - recentToolButton->setMenu(createRecentFileMenu()); - recentToolButton->setIcon(CompanionIcon("recentdocument.png")); - recentToolButton->setToolTip(tr("Recent Models+Settings")); - recentToolButton->setStatusTip(tr("Show recent Models+Settings documents")); - - fileToolBar->addWidget(recentToolButton); - fileToolBar->addAction(saveAct); - fileToolBar->addSeparator(); - fileToolBar->addAction(logsAct); - fileToolBar->addAction(fwPrefsAct); - fileToolBar->addSeparator(); - fileToolBar->addAction(appPrefsAct); - - QToolButton * profileButton = new QToolButton; - profileButton->setPopupMode(QToolButton::InstantPopup); - profileButton->setFocusPolicy(Qt::NoFocus); - profileButton->setMenu(createProfilesMenu()); - profileButton->setIcon(CompanionIcon("profiles.png")); - profileButton->setToolTip(tr("Radio Profile")); - profileButton->setStatusTip(tr("Show the list of radio profiles")); - - fileToolBar->addWidget(profileButton); - fileToolBar->addAction(editSplashAct); - fileToolBar->addSeparator(); - fileToolBar->addAction(simulateAct); - fileToolBar->addAction(printAct); - fileToolBar->addAction(compareAct); - fileToolBar->addAction(sdsyncAct); - - if (editToolBar) { - removeToolBar(editToolBar); - editToolBar->deleteLater(); - } - - editToolBar = addToolBar(tr("Edit")); - editToolBar->setIconSize(size); - editToolBar->setObjectName("Edit"); - editToolBar->addAction(cutAct); - editToolBar->addAction(copyAct); - editToolBar->addAction(pasteAct); - - if (burnToolBar) { - removeToolBar(burnToolBar); - burnToolBar->deleteLater(); - } - - burnToolBar = new QToolBar(tr("Write")); - addToolBar( Qt::LeftToolBarArea, burnToolBar ); - burnToolBar->setIconSize(size); - burnToolBar->setObjectName("Write"); - burnToolBar->addAction(writeEepromAct); - burnToolBar->addAction(readEepromAct); - burnToolBar->addSeparator(); - burnToolBar->addAction(writeBackupToRadioAct); - burnToolBar->addAction(readBackupToFileAct); - burnToolBar->addSeparator(); - burnToolBar->addAction(writeFlashAct); - burnToolBar->addAction(readFlashAct); - burnToolBar->addSeparator(); - burnToolBar->addAction(burnConfigAct); - - if (helpToolBar) { - removeToolBar(helpToolBar); - helpToolBar->deleteLater(); - } - - helpToolBar = addToolBar(tr("Help")); - helpToolBar->setIconSize(size); - helpToolBar->setObjectName("Help"); - helpToolBar->addAction(checkForUpdatesAct); - helpToolBar->addAction(aboutAct); -} - -void MainWindow::createStatusBar() +void MainWindow::showReadyStatus() { statusBar()->showMessage(tr("Ready")); } @@ -1377,24 +1386,18 @@ QMdiSubWindow *MainWindow::findMdiChild(const QString &fileName) return 0; } -void MainWindow::setActiveSubWindow(QWidget *window) -{ - if (!window) return; - mdiArea->setActiveSubWindow(qobject_cast(window)); -} - void MainWindow::updateRecentFileActions() { // Hide all document slots - for (int i=0 ; isetVisible(false); } // Fill slots with content and unhide them QStringList files = g.recentFiles(); - int numRecentFiles = qMin(files.size(), g.historySize()); + int numRecentFiles = qMin(recentFileActs.size(), qMin(files.size(), g.historySize())); - for (int i=0; isetText(text); @@ -1406,7 +1409,7 @@ void MainWindow::updateRecentFileActions() void MainWindow::updateProfilesActions() { - for (int i=0; isetText(text); @@ -1421,6 +1424,77 @@ void MainWindow::updateProfilesActions() } } +void MainWindow::updateWindowActions() +{ + if (!windowsListActions) + return; + + foreach (QAction * act, windowsListActions->actions()) { + windowsListActions->removeAction(act); + if (windowMenu->actions().contains(act)) + windowMenu->removeAction(act); + delete act; + } + int count = 0; + foreach (QMdiSubWindow * win, mdiArea->subWindowList()) { + QString scut; + if (++count < 10) + scut = tr("Alt+%1").arg(count); + QAction * act = addActToGroup(windowsListActions, "", "", "window_ptr", qVariantFromValue(win), QVariant(), scut); + act->setChecked(win == mdiArea->activeSubWindow()); + updateWindowActionTitle(win, act); + } + windowMenu->addActions(windowsListActions->actions()); +} + +void MainWindow::updateWindowActionTitle(const QMdiSubWindow * win, QAction * act) +{ + MdiChild * child = qobject_cast(win->widget()); + if (!child) + return; + + if (!act) { + foreach (QAction * a, windowsListActions->actions()) { + if (a->property("window_ptr").canConvert() && + a->property("window_ptr").value() == win) { + act = a; + break; + } + } + } + if (!act) + return; + + QString ttl = child->userFriendlyCurrentFile(); + if (child->isWindowModified()) + ttl.prepend("* "); + act->setText(ttl); +} + +void MainWindow::onSubwindowTitleChanged() +{ + QMdiSubWindow * win = NULL; + if ((win = qobject_cast(sender()->parent()))) + updateWindowActionTitle(win); +} + +void MainWindow::onSubwindowModified() +{ + onSubwindowTitleChanged(); +} + +void MainWindow::onChangeWindowAction(QAction * act) +{ + if (!act->isChecked()) + return; + + QMdiSubWindow * win = NULL; + if (act->property("window_ptr").canConvert()) + win = act->property("window_ptr").value(); + if (win) + mdiArea->setActiveSubWindow(win); +} + int MainWindow::newProfile(bool loadProfile) { int i; diff --git a/companion/src/mainwindow.h b/companion/src/mainwindow.h index cd51184d4..f71e454d3 100644 --- a/companion/src/mainwindow.h +++ b/companion/src/mainwindow.h @@ -27,8 +27,6 @@ #include "eeprominterface.h" #define SPLASH_TIME 5 -#define MAX_RECENT 15 -#define MAX_PROFILES 15 class MdiChild; QT_BEGIN_NAMESPACE @@ -52,9 +50,10 @@ class MainWindow : public QMainWindow public: MainWindow(); + ~MainWindow(); signals: - void FirmwareChanged(); + void firmwareChanged(); protected: QString getCompanionUpdateBaseUrl(); @@ -70,7 +69,7 @@ class MainWindow : public QMainWindow private slots: void openDocURL(); - void retranslateUi(); + void retranslateUi(bool showMsg = false); void setLanguage(const QString & langString); void onLanguageChanged(QAction * act); @@ -78,6 +77,12 @@ class MainWindow : public QMainWindow void onThemeChanged(QAction * act); void setIconThemeSize(int index); void onIconSizeChanged(QAction * act); + void setTabbedWindows(bool on); + void onChangeWindowAction(QAction * act); + void updateWindowActions(); + void updateWindowActionTitle(const QMdiSubWindow * win, QAction * act = NULL); + void onSubwindowTitleChanged(); + void onSubwindowModified(); void checkForUpdates(); void checkForFirmwareUpdate(); @@ -94,13 +99,11 @@ class MainWindow : public QMainWindow void openFile(); void save(); void saveAs(); - void cut(); + void closeFile(); void openRecentFile(); void loadProfileId(const unsigned pid); void loadProfile(); void logFile(); - void copy(); - void paste(); void writeEeprom(); void readEeprom(); void writeFlash(QString fileToFlash=""); @@ -110,7 +113,6 @@ class MainWindow : public QMainWindow void burnConfig(); void burnList(); void burnFuses(); - void simulate(); void contributors(); void sdsync(); void changelog(); @@ -118,8 +120,6 @@ class MainWindow : public QMainWindow void customizeSplash(); void about(); void compare(); - void print(); - void loadBackup(); void appPrefs(); void fwPrefs(); void updateMenus(); @@ -127,7 +127,6 @@ class MainWindow : public QMainWindow void copyProfile(); void deleteProfile(const int pid); void deleteCurrentProfile(); - void setActiveSubWindow(QWidget *window); void autoClose(); void closeUpdatesWaitDialog(); @@ -135,20 +134,17 @@ class MainWindow : public QMainWindow void openFile(const QString & fileName, bool updateLastUsedDir = false); private: - QAction * addAct(const QString &, const QString &, const QString &, enum QKeySequence::StandardKey, const char *, QObject *slotObj=NULL); - QAction * addAct(const QString &, const QString &, const QString &, const QKeySequence &, const char *, QObject *slotObj=NULL); - QAction * addAct(const QString &, const QString &, const QString &, const char *); - QAction * addActToGroup(QActionGroup * aGroup, const QString & sName, const QString & lName, - const char * propName = 0, const QVariant & propValue = QVariant(), const QVariant & dfltValue = QVariant()); + QAction * addAct(const QString & icon, const char * slot = NULL, const QKeySequence & shortcut = 0, QObject * slotObj = NULL, const char * signal = NULL); + QAction * addActToGroup(QActionGroup * aGroup, const QString & sName, const QString & lName, const char * propName = 0, + const QVariant & propValue = QVariant(), const QVariant & dfltValue = QVariant(), const QKeySequence & shortcut = 0); + void trAct(QAction * act, const QString & text, const QString & descript); QMenu * createLanguageMenu(QWidget * parent = Q_NULLPTR); - QMenu * createRecentFileMenu(); - QMenu * createProfilesMenu(); void createActions(); void createMenus(); void createToolBars(); - void createStatusBar(); + void showReadyStatus(); void updateRecentFileActions(); void updateProfilesActions(); @@ -172,13 +168,21 @@ class MainWindow : public QMainWindow QNetworkAccessManager *networkManager; - QVector actionsList; + QVector recentFileActs; + QVector profileActs; + QList fileWindowActions; QMenu *fileMenu; QMenu *editMenu; QMenu *settingsMenu; QMenu *burnMenu; QMenu *helpMenu; + QMenu *windowMenu; + QMenu *iconThemeSizeMenu; + QMenu *themeMenu; + QMenu *recentFilesMenu; + QMenu *profilesMenu; + QActionGroup * windowsListActions; QToolBar *fileToolBar; QToolBar *editToolBar; QToolBar *burnToolBar; @@ -187,6 +191,8 @@ class MainWindow : public QMainWindow QAction *openAct; QAction *saveAct; QAction *saveAsAct; + QAction *closeAct; + QAction *recentFilesAct; QAction *exitAct; QAction *appPrefsAct; QAction *fwPrefsAct; @@ -197,9 +203,6 @@ class MainWindow : public QMainWindow QAction *fwchangelogAct; QAction *compareAct; QAction *editSplashAct; - QAction *cutAct; - QAction *copyAct; - QAction *pasteAct; QAction *writeEepromAct; QAction *readEepromAct; QAction *burnConfigAct; @@ -207,20 +210,19 @@ class MainWindow : public QMainWindow QAction *burnFusesAct; QAction *writeFlashAct; QAction *readFlashAct; - QAction *writeBackupToRadioAct; - QAction *readBackupToFileAct; - QAction *simulateAct; - QAction *separatorAct; + QAction *writeBUToRadioAct; + QAction *readBUToFileAct; QAction *aboutAct; - QAction *printAct; - QAction *loadbackupAct; QAction *logsAct; - QAction *recentFileActs[MAX_RECENT]; - QAction *profileActs[MAX_PROFILES]; + QAction *profilesMenuAct; QAction *createProfileAct; QAction *copyProfileAct; QAction *deleteProfileAct; QAction *openDocURLAct; + QAction *actTabbedWindows; + QAction *actTileWindows; + QAction *actCascadeWindows; + QAction *actCloseAllWindows; }; #endif // _MAINWINDOW_H_ diff --git a/companion/src/mdichild.cpp b/companion/src/mdichild.cpp index ac94dbdde..65cb37039 100644 --- a/companion/src/mdichild.cpp +++ b/companion/src/mdichild.cpp @@ -20,7 +20,6 @@ #include "mdichild.h" #include "ui_mdichild.h" -#include "mainwindow.h" #include "modeledit/modeledit.h" #include "generaledit/generaledit.h" #include "burnconfigdialog.h" @@ -33,37 +32,78 @@ #include "storage.h" #include "radiointerface.h" -MdiChild::MdiChild(MainWindow * parent): - QWidget(), - parent(parent), +#include + +MdiChild::MdiChild(QWidget * parent, QWidget * parentWin, Qt::WindowFlags f): + QWidget(parent, f), ui(new Ui::MdiChild), modelsListModel(NULL), + parentWindow(parentWin), + radioToolbar(NULL), + categoriesToolbar(NULL), + modelsToolbar(NULL), firmware(getCurrentFirmware()), + lastSelectedModel(-1), isUntitled(true), - fileChanged(false) + fileChanged(false), + showCatToolbar(true), + stateDataVersion(1) { ui->setupUi(this); setWindowIcon(CompanionIcon("open.png")); - ui->simulateButton->setIcon(CompanionIcon("simulate.png")); setAttribute(Qt::WA_DeleteOnClose); + setContextMenuPolicy(Qt::CustomContextMenu); + if (parentWindow) + parentWindow->setWindowIcon(windowIcon()); + + setupNavigation(); initModelsList(); - connect(parent, &MainWindow::FirmwareChanged, this, &MdiChild::onFirmwareChanged); - connect(ui->modelsList, &QTreeView::doubleClicked, this, &MdiChild::openModelEditWindow); - connect(ui->modelsList, &QTreeView::activated, this, &MdiChild::openModelEditWindow); - connect(ui->modelsList, &QTreeView::pressed, this, &MdiChild::onItemSelected); - connect(ui->modelsList, &QTreeView::customContextMenuRequested, this, &MdiChild::showModelsListContextMenu); - // connect(ui->modelsList, SIGNAL(currentItemChanged(QTreeWidgetItem *, QTreeWidgetItem *)), this, SLOT(onCurrentItemChanged(QTreeWidgetItem *, QTreeWidgetItem *))); ui->modelsList->setContextMenuPolicy(Qt::CustomContextMenu); ui->modelsList->setSelectionBehavior(QAbstractItemView::SelectRows); ui->modelsList->setSelectionMode(QAbstractItemView::ExtendedSelection); - // ui->modelsList->setDragEnabled(true); - // ui->modelsList->setAcceptDrops(true); - // ui->modelsList->setDragDropOverwriteMode(true); - // ui->modelsList->setDropIndicatorShown(true); + ui->modelsList->setEditTriggers(QAbstractItemView::DoubleClicked | QAbstractItemView::EditKeyPressed); + ui->modelsList->setDragEnabled(true); + ui->modelsList->setAcceptDrops(true); + ui->modelsList->setDragDropOverwriteMode(false); + ui->modelsList->setDropIndicatorShown(true); + ui->modelsList->setDragDropMode(QAbstractItemView::DragDrop); + ui->modelsList->setStyle(new ItemViewProxyStyle(ui->modelsList->style())); + ui->modelsList->setStyleSheet("QTreeView::item {margin: 2px 0;}"); // a little more space for our drop indicators + + retranslateUi(); + + connect(this, &MdiChild::customContextMenuRequested, this, &MdiChild::showContextMenu); + connect(ui->modelsList, &QTreeView::activated, this, &MdiChild::onItemActivated); + connect(ui->modelsList, &QTreeView::customContextMenuRequested, this, &MdiChild::showModelsListContextMenu); + connect(ui->modelsList, &QTreeView::pressed, this, &MdiChild::onItemSelected); + connect(ui->modelsList->selectionModel(), &QItemSelectionModel::currentRowChanged, this, &MdiChild::onCurrentItemChanged); if (!(isMaximized() || isMinimized())) { - adjustSize(); + QByteArray geo = g.mdiWinGeo(); + if (geo.isEmpty()) + adjustSize(); + else if (geo.size() < 10 && geo == "maximized") { + if (!parentWindow) // otherwise we let the MdiArea manage the window maximizing + setWindowState(windowState() ^ Qt::WindowMaximized); + } + else if (parentWindow) + parentWindow->restoreGeometry(geo); + else + restoreGeometry(geo); + } + if (!g.mdiWinState().isEmpty()) { + QByteArray state = g.mdiWinState(); + QDataStream stream(&state, QIODevice::ReadOnly); + quint16 ver; + stream >> ver; + if (ver <= stateDataVersion) { + bool visMdl, visGen; + stream >> showCatToolbar >> visMdl >> visGen; + categoriesToolbar->setVisible(showCatToolbar); + modelsToolbar->setVisible(visMdl); + radioToolbar->setVisible(visGen); + } } } @@ -72,80 +112,233 @@ MdiChild::~MdiChild() delete ui; } -void MdiChild::refresh(bool expand) +void MdiChild::closeEvent(QCloseEvent *event) { - modelsListModel->refresh(); - if (1 || expand) { - ui->modelsList->expandAll(); + if (!maybeSave()) { + event->ignore(); + return; } - ui->simulateButton->setEnabled(firmware->getCapability(Simulation)); - updateTitle(); -} - -void MdiChild::onItemSelected(QModelIndex idx) -{ - emit copyAvailable(isModel(idx) ? true : false); -} - -bool MdiChild::isModel(QModelIndex idx) -{ - return (modelsListModel->getModelIndex(idx) >= 0 ? true : false); -} - -bool MdiChild::isCategory(QModelIndex idx) -{ - if (isModel(idx)) { - return false; + if (!isMinimized()) { + QByteArray geo; + if (isMaximized()) + geo.append("maximized"); + else if (parentWindow) + geo = parentWindow->saveGeometry(); + else + geo = saveGeometry(); + g.mdiWinGeo(geo); } - else { - return (modelsListModel->getCategoryIndex(idx) >= 0); + + QByteArray state; + QDataStream stream(&state, QIODevice::WriteOnly); + stream << stateDataVersion + << (firmware->getCapability(Capability::HasModelCategories) ? categoriesToolbar->isVisible() : showCatToolbar) + << modelsToolbar->isVisible() + << radioToolbar->isVisible(); + g.mdiWinState(state); + + event->accept(); +} + +void MdiChild::resizeEvent(QResizeEvent * event) +{ + QWidget::resizeEvent(event); + adjustToolbarLayout(); +} + +QSize MdiChild::sizeHint() const +{ + QWidget * p; + if (parentWindow) + p = parentWindow->parentWidget(); + else + p = parentWidget(); + if (!p) + return QWidget::sizeHint(); + // use toolbar as a gauge for width, and take all the height availabe. + int w = qMax(ui->topToolbarLayout->sizeHint().width(), ui->botToolbarLayout->sizeHint().width()); + return QSize(w + 30, qMin(p->height(), 1000)); +} + +void MdiChild::changeEvent(QEvent * event) +{ + QWidget::changeEvent(event); + switch (event->type()) { + case QEvent::LanguageChange: + retranslateUi(); + break; + default: + break; } } -void MdiChild::confirmDelete() +QAction * MdiChild::addAct(Actions actId, const QString & icon, const char * slot, const QKeySequence & shortcut, QObject * slotObj) { - if (QMessageBox::warning(this, "Companion", tr("Delete selected models?"), QMessageBox::Yes | QMessageBox::No) == QMessageBox::Yes) { - deleteSelectedModels(); - } + QAction * newAction = new QAction(this); + newAction->setMenuRole(QAction::NoRole); + if (!icon.isEmpty()) + newAction->setIcon(CompanionIcon(icon)); + if (!shortcut.isEmpty()) + newAction->setShortcut(shortcut); + if (slotObj == NULL) + slotObj = this; + if (slot) + connect(newAction, SIGNAL(triggered()), slotObj, slot); + action.replace(actId, newAction); + return newAction; } -void MdiChild::deleteSelectedModels() +void MdiChild::setupNavigation() { - foreach (QModelIndex index, ui->modelsList->selectionModel()->selectedIndexes()) { - if (index.column() == 0) { - unsigned int modelIndex = modelsListModel->getModelIndex(index); - if (radioData.generalSettings.currModelIndex != modelIndex) { - qDebug() << "delete" << modelIndex; - radioData.models[modelIndex].clear(); - setModified(); - } - else { - QMessageBox::warning(this, "Companion", tr("Cannot delete default model."), QMessageBox::Ok); - } - } + foreach (QAction * act, action) { + if (act) + act->deleteLater(); } + action.clear(); + action.fill(NULL, ACT_ENUM_END); + + addAct(ACT_GEN_EDT, "edit.png", SLOT(generalEdit()), tr("Alt+Shift+E")); + addAct(ACT_GEN_CPY, "copy.png", SLOT(copyGeneralSettings()), tr("Ctrl+Alt+C")); + addAct(ACT_GEN_PST, "paste.png", SLOT(pasteGeneralSettings()), tr("Ctrl+Alt+V")); + addAct(ACT_GEN_SIM, "simulate.png", SLOT(radioSimulate()), tr("Alt+Shift+S")); + + addAct(ACT_ITM_EDT, "edit.png", SLOT(edit()), Qt::Key_Enter); + addAct(ACT_ITM_DEL, "clear.png", SLOT(confirmDelete()), QKeySequence::Delete); + + addAct(ACT_CAT_ADD, "add.png", SLOT(categoryAdd()), tr("Alt+C")); + //addAct(ACT_CAT_EDT, "edit.png", SLOT(edit()), Qt::Key_Enter); + //addAct(ACT_CAT_DEL, "clear.png", SLOT(confirmDelete()), QKeySequence::Delete); + action[ACT_CAT_SEP] = new QAction(this); + action[ACT_CAT_SEP]->setSeparator(true); + + addAct(ACT_MDL_ADD, "add.png", SLOT(modelAdd()), tr("Alt+A")); + addAct(ACT_MDL_RTR, "open.png", SLOT(loadBackup()), tr("Alt+R")); + addAct(ACT_MDL_WIZ, "wizard.png", SLOT(wizardEdit()), tr("Alt+W")); + + addAct(ACT_MDL_DFT, "currentmodel.png", SLOT(setDefault()), tr("Alt+U")); + addAct(ACT_MDL_PRT, "print.png", SLOT(print()), QKeySequence::Print); + addAct(ACT_MDL_SIM, "simulate.png", SLOT(modelSimulate()), tr("Alt+S")); + addAct(ACT_MDL_DUP, "duplicate.png", SLOT(modelDuplicate()), QKeySequence::Underline); + + addAct(ACT_MDL_CUT, "cut.png", SLOT(cut()), QKeySequence::Cut); + addAct(ACT_MDL_CPY, "copy.png", SLOT(copy()), QKeySequence::Copy); + addAct(ACT_MDL_PST, "paste.png", SLOT(paste()), QKeySequence::Paste); + addAct(ACT_MDL_INS, "list.png", SLOT(insert()), QKeySequence::Italic); + + addAct(ACT_MDL_MOV, "arrow-right.png"); + QMenu * catsMenu = new QMenu(this); + action[ACT_MDL_MOV]->setMenu(catsMenu); + + // set up the toolbars + + QToolButton * btn; + QSize tbIcnSz(16, 16); + QString tbCss = "QToolBar {border: 1px solid palette(midlight);}"; + + if (categoriesToolbar) + categoriesToolbar->deleteLater(); + categoriesToolbar = new QToolBar(this); + categoriesToolbar->setObjectName("TB_CATEGORIES"); + categoriesToolbar->setToolButtonStyle(Qt::ToolButtonTextBesideIcon); + categoriesToolbar->setFloatable(false); + categoriesToolbar->setIconSize(tbIcnSz); + categoriesToolbar->setStyleSheet(tbCss); + categoriesToolbar->addAction(getAction(ACT_CAT_ADD)); + ui->topToolbarLayout->addWidget(categoriesToolbar); + + if (radioToolbar) + radioToolbar->deleteLater(); + radioToolbar = new QToolBar(this); + radioToolbar->setObjectName("TB_GENERAL"); + radioToolbar->setFloatable(false); + radioToolbar->setIconSize(tbIcnSz); + radioToolbar->setStyleSheet(tbCss); + radioToolbar->setSizePolicy(QSizePolicy::Expanding, QSizePolicy::Fixed); + radioToolbar->addActions(getGeneralActions()); + if ((btn = qobject_cast(radioToolbar->widgetForAction(action[ACT_GEN_EDT])))) { + btn->setToolButtonStyle(Qt::ToolButtonTextBesideIcon); + } + if ((btn = qobject_cast(radioToolbar->widgetForAction(action[ACT_GEN_SIM])))) { + btn->setToolButtonStyle(Qt::ToolButtonTextBesideIcon); + } + // add spacer to right-align the buttons + QWidget * sp = new QWidget(this); + sp->setSizePolicy(QSizePolicy::Expanding, QSizePolicy::Fixed); + radioToolbar->insertWidget(radioToolbar->actions().first(), sp); + ui->topToolbarLayout->addWidget(radioToolbar); + + if (modelsToolbar) + modelsToolbar->deleteLater(); + modelsToolbar = new QToolBar(this); + modelsToolbar->setObjectName("TB_MODELS"); + modelsToolbar->setFloatable(false); + modelsToolbar->setIconSize(tbIcnSz); + modelsToolbar->setStyleSheet(tbCss); + modelsToolbar->addActions(getEditActions(false)); + modelsToolbar->addSeparator(); + modelsToolbar->addActions(getModelActions()); + if ((btn = qobject_cast(modelsToolbar->widgetForAction(action[ACT_MDL_ADD])))) { + btn->setToolButtonStyle(Qt::ToolButtonTextBesideIcon); + } + if ((btn = qobject_cast(modelsToolbar->widgetForAction(action[ACT_MDL_MOV])))) { + btn->setPopupMode(QToolButton::InstantPopup); + } + ui->botToolbarLayout->addWidget(modelsToolbar); + + connect(categoriesToolbar, &QToolBar::visibilityChanged, this, &MdiChild::adjustToolbarLayout); + connect(radioToolbar, &QToolBar::visibilityChanged, this, &MdiChild::adjustToolbarLayout); + connect(modelsToolbar, &QToolBar::visibilityChanged, this, &MdiChild::adjustToolbarLayout); } -void MdiChild::showModelsListContextMenu(const QPoint & pos) +void MdiChild::updateNavigation() { - QModelIndex modelIndex = ui->modelsList->indexAt(pos); - QPoint globalPos = ui->modelsList->mapToGlobal(pos); - QMenu contextMenu; - const QClipboard * clipboard = QApplication::clipboard(); - const QMimeData * mimeData = clipboard->mimeData(); - bool hasData = mimeData->hasFormat("application/x-companion"); - if (modelsListModel->getModelIndex(modelIndex) >= 0) { - contextMenu.addAction(CompanionIcon("edit.png"), tr("&Edit"), this, SLOT(modelEdit())); - contextMenu.addAction(CompanionIcon("open.png"), tr("&Restore from backup"), this, SLOT(loadBackup())); - contextMenu.addAction(CompanionIcon("wizard.png"), tr("&Model Wizard"), this, SLOT(wizardEdit())); - contextMenu.addSeparator(); - contextMenu.addAction(CompanionIcon("clear.png"), tr("&Delete"), this, SLOT(confirmDelete()), tr("Delete")); - contextMenu.addAction(CompanionIcon("copy.png"), tr("&Copy"), this, SLOT(copy()), tr("Ctrl+C")); - contextMenu.addAction(CompanionIcon("cut.png"), tr("&Cut"), this, SLOT(cut()), tr("Ctrl+X")); - contextMenu.addAction(CompanionIcon("paste.png"), tr("&Paste"), this, SLOT(paste()), tr("Ctrl+V"))->setEnabled(hasData); - contextMenu.addAction(CompanionIcon("duplicate.png"), tr("D&uplicate"), this, SLOT(modelDuplicate()), tr("Ctrl+U")); - if (radioData.categories.size() > 1) { - QMenu * catsMenu = contextMenu.addMenu(CompanionIcon("arrow-right.png"), tr("Move to Category")); + const int modelsSelected = countSelectedModels(); + const int catsSelected = countSelectedCats(); + const bool singleModelSelected = (modelsSelected == 1); + const bool hasModelSlotSelcted = (getCurrentModel() > -1); + const bool hasCats = firmware->getCapability(Capability::HasModelCategories); + const bool hasCatSelected = hasCats && modelsListModel->isCategoryType(getCurrentIndex()); + const int numOnClipbrd = modelsListModel->countModelsInMimeData(QApplication::clipboard()->mimeData()); + const QString modelsRemvTxt = tr("%n Model(s)", "As in \"Copy 3 Models\" or \"Cut 1 Model\" or \"Delete 3 Models\" action).", modelsSelected); + const QString modelsAddTxt = tr("%n Model(s)", "As in \"Paste 3 Models\" or \"Insert 1 Model.\"", numOnClipbrd); + const QString catsRemvTxt = tr("%n Category(ies)", "As in \"Delete 3 Categories\" or \"Delete 1 Category.\"", catsSelected); + static const QString noSelection = tr("Nothing selected"); + static const QString sp = " "; + static const QString ns; + + categoriesToolbar->setVisible(hasCats && showCatToolbar); + + action[ACT_GEN_PST]->setEnabled(hasClipboardData(1)); + + action[ACT_ITM_EDT]->setEnabled(singleModelSelected || catsSelected == 1); + action[ACT_ITM_EDT]->setText((hasCatSelected ? tr("Rename Category") : modelsSelected ? tr("Edit Model") : noSelection)); + action[ACT_ITM_DEL]->setEnabled(modelsSelected || catsSelected); + action[ACT_ITM_DEL]->setText((action[ACT_ITM_DEL]->isEnabled() ? tr("Delete") % " " % (hasCatSelected ? catsRemvTxt : modelsRemvTxt) : noSelection)); + + action[ACT_CAT_ADD]->setVisible(hasCats); + action[ACT_CAT_SEP]->setVisible(hasCats); +// action[ACT_CAT_EDT]->setVisible(hasCats); +// action[ACT_CAT_EDT]->setEnabled(catsSelected == 1); +// action[ACT_CAT_DEL]->setVisible(hasCats); +// action[ACT_CAT_DEL]->setEnabled(catsSelected); +// action[ACT_CAT_DEL]->setText((hasCatSelected ? tr("Delete") % " " % catsRemTxt : noSelection)); + + action[ACT_MDL_CUT]->setEnabled(modelsSelected); + action[ACT_MDL_CUT]->setText(tr("Cut") % (modelsSelected ? sp % modelsRemvTxt : ns)); + action[ACT_MDL_CPY]->setEnabled(modelsSelected); + action[ACT_MDL_CPY]->setText(tr("Copy") % (modelsSelected ? sp % modelsRemvTxt : ns)); + action[ACT_MDL_PST]->setEnabled(numOnClipbrd); + action[ACT_MDL_PST]->setText(tr("Paste") % (numOnClipbrd ? sp % modelsAddTxt : ns)); + action[ACT_MDL_INS]->setEnabled(numOnClipbrd && (hasModelSlotSelcted || catsSelected)); + action[ACT_MDL_INS]->setText(tr("Insert") % QString(action[ACT_MDL_INS]->isEnabled() ? sp % modelsAddTxt : ns)); + + if (hasCats && action[ACT_MDL_MOV]->menu()) { + action[ACT_MDL_MOV]->setVisible(true); + QModelIndex modelIndex = getCurrentIndex(); + QMenu * catsMenu = action[ACT_MDL_MOV]->menu(); + catsMenu->clear(); + if (modelsSelected && modelsListModel && radioData.categories.size() > 1) { + action[ACT_MDL_MOV]->setEnabled(true); for (unsigned i=0; i < radioData.categories.size(); ++i) { QAction * act = catsMenu->addAction(QString(radioData.categories[i].name), this, SLOT(onModelMoveToCategory())); act->setProperty("categoryId", i); @@ -157,68 +350,185 @@ void MdiChild::showModelsListContextMenu(const QPoint & pos) act->setEnabled(false); } } - contextMenu.addSeparator(); - contextMenu.addAction(CompanionIcon("currentmodel.png"), tr("&Use as default"), this, SLOT(setDefault())); - contextMenu.addSeparator(); - contextMenu.addAction(CompanionIcon("print.png"), tr("P&rint model"), this, SLOT(print()), QKeySequence(tr("Ctrl+P"))); - contextMenu.addSeparator(); - contextMenu.addAction(CompanionIcon("simulate.png"), tr("&Simulate model"), this, SLOT(modelSimulate()), tr("Alt+S")); - } - else if (IS_HORUS(firmware->getBoard())) { - if (modelsListModel->getCategoryIndex(modelIndex) >= 0) { - contextMenu.addAction(CompanionIcon("add.png"), tr("&Add model"), this, SLOT(modelAdd())); - contextMenu.addAction(CompanionIcon("paste.png"), tr("&Paste"), this, SLOT(paste()), tr("Ctrl+V"))->setEnabled(hasData); - contextMenu.addSeparator(); - contextMenu.addAction(CompanionIcon("rename.png"), tr("&Rename category"), this, SLOT(categoryRename())); - contextMenu.addAction(CompanionIcon("delete.png"), tr("&Delete category"), this, SLOT(categoryDelete())); - } else { - contextMenu.addAction(CompanionIcon("add.png"), tr("&Add category"), this, SLOT(categoryAdd())); + action[ACT_MDL_MOV]->setDisabled(true); } } else { - return; + action[ACT_MDL_MOV]->setVisible(false); } - contextMenu.exec(globalPos); + action[ACT_MDL_DUP]->setEnabled(singleModelSelected); + action[ACT_MDL_RTR]->setEnabled(singleModelSelected); + action[ACT_MDL_WIZ]->setEnabled(singleModelSelected); + action[ACT_MDL_DFT]->setEnabled(singleModelSelected && getCurrentModel() != (int)radioData.generalSettings.currModelIndex); + action[ACT_MDL_PRT]->setEnabled(singleModelSelected); + action[ACT_MDL_SIM]->setEnabled(singleModelSelected); } -void MdiChild::forceNewFilename(const QString & suffix, const QString & ext) +void MdiChild::retranslateUi() { - QFileInfo info(curFile); - curFile = info.path() + "/" + info.baseName() + suffix + ext; + action[ACT_GEN_EDT]->setText(tr("Edit Radio Settings")); + action[ACT_GEN_CPY]->setText(tr("Copy Radio Settings")); + action[ACT_GEN_PST]->setText(tr("Paste Radio Settings")); + action[ACT_GEN_SIM]->setText(tr("Simulate Radio")); + + action[ACT_CAT_ADD]->setText(tr("Add Category")); + action[ACT_CAT_ADD]->setIconText(tr("Category")); + //action[ACT_CAT_EDT]->setText(tr("Rename Category")); + + action[ACT_MDL_ADD]->setText(tr("Add Model")); + action[ACT_MDL_ADD]->setIconText(tr("Model")); + action[ACT_MDL_RTR]->setText(tr("Restore from Backup")); + action[ACT_MDL_WIZ]->setText(tr("Model Wizard")); + action[ACT_MDL_DFT]->setText(tr("Set as Default")); + action[ACT_MDL_PRT]->setText(tr("Print Model")); + action[ACT_MDL_SIM]->setText(tr("Simulate Model")); + action[ACT_MDL_DUP]->setText(tr("Duplicate Model")); + + action[ACT_MDL_MOV]->setText(tr("Move to Category")); + + categoriesToolbar->setWindowTitle(tr("Show Category Actions Toolbar")); + radioToolbar->setWindowTitle(tr("Show Radio Actions Toolbar")); + modelsToolbar->setWindowTitle(tr("Show Model Actions Toolbar")); } -void MdiChild::onFirmwareChanged() +QList MdiChild::getGeneralActions() { - Firmware * previous = firmware; - firmware = getCurrentFirmware(); - qDebug() << "onFirmwareChanged" << previous->getName() << "=>" << firmware->getName(); - if (previous->getBoard() != firmware->getBoard()) { - convertStorage(previous->getBoard(), firmware->getBoard()); + QList actGrp; + actGrp.append(getAction(ACT_GEN_SIM)); + actGrp.append(getAction(ACT_GEN_EDT)); + actGrp.append(getAction(ACT_GEN_CPY)); + actGrp.append(getAction(ACT_GEN_PST)); + return actGrp; +} + +QList MdiChild::getEditActions(bool incCatNew) +{ + QList actGrp; + if (incCatNew) { + actGrp.append(getAction(ACT_CAT_ADD)); + actGrp.append(getAction(ACT_CAT_SEP)); + } + actGrp.append(action[ACT_MDL_ADD]); + QAction * sep2 = new QAction(this); + sep2->setSeparator(true); + actGrp.append(sep2); + actGrp.append(getAction(ACT_ITM_EDT)); + actGrp.append(getAction(ACT_ITM_DEL)); + actGrp.append(getAction(ACT_MDL_CUT)); + actGrp.append(getAction(ACT_MDL_CPY)); + actGrp.append(getAction(ACT_MDL_PST)); + actGrp.append(getAction(ACT_MDL_INS)); + actGrp.append(getAction(ACT_MDL_DUP)); + actGrp.append(getAction(ACT_MDL_MOV)); + return actGrp; +} + +QList MdiChild::getModelActions() +{ + QList actGrp; + actGrp.append(getAction(ACT_MDL_RTR)); + actGrp.append(getAction(ACT_MDL_WIZ)); + actGrp.append(getAction(ACT_MDL_DFT)); + actGrp.append(getAction(ACT_MDL_PRT)); + actGrp.append(getAction(ACT_MDL_SIM)); + return actGrp; +} + +//QList MdiChild::getCategoryActions() +//{ +// QList actGrp; +// actGrp.append(getAction(ACT_CAT_ADD)); +// actGrp.append(getAction(ACT_CAT_EDT)); +// actGrp.append(getAction(ACT_CAT_DEL)); +// actGrp.append(getAction(ACT_CAT_SEP)); +// return actGrp; +//} + +QAction * MdiChild::getAction(const MdiChild::Actions type) +{ + if (type < ACT_ENUM_END) + return action[type]; + else + return NULL; +} + +void MdiChild::showModelsListContextMenu(const QPoint & pos) +{ + QModelIndex modelIndex = ui->modelsList->indexAt(pos); + QMenu contextMenu; + + updateNavigation(); + + if (firmware->getCapability(Capability::HasModelCategories)) { + contextMenu.addAction(action[ACT_CAT_ADD]); + if(modelsListModel->isCategoryType(modelIndex)) { + contextMenu.addAction(action[ACT_ITM_EDT]); + contextMenu.addAction(action[ACT_ITM_DEL]); + } + contextMenu.addSeparator(); + } + + if (modelsListModel->isModelType(modelIndex)) { + contextMenu.addActions(getEditActions()); + if (countSelectedModels() == 1) { + contextMenu.addSeparator(); + contextMenu.addActions(getModelActions()); + } + } + else { + contextMenu.addAction(action[ACT_MDL_ADD]); + if (hasClipboardData()) + contextMenu.addAction(action[ACT_MDL_PST]); + } + + if (!contextMenu.isEmpty()) + contextMenu.exec(ui->modelsList->mapToGlobal(pos)); +} + +void MdiChild::showContextMenu(const QPoint & pos) +{ + QMenu contextMenu; + if (firmware->getCapability(Capability::HasModelCategories)) + contextMenu.addAction(categoriesToolbar->toggleViewAction()); + contextMenu.addAction(modelsToolbar->toggleViewAction()); + contextMenu.addAction(radioToolbar->toggleViewAction()); + if (!contextMenu.isEmpty()) + contextMenu.exec(mapToGlobal(pos)); +} + +void MdiChild::adjustToolbarLayout() +{ + if (size().width() > ui->topToolbarLayout->sizeHint().width() + ui->botToolbarLayout->sizeHint().width() + 30) { + ui->botToolbarLayout->removeWidget(modelsToolbar); + ui->topToolbarLayout->insertWidget(1, modelsToolbar); + } + else { + ui->topToolbarLayout->removeWidget(modelsToolbar); + ui->botToolbarLayout->insertWidget(0, modelsToolbar); } } -void MdiChild::convertStorage(Board::Type from, Board::Type to) -{ - QMessageBox::warning(this, "Companion", tr("Models and settings will be automatically converted.\nIf that is not what you intended, please close the file\nand choose the correct radio type/profile before reopening it."), QMessageBox::Ok); - radioData.convert(from, to); - forceNewFilename("_converted", ".otx"); - initModelsList(); - fileChanged = true; - isUntitled = true; - documentWasModified(); -} +/* + * Data model +*/ void MdiChild::initModelsList() { Board::Type board = firmware->getBoard(); - delete modelsListModel; + if (modelsListModel) + delete modelsListModel; + modelsListModel = new TreeModel(&radioData, this); + connect(modelsListModel, &TreeModel::modelsDropped, this, &MdiChild::pasteModelData); + connect(modelsListModel, &TreeModel::modelsRemoved, this, &MdiChild::deleteModels); + connect(modelsListModel, &TreeModel::refreshRequested, this, &MdiChild::refresh); connect(modelsListModel, &QAbstractItemModel::dataChanged, this, &MdiChild::onDataChanged); + ui->modelsList->setModel(modelsListModel); - ui->modelsList->header()->setVisible(!IS_HORUS(board)); + ui->modelsList->header()->setVisible(!firmware->getCapability(Capability::HasModelCategories)); if (IS_HORUS(board)) { ui->modelsList->setIndentation(20); // ui->modelsList->resetIndentation(); // introduced in next Qt versions ... @@ -229,133 +539,150 @@ void MdiChild::initModelsList() refresh(); } -void MdiChild::cut() +void MdiChild::refresh() { - copy(); - deleteSelectedModels(); -} - -void MdiChild::copy() -{ - QByteArray gmData; - doCopy(&gmData); - - QMimeData * mimeData = new QMimeData; - mimeData->setData("application/x-companion", gmData); - - QClipboard * clipboard = QApplication::clipboard(); - clipboard->setMimeData(mimeData, QClipboard::Clipboard); -} - -void MdiChild::doCopy(QByteArray * gmData) -{ - foreach(QModelIndex index, ui->modelsList->selectionModel()->selectedIndexes()) { - if (index.column() == 0) { - int modelIndex = modelsListModel->getModelIndex(index); - if (modelIndex >= 0) { - gmData->append('M'); - gmData->append((char *) &radioData.models[modelIndex], sizeof(ModelData)); - } - } + bool expand = true; // TODO: restore user-preferred state + clearCutList(); + modelsListModel->refresh(); + if (expand) + ui->modelsList->expandAll(); + if (lastSelectedModel > -1) { + setSelectedModel(lastSelectedModel); + lastSelectedModel = -1; } - -// TODO to copy radio settings -// gmData->append('G'); -// gmData->append((char *) &radioData.generalSettings, sizeof(GeneralSettings)); + updateNavigation(); + updateTitle(); } -void MdiChild::doPaste(QByteArray * gmData, QModelIndex row) +void MdiChild::onItemActivated(const QModelIndex index) { - char * gData = gmData->data(); - bool modified = false; - int size = 0; - int modelIdx = modelsListModel->getModelIndex(row); - int categoryIdx = modelsListModel->getCategoryIndex(row); - int childNumber = modelsListModel->rowNumber(row); - - while (size < gmData->size()) { - char c = *gData++; - size++; - if (c == 'G') { - // General settings - int ret = QMessageBox::question(this, "Companion", tr("Do you want to overwrite radio general settings?"), - QMessageBox::Yes | QMessageBox::No); - if (ret == QMessageBox::Yes) { - radioData.generalSettings = *((GeneralSettings *)gData); - modified = 1; - } - gData += sizeof(GeneralSettings); - size += sizeof(GeneralSettings); - } - else if (c == 'M') { - if (firmware->getCapability(Models) == 0 || modelIdx < firmware->getCapability(Models)) { - // Model data - int ret = QMessageBox::Yes; - - if (modelIdx == -1) { - // This handles pasting onto a category label or pasting past the end - // of a category when pasting multiple models. - ModelData blank; - blank.used = false; - blank.category = categoryIdx; - radioData.models.push_back(blank); - modelIdx = radioData.models.size() - 1; - } - - if (!radioData.models[modelIdx].isEmpty()) { - ret = QMessageBox::question(this, "Companion", tr("You are pasting on an not empty model, are you sure?"), - QMessageBox::Yes | QMessageBox::No); - } - if (ret == QMessageBox::Yes) { - // Set the destination category, so a user can copy/paste across categories. - radioData.models[modelIdx] = *((ModelData *)gData); - radioData.models[modelIdx].category = categoryIdx; - strcpy(radioData.models[modelIdx].filename, radioData.getNextModelFilename().toStdString().c_str()); - modified = 1; - } - gData += sizeof(ModelData); - size += sizeof(ModelData); - // This gets the next row in the UI, which works for category-capable - // and non-category radio profiles. modelIndex will be -1, if there - // is no next row in the current category. - modelIdx = modelsListModel->getModelIndex(row.sibling(++childNumber, 0)); - } - } - else { - qWarning() << "paste error"; - break; - } + if (modelsListModel->isModelType(index)) { + int mIdx = modelsListModel->getModelIndex(index); + if (mIdx < 0 || mIdx >= (int)radioData.models.size()) + return; + if (radioData.models[mIdx].isEmpty()) + newModel(mIdx); + else + openModelEditWindow(mIdx); } - if (modified) { - setModified(); + else if (modelsListModel->isCategoryType(index)) { + ui->modelsList->edit(index); } } -void MdiChild::paste() +void MdiChild::onItemSelected(const QModelIndex &) { - if (hasPasteData()) { - const QClipboard * clipboard = QApplication::clipboard(); - const QMimeData * mimeData = clipboard->mimeData(); - QByteArray gmData = mimeData->data("application/x-companion"); - doPaste(&gmData, ui->modelsList->currentIndex()); + updateNavigation(); +} + +void MdiChild::onCurrentItemChanged(const QModelIndex &, const QModelIndex &) +{ + updateNavigation(); +} + +void MdiChild::onDataChanged(const QModelIndex & index) +{ + if (!modelsListModel->isCategoryType(index)) + return; + + int categoryIndex = modelsListModel->getCategoryIndex(index); + if (categoryIndex < 0 || categoryIndex >= (int)radioData.categories.size()) { + return; } + strcpy(radioData.categories[categoryIndex].name, modelsListModel->data(index, 0).toString().left(sizeof(CategoryData::name)-1).toStdString().c_str()); + + setModified(); } -bool MdiChild::hasPasteData() const +/* + * Get info from data model +*/ + +QModelIndex MdiChild::getCurrentIndex() const { - const QClipboard * clipboard = QApplication::clipboard(); - const QMimeData * mimeData = clipboard->mimeData(); - return mimeData->hasFormat("application/x-companion"); + return ui->modelsList->selectionModel()->currentIndex(); } -bool MdiChild::hasModelSelected() +int MdiChild::getCurrentCategory() const { - return isModel(ui->modelsList->currentIndex()); + return modelsListModel->getCategoryIndex(getCurrentIndex()); } +int MdiChild::countSelectedCats() const +{ + int ret = 0; + + foreach (QModelIndex index, ui->modelsList->selectionModel()->selectedRows()) { + if (index.isValid() && modelsListModel->isCategoryType(index)) + ++ret; + } + return ret; +} + +bool MdiChild::hasSelectedCat() +{ + return modelsListModel->isCategoryType(getCurrentIndex()); +} + +QVector MdiChild::getSelectedCategories() const +{ + QVector cats; + foreach (QModelIndex index, ui->modelsList->selectionModel()->selectedRows()) { + if (index.isValid() && modelsListModel->isCategoryType(index)) + cats.append(modelsListModel->getCategoryIndex(index)); + } + return cats; +} + +int MdiChild::getCurrentModel() const +{ + return modelsListModel->getModelIndex(getCurrentIndex()); +} + +int MdiChild::countSelectedModels() const +{ + int ret = 0; + + foreach (QModelIndex index, ui->modelsList->selectionModel()->selectedRows()) { + if (index.isValid() && modelsListModel->isModelType(index) && !radioData.models.at(modelsListModel->getModelIndex(index)).isEmpty()) + ++ret; + } + return ret; +} + +bool MdiChild::hasSelectedModel() +{ + return modelsListModel->isModelType(getCurrentIndex()); +} + +bool MdiChild::setSelectedModel(const int modelIndex) +{ + QModelIndex idx = modelsListModel->getIndexForModel(modelIndex); + if (idx.isValid()) { + ui->modelsList->scrollTo(idx); + ui->modelsList->setCurrentIndex(idx); + return true; + } + return false; +} + +QVector MdiChild::getSelectedModels() const +{ + QVector models; + foreach (QModelIndex index, ui->modelsList->selectionModel()->selectedRows()) { + if (index.isValid() && modelsListModel->isModelType(index)) + models.append(modelsListModel->getModelIndex(index)); + } + return models; +} + +/* + * Misc. internal event handlers +*/ + void MdiChild::updateTitle() { - QString title = userFriendlyCurrentFile() + "[*]" + " (" + firmware->getName() + QString(")"); + QString title = "[*]" + userFriendlyCurrentFile(); // + " (" + firmware->getName() + QString(")"); int availableEEpromSize = modelsListModel->getAvailableEEpromSize(); if (availableEEpromSize >= 0) { title += QString(" - %1 ").arg(availableEEpromSize) + tr("free bytes"); @@ -365,43 +692,374 @@ void MdiChild::updateTitle() void MdiChild::setModified() { - refresh(); fileChanged = true; - documentWasModified(); + refresh(); + setWindowModified(true); + emit modified(); } -void MdiChild::keyPressEvent(QKeyEvent * event) +void MdiChild::onFirmwareChanged() { - if (event->matches(QKeySequence::Delete)) { - deleteSelectedModels(); - } - else if (event->matches(QKeySequence::Cut)) { - cut(); - } - else if (event->matches(QKeySequence::Copy)) { - copy(); - } - else if (event->matches(QKeySequence::Paste)) { - paste(); - } - else if (event->matches(QKeySequence::Underline)) { - // TODO duplicate(); - } - else { - QWidget::keyPressEvent(event); // run the standard event in case we didn't catch an action + Firmware * previous = firmware; + firmware = getCurrentFirmware(); + //qDebug() << "onFirmwareChanged" << previous->getName() << "=>" << firmware->getName(); + if (previous->getBoard() != firmware->getBoard()) { + convertStorage(previous->getBoard(), firmware->getBoard()); + setModified(); } } -void MdiChild::on_simulateButton_clicked() +/* + * Categories CRUD +*/ + +void MdiChild::categoryAdd() { - radioSimulate(); + /*: Translators do NOT use accent for this, this is the default category name on Horus. */ + CategoryData category(qPrintable(tr("New category"))); + radioData.categories.push_back(category); + setModified(); + QModelIndex idx = modelsListModel->getIndexForCategory(radioData.categories.size()-1); + if (idx.isValid()) { + ui->modelsList->scrollTo(idx); + ui->modelsList->setCurrentIndex(idx); + ui->modelsList->edit(idx); + } } +// NOTE: this does not refresh the data/view, need to call setModified() at some point afterwards. +bool MdiChild::deleteCategory(int categoryIndex, QString * error) +{ + if (categoryIndex < 0) + categoryIndex = modelsListModel->getCategoryIndex(getCurrentIndex()); + if (categoryIndex < 0 || categoryIndex >= (int)radioData.categories.size()) { + if (error) + *error = tr("Category index out of range."); + return false; + } + if (radioData.categories.size() <= 1) { + if (error) + *error = tr("Cannot delete the last category."); + return false; + } + + QVector modelsToMove; + for (unsigned i=0; i < radioData.models.size(); i++) { + ModelData & model = radioData.models[i]; + if (model.used && model.category == categoryIndex) { + if (error) + *error = tr("This category is not empty!"); + return false; + } + else if (model.used && model.category > categoryIndex) { + modelsToMove.append(i); + } + } + + radioData.categories.erase(radioData.categories.begin() + categoryIndex); + foreach (const int i, modelsToMove) { + --radioData.models[i].category; + } + return true; +} + +void MdiChild::deleteSelectedCats() +{ + bool modified = false; + QString error; + QVector cats = getSelectedCategories(); + std::sort(cats.begin(), cats.end()); + std::reverse(cats.begin(), cats.end()); + foreach (const int cat, cats) { + error.clear(); + if (deleteCategory(cat, &error)) + modified = true; + else + showWarning(error); + } + if (modified) + setModified(); +} + +/* + * Models CRUD +*/ + void MdiChild::checkAndInitModel(int row) { - ModelData & model = radioData.models[row]; - if (model.isEmpty()) { - model.setDefaultValues(row, radioData.generalSettings); + if (row < (int)radioData.models.size() && radioData.models[row].isEmpty()) { + radioData.models[row].setDefaultValues(row, radioData.generalSettings); + setModified(); + } +} + +void MdiChild::findNewDefaultModel(const unsigned startAt) +{ + for (unsigned i = startAt; i < radioData.models.size(); ++i) { + if (!radioData.models[i].isEmpty()) { + radioData.setCurrentModel(i); + return; + } + } + if (startAt > 0) + findNewDefaultModel(0); // restart search from beginning + else + radioData.setCurrentModel(0); +} + +// NOTE: insertModelRows() does not update the TreeModel, only modifies radioData.models[] array by inserting row(s) of blank model(s). +// TreeModel::refresh() needs to be called at some point afterwards to sync the data. +// This invalidates any model indices stored previously. +bool MdiChild::insertModelRows(int atModelIdx, int count) +{ + const unsigned maxModels = firmware->getCapability(Models); + if (atModelIdx < 0) + return false; + + for (int i=0; i < count; ++i) { + //qDebug() << atRow << atRow.row() + i << modelIdx + i << maxModels << radioData.models.size(); + if (maxModels > 0 && radioData.models.size() >= maxModels) { + // trim the array, unless the last model slot is being used. + if (radioData.models[maxModels-1].isEmpty()) { + radioData.models.pop_back(); + } + else { + showWarning(tr("Cannot insert model, last model in list would be deleted.")); + return false; // TODO: perhaps something more elegant... + } + } + // add a placeholder model + radioData.models.insert(radioData.models.begin() + atModelIdx + i, ModelData()); + // adjust current model index if needed + if ((int)radioData.generalSettings.currModelIndex >= atModelIdx + i) + findNewDefaultModel(radioData.generalSettings.currModelIndex + 1); + } + return true; +} + +// Finds the first empty slot and inserts the model into it. In case of category-style models, will append to end of list. +// Return -1 if no slot was found, otherwise new array index. +// TreeModel::refresh() needs to be called at some point afterwards to sync the data. +int MdiChild::modelAppend(const ModelData model) +{ + int newIdx = -1; + int trySlot = 0; + // try to find the next empty slot + for ( ; trySlot < (int)radioData.models.size(); ++trySlot) { + if (radioData.models[trySlot].isEmpty()) { + newIdx = trySlot; + radioData.models[newIdx] = model; + break; + } + } + // if no empty slots then check if we can append it + if (newIdx < 0 && (firmware->getCapability(Models) == 0 || trySlot < firmware->getCapability(Models) - 1)) { + radioData.models.push_back(model); + newIdx = radioData.models.size() - 1; + } + return newIdx; +} + +int MdiChild::newModel(int modelIndex, int categoryIndex) +{ + if (modelIndex < 0) + modelIndex = modelAppend(ModelData()); + + if (modelIndex < 0) { + showWarning(tr("Cannot add model, could not find an available model slot.")); + return modelIndex; + } + + if (categoryIndex < 0) + categoryIndex = modelsListModel->getCategoryIndex(getCurrentIndex()); + //qDebug() << modelIndex << categoryIndex; + + bool isNewModel = radioData.models[modelIndex].isEmpty(); + checkAndInitModel(modelIndex); + if (isNewModel && firmware->getCapability(Capability::HasModelCategories) && categoryIndex > -1) { + radioData.models[modelIndex].category = categoryIndex; + strcpy(radioData.models[modelIndex].filename, radioData.getNextModelFilename().toStdString().c_str()); + strcpy(radioData.models[modelIndex].name, qPrintable(tr("New model"))); // TODO: Why not just use existing default model name? + } + // Only set the default model if we just added the first one. + if (modelIndex == 0) { + radioData.setCurrentModel(modelIndex); + } + setModified(); + setSelectedModel(modelIndex); + + if (g.newModelAction() == 1) + openModelWizard(modelIndex); + else if (g.newModelAction() == 2) + openModelEditWindow(modelIndex); + + return modelIndex; +} + + +// NOTE: deleteModelss() does not update the TreeModel, only modifies radioData.models[] array by clearing the model data. +// If (removeModelSlotsWhenDeleting == true) then removes array rows entirely (and pads w/blank model at the end if needed). +// TreeModel::refresh() needs to be called at some point afterwards to sync the data +// We delete using stored indexes because actual indexes may change during inserts/deletes. +// Obviously this only works before the stored indexes get updated in TreeModel::refresh(). +unsigned MdiChild::deleteModels(const QVector modelIndices) +{ + unsigned deletes = 0; + int idx; + + for (int i = (int)radioData.models.size() - 1; i > -1; --i) { + idx = radioData.models.at(i).modelIndex; + if (idx > -1 && modelIndices.contains(idx)) { + radioData.models[i].clear(); + if (g.removeModelSlots() || firmware->getCapability(Models) == 0) { + radioData.models.erase(radioData.models.begin() + i); + // append padding rows at the end if needed + if (firmware->getCapability(Models) > 0) + insertModelRows(radioData.models.size(), 1); + } + ++deletes; + // adjust current model index if needed + if ((int)radioData.generalSettings.currModelIndex >= idx) + findNewDefaultModel(qMax((int)radioData.generalSettings.currModelIndex - 1, 0)); + + } + //qDebug() << "i:" << i << "modelIndex:" << idx << "deletes:" << deletes; + } + + if (deletes) + setModified(); + + return deletes; +} + +bool MdiChild::deleteModel(const int modelIndex) +{ + QVector list = QVector() << modelIndex; + if (deleteModels(list) == 1) + return true; + else + return false; +} + +void MdiChild::deleteSelectedModels() +{ + deleteModels(getSelectedModels()); +} + +void MdiChild::moveModelsToCategory(const QVector models, const int toCategoryId) +{ + if (toCategoryId < 0 || !models.size()) + return; + + bool modified = false; + //QVector models = getSelectedModels(); + foreach(const int model, models) { + if (model < 0 || model >= (int)radioData.models.size()) + continue; + + if (radioData.models[model].category != toCategoryId) { + radioData.models[model].category = toCategoryId; + modified = true; + } + } + if (modified) + setModified(); +} + +void MdiChild::moveSelectedModelsToCat(const int toCategoryId) +{ + moveModelsToCategory(getSelectedModels(), toCategoryId); +} + +void MdiChild::pasteModelData(const QMimeData * mimeData, const QModelIndex row, bool insert, bool move) +{ + QVector modelsList; + if (!TreeModel::decodeMimeData(mimeData, &modelsList)) + return; + + bool modified = false; + int modelIdx = modelsListModel->getModelIndex(row); + int categoryIdx = modelsListModel->getCategoryIndex(row); + unsigned inserts = 0; + QVector deletesList; + + // Force DnD moves from other file windows to be copy actions because we don't want to delete our models. + bool hasOwnData = modelsListModel->hasOwnMimeData(mimeData); + move = (move && hasOwnData); + + //qDebug().nospace() << "row: " << row << "; ins: " << insert << "; mv: " << move << "; row modelIdx: " << modelIdx << "; row categoryIdx: " << categoryIdx << "; removeSlots: " << removeModelSlotsWhenDeleting; + + // Model data + for (int i=0; i < modelsList.size(); ++i) { + int origMdlIdx = hasOwnData ? modelsList.at(i).modelIndex : -1; // where is the modeul in *our* current array? + bool doMove = (origMdlIdx > -1 && origMdlIdx < (int)radioData.models.size() && (move || cutModels.contains(origMdlIdx))); // DnD-moved or clipboard cut + bool ok = true; + + if (modelIdx == -1 || (!insert && modelIdx >= (int)radioData.models.size())) { + // This handles pasting onto a category label or pasting past the end + // of a category when pasting multiple models. + modelIdx = modelAppend(modelsList[i]); + if (modelIdx < 0) { + ok = false; + showWarning(tr("Cannot paste model, out of available model slots.")); + } + } + else if (insert) { + ok = insertModelRows(modelIdx, 1); + if (ok) { + radioData.models[modelIdx] = modelsList[i]; + ++inserts; + } + } + else { // pasting on top of a slot + if (!radioData.models[modelIdx].isEmpty() && !deletesList.contains(modelIdx)) + ok = askQuestion(tr("You are replacing an existing model, are you sure?")) == QMessageBox::Yes; + if (ok) + radioData.models[modelIdx] = modelsList[i]; + } + + if (ok) { + // We don't want to create an index value conflict so use an invalid one (it will get updated after we're done here) + // this is esp. important because otherwise we may delete this model during a move operation (eg. after a cut) + radioData.models[modelIdx].modelIndex = -modelIdx; + // Set the destination category, so a user can copy/paste across categories. + if (categoryIdx > -1) + radioData.models[modelIdx].category = categoryIdx; + strcpy(radioData.models[modelIdx].filename, radioData.getNextModelFilename().toStdString().c_str()); + lastSelectedModel = modelIdx; // after refresh the last pasted model will be selected + modified = true; + if (doMove) { + deletesList.append(origMdlIdx); + removeModelFromCutList(origMdlIdx); + } + } + //qDebug().nospace() << "i: " << i << "; modelIdx:" << modelIdx << "; origMdlIdx: " << origMdlIdx << "; doMove: " << doMove << "; inserts:" << inserts << "; deletes: " << deletesList; + + ++modelIdx; + } + + if (deletesList.size()) { + deleteModels(deletesList); + } + if (modified) { + setModified(); + } +} + +/* + * General settings CRUD +*/ + +void MdiChild::pasteGeneralData(const QMimeData * mimeData) +{ + GeneralSettings gs; + bool hasGenSettings = false; + + if (!TreeModel::decodeMimeData(mimeData, NULL, &gs, &hasGenSettings)) + return; + + if (hasGenSettings && askQuestion(tr("Do you want to overwrite radio general settings?")) == QMessageBox::Yes) { + radioData.generalSettings = gs; setModified(); } } @@ -413,97 +1071,173 @@ void MdiChild::generalEdit() t->show(); } -void MdiChild::categoryAdd() +void MdiChild::copyGeneralSettings() { - /*: Translators do NOT use accent for this, this is the default category name on Horus. */ - CategoryData category(qPrintable(tr("New category"))); - radioData.categories.push_back(category); - setModified(); - emit copyAvailable(false); // workaround : nothing is selected after model creation + QMimeData * mimeData = modelsListModel->getGeneralMimeData(); + modelsListModel->getHeaderMimeData(mimeData); + QApplication::clipboard()->setMimeData(mimeData, QClipboard::Clipboard); + updateNavigation(); } -void MdiChild::categoryRename() +void MdiChild::pasteGeneralSettings() { - QModelIndex modelIndex = ui->modelsList->currentIndex(); - int categoryIndex = modelsListModel->getCategoryIndex(modelIndex); - if (categoryIndex < 0 || categoryIndex >= (int)radioData.categories.size()) { - return; + if (hasClipboardData(1)) { + pasteGeneralData(QApplication::clipboard()->mimeData()); } - - // Not calling setModified() here because QAbstractItemView::edit will - // haandle it if the user actually makes a change - ui->modelsList->edit(modelIndex); } -void MdiChild::categoryDelete() -{ - int categoryIndex = modelsListModel->getCategoryIndex(ui->modelsList->currentIndex()); - if (categoryIndex < 0 || categoryIndex >= (int)radioData.categories.size()) { - return; - } +/* + * Action targets +*/ - for (unsigned i=0; igetModelsMimeData(ui->modelsList->selectionModel()->selectedRows()); + modelsListModel->getHeaderMimeData(mimeData); + QApplication::clipboard()->setMimeData(mimeData, QClipboard::Clipboard); + + clearCutList(); // clear the list by default, populate afterwards, eg. in cut(). + updateNavigation(); +} + +void MdiChild::cut() +{ + copy(); + cutModels = getSelectedModels(); + modelsListModel->markItemsForCut(ui->modelsList->selectionModel()->selectedIndexes()); +} + +void MdiChild::removeModelFromCutList(const int modelIndex) +{ + int idx = cutModels.indexOf(modelIndex); + if (idx > -1) { + cutModels.remove(idx); + modelsListModel->markItemForCut(modelsListModel->getIndexForModel(modelIndex), false); + } +} + +void MdiChild::clearCutList() +{ + foreach (const int id, cutModels) { + removeModelFromCutList(id); + } +} + +// type = 0 for models (default), 1 for general radio data +bool MdiChild::hasClipboardData(const quint8 type) const +{ + if (!type) { + return modelsListModel->hasModelsMimeData(QApplication::clipboard()->mimeData()); + } + else { + return modelsListModel->hasGenralMimeData(QApplication::clipboard()->mimeData()); + } +} + +void MdiChild::paste() +{ + if (hasClipboardData()) { + pasteModelData(QApplication::clipboard()->mimeData(), getCurrentIndex()); + } +} + +void MdiChild::insert() +{ + if (hasClipboardData()) { + pasteModelData(QApplication::clipboard()->mimeData(), getCurrentIndex(), true); + } +} + +void MdiChild::edit() +{ + onItemActivated(getCurrentIndex()); +} + +void MdiChild::confirmDelete() +{ + if (hasSelectedModel()) { + if (!countSelectedModels() || askQuestion(tr("Delete %n selected model(s)?", 0, countSelectedModels())) == QMessageBox::Yes) { + deleteSelectedModels(); } } - - radioData.categories.erase(radioData.categories.begin() + categoryIndex); - for (unsigned i=0; i categoryIndex) { - model.category--; + else if (hasSelectedCat()) { + if (askQuestion(tr("Delete %n selected category(ies)?", 0, countSelectedCats())) == QMessageBox::Yes) { + deleteSelectedCats(); } } - - setModified(); -} - -void MdiChild::onDataChanged(const QModelIndex & index) -{ - int modelIndex = modelsListModel->getModelIndex(index); - if (modelIndex >= 0) { - return; - } - int categoryIndex = modelsListModel->getCategoryIndex(index); - if (categoryIndex < 0 || categoryIndex >= (int)radioData.categories.size()) { - return; - } - strcpy(radioData.categories[categoryIndex].name, modelsListModel->data(index, 0).toString().left(sizeof(CategoryData::name)-1).toStdString().c_str()); - fileChanged = true; - documentWasModified(); } void MdiChild::modelAdd() { - int categoryIndex = modelsListModel->getCategoryIndex(ui->modelsList->currentIndex()); - if (categoryIndex < 0 || categoryIndex >= (int)radioData.categories.size()) { + int modelIdx = -1; + // add to currently selected empty slot? + if (modelsListModel->isModelType(getCurrentIndex())) { + int mIdx = modelsListModel->getModelIndex(getCurrentIndex()); + if (mIdx > -1 && mIdx < (int)radioData.models.size() && radioData.models[mIdx].isEmpty()) { + modelIdx = mIdx; + } + } + newModel(modelIdx); +} + +void MdiChild::modelDuplicate() +{ + int srcModelIndex = getCurrentModel(); + if (srcModelIndex < 0) { return; } - ModelData model; - radioData.models.push_back(model); - int row = radioData.models.size() - 1; - checkAndInitModel(row); - radioData.models[row].category = categoryIndex; - strcpy(radioData.models[row].filename, radioData.getNextModelFilename().toStdString().c_str()); - strcpy(radioData.models[row].name, qPrintable(tr("New model"))); + int newIdx = modelAppend(ModelData(radioData.models[srcModelIndex])); + if (newIdx > -1) { + newModel(newIdx); + } + else { + showWarning(tr("Cannot duplicate model, could not find an available model slot.")); + } +} - // Only set the default model if we just added the first one. - if (row == 0) { - radioData.setCurrentModel(row); +void MdiChild::onModelMoveToCategory() +{ + if (!sender()) { + return; + } + bool ok = false; + int toCatId = sender()->property("categoryId").toInt(&ok); + if (ok && toCatId >= 0) { + moveSelectedModelsToCat(toCatId); } - setModified(); - emit copyAvailable(false); // workaround : nothing is selected after model creation } void MdiChild::modelEdit() { - int row = getCurrentModel(); + openModelEditWindow(getCurrentModel()); +} + +void MdiChild::wizardEdit() +{ + openModelWizard(getCurrentModel()); +} + +void MdiChild::openModelWizard(int row) +{ + if (row < 0 && (row = getCurrentModel()) < 0) + return; + + WizardDialog * wizard = new WizardDialog(radioData.generalSettings, row+1, radioData.models[row], this); + int res = wizard->exec(); + if (res == QDialog::Accepted && wizard->mix.complete /*TODO rather test the exec() result?*/) { + radioData.models[row] = wizard->mix; + radioData.fixModelFilenames(); + setModified(); + setSelectedModel(row); + } +} + +void MdiChild::openModelEditWindow(int row) +{ + if (row < 0 && (row = getCurrentModel()) < 0) + return; + QApplication::setOverrideCursor(Qt::WaitCursor); checkAndInitModel(row); ModelData & model = radioData.models[row]; @@ -517,42 +1251,24 @@ void MdiChild::modelEdit() t->show(); QApplication::restoreOverrideCursor(); gStopwatch.report("ModelEdit shown"); + } -void MdiChild::modelDuplicate() +void MdiChild::print(int model, const QString & filename) { - int srcModelIndex = getCurrentModel(); - if (srcModelIndex < 0) { - return; + // TODO + PrintDialog * pd = NULL; + + if (model>=0 && !filename.isEmpty()) { + pd = new PrintDialog(this, firmware, radioData.generalSettings, radioData.models[model], filename); + } + else { + pd = new PrintDialog(this, firmware, radioData.generalSettings, radioData.models[getCurrentModel()]); } - ModelData model(radioData.models[srcModelIndex]); - strcpy(model.filename, radioData.getNextModelFilename().toStdString().c_str()); - radioData.models.push_back(model); - setModified(); -} - -void MdiChild::modelChangeCategory(int toCategoryId) -{ - int row = getCurrentModel(); - if (row < 0 || row >= (int)radioData.models.size() || toCategoryId < 0) { - return; - } - if (radioData.models[row].category != toCategoryId) { - radioData.models[row].category = toCategoryId; - setModified(); - } -} - -void MdiChild::onModelMoveToCategory() -{ - if (!sender()) { - return; - } - bool ok = false; - int toCatId = sender()->property("categoryId").toInt(&ok); - if (ok && toCatId >= 0) { - modelChangeCategory(toCatId); + if (pd) { + pd->setAttribute(Qt::WA_DeleteOnClose, true); + pd->show(); } } @@ -561,35 +1277,17 @@ void MdiChild::setDefault() int row = getCurrentModel(); if (!radioData.models[row].isEmpty() && radioData.generalSettings.currModelIndex != (unsigned)row) { radioData.setCurrentModel(row); - setModified(); } } -void MdiChild::wizardEdit() +void MdiChild::radioSimulate() { - int row = getCurrentModel(); - checkAndInitModel(row); - WizardDialog * wizard = new WizardDialog(radioData.generalSettings, row+1, radioData.models[row], this); - wizard->exec(); - if (wizard->mix.complete /*TODO rather test the exec() result?*/) { - radioData.models[row] = wizard->mix; - radioData.fixModelFilenames(); - setModified(); - } + startSimulation(this, radioData, -1); } -void MdiChild::openModelEditWindow() +void MdiChild::modelSimulate() { - int row = getCurrentModel(); - if (row >= 0) { - ModelData & model = radioData.models[row]; - if (model.isEmpty() && g.useWizard()) { - wizardEdit(); - } - else { - modelEdit(); - } - } + startSimulation(this, radioData, getCurrentModel()); } void MdiChild::newFile() @@ -598,6 +1296,10 @@ void MdiChild::newFile() isUntitled = true; curFile = QString("document%1.otx").arg(sequenceNumber++); updateTitle(); + + if (firmware->getCapability(Capability::HasModelCategories)) { + categoryAdd(); + } } bool MdiChild::loadFile(const QString & filename, bool resetCurrentFile) @@ -613,13 +1315,16 @@ bool MdiChild::loadFile(const QString & filename, bool resetCurrentFile) // TODO ShowEepromWarnings(this, tr("Warning"), warning); } - refresh(true); if (resetCurrentFile) { setCurrentFile(filename); } if (!storage.isBoardCompatible(getCurrentBoard())) { convertStorage(storage.getBoard(), getCurrentBoard()); + setModified(); + } + else { + refresh(); } return true; @@ -680,34 +1385,11 @@ bool MdiChild::saveFile(const QString & filename, bool setCurrent) return true; } -QString MdiChild::userFriendlyCurrentFile() const -{ - return QFileInfo(curFile).fileName(); -} - -void MdiChild::closeEvent(QCloseEvent *event) -{ - if (maybeSave()) { - event->accept(); - } - else { - event->ignore(); - } -} - -void MdiChild::documentWasModified() -{ - setWindowModified(fileChanged); -} - bool MdiChild::maybeSave() { if (fileChanged) { - QMessageBox::StandardButton ret; - ret = QMessageBox::warning(this, tr("Companion"), - tr("%1 has been modified.\n" - "Do you want to save your changes?").arg(userFriendlyCurrentFile()), - QMessageBox::Save | QMessageBox::Discard | QMessageBox::Cancel); + int ret = askQuestion(tr("%1 has been modified.\nDo you want to save your changes?").arg(userFriendlyCurrentFile()), + QMessageBox::Save, QMessageBox::Discard, QMessageBox::Cancel | QMessageBox::Default); if (ret == QMessageBox::Save) return save(); @@ -717,6 +1399,16 @@ bool MdiChild::maybeSave() return true; } +QString MdiChild::currentFile() const +{ + return curFile; +} + +QString MdiChild::userFriendlyCurrentFile() const +{ + return QFileInfo(curFile).fileName(); +} + void MdiChild::setCurrentFile(const QString & fileName) { curFile = QFileInfo(fileName).canonicalFilePath(); @@ -733,6 +1425,34 @@ void MdiChild::setCurrentFile(const QString & fileName) g.recentFiles(files); } +void MdiChild::forceNewFilename(const QString & suffix, const QString & ext) +{ + QFileInfo info(curFile); + curFile = info.path() + "/" + info.baseName() + suffix + ext; +} + + +void MdiChild::convertStorage(Board::Type from, Board::Type to) +{ + showWarning(tr("Models and settings will be automatically converted.\nIf that is not what you intended, please close the file\nand choose the correct radio type/profile before reopening it.")); + radioData.convert(from, to); + forceNewFilename("_converted", ".otx"); + initModelsList(); + fileChanged = true; + isUntitled = true; +} + +void MdiChild::showWarning(const QString & msg) +{ + if (!msg.isEmpty()) + QMessageBox::warning(this, "Companion", msg); +} + +int MdiChild::askQuestion(const QString & msg, int button0, int button1, int button2) +{ + return QMessageBox::question(this, tr("Companion"), msg, button0, button1, button2); +} + void MdiChild::writeEeprom() // write to Tx { Board::Type board = getCurrentBoard(); @@ -745,7 +1465,7 @@ void MdiChild::writeEeprom() // write to Tx return; } if (saveFile(radioPath, false)) { - parent->statusBar()->showMessage(tr("Models and Settings written"), 2000); + emit newStatusMessage(tr("Models and Settings written"), 2000); } else { qDebug() << "MdiChild::writeEeprom(): saveFile error"; @@ -763,49 +1483,6 @@ void MdiChild::writeEeprom() // write to Tx } } -void MdiChild::on_radioSettings_clicked() -{ - generalEdit(); -} - -void MdiChild::radioSimulate() -{ - startSimulation(this, radioData, -1); -} - -void MdiChild::modelSimulate() -{ - startSimulation(this, radioData, getCurrentModel()); -} - -void MdiChild::print(int model, const QString & filename) -{ - // TODO - PrintDialog * pd = NULL; - - if (model>=0 && !filename.isEmpty()) { - pd = new PrintDialog(this, firmware, radioData.generalSettings, radioData.models[model], filename); - } - else { - pd = new PrintDialog(this, firmware, radioData.generalSettings, radioData.models[getCurrentModel()]); - } - - if (pd) { - pd->setAttribute(Qt::WA_DeleteOnClose, true); - pd->show(); - } -} - -int MdiChild::getCurrentModel() const -{ - return modelsListModel->getModelIndex(ui->modelsList->currentIndex()); -} - -int MdiChild::getCurrentCategory() const -{ - return modelsListModel->getCategoryIndex(ui->modelsList->currentIndex()); -} - bool MdiChild::loadBackup() { QString fileName = QFileDialog::getOpenFileName(this, tr("Open backup Models and Settings file"), g.eepromDir(), tr(EEPROM_FILES_FILTER)); diff --git a/companion/src/mdichild.h b/companion/src/mdichild.h index 7ab23c6a2..2aa20ae1f 100644 --- a/companion/src/mdichild.h +++ b/companion/src/mdichild.h @@ -23,9 +23,14 @@ #include "eeprominterface.h" #include "modelslist.h" -#include -class MainWindow; +#include +#include +#include +#include +#include + +class QToolBar; namespace Ui { class MdiChild; @@ -33,93 +38,198 @@ class MdiChild; class MdiChild : public QWidget { - // friend class ModelsListWidget; - - Q_OBJECT + Q_OBJECT public: - MdiChild(MainWindow * parent); + enum Actions { + ACT_GEN_EDT, // radio general settings + ACT_GEN_CPY, + ACT_GEN_PST, + ACT_GEN_SIM, + ACT_ITM_EDT, // edit model/rename category + ACT_ITM_DEL, // delete model or cat + ACT_CAT_ADD, // category actions... + //ACT_CAT_EDT, // not sure these are needed... + //ACT_CAT_DEL, // the ACT_ITM_* actions do the same thing + ACT_CAT_SEP, // convenience separator shown/hidden with category actions + ACT_MDL_ADD, // model actions... + ACT_MDL_CPY, + ACT_MDL_CUT, + ACT_MDL_PST, + ACT_MDL_DUP, + ACT_MDL_INS, + ACT_MDL_MOV, + ACT_MDL_RTR, // ResToRe backup + ACT_MDL_WIZ, + ACT_MDL_DFT, // set as DeFaulT + ACT_MDL_PRT, // print + ACT_MDL_SIM, + ACT_ENUM_END + }; + + MdiChild(QWidget *parent = Q_NULLPTR, QWidget * parentWin = Q_NULLPTR, Qt::WindowFlags f = Qt::WindowFlags()); ~MdiChild(); + QString currentFile() const; + QString userFriendlyCurrentFile() const; + QVector getSelectedCategories() const; + QVector getSelectedModels() const; + QList getGeneralActions(); + QList getEditActions(bool incCatNew = true); + QList getModelActions(); + //QList getCategoryActions(); + QAction * getAction(const Actions type); + + public slots: void newFile(); bool loadFile(const QString & fileName, bool resetCurrentFile=true); bool save(); bool saveAs(bool isNew=false); bool saveFile(const QString & fileName, bool setCurrent=true); - bool hasModelSelected(); - bool hasPasteData() const; - QString userFriendlyCurrentFile() const; - QString currentFile() const { return curFile; } - int getCurrentModel() const; - int getCurrentCategory() const; - void refresh(bool expand=false); - void keyPressEvent(QKeyEvent * event); - - signals: - void copyAvailable(bool val); - - protected: - void convertStorage(Board::Type from, Board::Type to); - void forceNewFilename(const QString & suffix, const QString & ext); - void closeEvent(QCloseEvent * event); - - protected slots: - void documentWasModified(); - void on_simulateButton_clicked(); - void onModelMoveToCategory(); - void on_radioSettings_clicked(); - void setDefault(); + void writeEeprom(); + void print(int model=-1, const QString & filename=""); void onFirmwareChanged(); - public slots: + signals: + void modified(); + void newStatusMessage(const QString & msg, const int duration); + + protected: + virtual void changeEvent(QEvent * event); + virtual void closeEvent(QCloseEvent * event); + virtual void resizeEvent(QResizeEvent * event); + virtual QSize sizeHint() const; + + private slots: + void setupNavigation(); + void updateNavigation(); + void updateTitle(); + void setModified(); + void retranslateUi(); void showModelsListContextMenu(const QPoint & pos); - void checkAndInitModel(int row); - void generalEdit(); - void categoryAdd(); - void categoryRename(); - void categoryDelete(); - void modelAdd(); - void modelEdit(); - void modelDuplicate(); - void modelChangeCategory(int toCategoryId); - void wizardEdit(); - void openModelEditWindow(); - bool loadBackup(); - void confirmDelete(); - void deleteSelectedModels(); + void showContextMenu(const QPoint & pos); + void adjustToolbarLayout(); + + void initModelsList(); + void refresh(); + void onItemActivated(const QModelIndex index); + void onItemSelected(const QModelIndex &); + void onCurrentItemChanged(const QModelIndex &, const QModelIndex &); void onDataChanged(const QModelIndex & index); - void cut(); + void generalEdit(); + void copyGeneralSettings(); + void pasteGeneralSettings(); + void copy(); + void cut(); void paste(); - void writeEeprom(); + void insert(); + void edit(); + void confirmDelete(); + void categoryAdd(); + void modelAdd(); + void modelEdit(); + void wizardEdit(); + void modelDuplicate(); + void onModelMoveToCategory(); + + void openModelWizard(int row = -1); + void openModelEditWindow(int row = -1); + + void setDefault(); void modelSimulate(); void radioSimulate(); - void print(int model=-1, const QString & filename=""); - void setModified(); - void updateTitle(); - void onItemSelected(QModelIndex); - bool isModel(QModelIndex); - bool isCategory(QModelIndex); + bool loadBackup(); + + void pasteModelData(const QMimeData * mimeData, const QModelIndex row, bool insert = false, bool move = false); + void pasteGeneralData(const QMimeData * mimeData); private: + QAction *addAct(Actions actId, const QString & icon, const char * slot = 0, const QKeySequence & shortcut = 0, QObject * slotObj = NULL); + + QModelIndex getCurrentIndex() const; + int getCurrentModel() const; + int countSelectedModels() const; + bool hasSelectedModel(); + bool setSelectedModel(const int modelIndex); + int getCurrentCategory() const; + int countSelectedCats() const; + bool hasSelectedCat(); + + bool deleteCategory(int categoryIndex = -1, QString * error = NULL); + void deleteSelectedCats(); + + void checkAndInitModel(int row); + void findNewDefaultModel(const unsigned startAt = 0); + bool insertModelRows(int atModelIdx, int count); + int modelAppend(const ModelData model); + int newModel(int modelIndex = -1, int categoryIndex = -1); + unsigned deleteModels(const QVector modelIndices); + bool deleteModel(const int modelIndex); + void deleteSelectedModels(); + void moveModelsToCategory(const QVector models, const int toCategoryId); + void moveSelectedModelsToCat(const int toCategoryId); + + void clearCutList(); + void removeModelFromCutList(const int modelIndex); + bool hasClipboardData(const quint8 type = 0) const; + bool maybeSave(); void setCurrentFile(const QString & fileName); - void doCopy(QByteArray * gmData); - void doPaste(QByteArray * gmData, QModelIndex row); - void initModelsList(); + void forceNewFilename(const QString & suffix, const QString & ext); + void convertStorage(Board::Type from, Board::Type to); + void showWarning(const QString & msg); + int askQuestion(const QString & msg, int button0 = QMessageBox::Yes, int button1 = QMessageBox::No | QMessageBox::Default, int button2 = 0); - MainWindow * parent; Ui::MdiChild * ui; TreeModel * modelsListModel; + QWidget * parentWindow; QString curFile; + QVector cutModels; + QVector action; + QToolBar * radioToolbar; + QToolBar * categoriesToolbar; + QToolBar * modelsToolbar; Firmware * firmware; RadioData radioData; + int lastSelectedModel; bool isUntitled; bool fileChanged; + bool showCatToolbar; + const quint16 stateDataVersion; +}; + +// This will draw the drop indicator across all columns of a model View (vs. in just one column), and lets us make the indicator more obvious. +class ItemViewProxyStyle: public QProxyStyle +{ + public: + ItemViewProxyStyle(QStyle * style = 0) : QProxyStyle(style) {} + + void drawPrimitive(PrimitiveElement element, const QStyleOption * option, QPainter * painter, const QWidget * widget = 0) const + { + if (element == QStyle::PE_IndicatorItemViewItemDrop && !option->rect.isNull()) { + painter->save(); + // set a wider stroke + QPen pen(painter->pen()); + pen.setWidthF(2.5f); + painter->setPen(pen); + // adjust the rectangle size of the indicator to encompass the whole row + QStyleOption opt(*option); + opt.rect.setLeft(0); + if (widget) + opt.rect.setRight(widget->width()); + // call default handler and exit + QProxyStyle::drawPrimitive(element, &opt, painter, widget); + painter->restore(); + } + else { + QProxyStyle::drawPrimitive(element, option, painter, widget); + } + } }; #endif // _MDICHILD_H_ diff --git a/companion/src/mdichild.ui b/companion/src/mdichild.ui index 0b8a6c1b3..d4b48cfa7 100644 --- a/companion/src/mdichild.ui +++ b/companion/src/mdichild.ui @@ -6,35 +6,37 @@ 0 0 - 468 - 414 + 545 + 575 - - - - + + + 5 + - - - Radio settings + + + 2 - + - + + + 2 + + - - - Simulate Tx + + + true - - - + diff --git a/companion/src/modelslist.cpp b/companion/src/modelslist.cpp index 19ffff11a..98ef3dbeb 100644 --- a/companion/src/modelslist.cpp +++ b/companion/src/modelslist.cpp @@ -24,16 +24,17 @@ TreeItem::TreeItem(const QVector & itemData): itemData(itemData), parentItem(NULL), categoryIndex(-1), - modelIndex(-1) + modelIndex(-1), + flags(0) { } TreeItem::TreeItem(TreeItem * parent, int categoryIndex, int modelIndex): - itemData(parent->columnCount()), - parentItem(parent), - categoryIndex(categoryIndex), - modelIndex(modelIndex) + TreeItem(QVector(parent->columnCount())) { + setParent(parent); + setCategoryIndex(categoryIndex); + setModelIndex(modelIndex); } TreeItem::~TreeItem() @@ -69,16 +70,16 @@ QVariant TreeItem::data(int column) const return itemData.value(column); } -TreeItem * TreeItem::appendChild(int categoryIndex, int modelIndex) +TreeItem *TreeItem::insertChild(const int row, int categoryIndex, int modelIndex) { TreeItem * item = new TreeItem(this, categoryIndex, modelIndex); - childItems.insert(childItems.size(), item); + childItems.insert(row, item); return item; } -TreeItem * TreeItem::parent() +TreeItem * TreeItem::appendChild(int categoryIndex, int modelIndex) { - return parentItem; + return insertChild(childItems.size(), categoryIndex, modelIndex); } bool TreeItem::removeChildren(int position, int count) @@ -92,6 +93,14 @@ bool TreeItem::removeChildren(int position, int count) return true; } +bool TreeItem::insertChildren(int row, int count) +{ + for (int i=0; i < count; ++i) { + insertChild(row + i, -1, -1); + } + return true; +} + bool TreeItem::setData(int column, const QVariant & value) { if (column < 0 || column >= itemData.size()) @@ -101,6 +110,29 @@ bool TreeItem::setData(int column, const QVariant & value) return true; } +void TreeItem::setFlag(const quint16 & flag, const bool on) +{ + if (on) + flags |= flag; + else + flags &= ~flag; +} + +bool TreeItem::isCategory() const +{ + return (modelIndex < 0 && categoryIndex > -1); +} + +bool TreeItem::isModel() const +{ + return (modelIndex > -1); +} + + +/* + * TreeModel +*/ + TreeModel::TreeModel(RadioData * radioData, QObject * parent): QAbstractItemModel(parent), radioData(radioData), @@ -108,14 +140,20 @@ TreeModel::TreeModel(RadioData * radioData, QObject * parent): { Board::Type board = getCurrentBoard(); QVector labels; - if (!IS_HORUS(board)) + if (!getCurrentFirmware()->getCapability(Capability::HasModelCategories)) labels << tr("Index"); labels << tr("Name"); if (!(IS_HORUS(board) || IS_SKY9X(board))) { labels << tr("Size"); } rootItem = new TreeItem(labels); + // uniqueId and version for drag/drop operations (see encodeHeaderData()) + mimeHeaderData.instanceId = QUuid::createUuid(); + mimeHeaderData.dataVersion = 1; + refresh(); + //connect(this, &QAbstractItemModel::rowsAboutToBeRemoved, this, &TreeModel::onRowsAboutToBeRemoved); + connect(this, &QAbstractItemModel::rowsRemoved, this, &TreeModel::onRowsRemoved); } TreeModel::~TreeModel() @@ -133,39 +171,38 @@ QVariant TreeModel::data(const QModelIndex & index, int role) const if (!index.isValid()) return QVariant(); - if (role != Qt::DisplayRole && role != Qt::EditRole && role != Qt::FontRole) { - return QVariant(); - } - TreeItem * item = getItem(index); - if (role == Qt::FontRole) { - if (item->getModelIndex() == (int)radioData->generalSettings.currModelIndex) { - QFont font; - font.setBold(true); - return font; - } + if (role == Qt::DisplayRole || role == Qt::EditRole) { + return item->data(index.column()); } - return item->data(index.column()); + + if (role == Qt::FontRole && item->getModelIndex() == (int)radioData->generalSettings.currModelIndex) { + QFont font; + font.setBold(true); + return font; + } + + if (role == Qt::ForegroundRole && (item->getFlags() & TreeItem::MarkedForCut)) { + return QPalette().brush(QPalette::Disabled, QPalette::Text); + } + + return QVariant(); } Qt::ItemFlags TreeModel::flags(const QModelIndex &index) const { - if (!index.isValid()) - return 0; + Qt::ItemFlags f = QAbstractItemModel::flags(index); - return Qt::ItemIsEditable | QAbstractItemModel::flags(index); -} - -TreeItem * TreeModel::getItem(const QModelIndex & index) const -{ if (index.isValid()) { - TreeItem * item = static_cast(index.internalPointer()); - if (item) { - return item; - } + if (getItem(index)->isCategory()) + f |= Qt::ItemIsEditable; + else + f |= Qt::ItemIsDragEnabled; // TODO drag/drop categories } - return rootItem; + f |= Qt::ItemIsDropEnabled; + + return f; } QVariant TreeModel::headerData(int section, Qt::Orientation orientation, int role) const @@ -206,8 +243,10 @@ QModelIndex TreeModel::parent(const QModelIndex & index) const bool TreeModel::removeRows(int position, int rows, const QModelIndex & parent) { TreeItem * parentItem = getItem(parent); - bool success = true; + if (!parentItem) + return false; + bool success = true; if (position >= 0 && rows > 0) { beginRemoveRows(parent, position, position + rows - 1); success = parentItem->removeChildren(position, rows); @@ -217,6 +256,23 @@ bool TreeModel::removeRows(int position, int rows, const QModelIndex & parent) return success; } +/* unused but possibly useful in future +bool TreeModel::insertRows(int row, int count, const QModelIndex & parent) +{ + TreeItem * parentItem = getItem(parent); + if (!parentItem) + return false; + + bool success = true; + if (row >= 0 && count > 0) { + beginInsertRows(parent, row, row + count - 1); + success = parentItem->insertChildren(row, count); + endInsertRows(); + } + + return success; +} */ + int TreeModel::rowCount(const QModelIndex &parent) const { TreeItem * parentItem = getItem(parent); @@ -241,21 +297,361 @@ bool TreeModel::setData(const QModelIndex & index, const QVariant & value, int r return result; } +QStringList TreeModel::mimeTypes() const +{ + QStringList types; + types << "application/x-companion-modeldata"; + types << "application/x-companion-generaldata"; + //type << "application/x-companion-radiodata-header"; // supported but not advertised, must be in conjunction with one of the above + return types; +} + +Qt::DropActions TreeModel::supportedDropActions() const +{ + return Qt::CopyAction | Qt::MoveAction; +} + +Qt::DropActions TreeModel::supportedDragActions() const +{ + return Qt::CopyAction | Qt::MoveAction; +} + +// This method encodes all the data on default drag operation, including general radio settings. This is useful for eg. Compare dialog/model printer. +QMimeData * TreeModel::mimeData(const QModelIndexList & indexes) const +{ + QMimeData * mimeData = new QMimeData(); + getModelsMimeData(indexes, mimeData); + getGeneralMimeData(mimeData); + getHeaderMimeData(mimeData); + return mimeData; +} + +bool TreeModel::canDropMimeData(const QMimeData * data, Qt::DropAction action, int row, int column, const QModelIndex & parent) const +{ + Q_UNUSED(action); + //qDebug() << action << row << column << parent.row(); + + // we do not accept dropped general settings right now (user must copy/paste those) + if (hasHeaderMimeData(data) && hasModelsMimeData(data) && (row > -1 || parent.isValid())) + return true; + + return false; +} + +bool TreeModel::dropMimeData(const QMimeData * data, Qt::DropAction action, int row, int column, const QModelIndex & parent) +{ + if (!canDropMimeData(data, action, row, column, parent)) + return false; + + if (action == Qt::IgnoreAction) + return true; + + QModelIndex idx; + bool isInsert = false; + if (row > -1) { + // dropped between rows (insert) + isInsert = true; + idx = index(row, column, parent); + } + else if (parent.isValid()) { + // was dropped on a row (overwrite) + idx = parent; + } + else { + // dropped who knows where, (shouldn't be here though due check in canDropMimeData()) + return false; + } + //qDebug() << action << row << column << parent.row() << idx << idx.row() << hasOwnMimeData(data); + + // Force drops from other file windows to be copy actions because we don't want to delete our models. + if (action == Qt::MoveAction && !hasOwnMimeData(data)) + action = Qt::CopyAction; + + // canDropMimeData() only accepts models + emit modelsDropped(data, idx, isInsert, (action == Qt::MoveAction)); + + return true; +} + +QMimeData *TreeModel::getModelsMimeData(const QModelIndexList & indexes, QMimeData * mimeData) const +{ + if (!mimeData) + mimeData = new QMimeData(); + QByteArray mData; + encodeModelsData(indexes, &mData); + mimeData->setData("application/x-companion-modeldata", mData); + return mimeData; +} + +QMimeData *TreeModel::getGeneralMimeData(QMimeData * mimeData) const +{ + if (!mimeData) + mimeData = new QMimeData(); + QByteArray mData; + encodeGeneralData(&mData); + mimeData->setData("application/x-companion-generaldata", mData); + return mimeData; +} + +QMimeData *TreeModel::getHeaderMimeData(QMimeData * mimeData) const +{ + if (!mimeData) + mimeData = new QMimeData(); + QByteArray mData; + encodeHeaderData(&mData); + mimeData->setData("application/x-companion-radiodata-header", mData); + return mimeData; +} + +QUuid TreeModel::getMimeDataSourceId(const QMimeData * mimeData) const +{ + MimeHeaderData header; + decodeHeaderData(mimeData, &header); + return header.instanceId; +} + +bool TreeModel::hasSupportedMimeData(const QMimeData * mimeData) const +{ + foreach (const QString & mtype, mimeTypes()) { + if (mimeData->hasFormat(mtype)) + return true; + } + return false; +} + +bool TreeModel::hasModelsMimeData(const QMimeData * mimeData) const +{ + return mimeData->hasFormat("application/x-companion-modeldata"); +} + +bool TreeModel::hasGenralMimeData(const QMimeData * mimeData) const +{ + return mimeData->hasFormat("application/x-companion-generaldata"); +} + +bool TreeModel::hasHeaderMimeData(const QMimeData * mimeData) const +{ + return mimeData->hasFormat("application/x-companion-radiodata-header"); +} + +// returns true if mime data origin was this data model (vs. from another file window) +bool TreeModel::hasOwnMimeData(const QMimeData * mimeData) const +{ + return (getMimeDataSourceId(mimeData) == mimeHeaderData.instanceId); +} + +void TreeModel::encodeModelsData(const QModelIndexList & indexes, QByteArray * data) const +{ + foreach (const QModelIndex &index, indexes) { + if (index.isValid() && index.column() == 0) { + if (!getItem(index)->isCategory()) { // TODO: encode categoreis also + data->append('M'); + data->append((char *)&radioData->models[getModelIndex(index)], sizeof(ModelData)); + } + } + } +} + +void TreeModel::encodeGeneralData(QByteArray * data) const +{ + data->append('G'); + data->append((char *)&radioData->generalSettings, sizeof(GeneralSettings)); +} + +void TreeModel::encodeHeaderData(QByteArray * data) const +{ + // We use a unique ID representing this TreeModel instance (a unique file). + // This can be used eg. to detect cross-file drop operations. + QDataStream stream(data, QIODevice::WriteOnly); + stream << mimeHeaderData.dataVersion; + stream << mimeHeaderData.instanceId; +} + +// static +bool TreeModel::decodeHeaderData(const QMimeData * mimeData, MimeHeaderData * header) +{ + if (header && mimeData->hasFormat("application/x-companion-radiodata-header")) { + QByteArray data = mimeData->data("application/x-companion-radiodata-header"); + QDataStream stream(&data, QIODevice::ReadOnly); + stream >> header->dataVersion >> header->instanceId; + return true; + } + return false; +} + +// static +bool TreeModel::decodeMimeData(const QMimeData * mimeData, QVector * models, GeneralSettings * gs, bool * hasGenSet) +{ + bool ret = false; + char * gData; + + if (hasGenSet) + *hasGenSet = false; + + if (models && mimeData->hasFormat("application/x-companion-modeldata")) { + QByteArray mdlData = mimeData->data("application/x-companion-modeldata"); + gData = mdlData.data(); + int size = 0; + while (size < mdlData.size()) { + char c = *gData++; + if (c != 'M') + break; + ModelData model(*((ModelData *)gData)); + models->append(model); + gData += sizeof(ModelData); + size += sizeof(ModelData) + 1; + ret = true; + } + } + + // General settings + if (gs && mimeData->hasFormat("application/x-companion-generaldata")) { + QByteArray genData = mimeData->data("application/x-companion-generaldata"); + gData = genData.data(); + char c = *gData++; + if (c == 'G') { + *gs = *((GeneralSettings *)gData); + ret = true; + if (hasGenSet) + *hasGenSet = true; + } + } + + return ret; +} + +// static +int TreeModel::countModelsInMimeData(const QMimeData * mimeData) +{ + int ret = 0; + if (mimeData->hasFormat("application/x-companion-modeldata")) { + QByteArray mdlData = mimeData->data("application/x-companion-modeldata"); + ret = mdlData.size() / (sizeof(ModelData) + 1); + } + return ret; +} + + +TreeItem * TreeModel::getItem(const QModelIndex & index) const +{ + if (index.isValid()) { + TreeItem * item = static_cast(index.internalPointer()); + if (item) { + return item; + } + } + return rootItem; +} + +// recursive +QModelIndex TreeModel::getIndexForModel(const int modelIndex, QModelIndex parent) +{ + for (int i=0; i < rowCount(parent); ++i) { + QModelIndex idx = index(i, 0, parent); + if (hasChildren(idx) && (idx = getIndexForModel(modelIndex, idx)).isValid()) + return idx; + if (getItem(idx)->getModelIndex() == modelIndex) + return idx; + } + return QModelIndex(); +} + +QModelIndex TreeModel::getIndexForCategory(const int categoryIndex) +{ + for (int i=0; i < rowCount(); ++i) { + if (getItem(index(i, 0))->getCategoryIndex() == categoryIndex) + return index(i, 0); + } + return QModelIndex(); +} + +int TreeModel::getAvailableEEpromSize() +{ + return availableEEpromSize; +} + +int TreeModel::getModelIndex(const QModelIndex & index) const +{ + return getItem(index)->getModelIndex(); +} + +int TreeModel::getCategoryIndex(const QModelIndex & index) const +{ + return getItem(index)->getCategoryIndex(); +} + +int TreeModel::rowNumber(const QModelIndex & index) const +{ + return getItem(index)->childNumber(); +} + +bool TreeModel::isCategoryType(const QModelIndex & index) const +{ + return index.isValid() && getItem(index)->isCategory(); +} + +bool TreeModel::isModelType(const QModelIndex & index) const +{ + return index.isValid() && getItem(index)->isModel(); +} + +void TreeModel::markItemForCut(const QModelIndex & index, bool on) +{ + if (index.isValid() && index.column() == 0) + getItem(index)->setFlag(TreeItem::MarkedForCut, on); +} + +void TreeModel::markItemsForCut(const QModelIndexList & indexes, bool on) +{ + foreach (const QModelIndex &index, indexes) + markItemForCut(index, on); +} + +// onRowsAboutToBeRemoved could be a way to deal with models being drag-drop moved to another window/file. +// TreeModel detects these as removals and runs removeRows(), which deletes the Model indexes +// but not the actual models from the RadioData::models array. +// BUT this also runs when moving rows within our own tree, and if there is an error during the move, +// or the user cancels the operation, removeRows() is still called automatically somewhere inside QAbstractItemModel(). +// If a solution could be found to this problem then we could enable DnD-moving models between file windows. +/* +void TreeModel::onRowsAboutToBeRemoved(const QModelIndex & parent, int first, int last) +{ + qDebug() << parent << first << last; + QVector modelIndices; + for (int i=first; i <= last; ++i) { + modelIndices << getItem(index(i, 0, parent))->getModelIndex(); + } + if (modelIndices.size()) + emit modelsRemoved(modelIndices); +} +*/ + +void TreeModel::onRowsRemoved(const QModelIndex & parent, int first, int last) +{ + // This is a workaround to deal with models being DnD moved to another window/file or if user cancels a DnD move within our own. + // TreeModel detects these as removals and runs removeRows(), which deletes the Model indexes but not our actual models. See notes above. + //qDebug() << parent << first << last; + emit refreshRequested(); // request refresh from View because it may have it's own ideas +} + void TreeModel::refresh() { EEPROMInterface * eepromInterface = getCurrentEEpromInterface(); Board::Type board = eepromInterface->getBoard(); + TreeItem * defaultCategoryItem = NULL; + bool hasCategories = getCurrentFirmware()->getCapability(Capability::HasModelCategories); + bool hasEepromSizeData = (rootItem->columnCount() > 2); - if (!IS_SKY9X(board) && !IS_HORUS(board)) { + if (hasEepromSizeData) { availableEEpromSize = Boards::getEEpromSize(board) - 64; // let's consider fat availableEEpromSize -= 16 * ((eepromInterface->getSize(radioData->generalSettings) + 14) / 15); } + this->blockSignals(true); // make sure onRowsRemoved is not triggered removeRows(0, rowCount()); + this->blockSignals(false); - TreeItem * defaultCategoryItem = NULL; - - if (IS_HORUS(board)) { + if (hasCategories) { for (unsigned i = 0; i < radioData->categories.size(); i++) { TreeItem * current = rootItem->appendChild(i, -1); current->setData(0, QString(radioData->categories[i].name)); @@ -266,7 +662,10 @@ void TreeModel::refresh() ModelData & model = radioData->models[i]; int currentColumn = 0; TreeItem * current = NULL; - if (IS_HORUS(board)) { + + model.modelIndex = i; + + if (hasCategories) { if (!model.isEmpty()) { TreeItem * categoryItem; // TODO category should be set to -1 if not Horus @@ -297,7 +696,7 @@ void TreeModel::refresh() else modelName = QString().sprintf("Model%02d", i+1); current->setData(currentColumn++, modelName); - if (!IS_SKY9X(board) && !IS_HORUS(board)) { + if (hasEepromSizeData) { int size = eepromInterface->getSize(model); current->setData(currentColumn++, QString().sprintf("%5d", size)); size = 16 * ((size + 14) / 15); @@ -310,190 +709,7 @@ void TreeModel::refresh() } } - if (!IS_SKY9X(board) && !IS_HORUS(board)) { + if (hasEepromSizeData) { availableEEpromSize = (availableEEpromSize / 16) * 15; } } - -#if 0 -ModelsListWidget::ModelsListWidget(QWidget * parent): - QTreeView(parent), - radioData(NULL) -{ - setColumnWidth(0, 50); - setColumnWidth(2, 100); - - active_highlight_color = palette().color(QPalette::Active, QPalette::Highlight); -} - -void ModelsListWidget::mousePressEvent(QMouseEvent *event) -{ - if (event->button() == Qt::LeftButton) - dragStartPosition = event->pos(); - - QTreeView::mousePressEvent(event); -} - -void ModelsListWidget::mouseMoveEvent(QMouseEvent *event) -{ - if (!(event->buttons() & Qt::LeftButton)) - return; - - if ((event->pos() - dragStartPosition).manhattanLength() < QApplication::startDragDistance()) - return; - - QDrag * drag = new QDrag(this); - - QByteArray gmData; - doCopy(&gmData); - - QMimeData * mimeData = new QMimeData; - mimeData->setData("application/x-companion", gmData); - - drag->setMimeData(mimeData); - - //Qt::DropAction dropAction = drag->exec(Qt::CopyAction | Qt::MoveAction, Qt::CopyAction); - - //if(dropAction==Qt::MoveAction) - - // QTreeWidget::mouseMoveEvent(event); -} - -void ModelsListWidget::saveSelection() -{ - /*currentSelection.current_item = currentItem(); - for (int i=0; igetCapability(Models)+1; ++i) { - currentSelection.selected[i] = selectionModel()->isSelected(model()->index(i, 0)); - }*/ -} - -void ModelsListWidget::restoreSelection() -{ - /*setCurrentItem(currentSelection.current_item); - for (int i=0; igetCapability(Models)+1; ++i) { - selectionModel()->select(model()->index(i, 0), currentSelection.selected[i] ? QItemSelectionModel::Select : QItemSelectionModel::Deselect); - }*/ -} - -void ModelsListWidget::dragEnterEvent(QDragEnterEvent *event) -{ - if (event->mimeData()->hasFormat("application/x-companion")) { - event->acceptProposedAction(); - saveSelection(); - } -} - -void ModelsListWidget::dragLeaveEvent(QDragLeaveEvent *) -{ - restoreSelection(); -} - -void ModelsListWidget::dragMoveEvent(QDragMoveEvent *event) -{ - int row = indexAt(event->pos()).row(); - const QMimeData * mimeData = event->mimeData(); - if (mimeData->hasFormat("application/x-companion")) { - QByteArray gmData = mimeData->data("application/x-companion"); - event->acceptProposedAction(); - clearSelection(); - DragDropHeader * header = (DragDropHeader *)gmData.data(); - if (row >= 0) { - if (header->general_settings) - selectionModel()->select(model()->index(0, 0), QItemSelectionModel::Select); - for (int i=row, end=std::min(getCurrentFirmware()->getCapability(Models)+1, row+header->models_count); iselect(model()->index(i, 0), QItemSelectionModel::Select); - } - } -} - -void ModelsListWidget::dropEvent(QDropEvent *event) -{ - int row = this->indexAt(event->pos()).row(); - if (row < 0) - return; - - // QMessageBox::warning(this, tr("Companion"), tr("Index :%1").arg(row)); - const QMimeData * mimeData = event->mimeData(); - - if (mimeData->hasFormat("application/x-companion")) { - QByteArray gmData = mimeData->data("application/x-companion"); - if (event->source() && event->dropAction() == Qt::MoveAction) - ((ModelsListWidget*)event->source())->doCut(&gmData); - doPaste(&gmData, row); - clearSelection(); - // setCurrentItem(topLevelItem(row)); - DragDropHeader * header = (DragDropHeader *)gmData.data(); - if (header->general_settings) - selectionModel()->select(model()->index(0, 0), QItemSelectionModel::Select); - for (int i=row, end=std::min(getCurrentFirmware()->getCapability(Models)+1, row+header->models_count); iselect(model()->index(i, 0), QItemSelectionModel::Select); - } - event->acceptProposedAction(); -} - -#ifndef WIN32 -void ModelsListWidget::focusInEvent ( QFocusEvent * event ) -{ - QTreeView::focusInEvent(event); - QPalette palette = this->palette(); - palette.setColor(QPalette::Active, QPalette::Highlight, active_highlight_color); - palette.setColor(QPalette::Inactive, QPalette::Highlight, active_highlight_color); - setPalette(palette); -} - -void ModelsListWidget::focusOutEvent ( QFocusEvent * event ) -{ - QTreeView::focusOutEvent(event); - QPalette palette = this->palette(); - palette.setColor(QPalette::Active, QPalette::Highlight, palette.color(QPalette::Active, QPalette::Midlight)); - palette.setColor(QPalette::Inactive, QPalette::Highlight, palette.color(QPalette::Active, QPalette::Midlight)); - setPalette(palette); -} -#endif - -void ModelsListWidget::doCut(QByteArray * gmData) -{ - bool modified = false; - DragDropHeader * header = (DragDropHeader *)gmData->data(); - for (int i=0; imodels_count; i++) { - if (radioData->generalSettings.currModelIndex != (unsigned int)header->models[i]-1) { - radioData->models[header->models[i]-1].clear(); - modified=true; - } - } - if (modified) { - ((MdiChild *)parent())->setModified(); - } -} - -void ModelsListWidget::duplicate() -{ - int i = this->currentRow(); - if (i && igetCapability(Models)) { - ModelData * model = &radioData->models[i-1]; - while (igetCapability(Models)) { - if (radioData->models[i].isEmpty()) { - radioData->models[i] = *model; - strcpy(radioData->models[i].filename, qPrintable(radioData->getNextModelFilename())); - ((MdiChild *)parent())->setModified(); - break; - } - i++; - } - if (i==getCurrentFirmware()->getCapability(Models)) { - QMessageBox::warning(this, "Companion", tr("No free slot available, cannot duplicate"), QMessageBox::Ok); - } - } -} - -void ModelsListWidget::onCurrentItemChanged(QTreeWidgetItem * current, QTreeWidgetItem *) -{ - /*int index = indexOfTopLevelItem(current); - if (!isVisible()) - ((MdiChild*)parent())->viableModelSelected(false); - else if (index<1) - ((MdiChild*)parent())->viableModelSelected(false); - else - ((MdiChild*)parent())->viableModelSelected(!radioData->models[currentRow()-1].isEmpty()); */ -} -#endif diff --git a/companion/src/modelslist.h b/companion/src/modelslist.h index 46668dd0d..499e96a6b 100644 --- a/companion/src/modelslist.h +++ b/companion/src/modelslist.h @@ -22,17 +22,15 @@ #define _MODELSLIST_H_ #include "eeprominterface.h" -#include - -struct CurrentSelection -{ - QTreeWidgetItem * current_item; - bool selected[CPN_MAX_MODELS+1]; -}; +#include +#include +#include class TreeItem { public: + enum TreeItemFlags { MarkedForCut = 0x01 }; + explicit TreeItem(const QVector & itemData); explicit TreeItem(TreeItem * parent, int categoryIndex, int modelIndex); ~TreeItem(); @@ -42,14 +40,26 @@ class TreeItem int columnCount() const; QVariant data(int column) const; TreeItem * appendChild(int categoryIndex, int modelIndex); - TreeItem * parent(); + TreeItem * insertChild(const int row, int categoryIndex, int modelIndex); bool removeChildren(int position, int count); + bool insertChildren(int row, int count); int childNumber() const; bool setData(int column, const QVariant &value); + TreeItem * parent() { return parentItem; } + void setParent(TreeItem * p) { parentItem = p; } int getModelIndex() const { return modelIndex; } + void setModelIndex(int value) { modelIndex = value; } int getCategoryIndex() const { return categoryIndex; } + void setCategoryIndex(int value) { categoryIndex = value; } + + quint16 getFlags() const { return flags; } + void setFlags(const quint16 & value) { flags = value; } + void setFlag(const quint16 & flag, const bool on = true); + + bool isCategory() const; + bool isModel() const; private: QList childItems; @@ -57,6 +67,7 @@ class TreeItem TreeItem * parentItem; int categoryIndex; int modelIndex; + quint16 flags; }; @@ -65,47 +76,81 @@ class TreeModel : public QAbstractItemModel Q_OBJECT public: + struct MimeHeaderData { + QUuid instanceId; + quint16 dataVersion; + }; + TreeModel(RadioData * radioData, QObject *parent = 0); virtual ~TreeModel(); - QVariant data(const QModelIndex &index, int role) const Q_DECL_OVERRIDE; - QVariant headerData(int section, Qt::Orientation orientation, - int role = Qt::DisplayRole) const Q_DECL_OVERRIDE; + virtual QVariant data(const QModelIndex &index, int role = Qt::DisplayRole) const Q_DECL_OVERRIDE; + virtual QVariant headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const Q_DECL_OVERRIDE; + virtual bool setData(const QModelIndex &index, const QVariant &value, int role = Qt::EditRole) Q_DECL_OVERRIDE; - QModelIndex index(int row, int column, - const QModelIndex &parent = QModelIndex()) const Q_DECL_OVERRIDE; - QModelIndex parent(const QModelIndex &index) const Q_DECL_OVERRIDE; + virtual QModelIndex index(int row, int column, const QModelIndex &parent = QModelIndex()) const Q_DECL_OVERRIDE; + virtual QModelIndex parent(const QModelIndex &index) const Q_DECL_OVERRIDE; + virtual Qt::ItemFlags flags(const QModelIndex &index) const Q_DECL_OVERRIDE; - int rowCount(const QModelIndex &parent = QModelIndex()) const Q_DECL_OVERRIDE; - int columnCount(const QModelIndex &parent = QModelIndex()) const Q_DECL_OVERRIDE; + virtual int rowCount(const QModelIndex &parent = QModelIndex()) const Q_DECL_OVERRIDE; + virtual int columnCount(const QModelIndex &parent = QModelIndex()) const Q_DECL_OVERRIDE; + virtual bool removeRows(int position, int rows, const QModelIndex &parent = QModelIndex()) Q_DECL_OVERRIDE; + //virtual bool insertRows(int row, int count, const QModelIndex & parent) Q_DECL_OVERRIDE; - Qt::ItemFlags flags(const QModelIndex &index) const Q_DECL_OVERRIDE; - bool setData(const QModelIndex &index, const QVariant &value, - int role = Qt::EditRole) Q_DECL_OVERRIDE; + virtual QStringList mimeTypes() const Q_DECL_OVERRIDE; + virtual Qt::DropActions supportedDropActions() const Q_DECL_OVERRIDE; + virtual Qt::DropActions supportedDragActions() const Q_DECL_OVERRIDE; + virtual QMimeData * mimeData(const QModelIndexList & indexes) const Q_DECL_OVERRIDE; + virtual bool canDropMimeData(const QMimeData * data, Qt::DropAction action, int row, int column, const QModelIndex & parent) const Q_DECL_OVERRIDE; + virtual bool dropMimeData(const QMimeData * data, Qt::DropAction action, int row, int column, const QModelIndex & parent) Q_DECL_OVERRIDE; - bool removeRows(int position, int rows, - const QModelIndex &parent = QModelIndex()) Q_DECL_OVERRIDE; + void encodeModelsData(const QModelIndexList & indexes, QByteArray * data) const; + void encodeGeneralData(QByteArray * data) const; + void encodeHeaderData(QByteArray * data) const; + QMimeData * getModelsMimeData(const QModelIndexList & indexes, QMimeData * mimeData = NULL) const; + QMimeData * getGeneralMimeData(QMimeData * mimeData = NULL) const; + QMimeData * getHeaderMimeData(QMimeData * mimeData = NULL) const; + QUuid getMimeDataSourceId(const QMimeData * mimeData) const; + bool hasSupportedMimeData(const QMimeData * mimeData) const; + bool hasModelsMimeData(const QMimeData * mimeData) const; + bool hasGenralMimeData(const QMimeData * mimeData) const; + bool hasHeaderMimeData(const QMimeData * mimeData) const; + bool hasOwnMimeData(const QMimeData * mimeData) const; + static bool decodeHeaderData(const QMimeData * mimeData, MimeHeaderData * header); + static bool decodeMimeData(const QMimeData * mimeData, QVector * models = NULL, GeneralSettings * gs = NULL, bool * hasGenSet = NULL); + static int countModelsInMimeData(const QMimeData * mimeData); + + QModelIndex getIndexForModel(const int modelIndex, QModelIndex parent = QModelIndex()); + QModelIndex getIndexForCategory(const int categoryIndex); + int getAvailableEEpromSize(); + int getModelIndex(const QModelIndex & index) const; + int getCategoryIndex(const QModelIndex & index) const; + int rowNumber(const QModelIndex & index = QModelIndex()) const; + bool isCategoryType(const QModelIndex & index) const; + bool isModelType(const QModelIndex & index) const; + + public slots: + void markItemForCut(const QModelIndex & index, bool on = true); + void markItemsForCut(const QModelIndexList & indexes, bool on = true); void refresh(); - int getAvailableEEpromSize() { return availableEEpromSize; } + signals: + void modelsDropped(const QMimeData * mimeData, const QModelIndex toRowIdx, const bool insert, const bool move); + void modelsRemoved(const QVector modelIndices); + void refreshRequested(); - int getModelIndex(const QModelIndex & index) const { - return getItem(index)->getModelIndex(); - } + private slots: + //void onRowsAboutToBeRemoved(const QModelIndex & parent, int first, int last); + void onRowsRemoved(const QModelIndex & parent, int first, int last); - int getCategoryIndex(const QModelIndex & index) const { - return getItem(index)->getCategoryIndex(); - } - - int rowNumber(const QModelIndex & index = QModelIndex()) const { - return getItem(index)->childNumber(); - } private: TreeItem * getItem(const QModelIndex & index) const; + TreeItem * rootItem; RadioData * radioData; int availableEEpromSize; + MimeHeaderData mimeHeaderData; }; #endif // _MODELSLIST_H_ diff --git a/companion/src/multimodelprinter.cpp b/companion/src/multimodelprinter.cpp index 858664609..73df83002 100644 --- a/companion/src/multimodelprinter.cpp +++ b/companion/src/multimodelprinter.cpp @@ -121,13 +121,10 @@ MultiModelPrinter::MultiModelPrinter(Firmware * firmware): MultiModelPrinter::~MultiModelPrinter() { - for(int i=0; i < modelPrinterMap.size(); i++) { - if (modelPrinterMap.value(i).second) - delete modelPrinterMap.value(i).second; - } + clearModels(); } -void MultiModelPrinter::setModel(int idx, const ModelData & model, const GeneralSettings & generalSettings) +void MultiModelPrinter::setModel(int idx, const ModelData * model, const GeneralSettings * generalSettings) { if (modelPrinterMap.contains(idx) && modelPrinterMap.value(idx).second) { // free existing model printer @@ -135,13 +132,22 @@ void MultiModelPrinter::setModel(int idx, const ModelData & model, const General modelPrinterMap[idx].second = NULL; } - QPair pair(&model, new ModelPrinter(firmware, generalSettings, model)); + QPair pair(model, new ModelPrinter(firmware, *generalSettings, *model)); modelPrinterMap.insert(idx, pair); // QMap.insert will replace any existing key } -void MultiModelPrinter::setModel(int idx, const ModelData & model) +void MultiModelPrinter::setModel(int idx, const ModelData * model) { - setModel(idx, model, defaultSettings); + setModel(idx, model, &defaultSettings); +} + +void MultiModelPrinter::clearModels() +{ + for(int i=0; i < modelPrinterMap.size(); i++) { + if (modelPrinterMap.value(i).second) + delete modelPrinterMap.value(i).second; + } + modelPrinterMap.clear(); } QString MultiModelPrinter::print(QTextDocument * document) diff --git a/companion/src/multimodelprinter.h b/companion/src/multimodelprinter.h index 97332691a..a896f9d6e 100644 --- a/companion/src/multimodelprinter.h +++ b/companion/src/multimodelprinter.h @@ -34,8 +34,9 @@ class MultiModelPrinter: public QObject MultiModelPrinter(Firmware * firmware); virtual ~MultiModelPrinter(); - void setModel(int idx, const ModelData & model, const GeneralSettings & generalSettings); - void setModel(int idx, const ModelData & model); + void setModel(int idx, const ModelData * model, const GeneralSettings * generalSettings); + void setModel(int idx, const ModelData * model); + void clearModels(); QString print(QTextDocument * document); protected: diff --git a/companion/src/printdialog.cpp b/companion/src/printdialog.cpp index 6f403dfb9..8ea8d0525 100644 --- a/companion/src/printdialog.cpp +++ b/companion/src/printdialog.cpp @@ -36,7 +36,7 @@ PrintDialog::PrintDialog(QWidget *parent, Firmware * firmware, GeneralSettings & ui->setupUi(this); setWindowIcon(CompanionIcon("print.png")); setWindowTitle(model.name); - multimodelprinter.setModel(0, model, generalSettings); + multimodelprinter.setModel(0, &model, &generalSettings); ui->textEdit->setHtml(multimodelprinter.print(ui->textEdit->document())); if (!printfilename.isEmpty()) { printToFile(); diff --git a/companion/src/radiodata.h b/companion/src/radiodata.h index 7a099220f..d04dbabd4 100644 --- a/companion/src/radiodata.h +++ b/companion/src/radiodata.h @@ -1021,6 +1021,8 @@ class ModelData { int category; char name[15+1]; char filename[16+1]; + int modelIndex; // Companion only, temporary index position managed by data model. + TimerData timers[CPN_MAX_TIMERS]; bool noGlobalFunctions; bool thrTrim; // Enable Throttle Trim diff --git a/companion/src/storage/appdata.cpp b/companion/src/storage/appdata.cpp index 0c9ae6dfe..e6feb194c 100644 --- a/companion/src/storage/appdata.cpp +++ b/companion/src/storage/appdata.cpp @@ -434,6 +434,9 @@ QStringList AppData::simuDbgFilters() { return _simuDbgFilters; } QByteArray AppData::mainWinGeo() { return _mainWinGeo; } QByteArray AppData::mainWinState() { return _mainWinState; } QByteArray AppData::modelEditGeo() { return _modelEditGeo; } +QByteArray AppData::mdiWinGeo() { return _mdiWinGeo; } +QByteArray AppData::mdiWinState() { return _mdiWinState; } +QByteArray AppData::compareWinGeo(){ return _compareWinGeo; } QString AppData::armMcu() { return _armMcu; } QString AppData::avrArguments() { return _avrArguments; } @@ -464,8 +467,10 @@ bool AppData::snapToClpbrd() { return _snapToClpbrd; } bool AppData::autoCheckApp() { return _autoCheckApp; } bool AppData::autoCheckFw() { return _autoCheckFw; } bool AppData::simuSW() { return _simuSW; } -bool AppData::useWizard() { return _useWizard; } +bool AppData::tabbedMdi() { return _tabbedMdi; } +bool AppData::removeModelSlots() { return _remvModelSlots; } +int AppData::newModelAction() { return _newModelAction; } int AppData::backLight() { return _backLight; } int AppData::embedSplashes() { return _embedSplashes; } int AppData::fwServerFails() { return _fwServerFails; } @@ -486,6 +491,9 @@ void AppData::simuDbgFilters (const QStringList x) { store(x, _simuDbgFilters, void AppData::mainWinGeo (const QByteArray x) { store(x, _mainWinGeo, "mainWindowGeometry" );} void AppData::mainWinState (const QByteArray x) { store(x, _mainWinState, "mainWindowState" );} void AppData::modelEditGeo (const QByteArray x) { store(x, _modelEditGeo, "modelEditGeometry" );} +void AppData::mdiWinGeo (const QByteArray x) { store(x, _mdiWinGeo, "mdiWinGeo" );} +void AppData::mdiWinState (const QByteArray x) { store(x, _mdiWinState, "mdiWinState" );} +void AppData::compareWinGeo (const QByteArray x) { store(x, _compareWinGeo, "compareWinGeo" );} void AppData::armMcu (const QString x) { store(x, _armMcu, "arm_mcu" );} void AppData::avrArguments (const QString x) { store(x, _avrArguments, "avr_arguments" );} @@ -516,8 +524,10 @@ void AppData::snapToClpbrd (const bool x) { store(x, _snapToClpbrd, void AppData::autoCheckApp (const bool x) { store(x, _autoCheckApp, "startup_check_companion" );} void AppData::autoCheckFw (const bool x) { store(x, _autoCheckFw, "startup_check_fw" );} void AppData::simuSW (const bool x) { store(x, _simuSW, "simuSW" );} -void AppData::useWizard (const bool x) { store(x, _useWizard, "useWizard" );} +void AppData::tabbedMdi (const bool x) { store(x, _tabbedMdi, "tabbedMdi" );} +void AppData::removeModelSlots(const bool x) { store(x, _remvModelSlots, "removeModelSlots" );} +void AppData::newModelAction (const int x) { store(x, _newModelAction, "newModelAction" );} void AppData::backLight (const int x) { store(x, _backLight, "backLight" );} void AppData::embedSplashes (const int x) { store(x, _embedSplashes, "embedded_splashes" );} void AppData::fwServerFails (const int x) { store(x, _fwServerFails, "fwserver" );} @@ -569,6 +579,9 @@ void AppData::init() getset( _mainWinGeo, "mainWindowGeometry" ,"" ); getset( _mainWinState, "mainWindowState" ,"" ); getset( _modelEditGeo, "modelEditGeometry" ,"" ); + getset( _mdiWinGeo, "mdiWinGeo" ,"" ); + getset( _mdiWinState, "mdiWinState" ,"" ); + getset( _compareWinGeo, "compareWinGeo" ,"" ); getset( _armMcu, "arm_mcu" ,"at91sam3s4-9x" ); getset( _avrArguments, "avr_arguments" ,"" ); @@ -607,8 +620,10 @@ void AppData::init() getset( _autoCheckApp, "startup_check_companion" ,true ); getset( _autoCheckFw, "startup_check_fw" ,true ); getset( _simuSW, "simuSW" ,false ); - getset( _useWizard, "useWizard" ,true ); + getset( _tabbedMdi, "tabbedMdi" ,false ); + getset( _remvModelSlots, "removeModelSlots" ,true ); + getset( _newModelAction, "newModelAction" ,1 ); getset( _backLight, "backLight" ,0 ); getset( _embedSplashes, "embedded_splashes" ,0 ); getset( _fwServerFails, "fwserver" ,0 ); @@ -636,7 +651,7 @@ QMap AppData::getActiveProfiles() bool AppData::importSettings(QSettings & toSettings) { - QSettings * fromSettings; + QSettings * fromSettings = NULL; QSettings settings21("OpenTX", "Companion 2.1"); QSettings settings20("OpenTX", "Companion 2.0"); @@ -651,8 +666,6 @@ bool AppData::importSettings(QSettings & toSettings) fromSettings = &settings16; else if (settings9x.contains("default_mode")) fromSettings = &settings9x; - else - return false; // do not copy these settings QStringList excludeKeys = QStringList() << "compilation-server"; @@ -664,17 +677,19 @@ bool AppData::importSettings(QSettings & toSettings) #endif // import settings - foreach (const QString & key, fromSettings->allKeys()) { - if (fromSettings->value(key).isValid() && !excludeKeys.contains(key)) { - toSettings.setValue(key, fromSettings->value(key)); + if (fromSettings) { + foreach (const QString & key, fromSettings->allKeys()) { + if (fromSettings->value(key).isValid() && !excludeKeys.contains(key)) { + toSettings.setValue(key, fromSettings->value(key)); + } } } // Additional adjustments for companion9x settings - if (fromSettings->applicationName() == "companion9x") { + if (fromSettings && fromSettings->applicationName() == "companion9x") { // Store old values in new locations autoCheckApp(toSettings.value("startup_check_companion9x", true).toBool()); - useWizard(toSettings.value("wizardEnable", true).toBool()); + toSettings.setValue("useWizard", toSettings.value("wizardEnable", true)); // Convert and store the firmware type QString fwType = toSettings.value("firmware", "").toString(); @@ -717,5 +732,14 @@ bool AppData::importSettings(QSettings & toSettings) id( 0 ); } - return true; + // convert old settings to new + + if (toSettings.contains("useWizard")) { + if (!toSettings.contains("newModelAction")) { + newModelAction(toSettings.value("useWizard").toBool() ? 1 : 2); + } + toSettings.remove("useWizard"); + } + + return fromSettings ? true : false; } diff --git a/companion/src/storage/appdata.h b/companion/src/storage/appdata.h index f7d3d0cd4..2f85e50e8 100644 --- a/companion/src/storage/appdata.h +++ b/companion/src/storage/appdata.h @@ -255,6 +255,9 @@ class AppData: protected CompStoreObj QByteArray _mainWinGeo; QByteArray _mainWinState; QByteArray _modelEditGeo; + QByteArray _mdiWinGeo; + QByteArray _mdiWinState; + QByteArray _compareWinGeo; QString _armMcu; QString _avrArguments; @@ -285,8 +288,10 @@ class AppData: protected CompStoreObj bool _autoCheckApp; bool _autoCheckFw; bool _simuSW; - bool _useWizard; + bool _tabbedMdi; + bool _remvModelSlots; + int _newModelAction; // 0=no action; 1=model wizard; 2=model edit int _backLight; int _embedSplashes; int _fwServerFails; @@ -309,6 +314,9 @@ class AppData: protected CompStoreObj QByteArray mainWinGeo(); QByteArray mainWinState(); QByteArray modelEditGeo(); + QByteArray mdiWinGeo(); + QByteArray mdiWinState(); + QByteArray compareWinGeo(); QString armMcu(); QString avrArguments(); @@ -340,8 +348,10 @@ class AppData: protected CompStoreObj bool autoCheckApp(); bool autoCheckFw(); bool simuSW(); - bool useWizard(); + bool tabbedMdi(); + bool removeModelSlots(); + int newModelAction(); int backLight(); int embedSplashes(); int fwServerFails(); @@ -362,6 +372,9 @@ class AppData: protected CompStoreObj void mainWinGeo (const QByteArray); void mainWinState (const QByteArray); void modelEditGeo (const QByteArray); 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May be different from firmware language - + Build Options - + Splash Screen - + Other Settings - + SD Structure path - - + + The profile specific folder, if set, will override general Backup folder - + Backup folder - + If set it will override the application general setting - + if set, will override general backup enable - - + + Enable automatic backup before writing firmware - + General Settings - + Default Stick Mode - + Mode selection: Mode 1: @@ -176,331 +176,326 @@ Mode 4: - + Mode 1 (RUD ELE THR AIL) - + Mode 2 (RUD THR ELE AIL) - + Mode 3 (AIL ELE THR RUD) - + Mode 4 (AIL THR ELE RUD) - + Default Channel Order - + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> - + R E T A - + R E A T - + R T E A - + R T A E - + R A E T - + R A T E - + E R T A - + E R A T - + E T R A - + E T A R - + E A R T - + E A T R - + T R E A - + T R A E - + T E R A - + T E A R - + T A R E - + T A E R - + A R E T - + A R T E - + A E R T - + A E T R - + A T R E - + A T E R - + Append version number to FW file name - + Offer to write FW to Tx after download - + Clear Image - + Select Image - - Remove Profile - - - - - - - - + + + + + Select Folder - + Application Settings - + Automatic check for Companion updates - + Show splash screen when Companion starts - + Automatic check for OpenTX firmware updates - + Splash Screen Library - + Files to keep - + Google Earth Executable - + User Splash Screens - + Automatic Backup Folder - + Use model wizard when creating a new model - + Only show user splash images - + Show user and companion splash images - + Select Executable - + Use OpenTX firmware nightly builds - + Use Companion nightly builds - + Simulator Settings - + Calibrate - + Blue - + Green - + Red - + Orange - + Yellow - + Simulator capture folder - + Only capture to clipboard - + Enable - + Joystick - + Simulator BackLight - + Remember simulator switch values - + Simulator Volume Gain @@ -510,13 +505,13 @@ Mode 4: - + Select your snapshot folder - - + + No joysticks found @@ -536,43 +531,33 @@ Mode 4: - + Select your library folder - - + + Select your Models and Settings backup folder - + Select Google Earth executable - + Select the folder replicating your SD structure - - Not possible to remove profile - - - - - The default profile can not be removed. - - - - + Open Image to load - + Images (%1) @@ -656,42 +641,42 @@ Mode 4: - - Drag first model here + + To compare models, drag and drop them anywhere in this window. - - Drag second model here - - - - + Close - + Print - + Print to file - - No name + + Unnamed Model %1 - + + Click to remove this model. + + + + Print Document - + Select PDF output file @@ -699,7 +684,7 @@ Mode 4: ConclusionPage - + OK, I understand. @@ -1040,22 +1025,22 @@ Mode 4: CyclicPage - + 90 - + 120 - + 120x - + 140 @@ -1134,12 +1119,12 @@ To <b>remove a remembered entry</b> from the filter list, first cho - + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> - + Debug Console Filter Help @@ -1147,90 +1132,90 @@ To <b>remove a remembered entry</b> from the filter list, first cho EepromInterface - + Possible causes for this: - + - Eeprom is from a newer version of OpenTX - + - Eeprom is not from OpenTX - + - Eeprom is not from Th9X - + - Eeprom is not from Gruvin9X - + - Eeprom is not from ErSky9X - + - Eeprom is not from Er9X - + - Eeprom size is invalid - + - Eeprom file system is invalid - + - Eeprom is from a unknown board - + - Eeprom is from the wrong board - + - Eeprom backup not supported - + - Something that couldn't be guessed, sorry - + Warning: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - + Warnings! @@ -1238,12 +1223,12 @@ To <b>remove a remembered entry</b> from the filter list, first cho ElevonsPage - + <br>First Elevon Channel: - + Second Elevon Channel: @@ -1387,22 +1372,22 @@ If blank then the input is considered to be "ON" all the time. FblPage - + Throttle Channel: - + Yaw Channel: - + Pitch Channel: - + Roll Channel: @@ -1454,27 +1439,27 @@ May be different from firmware language FlapsPage - + No No - + Yes, controlled by a single channel - + Yes, controlled by two channels - + <br>First Flap Channel: - + Second Flap Channel: @@ -1983,17 +1968,17 @@ Please use ZADIG to properly install the driver. FlybarSelectionPage - + Has Flybar - + Flybarless - + Flybar: @@ -2956,17 +2941,17 @@ Are you sure ? GyroPage - + No No - + Yes, controled by a switch - + Yes, controlled by a pot @@ -3350,22 +3335,22 @@ Are you sure ? HeliPage - + Throttle Channel: - + Yaw Channel: - + Pitch Channel: - + Roll Channel: @@ -3756,122 +3741,122 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt MainWindow - - + + File loaded - + Display previous warning again at startup ? - + Checking for updates - + Unable to check for updates. - + A new version of Companion is available (version %1)<br>Would you like to download it? - - + + Save As - + Executable (*.exe) - + New release available - + A new release of Companion is available, please check the OpenTX website! - - + + No updates available at this time. - + Would you like to launch the installer? - - + + Error - + Error opening file %1: %2. - + Not enough flash available on this board for all the selected options - + Compilation server temporary failure, try later - + Compilation server too busy, try later - + Compilation error - + Invalid firmware - + Invalid board - + Invalid language - + Unknown server failure, try later - + Do you want to write the firmware to the radio now ? - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -3880,31 +3865,31 @@ We recommend you view the release notes using the button below to learn about an - - + + Yes - - + + No No - - + + Release Notes - - + + Do you want to download release %1 now ? - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -3915,625 +3900,624 @@ We recommend you view the release notes using the button below to learn about an - + Ignore this release %1? - - - + + Companion - + The new theme will be loaded the next time you start Companion. - - The icon size will be used the next time you start Companion. - - - - - + + Open Models and Settings file - - + + File saved - - + + Synchronize SD - + Firmware updates - + Current firmware does not provide release notes informations. - - + + Read Firmware from Radio - - + + Read Models and Settings from Radio - + Models and Settings read - - + + This function is not yet implemented - + Save Radio Backup to File - + Read Radio Firmware to File - + OpenTX Home Page: <a href='%1'>%1</a> - + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> - + Copyright OpenTX Team - + About Companion - + OpenTX Companion %1 - Radio: %2 - Profile: %3 - + New - + Create a new Models and Settings file - + Open... - + Save - - + + Save Models and Settings file - + Save As... - + Exit - + Exit the application - - Cut Model + + Create a new Radio Settings Profile - - Cut current model to the clipboard + + Copy Current Radio Profile - - Copy Model + + Duplicate current Radio Settings Profile - - Copy current model to the clipboard + + Delete Current Radio Profile - - Paste Model + + Delete the current Radio Settings Profile - - Paste model from clipboard - - - - + Classical - + The classic companion9x icon theme - + Yerico - + Yellow round honey sweet icon theme - + Monochrome - + A monochrome black icon theme - + MonoWhite - + A monochrome white icon theme - + + Windows + + + + + Tabbed Windows + + + + + Tile Windows + + + + + Cascade Windows + + + + + Close All Windows + + + + + - Copy + + + + + Not possible to remove profile + + + + + The default profile can not be removed. + + + + + Confirm Delete Profile + + + + + Are you sure you wish to delete the "%1" radio profile? There is no way to undo this action! + + + + MonoBlue - + A monochrome blue icon theme - + Small - + Use small toolbar icons - + Normal - + Use normal size toolbar icons - + Big - + Use big toolbar icons - + Huge - + Use huge toolbar icons - + System language - + About... - + Show the application's About box - - Print... - - - - - Print current model - - - - - Simulate... - - - - - Simulate current model - - - - - Alt+S - - - - - Load Backup... - - - - - Load backup from file - - - - + View Log File... - + Open and view log file - + Settings... - + Edit Settings - + Download... - + Download firmware and voice files - + Check for Updates... - + Check OpenTX and Companion updates - + Companion Changes... - + Show Companion change log - + Firmware Changes... - + Show firmware change log - + Compare Models... - + Compare models - + Edit Radio Splash Image... - + Edit the splash image of your Radio - + List programmers... - + List available programmers - + Fuses... - + Show fuses dialog - + Read firmware from Radio - + Write Firmware to Radio - + Write firmware to Radio - + Add Radio Profile - - Create a new Radio Setting Profile - - - - + Manuals and other Documents - + Open the OpenTX document page in a web browser - + Write Models and Settings To Radio - + Write Models and Settings to Radio - + Read Models and Settings From Radio - + Configure Communications... - + Configure software for communicating with the Radio - + Write Backup to Radio - + Write Backup from file to Radio - + Backup Radio to File - + Save a complete backup file of all settings and model data in the Radio - + Contributors... - + A tribute to those who have contributed to OpenTX and Companion - + SD card synchronization - + Use default system language. - + Use %1 language (some translations may not be complete). - + Recent Files - + Set Menu Language - + Set Icon Theme - + Set Icon Size - - + + File - + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. - - + + Edit - + Settings - + Read/Write - - + + Help - - + + Radio Profile - + Recent Models+Settings - + Show recent Models+Settings documents - + Show the list of radio profiles - + Write - + Ready - + %2 - + New Radio @@ -4541,254 +4525,372 @@ We recommend you view the release notes using the button below to learn about an MdiChild - - Radio settings - - - - - Simulate Tx - - - - - Delete selected models? - - - - - Cannot delete default model. - - - - - &Edit - - - - - &Restore from backup - - - - - &Model Wizard - - - - - &Delete - - - - - Delete - - - - - &Copy - - - - - Ctrl+C - - - - - &Cut - - - - - Ctrl+X - - - - - - &Paste - - - - - - Ctrl+V - - - - - D&uplicate - - - - - Ctrl+U - - - - - Move to Category - - - - - &Use as default - - - - - P&rint model - - - - - Ctrl+P - - - - - &Simulate model - - - - + Alt+S - - &Add model - - - - - &Rename category - - - - - &Delete category - - - - - &Add category - - - - + Models and settings will be automatically converted. If that is not what you intended, please close the file and choose the correct radio type/profile before reopening it. + + + Delete %n selected model(s)? + + Delete %n selected model? + Delete %n selected models? + + - + + Edit Radio Settings + + + + + Alt+Shift+E + + + + + Copy Radio Settings + + + + + Ctrl+Alt+C + + + + + Paste Radio Settings + + + + + Ctrl+Alt+V + + + + + Simulate Radio + + + + + Alt+Shift+S + + + + + Alt+C + + + + + Alt+R + + + + + Alt+A + + + + + Alt+W + + + + + Duplicate Model + + + + + Alt+U + + + + + Print Model + + + + + + Model + + + + + Cannot insert model, last model in list would be deleted. + + + + + Cannot paste model, out of available model slots. + + + + + You are replacing an existing model, are you sure? + + + + Do you want to overwrite radio general settings? - - You are pasting on an not empty model, are you sure? - - - - + free bytes - - + + New category + Translators do NOT use accent for this, this is the default category name on Horus. + + + + Companion - + This category is not empty! - + New model - + + Cannot add model, could not find an available model slot. + + + + + Cut + + + + + Copy + + + + + Paste + + + + + Insert + + + + + Rename Category + + + + + %n Model(s) + As in "Copy 3 Models" or "Cut 1 Model" or "Delete 3 Models" action). + + %n Model + %n Models + + + + + %n Model(s) + As in "Paste 3 Models" or "Insert 1 Model." + + %n Model + %n Models + + + + + %n Category(ies) + As in "Delete 3 Categories" or "Delete 1 Category." + + %n Category + %n Categories + + + + + Nothing selected + + + + + empty model slot + + + + + Edit Model + + + + + Delete + + + + + Add Category + + + + + + Category + + + + + Add Model + + + + + Restore from Backup + + + + + Model Wizard + + + + + Set as Default + + + + + Simulate Model + + + + + Move to Category + + + + + Radio + + + + + Category index out of range. + + + + + Cannot delete the last category. + + + + + Delete %n selected category(ies)? + + Delete %n selected category? + Delete %n selected categories? + + + + + Cannot duplicate model, could not find an available model slot. + + + + Editing model %1: - - - - - - - + + + + + + + Error - - - - + + + + Save As - + %1 has been modified. Do you want to save your changes? - + Unable to find Horus radio SD card! - + Models and Settings written - + Cannot write temporary file! - + Open backup Models and Settings file - + Unable to find file %1! - + Error opening file %1: %2. - + Error reading file %1: %2. - + Invalid binary backup File %1 - + Warning @@ -5152,52 +5254,52 @@ If blank then the mix is considered to be "ON" all the time. - + Setup - + Heli - + Flight Modes - + Inputs - + Mixes - + Outputs - + Curves - + Logical Switches - + Special Functions - + Telemetry @@ -5539,14 +5641,6 @@ If blank then the mix is considered to be "ON" all the time. - - ModelsListWidget - - - No free slot available, cannot duplicate - - - Module @@ -5794,256 +5888,256 @@ If blank then the mix is considered to be "ON" all the time. MultiModelPrinter - + General Model Settings - + Name: - + EEprom Size: - + Timer%1: - + Module%1: - + Module: - + Trainer port: - + Throttle Trim: - + Trim Increment: - + Center Beep: - + Helicopter Setup - + Swash Type: - + Swash Ring: - + Input - + Weight - + Long. cyc - + Lateral cyc - + Collective - + Flight modes - - + + Flight mode - + Switch - + Fade IN - + Fade OUT - - + + FM%1 - - + + GV%1 - + RE%1 - + Limits - + Channel - + Name - - + + Offset - + Min - + Max - + Invert - + Global Variables - + Inputs - + Mixers - + CV%1 - + Curves - + L%1 - + Logical Switches - + SF%1 - + Special Functions - + Telemetry Settings - + Analogs - + Unit - + Scale - + A%1 - + RSSI Alarms - + Low Alarm - + Critical Alarm @@ -6062,7 +6156,7 @@ If blank then the mix is considered to be "ON" all the time. - C2500 frequency fine tune + CC2500 frequency fine tune @@ -6094,22 +6188,22 @@ If blank then the mix is considered to be "ON" all the time. MultirotorPage - + Throttle Channel: - + Yaw Channel: - + Pitch Channel: - + Roll Channel: @@ -6117,17 +6211,17 @@ If blank then the mix is considered to be "ON" all the time. OptionsPage - + Throttle Cut - + Throttle Timer - + Flight Timer @@ -6225,7 +6319,7 @@ If blank then the mix is considered to be "ON" all the time. - + Unknown @@ -6269,7 +6363,7 @@ If blank then the mix is considered to be "ON" all the time. - + V @@ -6399,7 +6493,7 @@ If blank then the mix is considered to be "ON" all the time. - + s @@ -6426,14 +6520,14 @@ If blank then the mix is considered to be "ON" all the time. - + REa - + REb @@ -6482,21 +6576,21 @@ If blank then the mix is considered to be "ON" all the time. - + Timer1 - + Timer2 - + Timer3 @@ -6738,7 +6832,7 @@ If blank then the mix is considered to be "ON" all the time. - + ---- @@ -6886,14 +6980,14 @@ If blank then the mix is considered to be "ON" all the time. - + OFF - + ON @@ -6914,351 +7008,352 @@ If blank then the mix is considered to be "ON" all the time. - + One - + + ??? - + Diff(%1) - + Expo(%1) - + Function(%1) - + Curve(%1) - + !Curve(%1) - + --- - + a>x - + a<x - + |a|>x - + |a|<x - + AND - + OR - + XOR - + a=b - + a!=b - + a>b - + a<b - + a>=b - + a<=b - + d>=x - + |d|>=x - + a=x - + a~x - + Timer - + Sticky - + Edge - + Override %1 - + Trainer - + Trainer RUD - + Trainer ELE - + Trainer THR - + Trainer AIL - + Instant Trim - + Play Sound - + Haptic - + Reset - + Set Timer %1 - + Vario - + Play Track - + Play Both - + Play Value - + Play Script - + SD Logs - + Volume - + Backlight - + Screenshot - + Background Music - + Background Music Pause - + Adjust GV%1 - + SetFailsafe Int. Module - + SetFailsafe Ext. Module - + RangeCheck Int. Module - + RangeCheck Ext. Module - + Bind Int. Module - + Bind Ext. Module - + Flight - + Telemetry - + Rotary Encoder - - - + + + <font color=red><b>Inconsistent parameter</b></font> - + Value - + Decr: - + Incr: - + played once, not during startup - + repeat(%1s) - + DISABLED - + INV - + NOR @@ -8252,6 +8347,7 @@ If blank then the mix is considered to be "ON" all the time. + Warning @@ -8262,6 +8358,7 @@ If blank then the mix is considered to be "ON" all the time. + Uknown error during Simulator startup. @@ -8273,18 +8370,18 @@ If blank then the mix is considered to be "ON" all the time. - + Data Load Error - + Error occurred while starting simulator. - - + + @@ -8292,12 +8389,12 @@ If blank then the mix is considered to be "ON" all the time. - + No SD directory configured! - + No Radio connected! @@ -8372,7 +8469,7 @@ If blank then the mix is considered to be "ON" all the time. - + Models Translators do NOT use accent for this, this is the default category name on Horus. @@ -8405,12 +8502,12 @@ If blank then the mix is considered to be "ON" all the time. - + Positive - + Negative @@ -8442,77 +8539,89 @@ If blank then the mix is considered to be "ON" all the time. - + Select a data file - + Select Data Directory - + Select SD Card Image Folder + Available profiles: + ID: + Name: + Available radios: + WARNING: couldn't initialize SDL: %1 + ERROR: No simulator libraries available. + Radio profile ID or Name to use for simulator. + Radio type to simulate (usually defined in profile). + show this help text + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] + Options: + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. Profile ID: [%1]; Radio ID: [%2]; @@ -8520,6 +8629,7 @@ Data File: [%3] + ERROR: Radio profile or simulator firmware not found. Profile ID: [%1]; Radio ID: [%2] @@ -8804,7 +8914,12 @@ The OpenTX Team. RadioKnobWidget - + + <p>Value (input): <b>%1</b></p> + + + + Right-double-click to reset to center. @@ -8936,17 +9051,17 @@ s RudderPage - + No No - + Yes - + <br>Rudder Channel: @@ -9128,7 +9243,7 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi SimpleTailPage - + Elevator Channel: @@ -9136,419 +9251,205 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi SimulatedUIWidget - - Rotary encoder click - - - - - Take Screenshot - - - - + + screenshot Simulator LCD screenshot file name prefix + + + ENTER + + + + + PG-UP + + + + + PG-DN + + + + + DEL + + + + + BKSP + + + + + ESC + + + + + INS + + + + + <font size=+3>+</font> + + + + + <font size=+3>-</font> + + + + + <font size=+3>&larr;</font> + + + + + <font size=+3>&rarr;</font> + + + + + <font size=+3>&uarr;</font> + + + + + <font size=+3>&darr;</font> + + + + + <font size=+3>&#x2686;</font> + + + + + <font size=+3>&#x21b6;</font> + + + + + <font size=+3>&#x21b7;</font> + + + + + <font size=+3>&#x21c6;</font> + + + + + + <font size=+3>&#x21d3;</font> + + + + + <font size=+3>&#x21d1;</font> + + + + + <font size=+3>&#x21d5;</font> + + + + + <img src='qrc:/images/simulator/icons/svg/mouse.svg' width=20 height=18 /> + + + + + <img src='qrc:/images/simulator/icons/svg/arrow_click.svg' width=18 height=18 /> + + + + + <pre>[ MENU ]</pre> + + + + + <pre>[ PAGE ]</pre> + + + + + <pre>[ EXIT ]</pre> + + + + + <pre>[ ENT ]</pre> + + + + + <pre>[ UP ]</pre> + + + + + <pre>[ DN ]</pre> + + + + + <pre>[ <font size=+2>+</font> ]</pre> + + + + + <pre>[ <font size=+2>-</font> ]</pre> + + + + + <pre>[ PgUp ]</pre> + + + + + <pre>[ PgDn ]</pre> + + + + + <pre>[ MDL ]</pre> + + + + + <pre>[ RTN ]</pre> + + + + + <pre>[ SYS ]</pre> + + + + + <pre>[ TELE ]</pre> + + + + + <font size=+3>&#x2261;</font> + + SimulatedUIWidget9X - - UP/PG-UP - - - - - [ UP ] - - - - - DN/PG-DN - - - - - [ DN ] - - - - - RIGHT/+ - - - - - [ + ] - - - - - LEFT/- - - - - - [ - ] - - - - - ENTER/MOUSE-MID - - - - - [ MENU ] - - - - - DEL/BKSP/ESC - - - - - [ EXIT ] - - - - - WHEEL/PAD SCRL - - - - - [ UP ]/[ DN ] or Rotary Sel. - - - - - SimulatedUIWidgetX12 - - - PG-UP - - - - - [ PgUp ] - - - - - PG-DN - - - - - [ PgDn ] - - - - - UP - - - - - [ MDL ] - - - - - DN/DEL/BKSP - - - - - [ RTN ] - - - - - LEFT - - - - - [ SYS ] - - - - - RIGHT - - - - - [ TELE ] - - - - - WHEEL/PAD SCRL - - - - - Rotary Selector - - - - - -/X - - - - - Rotary UP - - - - - +/C - - - - - Rotary DOWN - - - - - ENTER/MOUSE-MID - - - - - Selector Press - - - - - SimulatedUIWidgetX7 - - - Taranis X7 Simulator - - - - - PG-UP - - - - - [ PAGE ] - - - - - PG-DN - - - - - [ MENU ] - - - - - DEL/BKSP/ESC - - - - - [ EXIT ] - - - - - WHEEL/PAD SCRL - - - - - Rotary Selector - - - - - -/UP - - - - - Rotary UP - - - - - +/DN - - - - - Rotary DOWN - - - - - ENTER/MOUSE-MID - - - - - Selector Press - - - - - SimulatedUIWidgetX9 - - - PG-UP - - - - - [ MENU ] - - - - - PG-DN - - - - - [ PAGE ] - - - - - DEL/BKSP/ESC - - - - - [ EXIT ] - - - - - +/UP - - - - - [ + ] - - - - - -/DN - - - - - [ - ] - - - - - ENTER/MOUSE-MID - - - - - [ ENT ] - - - - - WHEEL/PAD SCRL - - - - - [ + ]/[ - ] - - - - - SimulatedUIWidgetX9E - - - PG-UP - - - - - [ MENU ] - - - - - PG-DN - - - - - [ PAGE ] - - - - - DEL/BKSP/ESC - - - - - [ EXIT ] - - - - - WHEEL/PAD SCRL - - - - - Rotary Selector - - - - - -/UP - - - - - Rotary UP - - - - - +/DN - - - - - Rotary DOWN - - - - - ENTER/MOUSE-MID - - - - - Selector Press + + + | @@ -9705,67 +9606,88 @@ If this is checked the throttle will be reversed. Idle will be forward, trim wi + ERROR: Failed to create simulator interface, possibly missing or bad library. - + + Alt+T - + + Radio Outputs - + + F2 - + + Telemetry Simulator - + + F4 - + + Trainer Simulator - + + F5 - + + Debug Output - + + F6 - - Simulator Controls: + + + <b>Simulator Controls:</b> - - <tr><th>Key/Mouse</td><th>Action</td></tr> + + + <tr><th>Key/Mouse</th><th>Action</th></tr> + note: must match html layout of each table row (keyTemplate). - + + + <tr><td><kbd>%1</kbd></td><td>%2</td></tr> + note: must match html layout of help text table header. + + + + + Simulator Help @@ -9885,7 +9807,7 @@ The default is configured in the chosen Radio Profile. - + All files (*.*) @@ -9898,78 +9820,102 @@ The default is configured in the chosen Radio Profile. - + + Radio Simulator (%1) - + + Could not determine startup data source. - + + Could not load data, possibly wrong format. - + + Data Load Error - + + Invalid startup data provided. Plese specify a proper file/path. - + + Simulator Startup Error - + + Error saving data: could open file for writing: '%1' - + + Error saving data: could not get data from simulator interface. - + + An unexpected error occurred while attempting to save radio data to file '%1'. - + + Data Save Error - + + Warning - + + Cannot open joystick, joystick disabled - - Firmware %1 error: %2 + + + Radio firmware error: %1 + + + + + + - Flight Mode %1 (#%2) SliderWidget - + Right-double-click to reset to center. + + + <p>Value (input): <b>%1</b></p> + + SplashLibraryDialog @@ -10040,17 +9986,17 @@ The default is configured in the chosen Radio Profile. TailPage - + Rudder Channel: - + Elevator Channel: - + Only one channel still available!<br>You probably should configure your model without using the wizard. @@ -10058,22 +10004,22 @@ The default is configured in the chosen Radio Profile. TailSelectionPage - + Elevator and Rudder - + Only Elevator - + V-tail - + Tail Type: @@ -11131,17 +11077,20 @@ hh:mm:ss - + + Log File - + + LOG Files (*.csv) - + + ERROR - invalid file @@ -11366,17 +11315,17 @@ hh:mm:ss ThrottlePage - + Yes - + No No - + <br>Throttle Channel: @@ -11560,17 +11509,17 @@ hh:mm:ss TreeModel - + Index - + Name - + Size @@ -11578,12 +11527,12 @@ hh:mm:ss VTailPage - + First Tail Channel: - + Second Tail Channel: @@ -11591,42 +11540,50 @@ hh:mm:ss VirtualJoystickWidget - + + Hld Y - + + Hold Vertical stick position. - + + Fix Y - + + Prevent Vertical movement of stick. - + + Fix X - + + Prevent Horizontal movement of stick. - + + Hld X - + + Hold Horizontal stick position. @@ -11634,12 +11591,12 @@ hh:mm:ss WingtypeSelectionPage - + Standard Wing - + Flying Wing / Deltawing @@ -11921,37 +11878,37 @@ hh:mm:ss WizardPrinter - + Plane - + Multicopter - + Helicopter - + Model Name: - + Model Type: - + Options: - + Channel %1: diff --git a/companion/src/wizarddata.cpp b/companion/src/wizarddata.cpp index 1fc337a02..9e9d2c2ec 100644 --- a/companion/src/wizarddata.cpp +++ b/companion/src/wizarddata.cpp @@ -44,7 +44,7 @@ WizMix::WizMix(const GeneralSettings & settings, unsigned int modelId, const Mod originalModelData(modelData), vehicle(NOVEHICLE) { - strcpy(name, " "); + strncpy(name, originalModelData.name, WIZ_MODEL_NAME_LENGTH); } diff --git a/companion/src/wizarddialog.cpp b/companion/src/wizarddialog.cpp index 9d83e97d1..e681cfc6e 100644 --- a/companion/src/wizarddialog.cpp +++ b/companion/src/wizarddialog.cpp @@ -295,6 +295,11 @@ ModelSelectionPage::ModelSelectionPage(WizardDialog *dlg, QString image, QString l->addWidget(helicopterRB); } +void ModelSelectionPage::initializePage() +{ + nameLineEdit->setText(wizDlg->mix.name); +} + bool ModelSelectionPage::validatePage() { //Filter and insert model name in mix data diff --git a/companion/src/wizarddialog.h b/companion/src/wizarddialog.h index 7f6988033..32a7c4b49 100644 --- a/companion/src/wizarddialog.h +++ b/companion/src/wizarddialog.h @@ -73,6 +73,7 @@ private: QRadioButton *planeRB; QRadioButton *multirotorRB; QRadioButton *helicopterRB; + void initializePage(); bool validatePage(); int nextId() const; }; From df0e306458f1cd41936eaf35f4360117a29bb9f1 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Tue, 11 Apr 2017 07:48:23 +0200 Subject: [PATCH 107/203] Update DONATIONS.txt --- DONATIONS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index dca7fa5aa..07e3c6c44 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1152,3 +1152,4 @@ Jonathan Pruett Charles Nowell Randy Melton Jo Jung +Chris Monk From 7779bc51cd29721f4cbd7b48b36645d8b9efcccc Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Tue, 11 Apr 2017 07:50:02 +0200 Subject: [PATCH 108/203] Remove unused pointer startP (#4770) Clang complains about startP pointer pointing to a member of a packed structure, resulting on in a unaligned pointered address. The compiler will optimise the pointer out anyway --- radio/src/storage/eeprom_rlc.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/radio/src/storage/eeprom_rlc.cpp b/radio/src/storage/eeprom_rlc.cpp index 7d3b3929a..28898fb43 100644 --- a/radio/src/storage/eeprom_rlc.cpp +++ b/radio/src/storage/eeprom_rlc.cpp @@ -137,9 +137,8 @@ void eepromCheck() #if defined(CPUARM) blocksCount = 0; #endif - blkid_t *startP = (i==MAXFILES ? &eeFs.freeList : &eeFs.files[i].startBlk); + blkid_t blk = (i==MAXFILES ? eeFs.freeList : eeFs.files[i].startBlk); blkid_t lastBlk = 0; - blk = *startP; while (blk) { if (blk < FIRSTBLK || // bad blk index blk >= BLOCKS || // bad blk indexchan @@ -149,7 +148,6 @@ void eepromCheck() EeFsSetLink(lastBlk, 0); } else { - *startP = 0; // interrupt chain at startpos EeFsFlush(); } blk = 0; // abort From 95b31ee1471a9bae8a4640238047668174c42d98 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Tue, 11 Apr 2017 07:52:50 +0200 Subject: [PATCH 109/203] Update DONATIONS.txt --- DONATIONS.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index 07e3c6c44..3f63760e6 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1153,3 +1153,5 @@ Charles Nowell Randy Melton Jo Jung Chris Monk +Alvin Burke +Georges d'Haussy From de3c503e02eb232eeb1bc514c883fc8c430c7aaa Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Tue, 11 Apr 2017 12:06:16 -0400 Subject: [PATCH 110/203] [Companion] Fix startup switch warnings wraparound issue with X9E SQ-SR switches (closes #3359). --- companion/src/modeledit/setup.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/companion/src/modeledit/setup.cpp b/companion/src/modeledit/setup.cpp index b24a9d3a4..ec27a331f 100644 --- a/companion/src/modeledit/setup.cpp +++ b/companion/src/modeledit/setup.cpp @@ -1161,7 +1161,7 @@ void SetupPanel::updateStartupSwitches() int index = slider->property("index").toInt(); bool enabled = !(model->switchWarningEnable & (1 << index)); if (IS_HORUS_OR_TARANIS(firmware->getBoard())) { - value = (switchStates >> 2*index) & 0x03; + value = (switchStates >> (2*index)) & 0x03; if (generalSettings.switchConfig[index] != Board::SWITCH_3POS && value == 2) { value = 1; } @@ -1187,7 +1187,7 @@ void SetupPanel::startupSwitchEdited(int value) if (IS_HORUS_OR_TARANIS(firmware->getBoard())) { shift = index * 2; - mask = 0x03ul << shift; + mask = 0x03ull << shift; } else { if (index == 0) { From 350c3a6d44dfe94ba6eda731af2f57bb3d676899 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Tue, 11 Apr 2017 16:08:53 -0400 Subject: [PATCH 111/203] [Companion] Do not run model wizard on a duplicated/copied model (fixes #4773); Replace existing file extension with .otx when first saving a converted bin/hex/eepe file (fixes #4772); Make sure no other models exist before setting first model as default (fix index 0 always being auto-selected). --- companion/src/mdichild.cpp | 66 ++++++++++++++++++------------------ companion/src/mdichild.h | 1 + companion/src/modelslist.cpp | 2 +- 3 files changed, 35 insertions(+), 34 deletions(-) diff --git a/companion/src/mdichild.cpp b/companion/src/mdichild.cpp index 65cb37039..0561e6d42 100644 --- a/companion/src/mdichild.cpp +++ b/companion/src/mdichild.cpp @@ -742,24 +742,21 @@ bool MdiChild::deleteCategory(int categoryIndex, QString * error) *error = tr("Cannot delete the last category."); return false; } - - QVector modelsToMove; - for (unsigned i=0; i < radioData.models.size(); i++) { - ModelData & model = radioData.models[i]; - if (model.used && model.category == categoryIndex) { - if (error) - *error = tr("This category is not empty!"); - return false; - } - else if (model.used && model.category > categoryIndex) { - modelsToMove.append(i); - } + if (countUsedModels(categoryIndex)) { + if (error) + *error = tr("This category is not empty!"); + return false; } radioData.categories.erase(radioData.categories.begin() + categoryIndex); - foreach (const int i, modelsToMove) { - --radioData.models[i].category; + + for (unsigned i=0; i < radioData.models.size(); ++i) { + ModelData & model = radioData.models.at(i); + if (model.used && model.category > categoryIndex) { + --radioData.models[i].category; + } } + return true; } @@ -865,14 +862,13 @@ int MdiChild::newModel(int modelIndex, int categoryIndex) if (modelIndex < 0) modelIndex = modelAppend(ModelData()); - if (modelIndex < 0) { + if (modelIndex < 0 || modelIndex >= (int)radioData.models.size()) { showWarning(tr("Cannot add model, could not find an available model slot.")); - return modelIndex; + return -1; } if (categoryIndex < 0) categoryIndex = modelsListModel->getCategoryIndex(getCurrentIndex()); - //qDebug() << modelIndex << categoryIndex; bool isNewModel = radioData.models[modelIndex].isEmpty(); checkAndInitModel(modelIndex); @@ -882,13 +878,14 @@ int MdiChild::newModel(int modelIndex, int categoryIndex) strcpy(radioData.models[modelIndex].name, qPrintable(tr("New model"))); // TODO: Why not just use existing default model name? } // Only set the default model if we just added the first one. - if (modelIndex == 0) { + if (countUsedModels() == 1) { radioData.setCurrentModel(modelIndex); } setModified(); setSelectedModel(modelIndex); + //qDebug() << modelIndex << categoryIndex << isNewModel; - if (g.newModelAction() == 1) + if (isNewModel && g.newModelAction() == 1) openModelWizard(modelIndex); else if (g.newModelAction() == 2) openModelEditWindow(modelIndex); @@ -971,6 +968,17 @@ void MdiChild::moveSelectedModelsToCat(const int toCategoryId) moveModelsToCategory(getSelectedModels(), toCategoryId); } +unsigned MdiChild::countUsedModels(const int categoryId) +{ + unsigned count = 0; + for (unsigned i=0; i < radioData.models.size(); ++i) { + ModelData & model = radioData.models.at(i); + if (!model.isEmpty() && (categoryId < 0 || model.category == categoryId)) + ++count; + } + return count; +} + void MdiChild::pasteModelData(const QMimeData * mimeData, const QModelIndex row, bool insert, bool move) { QVector modelsList; @@ -1343,23 +1351,15 @@ bool MdiChild::save() bool MdiChild::saveAs(bool isNew) { QString fileName; - if (IS_SKY9X(getCurrentBoard())) { - curFile.replace(".eepe", ".bin"); - QFileInfo fi(curFile); + curFile.replace(QRegExp("\\.(eepe|bin|hex)$"), ".otx"); + QFileInfo fi(curFile); #ifdef __APPLE__ - fileName = QFileDialog::getSaveFileName(this, tr("Save As"), g.eepromDir() + "/" +fi.fileName()); + QString filter; #else - fileName = QFileDialog::getSaveFileName(this, tr("Save As"), g.eepromDir() + "/" +fi.fileName(), tr(BIN_FILES_FILTER)); + QString filter(OTX_FILES_FILTER); #endif - } - else { - QFileInfo fi(curFile); -#ifdef __APPLE__ - fileName = QFileDialog::getSaveFileName(this, tr("Save As"), g.eepromDir() + "/" +fi.fileName()); -#else - fileName = QFileDialog::getSaveFileName(this, tr("Save As"), g.eepromDir() + "/" +fi.fileName(), tr(OTX_FILES_FILTER)); -#endif - } + + fileName = QFileDialog::getSaveFileName(this, tr("Save As"), g.eepromDir() + "/" +fi.fileName(), filter); if (fileName.isEmpty()) return false; g.eepromDir( QFileInfo(fileName).dir().absolutePath() ); diff --git a/companion/src/mdichild.h b/companion/src/mdichild.h index 2aa20ae1f..80c389897 100644 --- a/companion/src/mdichild.h +++ b/companion/src/mdichild.h @@ -170,6 +170,7 @@ class MdiChild : public QWidget void deleteSelectedModels(); void moveModelsToCategory(const QVector models, const int toCategoryId); void moveSelectedModelsToCat(const int toCategoryId); + unsigned countUsedModels(const int categoryId = -1); void clearCutList(); void removeModelFromCutList(const int modelIndex); diff --git a/companion/src/modelslist.cpp b/companion/src/modelslist.cpp index 98ef3dbeb..be5957878 100644 --- a/companion/src/modelslist.cpp +++ b/companion/src/modelslist.cpp @@ -177,7 +177,7 @@ QVariant TreeModel::data(const QModelIndex & index, int role) const return item->data(index.column()); } - if (role == Qt::FontRole && item->getModelIndex() == (int)radioData->generalSettings.currModelIndex) { + if (role == Qt::FontRole && item->isModel() && item->getModelIndex() == (int)radioData->generalSettings.currModelIndex) { QFont font; font.setBold(true); return font; From c2ef10724d30f896531859f6fae9954078b64c9b Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Tue, 11 Apr 2017 19:11:31 -0400 Subject: [PATCH 112/203] [Simulator] Fix data not being saved back to file in standalone simulator when using .otx file with non-Horus radio types. --- companion/src/simulation/simulatorwidget.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/companion/src/simulation/simulatorwidget.cpp b/companion/src/simulation/simulatorwidget.cpp index c687c2226..00a481028 100644 --- a/companion/src/simulation/simulatorwidget.cpp +++ b/companion/src/simulation/simulatorwidget.cpp @@ -118,13 +118,11 @@ SimulatorWidget::SimulatorWidget(QWidget * parent, SimulatorInterface * simulato connect(this, &SimulatorWidget::simulatorInit, simulator, &SimulatorInterface::init); connect(this, &SimulatorWidget::simulatorStart, simulator, &SimulatorInterface::start); connect(this, &SimulatorWidget::simulatorStop, simulator, &SimulatorInterface::stop); - //connect(this, &SimulatorWidget::simulatorSetData, simulator, &SimulatorInterface::setRadioData); connect(this, &SimulatorWidget::inputValueChange, simulator, &SimulatorInterface::setInputValue); connect(this, &SimulatorWidget::simulatorSdPathChange, simulator, &SimulatorInterface::setSdPath); connect(this, &SimulatorWidget::simulatorVolumeGainChange, simulator, &SimulatorInterface::setVolumeGain); connect(simulator, &SimulatorInterface::started, this, &SimulatorWidget::onSimulatorStarted); - connect(simulator, &SimulatorInterface::stopped, this, &SimulatorWidget::onSimulatorStopped); connect(simulator, &SimulatorInterface::heartbeat, this, &SimulatorWidget::onSimulatorHeartbeat); connect(simulator, &SimulatorInterface::runtimeError, this, &SimulatorWidget::onSimulatorError); connect(simulator, &SimulatorInterface::phaseChanged, this, &SimulatorWidget::onPhaseChanged); @@ -467,10 +465,11 @@ void SimulatorWidget::stop() while (simulator->isRunning()) { if (tmout.hasExpired(2000)) { onSimulatorError("Timeout while trying to stop simulation!"); - onSimulatorStopped(); - return; + break; } + QApplication::processEvents(); } + onSimulatorStopped(); } void SimulatorWidget::onSimulatorStarted() From 077a651dc315c43254cfff78a4d085181c49652e Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Tue, 11 Apr 2017 21:20:47 -0400 Subject: [PATCH 113/203] [Simulator] Fix intermittent crc errors with telemetry simulator. --- companion/src/simulation/simulatorinterface.h | 2 +- companion/src/simulation/telemetrysimu.cpp | 15 ++++++++------- companion/src/simulation/telemetrysimu.h | 2 +- radio/src/targets/simu/opentxsimulator.cpp | 6 +++--- radio/src/targets/simu/opentxsimulator.h | 2 +- 5 files changed, 14 insertions(+), 13 deletions(-) diff --git a/companion/src/simulation/simulatorinterface.h b/companion/src/simulation/simulatorinterface.h index bfb35d98b..6be9040ad 100644 --- a/companion/src/simulation/simulatorinterface.h +++ b/companion/src/simulation/simulatorinterface.h @@ -141,7 +141,7 @@ class SimulatorInterface : public QObject virtual void setInputValue(int type, uint8_t index, int16_t value) = 0; virtual void rotaryEncoderEvent(int steps) = 0; virtual void setTrainerTimeout(uint16_t ms) = 0; - virtual void sendTelemetry(uint8_t * data, unsigned int len) = 0; + virtual void sendTelemetry(const QByteArray data) = 0; virtual void setLuaStateReloadPermanentScripts() = 0; virtual void addTracebackDevice(QIODevice * device) = 0; virtual void removeTracebackDevice(QIODevice * device) = 0; diff --git a/companion/src/simulation/telemetrysimu.cpp b/companion/src/simulation/telemetrysimu.cpp index 28e330a72..3f2594286 100644 --- a/companion/src/simulation/telemetrysimu.cpp +++ b/companion/src/simulation/telemetrysimu.cpp @@ -227,7 +227,6 @@ void setSportPacketCrc(uint8_t * packet) crc &= 0x00ff; } packet[FRSKY_SPORT_PACKET_SIZE-1] = 0xFF - (crc & 0x00ff); - //TRACE("crc set: %x", packet[FRSKY_SPORT_PACKET_SIZE-1]); } uint8_t getBit(uint8_t position, uint8_t value) @@ -257,15 +256,13 @@ void TelemetrySimulator::generateTelemetryFrame() { static int item = 0; bool ok = true; - uint8_t buffer[FRSKY_SPORT_PACKET_SIZE]; + uint8_t buffer[FRSKY_SPORT_PACKET_SIZE] = {0}; static FlvssEmulator *flvss = new FlvssEmulator(); static GPSEmulator *gps = new GPSEmulator(); if (!m_simuStarted) return; - memset(buffer, 0, sizeof(buffer)); - switch (item++) { case 0: #if defined(XJT_VERSION_ID) @@ -431,10 +428,14 @@ void TelemetrySimulator::generateTelemetryFrame() return; } - if (ok && (buffer[2] || buffer[3])) - emit telemetryDataChanged(buffer, FRSKY_SPORT_PACKET_SIZE); - else + if (ok && (buffer[2] || buffer[3])) { + QByteArray ba((char *)buffer, FRSKY_SPORT_PACKET_SIZE); + emit telemetryDataChanged(ba); + //qDebug("%02X %02X %02X %02X %02X %02X %02X %02X %02X", buffer[0], buffer[1], buffer[2], buffer[3], buffer[4], buffer[5], buffer[6], buffer[7], buffer[8]); + } + else { generateTelemetryFrame(); + } } uint32_t TelemetrySimulator::FlvssEmulator::encodeCellPair(uint8_t cellNum, uint8_t firstCellNo, double cell1, double cell2) diff --git a/companion/src/simulation/telemetrysimu.h b/companion/src/simulation/telemetrysimu.h index 23fc8948c..08bdd9fa0 100644 --- a/companion/src/simulation/telemetrysimu.h +++ b/companion/src/simulation/telemetrysimu.h @@ -48,7 +48,7 @@ class TelemetrySimulator : public QWidget signals: - void telemetryDataChanged(uint8_t * data, unsigned int len); + void telemetryDataChanged(const QByteArray data); protected slots: diff --git a/radio/src/targets/simu/opentxsimulator.cpp b/radio/src/targets/simu/opentxsimulator.cpp index a07a02955..e7260e39c 100644 --- a/radio/src/targets/simu/opentxsimulator.cpp +++ b/radio/src/targets/simu/opentxsimulator.cpp @@ -305,11 +305,11 @@ void OpenTxSimulator::setTrainerTimeout(uint16_t ms) ppmInputValidityTimer = ms; } -void OpenTxSimulator::sendTelemetry(uint8_t * data, unsigned int len) +void OpenTxSimulator::sendTelemetry(const QByteArray data) { - Q_UNUSED(len) #if defined(TELEMETRY_FRSKY_SPORT) - sportProcessTelemetryPacket(data); + //OTXS_DBG << data; + sportProcessTelemetryPacket((uint8_t *)data.constData()); #else Q_UNUSED(data) #endif diff --git a/radio/src/targets/simu/opentxsimulator.h b/radio/src/targets/simu/opentxsimulator.h index d3ba6689a..e38f2bdfb 100644 --- a/radio/src/targets/simu/opentxsimulator.h +++ b/radio/src/targets/simu/opentxsimulator.h @@ -65,7 +65,7 @@ class DLLEXPORT OpenTxSimulator : public SimulatorInterface virtual void setInputValue(int type, uint8_t index, int16_t value); virtual void rotaryEncoderEvent(int steps); virtual void setTrainerTimeout(uint16_t ms); - virtual void sendTelemetry(uint8_t * data, unsigned int len); + virtual void sendTelemetry(const QByteArray data); virtual void setLuaStateReloadPermanentScripts(); virtual void addTracebackDevice(QIODevice * device); virtual void removeTracebackDevice(QIODevice * device); From 924ecced98c93e4c7cfe1c81fc533ccf8254fa1d Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Tue, 11 Apr 2017 22:53:07 -0400 Subject: [PATCH 114/203] [Companion] Fix issue with category edit and dbl-click not working after category name edit; Add translator warnings on default model names; Remove redundant variable and consolidate filename change routines. --- companion/src/mdichild.cpp | 20 ++++++++------------ companion/src/mdichild.h | 3 +-- companion/src/modelslist.cpp | 12 ++++++++---- 3 files changed, 17 insertions(+), 18 deletions(-) diff --git a/companion/src/mdichild.cpp b/companion/src/mdichild.cpp index 0561e6d42..e9545888a 100644 --- a/companion/src/mdichild.cpp +++ b/companion/src/mdichild.cpp @@ -45,7 +45,6 @@ MdiChild::MdiChild(QWidget * parent, QWidget * parentWin, Qt::WindowFlags f): firmware(getCurrentFirmware()), lastSelectedModel(-1), isUntitled(true), - fileChanged(false), showCatToolbar(true), stateDataVersion(1) { @@ -566,6 +565,7 @@ void MdiChild::onItemActivated(const QModelIndex index) openModelEditWindow(mIdx); } else if (modelsListModel->isCategoryType(index)) { + ui->modelsList->setCurrentIndex(index); ui->modelsList->edit(index); } } @@ -591,6 +591,7 @@ void MdiChild::onDataChanged(const QModelIndex & index) } strcpy(radioData.categories[categoryIndex].name, modelsListModel->data(index, 0).toString().left(sizeof(CategoryData::name)-1).toStdString().c_str()); + ui->modelsList->setCurrentIndex(QModelIndex()); // must do this otherwise leaves QTreeView in limbo after TreeModel::refresh() (Qt undoc/bug?) setModified(); } @@ -692,7 +693,6 @@ void MdiChild::updateTitle() void MdiChild::setModified() { - fileChanged = true; refresh(); setWindowModified(true); emit modified(); @@ -875,6 +875,7 @@ int MdiChild::newModel(int modelIndex, int categoryIndex) if (isNewModel && firmware->getCapability(Capability::HasModelCategories) && categoryIndex > -1) { radioData.models[modelIndex].category = categoryIndex; strcpy(radioData.models[modelIndex].filename, radioData.getNextModelFilename().toStdString().c_str()); + /*: Translators: do NOT use accents here, this is a default model name. */ strcpy(radioData.models[modelIndex].name, qPrintable(tr("New model"))); // TODO: Why not just use existing default model name? } // Only set the default model if we just added the first one. @@ -1350,8 +1351,7 @@ bool MdiChild::save() bool MdiChild::saveAs(bool isNew) { - QString fileName; - curFile.replace(QRegExp("\\.(eepe|bin|hex)$"), ".otx"); + forceNewFilename(); QFileInfo fi(curFile); #ifdef __APPLE__ QString filter; @@ -1359,7 +1359,7 @@ bool MdiChild::saveAs(bool isNew) QString filter(OTX_FILES_FILTER); #endif - fileName = QFileDialog::getSaveFileName(this, tr("Save As"), g.eepromDir() + "/" +fi.fileName(), filter); + QString fileName = QFileDialog::getSaveFileName(this, tr("Save As"), g.eepromDir() + "/" +fi.fileName(), filter); if (fileName.isEmpty()) return false; g.eepromDir( QFileInfo(fileName).dir().absolutePath() ); @@ -1387,7 +1387,7 @@ bool MdiChild::saveFile(const QString & filename, bool setCurrent) bool MdiChild::maybeSave() { - if (fileChanged) { + if (isWindowModified()) { int ret = askQuestion(tr("%1 has been modified.\nDo you want to save your changes?").arg(userFriendlyCurrentFile()), QMessageBox::Save, QMessageBox::Discard, QMessageBox::Cancel | QMessageBox::Default); @@ -1413,7 +1413,6 @@ void MdiChild::setCurrentFile(const QString & fileName) { curFile = QFileInfo(fileName).canonicalFilePath(); isUntitled = false; - fileChanged = false; setWindowModified(false); updateTitle(); int MaxRecentFiles = g.historySize(); @@ -1427,18 +1426,15 @@ void MdiChild::setCurrentFile(const QString & fileName) void MdiChild::forceNewFilename(const QString & suffix, const QString & ext) { - QFileInfo info(curFile); - curFile = info.path() + "/" + info.baseName() + suffix + ext; + curFile.replace(QRegExp("\\.(eepe|bin|hex|otx)$"), suffix + "." + ext); } - void MdiChild::convertStorage(Board::Type from, Board::Type to) { showWarning(tr("Models and settings will be automatically converted.\nIf that is not what you intended, please close the file\nand choose the correct radio type/profile before reopening it.")); radioData.convert(from, to); - forceNewFilename("_converted", ".otx"); + forceNewFilename("_converted"); initModelsList(); - fileChanged = true; isUntitled = true; } diff --git a/companion/src/mdichild.h b/companion/src/mdichild.h index 80c389897..f9f062553 100644 --- a/companion/src/mdichild.h +++ b/companion/src/mdichild.h @@ -178,7 +178,7 @@ class MdiChild : public QWidget bool maybeSave(); void setCurrentFile(const QString & fileName); - void forceNewFilename(const QString & suffix, const QString & ext); + void forceNewFilename(const QString & suffix = "", const QString & ext = "otx"); void convertStorage(Board::Type from, Board::Type to); void showWarning(const QString & msg); int askQuestion(const QString & msg, int button0 = QMessageBox::Yes, int button1 = QMessageBox::No | QMessageBox::Default, int button2 = 0); @@ -199,7 +199,6 @@ class MdiChild : public QWidget int lastSelectedModel; bool isUntitled; - bool fileChanged; bool showCatToolbar; const quint16 stateDataVersion; }; diff --git a/companion/src/modelslist.cpp b/companion/src/modelslist.cpp index be5957878..32079bc22 100644 --- a/companion/src/modelslist.cpp +++ b/companion/src/modelslist.cpp @@ -192,7 +192,7 @@ QVariant TreeModel::data(const QModelIndex & index, int role) const Qt::ItemFlags TreeModel::flags(const QModelIndex &index) const { - Qt::ItemFlags f = QAbstractItemModel::flags(index); + Qt::ItemFlags f = Qt::ItemIsSelectable | Qt::ItemIsEnabled; if (index.isValid()) { if (getItem(index)->isCategory()) @@ -202,6 +202,7 @@ Qt::ItemFlags TreeModel::flags(const QModelIndex &index) const } f |= Qt::ItemIsDropEnabled; + //qDebug() << f; return f; } @@ -691,10 +692,13 @@ void TreeModel::refresh() if (!model.isEmpty() && current) { QString modelName; - if (strlen(model.name) > 0) + if (strlen(model.name) > 0) { modelName = model.name; - else - modelName = QString().sprintf("Model%02d", i+1); + } + else { + /*: Translators: do NOT use accents here, this is a default model name. */ + modelName = tr("Model %1").arg(uint(i+1), 2, 10, QChar('0')); + } current->setData(currentColumn++, modelName); if (hasEepromSizeData) { int size = eepromInterface->getSize(model); From 2808b85fcedafd95680a8a888265fbb126b811ed Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Wed, 12 Apr 2017 00:07:32 -0400 Subject: [PATCH 115/203] [Companion] Clean up some AppPreferencesDialog layout size policies and fix height shrinking when options change; Fixes issues on HiDPI displays. --- companion/src/apppreferencesdialog.cpp | 5 +- companion/src/apppreferencesdialog.ui | 314 +++++++++++++++++++------ 2 files changed, 249 insertions(+), 70 deletions(-) diff --git a/companion/src/apppreferencesdialog.cpp b/companion/src/apppreferencesdialog.cpp index 4f3b8fc24..c68d44332 100644 --- a/companion/src/apppreferencesdialog.cpp +++ b/companion/src/apppreferencesdialog.cpp @@ -383,7 +383,6 @@ void AppPreferencesDialog::showVoice(bool show) { ui->voiceLabel->setVisible(show); ui->voiceCombo->setVisible(show); - QTimer::singleShot(0, this, SLOT(shrink())); } void AppPreferencesDialog::baseFirmwareChanged() @@ -533,11 +532,11 @@ void AppPreferencesDialog::populateFirmwareOptions(const Firmware * firmware) } updateLock = false; - QTimer::singleShot(0, this, SLOT(shrink())); + QTimer::singleShot(50, this, SLOT(shrink())); } void AppPreferencesDialog::shrink() { - resize(0,0); + adjustSize(); } diff --git a/companion/src/apppreferencesdialog.ui b/companion/src/apppreferencesdialog.ui index 23ad622d0..9bd90b07d 100644 --- a/companion/src/apppreferencesdialog.ui +++ b/companion/src/apppreferencesdialog.ui @@ -6,26 +6,29 @@ 0 0 - 686 - 713 + 623 + 537 - + 0 0 - - - 685 - 0 - - Edit Settings + + true + + + true + + + 6 + @@ -38,6 +41,12 @@ + + + 0 + 0 + + 0 @@ -84,7 +93,7 @@ - + 0 0 @@ -120,7 +129,7 @@ - + 0 0 @@ -163,6 +172,12 @@ + + + 0 + 0 + + Qt::Horizontal @@ -173,6 +188,12 @@ + + + 0 + 0 + + 75 @@ -189,6 +210,12 @@ + + + 0 + 0 + + Qt::Horizontal @@ -197,7 +224,7 @@ - + 0 0 @@ -226,6 +253,12 @@ + + + 0 + 0 + + Menu Language @@ -252,7 +285,7 @@ - + 0 0 @@ -290,6 +323,12 @@ May be different from firmware language + + + 0 + 0 + + Build Options @@ -298,33 +337,23 @@ May be different from firmware language - - - + + + 0 + 0 + + Qt::Horizontal - - - - - 75 - true - - - - Other Settings - - - - + 0 0 @@ -352,6 +381,12 @@ May be different from firmware language + + + 0 + 0 + + The profile specific folder, if set, will override general Backup folder @@ -372,6 +407,12 @@ May be different from firmware language + + + 0 + 0 + + if set, will override general backup enable @@ -382,6 +423,12 @@ May be different from firmware language + + + 0 + 0 + + General Settings @@ -392,6 +439,12 @@ May be different from firmware language true + + + 0 + 0 + + General Settings Label @@ -400,7 +453,7 @@ May be different from firmware language - + 0 0 @@ -467,7 +520,7 @@ Mode 4: - + 0 0 @@ -483,23 +536,11 @@ Mode 4: - + 0 0 - - - 0 - 0 - - - - - 16777215 - 16777215 - - <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> @@ -630,6 +671,12 @@ Mode 4: + + + 0 + 0 + + Append version number to FW file name @@ -637,6 +684,12 @@ Mode 4: + + + 0 + 0 + + Offer to write FW to Tx after download @@ -650,11 +703,60 @@ Mode 4: 20 - 40 + 5 + + + + + 0 + 0 + + + + + 75 + true + + + + Other Settings + + + + + + + + 0 + 0 + + + + + 0 + + + 0 + + + 0 + + + 0 + + + 5 + + + 4 + + + + @@ -664,6 +766,12 @@ Mode 4: + + + 0 + 0 + + Automatic Backup Folder @@ -764,7 +872,7 @@ Mode 4: - + 0 0 @@ -800,6 +908,12 @@ Mode 4: + + + 0 + 0 + + Select Folder @@ -808,7 +922,7 @@ Mode 4: - + 0 0 @@ -820,6 +934,12 @@ Mode 4: + + + 0 + 0 + + Google Earth Executable @@ -833,13 +953,19 @@ Mode 4: 20 - 40 + 5 + + + 0 + 0 + + Enable automatic backup before writing firmware @@ -865,7 +991,7 @@ Mode 4: - + 0 0 @@ -900,6 +1026,12 @@ Mode 4: + + + 0 + 0 + + Select Executable @@ -907,6 +1039,12 @@ Mode 4: + + + 0 + 0 + + Select Folder @@ -915,7 +1053,7 @@ Mode 4: - + 0 0 @@ -925,7 +1063,17 @@ Mode 4: - + + + + <html><head/><body><p>This option maintains the behaviour from older OpenTx versions where empty model slots are preserved when a model is deleted or moved. </p><p>When this option is de-selected, the other models may be re-arranged to fill the gap left by the removed model.</p></body></html> + + + Remove empty model slots when deleting models (only applies for radios w/out categories) + + + + @@ -959,16 +1107,6 @@ Mode 4: - - - - <html><head/><body><p>This option maintains the behaviour from older OpenTx versions where empty model slots are preserved when a model is deleted or moved. </p><p>When this option is de-selected, the other models may be re-arranged to fill the gap left by the removed model.</p></body></html> - - - Remove empty model slots when deleting models (only applies for radios w/out categories) - - - @@ -976,14 +1114,20 @@ Mode 4: Simulator Settings + + 6 + - + 0 0 + + QComboBox::AdjustToContents + @@ -1030,6 +1174,12 @@ Mode 4: + + + 0 + 0 + + Simulator capture folder @@ -1043,13 +1193,19 @@ Mode 4: 20 - 40 + 5 + + + 0 + 0 + + Only capture to clipboard @@ -1057,6 +1213,12 @@ Mode 4: + + + 0 + 0 + + Enable @@ -1075,7 +1237,7 @@ Mode 4: - + 0 0 @@ -1088,7 +1250,7 @@ Mode 4: - + 0 0 @@ -1107,7 +1269,7 @@ Mode 4: true - + 0 0 @@ -1125,6 +1287,12 @@ Mode 4: + + + 0 + 0 + + Remember simulator switch values @@ -1132,6 +1300,12 @@ Mode 4: + + + 0 + 0 + + Simulator Volume Gain @@ -1139,6 +1313,12 @@ Mode 4: + + + 0 + 0 + + 50 From 37a21ffef696a2e003bd9da5254382a151462652 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Wed, 12 Apr 2017 09:06:11 +0200 Subject: [PATCH 116/203] Update DONATIONS.txt --- DONATIONS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index 3f63760e6..788aad4af 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1155,3 +1155,4 @@ Jo Jung Chris Monk Alvin Burke Georges d'Haussy +Philippe Lhomme From 0a6518eb3030d8814b87bb4ef68b3d44d96c965c Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Wed, 12 Apr 2017 09:50:17 +0200 Subject: [PATCH 117/203] Compilation fix for french firmware / AVR --- radio/src/translations/fr.h.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index 599c7781d..a91294ae9 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -344,7 +344,7 @@ #define LEN_FUNCSOUNDS TR("\004", "\006") #define TR_FUNCSOUNDS TR("Bp1\0""Bp2\0""Bp3\0""Wrn1""Wrn2""Chee""Rata""Tick""Sirn""Ring""SciF""Robt""Chrp""Tada""Crck""Alrm", "Beep1 ""Beep2 ""Beep3 ""Warn1 ""Warn2 ""Cheep ""Ratata""Tick ""Siren ""Ring ""SciFi ""Robot ""Chirp ""Tada ""Crickt""AlmClk") -#define LEN_VTELEMCHNS "\004" +#define LEN_VTELEMCHNS TR("\004", "\005") #if defined(CPUARM) #define TR_TELEM_RESERVE TR("[--]", "[---]") @@ -376,6 +376,12 @@ #define TR_TELEM_TIMERS TR("Chr1""Chr2", "Chr1\0""Chr2\0") #endif +#if LCD_W >= 212 + #define TR_VTELEMCHNS "---\0 ""Batt\0" TR_TELEM_TIME TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_TIMERS TR_SWR "Tx\0 " TR_TELEM_RSSI_RX TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0 ""Rpm\0 ""Carbu""T1\0 ""T2\0 ""Vit\0 ""Dist\0""AltG\0""Elem\0""Velm\0""Vfas\0""Cour\0""Consm""Puiss""AccX\0""AccY\0""AccZ\0""Cap\0 ""VitV\0""VitA\0""dET\0 " TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0 ""A2-\0 " TR_A3_A4_MIN "Alt-\0""Alt+\0""Rpm+\0""T1+\0 ""T2+\0 ""Vit+\0""Dst+\0" TR_ASPD_MAX "Elem-""Els-\0""Vfas-""Curr+""Puis+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Accel""Temps" +#else + #define TR_VTELEMCHNS "---\0""Batt" TR_TELEM_TIME TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_TIMERS TR_SWR "Tx\0 " TR_TELEM_RSSI_RX TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0""Rpm\0""Carb""T1\0 ""T2\0 ""Vit\0""Dist""AltG""Elem""Velm""Vfas""Cour""Cnsm""Puis""AccX""AccY""AccZ""Cap\0""VitV""VitA""dET\0" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0""A2-\0" TR_A3_A4_MIN "Alt-""Alt+""Rpm+""T1+\0""T2+\0""Vit+""Dst+" TR_ASPD_MAX "Elm-""Els-""Vfs-""Cur+""Pui+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Acc\0""Tmps" +#endif + #define LENGTH_UNIT_IMP "ft\0" #define SPEED_UNIT_IMP "mph" #define LENGTH_UNIT_METR "m\0 " From 39a631d31d5da54fd67a6c3739afb9ba44748134 Mon Sep 17 00:00:00 2001 From: 3djc Date: Wed, 12 Apr 2017 10:07:47 +0200 Subject: [PATCH 118/203] Dramaticaly reduce spam on companion/simu 'debug' output --- radio/src/lua/interface.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/lua/interface.cpp b/radio/src/lua/interface.cpp index c4fcde2f4..c013702db 100644 --- a/radio/src/lua/interface.cpp +++ b/radio/src/lua/interface.cpp @@ -204,7 +204,7 @@ void luaDoGc(lua_State * L, bool full) else { lua_gc(L, LUA_GCSTEP, 10); } -#if defined(SIMU) || defined(DEBUG) +#if defined(DEBUG) if (L == lsScripts) { static uint32_t lastgcSctipts = 0; uint32_t gc = luaGetMemUsed(L); From d4ed05c98c12d4ad3a08d9b0521fa474d1022fa7 Mon Sep 17 00:00:00 2001 From: Andre Bernet Date: Wed, 12 Apr 2017 10:09:16 +0200 Subject: [PATCH 119/203] Fix translations again --- radio/src/translations/de.h.txt | 1 + radio/src/translations/fr.h.txt | 9 ++------- radio/src/translations/it.h.txt | 5 +++-- radio/src/translations/pl.h.txt | 1 + radio/src/translations/se.h.txt | 1 + 5 files changed, 8 insertions(+), 9 deletions(-) diff --git a/radio/src/translations/de.h.txt b/radio/src/translations/de.h.txt index 246e5c57a..0de76049a 100644 --- a/radio/src/translations/de.h.txt +++ b/radio/src/translations/de.h.txt @@ -556,6 +556,7 @@ #define TR_EXTRA_VSRCRAW "Batt""Time""GPS\0" TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW "Tmr1""Tmr2""Tmr3" #else #define TR_EXTRA_VSRCRAW + #define TR_VTELEMCHNS "---\0""Akku" TR_TELEM_TIME TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_TIMERS TR_SWR "Tx\0 " TR_TELEM_RSSI_RX TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0""Rpm\0""Fuel""T1\0 ""T2\0 ""Spd\0""Dist""GAlt""Cell""Cels""Vfas""Curr""Cnsp""Powr""AccX""AccY""AccZ""Hdg\0""VSpd""ASpd""dTE\0" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0""A2-\0" TR_A3_A4_MIN "Alt-""Alt+""Rpm+""T1+\0""T2+\0""Spd+""Dst+" TR_ASPD_MAX "Cel-""Cls-""Vfs-""Cur+""Pwr+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Acc\0""Zeit" #endif #define TR_VSRCRAW "---\0" TR_STICKS_VSRCRAW TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW TR_TRIMS_VSRCRAW TR_SW_VSRCRAW TR_EXTRA_VSRCRAW diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index a91294ae9..6ba238856 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -344,7 +344,7 @@ #define LEN_FUNCSOUNDS TR("\004", "\006") #define TR_FUNCSOUNDS TR("Bp1\0""Bp2\0""Bp3\0""Wrn1""Wrn2""Chee""Rata""Tick""Sirn""Ring""SciF""Robt""Chrp""Tada""Crck""Alrm", "Beep1 ""Beep2 ""Beep3 ""Warn1 ""Warn2 ""Cheep ""Ratata""Tick ""Siren ""Ring ""SciFi ""Robot ""Chirp ""Tada ""Crickt""AlmClk") -#define LEN_VTELEMCHNS TR("\004", "\005") +#define LEN_VTELEMCHNS "\004" #if defined(CPUARM) #define TR_TELEM_RESERVE TR("[--]", "[---]") @@ -376,12 +376,6 @@ #define TR_TELEM_TIMERS TR("Chr1""Chr2", "Chr1\0""Chr2\0") #endif -#if LCD_W >= 212 - #define TR_VTELEMCHNS "---\0 ""Batt\0" TR_TELEM_TIME TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_TIMERS TR_SWR "Tx\0 " TR_TELEM_RSSI_RX TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0 ""Rpm\0 ""Carbu""T1\0 ""T2\0 ""Vit\0 ""Dist\0""AltG\0""Elem\0""Velm\0""Vfas\0""Cour\0""Consm""Puiss""AccX\0""AccY\0""AccZ\0""Cap\0 ""VitV\0""VitA\0""dET\0 " TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0 ""A2-\0 " TR_A3_A4_MIN "Alt-\0""Alt+\0""Rpm+\0""T1+\0 ""T2+\0 ""Vit+\0""Dst+\0" TR_ASPD_MAX "Elem-""Els-\0""Vfas-""Curr+""Puis+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Accel""Temps" -#else - #define TR_VTELEMCHNS "---\0""Batt" TR_TELEM_TIME TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_TIMERS TR_SWR "Tx\0 " TR_TELEM_RSSI_RX TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0""Rpm\0""Carb""T1\0 ""T2\0 ""Vit\0""Dist""AltG""Elem""Velm""Vfas""Cour""Cnsm""Puis""AccX""AccY""AccZ""Cap\0""VitV""VitA""dET\0" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0""A2-\0" TR_A3_A4_MIN "Alt-""Alt+""Rpm+""T1+\0""T2+\0""Vit+""Dst+" TR_ASPD_MAX "Elm-""Els-""Vfs-""Cur+""Pui+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Acc\0""Tmps" -#endif - #define LENGTH_UNIT_IMP "ft\0" #define SPEED_UNIT_IMP "mph" #define LENGTH_UNIT_METR "m\0 " @@ -550,6 +544,7 @@ #define TR_EXTRA_VSRCRAW "Batt""H:M\0""GPS\0" TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW "Chr1""Chr2""Chr3" #else #define TR_EXTRA_VSRCRAW + #define TR_VTELEMCHNS "---\0""Batt" TR_TELEM_TIME TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_TIMERS TR_SWR "Tx\0 " TR_TELEM_RSSI_RX TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0""Rpm\0""Carb""T1\0 ""T2\0 ""Vit\0""Dist""AltG""Elem""Velm""Vfas""Cour""Cnsm""Puis""AccX""AccY""AccZ""Cap\0""VitV""VitA""dET\0" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0""A2-\0" TR_A3_A4_MIN "Alt-""Alt+""Rpm+""T1+\0""T2+\0""Vit+""Dst+" TR_ASPD_MAX "Elm-""Els-""Vfs-""Cur+""Pui+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Acc\0""Tmps" #endif #define TR_VSRCRAW "---\0" TR_STICKS_VSRCRAW TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW TR_TRIMS_VSRCRAW TR_SW_VSRCRAW TR_EXTRA_VSRCRAW diff --git a/radio/src/translations/it.h.txt b/radio/src/translations/it.h.txt index 1a1c50ca9..d7311a827 100644 --- a/radio/src/translations/it.h.txt +++ b/radio/src/translations/it.h.txt @@ -528,9 +528,9 @@ #endif #if defined(HELI) -#define TR_CYC_VSRCRAW "CYC1""CYC2""CYC3" + #define TR_CYC_VSRCRAW "CYC1""CYC2""CYC3" #else -#define TR_CYC_VSRCRAW "[C1]""[C2]""[C3]" + #define TR_CYC_VSRCRAW "[C1]""[C2]""[C3]" #endif #if defined(CPUARM) @@ -538,6 +538,7 @@ #define TR_EXTRA_VSRCRAW "Batt""Time""GPS\0" TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW "Tmr1""Tmr2""Tmr3" #else #define TR_EXTRA_VSRCRAW + #define TR_VTELEMCHNS "---\0""Batt" TR_TELEM_TIME TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_TIMERS TR_SWR "Tx\0 " TR_TELEM_RSSI_RX TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0""Rpm\0""Fuel""T1\0 ""T2\0 ""Spd\0""Dist""GAlt""Cell""Cels""Vfas""Curr""Cnsp""Powr""AccX""AccY""AccZ""Hdg\0""VSpd""ASpd""dTE\0" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0""A2-\0" TR_A3_A4_MIN "Alt-""Alt+""Rpm+""T1+\0""T2+\0""Spd+""Dst+" TR_ASPD_MAX "Cel-""Cls-""Vfs-""Cur+""Pwr+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Acc\0""Ora\0" #endif #define TR_VSRCRAW "---\0" TR_STICKS_VSRCRAW TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW TR_TRIMS_VSRCRAW TR_SW_VSRCRAW TR_EXTRA_VSRCRAW diff --git a/radio/src/translations/pl.h.txt b/radio/src/translations/pl.h.txt index 0aa99f530..37a868b77 100644 --- a/radio/src/translations/pl.h.txt +++ b/radio/src/translations/pl.h.txt @@ -540,6 +540,7 @@ #define TR_EXTRA_VSRCRAW "Batt""Time""GPS\0" TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW "Tmr1""Tmr2""Tmr3" #else #define TR_EXTRA_VSRCRAW + #define TR_VTELEMCHNS "---\0""Bat\0" TR_TELEM_TIME TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_TIMERS TR_SWR "Tx\0 " TR_TELEM_RSSI_RX TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0""Rpm\0""Fuel""T1\0 ""T2\0 ""Spd\0""Dist""GAlt""Cell""Cels""Vfas""Curr""Cnsp""Powr""AccX""AccY""AccZ""Hdg\0""VSpd""ASpd""dTE\0" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0""A2-\0" TR_A3_A4_MIN "Alt-""Alt+""Rpm+""T1+\0""T2+\0""Spd+""Dst+" TR_ASPD_MAX "Cel-""Cls-""Vfs-""Cur+""Pwr+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Acc\0""Time" #endif #define TR_VSRCRAW "---\0" TR_STICKS_VSRCRAW TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW TR_TRIMS_VSRCRAW TR_SW_VSRCRAW TR_EXTRA_VSRCRAW diff --git a/radio/src/translations/se.h.txt b/radio/src/translations/se.h.txt index 7a8ed46b8..aa94942a8 100644 --- a/radio/src/translations/se.h.txt +++ b/radio/src/translations/se.h.txt @@ -549,6 +549,7 @@ #define TR_EXTRA_VSRCRAW "Batt""Tid\0""GPS\0" TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW TR_RESERVE_VSRCRAW "Tmr1""Tmr2""Tmr3" #else #define TR_EXTRA_VSRCRAW + #define TR_VTELEMCHNS "---\0""Batt" TR_TELEM_TIME TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_TIMERS TR_SWR "Tx\0 ""Rx\0 " TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0""Rpm\0""Fuel""T1\0 ""T2\0 ""Spd\0""Dist""GAlt""Cell""Cels""Vfas""Curr""Cnsp""Powr""AccX""AccY""AccZ""Hdg\0""VSpd""ASpd""dTE\0" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0""A2-\0" TR_A3_A4_MIN "Alt-""Alt+""Rpm+""T1+\0""T2+\0""Spd+""Dst+" TR_ASPD_MAX "Cel-""Cls-""Vfs-""Cur+""Pwr+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Acc\0""Tid\0" #endif #define TR_VSRCRAW "---\0" TR_STICKS_VSRCRAW TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "Max\0" TR_CYC_VSRCRAW TR_TRIMS_VSRCRAW TR_SW_VSRCRAW TR_EXTRA_VSRCRAW From a062efeb21d9caacd3b1627e4018e485ec67b93a Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Wed, 12 Apr 2017 05:39:28 -0400 Subject: [PATCH 120/203] [Companion] Fix some Special/Global Functions editor source selection lists being broken and Action selector disappearing for simple actions with no parameters (fixes #4775 and #4779). --- companion/src/modeledit/customfunctions.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/companion/src/modeledit/customfunctions.cpp b/companion/src/modeledit/customfunctions.cpp index 559b5a245..26e618ac9 100644 --- a/companion/src/modeledit/customfunctions.cpp +++ b/companion/src/modeledit/customfunctions.cpp @@ -563,7 +563,7 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) } - fswtchFunc[i]->setVisible(widgetsMask); + fswtchFunc[i]->setVisible(cfn.swtch.toValue()); fswtchParam[i]->setVisible(widgetsMask & CUSTOM_FUNCTION_NUMERIC_PARAM); fswtchParamTime[i]->setVisible(widgetsMask & CUSTOM_FUNCTION_TIME_PARAM); fswtchParamGV[i]->setVisible(widgetsMask & CUSTOM_FUNCTION_GV_TOOGLE); @@ -701,7 +701,7 @@ void CustomFunctionsPanel::populateGVmodeCB(QComboBox *b, unsigned int value) void CustomFunctionsPanel::populateFuncParamCB(QComboBox *b, uint function, unsigned int value, unsigned int adjustmode) { QStringList qs; - b->clear(); + b->setModel(new QStandardItemModel(b)); // clear combo box but not any shared item model if (function==FuncPlaySound) { CustomFunctionData::populatePlaySoundParams(qs); b->addItems(qs); From 111bcad9a7041679742eaaa1c2f04017fa526871 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Wed, 12 Apr 2017 07:18:01 -0400 Subject: [PATCH 121/203] [Companion] Do not create a category in new file when loading data from radio; Fix crashes when editing category name. --- companion/src/mainwindow.cpp | 2 +- companion/src/mdichild.cpp | 9 ++++----- companion/src/mdichild.h | 2 +- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/companion/src/mainwindow.cpp b/companion/src/mainwindow.cpp index c7fb519e4..443efa8ac 100644 --- a/companion/src/mainwindow.cpp +++ b/companion/src/mainwindow.cpp @@ -805,7 +805,7 @@ void MainWindow::readEeprom() if (readEepromFromRadio(tempFile)) { MdiChild * child = createMdiChild(); - child->newFile(); + child->newFile(false); child->loadFile(tempFile, false); child->show(); qunlink(tempFile); diff --git a/companion/src/mdichild.cpp b/companion/src/mdichild.cpp index e9545888a..7676e9b49 100644 --- a/companion/src/mdichild.cpp +++ b/companion/src/mdichild.cpp @@ -565,7 +565,6 @@ void MdiChild::onItemActivated(const QModelIndex index) openModelEditWindow(mIdx); } else if (modelsListModel->isCategoryType(index)) { - ui->modelsList->setCurrentIndex(index); ui->modelsList->edit(index); } } @@ -591,8 +590,8 @@ void MdiChild::onDataChanged(const QModelIndex & index) } strcpy(radioData.categories[categoryIndex].name, modelsListModel->data(index, 0).toString().left(sizeof(CategoryData::name)-1).toStdString().c_str()); - ui->modelsList->setCurrentIndex(QModelIndex()); // must do this otherwise leaves QTreeView in limbo after TreeModel::refresh() (Qt undoc/bug?) - setModified(); + setWindowModified(true); + emit modified(); } /* @@ -1299,14 +1298,14 @@ void MdiChild::modelSimulate() startSimulation(this, radioData, getCurrentModel()); } -void MdiChild::newFile() +void MdiChild::newFile(bool createDefaults) { static int sequenceNumber = 1; isUntitled = true; curFile = QString("document%1.otx").arg(sequenceNumber++); updateTitle(); - if (firmware->getCapability(Capability::HasModelCategories)) { + if (createDefaults && firmware->getCapability(Capability::HasModelCategories)) { categoryAdd(); } } diff --git a/companion/src/mdichild.h b/companion/src/mdichild.h index f9f062553..3c3cc333e 100644 --- a/companion/src/mdichild.h +++ b/companion/src/mdichild.h @@ -81,7 +81,7 @@ class MdiChild : public QWidget QAction * getAction(const Actions type); public slots: - void newFile(); + void newFile(bool createDefaults = true); bool loadFile(const QString & fileName, bool resetCurrentFile=true); bool save(); bool saveAs(bool isNew=false); From fe55889495958ddcaa6ae1d8bc21b2af7790b867 Mon Sep 17 00:00:00 2001 From: 3djc Date: Wed, 12 Apr 2017 14:19:15 +0200 Subject: [PATCH 122/203] Prevent delay to be accessible for edge LS (#4781) --- radio/src/gui/128x64/model_logical_switches.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/radio/src/gui/128x64/model_logical_switches.cpp b/radio/src/gui/128x64/model_logical_switches.cpp index a41a89311..cb0c65c00 100644 --- a/radio/src/gui/128x64/model_logical_switches.cpp +++ b/radio/src/gui/128x64/model_logical_switches.cpp @@ -217,6 +217,13 @@ void menuModelLogicalSwitchOne(event_t event) case LS_FIELD_DELAY: lcdDrawTextAlignedLeft(y, STR_DELAY); + if (cstate == LS_FAMILY_EDGE) { + lcdDrawText(CSWONE_2ND_COLUMN, y, STR_NA); + if (attr) { + REPEAT_LAST_CURSOR_MOVE(); + } + break; + } if (cs->delay > 0) lcdDrawNumber(CSWONE_2ND_COLUMN, y, cs->delay, attr|PREC1|LEFT); else From c6a024289f04deb3db73b8ec9d224744af11d76e Mon Sep 17 00:00:00 2001 From: Sebastien Charpentier Date: Wed, 12 Apr 2017 14:20:11 +0200 Subject: [PATCH 123/203] Updated FR translation for Companion 2.2.0N368 (#4771) --- companion/src/translations/companion_fr.ts | 2027 +++++++++++--------- 1 file changed, 1084 insertions(+), 943 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index e9de273d8..4b1e95b45 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -4,27 +4,27 @@ AileronsPage - + No Non - + Yes, controlled by a single channel Oui, contrôlés par une seule voie - + Yes, controlled by two channels Oui, contrôlés par 2 voies - + <br>First Aileron Channel: <br>Première voie d'ailerons: - + Second Aileron Channel: Deuxième voie d'ailerons: @@ -32,27 +32,27 @@ AirbrakesPage - + No Non - + Yes, controlled by a single channel Oui, contrôlés par une seule voie - + Yes, controlled by two channels Oui, contrôlés par 2 voies - + <br>First Airbrake Channel: <br>Première voie de volets: - + Second Airbrake Channel: Deuxième voie de volets: @@ -62,7 +62,7 @@ Edit Settings - Modifier les réglages + Éditer les réglages @@ -309,29 +309,29 @@ Manche Droit: Profondeur, Direction - - - + + + Select Folder Sélectionner dossier - + Select Executable Sélectionner exécutable - + Use OpenTX firmware nightly builds Utlilser les nightly builds du firmware - + Use Companion nightly builds Utlilser les nightly builds de Companion - + Simulator Volume Gain Gain de volume du simulateur @@ -393,190 +393,215 @@ Peut être différente de la langue du firmware Réglages de l'application - + Show splash screen when Companion starts Afficher l'écran d'accueil au lancement de Companion - + Automatic check for Companion updates Vérifier la présence de mises à jour de Companion automatiquement - + Enable automatic backup before writing firmware Sauvegarder les réglages et modèles automatiquement lors des transferts - + Automatic check for OpenTX firmware updates Vérifier la présence de mises à jour de firmware automatiquement - + Splash Screen Library Bibliothèque d'écrans d'accueil - + Files to keep Fichiers à conserver - + Google Earth Executable Exécutable Google Earth - + Only show user splash images Ne montrer que les images de l'utilisateur - + Show user and companion splash images Montrer les images de Companion et de l'utilisateur - + User Splash Screens Ecrans d'accueil personnalisés - + Automatic Backup Folder Dossier de sauvegardes automatiques - - Use model wizard when creating a new model - Utiliser l'assistant à la création d'un nouveau modèle - - - + Simulator Settings Paramètres du simulateur - + Simulator BackLight Rétroéclairage du simulateur - + Enable Actif - + + Action on New Model + Action par défaut "Ajout Modèle" + + + + Use model wizard + Assistant + + + + Open model editor + Éditer modèle + + + + Just create the model + Créer modèle + + + + <html><head/><body><p>This option maintains the behaviour from older OpenTx versions where empty model slots are preserved when a model is deleted or moved. </p><p>When this option is de-selected, the other models may be re-arranged to fill the gap left by the removed model.</p></body></html> + <html><head/><body><p><b><u>/!\</u> Uniquement pour les radios sans catégories <u>/!\</u></b></p><p>Cette option maintient le comportement des anciennes versions d’OpenTx où les emplacements des modèles vides sont conservés lorsqu'un modèle est supprimé ou déplacé.</p><p>Lorsque cette option est désélectionnée, les autres modèles peuvent être réarrangés pour combler l'écart laissé par le modèle supprimé.</p></body></html> + + + + Remove empty model slots when deleting models (only applies for radios w/out categories) + Supprimer les emplacements vides lors de la suppression de modèles + + + Blue Bleu - + Green Vert - + Red Rouge - + Orange Orange - + Yellow Jaune - + Joystick - + Calibrate Calibrer - + Simulator capture folder Dossier des captures d'écran - + Only capture to clipboard Capturer dans le presse-papiers uniquement - + Remember simulator switch values Mémoriser les positions des inters du simulateur - + My Radio Ma radio - + Select your snapshot folder Sélectionner le dossier où stocker les captures d'écran - - + + No joysticks found Aucun Joystick trouvé - + EMPTY: No radio settings stored in profile VIDE: Aucune donnée stockée dans le profil - + AVAILABLE: Radio settings of unknown age DISPONIBLE: Réglages enregistrés à une date inconnue - + AVAILABLE: Radio settings stored %1 DISPONIBLE: Réglages enregistrés le %1 - + Select your library folder Sélectionner le dossier de bibliothèque - - + + Select your Models and Settings backup folder Sélectionner le dossier dans lequel une sauvegarde des réglages et modèles sera placée automatiquement lors de chaque opération - + Select Google Earth executable Sélectionner l'emplacement de l'exécutable Google Earth - + Select the folder replicating your SD structure Sélectionner un dossier contenant une copie des dossiers de la carte SD - + Open Image to load Ouvrir l'image à charger - + Images (%1) Images (%1) @@ -660,42 +685,42 @@ Peut être différente de la langue du firmware Comparer les modèles - - Drag first model here - Glisser le premier modèle ici + + To compare models, drag and drop them anywhere in this window. + Pour comparer les modèles, faites un glisser/déposer n'importe où dans cette fenêtre. - - Drag second model here - Glisser le second modèle ici - - - + Close Fermer - + Print Imprimer - + Print to file Imprimer vers un fichier - - No name - Sans titre + + Unnamed Model %1 + Modèle sans Nom %1 - + + Click to remove this model. + Cliquer pour supprimer ce modèle. + + + Print Document Imprimer le document - + Select PDF output file Choisir le fichier PDF de sortie @@ -703,7 +728,7 @@ Peut être différente de la langue du firmware ConclusionPage - + OK, I understand. OK, compris. @@ -1044,22 +1069,22 @@ Peut être différente de la langue du firmware CyclicPage - + 90 - + 120 - + 120x - + 140 @@ -1086,7 +1111,7 @@ Peut être différente de la langue du firmware <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> <html><head/><body><p>Entrer le filtre ici. Cliquer sur le bouton d'aide/info pour plus de détails sur l'utilisation du filtre. </p><p> -Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le d'abord, puis faite le raccourci clavier <code>Shift-Supprimer</code> (ou <code>Shift-Retour Arrière</code>).</p></body></html> +Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le d'abord, puis faite le raccourci clavier <code>Shift-Suppr</code> (ou <code>Shift-Retour Arrière</code>).</p></body></html> @@ -1141,7 +1166,7 @@ Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> - <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>Le filtre supporte deux types de syntaxes: la recherche simple utilisant les métacaractères ou la recherche avancée utilisant les expressions régulières (<code>RegEx</code>) de type Perl.</p><p>Par défaut, un filtre ne montre que les lignes qui correspondent (<b>inclusif</b>). Pour faire un filtre <b>exclusif</b> qui supprime les lignes de correspondance, préfixez l'expression du filtre avec un <kbd>!</kbd> (point d'exclamation).</p><p>Pour utiliser les <b>Expressions Régulières</b> (RegEx), préfixez le texte du filtre avec un <kbd>/</kbd> (slash) ou <kbd>^</kbd> (accent circonflexe).<ul><li>Il faut mettre le <kbd>!</kbd> <u>avant</u> le <kbd>/</kbd> ou <kbd>^</kbd> dans le cas d'un filtre exclusif.</li><li>Par défaut, la correspondance est sensible à la casse (ex: a &ne; A). Pour la rendre insensible (ex: a = A), ajoutez l'opérateur typique <kbd>/i</kbd> (slash i) à la fin de votre RegEx.</li><li>Si vous utilisez un <kbd>^</kbd> pour désigner une RegEx, il deviendra une partie de la RegEx (<kbd>^</kbd> est le caractère de début de chaîne).</li><li>Si la RegEx n'est pas valide, le champ d'édition du filtre affichera une bordure rouge et vous ne pourrez pas activer le filtre.</li><li>Une ressource utile pour tester les RegExs (avec une référence complète) peut être trouvée sur le site <a href="http://www.regexr.com/">http://www.regexr.com/</a> (tutoriel en français: <a href="http://perl.mines-albi.fr/DocFr/perlretut.html">Expressions rationnelles/régulières en Perl</a>)</li></ul></p><p>Pour utiliser la <b>recherche simple</b>, tapez simplement le texte recherché.<ul><li>Métacaractères: le quantificateur <kbd>*</kbd> (astérisque) correspond à zéro ou plus de n'importe quel caractère, et le quantificateur <kbd>?</kbd> (point d'interrogation) correspond à un caractère unique.</li><li>La correspondance est toujours sensible à la casse.</li><li>La correspondance commence toujours au début du Log. Pour ignorer les caractères au début, utilisez le métacaractère <kbd>*</kbd>.</li><li>Un métacaractère <kbd>*</kbd> est implicitement ajouté à la fin (ainsi, toutes les correspondances valides soient bien affichées jusqu'à la fin du Log). Si vous voulez éviter ce métacaractère implicite, il faut utiliser une RegEx.</li><li>Pour rechercher un caractère qui est lui-même un métacaractère, il faut préfixer avec un <kbd>\</kbd> (backslash) (ex: "<i>toto\*titi</i>" correspond à "<i>toto*titi</i>").</li></ul></p><p>Quand l'<b>édition</b> est terminée, appuyez sur la touche ENTRER ou TAB (ou cliquez n'importe où à l'extérieur du champ du filtre) afin de mettre à jour le filtre.</p><p>Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le d'abord, puis faite le raccourci clavier <kbd>Shift-Supprimer</kbd> (ou <kbd>Shift-Retour Arrière</kbd>). Les filtres par défaut ne peuvent pas être effacés. Jusqu'à 50 filtres peuvent être mémorisés.</p></body></html> + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>Le filtre supporte deux types de syntaxes: la recherche simple utilisant les métacaractères ou la recherche avancée utilisant les expressions régulières (<code>RegEx</code>) de type Perl.</p><p>Par défaut, un filtre ne montre que les lignes qui correspondent (<b>inclusif</b>). Pour faire un filtre <b>exclusif</b> qui supprime les lignes de correspondance, préfixez l'expression du filtre avec un <kbd>!</kbd> (point d'exclamation).</p><p>Pour utiliser les <b>Expressions Régulières</b> (RegEx), préfixez le texte du filtre avec un <kbd>/</kbd> (slash) ou <kbd>^</kbd> (accent circonflexe).<ul><li>Il faut mettre le <kbd>!</kbd> <u>avant</u> le <kbd>/</kbd> ou <kbd>^</kbd> dans le cas d'un filtre exclusif.</li><li>Par défaut, la correspondance est sensible à la casse (ex: a &ne; A). Pour la rendre insensible (ex: a = A), ajoutez l'opérateur typique <kbd>/i</kbd> (slash i) à la fin de votre RegEx.</li><li>Si vous utilisez un <kbd>^</kbd> pour désigner une RegEx, il deviendra une partie de la RegEx (<kbd>^</kbd> est le caractère de début de chaîne).</li><li>Si la RegEx n'est pas valide, le champ d'édition du filtre affichera une bordure rouge et vous ne pourrez pas activer le filtre.</li><li>Une ressource utile pour tester les RegExs (avec une référence complète) peut être trouvée sur le site <a href="http://www.regexr.com/">http://www.regexr.com/</a> (tutoriel en français: <a href="http://perl.mines-albi.fr/DocFr/perlretut.html">Expressions rationnelles/régulières en Perl</a>)</li></ul></p><p>Pour utiliser la <b>recherche simple</b>, tapez simplement le texte recherché.<ul><li>Métacaractères: le quantificateur <kbd>*</kbd> (astérisque) correspond à zéro ou plus de n'importe quel caractère, et le quantificateur <kbd>?</kbd> (point d'interrogation) correspond à un caractère unique.</li><li>La correspondance est toujours sensible à la casse.</li><li>La correspondance commence toujours au début du Log. Pour ignorer les caractères au début, utilisez le métacaractère <kbd>*</kbd>.</li><li>Un métacaractère <kbd>*</kbd> est implicitement ajouté à la fin (ainsi, toutes les correspondances valides soient bien affichées jusqu'à la fin du Log). Si vous voulez éviter ce métacaractère implicite, il faut utiliser une RegEx.</li><li>Pour rechercher un caractère qui est lui-même un métacaractère, il faut préfixer avec un <kbd>\</kbd> (backslash) (ex: "<i>toto\*titi</i>" correspond à "<i>toto*titi</i>").</li></ul></p><p>Quand l'<b>édition</b> est terminée, appuyez sur la touche ENTRER ou TAB (ou cliquez n'importe où à l'extérieur du champ du filtre) afin de mettre à jour le filtre.</p><p>Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le d'abord, puis faite le raccourci clavier <kbd>Shift-Suppr</kbd> (ou <kbd>Shift-Retour Arrière</kbd>). Les filtres par défaut ne peuvent pas être effacés. Jusqu'à 50 filtres peuvent être mémorisés.</p></body></html> @@ -1152,78 +1177,78 @@ Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le EepromInterface - + Possible causes for this: Causes possibles: - + - Eeprom is from a newer version of OpenTX - L'EEPROM peut avoir été créée avec une version d'OpenTX plus récente - + - Eeprom is not from OpenTX - L'EEPROM peut avoir été créée avec un firmware autre qu'OpenTX - + - Eeprom is not from Th9X - L'EEPROM n'est pas une EEPROM TX9X - + - Eeprom is not from Gruvin9X - L'EEPROM n'est pas une EEPROM Gruvin9X - + - Eeprom is not from ErSky9X - L'EEPROM n'est pas une EEPROM ErSky9X - + - Eeprom is not from Er9X - L'EEPROM n'est pas une EEPROM ER9X - + - Eeprom size is invalid - La taille de l'EEPROM est invalide - + - Eeprom file system is invalid - Le système de fichier de l'EEPROM est invalide - + - Eeprom is from a unknown board - L'EEPROM ne correspond à aucune carte supportée - + - Eeprom is from the wrong board - L'EEPROM ne correspond pas au type de radio sélectionné - + - Eeprom backup not supported - Sauvegarde d'EEPROM non supportée - + - Something that couldn't be guessed, sorry - Erreur inconnue - + Warning: Avertissement: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - Le firmware de la radio est probablement incorrect, @@ -1231,14 +1256,14 @@ la taille de l'EEPROM est de 4096 mais seulement 2048 bytes sont utilisés. Vérifier la sélection (M64/M128) - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - Le fichier qui vient d'être ouvert provient d'une ancienne verison d'OpenTX et a été converti. Il est recommandé d'"Enregistrer Sous" au plus vite pour ne pas risquer d'écraser votre ancien fichier. - + Warnings! Avertissements ! @@ -1246,12 +1271,12 @@ Il est recommandé d'"Enregistrer Sous" au plus vite pour ne pas ElevonsPage - + <br>First Elevon Channel: <br>Première voie d'élevons: - + Second Elevon Channel: Deuxième voie d'élevons: @@ -1370,7 +1395,7 @@ Si vide, la ligne est toujours active. Edit %1 - Editer %1 + Éditer %1 @@ -1396,22 +1421,22 @@ Si vide, la ligne est toujours active. FblPage - + Throttle Channel: Voie des gaz: - + Yaw Channel: Voie du lacet: - + Pitch Channel: Voie du tangage: - + Roll Channel: Voie du roulis: @@ -1464,27 +1489,27 @@ Peut être différente de la langue du firmware FlapsPage - + No Non - + Yes, controlled by a single channel Oui, contrôlés par une seule voie - + Yes, controlled by two channels Oui, contrôlés par 2 voies - + <br>First Flap Channel: <br>Première voie de volets: - + Second Flap Channel: Deuxième voie de volets: @@ -2003,17 +2028,17 @@ Veuillez utiliser Zadig pour installer le pilote. FlybarSelectionPage - + Has Flybar Avec barre de Bell - + Flybarless Sans barre de Bell - + Flybar: Barre de Bell: @@ -3069,17 +3094,17 @@ Are you sure ? GyroPage - + No Non - + Yes, controled by a switch Oui, contrôlé par un inter - + Yes, controlled by a pot Oui, contrôlé par un potentiomètre @@ -3469,22 +3494,22 @@ Extra long : bips extra longs. HeliPage - + Throttle Channel: Voie des gaz: - + Yaw Channel: Voie du lacet: - + Pitch Channel: Voie du tangage: - + Roll Channel: Voie du roulis: @@ -3528,7 +3553,7 @@ Extra long : bips extra longs. Delete Selected Inputs? - Effacer les entrées sélectionnées ? + Supprimer les entrées sélectionnées ? @@ -3878,111 +3903,106 @@ Les colonnes contenant l'altitude "GAlt" et la vitesse "GSpd MainWindow - - + + Edit - Edition + Édition - - + + File Fichier - + Display previous warning again at startup ? Afficher les alertes précédentes lors du prochain démarrage ? - + New release available Nouvelle version disponible - - + + Error Erreur - + Error opening file %1: %2. Erreur à l'ouverture du fichier %1: %2. - + Compilation server too busy, try later Serveur de compilation surchargé, veuillez réessayer plus tard - + Unknown server failure, try later Erreur inconnue du serveur de compilation, veuillez réessayer plus tard - + Do you want to write the firmware to the radio now ? Voulez vous transférer le firmware à la radio maintenant ? - - + + Yes Oui - - + + No Non - - + + Release Notes Notes de version - - + + Do you want to download release %1 now ? Voulez-vous télécharger la version %1 maintenant ? - + Firmware updates Mises à jour de firmware - + Current firmware does not provide release notes informations. Le firmware actuel ne contient pas de notes de version. - - Load backup from file - Charger une sauvegarde à partir du fichier - - - + Compare models Comparer les modèles - + Show fuses dialog Afficher les réglages des fusibles - + A monochrome black icon theme Thème avec icônes monochromes noires - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -3995,7 +4015,7 @@ Voulez-vous la télécharger maintenant ? Nous recommandons de lire attentivement les notes de version à l'aide du bouton ci-dessous, celles-ci peuvent contenir des infos importantes concernant les changements effectués depuis la version précédente. - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -4012,706 +4032,714 @@ Voulez vous la télécharger maintenant ? Nous recommandons de lire attentivement les notes de version à l'aide du bouton ci-dessous, celles-ci peuvent contenir des infos importantes concernant les changements effectués depuis la version précédente. - - + + Synchronize SD Synchroniser la carte SD - + New Nouveau - + Open... Ouvrir... - - Copy Model - Copier le modèle - - - + A monochrome white icon theme Thème avec icônes monochromes blanches - + A monochrome blue icon theme Thème avec icônes monochromes bleues - + Small Petites - + Use small toolbar icons Petites icônes de barre d'outils - + Use normal size toolbar icons Icônes de barre d'outils normales - + Normal Normales - + Use big toolbar icons Grosses icônes de barre d'outils - + Big Grandes - + Use huge toolbar icons Immenses icônes de barre d'outils - + Huge Immenses - + List programmers... Lister les programmateurs... - + Fuses... Fusibles... - - + + Read Firmware from Radio Lire le firmware de la radio - + Read firmware from Radio Lire le firmware de la radio - + Write Firmware to Radio Transférer le firmware à la radio - + Write firmware to Radio Transférer le firmware à la radio - + Add Radio Profile Ajouter un profil de radio - + Manuals and other Documents Manuels et documents - + Open the OpenTX document page in a web browser Ouvre la page de documentation d'OpenTX dans un navigateur - + Write Models and Settings To Radio Transférer les réglages et modèles vers la radio - + Write Models and Settings to Radio Transférer les réglages et modèles vers la radio - - - + + Companion - - + + Read Models and Settings from Radio Lire les réglages et modèles depuis la radio - + OpenTX Companion %1 - Radio: %2 - Profile: %3 OpenTX Companion %1 - Radio: %2 - Profil: %3 - + + List of recently used files + Liste des fichiers récemment utilisés + + + + Radio Profiles + Profil radio + + + + Create or Select Radio Profiles + Créer ou Sélectionner un profil radio + + + Configure Communications... Configurer les communications... - + Configure software for communicating with the Radio Configurer le programme gérant les communications avec la radio - + Write Backup to Radio Transférer une sauvegarde à la radio - + Write Backup from file to Radio Transférer une sauvegarde à la radio - + Backup Radio to File Sauvegarder la radio - + Save a complete backup file of all settings and model data in the Radio Créer une copie de sauvegarde de tous les réglages et modèles de la radio - + Contributors... Contributeurs... - + A tribute to those who have contributed to OpenTX and Companion Remerciements à tout ceux qui ont contribué à OpenTX et Companion - + SD card synchronization Synchronisation de la carte SD - + Recent Files Fichiers récents - - Recent Models+Settings - Fichiers de réglages et modèles récents - - - + Set Icon Theme Choisir le thème d'icônes - + Set Icon Size Choisir la taille des icônes - + Write Ecrire - + A new version of Companion is available (version %1)<br>Would you like to download it? Une nouvelle version de Companion est disponible (version %1)<br>Voulez-vous la télécharger ? - + OpenTX Home Page: <a href='%1'>%1</a> Page d'accueil d'OpenTX: <a href='%1'>%1</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> Si vous trouvez ce programme utile, merci de le supporter par une <a href='%1'>donation</a> - - Show the list of radio profiles - Voir la liste des profils de radio - - - + Ready Prêt - + Show the application's About box Afficher la fenêtre "A propos" de l'application - - + + File loaded Fichier chargé - + A new release of Companion is available, please check the OpenTX website! Une nouvelle version de Companion est disponible, veuillez vous référer au site web d'OpenTX ! - - + + Open Models and Settings file Ouvrir un fichier de réglages et modèles - - + + File saved Fichier sauvegardé - + Read Models and Settings From Radio Lire les réglages et modèles depuis la radio - + Ignore this release %1? Ignorer la version %1 ? - + Not enough flash available on this board for all the selected options Pas assez de place disponible pour les options sélectionnées - + Compilation server temporary failure, try later Erreur de compilation sur le serveur, veuillez réessayer plus tard - + Compilation error Erreur de compilation - + Invalid firmware Firmware invalide - + Invalid board Carte non valide - + Invalid language Language non valide - + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. Certains textes ne seront pas traduits avant le prochain redémarrage de Companion. Veuillez noter que certaines traductions peuvent ne pas être complètes. - + Models and Settings read Lecture des modèles et réglages - - + + This function is not yet implemented Cette fonction n'est pas implémentée pour l'instant - + Save Radio Backup to File Sauvegarder la radio - + Read Radio Firmware to File Sauvegarder le firmware de la radio - + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> Le projet OpenTX Companion a été créé à partir d'<a href='%1'>eePe</a> - + Copyright OpenTX Team - + Create a new Models and Settings file Créer un nouveau fichier de réglages et modèles - - + + Save Models and Settings file Enregistrer le fichier de réglages et modèles - + Save Enregistrer - + Save As... Enregistrer sous... - + + Close + Fermer + + + + Close Models and Settings file + Fermer le fichier de réglages et modèles + + + Exit the application Quitter l'application - + Exit Quitter - - Cut Model - Couper le modèle - - - - Cut current model to the clipboard - Couper le modèle courant dans le presse-papier - - - - Copy current model to the clipboard - Copier le modèle courant dans le presse-papier - - - - Paste model from clipboard - Coller le modèle depuis le presse-papier - - - - Paste Model - Coller le modèle - - - + Create a new Radio Settings Profile Créer un nouveau profil de réglages et modèles - + Copy Current Radio Profile Copier le profil radio actuel - + Duplicate current Radio Settings Profile Dupliquer les réglages radio du profil actuel - - Delete Current Radio Profile - Effacer le profil radio actuel - - - + Delete the current Radio Settings Profile - Effacer les réglages radio du profil actuel + Supprimer les réglages radio du profil actuel - + Use default system language. Utiliser le langage système par défaut. - + Use %1 language (some translations may not be complete). Utiliser la langue %1 (certaines traductions peuvent être incomplètes). - + Classical Classique - + + Delete Current Radio Profile... + Supprimer le profil radio actuel... + + + + Tabbed Windows + Fenêtres à onglets + + + + Use tabs to arrange open windows. + Utilisez les onglets pour organiser les fenêtres ouvertes. + + + + Tile Windows + Titre de la fenêtre + + + + Arrange open windows across all the available space. + Disposez les fenêtres ouvertes sur tout l'espace disponible. + + + + Cascade Windows + Fenêtres en cascade + + + + Arrange all open windows in a stack. + Organisez toutes les fenêtres ouvertes dans une pile. + + + + Close All Windows + Fermer toutes les fenêtres + + + + Closes all open files (prompts to save if necessary. + Fermer tous les fichiers ouverts (proposer de sauvegarder si nécessaire). + + + + Window + Fenêtre + + + + Ctrl+Shift+S + + + + + Ctrl+Alt+L + + + + + Ctrl+Alt+D + + + + + Ctrl+Alt+R + + + + The classic companion9x icon theme Thème d'icônes classique de Companion - + Yerico - + Yellow round honey sweet icon theme Thème d'icônes rondes jaunes - + Monochrome - + MonoWhite Monochrome Blanc - + + Alt+%1 + + + + - Copy - Copier - + Not possible to remove profile Impossible de supprimer le profil - + The default profile can not be removed. Le profil par défaut ne peut pas être supprimé. - + Confirm Delete Profile Confirmer la suppression du profil - + Are you sure you wish to delete the "%1" radio profile? There is no way to undo this action! - Etes-vous sûr de vouloir effacer le profil radio %1 ? Cette action est irréversible ! + Etes-vous sûr de vouloir supprimer le profil radio %1 ? Cette action est irréversible ! - + MonoBlue Monochrome Bleu - + System language Langue du système - + About... A propos... - - Print... - Imprimer... - - - - Print current model - Imprimer le modèle courant - - - - Simulate... - Simuler... - - - - Simulate current model - Simuler le modèle courant - - - - Alt+S - - - - - Load Backup... - Ouvrir la sauvegarde... - - - + View Log File... Ouvrir un Log... - + Open and view log file Ouvrir et visualiser un log - + Settings... Préférences... - + Edit Settings - Modifier les réglages + Éditier les réglages - + Download... Télécharger... - + Download firmware and voice files Télécharger firmware et fichiers son - + Check for Updates... Vérifier les mises à jour... - + Check OpenTX and Companion updates Vérifier les mises à jour d'OpenTX et Companion - + Companion Changes... Changements de Companion... - + Show Companion change log Voir l'historique des changements de Companion - + Firmware Changes... Changements du firmware... - + Show firmware change log Voir l'historique des changements du firmware - + Compare Models... Comparer 2 modèles... - + Edit Radio Splash Image... - Modifier l'écran d'accueil de la radio... + Éditier l'écran d'accueil de la radio... - + Edit the splash image of your Radio - Modifier l'écran d'accueil de la radio + Éditier l'écran d'accueil de la radio - + List available programmers Lister les programmateurs supportés - - + + Save As Enregistrer Sous - + Executable (*.exe) Exécutable (*.exe) - - + + No updates available at this time. Aucune mise à jour disponible. - + Unable to check for updates. Impossible de rechercher des mises à jour. - + Would you like to launch the installer? Voulez-vous lancer l'installation ? - - + + Help Aide - + Checking for updates Recherche de mises à jour - + The new theme will be loaded the next time you start Companion. Le nouveau thème sera utilisé lors du prochain lancement de Companion. - - The icon size will be used the next time you start Companion. - La nouvelle taille d'icônes sera utilisée lors du prochain lancement de Companion. - - - + About Companion A propos de Companion - + Set Menu Language Choisir la langue des menus - + Settings Réglages - + Read/Write Transfert - - - Radio Profile - Profil de radio - - - - Show recent Models+Settings documents - Voir les fichiers récents - - - + %2 - + New Radio Nouvelle radio @@ -4719,202 +4747,333 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b MdiChild - - - - - - - + + + + + + + Error Erreur - + Unable to find file %1! Fichier %1 introuvable ! - - - - + + + + Save As Enregister Sous - + + Alt+Shift+E + + + + + Ctrl+Alt+C + + + + + Ctrl+Alt+V + + + + + Alt+Shift+S + + + + + Alt+C + + + + + Alt+A + + + + + Alt+R + + + + + Alt+W + + + + + Alt+U + + + + + %n Model(s) + As in "Copy 3 Models" or "Cut 1 Model" or "Delete 3 Models" action). + + %n Modèle + %n Modèles + + + + + %n Model(s) + As in "Paste 3 Models" or "Insert 1 Model." + + %n Modèle + %n Modèles + + + + + %n Category(ies) + As in "Delete 3 Categories" or "Delete 1 Category." + + %n Catégorie + %n Catégories + + + + + Nothing selected + Rien n'a été sélectionné + + + + Rename Category + Renommer la catégorie + + + + Edit Model + Éditer le modèle + + + + Cut + Couper + + + + Copy + Copier + + + + Paste + Coller + + + + Insert + Insérer + + + + Edit Radio Settings + Éditer les réglages radio + + + + Copy Radio Settings + Copier les réglages radio + + + + Paste Radio Settings + Coller les réglages radio + + + + Simulate Radio + Simuler la radio + + + + Add Category + Ajouter catégorie + + + + Category + Catégorie + + + + Add Model + Ajouter modèle + + + + Model + Modèle + + + + Restore from Backup + Restaurer depuis une sauvegarde + + + + Model Wizard + Assistant de configuration du modèle + + + + Set as Default + Définir par défaut + + + + Print Model + Imprimer modèle + + + + Simulate Model + Simuler modèle + + + + Duplicate Model + Dupliquer modèle + + + + Show Category Actions Toolbar + Afficher la barre d'outils "Catégorie" + + + + Show Radio Actions Toolbar + Afficher la barre d'outils "Radio" + + + + Show Model Actions Toolbar + Afficher la barre d'outils "Modèle" + + + + Category index out of range. + Index de catégorie hors limite. + + + + Cannot delete the last category. + Impossible d'effacer la dernière catégorie. + + + This category is not empty! Catégorie non vide ! - + + Cannot insert model, last model in list would be deleted. + Impossible d'insérer le modèle, le dernier modèle dans la liste serait supprimé. + + + + Cannot add model, could not find an available model slot. + Impossible d'ajouter un modèle, aucun emplacement libre n’est disponible. + + + New model Nouveau modele - + + Cannot paste model, out of available model slots. + Impossible de coller le modèle, aucun emplacement libre n’est disponible. + + + + You are replacing an existing model, are you sure? + Vous allez écraser un modèle existant, êtes-vous sûr ? + + + + Delete %n selected model(s)? + + Supprimer le modèle sélectionné %n ? + Supprimer les modèles sélectionnés %n ? + + + + + Delete %n selected category(ies)? + + Supprimer la catégorie sélectionnée %n ? + Supprimer les catégories sélectionnées %n ? + + + + + Cannot duplicate model, could not find an available model slot. + Impossible de dupliquer le modèle, aucun emplacement libre n’est disponible. + + + Unable to find Horus radio SD card! Impossible de trouver la carte SD de la Horus ! - + Models and Settings written Modèle et réglages écrit - + Cannot write temporary file! Ecriture de fichier temporaire impossible ! - + Editing model %1: Édition du modèle %1 : - + Error reading file %1: %2. Fichier %1 corrompu: %2. - + Error opening file %1: %2. Erreur à l'ouverture du fichier %1: %2. - - Delete selected models? - Effacer les modèles sélectionnés ? - - - - Cannot delete default model. - Le modèle actif ne peut être supprimé. - - - - &Edit - &Édition - - - - &Restore from backup - &Restaurer à partir d'une sauvegarde - - - - &Model Wizard - &Assistant de configuration - - - - &Delete - &Supprimer - - - + Delete Supprimer - - &Copy - &Copier - - - - Ctrl+C - - - - - &Cut - &Couper - - - - Ctrl+X - Ctrl+X - - - - - &Paste - &Coller - - - - - Ctrl+V - - - - - D&uplicate - &Dupliquer - - - - Ctrl+U - - - - + Move to Category Déplacer dans la catégorie - - &Use as default - &Choisir comme modèle par défaut - - - - P&rint model - &Imprimer les données du modèle - - - - Ctrl+P - - - - - &Simulate model - &Simuler le modèle sélectionné - - - + Alt+S - - &Add model - &Ajouter modèle - - - - &Rename category - &Renommer catégorie - - - - &Delete category - &Supprimer catégorie - - - - &Add category - &Ajouter une catégorie - - - + Models and settings will be automatically converted. If that is not what you intended, please close the file and choose the correct radio type/profile before reopening it. @@ -4923,64 +5082,48 @@ Si ce n'est pas ce que vous voulez, fermer le fichier et choisissez la bonne radio avant de l'ouvrir.à nouveau. - + Do you want to overwrite radio general settings? Voulez-vous vraiment écraser les paramètres généraux ? - - You are pasting on an not empty model, are you sure? - Vous allez écraser un modèle, êtes vous sûr ? - - - + free bytes octets libres - + New category Translators do NOT use accent for this, this is the default category name on Horus. Nouvelle categorie - - + Companion - + Open backup Models and Settings file Ouvrir la sauvegarde de réglages et modèles - + Warning Avertissement - + Invalid binary backup File %1 Fichier de sauvegarde %1 invalide - + %1 has been modified. Do you want to save your changes? %1 a été modifié. Enregistrer les changements ? - - - Radio settings - Réglages Radio - - - - Simulate Tx - Simulation de l'émetteur - MixerDialog @@ -5253,7 +5396,7 @@ Mixage actif par défaut si non-renseigné. Delete Selected Mixes? - Supprimer mixages sélectionnés ? + Supprimer les mixages sélectionnés ? @@ -5746,14 +5889,6 @@ Mixage actif par défaut si non-renseigné. Type de modèle: - - ModelsListWidget - - - No free slot available, cannot duplicate - Pas d'emplacement libre, impossible de dupliquer - - Module @@ -6001,256 +6136,256 @@ Mixage actif par défaut si non-renseigné. MultiModelPrinter - + General Model Settings Paramètres généraux - + Name: Nom: - + EEprom Size: Taille d'EEPROM: - + Timer%1: Chrono%1: - + Module%1: - + Module: - + Trainer port: Port écolage: - + Throttle Trim: Trim gaz: - + Trim Increment: Pas des trims: - + Center Beep: Bip de centrage: - + Helicopter Setup Réglage hélicoptère - + Swash Type: Type Cyclique: - + Swash Ring: Anneau Cyclique: - + Input Entrée - + Weight Ratio - + Long. cyc Cyc. longitudinal - + Lateral cyc Cyc. latéral - + Collective Source du pas collectif - + Flight modes Phases de vol - - + + Flight mode Phase de vol - + Switch Inter - + Fade IN Fondu en entrée - + Fade OUT Fondu en sortie - - + + FM%1 PV%1 - - + + GV%1 VG%1 - + RE%1 - + Limits Limites - + Channel Voie - + Name Nom - - + + Offset Décalage - + Min - + Max - + Invert Inversé - + Global Variables Variables globales - + Inputs Entrées - + Mixers Mixages - + CV%1 CB%1 - + Curves Courbes - + L%1 - + Logical Switches Inters logiques - + SF%1 FS%1 - + Special Functions Fonctions spéciales - + Telemetry Settings Paramètres de télémesure - + Analogs Analogiques - + Unit Unité - + Scale Echelle - + A%1 - + RSSI Alarms Alarmes RSSI - + Low Alarm Alarme basse - + Critical Alarm Alarme critique @@ -6301,22 +6436,22 @@ Mixage actif par défaut si non-renseigné. MultirotorPage - + Throttle Channel: Voie des gaz: - + Yaw Channel: Voie du lacet: - + Pitch Channel: Voie du tangage: - + Roll Channel: Voie du roulis: @@ -6324,17 +6459,17 @@ Mixage actif par défaut si non-renseigné. OptionsPage - + Throttle Cut Coupure de gaz - + Throttle Timer Chrono de gaz - + Flight Timer Chrono de vol @@ -6441,42 +6576,42 @@ Mixage actif par défaut si non-renseigné. Sel.Rot. E - + Trainer Écolage - + Trainer RUD Écolage Direction - + Trainer ELE Écolage Profondeur - + Trainer THR Écolage Gaz - + Trainer AIL Écolage Ailerons - + Instant Trim Trims instantanés - + Play Sound Jouer Son - + Haptic Vibreur @@ -6682,102 +6817,102 @@ Mixage actif par défaut si non-renseigné. Trim 6 Haut - + One Un - + a>x - + a<x - + |a|>x - + |a|<x - + AND ET - + OR OU - + XOR OUX - + a=b - + a!=b - + a>b - + a<b - + a>=b - + a<=b - + d>=x - + |d|>=x - + a=x - + a~x - + Timer Chrono - + Sticky Bistable @@ -6813,77 +6948,77 @@ Mixage actif par défaut si non-renseigné. - + Unknown Inconnu - + SD Logs Logs SD - + played once, not during startup !1x Lu une fois, mais pas à la mise en route - + repeat(%1s) Répéter chaque %1s - + DISABLED DESACTIVE - + INV - + NOR - + Reset Remise à zéro - + Set Timer %1 Définir chrono %1 - + Vario - + Volume - + Play Value Lire valeur - + Backlight Rétroéclairage - + Play Track Jouer fichier - + --- @@ -6975,64 +7110,64 @@ Mixage actif par défaut si non-renseigné. 1x Lu une fois - + Play Both Jouer les 2 - + Override %1 Remplacer %1 - + Play Script Exécuter script - + Screenshot Capture d'écran - + Background Music Musique de fond - + Background Music Pause Pause musique de fond - + Edge Flanc - - - + + + <font color=red><b>Inconsistent parameter</b></font> <font color=red><b>Paramètre inconsistant</b></font> - + Telemetry Télémesure - + Value Valeur - + Decr: Décr: - + Incr: Incr: @@ -7067,7 +7202,7 @@ Mixage actif par défaut si non-renseigné. Incrément - + Flight Vol @@ -7114,42 +7249,42 @@ Mixage actif par défaut si non-renseigné. -VG%1 - + Adjust GV%1 Ajuster VG%1 - + SetFailsafe Int. Module Déf. failsafe module interne - + SetFailsafe Ext. Module Déf. failsafe module externe - + RangeCheck Int. Module Test portée module interne - + RangeCheck Ext. Module Test portée module externe - + Bind Int. Module Bind module interne - + Bind Ext. Module Bind module externe - + Rotary Encoder Sélecteur Rotatif @@ -7239,7 +7374,7 @@ Mixage actif par défaut si non-renseigné. - + ---- @@ -7273,13 +7408,13 @@ Mixage actif par défaut si non-renseigné. - + V - + s @@ -7435,32 +7570,33 @@ Mixage actif par défaut si non-renseigné. GZt - + + ??? - + Diff(%1) - + Expo(%1) - + Function(%1) Fonction(%1) - + Curve(%1) Courbe(%1) - + !Curve(%1) !Courbe(%1) @@ -7624,14 +7760,14 @@ Mixage actif par défaut si non-renseigné. - + REa - + REb @@ -7648,7 +7784,7 @@ Mixage actif par défaut si non-renseigné. - + Timer3 Chrono 3 @@ -7775,68 +7911,58 @@ Mixage actif par défaut si non-renseigné. - + ON - + OFF - - + + Support for frsky telemetry mod Support de la télémétrie FrSky - - + + Support for jeti telemetry mod Support de la télémétrie JETI - - + + Support for receiving ardupilot data Support de la télémétrie ARDUPILOT - - + + Support for receiving NMEA data Support de la télémétrie NMEA - + Support for telemetry easy board Support de la carte TelemetrEZ - - + + Support for MAVLINK devices Support du protocole MAVLINK - + Rotary Encoder use in menus navigation Utiliser le sélecteur rotatif pour la navigation - - - - - - - - Enable heli menu and cyclic mix support - Activer le menu hélico et les mixages CCPM - @@ -7844,6 +7970,16 @@ Mixage actif par défaut si non-renseigné. + Enable heli menu and cyclic mix support + Activer le menu hélico et les mixages CCPM + + + + + + + + Enable TEMPLATES menu Inclure les gabarits @@ -7893,102 +8029,107 @@ Mixage actif par défaut si non-renseigné. - + + Enable bindings options + Activer les options de Bind (désactiver la télémétrie pour les XSR, etc...) + + + KS108 LCD - + WTV20 voice module Module voix WTV20 - + JQ6500 voice module Module voix JQ6500 - + FrSky Taranis X9D+ - + FrSky Taranis X9D - + Horus gimbals installed (Hall sensors) Manches à effet HALL de Horus installés - + FrSky Taranis X7 - + FrSky Horus - + Use ONLY with first DEV pcb version Exclusivement pour les Horus DEV - + Turnigy 9XR-PRO - + Turnigy 9XR with m128 chip Turnigy 9XR avec une puce m128 - - - - + + + + No splash screen Pas d'écran de démarrage - - - - - - - - Disable curves menus - Désactiver le menu des courbes - - - Support for radio modified with regular speaker - Haut-parleur au lieu du buzzer d'origine + + + Disable curves menus + Désactiver le menu des courbes - - Used if you have modified your radio with voice mode - Support du module vocal + + Support for radio modified with regular speaker + Haut-parleur au lieu du buzzer d'origine - + + Used if you have modified your radio with voice mode + Support du module vocal + + + + + + + Used if you have modified your radio with haptic mode Support du vibreur @@ -7998,30 +8139,30 @@ Mixage actif par défaut si non-renseigné. Positions de voies affichées en µs - - - - - - - - - + + + + + + + + + Battery graph Graphique de batterie - - - - - - - - - - - + + + + + + + + + + + Use alternative SQT5 font Utiliser la police alternative SQT5 @@ -8036,12 +8177,12 @@ Mixage actif par défaut si non-renseigné. Mode FAI (télémétrie désactivée) toujours actif - + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) Le port USB connecte les disques virtuels au lieu du Joystick (comme dans le bootloader) - + Instead of Joystick emulation, USB connection is Command Line Interface Le port USB est utilisé pour un port série avec interface par ligne de commande au lieu du Joystick @@ -8051,111 +8192,111 @@ Mixage actif par défaut si non-renseigné. Masque le protocole D8. Légalement obligatoire sur les radios Européennes importées après le 1er janvier 2015 - - + + Support for PPM internal module hack Support du remplacement du module interne par un module PPM - + ST7565P LCD or compatible ST7565P LCD ou compatible - + ST7565R LCD or compatible ST7565R LCD ou compatible - + ERC12864FSF LCD LCD ERC12864FSF - + ST7920 LCD LCD ST7920 - - - - + + + + Enable the throttle trace in Statistics Activer l'historique du manche des gaz dans les statistiques - + EEprom write progress bar Barre de progression pour l'écriture de l'EEPROM - - + + No Winged Shadow How High support Supprimer le support du variomètre Winged Shadow How High - + Turnigy 9XR - - + + No vario support Supprimer la fonction variomètre audio - - + + No GPS support Supprimer le support du GPS - - + + No gauges in the custom telemetry screen Supprimer l'affichage des valeurs de télémesure par barres - + 9X with stock board 9X avec carte mère d'origine - + Allow compensating for offset errors in FrSky FAS current sensors Permettre la compensation d'un décalage des capteurs de courant FASxx FrSky - - + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) Ajoute le support de l'inversion des manches (nécessaire pour l'utilisation de manches FrSky) - + DIY MEGA2560 radio - + Power management by soft-off circuitry Gestion alim. par software - + FrSky Taranis X9E - + Confirmation before radio shutdown Confirmation avant l'arrêt de la radio - + Haptic module installed Module vibreur installé @@ -8165,8 +8306,8 @@ Mixage actif par défaut si non-renseigné. Support des scripts Lua - - + + Support of FrSky PXX protocol Support du protocole PXX FrSky @@ -8181,42 +8322,42 @@ Mixage actif par défaut si non-renseigné. Supprimer le support des variables globales - - - - - - Support for DSM2 modules - Support du protocole DSM2 - - + - - + Support for DSM2 modules + Support du protocole DSM2 + + + + + + + + PPM center adjustment in limits Neutres PPM ajustables - - - - - - + + + + + + Symetrical Limits Limites symétriques - - - - - - - + + + + + + + Pots use in menus navigation Support de la navigation dans les menus avec les POTS @@ -8226,112 +8367,99 @@ Mixage actif par défaut si non-renseigné. Désactive la fonction spéciale "Remplacer VOIEx" - - - - - - - - - + + + + + + + + + No flight modes Pas de phases de vol - - + + SmartieParts 2.2 Backlight support Support du rétroéclairage pour la carte SmartieParts 2.2 - - - - - - - Enable resetting values by pressing up and down at the same time - Permet la remise à zéro des valeurs en pressant haut-bas en même temps, valeur min avec gauche/bas, valeur max avec haut/droite, inversion avec gauche/droite - - - - - + Enable resetting values by pressing up and down at the same time + Permet la remise à zéro des valeurs en pressant haut-bas en même temps, valeur min avec gauche/bas, valeur max avec haut/droite, inversion avec gauche/droite + + + + + + + + + + + No graphical check boxes and sliders Pas de cases à cocher et de curseurs graphiques - - - - - - - - - + + + + + + + + + Don't use bold font for highlighting active items Ne pas mettre les lignes actives en gras - - - - - + + + + + EEprom write Progress bar Barre de progression affichée lors des écritures EEPROM - - - - - - + + + + + + Imperial units Unités Impériales - - - + + + Bluetooth interface Interface Bluetooth - - - - - - - - - + + + + + + + + + Global variables Variables globales - - - - - - - - - - - In model setup menus automatically set source by moving the control - Sélectionner les sources des mixeurs en bougeant le contrôle désiré - @@ -8342,58 +8470,71 @@ Mixage actif par défaut si non-renseigné. + In model setup menus automatically set source by moving the control + Sélectionner les sources des mixeurs en bougeant le contrôle désiré + + + + + + + + + + + In model setup menus automatically set switch by moving the control Sélectionner les interrupteurs en bougeant le contrôle désiré - + 9X with stock board and m128 chip Carte 9x avec un chip m128 - + 9X with AR9X board 9X avec carte AR9X - + 9X with Sky9x board 9X avec carte Sky9x - + 9X with Gruvin9x board 9X avec carte Gruvin9x - - + + Support for SD memory card Support de la carte SD - + Support for DSM2 modules using ppm instead of true serial Support pour les modules DSM2 par le signal PPM - - - + + + Enable HELI menu and cyclic mix support Activer le menu hélico et les mixages CCPM - + Timer1 Chrono 1 - + Timer2 Chrono 2 @@ -8530,8 +8671,8 @@ The OpenTX Team. L'équipe OpenTX. - - + + @@ -8539,12 +8680,12 @@ L'équipe OpenTX. Erreur de synchronisation - + No SD directory configured! Aucun dossier SD configuré ! - + No Radio connected! Aucune radio connectée ! @@ -8649,7 +8790,7 @@ L'équipe OpenTX. Amp. Positive - + Models Translators do NOT use accent for this, this is the default category name on Horus. @@ -9167,17 +9308,17 @@ E RudderPage - + No Non - + Yes Oui - + <br>Rudder Channel: <br>Voie de dérive: @@ -9362,7 +9503,7 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo SimpleTailPage - + Elevator Channel: Voie de profondeur: @@ -10081,17 +10222,17 @@ La valeur par défaut est configurée dans le profil radio sélectionné. TailPage - + Rudder Channel: Voie de dérive: - + Elevator Channel: Voie de profondeur: - + Only one channel still available!<br>You probably should configure your model without using the wizard. Plus qu'une seule voie de disponible !<br>Vous devriez peut-être configurer ce modèle sans l'assistant. @@ -10099,22 +10240,22 @@ La valeur par défaut est configurée dans le profil radio sélectionné. TailSelectionPage - + Elevator and Rudder Profondeur et Dérive - + Only Elevator Profondeur uniquement - + V-tail Empennage en V - + Tail Type: Type d'empennage: @@ -11409,17 +11550,17 @@ hh:mm:ss ThrottlePage - + Yes Oui - + No Non - + <br>Throttle Channel: <br>Voie des gaz: @@ -11609,17 +11750,17 @@ Extra long : bips extra longs. TreeModel - + Index - + Name Nom - + Size Taille @@ -11627,12 +11768,12 @@ Extra long : bips extra longs. VTailPage - + First Tail Channel: Première voie d'empennage: - + Second Tail Channel: Deuxième voie d'empennage: @@ -11683,12 +11824,12 @@ Extra long : bips extra longs. WingtypeSelectionPage - + Standard Wing Aile standard - + Flying Wing / Deltawing Aile delta @@ -11970,37 +12111,37 @@ Extra long : bips extra longs. WizardPrinter - + Plane Avion - + Multicopter Multicoptère - + Helicopter Hélicoptère - + Model Name: Nom du modèle: - + Model Type: Type de modèle: - + Options: - + Channel %1: Voie %1: @@ -12222,7 +12363,7 @@ m2560 for v4.1 boards Transmitter Splash Screen Editor - Editeur d'écran d'accueil + Éditeur d'écran d'accueil From 78c5bf1ec2cee1dc1145a7c211483fd037d81941 Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Thu, 13 Apr 2017 12:11:30 +0200 Subject: [PATCH 124/203] Fix high dpi on Windows --- companion/src/companion.cpp | 8 +++++--- companion/src/simulator.cpp | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/companion/src/companion.cpp b/companion/src/companion.cpp index 4be914d1d..7519ff054 100644 --- a/companion/src/companion.cpp +++ b/companion/src/companion.cpp @@ -50,14 +50,16 @@ class MyProxyStyle : public QProxyStyle int main(int argc, char *argv[]) { +#if (QT_VERSION >= QT_VERSION_CHECK(5, 6, 0)) + /* From doc: This attribute must be set before Q(Gui)Application is constructed. */ + QApplication::setAttribute(Qt::AA_EnableHighDpiScaling); +#endif + QApplication app(argc, argv); app.setApplicationName(APP_COMPANION); app.setOrganizationName(COMPANY); app.setOrganizationDomain(COMPANY_DOMAIN); app.setAttribute(Qt::AA_DontShowIconsInMenus, false); -#if (QT_VERSION >= QT_VERSION_CHECK(5, 6, 0)) - app.setAttribute(Qt::AA_EnableHighDpiScaling); -#endif Q_INIT_RESOURCE(companion); diff --git a/companion/src/simulator.cpp b/companion/src/simulator.cpp index 5da404801..559318ec7 100644 --- a/companion/src/simulator.cpp +++ b/companion/src/simulator.cpp @@ -71,13 +71,15 @@ void sharedHelpText(QTextStream &stream) int main(int argc, char *argv[]) { +#if (QT_VERSION >= QT_VERSION_CHECK(5, 6, 0)) + /* From doc: This attribute must be set before Q(Gui)Application is constructed. */ + QApplication::setAttribute(Qt::AA_EnableHighDpiScaling); +#endif + QApplication app(argc, argv); app.setApplicationName(APP_SIMULATOR); app.setOrganizationName(COMPANY); app.setOrganizationDomain(COMPANY_DOMAIN); -#if (QT_VERSION >= QT_VERSION_CHECK(5, 6, 0)) - app.setAttribute(Qt::AA_EnableHighDpiScaling); -#endif Q_INIT_RESOURCE(companion); From 70c837f9f0e831cd7b3cd6193337bcdf23efec72 Mon Sep 17 00:00:00 2001 From: Jacek Drewniak Date: Thu, 13 Apr 2017 18:31:33 +0200 Subject: [PATCH 125/203] Driver33/pl translation (#4785) * partial pl translation * pl partial translation * partial pl translation * partial pl translation * pl translation changes * pl translation changes --- companion/src/translations/companion_pl.ts | 3930 +++++++++++--------- 1 file changed, 2080 insertions(+), 1850 deletions(-) diff --git a/companion/src/translations/companion_pl.ts b/companion/src/translations/companion_pl.ts index 29dcfcba5..bdc3e2999 100644 --- a/companion/src/translations/companion_pl.ts +++ b/companion/src/translations/companion_pl.ts @@ -4,27 +4,27 @@ AileronsPage - + No Nie - + Yes, controlled by a single channel Tak, kontrolowane przez 1 kanał - + Yes, controlled by two channels Tak, kontrolowane przez 2 kanały - + <br>First Aileron Channel: <br> Pierwszy kanał lotek: - + Second Aileron Channel: Drugi kanał lotek: @@ -32,27 +32,27 @@ AirbrakesPage - + No Nie - + Yes, controlled by a single channel Tak, kontrolowane przez 1 kanał - + Yes, controlled by two channels Tak, kontrolowane przez 2 kanały - + <br>First Airbrake Channel: <br> Pierwszy kanał hamulców: - + Second Airbrake Channel: Drugi kanał hamulców: @@ -60,42 +60,42 @@ AppPreferencesDialog - + Edit Settings Edycja Ustawień - + Radio Profile Profil radia - + Default Channel Order Bazowa kolejność kanałów - + Build Options Opcje kompilacji - + Menu Language Język Menu - + Default Stick Mode Bazowy mod drążków - + Select Image Wybierz obrazek - + Mode selection: Mode 1: @@ -118,462 +118,476 @@ Mode 4: - + Mode 1 (RUD ELE THR AIL) Mod 1 (SK.SW.Gaz.Lot) - + Mode 2 (RUD THR ELE AIL) Mod 2 (SK.Gaz.SW.Lot) - + Mode 3 (AIL ELE THR RUD) Mod 2 (Lot.SW.Gaz.SK) - + Mode 4 (AIL THR ELE RUD) Mod 4 (Lot.Gaz.SW.SK) - + Splash Screen Ekran startowy - - + + The profile specific folder, if set, will override general Backup folder Katalog profili, jeśli ustawiony zmieni główny katalog backupów - + Backup folder Katalog Backupów - + If set it will override the application general setting Jeśli ustawione, nadpisze główne ustawienia aplikacji - + if set, will override general backup enable Jeśli ustawione, nadpisze główne ustawienia backupów - + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> <html><head/><body><p>Kolejność kanałów</p><p><br/></p><p>Definiuje kolejność standardowych mikserów dla nowego modelu.</p></body></html> - + R E T A K W G L - + R E A T K W L G - + R T E A K G W L - + R T A E K G L W - + R A E T K L W G - + R A T E - + E R T A W K G L - + E R A T W K L G - + E T R A W G K L - + E T A R W G L K - + E A R T W L K G - + E A T R W L G K - + T R E A G K W L - + T R A E G K L W - + T E R A G W K L - + T E A R G W L K - + T A R E G L K W - + T A E R G L W K - + A R E T L K W G - + A R T E L R G W - + A E R T L W K G - + A E T R L W G K - + A T R E L G K W - + A T E R L G W K - - - - - + + + + + Select Folder - + Wybierz Folder - + Select Executable - + Wybierz EXE - + Use OpenTX firmware nightly builds Użyj Firmware OpenTX w wersji Nightbuilds - + Use Companion nightly builds Użyj Companion w wersji Nightbuilds - + Simulator Volume Gain Głośność symulatora - + Profile Name Nazwa profilu - - Remove Profile - Usuń Profil - - - + Clear Image Wyczyść obrazek - + Append version number to FW file name Dodaj numer Firmware do nazwy pliku - + Offer to write FW to Tx after download Zaproponuj zapisanie Firmware do radia po pobraniu - + Radio Type Typ Radia - + Set voice language. May be different from firmware language Ustaw język komunikatów głosowych. Może być różny od języka firmware - + Other Settings Inne ustawienia - + General Settings Główne ustawienia - + SD Structure path Struktura karty SD - + Voice Language Język komunikatów - + Application Settings Ustawienia Aplikacji - + Show splash screen when Companion starts Pokaż ekran startowy przy uruchamianiu Companion - + Automatic check for Companion updates Automatycznie sprawdź aktualizacje Companion - - + + Enable automatic backup before writing firmware Uaktywnij automatyczny backup przed zapisem firmware - + Automatic check for OpenTX firmware updates Automatycznie sprawdź aktualizacje firmware OpenTX - + Splash Screen Library Biblioteka ekranów startowych - + Files to keep Pliki do zapamiętania - + Google Earth Executable Plik wykonywalny Google Earth - + Only show user splash images Pokaż tylko ekrany startowe użytkownika - + Show user and companion splash images Pokaż ekrany startowe użytkownika i Companion - + User Splash Screens Użyj ekranu startowego - + Automatic Backup Folder Automatyczny Katalog Backupów - Use model wizard when creating a new model - Użyj konfiguratora do stworzenia nowego modelu + Użyj konfiguratora do stworzenia nowego modelu - + Simulator Settings Ustawienia Symulatora - + Simulator BackLight Podświetlenie symulatora - + Enable Aktywuj - + + Action on New Model + Akcje na nowym modelu + + + + <html><head/><body><p>This option maintains the behaviour from older OpenTx versions where empty model slots are preserved when a model is deleted or moved. </p><p>When this option is de-selected, the other models may be re-arranged to fill the gap left by the removed model.</p></body></html> + <html><head/><body><p>This option maintains the behaviour from older OpenTx versions where empty model slots are preserved when a model is deleted or moved. </p><p>When this option is de-selected, the other models may be re-arranged to fill the gap left by the removed model.</p></body></html> + + + + Remove empty model slots when deleting models (only applies for radios w/out categories) + Usuń puste sloty modeli gry kasujesz modele (dziala tylko z radiem bez kategori) + + + + Use model wizard + Użyj kreatora modelu + + + + Open model editor + Otwórz edytor modelu + + + + Just create the model + TYlko utwórz model + + + Blue Niebieskie - + Green Zielone - + Red Czerwone - + Orange Pomarańczowe - + Yellow Żółte - + Joystick Joystick - + Calibrate Kalibracja - + Simulator capture folder Katalog zapisu symulatora - + Only capture to clipboard Zapisz tylko do schowka - + Remember simulator switch values Zapamiętaj ustawienia przełączników w symulatorze - + My Radio Moje Radio - + Select your snapshot folder Katalog zrzutów - - + + No joysticks found Brak joysticka - + EMPTY: No radio settings stored in profile PUSTY:Brak ustawień radia w profilu - + AVAILABLE: Radio settings of unknown age DOSTĘPNY:Nieznany wiek ustawień radia - + AVAILABLE: Radio settings stored %1 DOSTĘPNY:Zapamiętane ustawienia radia %1 - + Select your library folder Wybierz katalog biblioteki - - + + Select your Models and Settings backup folder Wybierz folder do backupowania Modeli i Ustawień - + Select Google Earth executable Wybierz wykonywalny plik Google Earth - + Select the folder replicating your SD structure Wybierz folder do zreplikowania struktury Twojej karty SD - - Not possible to remove profile - Usunięcie profilu jest niemożliwe - - - - The default profile can not be removed. - Podstawowy profil nie może być usunięty. - - - + Open Image to load Otwórz obrazek do załadowania - + Images (%1) Obrazki (%1) @@ -603,7 +617,7 @@ Może być różny od języka firmware CH%1 - Kan %1 + Kan %1 @@ -641,12 +655,12 @@ Może być różny od języka firmware files - + Pliki Radio and Models settings - + Ustawienia Radia i Modeli @@ -657,42 +671,54 @@ Może być różny od języka firmware Porównaj modele - Drag first model here - Przeciągnij tutaj pierwszy model + Przeciągnij tutaj pierwszy model - Drag second model here - Przeciągnij tutaj drugi model + Przeciągnij tutaj drugi model - + + To compare models, drag and drop them anywhere in this window. + Aby porównaćmodele przeciąnij i upuść je gdziekowiek do tego okna. + + + Close Zamknij - + Print Drukuj - + Print to file Drukuj do pliku - No name - Model bez nazwy + Model bez nazwy - + + Unnamed Model %1 + Nienazwany Model %1 + + + + Click to remove this model. + Klinij by usunąć ten model. + + + Print Document Drukuj dokument - + Select PDF output file Wybierz plik docelowy PDF @@ -700,7 +726,7 @@ Może być różny od języka firmware ConclusionPage - + OK, I understand. OK, Rozumiem. @@ -1041,22 +1067,22 @@ Może być różny od języka firmware CyclicPage - + 90 90 - + 120 120 - + 120x 120x - + 140 140 @@ -1071,169 +1097,170 @@ Może być różny od języka firmware <html><head/><body><p>Enable or disable the filter. If the button won't stay enabled, it is likely there is a syntax error in the Regular Expression entered.</p></body></html> - + <html><hrad/><body><p>Włącz lub wyłącz filtr. Jeśli przycisk nie będzie aktywny to znaczy że jest błąd składni we wprowadzonym wyrażeniu regularnym.</p></body></html> Filter: - + Filtr: <html><head/><body><p>Enter filter text here. Click the help/info button for details about using the filter. </p><p> To <b>remove a remembered entry</b> from the filter list, first choose it, and then press <code>Shift-Delete</code> (or <code>Shift-Backspace</code>) key combination.</p></body></html> - + <html><head/><body><p>Wpisz teks filtru tutaj. Kliknij przycisk. pomoc/info w celu uzyskania szczegółów użycia filtra.</p><p> +W celu <b>usunięcia filtru</b> z listy, najpierw wybierz go, a nastepnie użyj kombinacji klawiszy <code>Shift-Delete</code> (lub <code>Shift-Backspace</code>).</p></body></html> Buffer: - + Bufor: Number of lines to keep in display. - + Ilość linii trzymanej na wyświetlaczu. Filter &Help - + &Pomoc Filtra Show information about using the filter. - + Pokaż informacje jak uzywać filtra. Word &Wrap - + Podział &Słowa Toggle word wrapping on/off. - + Przełącz dzielenie słowa on/off. &Clear - + &Wyczyść Clear the output window of all text. - + Wyczyść tekst z okna. Enable &Filter - + Włącz &Filtr Turn the filter on/off. - + Przełącz filtr on/off. - + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> - + <html><head><style>kbd {background-color: palette(alternate-base); font-size: large; white-space: nowrap;}</style></head><body><p>The filter supports two syntax types: basic matching with common wildcards as well as full Perl-style (<code>pcre</code>) Regular Expressions.</p><p>By default a filter will only show lines which match (<b>inclusive</b>). To make an <b>exclusive</b> filter which removes matching lines, prefix the filter expression with a <kbd>!</kbd> (exclamation mark).</p><p>To use <b>Regular Expressions</b> (RegEx), prefix the filter text with a <kbd>/</kbd> (slash) or <kbd>^</kbd> (up caret). <ul><li>Put the <kbd>/</kbd> or <kbd>^</kbd> after the exclusive <kbd>!</kbd> indicator if you're using one.</li><li>By default the match is case-sensitive. To make it insensitive, add the typical <kbd>/i</kbd> (slash i) operator at the end of your RegEx.</li><li>If you use a caret (^) to denote a RegEx, it will become part of the Reg. Ex. (that is, matches from start of line).</li><li>If the RegEx is invalid, the filter edit field should show a red border and you will not be able to enable the filter.</li><li>A useful resource for testing REs (with a full reference) can be found at <a href="http://www.regexr.com/">http://www.regexr.com/</a></li></ul></p><p>To use <b>basic matching</b> just type any text.<ul><li>Wildcards: <kbd>*</kbd> (asterisk) matches zero or more of any character(s), and <kbd>?</kbd> (question mark) matches any single character.</li><li>The match is always case-insensitive.</li><li>The match always starts from the beginning of a log line. To ignore characters at the start, use a leading <kbd>*</kbd> wildcard.</li><li>A trailing <kbd>*</kbd> is always implied (that is, matches anything to the end of the log line). To avoid this, use a RegEx.</li><li>You can match literal wildcard characters by prefixing them with a <kbd>\</kbd> (backslash) character (eg. "foo\*bar" matches "foo*bar").</li></ul></p><p>After <b>editing text</b>, press ENTER or TAB key (or click anywhere outside the box) to update the filter.</p><p>To <b>remove an entry</b> from the filter selector list, first choose it, and while in the line editor press <kbd>Shift-Delete</kbd> (or <kbd>Shift-Backspace</kbd>) key combination. The default filters cannot be removed. Up to 50 filters are stored.</p></body></html> - + Debug Console Filter Help - + Debug Konsola Filtr Help EepromInterface - + Possible causes for this: Możliwe przyczyny tego: - + - Eeprom is from a newer version of OpenTX - Eeprom jest z nowszej wersji OpenTX - + - Eeprom is not from OpenTX - Eeprom nie jest z OpenTX - + - Eeprom is not from Th9X - Eeprom nie jest z Th9X - + - Eeprom is not from Gruvin9X - Eeprom nie jest z Gruvin9X - + - Eeprom is not from ErSky9X - Eeprom nie jest z ErSky9X - + - Eeprom is not from Er9X - Eeprom nie jest z Er9X - + - Eeprom size is invalid - Nieprawidłowa wielkość Eeproma - + - Eeprom file system is invalid - Błedny system plików Eeproma - + - Eeprom is from a unknown board - Eeprom z nieznanej płyty - + - Eeprom is from the wrong board - Eeprom ze złej płyty - + - Eeprom backup not supported - Backup Eepromu nieobsługiwany - + - Something that couldn't be guessed, sorry - Coś czego nie można odgadnąć, przepraszam - + Warning: Ostrzeżenie: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - Twoje radio prawdopodobnie używa złego firmware, wielkość eepromu to 4096 ale tylko pierwsze 2048 jest użyte - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - Twój eeprom jest ze starej wersji OpenTX, Zupgraduj! Powinieneś 'zapisać jako' stary plik jako kopię zapasową. - + Warnings! Ostrzeżenia! @@ -1241,12 +1268,12 @@ Powinieneś 'zapisać jako' stary plik jako kopię zapasową. ElevonsPage - + <br>First Elevon Channel: <br> Pierwszy Kanał Sterolotek: - + Second Elevon Channel: Drugi Kanał Sterolotek: @@ -1370,43 +1397,43 @@ Jeśli puste linia jest uznawana za aktywną cały czas. Click to access popup menu - + Kliknij by uzyskać wyskakujące mene Clear All - + Wyczyść wszytko Set All - + Ustaw wszystko Invert All - + Odwróć wszytko FblPage - + Throttle Channel: Kanał gazu: - + Yaw Channel: Kanał odchylenia: - + Pitch Channel: Kanał pochylenia: - + Roll Channel: Kanał przechylenia: @@ -1459,27 +1486,27 @@ Może być różny od języka firmware FlapsPage - + No Nie - + Yes, controlled by a single channel Tak, kontrolowane przez 1 kanał - + Yes, controlled by two channels Tak, kontrolowane przez 2 kanały - + <br>First Flap Channel: <br> Pierwszy kanał klap: - + Second Flap Channel: Drugi kanał Klap: @@ -1515,7 +1542,7 @@ Może być różny od języka firmware <html><head/><body><p>Saves a dated copy of your eeprom to the backup folder you specified in the Companion settings before writing the current model to the radio.</p></body></html> - + <html><head/><body><p>Zapisuje datowaną kopię Twojego eepromu do folderu backupowego zdefiniowanego w Companion przed zapisem aktualnego modelu do radia.</p></body></html> @@ -1939,17 +1966,17 @@ W celu instalacji drivera użyj ZADIG. Name - Nazwa + Nazwa Value source - + Źródło wartości Value - Wartość + Wartość @@ -1964,17 +1991,17 @@ W celu instalacji drivera użyj ZADIG. &Clear - + &Clear Clear - Wyczyść + Wyczyść Clear all current Flight Mode properties? - + Wyczyścić wszystkie ustawienia Trybów Lotu ? @@ -1998,17 +2025,17 @@ W celu instalacji drivera użyj ZADIG. FlybarSelectionPage - + Has Flybar Posiada flaybar - + Flybarless Bez flybara - + Flybar: Flaybar: @@ -2180,7 +2207,7 @@ p, li { white-space: pre-wrap; } Radio settings - + Ustawinia radia @@ -2207,12 +2234,12 @@ Będą one obowiązywać dla wszystkich modeli w tym samym EEPROM-ie. Hardware - + Sprzęt Calibration - + Kalibracja @@ -2229,7 +2256,7 @@ Będą one obowiązywać dla wszystkich modeli w tym samym EEPROM-ie. Wrong data in profile, Switch/pot config not retrieved - + Błędne dane w profilu, Ustawienia przełączników/potencjometrów nie uzyskane @@ -2836,12 +2863,12 @@ p, li { white-space: pre-wrap; } Automatically adjust the radio's clock if a GPS is connected to telemetry. - + Dostrój automatycznie zegar radia jesli GPS jest podłączony do telemetri. Backlight OFF Brightness - + Jacność wyłączonego podświetlenia @@ -3065,17 +3092,17 @@ Jesteś pewien ? GyroPage - + No Nie - + Yes, controled by a switch Tak, kontrolowane przez przełącznik - + Yes, controlled by a pot Tak, kontrolowane przez potencjometr @@ -3085,52 +3112,52 @@ Jesteś pewien ? Form - Formularz + Formularz SQ - SQ + SQ SR - SR + SR LS2 - LS2 + LS2 SP - SP + SP SO - SO + SO S4 - S4 + S4 RS - + Prawy suwak SB - SB + SB PPM 2 - PPM 2 + PPM 2 @@ -3150,7 +3177,7 @@ Jesteś pewien ? 2 - Normal. 3 - Loud. 4 - Extra loud. - Głośność piknięć + Głośność piknięć 0 -Cicho. Żadnych piknięć. 1 - Bez przycisków. Normalne piknięcia ale bez pikania dla przycisków menu. @@ -3161,187 +3188,187 @@ Jesteś pewien ? OFF - Wyłącz + Wyłącz S-Port Mirror - Kopia S-Port + Kopia S-Port Telemetry - Telemetria + Telemetria SBUS Trainer - Trener SBUS + Trener SBUS Debug - Debugowanie + Debugowanie Rud - SK + SK PPM 3 - PPM 3 + PPM 3 S1 - Potencjometr 1 + Potencjometr 1 S2 - Potencjometr 2 + Potencjometr 2 S3 - S3 + S3 PPM 1 - PPM 1 + PPM 1 Serial Port - Port szeregowy + Port szeregowy v - V + V PPM Multiplier - Mnożnik PPM + Mnożnik PPM Current Offset - Aktuany ofset + Aktuany ofset PPM 4 - PPM 4 + PPM 4 SA - SA + SA Ele - SW + SW Ail - Lotki + Lotki Thr - Gaz + Gaz SC - SC + SC LS - + Lewy suwak SD - SD + SD Battery Offset - Ofset baterii + Ofset baterii SE - SE + SE SF - SF + SF SG - SG + SG SH - SH + SH SI - SI + SI SJ - SJ + SJ SK - SK + SK SL - SL + SL SM - SM + SM SN - SN + SN RS2 - RS2 + RS2 Bluetooth - Bluetooth + Bluetooth ADC Filter - + Filtr ADC @@ -3351,42 +3378,42 @@ Jesteś pewien ? None - + Brak 2 Positions Toggle - 2 Poz. Przełącznik chwilowy + 2 Poz. Przełącznik chwilowy 2 Positions - 2 Pozycje + 2 Pozycje 3 Positions - 3 Pozycje + 3 Pozycje Pot with detent - Potencj. z zapadką + Potencj. z zapadką Multipos switch - Przeł. wielopoz + Przeł. wielopoz Pot without detent - Potencjometr bez zapadki + Potencjometr bez zapadki Slider with detent - Suwak z zapadką + Suwak z zapadką @@ -3465,22 +3492,22 @@ Jesteś pewien ? HeliPage - + Throttle Channel: Kanał gazu: - + Yaw Channel: Kanał odchylenia: - + Pitch Channel: Kanał pochylenia: - + Roll Channel: Kanał przechylenia: @@ -3808,22 +3835,22 @@ Kolumny wysokości "GAlt" i prędkości "GSpd" są opcjonaln Cursor A: %1 m - + Wskaźnik A: %1 m Cursor B: %1 m - + Wskaźnik B: %1 m Time delta: %1 - + Delta czasu: %1 Climb rate: %1 m/s - + Wznoszenie: %1 m/s @@ -3874,553 +3901,662 @@ Kolumny wysokości "GAlt" i prędkości "GSpd" są opcjonaln MainWindow - - + + File loaded Plik załadowany - + Display previous warning again at startup ? Wyświetlić poprzednie ostrzeżenie przy uruchomieniu? - + Checking for updates Sprawdź aktualizacje - + Unable to check for updates. Nie mogę sprawdzić aktualizacji. - - + + Save As Zapisz jako - + Executable (*.exe) Wykonywalny (*.exe) - + New release available Dostępne jest nowe wydanie - - + + No updates available at this time. Brak aktualizacji dostępnych teraz. - + Would you like to launch the installer? Chcesz uruchomić instalator? - - + + Error Błąd - + Error opening file %1: %2. Błąd otwarcia pliku %1: %2. - + A new release of Companion is available, please check the OpenTX website! Nowe wydanie Companion jest dostępne, proszę sprawdzić stronę OpenTX! - + Compilation server too busy, try later Serwer kompilacji zbyt zajęty, spróbuj później - - - Compilation error - - - - - Invalid firmware - - - Invalid board - + Compilation error + Błąd kompilacji - Invalid language - + Invalid firmware + Błedne firmware + Invalid board + Błędna płyta główna + + + + Invalid language + Błedny język + + + Unknown server failure, try later Nieznany błąd serwera, spróbuj później - - + + Yes Tak - - + + No Nie - - + + Release Notes Informacje o wydaniu - - + + Do you want to download release %1 now ? Chcesz pobrać wydanie %1 teraz? - - Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. - + + Close + Zamknij - - + + Close Models and Settings file + Zamknij plik modeli i ustawień + + + + List of recently used files + Lista użytych plików + + + + Radio Profiles + Profile radia + + + + Create or Select Radio Profiles + Utwórz lub Wybierz Profile Radia + + + + Delete Current Radio Profile... + Skasuj Aktualny Profil Radia... + + + + Tabbed Windows + Zakładkowane okna + + + + Use tabs to arrange open windows. + Użyj zakładek do ustawienia otwartych okien. + + + + Tile Windows + Tytuł Okien + + + + Arrange open windows across all the available space. + Ustaw otwarte okna na całej dostępnej przestrzeni. + + + + Cascade Windows + Okna kaskadowo + + + + Arrange all open windows in a stack. + Ustaw wszytkie otwarte okna na stosie. + + + + Close All Windows + Zamknij wszytkie okna + + + + Closes all open files (prompts to save if necessary. + Zamknij wszystkie otwarte pliki (zapytaj by zapisać jeśli trzeba). + + + + Window + Okno + + + + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. + Część tekstów nie będzie przetłumaczona do następnego uruchomienia Comapnion. Zwróć uwagę ze część tłumaczeń może nie być dokończona. + + + + File saved Plik zapisany - + Firmware updates Aktualizacja firmware - + Current firmware does not provide release notes informations. Aktualny firmware nie zawiera opisu wydania. - + Models and Settings read - + Odczytaj Modele i Ustawienia - - + + This function is not yet implemented - + Funkcja niezaimplementowana jeszcze - + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> Projekt Companion odłączony z oryginalnego <a href='%1'>eePe</a> - + New Nowy - + Open... Otwórz... - + Save Zapisz - + Save As... Zapisz jako... - Copy Model - Kopiuj Model + Kopiuj Model - Paste Model - Wklej Model + Wklej Model - + About... O aplikacji... - Print... - Drukuj... + Drukuj... - Simulate... - Symulacja... + Symulacja... - Simulate current model - Symulacja aktualnego modelu + Symulacja aktualnego modelu - Alt+S - Alt+S + Alt+S - Load Backup... - Załaduj backup... + Załaduj backup... - + View Log File... Obejrzyj plik logów... - + Open and view log file Otwórz i obejrzyj plik logów - + Edit Settings Edycja Ustawień - + Settings... Ustawienia... - + Download firmware and voice files Pobierz firmware i pliki dźwiękowe - - Create a new Radio Setting Profile - Utwórz nowy Profil Ustawień Radia + + Ctrl+Shift+S + Ctrl+Shift+S - + + Ctrl+Alt+L + Ctrl+Alt+L + + + + Ctrl+Alt+D + Ctrl+Alt+D + + + + Ctrl+Alt+R + Ctrl+Alt+R + + + + Alt+%1 + Alt+%1 + + + + - Copy + - Skopiuj + + + + Not possible to remove profile + Usunięcie profilu jest niemożliwe + + + + The default profile can not be removed. + Podstawowy profil nie może być usunięty. + + + + Confirm Delete Profile + Potwierdź usunięcie profilu + + + + Are you sure you wish to delete the "%1" radio profile? There is no way to undo this action! + Jesteś pewien że chcesz wykasować profil radia %1? Nie ma możliwości cofnięcia tego działania! + + + + Copy Current Radio Profile + Kopiuj aktualny profil radia + + + Use default system language. - + Uzyj języja bazowego systemu. - + Use %1 language (some translations may not be complete). - + Użyj języka %1 (częsć tłumaczeń może być niekompletna). - + A monochrome black icon theme Monochromatyczny czarny wygląd ikon - + Do you want to write the firmware to the radio now ? Chcesz wgrać firmware do radia teraz? - + Ignore this release %1? Zignorować to wydanie %1? - - + + Open Models and Settings file Otwórz plik Modeli i Ustawień - + Read Models and Settings From Radio Wczytaj Modele i Ustawienia z radia - + Save Radio Backup to File Zapisz Backup radia do pliku - + Read Radio Firmware to File Odczytaj Firmware radia do pliku - + Create a new Models and Settings file Utwórz nowy plik Modeli i Ustawień - - + + Save Models and Settings file Zapisz plik Modeli i Ustawień - Cut Model - Wytnij Model + Wytnij Model - Cut current model to the clipboard - Wytnij aktualny model do schowka + Wytnij aktualny model do schowka - Copy current model to the clipboard - Wytnij aktualny model do schowka + Wytnij aktualny model do schowka - Paste model from clipboard - Wklej Model ze schowka + Wklej Model ze schowka - + The classic companion9x icon theme Klasyczny zestaw ikon Companion - + A monochrome white icon theme Monochromatyczny biały wygląd ikon - + A monochrome blue icon theme Monochromatyczny niebieski wygląd ikon - + Small Małe - + Use small toolbar icons Użyj małych ikon paska narzędzi - + Use normal size toolbar icons Użyj normalnych ikon paska narzędzi - + Normal Normalne - + Use big toolbar icons Użyj dużych ikon paska narzędzi - + Big Duże - + Use huge toolbar icons Użyj olbrzymich ikon paska narzędzi - + Huge Olbrzymie - + Edit Radio Splash Image... Edytor ekranu startowego radia... - + Edit the splash image of your Radio Edytuj ekran startowy swojego radia - - + + Read Firmware from Radio Odczytaj Firmware z radia - + Read firmware from Radio Odczytaj Firmware z radia - + Write Firmware to Radio Zapisz firmware do radia - + Write firmware to Radio Zapisz firmware do radia - + Write Models and Settings To Radio Zapisz Modele i Ustawienia do radia - + Write Models and Settings to Radio Zapisz Modele i Ustawienia do radia - - + + Read Models and Settings from Radio Wczytaj Modele i Ustawienia z radia - + Configure software for communicating with the Radio Ustaw oprogramowanie komunikacyjne z radiem - + Write Backup to Radio Zapisz Backup do radia - + Backup Radio to File Zbackupuj radio do pliku - + Save a complete backup file of all settings and model data in the Radio Zachowaj kompletny plik backup wszystkich ustawień i danych modeli z radia - + Recent Files Ostatnie Pliki - Show recent Models+Settings documents - Pokaż ostatnie dokumenty Modeli i Ustawień + Pokaż ostatnie dokumenty Modeli i Ustawień - Print current model - Drukuj aktualny model + Drukuj aktualny model - + Check OpenTX and Companion updates Sprawdź aktualizacje OpenTX i Companion - + Fuses... Bezpieczniki... - + Manuals and other Documents Podręcznik i dokumentacja - + Open the OpenTX document page in a web browser Otwórz stronę dokumentacji OpenTX w przeglądarce - + A tribute to those who have contributed to OpenTX and Companion Hołd dla tych, którzy przyczynili się do rozwoju OpenTX i Companion - + Contributors... Współpracownicy... - Recent Models+Settings - Ostatnie Modele+Ustawienia + Ostatnie Modele+Ustawienia - + Set Icon Theme Ustaw wygląd ikon - + Set Icon Size Ustaw wielkość ikon - + A new version of Companion is available (version %1)<br>Would you like to download it? Dostępna jest nowy Companion (wersja %1)<br>Chcesz ją pobrać ? - + The new theme will be loaded the next time you start Companion. Wybrany wygląd będzie użyty po ponownym uruchomieniu Comapnion. - The icon size will be used the next time you start Companion. - Wybrana wielkość ikon będzie użyta po ponownym uruchomieniu Comapnion. + Wybrana wielkość ikon będzie użyta po ponownym uruchomieniu Comapnion. - + OpenTX Home Page: <a href='%1'>%1</a> Strona domowa OpenTX: <a href='%1'>%1</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> Jeśli uważasz, że ten program jest użyteczny, wesprzyj poprzez <a href='%1'>donację</a> - + About Companion O aplikacji Companion - Load backup from file - Załaduj backup z pliku + Załaduj backup z pliku - + Exit Zakończ - + Firmware %1 does not seem to have ever been downloaded. Release %2 is available. Do you want to download it now? @@ -4433,7 +4569,7 @@ Czy chcesz teraz je pobrać? Zalecamy przeczytanie informacji o wydaniu (przycisk poniżej) w celu poznania zmian które mogą być istotne dla Ciebie. - + A new version of %1 firmware is available: - current is %2 - newer is %3 @@ -4449,219 +4585,234 @@ Czy chcesz teraz pobrać ? Zalecamy przeczytanie informacji o wydaniu (przycisk poniżej) w celu poznania zmian które mogą być istotne dla Ciebie. - - - + + Companion Companion - - + + Synchronize SD Zsynchronizuj kartę pamięci - + OpenTX Companion %1 - Radio: %2 - Profile: %3 OpenTX Companion %1 - Radio: %2 - Profil: %3 - + Monochrome Monochromatyczny - + MonoWhite Mono-Biały - + MonoBlue Mono-Niebieski - + System language Język systemu - + Download... Pobieranie... - + Check for Updates... Sprawdź aktualizacje... - + Companion Changes... Zmiany w Companion... - + Show Companion change log Pokaż log zmian Companion - + Firmware Changes... Zmiany w Firmware... - + Show firmware change log Pokaż log zmian Firmware - + Compare Models... Porównaj modele... - + List programmers... Lista programistów... - + Add Radio Profile Dodaj profil radia - + Configure Communications... Ustaw komunikację... - + Yerico - + Yellow round honey sweet icon theme Żółty zaokrąglony miodowy motyw ikon - - Radio Profile - Profil radia + Profil radia - + Write Zapis - + %2 %2 - + Compare models Porównaj modele - + Exit the application Zakończ aplikację companion9x - + List available programmers Lista dostępnych programatorów - + Show fuses dialog Pokaż okno ustawień mikro-kontrolera - + Show the application's About box O aplikacji companion9x - + Copyright OpenTX Team Prawa Zespół OpenTX - + Classical Klasyczny - + Write Backup from file to Radio Zapisz Backup z pliku do radia - + Not enough flash available on this board for all the selected options - + Ta platforma posiada za mało pamięci flash dla wybranych opcji - + Compilation server temporary failure, try later - + Serwer kompilacji czasowo niesprawny, spróbuj później - + SD card synchronization Synchronizacja karty SD - + + Create a new Radio Settings Profile + Utwórz nowy Profil Ustawień Radia + + + + Duplicate current Radio Settings Profile + Zdupilkuj aktualny Profil Ustawień Radia + + + Delete Current Radio Profile + Skasuj Aktualny Profil Radia + + + + Delete the current Radio Settings Profile + Skasuj aktualny Profil Ustawień Radia + + + Set Menu Language Ustaw język menu - - + + File Plik - - + + Edit Edycja - + Settings Ustawienia - + Read/Write Odczyt/Zapis - - + + Help Pomoc - Show the list of radio profiles - Pokaż listę profili radia + Pokaż listę profili radia - + Ready Gotowe - + New Radio Nowe Radio @@ -4669,259 +4820,485 @@ Zalecamy przeczytanie informacji o wydaniu (przycisk poniżej) w celu poznania z MdiChild - + free bytes wolna pamięć[B] - + Editing model %1: Edycja modelu %1: - - - - - - - + + + + + + + Error Błąd - + Unable to find file %1! Nie mogę odnaleźć pliku %1! - + Error opening file %1: %2. Błąd otwarcia pliku %1: %2. - + Warning Ostrzeżenie - - - - + Save As Zapisz jako - - + + Alt+Shift+E + Alt+Shift+E + + + + Ctrl+Alt+C + Ctrl+Alt+C + + + + Ctrl+Alt+V + Ctrl+Alt+V + + + + Alt+Shift+S + Alt+Shift+S + + + + Alt+C + Alt+C + + + + Alt+A + Alt+A + + + + Alt+R + Alt+R + + + + Alt+W + Alt+W + + + + Alt+U + Alt+U + + + + %n Model(s) + As in "Copy 3 Models" or "Cut 1 Model" or "Delete 3 Models" action). + + %n Model + %n Modele + %n Modeli + + + + + %n Model(s) + As in "Paste 3 Models" or "Insert 1 Model." + + %n Model + %n Modele + %n Modeli + + + + + %n Category(ies) + As in "Delete 3 Categories" or "Delete 1 Category." + + %n Kategorię + %n Kategorie + %n Kategori + + + + + Nothing selected + Brak wyboru + + + + Rename Category + Przemianuj kategorię + + + + Edit Model + Edytuj model + + + + Cut + Wytnij + + + + Copy + Skopiuj + + + + Paste + Wklej + + + + Insert + Wprowadź + + + + Edit Radio Settings + Edytuj ustawienia radia + + + + Copy Radio Settings + Skopiuj ustawienia radia + + + + Paste Radio Settings + Wklej ustawienia radia + + + + Simulate Radio + Symulacja radia + + + + Add Category + Dodaj Kategorię + + + + Category + Kategoria + + + + Add Model + Dodaj model + + + + Model + Model + + + + Restore from Backup + Odtworzyć z backupu + + + + Model Wizard + Kreator ustawień modelu + + + + Set as Default + Ustaw jako bazowy + + + + Print Model + Wydrukuj model + + + + Simulate Model + Zasymuluj model + + + + Duplicate Model + Duplikuj model + + + + Show Category Actions Toolbar + Pokaż kategorię na pasku akcji + + + + Show Radio Actions Toolbar + Pokar pasek akcji radia + + + + Show Model Actions Toolbar + Pokar pasek akcji modelu + + + + Category index out of range. + Indek kategorii poza limitem. + + + + Cannot delete the last category. + Nie mogę wykasować ostatniej kategori. + + + + Cannot insert model, last model in list would be deleted. + Nie moge dodać modelu, ostatni model z listy zostanie skasowany. + + + + Cannot add model, could not find an available model slot. + Nie moge dodać modelu, brak dostępnego miejsca. + + + + Cannot paste model, out of available model slots. + Nie moge wkleić modelu, brak dostępnego miejsca. + + + + You are replacing an existing model, are you sure? + Podmieniasz istniejący, czy modeś jestes pewien? + + + + Delete %n selected model(s)? + + Wykasuj %n wybrany model? + Wykasuj %n wybrane modele? + Wykasuj %n wybranych modeli? + + + + + Delete %n selected category(ies)? + + Wykasuj %n wybraną kategorię? + Wykasuj %n wybrane kategorie? + Wykasuj %n wybranych kategori? + + + + + Cannot duplicate model, could not find an available model slot. + Nie moge powielić modelu, brak dostępnego miejsca. + + + Companion Companion - + Error reading file %1: %2. Błąd odczytu pliku %1: %2. - + %1 has been modified. Do you want to save your changes? %1 został zmieniony. Zapisać? - Delete selected models? - + Skasować wybrane modele? - Cannot delete default model. - Nie mogę wykasować bazowego modelu. + Nie mogę wykasować bazowego modelu. - &Edit - &Edycja + &Edycja - &Restore from backup - &Odtworzyć z backupu + &Odtworzyć z backupu - &Model Wizard - &Kreator ustawień modelu + &Kreator ustawień modelu - &Delete - &Wykasuj + &Wykasuj - + Delete - Wykasuj + Wykasuj - &Copy - &Kopiuj + &Kopiuj - Ctrl+C - + Ctrl+C - &Cut - + W&ytnij - Ctrl+X - Ctrl+X + Ctrl+X - - &Paste - + &Wklej - - Ctrl+V - Ctrl+V + Ctrl+V - D&uplicate - &Zduplikuj + &Zduplikuj - Ctrl+U - Ctrl+U + Ctrl+U - + Move to Category - + Przesuń do kategori - &Use as default - &Użyj jako bazowy + &Użyj jako bazowy - P&rint model - Wy&drukuj model + Wy&drukuj model - Ctrl+P - Ctrl+P + Ctrl+P - &Simulate model - &Zasymuluj model + &Zasymuluj model - + Alt+S - Alt+S + Alt+S - &Add model - + &Dodaj model - &Rename category - + &Przemianuj model - &Delete category - + &Skasuj kategorię - &Add category - + &Dodaj Kategorię - + Models and settings will be automatically converted. If that is not what you intended, please close the file and choose the correct radio type/profile before reopening it. - + Modele i ustawienia będą automatycznie przekonwertowane. +Jeśli to NIE jest twoim zamiarem. proszę zamknąć plik +i wybrać prawidłowy typ radia/profil przed otwarciem. - + Do you want to overwrite radio general settings? - Czy chcesz nadpisać główne ustawienia radia? + Czy chcesz nadpisać główne ustawienia radia? - You are pasting on an not empty model, are you sure? - Wklejasz na niepustym modelu, jesteś pewien? + Wklejasz na niepustym modelu, jesteś pewien? - + + New category + Translators do NOT use accent for this, this is the default category name on Horus. + Nowa Kategoria + + + This category is not empty! - + Ta kategoria nie jest pusta! - + New model - + Translators: do NOT use accents here, this is a default model name. + Nowy model - + Unable to find Horus radio SD card! - + Nie mogę znaleźc karty SD radia Horus! - + Models and Settings written - + Zapisane modele i ustawienia - + Cannot write temporary file! Nie mogę zapisać pliku tymczasowego! - + Open backup Models and Settings file Otwórz plik backupu Modeli i Ustawień - + Invalid binary backup File %1 nieprawidłowy binarny plik %1 - Radio settings - + Ustawienia radia - Simulate Tx - Symulacja radia + Symulacja radia @@ -5138,22 +5515,22 @@ p, li { white-space: pre-wrap; } Click to access popup menu - + Kliknij by uzyskać wyskakujące menu Clear All - + Wyczyść wszytko Set All - + Ustaw wszystko Invert All - + Odwróć wszytko @@ -5301,52 +5678,52 @@ p, li { white-space: pre-wrap; } Symulacja - + Setup Ustawienia - + Heli Heli - + Inputs Wejścia - + Logical Switches Przełączniki logiczne - + Mixes Miksery - + Flight Modes Fazy lotu - + Outputs Wyjścia - + Special Functions Funkcje Specjalne - + Curves Krzywe - + Telemetry Telemetria @@ -5421,7 +5798,7 @@ p, li { white-space: pre-wrap; } radio Protocol %1, subType %2, option value %3 - + radio Protokół %1, podTyp %2, opcjonalne wartości %3 @@ -5451,22 +5828,22 @@ p, li { white-space: pre-wrap; } 90 - 90 + 90 120 - 120 + 120 120X - 120X + 120X 140 - 140 + 140 @@ -5691,9 +6068,8 @@ p, li { white-space: pre-wrap; } ModelsListWidget - No free slot available, cannot duplicate - Brak wolnych miejsc, nie mogę zduplikować + Brak wolnych miejsc, nie mogę zduplikować @@ -5746,37 +6122,37 @@ p, li { white-space: pre-wrap; } SubType - + PodTyp Antenna - + Antena Internal - + Wewnętrzny Ext. + Int. - + Zewn. + Wewn. Option value - + Wartość opcjonalna Bind on startup - + Binduj na starcie Low Power - + Słabe zasilanie @@ -5786,7 +6162,7 @@ p, li { white-space: pre-wrap; } Multi Radio Protocol - + Wieloradiowy Protokół @@ -5816,19 +6192,19 @@ p, li { white-space: pre-wrap; } Show values in: - + Pokaż wartości w: % abbreviation for percent - % + % μs abbreviation for microseconds - + µs @@ -5945,258 +6321,258 @@ p, li { white-space: pre-wrap; } MultiModelPrinter - + General Model Settings Główne ustawienia modelu - + Name: Nazwa: - + EEprom Size: Wielkosć EEPROMu: - + Timer%1: Timer%1: - + Module%1: Moduł%1: - + Module: Moduł: - + Trainer port: Port trenera: - + Throttle Trim: Trymer gazu: - + Trim Increment: Zwiększanie trymera: - + Center Beep: Dźwięk środka: - - - Helicopter Setup - - - - - Swash Type: - - + Helicopter Setup + Ustawienie śmigłowca + + + + Swash Type: + Typ tarczy: + + + Swash Ring: - + Pierścień tarczy: - + Input - Wejście + Wejście - + Weight - Waga - - - - Long. cyc - Długi cykl + Waga + Long. cyc + Długi cykl + + + Lateral cyc - Boczny cykl + Boczny cykl - + Collective - Pochylenie (Collective) + Pochylenie (Collective) - + Flight modes Fazy lotu - - + + Flight mode Faza lotu - + Switch Przełącznik - + Fade IN Pojawianie - + Fade OUT Zanikanie - - + + FM%1 FM%1 - - + + GV%1 ZG%1 - + RE%1 RE%1 - + Limits Limity - + Channel Kanał - + Name Nazwa - - + + Offset Wyrównanie - + Min Min - + Max Maks - + Invert Odwróć - + Global Variables Zmienne globalne - + Inputs Wejścia - + Mixers Miksery - + CV%1 CV%1 - + Curves Krzywe - + L%1 L%1 - + Logical Switches Przełączniki logiczne - + SF%1 SF%1 - + Special Functions Funkcje Specjalne - + Telemetry Settings Ustawienia telemetrii - + Analogs Analogowe - + Unit Jednostka - + Scale Skala - + A%1 A%1 - + RSSI Alarms Alarmy RSSI - + Low Alarm - Alarm niski + Alarm niski - + Critical Alarm - Alarm krytyczny + Alarm krytyczny @@ -6204,63 +6580,63 @@ p, li { white-space: pre-wrap; } Subtype - + Podtyp Video TX frequency - + Częstotliwość nadajnika wideo - C2500 frequency fine tune - + CC2500 frequency fine tune + Dokadne dostrojenie częstotl. CC2500 Telemetry - Telemetria + Telemetria Radio output power - + Moc wyjściowa radia Servo output frequency - + Częstotliwość wyjściowa serwa Option value - + Wartość opcjonalna DEFAULT - + PODSTAWOWY MultirotorPage - + Throttle Channel: Kanał gazu: - + Yaw Channel: Kanał odchylenia: - + Pitch Channel: Kanał kąta: - + Roll Channel: Kanał rotacji: @@ -6268,17 +6644,17 @@ p, li { white-space: pre-wrap; } OptionsPage - + Throttle Cut Odcięcie Gazu - + Throttle Timer Timer Gazu - + Flight Timer Timer Lotu @@ -6437,14 +6813,14 @@ p, li { white-space: pre-wrap; } - + REa Pokrętło :a - + REb Pokrętło :b @@ -6496,13 +6872,13 @@ p, li { white-space: pre-wrap; } - + V V - + s s @@ -6573,7 +6949,7 @@ p, li { white-space: pre-wrap; } mW - + mW @@ -6594,7 +6970,7 @@ p, li { white-space: pre-wrap; } Rad - + Rad @@ -6794,7 +7170,7 @@ p, li { white-space: pre-wrap; } - + ---- @@ -6806,93 +7182,83 @@ p, li { white-space: pre-wrap; } - + ON Włącz - + OFF Wyłącz - + Diff(%1) Różnicowość(%1) - + Expo(%1) Expo(%1) - + Function(%1) Funkcja(%1) - + Curve(%1) Krzywa(%1) - + !Curve(%1) !Krzywa(%1) - - + + Support for frsky telemetry mod Wsparcie dla telemetrii FrSky - - + + Support for jeti telemetry mod Wsparcie telemetrii JETI - - + + Support for receiving ardupilot data Wsparcie dla otrzymywania danych ardupilota - - + + Support for receiving NMEA data Wsparcie dla otrzymywania danych NMEA - + Support for telemetry easy board Wsparcie dla platformy TelemetrEZ - - + + Support for MAVLINK devices Wsparcie urządzeń MAVLINK - + Rotary Encoder use in menus navigation Użycie pokrętła do nawigacji w menu - - - - - - - - Enable heli menu and cyclic mix support - Uaktywnione menu Heli i wsparcie dla cyklicznych mikserów - @@ -6900,27 +7266,37 @@ p, li { white-space: pre-wrap; } - Enable TEMPLATES menu - Uaktywnienie menu szablonów + Enable heli menu and cyclic mix support + Uaktywnione menu Heli i wsparcie dla cyklicznych mikserów - No splash screen - Bez loga na ekranie + + + Enable TEMPLATES menu + Uaktywnienie menu szablonów - - - - - + No splash screen + Bez loga na ekranie + + + + + + + + + + + No flight modes Firmware bez menu faz lotu @@ -6930,17 +7306,17 @@ p, li { white-space: pre-wrap; } Wartości kanałów wyświetlone w us - - - - - - - - - - - + + + + + + + + + + + Use alternative SQT5 font Użyj alternatywnego fontu SQT5 @@ -6960,97 +7336,97 @@ p, li { white-space: pre-wrap; } Tryb FAI (brak telemetrii) zawsze aktywny - + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) Zamiast emulacji joysticka, podłaczenie USB działa jako dysk zewnętrzny (jak w Bootloaderze) - + Instead of Joystick emulation, USB connection is Command Line Interface Zamiast emulacji joysticka, podłaczenie USB działa jako interface linii komend - - + + Support for PPM internal module hack Wsparcie dla shakowania wewnętrznego modułu PPM - + ERC12864FSF LCD LCD: ERC12864FSF - + ST7920 LCD LCD: ST7920 - + EEprom write progress bar Pasek postępu wgrywania EEPROMu - - + + No Winged Shadow How High support Bez wsparcia - Winged Shadow How High - + Turnigy 9XR - - - - - - No vario support - Bez wsparcia wario + Turnigy 9XR - No GPS support - Bez wsparcia GPS + No vario support + Bez wsparcia wario + No GPS support + Bez wsparcia GPS + + + + No gauges in the custom telemetry screen Bez graficznych wskazań telemetrii - + 9X with stock board - + 9X ze standardową platformą - + Allow compensating for offset errors in FrSky FAS current sensors Pozwolenie na kompensację błędów w czujnikach natężenia FrSky FAS - + FrSky Taranis X9E FrSky Taranis X9E - + Confirmation before radio shutdown Potwierdzenie przez wyłączeniem radia - + ST7565P LCD or compatible LCD ST7565P lub kompatybilny - + ST7565R LCD or compatible LCD ST7565R lub kompatybilny - + Haptic module installed Moduł wibracji zainstalowany @@ -7062,47 +7438,47 @@ p, li { white-space: pre-wrap; } Unknown error - + Nieznany błąd ... plus %1 errors - + ,,, plus %1 błędów Cannot write radio settings - + Nie mogę zapisać ustawień radia Cannot write model %1 - + Nie mogę zapisać modelu %1 6P - 6P + 6P JSx - + JSy - + Support for the DIY-Multiprotocol-TX-Module - + Wsparcie dla wieloprotokołowego modułu nadawczego DIY Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 - + Usuwa wsparcie dla protokołu D8 FrSky, który jest nielegany w UE w radiach spradawanych po 01-01-2015 @@ -7117,200 +7493,105 @@ p, li { white-space: pre-wrap; } Enable Lua compiler - + Uaktywnia kompilator LUA - + + Enable bindings options + Uaktywnij opcje mapowania + + + KS108 LCD - - - - - WTV20 voice module - + KS108 LCD + WTV20 voice module + Moduł dźwiękowy WT20 + + + JQ6500 voice module - + Moduł dźwiękowy JQ6500 - + FrSky Taranis X9D+ - + FrSky Taranis X9D+ - + FrSky Taranis X9D - FrSky Taranis X9E {9D?} + FrSky Taranis X9D - + Horus gimbals installed (Hall sensors) - + Zainstalowane gimbale Horusa (na czujnikach Halla) - + FrSky Taranis X7 - FrSky Taranis X9E {7?} + FrSky Taranis X7 - + FrSky Horus - + FrSky Horus - + Use ONLY with first DEV pcb version - + Użyć tylko dla pierwszych deweloperskich platform - + Turnigy 9XR-PRO - + Turnigy 9XR-PRO - + Turnigy 9XR with m128 chip - - - - - - - - - - Disable curves menus - Bez menu krzywych + Turnigy 9XR z kością m128 - - Support for radio modified with regular speaker - Wsparcie dla modyfikacji radia zwykłym głośnikiem + + + Disable curves menus + Bez menu krzywych - - Used if you have modified your radio with voice mode - Używane jeśli radio jest zmodyfikowane w calu użycia komunikatów głosowych + + Support for radio modified with regular speaker + Wsparcie dla modyfikacji radia zwykłym głośnikiem - + + Used if you have modified your radio with voice mode + Używane jeśli radio jest zmodyfikowane w calu użycia komunikatów głosowych + + + + + + + Used if you have modified your radio with haptic mode Używane jeśli radio jest zmodyfikowane do użycia wibracji - - - - - - - - - - - Battery graph - Grafika baterii - - - - - - - Enable the throttle trace in Statistics - Uaktywnić śledzenie gazu w statystykach - - - - - Support of FrSky PXX protocol - Wsparcie dla protokołu Frsky PXX - - - - - - - - Support for DSM2 modules - wsparcie modułu DSM2 - - - - - - - - - PPM center adjustment in limits - Limit dostrojenia centrowania PPM - - - - - - - - - Symetrical Limits - Limity symetryczne - - - - - - - - - - Pots use in menus navigation - Użycie potencjometrów do nawigacji w menu - - - - - SmartieParts 2.2 Backlight support - Wsparcie podświetlenia SmartieParts 2.2 - - - - - - - - - Enable resetting values by pressing up and down at the same time - Szybkie nastawianie wartości -(+) a (-) neguje wartość -(+)a (UP) ustawia max -(-) a (DN) ustawia min -(UP) a (DN) ustawia 0 - - - - - - - - - - - - No graphical check boxes and sliders - Brak graficznych pol wyboru i suwaków - @@ -7321,60 +7602,147 @@ p, li { white-space: pre-wrap; } - Don't use bold font for highlighting active items - Nie używaj podświetlenia dla wybranych aktywnych elementów, mikserów, krzywych, expo, etc + Battery graph + Grafika baterii + - - - EEprom write Progress bar - Pasek postępu zapisywania EEPROM + Enable the throttle trace in Statistics + Uaktywnić śledzenie gazu w statystykach - - - - - - - Imperial units - Imperialne jednostki w telemetrii + + + Support of FrSky PXX protocol + Wsparcie dla protokołu Frsky PXX - - - - Bluetooth interface - Interface Bluetooth + + + + + + Support for DSM2 modules + wsparcie modułu DSM2 - - - - Global variables - Globalne zmienne + PPM center adjustment in limits + Limit dostrojenia centrowania PPM + + + + + + + Symetrical Limits + Limity symetryczne + + + - - - - In model setup menus automatically set source by moving the control - W menu ustawień modelu automatycznie wybierz źródło poprzez poruszenie nim + Pots use in menus navigation + Użycie potencjometrów do nawigacji w menu + + + + + SmartieParts 2.2 Backlight support + Wsparcie podświetlenia SmartieParts 2.2 + + + + + + + + + Enable resetting values by pressing up and down at the same time + Szybkie nastawianie wartości +(+) a (-) neguje wartość +(+)a (UP) ustawia max +(-) a (DN) ustawia min +(UP) a (DN) ustawia 0 + + + + + + + + + + + + No graphical check boxes and sliders + Brak graficznych pol wyboru i suwaków + + + + + + + + + + + + Don't use bold font for highlighting active items + Nie używaj podświetlenia dla wybranych aktywnych elementów, mikserów, krzywych, expo, etc + + + + + + + + EEprom write Progress bar + Pasek postępu zapisywania EEPROM + + + + + + + + + Imperial units + Imperialne jednostki w telemetrii + + + + + + Bluetooth interface + Interface Bluetooth + + + + + + + + + + + + Global variables + Globalne zmienne @@ -7386,64 +7754,78 @@ p, li { white-space: pre-wrap; } + In model setup menus automatically set source by moving the control + W menu ustawień modelu automatycznie wybierz źródło poprzez poruszenie nim + + + + + + + + + + + In model setup menus automatically set switch by moving the control W menu ustawień modelu automatycznie wybierz źródło poprzez poruszenie nim - - + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) Dodanie wsparcia dla odwracania wejścia drążków (np. potrzebne dla gimbali FrSky) - + 9X with stock board and m128 chip - + 9X ze standardową platformą i kością m128 - + 9X with AR9X board - + 9X z platformą AR9X - + 9X with Sky9x board - + 9X z platformą Sky9X - + 9X with Gruvin9x board - + 9X z platformą Gruvin9X - - + + Support for SD memory card Wsparcie karty SD - + Support for DSM2 modules using ppm instead of true serial Wsparcie modułu DSM2 przez użycie PPM zamiast prawdziwego szeregowego - + DIY MEGA2560 radio - + Radio DIY MEGA2560 - + Power management by soft-off circuitry Zarządzanie zasilaniem przez obwód Soft-Off - - - + + + Enable HELI menu and cyclic mix support Uaktywnij menu HELI i cyklicznych mikserów + Warning Ostrzeżenie @@ -7496,12 +7878,12 @@ p, li { white-space: pre-wrap; } Dutch - + Holenderski Hungarian - + Węgierski @@ -7546,7 +7928,7 @@ p, li { white-space: pre-wrap; } - + Timer3 Timer3 @@ -7723,22 +8105,22 @@ p, li { white-space: pre-wrap; } Trim 5 Down - + Trymer 5 w dół Trim 5 Up - + Trymer 5 w górę Trim 6 Down - + Trymer 6 w dół Trim 6 Up - + Trymer 6 w górę @@ -7756,318 +8138,319 @@ p, li { white-space: pre-wrap; } THt - + One Jeden - + + ??? ??? - + a>x a>x - + a<x a<x - + |a|>x |a|>x - + |a|<x |a|<x - + AND I (logiczne) - + OR Lub (logiczne) - + XOR XOR (Logiczne) - + a=b a=b - + a!=b a!=b - + a>b a>b - + a<b a<b - + a>=b a>=b - + a<=b a<=b - + d>=x d>=x - + |d|>=x |d|>=x - + a=x a=x - + a~x a~x - + Timer Timer - + Sticky Trwałe przełączenie Left Horizontal - Lewy poziomy + Lewy poziomy Left Vertical - Lewy pionowy + Lewy pionowy Right Vertical - Prawy pionowy + Prawy pionowy Right Horizontal - Prawy poziomy + Prawy poziomy Aux. 1 - + Dodatk. 1 Aux. 2 - + Dodatk. 2 - + Unknown Nieznane - + Override %1 Nadpisanie %1 - + Trainer Trener - + Trainer RUD Trener - SK - + Trainer ELE Trener - SW - + Trainer THR Trener - Gaz - + Trainer AIL Trener - Lotki - + Instant Trim Natychmiastowe trymowanie - + Play Sound Odtwórz dźwięk - + Reset Zresetuj - + Set Timer %1 Ustaw Timer %1 - + Vario Wariometr - + Play Both Odtwórz oba - + Play Value Odtwórz wartość - + Play Script Odtwórz Skrypt - + Volume Głośność - + Backlight Podświetlenie - + Screenshot Zrzut ekranu - + Adjust GV%1 Ustaw ZG%1 - + SetFailsafe Int. Module Ustaw FailSafe Wew. Modułu - + SetFailsafe Ext. Module Ustaw FailSafe Zew. Modułu - + RangeCheck Int. Module Sprawdzenie Zasiegu Wew. Modułu - + RangeCheck Ext. Module Sprawdzenie Zasiegu Zew. Modułu - + Bind Int. Module Bindowanie Wew. Modułu - + Bind Ext. Module Bindowanie Zew. Modułu - + Flight Lot - + Rotary Encoder Pokrętło - - - + + + <font color=red><b>Inconsistent parameter</b></font> Niespójny parametr <font color=red><b>Niespójny parametr</b></font> - + played once, not during startup Odtworzone raz, nie w czasie startu - + repeat(%1s) powtórz(%1s) - + DISABLED Wyłączone - + INV Odwróć - + NOR NormalnyNOR -GV%1 (%2) - + -ZG%1 (%2) GV%1 (%2) - + ZG%1 (%2) @@ -8128,30 +8511,30 @@ p, li { white-space: pre-wrap; } Uknown error during Simulator startup. - + Nieznany błąd w trakcie startu Symulatora. Simulator Error - + Błąd Symulatora - + Data Load Error - + Błąd wczytania danych - + Error occurred while starting simulator. - + Błąd wystąpił w trakcie startu Symulatora. - + Play Track Odtwórz ścieżkę - + --- @@ -8193,41 +8576,41 @@ p, li { white-space: pre-wrap; } Kan %1 - + Haptic Wibracje - + Background Music Muzyka tła - + Background Music Pause Muzyka tła - pauza - + Timer1 Timer1 Trm5 - + Trymer 5 Trm6 - + Trymer 6 - + Timer2 Timer2 @@ -8270,35 +8653,35 @@ p, li { white-space: pre-wrap; } L%1 - L%1 + L%1 - + Edge Brzeg - + SD Logs - + Logi SD - + Telemetry Telemetria - + Value Wartość - + Decr: Zmniejsz: - + Incr: Zwiększ: @@ -8379,17 +8762,17 @@ p, li { white-space: pre-wrap; } Switch - Przełącznik + Przełącznik Switch - + Przełącznik cannot be exported on this board! - + nie może być wyeksportowana na tę platformę! @@ -8483,8 +8866,8 @@ Zespół OpenTX. ZG - - + + @@ -8492,12 +8875,12 @@ Zespół OpenTX. Błąd synchronizacji - + No SD directory configured! Nieskonfigurowany katalog karty SD! - + No Radio connected! Radio niepodłączone! @@ -8533,12 +8916,12 @@ Zespół OpenTX. -%1 - + Positive Dodatni - + Negative Ujemny @@ -8579,135 +8962,139 @@ Zespół OpenTX. Unable to find Horus radio SD card! - + Nie mogę znaleźc karty SD radia Horus! Conversion error on field %1 - + Błąd konwersji pola %1 Negative span - Ujemny zakres + Ujemny zakres Mid value - Wartość środkowa + Wartość środkowa Positive span - Dodatni zakres + Dodatni zakres - + Models Translators do NOT use accent for this, this is the default category name on Horus. - + Modele - + Select a data file - + Wybierz plik danych - + Select Data Directory - + Wybierz katalog danych - + Select SD Card Image Folder - + Wybierz folder obrazu karty SD Available profiles: - + Dostępne profile: ID: - + ID: Name: - + Nazwa: Available radios: - + Dostępne radia: WARNING: couldn't initialize SDL: %1 - + Osrzeżenie: nie mogę zainicjalizować SDL: +%1 ERROR: No simulator libraries available. - + BŁĄD: biblioteki symulatora niedostępne. Radio profile ID or Name to use for simulator. - + Profil radia lub ID użyte w symulatorze. Radio type to simulate (usually defined in profile). - + Typ radia do symulacji (zwykle zdefiniowane w profilu). show this help text - + pokaż tekst tej pomocy Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] - + Użycie: simulator [OPCJE] ... [PLIK EEPROM.BIN lub FOLDER DANYCH] Options: - + Opcje: ERROR: Couldn't start simulator, missing radio/profile/data file/folder. Profile ID: [%1]; Radio ID: [%2]; Data File: [%3] - + BŁĄD: Nie mogę wystartować symulatora, brakuje radia/profilu/pliku danych/folderu +ID Profilu: [%1]; ID Radia: [%2]; +Plik Danych: [%3] ERROR: Radio profile or simulator firmware not found. Profile ID: [%1]; Radio ID: [%2] - + BŁĄD: Porfil radia lub fimware symulatora nie znalezione. ID Profilu: [%1]; ID Radia: [%2] Error reading %1: %2 - + Błąd odczytu %1: %2 Cannot save EEPROM - + Nie mogę zapisać EEPROMu Cannot open file %1: %2. - + Nie mogę otwprzyć pliku %1: +%2. @@ -8715,88 +9102,90 @@ Profile ID: [%1]; Radio ID: [%2] Error writing file %1: %2. - Błąd zapisu pliku %1: + Błąd zapisu pliku %1: %2. Invalid binary EEPROM file %1 - + Nieprawidłowy binarny plik EEPROMu %1 Can't extract RADIO/radio.bin - + Nie mogę uzyskać RADIO/radio.bin Can't extract RADIO/models.txt - + Nie mogę uzyskać RADIO/models.txt Can't extract %1 - + Nie mogę uzyskać %1 Unable to open %1: %2 - + Nie mogę otworzyć %1: %2 Invalid EEPROM file %1 - + Nieprawidłowy plik EEPROMu %1 Invalid EEPROM File %1 - Zły plik EEPROM %1 + Nieprawidłowy plik EEPROMu %1 Error opening file %1: %2. - Błąd otwarcia pliku %1: + Błąd otwarcia pliku %1: %2. Error opening OTX archive %1 - + Błąd otwarcia archiwum OTX %1 Error initializing OTX archive writer - + Błąd inicjalizacji zapisu archiwum OTX Error creating OTX file %1: %2. - + Błąd tworzenia pliku OTX %1: +%2. Error creating OTX archive - + Błąd tworzenia archiwum OTX Error adding %1 to OTX archive - + Błąd dodania %1 do archiwum OTX Error opening file %1 in write mode: %2. - + Błąd otwarcia pliku %1 w trybie zapisu: +%2. Unable to find file %1! - Nie mogę odnaleźć pliku %1! + Nie mogę odnaleźć pliku %1! @@ -8804,171 +9193,176 @@ Profile ID: [%1]; Radio ID: [%2] sets the application GUI style - + Ustaw styl GUI aplikacji sets the application stylesheet - + Ustaw arkusz stylów aplikacji restores the application from an earlier session - + odtwarza aplikacji z poprzedniej sesji displays debugging information about widgets - + wyswietla informacje debugowania widgetów use right-to-left layout - + Użyj uladu or prawej do lewej never grab the mouse or keyboard - + nie przechwytuj myszy ani klawiatury grab the mouse/keyboard even in a debugger - + przechwytuj mysz/klawiarutę nawet w debugerze run in synchronous mode for debugging - + pracuj w trybie sunchronicznym w debugerze use Direct3D by default - + użyj domyślnie Dirext3D sets the X11 display - + ustaw wyświetlacz X11 sets the geometry of the first window - + ustaw geometrię pierwszego okna sets the default font - + ustaw domyślny font sets the default background color - + ustaw domyśly kolor tła sets the default foreground color - + ustaw kolor pierwszego planu sets the default button color - + ustaw domyślny kolor przycisku sets the application name - + ustaw nazwę aplikacji sets the application title - + ustaw tytuł aplikacji sets the X11 visual type - + ustaw typ widoku X11 limit the number of colors on an 8-bit display - + ogranicz ilość kolorów na 8-bitowym wyświetlaczu use a private color map - + uzyj własnej palety barw sets the input method server - + ustaw metodę wprowadzania serwera disable the X Input Method - + zdezaktywuj Metodę Wprowadzania X sets the style used by the input method - + ustaw styl uzywany przez metodę wprowadzania option "%1" not found - + opcja %1 nie znaloziona Short options cannot have optional parameters - + Którkie opcje nie mogą posiadać parametrów dodatkowych positional() called before parse() - + positional() wołana przed parse() unrecognized() called before parse() - + unrecognized() wołana przed parse() count() called before parse() - + count() wołana przed parse() value() called before parse() - + value() wołana przed parse() parameters() called before parse() - + parameters() wołana przed parse() unrecognized parameters: - + nierozpoznane parametry: %1 requires a parameter - + %1 wymaga parametru RadioKnobWidget - + + <p>Value (input): <b>%1</b></p> + <p>Wartość (wejściowa): <b>%1</b></p> + + + Right-double-click to reset to center. - + Podwójny klik PPM w celu zresetowania środka. @@ -8994,27 +9388,27 @@ Profile ID: [%1]; Radio ID: [%2] Form - Formularz + Formularz View: - + Widok: Logical Switches - Przełączniki logiczne + Przełączniki logiczne Global Variables - Zmienne globalne + Zmienne globalne Channel Outputs - + @@ -9023,7 +9417,12 @@ o g i c - + L +o +g +i +k +a @@ -9033,7 +9432,12 @@ o b a l - + G +l +o +b +a +l @@ -9045,7 +9449,12 @@ n e l s - + K +a +n +a +ł +y @@ -9053,7 +9462,7 @@ s Latch/unlatch the momentary switch. - + Zablokuj/odblokuj przełącznik chwilowy. @@ -9061,22 +9470,22 @@ s ↑ - + ↑ ↓ - + ↓ - - + ! - + ! @@ -9098,17 +9507,17 @@ s RudderPage - + No Nie - + Yes Tak - + <br>Rudder Channel: <br> Kanał Steru Kierunku: @@ -9292,7 +9701,7 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również SimpleTailPage - + Elevator Channel: Kanał Steru Wysokości: @@ -9300,420 +9709,205 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również SimulatedUIWidget - - Rotary encoder click - - - - - Take Screenshot - - - - + screenshot Simulator LCD screenshot file name prefix - + zrzut ekranu + + + + ENTER + ENTER + + + + PG-UP + PG-UP + + + + PG-DN + PG-DN + + + + DEL + DEL + + + + BKSP + BKSP + + + + ESC + ESC + + + + INS + INS + + + + <font size=+3>+</font> + <font size=+3>+</font> + + + + <font size=+3>-</font> + <font size=+3>-</font> + + + + <font size=+3>&larr;</font> + <font size=+3>&larr;</font> + + + + <font size=+3>&rarr;</font> + <font size=+3>&rarr;</font> + + + + <font size=+3>&uarr;</font> + <font size=+3>&uarr;</font> + + + + <font size=+3>&darr;</font> + <font size=+3>&darr;</font> + + + + <font size=+3>&#x2686;</font> + <font size=+3>&#x2686;</font> + + + + <font size=+3>&#x21b6;</font> + <font size=+3>&#x21b6;</font> + + + + <font size=+3>&#x21b7;</font> + <font size=+3>&#x21b7;</font> + + + + <font size=+3>&#x21c6;</font> + <font size=+3>&#x21c6;</font> + + + + + <font size=+3>&#x21d3;</font> + <font size=+3>&#x21d3;</font> + + + + <font size=+3>&#x21d1;</font> + <font size=+3>&#x21d1;</font> + + + + <font size=+3>&#x21d5;</font> + <font size=+3>&#x21d5;</font> + + + + <img src='qrc:/images/simulator/icons/svg/mouse.svg' width=20 height=18 /> + <img src='qrc:/images/simulator/icons/svg/mouse.svg' width=20 height=18 /> + + + + <img src='qrc:/images/simulator/icons/svg/arrow_click.svg' width=18 height=18 /> + <img src='qrc:/images/simulator/icons/svg/arrow_click.svg' width=18 height=18 /> + + + + <pre>[ MENU ]</pre> + <pre>[ MENU ]</pre> + + + + <pre>[ PAGE ]</pre> + <pre>[ PAGE ]</pre> + + + + <pre>[ EXIT ]</pre> + <pre>[ WYJŚCIE ]</pre> + + + + <pre>[ ENT ]</pre> + <pre>[ ENT ]</pre> + + + + <pre>[ UP ]</pre> + <pre>[ GÓRA ]</pre> + + + + <pre>[ DN ]</pre> + <pre>[ DÓŁ ]</pre> + + + + <pre>[ <font size=+2>+</font> ]</pre> + <pre>[ <font size=+2>+</font> ]</pre> + + + + <pre>[ <font size=+2>-</font> ]</pre> + <pre>[ <font size=+2>-</font> ]</pre> + + + + <pre>[ PgUp ]</pre> + <pre>[ PgUp ]</pre> + + + + <pre>[ PgDn ]</pre> + <pre>[ PgDn ]</pre> + + + + <pre>[ MDL ]</pre> + <pre>[ MDL ]</pre> + + + + <pre>[ RTN ]</pre> + <pre>[ RTN ]</pre> + + + + <pre>[ SYS ]</pre> + <pre>[ SYS ]</pre> + + + + <pre>[ TELE ]</pre> + <pre>[ TELE ]</pre> + + + + <font size=+3>&#x2261;</font> + <font size=+3>&#x2261;</font> SimulatedUIWidget9X - - UP/PG-UP - - - - - [ UP ] - - - - - DN/PG-DN - - - - - [ DN ] - - - - - RIGHT/+ - - - - - [ + ] - - - - - LEFT/- - - - - - [ - ] - - - - - ENTER/MOUSE-MID - - - - - [ MENU ] - - - - - DEL/BKSP/ESC - - - - - [ EXIT ] - - - - - WHEEL/PAD SCRL - - - - - [ UP ]/[ DN ] or Rotary Sel. - - - - - SimulatedUIWidgetX12 - - - PG-UP - - - - - [ PgUp ] - - - - - PG-DN - - - - - [ PgDn ] - - - - - UP - - - - - [ MDL ] - - - - - DN/DEL/BKSP - - - - - [ RTN ] - - - - - LEFT - - - - - [ SYS ] - - - - - RIGHT - - - - - [ TELE ] - - - - - WHEEL/PAD SCRL - - - - - Rotary Selector - - - - - -/X - - - - - Rotary UP - - - - - +/C - - - - - Rotary DOWN - - - - - ENTER/MOUSE-MID - - - - - Selector Press - - - - - SimulatedUIWidgetX7 - - - Taranis X7 Simulator - - - - - PG-UP - - - - - [ PAGE ] - - - - - PG-DN - - - - - [ MENU ] - - - - - DEL/BKSP/ESC - - - - - [ EXIT ] - - - - - WHEEL/PAD SCRL - - - - - Rotary Selector - - - - - -/UP - - - - - Rotary UP - - - - - +/DN - - - - - Rotary DOWN - - - - - ENTER/MOUSE-MID - - - - - Selector Press - - - - - SimulatedUIWidgetX9 - - - PG-UP - - - - - [ MENU ] - - - - - PG-DN - - - - - [ PAGE ] - - - - - DEL/BKSP/ESC - - - - - [ EXIT ] - - - - - +/UP - - - - - [ + ] - - - - - -/DN - - - - - [ - ] - - - - - ENTER/MOUSE-MID - - - - - [ ENT ] - - - - - WHEEL/PAD SCRL - - - - - [ + ]/[ - ] - - - - - SimulatedUIWidgetX9E - - - PG-UP - - - - - [ MENU ] - - - - - PG-DN - - - - - [ PAGE ] - - - - - DEL/BKSP/ESC - - - - - [ EXIT ] - - - - - WHEEL/PAD SCRL - - - - - Rotary Selector - - - - - -/UP - - - - - Rotary UP - - - - - +/DN - - - - - Rotary DOWN - - - - - ENTER/MOUSE-MID - - - - - Selector Press - + + + | + | @@ -9721,217 +9915,224 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również OpenTx Simulator - + Symulator OpenTX View - + Widok Radio Window - + Okno Radia Reload... - + Przeładuj... Tools - + Narzędzia Toolbar - + Pasek narzędzi Reload Lua Scripts - + Przeładuj skrypty LUA Reload the Lua environment on the simulated radio. - + Przeładuj środowisko LUA na symulowanym radiu. F7 - F7 + F7 Reload Radio Data - + Przeładuj Dane Radia Reload all radio data without restarting the simulator. - + Przeładuj dane radia bez restartowania symulatora. F9 - F9 + F9 Key Mapping - + Mapowanie Klawiszy Show keyboard maping reference. - + Pokaż mapowanie klawiatury. F1 - F1 + F1 Joystick Settings - + Ustawienia Joystika Open joystick configuration settings dialog. - + Otwórz dialog ustawień joystika. F3 - F3 + F3 LCD Screenshot - + Zrzut ekrany LCD Save a screenshot of the current simulated LCD screen. - + Zapisz zrzut ekranu aktualnnie symulowanego monitora LCD. F8 - F8 + F8 Dock In Main Window - + Zadokuj w głównym oknie Show the radio in the main window or as a separate "floating" window. - + Pokaż radio w głównym oknie lub w pływającym oddzielnym oknie. Menu Bar - + Pasek Menu Show or hide the top menu bar. - + Pokaż lub ukryj górny pasek menu. Alt+M - + Alt+M Constrain Width - + Wymuś szerokość Set radio widget width to be a fixed size. - + Ustaw stałą wielkość widgetu radia. Constrain Height - + Wymuś wysokość Set radio widget height to be a fixed size. - + Ustaw stałą wysokość widgetu radia. ERROR: Failed to create simulator interface, possibly missing or bad library. - + BŁĄD: Nieudane utoerzenie interfacu symulatora, mozliwa zła lub brakująca biblioteka. - + Alt+T - + Alt+T - + Radio Outputs - + Wyjścia radia - + F2 - F2 + F2 - + Telemetry Simulator - Symulator telemetrii + Symulator telemetrii - + F4 - F4 + F4 - + Trainer Simulator - + Symulator trenera - + F5 - F5 + F5 - + Debug Output - Wyjście debugera + Wyjście debugera - + F6 - F6 + F6 - - Simulator Controls: - + + <b>Simulator Controls:</b> + <b>Sterowanie Symulatora:</b> - - <tr><th>Key/Mouse</td><th>Action</td></tr> - + + <tr><th>Key/Mouse</th><th>Action</th></tr> + note: must match html layout of each table row (keyTemplate). + <tr><th>Klawisz/Mysz</th><th>Action</th></tr> - + + <tr><td><kbd>%1</kbd></td><td>%2</td></tr> + note: must match html layout of help text table header. + <tr><td><kbd>%1</kbd></td><td>%2</td></tr> + + + Simulator Help - + Pomoc Symulatora @@ -9939,119 +10140,123 @@ Wolne obroty będą na górze, trymer i ostrzeżenie o otwartym gazie również OpenTX Simulator - Startup Options - + Symulator OpenTX - Opcje Startowe Simulator Startup Options: - + Opcje Startowe Symulatora: Radio Profile: - + Profil radia: Existing radio profiles are shown here.<br /> Create or edit profiles using the Companion application. - + Tu są pokazane istniejące profile radia.<br /> +Stwórz lub edytuj profile używając aplikacji Companion. Radio Type: - + Typ Radia: Existing radio simulators are shown here.<br /> The radio type specified in the selected profile is used by default. - + Tu są pokazane istniejące profile radia.<br /> +Typ radia określony w wybranym profilu zostanie użyty jako domyślny. Data Source: - + Źródło Danych: Data File: - + Źródło Pliku: Data Folder: - + Folder Danych: SD Image Path: - + Ścieżka Obrazu SD: Radio data (.bin/.eeprom/.otx) image file to use. A new file with a default image will be created if necessary.<br /> <b>NOTE</b>: any existing EEPROM data incompatible with the selected radio type may be overwritten! - + Plik obrazu danych radia (.bin/.eeprom/.otx) do użytku. W razie potrzeby zostanie stworzony nowy plik z domyślnym obrazem.<br /> +<b>UWAGA</b>: każdy istniejący EEPROM niekompatybilny z wybranym typem radia zostanie nadpisany! Select data file... - + Wybierz plik danych... ... - ... + ... Directory containing RADIO and MODELS folders to use.<br /> New folder(s) with default radio/model will be created here if necessary. - + Katalog zawierajacy foldery RADIA i MODELI do użycia.<br />W razie potrzeby zostanią stworzone nowe foldery z domyślnym Radiem/Modelami. Select data folder... - + Wybierz folder danych... Directory containing the SD card image to use.<br/> The default is configured in the chosen Radio Profile. - + Katalog zawierajacy obraz karty SD do użycia.<br/> +Domyślny jest skonfigurowany w wybranym Profilu Radia. Select SD card image folder... - + Wybierz folder obrazu karty SD... Select which of the data sources (File/Folder/SD Card) you would like to start the simulator with. - + Wybierz jakie źródło danych (Plik/Folder/Karta SD) chcesz użyć do uruchomienia symulatora. File - Plik + Plik Folder - + Katalog SD Path - + Scieżka SD - + All files (*.*) - + Wszytkie pliki (*.*) @@ -10059,80 +10264,90 @@ The default is configured in the chosen Radio Profile. Companion Simulator - Symulator Companion + Symulator Companion - + Radio Simulator (%1) - - - - - Could not determine startup data source. - + Symulator Radia (%1) + Could not determine startup data source. + Nie mogę ustalić startowego źródła danych. + + + Could not load data, possibly wrong format. - + Nie mogę załadować danych, prawdopodobnie zły format. - + Data Load Error - + Błąd odczytu danych - + Invalid startup data provided. Plese specify a proper file/path. - + Dostarczone błędne dane startowe. Proszę określić prawidłowy plik/ścieżkę. - + Simulator Startup Error - + Błąd startu symulatora - + Error saving data: could open file for writing: '%1' - + Błąd zapisu danych: nie mogę otworzyć pliku do zapisu: '%1' - + Error saving data: could not get data from simulator interface. - + Błąd zapisu danych: nie mogę pobrać danych z interfacu symulatora. - + An unexpected error occurred while attempting to save radio data to file '%1'. - + Nastąpił nieoczekiwany błąd w trakcie próby zapisu danych radia do pliku '%1'. - + Data Save Error - + Błąd zapisu danych - + Warning - Ostrzeżenie + Ostrzeżenie - + Cannot open joystick, joystick disabled - Nie mogę otworzyć joysticka, dezaktywowany + Nie mogę otworzyć joysticka, dezaktywowany - - Firmware %1 error: %2 - Firmware %1 błąd: %2 + + Radio firmware error: %1 + Błąd Firmware Radia: %1 + + + + - Flight Mode %1 (#%2) + - Faza lotu %1 (#%2) SliderWidget - + Right-double-click to reset to center. - + Podwójny klik PPM w celu zresetowania środka. + + + + <p>Value (input): <b>%1</b></p> + <p>Wartość (wejściowa): <b>%1</b></p> @@ -10193,28 +10408,28 @@ The default is configured in the chosen Radio Profile. Copy %1 to %2 - Skopuj %1 do %2 {1 ?} {2?} + Skopuj %1 do %2 Write %1 - Zapisz %1 {1?} + Zapisz %1 TailPage - + Rudder Channel: Kanał Steru Kierunku: - + Elevator Channel: Kanał Steru Wysokości: - + Only one channel still available!<br>You probably should configure your model without using the wizard. TYlko jeden kanał jest dostepny!<br>Prawdopoobnie musisz skonfigurować swój model bez użycia konfiguratora. @@ -10222,22 +10437,22 @@ The default is configured in the chosen Radio Profile. TailSelectionPage - + Elevator and Rudder Ster Wysokości i Ster Kierunku - + Only Elevator Tylko Ster Wysokości - + V-tail Usterzenie motylkowe - + Tail Type: Typ ogona: @@ -10868,7 +11083,7 @@ The default is configured in the chosen Radio Profile. mW - + mW @@ -10888,7 +11103,7 @@ The default is configured in the chosen Radio Profile. Rad - + Rad @@ -11019,85 +11234,86 @@ The default is configured in the chosen Radio Profile. Simulate - Symulacja + Symulacja Replay SD Log File - + Odtwórz plig logów z SD Replay rate - + Współczynnik odtwarzania Load - + Załaduj |> - + |> <| - + <| > - > + > <- - + <- X - X + X Row # Timestamp - + Czysty # +Timestamp 1/5x - 1/5x + 1/5x 5x - 5x + 5x No Log File Currently Loaded - + Nie jest załadowany żaden plik logu V / ratio - + V / współczynnik Db - + RxBt - + RxBt @@ -11114,12 +11330,12 @@ Timestamp <html><head/><body><p><br/></p></body></html> - + <html><head/><body><p><br/></p></body></html> Tmp1 - + Tmp1 @@ -11134,154 +11350,156 @@ Timestamp Tmp2 - + Tmp2 Fuel - Paliwo + Paliwo °C - °C + °C ml - + ml Deg. C - + St. C % - % + % Meters - + Metry Alt - Wysokość + Wysokość VSpd - + Pr.Wznoszenia m/s - m/s + m/s Fuel Qty - + Ilość Paliwa km/h - km/h + km/h Hdg - + Kurs ASpd - + Prędk. Pow G - + G GPS - + GPS Lat,Lon (dec.deg.) - + Szer. Dł. +(dec.deg) AccX - + AccX dd-MM-yyyy hh:mm:ss - + dd-MM-yyyy +hh:mm:ss Date - + Data Amps - + Ampery AccZ - + AccZ GAlt - + Wys Volts - + Wolty Cels - + Cele Curr - Natężenie + Natężenie AccY - + AccY GSpd - + Pr.w.Ziemi Degrees - + Stopnie @@ -11295,19 +11513,19 @@ hh:mm:ss Kiedy aktywne, wysyła jakiekolwiek dane jako symulację danych telemetrii. - + Log File - + Plik Logu - + LOG Files (*.csv) - + Pliki LOGu (*.csv) - + ERROR - invalid file - + BŁĄD - błędny plik @@ -11315,82 +11533,82 @@ hh:mm:ss Simple 4-CH - Proste 4 kanały + Proste 4 kanały T-Cut - Wył Gazu + Wył Gazu Sticky T-Cut - Stały wyłącznik Gazu + Stały wyłącznik Gazu V-Tail - Motylkowy + Motylkowy Elevon\Delta - Elevon/Delta + Elevon/Delta Heli Setup - Ustawienie Heli + Ustawienie Heli Heli Setup with gyro gain control - Ustawienie heli ze stabilizacją Żyro + Ustawienie heli ze stabilizacją Żyro Gyro gain control - Stabilizacja Żyro + Stabilizacja Żyro Heli Setup (Futaba's channel assignment style) - Ustawienie heli (Ustawienie kanałów w stylu Futaby) + Ustawienie heli (Ustawienie kanałów w stylu Futaby) Heli Setup with gyro gain control (Futaba's channel assignment style) - Ustawienie heli ze stabilizacją Żyro(Ustawienie kanałów w stylu Futaby) + Ustawienie heli ze stabilizacją Żyro(Ustawienie kanałów w stylu Futaby) Gyro gain control (Futaba's channel assignment style) - Stabilizacja Żyro(Ustawienie kanałów w stylu Futaby) + Stabilizacja Żyro(Ustawienie kanałów w stylu Futaby) Servo Test - Test Serwa + Test Serwa MultiCopter - Wielowirnikowiec + Wielowirnikowiec Use Model Config Wizard - Użyj konfiguratora modelu + Użyj konfiguratora modelu Apply Template? - Dodać szablon ? + Dodać szablon ? Apply template "%1"? - Dodać szablon "%1"? + Dodać szablon "%1"? @@ -11401,7 +11619,7 @@ hh:mm:ss RUD - SK + SK @@ -11415,14 +11633,14 @@ hh:mm:ss ELE - SW + SW THR - + THR @@ -11434,7 +11652,7 @@ hh:mm:ss AIL - Lotki + Lotki @@ -11442,7 +11660,7 @@ hh:mm:ss AIL2 - Lotka2 + Lotka2 @@ -11450,7 +11668,7 @@ hh:mm:ss ELE2 - SW2 + SW2 @@ -11460,7 +11678,7 @@ hh:mm:ss FLAPS - Klapy + Klapy @@ -11470,7 +11688,7 @@ hh:mm:ss FLAP%1 - Klapy %1 + Klapy %1 @@ -11478,7 +11696,7 @@ hh:mm:ss PITCH - Pochylenie + Pochylenie @@ -11490,57 +11708,57 @@ hh:mm:ss GYRO - ŻYRO + ŻYRO SPOIL - Spoiler + Spoiler SPOIL%1 - Spoiler%1 + Spoiler%1 RUD2 - SK2 + SK2 Clear Mixes? - Wyczyść miksery? + Wyczyść miksery? Really clear existing mixes on CH6? - Na pewno wyczyścić mikser na kanale 6? + Na pewno wyczyścić mikser na kanale 6? Really clear existing mixes on CH5? - Na pewno wyczyścić mikser na kanale 5? + Na pewno wyczyścić mikser na kanale 5? ThrottlePage - + Yes Tak - + No Nie - + <br>Throttle Channel: <br>Kanał gazu: @@ -11730,30 +11948,36 @@ hh:mm:ss TreeModel - + Index - + Indeks - + Name - Nazwa + Nazwa - + Size - + Wielkość + + + + Model %1 + Translators: do NOT use accents here, this is a default model name. + Model %1 VTailPage - + First Tail Channel: Pierwszy Kanał Ogona: - + Second Tail Channel: Drugi Kanał Ogona: @@ -11761,55 +11985,55 @@ hh:mm:ss VirtualJoystickWidget - + Hld Y - + Trzymaj Y - + Hold Vertical stick position. - + Trzymaj pionową pozycję drążka. - + Fix Y - Zablokuj Y + Ustal Y - + Prevent Vertical movement of stick. - + Zabroń pionowego ruchu drążka. - + Fix X - Zablokuj X + Ustal X - + Prevent Horizontal movement of stick. - + Zabroń poziomego ruchu drążka. - + Hld X - + Trzymaj X - + Hold Horizontal stick position. - + Trzymaj poziomą pozycję drążka. WingtypeSelectionPage - + Standard Wing Standardowe Skrzydło - + Flying Wing / Deltawing Latające skrzydło / Delta @@ -12091,37 +12315,37 @@ hh:mm:ss WizardPrinter - + Plane Samolot - + Multicopter Multikopter - + Helicopter Śmigłowiec - + Model Name: Nazwa Modelu: - + Model Type: Typ Modelu: - + Options: Opcje: - + Channel %1: Kanał %1: @@ -12542,7 +12766,7 @@ m2560 dla platformy V4 Enable - + Aktywuj @@ -12552,12 +12776,12 @@ m2560 dla platformy V4 Back - + Cofnij Start - Start + Start @@ -12572,22 +12796,22 @@ m2560 dla platformy V4 Not Assigned - + Nieprzypisany Stick - + Drążek Knob/Slider %1 - + Gałka/Suwak %1 No joysticks found - Brak joysticka + Brak joysticka @@ -12603,47 +12827,53 @@ m2560 dla platformy V4 Press the Start button to start the stick range calibration procedure. You may change the channel assignments or inversion at any time. - + W celu uruchomeinia procedury kalibracji wciśnij przycisk Start. +W każdej chwili możesz zmienić przypisanie kanału lub rewers. Move sticks and pots in every direction making full movement Press Next when finished - + Porusz drążkami i potencjometrami we wszytkich kierunkach po oporach +Wciśnij Dalej kiedy skończysz Place sticks and pots in middle position. Press Next when done - + Wyśrodkuj drążki i potencjomety. +Wciśnij Dalej kiedy skończysz Map joystick channels to controls using comboboxes. Press Next when done. - + Zmapuj kanały joystika do elementów sterujących używając pól kombi. +Wciśnij Dalej kiedy skończysz. Check inversion checkbox to if necessary to reverse direction. Press Next when done. - + Zaznacz pola wyboru rewersu jeśli konieczne jest odwrócenie działania. +Wciśnij Dalej kiedy skończysz. Press OK to save configuration Press Cancel to abort joystick calibration without saving. - + Naciśnij OK w celu zapisania konfiguracji +Naciśnij Porzuć w celu zakończyć kalibrację joystika bez zapisu. Warning - Ostrzeżenie + Ostrzeżenie Calibration not complete, save anyway? - + Kalibracja nie zakończona, zapisać mimo to? From adeb088e93ecf399b8e8dac2f13a0d2f3e783771 Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Thu, 13 Apr 2017 18:31:50 +0200 Subject: [PATCH 126/203] Fix IBUS telemetry scaling (#4784) In my first implementation I guess some scalings wrong (and forgot PREC1 when trying to subtract 40) --- radio/src/telemetry/flysky_ibus.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/radio/src/telemetry/flysky_ibus.cpp b/radio/src/telemetry/flysky_ibus.cpp index d690458ea..7f54c6594 100644 --- a/radio/src/telemetry/flysky_ibus.cpp +++ b/radio/src/telemetry/flysky_ibus.cpp @@ -58,7 +58,7 @@ const FlySkySensor flySkySensors[] = { // RPM {0x02, ZSTR_RPM, UNIT_RAW, 0}, // External voltage - {0x03, ZSTR_A3, UNIT_VOLTS, 1}, + {0x03, ZSTR_A3, UNIT_VOLTS, 2}, // RX SNR {FS_ID_SNR, ZSTR_RX_SNR, UNIT_DB, 0}, // RX Noise @@ -66,7 +66,7 @@ const FlySkySensor flySkySensors[] = { // RX RSSI (0xfc) {FS_ID_RSSI, ZSTR_RSSI, UNIT_DB, 0}, // RX error rate - {0xfe, ZSTR_RX_QUALITY, UNIT_RAW, 1}, + {0xfe, ZSTR_RX_QUALITY, UNIT_RAW, 0}, // 0xff is an unused sensor slot // Pseudo sensor for TRSSI {TX_RSSI_ID, ZSTR_TX_RSSI, UNIT_RAW, 0}, @@ -102,7 +102,7 @@ static void processFlySkySensor(const uint8_t *packet) value = -value; else if (id == FS_ID_TEMP) // Temperature sensors have 40 degree offset - value -= 40; + value -= 400; setTelemetryValue(TELEM_PROTO_FLYSKY_IBUS, id, 0, instance, value, sensor->unit, sensor->precision); return; } From c152f983da9f1cb15b9475fa4778f0d0fad682b2 Mon Sep 17 00:00:00 2001 From: mhotar Date: Thu, 13 Apr 2017 21:57:42 +0200 Subject: [PATCH 127/203] yerico add model and category icons --- companion/src/themes/yerico/16/add_category.png | Bin 0 -> 869 bytes companion/src/themes/yerico/16/add_model.png | Bin 0 -> 889 bytes companion/src/themes/yerico/24/add_category.png | Bin 0 -> 1490 bytes companion/src/themes/yerico/24/add_model.png | Bin 0 -> 1456 bytes companion/src/themes/yerico/32/add_category.png | Bin 0 -> 2074 bytes companion/src/themes/yerico/32/add_model.png | Bin 0 -> 2070 bytes companion/src/themes/yerico/48/add_category.png | Bin 0 -> 3356 bytes companion/src/themes/yerico/48/add_model.png | Bin 0 -> 3363 bytes 8 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 companion/src/themes/yerico/16/add_category.png create mode 100644 companion/src/themes/yerico/16/add_model.png create mode 100644 companion/src/themes/yerico/24/add_category.png create mode 100644 companion/src/themes/yerico/24/add_model.png create mode 100644 companion/src/themes/yerico/32/add_category.png create mode 100644 companion/src/themes/yerico/32/add_model.png create mode 100644 companion/src/themes/yerico/48/add_category.png create mode 100644 companion/src/themes/yerico/48/add_model.png diff --git a/companion/src/themes/yerico/16/add_category.png b/companion/src/themes/yerico/16/add_category.png new file mode 100644 index 0000000000000000000000000000000000000000..d796af414f6a1eead1420eabd64dc9a101a47b26 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b/launchpad/prepare.sh @@ -35,7 +35,7 @@ sed -i "s/__VERSION_SUFFIX__/${suffix}/g" ../debian/rules # remove old package and prepare new one cd .. rm -f ../opentx-companion22_*${distro}* -debuild -S -sa -I -Ijenkins -Ilaunchpad -Idoc -I*.luac +debuild -S -sa -I -Ijenkins -Ilaunchpad -Idoc -Ibuild -I*.luac echo "Use this command to upload to launchpad:" echo " dput ppa:opentx-test/ppa opentx-companion22_.changes" diff --git a/launchpad/trusty/changelog b/launchpad/trusty/changelog index 4c4d3a86f..b928ddbf0 100644 --- a/launchpad/trusty/changelog +++ b/launchpad/trusty/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N369~trusty) trusty; urgency=low + + * New release 2.2.0~N369 RC16 + + -- projectkk2glider Sat, 15 Apr 2017 09:58:45 +0200 + opentx-companion22 (2.2.0~N366.1~trusty) trusty; urgency=low * New release 2.2.0~N366 RC14 diff --git a/launchpad/xenial/changelog b/launchpad/xenial/changelog index 5929c6e3b..1fe96e105 100644 --- a/launchpad/xenial/changelog +++ b/launchpad/xenial/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N369~xenial) xenial; urgency=low + + * New release 2.2.0~N369 RC16 + + -- projectkk2glider Sat, 15 Apr 2017 09:58:51 +0200 + opentx-companion22 (2.2.0~N366~xenial) xenial; urgency=low * New release 2.2.0~N366 RC14 diff --git a/launchpad/yakkety/changelog b/launchpad/yakkety/changelog index 230487cce..4eb2dd6a2 100644 --- a/launchpad/yakkety/changelog +++ b/launchpad/yakkety/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N369~yakkety) yakkety; urgency=low + + * New release 2.2.0~N369 RC16 + + -- projectkk2glider Sat, 15 Apr 2017 09:58:55 +0200 + opentx-companion22 (2.2.0~N366~yakkety) yakkety; urgency=low * New release 2.2.0~N366 RC14 From 1d4ec6f73e0105961c83cfa9f41b4d560f6077ae Mon Sep 17 00:00:00 2001 From: 3djc Date: Sun, 16 Apr 2017 10:18:52 +0200 Subject: [PATCH 129/203] 3djc/fix #4795 (#4802) * Prevent popup in undue places * Working fix ? --- .../gui/128x64/model_special_functions.cpp | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/radio/src/gui/128x64/model_special_functions.cpp b/radio/src/gui/128x64/model_special_functions.cpp index 7a50aff6d..d120965f5 100644 --- a/radio/src/gui/128x64/model_special_functions.cpp +++ b/radio/src/gui/128x64/model_special_functions.cpp @@ -68,7 +68,7 @@ void onCustomFunctionsFileSelectionMenu(const char * result) storageDirty(eeFlags); } } -#endif +#endif // CPUARM && SDCARD #if defined(PCBX7) @@ -171,7 +171,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF } POPUP_MENU_START(onCustomFunctionsMenu); } -#endif +#endif // PCBX7 for (uint8_t i=0; iactiveSwitches & ((MASK_CFN_TYPE)1 << k)) ? BOLD : 0)); if (active || AUTOSWITCH_ENTER_LONG()) CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); -#endif +#endif //CPUARM #if defined(CPUARM) if (func == FUNC_OVERRIDE_CHANNEL && functions != g_model.customFn) { func = CFN_FUNC(cfn) = func+1; @@ -252,7 +252,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF #endif break; } -#endif +#endif // GVARS #if defined(CPUARM) else if (func == FUNC_SET_TIMER) { maxParam = MAX_TIMERS-1; @@ -260,7 +260,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF if (active) CFN_TIMER_INDEX(cfn) = checkIncDec(event, CFN_TIMER_INDEX(cfn), 0, maxParam, eeFlags); break; } -#endif +#endif // CPUARM else if (attr) { REPEAT_LAST_CURSOR_MOVE(); } @@ -294,7 +294,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF #else val_max = FUNC_RESET_PARAM_LAST; lcdDrawTextAtIndex(MODEL_SPECIAL_FUNC_3RD_COLUMN, y, STR_VFSWRESET, CFN_PARAM(cfn), attr); -#endif +#endif // CPUARM } #if defined(OVERRIDE_CHANNEL_FUNCTION) else if (func == FUNC_OVERRIDE_CHANNEL) { @@ -304,14 +304,12 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF val_min = -LIMIT_EXT_PERCENT; val_max = +LIMIT_EXT_PERCENT; lcdDrawNumber(MODEL_SPECIAL_FUNC_3RD_COLUMN, y, val_displayed, attr|LEFT); } -#endif +#endif // OVERRIDE_CHANNEL_FUNCTION #if defined(CPUARM) else if (func >= FUNC_SET_FAILSAFE && func <= FUNC_BIND) { val_max = NUM_MODULES-1; lcdDrawTextAtIndex(MODEL_SPECIAL_FUNC_3RD_COLUMN, y, "\004Int.Ext.", CFN_PARAM(cfn), attr); } -#endif -#if defined(CPUARM) else if (func == FUNC_SET_TIMER) { val_max = 539*60+59; drawTimer(MODEL_SPECIAL_FUNC_3RD_COLUMN, y, val_displayed, attr|LEFT, attr); @@ -358,10 +356,12 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF else if (func == FUNC_PLAY_VALUE) { val_max = MIXSRC_LAST_TELEM; drawSource(MODEL_SPECIAL_FUNC_3RD_COLUMN, y, val_displayed, attr); - INCDEC_SET_FLAG(eeFlags | INCDEC_SOURCE); - INCDEC_ENABLE_CHECK(isSourceAvailable); + if (active) { + INCDEC_SET_FLAG(eeFlags | INCDEC_SOURCE); + INCDEC_ENABLE_CHECK(isSourceAvailable); + } } -#endif +#endif // CPUARM && SDCARD #if defined(CPUARM) else if (func == FUNC_VOLUME) { val_max = MIXSRC_LAST_CH; @@ -386,7 +386,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF } #else lcdDrawNumber(MODEL_SPECIAL_FUNC_3RD_COLUMN, y, val_displayed+PROMPT_CUSTOM_BASE, attr|LEFT); -#endif +#endif // GVARS } else if (func == FUNC_PLAY_BOTH) { lcdDrawChar(MODEL_SPECIAL_FUNC_3RD_COLUMN+3*FWNUM, y, '|', attr); @@ -439,7 +439,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF #else val_max = 1; lcdDrawTextAtIndex(MODEL_SPECIAL_FUNC_3RD_COLUMN, y, PSTR("\003-=1+=1"), val_displayed, attr); -#endif +#endif // PCBX7 break; } @@ -454,7 +454,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF val_displayed = 0; } } -#endif +#endif // GVARS else if (attr) { REPEAT_LAST_CURSOR_MOVE(); } @@ -477,7 +477,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF #else if (active) { CFN_PARAM(cfn) = CHECK_INCDEC_PARAM(event, val_displayed, val_min, val_max); -#endif +#endif // PCBX7 } break; } From f795528d219ee059767517798703bb41336d8a20 Mon Sep 17 00:00:00 2001 From: Sebastien Charpentier Date: Sun, 16 Apr 2017 20:58:14 +0200 Subject: [PATCH 130/203] Translate last missing field + correct some translation (confirmation box) when deleting models/categories. (#4797) --- companion/src/translations/companion_fr.ts | 406 +++++++++++---------- 1 file changed, 205 insertions(+), 201 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 4b1e95b45..6a97bdd3c 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -60,42 +60,42 @@ AppPreferencesDialog - + Edit Settings Éditer les réglages - + Radio Profile Profil de radio - + Default Channel Order Ordre des voies par défaut - + Build Options Options de compilation - + Menu Language Langue des menus - + Default Stick Mode Mode par défaut - + Select Image Sélectionner une image - + Mode selection: Mode 1: @@ -136,410 +136,410 @@ Manche Droit: Profondeur, Direction - + Mode 1 (RUD ELE THR AIL) Mode 1 (DIR PROF GAZ AIL) - + Mode 2 (RUD THR ELE AIL) Mode 2 (DIR GAZ PROF AIL) - + Mode 3 (AIL ELE THR RUD) Mode 3 (AIL PROF GAZ DIR) - + Mode 4 (AIL THR ELE RUD) Mode 4 (AIL GAZ PROF DIR) - + Splash Screen Ecran d'accueil - - + + The profile specific folder, if set, will override general Backup folder Dossier de sauvegarde spécifique au profil courant, si défini remplace le réglage de l'application - + Backup folder Dossier de sauvegarde - + If set it will override the application general setting Si défini, remplace le réglage de l'application pour ce profil - + if set, will override general backup enable Si défini, remplace le réglage de l'application pour ce profil - + <html><head/><body><p>Channel order</p><p><br/></p><p>Defines the order of the default mixes created on a new model.</p></body></html> <html><head/><body><p>Ordre des voies</p><p><br/></p><p>Détermine l'ordre des mixages par défaut sur un nouveau modèle.</p></body></html> - + R E T A D P G A - + R E A T D P A G - + R T E A D G P A - + R T A E D G A P - + R A E T D A P G - + R A T E D A G P - + E R T A P D G A - + E R A T P D A G - + E T R A P G D A - + E T A R P G A D - + E A R T P A D G - + E A T R P A G D - + T R E A G D P A - + T R A E G D A P - + T E R A G P D A - + T E A R G P A D - + T A R E G A D P - + T A E R G A P D - + A R E T A D P G - + A R T E A D G P - + A E R T A P D G - + A E T R A P G D - + A T R E A G D P - + A T E R A G P D - - - - - + + + + + Select Folder Sélectionner dossier - + Select Executable Sélectionner exécutable - + Use OpenTX firmware nightly builds Utlilser les nightly builds du firmware - + Use Companion nightly builds Utlilser les nightly builds de Companion - + Simulator Volume Gain Gain de volume du simulateur - + Profile Name Nom du profil - + Clear Image Effacer l'image - + Append version number to FW file name Ajouter le numéro de version au nom du fichier téléchargé - + Offer to write FW to Tx after download Proposer de transférer le firmware à la radio après téléchargement - + Radio Type Type de radio - + Other Settings Autres réglages - + General Settings Paramètres généraux - + SD Structure path Chemin de la structure de la carte SD - + Set voice language. May be different from firmware language Langue des voix. Peut être différente de la langue du firmware - + Voice Language Langue des voix - + Application Settings Réglages de l'application - + Show splash screen when Companion starts Afficher l'écran d'accueil au lancement de Companion - + Automatic check for Companion updates Vérifier la présence de mises à jour de Companion automatiquement - - + + Enable automatic backup before writing firmware Sauvegarder les réglages et modèles automatiquement lors des transferts - + Automatic check for OpenTX firmware updates Vérifier la présence de mises à jour de firmware automatiquement - + Splash Screen Library Bibliothèque d'écrans d'accueil - + Files to keep Fichiers à conserver - + Google Earth Executable Exécutable Google Earth - + Only show user splash images Ne montrer que les images de l'utilisateur - + Show user and companion splash images Montrer les images de Companion et de l'utilisateur - + User Splash Screens Ecrans d'accueil personnalisés - + Automatic Backup Folder Dossier de sauvegardes automatiques - + Simulator Settings Paramètres du simulateur - + Simulator BackLight Rétroéclairage du simulateur - + Enable Actif - + Action on New Model Action par défaut "Ajout Modèle" - + Use model wizard Assistant - + Open model editor Éditer modèle - + Just create the model Créer modèle - + <html><head/><body><p>This option maintains the behaviour from older OpenTx versions where empty model slots are preserved when a model is deleted or moved. </p><p>When this option is de-selected, the other models may be re-arranged to fill the gap left by the removed model.</p></body></html> <html><head/><body><p><b><u>/!\</u> Uniquement pour les radios sans catégories <u>/!\</u></b></p><p>Cette option maintient le comportement des anciennes versions d’OpenTx où les emplacements des modèles vides sont conservés lorsqu'un modèle est supprimé ou déplacé.</p><p>Lorsque cette option est désélectionnée, les autres modèles peuvent être réarrangés pour combler l'écart laissé par le modèle supprimé.</p></body></html> - + Remove empty model slots when deleting models (only applies for radios w/out categories) Supprimer les emplacements vides lors de la suppression de modèles - + Blue Bleu - + Green Vert - + Red Rouge - + Orange Orange - + Yellow Jaune - + Joystick - + Calibrate Calibrer - + Simulator capture folder Dossier des captures d'écran - + Only capture to clipboard Capturer dans le presse-papiers uniquement - + Remember simulator switch values Mémoriser les positions des inters du simulateur @@ -4747,76 +4747,73 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b MdiChild - - - - - - - + + + + + + + Error Erreur - + Unable to find file %1! Fichier %1 introuvable ! - - - - + Save As Enregister Sous - + Alt+Shift+E - + Ctrl+Alt+C - + Ctrl+Alt+V - + Alt+Shift+S - + Alt+C - + Alt+A - + Alt+R - + Alt+W - + Alt+U - + %n Model(s) As in "Copy 3 Models" or "Cut 1 Model" or "Delete 3 Models" action). @@ -4825,7 +4822,7 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b - + %n Model(s) As in "Paste 3 Models" or "Insert 1 Model." @@ -4834,7 +4831,7 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b - + %n Category(ies) As in "Delete 3 Categories" or "Delete 1 Category." @@ -4843,237 +4840,238 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b - + Nothing selected Rien n'a été sélectionné - + Rename Category Renommer la catégorie - + Edit Model Éditer le modèle - + Cut Couper - + Copy Copier - + Paste Coller - + Insert Insérer - + Edit Radio Settings Éditer les réglages radio - + Copy Radio Settings Copier les réglages radio - + Paste Radio Settings Coller les réglages radio - + Simulate Radio Simuler la radio - + Add Category Ajouter catégorie - + Category Catégorie - + Add Model Ajouter modèle - + Model Modèle - + Restore from Backup Restaurer depuis une sauvegarde - + Model Wizard Assistant de configuration du modèle - + Set as Default Définir par défaut - + Print Model Imprimer modèle - + Simulate Model Simuler modèle - + Duplicate Model Dupliquer modèle - + Show Category Actions Toolbar Afficher la barre d'outils "Catégorie" - + Show Radio Actions Toolbar Afficher la barre d'outils "Radio" - + Show Model Actions Toolbar Afficher la barre d'outils "Modèle" - + Category index out of range. Index de catégorie hors limite. - + Cannot delete the last category. Impossible d'effacer la dernière catégorie. - + This category is not empty! Catégorie non vide ! - + Cannot insert model, last model in list would be deleted. Impossible d'insérer le modèle, le dernier modèle dans la liste serait supprimé. - + Cannot add model, could not find an available model slot. Impossible d'ajouter un modèle, aucun emplacement libre n’est disponible. - + New model + Translators: do NOT use accents here, this is a default model name. Nouveau modele - + Cannot paste model, out of available model slots. Impossible de coller le modèle, aucun emplacement libre n’est disponible. - + You are replacing an existing model, are you sure? Vous allez écraser un modèle existant, êtes-vous sûr ? - + Delete %n selected model(s)? - Supprimer le modèle sélectionné %n ? - Supprimer les modèles sélectionnés %n ? + Supprimer le modèle sélectionné ? + Supprimer les %n modèles sélectionnés ? - + Delete %n selected category(ies)? - Supprimer la catégorie sélectionnée %n ? - Supprimer les catégories sélectionnées %n ? + Supprimer la catégorie sélectionnée ? + Supprimer les %n catégories sélectionnées ? - + Cannot duplicate model, could not find an available model slot. Impossible de dupliquer le modèle, aucun emplacement libre n’est disponible. - + Unable to find Horus radio SD card! Impossible de trouver la carte SD de la Horus ! - + Models and Settings written Modèle et réglages écrit - + Cannot write temporary file! Ecriture de fichier temporaire impossible ! - + Editing model %1: Édition du modèle %1 : - + Error reading file %1: %2. Fichier %1 corrompu: %2. - + Error opening file %1: %2. Erreur à l'ouverture du fichier %1: %2. - + Delete Supprimer - + Move to Category Déplacer dans la catégorie - + Alt+S - + Models and settings will be automatically converted. If that is not what you intended, please close the file and choose the correct radio type/profile before reopening it. @@ -5082,7 +5080,7 @@ Si ce n'est pas ce que vous voulez, fermer le fichier et choisissez la bonne radio avant de l'ouvrir.à nouveau. - + Do you want to overwrite radio general settings? Voulez-vous vraiment écraser les paramètres généraux ? @@ -5092,33 +5090,33 @@ et choisissez la bonne radio avant de l'ouvrir.à nouveau. octets libres - + New category Translators do NOT use accent for this, this is the default category name on Horus. Nouvelle categorie - + Companion - + Open backup Models and Settings file Ouvrir la sauvegarde de réglages et modèles - + Warning Avertissement - + Invalid binary backup File %1 Fichier de sauvegarde %1 invalide - + %1 has been modified. Do you want to save your changes? %1 a été modifié. @@ -7345,7 +7343,7 @@ Mixage actif par défaut si non-renseigné. - + Uknown error during Simulator startup. Erreur inconnue pendant le démarrage du simulateur. @@ -8790,7 +8788,7 @@ L'équipe OpenTX. Amp. Positive - + Models Translators do NOT use accent for this, this is the default category name on Horus. @@ -8832,44 +8830,44 @@ L'équipe OpenTX. Radio disponibles: - + WARNING: couldn't initialize SDL: %1 ATTENTION: erreur initialisation SDL: %1 - + ERROR: No simulator libraries available. ERREUR: pas de simulateur disponible. - + Radio profile ID or Name to use for simulator. Nom du profil radio pour le simulateur. - + Radio type to simulate (usually defined in profile). Type de radio à simuler (souvent défini dans le profil). - + show this help text afficher ce texte d'aide - + Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] Utilisation: simulator [OPTION]... [EEPROM.BIN FICHIER OUT REPERTOIRE DE DONNER] - + Options: - + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. Profile ID: [%1]; Radio ID: [%2]; Data File: [%3] @@ -8878,7 +8876,7 @@ Data File: [%3] Fichier de Données: [%3] - + ERROR: Radio profile or simulator firmware not found. Profile ID: [%1]; Radio ID: [%2] ERREUR: Profil radio ou firmware du simulateur non trouvé @@ -10075,67 +10073,67 @@ La valeur par défaut est configurée dans le profil radio sélectionné.Simulateur Radio (%1) - + Could not determine startup data source. Impossible de déterminer les données source. - + Could not load data, possibly wrong format. Impossible de charger les données, mauvais format. - + Data Load Error Erreur de lecture des données - + Invalid startup data provided. Plese specify a proper file/path. Données de démarrage fournies non valides. Veuillez spécifier un fichier/chemin approprié. - + Simulator Startup Error Erreur de démarrage du simulateur - + Error saving data: could open file for writing: '%1' Erreur de sauvegarde des données: impossible d'écrire le fichier '%1' - + Error saving data: could not get data from simulator interface. Erreur de sauvegarde des données: impossible de récupérer les données depuis l'interface de simulation. - + An unexpected error occurred while attempting to save radio data to file '%1'. Une erreur inattendue s'est produite lors de l'enregistrement des données radio dans le fichier '%1'. - + Data Save Error Erreur de sauvegarde des données - + Warning Avertissement - + Cannot open joystick, joystick disabled Impossible d'accéder au Joystick, Joystick désactivé - + Radio firmware error: %1 Erreur firmware radio: %1 - + - Flight Mode %1 (#%2) - Phase de Vol %1 (#%2) @@ -11315,17 +11313,17 @@ hh:mm:ss Transmet les valeurs non vides au simulateur. - + Log File Fichier de Log - + LOG Files (*.csv) Fichier LOG (*.csv) - + ERROR - invalid file ERREUR - fichier non valide @@ -11764,6 +11762,12 @@ Extra long : bips extra longs. Size Taille + + + Model %1 + Translators: do NOT use accents here, this is a default model name. + Modele %1 + VTailPage From 5d5c915ea96c518ceab2d4d7ac7fd95b9f98c6ac Mon Sep 17 00:00:00 2001 From: Andre Bernet Date: Sun, 16 Apr 2017 21:01:49 +0200 Subject: [PATCH 131/203] [Horus] Language specific char handling was missing in text view --- radio/src/gui/480x272/view_text.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/radio/src/gui/480x272/view_text.cpp b/radio/src/gui/480x272/view_text.cpp index 71a31127f..8b9f471b8 100644 --- a/radio/src/gui/480x272/view_text.cpp +++ b/radio/src/gui/480x272/view_text.cpp @@ -51,7 +51,7 @@ void readTextFile(int & lines_count) escape = 1; continue; } - else if (c!='\\' && escape>0 && escape<3) { + else if (c!='\\' && escape>0 && escape<4) { escape_chars[escape-1] = c; if (escape == 2 && !strncmp(escape_chars, "up", 2)) { c = '\300'; @@ -61,6 +61,13 @@ void readTextFile(int & lines_count) c = '\301'; escape = 0; } + else if (escape == 3) { + int val = atoi(escape_chars); + if (val >= 200 && val < 225) { + c = '\200' + val-200; + } + escape = 0; + } else { escape++; continue; From 1d6f2acbc2bb6329b06a72dca91dc4e0e167f007 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sun, 16 Apr 2017 15:03:31 -0400 Subject: [PATCH 132/203] [Simulator] Refactor CLI option parsing, add "--sd-path" and "--start-with" options (#4798) * [Simulator] Refactor CLI option parsing to use QCommandLineParser, remove QxtCommandOptions external lib; Add "--sd-path" and "--start-with" options; Qualify all translatable text (SimulatorMain context). * Add date string to version. --- companion/src/CMakeLists.txt | 4 +- companion/src/simulator.cpp | 272 ++++-- .../src/thirdparty/qxtcommandoptions/AUTHORS | 7 - .../src/thirdparty/qxtcommandoptions/CHANGES | 230 ----- .../qxtcommandoptions/CMakeLists.txt | 9 - .../src/thirdparty/qxtcommandoptions/LICENSE | 89 -- .../thirdparty/qxtcommandoptions/cpl1.0.txt | 213 ---- .../thirdparty/qxtcommandoptions/lgpl-2.1.txt | 504 ---------- .../qxtcommandoptions/qxtcommandoptions.cpp | 914 ------------------ .../qxtcommandoptions/qxtcommandoptions.h | 124 --- .../thirdparty/qxtcommandoptions/qxtglobal.h | 207 ---- 11 files changed, 196 insertions(+), 2377 deletions(-) delete mode 100644 companion/src/thirdparty/qxtcommandoptions/AUTHORS delete mode 100644 companion/src/thirdparty/qxtcommandoptions/CHANGES delete mode 100644 companion/src/thirdparty/qxtcommandoptions/CMakeLists.txt delete mode 100644 companion/src/thirdparty/qxtcommandoptions/LICENSE delete mode 100644 companion/src/thirdparty/qxtcommandoptions/cpl1.0.txt delete mode 100644 companion/src/thirdparty/qxtcommandoptions/lgpl-2.1.txt delete mode 100644 companion/src/thirdparty/qxtcommandoptions/qxtcommandoptions.cpp delete mode 100644 companion/src/thirdparty/qxtcommandoptions/qxtcommandoptions.h delete mode 100644 companion/src/thirdparty/qxtcommandoptions/qxtglobal.h diff --git a/companion/src/CMakeLists.txt b/companion/src/CMakeLists.txt index 16432924a..cad619d2f 100644 --- a/companion/src/CMakeLists.txt +++ b/companion/src/CMakeLists.txt @@ -104,7 +104,6 @@ include_directories( ${COMPANION_SRC_DIRECTORY} ${COMPANION_SRC_DIRECTORY}/shared ${SIMU_SRC_DIRECTORY} - ${COMPANION_SRC_DIRECTORY}/thirdparty/qxtcommandoptions ${COMPANION_SRC_DIRECTORY}/thirdparty/qcustomplot ${COMPANION_SRC_DIRECTORY}/thirdparty/miniz ${COMPANION_SRC_DIRECTORY}/storage @@ -207,7 +206,6 @@ add_subdirectory(generaledit) add_subdirectory(simulation) add_subdirectory(storage) add_subdirectory(thirdparty/qcustomplot) -add_subdirectory(thirdparty/qxtcommandoptions) ############# Companion ############### @@ -315,7 +313,7 @@ PrintTargetReport("${COMPANION_NAME}") set(simu_SRCS simulator.cpp ) add_executable(${SIMULATOR_NAME} MACOSX_BUNDLE ${WIN_EXECUTABLE_TYPE} ${simu_SRCS} ${icon_RC}) -target_link_libraries(${SIMULATOR_NAME} PRIVATE simulation ${CPN_COMMON_LIB} storage qxtcommandoptions ${PTHREAD_LIBRARY} ${SDL_LIBRARY} ${WIN_LINK_LIBRARIES}) +target_link_libraries(${SIMULATOR_NAME} PRIVATE simulation ${CPN_COMMON_LIB} storage ${PTHREAD_LIBRARY} ${SDL_LIBRARY} ${WIN_LINK_LIBRARIES}) ############# Install #################### diff --git a/companion/src/simulator.cpp b/companion/src/simulator.cpp index 559318ec7..2f8d3f0f8 100644 --- a/companion/src/simulator.cpp +++ b/companion/src/simulator.cpp @@ -19,6 +19,7 @@ */ #include +#include #include #include #include @@ -36,7 +37,6 @@ #include "simulatormainwindow.h" #include "simulatorstartupdialog.h" #include "storage.h" -#include "qxtcommandoptions.h" #include "translations.h" #include "version.h" @@ -44,28 +44,188 @@ using namespace Simulator; int finish(int exitCode); -void showMessage(const QString & message, enum QMessageBox::Icon icon = QMessageBox::NoIcon) +void showMessage(const QString & message, enum QMessageBox::Icon icon = QMessageBox::NoIcon, bool useConsole = false) { + if (useConsole) { + if (icon < QMessageBox::Warning) + QTextStream(stdout) << message << endl; + else + QTextStream(stderr) << message << endl; + + return; + } + // use GUI QMessageBox msgBox; - msgBox.setText(message); + QString escMsg(message); + escMsg.replace("<", "<"); + msgBox.setText("
" + escMsg + "
"); msgBox.setIcon(icon); msgBox.exec(); } -void sharedHelpText(QTextStream &stream) +const QString sharedHelpText() { + QString ret; + QTextStream stream(&ret); // list all available profiles - stream << endl << QObject::tr("Available profiles:") << endl; + stream << endl << QApplication::translate("SimulatorMain", "Available profiles:") << endl; QMapIterator pi(g.getActiveProfiles()); while (pi.hasNext()) { pi.next(); - stream << "\t" << QObject::tr("ID: ") << pi.key() << QObject::tr(" Name: ") << pi.value() << endl; + stream << "\t" << QApplication::translate("SimulatorMain", "ID: ") << pi.key() << "; " << QApplication::translate("SimulatorMain", "Name: ") << pi.value() << endl; } // list all available radios - stream << endl << QObject::tr("Available radios:") << endl; + stream << endl << QApplication::translate("SimulatorMain", "Available radios:") << endl; foreach(QString name, SimulatorLoader::getAvailableSimulators()) { stream << "\t" << name << endl; } + return ret; +} + +void showHelp(QCommandLineParser & parser, const QString & addMsg = QString(), int exitCode = 0) { + QString msg = "\n"; + if (!addMsg.isEmpty()) + msg.append(addMsg).append("\n\n"); + msg.append(parser.helpText()); + msg.append(sharedHelpText()); + // display + showMessage(msg, (exitCode ? QMessageBox::Warning : QMessageBox::Information)); +} + +enum CommandLineParseResult +{ + CommandLineNone, + CommandLineFound, + CommandLineExitOk, + CommandLineExitErr +}; + +CommandLineParseResult cliOptions(SimulatorOptions * simOptions, int * profileId) +{ + QCommandLineParser cliOptions; + bool cliOptsFound = false; + int pId = *profileId; + + const QCommandLineOption optHelp = cliOptions.addHelpOption(); + const QCommandLineOption optVer = cliOptions.addVersionOption(); + + const QCommandLineOption optProfi(QStringList() << "profile" << "p", + QApplication::translate("SimulatorMain", "Radio profile ID or Name to use for simulator."), + QApplication::translate("SimulatorMain", "profile")); + + const QCommandLineOption optRadio(QStringList() << "radio" << "r", + QApplication::translate("SimulatorMain", "Radio type to simulate (usually defined in profile)."), + QApplication::translate("SimulatorMain", "radio")); + + const QCommandLineOption optSdDir(QStringList() << "sd-path" << "s", + QApplication::translate("SimulatorMain", "Directory containing the SD card image to use. The default is configured in the chosen Radio Profile."), + QApplication::translate("SimulatorMain", "path")); + + const QCommandLineOption optStart(QStringList() << "start-with" << "w", + QApplication::translate("SimulatorMain", "Data source type to use (applicable to Horus only). One of:") + " (file|folder|sd)", + QApplication::translate("SimulatorMain", "type")); + + cliOptions.addPositionalArgument(QApplication::translate("SimulatorMain", "data-source"), + QApplication::translate("SimulatorMain", "Radio data (.bin/.eeprom/.otx) image file to use OR data folder path (for Horus-style radios).\n" + "NOTE: any existing EEPROM data incompatible with the selected radio type may be overwritten!"), + QApplication::translate("SimulatorMain", "[data-source]")); + + cliOptions.addOption(optProfi); + cliOptions.addOption(optRadio); + cliOptions.addOption(optSdDir); + cliOptions.addOption(optStart); + + QStringList args = QCoreApplication::arguments(); +#ifdef Q_OS_WIN + // For backwards compat. with QxtCommandOptions, convert Windows-style CLI switches (/opt) since QCommandLineParser doesn't support them + for (int i=0; i < args.size(); ++i) { + args[i].replace(QRegExp("^/([^\\s]{2,10})$"), "--\\1"); // long opts + args[i].replace(QRegExp("^/([^\\s]){1}$"), "-\\1"); // short opts + } +#endif + + if (!cliOptions.parse(args)) { + showHelp(cliOptions, cliOptions.errorText()); + return CommandLineExitErr; + } + + if (cliOptions.isSet(optHelp)) { + showHelp(cliOptions); + return CommandLineExitOk; + } + + if (cliOptions.isSet(optVer)) { + showMessage(APP_SIMULATOR " v" VERSION " " __DATE__, QMessageBox::Information); + return CommandLineExitOk; + } + + if (cliOptions.isSet(optProfi)) { + bool chk; + pId = cliOptions.value(optProfi).toInt(&chk); + if (!chk) + pId = g.getActiveProfiles().key(cliOptions.value(optProfi), -1); + + if (!g.getActiveProfiles().contains(pId)) { + showHelp(cliOptions, QApplication::translate("SimulatorMain", "Error: Profile ID %1 was not found.").arg(pId)); + return CommandLineExitErr; + } + + *simOptions = g.profile[pId].simulatorOptions(); + cliOptsFound = true; + } + + if (cliOptions.isSet(optRadio)) { + simOptions->firmwareId = cliOptions.value(optRadio); + cliOptsFound = true; + } + + if (cliOptsFound || (simOptions->dataFile.isEmpty() && !simOptions->firmwareId.isEmpty())) { + // this constructs a new default radio data file name in the user-configured eeprom directory + simOptions->dataFile = SimulatorStartupDialog::radioEepromFileName(simOptions->firmwareId, g.eepromDir()); + } + + if (cliOptions.isSet(optSdDir)) { + simOptions->sdPath = cliOptions.value(optSdDir); + cliOptsFound = true; + } + + if (cliOptions.positionalArguments().size()) { + QString datasrc = cliOptions.positionalArguments().at(0); + if (datasrc.contains(QRegExp(".*\\.[\\w]{2,6}$"))) { + simOptions->dataFile = datasrc; + simOptions->startupDataType = SimulatorOptions::START_WITH_FILE; + } + else { + simOptions->dataFolder = datasrc; + simOptions->startupDataType = SimulatorOptions::START_WITH_FOLDER; + } + cliOptsFound = true; + } + + if (cliOptions.isSet(optStart)) { + QString stTyp = cliOptions.value(optStart); + if (stTyp == "file") { + simOptions->startupDataType = SimulatorOptions::START_WITH_FILE; + } + else if (stTyp == "folder") { + simOptions->startupDataType = SimulatorOptions::START_WITH_FOLDER; + } + else if (stTyp == "sd") { + simOptions->startupDataType = SimulatorOptions::START_WITH_SDPATH; + } + else { + showHelp(cliOptions, QApplication::translate("SimulatorMain", "Unrecognized startup data source type: %1").arg(stTyp)); + return CommandLineExitErr; + } + + cliOptsFound = true; + } + + *profileId = pId; + if (cliOptsFound) + return CommandLineFound; + else + return CommandLineNone; } int main(int argc, char *argv[]) @@ -78,6 +238,7 @@ int main(int argc, char *argv[]) QApplication app(argc, argv); app.setApplicationName(APP_SIMULATOR); + app.setApplicationVersion(VERSION); app.setOrganizationName(COMPANY); app.setOrganizationDomain(COMPANY_DOMAIN); @@ -88,9 +249,7 @@ int main(int argc, char *argv[]) CustomDebug::setFilterRules(); - g.init(); - - QString resultMsg; + g.init(); // init settings before installing translations Translations::installTranslators(); @@ -103,41 +262,21 @@ int main(int argc, char *argv[]) sdlFlags |= SDL_INIT_AUDIO; #endif if (SDL_Init(sdlFlags) < 0) { - showMessage(QObject::tr("WARNING: couldn't initialize SDL:\n%1").arg(SDL_GetError()), QMessageBox::Warning); + showMessage(QApplication::translate("SimulatorMain", "WARNING: couldn't initialize SDL:\n%1").arg(SDL_GetError()), QMessageBox::Warning); } #endif - QxtCommandOptions cliOptions; - bool cliOptsFound = false; - int profileId = (g.simuLastProfId() > -1 ? g.simuLastProfId() : g.id()); - SimulatorOptions simOptions = g.profile[profileId].simulatorOptions(); - registerStorageFactories(); registerOpenTxFirmwares(); SimulatorLoader::registerSimulators(); if (!SimulatorLoader::getAvailableSimulators().size()) { - showMessage(QObject::tr("ERROR: No simulator libraries available."), QMessageBox::Critical); + showMessage(QApplication::translate("SimulatorMain", "ERROR: No simulator libraries available."), QMessageBox::Critical); return finish(3); } - cliOptions.add("profile", QObject::tr("Radio profile ID or Name to use for simulator."), QxtCommandOptions::ValueRequired); - cliOptions.alias("profile", "p"); - cliOptions.add("radio", QObject::tr("Radio type to simulate (usually defined in profile)."), QxtCommandOptions::ValueRequired); - cliOptions.alias("radio", "r"); - cliOptions.add("help", QObject::tr("show this help text")); - cliOptions.alias("help", "h"); - cliOptions.parse(QCoreApplication::arguments()); - if (cliOptions.count("help") || cliOptions.showUnrecognizedWarning()) { - QTextStream stream(&resultMsg); - stream << QObject::tr("Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] ") << endl << endl; - stream << QObject::tr("Options:") << endl; - cliOptions.showUsage(false, stream); - sharedHelpText(stream); - // display - showMessage(resultMsg, QMessageBox::Information); - return finish(1); - } + int profileId = (g.simuLastProfId() > -1 ? g.simuLastProfId() : g.id()); + SimulatorOptions simOptions = g.profile[profileId].simulatorOptions(); // TODO : defaults should be set in Profile::init() if (simOptions.firmwareId.isEmpty()) @@ -147,44 +286,18 @@ int main(int argc, char *argv[]) if (simOptions.sdPath.isEmpty()) simOptions.sdPath = g.profile[profileId].sdPath(); - if (cliOptions.count("profile") == 1) { - bool chk; - int pid = cliOptions.value("profile").toInt(&chk); - if (chk) - profileId = pid; - else - profileId = g.getActiveProfiles().key(cliOptions.value("profile").toString(), -1); + // Handle startup options - if (!g.getActiveProfiles().contains(profileId)) { - fprintf(stderr, "Error: Profile ID %d was not found.", profileId); - return finish(1); - } + // check for command-line options + CommandLineParseResult cliResult = cliOptions(&simOptions, &profileId); - simOptions = g.profile[profileId].simulatorOptions(); - cliOptsFound = true; - } + if (cliResult == CommandLineExitOk) + return finish(0); + if (cliResult == CommandLineExitErr) + return finish(1); - if (cliOptions.count("radio") == 1) { - simOptions.firmwareId = cliOptions.value("radio").toString(); - cliOptsFound = true; - } - - if (cliOptsFound || (simOptions.dataFile.isEmpty() && !simOptions.firmwareId.isEmpty())) - simOptions.dataFile = SimulatorStartupDialog::radioEepromFileName(simOptions.firmwareId, g.eepromDir()); - - if (!cliOptions.positional().isEmpty()) { - if (QString(cliOptions.positional().at(0)).contains(QRegExp(".*\\.[\\w]{2,6}$"))) { - simOptions.dataFile = cliOptions.positional()[0]; - simOptions.startupDataType = SimulatorOptions::START_WITH_FILE; - } - else { - simOptions.dataFolder = cliOptions.positional()[0]; - simOptions.startupDataType = SimulatorOptions::START_WITH_FOLDER; - } - cliOptsFound = true; - } - - if (!cliOptsFound || profileId == -1 || simOptions.firmwareId.isEmpty() || (simOptions.dataFile.isEmpty() && simOptions.dataFolder.isEmpty())) { + // Present GUI startup options dialog if necessary + if (cliResult == CommandLineNone || profileId == -1 || simOptions.firmwareId.isEmpty() || (simOptions.dataFile.isEmpty() && simOptions.dataFolder.isEmpty())) { SimulatorStartupDialog * dlg = new SimulatorStartupDialog(&simOptions, &profileId); int ret = dlg->exec(); delete dlg; @@ -192,32 +305,37 @@ int main(int argc, char *argv[]) return finish(0); } } - qDebug() << "profileId=" << profileId << simOptions; + qDebug() << "Starting with options: profileId=" << profileId << simOptions; + // Validate startup options + + QString resultMsg; if (profileId < 0 || simOptions.firmwareId.isEmpty() || (simOptions.dataFile.isEmpty() && simOptions.dataFolder.isEmpty())) { - resultMsg = QObject::tr("ERROR: Couldn't start simulator, missing radio/profile/data file/folder.\n Profile ID: [%1]; Radio ID: [%2];\nData File: [%3]"); + resultMsg = QApplication::translate("SimulatorMain", "ERROR: Couldn't start simulator, missing radio/profile/data file/folder.\n Profile ID: [%1]; Radio ID: [%2];\nData File: [%3]"); showMessage(resultMsg.arg(profileId).arg(simOptions.firmwareId, simOptions.dataFile), QMessageBox::Critical); return finish(1); } if (!g.getActiveProfiles().contains(profileId) || !SimulatorLoader::getAvailableSimulators().contains(simOptions.firmwareId)) { QTextStream stream(&resultMsg); - stream << QObject::tr("ERROR: Radio profile or simulator firmware not found.\nProfile ID: [%1]; Radio ID: [%2]") - .arg(profileId).arg(simOptions.firmwareId); - sharedHelpText(stream); + stream << QApplication::translate("SimulatorMain", "ERROR: Radio profile or simulator firmware not found.\nProfile ID: [%1]; Radio ID: [%2]").arg(profileId).arg(simOptions.firmwareId); + stream << sharedHelpText(); showMessage(resultMsg, QMessageBox::Critical); - return finish(2); + return finish(1); } - Firmware::setCurrentVariant(Firmware::getFirmwareForId(simOptions.firmwareId)); + // All checks passed, save profile ID and start simulator g.sessionId(profileId); g.simuLastProfId(profileId); + // Set global firmware environment + Firmware::setCurrentVariant(Firmware::getFirmwareForId(simOptions.firmwareId)); + int result = 0; SimulatorMainWindow * mainWindow = new SimulatorMainWindow(NULL, simOptions.firmwareId, SIMULATOR_FLAGS_STANDALONE); if ((result = mainWindow->getExitStatus(&resultMsg))) { if (resultMsg.isEmpty()) - resultMsg = QObject::tr("Uknown error during Simulator startup."); + resultMsg = QApplication::translate("SimulatorMain", "Uknown error during Simulator startup."); showMessage(resultMsg, QMessageBox::Critical); } else if (mainWindow->setOptions(simOptions, true)) { diff --git a/companion/src/thirdparty/qxtcommandoptions/AUTHORS b/companion/src/thirdparty/qxtcommandoptions/AUTHORS deleted file mode 100644 index 4490d1aa9..000000000 --- a/companion/src/thirdparty/qxtcommandoptions/AUTHORS +++ /dev/null @@ -1,7 +0,0 @@ -Arvid Picciani -Adam Higerd -J-P Nurmi -Benjamin Zeller -Thomas Mueller - -thanks for all the minor contributions, bug reports, beta tests, and the free beer :-) diff --git a/companion/src/thirdparty/qxtcommandoptions/CHANGES b/companion/src/thirdparty/qxtcommandoptions/CHANGES deleted file mode 100644 index a1cacd7e0..000000000 --- a/companion/src/thirdparty/qxtcommandoptions/CHANGES +++ /dev/null @@ -1,230 +0,0 @@ -LibQxt 0.6.2 contains improvements and bug fixes to the 0.6.x series. For more -details, see the documentation included in this package or online at -http://docs.libqxt.org. - -0.6.2 ------ - - * QxtWindowSystem: - - X11 implementation cleanup/overhaul - - Fixed #85 QxtWindowSystem::windowGeometry issue - * QxtSpanSlider: Improved span drawing on Mac - * QxtGlobalShortcut: - - Fixed #51 QxtGlobalShortcut doesn't send signal - - Fixed #131 QxtGlobalShortcutKey unregistered other's shortcut key by mistake - * QxtZeroconf: Fixed a bug in the custom AvahiPoll introduced by a timestamp wrap-around that accured just last week. - * QxtCrumbView: - - Don't render delegate for invalid indexes - - Remove unnecessary padding - * QxtDataStreamSignalSerializer: - - Handle incomplete length - - Added cast to eliminate a compiler warning - * QxtMailMessage: - - Fix some encoding issues, support explicit transfer encodings - - Handle lines with only one word - * QxtJSON: - - Add support for long long ints - - Handle control characters in QxtJSON::stringify - - Fix \u decoding - - Fixed a error in json parsing code. Nested arrays were incorrectly combined into one big array. - * Build system - - Various enhancements - - Fixed #130 DEPENTPATH = DEPENDPATH? - * QxtLogger: Fixed the incorrect association of log level string names to their enumerations - * QxtAbstractHttpConnector: remove request disconnected on (QHash)"requests" - * QxtWebContent: Fix comparison on size - * QxtLanguageBox: - - Fixed #124 QxtLanguageBox logic maybe bug - - Fixed #125 QxtLanguageBox improvment in logic - -0.6.1 ------ - -- Improvements - * Revised configure.bat: - - added -make-bin option - - removed -msvc from help - - added build_all config for -debug_and_release - - cleaned up possible mkdir/move output - * Added -I, -i and -L options to configure - * Revised QxtConfig.cmake, based on a proposal from zeke (thanks!) - * QxtGlobalShortcut/Mac: removed the extra route via QApplication::macEventFilter() - use qxt_mac_handle_hot_key() directly - * tests/other/app: changed the shortcut to "ctrl+alt+s" (ie. "cmd+alt+s" on mac) - * examples/jsonrpcclient: added CONFIG+=console to make windows users happy - * Configure: added -nomake docs - * Configure: added -no-openssl to -help - * Added MediaKeys to qxtglobalshortcut_win - * Added mod4 support in qxtglobalshortcut_x11 - * Added QXT_RPCSERVICE_DEBUG environment variable for convenient network debugging - * Improved QxtSlotMapper docs - * Fixed qmake deprecation warnings - -- Bug fixes - * #48 Won't build using Qt 4.4.3 b/c of QVariant::Hash - * #6 QxtFileLockTest::rw_same() does not pass on Windows - * Fixed QxtFileLock docs - * Fixed examples/jsonrpcclient: exit properly with no arguments set - * Fixed config.tests/db version check to respect MAJOR>4 - * #69 Documentation errors - * #46 Install on Mac - * #62 QxtXMLFileLoggerEngine vs QxtXmlFileLoggerEngine - * #60 including doens't work - * #63 QxtCheckComboBox display not correct - * Fixed qdoc3 tags in QxtZeroConf docs - * QxtSerialDevice: fixed r/w in open, disable ionotifier on error - * #77 QxtXmlRpcCall: default type not handled - * #78 Case of an empty string as return parameter without type specified - * #79 Missing element inside element in XML-RPC - * #65 QxtCountryComboBox - * #70 QxtConfigWidget display not correct - * QxtAbstractHttpConnector: don't add null devices to buffer list - * QxtZeroconf: Fixed the avahipoll so that the avahi mdns implementation work - -0.6.0 ------ -- General - * Revised the build system - * Revised docs (now based on qdoc3) - * QxtConfig.cmake - -- Bug fixes - * #4 QxtDaemon::daemonize() compilation warning - * #24 QxtFlowView::currentIndex() - * #29 qxtwecore - * #33 Problem in QxtMailMessage - * #34 Debug PDB files - * #36 QxtCommandoptions on Windows wrong option parsing - * #41 Compilation issue on Mac - -- QxtCore - * Added QxtModelSerializer - * Removed obsolete QxtSemaphore - * Added QxtJSON - -- QxtGui - * Added rich text support to QxtItemDelegate - * Removed obsolete QxtTabWidget::TabMovementMode & QxtTabBar - * Removed obsolete QxtDockWidget - * Revised QxtConfigDialog & QxtConfigWidget - * Enhanced QxtWindowSystem::idleTime() to resolve libXss at run-time - * Added QxtCrumbView::crumbDelegate() - * Added QxtFilterDialog and QxtLookupLineEdit - -- QxtNetwork - * Added QxtXmlRpc - * Added QxtMainAttachment::fromFile() - * Revised QxtSmtp - * Added QxtJSONRpcClient and QxtJSONRpcCall - -- Added QxtZeroConf module - -0.5.2 ------ - -- Bug fixes - * QxtSerialDevice: update QIODevice status when device is closed - * QxtSerialDevice: destroy QSocketNotifier when device is closed - * Modified QxtGlobalShortcut to use XSetErrorHandler() to catch X(Un)GrabKey() errors on X11 - -0.5.1 ------ - -- Bug fixes - * #3 [Vista/Qt 4.5.0] - static build issue - * #9 QxtCheckComboBox display is inconsistent - * #10 qxtwindowsystem_win.cpp(105) : error C2065: 'LASTINPUTINFO': undeclared identifier - * #16 Static lib linkage problem in Qt Creator - * #17 QxtPushButton::minimumSizeHint returns wrong value - * Fixed QxtGlobalShortcut to allow NumLock on X11 - * Fixed compilation problems with the GCC-4.4.X series - * Fixed QxtGlobalShortcut::shortcut() - -0.5.0 ------ - -- General - * Added LGPL license option - * Run Krazy checks and fixed found issues - * Improved configure.bat - * Added missing export macros - * Added missing convenience headers - * Improved compatibility - - QT_FORWARD_DECLARE_CLASS - - Q_SLOTS, Q_SIGNALS & Q_FOREACH in headers - - interface - -- QxtCore - * Revised QxtFifo - * Added QxtAlgorithms - * Added QxtSerialDevice - * Added QxtSlotMapper - -- QxtCrypto - * Revised QxtBlowfish - -- QxtGui - * Added QxtWindowSystem::idleTime() - * Added QxtCrumbView - * Improved QxtScheduleView - * Added QxtSortFilterProxyModel - * Improved QxtSpanSlider - - Added QxtSpanSlider::HandleMovementMode - * Improved QxtItemDelegate - - Added ProgressMinimumRole & ProgressMaximumRole - - Added support for busy indicator mode - * Improved QxtLetterBoxWidget - - Added QxtLetterBoxWidget::margin - - Added QxtLetterBoxWidget::resizeWidget - -- QxtWeb - * Added QxtWebCgiService - -0.4.0 ------ - -- QxtCore - * Added QxtDeplex - * Added QxtLocale - * Added QxtPointerList - * Added QxtMultiSignalWaiter - * Added QxtSignalGroup - * Added QxtCommandOptions - * Added QxtLogger - * Added QxtAbstractConnectionManager - * Added QxtDataStreamSignalSerializer - * Added QxtAbstractSignalSerializer - -- QxtCrypto - * Added QxtHmac - -- QxtGui - * Added QxtItemEditorCreatorBase - * Added QxtStandardItemEditorCreator - * Added QxtItemEditorCreator - * Added QxtBaseSpinBox - * Added QxtCountryComboBox - * Added QxtCountryModel - * Added QxtLanguageComboBox - * Added QxtScheduleView - * Added QxtTabBar - * Added QxtFlowView - * Added QxtLetterBoxWidget - * Improved QxtTabWidget - - Added QxtTabWidget::alwaysShowTabBar - - Added QxtTabWidget::tabAnimation - - Added QxtTabWidget::tabMovementMode - * Improved QxtConfirmationMessage - - Added QxtConfirmationMessage::settingsFormat - - Added QxtConfirmationMessage::rememberOnReject - - Added QxtConfirmationMessage::overrideSettingsApplication - - Added QxtConfirmationMessage::overrideSettingsKey - - Added QxtConfirmationMessage::overrideSettingsOrganization - -- QxtBerkeley - * Added QxtBdbTree - -- QxtWeb - * Revised the whole module - -- QxtNetwork - * Added QxtTcpConnectionManager diff --git a/companion/src/thirdparty/qxtcommandoptions/CMakeLists.txt b/companion/src/thirdparty/qxtcommandoptions/CMakeLists.txt deleted file mode 100644 index 80074c141..000000000 --- a/companion/src/thirdparty/qxtcommandoptions/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -set(qxtcommandoptions_SRCS - qxtcommandoptions.cpp -) - -qt5_wrap_cpp(qxtcommandoptions_SRCS) - -add_library(qxtcommandoptions ${qxtcommandoptions_SRCS}) -qt5_use_modules(qxtcommandoptions Widgets) - diff --git a/companion/src/thirdparty/qxtcommandoptions/LICENSE b/companion/src/thirdparty/qxtcommandoptions/LICENSE deleted file mode 100644 index 91a9970ff..000000000 --- a/companion/src/thirdparty/qxtcommandoptions/LICENSE +++ /dev/null @@ -1,89 +0,0 @@ -Qt Extension Library -Copyright (C) 2007 Qxt Foundation - -------------------- Disclaimer ------------------------------------------------ - -Until the Qxt Foundation is legally established, copyright for the -source code falls back to the original contributor. For information about the -status of the Qxt Foundation, or about the copyright status of any part of Qxt, -contact the Qxt project maintainers at - -Once the Qxt Foundation has been legally established, all contributors must -transfer all copyright interest to the Qxt Foundation before their submissions -will be added to the project. - -------------------- License --------------------------------------------------- - -This library is free software; you can redistribute it and/or modify it -under the terms of the Common Public License, version 1.0, as published by IBM -or under the terms of the GNU Lesser General Public License, version 2.1, -as published by the Free Software Foundation - -This file is provided "AS IS", without WARRANTIES OR CONDITIONS OF ANY -KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT LIMITATION, ANY -WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, MERCHANTABILITY OR -FITNESS FOR A PARTICULAR PURPOSE. - -You should have received a copy of the CPL along with this file. -See the LICENSE file and the cpl1.0.txt file included with the source -distribution for more information. If you did not receive a copy of the -license, contact the Qxt Foundation. - -You should have received a copy of the LGPL along with this file. -See the LICENSE file and the lgpl-2.1.txt file included with the source -distribution for more information. If you did not receive a copy of the -license, contact the Qxt Foundation. - -Parts of Qxt depend on Qt 4 and/or other libraries that have their own -licenses. Qxt is independent of these licenses; however, use of these other -libraries is subject to their respective license agreements. - -------------------- Intent ---------------------------------------------------- - -The following section describes the opinions and intent of the Qxt Foundation -with regards to the licensing and use of the Qxt source code and library. In -the event that the CPL is found to be illegal or invalid, or if any application -or clause of the license is subjected to question or abuse, this section is a -general statement of the desired interpretation. - -This section has no legal standing and the statements made here are strictly -subject to the text of the CPL; that is, if this section and the CPL are in -disagreement, the text of the CPL takes precedence. In no way does this -intent grant you any additional rights or impose any additional restrictions. - -If you have questions about licensing, contact the maintainers. - -Qxt is built and supported by open-source enthusiasts. -- Please respect the open-source background of the contributors. The code is - provided for everyone's use; you may not restrict the rights of anyone to - use it. - - No individual may claim ownership of any part of the code. It belongs - to the community. - - You may modify the source code to suit your needs, but these changes - must be made free. If you distribute a modified form of Qxt, you must - also distribute the entire source code of the modified form. - - Digital Rights Management (DRM) puts unfair, unfree restrictions on - users and developers. It is the opposite of Free Software. We can't - stop you from using it, but please don't use the Qxt name for software - restricted by DRM. -- Please respect the time and effort put into the project by the developers. - - If you find Qxt useful, it would be appreciated if you would include - text in your application (for instance, in the About dialog) giving - acknowledgement to Qxt. - - If you make modifications to the source code, you must not call the - modified version "Qxt." It's okay to include "Qxt" in the name, but - anyone who receives the modified version needs to know that it's not - the same as the version distributed by the Qxt Foundation. -- We want everyone to be able to use Qxt without restrictions. - - If you distribute Qxt in compiled binary form, please ensure that - everyone who receives it can get the source code used to create it. - - You are free to use Qxt in closed-source applications as long as you - distribute Qxt in an open-source fashion. This does not require you - to make your entire application open-source. -- The Qxt Foundation is a non-profit, non-political organization. - - Please don't use the Qxt name in any political or semi-political - propaganda or publication. We don't like it. -- Qxt is distributed "as-is," with no warranty. - - If it makes your program crash, your computer blow up, or tiny demons - fly out of your nose, please don't sue us. - diff --git a/companion/src/thirdparty/qxtcommandoptions/cpl1.0.txt b/companion/src/thirdparty/qxtcommandoptions/cpl1.0.txt deleted file mode 100644 index c448ea00a..000000000 --- a/companion/src/thirdparty/qxtcommandoptions/cpl1.0.txt +++ /dev/null @@ -1,213 +0,0 @@ - - -THE ACCOMPANYING PROGRAM IS PROVIDED UNDER THE TERMS OF THIS COMMON PUBLIC -LICENSE ("AGREEMENT"). ANY USE, REPRODUCTION OR DISTRIBUTION OF THE PROGRAM -CONSTITUTES RECIPIENT'S ACCEPTANCE OF THIS AGREEMENT. - -1. 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Here is a sample; alter the names: - - Yoyodyne, Inc., hereby disclaims all copyright interest in the - library `Frob' (a library for tweaking knobs) written by James Random Hacker. - - , 1 April 1990 - Ty Coon, President of Vice - -That's all there is to it! - - diff --git a/companion/src/thirdparty/qxtcommandoptions/qxtcommandoptions.cpp b/companion/src/thirdparty/qxtcommandoptions/qxtcommandoptions.cpp deleted file mode 100644 index f1b6fde20..000000000 --- a/companion/src/thirdparty/qxtcommandoptions/qxtcommandoptions.cpp +++ /dev/null @@ -1,914 +0,0 @@ -/**************************************************************************** - ** - ** Copyright (C) Qxt Foundation. Some rights reserved. - ** - ** This file is part of the QxtCore module of the Qxt library. - ** - ** This library is free software; you can redistribute it and/or modify it - ** under the terms of the Common Public License, version 1.0, as published - ** by IBM, and/or under the terms of the GNU Lesser General Public License, - ** version 2.1, as published by the Free Software Foundation. - ** - ** This file is provided "AS IS", without WARRANTIES OR CONDITIONS OF ANY - ** KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT LIMITATION, ANY - ** WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, MERCHANTABILITY OR - ** FITNESS FOR A PARTICULAR PURPOSE. - ** - ** You should have received a copy of the CPL and the LGPL along with this - ** file. See the LICENSE file and the cpl1.0.txt/lgpl-2.1.txt files - ** included with the source distribution for more information. - ** If you did not receive a copy of the licenses, contact the Qxt Foundation. - ** - ** - ** - ****************************************************************************/ - -#include "qxtcommandoptions.h" - -#include -#include -#include -#include - -/*! -\class QxtCommandOptions - -\inmodule QxtCore - -\brief The QxtCommandOptions class is a Parser for command-line options - -This class is used by applications that need to accept command-line arguments. It can -also automatically generate help text, which keeps it from accidentally falling out of -sync with the supported options, and it can produce warnings for common errors. - -It accepts Windows-style ("/option"), UNIX-style ("-option"), and GNU-style -("--option") options. By default, QxtCommandOptions uses Windows-style options -(QxtCommandOptions::Slash) on Windows and GNU-style options (QxtCommandOptions::DoubleDash) -on UNIX and Mac. When using GNU-style options, single-character option names only -require a single leading dash and can be grouped together, for example, "-abc". - -Any parameter that does not start with the option prefix is considered a positional -parameter. Most applications treat positional parameters as filenames. When using -GNU- or UNIX-style options, use a double dash ("--") alone to force the remaining -parameters to be interpreted as positional parameters. - -To use QxtCommandOptions, first add the supported options using the add() and alias() -methods, then process the command line using the parse() method, and finally retrieve -the processed options using the positional(), count(), value() and/or parameters() -methods. - -Mutually-exclusive options can be specified by using the \a group parameter to add(). -Only one option in a group will be accepted on the command line; if multiple options -are provided, only the last one takes effect. - -Some options may accept an optional or required parameter. Depending on the value -of the paramStyle() property, the parameter may be separated from the option by -an equals sign ("/option=value") or by a space ("-option value"). By default, -Windows uses an equals sign and UNIX and Mac accept both an equals sign and a -space. Optional parameters always require an equals sign. Note that, when using -GNU-style options, single-character options cannot have optional parameters. - -A simple archiving application might use code similar to this: -\code -QxtCommandOptions options; -options.add("compress", "create a new archive"); -options.alias("compress", "c"); -options.add("extract", "extract files from an archive"); -options.alias("extract", "x"); -options.add("level", "set the compression level (0-9)", QxtCommandOptions::Required); -options.alias("level", "l"); -options.add("verbose", "show more information about the process; specify twice for more detail", QxtCommandOptions::AllowMultiple); -options.alias("verbose", "v"); -options.add("help", "show this help text"); -options.alias("help", "h"); -options.parse(QCoreApplication::arguments()); -if(options.count("help") || options.showUnrecognizedWarning()) { - options.showUsage(); - return -1; -} -bool verbose = options.count("verbose"); -int level = 5; -if(options.count("level")) { - level = options.value("level").toInt(); -} -\endcode - -\sa QCoreApplication::arguments() -*/ - -static const char* qxt_qt_options[] = -{ - "=style", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the application GUI style"), - "=stylesheet", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the application stylesheet"), - "=session", QT_TRANSLATE_NOOP("QxtCommandOptions", "restores the application from an earlier session"), - "widgetcount", QT_TRANSLATE_NOOP("QxtCommandOptions", "displays debugging information about widgets"), - "reverse", QT_TRANSLATE_NOOP("QxtCommandOptions", "use right-to-left layout"), -#ifdef QT_DEBUG - "nograb", QT_TRANSLATE_NOOP("QxtCommandOptions", "never grab the mouse or keyboard"), -#endif -#if defined(QT_DEBUG) && defined(Q_WS_X11) - "dograb", QT_TRANSLATE_NOOP("QxtCommandOptions", "grab the mouse/keyboard even in a debugger"), - "sync", QT_TRANSLATE_NOOP("QxtCommandOptions", "run in synchronous mode for debugging"), -#endif -#ifdef Q_WS_WIN - "direct3d", QT_TRANSLATE_NOOP("QxtCommandOptions", "use Direct3D by default"), -#endif -#ifdef Q_WS_X11 - "=display", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the X11 display"), - "=geometry", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the geometry of the first window"), - "=font", "", - "=fn", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the default font"), - "=background", "", - "=bg", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the default background color"), - "=foreground", "", - "=fg", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the default foreground color"), - "=button", "", - "=btn", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the default button color"), - "=name", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the application name"), - "=title", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the application title"), - "=visual", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the X11 visual type"), - "=ncols", QT_TRANSLATE_NOOP("QxtCommandOptions", "limit the number of colors on an 8-bit display"), - "cmap", QT_TRANSLATE_NOOP("QxtCommandOptions", "use a private color map"), - "=im", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the input method server"), - "noxim", QT_TRANSLATE_NOOP("QxtCommandOptions", "disable the X Input Method"), - "=inputstyle", QT_TRANSLATE_NOOP("QxtCommandOptions", "sets the style used by the input method"), -#endif - 0, 0 -}; - -/* - * This function is used to check to see if a parameter - * is used by Qt. - */ -static int isQtOption(const QString& param) -{ - // Qt options all start with a single dash regardless of platform - if (param.length() < 2) return 0; - if (param[0] != '-') return 0; - if (param[1] == '-') return 0; -#ifdef Q_OS_MAC - if (param.left(5) == "-psn_") return 1; -#endif - QString name = param.mid(1), value; - // bool hasEquals; - - // Separate the option and the value, if present - if (name.indexOf('=') != -1) - { - value = param.section('=', 1); - name = param.section('=', 0, 0); - // hasEquals = true; - } - else - { - value = ""; - // hasEquals = false; - } - - const char* option; - bool optionHasValue; - for (int i = 0; qxt_qt_options[i]; i += 2) - { - option = qxt_qt_options[i]; - // In the table above, options that require parameters start with = - if (option[0] == '=') - { - optionHasValue = true; - option = option + 1; // pointer math to skip = - } - else - { - optionHasValue = false; - } - - // The return value indicates how many parameters to skip - if (name == option) - { - if (optionHasValue) return 2; - return 1; - } - } - - return 0; -} - -// Storage structure for option data -struct QxtCommandOption -{ - QStringList names; // aliases accepted at the command line - QString canonicalName; // name used for alias()/count()/value() - QString desc; // documentation string - QStringList values; // values passed on command line - QxtCommandOptions::ParamTypes paramType; // flags - quint16 group; // mutual exclusion group -}; - -class QxtCommandOptionsPrivate : public QxtPrivate -{ - Q_DECLARE_TR_FUNCTIONS(QxtCommandOptions) -public: - QXT_DECLARE_PUBLIC(QxtCommandOptions) - - QList options; - QHash lookup; // cache structure to simplify processing - QHash > groups; // cache structure to simplify processing - QxtCommandOptions::FlagStyle flagStyle; - QxtCommandOptions::ParamStyle paramStyle; - QStringList positional; // prefixless parameters - QStringList unrecognized; // prefixed parameters not in recognized options - QStringList missingParams; // parameters with required values missing - int screenWidth; - bool parsed; - - QxtCommandOption* findOption(const QString& name); - const QxtCommandOption* findOption(const QString& name) const; - void setOption(QxtCommandOption* option, const QString& value = QString()); - void parse(const QStringList& params); -}; - -/* Looks up an option in qxt_d().options by canonical name */ -QxtCommandOption* QxtCommandOptionsPrivate::findOption(const QString& name) -{ - // The backwards loop will find what we're looking for more quickly in the - // typical use case, where you add aliases immediately after adding the option. - for (int i = options.count() - 1; i >= 0; --i) - { - if (options[i].canonicalName == name) return &options[i]; - } - qWarning() << qPrintable(QString("QxtCommandOptions: ") + tr("option \"%1\" not found").arg(name)); - return 0; -} - -/* Looks up an option in qxt_d().options by canonical name - * This is a const overload for const functions */ -const QxtCommandOption* QxtCommandOptionsPrivate::findOption(const QString& name) const -{ - // The backwards loop will find what we're looking for more quickly in the - // typical use case, where you add aliases immediately after adding the option. - for (int i = options.count() - 1; i >= 0; --i) - { - if (options[i].canonicalName == name) return &(options.at(i)); - } - qWarning() << qPrintable(QString("QxtCommandOptions: ") + tr("option \"%1\" not found").arg(name)); - return 0; -} - -/*! - * Constructs a QxtCommandOptions object. - */ -QxtCommandOptions::QxtCommandOptions() -{ - QXT_INIT_PRIVATE(QxtCommandOptions); - qxt_d().screenWidth = 80; - qxt_d().parsed = false; -#ifdef Q_OS_WIN - setFlagStyle(Slash); - setParamStyle(Equals); -#else - setFlagStyle(DoubleDash); - setParamStyle(SpaceAndEquals); -#endif -} - -/*! - * Sets which prefix is used to identify options. The default value is Slash on Windows - * and DoubleDash on all other platforms. - * - * Note that Qt's built-in options (see QApplication) always use a single dash, - * regardless of this setting. - */ -void QxtCommandOptions::setFlagStyle(FlagStyle style) -{ - qxt_d().flagStyle = style; -} - -/*! - * Gets which prefix is used to identify options. - */ -QxtCommandOptions::FlagStyle QxtCommandOptions::flagStyle() const -{ - return qxt_d().flagStyle; -} - -/*! - * Sets which value separator is used for options that accept parameters. - * The default value is Equals on Windows and SpaceAndEquals on all other - * platforms. - * - * Single-letter options with optional parameters in DoubleDash mode - * always use an equals sign, regardless of this setting. - * - * Qt's built-in options always behave as SpaceAndEquals, regardless of - * this setting. - */ -void QxtCommandOptions::setParamStyle(ParamStyle style) -{ - qxt_d().paramStyle = style; -} - -/*! - * Sets which value separator is used for options that accept parameters. - */ -QxtCommandOptions::ParamStyle QxtCommandOptions::paramStyle() const -{ - return qxt_d().paramStyle; -} - -/*! - * Sets the width of the screen, in characters. This is used for word-wrapping - * the automatically-generated help text to the size of the screen. The default - * value is 80 characters. Pass 0 to disable word-wrapping. - */ -void QxtCommandOptions::setScreenWidth(quint16 width) -{ - qxt_d().screenWidth = width; -} - -/*! - * Gets the width of the screen, in characters. - */ -quint16 QxtCommandOptions::screenWidth() const -{ - return qxt_d().screenWidth; -} - -/*! - * Adds a section separator. Section separators are only used in generating - * help text, and can be used to visually separate related groups of - * options. - */ -void QxtCommandOptions::addSection(const QString& name) -{ - QxtCommandOption option; - option.canonicalName.clear(); - option.desc = name; - qxt_d().options.append(option); -} - -/*! - * Adds an option to the parser. - * - * The name parameter defines the name that will be used by the alias(), - * count(), value(), and parameters() methods. Additional names for the - * same option can be defined using the alias() method. - * - * The group parameter, if used, defines a set of mutually-exclusive options. - * If more than one option in the same group is passed on the command line, - * only the last one takes effect. - */ -void QxtCommandOptions::add(const QString& name, const QString& desc, ParamTypes paramType, int group) -{ - QxtCommandOption option; - option.canonicalName = name; - option.desc = desc; - option.paramType = paramType; - option.group = group; - qxt_d().options.append(option); - if (group != -1) - qxt_d().groups[group].append(&(qxt_d().options.last())); - // Connect the canonical name to a usable name - alias(name, name); -} - -/*! - * Provides an alias for an option. An alias is another name for the option that can be - * given on the command line. Aliases cannot be used as parameters to alias(), count() - * or value() nor can single-letter aliases be created for options with an optional value. - * - * The from parameter must be a name has previously been added with the add() method. - */ -void QxtCommandOptions::alias(const QString& from, const QString& to) -{ - QxtCommandOption* option = qxt_d().findOption(from); - if (!option) return; // findOption outputs the warning - option->names.append(to); - qxt_d().lookup[to] = option; - if (option->paramType & ValueOptional && qxt_d().flagStyle == DoubleDash && to.length() == 1) - qWarning() << qPrintable(QString("QxtCommandOptions: ") + tr("Short options cannot have optional parameters")); -} - -/*! - * Returns the positional parameters from the command line, that is, the arguments that - * do not begin with the option prefix. - * - * \sa flagStyle() - */ -QStringList QxtCommandOptions::positional() const -{ - if (!qxt_d().parsed) - qWarning() << qPrintable(QString("QxtCommandOptions: ") + tr("positional() called before parse()")); - return qxt_d().positional; -} - -/*! - * Returns the options that could not be parsed. - * - * An argument is unrecognized if it begins with the option prefix but was never - * defined using the add() or alias() methods, or if it requires a value but the - * user did not provide one. - */ -QStringList QxtCommandOptions::unrecognized() const -{ - if (!qxt_d().parsed) - qWarning() << qPrintable(QString("QxtCommandOptions: ") + tr("unrecognized() called before parse()")); - return qxt_d().unrecognized + qxt_d().missingParams; -} - -/*! - * Returns the number of times an option was passed on the command line. - * - * This function will only return 0 or 1 for options that were not created with the - * QxtCommandOptions::AllowMultiple flag set. - */ -int QxtCommandOptions::count(const QString& name) const -{ - if (!qxt_d().parsed) - qWarning() << qPrintable(QString("QxtCommandOptions: ") + tr("count() called before parse()")); - const QxtCommandOption* option = qxt_d().findOption(name); - if (!option) return 0; // findOption outputs the warning - return option->values.count(); -} - -/*! - * Returns the value or values for an option passed on the command line. - * - * If the option was not passed on the command line, this function returns a null QVariant. - * If the option was created with the QxtCommandOptions::AllowMultiple flag, and the option - * was passed more than once, this function returns a QStringList containing the values. - * Otherwise, this function returns the last (or only) value given to the option on the - * command line. When an option allowing an optional value is provided on the command - * line and for which no value is provided, an empty but non-null QString will be returned - * in the QVariant. - */ -QVariant QxtCommandOptions::value(const QString& name) const -{ - if (!qxt_d().parsed) - qWarning() << qPrintable(QString("QxtCommandOptions: ") + tr("value() called before parse()")); - const QxtCommandOption* option = qxt_d().findOption(name); - if (!option) return QVariant(); // findOption outputs the warning - int ct = option->values.count(); - if (ct == 0) return QVariant(); - if (ct == 1) return option->values.first(); - return option->values; -} - -/*! - * Returns all of the recognized options passed on the command line. - */ -QMultiHash QxtCommandOptions::parameters() const -{ - if (!qxt_d().parsed) - qWarning() << qPrintable(QString("QxtCommandOptions: ") + tr("parameters() called before parse()")); - QMultiHash params; - int ct; - foreach(const QxtCommandOption& option, qxt_d().options) - { - ct = option.values.count(); - if (!ct) - { - continue; - } - else if (!(option.paramType & (ValueOptional | ValueRequired))) - { - // Valueless options are really a true/false flag - params.insert(option.canonicalName, true); - } - else - { - foreach(const QVariant& value, option.values) - params.insert(option.canonicalName, value); - } - } - return params; -} - -/*! - * This is an overloaded member function, provided for convenience. - * - * Process a set of command-line options. This overload accepts a number of - * arguments and a pointer to the list of arguments. - * - * Note that parse() may be invoked multiple times to handle arguments from - * more than one source. - */ -void QxtCommandOptions::parse(int argc, char** argv) -{ - QStringList args; - for (int i = 0; i < argc; i++) - args << argv[i]; - parse(args); -} - -/*! - * Process a set of command-line options. This overload accepts a QStringList - * containing the command-line options, such as the one returned by - * QCoreApplication::arguments(). - * - * Note that parse() may be invoked multiple times to handle arguments from - * more than one source. - * - * \sa QCoreApplication::arguments() - */ -void QxtCommandOptions::parse(QStringList params) -{ - qxt_d().parse(params); - qxt_d().parsed = true; -} - -/* Update the internal data structures with an option from the command line. */ -void QxtCommandOptionsPrivate::setOption(QxtCommandOption* option, const QString& value) -{ - if (groups.contains(option->group)) - { - // Clear mutually-exclusive options - QList& others = groups[option->group]; - foreach(QxtCommandOption* other, others) - { - if (other != option) other->values.clear(); - } - } - // Clear all previous values if multiples are not accepted - if (!(option->paramType & QxtCommandOptions::AllowMultiple)) - option->values.clear(); - option->values.append(value); -} - -/* Do the work of parsing the command line */ -void QxtCommandOptionsPrivate::parse(const QStringList& params) -{ - int pos = 1; // 0 is the application name - int ct = params.count(); - int skip = 0; - bool endFlags = false; - bool /*notUnrecognized, */hasEquals; - QString name, param, value; - - while (pos < ct) - { - // Ignore Qt built-in options - while ((skip = isQtOption(params[pos]))) - { - pos += skip; - if (pos >= ct) - return; - } - - param = params[pos]; - pos++; - - if (!endFlags && ((flagStyle == QxtCommandOptions::Slash && param[0] == '/') || - (flagStyle != QxtCommandOptions::Slash && param[0] == '-'))) - { - // tagged argument - if (param.length() == 1) - { - // "-" or "/" alone can't possibly match a flag, so use positional. - positional.append(param); - continue; - } - // notUnrecognized = false; - - if (flagStyle != QxtCommandOptions::Slash && param == "--") - { - // End of parameters flag - endFlags = true; - } - else if (flagStyle == QxtCommandOptions::DoubleDash && param[1] != '-') - { - // Handle short-form options - int len = param.length(); - QxtCommandOption* option; - for (int i = 1; i < len; i++) - { - QString ch(param[i]); - if (ch == "-") - { - endFlags = true; - } - else - { - option = lookup.value(ch, 0); - if (!option) - { - // single-letter flag has no known equivalent - unrecognized.append(QString("-") + param[i]); - } - else - { - if (option->paramType & QxtCommandOptions::ValueRequired) - { - // Check for required parameters - // Short options can't have optional parameters - if (pos >= params.count()) - { - missingParams.append(param); - break; - } - value = params[pos]; - } - else - { - value = ""; - } - setOption(option, value); - } - } - } - } - else - { - // Break apart a value - if (param.indexOf('=') != -1) - { - value = param.section('=', 1); - param = param.section('=', 0, 0); - hasEquals = true; - } - else - { - value = ""; - hasEquals = false; - } - - if (flagStyle == QxtCommandOptions::DoubleDash) - name = param.mid(2); - else - name = param.mid(1); - - QxtCommandOption* option = lookup.value(name, 0); - if (!option) - { - unrecognized.append(param); - } - else - { - if (option->paramType & QxtCommandOptions::ValueRequired && !hasEquals) - { - // Check for parameters - if (pos >= params.count()) - { - missingParams.append(param); - break; - } - value = params[pos]; - pos++; - } - else if ((paramStyle & QxtCommandOptions::Space) - && (option->paramType & QxtCommandOptions::ValueOptional) - && !hasEquals) - { - if (pos < params.count()) - { - if (!((flagStyle == QxtCommandOptions::Slash && params.at(pos)[0] == '/') || - (flagStyle != QxtCommandOptions::Slash && params.at(pos)[0] == '-'))) - { - value = params[pos]; - pos++; - } - } - } - - setOption(option, value); - } - } - } - else - { - // positional argument - positional.append(param); - } - } -} - -/*! - * This is an overloaded member function, provided for convenience. - * - * Outputs a warning about any unrecognized options to the provided device, or - * standard error by default. The device must already be opened for writing. - * - * This function returns true if any warnings were output, or false otherwise. - * - * If a QCoreApplication or a subclass of QCoreApplication has been instantiated, - * this function uses QCoreApplication::applicationFilePath() to get the name - * of the executable to include in the message. - * - * \sa QCoreApplication::applicationFilePath() - */ -bool QxtCommandOptions::showUnrecognizedWarning(QIODevice* device) const -{ - if (!device) - { - QTextStream stream(stderr); - return showUnrecognizedWarning(*&stream); - } - else - { - QTextStream stream(device); - return showUnrecognizedWarning(*&stream); - } -} - -/*! - * Returns the automatically-generated warning text about any unrecognized options. - * - * If a QCoreApplication or a subclass of QCoreApplication has been instantiated, - * this function uses QCoreApplication::applicationFilePath() to get the name - * of the executable to include in the message. - * - * \sa QCoreApplication::applicationFilePath() - */ -QString QxtCommandOptions::getUnrecognizedWarning() const -{ - QString usage; - QTextStream stream(&usage); - showUnrecognizedWarning(*&stream); - return usage; -} - -/*! - * This is an overloaded member function, provided for convenience. - * - * Outputs a warning about any unrecognized options to the provided stream. - * - * This function returns true if any warnings were output, or false otherwise. - * - * If a QCoreApplication or a subclass of QCoreApplication has been instantiated, - * this function uses QCoreApplication::applicationFilePath() to get the name - * of the executable to include in the message. - * - * \sa QCoreApplication::applicationFilePath() - */ -bool QxtCommandOptions::showUnrecognizedWarning(QTextStream& stream) const -{ - if (!qxt_d().unrecognized.count() && !qxt_d().missingParams.count()) return false; - - QString name; - if (QCoreApplication::instance()) - name = QDir(QCoreApplication::applicationFilePath()).dirName(); - if (name.isEmpty()) - name = "QxtCommandOptions"; - - if (qxt_d().unrecognized.count()) - stream << name << ": " << tr("unrecognized parameters: ") << qxt_d().unrecognized.join(" ") << endl; - - foreach(const QString& param, qxt_d().missingParams) - stream << name << ": " << tr("%1 requires a parameter").arg(param) << endl; - - return true; -} - -/*! - * This is an overloaded member function, provided for convenience. - * - * Outputs automatically-generated usage text for the accepted options to the provided - * device, or standard error by default. The device must already be opened for writing. - * - * Pass true to showQtOptions to output usage text for the options recognized by - * QApplication. - * - * \sa QApplication - */ -void QxtCommandOptions::showUsage(bool showQtOptions, QIODevice* device) const -{ - if (!device) - { - QTextStream stream(stdout); - showUsage(showQtOptions, *&stream); - } - else - { - QTextStream stream(device); - showUsage(showQtOptions, *&stream); - } -} - -/*! - * Returns the automatically-generated usage text for the accepted options. - */ -QString QxtCommandOptions::getUsage(bool showQtOptions) const -{ - QString usage; - QTextStream stream(&usage); - showUsage(showQtOptions, *&stream); - return usage; -} - -/*! - * This is an overloaded member function, provided for convenience. - * - * Outputs automatically-generated usage text for the accepted options to the provided - * stream. - * - * Pass true to showQtOptions to output usage text for the options recognized by - * QApplication. - * - * \sa QApplication - */ -void QxtCommandOptions::showUsage(bool showQtOptions, QTextStream& stream) const -{ - QStringList names; - QStringList descs; - int maxNameLength = 0; - QString name; - - foreach(const QxtCommandOption& option, qxt_d().options) - { - // Don't generate usage for undocumented parameters - if (option.paramType & Undocumented) continue; - - foreach(const QString& n, option.names) - { - if (name.length()) name += ", "; - if (qxt_d().flagStyle == Slash) - name += '/'; - else if (qxt_d().flagStyle == DoubleDash && n.length() > 1) - name += "--"; - else - name += '-'; - name += n; - if (option.paramType & (ValueOptional | ValueRequired)) - { - if (option.paramType & ValueOptional) - name += "[=x]"; - else if (qxt_d().paramStyle == SpaceAndEquals) - name += "[=]x"; - else if (qxt_d().paramStyle == Equals) - name += "=x"; - else - name += " x"; - } - } - - // The maximum name length is used for formatting the output columns - if (name.length() > maxNameLength) - maxNameLength = name.length(); - names.append(name); - descs.append(option.desc); - name = ""; - } - - if (showQtOptions) - { - // Add a section header - names.append(QString()); - descs.append("Common Qt Options"); - - // Parse through qxt_qt_options - const char* option; - bool optionHasValue; - for (int i = 0; qxt_qt_options[i]; i += 2) - { - option = qxt_qt_options[i]; - - if (option[0] == '=') - { - // The option takes a parameter - optionHasValue = true; - option = option + 1; // pointer math to skip the = - } - else - { - optionHasValue = false; - } - - // Concatenate on the option alias - if (!name.isEmpty()) name += ", "; - name += '-'; - name += option; - if (optionHasValue) name += "[=]x"; - - if (qxt_qt_options[i+1][0] != 0) - { - // The last alias for the option has the description - if (name.length() > maxNameLength) - maxNameLength = name.length(); - names.append(name); - descs.append(qxt_qt_options[i+1]); - name = ""; - } - } - } - - int ct = names.count(); - QString line, wrap(maxNameLength + 3, ' '); - for (int i = 0; i < ct; i++) - { - if (names[i].isEmpty()) - { - // Section headers have no name entry - stream << endl << descs[i] << ":" << endl; - continue; - } - line = ' ' + names[i] + QString(maxNameLength - names[i].length() + 2, ' '); - foreach(const QString& word, descs[i].split(' ', QString::SkipEmptyParts)) - { - if (qxt_d().screenWidth > 0 && line.length() + word.length() >= qxt_d().screenWidth) - { - stream << line << endl; - line = wrap; - } - line += word + ' '; - } - stream << line << endl; - } -} diff --git a/companion/src/thirdparty/qxtcommandoptions/qxtcommandoptions.h b/companion/src/thirdparty/qxtcommandoptions/qxtcommandoptions.h deleted file mode 100644 index e302d90f1..000000000 --- a/companion/src/thirdparty/qxtcommandoptions/qxtcommandoptions.h +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** - ** - ** Copyright (C) Qxt Foundation. Some rights reserved. - ** - ** This file is part of the QxtCore module of the Qxt library. - ** - ** This library is free software; you can redistribute it and/or modify it - ** under the terms of the Common Public License, version 1.0, as published - ** by IBM, and/or under the terms of the GNU Lesser General Public License, - ** version 2.1, as published by the Free Software Foundation. - ** - ** This file is provided "AS IS", without WARRANTIES OR CONDITIONS OF ANY - ** KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT LIMITATION, ANY - ** WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, MERCHANTABILITY OR - ** FITNESS FOR A PARTICULAR PURPOSE. - ** - ** You should have received a copy of the CPL and the LGPL along with this - ** file. See the LICENSE file and the cpl1.0.txt/lgpl-2.1.txt files - ** included with the source distribution for more information. - ** If you did not receive a copy of the licenses, contact the Qxt Foundation. - ** - ** - ** - ****************************************************************************/ - -#ifndef QXTCOMMANDOPTIONS_H -#define QXTCOMMANDOPTIONS_H -#include -#include -#include -#include // for Q_DECLARE_TR_FUNCTIONS -#include -#include -class QxtCommandOptionsPrivate; -QT_FORWARD_DECLARE_CLASS(QTextStream) -QT_FORWARD_DECLARE_CLASS(QIODevice) - - -class QxtCommandOptions -{ - Q_DECLARE_TR_FUNCTIONS(QxtCommandOptions) - -public: - /*! - * \enum QxtCommandOptions::FlagStyle - * This enum type defines which type of option prefix is used. - * Slash is the default on Windows. - * DoubleDash is the default on all other platforms. - */ - enum FlagStyle - { - DoubleDash, /*!< Two dashes (GNU-style) */ - SingleDash, /*!< One dash (UNIX-style) */ - Slash /*!< Forward slash (Windows-style) */ - }; - /*! - * \enum QxtCommandOptions::ParamStyle - * This enum type defines what syntax is used for options that - * require parameters. Equals is the default on Windows. - * SpaceAndEquals is the default on all other platforms. - */ - enum ParamStyle - { - Space = 1, /*!< Space ("-option value") */ - Equals = 2, /*!< Equals sign ("/option=value") */ - SpaceAndEquals = 3 /*!< Accept either */ - }; - /*! - * \enum QxtCommandOptions::ParamType - * \flags QxtCommandOptions::ParamTypes - * This enum type is used to specify flags that control the - * interpretation of an option. - * - * The ParamTypes type is a typedef for QFlags. It stores - * an OR combination of ParamType values. - */ - enum ParamType - { - NoValue = 0, /*!< The option does not accept a value. */ - ValueOptional = 1, /*!< The option may accept a value. */ - ValueRequired = 2, /*!< The option requires a value. */ - Optional = ValueOptional, /*!< The option may accept a value. Deprecated in favor of ValueOptional. */ - Required = ValueRequired, /*!< The option requires a value. Deprecated in favor of ValueRequired. */ - AllowMultiple = 4, /*!< The option may be passed multiple times. */ - Undocumented = 8 /*!< The option is not output in the help text. */ - }; - Q_DECLARE_FLAGS(ParamTypes, ParamType) - - QxtCommandOptions(); - - void setFlagStyle(FlagStyle style); - FlagStyle flagStyle() const; - void setParamStyle(ParamStyle style); - ParamStyle paramStyle() const; - void setScreenWidth(quint16 width); - quint16 screenWidth() const; - - void addSection(const QString& name); - void add(const QString& name, const QString& desc = QString(), ParamTypes paramType = NoValue, int group = -1); - void alias(const QString& from, const QString& to); - - QStringList positional() const; - QStringList unrecognized() const; - int count(const QString& name) const; - QVariant value(const QString& name) const; - QMultiHash parameters() const; - - void parse(int argc, char** argv); - void parse(QStringList params); - - void showUsage(bool showQtOptions = false, QIODevice* device = 0) const; - void showUsage(bool showQtOptions, QTextStream& stream) const; - QString getUsage(bool showQtOptions = false) const; - - bool showUnrecognizedWarning(QIODevice* device = 0) const; - bool showUnrecognizedWarning(QTextStream& stream) const; - QString getUnrecognizedWarning() const; - -private: - QXT_DECLARE_PRIVATE(QxtCommandOptions) -}; -Q_DECLARE_OPERATORS_FOR_FLAGS(QxtCommandOptions::ParamTypes) - -#endif // QXTCOMMANDOPTIONS_H diff --git a/companion/src/thirdparty/qxtcommandoptions/qxtglobal.h b/companion/src/thirdparty/qxtcommandoptions/qxtglobal.h deleted file mode 100644 index a5744d88f..000000000 --- a/companion/src/thirdparty/qxtcommandoptions/qxtglobal.h +++ /dev/null @@ -1,207 +0,0 @@ -/**************************************************************************** - ** - ** Copyright (C) Qxt Foundation. Some rights reserved. - ** - ** This file is part of the QxtCore module of the Qxt library. - ** - ** This library is free software; you can redistribute it and/or modify it - ** under the terms of the Common Public License, version 1.0, as published - ** by IBM, and/or under the terms of the GNU Lesser General Public License, - ** version 2.1, as published by the Free Software Foundation. - ** - ** This file is provided "AS IS", without WARRANTIES OR CONDITIONS OF ANY - ** KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT LIMITATION, ANY - ** WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, MERCHANTABILITY OR - ** FITNESS FOR A PARTICULAR PURPOSE. - ** - ** You should have received a copy of the CPL and the LGPL along with this - ** file. See the LICENSE file and the cpl1.0.txt/lgpl-2.1.txt files - ** included with the source distribution for more information. - ** If you did not receive a copy of the licenses, contact the Qxt Foundation. - ** - ** - ** - ****************************************************************************/ - -#ifndef QXTGLOBAL_H -#define QXTGLOBAL_H - -#include - -#define QXT_VERSION 0x000602 -#define QXT_VERSION_STR "0.6.2" - -//--------------------------global macros------------------------------ - -#ifndef QXT_NO_MACROS - -#endif // QXT_NO_MACROS - -//--------------------------export macros------------------------------ - -#define QXT_DLLEXPORT DO_NOT_USE_THIS_ANYMORE - -#if !defined(QXT_STATIC) -# if defined(BUILD_QXT_CORE) -# define QXT_CORE_EXPORT Q_DECL_EXPORT -# else -# define QXT_CORE_EXPORT Q_DECL_IMPORT -# endif -#else -# define QXT_CORE_EXPORT -#endif // BUILD_QXT_CORE - -#if !defined(QXT_STATIC) -# if defined(BUILD_QXT_GUI) -# define QXT_GUI_EXPORT Q_DECL_EXPORT -# else -# define QXT_GUI_EXPORT Q_DECL_IMPORT -# endif -#else -# define QXT_GUI_EXPORT -#endif // BUILD_QXT_GUI - -#if !defined(QXT_STATIC) -# if defined(BUILD_QXT_NETWORK) -# define QXT_NETWORK_EXPORT Q_DECL_EXPORT -# else -# define QXT_NETWORK_EXPORT Q_DECL_IMPORT -# endif -#else -# define QXT_NETWORK_EXPORT -#endif // BUILD_QXT_NETWORK - -#if !defined(QXT_STATIC) -# if defined(BUILD_QXT_SQL) -# define QXT_SQL_EXPORT Q_DECL_EXPORT -# else -# define QXT_SQL_EXPORT Q_DECL_IMPORT -# endif -#else -# define QXT_SQL_EXPORT -#endif // BUILD_QXT_SQL - -#if !defined(QXT_STATIC) -# if defined(BUILD_QXT_WEB) -# define QXT_WEB_EXPORT Q_DECL_EXPORT -# else -# define QXT_WEB_EXPORT Q_DECL_IMPORT -# endif -#else -# define QXT_WEB_EXPORT -#endif // BUILD_QXT_WEB - -#if !defined(QXT_STATIC) -# if defined(BUILD_QXT_BERKELEY) -# define QXT_BERKELEY_EXPORT Q_DECL_EXPORT -# else -# define QXT_BERKELEY_EXPORT Q_DECL_IMPORT -# endif -#else -# define QXT_BERKELEY_EXPORT -#endif // BUILD_QXT_BERKELEY - -#if !defined(QXT_STATIC) -# if defined(BUILD_QXT_ZEROCONF) -# define QXT_ZEROCONF_EXPORT Q_DECL_EXPORT -# else -# define QXT_ZEROCONF_EXPORT Q_DECL_IMPORT -# endif -#else -# define QXT_ZEROCONF_EXPORT -#endif // QXT_ZEROCONF_EXPORT - -#if defined BUILD_QXT_CORE || defined BUILD_QXT_GUI || defined BUILD_QXT_SQL || defined BUILD_QXT_NETWORK || defined BUILD_QXT_WEB || defined BUILD_QXT_BERKELEY || defined BUILD_QXT_ZEROCONF -# define BUILD_QXT -#endif - -QXT_CORE_EXPORT const char* qxtVersion(); - -#ifndef QT_BEGIN_NAMESPACE -#define QT_BEGIN_NAMESPACE -#endif - -#ifndef QT_END_NAMESPACE -#define QT_END_NAMESPACE -#endif - -#ifndef QT_FORWARD_DECLARE_CLASS -#define QT_FORWARD_DECLARE_CLASS(Class) class Class; -#endif - -/**************************************************************************** -** This file is derived from code bearing the following notice: -** The sole author of this file, Adam Higerd, has explicitly disclaimed all -** copyright interest and protection for the content within. This file has -** been placed in the public domain according to United States copyright -** statute and case law. In jurisdictions where this public domain dedication -** is not legally recognized, anyone who receives a copy of this file is -** permitted to use, modify, duplicate, and redistribute this file, in whole -** or in part, with no restrictions or conditions. In these jurisdictions, -** this file shall be copyright (C) 2006-2008 by Adam Higerd. -****************************************************************************/ - -#define QXT_DECLARE_PRIVATE(PUB) friend class PUB##Private; QxtPrivateInterface qxt_d; -#define QXT_DECLARE_PUBLIC(PUB) friend class PUB; -#define QXT_INIT_PRIVATE(PUB) qxt_d.setPublic(this); -#define QXT_D(PUB) PUB##Private& d = qxt_d() -#define QXT_P(PUB) PUB& p = qxt_p() - -template -class QxtPrivate -{ -public: - virtual ~QxtPrivate() - {} - inline void QXT_setPublic(PUB* pub) - { - qxt_p_ptr = pub; - } - -protected: - inline PUB& qxt_p() - { - return *qxt_p_ptr; - } - inline const PUB& qxt_p() const - { - return *qxt_p_ptr; - } - -private: - PUB* qxt_p_ptr; -}; - -template -class QxtPrivateInterface -{ - friend class QxtPrivate; -public: - QxtPrivateInterface() - { - pvt = new PVT; - } - ~QxtPrivateInterface() - { - delete pvt; - } - - inline void setPublic(PUB* pub) - { - pvt->QXT_setPublic(pub); - } - inline PVT& operator()() - { - return *static_cast(pvt); - } - inline const PVT& operator()() const - { - return *static_cast(pvt); - } -private: - QxtPrivateInterface(const QxtPrivateInterface&) { } - QxtPrivateInterface& operator=(const QxtPrivateInterface&) { } - QxtPrivate* pvt; -}; - -#endif // QXT_GLOBAL From 95bc595f50648d0894a82ba299956b076d42dcfe Mon Sep 17 00:00:00 2001 From: 3djc Date: Sun, 16 Apr 2017 21:13:51 +0200 Subject: [PATCH 133/203] Better manage additional switches declared as toggle or 2pos (#4793) --- radio/src/targets/taranis/keys_driver.cpp | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/radio/src/targets/taranis/keys_driver.cpp b/radio/src/targets/taranis/keys_driver.cpp index 0794419d9..3a43bbdb2 100644 --- a/radio/src/targets/taranis/keys_driver.cpp +++ b/radio/src/targets/taranis/keys_driver.cpp @@ -2,7 +2,7 @@ * Copyright (C) OpenTX * * Based on code named - * th9x - http://code.google.com/p/th9x + * th9x - http://code.google.com/p/th9x * er9x - http://code.google.com/p/er9x * gruvin9x - http://code.google.com/p/gruvin9x * @@ -123,17 +123,7 @@ void readKeysAndTrims() break; \ case SW_S ## x ## 0: \ xxx = ~SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ - break - #define ADD_3POS_CASE(x, i) \ - case SW_S ## x ## 0: \ - xxx = (SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H) && (~SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ - break; \ - case SW_S ## x ## 1: \ - xxx = (SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H) && (SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ - break; \ - case SW_S ## x ## 2: \ - xxx = (~SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H) && (SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ - break + break; #else #define ADD_2POS_CASE(x) \ case SW_S ## x ## 0: \ @@ -141,7 +131,8 @@ void readKeysAndTrims() break; \ case SW_S ## x ## 2: \ xxx = ~SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ - break + break; +#endif #define ADD_3POS_CASE(x, i) \ case SW_S ## x ## 0: \ xxx = (SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H); \ @@ -158,7 +149,6 @@ void readKeysAndTrims() xxx = xxx && (SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ } \ break -#endif uint8_t keyState(uint8_t index) { @@ -169,7 +159,7 @@ uint8_t keyState(uint8_t index) uint32_t switchState(uint8_t index) { uint32_t xxx = 0; - + switch (index) { ADD_3POS_CASE(A, 0); ADD_3POS_CASE(B, 1); @@ -248,7 +238,7 @@ void keysInit() GPIO_InitStructure.GPIO_Pin = KEYS_GPIOG_PINS; GPIO_Init(GPIOG, &GPIO_InitStructure); #endif - + #if defined(ROTARY_ENCODER_NAVIGATION) rotencPosition = ROTARY_ENCODER_POSITION(); #endif From c6148c109c6326cf1a22a9b03a1417cf50d2cebf Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Mon, 17 Apr 2017 09:59:12 +0200 Subject: [PATCH 134/203] Update DONATIONS.txt --- DONATIONS.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index 788aad4af..fe60c0588 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1156,3 +1156,16 @@ Chris Monk Alvin Burke Georges d'Haussy Philippe Lhomme +Carsten Ullerup +Wolfgang Schneider-Reif +Anselm Schopplick +Georgios Papadopoulos +Thorsten Weber +Alexander Röhlich +Karl-Heinz Behn +Stefan Köhler +Jochen Kaphengst +Hans-Jüergen Duwe +Christoph Dalloz +Alexander Wimmer +Horst Efftinge From 13e6ae1d08cc35e9e8dffe6048ff2d2a106632ba Mon Sep 17 00:00:00 2001 From: 3djc Date: Mon, 17 Apr 2017 10:03:45 +0200 Subject: [PATCH 135/203] Move tm_year to unsigned (#4811) Fixes 4627 --- radio/src/rtc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/radio/src/rtc.h b/radio/src/rtc.h index ad43fc9c8..cf037ede8 100644 --- a/radio/src/rtc.h +++ b/radio/src/rtc.h @@ -2,7 +2,7 @@ * Copyright (C) OpenTX * * Based on code named - * th9x - http://code.google.com/p/th9x + * th9x - http://code.google.com/p/th9x * er9x - http://code.google.com/p/er9x * gruvin9x - http://code.google.com/p/gruvin9x * @@ -39,7 +39,7 @@ struct gtm int8_t tm_hour; /* Hours. [0-23] */ int8_t tm_mday; /* Day. [1-31] */ int8_t tm_mon; /* Month. [0-11] */ - int8_t tm_year; /* Year - 1900. Limited to the year 2115. Oh no! :P */ + uint8_t tm_year; /* Year - 1900. Limited to the year 2155. */ int8_t tm_wday; /* Day of week. [0-6] */ int16_t tm_yday; /* Day of year. [0-365] Needed internally for calculations */ }; From a719c391a11bfbe28272b26bd22db8f69c56f8b2 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Mon, 17 Apr 2017 10:04:09 +0200 Subject: [PATCH 136/203] Fixes #4768 (#4807) --- companion/src/firmwares/opentx/opentxeeprom.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/companion/src/firmwares/opentx/opentxeeprom.cpp b/companion/src/firmwares/opentx/opentxeeprom.cpp index b72db253f..65abe0833 100644 --- a/companion/src/firmwares/opentx/opentxeeprom.cpp +++ b/companion/src/firmwares/opentx/opentxeeprom.cpp @@ -243,9 +243,12 @@ class SourcesConversionTable: public ConversionTable { for (int i=0; i<32; i++) { addConversion(RawSource(SOURCE_TYPE_VIRTUAL_INPUT, i), val++); } - for (int i=0; i= 216) { + for (int i = 0; i < MAX_SCRIPTS(board); i++) { + for (int j = 0; j < 6; j++) { + addConversion(RawSource(SOURCE_TYPE_LUA_OUTPUT, i * 16 + j), val++); } } } From b0b270963c0dbcca74c5d314ccb607ae0daf9856 Mon Sep 17 00:00:00 2001 From: Andre Bernet Date: Mon, 17 Apr 2017 10:16:20 +0200 Subject: [PATCH 137/203] Cosmetics --- radio/src/rtc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/rtc.h b/radio/src/rtc.h index cf037ede8..db421a4ea 100644 --- a/radio/src/rtc.h +++ b/radio/src/rtc.h @@ -39,7 +39,7 @@ struct gtm int8_t tm_hour; /* Hours. [0-23] */ int8_t tm_mday; /* Day. [1-31] */ int8_t tm_mon; /* Month. [0-11] */ - uint8_t tm_year; /* Year - 1900. Limited to the year 2155. */ + uint8_t tm_year; /* Year - 1900. Limited to the year 2155. */ int8_t tm_wday; /* Day of week. [0-6] */ int16_t tm_yday; /* Day of year. [0-365] Needed internally for calculations */ }; From 471c38628fc9c204ceb3809f2afdc4c308a73b75 Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Mon, 17 Apr 2017 10:22:21 +0200 Subject: [PATCH 138/203] Fix key variable not initialised (#4790) --- radio/src/targets/simu/opentxsimulator.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/radio/src/targets/simu/opentxsimulator.cpp b/radio/src/targets/simu/opentxsimulator.cpp index e7260e39c..97ca3efc0 100644 --- a/radio/src/targets/simu/opentxsimulator.cpp +++ b/radio/src/targets/simu/opentxsimulator.cpp @@ -284,6 +284,9 @@ void OpenTxSimulator::rotaryEncoderEvent(int steps) key = KEY_MINUS; else if (steps < 0) key = KEY_PLUS; + else + // Should not happen but Clang complains that key is unset otherwise + return; setKey(key, 1); #if (QT_VERSION >= QT_VERSION_CHECK(5, 4, 0)) From 2b41ba94ff7d5c050364f89a5a4e95a2602846c4 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Mon, 17 Apr 2017 10:23:09 +0200 Subject: [PATCH 139/203] Update opentxsimulator.cpp --- radio/src/targets/simu/opentxsimulator.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/radio/src/targets/simu/opentxsimulator.cpp b/radio/src/targets/simu/opentxsimulator.cpp index 97ca3efc0..16c8566ee 100644 --- a/radio/src/targets/simu/opentxsimulator.cpp +++ b/radio/src/targets/simu/opentxsimulator.cpp @@ -285,8 +285,8 @@ void OpenTxSimulator::rotaryEncoderEvent(int steps) else if (steps < 0) key = KEY_PLUS; else - // Should not happen but Clang complains that key is unset otherwise - return; + // Should not happen but Clang complains that key is unset otherwise + return; setKey(key, 1); #if (QT_VERSION >= QT_VERSION_CHECK(5, 4, 0)) From 54c1f223120ee2cab8bc434ab0e330a990e14b5b Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Mon, 17 Apr 2017 10:25:56 +0200 Subject: [PATCH 140/203] Multimodule has a pulldown resistor and does not work with open drain, use push pull instead (#4808) --- radio/src/targets/sky9x/pulses_driver.cpp | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/radio/src/targets/sky9x/pulses_driver.cpp b/radio/src/targets/sky9x/pulses_driver.cpp index f51766cca..08ea1f630 100644 --- a/radio/src/targets/sky9x/pulses_driver.cpp +++ b/radio/src/targets/sky9x/pulses_driver.cpp @@ -51,7 +51,7 @@ void module_output_active() pioptr->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 } else { - pioptr->PIO_MDER = PIO_PA17; // Open Drain O/p in A17 + pioptr->PIO_MDER = PIO_PA17; // Open Drain O/p in A17 } #else pioptr->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 @@ -163,21 +163,25 @@ void disable_ppm(uint32_t port) // TD is on PA17, peripheral A void init_ssc(uint8_t baudrateDiv1000) { - Ssc * sscptr; + Ssc *sscptr; PMC->PMC_PCER0 |= 0x00400000L; // Enable peripheral clock to SSC configure_pins(PIO_PA17, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA); sscptr = SSC; - sscptr->SSC_THR = 0xFF; // Make the output high. + sscptr->SSC_THR = 0xFF; // Make the output high. sscptr->SSC_TFMR = 0x00000027; // 0000 0000 0000 0000 0000 0000 1010 0111 (8 bit data, lsb) - sscptr->SSC_CMR = Master_frequency / (1000*baudrateDiv1000*2); + sscptr->SSC_CMR = Master_frequency / (1000 * baudrateDiv1000 * 2); sscptr->SSC_TCMR = 0; sscptr->SSC_CR = SSC_CR_TXEN; #if defined(REVX) - PIOA->PIO_MDER = PIO_PA17; // Open Drain O/p in A17 + if (IS_MODULE_MULTIMODULE(EXTERNAL_MODULE)) { + PIOA->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 + } else { + PIOA->PIO_MDER = PIO_PA17; // Open Drain O/p in A17 + } #else PIOA->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 #endif From 46f03848281734f67c790b5fe4bd9ccaa8dc079c Mon Sep 17 00:00:00 2001 From: 3djc Date: Mon, 17 Apr 2017 12:02:33 +0200 Subject: [PATCH 141/203] No reason for that just yet --- tools/build-companion.sh | 3 --- 1 file changed, 3 deletions(-) diff --git a/tools/build-companion.sh b/tools/build-companion.sh index 998d073b3..fa4ef3be0 100755 --- a/tools/build-companion.sh +++ b/tools/build-companion.sh @@ -65,9 +65,6 @@ make -j${JOBS} libsimulator cmake ${COMMON_OPTIONS} -DPCB=X9E ${SRCDIR} make -j${JOBS} libsimulator -cmake ${COMMON_OPTIONS} -DPCB=X10 ${SRCDIR} -make -j${JOBS} libsimulator - cmake ${COMMON_OPTIONS} -DPCB=X12S ${SRCDIR} make -j${JOBS} libsimulator From 9a93d85ef6e163f2f32d500eb5092fcd17142c09 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Tue, 18 Apr 2017 08:33:23 +0200 Subject: [PATCH 142/203] Update DONATIONS.txt --- DONATIONS.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index fe60c0588..bb76d92e7 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1169,3 +1169,5 @@ Hans-Jüergen Duwe Christoph Dalloz Alexander Wimmer Horst Efftinge +Nektarios Ntikmpasanis +Derek Gates From 0c260ce12d336255c8e69e0b398b5e20b95dd2fc Mon Sep 17 00:00:00 2001 From: 3djc Date: Tue, 18 Apr 2017 12:55:43 +0200 Subject: [PATCH 143/203] Invert outputs limits when output is reversed (#4813) * Invert outputs limits when output is reversed * Cosmetics --- radio/src/gui/480x272/view_channels.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/radio/src/gui/480x272/view_channels.cpp b/radio/src/gui/480x272/view_channels.cpp index a64a73f1e..c2bb86704 100644 --- a/radio/src/gui/480x272/view_channels.cpp +++ b/radio/src/gui/480x272/view_channels.cpp @@ -149,14 +149,17 @@ void drawComboOutputBar(coord_t x, coord_t y, coord_t w, coord_t h, uint8_t chan lcdDrawSolidFilledRect(endpoint - size, y + Y_OUTBAR, size, h, BARGRAPH1_COLOR); } - if (ld) + if (ld && ld->revert) { + drawOutputBarLimits(x + posOnBar(-100 - ld->max / 10), x + posOnBar(100 - ld->min / 10), y + Y_OUTBAR); + lcd->drawBitmap(x - X_OFFSET + 7, y + 25, chanMonInvertedBitmap); + } + else if (ld) { drawOutputBarLimits(x + posOnBar(-100 + ld->min / 10), x + posOnBar(100 + ld->max / 10), y + Y_OUTBAR); + } #if defined(OVERRIDE_CHANNEL_FUNCTION) if (safetyCh[channel] != OVERRIDE_CHANNEL_UNDEFINED) lcd->drawBitmap(x - X_OFFSET + 7, y + 7, chanMonLockedBitmap); #endif - if (ld && ld->revert) - lcd->drawBitmap(x - X_OFFSET + 7, y + 25, chanMonInvertedBitmap); lcd->drawSolidVerticalLine(x + w / 2, y + Y_OUTBAR, h, TEXT_COLOR); } From 6e427bca74f640ca471cc687deee5193c145469f Mon Sep 17 00:00:00 2001 From: 3djc Date: Tue, 18 Apr 2017 12:56:03 +0200 Subject: [PATCH 144/203] Do not allow past SWSRC_TELEMETRY_STREAMING for global functions (#4814) --- radio/src/gui/128x64/model_special_functions.cpp | 2 +- radio/src/gui/212x64/model_special_functions.cpp | 2 +- radio/src/gui/480x272/model_special_functions.cpp | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/radio/src/gui/128x64/model_special_functions.cpp b/radio/src/gui/128x64/model_special_functions.cpp index d120965f5..962f63424 100644 --- a/radio/src/gui/128x64/model_special_functions.cpp +++ b/radio/src/gui/128x64/model_special_functions.cpp @@ -191,7 +191,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF } else { drawSwitch(MODEL_SPECIAL_FUNC_1ST_COLUMN, y, CFN_SWITCH(cfn), attr | ((functionsContext->activeSwitches & ((MASK_CFN_TYPE)1 << k)) ? BOLD : 0)); - if (active || AUTOSWITCH_ENTER_LONG()) CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); + if (active || AUTOSWITCH_ENTER_LONG()) CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, g_eeGeneral.customFn ? SWSRC_TELEMETRY_STREAMING : SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); } #else drawSwitch(MODEL_SPECIAL_FUNC_1ST_COLUMN, y, CFN_SWITCH(cfn), attr | ((functionsContext->activeSwitches & ((MASK_CFN_TYPE)1 << k)) ? BOLD : 0)); diff --git a/radio/src/gui/212x64/model_special_functions.cpp b/radio/src/gui/212x64/model_special_functions.cpp index c02c90faa..242edc9ae 100644 --- a/radio/src/gui/212x64/model_special_functions.cpp +++ b/radio/src/gui/212x64/model_special_functions.cpp @@ -182,7 +182,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF switch (j) { case ITEM_CUSTOM_FUNCTIONS_SWITCH: drawSwitch(MODEL_SPECIAL_FUNC_1ST_COLUMN, y, CFN_SWITCH(cfn), attr | ((functionsContext->activeSwitches & ((MASK_CFN_TYPE)1 << k)) ? BOLD : 0)); - if (active || AUTOSWITCH_ENTER_LONG()) CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); + if (active || AUTOSWITCH_ENTER_LONG()) CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, g_eeGeneral.customFn ? SWSRC_TELEMETRY_STREAMING : SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); if (func == FUNC_OVERRIDE_CHANNEL && functions != g_model.customFn) { func = CFN_FUNC(cfn) = func+1; } diff --git a/radio/src/gui/480x272/model_special_functions.cpp b/radio/src/gui/480x272/model_special_functions.cpp index 18b6a5756..a31208d3e 100644 --- a/radio/src/gui/480x272/model_special_functions.cpp +++ b/radio/src/gui/480x272/model_special_functions.cpp @@ -182,7 +182,7 @@ bool menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF case ITEM_SPECIAL_FUNCTIONS_SWITCH: drawSwitch(MODEL_SPECIAL_FUNC_1ST_COLUMN, y, CFN_SWITCH(cfn), attr | ((functionsContext.activeSwitches & ((MASK_CFN_TYPE)1 << k)) ? BOLD : 0)); if (active || AUTOSWITCH_ENTER_LONG()) { - CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); + CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, g_eeGeneral.customFn ? SWSRC_TELEMETRY_STREAMING : SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); } if (func == FUNC_OVERRIDE_CHANNEL && functions != g_model.customFn) { func = CFN_FUNC(cfn) = func+1; From 189b65b7241d1e494e7c0c25013669a188bfd5b8 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Tue, 18 Apr 2017 22:11:39 +0200 Subject: [PATCH 145/203] Update DONATIONS.txt --- DONATIONS.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index bb76d92e7..92af6bd87 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1171,3 +1171,5 @@ Alexander Wimmer Horst Efftinge Nektarios Ntikmpasanis Derek Gates +John Alsbrooks +Jürgen Deininger From fa951acf404bdbf3bd28d2f4a81058029350e774 Mon Sep 17 00:00:00 2001 From: 3djc Date: Wed, 19 Apr 2017 10:54:43 +0200 Subject: [PATCH 146/203] Review line ending handling (#4820) * New line end handling rules * Normalize all the line endings --- .gitattributes | 111 + cmake/FindXercesC.cmake | 134 +- companion/src/icon.rc | 2 +- companion/targets/windows/FileAssociation.nsh | 378 +- companion/targets/windows/license.txt | 22 +- radio/sdcard/horus/S6R/S6R.lua | 680 +- radio/sdcard/taranis-x7/SCRIPTS/snake.lua | 352 +- .../taranis-x9/SCRIPTS/WIZARD/delta.lua | 750 +- .../taranis-x9/SCRIPTS/WIZARD/multi.lua | 610 +- .../taranis-x9/SCRIPTS/WIZARD/plane.lua | 1134 +- .../taranis-x9/SCRIPTS/WIZARD/wizard.lua | 148 +- radio/sdcard/taranis-x9/SCRIPTS/snake.lua | 352 +- radio/src/bitmaps/sticks.xbm | 22 +- radio/src/buzzer.h | 350 +- radio/src/disk_cache.cpp | 360 +- radio/src/disk_cache.h | 148 +- radio/src/dmafifo.h | 164 +- radio/src/fifo.h | 210 +- radio/src/fonts.h | 112 +- radio/src/gui/480x272/bitmapbuffer.cpp | 1662 +- radio/src/gui/480x272/fonts.cpp | 220 +- radio/src/gui/480x272/view_about.cpp | 306 +- radio/src/gui/480x272/view_channels.cpp | 384 +- radio/src/gui/480x272/view_statistics.cpp | 476 +- radio/src/haptic.h | 152 +- radio/src/keys.h | 226 +- radio/src/pwr.h | 18 +- radio/src/rtc.h | 126 +- radio/src/serial.h | 32 +- radio/src/storage/eeprom_common.cpp | 274 +- radio/src/storage/eeprom_common.h | 38 +- radio/src/storage/eeprom_conversions.cpp | 2608 +- radio/src/syscalls.c | 232 +- radio/src/targets/9x/board.cpp | 728 +- radio/src/targets/9x/board.h | 520 +- radio/src/targets/9x/lcd_default_driver.cpp | 276 +- radio/src/targets/9x/lcd_driver.cpp | 76 +- radio/src/targets/9x/lcd_ks108_driver.cpp | 184 +- radio/src/targets/9x/lcd_st7920_driver.cpp | 274 +- radio/src/targets/9x/voice.cpp | 278 +- radio/src/targets/9x/voice.h | 250 +- radio/src/targets/common/arm/stm32/delays.cpp | 112 +- .../common/arm/stm32/f4/system_stm32f4xx.c | 1142 +- .../targets/common/arm/stm32/rtc_driver.cpp | 172 +- .../common/arm/stm32/serial2_driver.cpp | 342 +- radio/src/targets/common/arm/stm32/usb_bsp.c | 236 +- radio/src/targets/common/arm/stm32/usb_conf.h | 336 +- .../src/targets/common/arm/stm32/usbd_cdc.cpp | 464 +- .../src/targets/common/arm/stm32/usbd_conf.h | 82 +- .../src/targets/common/arm/stm32/usbd_desc.c | 478 +- .../src/targets/common/arm/stm32/usbd_desc.h | 182 +- .../common/arm/stm32/usbd_hid_joystick.c | 910 +- .../common/arm/stm32/usbd_storage_msd.cpp | 1542 +- .../src/targets/common/arm/stm32/usbd_usr.cpp | 244 +- radio/src/targets/gruvin9x/board.h | 342 +- radio/src/targets/gruvin9x/diskio.cpp | 1352 +- radio/src/targets/gruvin9x/rtc_driver.cpp | 608 +- radio/src/targets/horus/adc_driver.cpp | 520 +- radio/src/targets/horus/bluetooth_driver.cpp | 522 +- radio/src/targets/horus/diskio.cpp | 752 +- radio/src/targets/horus/extmodule_driver.cpp | 618 +- radio/src/targets/horus/hal.h | 1254 +- radio/src/targets/horus/keys_driver.cpp | 434 +- radio/src/targets/horus/lcd_driver.cpp | 1164 +- radio/src/targets/horus/pulses_driver.cpp | 540 +- radio/src/targets/horus/pwr_driver.cpp | 300 +- radio/src/targets/horus/sdio_sd.c | 5534 ++-- radio/src/targets/horus/sdio_sd.h | 440 +- radio/src/targets/horus/sdram_driver.c | 930 +- .../targets/horus/startup_stm32f40_41xxx.s | 1058 +- radio/src/targets/horus/telemetry_driver.cpp | 464 +- radio/src/targets/horus/trainer_driver.cpp | 308 +- radio/src/targets/mega2560/00readme.txt | 14 +- radio/src/targets/mega2560/board.h | 392 +- radio/src/targets/sky9x/AT91SAM3S2.h | 14024 +++++----- radio/src/targets/sky9x/AT91SAM3S4.h | 14226 +++++----- radio/src/targets/sky9x/MEDSdcard.c | 492 +- radio/src/targets/sky9x/Media.h | 512 +- radio/src/targets/sky9x/adc_driver.cpp | 296 +- radio/src/targets/sky9x/audio_driver.cpp | 390 +- radio/src/targets/sky9x/board.cpp | 1218 +- radio/src/targets/sky9x/board.h | 828 +- radio/src/targets/sky9x/board_lowlevel.c | 506 +- radio/src/targets/sky9x/board_lowlevel.h | 1278 +- radio/src/targets/sky9x/buzzer_driver.cpp | 118 +- radio/src/targets/sky9x/chip.h | 196 +- radio/src/targets/sky9x/coproc_driver.cpp | 410 +- radio/src/targets/sky9x/core_cm3.c | 1696 +- radio/src/targets/sky9x/core_cm3.h | 3584 +-- radio/src/targets/sky9x/crt.c | 262 +- radio/src/targets/sky9x/diskio.cpp | 2760 +- radio/src/targets/sky9x/eeprom_driver.cpp | 400 +- radio/src/targets/sky9x/haptic_driver.cpp | 88 +- radio/src/targets/sky9x/keys_driver.cpp | 394 +- radio/src/targets/sky9x/massstorage.cpp | 416 +- radio/src/targets/sky9x/pulses_driver.cpp | 732 +- radio/src/targets/sky9x/pwr_driver.cpp | 94 +- radio/src/targets/sky9x/rotenc_driver.cpp | 114 +- radio/src/targets/sky9x/rtc_driver.cpp | 574 +- radio/src/targets/sky9x/sam3s2c_flash.ld | 300 +- radio/src/targets/sky9x/sam3s4c_flash.ld | 308 +- radio/src/targets/sky9x/sam3s8c_flash.ld | 312 +- radio/src/targets/sky9x/sdcard_driver.cpp | 104 +- radio/src/targets/sky9x/serial2_driver.cpp | 238 +- .../common/core/USBConfigurationDescriptor.c | 324 +- .../common/core/USBConfigurationDescriptor.h | 300 +- .../usb/common/core/USBDeviceDescriptor.h | 250 +- .../core/USBDeviceQualifierDescriptor.h | 178 +- .../usb/common/core/USBEndpointDescriptor.c | 218 +- .../usb/common/core/USBEndpointDescriptor.h | 448 +- .../sky9x/usb/common/core/USBFeatureRequest.c | 140 +- .../sky9x/usb/common/core/USBFeatureRequest.h | 292 +- .../usb/common/core/USBGenericDescriptor.c | 160 +- .../usb/common/core/USBGenericDescriptor.h | 266 +- .../sky9x/usb/common/core/USBGenericRequest.c | 276 +- .../sky9x/usb/common/core/USBGenericRequest.h | 488 +- .../usb/common/core/USBGetDescriptorRequest.c | 144 +- .../usb/common/core/USBGetDescriptorRequest.h | 134 +- .../core/USBInterfaceAssociationDescriptor.h | 172 +- .../usb/common/core/USBInterfaceDescriptor.h | 174 +- .../usb/common/core/USBInterfaceRequest.c | 138 +- .../usb/common/core/USBInterfaceRequest.h | 136 +- .../sky9x/usb/common/core/USBIrqHandler.c | 124 +- .../sky9x/usb/common/core/USBIrqHandler.h | 104 +- .../usb/common/core/USBSetAddressRequest.c | 112 +- .../usb/common/core/USBSetAddressRequest.h | 120 +- .../common/core/USBSetConfigurationRequest.c | 116 +- .../common/core/USBSetConfigurationRequest.h | 122 +- .../usb/common/core/USBStringDescriptor.h | 148 +- .../common/massstorage/MSDeviceDescriptor.h | 146 +- .../massstorage/MSInterfaceDescriptor.h | 150 +- .../sky9x/usb/device/massstorage/MSD.h | 466 +- .../usb/device/massstorage/MSDDStateMachine.c | 1220 +- .../usb/device/massstorage/MSDDStateMachine.h | 528 +- .../sky9x/usb/device/massstorage/MSDDriver.c | 684 +- .../sky9x/usb/device/massstorage/MSDDriver.h | 150 +- .../device/massstorage/MSDDriverDescriptors.c | 938 +- .../device/massstorage/MSDDriverDescriptors.h | 166 +- .../sky9x/usb/device/massstorage/MSDIOFifo.h | 270 +- .../sky9x/usb/device/massstorage/MSDLun.c | 734 +- .../sky9x/usb/device/massstorage/MSDLun.h | 322 +- .../sky9x/usb/device/massstorage/SBC.h | 1342 +- .../sky9x/usb/device/massstorage/SBCMethods.c | 3270 +-- .../sky9x/usb/device/massstorage/SBCMethods.h | 220 +- radio/src/targets/sky9x/vectors_sam3s.c | 306 +- .../src/targets/taranis/backlight_driver.cpp | 336 +- .../src/targets/taranis/bluetooth_driver.cpp | 498 +- radio/src/targets/taranis/board.cpp | 650 +- radio/src/targets/taranis/diskio.cpp | 2082 +- radio/src/targets/taranis/dwt.h | 324 +- .../src/targets/taranis/extmodule_driver.cpp | 508 +- radio/src/targets/taranis/hal.h | 1666 +- radio/src/targets/taranis/i2c_driver.cpp | 584 +- radio/src/targets/taranis/keys_driver.cpp | 490 +- radio/src/targets/taranis/lcd_driver_aspi.cpp | 602 +- radio/src/targets/taranis/lcd_driver_spi.cpp | 674 +- radio/src/targets/taranis/pulses_driver.cpp | 584 +- radio/src/targets/taranis/pwr_driver.cpp | 198 +- .../targets/taranis/startup_stm32f40_41xxx.s | 1054 +- .../src/targets/taranis/telemetry_driver.cpp | 376 +- radio/src/targets/taranis/trainer_driver.cpp | 550 +- radio/src/tasks_arm.h | 162 +- radio/src/telemetry/ardupilot.cpp | 1432 +- radio/src/telemetry/mavlink.h | 652 +- radio/src/templates.h | 160 +- radio/src/thirdparty/CoOS/OsConfig.h | 628 +- radio/src/thirdparty/FatFs/00history.txt | 558 +- radio/src/thirdparty/FatFs/00readme.txt | 42 +- radio/src/thirdparty/FatFs/diskio.h | 160 +- radio/src/thirdparty/FatFs/ff.c | 12082 ++++----- radio/src/thirdparty/FatFs/ff.h | 740 +- radio/src/thirdparty/FatFs/ffconf.h | 594 +- radio/src/thirdparty/FatFs/integer.h | 76 +- radio/src/thirdparty/FatFs/option/cc932.c | 7740 +++--- radio/src/thirdparty/FatFs/option/cc936.c | 22090 ++++++++-------- radio/src/thirdparty/FatFs/option/cc949.c | 17348 ++++++------ radio/src/thirdparty/FatFs/option/cc950.c | 13800 +++++----- radio/src/thirdparty/FatFs/option/ccsbcs.c | 776 +- radio/src/thirdparty/FatFs/option/syscall.c | 302 +- radio/src/thirdparty/FatFs/option/unicode.c | 34 +- .../Device/ST/STM32F2xx/Include/stm32f2xx.h | 13934 +++++----- .../ST/STM32F2xx/Include/system_stm32f2xx.h | 210 +- .../Templates/gcc_ride7/startup_stm32f2xx.s | 1054 +- .../CMSIS/Include/arm_common_tables.h | 70 +- .../Libraries/CMSIS/Include/arm_math.h | 14102 +++++----- .../Libraries/CMSIS/Include/core_cm0.h | 1330 +- .../Libraries/CMSIS/Include/core_cm3.h | 2480 +- .../Libraries/CMSIS/Include/core_cm4.h | 2756 +- .../Libraries/CMSIS/Include/core_cm4_simd.h | 1402 +- .../Libraries/CMSIS/Include/core_cmFunc.h | 1218 +- .../Libraries/CMSIS/Include/core_cmInstr.h | 1170 +- .../STM32F2xx_StdPeriph_Driver/inc/misc.h | 356 +- .../inc/stm32f2xx_adc.h | 1298 +- .../inc/stm32f2xx_can.h | 1288 +- .../inc/stm32f2xx_crc.h | 166 +- .../inc/stm32f2xx_cryp.h | 688 +- .../inc/stm32f2xx_dac.h | 608 +- .../inc/stm32f2xx_dbgmcu.h | 218 +- .../inc/stm32f2xx_dcmi.h | 624 +- .../inc/stm32f2xx_dma.h | 1218 +- .../inc/stm32f2xx_exti.h | 366 +- .../inc/stm32f2xx_flash.h | 680 +- .../inc/stm32f2xx_fsmc.h | 1350 +- .../inc/stm32f2xx_gpio.h | 822 +- .../inc/stm32f2xx_hash.h | 500 +- .../inc/stm32f2xx_i2c.h | 1396 +- .../inc/stm32f2xx_iwdg.h | 262 +- .../inc/stm32f2xx_pwr.h | 332 +- .../inc/stm32f2xx_rcc.h | 1030 +- .../inc/stm32f2xx_rng.h | 240 +- .../inc/stm32f2xx_rtc.h | 1300 +- .../inc/stm32f2xx_sdio.h | 1072 +- .../inc/stm32f2xx_spi.h | 1052 +- .../inc/stm32f2xx_syscfg.h | 358 +- .../inc/stm32f2xx_tim.h | 2300 +- .../inc/stm32f2xx_usart.h | 858 +- .../inc/stm32f2xx_wwdg.h | 222 +- .../STM32F2xx_StdPeriph_Driver/src/misc.c | 498 +- .../src/stm32f2xx_adc.c | 3496 +-- .../src/stm32f2xx_can.c | 3408 +-- .../src/stm32f2xx_crc.c | 266 +- .../src/stm32f2xx_cryp.c | 1712 +- .../src/stm32f2xx_cryp_aes.c | 1288 +- .../src/stm32f2xx_cryp_des.c | 594 +- .../src/stm32f2xx_cryp_tdes.c | 628 +- .../src/stm32f2xx_dac.c | 1414 +- .../src/stm32f2xx_dbgmcu.c | 360 +- .../src/stm32f2xx_dcmi.c | 1080 +- .../src/stm32f2xx_dma.c | 2578 +- .../src/stm32f2xx_exti.c | 624 +- .../src/stm32f2xx_flash.c | 2120 +- .../src/stm32f2xx_fsmc.c | 1974 +- .../src/stm32f2xx_gpio.c | 1132 +- .../src/stm32f2xx_hash.c | 1412 +- .../src/stm32f2xx_hash_md5.c | 640 +- .../src/stm32f2xx_hash_sha1.c | 646 +- .../src/stm32f2xx_i2c.c | 2802 +- .../src/stm32f2xx_iwdg.c | 538 +- .../src/stm32f2xx_pwr.c | 1240 +- .../src/stm32f2xx_rcc.c | 3634 +-- .../src/stm32f2xx_rng.c | 810 +- .../src/stm32f2xx_rtc.c | 4488 ++-- .../src/stm32f2xx_sdio.c | 2020 +- .../src/stm32f2xx_spi.c | 2366 +- .../src/stm32f2xx_syscfg.c | 420 +- .../src/stm32f2xx_tim.c | 6716 ++--- .../src/stm32f2xx_usart.c | 2938 +- .../src/stm32f2xx_wwdg.c | 618 +- .../Device/ST/STM32F4xx/Include/stm32f4xx.h | 18358 ++++++------- .../ST/STM32F4xx/Include/system_stm32f4xx.h | 210 +- .../gcc_ride7/startup_stm32f40_41xxx.s | 1054 +- .../CMSIS/Include/arm_common_tables.h | 186 +- .../CMSIS/Include/arm_const_structs.h | 170 +- .../Libraries/CMSIS/Include/arm_math.h | 14612 +++++----- .../Libraries/CMSIS/Include/core_cm0.h | 1364 +- .../Libraries/CMSIS/Include/core_cm0plus.h | 1586 +- .../Libraries/CMSIS/Include/core_cm3.h | 3254 +-- .../Libraries/CMSIS/Include/core_cm4.h | 3554 +-- .../Libraries/CMSIS/Include/core_cm4_simd.h | 1346 +- .../Libraries/CMSIS/Include/core_cmFunc.h | 1272 +- .../Libraries/CMSIS/Include/core_cmInstr.h | 1376 +- .../Libraries/CMSIS/Include/core_sc000.h | 1626 +- .../Libraries/CMSIS/Include/core_sc300.h | 3196 +-- .../STM32F4xx_StdPeriph_Driver/inc/misc.h | 356 +- .../inc/stm32f4xx_adc.h | 1312 +- .../inc/stm32f4xx_can.h | 1288 +- .../inc/stm32f4xx_crc.h | 166 +- .../inc/stm32f4xx_cryp.h | 768 +- .../inc/stm32f4xx_dac.h | 608 +- .../inc/stm32f4xx_dbgmcu.h | 218 +- .../inc/stm32f4xx_dcmi.h | 624 +- .../inc/stm32f4xx_dma.h | 1218 +- .../inc/stm32f4xx_dma2d.h | 950 +- .../inc/stm32f4xx_exti.h | 366 +- .../inc/stm32f4xx_flash.h | 976 +- .../inc/stm32f4xx_flash_ramfunc.h | 206 +- .../inc/stm32f4xx_fmc.h | 2286 +- .../inc/stm32f4xx_fsmc.h | 1350 +- .../inc/stm32f4xx_gpio.h | 1004 +- .../inc/stm32f4xx_hash.h | 514 +- .../inc/stm32f4xx_i2c.h | 1422 +- .../inc/stm32f4xx_iwdg.h | 262 +- .../inc/stm32f4xx_ltdc.h | 1062 +- .../inc/stm32f4xx_pwr.h | 424 +- .../inc/stm32f4xx_rcc.h | 1260 +- .../inc/stm32f4xx_rng.h | 240 +- .../inc/stm32f4xx_rtc.h | 1762 +- .../inc/stm32f4xx_sai.h | 1222 +- .../inc/stm32f4xx_sdio.h | 1072 +- .../inc/stm32f4xx_spi.h | 1098 +- .../inc/stm32f4xx_syscfg.h | 420 +- .../inc/stm32f4xx_tim.h | 2300 +- .../inc/stm32f4xx_usart.h | 862 +- .../inc/stm32f4xx_wwdg.h | 222 +- .../STM32F4xx_StdPeriph_Driver/src/misc.c | 498 +- .../src/stm32f4xx_adc.c | 3490 +-- .../src/stm32f4xx_can.c | 3400 +-- .../src/stm32f4xx_crc.c | 266 +- .../src/stm32f4xx_cryp.c | 1868 +- .../src/stm32f4xx_cryp_aes.c | 3414 +-- .../src/stm32f4xx_cryp_des.c | 616 +- .../src/stm32f4xx_cryp_tdes.c | 650 +- .../src/stm32f4xx_dac.c | 1428 +- .../src/stm32f4xx_dbgmcu.c | 360 +- .../src/stm32f4xx_dcmi.c | 1076 +- .../src/stm32f4xx_dma.c | 2602 +- .../src/stm32f4xx_dma2d.c | 1568 +- .../src/stm32f4xx_exti.c | 622 +- .../src/stm32f4xx_flash.c | 3224 +-- .../src/stm32f4xx_flash_ramfunc.c | 316 +- .../src/stm32f4xx_fmc.c | 2734 +- .../src/stm32f4xx_fsmc.c | 1970 +- .../src/stm32f4xx_gpio.c | 1222 +- .../src/stm32f4xx_hash.c | 1452 +- .../src/stm32f4xx_hash_md5.c | 640 +- .../src/stm32f4xx_hash_sha1.c | 646 +- .../src/stm32f4xx_i2c.c | 2924 +- .../src/stm32f4xx_iwdg.c | 532 +- .../src/stm32f4xx_ltdc.c | 2220 +- .../src/stm32f4xx_pwr.c | 1878 +- .../src/stm32f4xx_rcc.c | 4614 ++-- .../src/stm32f4xx_rng.c | 794 +- .../src/stm32f4xx_rtc.c | 5522 ++-- .../src/stm32f4xx_sai.c | 2158 +- .../src/stm32f4xx_sdio.c | 2022 +- .../src/stm32f4xx_spi.c | 2638 +- .../src/stm32f4xx_syscfg.c | 480 +- .../src/stm32f4xx_tim.c | 6730 ++--- .../src/stm32f4xx_usart.c | 2972 +-- .../src/stm32f4xx_wwdg.c | 614 +- .../Class/audio/inc/usbd_audio_core.h | 328 +- .../Class/audio/inc/usbd_audio_out_if.h | 250 +- .../Class/audio/src/usbd_audio_core.c | 1346 +- .../Class/audio/src/usbd_audio_out_if.c | 666 +- .../Class/cdc/inc/usbd_cdc_core.h | 282 +- .../Class/cdc/inc/usbd_cdc_if_template.h | 92 +- .../Class/cdc/src/usbd_cdc_core.c | 1676 +- .../Class/cdc/src/usbd_cdc_if_template.c | 414 +- .../Class/customhid/inc/usbd_customhid_core.h | 258 +- .../Class/customhid/src/usbd_customhid_core.c | 1436 +- .../Class/dfu/inc/usbd_dfu_core.h | 386 +- .../Class/dfu/inc/usbd_dfu_mal.h | 162 +- .../Class/dfu/inc/usbd_flash_if.h | 128 +- .../Class/dfu/inc/usbd_mem_if_template.h | 102 +- .../Class/dfu/inc/usbd_otp_if.h | 98 +- .../Class/dfu/src/usbd_dfu_core.c | 2104 +- .../Class/dfu/src/usbd_dfu_mal.c | 574 +- .../Class/dfu/src/usbd_flash_if.c | 454 +- .../Class/dfu/src/usbd_mem_if_template.c | 278 +- .../Class/dfu/src/usbd_otp_if.c | 252 +- .../Class/hid/inc/usbd_hid_core.h | 242 +- .../Class/hid/src/usbd_hid_core.c | 1038 +- .../inc/usbd_hid_cdc_wrapper.h | 192 +- .../src/usbd_hid_cdc_wrapper.c | 922 +- .../hid_msc_wrapper/inc/usbd_msc_hid_core.h | 200 +- .../hid_msc_wrapper/src/usbd_msc_hid_core.c | 756 +- .../Class/msc/inc/usbd_msc_bot.h | 306 +- .../Class/msc/inc/usbd_msc_core.h | 154 +- .../Class/msc/inc/usbd_msc_data.h | 208 +- .../Class/msc/inc/usbd_msc_mem.h | 224 +- .../Class/msc/inc/usbd_msc_scsi.h | 390 +- .../Class/msc/src/usbd_msc_bot.c | 804 +- .../Class/msc/src/usbd_msc_core.c | 994 +- .../Class/msc/src/usbd_msc_data.c | 268 +- .../Class/msc/src/usbd_msc_scsi.c | 1536 +- .../Core/inc/usbd_conf_template.h | 164 +- .../Core/inc/usbd_core.h | 240 +- .../Core/inc/usbd_def.h | 312 +- .../Core/inc/usbd_ioreq.h | 242 +- .../Core/inc/usbd_req.h | 216 +- .../Core/inc/usbd_usr.h | 282 +- .../Core/src/usbd_core.c | 1060 +- .../Core/src/usbd_ioreq.c | 488 +- .../Core/src/usbd_req.c | 1760 +- .../Release_Notes.html | 1940 +- .../STM32_USB_OTG_Driver/Release_Notes.html | 1900 +- .../STM32_USB_OTG_Driver/inc/usb_bsp.h | 216 +- .../inc/usb_conf_template.h | 612 +- .../STM32_USB_OTG_Driver/inc/usb_core.h | 822 +- .../STM32_USB_OTG_Driver/inc/usb_dcd.h | 328 +- .../STM32_USB_OTG_Driver/inc/usb_dcd_int.h | 256 +- .../STM32_USB_OTG_Driver/inc/usb_defines.h | 498 +- .../STM32_USB_OTG_Driver/inc/usb_hcd.h | 220 +- .../STM32_USB_OTG_Driver/inc/usb_hcd_int.h | 286 +- .../STM32_USB_OTG_Driver/inc/usb_otg.h | 198 +- .../STM32_USB_OTG_Driver/inc/usb_regs.h | 2378 +- .../STM32_USB_OTG_Driver/src/usb_core.c | 4464 ++-- .../STM32_USB_OTG_Driver/src/usb_dcd.c | 976 +- .../STM32_USB_OTG_Driver/src/usb_dcd_int.c | 1926 +- .../STM32_USB_OTG_Driver/src/usb_hcd.c | 550 +- .../STM32_USB_OTG_Driver/src/usb_hcd_int.c | 1716 +- .../STM32_USB_OTG_Driver/src/usb_otg.c | 836 +- radio/src/translations.h | 2152 +- radio/src/translations/tts_nl.cpp | 324 +- radio/util/maxvolume.cmd | 32 +- tools/eeprom_upgd_check/check.lua | 58 +- tools/eeprom_upgd_check/create.lua | 28 +- 397 files changed, 252824 insertions(+), 252713 deletions(-) diff --git a/.gitattributes b/.gitattributes index 50ca329f2..bbdbb3b93 100644 --- a/.gitattributes +++ b/.gitattributes @@ -1 +1,112 @@ +# Handle line endings automatically for files detected as text +# and leave all files detected as binary untouched. +* text=auto + +# +# The above will handle all files NOT found below +# +# These files are text and should be normalized (Convert crlf => lf) + +# Source files +*.c text +*.cc text +*.cxx text +*.cpp text +*.c++ text +*.hpp text +*.h text +*.h++ text +*.hh text +*.lua text +*.pxd text +*.py text +*.py3 text +*.pyw text +*.pyx text +*.pl text +*.pm text +*.sln text eol=crlf +*.csproj text eol=crlf +*.vbproj text eol=crlf +*.vcxproj text eol=crlf +*.vcproj text eol=crlf +*.dbproj text eol=crlf +*.fsproj text eol=crlf +*.lsproj text eol=crlf +*.wixproj text eol=crlf +*.modelproj text eol=crlf +*.sqlproj text eol=crlf +*.wmaproj text eol=crlf +*.xproj text eol=crlf +*.props text eol=crlf +*.filters text eol=crlf +*.vcxitems text eol=crlf *.sh eol=lf + +# Compiled Object files +*.slo binary +*.lo binary +*.o binary +*.obj binary + +# Precompiled Headers +*.gch binary +*.pch binary + +# Compiled Dynamic libraries +*.so binary +*.dylib binary +*.dll binary + +# Compiled Static libraries +*.lai binary +*.la binary +*.a binary +*.lib binary + +# Executables +*.exe binary +*.out binary +*.app binary + +# Binary files +*.db binary +*.p binary +*.pkl binary +*.pyc binary +*.pyd binary +*.pyo binary + +# Documents +*.doc diff=astextplain +*.DOC diff=astextplain +*.docx diff=astextplain +*.DOCX diff=astextplain +*.dot diff=astextplain +*.DOT diff=astextplain +*.pdf diff=astextplain +*.PDF diff=astextplain +*.rtf diff=astextplain +*.RTF diff=astextplain +*.md text +*.adoc text +*.textile text +*.mustache text +*.csv text +*.tab text +*.tsv text +*.sql text + +# Graphics +*.png binary +*.jpg binary +*.jpeg binary +*.gif binary +*.tif binary +*.tiff binary +*.ico binary +# SVG treated as an asset (binary) by default. If you want to treat it as text, +# comment-out the following line and uncomment the line after. +*.svg binary +#*.svg text +*.eps binary diff --git a/cmake/FindXercesC.cmake b/cmake/FindXercesC.cmake index cb28a49d9..4431cbdf5 100644 --- a/cmake/FindXercesC.cmake +++ b/cmake/FindXercesC.cmake @@ -1,68 +1,68 @@ -# Find Xerces-C -# The following setings are defined -# XERCESC_ROOT_DIR, the root of the include and lib directory -# XERCESC_INCLUDE_DIR, the full path of the include dir (ADVANCED) -# XERCESC_LIBRARIES, the name of the xerces-c library (ADVANCED) - -# Look for a root installation -IF( MSVC ) -SET( XERCES_WINDIR C:/Programs/xerces-vc ) -ELSE( ) -SET( XERCES_WINDIR C:/Programs/xerces ) -ENDIF( ) - -FIND_PATH(XERCESC_ROOT_DIR include/xercesc/parsers/SAXParser.hpp - ${XERCES_WINDIR} - "C:/mingw/msys/1.0/local" - "C:/Program Files/CodeSynthesis XSD 3.2" - /usr - /usr/local - "C:/MinGW" - $ENV{CODESYNTH} - DOC "The root of an installed xerces-c installation" -) - -# try to find the header -FIND_PATH(XERCESC_INCLUDE_DIR xercesc/parsers/SAXParser.hpp - ${XERCESC_ROOT_DIR}/include - /usr/include - /usr/local/include -) - -# Find the library -FIND_LIBRARY(XERCESC_LIBRARY - NAMES xerces-c xerces-c_3 - PATHS - ${XERCESC_ROOT_DIR}/lib - ${XERCESC_ROOT_DIR}/lib/vc-9.0 - ${XERCESC_ROOT_DIR}/lib64/vc-9.0 - /usr/lib - /usr/local/lib - DOC "The name of the xerces-c library" -) - -IF (XERCESC_ROOT_DIR) - IF (XERCESC_INCLUDE_DIR AND XERCESC_LIBRARY) - SET (XERCESC_FOUND TRUE) - SET (XERCESC_LIBRARIES "${XERCESC_LIBRARY}") - # FIXME: There should be a better way of handling this? - # FIXME: How can we test to see if the lib dir isn't - # FIXME: one of the default dirs? - LINK_DIRECTORIES(${XERCESC_ROOT_DIR}/lib) - ENDIF (XERCESC_INCLUDE_DIR AND XERCESC_LIBRARY) -ENDIF (XERCESC_ROOT_DIR) - -IF (XERCESC_FOUND) - IF (NOT XERCESC_FIND_QUIETLY) - MESSAGE (STATUS " found xerces-c: ${XERCESC_LIBRARY}") - ENDIF (NOT XERCESC_FIND_QUIETLY) -ELSE (XERCESC_FOUND) - IF (XERCESC_FIND_REQUIRED) - MESSAGE(FATAL_ERROR "Could not find Xerces-C") - ENDIF (XERCESC_FIND_REQUIRED) -ENDIF (XERCESC_FOUND) - -MARK_AS_ADVANCED( - XERCESC_INCLUDE_DIR - XERCESC_LIBRARY +# Find Xerces-C +# The following setings are defined +# XERCESC_ROOT_DIR, the root of the include and lib directory +# XERCESC_INCLUDE_DIR, the full path of the include dir (ADVANCED) +# XERCESC_LIBRARIES, the name of the xerces-c library (ADVANCED) + +# Look for a root installation +IF( MSVC ) +SET( XERCES_WINDIR C:/Programs/xerces-vc ) +ELSE( ) +SET( XERCES_WINDIR C:/Programs/xerces ) +ENDIF( ) + +FIND_PATH(XERCESC_ROOT_DIR include/xercesc/parsers/SAXParser.hpp + ${XERCES_WINDIR} + "C:/mingw/msys/1.0/local" + "C:/Program Files/CodeSynthesis XSD 3.2" + /usr + /usr/local + "C:/MinGW" + $ENV{CODESYNTH} + DOC "The root of an installed xerces-c installation" +) + +# try to find the header +FIND_PATH(XERCESC_INCLUDE_DIR xercesc/parsers/SAXParser.hpp + ${XERCESC_ROOT_DIR}/include + /usr/include + /usr/local/include +) + +# Find the library +FIND_LIBRARY(XERCESC_LIBRARY + NAMES xerces-c xerces-c_3 + PATHS + ${XERCESC_ROOT_DIR}/lib + ${XERCESC_ROOT_DIR}/lib/vc-9.0 + ${XERCESC_ROOT_DIR}/lib64/vc-9.0 + /usr/lib + /usr/local/lib + DOC "The name of the xerces-c library" +) + +IF (XERCESC_ROOT_DIR) + IF (XERCESC_INCLUDE_DIR AND XERCESC_LIBRARY) + SET (XERCESC_FOUND TRUE) + SET (XERCESC_LIBRARIES "${XERCESC_LIBRARY}") + # FIXME: There should be a better way of handling this? + # FIXME: How can we test to see if the lib dir isn't + # FIXME: one of the default dirs? + LINK_DIRECTORIES(${XERCESC_ROOT_DIR}/lib) + ENDIF (XERCESC_INCLUDE_DIR AND XERCESC_LIBRARY) +ENDIF (XERCESC_ROOT_DIR) + +IF (XERCESC_FOUND) + IF (NOT XERCESC_FIND_QUIETLY) + MESSAGE (STATUS " found xerces-c: ${XERCESC_LIBRARY}") + ENDIF (NOT XERCESC_FIND_QUIETLY) +ELSE (XERCESC_FOUND) + IF (XERCESC_FIND_REQUIRED) + MESSAGE(FATAL_ERROR "Could not find Xerces-C") + ENDIF (XERCESC_FIND_REQUIRED) +ENDIF (XERCESC_FOUND) + +MARK_AS_ADVANCED( + XERCESC_INCLUDE_DIR + XERCESC_LIBRARY ) \ No newline at end of file diff --git a/companion/src/icon.rc b/companion/src/icon.rc index 46a5a428b..8f9d9ca03 100644 --- a/companion/src/icon.rc +++ b/companion/src/icon.rc @@ -1 +1 @@ -IDI_ICON1 ICON DISCARDABLE "icon.ico" +IDI_ICON1 ICON DISCARDABLE "icon.ico" diff --git a/companion/targets/windows/FileAssociation.nsh b/companion/targets/windows/FileAssociation.nsh index 157257f1b..b8c1e5ee7 100644 --- a/companion/targets/windows/FileAssociation.nsh +++ b/companion/targets/windows/FileAssociation.nsh @@ -1,190 +1,190 @@ -/* -_____________________________________________________________________________ - - File Association -_____________________________________________________________________________ - - Based on code taken from http://nsis.sourceforge.net/File_Association - - Usage in script: - 1. !include "FileAssociation.nsh" - 2. [Section|Function] - ${FileAssociationFunction} "Param1" "Param2" "..." $var - [SectionEnd|FunctionEnd] - - FileAssociationFunction=[RegisterExtension|UnRegisterExtension] - -_____________________________________________________________________________ - - ${RegisterExtension} "[executable]" "[extension]" "[description]" - -"[executable]" ; executable which opens the file format - ; -"[extension]" ; extension, which represents the file format to open - ; -"[description]" ; description for the extension. This will be display in Windows Explorer. - ; - - - ${UnRegisterExtension} "[extension]" "[description]" - -"[extension]" ; extension, which represents the file format to open - ; -"[description]" ; description for the extension. This will be display in Windows Explorer. - ; - -_____________________________________________________________________________ - - Macros -_____________________________________________________________________________ - - Change log window verbosity (default: 3=no script) - - Example: - !include "FileAssociation.nsh" - !insertmacro RegisterExtension - ${FileAssociation_VERBOSE} 4 # all verbosity - !insertmacro UnRegisterExtension - ${FileAssociation_VERBOSE} 3 # no script -*/ - - -!ifndef FileAssociation_INCLUDED -!define FileAssociation_INCLUDED - -!include Util.nsh - -!verbose push -!verbose 3 -!ifndef _FileAssociation_VERBOSE - !define _FileAssociation_VERBOSE 3 -!endif -!verbose ${_FileAssociation_VERBOSE} -!define FileAssociation_VERBOSE `!insertmacro FileAssociation_VERBOSE` -!verbose pop - -!macro FileAssociation_VERBOSE _VERBOSE - !verbose push - !verbose 3 - !undef _FileAssociation_VERBOSE - !define _FileAssociation_VERBOSE ${_VERBOSE} - !verbose pop -!macroend - - - -!macro RegisterExtensionCall _EXECUTABLE _EXTENSION _DESCRIPTION - !verbose push - !verbose ${_FileAssociation_VERBOSE} - Push `${_DESCRIPTION}` - Push `${_EXTENSION}` - Push `${_EXECUTABLE}` - ${CallArtificialFunction} RegisterExtension_ - !verbose pop -!macroend - -!macro UnRegisterExtensionCall _EXTENSION _DESCRIPTION - !verbose push - !verbose ${_FileAssociation_VERBOSE} - Push `${_EXTENSION}` - Push `${_DESCRIPTION}` - ${CallArtificialFunction} UnRegisterExtension_ - !verbose pop -!macroend - - - -!define RegisterExtension `!insertmacro RegisterExtensionCall` -!define un.RegisterExtension `!insertmacro RegisterExtensionCall` - -!macro RegisterExtension -!macroend - -!macro un.RegisterExtension -!macroend - -!macro RegisterExtension_ - !verbose push - !verbose ${_FileAssociation_VERBOSE} - - Exch $R2 ;exe - Exch - Exch $R1 ;ext - Exch - Exch 2 - Exch $R0 ;desc - Exch 2 - Push $0 - Push $1 - - ReadRegStr $1 HKCR $R1 "" ; read current file association - StrCmp "$1" "" NoBackup ; is it empty - StrCmp "$1" "$R0" NoBackup ; is it our own - WriteRegStr HKCR $R1 "backup_val" "$1" ; backup current value -NoBackup: - WriteRegStr HKCR $R1 "" "$R0" ; set our file association - - ReadRegStr $0 HKCR $R0 "" - StrCmp $0 "" 0 Skip - WriteRegStr HKCR "$R0" "" "$R0" - WriteRegStr HKCR "$R0\shell" "" "open" - WriteRegStr HKCR "$R0\DefaultIcon" "" "$R2,0" -Skip: - WriteRegStr HKCR "$R0\shell\open\command" "" '"$R2" "%1"' - WriteRegStr HKCR "$R0\shell\edit" "" "Edit $R0" - WriteRegStr HKCR "$R0\shell\edit\command" "" '"$R2" "%1"' - - Pop $1 - Pop $0 - Pop $R2 - Pop $R1 - Pop $R0 - - !verbose pop -!macroend - - - -!define UnRegisterExtension `!insertmacro UnRegisterExtensionCall` -!define un.UnRegisterExtension `!insertmacro UnRegisterExtensionCall` - -!macro UnRegisterExtension -!macroend - -!macro un.UnRegisterExtension -!macroend - -!macro UnRegisterExtension_ - !verbose push - !verbose ${_FileAssociation_VERBOSE} - - Exch $R1 ;desc - Exch - Exch $R0 ;ext - Exch - Push $0 - Push $1 - - ReadRegStr $1 HKCR $R0 "" - StrCmp $1 $R1 0 NoOwn ; only do this if we own it - ReadRegStr $1 HKCR $R0 "backup_val" - StrCmp $1 "" 0 Restore ; if backup="" then delete the whole key - DeleteRegKey HKCR $R0 - Goto NoOwn - -Restore: - WriteRegStr HKCR $R0 "" $1 - DeleteRegValue HKCR $R0 "backup_val" - DeleteRegKey HKCR $R1 ;Delete key with association name settings - -NoOwn: - - Pop $1 - Pop $0 - Pop $R1 - Pop $R0 - - !verbose pop -!macroend - +/* +_____________________________________________________________________________ + + File Association +_____________________________________________________________________________ + + Based on code taken from http://nsis.sourceforge.net/File_Association + + Usage in script: + 1. !include "FileAssociation.nsh" + 2. [Section|Function] + ${FileAssociationFunction} "Param1" "Param2" "..." $var + [SectionEnd|FunctionEnd] + + FileAssociationFunction=[RegisterExtension|UnRegisterExtension] + +_____________________________________________________________________________ + + ${RegisterExtension} "[executable]" "[extension]" "[description]" + +"[executable]" ; executable which opens the file format + ; +"[extension]" ; extension, which represents the file format to open + ; +"[description]" ; description for the extension. This will be display in Windows Explorer. + ; + + + ${UnRegisterExtension} "[extension]" "[description]" + +"[extension]" ; extension, which represents the file format to open + ; +"[description]" ; description for the extension. This will be display in Windows Explorer. + ; + +_____________________________________________________________________________ + + Macros +_____________________________________________________________________________ + + Change log window verbosity (default: 3=no script) + + Example: + !include "FileAssociation.nsh" + !insertmacro RegisterExtension + ${FileAssociation_VERBOSE} 4 # all verbosity + !insertmacro UnRegisterExtension + ${FileAssociation_VERBOSE} 3 # no script +*/ + + +!ifndef FileAssociation_INCLUDED +!define FileAssociation_INCLUDED + +!include Util.nsh + +!verbose push +!verbose 3 +!ifndef _FileAssociation_VERBOSE + !define _FileAssociation_VERBOSE 3 +!endif +!verbose ${_FileAssociation_VERBOSE} +!define FileAssociation_VERBOSE `!insertmacro FileAssociation_VERBOSE` +!verbose pop + +!macro FileAssociation_VERBOSE _VERBOSE + !verbose push + !verbose 3 + !undef _FileAssociation_VERBOSE + !define _FileAssociation_VERBOSE ${_VERBOSE} + !verbose pop +!macroend + + + +!macro RegisterExtensionCall _EXECUTABLE _EXTENSION _DESCRIPTION + !verbose push + !verbose ${_FileAssociation_VERBOSE} + Push `${_DESCRIPTION}` + Push `${_EXTENSION}` + Push `${_EXECUTABLE}` + ${CallArtificialFunction} RegisterExtension_ + !verbose pop +!macroend + +!macro UnRegisterExtensionCall _EXTENSION _DESCRIPTION + !verbose push + !verbose ${_FileAssociation_VERBOSE} + Push `${_EXTENSION}` + Push `${_DESCRIPTION}` + ${CallArtificialFunction} UnRegisterExtension_ + !verbose pop +!macroend + + + +!define RegisterExtension `!insertmacro RegisterExtensionCall` +!define un.RegisterExtension `!insertmacro RegisterExtensionCall` + +!macro RegisterExtension +!macroend + +!macro un.RegisterExtension +!macroend + +!macro RegisterExtension_ + !verbose push + !verbose ${_FileAssociation_VERBOSE} + + Exch $R2 ;exe + Exch + Exch $R1 ;ext + Exch + Exch 2 + Exch $R0 ;desc + Exch 2 + Push $0 + Push $1 + + ReadRegStr $1 HKCR $R1 "" ; read current file association + StrCmp "$1" "" NoBackup ; is it empty + StrCmp "$1" "$R0" NoBackup ; is it our own + WriteRegStr HKCR $R1 "backup_val" "$1" ; backup current value +NoBackup: + WriteRegStr HKCR $R1 "" "$R0" ; set our file association + + ReadRegStr $0 HKCR $R0 "" + StrCmp $0 "" 0 Skip + WriteRegStr HKCR "$R0" "" "$R0" + WriteRegStr HKCR "$R0\shell" "" "open" + WriteRegStr HKCR "$R0\DefaultIcon" "" "$R2,0" +Skip: + WriteRegStr HKCR "$R0\shell\open\command" "" '"$R2" "%1"' + WriteRegStr HKCR "$R0\shell\edit" "" "Edit $R0" + WriteRegStr HKCR "$R0\shell\edit\command" "" '"$R2" "%1"' + + Pop $1 + Pop $0 + Pop $R2 + Pop $R1 + Pop $R0 + + !verbose pop +!macroend + + + +!define UnRegisterExtension `!insertmacro UnRegisterExtensionCall` +!define un.UnRegisterExtension `!insertmacro UnRegisterExtensionCall` + +!macro UnRegisterExtension +!macroend + +!macro un.UnRegisterExtension +!macroend + +!macro UnRegisterExtension_ + !verbose push + !verbose ${_FileAssociation_VERBOSE} + + Exch $R1 ;desc + Exch + Exch $R0 ;ext + Exch + Push $0 + Push $1 + + ReadRegStr $1 HKCR $R0 "" + StrCmp $1 $R1 0 NoOwn ; only do this if we own it + ReadRegStr $1 HKCR $R0 "backup_val" + StrCmp $1 "" 0 Restore ; if backup="" then delete the whole key + DeleteRegKey HKCR $R0 + Goto NoOwn + +Restore: + WriteRegStr HKCR $R0 "" $1 + DeleteRegValue HKCR $R0 "backup_val" + DeleteRegKey HKCR $R1 ;Delete key with association name settings + +NoOwn: + + Pop $1 + Pop $0 + Pop $R1 + Pop $R0 + + !verbose pop +!macroend + !endif # !FileAssociation_INCLUDED \ No newline at end of file diff --git a/companion/targets/windows/license.txt b/companion/targets/windows/license.txt index 99729ba2f..492d4a82a 100644 --- a/companion/targets/windows/license.txt +++ b/companion/targets/windows/license.txt @@ -1,12 +1,12 @@ -Copyright 2011-2016 OpenTX team - -OpenTX Companion is based on code named eePe by author - Erez Raviv - -This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software. - -Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions: - -1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software. - If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required. -2. Altered versions must be plainly marked as such, and must not be misrepresented as being the original software. +Copyright 2011-2016 OpenTX team + +OpenTX Companion is based on code named eePe by author - Erez Raviv + +This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software. + +Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions: + +1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software. + If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required. +2. Altered versions must be plainly marked as such, and must not be misrepresented as being the original software. 3. This notice may not be removed or altered from any distribution. \ No newline at end of file diff --git a/radio/sdcard/horus/S6R/S6R.lua b/radio/sdcard/horus/S6R/S6R.lua index 16d2a4d35..2f3b07566 100755 --- a/radio/sdcard/horus/S6R/S6R.lua +++ b/radio/sdcard/horus/S6R/S6R.lua @@ -1,340 +1,340 @@ -local VALUE = 0 -local COMBO = 1 - -local COLUMN_2 = 300 - -local edit = false -local page = 1 -local current = 1 -local refreshState = 0 -local refreshIndex = 0 -local calibrationState = 0 -local pageOffset = 0 -local calibrationStep = 0 -local pages = {} -local fields = {} -local modifications = {} -local wingBitmaps = {} -local mountBitmaps = {} -local calibBitmaps = {} - -local configFields = { - {"Wing type:", COMBO, 0x80, nil, { "Normal", "Delta", "VTail" } }, - {"Mounting type:", COMBO, 0x81, nil, { "Horz", "Horz rev.", "Vert", "Vert rev." } }, -} -local calibrationPositions = { "up", "down", "left", "right", "forward", "back" } -local wingBitmapsFile = {"img/plane_b.png", "img/delta_b.png", "img/planev_b.png"} -local mountBitmapsFile = {"img/up.png", "img/down.png", "img/vert.png", "img/vert-r.png"} -local calibBitmapsFile = {"img/up.png", "img/down.png", "img/left.png", "img/right.png", "img/forward.png", "img/back.png"} - -local settingsFields = { - {"S6R functions:", COMBO, 0x9C, nil, { "Disable", "Enable" } }, - {"CH5 mode:", COMBO, 0xA8, nil, { "AIL2", "AUX1" } }, - {"CH6 mode:", COMBO, 0xA9, nil, { "ELE2", "AUX2" } }, - {"AIL direction:", COMBO, 0x82, nil, { "Normal", "Invers" }, { 255, 0 } }, - {"ELE direction:", COMBO, 0x83, nil, { "Normal", "Invers" }, { 255, 0 } }, - {"RUD direction:", COMBO, 0x84, nil, { "Normal", "Invers" }, { 255, 0 } }, - {"AIL2 direction:", COMBO, 0x9A, nil, { "Normal", "Invers" }, { 255, 0 } }, - {"ELE2 direction:", COMBO, 0x9B, nil, { "Normal", "Invers" }, { 255, 0 } }, - {"AIL stabilize gain:", VALUE, 0x85, nil, 0, 200, "%"}, - {"ELE stabilize gain:", VALUE, 0x86, nil, 0, 200, "%"}, - {"RUD stabilize gain:", VALUE, 0x87, nil, 0, 200, "%"}, - {"AIL auto level gain:", VALUE, 0x88, nil, 0, 200, "%"}, - {"ELE auto level gain:", VALUE, 0x89, nil, 0, 200, "%"}, - {"ELE upright gain:", VALUE, 0x8C, nil, 0, 200, "%"}, - {"RUD upright gain:", VALUE, 0x8D, nil, 0, 200, "%"}, - {"AIL crab gain:", VALUE, 0x8E, nil, 0, 200, "%"}, - {"RUD crab gain:", VALUE, 0x90, nil, 0, 200, "%"}, - {"AIL auto angle offset:", VALUE, 0x91, nil, -20, 20, "%", 0x6C}, - {"ELE auto angle offset:", VALUE, 0x92, nil, -20, 20, "%", 0x6C}, - {"ELE upright angle offset:", VALUE, 0x95, nil, -20, 20, "%", 0x6C}, - {"RUD upright angle offset:", VALUE, 0x96, nil, -20, 20, "%", 0x6C}, - {"AIL crab angle offset:", VALUE, 0x97, nil, -20, 20, "%", 0x6C}, - {"RUD crab angle offset:", VALUE, 0x99, nil, -20, 20, "%", 0x6C}, -} - -local calibrationFields = { - {"X:", VALUE, 0x9E, 0, -100, 100, "%"}, - {"Y:", VALUE, 0x9F, 0, -100, 100, "%"}, - {"Z:", VALUE, 0xA0, 0, -100, 100, "%"} -} - -local function drawScreenTitle(title,page, pages) - lcd.drawFilledRectangle(0, 0, LCD_W, 30, TITLE_BGCOLOR) - lcd.drawText(1, 5, title, MENU_TITLE_COLOR) - lcd.drawText(LCD_W-40, 5, page.."/"..pages, MENU_TITLE_COLOR) -end - --- Change display attribute to current field -local function addField(step) - local field = fields[current] - local min, max - if field[2] == VALUE then - min = field[5] - max = field[6] - elseif field[2] == COMBO then - min = 0 - max = #(field[5]) - 1 - end - if (step < 0 and field[4] > min) or (step > 0 and field[4] < max) then - field[4] = field[4] + step - end -end - --- Select the next or previous page -local function selectPage(step) - page = 1 + ((page + step - 1 + #pages) % #pages) - refreshIndex = 0 - calibrationStep = 0 - pageOffset = 0 -end - --- Select the next or previous editable field -local function selectField(step) - current = 1 + ((current + step - 1 + #fields) % #fields) - if current > 7 + pageOffset then - pageOffset = current - 7 - elseif current <= pageOffset then - pageOffset = current - 1 - end -end - -local function drawProgressBar() - local width = (300 * refreshIndex) / #fields - lcd.drawRectangle(100, 10, 300, 6) - lcd.drawFilledRectangle(102, 13, width, 2); -end - --- Redraw the current page -local function redrawFieldsPage(event) - lcd.clear() - drawScreenTitle("S6R", page, #pages) - - if refreshIndex < #fields then - drawProgressBar() - end - - for index = 1, 10, 1 do - local field = fields[pageOffset+index] - if field == nil then - break - end - - local attr = current == (pageOffset+index) and ((edit == true and BLINK or 0) + INVERS) or 0 - attr = attr + TEXT_COLOR - - lcd.drawText(1, 30+20*index, field[1], TEXT_COLOR) - - if field[4] == nil then - lcd.drawText(COLUMN_2, 30+20*index, "---", attr) - else - if field[2] == VALUE then - lcd.drawNumber(COLUMN_2, 30+20*index, field[4], LEFT + attr) - elseif field[2] == COMBO then - if field[4] >= 0 and field[4] < #(field[5]) then - lcd.drawText(COLUMN_2, 30+20*index, field[5][1+field[4]], attr) - end - end - end - end -end - -local function telemetryRead(field) - return sportTelemetryPush(0x17, 0x30, 0x0C30, field) -end - -local function telemetryWrite(field, value) - return sportTelemetryPush(0x17, 0x31, 0x0C30, field + value*256) -end - -local telemetryPopTimeout = 0 -local function refreshNext() - if refreshState == 0 then - if calibrationState == 1 then - if telemetryWrite(0x9D, calibrationStep) == true then - refreshState = 1 - calibrationState = 2 - telemetryPopTimeout = getTime() + 80 -- normal delay is 500ms - end - elseif #modifications > 0 then - telemetryWrite(modifications[1][1], modifications[1][2]) - modifications[1] = nil - elseif refreshIndex < #fields then - local field = fields[refreshIndex + 1] - if telemetryRead(field[3]) == true then - refreshState = 1 - telemetryPopTimeout = getTime() + 80 -- normal delay is 500ms - end - end - elseif refreshState == 1 then - local physicalId, primId, dataId, value = sportTelemetryPop() - if physicalId == 0x1A and primId == 0x32 and dataId == 0x0C30 then - local fieldId = value % 256 - if calibrationState == 2 then - if fieldId == 0x9D then - refreshState = 0 - calibrationState = 0 - calibrationStep = (calibrationStep + 1) % 7 - end - else - local field = fields[refreshIndex + 1] - if fieldId == field[3] then - local value = math.floor(value / 256) - if field[3] >= 0x9E and field[3] <= 0xA0 then - local b1 = value % 256 - local b2 = math.floor(value / 256) - value = b1*256 + b2 - value = value - bit32.band(value, 0x8000) * 2 - end - if field[2] == COMBO and #field == 6 then - for index = 1, #(field[6]), 1 do - if value == field[6][index] then - value = index - 1 - break - end - end - elseif field[2] == VALUE and #field == 8 then - value = value - field[8] + field[5] - end - fields[refreshIndex + 1][4] = value - refreshIndex = refreshIndex + 1 - refreshState = 0 - end - end - elseif getTime() > telemetryPopTimeout then - refreshState = 0 - calibrationState = 0 - end - end -end - -local function updateField(field) - local value = field[4] - if field[2] == COMBO and #field == 6 then - value = field[6][1+value] - elseif field[2] == VALUE and #field == 8 then - value = value + field[8] - field[5] - end - modifications[#modifications+1] = { field[3], value } -end - --- Main -local function runFieldsPage(event) - if event == EVT_EXIT_BREAK then -- exit script - return 2 - elseif event == EVT_ENTER_BREAK or event == EVT_ROT_BREAK then -- toggle editing/selecting current field - if fields[current][4] ~= nil then - edit = not edit - if edit == false then - updateField(fields[current]) - end - end - elseif edit then - if event == EVT_PLUS_FIRST or event == EVT_ROT_RIGHT or event == EVT_PLUS_REPT then - addField(1) - elseif event == EVT_MINUS_FIRST or event == EVT_ROT_LEFT or event == EVT_MINUS_REPT then - addField(-1) - end - else - if event == EVT_MINUS_FIRST or event == EVT_ROT_RIGHT then - selectField(1) - elseif event == EVT_PLUS_FIRST or event == EVT_ROT_LEFT then - selectField(-1) - end - end - redrawFieldsPage(event) - return 0 -end - -local function runConfigPage(event) - fields = configFields - local result = runFieldsPage(event) - if fields[1][4] ~= nil then - if wingBitmaps[1 + fields[1][4]] == nil then - wingBitmaps[1 + fields[1][4]] = Bitmap.open(wingBitmapsFile[1 + fields[1][4]]) - end - lcd.drawBitmap(wingBitmaps[1 + fields[1][4]], 10, 90) - end - if fields[2][4] ~= nil then - if mountBitmaps[1 + fields[2][4]] == nil then - mountBitmaps[1 + fields[2][4]] = Bitmap.open(mountBitmapsFile[1 + fields[2][4]]) - end - lcd.drawBitmap(mountBitmaps[1 + fields[2][4]], 190, 110) - end - return result -end - -local function runSettingsPage(event) - fields = settingsFields - return runFieldsPage(event) -end - -local function runCalibrationPage(event) - fields = calibrationFields - if refreshIndex == #fields then - refreshIndex = 0 - end - lcd.clear() - drawScreenTitle("S6R", page, #pages) - if(calibrationStep < 6) then - local position = calibrationPositions[1 + calibrationStep] - lcd.drawText(100, 50, "Place the S6R in the following position", TEXT_COLOR) - if calibBitmaps[calibrationStep + 1] == nil then - calibBitmaps[calibrationStep + 1] = Bitmap.open(calibBitmapsFile[calibrationStep + 1]) - end - lcd.drawBitmap(calibBitmaps[calibrationStep + 1], 200, 70) - for index = 1, 3, 1 do - local field = fields[index] - lcd.drawText(70, 80+20*index, field[1]..":", TEXT_COLOR) - lcd.drawNumber(90, 80+20*index, field[4]/10, LEFT+PREC2) - end - - local attr = calibrationState == 0 and INVERS or 0 - lcd.drawText(160, 220, "Press [Enter] when ready", attr) - else - lcd.drawText(160, 50, "Calibration completed", 0) - lcd.drawBitmap(Bitmap.open("img/done.bmp"),200, 100) - lcd.drawText(160, 220, "Press [RTN] when ready", attr) - end - if calibrationStep > 6 and (event == EVT_ENTER_BREAK or event == EVT_EXIT_BREAK) then - return 2 - elseif event == EVT_ENTER_BREAK then - calibrationState = 1 - elseif event == EVT_EXIT_BREAK then - if calibrationStep > 0 then - calibrationStep = 0 - end - end - return 0 - -end - --- Init -local function init() - current, edit, refreshState, refreshIndex = 1, false, 0, 0 - pages = { - runConfigPage, - runSettingsPage, - runCalibrationPage - } -end - --- Main -local function run(event) - if event == nil then - error("Cannot be run as a model script!") - return 2 - elseif event == EVT_PAGE_BREAK or event == EVT_PAGEDN_FIRST then - selectPage(1) - elseif event == EVT_PAGE_LONG or event == EVT_PAGEUP_FIRST then - killEvents(event); - selectPage(-1) - end - - local result = pages[page](event) - refreshNext() - - return result -end - -return { init=init, run=run } +local VALUE = 0 +local COMBO = 1 + +local COLUMN_2 = 300 + +local edit = false +local page = 1 +local current = 1 +local refreshState = 0 +local refreshIndex = 0 +local calibrationState = 0 +local pageOffset = 0 +local calibrationStep = 0 +local pages = {} +local fields = {} +local modifications = {} +local wingBitmaps = {} +local mountBitmaps = {} +local calibBitmaps = {} + +local configFields = { + {"Wing type:", COMBO, 0x80, nil, { "Normal", "Delta", "VTail" } }, + {"Mounting type:", COMBO, 0x81, nil, { "Horz", "Horz rev.", "Vert", "Vert rev." } }, +} +local calibrationPositions = { "up", "down", "left", "right", "forward", "back" } +local wingBitmapsFile = {"img/plane_b.png", "img/delta_b.png", "img/planev_b.png"} +local mountBitmapsFile = {"img/up.png", "img/down.png", "img/vert.png", "img/vert-r.png"} +local calibBitmapsFile = {"img/up.png", "img/down.png", "img/left.png", "img/right.png", "img/forward.png", "img/back.png"} + +local settingsFields = { + {"S6R functions:", COMBO, 0x9C, nil, { "Disable", "Enable" } }, + {"CH5 mode:", COMBO, 0xA8, nil, { "AIL2", "AUX1" } }, + {"CH6 mode:", COMBO, 0xA9, nil, { "ELE2", "AUX2" } }, + {"AIL direction:", COMBO, 0x82, nil, { "Normal", "Invers" }, { 255, 0 } }, + {"ELE direction:", COMBO, 0x83, nil, { "Normal", "Invers" }, { 255, 0 } }, + {"RUD direction:", COMBO, 0x84, nil, { "Normal", "Invers" }, { 255, 0 } }, + {"AIL2 direction:", COMBO, 0x9A, nil, { "Normal", "Invers" }, { 255, 0 } }, + {"ELE2 direction:", COMBO, 0x9B, nil, { "Normal", "Invers" }, { 255, 0 } }, + {"AIL stabilize gain:", VALUE, 0x85, nil, 0, 200, "%"}, + {"ELE stabilize gain:", VALUE, 0x86, nil, 0, 200, "%"}, + {"RUD stabilize gain:", VALUE, 0x87, nil, 0, 200, "%"}, + {"AIL auto level gain:", VALUE, 0x88, nil, 0, 200, "%"}, + {"ELE auto level gain:", VALUE, 0x89, nil, 0, 200, "%"}, + {"ELE upright gain:", VALUE, 0x8C, nil, 0, 200, "%"}, + {"RUD upright gain:", VALUE, 0x8D, nil, 0, 200, "%"}, + {"AIL crab gain:", VALUE, 0x8E, nil, 0, 200, "%"}, + {"RUD crab gain:", VALUE, 0x90, nil, 0, 200, "%"}, + {"AIL auto angle offset:", VALUE, 0x91, nil, -20, 20, "%", 0x6C}, + {"ELE auto angle offset:", VALUE, 0x92, nil, -20, 20, "%", 0x6C}, + {"ELE upright angle offset:", VALUE, 0x95, nil, -20, 20, "%", 0x6C}, + {"RUD upright angle offset:", VALUE, 0x96, nil, -20, 20, "%", 0x6C}, + {"AIL crab angle offset:", VALUE, 0x97, nil, -20, 20, "%", 0x6C}, + {"RUD crab angle offset:", VALUE, 0x99, nil, -20, 20, "%", 0x6C}, +} + +local calibrationFields = { + {"X:", VALUE, 0x9E, 0, -100, 100, "%"}, + {"Y:", VALUE, 0x9F, 0, -100, 100, "%"}, + {"Z:", VALUE, 0xA0, 0, -100, 100, "%"} +} + +local function drawScreenTitle(title,page, pages) + lcd.drawFilledRectangle(0, 0, LCD_W, 30, TITLE_BGCOLOR) + lcd.drawText(1, 5, title, MENU_TITLE_COLOR) + lcd.drawText(LCD_W-40, 5, page.."/"..pages, MENU_TITLE_COLOR) +end + +-- Change display attribute to current field +local function addField(step) + local field = fields[current] + local min, max + if field[2] == VALUE then + min = field[5] + max = field[6] + elseif field[2] == COMBO then + min = 0 + max = #(field[5]) - 1 + end + if (step < 0 and field[4] > min) or (step > 0 and field[4] < max) then + field[4] = field[4] + step + end +end + +-- Select the next or previous page +local function selectPage(step) + page = 1 + ((page + step - 1 + #pages) % #pages) + refreshIndex = 0 + calibrationStep = 0 + pageOffset = 0 +end + +-- Select the next or previous editable field +local function selectField(step) + current = 1 + ((current + step - 1 + #fields) % #fields) + if current > 7 + pageOffset then + pageOffset = current - 7 + elseif current <= pageOffset then + pageOffset = current - 1 + end +end + +local function drawProgressBar() + local width = (300 * refreshIndex) / #fields + lcd.drawRectangle(100, 10, 300, 6) + lcd.drawFilledRectangle(102, 13, width, 2); +end + +-- Redraw the current page +local function redrawFieldsPage(event) + lcd.clear() + drawScreenTitle("S6R", page, #pages) + + if refreshIndex < #fields then + drawProgressBar() + end + + for index = 1, 10, 1 do + local field = fields[pageOffset+index] + if field == nil then + break + end + + local attr = current == (pageOffset+index) and ((edit == true and BLINK or 0) + INVERS) or 0 + attr = attr + TEXT_COLOR + + lcd.drawText(1, 30+20*index, field[1], TEXT_COLOR) + + if field[4] == nil then + lcd.drawText(COLUMN_2, 30+20*index, "---", attr) + else + if field[2] == VALUE then + lcd.drawNumber(COLUMN_2, 30+20*index, field[4], LEFT + attr) + elseif field[2] == COMBO then + if field[4] >= 0 and field[4] < #(field[5]) then + lcd.drawText(COLUMN_2, 30+20*index, field[5][1+field[4]], attr) + end + end + end + end +end + +local function telemetryRead(field) + return sportTelemetryPush(0x17, 0x30, 0x0C30, field) +end + +local function telemetryWrite(field, value) + return sportTelemetryPush(0x17, 0x31, 0x0C30, field + value*256) +end + +local telemetryPopTimeout = 0 +local function refreshNext() + if refreshState == 0 then + if calibrationState == 1 then + if telemetryWrite(0x9D, calibrationStep) == true then + refreshState = 1 + calibrationState = 2 + telemetryPopTimeout = getTime() + 80 -- normal delay is 500ms + end + elseif #modifications > 0 then + telemetryWrite(modifications[1][1], modifications[1][2]) + modifications[1] = nil + elseif refreshIndex < #fields then + local field = fields[refreshIndex + 1] + if telemetryRead(field[3]) == true then + refreshState = 1 + telemetryPopTimeout = getTime() + 80 -- normal delay is 500ms + end + end + elseif refreshState == 1 then + local physicalId, primId, dataId, value = sportTelemetryPop() + if physicalId == 0x1A and primId == 0x32 and dataId == 0x0C30 then + local fieldId = value % 256 + if calibrationState == 2 then + if fieldId == 0x9D then + refreshState = 0 + calibrationState = 0 + calibrationStep = (calibrationStep + 1) % 7 + end + else + local field = fields[refreshIndex + 1] + if fieldId == field[3] then + local value = math.floor(value / 256) + if field[3] >= 0x9E and field[3] <= 0xA0 then + local b1 = value % 256 + local b2 = math.floor(value / 256) + value = b1*256 + b2 + value = value - bit32.band(value, 0x8000) * 2 + end + if field[2] == COMBO and #field == 6 then + for index = 1, #(field[6]), 1 do + if value == field[6][index] then + value = index - 1 + break + end + end + elseif field[2] == VALUE and #field == 8 then + value = value - field[8] + field[5] + end + fields[refreshIndex + 1][4] = value + refreshIndex = refreshIndex + 1 + refreshState = 0 + end + end + elseif getTime() > telemetryPopTimeout then + refreshState = 0 + calibrationState = 0 + end + end +end + +local function updateField(field) + local value = field[4] + if field[2] == COMBO and #field == 6 then + value = field[6][1+value] + elseif field[2] == VALUE and #field == 8 then + value = value + field[8] - field[5] + end + modifications[#modifications+1] = { field[3], value } +end + +-- Main +local function runFieldsPage(event) + if event == EVT_EXIT_BREAK then -- exit script + return 2 + elseif event == EVT_ENTER_BREAK or event == EVT_ROT_BREAK then -- toggle editing/selecting current field + if fields[current][4] ~= nil then + edit = not edit + if edit == false then + updateField(fields[current]) + end + end + elseif edit then + if event == EVT_PLUS_FIRST or event == EVT_ROT_RIGHT or event == EVT_PLUS_REPT then + addField(1) + elseif event == EVT_MINUS_FIRST or event == EVT_ROT_LEFT or event == EVT_MINUS_REPT then + addField(-1) + end + else + if event == EVT_MINUS_FIRST or event == EVT_ROT_RIGHT then + selectField(1) + elseif event == EVT_PLUS_FIRST or event == EVT_ROT_LEFT then + selectField(-1) + end + end + redrawFieldsPage(event) + return 0 +end + +local function runConfigPage(event) + fields = configFields + local result = runFieldsPage(event) + if fields[1][4] ~= nil then + if wingBitmaps[1 + fields[1][4]] == nil then + wingBitmaps[1 + fields[1][4]] = Bitmap.open(wingBitmapsFile[1 + fields[1][4]]) + end + lcd.drawBitmap(wingBitmaps[1 + fields[1][4]], 10, 90) + end + if fields[2][4] ~= nil then + if mountBitmaps[1 + fields[2][4]] == nil then + mountBitmaps[1 + fields[2][4]] = Bitmap.open(mountBitmapsFile[1 + fields[2][4]]) + end + lcd.drawBitmap(mountBitmaps[1 + fields[2][4]], 190, 110) + end + return result +end + +local function runSettingsPage(event) + fields = settingsFields + return runFieldsPage(event) +end + +local function runCalibrationPage(event) + fields = calibrationFields + if refreshIndex == #fields then + refreshIndex = 0 + end + lcd.clear() + drawScreenTitle("S6R", page, #pages) + if(calibrationStep < 6) then + local position = calibrationPositions[1 + calibrationStep] + lcd.drawText(100, 50, "Place the S6R in the following position", TEXT_COLOR) + if calibBitmaps[calibrationStep + 1] == nil then + calibBitmaps[calibrationStep + 1] = Bitmap.open(calibBitmapsFile[calibrationStep + 1]) + end + lcd.drawBitmap(calibBitmaps[calibrationStep + 1], 200, 70) + for index = 1, 3, 1 do + local field = fields[index] + lcd.drawText(70, 80+20*index, field[1]..":", TEXT_COLOR) + lcd.drawNumber(90, 80+20*index, field[4]/10, LEFT+PREC2) + end + + local attr = calibrationState == 0 and INVERS or 0 + lcd.drawText(160, 220, "Press [Enter] when ready", attr) + else + lcd.drawText(160, 50, "Calibration completed", 0) + lcd.drawBitmap(Bitmap.open("img/done.bmp"),200, 100) + lcd.drawText(160, 220, "Press [RTN] when ready", attr) + end + if calibrationStep > 6 and (event == EVT_ENTER_BREAK or event == EVT_EXIT_BREAK) then + return 2 + elseif event == EVT_ENTER_BREAK then + calibrationState = 1 + elseif event == EVT_EXIT_BREAK then + if calibrationStep > 0 then + calibrationStep = 0 + end + end + return 0 + +end + +-- Init +local function init() + current, edit, refreshState, refreshIndex = 1, false, 0, 0 + pages = { + runConfigPage, + runSettingsPage, + runCalibrationPage + } +end + +-- Main +local function run(event) + if event == nil then + error("Cannot be run as a model script!") + return 2 + elseif event == EVT_PAGE_BREAK or event == EVT_PAGEDN_FIRST then + selectPage(1) + elseif event == EVT_PAGE_LONG or event == EVT_PAGEUP_FIRST then + killEvents(event); + selectPage(-1) + end + + local result = pages[page](event) + refreshNext() + + return result +end + +return { init=init, run=run } diff --git a/radio/sdcard/taranis-x7/SCRIPTS/snake.lua b/radio/sdcard/taranis-x7/SCRIPTS/snake.lua index 2f2cff87a..012a9f1e1 100644 --- a/radio/sdcard/taranis-x7/SCRIPTS/snake.lua +++ b/radio/sdcard/taranis-x7/SCRIPTS/snake.lua @@ -1,176 +1,176 @@ --------------------------------------------------------------- --- Classic snake game --- --- 2009 Led Lab @PUC-Rio www.eluaproject.net --- Dado Sutter --- Ives Negreiros --- To Benjamin ---------------------------------------------------------------- - -local xMax = math.floor( LCD_W / 6 ) - 1 -local yMax = math.floor( LCD_H / 8 ) - 1 -local game_map = {} - -local Head = {} -local Tail = {} - -local highscore = 0 -local size = 3 -Tail.x = 1 -Tail.y = 1 -Head.x = Tail.x + ( size - 1 ) -Head.y = Tail.y - -local Food = {} -Food.x = false -Food.y = false - -Head.dx = 1 -Head.dy = 0 -Tail.dx = Head.dx -Tail.dy = Head.dy -local direction = "right" -local score = 0 - -local function create_food() - Food.x, Food.y = math.random( xMax - 1), math.random( yMax - 1) - while game_map[ Food.x ][ Food.y ] do - Food.x, Food.y = math.random( xMax - 1 ), math.random( yMax - 1 ) - end - game_map[ Food.x ][ Food.y ] = "food" - lcd.drawText( Food.x * 6, Food.y * 8+2, "@", 0 ) -end - -local function eat_food() - playFile("/SCRIPTS/snake.wav") - lcd.drawText( Head.x * 6, Head.y * 8, " ", 0 ) - game_map[ Head.x ][ Head.y ] = nil - create_food() - score = score + 1 -end - -local function check_collision() - if Head.x < 0 or Head.x > xMax then - return true - elseif Head.y < 0 or Head.y > yMax then - return true - elseif ( ( game_map[ Head.x ][ Head.y ] ) and ( game_map[ Head.x ][ Head.y ] ~= "food" ) ) then - return true - end - return false -end - -local function move() - if game_map[ Tail.x ][ Tail.y ] == "right" then - Tail.dx = 1 - Tail.dy = 0 - elseif game_map[ Tail.x ][ Tail.y ] == "left" then - Tail.dx = -1 - Tail.dy = 0 - elseif game_map[ Tail.x ][ Tail.y ] == "up" then - Tail.dx = 0 - Tail.dy = -1 - elseif game_map[ Tail.x ][ Tail.y ] == "down" then - Tail.dx = 0 - Tail.dy = 1 - end - - game_map[ Head.x ][ Head.y ] = direction - Head.x = Head.x + Head.dx - Head.y = Head.y + Head.dy - - if Head.x < 0 or Head.x > xMax or Head.y < 0 or Head.y > yMax then - return - elseif game_map[ Head.x ][ Head.y ] == "food" then - eat_food() - else - lcd.drawText(Tail.x * 6, Tail.y * 8, " ", 16) - game_map[ Tail.x ][ Tail.y ] = nil - Tail.x = Tail.x + Tail.dx - Tail.y = Tail.y + Tail.dy - end - - lcd.drawText(Head.x * 6, Head.y * 8, "*", 0) -end - -local function init() - food = false - lcd.clear() - size = 3 - score = 0 - Tail.x = 1 - Tail.y = 1 - Head.x = Tail.x + ( size - 1 ) - Head.y = Tail.y - Head.dx = 1 - Head.dy = 0 - Tail.dx = Head.dx - Tail.dy = Head.dy - direction = "right" - - for i = 0, xMax, 1 do - game_map[ i ] = {} - end - - for i = 0, size - 1, 1 do - game_map[ Tail.x + ( i * Tail.dx ) ][ Tail.y + ( i * Tail.dy ) ] = direction - lcd.drawText( ( Tail.x + ( i * Tail.dx ) ) * 6, ( Tail.y + ( i * Tail.dy ) ) * 8, "*", 0 ) - end - - create_food() -end - -local snakeCounter = 0 - -local function run(event) - if event == nil then - raise("Cannot be run as a model script!") - end - - if event == EVT_EXIT_BREAK then - return 2 - end - - snakeCounter = snakeCounter + 1 - if snakeCounter < 30 then - return 0 - end - - snakeCounter = 0 - - local dir = direction - if getValue('rud') > 100 and direction ~= "left" then - dir = "right" - Head.dx = 1 - Head.dy = 0 - end - if getValue('rud') < -100 and direction ~= "right" then - dir = "left" - Head.dx = -1 - Head.dy = 0 - end - if getValue('ele') > 100 and direction ~= "down" then - dir = "up" - Head.dx = 0 - Head.dy = -1 - end - if getValue('ele') < -100 and direction ~= "up" then - dir = "down" - Head.dx = 0 - Head.dy = 1 - end - - direction = dir - move() - - lcd.refresh() - - if check_collision() then - return 1 - end - - return 0 -end - -return { init=init, run=run } - +-------------------------------------------------------------- +-- Classic snake game +-- +-- 2009 Led Lab @PUC-Rio www.eluaproject.net +-- Dado Sutter +-- Ives Negreiros +-- To Benjamin +--------------------------------------------------------------- + +local xMax = math.floor( LCD_W / 6 ) - 1 +local yMax = math.floor( LCD_H / 8 ) - 1 +local game_map = {} + +local Head = {} +local Tail = {} + +local highscore = 0 +local size = 3 +Tail.x = 1 +Tail.y = 1 +Head.x = Tail.x + ( size - 1 ) +Head.y = Tail.y + +local Food = {} +Food.x = false +Food.y = false + +Head.dx = 1 +Head.dy = 0 +Tail.dx = Head.dx +Tail.dy = Head.dy +local direction = "right" +local score = 0 + +local function create_food() + Food.x, Food.y = math.random( xMax - 1), math.random( yMax - 1) + while game_map[ Food.x ][ Food.y ] do + Food.x, Food.y = math.random( xMax - 1 ), math.random( yMax - 1 ) + end + game_map[ Food.x ][ Food.y ] = "food" + lcd.drawText( Food.x * 6, Food.y * 8+2, "@", 0 ) +end + +local function eat_food() + playFile("/SCRIPTS/snake.wav") + lcd.drawText( Head.x * 6, Head.y * 8, " ", 0 ) + game_map[ Head.x ][ Head.y ] = nil + create_food() + score = score + 1 +end + +local function check_collision() + if Head.x < 0 or Head.x > xMax then + return true + elseif Head.y < 0 or Head.y > yMax then + return true + elseif ( ( game_map[ Head.x ][ Head.y ] ) and ( game_map[ Head.x ][ Head.y ] ~= "food" ) ) then + return true + end + return false +end + +local function move() + if game_map[ Tail.x ][ Tail.y ] == "right" then + Tail.dx = 1 + Tail.dy = 0 + elseif game_map[ Tail.x ][ Tail.y ] == "left" then + Tail.dx = -1 + Tail.dy = 0 + elseif game_map[ Tail.x ][ Tail.y ] == "up" then + Tail.dx = 0 + Tail.dy = -1 + elseif game_map[ Tail.x ][ Tail.y ] == "down" then + Tail.dx = 0 + Tail.dy = 1 + end + + game_map[ Head.x ][ Head.y ] = direction + Head.x = Head.x + Head.dx + Head.y = Head.y + Head.dy + + if Head.x < 0 or Head.x > xMax or Head.y < 0 or Head.y > yMax then + return + elseif game_map[ Head.x ][ Head.y ] == "food" then + eat_food() + else + lcd.drawText(Tail.x * 6, Tail.y * 8, " ", 16) + game_map[ Tail.x ][ Tail.y ] = nil + Tail.x = Tail.x + Tail.dx + Tail.y = Tail.y + Tail.dy + end + + lcd.drawText(Head.x * 6, Head.y * 8, "*", 0) +end + +local function init() + food = false + lcd.clear() + size = 3 + score = 0 + Tail.x = 1 + Tail.y = 1 + Head.x = Tail.x + ( size - 1 ) + Head.y = Tail.y + Head.dx = 1 + Head.dy = 0 + Tail.dx = Head.dx + Tail.dy = Head.dy + direction = "right" + + for i = 0, xMax, 1 do + game_map[ i ] = {} + end + + for i = 0, size - 1, 1 do + game_map[ Tail.x + ( i * Tail.dx ) ][ Tail.y + ( i * Tail.dy ) ] = direction + lcd.drawText( ( Tail.x + ( i * Tail.dx ) ) * 6, ( Tail.y + ( i * Tail.dy ) ) * 8, "*", 0 ) + end + + create_food() +end + +local snakeCounter = 0 + +local function run(event) + if event == nil then + raise("Cannot be run as a model script!") + end + + if event == EVT_EXIT_BREAK then + return 2 + end + + snakeCounter = snakeCounter + 1 + if snakeCounter < 30 then + return 0 + end + + snakeCounter = 0 + + local dir = direction + if getValue('rud') > 100 and direction ~= "left" then + dir = "right" + Head.dx = 1 + Head.dy = 0 + end + if getValue('rud') < -100 and direction ~= "right" then + dir = "left" + Head.dx = -1 + Head.dy = 0 + end + if getValue('ele') > 100 and direction ~= "down" then + dir = "up" + Head.dx = 0 + Head.dy = -1 + end + if getValue('ele') < -100 and direction ~= "up" then + dir = "down" + Head.dx = 0 + Head.dy = 1 + end + + direction = dir + move() + + lcd.refresh() + + if check_collision() then + return 1 + end + + return 0 +end + +return { init=init, run=run } + diff --git a/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/delta.lua b/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/delta.lua index d26f6e1fe..b2a8eda07 100644 --- a/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/delta.lua +++ b/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/delta.lua @@ -1,375 +1,375 @@ --- Delta Wizard pages -local ENGINE_PAGE = 0 -local ELEVONS_PAGE = 1 -local RUDDER_PAGE = 2 -local CONFIRMATION_PAGE = 3 - --- Navigation variables -local page = ENGINE_PAGE -local dirty = true -local edit = false -local field = 0 -local fieldsMax = 0 - --- Model settings -local engineMode = 1 -local thrCH1 = 0 -local elevCH1 = 0 -local elevCH2 = 0 -local elevonsMode = 0 -local rudderMode = 0 -local rudCH1 = 0 -local servoPage = nil - --- Common functions -local lastBlink = 0 -local function blinkChanged() - local time = getTime() % 128 - local blink = (time - time % 64) / 64 - if blink ~= lastBlink then - lastBlink = blink - return true - else - return false - end -end - -local function fieldIncDec(event, value, max, force) - if edit or force==true then - if event == EVT_PLUS_BREAK or event == EVT_ROT_LEFT then - value = (value + max) - dirty = true - elseif event == EVT_MINUS_BREAK or event == EVT_ROT_RIGHT then - value = (value + max + 2) - dirty = true - end - value = (value % (max+1)) - end - return value -end - -local function valueIncDec(event, value, min, max) - if edit then - if event == EVT_PLUS_FIRST or event == EVT_PLUS_REPT or event == EVT_ROT_RIGHT then - if value < max then - value = (value + 1) - dirty = true - end - elseif event == EVT_MINUS_FIRST or event == EVT_MINUS_REPT or event == EVT_ROT_LEFT then - if value > min then - value = (value - 1) - dirty = true - end - end - end - return value -end - -local function navigate(event, fieldMax, prevPage, nextPage) - if event == EVT_ENTER_BREAK then - edit = not edit - dirty = true - elseif edit then - if event == EVT_EXIT_BREAK then - edit = false - dirty = true - elseif not dirty then - dirty = blinkChanged() - end - else - if event == EVT_PAGE_BREAK then - page = nextPage - field = 0 - dirty = true - elseif event == EVT_PAGE_LONG then - page = prevPage - field = 0 - killEvents(event); - dirty = true - else - field = fieldIncDec(event, field, fieldMax, true) - end - end -end - -local function getFieldFlags(position) - flags = 0 - if field == position then - flags = INVERS - if edit then - flags = INVERS + BLINK - end - end - return flags -end - -local function channelIncDec(event, value) - if not edit and event==EVT_MENU_BREAK then - servoPage = value - dirty = true - else - value = valueIncDec(event, value, 0, 15) - end - return value -end - --- Init function -local function init() - rudCH1 = defaultChannel(0) - thrCH1 = defaultChannel(2) - elevCH1 = defaultChannel(1) - elevCH2 = defaultChannel(3) -end - --- Engine Menu -local engineModeItems = {"No", "Yes..."} -local function drawEngineMenu() - lcd.clear() - lcd.drawText(1, 0, "Has your model got an engine?", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, engineModeItems, engineMode, getFieldFlags(0)) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - if engineMode == 0 then - -- No engine - lcd.drawPixmap(132, 8, "engine-0.bmp") - fieldsMax = 0 - else - -- 1 channel - lcd.drawPixmap(132, 8, "engine-1.bmp") - lcd.drawText(25, LCD_H-16, "Assign channel", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(151, LCD_H-8, MIXSRC_CH1+thrCH1, getFieldFlags(1)) - fieldsMax = 1 - end -end - -local function engineMenu(event) - if dirty then - dirty = false - drawEngineMenu() - end - - navigate(event, fieldsMax, page, page+1) - - if field==0 then - engineMode = fieldIncDec(event, engineMode, 1) - elseif field==1 then - thrCH1 = channelIncDec(event, thrCH1) - end -end - --- Elevons Menu -local elevonsModeItems = {"2 Channels..."} -local function drawElevonsMenu() - lcd.clear() - lcd.drawText(1, 0, "Select elevon channnels", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, elevonsModeItems, elevonsMode, 0) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - lcd.drawPixmap(110, 9, "elevons.bmp") - lcd.drawText(20, LCD_H-16, "Assign channels", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(116, LCD_H-8, MIXSRC_CH1+elevCH1, getFieldFlags(0)) - lcd.drawSource(175, LCD_H-8, MIXSRC_CH1+elevCH2, getFieldFlags(1)) - fieldsMax = 1 -end - -local function elevonsMenu(event) - if dirty then - dirty = false - drawElevonsMenu() - end - - navigate(event, fieldsMax, page-1, page+1) - - if field==0 then - elevCH1 = channelIncDec(event, elevCH1) - elseif field==1 then - elevCH2 = channelIncDec(event, elevCH2) - end -end - --- Rudder menu -local rudderModeItems = {"No", "Yes..."} - -local function drawRudderMenu() - lcd.clear() - lcd.drawText(1, 0, "Has your model got a rudder?", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, rudderModeItems, rudderMode, getFieldFlags(0)) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - if rudderMode == 0 then - -- No rudder - lcd.drawPixmap(109, 14, "drudder-0.bmp") - fieldsMax = 0 - else - -- 1 channel - lcd.drawPixmap(109, 14, "drudder-1.bmp") - lcd.drawText(25, LCD_H-16, "Assign channel", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(190, LCD_H-55, MIXSRC_CH1+rudCH1, getFieldFlags(1)) - fieldsMax = 1 - end -end - -local function rudderMenu(event) - if dirty then - dirty = false - drawRudderMenu() - end - - navigate(event, fieldsMax, page-1, page+1) - - if field==0 then - rudderMode = fieldIncDec(event, rudderMode, 1) - elseif field==1 then - rudCH1 = channelIncDec(event, rudCH1) - end -end - --- Servo (limits) Menu -local function drawServoMenu(limits) - lcd.clear() - lcd.drawSource(1, 0, MIXSRC_CH1+servoPage, 0) - lcd.drawText(25, 0, "servo min/max/center/direction?", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawLine(LCD_W/2-1, 8, LCD_W/2-1, LCD_H-1, DOTTED, 0) - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawPixmap(122, 8, "servo.bmp") - lcd.drawNumber(140, 35, limits.min, PREC1+getFieldFlags(0)); - lcd.drawNumber(205, 35, limits.max, PREC1+getFieldFlags(1)); - lcd.drawNumber(170, 9, limits.offset, PREC1+getFieldFlags(2)); - if limits.revert == 0 then - lcd.drawText(129, 50, "\126", getFieldFlags(3)); - else - lcd.drawText(129, 50, "\127", getFieldFlags(3)); - end - fieldsMax = 3 -end - -local function servoMenu(event) - local limits = model.getOutput(servoPage) - - if dirty then - dirty = false - drawServoMenu(limits) - end - - navigate(event, fieldsMax, page, page) - - if edit then - if field==0 then - limits.min = valueIncDec(event, limits.min, -1000, 0) - elseif field==1 then - limits.max = valueIncDec(event, limits.max, 0, 1000) - elseif field==2 then - limits.offset = valueIncDec(event, limits.offset, -1000, 1000) - elseif field==3 then - limits.revert = fieldIncDec(event, limits.revert, 1) - end - model.setOutput(servoPage, limits) - elseif event == EVT_EXIT_BREAK then - servoPage = nil - dirty = true - end -end - --- Confirmation Menu -local function addMix(channel, input, name, weight, index) - local mix = { source=input, name=name } - if weight ~= nil then - mix.weight = weight - end - if index == nil then - index = 0 - end - model.insertMix(channel, index, mix) -end - -local function applySettings() - model.defaultInputs() - model.deleteMixes() - if engineMode == 1 then - addMix(thrCH1, MIXSRC_FIRST_INPUT+defaultChannel(2), "Engine") - end - addMix(elevCH1, MIXSRC_FIRST_INPUT+defaultChannel(1), "Elev1-E", 50) - addMix(elevCH1, MIXSRC_FIRST_INPUT+defaultChannel(3), "Elev1-A", 50, 1) - addMix(elevCH2, MIXSRC_FIRST_INPUT+defaultChannel(1), "Elev2-E", 50) - addMix(elevCH2, MIXSRC_FIRST_INPUT+defaultChannel(3), "Elev2-A", -50, 1) - if rudderMode == 1 then - addMix(rudCH1, MIXSRC_FIRST_INPUT+defaultChannel(0), "Rudder") - end -end - -local function drawNextLine(x, y, label, channel) - lcd.drawText(x, y, label, 0); - lcd.drawSource(x+52, y, MIXSRC_CH1+channel, 0) - y = y + 8 - if y > 50 then - y = 12 - x = 120 - end - return x, y -end - -local function drawConfirmationMenu() - local x = 22 - local y = 12 - lcd.clear() - lcd.drawText(48, 1, "Ready to go?", 0); - lcd.drawFilledRectangle(0, 0, LCD_W, 9, 0) - if engineMode == 1 then - x, y = drawNextLine(x, y, "Throttle:", thrCH1) - end - x, y = drawNextLine(x, y, "Elevons:", elevCH1) - x, y = drawNextLine(x, y, "Elevons:", elevCH2) - if rudderMode == 1 then - drawNextLine(x, y, "Rudder:", rudCH1) - end - lcd.drawText(48, LCD_H-8, "[Enter Long] to confirm", 0); - lcd.drawFilledRectangle(0, LCD_H-9, LCD_W, 9, 0) - lcd.drawPixmap(LCD_W-18, 0, "confirm-tick.bmp") - lcd.drawPixmap(0, LCD_H-17, "confirm-plane.bmp") - fieldsMax = 0 -end - -local function confirmationMenu(event) - if dirty then - dirty = false - drawConfirmationMenu() - end - - navigate(event, fieldsMax, RUDDER_PAGE, page) - - if event == EVT_EXIT_BREAK then - return 2 - elseif event == EVT_ENTER_LONG then - killEvents(event) - applySettings() - return 2 - else - return 0 - end -end - --- Main - -local function run(event) - if event == nil then - error("Cannot be run as a model script!") - end - if servoPage ~= nil then - servoMenu(event) - elseif page == ENGINE_PAGE then - engineMenu(event) - elseif page == ELEVONS_PAGE then - elevonsMenu(event) - elseif page == RUDDER_PAGE then - rudderMenu(event) - elseif page == CONFIRMATION_PAGE then - return confirmationMenu(event) - end - return 0 -end - -return { init=init, run=run } +-- Delta Wizard pages +local ENGINE_PAGE = 0 +local ELEVONS_PAGE = 1 +local RUDDER_PAGE = 2 +local CONFIRMATION_PAGE = 3 + +-- Navigation variables +local page = ENGINE_PAGE +local dirty = true +local edit = false +local field = 0 +local fieldsMax = 0 + +-- Model settings +local engineMode = 1 +local thrCH1 = 0 +local elevCH1 = 0 +local elevCH2 = 0 +local elevonsMode = 0 +local rudderMode = 0 +local rudCH1 = 0 +local servoPage = nil + +-- Common functions +local lastBlink = 0 +local function blinkChanged() + local time = getTime() % 128 + local blink = (time - time % 64) / 64 + if blink ~= lastBlink then + lastBlink = blink + return true + else + return false + end +end + +local function fieldIncDec(event, value, max, force) + if edit or force==true then + if event == EVT_PLUS_BREAK or event == EVT_ROT_LEFT then + value = (value + max) + dirty = true + elseif event == EVT_MINUS_BREAK or event == EVT_ROT_RIGHT then + value = (value + max + 2) + dirty = true + end + value = (value % (max+1)) + end + return value +end + +local function valueIncDec(event, value, min, max) + if edit then + if event == EVT_PLUS_FIRST or event == EVT_PLUS_REPT or event == EVT_ROT_RIGHT then + if value < max then + value = (value + 1) + dirty = true + end + elseif event == EVT_MINUS_FIRST or event == EVT_MINUS_REPT or event == EVT_ROT_LEFT then + if value > min then + value = (value - 1) + dirty = true + end + end + end + return value +end + +local function navigate(event, fieldMax, prevPage, nextPage) + if event == EVT_ENTER_BREAK then + edit = not edit + dirty = true + elseif edit then + if event == EVT_EXIT_BREAK then + edit = false + dirty = true + elseif not dirty then + dirty = blinkChanged() + end + else + if event == EVT_PAGE_BREAK then + page = nextPage + field = 0 + dirty = true + elseif event == EVT_PAGE_LONG then + page = prevPage + field = 0 + killEvents(event); + dirty = true + else + field = fieldIncDec(event, field, fieldMax, true) + end + end +end + +local function getFieldFlags(position) + flags = 0 + if field == position then + flags = INVERS + if edit then + flags = INVERS + BLINK + end + end + return flags +end + +local function channelIncDec(event, value) + if not edit and event==EVT_MENU_BREAK then + servoPage = value + dirty = true + else + value = valueIncDec(event, value, 0, 15) + end + return value +end + +-- Init function +local function init() + rudCH1 = defaultChannel(0) + thrCH1 = defaultChannel(2) + elevCH1 = defaultChannel(1) + elevCH2 = defaultChannel(3) +end + +-- Engine Menu +local engineModeItems = {"No", "Yes..."} +local function drawEngineMenu() + lcd.clear() + lcd.drawText(1, 0, "Has your model got an engine?", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, engineModeItems, engineMode, getFieldFlags(0)) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + if engineMode == 0 then + -- No engine + lcd.drawPixmap(132, 8, "engine-0.bmp") + fieldsMax = 0 + else + -- 1 channel + lcd.drawPixmap(132, 8, "engine-1.bmp") + lcd.drawText(25, LCD_H-16, "Assign channel", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(151, LCD_H-8, MIXSRC_CH1+thrCH1, getFieldFlags(1)) + fieldsMax = 1 + end +end + +local function engineMenu(event) + if dirty then + dirty = false + drawEngineMenu() + end + + navigate(event, fieldsMax, page, page+1) + + if field==0 then + engineMode = fieldIncDec(event, engineMode, 1) + elseif field==1 then + thrCH1 = channelIncDec(event, thrCH1) + end +end + +-- Elevons Menu +local elevonsModeItems = {"2 Channels..."} +local function drawElevonsMenu() + lcd.clear() + lcd.drawText(1, 0, "Select elevon channnels", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, elevonsModeItems, elevonsMode, 0) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + lcd.drawPixmap(110, 9, "elevons.bmp") + lcd.drawText(20, LCD_H-16, "Assign channels", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(116, LCD_H-8, MIXSRC_CH1+elevCH1, getFieldFlags(0)) + lcd.drawSource(175, LCD_H-8, MIXSRC_CH1+elevCH2, getFieldFlags(1)) + fieldsMax = 1 +end + +local function elevonsMenu(event) + if dirty then + dirty = false + drawElevonsMenu() + end + + navigate(event, fieldsMax, page-1, page+1) + + if field==0 then + elevCH1 = channelIncDec(event, elevCH1) + elseif field==1 then + elevCH2 = channelIncDec(event, elevCH2) + end +end + +-- Rudder menu +local rudderModeItems = {"No", "Yes..."} + +local function drawRudderMenu() + lcd.clear() + lcd.drawText(1, 0, "Has your model got a rudder?", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, rudderModeItems, rudderMode, getFieldFlags(0)) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + if rudderMode == 0 then + -- No rudder + lcd.drawPixmap(109, 14, "drudder-0.bmp") + fieldsMax = 0 + else + -- 1 channel + lcd.drawPixmap(109, 14, "drudder-1.bmp") + lcd.drawText(25, LCD_H-16, "Assign channel", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(190, LCD_H-55, MIXSRC_CH1+rudCH1, getFieldFlags(1)) + fieldsMax = 1 + end +end + +local function rudderMenu(event) + if dirty then + dirty = false + drawRudderMenu() + end + + navigate(event, fieldsMax, page-1, page+1) + + if field==0 then + rudderMode = fieldIncDec(event, rudderMode, 1) + elseif field==1 then + rudCH1 = channelIncDec(event, rudCH1) + end +end + +-- Servo (limits) Menu +local function drawServoMenu(limits) + lcd.clear() + lcd.drawSource(1, 0, MIXSRC_CH1+servoPage, 0) + lcd.drawText(25, 0, "servo min/max/center/direction?", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawLine(LCD_W/2-1, 8, LCD_W/2-1, LCD_H-1, DOTTED, 0) + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawPixmap(122, 8, "servo.bmp") + lcd.drawNumber(140, 35, limits.min, PREC1+getFieldFlags(0)); + lcd.drawNumber(205, 35, limits.max, PREC1+getFieldFlags(1)); + lcd.drawNumber(170, 9, limits.offset, PREC1+getFieldFlags(2)); + if limits.revert == 0 then + lcd.drawText(129, 50, "\126", getFieldFlags(3)); + else + lcd.drawText(129, 50, "\127", getFieldFlags(3)); + end + fieldsMax = 3 +end + +local function servoMenu(event) + local limits = model.getOutput(servoPage) + + if dirty then + dirty = false + drawServoMenu(limits) + end + + navigate(event, fieldsMax, page, page) + + if edit then + if field==0 then + limits.min = valueIncDec(event, limits.min, -1000, 0) + elseif field==1 then + limits.max = valueIncDec(event, limits.max, 0, 1000) + elseif field==2 then + limits.offset = valueIncDec(event, limits.offset, -1000, 1000) + elseif field==3 then + limits.revert = fieldIncDec(event, limits.revert, 1) + end + model.setOutput(servoPage, limits) + elseif event == EVT_EXIT_BREAK then + servoPage = nil + dirty = true + end +end + +-- Confirmation Menu +local function addMix(channel, input, name, weight, index) + local mix = { source=input, name=name } + if weight ~= nil then + mix.weight = weight + end + if index == nil then + index = 0 + end + model.insertMix(channel, index, mix) +end + +local function applySettings() + model.defaultInputs() + model.deleteMixes() + if engineMode == 1 then + addMix(thrCH1, MIXSRC_FIRST_INPUT+defaultChannel(2), "Engine") + end + addMix(elevCH1, MIXSRC_FIRST_INPUT+defaultChannel(1), "Elev1-E", 50) + addMix(elevCH1, MIXSRC_FIRST_INPUT+defaultChannel(3), "Elev1-A", 50, 1) + addMix(elevCH2, MIXSRC_FIRST_INPUT+defaultChannel(1), "Elev2-E", 50) + addMix(elevCH2, MIXSRC_FIRST_INPUT+defaultChannel(3), "Elev2-A", -50, 1) + if rudderMode == 1 then + addMix(rudCH1, MIXSRC_FIRST_INPUT+defaultChannel(0), "Rudder") + end +end + +local function drawNextLine(x, y, label, channel) + lcd.drawText(x, y, label, 0); + lcd.drawSource(x+52, y, MIXSRC_CH1+channel, 0) + y = y + 8 + if y > 50 then + y = 12 + x = 120 + end + return x, y +end + +local function drawConfirmationMenu() + local x = 22 + local y = 12 + lcd.clear() + lcd.drawText(48, 1, "Ready to go?", 0); + lcd.drawFilledRectangle(0, 0, LCD_W, 9, 0) + if engineMode == 1 then + x, y = drawNextLine(x, y, "Throttle:", thrCH1) + end + x, y = drawNextLine(x, y, "Elevons:", elevCH1) + x, y = drawNextLine(x, y, "Elevons:", elevCH2) + if rudderMode == 1 then + drawNextLine(x, y, "Rudder:", rudCH1) + end + lcd.drawText(48, LCD_H-8, "[Enter Long] to confirm", 0); + lcd.drawFilledRectangle(0, LCD_H-9, LCD_W, 9, 0) + lcd.drawPixmap(LCD_W-18, 0, "confirm-tick.bmp") + lcd.drawPixmap(0, LCD_H-17, "confirm-plane.bmp") + fieldsMax = 0 +end + +local function confirmationMenu(event) + if dirty then + dirty = false + drawConfirmationMenu() + end + + navigate(event, fieldsMax, RUDDER_PAGE, page) + + if event == EVT_EXIT_BREAK then + return 2 + elseif event == EVT_ENTER_LONG then + killEvents(event) + applySettings() + return 2 + else + return 0 + end +end + +-- Main + +local function run(event) + if event == nil then + error("Cannot be run as a model script!") + end + if servoPage ~= nil then + servoMenu(event) + elseif page == ENGINE_PAGE then + engineMenu(event) + elseif page == ELEVONS_PAGE then + elevonsMenu(event) + elseif page == RUDDER_PAGE then + rudderMenu(event) + elseif page == CONFIRMATION_PAGE then + return confirmationMenu(event) + end + return 0 +end + +return { init=init, run=run } diff --git a/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/multi.lua b/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/multi.lua index ec41fac25..53866eab2 100644 --- a/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/multi.lua +++ b/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/multi.lua @@ -1,305 +1,305 @@ --- Multicopter Wizard pages -local THROTTLE_PAGE = 0 -local ROLL_PAGE = 1 -local PITCH_PAGE = 2 -local YAW_PAGE = 3 -local CONFIRMATION_PAGE = 4 - --- Navigation variables -local page = THROTTLE_PAGE -local dirty = true -local edit = false -local field = 0 -local fieldsMax = 0 -local comboBoxMode = 0 -- Scrap variable - --- Model settings -local thrCH1 = 0 -local rollCH1 = 0 -local yawCH1 = 0 -local pitchCH1 = 0 - --- Common functions -local lastBlink = 0 -local function blinkChanged() - local time = getTime() % 128 - local blink = (time - time % 64) / 64 - if blink ~= lastBlink then - lastBlink = blink - return true - else - return false - end -end - -local function fieldIncDec(event, value, max, force) - if edit or force==true then - if event == EVT_PLUS_BREAK or event == EVT_ROT_LEFT then - value = (value + max) - dirty = true - elseif event == EVT_MINUS_BREAK or event == EVT_ROT_RIGHT then - value = (value + max + 2) - dirty = true - end - value = (value % (max+1)) - end - return value -end - -local function valueIncDec(event, value, min, max) - if edit then - if event == EVT_PLUS_FIRST or event == EVT_PLUS_REPT or event == EVT_ROT_RIGHT then - if value < max then - value = (value + 1) - dirty = true - end - elseif event == EVT_MINUS_FIRST or event == EVT_MINUS_REPT or event == EVT_ROT_LEFT then - if value > min then - value = (value - 1) - dirty = true - end - end - end - return value -end - -local function navigate(event, fieldMax, prevPage, nextPage) - if event == EVT_ENTER_BREAK then - edit = not edit - dirty = true - elseif edit then - if event == EVT_EXIT_BREAK then - edit = false - dirty = true - elseif not dirty then - dirty = blinkChanged() - end - else - if event == EVT_PAGE_BREAK then - page = nextPage - field = 0 - dirty = true - elseif event == EVT_PAGE_LONG then - page = prevPage - field = 0 - killEvents(event); - dirty = true - else - field = fieldIncDec(event, field, fieldMax, true) - end - end -end - -local function getFieldFlags(position) - flags = 0 - if field == position then - flags = INVERS - if edit then - flags = INVERS + BLINK - end - end - return flags -end - -local function channelIncDec(event, value) - if not edit and event==EVT_MENU_BREAK then - servoPage = value - dirty = true - else - value = valueIncDec(event, value, 0, 15) - end - return value -end - --- Init function -local function init() - thrCH1 = defaultChannel(2) - rollCH1 = defaultChannel(3) - yawCH1 = defaultChannel(0) - pitchCH1 = defaultChannel(1) -end - --- Throttle Menu -local function drawThrottleMenu() - lcd.clear() - lcd.drawText(1, 0, "Select multicopter throttle channel", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, {"..."}, comboBoxMode, getFieldFlags(1)) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - lcd.drawPixmap(120, 8, "multi-thr.bmp") - lcd.drawText(20, LCD_H-16, "Assign Throttle", 0); - lcd.drawText(20, LCD_H-8, "Channel", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(113, LCD_H-8, MIXSRC_CH1+thrCH1, getFieldFlags(0)) - fieldsMax = 0 -end - -local function throttleMenu(event) - if dirty then - dirty = false - drawThrottleMenu() - end - navigate(event, fieldsMax, page, page+1) - thrCH1 = channelIncDec(event, thrCH1) -end - --- Roll Menu -local function drawRollMenu() - lcd.clear() - lcd.drawText(1, 0, "Select multicopter roll channel", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, {"..."}, comboBoxMode, getFieldFlags(1)) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - lcd.drawPixmap(120, 8, "multi-roll.bmp") - lcd.drawText(20, LCD_H-16, "Assign Roll", 0); - lcd.drawText(20, LCD_H-8, "Channel", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(113, LCD_H-8, MIXSRC_CH1+rollCH1, getFieldFlags(0)) - fieldsMax = 0 -end - -local function rollMenu(event) - if dirty then - dirty = false - drawRollMenu() - end - navigate(event, fieldsMax, page-1, page+1) - rollCH1 = channelIncDec(event, rollCH1) -end - --- Pitch Menu -local function drawPitchMenu() - lcd.clear() - lcd.drawText(1, 0, "Select multicopter pitch channel", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, {"..."}, comboBoxMode, getFieldFlags(1)) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - lcd.drawPixmap(120, 8, "multi-pitch.bmp") - lcd.drawText(20, LCD_H-16, "Assign Pitch", 0); - lcd.drawText(20, LCD_H-8, "Channel", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(113, LCD_H-8, MIXSRC_CH1+pitchCH1, getFieldFlags(0)) - fieldsMax = 0 -end - -local function pitchMenu(event) - if dirty then - dirty = false - drawPitchMenu() - end - navigate(event, fieldsMax, page-1, page+1) - pitchCH1 = channelIncDec(event, pitchCH1) -end - --- Yaw Menu -local function drawYawMenu() - lcd.clear() - lcd.drawText(1, 0, "Select multicopter yaw channel", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, {"..."}, comboBoxMode, getFieldFlags(1)) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - lcd.drawPixmap(120, 8, "multi-yaw.bmp") - lcd.drawText(20, LCD_H-16, "Assign Yaw", 0); - lcd.drawText(20, LCD_H-8, "Channel", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(113, LCD_H-8, MIXSRC_CH1+yawCH1, getFieldFlags(0)) - fieldsMax = 0 -end - -local function yawMenu(event) - if dirty then - dirty = false - drawYawMenu() - end - navigate(event, fieldsMax, page-1, page+1) - yawCH1 = channelIncDec(event, yawCH1) -end - --- Confirmation Menu -local function drawNextLine(x, y, label, channel) - lcd.drawText(x, y, label, 0); - lcd.drawSource(x+52, y, MIXSRC_CH1+channel, 0) - y = y + 8 - if y > 50 then - y = 12 - x = 120 - end - return x, y -end - -local function drawConfirmationMenu() - local x = 22 - local y = 12 - lcd.clear() - lcd.drawText(48, 1, "Ready to go?", 0); - lcd.drawFilledRectangle(0, 0, LCD_W, 9, 0) - x, y = drawNextLine(x, y, "Throttle:", thrCH1) - x, y = drawNextLine(x, y, "Roll:", rollCH1) - x, y = drawNextLine(x, y, "Pitch:", pitchCH1) - x, y = drawNextLine(x, y, "Yaw:", yawCH1) - lcd.drawText(48, LCD_H-8, "[Enter Long] to confirm", 0); - lcd.drawFilledRectangle(0, LCD_H-9, LCD_W, 9, 0) - lcd.drawPixmap(LCD_W-18, 0, "confirm-tick.bmp") - lcd.drawPixmap(0, LCD_H-17, "confirm-plane.bmp") - fieldsMax = 0 -end - -local function addMix(channel, input, name, weight, index) - local mix = { source=input, name=name } - if weight ~= nil then - mix.weight = weight - end - if index == nil then - index = 0 - end - model.insertMix(channel, index, mix) -end - -local function applySettings() - model.defaultInputs() - model.deleteMixes() - addMix(thrCH1, MIXSRC_FIRST_INPUT+defaultChannel(2), "Throttle") - addMix(rollCH1, MIXSRC_FIRST_INPUT+defaultChannel(3), "Roll") - addMix(yawCH1, MIXSRC_FIRST_INPUT+defaultChannel(0), "Yaw") - addMix(pitchCH1, MIXSRC_FIRST_INPUT+defaultChannel(1), "Pitch") -end - -local function confirmationMenu(event) - if dirty then - dirty = false - drawConfirmationMenu() - end - - navigate(event, fieldsMax, YAW_PAGE, page) - - if event == EVT_EXIT_BREAK then - return 2 - elseif event == EVT_ENTER_LONG then - killEvents(event) - applySettings() - return 2 - else - return 0 - end -end - --- Main -local function run(event) - if event == nil then - error("Cannot be run as a model script!") - end - if page == THROTTLE_PAGE then - throttleMenu(event) - elseif page == ROLL_PAGE then - rollMenu(event) - elseif page == YAW_PAGE then - yawMenu(event) - elseif page == PITCH_PAGE then - pitchMenu(event) - elseif page == CONFIRMATION_PAGE then - return confirmationMenu(event) - end - return 0 -end - -return { init=init, run=run } +-- Multicopter Wizard pages +local THROTTLE_PAGE = 0 +local ROLL_PAGE = 1 +local PITCH_PAGE = 2 +local YAW_PAGE = 3 +local CONFIRMATION_PAGE = 4 + +-- Navigation variables +local page = THROTTLE_PAGE +local dirty = true +local edit = false +local field = 0 +local fieldsMax = 0 +local comboBoxMode = 0 -- Scrap variable + +-- Model settings +local thrCH1 = 0 +local rollCH1 = 0 +local yawCH1 = 0 +local pitchCH1 = 0 + +-- Common functions +local lastBlink = 0 +local function blinkChanged() + local time = getTime() % 128 + local blink = (time - time % 64) / 64 + if blink ~= lastBlink then + lastBlink = blink + return true + else + return false + end +end + +local function fieldIncDec(event, value, max, force) + if edit or force==true then + if event == EVT_PLUS_BREAK or event == EVT_ROT_LEFT then + value = (value + max) + dirty = true + elseif event == EVT_MINUS_BREAK or event == EVT_ROT_RIGHT then + value = (value + max + 2) + dirty = true + end + value = (value % (max+1)) + end + return value +end + +local function valueIncDec(event, value, min, max) + if edit then + if event == EVT_PLUS_FIRST or event == EVT_PLUS_REPT or event == EVT_ROT_RIGHT then + if value < max then + value = (value + 1) + dirty = true + end + elseif event == EVT_MINUS_FIRST or event == EVT_MINUS_REPT or event == EVT_ROT_LEFT then + if value > min then + value = (value - 1) + dirty = true + end + end + end + return value +end + +local function navigate(event, fieldMax, prevPage, nextPage) + if event == EVT_ENTER_BREAK then + edit = not edit + dirty = true + elseif edit then + if event == EVT_EXIT_BREAK then + edit = false + dirty = true + elseif not dirty then + dirty = blinkChanged() + end + else + if event == EVT_PAGE_BREAK then + page = nextPage + field = 0 + dirty = true + elseif event == EVT_PAGE_LONG then + page = prevPage + field = 0 + killEvents(event); + dirty = true + else + field = fieldIncDec(event, field, fieldMax, true) + end + end +end + +local function getFieldFlags(position) + flags = 0 + if field == position then + flags = INVERS + if edit then + flags = INVERS + BLINK + end + end + return flags +end + +local function channelIncDec(event, value) + if not edit and event==EVT_MENU_BREAK then + servoPage = value + dirty = true + else + value = valueIncDec(event, value, 0, 15) + end + return value +end + +-- Init function +local function init() + thrCH1 = defaultChannel(2) + rollCH1 = defaultChannel(3) + yawCH1 = defaultChannel(0) + pitchCH1 = defaultChannel(1) +end + +-- Throttle Menu +local function drawThrottleMenu() + lcd.clear() + lcd.drawText(1, 0, "Select multicopter throttle channel", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, {"..."}, comboBoxMode, getFieldFlags(1)) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + lcd.drawPixmap(120, 8, "multi-thr.bmp") + lcd.drawText(20, LCD_H-16, "Assign Throttle", 0); + lcd.drawText(20, LCD_H-8, "Channel", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(113, LCD_H-8, MIXSRC_CH1+thrCH1, getFieldFlags(0)) + fieldsMax = 0 +end + +local function throttleMenu(event) + if dirty then + dirty = false + drawThrottleMenu() + end + navigate(event, fieldsMax, page, page+1) + thrCH1 = channelIncDec(event, thrCH1) +end + +-- Roll Menu +local function drawRollMenu() + lcd.clear() + lcd.drawText(1, 0, "Select multicopter roll channel", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, {"..."}, comboBoxMode, getFieldFlags(1)) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + lcd.drawPixmap(120, 8, "multi-roll.bmp") + lcd.drawText(20, LCD_H-16, "Assign Roll", 0); + lcd.drawText(20, LCD_H-8, "Channel", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(113, LCD_H-8, MIXSRC_CH1+rollCH1, getFieldFlags(0)) + fieldsMax = 0 +end + +local function rollMenu(event) + if dirty then + dirty = false + drawRollMenu() + end + navigate(event, fieldsMax, page-1, page+1) + rollCH1 = channelIncDec(event, rollCH1) +end + +-- Pitch Menu +local function drawPitchMenu() + lcd.clear() + lcd.drawText(1, 0, "Select multicopter pitch channel", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, {"..."}, comboBoxMode, getFieldFlags(1)) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + lcd.drawPixmap(120, 8, "multi-pitch.bmp") + lcd.drawText(20, LCD_H-16, "Assign Pitch", 0); + lcd.drawText(20, LCD_H-8, "Channel", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(113, LCD_H-8, MIXSRC_CH1+pitchCH1, getFieldFlags(0)) + fieldsMax = 0 +end + +local function pitchMenu(event) + if dirty then + dirty = false + drawPitchMenu() + end + navigate(event, fieldsMax, page-1, page+1) + pitchCH1 = channelIncDec(event, pitchCH1) +end + +-- Yaw Menu +local function drawYawMenu() + lcd.clear() + lcd.drawText(1, 0, "Select multicopter yaw channel", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, {"..."}, comboBoxMode, getFieldFlags(1)) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + lcd.drawPixmap(120, 8, "multi-yaw.bmp") + lcd.drawText(20, LCD_H-16, "Assign Yaw", 0); + lcd.drawText(20, LCD_H-8, "Channel", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(113, LCD_H-8, MIXSRC_CH1+yawCH1, getFieldFlags(0)) + fieldsMax = 0 +end + +local function yawMenu(event) + if dirty then + dirty = false + drawYawMenu() + end + navigate(event, fieldsMax, page-1, page+1) + yawCH1 = channelIncDec(event, yawCH1) +end + +-- Confirmation Menu +local function drawNextLine(x, y, label, channel) + lcd.drawText(x, y, label, 0); + lcd.drawSource(x+52, y, MIXSRC_CH1+channel, 0) + y = y + 8 + if y > 50 then + y = 12 + x = 120 + end + return x, y +end + +local function drawConfirmationMenu() + local x = 22 + local y = 12 + lcd.clear() + lcd.drawText(48, 1, "Ready to go?", 0); + lcd.drawFilledRectangle(0, 0, LCD_W, 9, 0) + x, y = drawNextLine(x, y, "Throttle:", thrCH1) + x, y = drawNextLine(x, y, "Roll:", rollCH1) + x, y = drawNextLine(x, y, "Pitch:", pitchCH1) + x, y = drawNextLine(x, y, "Yaw:", yawCH1) + lcd.drawText(48, LCD_H-8, "[Enter Long] to confirm", 0); + lcd.drawFilledRectangle(0, LCD_H-9, LCD_W, 9, 0) + lcd.drawPixmap(LCD_W-18, 0, "confirm-tick.bmp") + lcd.drawPixmap(0, LCD_H-17, "confirm-plane.bmp") + fieldsMax = 0 +end + +local function addMix(channel, input, name, weight, index) + local mix = { source=input, name=name } + if weight ~= nil then + mix.weight = weight + end + if index == nil then + index = 0 + end + model.insertMix(channel, index, mix) +end + +local function applySettings() + model.defaultInputs() + model.deleteMixes() + addMix(thrCH1, MIXSRC_FIRST_INPUT+defaultChannel(2), "Throttle") + addMix(rollCH1, MIXSRC_FIRST_INPUT+defaultChannel(3), "Roll") + addMix(yawCH1, MIXSRC_FIRST_INPUT+defaultChannel(0), "Yaw") + addMix(pitchCH1, MIXSRC_FIRST_INPUT+defaultChannel(1), "Pitch") +end + +local function confirmationMenu(event) + if dirty then + dirty = false + drawConfirmationMenu() + end + + navigate(event, fieldsMax, YAW_PAGE, page) + + if event == EVT_EXIT_BREAK then + return 2 + elseif event == EVT_ENTER_LONG then + killEvents(event) + applySettings() + return 2 + else + return 0 + end +end + +-- Main +local function run(event) + if event == nil then + error("Cannot be run as a model script!") + end + if page == THROTTLE_PAGE then + throttleMenu(event) + elseif page == ROLL_PAGE then + rollMenu(event) + elseif page == YAW_PAGE then + yawMenu(event) + elseif page == PITCH_PAGE then + pitchMenu(event) + elseif page == CONFIRMATION_PAGE then + return confirmationMenu(event) + end + return 0 +end + +return { init=init, run=run } diff --git a/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/plane.lua b/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/plane.lua index e66a9b03f..d3ca0d2de 100644 --- a/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/plane.lua +++ b/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/plane.lua @@ -1,567 +1,567 @@ --- Plane Wizard pages -local ENGINE_PAGE = 0 -local AILERONS_PAGE = 1 -local FLAPERONS_PAGE = 2 -local BRAKES_PAGE = 3 -local TAIL_PAGE = 4 -local CONFIRMATION_PAGE = 5 - --- Navigation variables -local page = ENGINE_PAGE -local dirty = true -local edit = false -local field = 0 -local fieldsMax = 0 - --- Model settings -local engineMode = 1 -local thrCH1 = 0 -local aileronsMode = 1 -local ailCH1 = 0 -local ailCH2 = 4 -local flapsMode = 0 -local flapsCH1 = 5 -local flapsCH2 = 6 -local brakesMode = 0 -local brakesCH1 = 8 -local brakesCH2 = 9 -local tailMode = 1 -local eleCH1 = 0 -local eleCH2 = 7 -local rudCH1 = 0 -local servoPage = nil - --- Common functions -local lastBlink = 0 -local function blinkChanged() - local time = getTime() % 128 - local blink = (time - time % 64) / 64 - if blink ~= lastBlink then - lastBlink = blink - return true - else - return false - end -end - -local function fieldIncDec(event, value, max, force) - if edit or force==true then - if event == EVT_PLUS_BREAK or event == EVT_ROT_LEFT then - value = (value + max) - dirty = true - elseif event == EVT_MINUS_BREAK or event == EVT_ROT_RIGHT then - value = (value + max + 2) - dirty = true - end - value = (value % (max+1)) - end - return value -end - -local function valueIncDec(event, value, min, max) - if edit then - if event == EVT_PLUS_FIRST or event == EVT_PLUS_REPT or event == EVT_ROT_RIGHT then - if value < max then - value = (value + 1) - dirty = true - end - elseif event == EVT_MINUS_FIRST or event == EVT_MINUS_REPT or event == EVT_ROT_LEFT then - if value > min then - value = (value - 1) - dirty = true - end - end - end - return value -end - -local function navigate(event, fieldMax, prevPage, nextPage) - if event == EVT_ENTER_BREAK then - edit = not edit - dirty = true - elseif edit then - if event == EVT_EXIT_BREAK then - edit = false - dirty = true - elseif not dirty then - dirty = blinkChanged() - end - else - if event == EVT_PAGE_BREAK then - page = nextPage - field = 0 - dirty = true - elseif event == EVT_PAGE_LONG then - page = prevPage - field = 0 - killEvents(event); - dirty = true - else - field = fieldIncDec(event, field, fieldMax, true) - end - end -end - -local function getFieldFlags(position) - flags = 0 - if field == position then - flags = INVERS - if edit then - flags = INVERS + BLINK - end - end - return flags -end - -local function channelIncDec(event, value) - if not edit and event==EVT_MENU_BREAK then - servoPage = value - dirty = true - else - value = valueIncDec(event, value, 0, 15) - end - return value -end - --- Init function -local function init() - rudCH1 = defaultChannel(0) - eleCH1 = defaultChannel(1) - thrCH1 = defaultChannel(2) - ailCH1 = defaultChannel(3) -end - --- Engine Menu -local engineModeItems = {"No", "Yes..."} -local function drawEngineMenu() - lcd.clear() - lcd.drawText(1, 0, "Has your model got an engine?", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, engineModeItems, engineMode, getFieldFlags(0)) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - if engineMode == 1 then - -- 1 channel - lcd.drawPixmap(132, 8, "engine-1.bmp") - lcd.drawText(25, LCD_H-16, "Assign channel", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(151, LCD_H-8, MIXSRC_CH1+thrCH1, getFieldFlags(1)) - fieldsMax = 1 - else - -- No engine - lcd.drawPixmap(132, 8, "engine-0.bmp") - fieldsMax = 0 - end -end - -local function engineMenu(event) - if dirty then - dirty = false - drawEngineMenu() - end - - navigate(event, fieldsMax, page, page+1) - - if field==0 then - engineMode = fieldIncDec(event, engineMode, 1) - elseif field==1 then - thrCH1 = channelIncDec(event, thrCH1) - end -end - --- Ailerons Menu -local aileronsModeItems = {"No", "Yes...", "Yes, 2 channels..."} -local function drawAileronsMenu() - lcd.clear() - lcd.drawText(1, 0, "Has your model got ailerons?", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, aileronsModeItems, aileronsMode, getFieldFlags(0)) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - if aileronsMode == 2 then - -- 2 channels - lcd.drawPixmap(112, 8, "ailerons-2.bmp") - lcd.drawText(20, LCD_H-16, "Assign channels", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(116, LCD_H-8, MIXSRC_CH1+ailCH1, getFieldFlags(1)) - lcd.drawSource(175, LCD_H-8, MIXSRC_CH1+ailCH2, getFieldFlags(2)) - fieldsMax = 2 - elseif aileronsMode == 1 then - -- 1 channel - lcd.drawPixmap(112, 8, "ailerons-1.bmp") - lcd.drawText(25, LCD_H-16, "Assign channel", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(151, LCD_H-8, MIXSRC_CH1+ailCH1, getFieldFlags(1)) - fieldsMax = 1 - else - -- No ailerons - lcd.drawPixmap(112, 8, "ailerons-0.bmp") - fieldsMax = 0 - end -end - -local function aileronsMenu(event) - if dirty then - dirty = false - drawAileronsMenu() - end - - navigate(event, fieldsMax, page-1, page+1) - - if field==0 then - aileronsMode = fieldIncDec(event, aileronsMode, 2) - elseif field==1 then - ailCH1 = channelIncDec(event, ailCH1) - elseif field==2 then - ailCH2 = channelIncDec(event, ailCH2) - end -end - --- Flaps Menu -local flapsModeItems = {"No", "Yes...", "Yes, 2 channels..."} -local function drawFlapsMenu() - lcd.clear() - lcd.drawText(1, 0, "Has your model got flaps?", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, flapsModeItems, flapsMode, getFieldFlags(0)) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - if flapsMode == 0 then - -- no flaps - lcd.drawPixmap(112, 8, "ailerons-0.bmp") - fieldsMax = 0 - elseif flapsMode == 1 then - -- 1 channel - lcd.drawPixmap(112, 8, "flaps-1.bmp") - lcd.drawText(25, LCD_H-16, "Assign channel", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(151, LCD_H-8, MIXSRC_CH1+flapsCH1, getFieldFlags(1)) - fieldsMax = 1 - elseif flapsMode == 2 then - -- 2 channels - lcd.drawPixmap(112, 8, "flaps-2.bmp") - lcd.drawText(20, LCD_H-16, "Assign channels", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(116, LCD_H-8, MIXSRC_CH1+flapsCH1, getFieldFlags(1)) - lcd.drawSource(175, LCD_H-8, MIXSRC_CH1+flapsCH2, getFieldFlags(2)) - fieldsMax = 2 - end -end - -local function flapsMenu(event) - if dirty then - dirty = false - drawFlapsMenu() - end - - navigate(event, fieldsMax, page-1, page+1) - - if field==0 then - flapsMode = fieldIncDec(event, flapsMode, 2) - elseif field==1 then - flapsCH1 = channelIncDec(event, flapsCH1) - elseif field==2 then - flapsCH2 = channelIncDec(event, flapsCH2) - end -end - --- Airbrakes Menu -local brakesModeItems = {"No", "Yes...", "Yes, 2 channels..."} -local function drawBrakesMenu() - lcd.clear() - lcd.drawText(1, 0, "Has your model got air brakes?", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, brakesModeItems, brakesMode, getFieldFlags(0)) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - if brakesMode == 0 then - -- no brakes - lcd.drawPixmap(112, 8, "ailerons-0.bmp") - fieldsMax = 0 - elseif brakesMode == 1 then - -- 1 channel - lcd.drawPixmap(112, 8, "brakes-1.bmp") - lcd.drawText(25, LCD_H-16, "Assign channel", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(151, LCD_H-8, MIXSRC_CH1+brakesCH1, getFieldFlags(1)) - fieldsMax = 1 - elseif brakesMode == 2 then - -- 2 channels - lcd.drawPixmap(112, 8, "brakes-2.bmp") - lcd.drawText(20, LCD_H-16, "Assign channels", 0); - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawSource(116, LCD_H-8, MIXSRC_CH1+brakesCH1, getFieldFlags(1)) - lcd.drawSource(175, LCD_H-8, MIXSRC_CH1+brakesCH2, getFieldFlags(2)) - fieldsMax = 2 - end -end - -local function brakesMenu(event) - if dirty then - dirty = false - drawBrakesMenu() - end - - navigate(event, fieldsMax, page-1, page+1) - - if field==0 then - brakesMode = fieldIncDec(event, brakesMode, 2) - elseif field==1 then - brakesCH1 = channelIncDec(event, brakesCH1) - elseif field==2 then - brakesCH2 = channelIncDec(event, brakesCH2) - end -end - --- Tail Menu -local tailModeItems = {"Ele(1ch), no Rud...", "Ele(1ch) + Rud...", "Ele(2ch) + Rud...", "V-Tail..."} -local function drawTailMenu() - lcd.clear() - lcd.drawText(1, 0, "Which is the tail config on your model?", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawCombobox(0, 8, LCD_W/2, tailModeItems, tailMode, getFieldFlags(0)) - lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - if tailMode == 0 then - -- Elevator(1ch), no rudder... - lcd.drawPixmap(112, 8, "tail-e.bmp") - lcd.drawText(25, LCD_H-16, "Assign channel", 0); - lcd.drawSource(175, 30, MIXSRC_CH1+eleCH1, getFieldFlags(1)) - fieldsMax = 1 - elseif tailMode == 1 then - -- Elevator(1ch) + rudder... - lcd.drawPixmap(112, 8, "tail-er.bmp") - lcd.drawText(20, LCD_H-16, "Assign channels", 0); - lcd.drawSource(175, 30, MIXSRC_CH1+eleCH1, getFieldFlags(1)) - lcd.drawSource(175, 10, MIXSRC_CH1+rudCH1, getFieldFlags(2)) - fieldsMax = 2 - elseif tailMode == 2 then - -- Elevator(2ch) + rudder... - lcd.drawPixmap(112, 8, "tail-eer.bmp") - lcd.drawText(20, LCD_H-16, "Assign channels", 0); - lcd.drawSource(175, 30, MIXSRC_CH1+eleCH1, getFieldFlags(1)) - lcd.drawSource(175, 20, MIXSRC_CH1+eleCH2, getFieldFlags(2)) - lcd.drawSource(175, 10, MIXSRC_CH1+rudCH1, getFieldFlags(3)) - fieldsMax = 3 - else - -- V-Tail... - lcd.drawPixmap(112, 8, "tail-v.bmp") - lcd.drawText(20, LCD_H-16, "Assign channels", 0); - lcd.drawSource(175, 20, MIXSRC_CH1+eleCH1, getFieldFlags(1)) - lcd.drawSource(175, 10, MIXSRC_CH1+eleCH2, getFieldFlags(2)) - fieldsMax = 2 - end -end - -local function tailMenu(event) - if dirty then - dirty = false - drawTailMenu() - end - - navigate(event, fieldsMax, page-1, page+1) - - if field==0 then - tailMode = fieldIncDec(event, tailMode, 3) - elseif field==1 then - eleCH1 = channelIncDec(event, eleCH1) - elseif (field==2 and tailMode==1) or field==3 then - rudCH1 = channelIncDec(event, rudCH1) - elseif field==2 then - eleCH2 = channelIncDec(event, eleCH2) - end -end - --- Servo (limits) Menu -local function drawServoMenu(limits) - lcd.clear() - lcd.drawSource(1, 0, MIXSRC_CH1+servoPage, 0) - lcd.drawText(25, 0, "servo min/max/center/direction?", 0) - lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) - lcd.drawLine(LCD_W/2-1, 8, LCD_W/2-1, LCD_H-1, DOTTED, 0) - lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); - lcd.drawPixmap(122, 8, "servo.bmp") - lcd.drawNumber(140, 35, limits.min, PREC1+getFieldFlags(0)); - lcd.drawNumber(205, 35, limits.max, PREC1+getFieldFlags(1)); - lcd.drawNumber(170, 9, limits.offset, PREC1+getFieldFlags(2)); - if limits.revert == 0 then - lcd.drawText(129, 50, "\126", getFieldFlags(3)); - else - lcd.drawText(129, 50, "\127", getFieldFlags(3)); - end - fieldsMax = 3 -end - -local function servoMenu(event) - local limits = model.getOutput(servoPage) - - if dirty then - dirty = false - drawServoMenu(limits) - end - - navigate(event, fieldsMax, page, page) - - if edit then - if field==0 then - limits.min = valueIncDec(event, limits.min, -1000, 0) - elseif field==1 then - limits.max = valueIncDec(event, limits.max, 0, 1000) - elseif field==2 then - limits.offset = valueIncDec(event, limits.offset, -1000, 1000) - elseif field==3 then - limits.revert = fieldIncDec(event, limits.revert, 1) - end - model.setOutput(servoPage, limits) - elseif event == EVT_EXIT_BREAK then - servoPage = nil - dirty = true - end -end - --- Confirmation Menu -local function drawNextLine(x, y, label, channel) - lcd.drawText(x, y, label, 0); - lcd.drawSource(x+52, y, MIXSRC_CH1+channel, 0) - y = y + 8 - if y > 50 then - y = 12 - x = 120 - end - return x, y -end - -local function drawConfirmationMenu() - local x = 22 - local y = 12 - lcd.clear() - lcd.drawText(48, 1, "Ready to go?", 0); - lcd.drawFilledRectangle(0, 0, LCD_W, 9, 0) - if engineMode == 1 then - x, y = drawNextLine(x, y, "Throttle:", thrCH1) - end - if aileronsMode > 0 then - x, y = drawNextLine(x, y, "Ailerons:", ailCH1) - if aileronsMode == 2 then - x, y = drawNextLine(x, y, "Ailerons:", ailCH2) - end - end - if flapsMode > 0 then - x, y = drawNextLine(x, y, "Flaps:", flapsCH1) - if flapsMode == 2 then - x, y = drawNextLine(x, y, "Flaps:", flapsCH2) - end - end - if brakesMode > 0 then - x, y = drawNextLine(x, y, "Brakes:", brakesCH1) - if brakesMode == 2 then - x, y = drawNextLine(x, y, "Brakes:", brakesCH2) - end - end - if tailMode == 3 then - x, y = drawNextLine(x, y, "V-Tail:", eleCH1) - x, y = drawNextLine(x, y, "V-Tail:", eleCH2) - else - x, y = drawNextLine(x, y, "Elevator:", eleCH1) - if tailMode == 2 then - x, y = drawNextLine(x, y, "Elevator:", eleCH2) - end - drawNextLine(x, y, "Rudder:", rudCH1) - end - lcd.drawText(48, LCD_H-8, "[Enter Long] to confirm", 0); - lcd.drawFilledRectangle(0, LCD_H-9, LCD_W, 9, 0) - lcd.drawPixmap(LCD_W-18, 0, "confirm-tick.bmp") - lcd.drawPixmap(0, LCD_H-17, "confirm-plane.bmp") - fieldsMax = 0 -end - -local function addMix(channel, input, name, weight, index) - local mix = { source=input, name=name } - if weight ~= nil then - mix.weight = weight - end - if index == nil then - index = 0 - end - model.insertMix(channel, index, mix) -end - -local function applySettings() - model.defaultInputs() - model.deleteMixes() - if engineMode > 0 then - addMix(thrCH1, MIXSRC_FIRST_INPUT+defaultChannel(2), "Engine") - end - if aileronsMode > 0 then - addMix(ailCH1, MIXSRC_FIRST_INPUT+defaultChannel(3), "Aileron") - if aileronsMode == 2 then - addMix(ailCH2, MIXSRC_FIRST_INPUT+defaultChannel(3), "Aileron", -100) - end - end - if flapsMode > 0 then - addMix(flapsCH1, MIXSRC_SA, "Flap") - if flapsMode == 2 then - addMix(flapsCH2, MIXSRC_SA, "Flap") - end - end - if brakesMode > 0 then - addMix(brakesCH1, MIXSRC_SE, "Brake") - if brakesMode == 2 then - addMix(brakesCH2, MIXSRC_SE, "Brake") - end - end - if tailMode == 3 then - addMix(eleCH1, MIXSRC_FIRST_INPUT+defaultChannel(1), "V-Tail-E", 50) - addMix(eleCH1, MIXSRC_FIRST_INPUT+defaultChannel(0), "V-Tail-R", 50, 1) - addMix(eleCH2, MIXSRC_FIRST_INPUT+defaultChannel(1), "V-Tail-E", 50) - addMix(eleCH2, MIXSRC_FIRST_INPUT+defaultChannel(0), "V-Tail-R", -50, 1) - else - addMix(eleCH1, MIXSRC_FIRST_INPUT+defaultChannel(1), "Elevator") - if tailMode > 0 then - addMix(rudCH1, MIXSRC_FIRST_INPUT+defaultChannel(0), "Rudder") - end - if tailMode == 2 then - addMix(eleCH2, MIXSRC_FIRST_INPUT+defaultChannel(1), "Elevator") - end - end -end - -local function confirmationMenu(event) - if dirty then - dirty = false - drawConfirmationMenu() - end - - navigate(event, fieldsMax, TAIL_PAGE, page) - - if event == EVT_EXIT_BREAK then - return 2 - elseif event == EVT_ENTER_LONG then - killEvents(event) - applySettings() - return 2 - else - return 0 - end -end - --- Main -local function run(event) - if event == nil then - error("Cannot be run as a model script!") - end - if servoPage ~= nil then - servoMenu(event) - elseif page == ENGINE_PAGE then - engineMenu(event) - elseif page == AILERONS_PAGE then - aileronsMenu(event) - elseif page == FLAPERONS_PAGE then - flapsMenu(event) - elseif page == BRAKES_PAGE then - brakesMenu(event) - elseif page == TAIL_PAGE then - tailMenu(event) - elseif page == CONFIRMATION_PAGE then - return confirmationMenu(event) - end - return 0 -end - -return { init=init, run=run } +-- Plane Wizard pages +local ENGINE_PAGE = 0 +local AILERONS_PAGE = 1 +local FLAPERONS_PAGE = 2 +local BRAKES_PAGE = 3 +local TAIL_PAGE = 4 +local CONFIRMATION_PAGE = 5 + +-- Navigation variables +local page = ENGINE_PAGE +local dirty = true +local edit = false +local field = 0 +local fieldsMax = 0 + +-- Model settings +local engineMode = 1 +local thrCH1 = 0 +local aileronsMode = 1 +local ailCH1 = 0 +local ailCH2 = 4 +local flapsMode = 0 +local flapsCH1 = 5 +local flapsCH2 = 6 +local brakesMode = 0 +local brakesCH1 = 8 +local brakesCH2 = 9 +local tailMode = 1 +local eleCH1 = 0 +local eleCH2 = 7 +local rudCH1 = 0 +local servoPage = nil + +-- Common functions +local lastBlink = 0 +local function blinkChanged() + local time = getTime() % 128 + local blink = (time - time % 64) / 64 + if blink ~= lastBlink then + lastBlink = blink + return true + else + return false + end +end + +local function fieldIncDec(event, value, max, force) + if edit or force==true then + if event == EVT_PLUS_BREAK or event == EVT_ROT_LEFT then + value = (value + max) + dirty = true + elseif event == EVT_MINUS_BREAK or event == EVT_ROT_RIGHT then + value = (value + max + 2) + dirty = true + end + value = (value % (max+1)) + end + return value +end + +local function valueIncDec(event, value, min, max) + if edit then + if event == EVT_PLUS_FIRST or event == EVT_PLUS_REPT or event == EVT_ROT_RIGHT then + if value < max then + value = (value + 1) + dirty = true + end + elseif event == EVT_MINUS_FIRST or event == EVT_MINUS_REPT or event == EVT_ROT_LEFT then + if value > min then + value = (value - 1) + dirty = true + end + end + end + return value +end + +local function navigate(event, fieldMax, prevPage, nextPage) + if event == EVT_ENTER_BREAK then + edit = not edit + dirty = true + elseif edit then + if event == EVT_EXIT_BREAK then + edit = false + dirty = true + elseif not dirty then + dirty = blinkChanged() + end + else + if event == EVT_PAGE_BREAK then + page = nextPage + field = 0 + dirty = true + elseif event == EVT_PAGE_LONG then + page = prevPage + field = 0 + killEvents(event); + dirty = true + else + field = fieldIncDec(event, field, fieldMax, true) + end + end +end + +local function getFieldFlags(position) + flags = 0 + if field == position then + flags = INVERS + if edit then + flags = INVERS + BLINK + end + end + return flags +end + +local function channelIncDec(event, value) + if not edit and event==EVT_MENU_BREAK then + servoPage = value + dirty = true + else + value = valueIncDec(event, value, 0, 15) + end + return value +end + +-- Init function +local function init() + rudCH1 = defaultChannel(0) + eleCH1 = defaultChannel(1) + thrCH1 = defaultChannel(2) + ailCH1 = defaultChannel(3) +end + +-- Engine Menu +local engineModeItems = {"No", "Yes..."} +local function drawEngineMenu() + lcd.clear() + lcd.drawText(1, 0, "Has your model got an engine?", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, engineModeItems, engineMode, getFieldFlags(0)) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + if engineMode == 1 then + -- 1 channel + lcd.drawPixmap(132, 8, "engine-1.bmp") + lcd.drawText(25, LCD_H-16, "Assign channel", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(151, LCD_H-8, MIXSRC_CH1+thrCH1, getFieldFlags(1)) + fieldsMax = 1 + else + -- No engine + lcd.drawPixmap(132, 8, "engine-0.bmp") + fieldsMax = 0 + end +end + +local function engineMenu(event) + if dirty then + dirty = false + drawEngineMenu() + end + + navigate(event, fieldsMax, page, page+1) + + if field==0 then + engineMode = fieldIncDec(event, engineMode, 1) + elseif field==1 then + thrCH1 = channelIncDec(event, thrCH1) + end +end + +-- Ailerons Menu +local aileronsModeItems = {"No", "Yes...", "Yes, 2 channels..."} +local function drawAileronsMenu() + lcd.clear() + lcd.drawText(1, 0, "Has your model got ailerons?", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, aileronsModeItems, aileronsMode, getFieldFlags(0)) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + if aileronsMode == 2 then + -- 2 channels + lcd.drawPixmap(112, 8, "ailerons-2.bmp") + lcd.drawText(20, LCD_H-16, "Assign channels", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(116, LCD_H-8, MIXSRC_CH1+ailCH1, getFieldFlags(1)) + lcd.drawSource(175, LCD_H-8, MIXSRC_CH1+ailCH2, getFieldFlags(2)) + fieldsMax = 2 + elseif aileronsMode == 1 then + -- 1 channel + lcd.drawPixmap(112, 8, "ailerons-1.bmp") + lcd.drawText(25, LCD_H-16, "Assign channel", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(151, LCD_H-8, MIXSRC_CH1+ailCH1, getFieldFlags(1)) + fieldsMax = 1 + else + -- No ailerons + lcd.drawPixmap(112, 8, "ailerons-0.bmp") + fieldsMax = 0 + end +end + +local function aileronsMenu(event) + if dirty then + dirty = false + drawAileronsMenu() + end + + navigate(event, fieldsMax, page-1, page+1) + + if field==0 then + aileronsMode = fieldIncDec(event, aileronsMode, 2) + elseif field==1 then + ailCH1 = channelIncDec(event, ailCH1) + elseif field==2 then + ailCH2 = channelIncDec(event, ailCH2) + end +end + +-- Flaps Menu +local flapsModeItems = {"No", "Yes...", "Yes, 2 channels..."} +local function drawFlapsMenu() + lcd.clear() + lcd.drawText(1, 0, "Has your model got flaps?", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, flapsModeItems, flapsMode, getFieldFlags(0)) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + if flapsMode == 0 then + -- no flaps + lcd.drawPixmap(112, 8, "ailerons-0.bmp") + fieldsMax = 0 + elseif flapsMode == 1 then + -- 1 channel + lcd.drawPixmap(112, 8, "flaps-1.bmp") + lcd.drawText(25, LCD_H-16, "Assign channel", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(151, LCD_H-8, MIXSRC_CH1+flapsCH1, getFieldFlags(1)) + fieldsMax = 1 + elseif flapsMode == 2 then + -- 2 channels + lcd.drawPixmap(112, 8, "flaps-2.bmp") + lcd.drawText(20, LCD_H-16, "Assign channels", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(116, LCD_H-8, MIXSRC_CH1+flapsCH1, getFieldFlags(1)) + lcd.drawSource(175, LCD_H-8, MIXSRC_CH1+flapsCH2, getFieldFlags(2)) + fieldsMax = 2 + end +end + +local function flapsMenu(event) + if dirty then + dirty = false + drawFlapsMenu() + end + + navigate(event, fieldsMax, page-1, page+1) + + if field==0 then + flapsMode = fieldIncDec(event, flapsMode, 2) + elseif field==1 then + flapsCH1 = channelIncDec(event, flapsCH1) + elseif field==2 then + flapsCH2 = channelIncDec(event, flapsCH2) + end +end + +-- Airbrakes Menu +local brakesModeItems = {"No", "Yes...", "Yes, 2 channels..."} +local function drawBrakesMenu() + lcd.clear() + lcd.drawText(1, 0, "Has your model got air brakes?", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, brakesModeItems, brakesMode, getFieldFlags(0)) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + if brakesMode == 0 then + -- no brakes + lcd.drawPixmap(112, 8, "ailerons-0.bmp") + fieldsMax = 0 + elseif brakesMode == 1 then + -- 1 channel + lcd.drawPixmap(112, 8, "brakes-1.bmp") + lcd.drawText(25, LCD_H-16, "Assign channel", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(151, LCD_H-8, MIXSRC_CH1+brakesCH1, getFieldFlags(1)) + fieldsMax = 1 + elseif brakesMode == 2 then + -- 2 channels + lcd.drawPixmap(112, 8, "brakes-2.bmp") + lcd.drawText(20, LCD_H-16, "Assign channels", 0); + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawSource(116, LCD_H-8, MIXSRC_CH1+brakesCH1, getFieldFlags(1)) + lcd.drawSource(175, LCD_H-8, MIXSRC_CH1+brakesCH2, getFieldFlags(2)) + fieldsMax = 2 + end +end + +local function brakesMenu(event) + if dirty then + dirty = false + drawBrakesMenu() + end + + navigate(event, fieldsMax, page-1, page+1) + + if field==0 then + brakesMode = fieldIncDec(event, brakesMode, 2) + elseif field==1 then + brakesCH1 = channelIncDec(event, brakesCH1) + elseif field==2 then + brakesCH2 = channelIncDec(event, brakesCH2) + end +end + +-- Tail Menu +local tailModeItems = {"Ele(1ch), no Rud...", "Ele(1ch) + Rud...", "Ele(2ch) + Rud...", "V-Tail..."} +local function drawTailMenu() + lcd.clear() + lcd.drawText(1, 0, "Which is the tail config on your model?", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawCombobox(0, 8, LCD_W/2, tailModeItems, tailMode, getFieldFlags(0)) + lcd.drawLine(LCD_W/2-1, 18, LCD_W/2-1, LCD_H-1, DOTTED, 0) + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + if tailMode == 0 then + -- Elevator(1ch), no rudder... + lcd.drawPixmap(112, 8, "tail-e.bmp") + lcd.drawText(25, LCD_H-16, "Assign channel", 0); + lcd.drawSource(175, 30, MIXSRC_CH1+eleCH1, getFieldFlags(1)) + fieldsMax = 1 + elseif tailMode == 1 then + -- Elevator(1ch) + rudder... + lcd.drawPixmap(112, 8, "tail-er.bmp") + lcd.drawText(20, LCD_H-16, "Assign channels", 0); + lcd.drawSource(175, 30, MIXSRC_CH1+eleCH1, getFieldFlags(1)) + lcd.drawSource(175, 10, MIXSRC_CH1+rudCH1, getFieldFlags(2)) + fieldsMax = 2 + elseif tailMode == 2 then + -- Elevator(2ch) + rudder... + lcd.drawPixmap(112, 8, "tail-eer.bmp") + lcd.drawText(20, LCD_H-16, "Assign channels", 0); + lcd.drawSource(175, 30, MIXSRC_CH1+eleCH1, getFieldFlags(1)) + lcd.drawSource(175, 20, MIXSRC_CH1+eleCH2, getFieldFlags(2)) + lcd.drawSource(175, 10, MIXSRC_CH1+rudCH1, getFieldFlags(3)) + fieldsMax = 3 + else + -- V-Tail... + lcd.drawPixmap(112, 8, "tail-v.bmp") + lcd.drawText(20, LCD_H-16, "Assign channels", 0); + lcd.drawSource(175, 20, MIXSRC_CH1+eleCH1, getFieldFlags(1)) + lcd.drawSource(175, 10, MIXSRC_CH1+eleCH2, getFieldFlags(2)) + fieldsMax = 2 + end +end + +local function tailMenu(event) + if dirty then + dirty = false + drawTailMenu() + end + + navigate(event, fieldsMax, page-1, page+1) + + if field==0 then + tailMode = fieldIncDec(event, tailMode, 3) + elseif field==1 then + eleCH1 = channelIncDec(event, eleCH1) + elseif (field==2 and tailMode==1) or field==3 then + rudCH1 = channelIncDec(event, rudCH1) + elseif field==2 then + eleCH2 = channelIncDec(event, eleCH2) + end +end + +-- Servo (limits) Menu +local function drawServoMenu(limits) + lcd.clear() + lcd.drawSource(1, 0, MIXSRC_CH1+servoPage, 0) + lcd.drawText(25, 0, "servo min/max/center/direction?", 0) + lcd.drawFilledRectangle(0, 0, LCD_W, 8, GREY_DEFAULT+FILL_WHITE) + lcd.drawLine(LCD_W/2-1, 8, LCD_W/2-1, LCD_H-1, DOTTED, 0) + lcd.drawText(LCD_W/2-19, LCD_H-8, ">>>", 0); + lcd.drawPixmap(122, 8, "servo.bmp") + lcd.drawNumber(140, 35, limits.min, PREC1+getFieldFlags(0)); + lcd.drawNumber(205, 35, limits.max, PREC1+getFieldFlags(1)); + lcd.drawNumber(170, 9, limits.offset, PREC1+getFieldFlags(2)); + if limits.revert == 0 then + lcd.drawText(129, 50, "\126", getFieldFlags(3)); + else + lcd.drawText(129, 50, "\127", getFieldFlags(3)); + end + fieldsMax = 3 +end + +local function servoMenu(event) + local limits = model.getOutput(servoPage) + + if dirty then + dirty = false + drawServoMenu(limits) + end + + navigate(event, fieldsMax, page, page) + + if edit then + if field==0 then + limits.min = valueIncDec(event, limits.min, -1000, 0) + elseif field==1 then + limits.max = valueIncDec(event, limits.max, 0, 1000) + elseif field==2 then + limits.offset = valueIncDec(event, limits.offset, -1000, 1000) + elseif field==3 then + limits.revert = fieldIncDec(event, limits.revert, 1) + end + model.setOutput(servoPage, limits) + elseif event == EVT_EXIT_BREAK then + servoPage = nil + dirty = true + end +end + +-- Confirmation Menu +local function drawNextLine(x, y, label, channel) + lcd.drawText(x, y, label, 0); + lcd.drawSource(x+52, y, MIXSRC_CH1+channel, 0) + y = y + 8 + if y > 50 then + y = 12 + x = 120 + end + return x, y +end + +local function drawConfirmationMenu() + local x = 22 + local y = 12 + lcd.clear() + lcd.drawText(48, 1, "Ready to go?", 0); + lcd.drawFilledRectangle(0, 0, LCD_W, 9, 0) + if engineMode == 1 then + x, y = drawNextLine(x, y, "Throttle:", thrCH1) + end + if aileronsMode > 0 then + x, y = drawNextLine(x, y, "Ailerons:", ailCH1) + if aileronsMode == 2 then + x, y = drawNextLine(x, y, "Ailerons:", ailCH2) + end + end + if flapsMode > 0 then + x, y = drawNextLine(x, y, "Flaps:", flapsCH1) + if flapsMode == 2 then + x, y = drawNextLine(x, y, "Flaps:", flapsCH2) + end + end + if brakesMode > 0 then + x, y = drawNextLine(x, y, "Brakes:", brakesCH1) + if brakesMode == 2 then + x, y = drawNextLine(x, y, "Brakes:", brakesCH2) + end + end + if tailMode == 3 then + x, y = drawNextLine(x, y, "V-Tail:", eleCH1) + x, y = drawNextLine(x, y, "V-Tail:", eleCH2) + else + x, y = drawNextLine(x, y, "Elevator:", eleCH1) + if tailMode == 2 then + x, y = drawNextLine(x, y, "Elevator:", eleCH2) + end + drawNextLine(x, y, "Rudder:", rudCH1) + end + lcd.drawText(48, LCD_H-8, "[Enter Long] to confirm", 0); + lcd.drawFilledRectangle(0, LCD_H-9, LCD_W, 9, 0) + lcd.drawPixmap(LCD_W-18, 0, "confirm-tick.bmp") + lcd.drawPixmap(0, LCD_H-17, "confirm-plane.bmp") + fieldsMax = 0 +end + +local function addMix(channel, input, name, weight, index) + local mix = { source=input, name=name } + if weight ~= nil then + mix.weight = weight + end + if index == nil then + index = 0 + end + model.insertMix(channel, index, mix) +end + +local function applySettings() + model.defaultInputs() + model.deleteMixes() + if engineMode > 0 then + addMix(thrCH1, MIXSRC_FIRST_INPUT+defaultChannel(2), "Engine") + end + if aileronsMode > 0 then + addMix(ailCH1, MIXSRC_FIRST_INPUT+defaultChannel(3), "Aileron") + if aileronsMode == 2 then + addMix(ailCH2, MIXSRC_FIRST_INPUT+defaultChannel(3), "Aileron", -100) + end + end + if flapsMode > 0 then + addMix(flapsCH1, MIXSRC_SA, "Flap") + if flapsMode == 2 then + addMix(flapsCH2, MIXSRC_SA, "Flap") + end + end + if brakesMode > 0 then + addMix(brakesCH1, MIXSRC_SE, "Brake") + if brakesMode == 2 then + addMix(brakesCH2, MIXSRC_SE, "Brake") + end + end + if tailMode == 3 then + addMix(eleCH1, MIXSRC_FIRST_INPUT+defaultChannel(1), "V-Tail-E", 50) + addMix(eleCH1, MIXSRC_FIRST_INPUT+defaultChannel(0), "V-Tail-R", 50, 1) + addMix(eleCH2, MIXSRC_FIRST_INPUT+defaultChannel(1), "V-Tail-E", 50) + addMix(eleCH2, MIXSRC_FIRST_INPUT+defaultChannel(0), "V-Tail-R", -50, 1) + else + addMix(eleCH1, MIXSRC_FIRST_INPUT+defaultChannel(1), "Elevator") + if tailMode > 0 then + addMix(rudCH1, MIXSRC_FIRST_INPUT+defaultChannel(0), "Rudder") + end + if tailMode == 2 then + addMix(eleCH2, MIXSRC_FIRST_INPUT+defaultChannel(1), "Elevator") + end + end +end + +local function confirmationMenu(event) + if dirty then + dirty = false + drawConfirmationMenu() + end + + navigate(event, fieldsMax, TAIL_PAGE, page) + + if event == EVT_EXIT_BREAK then + return 2 + elseif event == EVT_ENTER_LONG then + killEvents(event) + applySettings() + return 2 + else + return 0 + end +end + +-- Main +local function run(event) + if event == nil then + error("Cannot be run as a model script!") + end + if servoPage ~= nil then + servoMenu(event) + elseif page == ENGINE_PAGE then + engineMenu(event) + elseif page == AILERONS_PAGE then + aileronsMenu(event) + elseif page == FLAPERONS_PAGE then + flapsMenu(event) + elseif page == BRAKES_PAGE then + brakesMenu(event) + elseif page == TAIL_PAGE then + tailMenu(event) + elseif page == CONFIRMATION_PAGE then + return confirmationMenu(event) + end + return 0 +end + +return { init=init, run=run } diff --git a/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/wizard.lua b/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/wizard.lua index a66c13b51..55bd5f1be 100644 --- a/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/wizard.lua +++ b/radio/sdcard/taranis-x9/SCRIPTS/WIZARD/wizard.lua @@ -1,74 +1,74 @@ --- Navigation variables -local dirty = true - --- Model types -local modelType = 0 -local MODELTYPE_PLANE = 0 ---local MODELTYPE_HELI = 1 -local MODELTYPE_DELTA = 1 -local MODELTYPE_QUAD = 2 - --- Common functions -local function fieldIncDec(event, value, max) - if event == EVT_PLUS_BREAK or event == EVT_ROT_LEFT or event == EVT_PLUS_REPT then - value = (value + max) - dirty = true - elseif event == EVT_MINUS_BREAK or event == EVT_ROT_RIGHT or event == EVT_MINUS_REPT then - value = (value + max + 2) - dirty = true - end - value = (value % (max+1)) - return value -end - --- Model Type Menu -local function modelTypeSurround(index) - lcd.drawRectangle(12+47*index, 13, 48, 48) - lcd.drawPixmap(17+47*index, 8, "mark.bmp") -end - -local function drawModelChoiceMenu() - lcd.clear() - lcd.drawScreenTitle("", 0, 0) - -- lcd.drawText(58, 13, "Select model type", 0) - lcd.drawPixmap( 16, 17, "plane.bmp") - --lcd.drawPixmap( 63, 17, "heli.bmp") - lcd.drawPixmap(63, 17, "delta.bmp") - lcd.drawPixmap(110, 17, "quadri.bmp") - modelTypeSurround(modelType) -end - -local function modelTypeMenu(event) - if dirty == true then - drawModelChoiceMenu() - dirty = false - end - if event == EVT_ENTER_BREAK then - if modelType == MODELTYPE_PLANE then - return "plane.lua" - elseif modelType == MODELTYPE_HELI then - elseif modelType == MODELTYPE_DELTA then - return "delta.lua" - elseif modelType == MODELTYPE_QUAD then - return "multi.lua" - end - dirty = true - else - modelType = fieldIncDec(event, modelType, 2) - end - return 0 -end - --- Main -local function run(event) - if event == nil then - error("Cannot be run as a model script!") - end - - if event == EVT_EXIT_BREAK then - return 2 - end - return modelTypeMenu(event) -end - -return { run=run } +-- Navigation variables +local dirty = true + +-- Model types +local modelType = 0 +local MODELTYPE_PLANE = 0 +--local MODELTYPE_HELI = 1 +local MODELTYPE_DELTA = 1 +local MODELTYPE_QUAD = 2 + +-- Common functions +local function fieldIncDec(event, value, max) + if event == EVT_PLUS_BREAK or event == EVT_ROT_LEFT or event == EVT_PLUS_REPT then + value = (value + max) + dirty = true + elseif event == EVT_MINUS_BREAK or event == EVT_ROT_RIGHT or event == EVT_MINUS_REPT then + value = (value + max + 2) + dirty = true + end + value = (value % (max+1)) + return value +end + +-- Model Type Menu +local function modelTypeSurround(index) + lcd.drawRectangle(12+47*index, 13, 48, 48) + lcd.drawPixmap(17+47*index, 8, "mark.bmp") +end + +local function drawModelChoiceMenu() + lcd.clear() + lcd.drawScreenTitle("", 0, 0) + -- lcd.drawText(58, 13, "Select model type", 0) + lcd.drawPixmap( 16, 17, "plane.bmp") + --lcd.drawPixmap( 63, 17, "heli.bmp") + lcd.drawPixmap(63, 17, "delta.bmp") + lcd.drawPixmap(110, 17, "quadri.bmp") + modelTypeSurround(modelType) +end + +local function modelTypeMenu(event) + if dirty == true then + drawModelChoiceMenu() + dirty = false + end + if event == EVT_ENTER_BREAK then + if modelType == MODELTYPE_PLANE then + return "plane.lua" + elseif modelType == MODELTYPE_HELI then + elseif modelType == MODELTYPE_DELTA then + return "delta.lua" + elseif modelType == MODELTYPE_QUAD then + return "multi.lua" + end + dirty = true + else + modelType = fieldIncDec(event, modelType, 2) + end + return 0 +end + +-- Main +local function run(event) + if event == nil then + error("Cannot be run as a model script!") + end + + if event == EVT_EXIT_BREAK then + return 2 + end + return modelTypeMenu(event) +end + +return { run=run } diff --git a/radio/sdcard/taranis-x9/SCRIPTS/snake.lua b/radio/sdcard/taranis-x9/SCRIPTS/snake.lua index 2f2cff87a..012a9f1e1 100644 --- a/radio/sdcard/taranis-x9/SCRIPTS/snake.lua +++ b/radio/sdcard/taranis-x9/SCRIPTS/snake.lua @@ -1,176 +1,176 @@ --------------------------------------------------------------- --- Classic snake game --- --- 2009 Led Lab @PUC-Rio www.eluaproject.net --- Dado Sutter --- Ives Negreiros --- To Benjamin ---------------------------------------------------------------- - -local xMax = math.floor( LCD_W / 6 ) - 1 -local yMax = math.floor( LCD_H / 8 ) - 1 -local game_map = {} - -local Head = {} -local Tail = {} - -local highscore = 0 -local size = 3 -Tail.x = 1 -Tail.y = 1 -Head.x = Tail.x + ( size - 1 ) -Head.y = Tail.y - -local Food = {} -Food.x = false -Food.y = false - -Head.dx = 1 -Head.dy = 0 -Tail.dx = Head.dx -Tail.dy = Head.dy -local direction = "right" -local score = 0 - -local function create_food() - Food.x, Food.y = math.random( xMax - 1), math.random( yMax - 1) - while game_map[ Food.x ][ Food.y ] do - Food.x, Food.y = math.random( xMax - 1 ), math.random( yMax - 1 ) - end - game_map[ Food.x ][ Food.y ] = "food" - lcd.drawText( Food.x * 6, Food.y * 8+2, "@", 0 ) -end - -local function eat_food() - playFile("/SCRIPTS/snake.wav") - lcd.drawText( Head.x * 6, Head.y * 8, " ", 0 ) - game_map[ Head.x ][ Head.y ] = nil - create_food() - score = score + 1 -end - -local function check_collision() - if Head.x < 0 or Head.x > xMax then - return true - elseif Head.y < 0 or Head.y > yMax then - return true - elseif ( ( game_map[ Head.x ][ Head.y ] ) and ( game_map[ Head.x ][ Head.y ] ~= "food" ) ) then - return true - end - return false -end - -local function move() - if game_map[ Tail.x ][ Tail.y ] == "right" then - Tail.dx = 1 - Tail.dy = 0 - elseif game_map[ Tail.x ][ Tail.y ] == "left" then - Tail.dx = -1 - Tail.dy = 0 - elseif game_map[ Tail.x ][ Tail.y ] == "up" then - Tail.dx = 0 - Tail.dy = -1 - elseif game_map[ Tail.x ][ Tail.y ] == "down" then - Tail.dx = 0 - Tail.dy = 1 - end - - game_map[ Head.x ][ Head.y ] = direction - Head.x = Head.x + Head.dx - Head.y = Head.y + Head.dy - - if Head.x < 0 or Head.x > xMax or Head.y < 0 or Head.y > yMax then - return - elseif game_map[ Head.x ][ Head.y ] == "food" then - eat_food() - else - lcd.drawText(Tail.x * 6, Tail.y * 8, " ", 16) - game_map[ Tail.x ][ Tail.y ] = nil - Tail.x = Tail.x + Tail.dx - Tail.y = Tail.y + Tail.dy - end - - lcd.drawText(Head.x * 6, Head.y * 8, "*", 0) -end - -local function init() - food = false - lcd.clear() - size = 3 - score = 0 - Tail.x = 1 - Tail.y = 1 - Head.x = Tail.x + ( size - 1 ) - Head.y = Tail.y - Head.dx = 1 - Head.dy = 0 - Tail.dx = Head.dx - Tail.dy = Head.dy - direction = "right" - - for i = 0, xMax, 1 do - game_map[ i ] = {} - end - - for i = 0, size - 1, 1 do - game_map[ Tail.x + ( i * Tail.dx ) ][ Tail.y + ( i * Tail.dy ) ] = direction - lcd.drawText( ( Tail.x + ( i * Tail.dx ) ) * 6, ( Tail.y + ( i * Tail.dy ) ) * 8, "*", 0 ) - end - - create_food() -end - -local snakeCounter = 0 - -local function run(event) - if event == nil then - raise("Cannot be run as a model script!") - end - - if event == EVT_EXIT_BREAK then - return 2 - end - - snakeCounter = snakeCounter + 1 - if snakeCounter < 30 then - return 0 - end - - snakeCounter = 0 - - local dir = direction - if getValue('rud') > 100 and direction ~= "left" then - dir = "right" - Head.dx = 1 - Head.dy = 0 - end - if getValue('rud') < -100 and direction ~= "right" then - dir = "left" - Head.dx = -1 - Head.dy = 0 - end - if getValue('ele') > 100 and direction ~= "down" then - dir = "up" - Head.dx = 0 - Head.dy = -1 - end - if getValue('ele') < -100 and direction ~= "up" then - dir = "down" - Head.dx = 0 - Head.dy = 1 - end - - direction = dir - move() - - lcd.refresh() - - if check_collision() then - return 1 - end - - return 0 -end - -return { init=init, run=run } - +-------------------------------------------------------------- +-- Classic snake game +-- +-- 2009 Led Lab @PUC-Rio www.eluaproject.net +-- Dado Sutter +-- Ives Negreiros +-- To Benjamin +--------------------------------------------------------------- + +local xMax = math.floor( LCD_W / 6 ) - 1 +local yMax = math.floor( LCD_H / 8 ) - 1 +local game_map = {} + +local Head = {} +local Tail = {} + +local highscore = 0 +local size = 3 +Tail.x = 1 +Tail.y = 1 +Head.x = Tail.x + ( size - 1 ) +Head.y = Tail.y + +local Food = {} +Food.x = false +Food.y = false + +Head.dx = 1 +Head.dy = 0 +Tail.dx = Head.dx +Tail.dy = Head.dy +local direction = "right" +local score = 0 + +local function create_food() + Food.x, Food.y = math.random( xMax - 1), math.random( yMax - 1) + while game_map[ Food.x ][ Food.y ] do + Food.x, Food.y = math.random( xMax - 1 ), math.random( yMax - 1 ) + end + game_map[ Food.x ][ Food.y ] = "food" + lcd.drawText( Food.x * 6, Food.y * 8+2, "@", 0 ) +end + +local function eat_food() + playFile("/SCRIPTS/snake.wav") + lcd.drawText( Head.x * 6, Head.y * 8, " ", 0 ) + game_map[ Head.x ][ Head.y ] = nil + create_food() + score = score + 1 +end + +local function check_collision() + if Head.x < 0 or Head.x > xMax then + return true + elseif Head.y < 0 or Head.y > yMax then + return true + elseif ( ( game_map[ Head.x ][ Head.y ] ) and ( game_map[ Head.x ][ Head.y ] ~= "food" ) ) then + return true + end + return false +end + +local function move() + if game_map[ Tail.x ][ Tail.y ] == "right" then + Tail.dx = 1 + Tail.dy = 0 + elseif game_map[ Tail.x ][ Tail.y ] == "left" then + Tail.dx = -1 + Tail.dy = 0 + elseif game_map[ Tail.x ][ Tail.y ] == "up" then + Tail.dx = 0 + Tail.dy = -1 + elseif game_map[ Tail.x ][ Tail.y ] == "down" then + Tail.dx = 0 + Tail.dy = 1 + end + + game_map[ Head.x ][ Head.y ] = direction + Head.x = Head.x + Head.dx + Head.y = Head.y + Head.dy + + if Head.x < 0 or Head.x > xMax or Head.y < 0 or Head.y > yMax then + return + elseif game_map[ Head.x ][ Head.y ] == "food" then + eat_food() + else + lcd.drawText(Tail.x * 6, Tail.y * 8, " ", 16) + game_map[ Tail.x ][ Tail.y ] = nil + Tail.x = Tail.x + Tail.dx + Tail.y = Tail.y + Tail.dy + end + + lcd.drawText(Head.x * 6, Head.y * 8, "*", 0) +end + +local function init() + food = false + lcd.clear() + size = 3 + score = 0 + Tail.x = 1 + Tail.y = 1 + Head.x = Tail.x + ( size - 1 ) + Head.y = Tail.y + Head.dx = 1 + Head.dy = 0 + Tail.dx = Head.dx + Tail.dy = Head.dy + direction = "right" + + for i = 0, xMax, 1 do + game_map[ i ] = {} + end + + for i = 0, size - 1, 1 do + game_map[ Tail.x + ( i * Tail.dx ) ][ Tail.y + ( i * Tail.dy ) ] = direction + lcd.drawText( ( Tail.x + ( i * Tail.dx ) ) * 6, ( Tail.y + ( i * Tail.dy ) ) * 8, "*", 0 ) + end + + create_food() +end + +local snakeCounter = 0 + +local function run(event) + if event == nil then + raise("Cannot be run as a model script!") + end + + if event == EVT_EXIT_BREAK then + return 2 + end + + snakeCounter = snakeCounter + 1 + if snakeCounter < 30 then + return 0 + end + + snakeCounter = 0 + + local dir = direction + if getValue('rud') > 100 and direction ~= "left" then + dir = "right" + Head.dx = 1 + Head.dy = 0 + end + if getValue('rud') < -100 and direction ~= "right" then + dir = "left" + Head.dx = -1 + Head.dy = 0 + end + if getValue('ele') > 100 and direction ~= "down" then + dir = "up" + Head.dx = 0 + Head.dy = -1 + end + if getValue('ele') < -100 and direction ~= "up" then + dir = "down" + Head.dx = 0 + Head.dy = 1 + end + + direction = dir + move() + + lcd.refresh() + + if check_collision() then + return 1 + end + + return 0 +end + +return { init=init, run=run } + diff --git a/radio/src/bitmaps/sticks.xbm b/radio/src/bitmaps/sticks.xbm index 7ef10c94e..b250e83dc 100644 --- a/radio/src/bitmaps/sticks.xbm +++ b/radio/src/bitmaps/sticks.xbm @@ -1,11 +1,11 @@ -#define sticks_4x1_width 18 -#define sticks_4x1_height 32 -static unsigned char sticks_4x1_bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x88, 0x00, 0x44, 0x00, 0x00, - 0xfe, 0x24, 0x01, 0x44, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x20, 0x00, - 0x00, 0x00, 0x00, 0x20, 0x20, 0x00, 0x70, 0x88, 0x00, 0x20, 0x00, 0x00, - 0x20, 0x24, 0x01, 0x20, 0x00, 0x00, 0x70, 0x88, 0x00, 0x20, 0x20, 0x00, - 0x00, 0x00, 0x00, 0x10, 0x10, 0x00, 0x44, 0x38, 0x00, 0x00, 0x10, 0x00, - 0x92, 0x10, 0x00, 0x00, 0x10, 0x00, 0x44, 0x38, 0x00, 0x10, 0x10, 0x00, - 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x88, 0x00, - 0x92, 0xfc, 0x01, 0x00, 0x88, 0x00, 0x44, 0x00, 0x00, 0x10, 0x00, 0x00 }; +#define sticks_4x1_width 18 +#define sticks_4x1_height 32 +static unsigned char sticks_4x1_bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x88, 0x00, 0x44, 0x00, 0x00, + 0xfe, 0x24, 0x01, 0x44, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x20, 0x20, 0x00, 0x70, 0x88, 0x00, 0x20, 0x00, 0x00, + 0x20, 0x24, 0x01, 0x20, 0x00, 0x00, 0x70, 0x88, 0x00, 0x20, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x10, 0x10, 0x00, 0x44, 0x38, 0x00, 0x00, 0x10, 0x00, + 0x92, 0x10, 0x00, 0x00, 0x10, 0x00, 0x44, 0x38, 0x00, 0x10, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x88, 0x00, + 0x92, 0xfc, 0x01, 0x00, 0x88, 0x00, 0x44, 0x00, 0x00, 0x10, 0x00, 0x00 }; diff --git a/radio/src/buzzer.h b/radio/src/buzzer.h index 83c635393..9e2874533 100644 --- a/radio/src/buzzer.h +++ b/radio/src/buzzer.h @@ -1,175 +1,175 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BUZZER_H_ -#define _BUZZER_H_ - -#if defined(BUZZER) -extern uint8_t g_beepCnt; -extern uint8_t beepAgain; -extern uint8_t beepAgainOrig; -extern uint8_t beepOn; -extern bool warble; -extern bool warbleC; -#if defined(HAPTIC) -extern uint8_t hapticTick; -#endif /* HAPTIC */ -#endif /* BUZZER */ - -#if defined(BUZZER) - -#if defined(CPUARM) && !defined(SIMU) -inline void _beep(uint8_t b) -{ - buzzerSound(b); -} -#else /* CPUARM && !SIMU */ -inline void _beep(uint8_t b) -{ - g_beepCnt = b; -} -#endif /* CPUARM && !SIMU */ - -void beep(uint8_t val); -#else /* BUZZER */ -inline void beep(uint8_t) { } -#endif /* BUZZER */ - -#if !defined(AUDIO) - -#if defined(BUZZER) - #if defined(VOICE) - #define AUDIO_HELLO() PUSH_SYSTEM_PROMPT(AUDIO_HELLO) - #define AUDIO_BYE() - #define AUDIO_TX_BATTERY_LOW() PUSH_SYSTEM_PROMPT(AU_TX_BATTERY_LOW) - #define AUDIO_INACTIVITY() PUSH_SYSTEM_PROMPT(AU_INACTIVITY) - #define AUDIO_ERROR_MESSAGE(e) PUSH_SYSTEM_PROMPT((e)) - #define AUDIO_TIMER_MINUTE(t) playDuration(t) - // TODO - #define AUDIO_TIMER_30() PUSH_SYSTEM_PROMPT(AU_TIMER_30) - #define AUDIO_TIMER_20() PUSH_SYSTEM_PROMPT(AU_TIMER_20) - #else - #define AUDIO_HELLO() - #define AUDIO_BYE() - #define AUDIO_TX_BATTERY_LOW() beep(4) - #define AUDIO_INACTIVITY() beep(3) - #define AUDIO_ERROR_MESSAGE(e) beep(4) - #define AUDIO_TIMER_MINUTE(t) beep(2) - // TODO - #define AUDIO_TIMER_30() { beepAgain=2; beep(2); } - #define AUDIO_TIMER_20() { beepAgain=1; beep(2); } - #endif - - #define AUDIO_KEY_PRESS() beep(0) - #define AUDIO_KEY_ERROR() beep(2) - #define AUDIO_WARNING2() beep(2) - #define AUDIO_WARNING1() beep(3) - #define AUDIO_ERROR() beep(4) - #define AUDIO_MIX_WARNING(x) beep(1) - #define AUDIO_POT_MIDDLE() beep(2) - #define AUDIO_TIMER_COUNTDOWN(idx, val) beep(2) - #define AUDIO_TIMER_ELAPSED(idx) beep(3) - #define AUDIO_VARIO_UP() _beep(1) - #define AUDIO_VARIO_DOWN() _beep(1) - #define AUDIO_TRIM_PRESS(f) { if (!IS_KEY_FIRST(event)) warble = true; beep(1); } - #define AUDIO_TRIM_MIDDLE() beep(2) - #define AUDIO_TRIM_MIN() beep(2) - #define AUDIO_TRIM_MAX() beep(2) - #define AUDIO_PLAY(p) beep(3) - - #define IS_AUDIO_BUSY() (g_beepCnt || beepAgain || beepOn) -#else /* BUZZER */ - #define AUDIO_HELLO() - #define AUDIO_BYE() - #define AUDIO_TX_BATTERY_LOW() - #define AUDIO_INACTIVITY() - #define AUDIO_ERROR_MESSAGE(e) - #define AUDIO_TIMER_MINUTE(t) - #define AUDIO_TIMER_30() - #define AUDIO_TIMER_20() - #define AUDIO_WARNING2() - #define AUDIO_WARNING1() - #define AUDIO_ERROR() - #define AUDIO_MIX_WARNING(x) - #define AUDIO_POT_MIDDLE() - #define AUDIO_TIMER_LT10(m, x) - #define AUDIO_TIMER_00(m) - #define AUDIO_VARIO_UP() - #define AUDIO_VARIO_DOWN() - #define AUDIO_TRIM(event, f) - #define AUDIO_TRIM_MIDDLE(f) - #define AUDIO_TRIM_END(f) - #define AUDIO_PLAY(p) - #define IS_AUDIO_BUSY() false -#endif /* BUZZER */ - - #define AUDIO_RESET() - #define AUDIO_FLUSH() - - #define PLAY_PHASE_OFF(phase) - #define PLAY_PHASE_ON(phase) - #define PLAY_SWITCH_MOVED(sw) - #define PLAY_LOGICAL_SWITCH_OFF(sw) - #define PLAY_LOGICAL_SWITCH_ON(sw) - #define PLAY_MODEL_NAME() - #define START_SILENCE_PERIOD() -#endif /* !AUDIO */ - -#if !defined(CPUARM) -#if defined(BUZZER) -inline void BUZZER_HEARTBEAT() -{ - if (g_beepCnt) { - if (!beepAgainOrig) { - beepAgainOrig = g_beepCnt; - beepOn = true; - } - g_beepCnt--; - } - else { - if (beepAgain && beepAgainOrig) { - beepOn = !beepOn; - g_beepCnt = beepOn ? beepAgainOrig : 8; - if (beepOn) beepAgain--; - } - else { - beepAgainOrig = 0; - beepOn = false; - warble = false; - } - } - - if (beepOn) { - warbleC = warble && !warbleC; - if (warbleC) - buzzerOff(); - else - buzzerOn(); - } - else { - buzzerOff(); - } -} -#else // BUZZER -#define BUZZER_HEARTBEAT() -#endif // BUZZER -#endif // CPUARM - -#endif // _BUZZER_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BUZZER_H_ +#define _BUZZER_H_ + +#if defined(BUZZER) +extern uint8_t g_beepCnt; +extern uint8_t beepAgain; +extern uint8_t beepAgainOrig; +extern uint8_t beepOn; +extern bool warble; +extern bool warbleC; +#if defined(HAPTIC) +extern uint8_t hapticTick; +#endif /* HAPTIC */ +#endif /* BUZZER */ + +#if defined(BUZZER) + +#if defined(CPUARM) && !defined(SIMU) +inline void _beep(uint8_t b) +{ + buzzerSound(b); +} +#else /* CPUARM && !SIMU */ +inline void _beep(uint8_t b) +{ + g_beepCnt = b; +} +#endif /* CPUARM && !SIMU */ + +void beep(uint8_t val); +#else /* BUZZER */ +inline void beep(uint8_t) { } +#endif /* BUZZER */ + +#if !defined(AUDIO) + +#if defined(BUZZER) + #if defined(VOICE) + #define AUDIO_HELLO() PUSH_SYSTEM_PROMPT(AUDIO_HELLO) + #define AUDIO_BYE() + #define AUDIO_TX_BATTERY_LOW() PUSH_SYSTEM_PROMPT(AU_TX_BATTERY_LOW) + #define AUDIO_INACTIVITY() PUSH_SYSTEM_PROMPT(AU_INACTIVITY) + #define AUDIO_ERROR_MESSAGE(e) PUSH_SYSTEM_PROMPT((e)) + #define AUDIO_TIMER_MINUTE(t) playDuration(t) + // TODO + #define AUDIO_TIMER_30() PUSH_SYSTEM_PROMPT(AU_TIMER_30) + #define AUDIO_TIMER_20() PUSH_SYSTEM_PROMPT(AU_TIMER_20) + #else + #define AUDIO_HELLO() + #define AUDIO_BYE() + #define AUDIO_TX_BATTERY_LOW() beep(4) + #define AUDIO_INACTIVITY() beep(3) + #define AUDIO_ERROR_MESSAGE(e) beep(4) + #define AUDIO_TIMER_MINUTE(t) beep(2) + // TODO + #define AUDIO_TIMER_30() { beepAgain=2; beep(2); } + #define AUDIO_TIMER_20() { beepAgain=1; beep(2); } + #endif + + #define AUDIO_KEY_PRESS() beep(0) + #define AUDIO_KEY_ERROR() beep(2) + #define AUDIO_WARNING2() beep(2) + #define AUDIO_WARNING1() beep(3) + #define AUDIO_ERROR() beep(4) + #define AUDIO_MIX_WARNING(x) beep(1) + #define AUDIO_POT_MIDDLE() beep(2) + #define AUDIO_TIMER_COUNTDOWN(idx, val) beep(2) + #define AUDIO_TIMER_ELAPSED(idx) beep(3) + #define AUDIO_VARIO_UP() _beep(1) + #define AUDIO_VARIO_DOWN() _beep(1) + #define AUDIO_TRIM_PRESS(f) { if (!IS_KEY_FIRST(event)) warble = true; beep(1); } + #define AUDIO_TRIM_MIDDLE() beep(2) + #define AUDIO_TRIM_MIN() beep(2) + #define AUDIO_TRIM_MAX() beep(2) + #define AUDIO_PLAY(p) beep(3) + + #define IS_AUDIO_BUSY() (g_beepCnt || beepAgain || beepOn) +#else /* BUZZER */ + #define AUDIO_HELLO() + #define AUDIO_BYE() + #define AUDIO_TX_BATTERY_LOW() + #define AUDIO_INACTIVITY() + #define AUDIO_ERROR_MESSAGE(e) + #define AUDIO_TIMER_MINUTE(t) + #define AUDIO_TIMER_30() + #define AUDIO_TIMER_20() + #define AUDIO_WARNING2() + #define AUDIO_WARNING1() + #define AUDIO_ERROR() + #define AUDIO_MIX_WARNING(x) + #define AUDIO_POT_MIDDLE() + #define AUDIO_TIMER_LT10(m, x) + #define AUDIO_TIMER_00(m) + #define AUDIO_VARIO_UP() + #define AUDIO_VARIO_DOWN() + #define AUDIO_TRIM(event, f) + #define AUDIO_TRIM_MIDDLE(f) + #define AUDIO_TRIM_END(f) + #define AUDIO_PLAY(p) + #define IS_AUDIO_BUSY() false +#endif /* BUZZER */ + + #define AUDIO_RESET() + #define AUDIO_FLUSH() + + #define PLAY_PHASE_OFF(phase) + #define PLAY_PHASE_ON(phase) + #define PLAY_SWITCH_MOVED(sw) + #define PLAY_LOGICAL_SWITCH_OFF(sw) + #define PLAY_LOGICAL_SWITCH_ON(sw) + #define PLAY_MODEL_NAME() + #define START_SILENCE_PERIOD() +#endif /* !AUDIO */ + +#if !defined(CPUARM) +#if defined(BUZZER) +inline void BUZZER_HEARTBEAT() +{ + if (g_beepCnt) { + if (!beepAgainOrig) { + beepAgainOrig = g_beepCnt; + beepOn = true; + } + g_beepCnt--; + } + else { + if (beepAgain && beepAgainOrig) { + beepOn = !beepOn; + g_beepCnt = beepOn ? beepAgainOrig : 8; + if (beepOn) beepAgain--; + } + else { + beepAgainOrig = 0; + beepOn = false; + warble = false; + } + } + + if (beepOn) { + warbleC = warble && !warbleC; + if (warbleC) + buzzerOff(); + else + buzzerOn(); + } + else { + buzzerOff(); + } +} +#else // BUZZER +#define BUZZER_HEARTBEAT() +#endif // BUZZER +#endif // CPUARM + +#endif // _BUZZER_H_ diff --git a/radio/src/disk_cache.cpp b/radio/src/disk_cache.cpp index da65e286d..5553aedf3 100644 --- a/radio/src/disk_cache.cpp +++ b/radio/src/disk_cache.cpp @@ -1,180 +1,180 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "opentx.h" - -#if defined(SIMU) && !defined(SIMU_DISKIO) - #define __disk_read(...) (RES_OK) - #define __disk_write(...) (RES_OK) -#endif - -#if 0 // set to 1 to enable traces - #define TRACE_DISK_CACHE(...) TRACE(__VA_ARGS__) -#else - #define TRACE_DISK_CACHE(...) -#endif - -DiskCache diskCache; - -DiskCacheBlock::DiskCacheBlock(): - startSector(0), - endSector(0) -{ -} - -bool DiskCacheBlock::read(BYTE * buff, DWORD sector, UINT count) -{ - if (sector >= startSector && (sector+count) <= endSector) { - TRACE_DISK_CACHE("\tcache read(%u, %u) from %p", (uint32_t)sector, (uint32_t)count, this); - memcpy(buff, data + ((sector - startSector) * BLOCK_SIZE), count * BLOCK_SIZE); - return true; - } - return false; -} - -DRESULT DiskCacheBlock::fill(BYTE drv, BYTE * buff, DWORD sector, UINT count) -{ - DRESULT res = __disk_read(drv, data, sector, DISK_CACHE_BLOCK_SECTORS); - if (res != RES_OK) { - return res; - } - startSector = sector; - endSector = sector + DISK_CACHE_BLOCK_SECTORS; - memcpy(buff, data, count * BLOCK_SIZE); - TRACE_DISK_CACHE("\tcache %p FILLED from read(%u, %u)", this, (uint32_t)sector, (uint32_t)count); - return RES_OK; -} - -void DiskCacheBlock::free(DWORD sector, UINT count) -{ - if (sector < endSector && (sector+count) > startSector) { - TRACE_DISK_CACHE("\tINVALIDATING disk cache block %p (%u)", this, startSector); - endSector = 0; - } -} - -void DiskCacheBlock::free() -{ - endSector = 0; -} - -bool DiskCacheBlock::empty() const -{ - return (endSector == 0); -} - -DiskCache::DiskCache(): - lastBlock(0) -{ - stats.noHits = 0; - stats.noMisses = 0; - stats.noWrites = 0; - blocks = new DiskCacheBlock[DISK_CACHE_BLOCKS_NUM]; -} - -void DiskCache::clear() -{ - lastBlock = 0; - stats.noHits = 0; - stats.noMisses = 0; - stats.noWrites = 0; - for (int n=0; n DISK_CACHE_BLOCK_SECTORS) { - TRACE_DISK_CACHE("\t\t big read(%u, %u)", (uint32_t)sector, (uint32_t)count); - return __disk_read(drv, buff, sector, count); - } - - // if block + cache block size is beyond the end of the disk, then read it directly without using cache - if (sector+DISK_CACHE_BLOCK_SECTORS >= sdGetNoSectors()) { - TRACE_DISK_CACHE("\t\t cache would be beyond end of disk %u (%u)", (uint32_t)sector, sdGetNoSectors()); - return __disk_read(drv, buff, sector, count); - } - - for (int n=0; n= DISK_CACHE_BLOCKS_NUM) { - lastBlock = 0; - } - - return blocks[lastBlock].fill(drv, buff, sector, count); -} - -DRESULT DiskCache::write(BYTE drv, const BYTE* buff, DWORD sector, UINT count) -{ - ++stats.noWrites; - for(int n=0; n < DISK_CACHE_BLOCKS_NUM; ++n) { - blocks[n].free(sector, count); - } - return __disk_write(drv, buff, sector, count); -} - -const DiskCacheStats & DiskCache::getStats() const -{ - return stats; -} - -int DiskCache::getHitRate() const -{ - uint32_t all = stats.noHits + stats.noMisses; - if (all == 0) return 0; - return (stats.noHits * 1000) / all; -} - -DRESULT disk_read(BYTE drv, BYTE * buff, DWORD sector, UINT count) -{ - return diskCache.read(drv, buff, sector, count); -} - - -DRESULT disk_write(BYTE drv, const BYTE * buff, DWORD sector, UINT count) -{ - return diskCache.write(drv, buff, sector, count); -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "opentx.h" + +#if defined(SIMU) && !defined(SIMU_DISKIO) + #define __disk_read(...) (RES_OK) + #define __disk_write(...) (RES_OK) +#endif + +#if 0 // set to 1 to enable traces + #define TRACE_DISK_CACHE(...) TRACE(__VA_ARGS__) +#else + #define TRACE_DISK_CACHE(...) +#endif + +DiskCache diskCache; + +DiskCacheBlock::DiskCacheBlock(): + startSector(0), + endSector(0) +{ +} + +bool DiskCacheBlock::read(BYTE * buff, DWORD sector, UINT count) +{ + if (sector >= startSector && (sector+count) <= endSector) { + TRACE_DISK_CACHE("\tcache read(%u, %u) from %p", (uint32_t)sector, (uint32_t)count, this); + memcpy(buff, data + ((sector - startSector) * BLOCK_SIZE), count * BLOCK_SIZE); + return true; + } + return false; +} + +DRESULT DiskCacheBlock::fill(BYTE drv, BYTE * buff, DWORD sector, UINT count) +{ + DRESULT res = __disk_read(drv, data, sector, DISK_CACHE_BLOCK_SECTORS); + if (res != RES_OK) { + return res; + } + startSector = sector; + endSector = sector + DISK_CACHE_BLOCK_SECTORS; + memcpy(buff, data, count * BLOCK_SIZE); + TRACE_DISK_CACHE("\tcache %p FILLED from read(%u, %u)", this, (uint32_t)sector, (uint32_t)count); + return RES_OK; +} + +void DiskCacheBlock::free(DWORD sector, UINT count) +{ + if (sector < endSector && (sector+count) > startSector) { + TRACE_DISK_CACHE("\tINVALIDATING disk cache block %p (%u)", this, startSector); + endSector = 0; + } +} + +void DiskCacheBlock::free() +{ + endSector = 0; +} + +bool DiskCacheBlock::empty() const +{ + return (endSector == 0); +} + +DiskCache::DiskCache(): + lastBlock(0) +{ + stats.noHits = 0; + stats.noMisses = 0; + stats.noWrites = 0; + blocks = new DiskCacheBlock[DISK_CACHE_BLOCKS_NUM]; +} + +void DiskCache::clear() +{ + lastBlock = 0; + stats.noHits = 0; + stats.noMisses = 0; + stats.noWrites = 0; + for (int n=0; n DISK_CACHE_BLOCK_SECTORS) { + TRACE_DISK_CACHE("\t\t big read(%u, %u)", (uint32_t)sector, (uint32_t)count); + return __disk_read(drv, buff, sector, count); + } + + // if block + cache block size is beyond the end of the disk, then read it directly without using cache + if (sector+DISK_CACHE_BLOCK_SECTORS >= sdGetNoSectors()) { + TRACE_DISK_CACHE("\t\t cache would be beyond end of disk %u (%u)", (uint32_t)sector, sdGetNoSectors()); + return __disk_read(drv, buff, sector, count); + } + + for (int n=0; n= DISK_CACHE_BLOCKS_NUM) { + lastBlock = 0; + } + + return blocks[lastBlock].fill(drv, buff, sector, count); +} + +DRESULT DiskCache::write(BYTE drv, const BYTE* buff, DWORD sector, UINT count) +{ + ++stats.noWrites; + for(int n=0; n < DISK_CACHE_BLOCKS_NUM; ++n) { + blocks[n].free(sector, count); + } + return __disk_write(drv, buff, sector, count); +} + +const DiskCacheStats & DiskCache::getStats() const +{ + return stats; +} + +int DiskCache::getHitRate() const +{ + uint32_t all = stats.noHits + stats.noMisses; + if (all == 0) return 0; + return (stats.noHits * 1000) / all; +} + +DRESULT disk_read(BYTE drv, BYTE * buff, DWORD sector, UINT count) +{ + return diskCache.read(drv, buff, sector, count); +} + + +DRESULT disk_write(BYTE drv, const BYTE * buff, DWORD sector, UINT count) +{ + return diskCache.write(drv, buff, sector, count); +} diff --git a/radio/src/disk_cache.h b/radio/src/disk_cache.h index 1fccf1168..62c1d4f63 100644 --- a/radio/src/disk_cache.h +++ b/radio/src/disk_cache.h @@ -1,74 +1,74 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DISK_CACHE_H_ -#define _DISK_CACHE_H_ - -#include "diskio.h" -#include "sdio_sd.h" - -// tunable parameters -#define DISK_CACHE_BLOCKS_NUM 32 // no cache blocks -#define DISK_CACHE_BLOCK_SECTORS 16 // no sectors - -#define DISK_CACHE_BLOCK_SIZE (DISK_CACHE_BLOCK_SECTORS * BLOCK_SIZE) - -class DiskCacheBlock -{ -public: - DiskCacheBlock(); - bool read(BYTE* buff, DWORD sector, UINT count); - DRESULT fill(BYTE drv, BYTE* buff, DWORD sector, UINT count); - void free(DWORD sector, UINT count); - void free(); - bool empty() const; - -private: - uint8_t data[DISK_CACHE_BLOCK_SIZE]; - DWORD startSector; - DWORD endSector; -}; - -struct DiskCacheStats -{ - uint32_t noHits; - uint32_t noMisses; - uint32_t noWrites; -}; - -class DiskCache -{ - public: - DiskCache(); - DRESULT read(BYTE drv, BYTE* buff, DWORD sector, UINT count); - DRESULT write(BYTE drv, const BYTE* buff, DWORD sector, UINT count); - const DiskCacheStats & getStats() const; - int getHitRate() const; - void clear(); - - private: - DiskCacheStats stats; - uint32_t lastBlock; - DiskCacheBlock * blocks; -}; - -extern DiskCache diskCache; - -#endif // _DISK_CACHE_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DISK_CACHE_H_ +#define _DISK_CACHE_H_ + +#include "diskio.h" +#include "sdio_sd.h" + +// tunable parameters +#define DISK_CACHE_BLOCKS_NUM 32 // no cache blocks +#define DISK_CACHE_BLOCK_SECTORS 16 // no sectors + +#define DISK_CACHE_BLOCK_SIZE (DISK_CACHE_BLOCK_SECTORS * BLOCK_SIZE) + +class DiskCacheBlock +{ +public: + DiskCacheBlock(); + bool read(BYTE* buff, DWORD sector, UINT count); + DRESULT fill(BYTE drv, BYTE* buff, DWORD sector, UINT count); + void free(DWORD sector, UINT count); + void free(); + bool empty() const; + +private: + uint8_t data[DISK_CACHE_BLOCK_SIZE]; + DWORD startSector; + DWORD endSector; +}; + +struct DiskCacheStats +{ + uint32_t noHits; + uint32_t noMisses; + uint32_t noWrites; +}; + +class DiskCache +{ + public: + DiskCache(); + DRESULT read(BYTE drv, BYTE* buff, DWORD sector, UINT count); + DRESULT write(BYTE drv, const BYTE* buff, DWORD sector, UINT count); + const DiskCacheStats & getStats() const; + int getHitRate() const; + void clear(); + + private: + DiskCacheStats stats; + uint32_t lastBlock; + DiskCacheBlock * blocks; +}; + +extern DiskCache diskCache; + +#endif // _DISK_CACHE_H_ diff --git a/radio/src/dmafifo.h b/radio/src/dmafifo.h index 16e3e7892..74226d1d8 100644 --- a/radio/src/dmafifo.h +++ b/radio/src/dmafifo.h @@ -1,82 +1,82 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DMA_FIFO_H_ -#define _DMA_FIFO_H_ - -#include "definitions.h" - -template -class DMAFifo -{ - public: - DMAFifo(DMA_Stream_TypeDef * stream): - stream(stream), - ridx(0) - { - } - - void clear() - { - ridx = 0; - } - - uint32_t size() - { - return N; - } - - uint8_t last(int index) - { - return fifo[(2*N - stream->NDTR - index) & (N-1)]; - } - - bool isEmpty() - { -#if defined(SIMU) - return true; -#endif - return (ridx == N - stream->NDTR); - } - - bool pop(uint8_t & element) - { - if (isEmpty()) { - return false; - } - else { - element = fifo[ridx]; - ridx = (ridx+1) & (N-1); - return true; - } - } - - uint8_t * buffer() - { - return fifo; - } - - protected: - uint8_t fifo[N]; - DMA_Stream_TypeDef * stream; - volatile uint32_t ridx; -}; - -#endif // _DMA_FIFO_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DMA_FIFO_H_ +#define _DMA_FIFO_H_ + +#include "definitions.h" + +template +class DMAFifo +{ + public: + DMAFifo(DMA_Stream_TypeDef * stream): + stream(stream), + ridx(0) + { + } + + void clear() + { + ridx = 0; + } + + uint32_t size() + { + return N; + } + + uint8_t last(int index) + { + return fifo[(2*N - stream->NDTR - index) & (N-1)]; + } + + bool isEmpty() + { +#if defined(SIMU) + return true; +#endif + return (ridx == N - stream->NDTR); + } + + bool pop(uint8_t & element) + { + if (isEmpty()) { + return false; + } + else { + element = fifo[ridx]; + ridx = (ridx+1) & (N-1); + return true; + } + } + + uint8_t * buffer() + { + return fifo; + } + + protected: + uint8_t fifo[N]; + DMA_Stream_TypeDef * stream; + volatile uint32_t ridx; +}; + +#endif // _DMA_FIFO_H_ diff --git a/radio/src/fifo.h b/radio/src/fifo.h index 59eb1566e..e24b9ba80 100644 --- a/radio/src/fifo.h +++ b/radio/src/fifo.h @@ -1,105 +1,105 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _FIFO_H_ -#define _FIFO_H_ - -template -class Fifo -{ - static_assert((N > 1) & !(N & (N - 1)), "Fifo size must be a power of two!"); - - public: - Fifo(): - widx(0), - ridx(0) - { - } - - void clear() - { - widx = ridx = 0; - } - - void push(T element) - { - uint32_t next = (widx+1) & (N-1); - if (next != ridx) { - fifo[widx] = element; - widx = next; - } - } - - bool pop(T & element) - { - if (isEmpty()) { - return false; - } - else { - element = fifo[ridx]; - ridx = (ridx+1) & (N-1); - return true; - } - } - - bool isEmpty() const - { - return (ridx == widx); - } - - bool isFull() - { - uint32_t next = (widx+1) & (N-1); - return (next == ridx); - } - - void flush() - { - while (!isEmpty()) {}; - } - - uint32_t size() const - { - return (N + widx - ridx) & (N-1); - } - - uint32_t hasSpace(uint32_t n) const - { - return (N > (size() + n)); - } - - bool probe(T & element) const - { - if (isEmpty()) { - return false; - } - else { - element = fifo[ridx]; - return true; - } - } - - protected: - T fifo[N]; - volatile uint32_t widx; - volatile uint32_t ridx; -}; - -#endif // _FIFO_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _FIFO_H_ +#define _FIFO_H_ + +template +class Fifo +{ + static_assert((N > 1) & !(N & (N - 1)), "Fifo size must be a power of two!"); + + public: + Fifo(): + widx(0), + ridx(0) + { + } + + void clear() + { + widx = ridx = 0; + } + + void push(T element) + { + uint32_t next = (widx+1) & (N-1); + if (next != ridx) { + fifo[widx] = element; + widx = next; + } + } + + bool pop(T & element) + { + if (isEmpty()) { + return false; + } + else { + element = fifo[ridx]; + ridx = (ridx+1) & (N-1); + return true; + } + } + + bool isEmpty() const + { + return (ridx == widx); + } + + bool isFull() + { + uint32_t next = (widx+1) & (N-1); + return (next == ridx); + } + + void flush() + { + while (!isEmpty()) {}; + } + + uint32_t size() const + { + return (N + widx - ridx) & (N-1); + } + + uint32_t hasSpace(uint32_t n) const + { + return (N > (size() + n)); + } + + bool probe(T & element) const + { + if (isEmpty()) { + return false; + } + else { + element = fifo[ridx]; + return true; + } + } + + protected: + T fifo[N]; + volatile uint32_t widx; + volatile uint32_t ridx; +}; + +#endif // _FIFO_H_ diff --git a/radio/src/fonts.h b/radio/src/fonts.h index 17548110f..f9430b8cb 100644 --- a/radio/src/fonts.h +++ b/radio/src/fonts.h @@ -1,56 +1,56 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _FONTS_H_ -#define _FONTS_H_ - -#if defined(COLORLCD) - -extern const uint16_t * const fontspecsTable[16]; -extern const uint8_t * const fontsTable[16]; - -#if defined(PCBHORUS) -extern BitmapBuffer * fontCache[2]; -void loadFontCache(); -#endif - -#else - -extern const pm_uchar font_5x7[]; -extern const pm_uchar font_10x14[]; - -#if defined(BOLD_FONT) && ((!defined(CPUM64) && !defined(PCBMEGA2560)) || defined(TELEMETRY_NONE)) && !defined(BOOT) - #define BOLD_SPECIFIC_FONT - extern const pm_uchar font_5x7_B[]; -#endif - -#if defined(CPUARM) -extern const pm_uchar font_3x5[]; -extern const pm_uchar font_4x6[]; -extern const pm_uchar font_8x10[]; -extern const pm_uchar font_22x38_num[]; -extern const pm_uchar font_5x7_extra[]; -extern const pm_uchar font_10x14_extra[]; -extern const pm_uchar font_4x6_extra[]; -#endif - -#endif - -#endif // _FONTS_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _FONTS_H_ +#define _FONTS_H_ + +#if defined(COLORLCD) + +extern const uint16_t * const fontspecsTable[16]; +extern const uint8_t * const fontsTable[16]; + +#if defined(PCBHORUS) +extern BitmapBuffer * fontCache[2]; +void loadFontCache(); +#endif + +#else + +extern const pm_uchar font_5x7[]; +extern const pm_uchar font_10x14[]; + +#if defined(BOLD_FONT) && ((!defined(CPUM64) && !defined(PCBMEGA2560)) || defined(TELEMETRY_NONE)) && !defined(BOOT) + #define BOLD_SPECIFIC_FONT + extern const pm_uchar font_5x7_B[]; +#endif + +#if defined(CPUARM) +extern const pm_uchar font_3x5[]; +extern const pm_uchar font_4x6[]; +extern const pm_uchar font_8x10[]; +extern const pm_uchar font_22x38_num[]; +extern const pm_uchar font_5x7_extra[]; +extern const pm_uchar font_10x14_extra[]; +extern const pm_uchar font_4x6_extra[]; +#endif + +#endif + +#endif // _FONTS_H_ diff --git a/radio/src/gui/480x272/bitmapbuffer.cpp b/radio/src/gui/480x272/bitmapbuffer.cpp index b0fede61f..0eb85f7a1 100644 --- a/radio/src/gui/480x272/bitmapbuffer.cpp +++ b/radio/src/gui/480x272/bitmapbuffer.cpp @@ -1,831 +1,831 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "opentx.h" - -void BitmapBuffer::drawAlphaPixel(display_t * p, uint8_t opacity, uint16_t color) -{ - if (opacity == OPACITY_MAX) { - drawPixel(p, color); - } - else if (opacity != 0) { - uint8_t bgWeight = OPACITY_MAX - opacity; - RGB_SPLIT(color, red, green, blue); - RGB_SPLIT(*p, bgRed, bgGreen, bgBlue); - uint16_t r = (bgRed * bgWeight + red * opacity) / OPACITY_MAX; - uint16_t g = (bgGreen * bgWeight + green * opacity) / OPACITY_MAX; - uint16_t b = (bgBlue * bgWeight + blue * opacity) / OPACITY_MAX; - drawPixel(p, RGB_JOIN(r, g, b)); - } -} - -void BitmapBuffer::drawHorizontalLine(coord_t x, coord_t y, coord_t w, uint8_t pat, LcdFlags att) -{ - if (y >= height) return; - if (x+w > width) { w = width - x; } - - display_t * p = getPixelPtr(x, y); - display_t color = lcdColorTable[COLOR_IDX(att)]; - uint8_t opacity = 0x0F - (att >> 24); - - if (pat == SOLID) { - while (w--) { - drawAlphaPixel(p, opacity, color); - MOVE_TO_NEXT_RIGHT_PIXEL(p); - } - } - else { - while (w--) { - if (pat & 1) { - drawAlphaPixel(p, opacity, color); - pat = (pat >> 1) | 0x80; - } - else { - pat = pat >> 1; - } - MOVE_TO_NEXT_RIGHT_PIXEL(p); - } - } -} - -void BitmapBuffer::drawVerticalLine(coord_t x, coord_t y, coord_t h, uint8_t pat, LcdFlags att) -{ - if (x >= width) return; - if (y >= height) return; - if (h<0) { y+=h; h=-h; } - if (y<0) { h+=y; y=0; if (h<=0) return; } - if (y+h > height) { h = height - y; } - - display_t color = lcdColorTable[COLOR_IDX(att)]; - uint8_t opacity = 0x0F - (att >> 24); - - if (pat == SOLID) { - while (h--) { - drawAlphaPixel(x, y, opacity, color); - y++; - } - } - else { - if (pat==DOTTED && !(y%2)) { - pat = ~pat; - } - while (h--) { - if (pat & 1) { - drawAlphaPixel(x, y, opacity, color); - pat = (pat >> 1) | 0x80; - } - else { - pat = pat >> 1; - } - y++; - } - } -} - -void BitmapBuffer::drawRect(coord_t x, coord_t y, coord_t w, coord_t h, uint8_t thickness, uint8_t pat, LcdFlags att) -{ - for (int i=0; i= 360 || endAngle <= 0) - return false; - - if (startAngle == 0) { - slopes[1] = 100000; - slopes[2] = -100000; - } - else { - float angle1 = float(startAngle) * (PI / 180.0f); - if (startAngle >= 180) { - slopes[1] = -100000; - slopes[2] = cosf(angle1) * 100 / sinf(angle1); - } - else { - slopes[1] = cosf(angle1) * 100 / sinf(angle1); - slopes[2] = -100000; - } - } - - if (endAngle == 360) { - slopes[0] = -100000; - slopes[3] = 100000; - } - else { - float angle2 = float(endAngle) * (PI / 180.0f); - if (endAngle >= 180) { - slopes[0] = -100000; - slopes[3] = -cosf(angle2) * 100 / sinf(angle2); - } - else { - slopes[0] = cosf(angle2) * 100 / sinf(angle2); - slopes[3] = -100000; - } - } - - return true; -} - -void BitmapBuffer::drawPie(int x0, int y0, int radius, int startAngle, int endAngle) -{ - int slopes[4]; - if (!evalSlopes(slopes, startAngle, endAngle)) - return; - - for (int y=0; y<=radius; y++) { - for (int x=0; x<=radius; x++) { - if (x*x+y*y <= radius*radius) { - int slope = (x==0 ? (y<0 ? -99000 : 99000) : y*100/x); - if (slope >= slopes[0] && slope < slopes[1]) { - drawPixel(x0+x, y0-y, WHITE); - } - if (-slope >= slopes[0] && -slope < slopes[1]) { - drawPixel(x0+x, y0+y, WHITE); - } - if (slope >= slopes[2] && slope < slopes[3]) { - drawPixel(x0-x, y0-y, WHITE); - } - if (-slope >= slopes[2] && -slope < slopes[3]) { - drawPixel(x0-x, y0+y, WHITE); - } - } - } - } -} - -void BitmapBuffer::drawMask(coord_t x, coord_t y, BitmapBuffer * mask, LcdFlags flags, coord_t offset, coord_t width) -{ - if (mask == NULL) { - return; - } - - coord_t w = mask->getWidth(); - coord_t height = mask->getHeight(); - - if (!width || width > w) { - width = w; - } - - if (x+width > this->width) { - width = this->width-x; - } - - display_t color = lcdColorTable[COLOR_IDX(flags)]; - - for (coord_t row=0; rowgetPixelPtr(offset, row); - for (coord_t col=0; col w) { - width = w; - } - - if (x+width > this->width) { - width = this->width-x; - } - - display_t color = lcdColorTable[COLOR_IDX(flags)]; - - for (coord_t row=0; row 0) drawBitmapPattern(x, y, font, flags, offset, width); - return width; -} - -uint8_t BitmapBuffer::drawCharWithCache(coord_t x, coord_t y, const BitmapBuffer * font, const uint16_t * spec, int index, LcdFlags flags) -{ - coord_t offset = spec[index]; - coord_t width = spec[index+1] - offset; - drawBitmap(x, y, font, offset, 0, width); - return width; -} - -void BitmapBuffer::drawSizedText(coord_t x, coord_t y, const char * s, uint8_t len, LcdFlags flags) -{ -#define INCREMENT_POS(delta) \ - do { if (flags & VERTICAL) y -= delta; else x += delta; } while(0) - - int width = getTextWidth(s, len, flags); - int height = getFontHeight(flags); - uint32_t fontindex = FONTINDEX(flags); - const pm_uchar * font = fontsTable[fontindex]; - const uint16_t * fontspecs = fontspecsTable[fontindex]; - BitmapBuffer * fontcache = NULL; - - if (flags & RIGHT) - INCREMENT_POS(-width); - else if (flags & CENTERED) - INCREMENT_POS(-width/2); - - coord_t & pos = (flags & VERTICAL) ? y : x; - - if ((flags & INVERS) && ((~flags & BLINK) || BLINK_ON_PHASE)) { - uint16_t fgColor = lcdColorTable[COLOR_IDX(flags)]; - if (fgColor == lcdColorTable[TEXT_COLOR_INDEX]) { - flags = TEXT_INVERTED_COLOR | (flags & 0x0ffff); - } - if (fontindex == STDSIZE_INDEX) { - if (fgColor == lcdColorTable[TEXT_COLOR_INDEX]) { - drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y, INVERT_HORZ_MARGIN-1, INVERT_LINE_HEIGHT, TEXT_INVERTED_BGCOLOR); - drawSolidFilledRect(x+width-1, y, INVERT_HORZ_MARGIN, INVERT_LINE_HEIGHT, TEXT_INVERTED_BGCOLOR); - fontcache = fontCache[1]; - } - else { - drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y, width+2*INVERT_HORZ_MARGIN-1, INVERT_LINE_HEIGHT, TEXT_INVERTED_BGCOLOR); - } - } - else if (fontindex == TINSIZE_INDEX) { - drawSolidFilledRect(x-INVERT_HORZ_MARGIN+2, y, width+2*INVERT_HORZ_MARGIN-5, height+2, TEXT_INVERTED_BGCOLOR); - } - else if (fontindex == SMLSIZE_INDEX) { - drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y, width+2*INVERT_HORZ_MARGIN-2, height+2, TEXT_INVERTED_BGCOLOR); - } - else if (fontindex == MIDSIZE_INDEX) { - drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y-1, width+2*INVERT_HORZ_MARGIN-2, height+3, TEXT_INVERTED_BGCOLOR); // MIDSIZE and DBLSIZE font are missing a pixel on top compared to others - } - else if (fontindex == DBLSIZE_INDEX) { - drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y-1, width+2*INVERT_HORZ_MARGIN-2, height+3, TEXT_INVERTED_BGCOLOR); // MIDSIZE and DBLSIZE font are missing a pixel on top compared to others - } - else if (fontindex == XXLSIZE_INDEX) { - drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y, width+2*INVERT_HORZ_MARGIN-2, height+2, TEXT_INVERTED_BGCOLOR); - } - else { - drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y, width+2*INVERT_HORZ_MARGIN, INVERT_LINE_HEIGHT, TEXT_INVERTED_BGCOLOR); - } - } - else if (!(flags & NO_FONTCACHE)) { - if (fontindex == STDSIZE_INDEX) { - uint16_t fgColor = lcdColorTable[COLOR_IDX(flags)]; - uint16_t bgColor = *getPixelPtr(x, y); - if (fgColor == lcdColorTable[TEXT_COLOR_INDEX] && bgColor == lcdColorTable[TEXT_BGCOLOR_INDEX]) { - fontcache = fontCache[0]; - } - else if (fgColor == lcdColorTable[TEXT_INVERTED_COLOR_INDEX] && bgColor == lcdColorTable[TEXT_INVERTED_BGCOLOR_INDEX]) { - fontcache = fontCache[1]; - } - else { - // TRACE("No cache for \"%s\"", s); - } - } - } - - bool setpos = false; - const coord_t orig_pos = pos; - while (len--) { - unsigned char c; - if (flags & ZCHAR) - c = idx2char(*s); - else - c = pgm_read_byte(s); - if (setpos) { - pos = c; - setpos = false; - } - else if (!c) { - break; - } - else if (c >= 0x20) { - uint8_t width; - if (fontcache) - width = drawCharWithCache(x-1, y, fontcache, fontspecs, getMappedChar(c), flags); - else - width = drawCharWithoutCache(x-1, y, font, fontspecs, getMappedChar(c), flags); - INCREMENT_POS(width); - } - else if (c == 0x1F) { // X-coord prefix - setpos = true; - } - else if (c == 0x1E) { - pos = orig_pos; - if (flags & VERTICAL) - x += height; - else - y += height; - } - else if (c == 1) { - INCREMENT_POS(1); - } - else { - INCREMENT_POS(2*(c-1)); - } - s++; - } - lcdNextPos = pos; -} - -void BitmapBuffer::drawBitmapPie(int x0, int y0, const uint16_t * img, int startAngle, int endAngle) -{ - const uint16_t * q = img; - coord_t width = *q++; - coord_t height = *q++; - - int slopes[4]; - if (!evalSlopes(slopes, startAngle, endAngle)) - return; - - int w2 = width/2; - int h2 = height/2; - - for (int y=h2-1; y>=0; y--) { - for (int x=w2-1; x>=0; x--) { - int slope = (x==0 ? (y<0 ? -99000 : 99000) : y*100/x); - if (slope >= slopes[0] && slope < slopes[1]) { - *getPixelPtr(x0+w2+x, y0+h2-y) = q[(h2-y)*width + w2+x]; - } - if (-slope >= slopes[0] && -slope < slopes[1]) { - *getPixelPtr(x0+w2+x, y0+h2+y) = q[(h2+y)*width + w2+x]; - } - if (slope >= slopes[2] && slope < slopes[3]) { - *getPixelPtr(x0+w2-x, y0+h2-y) = q[(h2-y)*width + w2-x]; - } - if (-slope >= slopes[2] && -slope < slopes[3]) { - *getPixelPtr(x0+w2-x, y0+h2+y) = q[(h2+y)*width + w2-x]; - } - } - } -} - -void BitmapBuffer::drawBitmapPatternPie(coord_t x0, coord_t y0, const uint8_t * img, LcdFlags flags, int startAngle, int endAngle) -{ - coord_t width = *((uint16_t *)img); - coord_t height = *(((uint16_t *)img)+1); - const uint8_t * q = img+4; - - int slopes[4]; - if (!evalSlopes(slopes, startAngle, endAngle)) - return; - - display_t color = lcdColorTable[COLOR_IDX(flags)]; - - int w2 = width/2; - int h2 = height/2; - - for (int y=h2-1; y>=0; y--) { - for (int x=w2-1; x>=0; x--) { - int slope = (x==0 ? (y<0 ? -99000 : 99000) : y*100/x); - if (slope >= slopes[0] && slope < slopes[1]) { - drawAlphaPixel(x0+w2+x, y0+h2-y, q[(h2-y)*width + w2+x], color); - } - if (-slope >= slopes[0] && -slope < slopes[1]) { - drawAlphaPixel(x0+w2+x, y0+h2+y, q[(h2+y)*width + w2+x], color); - } - if (slope >= slopes[2] && slope < slopes[3]) { - drawAlphaPixel(x0+w2-x, y0+h2-y, q[(h2-y)*width + w2-x], color); - } - if (-slope >= slopes[2] && -slope < slopes[3]) { - drawAlphaPixel(x0+w2-x, y0+h2+y, q[(h2+y)*width + w2-x], color); - } - } - } -} - -BitmapBuffer * BitmapBuffer::load(const char * filename) -{ - const char * ext = getFileExtension(filename); - if (ext && !strcmp(ext, ".bmp")) - return load_bmp(filename); - else - return load_stb(filename); -} - -BitmapBuffer * BitmapBuffer::loadMask(const char * filename) -{ - BitmapBuffer * bitmap = BitmapBuffer::load(filename); - if (bitmap) { - display_t * p = bitmap->getPixelPtr(0, 0); - for (int i = bitmap->getWidth() * bitmap->getHeight(); i > 0; i--) { - *((uint8_t *)p) = OPACITY_MAX - ((*p) >> 12); - MOVE_TO_NEXT_RIGHT_PIXEL(p); - } - } - return bitmap; -} - -BitmapBuffer * BitmapBuffer::loadMaskOnBackground(const char * filename, LcdFlags foreground, LcdFlags background) -{ - BitmapBuffer * result = NULL; - BitmapBuffer * mask = BitmapBuffer::loadMask(getThemePath(filename)); - if (mask) { - result = new BitmapBuffer(BMP_RGB565, mask->getWidth(), mask->getHeight()); - if (result) { - result->clear(background); - result->drawMask(0, 0, mask, foreground); - } - delete mask; - } - return result; -} - -FIL imgFile __DMA; - -BitmapBuffer * BitmapBuffer::load_bmp(const char * filename) -{ - UINT read; - uint8_t palette[16]; - uint8_t bmpBuf[LCD_W]; /* maximum with LCD_W */ - uint8_t * buf = &bmpBuf[0]; - - FRESULT result = f_open(&imgFile, filename, FA_OPEN_EXISTING | FA_READ); - if (result != FR_OK) { - return NULL; - } - - if (f_size(&imgFile) < 14) { - f_close(&imgFile); - return NULL; - } - - result = f_read(&imgFile, buf, 14, &read); - if (result != FR_OK || read != 14) { - f_close(&imgFile); - return NULL; - } - - if (buf[0] != 'B' || buf[1] != 'M') { - f_close(&imgFile); - return NULL; - } - - uint32_t fsize = *((uint32_t *)&buf[2]); - uint32_t hsize = *((uint32_t *)&buf[10]); /* header size */ - - uint32_t len = limit((uint32_t)4, (uint32_t)(hsize-14), (uint32_t)32); - result = f_read(&imgFile, buf, len, &read); - if (result != FR_OK || read != len) { - f_close(&imgFile); - return NULL; - } - - uint32_t ihsize = *((uint32_t *)&buf[0]); /* more header size */ - - /* invalid header size */ - if (ihsize + 14 > hsize) { - f_close(&imgFile); - return NULL; - } - - /* sometimes file size is set to some headers size, set a real size in that case */ - if (fsize == 14 || fsize == ihsize + 14) - fsize = f_size(&imgFile) - 2; - - /* declared file size less than header size */ - if (fsize <= hsize) { - f_close(&imgFile); - return NULL; - } - - uint32_t w, h; - - switch (ihsize){ - case 40: // windib - case 56: // windib v3 - case 64: // OS/2 v2 - case 108: // windib v4 - case 124: // windib v5 - w = *((uint32_t *)&buf[4]); - h = *((uint32_t *)&buf[8]); - buf += 12; - break; - case 12: // OS/2 v1 - w = *((uint16_t *)&buf[4]); - h = *((uint16_t *)&buf[6]); - buf += 8; - break; - default: - f_close(&imgFile); - return NULL; - } - - if (*((uint16_t *)&buf[0]) != 1) { /* planes */ - f_close(&imgFile); - return NULL; - } - - uint16_t depth = *((uint16_t *)&buf[2]); - - buf = &bmpBuf[0]; - - if (depth == 4) { - if (f_lseek(&imgFile, hsize-64) != FR_OK || f_read(&imgFile, buf, 64, &read) != FR_OK || read != 64) { - f_close(&imgFile); - return NULL; - } - for (uint8_t i=0; i<16; i++) { - palette[i] = buf[4*i]; - } - } - else { - if (f_lseek(&imgFile, hsize) != FR_OK) { - f_close(&imgFile); - return NULL; - } - } - - BitmapBuffer * bmp = new BitmapBuffer(BMP_RGB565, w, h); - if (bmp == NULL || bmp->getData() == NULL) { - f_close(&imgFile); - return NULL; - } - - uint32_t rowSize; - bool hasAlpha = false; - - switch (depth) { - case 32: - for (int i=h-1; i>=0; i--) { - display_t * dst = bmp->getPixelPtr(0, i); - for (unsigned int j=0; j> 24) & 0xff, (pixel >> 16) & 0xff, (pixel >> 8) & 0xff); - } - else { - if ((pixel & 0xff) == 0xff) { - *dst = RGB(pixel >> 24, (pixel >> 16) & 0xff, (pixel >> 8) & 0xff); - } - else { - hasAlpha = true; - bmp->setFormat(BMP_ARGB4444); - for (display_t * p = bmp->getPixelPtr(j, i); p != bmp->getPixelPtr(0, h); MOVE_TO_NEXT_RIGHT_PIXEL(p)) { - display_t tmp = *p; - *p = ((tmp >> 1) & 0x0f) + (((tmp >> 7) & 0x0f) << 4) + (((tmp >> 12) & 0x0f) << 8); - } - *dst = ARGB(pixel & 0xff, (pixel >> 24) & 0xff, (pixel >> 16) & 0xff, (pixel >> 8) & 0xff); - } - } - MOVE_TO_NEXT_RIGHT_PIXEL(dst); - } - } - break; - - case 1: - break; - - case 4: - rowSize = ((4*w+31)/32)*4; - for (int32_t i=h-1; i>=0; i--) { - result = f_read(&imgFile, buf, rowSize, &read); - if (result != FR_OK || read != rowSize) { - f_close(&imgFile); - delete bmp; - return NULL; - } - display_t * dst = bmp->getPixelPtr(0, i); - for (uint32_t j=0; j> ((j & 1) ? 0 : 4)) & 0x0F; - uint8_t val = palette[index]; - *dst = RGB(val, val, val); - MOVE_TO_NEXT_RIGHT_PIXEL(dst); - } - } - break; - - default: - f_close(&imgFile); - delete bmp; - return NULL; - } - - f_close(&imgFile); - return bmp; -} - -#define STB_IMAGE_IMPLEMENTATION -#define STBI_ONLY_PNG -#define STBI_ONLY_JPEG -#define STBI_ONLY_BMP -#define STBI_ONLY_GIF -#define STBI_NO_STDIO -#define STBI_NO_HDR -#define STBI_NO_LINEAR - -// #define TRACE_STB_MALLOC - -#if defined(TRACE_STB_MALLOC) -#define STBI_MALLOC(sz) stb_malloc(sz) -#define STBI_REALLOC_SIZED(p,oldsz,newsz) stb_realloc(p,oldsz,newsz) -#define STBI_FREE(p) stb_free(p) - -void * stb_malloc(unsigned int size) -{ - void * res = malloc(size); - TRACE("malloc %d = %p", size, res); - return res; -} - -void stb_free(void *ptr) -{ - TRACE("free %p", ptr); - free(ptr); -} - -void *stb_realloc(void *ptr, unsigned int oldsz, unsigned int newsz) -{ - void * res = realloc(ptr, newsz); - TRACE("realloc %p, %d -> %d = %p", ptr, oldsz, newsz, res); - return res; -} -#endif // #if defined(TRACE_STB_MALLOC) - - -#include "thirdparty/Stb/stb_image.h" - -// fill 'data' with 'size' bytes. return number of bytes actually read -int stbc_read(void *user, char *data, int size) -{ - FIL * fp = (FIL *)user; - UINT br = 0; - FRESULT res = f_read(fp, data, size, &br); - if (res == FR_OK) { - return (int)br; - } - return 0; -} - -// skip the next 'n' bytes, or 'unget' the last -n bytes if negative -void stbc_skip(void *user, int n) -{ - FIL * fp = (FIL *)user; - f_lseek(fp, f_tell(fp) + n); -} - -// returns nonzero if we are at end of file/data -int stbc_eof(void *user) -{ - FIL * fp = (FIL *)user; - int res = f_eof(fp); - return res; -} - -// callbacks for stb-image -const stbi_io_callbacks stbCallbacks = { - stbc_read, - stbc_skip, - stbc_eof -}; - -BitmapBuffer * BitmapBuffer::load_stb(const char * filename) -{ - FRESULT result = f_open(&imgFile, filename, FA_OPEN_EXISTING | FA_READ); - if (result != FR_OK) { - return NULL; - } - - int w, h, n; - unsigned char * img = stbi_load_from_callbacks(&stbCallbacks, &imgFile, &w, &h, &n, 4); - f_close(&imgFile); - - if (!img) { - return NULL; - } - - // convert to RGB565 or ARGB4444 format - BitmapBuffer * bmp = new BitmapBuffer(n == 4 ? BMP_ARGB4444 : BMP_RGB565, w, h); - if (bmp == NULL) { - TRACE("load_stb() malloc failed"); - stbi_image_free(img); - return NULL; - } - -#if 0 - DMABitmapConvert(bmp->data, img, w, h, n == 4 ? DMA2D_ARGB4444 : DMA2D_RGB565); -#else - display_t * dest = bmp->getPixelPtr(0, 0); - const uint8_t * p = img; - if (n == 4) { - for (int row = 0; row < h; ++row) { - for (int col = 0; col < w; ++col) { - *dest = ARGB(p[3], p[0], p[1], p[2]); - MOVE_TO_NEXT_RIGHT_PIXEL(dest); - p += 4; - } - } - } - else { - for (int row = 0; row < h; ++row) { - for (int col = 0; col < w; ++col) { - *dest = RGB(p[0], p[1], p[2]); - MOVE_TO_NEXT_RIGHT_PIXEL(dest); - p += 4; - } - } - } -#endif - - stbi_image_free(img); - return bmp; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "opentx.h" + +void BitmapBuffer::drawAlphaPixel(display_t * p, uint8_t opacity, uint16_t color) +{ + if (opacity == OPACITY_MAX) { + drawPixel(p, color); + } + else if (opacity != 0) { + uint8_t bgWeight = OPACITY_MAX - opacity; + RGB_SPLIT(color, red, green, blue); + RGB_SPLIT(*p, bgRed, bgGreen, bgBlue); + uint16_t r = (bgRed * bgWeight + red * opacity) / OPACITY_MAX; + uint16_t g = (bgGreen * bgWeight + green * opacity) / OPACITY_MAX; + uint16_t b = (bgBlue * bgWeight + blue * opacity) / OPACITY_MAX; + drawPixel(p, RGB_JOIN(r, g, b)); + } +} + +void BitmapBuffer::drawHorizontalLine(coord_t x, coord_t y, coord_t w, uint8_t pat, LcdFlags att) +{ + if (y >= height) return; + if (x+w > width) { w = width - x; } + + display_t * p = getPixelPtr(x, y); + display_t color = lcdColorTable[COLOR_IDX(att)]; + uint8_t opacity = 0x0F - (att >> 24); + + if (pat == SOLID) { + while (w--) { + drawAlphaPixel(p, opacity, color); + MOVE_TO_NEXT_RIGHT_PIXEL(p); + } + } + else { + while (w--) { + if (pat & 1) { + drawAlphaPixel(p, opacity, color); + pat = (pat >> 1) | 0x80; + } + else { + pat = pat >> 1; + } + MOVE_TO_NEXT_RIGHT_PIXEL(p); + } + } +} + +void BitmapBuffer::drawVerticalLine(coord_t x, coord_t y, coord_t h, uint8_t pat, LcdFlags att) +{ + if (x >= width) return; + if (y >= height) return; + if (h<0) { y+=h; h=-h; } + if (y<0) { h+=y; y=0; if (h<=0) return; } + if (y+h > height) { h = height - y; } + + display_t color = lcdColorTable[COLOR_IDX(att)]; + uint8_t opacity = 0x0F - (att >> 24); + + if (pat == SOLID) { + while (h--) { + drawAlphaPixel(x, y, opacity, color); + y++; + } + } + else { + if (pat==DOTTED && !(y%2)) { + pat = ~pat; + } + while (h--) { + if (pat & 1) { + drawAlphaPixel(x, y, opacity, color); + pat = (pat >> 1) | 0x80; + } + else { + pat = pat >> 1; + } + y++; + } + } +} + +void BitmapBuffer::drawRect(coord_t x, coord_t y, coord_t w, coord_t h, uint8_t thickness, uint8_t pat, LcdFlags att) +{ + for (int i=0; i= 360 || endAngle <= 0) + return false; + + if (startAngle == 0) { + slopes[1] = 100000; + slopes[2] = -100000; + } + else { + float angle1 = float(startAngle) * (PI / 180.0f); + if (startAngle >= 180) { + slopes[1] = -100000; + slopes[2] = cosf(angle1) * 100 / sinf(angle1); + } + else { + slopes[1] = cosf(angle1) * 100 / sinf(angle1); + slopes[2] = -100000; + } + } + + if (endAngle == 360) { + slopes[0] = -100000; + slopes[3] = 100000; + } + else { + float angle2 = float(endAngle) * (PI / 180.0f); + if (endAngle >= 180) { + slopes[0] = -100000; + slopes[3] = -cosf(angle2) * 100 / sinf(angle2); + } + else { + slopes[0] = cosf(angle2) * 100 / sinf(angle2); + slopes[3] = -100000; + } + } + + return true; +} + +void BitmapBuffer::drawPie(int x0, int y0, int radius, int startAngle, int endAngle) +{ + int slopes[4]; + if (!evalSlopes(slopes, startAngle, endAngle)) + return; + + for (int y=0; y<=radius; y++) { + for (int x=0; x<=radius; x++) { + if (x*x+y*y <= radius*radius) { + int slope = (x==0 ? (y<0 ? -99000 : 99000) : y*100/x); + if (slope >= slopes[0] && slope < slopes[1]) { + drawPixel(x0+x, y0-y, WHITE); + } + if (-slope >= slopes[0] && -slope < slopes[1]) { + drawPixel(x0+x, y0+y, WHITE); + } + if (slope >= slopes[2] && slope < slopes[3]) { + drawPixel(x0-x, y0-y, WHITE); + } + if (-slope >= slopes[2] && -slope < slopes[3]) { + drawPixel(x0-x, y0+y, WHITE); + } + } + } + } +} + +void BitmapBuffer::drawMask(coord_t x, coord_t y, BitmapBuffer * mask, LcdFlags flags, coord_t offset, coord_t width) +{ + if (mask == NULL) { + return; + } + + coord_t w = mask->getWidth(); + coord_t height = mask->getHeight(); + + if (!width || width > w) { + width = w; + } + + if (x+width > this->width) { + width = this->width-x; + } + + display_t color = lcdColorTable[COLOR_IDX(flags)]; + + for (coord_t row=0; rowgetPixelPtr(offset, row); + for (coord_t col=0; col w) { + width = w; + } + + if (x+width > this->width) { + width = this->width-x; + } + + display_t color = lcdColorTable[COLOR_IDX(flags)]; + + for (coord_t row=0; row 0) drawBitmapPattern(x, y, font, flags, offset, width); + return width; +} + +uint8_t BitmapBuffer::drawCharWithCache(coord_t x, coord_t y, const BitmapBuffer * font, const uint16_t * spec, int index, LcdFlags flags) +{ + coord_t offset = spec[index]; + coord_t width = spec[index+1] - offset; + drawBitmap(x, y, font, offset, 0, width); + return width; +} + +void BitmapBuffer::drawSizedText(coord_t x, coord_t y, const char * s, uint8_t len, LcdFlags flags) +{ +#define INCREMENT_POS(delta) \ + do { if (flags & VERTICAL) y -= delta; else x += delta; } while(0) + + int width = getTextWidth(s, len, flags); + int height = getFontHeight(flags); + uint32_t fontindex = FONTINDEX(flags); + const pm_uchar * font = fontsTable[fontindex]; + const uint16_t * fontspecs = fontspecsTable[fontindex]; + BitmapBuffer * fontcache = NULL; + + if (flags & RIGHT) + INCREMENT_POS(-width); + else if (flags & CENTERED) + INCREMENT_POS(-width/2); + + coord_t & pos = (flags & VERTICAL) ? y : x; + + if ((flags & INVERS) && ((~flags & BLINK) || BLINK_ON_PHASE)) { + uint16_t fgColor = lcdColorTable[COLOR_IDX(flags)]; + if (fgColor == lcdColorTable[TEXT_COLOR_INDEX]) { + flags = TEXT_INVERTED_COLOR | (flags & 0x0ffff); + } + if (fontindex == STDSIZE_INDEX) { + if (fgColor == lcdColorTable[TEXT_COLOR_INDEX]) { + drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y, INVERT_HORZ_MARGIN-1, INVERT_LINE_HEIGHT, TEXT_INVERTED_BGCOLOR); + drawSolidFilledRect(x+width-1, y, INVERT_HORZ_MARGIN, INVERT_LINE_HEIGHT, TEXT_INVERTED_BGCOLOR); + fontcache = fontCache[1]; + } + else { + drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y, width+2*INVERT_HORZ_MARGIN-1, INVERT_LINE_HEIGHT, TEXT_INVERTED_BGCOLOR); + } + } + else if (fontindex == TINSIZE_INDEX) { + drawSolidFilledRect(x-INVERT_HORZ_MARGIN+2, y, width+2*INVERT_HORZ_MARGIN-5, height+2, TEXT_INVERTED_BGCOLOR); + } + else if (fontindex == SMLSIZE_INDEX) { + drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y, width+2*INVERT_HORZ_MARGIN-2, height+2, TEXT_INVERTED_BGCOLOR); + } + else if (fontindex == MIDSIZE_INDEX) { + drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y-1, width+2*INVERT_HORZ_MARGIN-2, height+3, TEXT_INVERTED_BGCOLOR); // MIDSIZE and DBLSIZE font are missing a pixel on top compared to others + } + else if (fontindex == DBLSIZE_INDEX) { + drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y-1, width+2*INVERT_HORZ_MARGIN-2, height+3, TEXT_INVERTED_BGCOLOR); // MIDSIZE and DBLSIZE font are missing a pixel on top compared to others + } + else if (fontindex == XXLSIZE_INDEX) { + drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y, width+2*INVERT_HORZ_MARGIN-2, height+2, TEXT_INVERTED_BGCOLOR); + } + else { + drawSolidFilledRect(x-INVERT_HORZ_MARGIN, y, width+2*INVERT_HORZ_MARGIN, INVERT_LINE_HEIGHT, TEXT_INVERTED_BGCOLOR); + } + } + else if (!(flags & NO_FONTCACHE)) { + if (fontindex == STDSIZE_INDEX) { + uint16_t fgColor = lcdColorTable[COLOR_IDX(flags)]; + uint16_t bgColor = *getPixelPtr(x, y); + if (fgColor == lcdColorTable[TEXT_COLOR_INDEX] && bgColor == lcdColorTable[TEXT_BGCOLOR_INDEX]) { + fontcache = fontCache[0]; + } + else if (fgColor == lcdColorTable[TEXT_INVERTED_COLOR_INDEX] && bgColor == lcdColorTable[TEXT_INVERTED_BGCOLOR_INDEX]) { + fontcache = fontCache[1]; + } + else { + // TRACE("No cache for \"%s\"", s); + } + } + } + + bool setpos = false; + const coord_t orig_pos = pos; + while (len--) { + unsigned char c; + if (flags & ZCHAR) + c = idx2char(*s); + else + c = pgm_read_byte(s); + if (setpos) { + pos = c; + setpos = false; + } + else if (!c) { + break; + } + else if (c >= 0x20) { + uint8_t width; + if (fontcache) + width = drawCharWithCache(x-1, y, fontcache, fontspecs, getMappedChar(c), flags); + else + width = drawCharWithoutCache(x-1, y, font, fontspecs, getMappedChar(c), flags); + INCREMENT_POS(width); + } + else if (c == 0x1F) { // X-coord prefix + setpos = true; + } + else if (c == 0x1E) { + pos = orig_pos; + if (flags & VERTICAL) + x += height; + else + y += height; + } + else if (c == 1) { + INCREMENT_POS(1); + } + else { + INCREMENT_POS(2*(c-1)); + } + s++; + } + lcdNextPos = pos; +} + +void BitmapBuffer::drawBitmapPie(int x0, int y0, const uint16_t * img, int startAngle, int endAngle) +{ + const uint16_t * q = img; + coord_t width = *q++; + coord_t height = *q++; + + int slopes[4]; + if (!evalSlopes(slopes, startAngle, endAngle)) + return; + + int w2 = width/2; + int h2 = height/2; + + for (int y=h2-1; y>=0; y--) { + for (int x=w2-1; x>=0; x--) { + int slope = (x==0 ? (y<0 ? -99000 : 99000) : y*100/x); + if (slope >= slopes[0] && slope < slopes[1]) { + *getPixelPtr(x0+w2+x, y0+h2-y) = q[(h2-y)*width + w2+x]; + } + if (-slope >= slopes[0] && -slope < slopes[1]) { + *getPixelPtr(x0+w2+x, y0+h2+y) = q[(h2+y)*width + w2+x]; + } + if (slope >= slopes[2] && slope < slopes[3]) { + *getPixelPtr(x0+w2-x, y0+h2-y) = q[(h2-y)*width + w2-x]; + } + if (-slope >= slopes[2] && -slope < slopes[3]) { + *getPixelPtr(x0+w2-x, y0+h2+y) = q[(h2+y)*width + w2-x]; + } + } + } +} + +void BitmapBuffer::drawBitmapPatternPie(coord_t x0, coord_t y0, const uint8_t * img, LcdFlags flags, int startAngle, int endAngle) +{ + coord_t width = *((uint16_t *)img); + coord_t height = *(((uint16_t *)img)+1); + const uint8_t * q = img+4; + + int slopes[4]; + if (!evalSlopes(slopes, startAngle, endAngle)) + return; + + display_t color = lcdColorTable[COLOR_IDX(flags)]; + + int w2 = width/2; + int h2 = height/2; + + for (int y=h2-1; y>=0; y--) { + for (int x=w2-1; x>=0; x--) { + int slope = (x==0 ? (y<0 ? -99000 : 99000) : y*100/x); + if (slope >= slopes[0] && slope < slopes[1]) { + drawAlphaPixel(x0+w2+x, y0+h2-y, q[(h2-y)*width + w2+x], color); + } + if (-slope >= slopes[0] && -slope < slopes[1]) { + drawAlphaPixel(x0+w2+x, y0+h2+y, q[(h2+y)*width + w2+x], color); + } + if (slope >= slopes[2] && slope < slopes[3]) { + drawAlphaPixel(x0+w2-x, y0+h2-y, q[(h2-y)*width + w2-x], color); + } + if (-slope >= slopes[2] && -slope < slopes[3]) { + drawAlphaPixel(x0+w2-x, y0+h2+y, q[(h2+y)*width + w2-x], color); + } + } + } +} + +BitmapBuffer * BitmapBuffer::load(const char * filename) +{ + const char * ext = getFileExtension(filename); + if (ext && !strcmp(ext, ".bmp")) + return load_bmp(filename); + else + return load_stb(filename); +} + +BitmapBuffer * BitmapBuffer::loadMask(const char * filename) +{ + BitmapBuffer * bitmap = BitmapBuffer::load(filename); + if (bitmap) { + display_t * p = bitmap->getPixelPtr(0, 0); + for (int i = bitmap->getWidth() * bitmap->getHeight(); i > 0; i--) { + *((uint8_t *)p) = OPACITY_MAX - ((*p) >> 12); + MOVE_TO_NEXT_RIGHT_PIXEL(p); + } + } + return bitmap; +} + +BitmapBuffer * BitmapBuffer::loadMaskOnBackground(const char * filename, LcdFlags foreground, LcdFlags background) +{ + BitmapBuffer * result = NULL; + BitmapBuffer * mask = BitmapBuffer::loadMask(getThemePath(filename)); + if (mask) { + result = new BitmapBuffer(BMP_RGB565, mask->getWidth(), mask->getHeight()); + if (result) { + result->clear(background); + result->drawMask(0, 0, mask, foreground); + } + delete mask; + } + return result; +} + +FIL imgFile __DMA; + +BitmapBuffer * BitmapBuffer::load_bmp(const char * filename) +{ + UINT read; + uint8_t palette[16]; + uint8_t bmpBuf[LCD_W]; /* maximum with LCD_W */ + uint8_t * buf = &bmpBuf[0]; + + FRESULT result = f_open(&imgFile, filename, FA_OPEN_EXISTING | FA_READ); + if (result != FR_OK) { + return NULL; + } + + if (f_size(&imgFile) < 14) { + f_close(&imgFile); + return NULL; + } + + result = f_read(&imgFile, buf, 14, &read); + if (result != FR_OK || read != 14) { + f_close(&imgFile); + return NULL; + } + + if (buf[0] != 'B' || buf[1] != 'M') { + f_close(&imgFile); + return NULL; + } + + uint32_t fsize = *((uint32_t *)&buf[2]); + uint32_t hsize = *((uint32_t *)&buf[10]); /* header size */ + + uint32_t len = limit((uint32_t)4, (uint32_t)(hsize-14), (uint32_t)32); + result = f_read(&imgFile, buf, len, &read); + if (result != FR_OK || read != len) { + f_close(&imgFile); + return NULL; + } + + uint32_t ihsize = *((uint32_t *)&buf[0]); /* more header size */ + + /* invalid header size */ + if (ihsize + 14 > hsize) { + f_close(&imgFile); + return NULL; + } + + /* sometimes file size is set to some headers size, set a real size in that case */ + if (fsize == 14 || fsize == ihsize + 14) + fsize = f_size(&imgFile) - 2; + + /* declared file size less than header size */ + if (fsize <= hsize) { + f_close(&imgFile); + return NULL; + } + + uint32_t w, h; + + switch (ihsize){ + case 40: // windib + case 56: // windib v3 + case 64: // OS/2 v2 + case 108: // windib v4 + case 124: // windib v5 + w = *((uint32_t *)&buf[4]); + h = *((uint32_t *)&buf[8]); + buf += 12; + break; + case 12: // OS/2 v1 + w = *((uint16_t *)&buf[4]); + h = *((uint16_t *)&buf[6]); + buf += 8; + break; + default: + f_close(&imgFile); + return NULL; + } + + if (*((uint16_t *)&buf[0]) != 1) { /* planes */ + f_close(&imgFile); + return NULL; + } + + uint16_t depth = *((uint16_t *)&buf[2]); + + buf = &bmpBuf[0]; + + if (depth == 4) { + if (f_lseek(&imgFile, hsize-64) != FR_OK || f_read(&imgFile, buf, 64, &read) != FR_OK || read != 64) { + f_close(&imgFile); + return NULL; + } + for (uint8_t i=0; i<16; i++) { + palette[i] = buf[4*i]; + } + } + else { + if (f_lseek(&imgFile, hsize) != FR_OK) { + f_close(&imgFile); + return NULL; + } + } + + BitmapBuffer * bmp = new BitmapBuffer(BMP_RGB565, w, h); + if (bmp == NULL || bmp->getData() == NULL) { + f_close(&imgFile); + return NULL; + } + + uint32_t rowSize; + bool hasAlpha = false; + + switch (depth) { + case 32: + for (int i=h-1; i>=0; i--) { + display_t * dst = bmp->getPixelPtr(0, i); + for (unsigned int j=0; j> 24) & 0xff, (pixel >> 16) & 0xff, (pixel >> 8) & 0xff); + } + else { + if ((pixel & 0xff) == 0xff) { + *dst = RGB(pixel >> 24, (pixel >> 16) & 0xff, (pixel >> 8) & 0xff); + } + else { + hasAlpha = true; + bmp->setFormat(BMP_ARGB4444); + for (display_t * p = bmp->getPixelPtr(j, i); p != bmp->getPixelPtr(0, h); MOVE_TO_NEXT_RIGHT_PIXEL(p)) { + display_t tmp = *p; + *p = ((tmp >> 1) & 0x0f) + (((tmp >> 7) & 0x0f) << 4) + (((tmp >> 12) & 0x0f) << 8); + } + *dst = ARGB(pixel & 0xff, (pixel >> 24) & 0xff, (pixel >> 16) & 0xff, (pixel >> 8) & 0xff); + } + } + MOVE_TO_NEXT_RIGHT_PIXEL(dst); + } + } + break; + + case 1: + break; + + case 4: + rowSize = ((4*w+31)/32)*4; + for (int32_t i=h-1; i>=0; i--) { + result = f_read(&imgFile, buf, rowSize, &read); + if (result != FR_OK || read != rowSize) { + f_close(&imgFile); + delete bmp; + return NULL; + } + display_t * dst = bmp->getPixelPtr(0, i); + for (uint32_t j=0; j> ((j & 1) ? 0 : 4)) & 0x0F; + uint8_t val = palette[index]; + *dst = RGB(val, val, val); + MOVE_TO_NEXT_RIGHT_PIXEL(dst); + } + } + break; + + default: + f_close(&imgFile); + delete bmp; + return NULL; + } + + f_close(&imgFile); + return bmp; +} + +#define STB_IMAGE_IMPLEMENTATION +#define STBI_ONLY_PNG +#define STBI_ONLY_JPEG +#define STBI_ONLY_BMP +#define STBI_ONLY_GIF +#define STBI_NO_STDIO +#define STBI_NO_HDR +#define STBI_NO_LINEAR + +// #define TRACE_STB_MALLOC + +#if defined(TRACE_STB_MALLOC) +#define STBI_MALLOC(sz) stb_malloc(sz) +#define STBI_REALLOC_SIZED(p,oldsz,newsz) stb_realloc(p,oldsz,newsz) +#define STBI_FREE(p) stb_free(p) + +void * stb_malloc(unsigned int size) +{ + void * res = malloc(size); + TRACE("malloc %d = %p", size, res); + return res; +} + +void stb_free(void *ptr) +{ + TRACE("free %p", ptr); + free(ptr); +} + +void *stb_realloc(void *ptr, unsigned int oldsz, unsigned int newsz) +{ + void * res = realloc(ptr, newsz); + TRACE("realloc %p, %d -> %d = %p", ptr, oldsz, newsz, res); + return res; +} +#endif // #if defined(TRACE_STB_MALLOC) + + +#include "thirdparty/Stb/stb_image.h" + +// fill 'data' with 'size' bytes. return number of bytes actually read +int stbc_read(void *user, char *data, int size) +{ + FIL * fp = (FIL *)user; + UINT br = 0; + FRESULT res = f_read(fp, data, size, &br); + if (res == FR_OK) { + return (int)br; + } + return 0; +} + +// skip the next 'n' bytes, or 'unget' the last -n bytes if negative +void stbc_skip(void *user, int n) +{ + FIL * fp = (FIL *)user; + f_lseek(fp, f_tell(fp) + n); +} + +// returns nonzero if we are at end of file/data +int stbc_eof(void *user) +{ + FIL * fp = (FIL *)user; + int res = f_eof(fp); + return res; +} + +// callbacks for stb-image +const stbi_io_callbacks stbCallbacks = { + stbc_read, + stbc_skip, + stbc_eof +}; + +BitmapBuffer * BitmapBuffer::load_stb(const char * filename) +{ + FRESULT result = f_open(&imgFile, filename, FA_OPEN_EXISTING | FA_READ); + if (result != FR_OK) { + return NULL; + } + + int w, h, n; + unsigned char * img = stbi_load_from_callbacks(&stbCallbacks, &imgFile, &w, &h, &n, 4); + f_close(&imgFile); + + if (!img) { + return NULL; + } + + // convert to RGB565 or ARGB4444 format + BitmapBuffer * bmp = new BitmapBuffer(n == 4 ? BMP_ARGB4444 : BMP_RGB565, w, h); + if (bmp == NULL) { + TRACE("load_stb() malloc failed"); + stbi_image_free(img); + return NULL; + } + +#if 0 + DMABitmapConvert(bmp->data, img, w, h, n == 4 ? DMA2D_ARGB4444 : DMA2D_RGB565); +#else + display_t * dest = bmp->getPixelPtr(0, 0); + const uint8_t * p = img; + if (n == 4) { + for (int row = 0; row < h; ++row) { + for (int col = 0; col < w; ++col) { + *dest = ARGB(p[3], p[0], p[1], p[2]); + MOVE_TO_NEXT_RIGHT_PIXEL(dest); + p += 4; + } + } + } + else { + for (int row = 0; row < h; ++row) { + for (int col = 0; col < w; ++col) { + *dest = RGB(p[0], p[1], p[2]); + MOVE_TO_NEXT_RIGHT_PIXEL(dest); + p += 4; + } + } + } +#endif + + stbi_image_free(img); + return bmp; +} diff --git a/radio/src/gui/480x272/fonts.cpp b/radio/src/gui/480x272/fonts.cpp index 32aa2d22b..ea953f059 100644 --- a/radio/src/gui/480x272/fonts.cpp +++ b/radio/src/gui/480x272/fonts.cpp @@ -1,110 +1,110 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -const uint16_t font_tinsize_specs[] = { -#include "font_tinsize.specs" -}; - -const pm_uchar font_tinsize[] = { -#include "font_tinsize.lbm" -}; - -const uint16_t font_smlsize_specs[] = { -#include "font_smlsize.specs" -}; - -const pm_uchar font_smlsize[] = { -#include "font_smlsize.lbm" -}; - -const uint16_t font_stdsize_specs[] = { -#include "font_stdsize.specs" -}; - -const pm_uchar font_stdsize[] = { -#include "font_stdsize.lbm" -}; - -const uint16_t font_midsize_specs[] = { -#include "font_midsize.specs" -}; - -const pm_uchar font_midsize[] = { -#include "font_midsize.lbm" -}; - -const uint16_t font_dblsize_specs[] = { -#include "font_dblsize.specs" -}; - -const pm_uchar font_dblsize[] = { -#include "font_dblsize.lbm" -}; - -const uint16_t font_xxlsize_specs[] = { -#include "font_xxlsize.specs" -}; - -const pm_uchar font_xxlsize[] = { -#include "font_xxlsize.lbm" -}; - -const uint16_t font_stdsizebold_specs[] = { -#include "font_stdsizebold.specs" -}; - -const pm_uchar font_stdsizebold[] = { -#include "font_stdsizebold.lbm" -}; - -const uint16_t * const fontspecsTable[16] = { - font_stdsize_specs, font_tinsize_specs, font_smlsize_specs, font_midsize_specs, font_dblsize_specs, font_xxlsize_specs, font_stdsize_specs, font_stdsize_specs, - font_stdsizebold_specs, font_tinsize_specs, font_smlsize_specs, font_midsize_specs, font_dblsize_specs, font_xxlsize_specs, font_stdsize_specs, font_stdsize_specs -}; - -const uint8_t * const fontsTable[16] = { - font_stdsize, font_tinsize, font_smlsize, font_midsize, font_dblsize, font_xxlsize, font_stdsize, font_stdsize, - font_stdsizebold, font_tinsize, font_smlsize, font_midsize, font_dblsize, font_xxlsize, font_stdsize, font_stdsize -}; - -BitmapBuffer * fontCache[2] = { NULL, NULL }; - -BitmapBuffer * createFontCache(const uint8_t * font, LcdFlags fg, LcdFlags bg) -{ - coord_t width = *((uint16_t *)font); - coord_t height = *(((uint16_t *)font)+1); - - BitmapBuffer * buffer = new BitmapBuffer(BMP_RGB565, width, height); - if (buffer) { - buffer->clear(bg); - buffer->drawBitmapPattern(0, 0, font, fg); - } - return buffer; -} - -void loadFontCache() -{ - delete fontCache[0]; - delete fontCache[1]; - fontCache[0] = createFontCache(fontsTable[0], TEXT_COLOR, TEXT_BGCOLOR); - fontCache[1] = createFontCache(fontsTable[0], TEXT_INVERTED_COLOR, TEXT_INVERTED_BGCOLOR); -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +const uint16_t font_tinsize_specs[] = { +#include "font_tinsize.specs" +}; + +const pm_uchar font_tinsize[] = { +#include "font_tinsize.lbm" +}; + +const uint16_t font_smlsize_specs[] = { +#include "font_smlsize.specs" +}; + +const pm_uchar font_smlsize[] = { +#include "font_smlsize.lbm" +}; + +const uint16_t font_stdsize_specs[] = { +#include "font_stdsize.specs" +}; + +const pm_uchar font_stdsize[] = { +#include "font_stdsize.lbm" +}; + +const uint16_t font_midsize_specs[] = { +#include "font_midsize.specs" +}; + +const pm_uchar font_midsize[] = { +#include "font_midsize.lbm" +}; + +const uint16_t font_dblsize_specs[] = { +#include "font_dblsize.specs" +}; + +const pm_uchar font_dblsize[] = { +#include "font_dblsize.lbm" +}; + +const uint16_t font_xxlsize_specs[] = { +#include "font_xxlsize.specs" +}; + +const pm_uchar font_xxlsize[] = { +#include "font_xxlsize.lbm" +}; + +const uint16_t font_stdsizebold_specs[] = { +#include "font_stdsizebold.specs" +}; + +const pm_uchar font_stdsizebold[] = { +#include "font_stdsizebold.lbm" +}; + +const uint16_t * const fontspecsTable[16] = { + font_stdsize_specs, font_tinsize_specs, font_smlsize_specs, font_midsize_specs, font_dblsize_specs, font_xxlsize_specs, font_stdsize_specs, font_stdsize_specs, + font_stdsizebold_specs, font_tinsize_specs, font_smlsize_specs, font_midsize_specs, font_dblsize_specs, font_xxlsize_specs, font_stdsize_specs, font_stdsize_specs +}; + +const uint8_t * const fontsTable[16] = { + font_stdsize, font_tinsize, font_smlsize, font_midsize, font_dblsize, font_xxlsize, font_stdsize, font_stdsize, + font_stdsizebold, font_tinsize, font_smlsize, font_midsize, font_dblsize, font_xxlsize, font_stdsize, font_stdsize +}; + +BitmapBuffer * fontCache[2] = { NULL, NULL }; + +BitmapBuffer * createFontCache(const uint8_t * font, LcdFlags fg, LcdFlags bg) +{ + coord_t width = *((uint16_t *)font); + coord_t height = *(((uint16_t *)font)+1); + + BitmapBuffer * buffer = new BitmapBuffer(BMP_RGB565, width, height); + if (buffer) { + buffer->clear(bg); + buffer->drawBitmapPattern(0, 0, font, fg); + } + return buffer; +} + +void loadFontCache() +{ + delete fontCache[0]; + delete fontCache[1]; + fontCache[0] = createFontCache(fontsTable[0], TEXT_COLOR, TEXT_BGCOLOR); + fontCache[1] = createFontCache(fontsTable[0], TEXT_INVERTED_COLOR, TEXT_INVERTED_BGCOLOR); +} diff --git a/radio/src/gui/480x272/view_about.cpp b/radio/src/gui/480x272/view_about.cpp index 87634a0fe..3f5e14660 100644 --- a/radio/src/gui/480x272/view_about.cpp +++ b/radio/src/gui/480x272/view_about.cpp @@ -1,153 +1,153 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -enum AboutScreens { - ABOUT_OPENTX, - ABOUT_HARDWARE, - ABOUT_BERTRAND, - ABOUT_ANDRE, - ABOUT_MIKE, - ABOUT_KJELL, - ABOUT_MARTIN, - ABOUT_ROMOLO, - ABOUT_ROB, - ABOUT_PARENTS, - ABOUT_END, - ABOUT_COUNT, -}; - -#define ABOUT_X 62 -#define ABOUT_INDENT 16 - -bool menuAboutView(event_t event) -{ - static uint8_t screenIndex = 0; - static uint8_t greyIndex = 0; - - switch (event) { - case EVT_ENTRY: - screenIndex = 0; - greyIndex = 0; - break; -#if defined(PCBX12S) - case EVT_KEY_FIRST(KEY_PGDN): -#elif defined(PCBX10) - case EVT_KEY_BREAK(KEY_PGDN): -#endif - screenIndex < ABOUT_PARENTS ? screenIndex++ : screenIndex = ABOUT_OPENTX; - greyIndex = 0; - break; - case EVT_KEY_FIRST(KEY_PGUP): -#if defined(PCBX10) - case EVT_KEY_LONG(KEY_PGDN): -#endif - screenIndex > ABOUT_OPENTX ? screenIndex-- : screenIndex = ABOUT_PARENTS; - greyIndex = 0; - killEvents(event); - break; - case EVT_KEY_FIRST(KEY_EXIT): - chainMenu(menuMainView); - break; - } - - theme->drawBackground(); - theme->drawTopbarBackground(0); - - uint8_t screenDuration = 150; - - switch (screenIndex) { - case ABOUT_OPENTX: - case ABOUT_END: - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_OPENTX_1); - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP + FH, STR_ABOUT_OPENTX_2); - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_OPENTX_3); - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP + 3*FH, STR_ABOUT_OPENTX_4); - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP + 4*FH, STR_ABOUT_OPENTX_5); - screenDuration = 255; - break; - - case ABOUT_BERTRAND: - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_BERTRAND_1, INVERS); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_BERTRAND_2); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_BERTRAND_3); - break; - - case ABOUT_ANDRE: - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_ANDRE_1, INVERS); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_ANDRE_2); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_ANDRE_3); - break; - - case ABOUT_MIKE: - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_MIKE_1, INVERS); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_MIKE_2); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_MIKE_3); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 3*FH, STR_ABOUT_MIKE_4); - break; - - case ABOUT_KJELL: - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_KJELL_1, INVERS); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_KJELL_2); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_KJELL_3); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 3*FH, STR_ABOUT_KJELL_4); - break; - - case ABOUT_MARTIN: - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_MARTIN_1, INVERS); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_MARTIN_2); - break; - - case ABOUT_ROMOLO: - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_ROMOLO_1, INVERS); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_ROMOLO_2); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_ROMOLO_3); - break; - - case ABOUT_ROB: - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_ROB_1, INVERS); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_ROB_2); - break; - - case ABOUT_HARDWARE: - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, "FrSky", INVERS); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_HARDWARE_2); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_HARDWARE_3); - break; - - case ABOUT_PARENTS: - lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_PARENTS_1, INVERS); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_PARENTS_2); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_PARENTS_3); - lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 3*FH, STR_ABOUT_PARENTS_4); - screenDuration = 255; - break; - } - - if (++greyIndex == screenDuration) { - greyIndex = 0; - if (++screenIndex == ABOUT_COUNT) { - chainMenu(menuMainView); - } - } - - return true; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +enum AboutScreens { + ABOUT_OPENTX, + ABOUT_HARDWARE, + ABOUT_BERTRAND, + ABOUT_ANDRE, + ABOUT_MIKE, + ABOUT_KJELL, + ABOUT_MARTIN, + ABOUT_ROMOLO, + ABOUT_ROB, + ABOUT_PARENTS, + ABOUT_END, + ABOUT_COUNT, +}; + +#define ABOUT_X 62 +#define ABOUT_INDENT 16 + +bool menuAboutView(event_t event) +{ + static uint8_t screenIndex = 0; + static uint8_t greyIndex = 0; + + switch (event) { + case EVT_ENTRY: + screenIndex = 0; + greyIndex = 0; + break; +#if defined(PCBX12S) + case EVT_KEY_FIRST(KEY_PGDN): +#elif defined(PCBX10) + case EVT_KEY_BREAK(KEY_PGDN): +#endif + screenIndex < ABOUT_PARENTS ? screenIndex++ : screenIndex = ABOUT_OPENTX; + greyIndex = 0; + break; + case EVT_KEY_FIRST(KEY_PGUP): +#if defined(PCBX10) + case EVT_KEY_LONG(KEY_PGDN): +#endif + screenIndex > ABOUT_OPENTX ? screenIndex-- : screenIndex = ABOUT_PARENTS; + greyIndex = 0; + killEvents(event); + break; + case EVT_KEY_FIRST(KEY_EXIT): + chainMenu(menuMainView); + break; + } + + theme->drawBackground(); + theme->drawTopbarBackground(0); + + uint8_t screenDuration = 150; + + switch (screenIndex) { + case ABOUT_OPENTX: + case ABOUT_END: + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_OPENTX_1); + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP + FH, STR_ABOUT_OPENTX_2); + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_OPENTX_3); + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP + 3*FH, STR_ABOUT_OPENTX_4); + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP + 4*FH, STR_ABOUT_OPENTX_5); + screenDuration = 255; + break; + + case ABOUT_BERTRAND: + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_BERTRAND_1, INVERS); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_BERTRAND_2); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_BERTRAND_3); + break; + + case ABOUT_ANDRE: + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_ANDRE_1, INVERS); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_ANDRE_2); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_ANDRE_3); + break; + + case ABOUT_MIKE: + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_MIKE_1, INVERS); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_MIKE_2); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_MIKE_3); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 3*FH, STR_ABOUT_MIKE_4); + break; + + case ABOUT_KJELL: + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_KJELL_1, INVERS); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_KJELL_2); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_KJELL_3); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 3*FH, STR_ABOUT_KJELL_4); + break; + + case ABOUT_MARTIN: + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_MARTIN_1, INVERS); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_MARTIN_2); + break; + + case ABOUT_ROMOLO: + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_ROMOLO_1, INVERS); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_ROMOLO_2); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_ROMOLO_3); + break; + + case ABOUT_ROB: + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_ROB_1, INVERS); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_ROB_2); + break; + + case ABOUT_HARDWARE: + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, "FrSky", INVERS); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_HARDWARE_2); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_HARDWARE_3); + break; + + case ABOUT_PARENTS: + lcdDrawText(ABOUT_X, MENU_CONTENT_TOP, STR_ABOUT_PARENTS_1, INVERS); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + FH, STR_ABOUT_PARENTS_2); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 2*FH, STR_ABOUT_PARENTS_3); + lcdDrawText(ABOUT_X+ABOUT_INDENT, MENU_CONTENT_TOP + 3*FH, STR_ABOUT_PARENTS_4); + screenDuration = 255; + break; + } + + if (++greyIndex == screenDuration) { + greyIndex = 0; + if (++screenIndex == ABOUT_COUNT) { + chainMenu(menuMainView); + } + } + + return true; +} diff --git a/radio/src/gui/480x272/view_channels.cpp b/radio/src/gui/480x272/view_channels.cpp index c2bb86704..1de4cfc00 100644 --- a/radio/src/gui/480x272/view_channels.cpp +++ b/radio/src/gui/480x272/view_channels.cpp @@ -1,192 +1,192 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#define RECT_OFFSET 80 -#define ROW_HEIGHT 42 -#define BAR_HEIGHT 13 -#define COLUMN_SIZE 200 -#define X_OFFSET 25 -#define Y_OFFSET 75 -#define Y_OUTBAR 15 -#define Y_MIXBAR 28 -#define LEG_COLORBOX 15 - -#define VIEW_CHANNELS_LIMIT_PCT (g_model.extendedLimits ? LIMIT_EXT_PERCENT : 100) - -bool menuChannelsMonitor(event_t event, uint8_t page); -bool menuLogicalSwitches(event_t); - -template -bool menuChannelsMonitor(event_t event) -{ - lastMonitorPage = e_MonChannelsFirst + index; - MENU(STR_MONITOR_CHANNELS[index], MONITOR_ICONS, menuTabMonitors, lastMonitorPage, 0, { 0 }); - return menuChannelsMonitor(event, index); -} - -const MenuHandlerFunc menuTabMonitors[] PROGMEM = { - menuChannelsMonitor<0>, - menuChannelsMonitor<1>, - menuChannelsMonitor<2>, - menuChannelsMonitor<3>, - menuLogicalSwitches -}; - -uint8_t lastMonitorPage = 0; - -uint16_t posOnBar(int16_t value_to100) -{ - return divRoundClosest((value_to100 + VIEW_CHANNELS_LIMIT_PCT) * COLUMN_SIZE, VIEW_CHANNELS_LIMIT_PCT * 2); -} - -void drawOutputBarLimits(coord_t left, coord_t right, coord_t y) -{ - lcd->drawSolidVerticalLine(left, y, BAR_HEIGHT, TEXT_COLOR); - lcd->drawSolidHorizontalLine(left, y, 3, TEXT_COLOR); - lcd->drawSolidHorizontalLine(left, y + BAR_HEIGHT - 1, 3, TEXT_COLOR); - - lcd->drawSolidVerticalLine(--right, y, BAR_HEIGHT, TEXT_COLOR); - lcd->drawSolidHorizontalLine(right - 3, y, 3, TEXT_COLOR); - lcd->drawSolidHorizontalLine(right - 3, y + BAR_HEIGHT - 1, 3, TEXT_COLOR); -} - -void drawSingleMixerBar(coord_t x, coord_t y, coord_t w, coord_t h, uint8_t channel) -{ - int16_t chanVal = calcRESXto100(ex_chans[channel]); - const int16_t displayVal = chanVal; - - // this could be handled nicer, but slower, by checking actual range for this mixer - chanVal = limit(-VIEW_CHANNELS_LIMIT_PCT, chanVal, VIEW_CHANNELS_LIMIT_PCT); - - lcdDrawSolidFilledRect(x, y, w, h, BARGRAPH_BGCOLOR); - if (chanVal > 0) { - lcdDrawSolidFilledRect(x + w / 2, y, divRoundClosest(chanVal * w, VIEW_CHANNELS_LIMIT_PCT * 2), h, BARGRAPH2_COLOR); - lcdDrawNumber(x - 10 + w / 2, y - 2, displayVal, SMLSIZE | TEXT_COLOR | RIGHT, 0, NULL, "%"); - } - else if (chanVal < 0) { - const uint16_t endpoint = x + w / 2; - const uint16_t size = divRoundClosest(-chanVal * w, VIEW_CHANNELS_LIMIT_PCT * 2); - lcdDrawSolidFilledRect(endpoint - size, y, size, h, BARGRAPH2_COLOR); - lcdDrawNumber(x + 10 + w / 2, y - 2, displayVal, SMLSIZE | TEXT_COLOR, 0, NULL, "%"); - } - - lcd->drawSolidVerticalLine(x + w / 2, y, h, TEXT_COLOR); -} - -void drawSingleOutputBar(coord_t x, coord_t y, coord_t w, coord_t h, uint8_t channel) -{ - int16_t chanVal = calcRESXto100(channelOutputs[channel]); - int16_t displayVal = chanVal; - - chanVal = limit(-VIEW_CHANNELS_LIMIT_PCT, chanVal, VIEW_CHANNELS_LIMIT_PCT); - - lcdDrawSolidFilledRect(x, y, w, h, BARGRAPH_BGCOLOR); - if (chanVal > 0) { - lcdDrawSolidFilledRect(x + w / 2, y, divRoundClosest(chanVal * w, VIEW_CHANNELS_LIMIT_PCT * 2), h, BARGRAPH1_COLOR); - lcdDrawNumber(x - 10 + w / 2, y - 2, displayVal, SMLSIZE | TEXT_COLOR | RIGHT, 0, NULL, "%"); - } - else if (chanVal < 0) { - uint16_t endpoint = x + w / 2; - uint16_t size = divRoundClosest(-chanVal * w, VIEW_CHANNELS_LIMIT_PCT * 2); - lcdDrawSolidFilledRect(endpoint - size, y, size, h, BARGRAPH1_COLOR); - lcdDrawNumber(x + 10 + w / 2, y - 2, displayVal, SMLSIZE | TEXT_COLOR, 0, NULL, "%"); - } - - lcd->drawSolidVerticalLine(x + w / 2, y, h, TEXT_COLOR); -} - -void drawComboOutputBar(coord_t x, coord_t y, coord_t w, coord_t h, uint8_t channel) -{ - char chanString[] = "Ch32 "; - int16_t chanVal = calcRESXto100(channelOutputs[channel]); - LimitData * ld = limitAddress(channel); - int usValue = PPM_CH_CENTER(channel) + channelOutputs[channel] / 2; - const uint16_t limPos = ld ? posOnBar(calcRESXto100(ld->offset)) : 0; - uint16_t valPos; - - strAppendSigned(&chanString[2], channel + 1, 2); - lcdDrawText(x, y, chanString, SMLSIZE | TEXT_COLOR | LEFT); - - lcdDrawSizedText(x + 45, y, g_model.limitData[channel].name, sizeof(g_model.limitData[channel].name), SMLSIZE | TEXT_COLOR | LEFT | ZCHAR); - lcdDrawNumber(x + w, y, usValue, SMLSIZE | TEXT_COLOR | RIGHT, 0, NULL, STR_US); - - lcdDrawSolidFilledRect(x, y + Y_OUTBAR, w, h, BARGRAPH_BGCOLOR); - lcd->drawSolidVerticalLine(x + limPos, y + Y_OUTBAR, h, MAINVIEW_GRAPHICS_COLOR); - - if (chanVal > 0) - lcdDrawNumber(x - 10 + w / 2, y + h, chanVal, SMLSIZE | TEXT_COLOR | RIGHT, 0, NULL, "%"); - else - lcdDrawNumber(x + 10 + w / 2, y + h, chanVal, SMLSIZE | TEXT_COLOR, 0, NULL, "%"); - - chanVal = limit(-VIEW_CHANNELS_LIMIT_PCT, chanVal, VIEW_CHANNELS_LIMIT_PCT); - valPos = posOnBar(chanVal); - - if (valPos > limPos) { - lcdDrawSolidFilledRect(x + limPos, y + Y_OUTBAR, valPos - limPos, h, BARGRAPH1_COLOR); - } - else if (valPos < limPos) { - uint16_t endpoint = x + limPos; - uint16_t size = limPos - valPos; - lcdDrawSolidFilledRect(endpoint - size, y + Y_OUTBAR, size, h, BARGRAPH1_COLOR); - } - - if (ld && ld->revert) { - drawOutputBarLimits(x + posOnBar(-100 - ld->max / 10), x + posOnBar(100 - ld->min / 10), y + Y_OUTBAR); - lcd->drawBitmap(x - X_OFFSET + 7, y + 25, chanMonInvertedBitmap); - } - else if (ld) { - drawOutputBarLimits(x + posOnBar(-100 + ld->min / 10), x + posOnBar(100 + ld->max / 10), y + Y_OUTBAR); - } -#if defined(OVERRIDE_CHANNEL_FUNCTION) - if (safetyCh[channel] != OVERRIDE_CHANNEL_UNDEFINED) - lcd->drawBitmap(x - X_OFFSET + 7, y + 7, chanMonLockedBitmap); -#endif - lcd->drawSolidVerticalLine(x + w / 2, y + Y_OUTBAR, h, TEXT_COLOR); -} - -coord_t drawChannelsMonitorLegend(coord_t x, const pm_char * s, int color) -{ - lcdDrawSolidFilledRect(x, MENU_FOOTER_TOP + 2, LEG_COLORBOX + 2, LEG_COLORBOX + 2, BARGRAPH_BGCOLOR); - lcdDrawSolidFilledRect(x + 1, MENU_FOOTER_TOP + 3, LEG_COLORBOX, LEG_COLORBOX, color); - lcdDrawText(x + 20, MENU_FOOTER_TOP, s, TEXT_STATUSBAR_COLOR); - return x + 25 + getTextWidth(s); -} - -bool menuChannelsMonitor(event_t event, uint8_t page) -{ - uint8_t channel = 8 * page; - coord_t x, y = Y_OFFSET; - - x = drawChannelsMonitorLegend(MENUS_MARGIN_LEFT, STR_MONITOR_OUTPUT_DESC, BARGRAPH1_COLOR); - drawChannelsMonitorLegend(x, STR_MONITOR_MIXER_DESC, BARGRAPH2_COLOR); - - x = X_OFFSET; - for (uint8_t i = 0; i < 8; i++, channel++, y += ROW_HEIGHT) { - if (i == 4) { - x = 1 + LCD_W / 2 + X_OFFSET; - y = Y_OFFSET; - } - drawComboOutputBar(x, y, COLUMN_SIZE, BAR_HEIGHT, channel); - drawSingleMixerBar(x, y + Y_MIXBAR + 1, COLUMN_SIZE, BAR_HEIGHT, channel); - } - return true; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#define RECT_OFFSET 80 +#define ROW_HEIGHT 42 +#define BAR_HEIGHT 13 +#define COLUMN_SIZE 200 +#define X_OFFSET 25 +#define Y_OFFSET 75 +#define Y_OUTBAR 15 +#define Y_MIXBAR 28 +#define LEG_COLORBOX 15 + +#define VIEW_CHANNELS_LIMIT_PCT (g_model.extendedLimits ? LIMIT_EXT_PERCENT : 100) + +bool menuChannelsMonitor(event_t event, uint8_t page); +bool menuLogicalSwitches(event_t); + +template +bool menuChannelsMonitor(event_t event) +{ + lastMonitorPage = e_MonChannelsFirst + index; + MENU(STR_MONITOR_CHANNELS[index], MONITOR_ICONS, menuTabMonitors, lastMonitorPage, 0, { 0 }); + return menuChannelsMonitor(event, index); +} + +const MenuHandlerFunc menuTabMonitors[] PROGMEM = { + menuChannelsMonitor<0>, + menuChannelsMonitor<1>, + menuChannelsMonitor<2>, + menuChannelsMonitor<3>, + menuLogicalSwitches +}; + +uint8_t lastMonitorPage = 0; + +uint16_t posOnBar(int16_t value_to100) +{ + return divRoundClosest((value_to100 + VIEW_CHANNELS_LIMIT_PCT) * COLUMN_SIZE, VIEW_CHANNELS_LIMIT_PCT * 2); +} + +void drawOutputBarLimits(coord_t left, coord_t right, coord_t y) +{ + lcd->drawSolidVerticalLine(left, y, BAR_HEIGHT, TEXT_COLOR); + lcd->drawSolidHorizontalLine(left, y, 3, TEXT_COLOR); + lcd->drawSolidHorizontalLine(left, y + BAR_HEIGHT - 1, 3, TEXT_COLOR); + + lcd->drawSolidVerticalLine(--right, y, BAR_HEIGHT, TEXT_COLOR); + lcd->drawSolidHorizontalLine(right - 3, y, 3, TEXT_COLOR); + lcd->drawSolidHorizontalLine(right - 3, y + BAR_HEIGHT - 1, 3, TEXT_COLOR); +} + +void drawSingleMixerBar(coord_t x, coord_t y, coord_t w, coord_t h, uint8_t channel) +{ + int16_t chanVal = calcRESXto100(ex_chans[channel]); + const int16_t displayVal = chanVal; + + // this could be handled nicer, but slower, by checking actual range for this mixer + chanVal = limit(-VIEW_CHANNELS_LIMIT_PCT, chanVal, VIEW_CHANNELS_LIMIT_PCT); + + lcdDrawSolidFilledRect(x, y, w, h, BARGRAPH_BGCOLOR); + if (chanVal > 0) { + lcdDrawSolidFilledRect(x + w / 2, y, divRoundClosest(chanVal * w, VIEW_CHANNELS_LIMIT_PCT * 2), h, BARGRAPH2_COLOR); + lcdDrawNumber(x - 10 + w / 2, y - 2, displayVal, SMLSIZE | TEXT_COLOR | RIGHT, 0, NULL, "%"); + } + else if (chanVal < 0) { + const uint16_t endpoint = x + w / 2; + const uint16_t size = divRoundClosest(-chanVal * w, VIEW_CHANNELS_LIMIT_PCT * 2); + lcdDrawSolidFilledRect(endpoint - size, y, size, h, BARGRAPH2_COLOR); + lcdDrawNumber(x + 10 + w / 2, y - 2, displayVal, SMLSIZE | TEXT_COLOR, 0, NULL, "%"); + } + + lcd->drawSolidVerticalLine(x + w / 2, y, h, TEXT_COLOR); +} + +void drawSingleOutputBar(coord_t x, coord_t y, coord_t w, coord_t h, uint8_t channel) +{ + int16_t chanVal = calcRESXto100(channelOutputs[channel]); + int16_t displayVal = chanVal; + + chanVal = limit(-VIEW_CHANNELS_LIMIT_PCT, chanVal, VIEW_CHANNELS_LIMIT_PCT); + + lcdDrawSolidFilledRect(x, y, w, h, BARGRAPH_BGCOLOR); + if (chanVal > 0) { + lcdDrawSolidFilledRect(x + w / 2, y, divRoundClosest(chanVal * w, VIEW_CHANNELS_LIMIT_PCT * 2), h, BARGRAPH1_COLOR); + lcdDrawNumber(x - 10 + w / 2, y - 2, displayVal, SMLSIZE | TEXT_COLOR | RIGHT, 0, NULL, "%"); + } + else if (chanVal < 0) { + uint16_t endpoint = x + w / 2; + uint16_t size = divRoundClosest(-chanVal * w, VIEW_CHANNELS_LIMIT_PCT * 2); + lcdDrawSolidFilledRect(endpoint - size, y, size, h, BARGRAPH1_COLOR); + lcdDrawNumber(x + 10 + w / 2, y - 2, displayVal, SMLSIZE | TEXT_COLOR, 0, NULL, "%"); + } + + lcd->drawSolidVerticalLine(x + w / 2, y, h, TEXT_COLOR); +} + +void drawComboOutputBar(coord_t x, coord_t y, coord_t w, coord_t h, uint8_t channel) +{ + char chanString[] = "Ch32 "; + int16_t chanVal = calcRESXto100(channelOutputs[channel]); + LimitData * ld = limitAddress(channel); + int usValue = PPM_CH_CENTER(channel) + channelOutputs[channel] / 2; + const uint16_t limPos = ld ? posOnBar(calcRESXto100(ld->offset)) : 0; + uint16_t valPos; + + strAppendSigned(&chanString[2], channel + 1, 2); + lcdDrawText(x, y, chanString, SMLSIZE | TEXT_COLOR | LEFT); + + lcdDrawSizedText(x + 45, y, g_model.limitData[channel].name, sizeof(g_model.limitData[channel].name), SMLSIZE | TEXT_COLOR | LEFT | ZCHAR); + lcdDrawNumber(x + w, y, usValue, SMLSIZE | TEXT_COLOR | RIGHT, 0, NULL, STR_US); + + lcdDrawSolidFilledRect(x, y + Y_OUTBAR, w, h, BARGRAPH_BGCOLOR); + lcd->drawSolidVerticalLine(x + limPos, y + Y_OUTBAR, h, MAINVIEW_GRAPHICS_COLOR); + + if (chanVal > 0) + lcdDrawNumber(x - 10 + w / 2, y + h, chanVal, SMLSIZE | TEXT_COLOR | RIGHT, 0, NULL, "%"); + else + lcdDrawNumber(x + 10 + w / 2, y + h, chanVal, SMLSIZE | TEXT_COLOR, 0, NULL, "%"); + + chanVal = limit(-VIEW_CHANNELS_LIMIT_PCT, chanVal, VIEW_CHANNELS_LIMIT_PCT); + valPos = posOnBar(chanVal); + + if (valPos > limPos) { + lcdDrawSolidFilledRect(x + limPos, y + Y_OUTBAR, valPos - limPos, h, BARGRAPH1_COLOR); + } + else if (valPos < limPos) { + uint16_t endpoint = x + limPos; + uint16_t size = limPos - valPos; + lcdDrawSolidFilledRect(endpoint - size, y + Y_OUTBAR, size, h, BARGRAPH1_COLOR); + } + + if (ld && ld->revert) { + drawOutputBarLimits(x + posOnBar(-100 - ld->max / 10), x + posOnBar(100 - ld->min / 10), y + Y_OUTBAR); + lcd->drawBitmap(x - X_OFFSET + 7, y + 25, chanMonInvertedBitmap); + } + else if (ld) { + drawOutputBarLimits(x + posOnBar(-100 + ld->min / 10), x + posOnBar(100 + ld->max / 10), y + Y_OUTBAR); + } +#if defined(OVERRIDE_CHANNEL_FUNCTION) + if (safetyCh[channel] != OVERRIDE_CHANNEL_UNDEFINED) + lcd->drawBitmap(x - X_OFFSET + 7, y + 7, chanMonLockedBitmap); +#endif + lcd->drawSolidVerticalLine(x + w / 2, y + Y_OUTBAR, h, TEXT_COLOR); +} + +coord_t drawChannelsMonitorLegend(coord_t x, const pm_char * s, int color) +{ + lcdDrawSolidFilledRect(x, MENU_FOOTER_TOP + 2, LEG_COLORBOX + 2, LEG_COLORBOX + 2, BARGRAPH_BGCOLOR); + lcdDrawSolidFilledRect(x + 1, MENU_FOOTER_TOP + 3, LEG_COLORBOX, LEG_COLORBOX, color); + lcdDrawText(x + 20, MENU_FOOTER_TOP, s, TEXT_STATUSBAR_COLOR); + return x + 25 + getTextWidth(s); +} + +bool menuChannelsMonitor(event_t event, uint8_t page) +{ + uint8_t channel = 8 * page; + coord_t x, y = Y_OFFSET; + + x = drawChannelsMonitorLegend(MENUS_MARGIN_LEFT, STR_MONITOR_OUTPUT_DESC, BARGRAPH1_COLOR); + drawChannelsMonitorLegend(x, STR_MONITOR_MIXER_DESC, BARGRAPH2_COLOR); + + x = X_OFFSET; + for (uint8_t i = 0; i < 8; i++, channel++, y += ROW_HEIGHT) { + if (i == 4) { + x = 1 + LCD_W / 2 + X_OFFSET; + y = Y_OFFSET; + } + drawComboOutputBar(x, y, COLUMN_SIZE, BAR_HEIGHT, channel); + drawSingleMixerBar(x, y + Y_MIXBAR + 1, COLUMN_SIZE, BAR_HEIGHT, channel); + } + return true; +} diff --git a/radio/src/gui/480x272/view_statistics.cpp b/radio/src/gui/480x272/view_statistics.cpp index 407c32179..a63e5eaf1 100644 --- a/radio/src/gui/480x272/view_statistics.cpp +++ b/radio/src/gui/480x272/view_statistics.cpp @@ -1,238 +1,238 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" -#include "stamp.h" - -#define MENU_STATS_COLUMN1 (MENUS_MARGIN_LEFT + 120) -#define MENU_STATS_COLUMN2 (LCD_W/2) -#define MENU_STATS_COLUMN3 (LCD_W/2 + 120) - -bool menuStatsGraph(event_t event) -{ - switch(event) { - case EVT_KEY_LONG(KEY_ENTER): - g_eeGeneral.globalTimer = 0; - storageDirty(EE_GENERAL); - sessionTimer = 0; - killEvents(event); - break; - } - - MENU(STR_STATISTICS, STATS_ICONS, menuTabStats, e_StatsGraph, 0, { 0 }); - - lcdDrawText(MENUS_MARGIN_LEFT, MENU_CONTENT_TOP, "Session"); - drawTimer(MENU_STATS_COLUMN1, MENU_CONTENT_TOP, sessionTimer, TIMEHOUR); - lcdDrawText(MENU_STATS_COLUMN2, MENU_CONTENT_TOP, "Battery"); - drawTimer(MENU_STATS_COLUMN3, MENU_CONTENT_TOP, g_eeGeneral.globalTimer+sessionTimer, TIMEHOUR); - - lcdDrawText(MENUS_MARGIN_LEFT, MENU_CONTENT_TOP+FH, "Throttle"); - drawTimer(MENU_STATS_COLUMN1, MENU_CONTENT_TOP+FH, s_timeCumThr, TIMEHOUR); - lcdDrawText(MENU_STATS_COLUMN2, MENU_CONTENT_TOP+FH, "Throttle %", TIMEHOUR); - drawTimer(MENU_STATS_COLUMN3, MENU_CONTENT_TOP+FH, s_timeCum16ThrP/16, TIMEHOUR); - - lcdDrawText(MENUS_MARGIN_LEFT, MENU_CONTENT_TOP+2*FH, "Timers"); - lcdDrawText(MENU_STATS_COLUMN1, MENU_CONTENT_TOP+2*FH, "[1]", HEADER_COLOR); - drawTimer(lcdNextPos+5, MENU_CONTENT_TOP+2*FH, timersStates[0].val, TIMEHOUR); - lcdDrawText(MENU_STATS_COLUMN2, MENU_CONTENT_TOP+2*FH, "[2]", HEADER_COLOR); - drawTimer(lcdNextPos+5, MENU_CONTENT_TOP+2*FH, timersStates[1].val, TIMEHOUR); -#if TIMERS > 2 - lcdDrawText(MENU_STATS_COLUMN3, MENU_CONTENT_TOP+2*FH, "[3]", HEADER_COLOR); - drawTimer(lcdNextPos+5, MENU_CONTENT_TOP+2*FH, timersStates[2].val, TIMEHOUR); -#endif - - const coord_t x = 10; - const coord_t y = 240; - lcdDrawHorizontalLine(x-3, y, MAXTRACE+3+3, SOLID, TEXT_COLOR); - lcdDrawVerticalLine(x, y-96, 96+3, SOLID, TEXT_COLOR); - for (coord_t i=0; i MAXTRACE ? s_traceWr - MAXTRACE : 0; - coord_t prev_yv = (coord_t)-1; - for (coord_t i=1; i<=MAXTRACE && traceRd= MOUSE1) - lcdDrawNumber(x+100, y, (int16_t)calibratedAnalogs[CALIBRATED_MOUSE1+i-MOUSE1]*25/256); -#endif - } - - // SWR - lcdDrawText(MENUS_MARGIN_LEFT, MENU_CONTENT_TOP+7*FH, "RAS"); - lcdDrawNumber(MENUS_MARGIN_LEFT+100, MENU_CONTENT_TOP+7*FH, telemetryData.swr.value); - - return true; -} - - -#if defined(DEBUG_TRACE_BUFFER) -#define STATS_TRACES_INDEX_POS MENUS_MARGIN_LEFT -#define STATS_TRACES_TIME_POS MENUS_MARGIN_LEFT + 4*10 -#define STATS_TRACES_EVENT_POS MENUS_MARGIN_LEFT + 14*10 -#define STATS_TRACES_DATA_POS MENUS_MARGIN_LEFT + 20*10 - -bool menuStatsTraces(event_t event) -{ - switch(event) - { - case EVT_KEY_LONG(KEY_ENTER): - dumpTraceBuffer(); - killEvents(event); - break; - } - - SIMPLE_MENU("", STATS_ICONS, menuTabStats, e_StatsTraces, TRACE_BUFFER_LEN); - - uint8_t k = 0; - int8_t sub = menuVerticalPosition; - - lcdDrawChar(STATS_TRACES_INDEX_POS, MENU_TITLE_TOP+2, '#', MENU_TITLE_COLOR); - lcdDrawText(STATS_TRACES_TIME_POS, MENU_TITLE_TOP+2, "Time", MENU_TITLE_COLOR); - lcdDrawText(STATS_TRACES_EVENT_POS, MENU_TITLE_TOP+2, "Event", MENU_TITLE_COLOR); - lcdDrawText(STATS_TRACES_DATA_POS, MENU_TITLE_TOP+2, "Data", MENU_TITLE_COLOR); - - for (uint8_t i=0; itime % SECS_PER_DAY; - drawTimer(STATS_TRACES_TIME_POS, y, tme, TIMEHOUR|LEFT); - // event - lcdDrawNumber(STATS_TRACES_EVENT_POS, y, te->event, LEADING0|LEFT, 3); - // data - lcdDrawSizedText(STATS_TRACES_DATA_POS, y, "0x", 2); - lcdDrawHexNumber(lcdNextPos, y, (uint16_t)(te->data >> 16)); - lcdDrawHexNumber(lcdNextPos, y, (uint16_t)(te->data & 0xFFFF)); - } - - } - - return true; -} -#endif // defined(DEBUG_TRACE_BUFFER) +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" +#include "stamp.h" + +#define MENU_STATS_COLUMN1 (MENUS_MARGIN_LEFT + 120) +#define MENU_STATS_COLUMN2 (LCD_W/2) +#define MENU_STATS_COLUMN3 (LCD_W/2 + 120) + +bool menuStatsGraph(event_t event) +{ + switch(event) { + case EVT_KEY_LONG(KEY_ENTER): + g_eeGeneral.globalTimer = 0; + storageDirty(EE_GENERAL); + sessionTimer = 0; + killEvents(event); + break; + } + + MENU(STR_STATISTICS, STATS_ICONS, menuTabStats, e_StatsGraph, 0, { 0 }); + + lcdDrawText(MENUS_MARGIN_LEFT, MENU_CONTENT_TOP, "Session"); + drawTimer(MENU_STATS_COLUMN1, MENU_CONTENT_TOP, sessionTimer, TIMEHOUR); + lcdDrawText(MENU_STATS_COLUMN2, MENU_CONTENT_TOP, "Battery"); + drawTimer(MENU_STATS_COLUMN3, MENU_CONTENT_TOP, g_eeGeneral.globalTimer+sessionTimer, TIMEHOUR); + + lcdDrawText(MENUS_MARGIN_LEFT, MENU_CONTENT_TOP+FH, "Throttle"); + drawTimer(MENU_STATS_COLUMN1, MENU_CONTENT_TOP+FH, s_timeCumThr, TIMEHOUR); + lcdDrawText(MENU_STATS_COLUMN2, MENU_CONTENT_TOP+FH, "Throttle %", TIMEHOUR); + drawTimer(MENU_STATS_COLUMN3, MENU_CONTENT_TOP+FH, s_timeCum16ThrP/16, TIMEHOUR); + + lcdDrawText(MENUS_MARGIN_LEFT, MENU_CONTENT_TOP+2*FH, "Timers"); + lcdDrawText(MENU_STATS_COLUMN1, MENU_CONTENT_TOP+2*FH, "[1]", HEADER_COLOR); + drawTimer(lcdNextPos+5, MENU_CONTENT_TOP+2*FH, timersStates[0].val, TIMEHOUR); + lcdDrawText(MENU_STATS_COLUMN2, MENU_CONTENT_TOP+2*FH, "[2]", HEADER_COLOR); + drawTimer(lcdNextPos+5, MENU_CONTENT_TOP+2*FH, timersStates[1].val, TIMEHOUR); +#if TIMERS > 2 + lcdDrawText(MENU_STATS_COLUMN3, MENU_CONTENT_TOP+2*FH, "[3]", HEADER_COLOR); + drawTimer(lcdNextPos+5, MENU_CONTENT_TOP+2*FH, timersStates[2].val, TIMEHOUR); +#endif + + const coord_t x = 10; + const coord_t y = 240; + lcdDrawHorizontalLine(x-3, y, MAXTRACE+3+3, SOLID, TEXT_COLOR); + lcdDrawVerticalLine(x, y-96, 96+3, SOLID, TEXT_COLOR); + for (coord_t i=0; i MAXTRACE ? s_traceWr - MAXTRACE : 0; + coord_t prev_yv = (coord_t)-1; + for (coord_t i=1; i<=MAXTRACE && traceRd= MOUSE1) + lcdDrawNumber(x+100, y, (int16_t)calibratedAnalogs[CALIBRATED_MOUSE1+i-MOUSE1]*25/256); +#endif + } + + // SWR + lcdDrawText(MENUS_MARGIN_LEFT, MENU_CONTENT_TOP+7*FH, "RAS"); + lcdDrawNumber(MENUS_MARGIN_LEFT+100, MENU_CONTENT_TOP+7*FH, telemetryData.swr.value); + + return true; +} + + +#if defined(DEBUG_TRACE_BUFFER) +#define STATS_TRACES_INDEX_POS MENUS_MARGIN_LEFT +#define STATS_TRACES_TIME_POS MENUS_MARGIN_LEFT + 4*10 +#define STATS_TRACES_EVENT_POS MENUS_MARGIN_LEFT + 14*10 +#define STATS_TRACES_DATA_POS MENUS_MARGIN_LEFT + 20*10 + +bool menuStatsTraces(event_t event) +{ + switch(event) + { + case EVT_KEY_LONG(KEY_ENTER): + dumpTraceBuffer(); + killEvents(event); + break; + } + + SIMPLE_MENU("", STATS_ICONS, menuTabStats, e_StatsTraces, TRACE_BUFFER_LEN); + + uint8_t k = 0; + int8_t sub = menuVerticalPosition; + + lcdDrawChar(STATS_TRACES_INDEX_POS, MENU_TITLE_TOP+2, '#', MENU_TITLE_COLOR); + lcdDrawText(STATS_TRACES_TIME_POS, MENU_TITLE_TOP+2, "Time", MENU_TITLE_COLOR); + lcdDrawText(STATS_TRACES_EVENT_POS, MENU_TITLE_TOP+2, "Event", MENU_TITLE_COLOR); + lcdDrawText(STATS_TRACES_DATA_POS, MENU_TITLE_TOP+2, "Data", MENU_TITLE_COLOR); + + for (uint8_t i=0; itime % SECS_PER_DAY; + drawTimer(STATS_TRACES_TIME_POS, y, tme, TIMEHOUR|LEFT); + // event + lcdDrawNumber(STATS_TRACES_EVENT_POS, y, te->event, LEADING0|LEFT, 3); + // data + lcdDrawSizedText(STATS_TRACES_DATA_POS, y, "0x", 2); + lcdDrawHexNumber(lcdNextPos, y, (uint16_t)(te->data >> 16)); + lcdDrawHexNumber(lcdNextPos, y, (uint16_t)(te->data & 0xFFFF)); + } + + } + + return true; +} +#endif // defined(DEBUG_TRACE_BUFFER) diff --git a/radio/src/haptic.h b/radio/src/haptic.h index cb2a7ee52..498a9f541 100644 --- a/radio/src/haptic.h +++ b/radio/src/haptic.h @@ -1,76 +1,76 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _HAPTIC_H_ -#define _HAPTIC_H_ - -#define HAPTIC_QUEUE_LENGTH 4 - -class hapticQueue -{ - public: - - hapticQueue(); - - // only difference between these two functions is that one does the - // interupt queue (Now) and the other queues for playing ASAP. - void play(uint8_t tLen, uint8_t tPause, uint8_t tRepeat=0); - - inline bool busy() { return (buzzTimeLeft > 0); } - - void event(uint8_t e); - - // heartbeat is responsibile for issueing the haptic buzzs and general square waves - // it is essentially the life of the class. - void heartbeat(); - - // bool freeslots(uint8_t slots); - - inline bool empty() { - return (t_queueRidx == t_queueWidx); - } - - protected: - inline uint8_t getHapticLength(uint8_t tLen) { - return ((g_eeGeneral.hapticLength * 2) + tLen) * 2; - } - - private: - uint8_t t_queueRidx; - uint8_t t_queueWidx; - - uint8_t buzzTimeLeft; - uint8_t buzzPause; - - uint8_t hapticTick; - - // queue arrays - uint8_t queueHapticLength[HAPTIC_QUEUE_LENGTH]; - uint8_t queueHapticPause[HAPTIC_QUEUE_LENGTH]; - uint8_t queueHapticRepeat[HAPTIC_QUEUE_LENGTH]; -}; - -extern hapticQueue haptic; - -#define IS_HAPTIC_BUSY() haptic.busy() -#define HAPTIC_HEARTBEAT() haptic.heartbeat() - - -#endif // _HAPTIC_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _HAPTIC_H_ +#define _HAPTIC_H_ + +#define HAPTIC_QUEUE_LENGTH 4 + +class hapticQueue +{ + public: + + hapticQueue(); + + // only difference between these two functions is that one does the + // interupt queue (Now) and the other queues for playing ASAP. + void play(uint8_t tLen, uint8_t tPause, uint8_t tRepeat=0); + + inline bool busy() { return (buzzTimeLeft > 0); } + + void event(uint8_t e); + + // heartbeat is responsibile for issueing the haptic buzzs and general square waves + // it is essentially the life of the class. + void heartbeat(); + + // bool freeslots(uint8_t slots); + + inline bool empty() { + return (t_queueRidx == t_queueWidx); + } + + protected: + inline uint8_t getHapticLength(uint8_t tLen) { + return ((g_eeGeneral.hapticLength * 2) + tLen) * 2; + } + + private: + uint8_t t_queueRidx; + uint8_t t_queueWidx; + + uint8_t buzzTimeLeft; + uint8_t buzzPause; + + uint8_t hapticTick; + + // queue arrays + uint8_t queueHapticLength[HAPTIC_QUEUE_LENGTH]; + uint8_t queueHapticPause[HAPTIC_QUEUE_LENGTH]; + uint8_t queueHapticRepeat[HAPTIC_QUEUE_LENGTH]; +}; + +extern hapticQueue haptic; + +#define IS_HAPTIC_BUSY() haptic.busy() +#define HAPTIC_HEARTBEAT() haptic.heartbeat() + + +#endif // _HAPTIC_H_ diff --git a/radio/src/keys.h b/radio/src/keys.h index 5475a7aed..c50c52857 100644 --- a/radio/src/keys.h +++ b/radio/src/keys.h @@ -1,113 +1,113 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _KEYS_H_ -#define _KEYS_H_ - -#define EVT_KEY_MASK(e) ((e) & 0x1f) - -#if defined(PCBHORUS) -#define _MSK_KEY_BREAK 0x0200 -#define _MSK_KEY_REPT 0x0400 -#define _MSK_KEY_FIRST 0x0600 -#define _MSK_KEY_LONG 0x0800 -#define _MSK_KEY_FLAGS 0x0e00 -#define EVT_ENTRY 0x1000 -#define EVT_ENTRY_UP 0x2000 -#else -#define _MSK_KEY_BREAK 0x20 -#define _MSK_KEY_REPT 0x40 -#define _MSK_KEY_FIRST 0x60 -#define _MSK_KEY_LONG 0x80 -#define _MSK_KEY_FLAGS 0xe0 -#define EVT_ENTRY 0xbf -#define EVT_ENTRY_UP 0xbe -#endif - -// normal order of events is: FIRST, LONG, REPEAT, REPEAT, ..., BREAK -#define EVT_KEY_FIRST(key) ((key)|_MSK_KEY_FIRST) // fired when key is pressed -#define EVT_KEY_LONG(key) ((key)|_MSK_KEY_LONG) // fired when key is held pressed for a while -#define EVT_KEY_REPT(key) ((key)|_MSK_KEY_REPT) // fired when key is held pressed long enough, fires multiple times with increasing speed -#define EVT_KEY_BREAK(key) ((key)|_MSK_KEY_BREAK) // fired when key is released (short or long), but only if the event was not killed - -#define IS_KEY_FIRST(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_FIRST) -#define IS_KEY_LONG(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_LONG) -#define IS_KEY_REPT(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_REPT) -#define IS_KEY_BREAK(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_BREAK) - -#if (defined(PCBHORUS) || defined(PCBFLAMENCO) || defined(PCBTARANIS)) && defined(ROTARY_ENCODER_NAVIGATION) - typedef uint16_t event_t; - #define EVT_ROTARY_BREAK EVT_KEY_BREAK(KEY_ENTER) - #define EVT_ROTARY_LONG EVT_KEY_LONG(KEY_ENTER) - #define EVT_ROTARY_LEFT 0xDF00 - #define EVT_ROTARY_RIGHT 0xDE00 - #define IS_NEXT_EVENT(event) (event==EVT_ROTARY_RIGHT) - #define IS_PREVIOUS_EVENT(event) (event==EVT_ROTARY_LEFT) -#elif defined(ROTARY_ENCODER_NAVIGATION) - typedef uint8_t event_t; - #define EVT_ROTARY_BREAK 0xcf - #define EVT_ROTARY_LONG 0xce - #define EVT_ROTARY_LEFT 0xdf - #define EVT_ROTARY_RIGHT 0xde - #define IS_NEXT_EVENT(event) (event==EVT_ROTARY_RIGHT || event==EVT_KEY_FIRST(KEY_DOWN) || event==EVT_KEY_REPT(KEY_DOWN)) - #define IS_PREVIOUS_EVENT(event) (event==EVT_ROTARY_LEFT || event==EVT_KEY_FIRST(KEY_UP) || event==EVT_KEY_REPT(KEY_UP)) -#else - typedef uint8_t event_t; - #define IS_NEXT_EVENT(event) (event==EVT_KEY_FIRST(KEY_DOWN) || event==EVT_KEY_REPT(KEY_DOWN)) - #define IS_PREVIOUS_EVENT(event) (event==EVT_KEY_FIRST(KEY_UP) || event==EVT_KEY_REPT(KEY_UP)) -#endif - -#if defined(COLORLCD) - #define EVT_REFRESH 0xDD00 -#endif - -class Key -{ - private: - uint8_t m_vals; - uint8_t m_cnt; - uint8_t m_state; - public: - void input(bool val); - bool state() const { return m_vals > 0; } - void pauseEvents(); - void killEvents(); - uint8_t key() const; -}; - -extern Key keys[NUM_KEYS]; -extern event_t s_evt; - -#define putEvent(evt) s_evt = evt - -void pauseEvents(event_t event); -void killEvents(event_t event); - -#if defined(CPUARM) - bool clearKeyEvents(); - event_t getEvent(bool trim=false); -#else - void clearKeyEvents(); - event_t getEvent(); -#endif - -uint8_t keyDown(); - -#endif // _KEYS_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _KEYS_H_ +#define _KEYS_H_ + +#define EVT_KEY_MASK(e) ((e) & 0x1f) + +#if defined(PCBHORUS) +#define _MSK_KEY_BREAK 0x0200 +#define _MSK_KEY_REPT 0x0400 +#define _MSK_KEY_FIRST 0x0600 +#define _MSK_KEY_LONG 0x0800 +#define _MSK_KEY_FLAGS 0x0e00 +#define EVT_ENTRY 0x1000 +#define EVT_ENTRY_UP 0x2000 +#else +#define _MSK_KEY_BREAK 0x20 +#define _MSK_KEY_REPT 0x40 +#define _MSK_KEY_FIRST 0x60 +#define _MSK_KEY_LONG 0x80 +#define _MSK_KEY_FLAGS 0xe0 +#define EVT_ENTRY 0xbf +#define EVT_ENTRY_UP 0xbe +#endif + +// normal order of events is: FIRST, LONG, REPEAT, REPEAT, ..., BREAK +#define EVT_KEY_FIRST(key) ((key)|_MSK_KEY_FIRST) // fired when key is pressed +#define EVT_KEY_LONG(key) ((key)|_MSK_KEY_LONG) // fired when key is held pressed for a while +#define EVT_KEY_REPT(key) ((key)|_MSK_KEY_REPT) // fired when key is held pressed long enough, fires multiple times with increasing speed +#define EVT_KEY_BREAK(key) ((key)|_MSK_KEY_BREAK) // fired when key is released (short or long), but only if the event was not killed + +#define IS_KEY_FIRST(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_FIRST) +#define IS_KEY_LONG(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_LONG) +#define IS_KEY_REPT(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_REPT) +#define IS_KEY_BREAK(evt) (((evt) & _MSK_KEY_FLAGS) == _MSK_KEY_BREAK) + +#if (defined(PCBHORUS) || defined(PCBFLAMENCO) || defined(PCBTARANIS)) && defined(ROTARY_ENCODER_NAVIGATION) + typedef uint16_t event_t; + #define EVT_ROTARY_BREAK EVT_KEY_BREAK(KEY_ENTER) + #define EVT_ROTARY_LONG EVT_KEY_LONG(KEY_ENTER) + #define EVT_ROTARY_LEFT 0xDF00 + #define EVT_ROTARY_RIGHT 0xDE00 + #define IS_NEXT_EVENT(event) (event==EVT_ROTARY_RIGHT) + #define IS_PREVIOUS_EVENT(event) (event==EVT_ROTARY_LEFT) +#elif defined(ROTARY_ENCODER_NAVIGATION) + typedef uint8_t event_t; + #define EVT_ROTARY_BREAK 0xcf + #define EVT_ROTARY_LONG 0xce + #define EVT_ROTARY_LEFT 0xdf + #define EVT_ROTARY_RIGHT 0xde + #define IS_NEXT_EVENT(event) (event==EVT_ROTARY_RIGHT || event==EVT_KEY_FIRST(KEY_DOWN) || event==EVT_KEY_REPT(KEY_DOWN)) + #define IS_PREVIOUS_EVENT(event) (event==EVT_ROTARY_LEFT || event==EVT_KEY_FIRST(KEY_UP) || event==EVT_KEY_REPT(KEY_UP)) +#else + typedef uint8_t event_t; + #define IS_NEXT_EVENT(event) (event==EVT_KEY_FIRST(KEY_DOWN) || event==EVT_KEY_REPT(KEY_DOWN)) + #define IS_PREVIOUS_EVENT(event) (event==EVT_KEY_FIRST(KEY_UP) || event==EVT_KEY_REPT(KEY_UP)) +#endif + +#if defined(COLORLCD) + #define EVT_REFRESH 0xDD00 +#endif + +class Key +{ + private: + uint8_t m_vals; + uint8_t m_cnt; + uint8_t m_state; + public: + void input(bool val); + bool state() const { return m_vals > 0; } + void pauseEvents(); + void killEvents(); + uint8_t key() const; +}; + +extern Key keys[NUM_KEYS]; +extern event_t s_evt; + +#define putEvent(evt) s_evt = evt + +void pauseEvents(event_t event); +void killEvents(event_t event); + +#if defined(CPUARM) + bool clearKeyEvents(); + event_t getEvent(bool trim=false); +#else + void clearKeyEvents(); + event_t getEvent(); +#endif + +uint8_t keyDown(); + +#endif // _KEYS_H_ diff --git a/radio/src/pwr.h b/radio/src/pwr.h index 4efcfbd94..eac37acca 100644 --- a/radio/src/pwr.h +++ b/radio/src/pwr.h @@ -20,13 +20,13 @@ #ifndef _PWR_H_ #define _PWR_H_ - -enum PowerState { - e_power_on, - e_power_trainer, - e_power_usb, - e_power_off, - e_power_press, -}; - + +enum PowerState { + e_power_on, + e_power_trainer, + e_power_usb, + e_power_off, + e_power_press, +}; + #endif // _PWR_H_ diff --git a/radio/src/rtc.h b/radio/src/rtc.h index db421a4ea..c65131b98 100644 --- a/radio/src/rtc.h +++ b/radio/src/rtc.h @@ -1,63 +1,63 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _RTC_H_ -#define _RTC_H_ - -#include - -#define SECS_PER_HOUR 3600ul -#define SECS_PER_DAY 86400ul -#define TM_YEAR_BASE 1900 - -#define TIME_T_MIN (-LONG_MAX) -#define TIME_T_MAX (LONG_MAX) - -typedef long int gtime_t; - -struct gtm -{ - int8_t tm_sec; /* Seconds. [0-60] (1 leap second) */ - int8_t tm_min; /* Minutes. [0-59] */ - int8_t tm_hour; /* Hours. [0-23] */ - int8_t tm_mday; /* Day. [1-31] */ - int8_t tm_mon; /* Month. [0-11] */ - uint8_t tm_year; /* Year - 1900. Limited to the year 2155. */ - int8_t tm_wday; /* Day of week. [0-6] */ - int16_t tm_yday; /* Day of year. [0-365] Needed internally for calculations */ -}; - -extern gtime_t g_rtcTime; -extern uint8_t g_ms100; // global to allow time set function to reset to zero - -void rtcInit(); -void rtcSetTime(const struct gtm * tm); -gtime_t gmktime (struct gtm *tm); -uint8_t rtcAdjust(uint16_t year, uint8_t mon, uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); - -#if defined(__cplusplus) && !defined(SIMU) -extern "C" { -#endif -void gettime(struct gtm * tm); -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif // _RTC_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _RTC_H_ +#define _RTC_H_ + +#include + +#define SECS_PER_HOUR 3600ul +#define SECS_PER_DAY 86400ul +#define TM_YEAR_BASE 1900 + +#define TIME_T_MIN (-LONG_MAX) +#define TIME_T_MAX (LONG_MAX) + +typedef long int gtime_t; + +struct gtm +{ + int8_t tm_sec; /* Seconds. [0-60] (1 leap second) */ + int8_t tm_min; /* Minutes. [0-59] */ + int8_t tm_hour; /* Hours. [0-23] */ + int8_t tm_mday; /* Day. [1-31] */ + int8_t tm_mon; /* Month. [0-11] */ + uint8_t tm_year; /* Year - 1900. Limited to the year 2155. */ + int8_t tm_wday; /* Day of week. [0-6] */ + int16_t tm_yday; /* Day of year. [0-365] Needed internally for calculations */ +}; + +extern gtime_t g_rtcTime; +extern uint8_t g_ms100; // global to allow time set function to reset to zero + +void rtcInit(); +void rtcSetTime(const struct gtm * tm); +gtime_t gmktime (struct gtm *tm); +uint8_t rtcAdjust(uint16_t year, uint8_t mon, uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); + +#if defined(__cplusplus) && !defined(SIMU) +extern "C" { +#endif +void gettime(struct gtm * tm); +#if defined(__cplusplus) && !defined(SIMU) +} +#endif + +#endif // _RTC_H_ diff --git a/radio/src/serial.h b/radio/src/serial.h index 9f0b20e57..992f83cf1 100644 --- a/radio/src/serial.h +++ b/radio/src/serial.h @@ -20,20 +20,20 @@ #ifndef _SERIAL_H_ #define _SERIAL_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -void serialPutc(char c); -void serialPrintf(const char *format, ...); -void serialCrlf(); - -#ifdef __cplusplus -} -#endif - -#define serialPrint(...) do { serialPrintf(__VA_ARGS__); serialCrlf(); } while(0) - + +#ifdef __cplusplus +extern "C" { +#endif + +void serialPutc(char c); +void serialPrintf(const char *format, ...); +void serialCrlf(); + +#ifdef __cplusplus +} +#endif + +#define serialPrint(...) do { serialPrintf(__VA_ARGS__); serialCrlf(); } while(0) + #endif // _SERIAL_H_ - + diff --git a/radio/src/storage/eeprom_common.cpp b/radio/src/storage/eeprom_common.cpp index c16eac557..9fc5e6874 100644 --- a/radio/src/storage/eeprom_common.cpp +++ b/radio/src/storage/eeprom_common.cpp @@ -1,137 +1,137 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "opentx.h" -#include "timers.h" - -void eeLoadModel(uint8_t index) -{ - if (index < MAX_MODELS) { - - preModelLoad(); - - uint16_t size = eeLoadModelData(index); - -#if defined(SIMU) && defined(EEPROM_ZONE_SIZE) - if (sizeof(uint16_t) + sizeof(g_model) > EEPROM_ZONE_SIZE) { - TRACE("Model data size can't exceed %d bytes (%d bytes)", int(EEPROM_ZONE_SIZE-sizeof(uint16_t)), (int)sizeof(g_model)); - } -#endif - -#if defined(SIMU) - if (size > 0 && size != sizeof(g_model)) { - TRACE("Model data read=%d bytes vs %d bytes\n", size, (int)sizeof(ModelData)); - } -#endif - - bool alarms = true; - if (size < EEPROM_MIN_MODEL_SIZE) { // if not loaded a fair amount - modelDefault(index) ; - storageCheck(true); - alarms = false; - } - - postModelLoad(alarms); - } -} - -uint8_t eeFindEmptyModel(uint8_t id, bool down) -{ - uint8_t i = id; - for (;;) { - i = (MAX_MODELS + (down ? i+1 : i-1)) % MAX_MODELS; - if (!eeModelExists(i)) break; - if (i == id) return 0xff; // no free space in directory left - } - return i; -} - -void selectModel(uint8_t sub) -{ -#if !defined(COLORLCD) - showMessageBox(STR_LOADINGMODEL); -#endif - storageFlushCurrentModel(); - storageCheck(true); // force writing of current model data before this is changed - g_eeGeneral.currModel = sub; - storageDirty(EE_GENERAL); - eeLoadModel(sub); -} - -#if defined(CPUARM) -ModelHeader modelHeaders[MAX_MODELS]; -void eeLoadModelHeaders() -{ - for (uint32_t i=0; iid, 2)) { - currentLanguagePackIdx = i; - currentLanguagePack = languagePacks[i]; - } - } -#endif -} - -void storageReadCurrentModel() -{ - eeLoadModel(g_eeGeneral.currModel); -} - -void storageReadAll() -{ - storageReadRadioSettings(); - storageReadCurrentModel(); -} - -void storageEraseAll(bool warn) -{ - TRACE("storageEraseAll"); - - generalDefault(); - modelDefault(0); - - if (warn) { - ALERT(STR_STORAGE_WARNING, STR_BAD_RADIO_DATA, AU_BAD_RADIODATA); - } - - RAISE_ALERT(STR_STORAGE_WARNING, STR_STORAGE_FORMAT, NULL, AU_NONE); - - storageFormat(); - storageDirty(EE_GENERAL|EE_MODEL); - storageCheck(true); -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "opentx.h" +#include "timers.h" + +void eeLoadModel(uint8_t index) +{ + if (index < MAX_MODELS) { + + preModelLoad(); + + uint16_t size = eeLoadModelData(index); + +#if defined(SIMU) && defined(EEPROM_ZONE_SIZE) + if (sizeof(uint16_t) + sizeof(g_model) > EEPROM_ZONE_SIZE) { + TRACE("Model data size can't exceed %d bytes (%d bytes)", int(EEPROM_ZONE_SIZE-sizeof(uint16_t)), (int)sizeof(g_model)); + } +#endif + +#if defined(SIMU) + if (size > 0 && size != sizeof(g_model)) { + TRACE("Model data read=%d bytes vs %d bytes\n", size, (int)sizeof(ModelData)); + } +#endif + + bool alarms = true; + if (size < EEPROM_MIN_MODEL_SIZE) { // if not loaded a fair amount + modelDefault(index) ; + storageCheck(true); + alarms = false; + } + + postModelLoad(alarms); + } +} + +uint8_t eeFindEmptyModel(uint8_t id, bool down) +{ + uint8_t i = id; + for (;;) { + i = (MAX_MODELS + (down ? i+1 : i-1)) % MAX_MODELS; + if (!eeModelExists(i)) break; + if (i == id) return 0xff; // no free space in directory left + } + return i; +} + +void selectModel(uint8_t sub) +{ +#if !defined(COLORLCD) + showMessageBox(STR_LOADINGMODEL); +#endif + storageFlushCurrentModel(); + storageCheck(true); // force writing of current model data before this is changed + g_eeGeneral.currModel = sub; + storageDirty(EE_GENERAL); + eeLoadModel(sub); +} + +#if defined(CPUARM) +ModelHeader modelHeaders[MAX_MODELS]; +void eeLoadModelHeaders() +{ + for (uint32_t i=0; iid, 2)) { + currentLanguagePackIdx = i; + currentLanguagePack = languagePacks[i]; + } + } +#endif +} + +void storageReadCurrentModel() +{ + eeLoadModel(g_eeGeneral.currModel); +} + +void storageReadAll() +{ + storageReadRadioSettings(); + storageReadCurrentModel(); +} + +void storageEraseAll(bool warn) +{ + TRACE("storageEraseAll"); + + generalDefault(); + modelDefault(0); + + if (warn) { + ALERT(STR_STORAGE_WARNING, STR_BAD_RADIO_DATA, AU_BAD_RADIODATA); + } + + RAISE_ALERT(STR_STORAGE_WARNING, STR_STORAGE_FORMAT, NULL, AU_NONE); + + storageFormat(); + storageDirty(EE_GENERAL|EE_MODEL); + storageCheck(true); +} diff --git a/radio/src/storage/eeprom_common.h b/radio/src/storage/eeprom_common.h index bd18c2279..ee510674a 100644 --- a/radio/src/storage/eeprom_common.h +++ b/radio/src/storage/eeprom_common.h @@ -18,25 +18,25 @@ * GNU General Public License for more details. */ -#define EEPROM_MIN_MODEL_SIZE 256 - -uint16_t eeLoadModelData(uint8_t id); -uint16_t eeLoadGeneralSettingsData(); - -bool eeModelExists(uint8_t id); -void eeLoadModel(uint8_t id); -bool eeConvert(); -void ConvertModel(int id, int version); -uint8_t eeFindEmptyModel(uint8_t id, bool down); -void selectModel(uint8_t sub); - -#if defined(CPUARM) - extern ModelHeader modelHeaders[MAX_MODELS]; - void eeLoadModelHeader(uint8_t id, ModelHeader *header); - void eeLoadModelHeaders(); -#else - #define eeLoadModelHeaders() -#endif +#define EEPROM_MIN_MODEL_SIZE 256 + +uint16_t eeLoadModelData(uint8_t id); +uint16_t eeLoadGeneralSettingsData(); + +bool eeModelExists(uint8_t id); +void eeLoadModel(uint8_t id); +bool eeConvert(); +void ConvertModel(int id, int version); +uint8_t eeFindEmptyModel(uint8_t id, bool down); +void selectModel(uint8_t sub); + +#if defined(CPUARM) + extern ModelHeader modelHeaders[MAX_MODELS]; + void eeLoadModelHeader(uint8_t id, ModelHeader *header); + void eeLoadModelHeaders(); +#else + #define eeLoadModelHeaders() +#endif void storageReadRadioSettings(); void storageReadCurrentModel(); diff --git a/radio/src/storage/eeprom_conversions.cpp b/radio/src/storage/eeprom_conversions.cpp index aaf7b57e2..f87e4a2d1 100644 --- a/radio/src/storage/eeprom_conversions.cpp +++ b/radio/src/storage/eeprom_conversions.cpp @@ -1,1304 +1,1304 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -enum Mix216Sources { - MIXSRC216_NONE, - -#if defined(PCBTARANIS) - MIXSRC216_FIRST_INPUT, - MIXSRC216_LAST_INPUT = MIXSRC216_FIRST_INPUT+MAX_INPUTS-1, - - MIXSRC216_FIRST_LUA, - MIXSRC216_LAST_LUA = MIXSRC216_FIRST_LUA+(MAX_SCRIPTS*MAX_SCRIPT_OUTPUTS)-1, -#endif - - MIXSRC216_Rud, - MIXSRC216_Ele, - MIXSRC216_Thr, - MIXSRC216_Ail, - - MIXSRC216_FIRST_POT, -#if defined(PCBTARANIS) - MIXSRC216_POT1 = MIXSRC216_FIRST_POT, - MIXSRC216_POT2, - MIXSRC216_POT3, - MIXSRC216_SLIDER1, - MIXSRC216_SLIDER2, - MIXSRC216_LAST_POT = MIXSRC216_SLIDER2, -#else - MIXSRC216_P1 = MIXSRC216_FIRST_POT, - MIXSRC216_P2, - MIXSRC216_P3, - MIXSRC216_LAST_POT = MIXSRC216_P3, -#endif - -#if defined(PCBSKY9X) - MIXSRC216_REa, - MIXSRC216_LAST_ROTARY_ENCODER = MIXSRC216_REa, -#endif - - MIXSRC216_MAX, - - MIXSRC216_CYC1, - MIXSRC216_CYC2, - MIXSRC216_CYC3, - - MIXSRC216_TrimRud, - MIXSRC216_TrimEle, - MIXSRC216_TrimThr, - MIXSRC216_TrimAil, - - MIXSRC216_FIRST_SWITCH, - -#if defined(PCBTARANIS) - MIXSRC216_SA = MIXSRC216_FIRST_SWITCH, - MIXSRC216_SB, - MIXSRC216_SC, - MIXSRC216_SD, - MIXSRC216_SE, - MIXSRC216_SF, - MIXSRC216_SG, - MIXSRC216_SH, -#else - MIXSRC216_3POS = MIXSRC216_FIRST_SWITCH, - MIXSRC216_THR, - MIXSRC216_RUD, - MIXSRC216_ELE, - MIXSRC216_AIL, - MIXSRC216_GEA, - MIXSRC216_TRN, -#endif - MIXSRC216_FIRST_LOGICAL_SWITCH, - MIXSRC216_SW1 = MIXSRC216_FIRST_LOGICAL_SWITCH, - MIXSRC216_SW9 = MIXSRC216_SW1 + 8, - MIXSRC216_SWA, - MIXSRC216_SWB, - MIXSRC216_SWC, - MIXSRC216_LAST_LOGICAL_SWITCH = MIXSRC216_FIRST_LOGICAL_SWITCH+32-1, - - MIXSRC216_FIRST_TRAINER, - MIXSRC216_LAST_TRAINER = MIXSRC216_FIRST_TRAINER+MAX_TRAINER_CHANNELS-1, - - MIXSRC216_FIRST_CH, - MIXSRC216_CH1 = MIXSRC216_FIRST_CH, - MIXSRC216_CH2, - MIXSRC216_CH3, - MIXSRC216_CH4, - MIXSRC216_CH5, - MIXSRC216_CH6, - MIXSRC216_CH7, - MIXSRC216_CH8, - MIXSRC216_CH9, - MIXSRC216_CH10, - MIXSRC216_CH11, - MIXSRC216_CH12, - MIXSRC216_CH13, - MIXSRC216_CH14, - MIXSRC216_CH15, - MIXSRC216_CH16, - MIXSRC216_LAST_CH = MIXSRC216_CH1+MAX_OUTPUT_CHANNELS-1, - - MIXSRC216_GVAR1, - MIXSRC216_LAST_GVAR = MIXSRC216_GVAR1+MAX_GVARS-1, - - MIXSRC216_FIRST_TELEM, -}; - -enum Telemetry216Source { - TELEM216_NONE, - TELEM216_TX_VOLTAGE, - TELEM216_TX_TIME, - TELEM216_RESERVE1, - TELEM216_RESERVE2, - TELEM216_RESERVE3, - TELEM216_RESERVE4, - TELEM216_RESERVE5, - TELEM216_TIMER1, - TELEM216_TIMER2, - TELEM216_SWR, - TELEM216_RSSI_TX, - TELEM216_RSSI_RX, - TELEM216_RESERVE0, - TELEM216_A1, - TELEM216_A2, - TELEM216_A3, - TELEM216_A4, - TELEM216_ALT, - TELEM216_RPM, - TELEM216_FUEL, - TELEM216_T1, - TELEM216_T2, - TELEM216_SPEED, - TELEM216_DIST, - TELEM216_GPSALT, - TELEM216_CELL, - TELEM216_CELLS_SUM, - TELEM216_VFAS, - TELEM216_CURRENT, - TELEM216_CONSUMPTION, - TELEM216_POWER, - TELEM216_ACCx, - TELEM216_ACCy, - TELEM216_ACCz, - TELEM216_HDG, - TELEM216_VSPEED, - TELEM216_ASPEED, - TELEM216_DTE, - TELEM216_RESERVE6, - TELEM216_RESERVE7, - TELEM216_RESERVE8, - TELEM216_RESERVE9, - TELEM216_RESERVE10, - TELEM216_MIN_A1, - TELEM216_MIN_A2, - TELEM216_MIN_A3, - TELEM216_MIN_A4, - TELEM216_MIN_ALT, - TELEM216_MAX_ALT, - TELEM216_MAX_RPM, - TELEM216_MAX_T1, - TELEM216_MAX_T2, - TELEM216_MAX_SPEED, - TELEM216_MAX_DIST, - TELEM216_MAX_ASPEED, - TELEM216_MIN_CELL, - TELEM216_MIN_CELLS_SUM, - TELEM216_MIN_VFAS, - TELEM216_MAX_CURRENT, - TELEM216_MAX_POWER, - TELEM216_RESERVE11, - TELEM216_RESERVE12, - TELEM216_RESERVE13, - TELEM216_RESERVE14, - TELEM216_RESERVE15, - TELEM216_ACC, - TELEM216_GPS_TIME, -}; - -#if defined(CPUARM) -PACK(typedef struct { - uint8_t type:3; - uint8_t smooth:1; - uint8_t spare:4; - int8_t points; -}) CurveData_v216; -#endif - -#if defined(PCBTARANIS) -PACK(typedef struct { - uint8_t srcRaw; - uint16_t scale; - uint8_t chn; - int8_t swtch; - uint16_t flightModes; - int8_t weight; - int8_t carryTrim:6; - uint8_t mode:2; - char name[LEN_EXPOMIX_NAME]; - int8_t offset; - CurveRef curve; - uint8_t spare; -}) ExpoData_v216; -PACK(typedef struct { - uint32_t srcRaw:10; - uint32_t scale:14; - uint32_t chn:8; - int8_t swtch; - uint16_t flightModes; - int8_t weight; - int8_t carryTrim:6; - uint8_t mode:2; - char name[LEN_EXPOMIX_NAME]; - int8_t offset; - CurveRef curve; -}) ExpoData_v217; -#else -PACK(typedef struct { - uint8_t mode:2; // 0=end, 1=pos, 2=neg, 3=both - uint8_t chn:4; - uint8_t curveMode:2; - int8_t swtch; - uint16_t flightModes; - int8_t weight; - char name[LEN_EXPOMIX_NAME]; - int8_t curveParam; -}) ExpoData_v216; -typedef ExpoData_v216 ExpoData_v217; -#endif - -#if defined(PCBTARANIS) -PACK(typedef struct { - int16_t min; - int16_t max; - int8_t ppmCenter; - int16_t offset:14; - uint16_t symetrical:1; - uint16_t revert:1; - char name[LEN_CHANNEL_NAME]; - int8_t curve; -}) LimitData_v216; -#else -#define LimitData_v216 LimitData -#endif - -#if defined(PCBTARANIS) -PACK(typedef struct { - uint8_t destCh; - uint16_t flightModes; - uint8_t mltpx:2; // multiplex method: 0 means +=, 1 means *=, 2 means := - uint8_t carryTrim:1; - uint8_t spare1:5; - int16_t weight; - int8_t swtch; - CurveRef curve; - uint8_t mixWarn:4; // mixer warning - uint8_t spare2:4; - uint8_t delayUp; - uint8_t delayDown; - uint8_t speedUp; - uint8_t speedDown; - uint8_t srcRaw; - int16_t offset; - char name[LEN_EXPOMIX_NAME]; - uint8_t spare3; -}) MixData_v216; -PACK(typedef struct { - uint8_t destCh; - uint16_t flightModes:9; - uint16_t mltpx:2; // multiplex method: 0 means +=, 1 means *=, 2 means := - uint16_t carryTrim:1; - uint16_t mixWarn:4; // mixer warning - int16_t weight; - uint32_t srcRaw:10; - int32_t offset:14; - int32_t swtch:8; - CurveRef curve; - uint8_t delayUp; - uint8_t delayDown; - uint8_t speedUp; - uint8_t speedDown; - char name[LEN_EXPOMIX_NAME]; -}) MixData_v217; -#else -PACK(typedef struct { - uint8_t destCh:5; - uint8_t mixWarn:3; // mixer warning - uint16_t flightModes; - uint8_t curveMode:1; - uint8_t noExpo:1; - int8_t carryTrim:3; - uint8_t mltpx:2; // multiplex method: 0 means +=, 1 means *=, 2 means := - uint8_t spare:1; - int16_t weight; - int8_t swtch; - int8_t curveParam; - uint8_t delayUp; - uint8_t delayDown; - uint8_t speedUp; - uint8_t speedDown; - uint8_t srcRaw; - int16_t offset; - char name[LEN_EXPOMIX_NAME]; -}) MixData_v216; -typedef MixData MixData_v217; -#endif - -PACK(typedef struct { - int8_t mode; // timer trigger source -> off, abs, stk, stk%, sw/!sw, !m_sw/!m_sw - uint16_t start; - uint8_t countdownBeep:2; - uint8_t minuteBeep:1; - uint8_t persistent:2; - uint8_t spare:3; - uint16_t value; -}) TimerData_v216; - -PACK(typedef struct { - int32_t mode:8; // timer trigger source -> off, abs, stk, stk%, sw/!sw, !m_sw/!m_sw - uint32_t start:24; - int32_t value:24; - uint32_t countdownBeep:2; - uint32_t minuteBeep:1; - uint32_t persistent:2; - uint32_t spare:3; - char name[LEN_TIMER_NAME]; -}) TimerData_v217; - -PACK(typedef struct { - int16_t trim[NUM_STICKS]; - int8_t swtch; // swtch of phase[0] is not used - char name[LEN_FLIGHT_MODE_NAME]; - uint8_t fadeIn; - uint8_t fadeOut; - int16_t rotaryEncoders[1]; - gvar_t gvars[9]; -}) FlightModeData_v216; - -PACK(typedef struct { // Logical Switches data - int8_t v1; - int16_t v2; - int16_t v3; - uint8_t func; - uint8_t delay; - uint8_t duration; - int8_t andsw; -}) LogicalSwitchData_v216; - -PACK(typedef struct { // Logical Switches data - uint16_t func:6; - int16_t v1:10; - int16_t v2; - int16_t v3; - uint8_t delay; - uint8_t duration; - int8_t andsw; -}) LogicalSwitchData_v217; - -#if defined(PCBTARANIS) -PACK(typedef struct { - int8_t swtch; - uint8_t func; - PACK(union { - PACK(struct { - char name[8]; - }) play; - - PACK(struct { - int16_t val; - uint8_t mode; - uint8_t param; - int32_t spare2; - }) all; - - PACK(struct { - int32_t val1; - int32_t val2; - }) clear; - }); - uint8_t active; -}) CustomFunctionData_v216; -#else -PACK(typedef struct { - int8_t swtch; - uint8_t func; - PACK(union { - PACK(struct { - char name[6]; - }) play; - - PACK(struct { - int16_t val; - uint8_t mode; - uint8_t param; - int16_t spare2; - }) all; - - PACK(struct { - int32_t val1; - int16_t val2; - }) clear; - }); - uint8_t active; -}) CustomFunctionData_v216; -#endif - -PACK(typedef struct { - uint8_t source; - uint8_t barMin; // minimum for bar display - uint8_t barMax; // ditto for max display (would usually = ratio) -}) FrSkyBarData_v216; - -PACK(typedef struct { - uint8_t sources[NUM_LINE_ITEMS]; -}) FrSkyLineData_v216; - -typedef union { - FrSkyBarData_v216 bars[4]; - FrSkyLineData_v216 lines[4]; -} FrSkyScreenData_v216; - -PACK(typedef struct { - FrSkyChannelData channels[4]; - uint8_t usrProto; // Protocol in FrSky user data, 0=None, 1=FrSky hub, 2=WS HowHigh, 3=Halcyon - uint8_t voltsSource:7; - uint8_t altitudeDisplayed:1; - int8_t blades; // How many blades for RPMs, 0=2 blades - uint8_t currentSource; - uint8_t screensType; // 2bits per screen (None/Gauges/Numbers/Script) - FrSkyScreenData_v216 screens[3]; - uint8_t varioSource; - int8_t varioCenterMax; - int8_t varioCenterMin; - int8_t varioMin; - int8_t varioMax; - FrSkyRSSIAlarm rssiAlarms[2]; - uint16_t mAhPersistent:1; - uint16_t storedMah:15; - int8_t fasOffset; -}) FrSkyData_v216; - -PACK(typedef struct { - char file[10]; - char name[10]; - int8_t inputs[10]; -}) ScriptData_v216; - -PACK(typedef struct { // Swash Ring data - uint8_t invertELE:1; - uint8_t invertAIL:1; - uint8_t invertCOL:1; - uint8_t type:5; - uint8_t collectiveSource; - uint8_t value; -}) SwashRingData_v216; - -PACK(typedef struct { - int8_t rfProtocol; - uint8_t channelsStart; - int8_t channelsCount; // 0=8 channels - uint8_t failsafeMode; - int16_t failsafeChannels[MAX_OUTPUT_CHANNELS]; - int8_t ppmDelay; - int8_t ppmFrameLength; - uint8_t ppmPulsePol; -}) ModuleData_v216; - -#if defined(PCBTARANIS) -#define MODELDATA_EXTRA_216 \ - uint8_t externalModule; \ - uint8_t trainerMode; \ - ModuleData_v216 moduleData[NUM_MODULES+1]; \ - char curveNames[MAX_CURVES][6]; \ - ScriptData_v216 scriptsData[MAX_SCRIPTS]; \ - char inputNames[MAX_INPUTS][LEN_INPUT_NAME]; \ - uint8_t nPotsToWarn; \ - int8_t potPosition[NUM_POTS+NUM_SLIDERS]; \ - uint8_t spare[2]; -#elif defined(PCBSKY9X) -#define MODELDATA_EXTRA_216 \ - uint8_t externalModule; \ - ModuleData_v216 moduleData[NUM_MODULES+1]; \ - uint8_t nPotsToWarn; \ - int8_t potPosition[NUM_POTS+NUM_SLIDERS]; \ - uint8_t rxBattAlarms[2]; -#endif - -#if defined(PCBTARANIS) -#define MODELDATA_EXTRA_217 \ - uint8_t spare:3; \ - uint8_t trainerMode:3; \ - uint8_t potsWarnMode:2; \ - ModuleData moduleData[NUM_MODULES+1]; \ - char curveNames[MAX_CURVES][6]; \ - ScriptData scriptsData[MAX_SCRIPTS]; \ - char inputNames[MAX_INPUTS][LEN_INPUT_NAME]; \ - uint8_t potsWarnEnabled; \ - int8_t potsWarnPosition[NUM_POTS+NUM_SLIDERS]; -#else -#define MODELDATA_EXTRA_217 \ - uint8_t spare:6; \ - uint8_t potsWarnMode:2; \ - ModuleData moduleData[NUM_MODULES+1]; \ - uint8_t potsWarnEnabled; \ - int8_t potsWarnPosition[NUM_POTS+NUM_SLIDERS]; \ - uint8_t rxBattAlarms[2]; -#endif - -#if defined(PCBTARANIS) && LCD_W >= 212 -PACK(typedef struct { - char name[LEN_MODEL_NAME]; - uint8_t modelId; - char bitmap[LEN_BITMAP_NAME]; -}) ModelHeader_v216; -#else -PACK(typedef struct { - char name[LEN_MODEL_NAME]; - uint8_t modelId; -}) ModelHeader_v216; -#endif - -PACK(typedef struct { - ModelHeader_v216 header; - TimerData_v216 timers[2]; - AVR_FIELD(uint8_t protocol:3) - ARM_FIELD(uint8_t telemetryProtocol:3) - uint8_t thrTrim:1; // Enable Throttle Trim - AVR_FIELD(int8_t ppmNCH:4) - ARM_FIELD(int8_t spare2:4) - int8_t trimInc:3; // Trim Increments - uint8_t disableThrottleWarning:1; - ARM_FIELD(uint8_t displayChecklist:1) - AVR_FIELD(uint8_t pulsePol:1) - uint8_t extendedLimits:1; - uint8_t extendedTrims:1; - uint8_t throttleReversed:1; - AVR_FIELD(int8_t ppmDelay) - BeepANACenter beepANACenter; // 1<<0->A1.. 1<<6->A7 - MixData_v216 mixData[MAX_MIXERS]; - LimitData_v216 limitData[MAX_OUTPUT_CHANNELS]; - ExpoData_v216 expoData[MAX_EXPOS]; - - CurveData_v216 curves[MAX_CURVES]; - int8_t points[MAX_CURVE_POINTS]; - - LogicalSwitchData_v216 logicalSw[32]; - CustomFunctionData_v216 customFn[MAX_SPECIAL_FUNCTIONS]; - SwashRingData_v216 swashR; - FlightModeData_v216 flightModeData[MAX_FLIGHT_MODES]; - - uint8_t thrTraceSrc; - - uint16_t switchWarningState; - uint8_t switchWarningEnable; - - GVarData gvars[MAX_GVARS]; - - FrSkyData_v216 frsky; - - MODELDATA_EXTRA_216 - -}) ModelData_v216; - -PACK(typedef struct { - ModelHeader header; - TimerData_v217 timers[MAX_TIMERS]; - ARM_FIELD(uint8_t telemetryProtocol:3) - uint8_t thrTrim:1; // Enable Throttle Trim - ARM_FIELD(uint8_t noGlobalFunctions:1) - ARM_FIELD(uint8_t displayTrims:2) - ARM_FIELD(uint8_t ignoreSensorIds:1) - int8_t trimInc:3; // Trim Increments - uint8_t disableThrottleWarning:1; - ARM_FIELD(uint8_t displayChecklist:1) - uint8_t extendedLimits:1; - uint8_t extendedTrims:1; - uint8_t throttleReversed:1; - BeepANACenter beepANACenter; - MixData_v217 mixData[MAX_MIXERS]; - LimitData limitData[MAX_OUTPUT_CHANNELS]; - ExpoData_v217 expoData[MAX_EXPOS]; - - CurveData_v216 curves[MAX_CURVES]; - int8_t points[MAX_CURVE_POINTS]; - - LogicalSwitchData_v217 logicalSw[32]; - CustomFunctionData_v216 customFn[MAX_SPECIAL_FUNCTIONS]; - SwashRingData swashR; - FlightModeData_v216 flightModeData[MAX_FLIGHT_MODES]; - - uint8_t thrTraceSrc; - - swarnstate_t switchWarningState; - swarnenable_t switchWarningEnable; - - GVarData gvars[MAX_GVARS]; - - FrSkyTelemetryData frsky; - - MODELDATA_EXTRA_217 - - TelemetrySensor telemetrySensors[MAX_TELEMETRY_SENSORS]; - - TARANIS_PCBX9E_FIELD(uint8_t toplcdTimer) -}) ModelData_v217; - -int ConvertTelemetrySource_216_to_217(int source) -{ - // TELEM_TIMER3 added -// if (source >= TELEM_TIMER3) - // source += 1; - - return source; -} - -#if defined(PCBTARANIS) -int ConvertSwitch_216_to_217(int swtch) -{ - if (swtch < 0) - return -ConvertSwitch_216_to_217(-swtch); - - if (swtch > SWSRC_SF0) - swtch += 1; - - if (swtch > SWSRC_SH0) - swtch += 1; - - return swtch; -} -#else -int ConvertSwitch_216_to_217(int swtch) -{ - return swtch; -} -#endif - -int ConvertSwitch_217_to_218(int swtch) -{ - // 32 additional logical switches - - if (swtch < 0) - return -ConvertSwitch_217_to_218(-swtch); - - if (swtch >= SWSRC_FIRST_LOGICAL_SWITCH+32) - return swtch+32; - - return swtch; -} - -int ConvertSource_216_to_217(int source) -{ -#if defined(PCBX9E) - // SI to SR switches added - if (source >= MIXSRC_SI) - source += 10; -#endif - // Telemetry conversions - if (source >= MIXSRC_FIRST_TELEM) - source = 0; - - return source; -} - -int ConvertSource_217_to_218(int source) -{ -#if defined(PCBTARANIS) - if (source >= MIXSRC_FIRST_LOGICAL_SWITCH + 32) - source += 32; -#endif - - return source; -} - -int ConvertGVar_216_to_217(int value) -{ - if (value < -4096 + 9) - value += 4096 - 1024; - else if (value > 4095 - 9) - value -= 4095 - 1023; - return value; -} - -PACK(typedef struct { - uint8_t version; - uint16_t variant; - CalibData calib[NUM_STICKS+NUM_POTS+NUM_SLIDERS]; - uint16_t chkSum; - int8_t currModel; - uint8_t contrast; - uint8_t vBatWarn; - int8_t txVoltageCalibration; - int8_t backlightMode; - TrainerData trainer; - uint8_t view; // index of view in main screen - int8_t buzzerMode:2; // -2=quiet, -1=only alarms, 0=no keys, 1=all - uint8_t fai:1; - int8_t beepMode:2; // -2=quiet, -1=only alarms, 0=no keys, 1=all - uint8_t alarmsFlash:1; - uint8_t disableMemoryWarning:1; - uint8_t disableAlarmWarning:1; - uint8_t stickMode:2; - int8_t timezone:5; - uint8_t adjustRTC:1; - uint8_t inactivityTimer; - uint8_t mavbaud:3; - int8_t splashMode:3; - int8_t hapticMode:2; // -2=quiet, -1=only alarms, 0=no keys, 1=all - int8_t switchesDelay; - uint8_t lightAutoOff; - uint8_t templateSetup; // RETA order for receiver channels - int8_t PPM_Multiplier; - int8_t hapticLength; - uint8_t reNavigation; - N_TARANIS_FIELD(uint8_t stickReverse) - int8_t beepLength:3; - int8_t hapticStrength:3; - uint8_t gpsFormat:1; - uint8_t unexpectedShutdown:1; - uint8_t speakerPitch; - int8_t speakerVolume; - int8_t vBatMin; - int8_t vBatMax; - - uint8_t backlightBright; - int8_t txCurrentCalibration; - int8_t temperatureWarn; - uint8_t mAhWarn; - uint16_t mAhUsed; - uint32_t globalTimer; - int8_t temperatureCalib; - uint8_t btBaudrate; - uint8_t optrexDisplay; - uint8_t sticksGain; - uint8_t rotarySteps; - uint8_t countryCode; - uint8_t imperial; - char ttsLanguage[2]; - int8_t beepVolume; - int8_t wavVolume; - int8_t varioVolume; - int8_t varioPitch; - int8_t varioRange; - int8_t varioRepeat; - int8_t backgroundVolume; - - TARANIS_FIELD(uint8_t serial2Mode:6) - TARANIS_FIELD(uint8_t slidersConfig:2) - TARANIS_FIELD(uint8_t potsConfig) - TARANIS_FIELD(uint8_t backlightColor) - TARANIS_FIELD(swarnstate_t switchUnlockStates) - TARANIS_FIELD(CustomFunctionData_v216 customFn[MAX_SPECIAL_FUNCTIONS]) - TARANIS_FIELD(swconfig_t switchConfig) - TARANIS_FIELD(char switchNames[NUM_SWITCHES][LEN_SWITCH_NAME]) - TARANIS_FIELD(char anaNames[NUM_STICKS+NUM_POTS+NUM_SLIDERS][LEN_ANA_NAME]) - N_TARANIS_FIELD(CustomFunctionData_v216 customFn[MAX_SPECIAL_FUNCTIONS]) - - TARANIS_PCBX9E_FIELD(uint8_t bluetoothEnable) - TARANIS_PCBX9E_FIELD(char bluetoothName[LEN_BLUETOOTH_NAME]) -}) RadioData_v216; - -void ConvertRadioData_216_to_217(RadioData & settings) -{ - RadioData_v216 * settings_v216 = (RadioData_v216 *)&settings; - settings_v216->version = 217; -#if defined(PCBTARANIS) - settings_v216->potsConfig = 0x05; // S1 and S2 = pots with detent - settings_v216->switchConfig = 0x00007bff; // 6x3POS, 1x2POS, 1xTOGGLE -#endif -} - -void ConvertSpecialFunctions_217_to_218(CustomFunctionData * cf218, CustomFunctionData_v216 * cf216) -{ - for (int i=0; i= 212 - memcpy(newModel.header.bitmap, oldModel.header.bitmap, LEN_BITMAP_NAME); -#endif - - for (uint8_t i=0; i<2; i++) { - TimerData_v217 & timer = newModel.timers[i]; - if (oldModel.timers[i].mode >= TMRMODE_COUNT) - timer.mode = TMRMODE_COUNT + ConvertSwitch_216_to_217(oldModel.timers[i].mode - TMRMODE_COUNT + 1) - 1; - else - timer.mode = ConvertSwitch_216_to_217(oldModel.timers[i].mode); - timer.start = oldModel.timers[i].start; - timer.countdownBeep = oldModel.timers[i].countdownBeep; - timer.minuteBeep = oldModel.timers[i].minuteBeep; - timer.persistent = oldModel.timers[i].persistent; - timer.value = oldModel.timers[i].value; - } - newModel.telemetryProtocol = oldModel.telemetryProtocol; - newModel.thrTrim = oldModel.thrTrim; - newModel.trimInc = oldModel.trimInc; - newModel.disableThrottleWarning = oldModel.disableThrottleWarning; - newModel.displayChecklist = oldModel.displayChecklist; - newModel.extendedLimits = oldModel.extendedLimits; - newModel.extendedTrims = oldModel.extendedTrims; - newModel.throttleReversed = oldModel.throttleReversed; - newModel.beepANACenter = oldModel.beepANACenter; - for (int i=0; i> 6; - newModel.potsWarnEnabled = oldModel.nPotsToWarn & 0x1f; - memcpy(newModel.potsWarnPosition, oldModel.potPosition, sizeof(newModel.potsWarnPosition)); -} - -void ConvertModel_217_to_218(ModelData & model) -{ - assert(sizeof(ModelData_v217) <= sizeof(ModelData)); - - ModelData_v217 oldModel; - memcpy(&oldModel, &model, sizeof(oldModel)); - ModelData & newModel = model; - memset(&newModel, 0, sizeof(ModelData)); - - char name[LEN_MODEL_NAME+1]; - zchar2str(name, oldModel.header.name, LEN_MODEL_NAME); - TRACE("Model %s conversion from v217 to v218", name); - - newModel.header = oldModel.header; - for (uint8_t i=0; i= TMRMODE_COUNT) - newModel.timers[i].mode = TMRMODE_COUNT + ConvertSwitch_217_to_218(oldModel.timers[i].mode - TMRMODE_COUNT + 1) - 1; - else - newModel.timers[i].mode = ConvertSwitch_217_to_218(oldModel.timers[i].mode); - if (oldModel.timers[i].mode) - TRACE("timer mode %d => %d", oldModel.timers[i].mode, newModel.timers[i].mode); - newModel.timers[i].start = oldModel.timers[i].start; - newModel.timers[i].value = oldModel.timers[i].value; - newModel.timers[i].countdownBeep = oldModel.timers[i].countdownBeep; - newModel.timers[i].minuteBeep = oldModel.timers[i].minuteBeep; - newModel.timers[i].persistent = oldModel.timers[i].persistent; - memcpy(newModel.timers[i].name, oldModel.timers[i].name, sizeof(newModel.timers[i].name)); - } - newModel.telemetryProtocol = oldModel.telemetryProtocol; - newModel.thrTrim = oldModel.thrTrim; - newModel.noGlobalFunctions = oldModel.noGlobalFunctions; - newModel.displayTrims = oldModel.displayTrims; - newModel.ignoreSensorIds = oldModel.ignoreSensorIds; - newModel.trimInc = oldModel.trimInc; - newModel.disableThrottleWarning = oldModel.disableThrottleWarning; - newModel.displayChecklist = oldModel.displayChecklist; - newModel.extendedLimits = oldModel.extendedLimits; - newModel.extendedTrims = oldModel.extendedTrims; - newModel.throttleReversed = oldModel.throttleReversed; - newModel.beepANACenter = oldModel.beepANACenter; - for (int i=0; i> (2*i)) & 0x03) == TELEMETRY_SCREEN_TYPE_VALUES) { - for (int j = 0; j < 4; j++) { - for (int k = 0; k < NUM_LINE_ITEMS; k++) { - newModel.frsky.screens[i].lines[j].sources[k] = ConvertSource_217_to_218(oldModel.frsky.screens[i].lines[j].sources[k]); - } - } - } - else if (((oldModel.frsky.screensType >> (2*i)) & 0x03) == TELEMETRY_SCREEN_TYPE_GAUGES) { - for (int j = 0; j < 4; j++) { - newModel.frsky.screens[i].bars[j].source = ConvertSource_217_to_218(oldModel.frsky.screens[i].bars[j].source); - } - } - } - for (int i=0; i UNIT_WATTS) - newModel.telemetrySensors[i].unit += 1; - } -#if defined(PCBX9E) - newModel.toplcdTimer = oldModel.toplcdTimer; -#endif -} - -void ConvertModel(int id, int version) -{ - eeLoadModelData(id); - - if (version == 216) { - version = 217; - ConvertModel_216_to_217(g_model); - } - if (version == 217) { - version = 218; - ConvertModel_217_to_218(g_model); - } - - uint8_t currModel = g_eeGeneral.currModel; - g_eeGeneral.currModel = id; - storageDirty(EE_MODEL); - storageCheck(true); - g_eeGeneral.currModel = currModel; -} - -bool eeConvert() -{ - const char *msg = NULL; - - if (g_eeGeneral.version == 216) { - msg = PSTR("EEprom Data v216"); - } - else if (g_eeGeneral.version == 217) { - msg = PSTR("EEprom Data v217"); - } - else { - return false; - } - - int conversionVersionStart = g_eeGeneral.version; - - // Information to the user and wait for key press -#if defined(PCBSKY9X) - g_eeGeneral.optrexDisplay = 0; -#endif - g_eeGeneral.backlightMode = e_backlight_mode_on; - g_eeGeneral.backlightBright = 0; - g_eeGeneral.contrast = 25; - - ALERT(STR_STORAGE_WARNING, msg, AU_BAD_RADIODATA); - - RAISE_ALERT(STR_STORAGE_WARNING, STR_EEPROM_CONVERTING, NULL, AU_NONE); - - // General Settings conversion - eeLoadGeneralSettingsData(); - int version = conversionVersionStart; - if (version == 216) { - version = 217; - ConvertRadioData_216_to_217(g_eeGeneral); - } - if (version == 217) { - version = 218; - ConvertRadioData_217_to_218(g_eeGeneral); - } - storageDirty(EE_GENERAL); - storageCheck(true); - -#if defined(COLORLCD) -#elif LCD_W >= 212 - lcdDrawRect(60, 6*FH+4, 132, 3); -#else - lcdDrawRect(10, 6*FH+4, 102, 3); -#endif - - // Models conversion - for (uint8_t id=0; id= 212 - lcdDrawSolidHorizontalLine(61, 6*FH+5, 10+id*2, FORCE); -#else - lcdDrawSolidHorizontalLine(11, 6*FH+5, 10+(id*3)/2, FORCE); -#endif - lcdRefresh(); - if (eeModelExists(id)) { - ConvertModel(id, conversionVersionStart); - } - - } - - return true; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +enum Mix216Sources { + MIXSRC216_NONE, + +#if defined(PCBTARANIS) + MIXSRC216_FIRST_INPUT, + MIXSRC216_LAST_INPUT = MIXSRC216_FIRST_INPUT+MAX_INPUTS-1, + + MIXSRC216_FIRST_LUA, + MIXSRC216_LAST_LUA = MIXSRC216_FIRST_LUA+(MAX_SCRIPTS*MAX_SCRIPT_OUTPUTS)-1, +#endif + + MIXSRC216_Rud, + MIXSRC216_Ele, + MIXSRC216_Thr, + MIXSRC216_Ail, + + MIXSRC216_FIRST_POT, +#if defined(PCBTARANIS) + MIXSRC216_POT1 = MIXSRC216_FIRST_POT, + MIXSRC216_POT2, + MIXSRC216_POT3, + MIXSRC216_SLIDER1, + MIXSRC216_SLIDER2, + MIXSRC216_LAST_POT = MIXSRC216_SLIDER2, +#else + MIXSRC216_P1 = MIXSRC216_FIRST_POT, + MIXSRC216_P2, + MIXSRC216_P3, + MIXSRC216_LAST_POT = MIXSRC216_P3, +#endif + +#if defined(PCBSKY9X) + MIXSRC216_REa, + MIXSRC216_LAST_ROTARY_ENCODER = MIXSRC216_REa, +#endif + + MIXSRC216_MAX, + + MIXSRC216_CYC1, + MIXSRC216_CYC2, + MIXSRC216_CYC3, + + MIXSRC216_TrimRud, + MIXSRC216_TrimEle, + MIXSRC216_TrimThr, + MIXSRC216_TrimAil, + + MIXSRC216_FIRST_SWITCH, + +#if defined(PCBTARANIS) + MIXSRC216_SA = MIXSRC216_FIRST_SWITCH, + MIXSRC216_SB, + MIXSRC216_SC, + MIXSRC216_SD, + MIXSRC216_SE, + MIXSRC216_SF, + MIXSRC216_SG, + MIXSRC216_SH, +#else + MIXSRC216_3POS = MIXSRC216_FIRST_SWITCH, + MIXSRC216_THR, + MIXSRC216_RUD, + MIXSRC216_ELE, + MIXSRC216_AIL, + MIXSRC216_GEA, + MIXSRC216_TRN, +#endif + MIXSRC216_FIRST_LOGICAL_SWITCH, + MIXSRC216_SW1 = MIXSRC216_FIRST_LOGICAL_SWITCH, + MIXSRC216_SW9 = MIXSRC216_SW1 + 8, + MIXSRC216_SWA, + MIXSRC216_SWB, + MIXSRC216_SWC, + MIXSRC216_LAST_LOGICAL_SWITCH = MIXSRC216_FIRST_LOGICAL_SWITCH+32-1, + + MIXSRC216_FIRST_TRAINER, + MIXSRC216_LAST_TRAINER = MIXSRC216_FIRST_TRAINER+MAX_TRAINER_CHANNELS-1, + + MIXSRC216_FIRST_CH, + MIXSRC216_CH1 = MIXSRC216_FIRST_CH, + MIXSRC216_CH2, + MIXSRC216_CH3, + MIXSRC216_CH4, + MIXSRC216_CH5, + MIXSRC216_CH6, + MIXSRC216_CH7, + MIXSRC216_CH8, + MIXSRC216_CH9, + MIXSRC216_CH10, + MIXSRC216_CH11, + MIXSRC216_CH12, + MIXSRC216_CH13, + MIXSRC216_CH14, + MIXSRC216_CH15, + MIXSRC216_CH16, + MIXSRC216_LAST_CH = MIXSRC216_CH1+MAX_OUTPUT_CHANNELS-1, + + MIXSRC216_GVAR1, + MIXSRC216_LAST_GVAR = MIXSRC216_GVAR1+MAX_GVARS-1, + + MIXSRC216_FIRST_TELEM, +}; + +enum Telemetry216Source { + TELEM216_NONE, + TELEM216_TX_VOLTAGE, + TELEM216_TX_TIME, + TELEM216_RESERVE1, + TELEM216_RESERVE2, + TELEM216_RESERVE3, + TELEM216_RESERVE4, + TELEM216_RESERVE5, + TELEM216_TIMER1, + TELEM216_TIMER2, + TELEM216_SWR, + TELEM216_RSSI_TX, + TELEM216_RSSI_RX, + TELEM216_RESERVE0, + TELEM216_A1, + TELEM216_A2, + TELEM216_A3, + TELEM216_A4, + TELEM216_ALT, + TELEM216_RPM, + TELEM216_FUEL, + TELEM216_T1, + TELEM216_T2, + TELEM216_SPEED, + TELEM216_DIST, + TELEM216_GPSALT, + TELEM216_CELL, + TELEM216_CELLS_SUM, + TELEM216_VFAS, + TELEM216_CURRENT, + TELEM216_CONSUMPTION, + TELEM216_POWER, + TELEM216_ACCx, + TELEM216_ACCy, + TELEM216_ACCz, + TELEM216_HDG, + TELEM216_VSPEED, + TELEM216_ASPEED, + TELEM216_DTE, + TELEM216_RESERVE6, + TELEM216_RESERVE7, + TELEM216_RESERVE8, + TELEM216_RESERVE9, + TELEM216_RESERVE10, + TELEM216_MIN_A1, + TELEM216_MIN_A2, + TELEM216_MIN_A3, + TELEM216_MIN_A4, + TELEM216_MIN_ALT, + TELEM216_MAX_ALT, + TELEM216_MAX_RPM, + TELEM216_MAX_T1, + TELEM216_MAX_T2, + TELEM216_MAX_SPEED, + TELEM216_MAX_DIST, + TELEM216_MAX_ASPEED, + TELEM216_MIN_CELL, + TELEM216_MIN_CELLS_SUM, + TELEM216_MIN_VFAS, + TELEM216_MAX_CURRENT, + TELEM216_MAX_POWER, + TELEM216_RESERVE11, + TELEM216_RESERVE12, + TELEM216_RESERVE13, + TELEM216_RESERVE14, + TELEM216_RESERVE15, + TELEM216_ACC, + TELEM216_GPS_TIME, +}; + +#if defined(CPUARM) +PACK(typedef struct { + uint8_t type:3; + uint8_t smooth:1; + uint8_t spare:4; + int8_t points; +}) CurveData_v216; +#endif + +#if defined(PCBTARANIS) +PACK(typedef struct { + uint8_t srcRaw; + uint16_t scale; + uint8_t chn; + int8_t swtch; + uint16_t flightModes; + int8_t weight; + int8_t carryTrim:6; + uint8_t mode:2; + char name[LEN_EXPOMIX_NAME]; + int8_t offset; + CurveRef curve; + uint8_t spare; +}) ExpoData_v216; +PACK(typedef struct { + uint32_t srcRaw:10; + uint32_t scale:14; + uint32_t chn:8; + int8_t swtch; + uint16_t flightModes; + int8_t weight; + int8_t carryTrim:6; + uint8_t mode:2; + char name[LEN_EXPOMIX_NAME]; + int8_t offset; + CurveRef curve; +}) ExpoData_v217; +#else +PACK(typedef struct { + uint8_t mode:2; // 0=end, 1=pos, 2=neg, 3=both + uint8_t chn:4; + uint8_t curveMode:2; + int8_t swtch; + uint16_t flightModes; + int8_t weight; + char name[LEN_EXPOMIX_NAME]; + int8_t curveParam; +}) ExpoData_v216; +typedef ExpoData_v216 ExpoData_v217; +#endif + +#if defined(PCBTARANIS) +PACK(typedef struct { + int16_t min; + int16_t max; + int8_t ppmCenter; + int16_t offset:14; + uint16_t symetrical:1; + uint16_t revert:1; + char name[LEN_CHANNEL_NAME]; + int8_t curve; +}) LimitData_v216; +#else +#define LimitData_v216 LimitData +#endif + +#if defined(PCBTARANIS) +PACK(typedef struct { + uint8_t destCh; + uint16_t flightModes; + uint8_t mltpx:2; // multiplex method: 0 means +=, 1 means *=, 2 means := + uint8_t carryTrim:1; + uint8_t spare1:5; + int16_t weight; + int8_t swtch; + CurveRef curve; + uint8_t mixWarn:4; // mixer warning + uint8_t spare2:4; + uint8_t delayUp; + uint8_t delayDown; + uint8_t speedUp; + uint8_t speedDown; + uint8_t srcRaw; + int16_t offset; + char name[LEN_EXPOMIX_NAME]; + uint8_t spare3; +}) MixData_v216; +PACK(typedef struct { + uint8_t destCh; + uint16_t flightModes:9; + uint16_t mltpx:2; // multiplex method: 0 means +=, 1 means *=, 2 means := + uint16_t carryTrim:1; + uint16_t mixWarn:4; // mixer warning + int16_t weight; + uint32_t srcRaw:10; + int32_t offset:14; + int32_t swtch:8; + CurveRef curve; + uint8_t delayUp; + uint8_t delayDown; + uint8_t speedUp; + uint8_t speedDown; + char name[LEN_EXPOMIX_NAME]; +}) MixData_v217; +#else +PACK(typedef struct { + uint8_t destCh:5; + uint8_t mixWarn:3; // mixer warning + uint16_t flightModes; + uint8_t curveMode:1; + uint8_t noExpo:1; + int8_t carryTrim:3; + uint8_t mltpx:2; // multiplex method: 0 means +=, 1 means *=, 2 means := + uint8_t spare:1; + int16_t weight; + int8_t swtch; + int8_t curveParam; + uint8_t delayUp; + uint8_t delayDown; + uint8_t speedUp; + uint8_t speedDown; + uint8_t srcRaw; + int16_t offset; + char name[LEN_EXPOMIX_NAME]; +}) MixData_v216; +typedef MixData MixData_v217; +#endif + +PACK(typedef struct { + int8_t mode; // timer trigger source -> off, abs, stk, stk%, sw/!sw, !m_sw/!m_sw + uint16_t start; + uint8_t countdownBeep:2; + uint8_t minuteBeep:1; + uint8_t persistent:2; + uint8_t spare:3; + uint16_t value; +}) TimerData_v216; + +PACK(typedef struct { + int32_t mode:8; // timer trigger source -> off, abs, stk, stk%, sw/!sw, !m_sw/!m_sw + uint32_t start:24; + int32_t value:24; + uint32_t countdownBeep:2; + uint32_t minuteBeep:1; + uint32_t persistent:2; + uint32_t spare:3; + char name[LEN_TIMER_NAME]; +}) TimerData_v217; + +PACK(typedef struct { + int16_t trim[NUM_STICKS]; + int8_t swtch; // swtch of phase[0] is not used + char name[LEN_FLIGHT_MODE_NAME]; + uint8_t fadeIn; + uint8_t fadeOut; + int16_t rotaryEncoders[1]; + gvar_t gvars[9]; +}) FlightModeData_v216; + +PACK(typedef struct { // Logical Switches data + int8_t v1; + int16_t v2; + int16_t v3; + uint8_t func; + uint8_t delay; + uint8_t duration; + int8_t andsw; +}) LogicalSwitchData_v216; + +PACK(typedef struct { // Logical Switches data + uint16_t func:6; + int16_t v1:10; + int16_t v2; + int16_t v3; + uint8_t delay; + uint8_t duration; + int8_t andsw; +}) LogicalSwitchData_v217; + +#if defined(PCBTARANIS) +PACK(typedef struct { + int8_t swtch; + uint8_t func; + PACK(union { + PACK(struct { + char name[8]; + }) play; + + PACK(struct { + int16_t val; + uint8_t mode; + uint8_t param; + int32_t spare2; + }) all; + + PACK(struct { + int32_t val1; + int32_t val2; + }) clear; + }); + uint8_t active; +}) CustomFunctionData_v216; +#else +PACK(typedef struct { + int8_t swtch; + uint8_t func; + PACK(union { + PACK(struct { + char name[6]; + }) play; + + PACK(struct { + int16_t val; + uint8_t mode; + uint8_t param; + int16_t spare2; + }) all; + + PACK(struct { + int32_t val1; + int16_t val2; + }) clear; + }); + uint8_t active; +}) CustomFunctionData_v216; +#endif + +PACK(typedef struct { + uint8_t source; + uint8_t barMin; // minimum for bar display + uint8_t barMax; // ditto for max display (would usually = ratio) +}) FrSkyBarData_v216; + +PACK(typedef struct { + uint8_t sources[NUM_LINE_ITEMS]; +}) FrSkyLineData_v216; + +typedef union { + FrSkyBarData_v216 bars[4]; + FrSkyLineData_v216 lines[4]; +} FrSkyScreenData_v216; + +PACK(typedef struct { + FrSkyChannelData channels[4]; + uint8_t usrProto; // Protocol in FrSky user data, 0=None, 1=FrSky hub, 2=WS HowHigh, 3=Halcyon + uint8_t voltsSource:7; + uint8_t altitudeDisplayed:1; + int8_t blades; // How many blades for RPMs, 0=2 blades + uint8_t currentSource; + uint8_t screensType; // 2bits per screen (None/Gauges/Numbers/Script) + FrSkyScreenData_v216 screens[3]; + uint8_t varioSource; + int8_t varioCenterMax; + int8_t varioCenterMin; + int8_t varioMin; + int8_t varioMax; + FrSkyRSSIAlarm rssiAlarms[2]; + uint16_t mAhPersistent:1; + uint16_t storedMah:15; + int8_t fasOffset; +}) FrSkyData_v216; + +PACK(typedef struct { + char file[10]; + char name[10]; + int8_t inputs[10]; +}) ScriptData_v216; + +PACK(typedef struct { // Swash Ring data + uint8_t invertELE:1; + uint8_t invertAIL:1; + uint8_t invertCOL:1; + uint8_t type:5; + uint8_t collectiveSource; + uint8_t value; +}) SwashRingData_v216; + +PACK(typedef struct { + int8_t rfProtocol; + uint8_t channelsStart; + int8_t channelsCount; // 0=8 channels + uint8_t failsafeMode; + int16_t failsafeChannels[MAX_OUTPUT_CHANNELS]; + int8_t ppmDelay; + int8_t ppmFrameLength; + uint8_t ppmPulsePol; +}) ModuleData_v216; + +#if defined(PCBTARANIS) +#define MODELDATA_EXTRA_216 \ + uint8_t externalModule; \ + uint8_t trainerMode; \ + ModuleData_v216 moduleData[NUM_MODULES+1]; \ + char curveNames[MAX_CURVES][6]; \ + ScriptData_v216 scriptsData[MAX_SCRIPTS]; \ + char inputNames[MAX_INPUTS][LEN_INPUT_NAME]; \ + uint8_t nPotsToWarn; \ + int8_t potPosition[NUM_POTS+NUM_SLIDERS]; \ + uint8_t spare[2]; +#elif defined(PCBSKY9X) +#define MODELDATA_EXTRA_216 \ + uint8_t externalModule; \ + ModuleData_v216 moduleData[NUM_MODULES+1]; \ + uint8_t nPotsToWarn; \ + int8_t potPosition[NUM_POTS+NUM_SLIDERS]; \ + uint8_t rxBattAlarms[2]; +#endif + +#if defined(PCBTARANIS) +#define MODELDATA_EXTRA_217 \ + uint8_t spare:3; \ + uint8_t trainerMode:3; \ + uint8_t potsWarnMode:2; \ + ModuleData moduleData[NUM_MODULES+1]; \ + char curveNames[MAX_CURVES][6]; \ + ScriptData scriptsData[MAX_SCRIPTS]; \ + char inputNames[MAX_INPUTS][LEN_INPUT_NAME]; \ + uint8_t potsWarnEnabled; \ + int8_t potsWarnPosition[NUM_POTS+NUM_SLIDERS]; +#else +#define MODELDATA_EXTRA_217 \ + uint8_t spare:6; \ + uint8_t potsWarnMode:2; \ + ModuleData moduleData[NUM_MODULES+1]; \ + uint8_t potsWarnEnabled; \ + int8_t potsWarnPosition[NUM_POTS+NUM_SLIDERS]; \ + uint8_t rxBattAlarms[2]; +#endif + +#if defined(PCBTARANIS) && LCD_W >= 212 +PACK(typedef struct { + char name[LEN_MODEL_NAME]; + uint8_t modelId; + char bitmap[LEN_BITMAP_NAME]; +}) ModelHeader_v216; +#else +PACK(typedef struct { + char name[LEN_MODEL_NAME]; + uint8_t modelId; +}) ModelHeader_v216; +#endif + +PACK(typedef struct { + ModelHeader_v216 header; + TimerData_v216 timers[2]; + AVR_FIELD(uint8_t protocol:3) + ARM_FIELD(uint8_t telemetryProtocol:3) + uint8_t thrTrim:1; // Enable Throttle Trim + AVR_FIELD(int8_t ppmNCH:4) + ARM_FIELD(int8_t spare2:4) + int8_t trimInc:3; // Trim Increments + uint8_t disableThrottleWarning:1; + ARM_FIELD(uint8_t displayChecklist:1) + AVR_FIELD(uint8_t pulsePol:1) + uint8_t extendedLimits:1; + uint8_t extendedTrims:1; + uint8_t throttleReversed:1; + AVR_FIELD(int8_t ppmDelay) + BeepANACenter beepANACenter; // 1<<0->A1.. 1<<6->A7 + MixData_v216 mixData[MAX_MIXERS]; + LimitData_v216 limitData[MAX_OUTPUT_CHANNELS]; + ExpoData_v216 expoData[MAX_EXPOS]; + + CurveData_v216 curves[MAX_CURVES]; + int8_t points[MAX_CURVE_POINTS]; + + LogicalSwitchData_v216 logicalSw[32]; + CustomFunctionData_v216 customFn[MAX_SPECIAL_FUNCTIONS]; + SwashRingData_v216 swashR; + FlightModeData_v216 flightModeData[MAX_FLIGHT_MODES]; + + uint8_t thrTraceSrc; + + uint16_t switchWarningState; + uint8_t switchWarningEnable; + + GVarData gvars[MAX_GVARS]; + + FrSkyData_v216 frsky; + + MODELDATA_EXTRA_216 + +}) ModelData_v216; + +PACK(typedef struct { + ModelHeader header; + TimerData_v217 timers[MAX_TIMERS]; + ARM_FIELD(uint8_t telemetryProtocol:3) + uint8_t thrTrim:1; // Enable Throttle Trim + ARM_FIELD(uint8_t noGlobalFunctions:1) + ARM_FIELD(uint8_t displayTrims:2) + ARM_FIELD(uint8_t ignoreSensorIds:1) + int8_t trimInc:3; // Trim Increments + uint8_t disableThrottleWarning:1; + ARM_FIELD(uint8_t displayChecklist:1) + uint8_t extendedLimits:1; + uint8_t extendedTrims:1; + uint8_t throttleReversed:1; + BeepANACenter beepANACenter; + MixData_v217 mixData[MAX_MIXERS]; + LimitData limitData[MAX_OUTPUT_CHANNELS]; + ExpoData_v217 expoData[MAX_EXPOS]; + + CurveData_v216 curves[MAX_CURVES]; + int8_t points[MAX_CURVE_POINTS]; + + LogicalSwitchData_v217 logicalSw[32]; + CustomFunctionData_v216 customFn[MAX_SPECIAL_FUNCTIONS]; + SwashRingData swashR; + FlightModeData_v216 flightModeData[MAX_FLIGHT_MODES]; + + uint8_t thrTraceSrc; + + swarnstate_t switchWarningState; + swarnenable_t switchWarningEnable; + + GVarData gvars[MAX_GVARS]; + + FrSkyTelemetryData frsky; + + MODELDATA_EXTRA_217 + + TelemetrySensor telemetrySensors[MAX_TELEMETRY_SENSORS]; + + TARANIS_PCBX9E_FIELD(uint8_t toplcdTimer) +}) ModelData_v217; + +int ConvertTelemetrySource_216_to_217(int source) +{ + // TELEM_TIMER3 added +// if (source >= TELEM_TIMER3) + // source += 1; + + return source; +} + +#if defined(PCBTARANIS) +int ConvertSwitch_216_to_217(int swtch) +{ + if (swtch < 0) + return -ConvertSwitch_216_to_217(-swtch); + + if (swtch > SWSRC_SF0) + swtch += 1; + + if (swtch > SWSRC_SH0) + swtch += 1; + + return swtch; +} +#else +int ConvertSwitch_216_to_217(int swtch) +{ + return swtch; +} +#endif + +int ConvertSwitch_217_to_218(int swtch) +{ + // 32 additional logical switches + + if (swtch < 0) + return -ConvertSwitch_217_to_218(-swtch); + + if (swtch >= SWSRC_FIRST_LOGICAL_SWITCH+32) + return swtch+32; + + return swtch; +} + +int ConvertSource_216_to_217(int source) +{ +#if defined(PCBX9E) + // SI to SR switches added + if (source >= MIXSRC_SI) + source += 10; +#endif + // Telemetry conversions + if (source >= MIXSRC_FIRST_TELEM) + source = 0; + + return source; +} + +int ConvertSource_217_to_218(int source) +{ +#if defined(PCBTARANIS) + if (source >= MIXSRC_FIRST_LOGICAL_SWITCH + 32) + source += 32; +#endif + + return source; +} + +int ConvertGVar_216_to_217(int value) +{ + if (value < -4096 + 9) + value += 4096 - 1024; + else if (value > 4095 - 9) + value -= 4095 - 1023; + return value; +} + +PACK(typedef struct { + uint8_t version; + uint16_t variant; + CalibData calib[NUM_STICKS+NUM_POTS+NUM_SLIDERS]; + uint16_t chkSum; + int8_t currModel; + uint8_t contrast; + uint8_t vBatWarn; + int8_t txVoltageCalibration; + int8_t backlightMode; + TrainerData trainer; + uint8_t view; // index of view in main screen + int8_t buzzerMode:2; // -2=quiet, -1=only alarms, 0=no keys, 1=all + uint8_t fai:1; + int8_t beepMode:2; // -2=quiet, -1=only alarms, 0=no keys, 1=all + uint8_t alarmsFlash:1; + uint8_t disableMemoryWarning:1; + uint8_t disableAlarmWarning:1; + uint8_t stickMode:2; + int8_t timezone:5; + uint8_t adjustRTC:1; + uint8_t inactivityTimer; + uint8_t mavbaud:3; + int8_t splashMode:3; + int8_t hapticMode:2; // -2=quiet, -1=only alarms, 0=no keys, 1=all + int8_t switchesDelay; + uint8_t lightAutoOff; + uint8_t templateSetup; // RETA order for receiver channels + int8_t PPM_Multiplier; + int8_t hapticLength; + uint8_t reNavigation; + N_TARANIS_FIELD(uint8_t stickReverse) + int8_t beepLength:3; + int8_t hapticStrength:3; + uint8_t gpsFormat:1; + uint8_t unexpectedShutdown:1; + uint8_t speakerPitch; + int8_t speakerVolume; + int8_t vBatMin; + int8_t vBatMax; + + uint8_t backlightBright; + int8_t txCurrentCalibration; + int8_t temperatureWarn; + uint8_t mAhWarn; + uint16_t mAhUsed; + uint32_t globalTimer; + int8_t temperatureCalib; + uint8_t btBaudrate; + uint8_t optrexDisplay; + uint8_t sticksGain; + uint8_t rotarySteps; + uint8_t countryCode; + uint8_t imperial; + char ttsLanguage[2]; + int8_t beepVolume; + int8_t wavVolume; + int8_t varioVolume; + int8_t varioPitch; + int8_t varioRange; + int8_t varioRepeat; + int8_t backgroundVolume; + + TARANIS_FIELD(uint8_t serial2Mode:6) + TARANIS_FIELD(uint8_t slidersConfig:2) + TARANIS_FIELD(uint8_t potsConfig) + TARANIS_FIELD(uint8_t backlightColor) + TARANIS_FIELD(swarnstate_t switchUnlockStates) + TARANIS_FIELD(CustomFunctionData_v216 customFn[MAX_SPECIAL_FUNCTIONS]) + TARANIS_FIELD(swconfig_t switchConfig) + TARANIS_FIELD(char switchNames[NUM_SWITCHES][LEN_SWITCH_NAME]) + TARANIS_FIELD(char anaNames[NUM_STICKS+NUM_POTS+NUM_SLIDERS][LEN_ANA_NAME]) + N_TARANIS_FIELD(CustomFunctionData_v216 customFn[MAX_SPECIAL_FUNCTIONS]) + + TARANIS_PCBX9E_FIELD(uint8_t bluetoothEnable) + TARANIS_PCBX9E_FIELD(char bluetoothName[LEN_BLUETOOTH_NAME]) +}) RadioData_v216; + +void ConvertRadioData_216_to_217(RadioData & settings) +{ + RadioData_v216 * settings_v216 = (RadioData_v216 *)&settings; + settings_v216->version = 217; +#if defined(PCBTARANIS) + settings_v216->potsConfig = 0x05; // S1 and S2 = pots with detent + settings_v216->switchConfig = 0x00007bff; // 6x3POS, 1x2POS, 1xTOGGLE +#endif +} + +void ConvertSpecialFunctions_217_to_218(CustomFunctionData * cf218, CustomFunctionData_v216 * cf216) +{ + for (int i=0; i= 212 + memcpy(newModel.header.bitmap, oldModel.header.bitmap, LEN_BITMAP_NAME); +#endif + + for (uint8_t i=0; i<2; i++) { + TimerData_v217 & timer = newModel.timers[i]; + if (oldModel.timers[i].mode >= TMRMODE_COUNT) + timer.mode = TMRMODE_COUNT + ConvertSwitch_216_to_217(oldModel.timers[i].mode - TMRMODE_COUNT + 1) - 1; + else + timer.mode = ConvertSwitch_216_to_217(oldModel.timers[i].mode); + timer.start = oldModel.timers[i].start; + timer.countdownBeep = oldModel.timers[i].countdownBeep; + timer.minuteBeep = oldModel.timers[i].minuteBeep; + timer.persistent = oldModel.timers[i].persistent; + timer.value = oldModel.timers[i].value; + } + newModel.telemetryProtocol = oldModel.telemetryProtocol; + newModel.thrTrim = oldModel.thrTrim; + newModel.trimInc = oldModel.trimInc; + newModel.disableThrottleWarning = oldModel.disableThrottleWarning; + newModel.displayChecklist = oldModel.displayChecklist; + newModel.extendedLimits = oldModel.extendedLimits; + newModel.extendedTrims = oldModel.extendedTrims; + newModel.throttleReversed = oldModel.throttleReversed; + newModel.beepANACenter = oldModel.beepANACenter; + for (int i=0; i> 6; + newModel.potsWarnEnabled = oldModel.nPotsToWarn & 0x1f; + memcpy(newModel.potsWarnPosition, oldModel.potPosition, sizeof(newModel.potsWarnPosition)); +} + +void ConvertModel_217_to_218(ModelData & model) +{ + assert(sizeof(ModelData_v217) <= sizeof(ModelData)); + + ModelData_v217 oldModel; + memcpy(&oldModel, &model, sizeof(oldModel)); + ModelData & newModel = model; + memset(&newModel, 0, sizeof(ModelData)); + + char name[LEN_MODEL_NAME+1]; + zchar2str(name, oldModel.header.name, LEN_MODEL_NAME); + TRACE("Model %s conversion from v217 to v218", name); + + newModel.header = oldModel.header; + for (uint8_t i=0; i= TMRMODE_COUNT) + newModel.timers[i].mode = TMRMODE_COUNT + ConvertSwitch_217_to_218(oldModel.timers[i].mode - TMRMODE_COUNT + 1) - 1; + else + newModel.timers[i].mode = ConvertSwitch_217_to_218(oldModel.timers[i].mode); + if (oldModel.timers[i].mode) + TRACE("timer mode %d => %d", oldModel.timers[i].mode, newModel.timers[i].mode); + newModel.timers[i].start = oldModel.timers[i].start; + newModel.timers[i].value = oldModel.timers[i].value; + newModel.timers[i].countdownBeep = oldModel.timers[i].countdownBeep; + newModel.timers[i].minuteBeep = oldModel.timers[i].minuteBeep; + newModel.timers[i].persistent = oldModel.timers[i].persistent; + memcpy(newModel.timers[i].name, oldModel.timers[i].name, sizeof(newModel.timers[i].name)); + } + newModel.telemetryProtocol = oldModel.telemetryProtocol; + newModel.thrTrim = oldModel.thrTrim; + newModel.noGlobalFunctions = oldModel.noGlobalFunctions; + newModel.displayTrims = oldModel.displayTrims; + newModel.ignoreSensorIds = oldModel.ignoreSensorIds; + newModel.trimInc = oldModel.trimInc; + newModel.disableThrottleWarning = oldModel.disableThrottleWarning; + newModel.displayChecklist = oldModel.displayChecklist; + newModel.extendedLimits = oldModel.extendedLimits; + newModel.extendedTrims = oldModel.extendedTrims; + newModel.throttleReversed = oldModel.throttleReversed; + newModel.beepANACenter = oldModel.beepANACenter; + for (int i=0; i> (2*i)) & 0x03) == TELEMETRY_SCREEN_TYPE_VALUES) { + for (int j = 0; j < 4; j++) { + for (int k = 0; k < NUM_LINE_ITEMS; k++) { + newModel.frsky.screens[i].lines[j].sources[k] = ConvertSource_217_to_218(oldModel.frsky.screens[i].lines[j].sources[k]); + } + } + } + else if (((oldModel.frsky.screensType >> (2*i)) & 0x03) == TELEMETRY_SCREEN_TYPE_GAUGES) { + for (int j = 0; j < 4; j++) { + newModel.frsky.screens[i].bars[j].source = ConvertSource_217_to_218(oldModel.frsky.screens[i].bars[j].source); + } + } + } + for (int i=0; i UNIT_WATTS) + newModel.telemetrySensors[i].unit += 1; + } +#if defined(PCBX9E) + newModel.toplcdTimer = oldModel.toplcdTimer; +#endif +} + +void ConvertModel(int id, int version) +{ + eeLoadModelData(id); + + if (version == 216) { + version = 217; + ConvertModel_216_to_217(g_model); + } + if (version == 217) { + version = 218; + ConvertModel_217_to_218(g_model); + } + + uint8_t currModel = g_eeGeneral.currModel; + g_eeGeneral.currModel = id; + storageDirty(EE_MODEL); + storageCheck(true); + g_eeGeneral.currModel = currModel; +} + +bool eeConvert() +{ + const char *msg = NULL; + + if (g_eeGeneral.version == 216) { + msg = PSTR("EEprom Data v216"); + } + else if (g_eeGeneral.version == 217) { + msg = PSTR("EEprom Data v217"); + } + else { + return false; + } + + int conversionVersionStart = g_eeGeneral.version; + + // Information to the user and wait for key press +#if defined(PCBSKY9X) + g_eeGeneral.optrexDisplay = 0; +#endif + g_eeGeneral.backlightMode = e_backlight_mode_on; + g_eeGeneral.backlightBright = 0; + g_eeGeneral.contrast = 25; + + ALERT(STR_STORAGE_WARNING, msg, AU_BAD_RADIODATA); + + RAISE_ALERT(STR_STORAGE_WARNING, STR_EEPROM_CONVERTING, NULL, AU_NONE); + + // General Settings conversion + eeLoadGeneralSettingsData(); + int version = conversionVersionStart; + if (version == 216) { + version = 217; + ConvertRadioData_216_to_217(g_eeGeneral); + } + if (version == 217) { + version = 218; + ConvertRadioData_217_to_218(g_eeGeneral); + } + storageDirty(EE_GENERAL); + storageCheck(true); + +#if defined(COLORLCD) +#elif LCD_W >= 212 + lcdDrawRect(60, 6*FH+4, 132, 3); +#else + lcdDrawRect(10, 6*FH+4, 102, 3); +#endif + + // Models conversion + for (uint8_t id=0; id= 212 + lcdDrawSolidHorizontalLine(61, 6*FH+5, 10+id*2, FORCE); +#else + lcdDrawSolidHorizontalLine(11, 6*FH+5, 10+(id*3)/2, FORCE); +#endif + lcdRefresh(); + if (eeModelExists(id)) { + ConvertModel(id, conversionVersionStart); + } + + } + + return true; +} diff --git a/radio/src/syscalls.c b/radio/src/syscalls.c index f38ba2ff8..b80ae58e9 100644 --- a/radio/src/syscalls.c +++ b/radio/src/syscalls.c @@ -1,116 +1,116 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "debug.h" - -#undef errno -extern int errno; -extern int _end; -extern int _heap_end; - -unsigned char * heap = (unsigned char *)&_end; - -extern caddr_t _sbrk(int nbytes) -{ - if (heap + nbytes < (unsigned char *)&_heap_end) { - unsigned char * prev_heap = heap; - heap += nbytes; - return (caddr_t)prev_heap; - } - else { - errno = ENOMEM; - return ((void *)-1); - } -} - -#if !defined(SEMIHOSTING) -extern int _gettimeofday(void *p1, void *p2) -{ - return 0; -} - -extern int _link(char *old, char *nw) -{ - return -1; -} - -extern int _unlink(const char *path) -{ - return -1; -} - -extern int _open(const char *name, int flags, int mode) -{ - return -1; -} - -extern int _close(int file) -{ - return -1; -} - -extern int _fstat(int file, struct stat * st) -{ - st->st_mode = S_IFCHR ; - return 0; -} - -extern int _isatty(int file) -{ - return 1; -} - -extern int _lseek(int file, int ptr, int dir) -{ - return 0; -} - -extern int _read(int file, char *ptr, int len) -{ - return 0; -} - -extern int _write(int file, char *ptr, int len) -{ - return 0; -} - -extern void _exit(int status) -{ - TRACE("_exit(%d)", status); - for (;;); -} - -extern void _kill(int pid, int sig) -{ - return ; -} - -extern int _getpid() -{ - return -1 ; -} -#endif - +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "debug.h" + +#undef errno +extern int errno; +extern int _end; +extern int _heap_end; + +unsigned char * heap = (unsigned char *)&_end; + +extern caddr_t _sbrk(int nbytes) +{ + if (heap + nbytes < (unsigned char *)&_heap_end) { + unsigned char * prev_heap = heap; + heap += nbytes; + return (caddr_t)prev_heap; + } + else { + errno = ENOMEM; + return ((void *)-1); + } +} + +#if !defined(SEMIHOSTING) +extern int _gettimeofday(void *p1, void *p2) +{ + return 0; +} + +extern int _link(char *old, char *nw) +{ + return -1; +} + +extern int _unlink(const char *path) +{ + return -1; +} + +extern int _open(const char *name, int flags, int mode) +{ + return -1; +} + +extern int _close(int file) +{ + return -1; +} + +extern int _fstat(int file, struct stat * st) +{ + st->st_mode = S_IFCHR ; + return 0; +} + +extern int _isatty(int file) +{ + return 1; +} + +extern int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +extern int _read(int file, char *ptr, int len) +{ + return 0; +} + +extern int _write(int file, char *ptr, int len) +{ + return 0; +} + +extern void _exit(int status) +{ + TRACE("_exit(%d)", status); + for (;;); +} + +extern void _kill(int pid, int sig) +{ + return ; +} + +extern int _getpid() +{ + return -1 ; +} +#endif + diff --git a/radio/src/targets/9x/board.cpp b/radio/src/targets/9x/board.cpp index 385a60024..7cb8fa1b9 100644 --- a/radio/src/targets/9x/board.cpp +++ b/radio/src/targets/9x/board.cpp @@ -1,364 +1,364 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#if defined(ROTARY_ENCODER_NAVIGATION) - -#if defined(TELEMETREZ) -uint8_t TrotCount; // TeZ version -uint8_t LastTrotCount; // TeZ version -uint8_t RotEncoder; -#else -uint8_t RotPosition; -int8_t LastRotaryValue; -int8_t Rotary_diff; -int8_t RotaryControl; -uint8_t RotEncoder; -#endif - -void rotencPoll() -{ -#if defined(TELEMETREZ) - if (TrotCount != LastTrotCount) { - rotencValue[0] = LastTrotCount = TrotCount; - } -#else - // Rotary Encoder polling - PORTA = 0; // No pullups - DDRA = 0x1F; // Top 3 bits input - - asm(" rjmp 1f"); - asm("1:"); - - uint8_t rotary; - rotary = PINA; - DDRA = 0xFF; // Back to all outputs - rotary &= 0xE0; - - RotEncoder = rotary; // just read the lcd pin - - rotary &= 0xDF; - if ( rotary != RotPosition ) { - uint8_t x; - x = RotPosition & 0x40; - x <<= 1; - x ^= rotary & 0x80; - if ( x ) { - rotencValue[0] -= 1; - } - else { - rotencValue[0] += 1; - } - RotPosition = rotary; - } -#endif // TELEMETREZ -} -#else -#define ROTENC_DOWN() (0) -#endif // ROTARY_ENCODER_NAVIGATION - -void boardInit() -{ -#if !defined(SIMU) - // Set up I/O port data directions and initial states - DDRA = 0xff; PORTA = 0x00; // LCD data - DDRB = 0x81; PORTB = 0x7e; //pullups keys+nc -#if defined(TELEMETRY_MOD_14051) || defined(TELEMETRY_MOD_14051_SWAPPED) - DDRC = 0xff; PORTC = 0x00; -#else - DDRC = 0x3e; PORTC = 0xc1; //pullups nc -#endif - DDRD = 0x00; PORTD = 0xff; //pullups keys - DDRE = (1<= (s_anaFilt[TX_VOLTAGE] / 2)) ? 1 : 0; - break; - } - - // set the mux number for the next ADC convert, - // stabilize voltage before ADC read. - muxNum = nextMuxNum; - PORTC &= ~((1 << PC7) | (1 << PC6) | (1 << PC0)); - if(muxNum & 1) PORTC |= (1 << PC7); // Mux CTRL A - if(muxNum & 2) PORTC |= (1 << PC6); // Mux CTRL B - if(muxNum & 4) PORTC |= (1 << PC0); // Mux CTRL C -} -#endif - -#if !defined(SIMU) && (defined(TELEMETRY_MOD_14051) || defined(TELEMETRY_MOD_14051_SWAPPED)) - #define THR_STATE() pf7_digital[PF7_THR] - #define AIL_STATE() pf7_digital[PF7_AIL] -#elif defined(TELEMETRY_JETI) || defined(TELEMETRY_FRSKY) || defined(TELEMETRY_ARDUPILOT) || defined(TELEMETRY_NMEA) || defined(TELEMETRY_MAVLINK) - #define THR_STATE() (PINC & (1< only phone jack = slave mode - static bool lastSlaveMode = false; - static uint8_t checkDelay = 0; - if (IS_AUDIO_BUSY()) { - checkDelay = 20; - } - else if (checkDelay) { - --checkDelay; - } - else { - lastSlaveMode = (PING & (1< bl_current) - OCR0A = pgm_read_byte(&pwmtable[++bl_current]); - else - OCR0A = pgm_read_byte(&pwmtable[--bl_current]); -#else - if (bl_target > bl_current) - OCR2 = pgm_read_byte(&pwmtable[++bl_current]); - else - OCR2 = pgm_read_byte(&pwmtable[--bl_current]); -#endif - } -} - -#endif +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#if defined(ROTARY_ENCODER_NAVIGATION) + +#if defined(TELEMETREZ) +uint8_t TrotCount; // TeZ version +uint8_t LastTrotCount; // TeZ version +uint8_t RotEncoder; +#else +uint8_t RotPosition; +int8_t LastRotaryValue; +int8_t Rotary_diff; +int8_t RotaryControl; +uint8_t RotEncoder; +#endif + +void rotencPoll() +{ +#if defined(TELEMETREZ) + if (TrotCount != LastTrotCount) { + rotencValue[0] = LastTrotCount = TrotCount; + } +#else + // Rotary Encoder polling + PORTA = 0; // No pullups + DDRA = 0x1F; // Top 3 bits input + + asm(" rjmp 1f"); + asm("1:"); + + uint8_t rotary; + rotary = PINA; + DDRA = 0xFF; // Back to all outputs + rotary &= 0xE0; + + RotEncoder = rotary; // just read the lcd pin + + rotary &= 0xDF; + if ( rotary != RotPosition ) { + uint8_t x; + x = RotPosition & 0x40; + x <<= 1; + x ^= rotary & 0x80; + if ( x ) { + rotencValue[0] -= 1; + } + else { + rotencValue[0] += 1; + } + RotPosition = rotary; + } +#endif // TELEMETREZ +} +#else +#define ROTENC_DOWN() (0) +#endif // ROTARY_ENCODER_NAVIGATION + +void boardInit() +{ +#if !defined(SIMU) + // Set up I/O port data directions and initial states + DDRA = 0xff; PORTA = 0x00; // LCD data + DDRB = 0x81; PORTB = 0x7e; //pullups keys+nc +#if defined(TELEMETRY_MOD_14051) || defined(TELEMETRY_MOD_14051_SWAPPED) + DDRC = 0xff; PORTC = 0x00; +#else + DDRC = 0x3e; PORTC = 0xc1; //pullups nc +#endif + DDRD = 0x00; PORTD = 0xff; //pullups keys + DDRE = (1<= (s_anaFilt[TX_VOLTAGE] / 2)) ? 1 : 0; + break; + } + + // set the mux number for the next ADC convert, + // stabilize voltage before ADC read. + muxNum = nextMuxNum; + PORTC &= ~((1 << PC7) | (1 << PC6) | (1 << PC0)); + if(muxNum & 1) PORTC |= (1 << PC7); // Mux CTRL A + if(muxNum & 2) PORTC |= (1 << PC6); // Mux CTRL B + if(muxNum & 4) PORTC |= (1 << PC0); // Mux CTRL C +} +#endif + +#if !defined(SIMU) && (defined(TELEMETRY_MOD_14051) || defined(TELEMETRY_MOD_14051_SWAPPED)) + #define THR_STATE() pf7_digital[PF7_THR] + #define AIL_STATE() pf7_digital[PF7_AIL] +#elif defined(TELEMETRY_JETI) || defined(TELEMETRY_FRSKY) || defined(TELEMETRY_ARDUPILOT) || defined(TELEMETRY_NMEA) || defined(TELEMETRY_MAVLINK) + #define THR_STATE() (PINC & (1< only phone jack = slave mode + static bool lastSlaveMode = false; + static uint8_t checkDelay = 0; + if (IS_AUDIO_BUSY()) { + checkDelay = 20; + } + else if (checkDelay) { + --checkDelay; + } + else { + lastSlaveMode = (PING & (1< bl_current) + OCR0A = pgm_read_byte(&pwmtable[++bl_current]); + else + OCR0A = pgm_read_byte(&pwmtable[--bl_current]); +#else + if (bl_target > bl_current) + OCR2 = pgm_read_byte(&pwmtable[++bl_current]); + else + OCR2 = pgm_read_byte(&pwmtable[--bl_current]); +#endif + } +} + +#endif diff --git a/radio/src/targets/9x/board.h b/radio/src/targets/9x/board.h index b2c5683b2..67ed58a4b 100644 --- a/radio/src/targets/9x/board.h +++ b/radio/src/targets/9x/board.h @@ -1,260 +1,260 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BOARD_STOCK_H_ -#define _BOARD_STOCK_H_ - -#include "../common/avr/board_avr.h" - -// -// elev thr -// LV RV -// 2 ^ 4 ^ -// 1 2 -// | rudd | aile -// <----X--3-> LH <----X--0-> RH -// 6 | 7 1 | 0 -// | | -// 3 v 5 v -// -//PORTA 7 6 5 4 3 2 1 0 -// O O O O O O O O -// ------------------------ LCD_DAT ----------------------- -// -//PORTB 7 6 5 4 3 2 1 0 -// O i i i i i i O -// light KEY_LFT KEY_RGT KEY_UP KEY_DWN KEY_EXT KEY_MEN PPM -// -//PORTC 7 6 5 4 3 2 1 0 -// - - O O O O O - -// NC NC LCD_E LCD_RNW LCD_A0 LCD_RES LCD_CS1 NC -// -//PORTD 7 6 5 4 3 2 1 0 -// i i i i i i i i -// TRM_D_DWN _UP TRM_C_DWN _UP TRM_B_DWN _UP TRM_A_DWN _UP -// -//PORTE 7 6 5 4 3 2 1 0 -// i i i i O i i i -// PPM_IN ID2 Trainer Gear Buzzer ElevDR AileDR THRCT -// -//PORTF 7 6 5 4 3 2 1 0 -// ai ai ai ai ai ai ai ai -// ANA_ BAT PITT_TRM HOV_THR HOV_PIT STCK_LH STCK_RV STCK_LV STCK_RH -// rud thro elev aile -//PORTG 7 6 5 4 3 2 1 0 -// - - - O i i i -// SIM_CTL ID1 Haptic RF_POW RuddDR - -// Board driver -void boardInit(void); -#define boardOff() pwrOff() - -// Keys -#define KEYS_GPIO_REG_MENU pinb -#define KEYS_GPIO_PIN_MENU (1<<1) -#define KEYS_GPIO_REG_EXIT pinb -#define KEYS_GPIO_PIN_EXIT (1<<2) -#define KEYS_GPIO_REG_RIGHT pinb -#define KEYS_GPIO_PIN_RIGHT (1<<5) -#define KEYS_GPIO_REG_LEFT pinb -#define KEYS_GPIO_PIN_LEFT (1<<6) -#define KEYS_GPIO_REG_UP pinb -#define KEYS_GPIO_PIN_UP (1<<4) -#define KEYS_GPIO_REG_DOWN pinb -#define KEYS_GPIO_PIN_DOWN (1<<3) - -// Trims -#define TRIMS_GPIO_REG_LHL pind -#define TRIMS_GPIO_PIN_LHL (1<<6) -#define TRIMS_GPIO_REG_LVD pind -#define TRIMS_GPIO_PIN_LVD (1<<3) -#define TRIMS_GPIO_REG_RVU pind -#define TRIMS_GPIO_PIN_RVU (1<<4) -#define TRIMS_GPIO_REG_RHL pind -#define TRIMS_GPIO_PIN_RHL (1<<1) -#define TRIMS_GPIO_REG_LHR pind -#define TRIMS_GPIO_PIN_LHR (1<<7) -#define TRIMS_GPIO_REG_LVU pind -#define TRIMS_GPIO_PIN_LVU (1<<2) -#define TRIMS_GPIO_REG_RVD pind -#define TRIMS_GPIO_PIN_RVD (1<<5) -#define TRIMS_GPIO_REG_RHR pind -#define TRIMS_GPIO_PIN_RHR (1<<0) - -#if defined(CPUM2561) - #define TIMER_16KHZ_VECT TIMER2_OVF_vect - #define COUNTER_16KHZ TCNT2 - #define TIMER_10MS_VECT TIMER2_COMPA_vect - #define TIMER_10MS_COMPVAL OCR2A - #define PAUSE_10MS_INTERRUPT() TIMSK2 &= ~(1< LH <----X--0-> RH +// 6 | 7 1 | 0 +// | | +// 3 v 5 v +// +//PORTA 7 6 5 4 3 2 1 0 +// O O O O O O O O +// ------------------------ LCD_DAT ----------------------- +// +//PORTB 7 6 5 4 3 2 1 0 +// O i i i i i i O +// light KEY_LFT KEY_RGT KEY_UP KEY_DWN KEY_EXT KEY_MEN PPM +// +//PORTC 7 6 5 4 3 2 1 0 +// - - O O O O O - +// NC NC LCD_E LCD_RNW LCD_A0 LCD_RES LCD_CS1 NC +// +//PORTD 7 6 5 4 3 2 1 0 +// i i i i i i i i +// TRM_D_DWN _UP TRM_C_DWN _UP TRM_B_DWN _UP TRM_A_DWN _UP +// +//PORTE 7 6 5 4 3 2 1 0 +// i i i i O i i i +// PPM_IN ID2 Trainer Gear Buzzer ElevDR AileDR THRCT +// +//PORTF 7 6 5 4 3 2 1 0 +// ai ai ai ai ai ai ai ai +// ANA_ BAT PITT_TRM HOV_THR HOV_PIT STCK_LH STCK_RV STCK_LV STCK_RH +// rud thro elev aile +//PORTG 7 6 5 4 3 2 1 0 +// - - - O i i i +// SIM_CTL ID1 Haptic RF_POW RuddDR + +// Board driver +void boardInit(void); +#define boardOff() pwrOff() + +// Keys +#define KEYS_GPIO_REG_MENU pinb +#define KEYS_GPIO_PIN_MENU (1<<1) +#define KEYS_GPIO_REG_EXIT pinb +#define KEYS_GPIO_PIN_EXIT (1<<2) +#define KEYS_GPIO_REG_RIGHT pinb +#define KEYS_GPIO_PIN_RIGHT (1<<5) +#define KEYS_GPIO_REG_LEFT pinb +#define KEYS_GPIO_PIN_LEFT (1<<6) +#define KEYS_GPIO_REG_UP pinb +#define KEYS_GPIO_PIN_UP (1<<4) +#define KEYS_GPIO_REG_DOWN pinb +#define KEYS_GPIO_PIN_DOWN (1<<3) + +// Trims +#define TRIMS_GPIO_REG_LHL pind +#define TRIMS_GPIO_PIN_LHL (1<<6) +#define TRIMS_GPIO_REG_LVD pind +#define TRIMS_GPIO_PIN_LVD (1<<3) +#define TRIMS_GPIO_REG_RVU pind +#define TRIMS_GPIO_PIN_RVU (1<<4) +#define TRIMS_GPIO_REG_RHL pind +#define TRIMS_GPIO_PIN_RHL (1<<1) +#define TRIMS_GPIO_REG_LHR pind +#define TRIMS_GPIO_PIN_LHR (1<<7) +#define TRIMS_GPIO_REG_LVU pind +#define TRIMS_GPIO_PIN_LVU (1<<2) +#define TRIMS_GPIO_REG_RVD pind +#define TRIMS_GPIO_PIN_RVD (1<<5) +#define TRIMS_GPIO_REG_RHR pind +#define TRIMS_GPIO_PIN_RHR (1<<0) + +#if defined(CPUM2561) + #define TIMER_16KHZ_VECT TIMER2_OVF_vect + #define COUNTER_16KHZ TCNT2 + #define TIMER_10MS_VECT TIMER2_COMPA_vect + #define TIMER_10MS_COMPVAL OCR2A + #define PAUSE_10MS_INTERRUPT() TIMSK2 &= ~(1<SEG1) - 0xA6, //REV = 0: non-reverse display - 0xA4, //EON = 0: normal display. non-entire - 0xA2, //Select LCD bias - 0xC8, //SHL = 1: reverse direction (COM64->COM1) - 0x2F, //Control power circuit operation VC=VR=VF=1 - 0x25, //Select int resistance ratio R2 R1 R0 =5 - 0x81, //Set reference voltage Mode - 0x22, //24 SV5 SV4 SV3 SV2 SV1 SV0 = 0x18 - 0xAF, //DON = 1: display ON - 0x60 //Set the display start line to zero -#elif defined(LCD_ERC12864FSF) - 0xE2, //Initialize the internal functions - 0xAE, //DON = 0: display OFF - 0xA1, //ADC = 1: reverse direction (SEG132->SEG1) - 0xA6, //REV = 0: non-reverse display - 0xA4, //EON = 0: normal display. non-entire - 0xA3, //Select LCD bias - 0xC0, //SHL = 0: normal direction (COM1->COM64) - 0x2F, //Control power circuit operation VC=VR=VF=1 - 0x27, //Select int resistance ratio R2 R1 R0 - 0x81, //Set reference voltage Mode - 0x2D, //24 SV5 SV4 SV3 SV2 SV1 SV0 - 0xAF //DON = 1: display ON -#else //ST7565P (default 9x LCD) - 0xE2, //Initialize the internal functions - 0xAE, //DON = 0: display OFF - 0xA1, //ADC = 1: reverse direction(SEG132->SEG1) - 0xA6, //REV = 0: non-reverse display - 0xA4, //EON = 0: normal display. non-entire - 0xA2, //Select LCD bias=0 - 0xC0, //SHL = 0: normal direction (COM1->COM64) - 0x2F, //Control power circuit operation VC=VR=VF=1 - 0x25, //Select int resistance ratio R2 R1 R0 =5 - 0x81, //Set reference voltage Mode - 0x22, //24 SV5 SV4 SV3 SV2 SV1 SV0 = 0x18 - 0xAF //DON = 1: display ON -#endif -}; - -void lcdInit() -{ - LCD_LOCK(); - PORTC_LCD_CTRL &= ~(1<0; --x) { - PORTA_LCD_DAT = *p++; - PORTC_LCD_CTRL |= (1<SEG1) + 0xA6, //REV = 0: non-reverse display + 0xA4, //EON = 0: normal display. non-entire + 0xA2, //Select LCD bias + 0xC8, //SHL = 1: reverse direction (COM64->COM1) + 0x2F, //Control power circuit operation VC=VR=VF=1 + 0x25, //Select int resistance ratio R2 R1 R0 =5 + 0x81, //Set reference voltage Mode + 0x22, //24 SV5 SV4 SV3 SV2 SV1 SV0 = 0x18 + 0xAF, //DON = 1: display ON + 0x60 //Set the display start line to zero +#elif defined(LCD_ERC12864FSF) + 0xE2, //Initialize the internal functions + 0xAE, //DON = 0: display OFF + 0xA1, //ADC = 1: reverse direction (SEG132->SEG1) + 0xA6, //REV = 0: non-reverse display + 0xA4, //EON = 0: normal display. non-entire + 0xA3, //Select LCD bias + 0xC0, //SHL = 0: normal direction (COM1->COM64) + 0x2F, //Control power circuit operation VC=VR=VF=1 + 0x27, //Select int resistance ratio R2 R1 R0 + 0x81, //Set reference voltage Mode + 0x2D, //24 SV5 SV4 SV3 SV2 SV1 SV0 + 0xAF //DON = 1: display ON +#else //ST7565P (default 9x LCD) + 0xE2, //Initialize the internal functions + 0xAE, //DON = 0: display OFF + 0xA1, //ADC = 1: reverse direction(SEG132->SEG1) + 0xA6, //REV = 0: non-reverse display + 0xA4, //EON = 0: normal display. non-entire + 0xA2, //Select LCD bias=0 + 0xC0, //SHL = 0: normal direction (COM1->COM64) + 0x2F, //Control power circuit operation VC=VR=VF=1 + 0x25, //Select int resistance ratio R2 R1 R0 =5 + 0x81, //Set reference voltage Mode + 0x22, //24 SV5 SV4 SV3 SV2 SV1 SV0 = 0x18 + 0xAF //DON = 1: display ON +#endif +}; + +void lcdInit() +{ + LCD_LOCK(); + PORTC_LCD_CTRL &= ~(1<0; --x) { + PORTA_LCD_DAT = *p++; + PORTC_LCD_CTRL |= (1<0; --x) { - PORTA_LCD_DAT = *p++; - lcdPulseEnable(); - } - p += 64; - } - A0_off; -} - -void lcdRefresh() -{ - lcdRefreshSide(); - lcdRefreshSide(); -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DISPLAY_SET_COLUMN 0x40 +#define DISPLAY_SET_PAGE 0xB8 +#define DISPLAY_SET_START 0XC0 +#define DISPLAY_ON_CMD 0x3F +#define CS1_on PORTC_LCD_CTRL |= (1<0; --x) { + PORTA_LCD_DAT = *p++; + lcdPulseEnable(); + } + p += 64; + } + A0_off; +} + +void lcdRefresh() +{ + lcdRefreshSide(); + lcdRefreshSide(); +} diff --git a/radio/src/targets/9x/lcd_st7920_driver.cpp b/radio/src/targets/9x/lcd_st7920_driver.cpp index 7cd02044a..f0acf748e 100644 --- a/radio/src/targets/9x/lcd_st7920_driver.cpp +++ b/radio/src/targets/9x/lcd_st7920_driver.cpp @@ -1,137 +1,137 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -void lcdSendCtl(uint8_t val) -{ - PORTC_LCD_CTRL &= ~(1< 31) { - y_addr = y - 32; //Because there are only 31 addressable lines in the ST7920 - x_addr += 8; //so we overflow x (7 visible bytes per line) to reach the bottom half - } - else { - y_addr = y; - } - lcdSendCtl( 0x80 | y_addr ); //Set Vertical Address - _delay_us(49); - lcdSendCtl( 0x80 | x_addr ); //Set Horizontal Address - _delay_us(49); - PORTC_LCD_CTRL |= (1< 0=0, 1=1..7=7, 8=0, 9=1... - col_offset = 1 << bit_count; //Build a value for a AND operation with the vorrect bitposition - line_offset = ( y / 8 ) * 128; //On the ST7565 there are 8 lines with each 128 bytes width - for (coord_t x=0; x<16; x++) { //Walk through 16 bytes form left to right (128 Pixel) - p = displayBuf + line_offset + ( x * 8 ); //Calculate the position of the first byte im array - // adressing the bytes sequential and set the bits at the correct position merging them with an OR operation to get all bits in one byte - // the position of the LSB is the right-most position of the byte to the ST7920 - result = ((*p++ & col_offset)!=0?0x80:0); - result |= ((*p++ & col_offset)!=0?0x40:0); - result |= ((*p++ & col_offset)!=0?0x20:0); - result |= ((*p++ & col_offset)!=0?0x10:0); - result |= ((*p++ & col_offset)!=0?0x08:0); - result |= ((*p++ & col_offset)!=0?0x04:0); - result |= ((*p++ & col_offset) !=0?0x02:0); - result |= ((*p++ & col_offset)!=0?0x01:0); - PORTA_LCD_DAT = result; - PORTC_LCD_CTRL |= (1< 31) { + y_addr = y - 32; //Because there are only 31 addressable lines in the ST7920 + x_addr += 8; //so we overflow x (7 visible bytes per line) to reach the bottom half + } + else { + y_addr = y; + } + lcdSendCtl( 0x80 | y_addr ); //Set Vertical Address + _delay_us(49); + lcdSendCtl( 0x80 | x_addr ); //Set Horizontal Address + _delay_us(49); + PORTC_LCD_CTRL |= (1< 0=0, 1=1..7=7, 8=0, 9=1... + col_offset = 1 << bit_count; //Build a value for a AND operation with the vorrect bitposition + line_offset = ( y / 8 ) * 128; //On the ST7565 there are 8 lines with each 128 bytes width + for (coord_t x=0; x<16; x++) { //Walk through 16 bytes form left to right (128 Pixel) + p = displayBuf + line_offset + ( x * 8 ); //Calculate the position of the first byte im array + // adressing the bytes sequential and set the bits at the correct position merging them with an OR operation to get all bits in one byte + // the position of the LSB is the right-most position of the byte to the ST7920 + result = ((*p++ & col_offset)!=0?0x80:0); + result |= ((*p++ & col_offset)!=0?0x40:0); + result |= ((*p++ & col_offset)!=0?0x20:0); + result |= ((*p++ & col_offset)!=0?0x10:0); + result |= ((*p++ & col_offset)!=0?0x08:0); + result |= ((*p++ & col_offset)!=0?0x04:0); + result |= ((*p++ & col_offset) !=0?0x02:0); + result |= ((*p++ & col_offset)!=0?0x01:0); + PORTA_LCD_DAT = result; + PORTC_LCD_CTRL |= (1<VoiceQueueCount < VOICE_Q_LENGTH) { - vptr->VoiceQueue[vptr->VoiceQueueInIndex++] = value; - vptr->VoiceQueueInIndex &= (VOICE_Q_LENGTH - 1); - vptr->VoiceQueueCount += 1; - } -} - -void pushCustomPrompt(uint8_t value) -{ - pushPrompt(PROMPT_CUSTOM_BASE + value); -} - -void pushNumberPrompt(uint8_t value) -{ - pushPrompt(PROMPT_I18N_BASE + value); -} - -struct t_voice *voiceaddress() -{ - return &Voice ; -} - -void t_voice::voice_process(void) -{ - if (Backlight) - VoiceLatch |= BACKLIGHT_BIT; - else - VoiceLatch &= ~BACKLIGHT_BIT; - - if (VoiceState == V_IDLE) { - PORTB |= (1 << OUT_B_LIGHT); // Latch clock high - if (VoiceQueueCount) { - VoiceSerial = VoiceQueue[VoiceQueueOutIndex++]; - VoiceQueueOutIndex &= (VOICE_Q_LENGTH - 1); - VoiceQueueCount -= 1; - VoiceTimer = 17; - if (VoiceSerial & 0x8000) { // Looking for sound volume 1F0-1F7 - VoiceTimer = 40; - } - VoiceLatch &= ~VOICE_CLOCK_BIT & ~VOICE_DATA_BIT ; - if (VoiceSerial & 0x8000) { - VoiceLatch |= VOICE_DATA_BIT; - } - PORTA_LCD_DAT = VoiceLatch ; // Latch data set - PORTB &= ~(1< 60) { // Give module 1.4 secs to initialise - VoiceState = V_WAIT_START_BUSY_OFF ; - } - PORTB &= ~(1<VoiceQueueCount < VOICE_Q_LENGTH) { + vptr->VoiceQueue[vptr->VoiceQueueInIndex++] = value; + vptr->VoiceQueueInIndex &= (VOICE_Q_LENGTH - 1); + vptr->VoiceQueueCount += 1; + } +} + +void pushCustomPrompt(uint8_t value) +{ + pushPrompt(PROMPT_CUSTOM_BASE + value); +} + +void pushNumberPrompt(uint8_t value) +{ + pushPrompt(PROMPT_I18N_BASE + value); +} + +struct t_voice *voiceaddress() +{ + return &Voice ; +} + +void t_voice::voice_process(void) +{ + if (Backlight) + VoiceLatch |= BACKLIGHT_BIT; + else + VoiceLatch &= ~BACKLIGHT_BIT; + + if (VoiceState == V_IDLE) { + PORTB |= (1 << OUT_B_LIGHT); // Latch clock high + if (VoiceQueueCount) { + VoiceSerial = VoiceQueue[VoiceQueueOutIndex++]; + VoiceQueueOutIndex &= (VOICE_Q_LENGTH - 1); + VoiceQueueCount -= 1; + VoiceTimer = 17; + if (VoiceSerial & 0x8000) { // Looking for sound volume 1F0-1F7 + VoiceTimer = 40; + } + VoiceLatch &= ~VOICE_CLOCK_BIT & ~VOICE_DATA_BIT ; + if (VoiceSerial & 0x8000) { + VoiceLatch |= VOICE_DATA_BIT; + } + PORTA_LCD_DAT = VoiceLatch ; // Latch data set + PORTB &= ~(1< 60) { // Give module 1.4 secs to initialise + VoiceState = V_WAIT_START_BUSY_OFF ; + } + PORTB &= ~(1<VoiceState == V_CLOCKING ) { \ - if ( vptr->VoiceTimer ) { \ - vptr->VoiceTimer -= 1; \ - } \ - else { \ - PORTB |= (1<VoiceCounter & 1) == 0) { \ - vptr->VoiceLatch &= ~VOICE_DATA_BIT; \ - if ( vptr->VoiceSerial & 0x4000 ) { \ - vptr->VoiceLatch |= VOICE_DATA_BIT; \ - } \ - vptr->VoiceSerial <<= 1; \ - } \ - vptr->VoiceLatch ^= VOICE_CLOCK_BIT; \ - PORTA_LCD_DAT = vptr->VoiceLatch; /* Latch data set */ \ - PORTB &= ~(1<VoiceCounter == 0 ) { \ - vptr->VoiceState = V_WAIT_BUSY_ON; \ - vptr->VoiceTimer = 5; /* 50 mS */ \ - } \ - } \ - } \ - } - -#define I18N_PLAY_FUNCTION(lng, x, ...) void x(__VA_ARGS__) -#define PLAY_FUNCTION(x, ...) void x(__VA_ARGS__) -#define PUSH_CUSTOM_PROMPT(p, ...) pushCustomPrompt((p)) -#define PUSH_NUMBER_PROMPT(p) pushNumberPrompt((p)) -#define PUSH_SYSTEM_PROMPT(p) pushNumberPrompt(PROMPT_SYSTEM_BASE-PROMPT_I18N_BASE+(p)) -#define PLAY_NUMBER(n, u, a) playNumber((n), (u), (a)) -#define PLAY_DURATION(d, att) playDuration((d)) -#define PLAY_DURATION_ATT -#define PLAY_TIME -#define IS_PLAY_TIME() (0) -#define IS_PLAYING(id) (0) /* isPlaying() */ -#define PLAY_VALUE(v, id) playValue((v)) +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Bits in VoiceLatch +#define VOICE_CLOCK_BIT 0x01 +#define VOICE_DATA_BIT 0x02 +#define BACKLIGHT_BIT 0x04 +#define SPARE_BIT 0x08 + +#if defined(CPUM64) + #define VOICE_Q_LENGTH 8 +#else + #define VOICE_Q_LENGTH 16 +#endif + +// Voice states +#define V_STARTUP 0 +#define V_IDLE 1 +#define V_CLOCKING 2 +#define V_WAIT_BUSY_ON 3 +#define V_WAIT_BUSY_OFF 4 +#define V_WAIT_BUSY_DELAY 5 +#define V_WAIT_START_BUSY_OFF 6 + +#define PROMPT_CUSTOM_BASE 0 +#define PROMPT_I18N_BASE 256 +#define PROMPT_SYSTEM_BASE 480 + +struct t_voice +{ + uint16_t VoiceQueue[VOICE_Q_LENGTH] ; + uint8_t Backlight ; + uint8_t VoiceLatch ; + uint8_t VoiceCounter ; + uint8_t VoiceTimer ; + uint16_t VoiceSerial ; + uint8_t VoiceState ; + uint8_t VoiceQueueCount ; + uint8_t VoiceQueueInIndex ; + uint8_t VoiceQueueOutIndex ; + + void voice_process( void ) ; +}; + +extern void pushPrompt(uint16_t value); +extern void pushCustomPrompt(uint8_t value); +extern void pushNumberPrompt(uint8_t value); + +extern struct t_voice *voiceaddress( void ) ; +extern struct t_voice Voice ; + +#define VOLUME_LEVEL_MAX 7 +#define VOLUME_LEVEL_DEF 7 +#define setScaledVolume(v) pushPrompt((v) | 0xFFF0) + +inline bool isPlaying() +{ +#if defined(SIMU) + return false; +#else + return Voice.VoiceState != V_IDLE; +#endif +} + +/* + * Handle the Voice output + * Check for LcdLocked (in interrupt), and voice_enabled + */ +#define VOICE_DRIVER() \ + if ( LcdLock == 0 ) { /* LCD not in use */ \ + struct t_voice *vptr; \ + vptr = voiceaddress(); \ + if ( vptr->VoiceState == V_CLOCKING ) { \ + if ( vptr->VoiceTimer ) { \ + vptr->VoiceTimer -= 1; \ + } \ + else { \ + PORTB |= (1<VoiceCounter & 1) == 0) { \ + vptr->VoiceLatch &= ~VOICE_DATA_BIT; \ + if ( vptr->VoiceSerial & 0x4000 ) { \ + vptr->VoiceLatch |= VOICE_DATA_BIT; \ + } \ + vptr->VoiceSerial <<= 1; \ + } \ + vptr->VoiceLatch ^= VOICE_CLOCK_BIT; \ + PORTA_LCD_DAT = vptr->VoiceLatch; /* Latch data set */ \ + PORTB &= ~(1<VoiceCounter == 0 ) { \ + vptr->VoiceState = V_WAIT_BUSY_ON; \ + vptr->VoiceTimer = 5; /* 50 mS */ \ + } \ + } \ + } \ + } + +#define I18N_PLAY_FUNCTION(lng, x, ...) void x(__VA_ARGS__) +#define PLAY_FUNCTION(x, ...) void x(__VA_ARGS__) +#define PUSH_CUSTOM_PROMPT(p, ...) pushCustomPrompt((p)) +#define PUSH_NUMBER_PROMPT(p) pushNumberPrompt((p)) +#define PUSH_SYSTEM_PROMPT(p) pushNumberPrompt(PROMPT_SYSTEM_BASE-PROMPT_I18N_BASE+(p)) +#define PLAY_NUMBER(n, u, a) playNumber((n), (u), (a)) +#define PLAY_DURATION(d, att) playDuration((d)) +#define PLAY_DURATION_ATT +#define PLAY_TIME +#define IS_PLAY_TIME() (0) +#define IS_PLAYING(id) (0) /* isPlaying() */ +#define PLAY_VALUE(v, id) playValue((v)) diff --git a/radio/src/targets/common/arm/stm32/delays.cpp b/radio/src/targets/common/arm/stm32/delays.cpp index c92c19579..c8eb8a3af 100644 --- a/radio/src/targets/common/arm/stm32/delays.cpp +++ b/radio/src/targets/common/arm/stm32/delays.cpp @@ -1,56 +1,56 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "board.h" -#if defined(STM32F2) - #include "dwt.h" // the old ST library that we use does not define DWT register for STM32F2xx -#endif - -#define SYSTEM_TICKS_1US ((CFG_CPU_FREQ + 500000) / 1000000) // number of system ticks in 1us -#define SYSTEM_TICKS_01US ((CFG_CPU_FREQ + 5000000) / 10000000) // number of system ticks in 0.1us (rounding needed for sys frequencies that are not multiple of 10MHz) - -void delaysInit(void) -{ - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - DWT->CYCCNT = 0; - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; -} - -void delay_01us(uint16_t nb) -{ - volatile uint32_t dwtStart = DWT->CYCCNT; - volatile uint32_t dwtTotal = (SYSTEM_TICKS_01US * nb) - 10; - while ((DWT->CYCCNT - dwtStart) < dwtTotal); -} - -void delay_us(uint16_t nb) -{ - volatile uint32_t dwtStart = DWT->CYCCNT; - volatile uint32_t dwtTotal = (SYSTEM_TICKS_1US * nb) - 10; - while ((DWT->CYCCNT - dwtStart) < dwtTotal); -} - -void delay_ms(uint32_t ms) -{ - while (ms--) { - delay_us(1000); - } -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "board.h" +#if defined(STM32F2) + #include "dwt.h" // the old ST library that we use does not define DWT register for STM32F2xx +#endif + +#define SYSTEM_TICKS_1US ((CFG_CPU_FREQ + 500000) / 1000000) // number of system ticks in 1us +#define SYSTEM_TICKS_01US ((CFG_CPU_FREQ + 5000000) / 10000000) // number of system ticks in 0.1us (rounding needed for sys frequencies that are not multiple of 10MHz) + +void delaysInit(void) +{ + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + DWT->CYCCNT = 0; + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; +} + +void delay_01us(uint16_t nb) +{ + volatile uint32_t dwtStart = DWT->CYCCNT; + volatile uint32_t dwtTotal = (SYSTEM_TICKS_01US * nb) - 10; + while ((DWT->CYCCNT - dwtStart) < dwtTotal); +} + +void delay_us(uint16_t nb) +{ + volatile uint32_t dwtStart = DWT->CYCCNT; + volatile uint32_t dwtTotal = (SYSTEM_TICKS_1US * nb) - 10; + while ((DWT->CYCCNT - dwtStart) < dwtTotal); +} + +void delay_ms(uint32_t ms) +{ + while (ms--) { + delay_us(1000); + } +} diff --git a/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c b/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c index 7c00ef1dc..dba520562 100644 --- a/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c +++ b/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c @@ -1,571 +1,571 @@ -/** - ****************************************************************************** - * @file system_stm32f4xx.c - * @author MCD Application Team - * @version V1.1.0 - * @date 25-March-2016 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F4xx devices, - * and is generated by the clock configuration tool - * stm32f4xx_Clock_Configuration_V1.1.0.xls - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define - * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F40xx/41xx/427x/437x devices - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 168000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 168000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 12000000 - *----------------------------------------------------------------------------- - * PLL_M | 12 - *----------------------------------------------------------------------------- - * PLL_N | 336 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 7 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Main regulator output voltage | Scale1 mode - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 5 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Enabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** @addtogroup STM32F4xx_System_Private_Includes - * @{ - */ - -#include "stm32f4xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM324xG_EVAL/STM324x7I_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -/************************* PLL Parameters *************************************/ -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M 12 -#define PLL_N 336 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 7 - -/******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 168000000; - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#if defined(SDRAM) - void SDRAM_Init(); - void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState); - - SDRAM_Init(); // calls SDRAM_GPIOConfig() - FMC_SDRAMWriteProtectionConfig(((uint32_t)0x00000001), DISABLE); -#endif - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - // SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ - extern uint32_t g_pfnVectors ; - SCB->VTOR = (uint32_t) &g_pfnVectors ; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - PWR->CR |= PWR_CR_VOS; - - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f4xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f4xx.s before jump to main. - * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE2 <-> FSMC_A23 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE3 <-> FSMC_A19 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE4 <-> FSMC_A20 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE5 <-> FSMC_A21 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE6 <-> FSMC_A22 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE7 <-> FSMC_D4 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE8 <-> FSMC_D5 | PF14 <-> FSMC_A8 | - | PD13 <-> FSMC_A18 | PE9 <-> FSMC_D6 | PF15 <-> FSMC_A9 | - | PD14 <-> FSMC_D0 | PE10 <-> FSMC_D7 |------------------+ - | PD15 <-> FSMC_D1 | PE11 <-> FSMC_D8 | - +-------------------| PE12 <-> FSMC_D9 | - | PE13 <-> FSMC_D10 | - | PE14 <-> FSMC_D11 | - | PE15 <-> FSMC_D12 | - +--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR |= 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcccccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xaaaa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xffff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xcccccccc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaaaaaa; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffffff; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001011; - FSMC_Bank1->BTCR[3] = 0x00000201; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 1; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 2; - p.FSMC_BusTurnAroundDuration = 0; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 25-March-2016 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F4xx devices, + * and is generated by the clock configuration tool + * stm32f4xx_Clock_Configuration_V1.1.0.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F40xx/41xx/427x/437x devices + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 168000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 168000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 12000000 + *----------------------------------------------------------------------------- + * PLL_M | 12 + *----------------------------------------------------------------------------- + * PLL_N | 336 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 7 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Main regulator output voltage | Scale1 mode + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 5 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2013 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + +#include "stm32f4xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM324xG_EVAL/STM324x7I_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/************************* PLL Parameters *************************************/ +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 12 +#define PLL_N 336 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 7 + +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 168000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined(SDRAM) + void SDRAM_Init(); + void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState); + + SDRAM_Init(); // calls SDRAM_GPIOConfig() + FMC_SDRAMWriteProtectionConfig(((uint32_t)0x00000001), DISABLE); +#endif + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + // SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + extern uint32_t g_pfnVectors ; + SCB->VTOR = (uint32_t) &g_pfnVectors ; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + PWR->CR |= PWR_CR_VOS; + + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f4xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE2 <-> FSMC_A23 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE3 <-> FSMC_A19 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE4 <-> FSMC_A20 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE5 <-> FSMC_A21 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE6 <-> FSMC_A22 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE7 <-> FSMC_D4 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE8 <-> FSMC_D5 | PF14 <-> FSMC_A8 | + | PD13 <-> FSMC_A18 | PE9 <-> FSMC_D6 | PF15 <-> FSMC_A9 | + | PD14 <-> FSMC_D0 | PE10 <-> FSMC_D7 |------------------+ + | PD15 <-> FSMC_D1 | PE11 <-> FSMC_D8 | + +-------------------| PE12 <-> FSMC_D9 | + | PE13 <-> FSMC_D10 | + | PE14 <-> FSMC_D11 | + | PE15 <-> FSMC_D12 | + +--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcccccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xaaaa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xffff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xcccccccc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaaaaaa; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffffff; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 1; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 2; + p.FSMC_BusTurnAroundDuration = 0; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/targets/common/arm/stm32/rtc_driver.cpp b/radio/src/targets/common/arm/stm32/rtc_driver.cpp index a47f632c8..486662713 100644 --- a/radio/src/targets/common/arm/stm32/rtc_driver.cpp +++ b/radio/src/targets/common/arm/stm32/rtc_driver.cpp @@ -1,86 +1,86 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void rtcSetTime(const struct gtm * t) -{ - g_ms100 = 0; // start of next second begins now - - RTC_TimeTypeDef RTC_TimeStruct; - RTC_DateTypeDef RTC_DateStruct; - - RTC_TimeStructInit(&RTC_TimeStruct); - RTC_DateStructInit(&RTC_DateStruct); - - RTC_TimeStruct.RTC_Hours = t->tm_hour; - RTC_TimeStruct.RTC_Minutes = t->tm_min; - RTC_TimeStruct.RTC_Seconds = t->tm_sec; - RTC_DateStruct.RTC_Year = t->tm_year - 100; - RTC_DateStruct.RTC_Month = t->tm_mon + 1; - RTC_DateStruct.RTC_Date = t->tm_mday; - - RTC_SetTime(RTC_Format_BIN, &RTC_TimeStruct); - RTC_SetDate(RTC_Format_BIN, &RTC_DateStruct); -} - -void rtcGetTime(struct gtm * t) -{ - RTC_TimeTypeDef RTC_TimeStruct; - RTC_DateTypeDef RTC_DateStruct; - - RTC_GetTime(RTC_Format_BIN, &RTC_TimeStruct); - RTC_GetDate(RTC_Format_BIN, &RTC_DateStruct); - - t->tm_hour = RTC_TimeStruct.RTC_Hours; - t->tm_min = RTC_TimeStruct.RTC_Minutes; - t->tm_sec = RTC_TimeStruct.RTC_Seconds; - t->tm_year = RTC_DateStruct.RTC_Year + 100; // STM32 year is two decimals only (so base is currently 2000), gtm is based on number of years since 1900 - t->tm_mon = RTC_DateStruct.RTC_Month - 1; - t->tm_mday = RTC_DateStruct.RTC_Date; -} - -void rtcInit() -{ - RTC_InitTypeDef RTC_InitStruct; - - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - PWR_BackupAccessCmd(ENABLE); - RCC_LSEConfig(RCC_LSE_ON); - while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET); - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); - RCC_RTCCLKCmd(ENABLE); - RTC_WaitForSynchro(); - - // RTC time base = LSE / ((AsynchPrediv+1) * (SynchPrediv+1)) = 1 Hz*/ - RTC_InitStruct.RTC_HourFormat = RTC_HourFormat_24; - RTC_InitStruct.RTC_AsynchPrediv = 127; - RTC_InitStruct.RTC_SynchPrediv = 255; - RTC_Init(&RTC_InitStruct); - - struct gtm utm; - rtcGetTime(&utm); - g_rtcTime = gmktime(&utm); - -#if defined(RAMBACKUP) - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_BKPSRAM, ENABLE); - PWR_BackupRegulatorCmd(ENABLE); -#endif -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +void rtcSetTime(const struct gtm * t) +{ + g_ms100 = 0; // start of next second begins now + + RTC_TimeTypeDef RTC_TimeStruct; + RTC_DateTypeDef RTC_DateStruct; + + RTC_TimeStructInit(&RTC_TimeStruct); + RTC_DateStructInit(&RTC_DateStruct); + + RTC_TimeStruct.RTC_Hours = t->tm_hour; + RTC_TimeStruct.RTC_Minutes = t->tm_min; + RTC_TimeStruct.RTC_Seconds = t->tm_sec; + RTC_DateStruct.RTC_Year = t->tm_year - 100; + RTC_DateStruct.RTC_Month = t->tm_mon + 1; + RTC_DateStruct.RTC_Date = t->tm_mday; + + RTC_SetTime(RTC_Format_BIN, &RTC_TimeStruct); + RTC_SetDate(RTC_Format_BIN, &RTC_DateStruct); +} + +void rtcGetTime(struct gtm * t) +{ + RTC_TimeTypeDef RTC_TimeStruct; + RTC_DateTypeDef RTC_DateStruct; + + RTC_GetTime(RTC_Format_BIN, &RTC_TimeStruct); + RTC_GetDate(RTC_Format_BIN, &RTC_DateStruct); + + t->tm_hour = RTC_TimeStruct.RTC_Hours; + t->tm_min = RTC_TimeStruct.RTC_Minutes; + t->tm_sec = RTC_TimeStruct.RTC_Seconds; + t->tm_year = RTC_DateStruct.RTC_Year + 100; // STM32 year is two decimals only (so base is currently 2000), gtm is based on number of years since 1900 + t->tm_mon = RTC_DateStruct.RTC_Month - 1; + t->tm_mday = RTC_DateStruct.RTC_Date; +} + +void rtcInit() +{ + RTC_InitTypeDef RTC_InitStruct; + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + PWR_BackupAccessCmd(ENABLE); + RCC_LSEConfig(RCC_LSE_ON); + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET); + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + RCC_RTCCLKCmd(ENABLE); + RTC_WaitForSynchro(); + + // RTC time base = LSE / ((AsynchPrediv+1) * (SynchPrediv+1)) = 1 Hz*/ + RTC_InitStruct.RTC_HourFormat = RTC_HourFormat_24; + RTC_InitStruct.RTC_AsynchPrediv = 127; + RTC_InitStruct.RTC_SynchPrediv = 255; + RTC_Init(&RTC_InitStruct); + + struct gtm utm; + rtcGetTime(&utm); + g_rtcTime = gmktime(&utm); + +#if defined(RAMBACKUP) + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_BKPSRAM, ENABLE); + PWR_BackupRegulatorCmd(ENABLE); +#endif +} diff --git a/radio/src/targets/common/arm/stm32/serial2_driver.cpp b/radio/src/targets/common/arm/stm32/serial2_driver.cpp index 5735c8453..68027ee30 100644 --- a/radio/src/targets/common/arm/stm32/serial2_driver.cpp +++ b/radio/src/targets/common/arm/stm32/serial2_driver.cpp @@ -1,171 +1,171 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -uint8_t serial2Mode = 0; -Fifo serial2TxFifo; -DMAFifo<32> serial2RxFifo __DMA (SERIAL_DMA_Stream_RX); - -void uart3Setup(unsigned int baudrate, bool dma) -{ - USART_InitTypeDef USART_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - GPIO_PinAFConfig(SERIAL_GPIO, SERIAL_GPIO_PinSource_RX, SERIAL_GPIO_AF); - GPIO_PinAFConfig(SERIAL_GPIO, SERIAL_GPIO_PinSource_TX, SERIAL_GPIO_AF); - - GPIO_InitStructure.GPIO_Pin = SERIAL_GPIO_PIN_TX | SERIAL_GPIO_PIN_RX; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_Init(SERIAL_GPIO, &GPIO_InitStructure); - - USART_InitStructure.USART_BaudRate = baudrate; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; - USART_Init(SERIAL_USART, &USART_InitStructure); - - if (dma) { - DMA_InitTypeDef DMA_InitStructure; - serial2RxFifo.clear(); - USART_ITConfig(SERIAL_USART, USART_IT_RXNE, DISABLE); - USART_ITConfig(SERIAL_USART, USART_IT_TXE, DISABLE); - DMA_InitStructure.DMA_Channel = SERIAL_DMA_Channel_RX; - DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&SERIAL_USART->DR); - DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(serial2RxFifo.buffer()); - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; - DMA_InitStructure.DMA_BufferSize = serial2RxFifo.size(); - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; - DMA_InitStructure.DMA_Priority = DMA_Priority_Low; - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - DMA_Init(SERIAL_DMA_Stream_RX, &DMA_InitStructure); - USART_DMACmd(SERIAL_USART, USART_DMAReq_Rx, ENABLE); - USART_Cmd(SERIAL_USART, ENABLE); - DMA_Cmd(SERIAL_DMA_Stream_RX, ENABLE); - } - else { - USART_Cmd(SERIAL_USART, ENABLE); - USART_ITConfig(SERIAL_USART, USART_IT_RXNE, ENABLE); - USART_ITConfig(SERIAL_USART, USART_IT_TXE, DISABLE); - NVIC_SetPriority(SERIAL_USART_IRQn, 7); - NVIC_EnableIRQ(SERIAL_USART_IRQn); - } -} - -void serial2Init(unsigned int mode, unsigned int protocol) -{ - serial2Stop(); - - serial2Mode = mode; - - switch (mode) { - case UART_MODE_TELEMETRY_MIRROR: - uart3Setup(FRSKY_SPORT_BAUDRATE, false); - break; -#if !defined(USB_SERIAL) && (defined(DEBUG) || defined(CLI)) - case UART_MODE_DEBUG: - uart3Setup(DEBUG_BAUDRATE, false); - break; -#endif - case UART_MODE_TELEMETRY: - if (protocol == PROTOCOL_FRSKY_D_SECONDARY) { - uart3Setup(FRSKY_D_BAUDRATE, true); - } - break; - } -} - -void serial2Putc(char c) -{ -#if !defined(SIMU) - int n = 0; - while (serial2TxFifo.isFull()) { - delay_ms(1); - if (++n > 100) return; - } - serial2TxFifo.push(c); - USART_ITConfig(SERIAL_USART, USART_IT_TXE, ENABLE); -#endif -} - -void serial2SbusInit() -{ - uart3Setup(SBUS_BAUDRATE, true); - SERIAL_USART->CR1 |= USART_CR1_M | USART_CR1_PCE ; -} - -void serial2Stop() -{ - DMA_DeInit(SERIAL_DMA_Stream_RX); - USART_DeInit(SERIAL_USART); -} - -uint8_t serial2TracesEnabled() -{ -#if defined(DEBUG) - return (serial2Mode == UART_MODE_DEBUG); -#else - return false; -#endif -} - -extern "C" void SERIAL_USART_IRQHandler(void) -{ - DEBUG_INTERRUPT(INT_SER2); - // Send - if (USART_GetITStatus(SERIAL_USART, USART_IT_TXE) != RESET) { - uint8_t txchar; - if (serial2TxFifo.pop(txchar)) { - /* Write one byte to the transmit data register */ - USART_SendData(SERIAL_USART, txchar); - } - else { - USART_ITConfig(SERIAL_USART, USART_IT_TXE, DISABLE); - } - } - -#if !defined(USB_SERIAL) && defined(CLI) - // Receive - uint32_t status = SERIAL_USART->SR; - while (status & (USART_FLAG_RXNE | USART_FLAG_ERRORS)) { - uint8_t data = SERIAL_USART->DR; - if (!(status & USART_FLAG_ERRORS)) { - switch (serial2Mode) { - case UART_MODE_DEBUG: - cliRxFifo.push(data); - break; - } - } - status = SERIAL_USART->SR; - } -#endif -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +uint8_t serial2Mode = 0; +Fifo serial2TxFifo; +DMAFifo<32> serial2RxFifo __DMA (SERIAL_DMA_Stream_RX); + +void uart3Setup(unsigned int baudrate, bool dma) +{ + USART_InitTypeDef USART_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_PinAFConfig(SERIAL_GPIO, SERIAL_GPIO_PinSource_RX, SERIAL_GPIO_AF); + GPIO_PinAFConfig(SERIAL_GPIO, SERIAL_GPIO_PinSource_TX, SERIAL_GPIO_AF); + + GPIO_InitStructure.GPIO_Pin = SERIAL_GPIO_PIN_TX | SERIAL_GPIO_PIN_RX; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_Init(SERIAL_GPIO, &GPIO_InitStructure); + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; + USART_Init(SERIAL_USART, &USART_InitStructure); + + if (dma) { + DMA_InitTypeDef DMA_InitStructure; + serial2RxFifo.clear(); + USART_ITConfig(SERIAL_USART, USART_IT_RXNE, DISABLE); + USART_ITConfig(SERIAL_USART, USART_IT_TXE, DISABLE); + DMA_InitStructure.DMA_Channel = SERIAL_DMA_Channel_RX; + DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&SERIAL_USART->DR); + DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(serial2RxFifo.buffer()); + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = serial2RxFifo.size(); + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_Low; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(SERIAL_DMA_Stream_RX, &DMA_InitStructure); + USART_DMACmd(SERIAL_USART, USART_DMAReq_Rx, ENABLE); + USART_Cmd(SERIAL_USART, ENABLE); + DMA_Cmd(SERIAL_DMA_Stream_RX, ENABLE); + } + else { + USART_Cmd(SERIAL_USART, ENABLE); + USART_ITConfig(SERIAL_USART, USART_IT_RXNE, ENABLE); + USART_ITConfig(SERIAL_USART, USART_IT_TXE, DISABLE); + NVIC_SetPriority(SERIAL_USART_IRQn, 7); + NVIC_EnableIRQ(SERIAL_USART_IRQn); + } +} + +void serial2Init(unsigned int mode, unsigned int protocol) +{ + serial2Stop(); + + serial2Mode = mode; + + switch (mode) { + case UART_MODE_TELEMETRY_MIRROR: + uart3Setup(FRSKY_SPORT_BAUDRATE, false); + break; +#if !defined(USB_SERIAL) && (defined(DEBUG) || defined(CLI)) + case UART_MODE_DEBUG: + uart3Setup(DEBUG_BAUDRATE, false); + break; +#endif + case UART_MODE_TELEMETRY: + if (protocol == PROTOCOL_FRSKY_D_SECONDARY) { + uart3Setup(FRSKY_D_BAUDRATE, true); + } + break; + } +} + +void serial2Putc(char c) +{ +#if !defined(SIMU) + int n = 0; + while (serial2TxFifo.isFull()) { + delay_ms(1); + if (++n > 100) return; + } + serial2TxFifo.push(c); + USART_ITConfig(SERIAL_USART, USART_IT_TXE, ENABLE); +#endif +} + +void serial2SbusInit() +{ + uart3Setup(SBUS_BAUDRATE, true); + SERIAL_USART->CR1 |= USART_CR1_M | USART_CR1_PCE ; +} + +void serial2Stop() +{ + DMA_DeInit(SERIAL_DMA_Stream_RX); + USART_DeInit(SERIAL_USART); +} + +uint8_t serial2TracesEnabled() +{ +#if defined(DEBUG) + return (serial2Mode == UART_MODE_DEBUG); +#else + return false; +#endif +} + +extern "C" void SERIAL_USART_IRQHandler(void) +{ + DEBUG_INTERRUPT(INT_SER2); + // Send + if (USART_GetITStatus(SERIAL_USART, USART_IT_TXE) != RESET) { + uint8_t txchar; + if (serial2TxFifo.pop(txchar)) { + /* Write one byte to the transmit data register */ + USART_SendData(SERIAL_USART, txchar); + } + else { + USART_ITConfig(SERIAL_USART, USART_IT_TXE, DISABLE); + } + } + +#if !defined(USB_SERIAL) && defined(CLI) + // Receive + uint32_t status = SERIAL_USART->SR; + while (status & (USART_FLAG_RXNE | USART_FLAG_ERRORS)) { + uint8_t data = SERIAL_USART->DR; + if (!(status & USART_FLAG_ERRORS)) { + switch (serial2Mode) { + case UART_MODE_DEBUG: + cliRxFifo.push(data); + break; + } + } + status = SERIAL_USART->SR; + } +#endif +} diff --git a/radio/src/targets/common/arm/stm32/usb_bsp.c b/radio/src/targets/common/arm/stm32/usb_bsp.c index df4ecb757..81b3277d6 100644 --- a/radio/src/targets/common/arm/stm32/usb_bsp.c +++ b/radio/src/targets/common/arm/stm32/usb_bsp.c @@ -1,118 +1,118 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Includes ------------------------------------------------------------------*/ - -#include "usb_bsp.h" -#include "board.h" -#include "usbd_conf.h" - -extern uint32_t SystemCoreClock; - -/** -* @brief USB_OTG_BSP_Init -* Initilizes BSP configurations -* @param None -* @retval None -*/ - -void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - RCC_AHB1PeriphClockCmd(USB_RCC_AHB1Periph_GPIO, ENABLE); - - /* Configure DM and DP Pins */ - GPIO_InitStructure.GPIO_Pin = USB_GPIO_PIN_DM | USB_GPIO_PIN_DP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(USB_GPIO, &GPIO_InitStructure); - - GPIO_PinAFConfig(USB_GPIO, USB_GPIO_PinSource_DM, USB_GPIO_AF); - GPIO_PinAFConfig(USB_GPIO, USB_GPIO_PinSource_DP, USB_GPIO_AF); - - /* Configure VBUS Pin */ - GPIO_InitStructure.GPIO_Pin = USB_GPIO_PIN_VBUS; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(USB_GPIO, &GPIO_InitStructure); - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE) ; -} - -void USB_OTG_BSP_Deinit(USB_OTG_CORE_HANDLE *pdev) -{ - //nothing to do -} - -/** -* @brief USB_OTG_BSP_EnableInterrupt -* Enable USB Global interrupt -* @param None -* @retval None -*/ -void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev) -{ - NVIC_SetPriority(OTG_FS_IRQn, 11); // Lower priority interrupt - NVIC_EnableIRQ(OTG_FS_IRQn); -} - -/** -* @brief USB_OTG_BSP_DisableInterrupt -* Disable USB Global interrupt -* @param None -* @retval None -*/ -void USB_OTG_BSP_DisableInterrupt(USB_OTG_CORE_HANDLE *pdev) -{ - NVIC_DisableIRQ(OTG_FS_IRQn); -} - - -/** -* @brief USB_OTG_BSP_uDelay -* This function provides delay time in micro sec -* @param usec : Value of delay required in micro sec -* @retval None -*/ -void USB_OTG_BSP_uDelay (const uint32_t usec) -{ - delay_us(usec); -} - - -/** -* @brief USB_OTG_BSP_mDelay -* This function provides delay time in milli sec -* @param msec : Value of delay required in milli sec -* @retval None -*/ -void USB_OTG_BSP_mDelay (const uint32_t msec) -{ - delay_ms(msec); -} - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Includes ------------------------------------------------------------------*/ + +#include "usb_bsp.h" +#include "board.h" +#include "usbd_conf.h" + +extern uint32_t SystemCoreClock; + +/** +* @brief USB_OTG_BSP_Init +* Initilizes BSP configurations +* @param None +* @retval None +*/ + +void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_AHB1PeriphClockCmd(USB_RCC_AHB1Periph_GPIO, ENABLE); + + /* Configure DM and DP Pins */ + GPIO_InitStructure.GPIO_Pin = USB_GPIO_PIN_DM | USB_GPIO_PIN_DP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(USB_GPIO, &GPIO_InitStructure); + + GPIO_PinAFConfig(USB_GPIO, USB_GPIO_PinSource_DM, USB_GPIO_AF); + GPIO_PinAFConfig(USB_GPIO, USB_GPIO_PinSource_DP, USB_GPIO_AF); + + /* Configure VBUS Pin */ + GPIO_InitStructure.GPIO_Pin = USB_GPIO_PIN_VBUS; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; + GPIO_Init(USB_GPIO, &GPIO_InitStructure); + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE) ; +} + +void USB_OTG_BSP_Deinit(USB_OTG_CORE_HANDLE *pdev) +{ + //nothing to do +} + +/** +* @brief USB_OTG_BSP_EnableInterrupt +* Enable USB Global interrupt +* @param None +* @retval None +*/ +void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev) +{ + NVIC_SetPriority(OTG_FS_IRQn, 11); // Lower priority interrupt + NVIC_EnableIRQ(OTG_FS_IRQn); +} + +/** +* @brief USB_OTG_BSP_DisableInterrupt +* Disable USB Global interrupt +* @param None +* @retval None +*/ +void USB_OTG_BSP_DisableInterrupt(USB_OTG_CORE_HANDLE *pdev) +{ + NVIC_DisableIRQ(OTG_FS_IRQn); +} + + +/** +* @brief USB_OTG_BSP_uDelay +* This function provides delay time in micro sec +* @param usec : Value of delay required in micro sec +* @retval None +*/ +void USB_OTG_BSP_uDelay (const uint32_t usec) +{ + delay_us(usec); +} + + +/** +* @brief USB_OTG_BSP_mDelay +* This function provides delay time in milli sec +* @param msec : Value of delay required in milli sec +* @retval None +*/ +void USB_OTG_BSP_mDelay (const uint32_t msec) +{ + delay_ms(msec); +} + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/targets/common/arm/stm32/usb_conf.h b/radio/src/targets/common/arm/stm32/usb_conf.h index 9db23007d..9bc6f5f96 100644 --- a/radio/src/targets/common/arm/stm32/usb_conf.h +++ b/radio/src/targets/common/arm/stm32/usb_conf.h @@ -1,168 +1,168 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef _USB_CONF_H_ -#define _USB_CONF_H_ - -#if defined(STM32F4) - #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#else - #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" -#endif - -/* USB Core and PHY interface configuration. - Tip: To avoid modifying these defines each time you need to change the USB - configuration, you can declare the needed define in your toolchain - compiler preprocessor. - */ -/****************** USB OTG FS PHY CONFIGURATION ******************************* -* The USB OTG FS Core supports one on-chip Full Speed PHY. -* -* The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor -* when FS core is used. -*******************************************************************************/ -#ifndef USE_USB_OTG_FS - #define USE_USB_OTG_FS // USB2.0 Full Speed == 12 Mbit -#endif /* USE_USB_OTG_FS */ - -#ifdef USE_USB_OTG_FS - #define USB_OTG_FS_CORE -#endif - -/******************************************************************************* -* FIFO Size Configuration in Device mode -* -* (i) Receive data FIFO size = RAM for setup packets + -* OUT endpoint control information + -* data OUT packets + miscellaneous -* Space = ONE 32-bits words -* --> RAM for setup packets = 10 spaces -* (n is the nbr of CTRL EPs the device core supports) -* --> OUT EP CTRL info = 1 space -* (one space for status information written to the FIFO along with each -* received packet) -* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces -* (MINIMUM to receive packets) -* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces -* (if high-bandwidth EP is enabled or multiple isochronous EPs) -* --> miscellaneous = 1 space per OUT EP -* (one space for transfer complete status information also pushed to the -* FIFO with each endpoint's last packet) -* -* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for -* that particular IN EP. More space allocated in the IN EP Tx FIFO results -* in a better performance on the USB and can hide latencies on the AHB. -* -* (iii) TXn min size = 16 words. (n : Transmit FIFO index) -* (iv) When a TxFIFO is not used, the Configuration should be as follows: -* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txm can use the space allocated for Txn. -* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txn should be configured with the minimum space of 16 words -* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top -* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. -* (vi) In HS case12 FIFO locations should be reserved for internal DMA registers -* so total FIFO size should be 1012 Only instead of 1024 -*******************************************************************************/ - -/****************** USB OTG FS CONFIGURATION **********************************/ -#ifdef USB_OTG_FS_CORE - #define RX_FIFO_FS_SIZE 128 - #define TX0_FIFO_FS_SIZE 64 - #define TX1_FIFO_FS_SIZE 128 - #define TX2_FIFO_FS_SIZE 0 - #define TX3_FIFO_FS_SIZE 0 - -// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT -// #define USB_OTG_FS_SOF_OUTPUT_ENABLED -#endif - -/****************** USB OTG MISC CONFIGURATION ********************************/ -#define VBUS_SENSING_ENABLED - -/****************** USB OTG MODE CONFIGURATION ********************************/ -//#define USE_HOST_MODE -#define USE_DEVICE_MODE -//#define USE_OTG_MODE - -#ifndef USB_OTG_FS_CORE - #ifndef USB_OTG_HS_CORE - #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined" - #endif -#endif - -#ifndef USE_DEVICE_MODE - #ifndef USE_HOST_MODE - #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" - #endif -#endif - -#ifndef USE_USB_OTG_HS - #ifndef USE_USB_OTG_FS - #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined" - #endif -#else //USE_USB_OTG_HS - #ifndef USE_ULPI_PHY - #ifndef USE_EMBEDDED_PHY - #error "USE_ULPI_PHY or USE_EMBEDDED_PHY should be defined" - #endif - #endif -#endif - -/****************** C Compilers dependant keywords ****************************/ -/* In HS mode and when the DMA is used, all variables and data structures dealing - with the DMA during the transaction process should be 4-bytes aligned */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined (__GNUC__) /* GNU Compiler */ - #define __ALIGN_END __attribute__ ((aligned (4))) - #define __ALIGN_BEGIN - #else - #define __ALIGN_END - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __ALIGN_BEGIN __align(4) - #endif /* __CC_ARM */ - #endif /* __GNUC__ */ -#else - #define __ALIGN_BEGIN - #define __ALIGN_END -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/* __packed keyword used to decrease the data type alignment to 1-byte */ -#if !defined(__packed) - #if defined (__CC_ARM) /* ARM Compiler */ - #define __packed __packed - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __packed __packed - #elif defined ( __GNUC__ ) /* GNU Compiler */ - #define __packed __attribute__ ((__packed__)) - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __packed __unaligned - #endif /* __CC_ARM */ -#endif - -#endif // _USB_CONF_H_ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _USB_CONF_H_ +#define _USB_CONF_H_ + +#if defined(STM32F4) + #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#else + #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" +#endif + +/* USB Core and PHY interface configuration. + Tip: To avoid modifying these defines each time you need to change the USB + configuration, you can declare the needed define in your toolchain + compiler preprocessor. + */ +/****************** USB OTG FS PHY CONFIGURATION ******************************* +* The USB OTG FS Core supports one on-chip Full Speed PHY. +* +* The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor +* when FS core is used. +*******************************************************************************/ +#ifndef USE_USB_OTG_FS + #define USE_USB_OTG_FS // USB2.0 Full Speed == 12 Mbit +#endif /* USE_USB_OTG_FS */ + +#ifdef USE_USB_OTG_FS + #define USB_OTG_FS_CORE +#endif + +/******************************************************************************* +* FIFO Size Configuration in Device mode +* +* (i) Receive data FIFO size = RAM for setup packets + +* OUT endpoint control information + +* data OUT packets + miscellaneous +* Space = ONE 32-bits words +* --> RAM for setup packets = 10 spaces +* (n is the nbr of CTRL EPs the device core supports) +* --> OUT EP CTRL info = 1 space +* (one space for status information written to the FIFO along with each +* received packet) +* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces +* (MINIMUM to receive packets) +* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces +* (if high-bandwidth EP is enabled or multiple isochronous EPs) +* --> miscellaneous = 1 space per OUT EP +* (one space for transfer complete status information also pushed to the +* FIFO with each endpoint's last packet) +* +* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for +* that particular IN EP. More space allocated in the IN EP Tx FIFO results +* in a better performance on the USB and can hide latencies on the AHB. +* +* (iii) TXn min size = 16 words. (n : Transmit FIFO index) +* (iv) When a TxFIFO is not used, the Configuration should be as follows: +* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) +* --> Txm can use the space allocated for Txn. +* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) +* --> Txn should be configured with the minimum space of 16 words +* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top +* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. +* (vi) In HS case12 FIFO locations should be reserved for internal DMA registers +* so total FIFO size should be 1012 Only instead of 1024 +*******************************************************************************/ + +/****************** USB OTG FS CONFIGURATION **********************************/ +#ifdef USB_OTG_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 128 + #define TX2_FIFO_FS_SIZE 0 + #define TX3_FIFO_FS_SIZE 0 + +// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT +// #define USB_OTG_FS_SOF_OUTPUT_ENABLED +#endif + +/****************** USB OTG MISC CONFIGURATION ********************************/ +#define VBUS_SENSING_ENABLED + +/****************** USB OTG MODE CONFIGURATION ********************************/ +//#define USE_HOST_MODE +#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_OTG_FS_CORE + #ifndef USB_OTG_HS_CORE + #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_OTG_HS + #ifndef USE_USB_OTG_FS + #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined" + #endif +#else //USE_USB_OTG_HS + #ifndef USE_ULPI_PHY + #ifndef USE_EMBEDDED_PHY + #error "USE_ULPI_PHY or USE_EMBEDDED_PHY should be defined" + #endif + #endif +#endif + +/****************** C Compilers dependant keywords ****************************/ +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned (4))) + #define __ALIGN_BEGIN + #else + #define __ALIGN_END + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #elif defined (__TASKING__) /* TASKING Compiler */ + #define __ALIGN_BEGIN __align(4) + #endif /* __CC_ARM */ + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +/* __packed keyword used to decrease the data type alignment to 1-byte */ +#if !defined(__packed) + #if defined (__CC_ARM) /* ARM Compiler */ + #define __packed __packed + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __packed __packed + #elif defined ( __GNUC__ ) /* GNU Compiler */ + #define __packed __attribute__ ((__packed__)) + #elif defined (__TASKING__) /* TASKING Compiler */ + #define __packed __unaligned + #endif /* __CC_ARM */ +#endif + +#endif // _USB_CONF_H_ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/targets/common/arm/stm32/usbd_cdc.cpp b/radio/src/targets/common/arm/stm32/usbd_cdc.cpp index 1bc2fef4a..dd0233941 100644 --- a/radio/src/targets/common/arm/stm32/usbd_cdc.cpp +++ b/radio/src/targets/common/arm/stm32/usbd_cdc.cpp @@ -1,232 +1,232 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED -#pragma data_alignment = 4 -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -#include "opentx.h" - -extern "C" { - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - - -/* These are external variables imported from CDC core to be used for IN - transfer management. */ -extern uint8_t APP_Rx_Buffer []; /* Write CDC received data in this buffer. - These data will be sent over USB IN endpoint - in the CDC core functions. */ -extern volatile uint32_t APP_Rx_ptr_in; /* Increment this pointer or roll it back to - start address when writing received data - in the buffer APP_Rx_Buffer. */ -extern volatile uint32_t APP_Rx_ptr_out; - -/* Private function prototypes -----------------------------------------------*/ -static uint16_t VCP_Init (void); -static uint16_t VCP_DeInit (void); -static uint16_t VCP_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len); -static uint16_t VCP_DataRx (uint8_t* Buf, uint32_t Len); - -extern "C" const CDC_IF_Prop_TypeDef VCP_fops = -{ - VCP_Init, - VCP_DeInit, - VCP_Ctrl, - 0, - VCP_DataRx -}; - -} // extern "C" - -bool cdcConnected = false; - -/* Private functions ---------------------------------------------------------*/ -/** - * @brief VCP_Init - * Initializes the Media on the STM32 - * @param None - * @retval Result of the opeartion (USBD_OK in all cases) - */ -static uint16_t VCP_Init(void) -{ - cdcConnected = true; - return USBD_OK; -} - -/** - * @brief VCP_DeInit - * DeInitializes the Media on the STM32 - * @param None - * @retval Result of the opeartion (USBD_OK in all cases) - */ -static uint16_t VCP_DeInit(void) -{ - cdcConnected = false; - return USBD_OK; -} - - -/** - * @brief VCP_Ctrl - * Manage the CDC class requests - * @param Cmd: Command code - * @param Buf: Buffer containing command data (request parameters) - * @param Len: Number of data to be sent (in bytes) - * @retval Result of the opeartion (USBD_OK in all cases) - */ -static uint16_t VCP_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len) -{ - switch (Cmd) - { - case SEND_ENCAPSULATED_COMMAND: - /* Not needed for this driver */ - break; - - case GET_ENCAPSULATED_RESPONSE: - /* Not needed for this driver */ - break; - - case SET_COMM_FEATURE: - /* Not needed for this driver */ - break; - - case GET_COMM_FEATURE: - /* Not needed for this driver */ - break; - - case CLEAR_COMM_FEATURE: - /* Not needed for this driver */ - break; - - case SET_LINE_CODING: - /* Not needed for this driver */ - break; - - case GET_LINE_CODING: - /* Not needed for this driver */ - break; - - case SET_CONTROL_LINE_STATE: - /* Not needed for this driver */ - break; - - case SEND_BREAK: - /* Not needed for this driver */ - break; - - default: - break; - } - - return USBD_OK; -} - -// some debug vars -uint16_t usbWraps = 0; -uint16_t charsWritten = 0; - -void usbSerialPutc(uint8_t c) -{ - - /* - Apparently there is no reliable way to tell if the - virtual serial port is opened or not. - - The cdcConnected variable only reports the state - of the physical USB connection. - */ - - if (!cdcConnected) return; - - uint32_t prim = __get_PRIMASK(); - __disable_irq(); - uint32_t txDataLen = APP_RX_DATA_SIZE + APP_Rx_ptr_in - APP_Rx_ptr_out; - if (!prim) __enable_irq(); - - if (txDataLen >= APP_RX_DATA_SIZE) { - txDataLen -= APP_RX_DATA_SIZE; - } - if (txDataLen > (APP_RX_DATA_SIZE - CDC_DATA_MAX_PACKET_SIZE)) return; // buffer is too full, skip this write - - ++charsWritten; - - /* - APP_Rx_Buffer and associated variables must be modified - atomically, because they are used from the interrupt - */ - - /* Read PRIMASK register, check interrupt status before you disable them */ - /* Returns 0 if they are enabled, or non-zero if disabled */ - prim = __get_PRIMASK(); - __disable_irq(); - APP_Rx_Buffer[APP_Rx_ptr_in++] = c; - if(APP_Rx_ptr_in >= APP_RX_DATA_SIZE) - { - APP_Rx_ptr_in = 0; - ++usbWraps; - } - if (!prim) __enable_irq(); -} - -/** - * @brief VCP_DataRx - * Data received over USB OUT endpoint is available here - * - * @note - * This function will block any OUT packet reception on USB endpoint - * until exiting this function. If you exit this function before transfer - * is complete on CDC interface (ie. using DMA controller) it will result - * in receiving more data while previous ones are still not sent. - * - * @note - * This function is executed inside the USBD_OTG_ISR_Handler() interrupt handler! - - * @param Buf: Buffer of data to be received - * @param Len: Number of data received (in bytes) - * @retval Result of the opeartion: USBD_OK if all operations are OK else VCP_FAIL - */ -static uint16_t VCP_DataRx (uint8_t* Buf, uint32_t Len) -{ - // TODO: try implementing inbound flow control: - // if the cliRxFifo does not have enough free space to receive all - // available characters, return VCP_FAIL. Maybe that will throttle down - // the sender and we will receive the same packet at a later time. - -#if defined(CLI) - //copy data to the application FIFO - for (uint32_t i = 0; i < Len; i++) - { - cliRxFifo.push(Buf[i]); - } -#endif - - return USBD_OK; -} - - - -// /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED +#pragma data_alignment = 4 +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +#include "opentx.h" + +extern "C" { + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + + +/* These are external variables imported from CDC core to be used for IN + transfer management. */ +extern uint8_t APP_Rx_Buffer []; /* Write CDC received data in this buffer. + These data will be sent over USB IN endpoint + in the CDC core functions. */ +extern volatile uint32_t APP_Rx_ptr_in; /* Increment this pointer or roll it back to + start address when writing received data + in the buffer APP_Rx_Buffer. */ +extern volatile uint32_t APP_Rx_ptr_out; + +/* Private function prototypes -----------------------------------------------*/ +static uint16_t VCP_Init (void); +static uint16_t VCP_DeInit (void); +static uint16_t VCP_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len); +static uint16_t VCP_DataRx (uint8_t* Buf, uint32_t Len); + +extern "C" const CDC_IF_Prop_TypeDef VCP_fops = +{ + VCP_Init, + VCP_DeInit, + VCP_Ctrl, + 0, + VCP_DataRx +}; + +} // extern "C" + +bool cdcConnected = false; + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief VCP_Init + * Initializes the Media on the STM32 + * @param None + * @retval Result of the opeartion (USBD_OK in all cases) + */ +static uint16_t VCP_Init(void) +{ + cdcConnected = true; + return USBD_OK; +} + +/** + * @brief VCP_DeInit + * DeInitializes the Media on the STM32 + * @param None + * @retval Result of the opeartion (USBD_OK in all cases) + */ +static uint16_t VCP_DeInit(void) +{ + cdcConnected = false; + return USBD_OK; +} + + +/** + * @brief VCP_Ctrl + * Manage the CDC class requests + * @param Cmd: Command code + * @param Buf: Buffer containing command data (request parameters) + * @param Len: Number of data to be sent (in bytes) + * @retval Result of the opeartion (USBD_OK in all cases) + */ +static uint16_t VCP_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len) +{ + switch (Cmd) + { + case SEND_ENCAPSULATED_COMMAND: + /* Not needed for this driver */ + break; + + case GET_ENCAPSULATED_RESPONSE: + /* Not needed for this driver */ + break; + + case SET_COMM_FEATURE: + /* Not needed for this driver */ + break; + + case GET_COMM_FEATURE: + /* Not needed for this driver */ + break; + + case CLEAR_COMM_FEATURE: + /* Not needed for this driver */ + break; + + case SET_LINE_CODING: + /* Not needed for this driver */ + break; + + case GET_LINE_CODING: + /* Not needed for this driver */ + break; + + case SET_CONTROL_LINE_STATE: + /* Not needed for this driver */ + break; + + case SEND_BREAK: + /* Not needed for this driver */ + break; + + default: + break; + } + + return USBD_OK; +} + +// some debug vars +uint16_t usbWraps = 0; +uint16_t charsWritten = 0; + +void usbSerialPutc(uint8_t c) +{ + + /* + Apparently there is no reliable way to tell if the + virtual serial port is opened or not. + + The cdcConnected variable only reports the state + of the physical USB connection. + */ + + if (!cdcConnected) return; + + uint32_t prim = __get_PRIMASK(); + __disable_irq(); + uint32_t txDataLen = APP_RX_DATA_SIZE + APP_Rx_ptr_in - APP_Rx_ptr_out; + if (!prim) __enable_irq(); + + if (txDataLen >= APP_RX_DATA_SIZE) { + txDataLen -= APP_RX_DATA_SIZE; + } + if (txDataLen > (APP_RX_DATA_SIZE - CDC_DATA_MAX_PACKET_SIZE)) return; // buffer is too full, skip this write + + ++charsWritten; + + /* + APP_Rx_Buffer and associated variables must be modified + atomically, because they are used from the interrupt + */ + + /* Read PRIMASK register, check interrupt status before you disable them */ + /* Returns 0 if they are enabled, or non-zero if disabled */ + prim = __get_PRIMASK(); + __disable_irq(); + APP_Rx_Buffer[APP_Rx_ptr_in++] = c; + if(APP_Rx_ptr_in >= APP_RX_DATA_SIZE) + { + APP_Rx_ptr_in = 0; + ++usbWraps; + } + if (!prim) __enable_irq(); +} + +/** + * @brief VCP_DataRx + * Data received over USB OUT endpoint is available here + * + * @note + * This function will block any OUT packet reception on USB endpoint + * until exiting this function. If you exit this function before transfer + * is complete on CDC interface (ie. using DMA controller) it will result + * in receiving more data while previous ones are still not sent. + * + * @note + * This function is executed inside the USBD_OTG_ISR_Handler() interrupt handler! + + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the opeartion: USBD_OK if all operations are OK else VCP_FAIL + */ +static uint16_t VCP_DataRx (uint8_t* Buf, uint32_t Len) +{ + // TODO: try implementing inbound flow control: + // if the cliRxFifo does not have enough free space to receive all + // available characters, return VCP_FAIL. Maybe that will throttle down + // the sender and we will receive the same packet at a later time. + +#if defined(CLI) + //copy data to the application FIFO + for (uint32_t i = 0; i < Len; i++) + { + cliRxFifo.push(Buf[i]); + } +#endif + + return USBD_OK; +} + + + +// /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/targets/common/arm/stm32/usbd_conf.h b/radio/src/targets/common/arm/stm32/usbd_conf.h index ef87f9b26..f9294ee71 100644 --- a/radio/src/targets/common/arm/stm32/usbd_conf.h +++ b/radio/src/targets/common/arm/stm32/usbd_conf.h @@ -18,47 +18,47 @@ * GNU General Public License for more details. */ -/* Define to prevent recursive inclusion -------------------------------------*/ +/* Define to prevent recursive inclusion -------------------------------------*/ #ifndef _USBD_CONF_H_ #define _USBD_CONF_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -#define USBD_CFG_MAX_NUM 1 -#define USBD_ITF_MAX_NUM 1 -#define USB_MAX_STR_DESC_SIZ 64 - -#define USBD_SELF_POWERED - -/* Class Layer Parameter */ - -#define MSC_IN_EP 0x81 -#define MSC_OUT_EP 0x01 -#define MSC_MAX_PACKET 64 - -#define MSC_MEDIA_PACKET 4096 - -#define HID_IN_EP 0x81 -#define HID_OUT_EP 0x01 - -#define HID_IN_PACKET 11 -#define HID_OUT_PACKET 9 - -#define CDC_IN_EP 0x81 /* EP1 for data IN */ -#define CDC_OUT_EP 0x01 /* EP1 for data OUT */ -#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ - -/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ -#define CDC_DATA_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ -#define CDC_CMD_PACKET_SZE 8 /* Control Endpoint Packet size */ - -#define CDC_IN_FRAME_INTERVAL 5 /* Number of frames between IN transfers */ -#define APP_RX_DATA_SIZE 512 // USB serial port output buffer. TODO: tune this buffer size /* Total size of IN buffer: APP_RX_DATA_SIZE*8/MAX_BAUDARATE*1000 should be > CDC_IN_FRAME_INTERVAL */ -#define APP_FOPS VCP_fops - + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 +#define USBD_ITF_MAX_NUM 1 +#define USB_MAX_STR_DESC_SIZ 64 + +#define USBD_SELF_POWERED + +/* Class Layer Parameter */ + +#define MSC_IN_EP 0x81 +#define MSC_OUT_EP 0x01 +#define MSC_MAX_PACKET 64 + +#define MSC_MEDIA_PACKET 4096 + +#define HID_IN_EP 0x81 +#define HID_OUT_EP 0x01 + +#define HID_IN_PACKET 11 +#define HID_OUT_PACKET 9 + +#define CDC_IN_EP 0x81 /* EP1 for data IN */ +#define CDC_OUT_EP 0x01 /* EP1 for data OUT */ +#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ + +/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ +#define CDC_DATA_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ +#define CDC_CMD_PACKET_SZE 8 /* Control Endpoint Packet size */ + +#define CDC_IN_FRAME_INTERVAL 5 /* Number of frames between IN transfers */ +#define APP_RX_DATA_SIZE 512 // USB serial port output buffer. TODO: tune this buffer size /* Total size of IN buffer: APP_RX_DATA_SIZE*8/MAX_BAUDARATE*1000 should be > CDC_IN_FRAME_INTERVAL */ +#define APP_FOPS VCP_fops + #endif // _USBD_CONF_H_ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/targets/common/arm/stm32/usbd_desc.c b/radio/src/targets/common/arm/stm32/usbd_desc.c index 7c9d7629f..09b805de0 100644 --- a/radio/src/targets/common/arm/stm32/usbd_desc.c +++ b/radio/src/targets/common/arm/stm32/usbd_desc.c @@ -1,239 +1,239 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_desc.h" - -#include - -#include "board.h" -#include "usbd_conf.h" -#include "usbd_core.h" -#include "usbd_req.h" -#include "usb_regs.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_DESC - * @brief USBD descriptors module - * @{ - */ - -/** @defgroup USBD_DESC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_DESC_Private_Defines - * @{ - */ - -#define USBD_VID 0x0483 - -#define USBD_LANGID_STRING 0x409 -#define USBD_MANUFACTURER_STRING "FrSky" -#define USBD_SERIALNUMBER_FS_STRING "00000000001B" - - -#if defined(BOOT) - #define USBD_PID 0x5720 - #define USBD_PRODUCT_FS_STRING USB_NAME " Bootloader" - #define USBD_CONFIGURATION_FS_STRING "MSC Config" - #define USBD_INTERFACE_FS_STRING "MSC Interface" -#elif defined(USB_JOYSTICK) - #define USBD_PID 0x5710 - #define USBD_PRODUCT_FS_STRING USB_NAME " Joystick" - #define USBD_CONFIGURATION_FS_STRING "HID Config" - #define USBD_INTERFACE_FS_STRING "HID Interface" -#elif defined(USB_SERIAL) - #define USBD_PID 0x5740 // do not change, this ID is used by the ST USB driver for Windows - #define USBD_PRODUCT_FS_STRING USB_NAME " Serial Port" - #define USBD_CONFIGURATION_FS_STRING "VSP Config" - #define USBD_INTERFACE_FS_STRING "VSP Interface" -#elif defined(USB_MASS_STORAGE) - #define USBD_PID 0x5720 - #define USBD_PRODUCT_FS_STRING USB_NAME " Mass Storage" - #define USBD_CONFIGURATION_FS_STRING "MSC Config" - #define USBD_INTERFACE_FS_STRING "MSC Interface" -#endif - -const USBD_DEVICE USR_desc = -{ - USBD_USR_DeviceDescriptor, - USBD_USR_LangIDStrDescriptor, - USBD_USR_ManufacturerStrDescriptor, - USBD_USR_ProductStrDescriptor, - USBD_USR_SerialStrDescriptor, - USBD_USR_ConfigStrDescriptor, - USBD_USR_InterfaceStrDescriptor, -}; - -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN const uint8_t USBD_DeviceDesc[USB_SIZ_DEVICE_DESC] __ALIGN_END = -{ - USB_SIZ_DEVICE_DESC, /*bLength */ - USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/ - 0x00, /*bcdUSB */ - 0x02, - 0x00, /*bDeviceClass*/ - 0x00, /*bDeviceSubClass*/ - 0x00, /*bDeviceProtocol*/ - USB_OTG_MAX_EP0_SIZE, /*bMaxPacketSize*/ - LOBYTE(USBD_VID), /*idVendor*/ - HIBYTE(USBD_VID), /*idVendor*/ - LOBYTE(USBD_PID), /*idVendor*/ - HIBYTE(USBD_PID), /*idVendor*/ - 0x00, /*bcdDevice rel. 2.00*/ - 0x02, - USBD_IDX_MFC_STR, /*Index of manufacturer string*/ - USBD_IDX_PRODUCT_STR, /*Index of product string*/ - USBD_IDX_SERIAL_STR, /*Index of serial number string*/ - USBD_CFG_MAX_NUM /*bNumConfigurations*/ -}; /* USB_DeviceDescriptor */ - -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN const uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = -{ - USB_LEN_DEV_QUALIFIER_DESC, - USB_DESC_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x01, - 0x00, -}; - -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN const uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID] __ALIGN_END = -{ - USB_SIZ_STRING_LANGID, - USB_DESC_TYPE_STRING, - LOBYTE(USBD_LANGID_STRING), - HIBYTE(USBD_LANGID_STRING), -}; - -__ALIGN_BEGIN uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ] __ALIGN_END ; // modified by OpenTX - -/* -* @brief USBD_USR_DeviceDescriptor -* return the device descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length) -{ - *length = sizeof(USBD_DeviceDesc); - memcpy(USBD_StrDesc, USBD_DeviceDesc, *length); - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_LangIDStrDescriptor -* return the LangID string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length) -{ - *length = sizeof(USBD_LangIDDesc); - memcpy(USBD_StrDesc, USBD_LangIDDesc, *length); - return USBD_StrDesc; -} - - -/** -* @brief USBD_USR_ProductStrDescriptor -* return the product string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ProductStrDescriptor( uint8_t speed , uint16_t *length) -{ - USBD_GetString ((uint8_t*)USBD_PRODUCT_FS_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_ManufacturerStrDescriptor -* return the manufacturer string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ManufacturerStrDescriptor( uint8_t speed , uint16_t *length) -{ - USBD_GetString ((uint8_t*)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_SerialStrDescriptor -* return the serial number string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length) -{ - USBD_GetString ((uint8_t*)USBD_SERIALNUMBER_FS_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_ConfigStrDescriptor -* return the configuration string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length) -{ - USBD_GetString ((uint8_t *)USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - - -/** -* @brief USBD_USR_InterfaceStrDescriptor -* return the interface string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length) -{ - USBD_GetString ((uint8_t*)USBD_INTERFACE_FS_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_desc.h" + +#include + +#include "board.h" +#include "usbd_conf.h" +#include "usbd_core.h" +#include "usbd_req.h" +#include "usb_regs.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_DESC + * @brief USBD descriptors module + * @{ + */ + +/** @defgroup USBD_DESC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_DESC_Private_Defines + * @{ + */ + +#define USBD_VID 0x0483 + +#define USBD_LANGID_STRING 0x409 +#define USBD_MANUFACTURER_STRING "FrSky" +#define USBD_SERIALNUMBER_FS_STRING "00000000001B" + + +#if defined(BOOT) + #define USBD_PID 0x5720 + #define USBD_PRODUCT_FS_STRING USB_NAME " Bootloader" + #define USBD_CONFIGURATION_FS_STRING "MSC Config" + #define USBD_INTERFACE_FS_STRING "MSC Interface" +#elif defined(USB_JOYSTICK) + #define USBD_PID 0x5710 + #define USBD_PRODUCT_FS_STRING USB_NAME " Joystick" + #define USBD_CONFIGURATION_FS_STRING "HID Config" + #define USBD_INTERFACE_FS_STRING "HID Interface" +#elif defined(USB_SERIAL) + #define USBD_PID 0x5740 // do not change, this ID is used by the ST USB driver for Windows + #define USBD_PRODUCT_FS_STRING USB_NAME " Serial Port" + #define USBD_CONFIGURATION_FS_STRING "VSP Config" + #define USBD_INTERFACE_FS_STRING "VSP Interface" +#elif defined(USB_MASS_STORAGE) + #define USBD_PID 0x5720 + #define USBD_PRODUCT_FS_STRING USB_NAME " Mass Storage" + #define USBD_CONFIGURATION_FS_STRING "MSC Config" + #define USBD_INTERFACE_FS_STRING "MSC Interface" +#endif + +const USBD_DEVICE USR_desc = +{ + USBD_USR_DeviceDescriptor, + USBD_USR_LangIDStrDescriptor, + USBD_USR_ManufacturerStrDescriptor, + USBD_USR_ProductStrDescriptor, + USBD_USR_SerialStrDescriptor, + USBD_USR_ConfigStrDescriptor, + USBD_USR_InterfaceStrDescriptor, +}; + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN const uint8_t USBD_DeviceDesc[USB_SIZ_DEVICE_DESC] __ALIGN_END = +{ + USB_SIZ_DEVICE_DESC, /*bLength */ + USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/ + 0x00, /*bcdUSB */ + 0x02, + 0x00, /*bDeviceClass*/ + 0x00, /*bDeviceSubClass*/ + 0x00, /*bDeviceProtocol*/ + USB_OTG_MAX_EP0_SIZE, /*bMaxPacketSize*/ + LOBYTE(USBD_VID), /*idVendor*/ + HIBYTE(USBD_VID), /*idVendor*/ + LOBYTE(USBD_PID), /*idVendor*/ + HIBYTE(USBD_PID), /*idVendor*/ + 0x00, /*bcdDevice rel. 2.00*/ + 0x02, + USBD_IDX_MFC_STR, /*Index of manufacturer string*/ + USBD_IDX_PRODUCT_STR, /*Index of product string*/ + USBD_IDX_SERIAL_STR, /*Index of serial number string*/ + USBD_CFG_MAX_NUM /*bNumConfigurations*/ +}; /* USB_DeviceDescriptor */ + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN const uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +{ + USB_LEN_DEV_QUALIFIER_DESC, + USB_DESC_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +}; + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN const uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID] __ALIGN_END = +{ + USB_SIZ_STRING_LANGID, + USB_DESC_TYPE_STRING, + LOBYTE(USBD_LANGID_STRING), + HIBYTE(USBD_LANGID_STRING), +}; + +__ALIGN_BEGIN uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ] __ALIGN_END ; // modified by OpenTX + +/* +* @brief USBD_USR_DeviceDescriptor +* return the device descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length) +{ + *length = sizeof(USBD_DeviceDesc); + memcpy(USBD_StrDesc, USBD_DeviceDesc, *length); + return USBD_StrDesc; +} + +/** +* @brief USBD_USR_LangIDStrDescriptor +* return the LangID string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length) +{ + *length = sizeof(USBD_LangIDDesc); + memcpy(USBD_StrDesc, USBD_LangIDDesc, *length); + return USBD_StrDesc; +} + + +/** +* @brief USBD_USR_ProductStrDescriptor +* return the product string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_ProductStrDescriptor( uint8_t speed , uint16_t *length) +{ + USBD_GetString ((uint8_t*)USBD_PRODUCT_FS_STRING, USBD_StrDesc, length); + return USBD_StrDesc; +} + +/** +* @brief USBD_USR_ManufacturerStrDescriptor +* return the manufacturer string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_ManufacturerStrDescriptor( uint8_t speed , uint16_t *length) +{ + USBD_GetString ((uint8_t*)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + return USBD_StrDesc; +} + +/** +* @brief USBD_USR_SerialStrDescriptor +* return the serial number string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length) +{ + USBD_GetString ((uint8_t*)USBD_SERIALNUMBER_FS_STRING, USBD_StrDesc, length); + return USBD_StrDesc; +} + +/** +* @brief USBD_USR_ConfigStrDescriptor +* return the configuration string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length) +{ + USBD_GetString ((uint8_t *)USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length); + return USBD_StrDesc; +} + + +/** +* @brief USBD_USR_InterfaceStrDescriptor +* return the interface string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length) +{ + USBD_GetString ((uint8_t*)USBD_INTERFACE_FS_STRING, USBD_StrDesc, length); + return USBD_StrDesc; +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/targets/common/arm/stm32/usbd_desc.h b/radio/src/targets/common/arm/stm32/usbd_desc.h index 171102a8e..5f25b0759 100644 --- a/radio/src/targets/common/arm/stm32/usbd_desc.h +++ b/radio/src/targets/common/arm/stm32/usbd_desc.h @@ -18,97 +18,97 @@ * GNU General Public License for more details. */ -/* Define to prevent recursive inclusion -------------------------------------*/ - +/* Define to prevent recursive inclusion -------------------------------------*/ + #ifndef _USBD_DESC_H_ #define _USBD_DESC_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usbd_def.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_DESC - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_DESC_Exported_Defines - * @{ - */ -#define USB_DEVICE_DESCRIPTOR_TYPE 0x01 -#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 -#define USB_STRING_DESCRIPTOR_TYPE 0x03 -#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 -#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 -#define USB_SIZ_DEVICE_DESC 18 -#define USB_SIZ_STRING_LANGID 4 - -/** - * @} - */ - - -/** @defgroup USBD_DESC_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_DESC_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_Variables - * @{ - */ -extern const uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; -extern uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ]; -extern const uint8_t USBD_OtherSpeedCfgDesc[USB_LEN_CFG_DESC]; -extern const uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]; -extern const uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID]; -extern const USBD_DEVICE USR_desc; -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_FunctionsPrototype - * @{ - */ - - -uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ManufacturerStrDescriptor ( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ProductStrDescriptor ( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length); - -#ifdef USB_SUPPORT_USER_STRING_DESC -uint8_t * USBD_USR_USRStringDesc (uint8_t speed, uint8_t idx , uint16_t *length); -#endif /* USB_SUPPORT_USER_STRING_DESC */ - -/** - * @} - */ - + +/* Includes ------------------------------------------------------------------*/ +#include "usb_core.h" +#include "usbd_def.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_DESC + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_DESC_Exported_Defines + * @{ + */ +#define USB_DEVICE_DESCRIPTOR_TYPE 0x01 +#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 +#define USB_STRING_DESCRIPTOR_TYPE 0x03 +#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 +#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 +#define USB_SIZ_DEVICE_DESC 18 +#define USB_SIZ_STRING_LANGID 4 + +/** + * @} + */ + + +/** @defgroup USBD_DESC_Exported_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_DESC_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_Variables + * @{ + */ +extern const uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; +extern uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ]; +extern const uint8_t USBD_OtherSpeedCfgDesc[USB_LEN_CFG_DESC]; +extern const uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]; +extern const uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID]; +extern const USBD_DEVICE USR_desc; +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_FunctionsPrototype + * @{ + */ + + +uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_ManufacturerStrDescriptor ( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_ProductStrDescriptor ( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length); + +#ifdef USB_SUPPORT_USER_STRING_DESC +uint8_t * USBD_USR_USRStringDesc (uint8_t speed, uint8_t idx , uint16_t *length); +#endif /* USB_SUPPORT_USER_STRING_DESC */ + +/** + * @} + */ + #endif // _USBD_DESC_H_ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/targets/common/arm/stm32/usbd_hid_joystick.c b/radio/src/targets/common/arm/stm32/usbd_hid_joystick.c index 8d3134427..673e7150c 100644 --- a/radio/src/targets/common/arm/stm32/usbd_hid_joystick.c +++ b/radio/src/targets/common/arm/stm32/usbd_hid_joystick.c @@ -1,455 +1,455 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_desc.h" -#include "usbd_hid_core.h" -#include "usbd_req.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_HID - * @brief usbd core module - * @{ - */ - -/** @defgroup USBD_HID_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_HID_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_HID_Private_Macros - * @{ - */ -/** - * @} - */ - - - - -/** @defgroup USBD_HID_Private_FunctionPrototypes - * @{ - */ - - -static uint8_t USBD_HID_Init (void *pdev, - uint8_t cfgidx); - -static uint8_t USBD_HID_DeInit (void *pdev, - uint8_t cfgidx); - -static uint8_t USBD_HID_Setup (void *pdev, - USB_SETUP_REQ *req); - -static const uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length); - -static uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum); -/** - * @} - */ - - - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* - This USB HID endpoint report description defines a device with: - * 24 digital buttons - * 8 analog axes with 8bit resolution - - Repot packet described as C struct is: - - struct { - uint8_t buttons1; //bit 0 - button 1, bit 1 - button 2, ..., mapped to channels 9-16, on if channel > 0 - uint8_t buttons2; // mapped to channels 17-24, on if channel > 0 - uint8_t buttons3; // mapped to channels 25-32, on if channel > 0 - uint8_t X; //analog value, mapped to channel 1 - uint8_t Y; //analog value, mapped to channel 2 - uint8_t Z; //analog value, mapped to channel 3 - uint8_t Rx; //analog value, mapped to channel 4 - uint8_t Ry //analog value, mapped to channel 5 - uint8_t Rz; //analog value, mapped to channel 6 - uint8_t S1; //analog value, mapped to channel 7 - uint8_t S2; //analog value, mapped to channel 8 - } -*/ -__ALIGN_BEGIN static const uint8_t HID_JOYSTICK_ReportDesc[] __ALIGN_END = -{ - 0x05, 0x01, // USAGE_PAGE (Generic Desktop) - 0x09, 0x05, // USAGE (Game Pad) - 0xa1, 0x01, // COLLECTION (Application) - 0xa1, 0x00, // COLLECTION (Physical) - 0x05, 0x09, // USAGE_PAGE (Button) - 0x19, 0x01, // USAGE_MINIMUM (Button 1) - 0x29, 0x18, // USAGE_MAXIMUM (Button 24) - 0x15, 0x00, // LOGICAL_MINIMUM (0) - 0x25, 0x01, // LOGICAL_MAXIMUM (1) - 0x95, 0x18, // REPORT_COUNT (24) - 0x75, 0x01, // REPORT_SIZE (1) - 0x81, 0x02, // INPUT (Data,Var,Abs) - 0x05, 0x01, // USAGE_PAGE (Generic Desktop) - 0x09, 0x30, // USAGE (X) - 0x09, 0x31, // USAGE (Y) - 0x09, 0x32, // USAGE (Z) - 0x09, 0x33, // USAGE (Rx) - 0x09, 0x34, // USAGE (Ry) - 0x09, 0x35, // USAGE (Rz) - 0x09, 0x36, // USAGE (Slider) - 0x09, 0x36, // USAGE (Slider) - 0x15, 0x81, // LOGICAL_MINIMUM (-127) - 0x25, 0x7f, // LOGICAL_MAXIMUM (127) - 0x75, 0x08, // REPORT_SIZE (8) - 0x95, 0x08, // REPORT_COUNT (8) - 0x81, 0x02, // INPUT (Data,Var,Abs) - 0xc0, // END_COLLECTION - 0xc0 // END_COLLECTION -}; - - -/** @defgroup USBD_HID_Private_Variables - * @{ - */ - -const USBD_Class_cb_TypeDef USBD_HID_cb = -{ - USBD_HID_Init, - USBD_HID_DeInit, - USBD_HID_Setup, - NULL, /*EP0_TxSent*/ - NULL, /*EP0_RxReady*/ - USBD_HID_DataIn, /*DataIn*/ - NULL, /*DataOut*/ - NULL, /*SOF */ - NULL, - NULL, - USBD_HID_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_HID_GetCfgDesc, /* use same config as per FS */ -#endif -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_AltSet __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_Protocol __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_IdleState __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB HID device Configuration Descriptor */ -__ALIGN_BEGIN static const uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ - USB_HID_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ - 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ - 0x00, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x00 /*0x01*/, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x00 /*0x02*/, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ - 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - sizeof(HID_JOYSTICK_ReportDesc),/*wItemLength: Total length of Report descriptor*/ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ - - HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */ - 0x00, - 0x0A, /*bInterval: Polling Interval (10 ms)*/ - /* 34 */ -} ; - - - -static uint8_t ReportSent; - -/** - * @} - */ - -/** @defgroup USBD_HID_Private_Functions - * @{ - */ - -/** - * @brief USBD_HID_Init - * Initialize the HID interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_HID_Init (void *pdev, - uint8_t cfgidx) -{ - - /* Open EP IN */ - DCD_EP_Open(pdev, - HID_IN_EP, - HID_IN_PACKET, - USB_OTG_EP_INT); - - /* Open EP OUT */ - DCD_EP_Open(pdev, - HID_OUT_EP, - HID_OUT_PACKET, - USB_OTG_EP_INT); - - ReportSent = 1; - return USBD_OK; -} - -/** - * @brief USBD_HID_Init - * DeInitialize the HID layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_HID_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* Close HID EPs */ - DCD_EP_Close (pdev , HID_IN_EP); - DCD_EP_Close (pdev , HID_OUT_EP); - - ReportSent = 1; - return USBD_OK; -} - -/** - * @brief USBD_HID_Setup - * Handle the HID specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t USBD_HID_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len = 0; - const uint8_t *pbuf = NULL; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - - - case HID_REQ_SET_PROTOCOL: - USBD_HID_Protocol = (uint8_t)(req->wValue); - break; - - case HID_REQ_GET_PROTOCOL: - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_Protocol, - 1); - break; - - case HID_REQ_SET_IDLE: - USBD_HID_IdleState = (uint8_t)(req->wValue >> 8); - break; - - case HID_REQ_GET_IDLE: - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_IdleState, - 1); - break; - - default: - USBD_CtlError (pdev, req); - return USBD_FAIL; - } - break; - - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - if( req->wValue >> 8 == HID_REPORT_DESC) - { - len = MIN(sizeof(HID_JOYSTICK_ReportDesc) , req->wLength); - pbuf = HID_JOYSTICK_ReportDesc; // wiiccReportDescriptor; // - } - else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE) - { - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pbuf = USBD_HID_Desc; -#else - pbuf = USBD_HID_CfgDesc + 0x12; -#endif - len = MIN(USB_HID_DESC_SIZ , req->wLength); - } - - USBD_CtlSendData (pdev, - pbuf, - len); - - break; - - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - USBD_HID_AltSet = (uint8_t)(req->wValue); - break; - } - } - return USBD_OK; -} - - -/** - * @brief USBD_HID_SendReport - * Send HID Report if TX buffer is free and USB device is configured. - * @param pdev: device instance - * @param buff: pointer to report, if this parameter is NULL then function just test if new buffer can be sent - * @retval status - */ -uint8_t USBD_HID_SendReport(USB_OTG_CORE_HANDLE *pdev, uint8_t * report, uint16_t len) -{ - if (pdev->dev.device_status == USB_OTG_CONFIGURED) { - if (ReportSent) { - if (report) { - ReportSent = 0; - DCD_EP_Tx (pdev, HID_IN_EP, report, len); - } - return USBD_OK; - } - } - return USBD_FAIL; -} - -/** - * @brief USBD_HID_GetCfgDesc - * return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static const uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (USBD_HID_CfgDesc); - return USBD_HID_CfgDesc; -} - -/** - * @brief USBD_HID_DataIn - * handle data IN Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - - This function is called when buffer has been sent over the USB. - The TX buffer is now empty and can be filled with new data. - */ -static uint8_t USBD_HID_DataIn (void *pdev, - uint8_t epnum) -{ - ReportSent = 1; - /* Ensure that the FIFO is empty before a new transfer, this condition could - be caused by a new transfer before the end of the previous transfer */ - DCD_EP_Flush(pdev, HID_IN_EP); - return USBD_OK; -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_desc.h" +#include "usbd_hid_core.h" +#include "usbd_req.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_HID + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_HID_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_HID_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_HID_Private_Macros + * @{ + */ +/** + * @} + */ + + + + +/** @defgroup USBD_HID_Private_FunctionPrototypes + * @{ + */ + + +static uint8_t USBD_HID_Init (void *pdev, + uint8_t cfgidx); + +static uint8_t USBD_HID_DeInit (void *pdev, + uint8_t cfgidx); + +static uint8_t USBD_HID_Setup (void *pdev, + USB_SETUP_REQ *req); + +static const uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length); + +static uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum); +/** + * @} + */ + + + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +/* + This USB HID endpoint report description defines a device with: + * 24 digital buttons + * 8 analog axes with 8bit resolution + + Repot packet described as C struct is: + + struct { + uint8_t buttons1; //bit 0 - button 1, bit 1 - button 2, ..., mapped to channels 9-16, on if channel > 0 + uint8_t buttons2; // mapped to channels 17-24, on if channel > 0 + uint8_t buttons3; // mapped to channels 25-32, on if channel > 0 + uint8_t X; //analog value, mapped to channel 1 + uint8_t Y; //analog value, mapped to channel 2 + uint8_t Z; //analog value, mapped to channel 3 + uint8_t Rx; //analog value, mapped to channel 4 + uint8_t Ry //analog value, mapped to channel 5 + uint8_t Rz; //analog value, mapped to channel 6 + uint8_t S1; //analog value, mapped to channel 7 + uint8_t S2; //analog value, mapped to channel 8 + } +*/ +__ALIGN_BEGIN static const uint8_t HID_JOYSTICK_ReportDesc[] __ALIGN_END = +{ + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x05, // USAGE (Game Pad) + 0xa1, 0x01, // COLLECTION (Application) + 0xa1, 0x00, // COLLECTION (Physical) + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM (Button 1) + 0x29, 0x18, // USAGE_MAXIMUM (Button 24) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x95, 0x18, // REPORT_COUNT (24) + 0x75, 0x01, // REPORT_SIZE (1) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x30, // USAGE (X) + 0x09, 0x31, // USAGE (Y) + 0x09, 0x32, // USAGE (Z) + 0x09, 0x33, // USAGE (Rx) + 0x09, 0x34, // USAGE (Ry) + 0x09, 0x35, // USAGE (Rz) + 0x09, 0x36, // USAGE (Slider) + 0x09, 0x36, // USAGE (Slider) + 0x15, 0x81, // LOGICAL_MINIMUM (-127) + 0x25, 0x7f, // LOGICAL_MAXIMUM (127) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x08, // REPORT_COUNT (8) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0xc0, // END_COLLECTION + 0xc0 // END_COLLECTION +}; + + +/** @defgroup USBD_HID_Private_Variables + * @{ + */ + +const USBD_Class_cb_TypeDef USBD_HID_cb = +{ + USBD_HID_Init, + USBD_HID_DeInit, + USBD_HID_Setup, + NULL, /*EP0_TxSent*/ + NULL, /*EP0_RxReady*/ + USBD_HID_DataIn, /*DataIn*/ + NULL, /*DataOut*/ + NULL, /*SOF */ + NULL, + NULL, + USBD_HID_GetCfgDesc, +#ifdef USB_OTG_HS_CORE + USBD_HID_GetCfgDesc, /* use same config as per FS */ +#endif +}; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_AltSet __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_Protocol __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_IdleState __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +/* USB HID device Configuration Descriptor */ +__ALIGN_BEGIN static const uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_HID_CONFIG_DESC_SIZ, + /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /*bNumInterfaces: 1 interface*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x00, /*iConfiguration: Index of string descriptor describing + the configuration*/ + 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /*bLength: Interface Descriptor size*/ + USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ + 0x00, /*bInterfaceNumber: Number of Interface*/ + 0x00, /*bAlternateSetting: Alternate setting*/ + 0x01, /*bNumEndpoints*/ + 0x03, /*bInterfaceClass: HID*/ + 0x00 /*0x01*/, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ + 0x00 /*0x02*/, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ + 0, /*iInterface: Index of string descriptor*/ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /*bLength: HID Descriptor size*/ + HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ + 0x11, /*bcdHID: HID Class Spec release number*/ + 0x01, + 0x00, /*bCountryCode: Hardware target country*/ + 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ + 0x22, /*bDescriptorType*/ + sizeof(HID_JOYSTICK_ReportDesc),/*wItemLength: Total length of Report descriptor*/ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /*bLength: Endpoint Descriptor size*/ + USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ + + HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ + 0x03, /*bmAttributes: Interrupt endpoint*/ + HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /*bInterval: Polling Interval (10 ms)*/ + /* 34 */ +} ; + + + +static uint8_t ReportSent; + +/** + * @} + */ + +/** @defgroup USBD_HID_Private_Functions + * @{ + */ + +/** + * @brief USBD_HID_Init + * Initialize the HID interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_HID_Init (void *pdev, + uint8_t cfgidx) +{ + + /* Open EP IN */ + DCD_EP_Open(pdev, + HID_IN_EP, + HID_IN_PACKET, + USB_OTG_EP_INT); + + /* Open EP OUT */ + DCD_EP_Open(pdev, + HID_OUT_EP, + HID_OUT_PACKET, + USB_OTG_EP_INT); + + ReportSent = 1; + return USBD_OK; +} + +/** + * @brief USBD_HID_Init + * DeInitialize the HID layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_HID_DeInit (void *pdev, + uint8_t cfgidx) +{ + /* Close HID EPs */ + DCD_EP_Close (pdev , HID_IN_EP); + DCD_EP_Close (pdev , HID_OUT_EP); + + ReportSent = 1; + return USBD_OK; +} + +/** + * @brief USBD_HID_Setup + * Handle the HID specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_HID_Setup (void *pdev, + USB_SETUP_REQ *req) +{ + uint16_t len = 0; + const uint8_t *pbuf = NULL; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + + + case HID_REQ_SET_PROTOCOL: + USBD_HID_Protocol = (uint8_t)(req->wValue); + break; + + case HID_REQ_GET_PROTOCOL: + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_HID_Protocol, + 1); + break; + + case HID_REQ_SET_IDLE: + USBD_HID_IdleState = (uint8_t)(req->wValue >> 8); + break; + + case HID_REQ_GET_IDLE: + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_HID_IdleState, + 1); + break; + + default: + USBD_CtlError (pdev, req); + return USBD_FAIL; + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + if( req->wValue >> 8 == HID_REPORT_DESC) + { + len = MIN(sizeof(HID_JOYSTICK_ReportDesc) , req->wLength); + pbuf = HID_JOYSTICK_ReportDesc; // wiiccReportDescriptor; // + } + else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE) + { + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + pbuf = USBD_HID_Desc; +#else + pbuf = USBD_HID_CfgDesc + 0x12; +#endif + len = MIN(USB_HID_DESC_SIZ , req->wLength); + } + + USBD_CtlSendData (pdev, + pbuf, + len); + + break; + + case USB_REQ_GET_INTERFACE : + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_HID_AltSet, + 1); + break; + + case USB_REQ_SET_INTERFACE : + USBD_HID_AltSet = (uint8_t)(req->wValue); + break; + } + } + return USBD_OK; +} + + +/** + * @brief USBD_HID_SendReport + * Send HID Report if TX buffer is free and USB device is configured. + * @param pdev: device instance + * @param buff: pointer to report, if this parameter is NULL then function just test if new buffer can be sent + * @retval status + */ +uint8_t USBD_HID_SendReport(USB_OTG_CORE_HANDLE *pdev, uint8_t * report, uint16_t len) +{ + if (pdev->dev.device_status == USB_OTG_CONFIGURED) { + if (ReportSent) { + if (report) { + ReportSent = 0; + DCD_EP_Tx (pdev, HID_IN_EP, report, len); + } + return USBD_OK; + } + } + return USBD_FAIL; +} + +/** + * @brief USBD_HID_GetCfgDesc + * return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static const uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_HID_CfgDesc); + return USBD_HID_CfgDesc; +} + +/** + * @brief USBD_HID_DataIn + * handle data IN Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + + This function is called when buffer has been sent over the USB. + The TX buffer is now empty and can be filled with new data. + */ +static uint8_t USBD_HID_DataIn (void *pdev, + uint8_t epnum) +{ + ReportSent = 1; + /* Ensure that the FIFO is empty before a new transfer, this condition could + be caused by a new transfer before the end of the previous transfer */ + DCD_EP_Flush(pdev, HID_IN_EP); + return USBD_OK; +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/targets/common/arm/stm32/usbd_storage_msd.cpp b/radio/src/targets/common/arm/stm32/usbd_storage_msd.cpp index 3a5854d2f..862037978 100644 --- a/radio/src/targets/common/arm/stm32/usbd_storage_msd.cpp +++ b/radio/src/targets/common/arm/stm32/usbd_storage_msd.cpp @@ -1,771 +1,771 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Includes ------------------------------------------------------------------*/ -#include "opentx.h" -#include "FatFs/diskio.h" - -#if defined(__cplusplus) && !defined(SIMU) -extern "C" { -#endif - -#include "usbd_msc_mem.h" -#include "usb_conf.h" - -enum MassstorageLuns { - STORAGE_SDCARD_LUN, -#if defined(EEPROM) - STORAGE_EEPROM_LUN, -#endif - STORAGE_LUN_NBR -}; - -/* USB Mass storage Standard Inquiry Data */ -const unsigned char STORAGE_Inquirydata[] = { //36 - /* LUN 0 */ - 0x00, - 0x80, - 0x02, - 0x02, - (USBD_STD_INQUIRY_LENGTH - 5), - 0x00, - 0x00, - 0x00, - USB_MANUFACTURER, /* Manufacturer : 8 bytes */ - USB_PRODUCT, /* Product : 16 Bytes */ - 'R', 'a', 'd', 'i', 'o', ' ', ' ', ' ', - '1', '.', '0', '0', /* Version : 4 Bytes */ -#if defined(EEPROM) - /* LUN 1 */ - 0x00, - 0x80, - 0x02, - 0x02, - (USBD_STD_INQUIRY_LENGTH - 5), - 0x00, - 0x00, - 0x00, - USB_MANUFACTURER, /* Manufacturer : 8 bytes */ - USB_PRODUCT, /* Product : 16 Bytes */ - 'R', 'a', 'd', 'i', 'o', ' ', ' ', ' ', - '1', '.', '0' ,'0', /* Version : 4 Bytes */ -#endif -}; - -#if defined(EEPROM) -int32_t fat12Write(const uint8_t * buffer, uint16_t sector, uint16_t count); -int32_t fat12Read(uint8_t * buffer, uint16_t sector, uint16_t count ); -#endif - -int8_t STORAGE_Init (uint8_t lun); - -int8_t STORAGE_GetCapacity (uint8_t lun, - uint32_t *block_num, - uint32_t *block_size); - -int8_t STORAGE_IsReady (uint8_t lun); - -int8_t STORAGE_IsWriteProtected (uint8_t lun); - -int8_t STORAGE_Read (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len); - -int8_t STORAGE_Write (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len); - -int8_t STORAGE_GetMaxLun (void); - -const USBD_STORAGE_cb_TypeDef USBD_MICRO_SDIO_fops = // modified my OpenTX -{ - STORAGE_Init, - STORAGE_GetCapacity, - STORAGE_IsReady, - STORAGE_IsWriteProtected, - STORAGE_Read, - STORAGE_Write, - STORAGE_GetMaxLun, - (int8_t *)STORAGE_Inquirydata, -}; - -const USBD_STORAGE_cb_TypeDef * const USBD_STORAGE_fops = &USBD_MICRO_SDIO_fops; // modified my OpenTX - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -int8_t STORAGE_Init (uint8_t lun) -{ - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority =0; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - -/* TODO if no SD ... if( SD_Init() != 0) - { - return (-1); - } -*/ - return (0); -} - -/** - * @brief return medium capacity and block size - * @param lun : logical unit number - * @param block_num : number of physical block - * @param block_size : size of a physical block - * @retval Status - */ -int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint32_t *block_size) -{ -#if defined(EEPROM) - if (lun == STORAGE_EEPROM_LUN) { - *block_size = BLOCK_SIZE; - *block_num = 3 + EEPROM_SIZE/BLOCK_SIZE + FLASHSIZE/BLOCK_SIZE; - return 0; - } -#endif - - if (!SD_CARD_PRESENT()) - return -1; - - *block_size = BLOCK_SIZE; - - static DWORD sector_count = 0; - if (sector_count == 0) { - if (disk_ioctl(0, GET_SECTOR_COUNT, §or_count) != RES_OK) { - sector_count = 0; - return -1; - } - } - - *block_num = sector_count; - - return 0; -} - -uint8_t lunReady[STORAGE_LUN_NBR]; - -void usbPluggedIn() -{ - lunReady[STORAGE_SDCARD_LUN] = 1; -#if defined(EEPROM) - lunReady[STORAGE_EEPROM_LUN] = 1; -#endif -} - -/** - * @brief check whether the medium is ready - * @param lun : logical unit number - * @retval Status - */ -int8_t STORAGE_IsReady (uint8_t lun) -{ -#if defined(EEPROM) - if (lun == STORAGE_EEPROM_LUN) { - return (lunReady[STORAGE_EEPROM_LUN] != 0) ? 0 : -1; - } -#endif - - return (lunReady[STORAGE_SDCARD_LUN] != 0 && SD_CARD_PRESENT()) ? 0 : -1; -} - -/** - * @brief check whether the medium is write-protected - * @param lun : logical unit number - * @retval Status - */ -int8_t STORAGE_IsWriteProtected (uint8_t lun) -{ - return 0; -} - -/** - * @brief Read data from the medium - * @param lun : logical unit number - * @param buf : Pointer to the buffer to save data - * @param blk_addr : address of 1st block to be read - * @param blk_len : nmber of blocks to be read - * @retval Status - */ - -int8_t STORAGE_Read (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len) -{ - WATCHDOG_SUSPEND(100/*1s*/); - -#if defined(EEPROM) - if (lun == STORAGE_EEPROM_LUN) { - return (fat12Read(buf, blk_addr, blk_len) == 0) ? 0 : -1; - } -#endif - - // read without cache - return (__disk_read(0, buf, blk_addr, blk_len) == RES_OK) ? 0 : -1; -} -/** - * @brief Write data to the medium - * @param lun : logical unit number - * @param buf : Pointer to the buffer to write from - * @param blk_addr : address of 1st block to be written - * @param blk_len : nmber of blocks to be read - * @retval Status - */ - -int8_t STORAGE_Write (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len) -{ - WATCHDOG_SUSPEND(100/*1s*/); - -#if defined(EEPROM) - if (lun == STORAGE_EEPROM_LUN) { - return (fat12Write(buf, blk_addr, blk_len) == 0) ? 0 : -1; - } -#endif - - // write without cache - return (__disk_write(0, buf, blk_addr, blk_len) == RES_OK) ? 0 : -1; -} - -/** - * @brief Return number of supported logical unit - * @param None - * @retval number of logical unit - */ - -int8_t STORAGE_GetMaxLun (void) -{ - return STORAGE_LUN_NBR - 1; -} - -#if defined(EEPROM) -//------------------------------------------------------------------------------ -/** - * FAT12 boot sector partition. - */ -const char g_FATboot[BLOCK_SIZE] = -{ - 0xeb, 0x3c, 0x90, // Jump instruction. - 0x39, 0x58, 0x20, 0x54, 0x45, 0x41, 0x4D, 0x00, // OEM Name - 0x00, 0x02, // Bytes per sector - 0x08, // Sectors per FS cluster. - 0x01, 0x00, // Reserved sector count - - 0x01, // Number of FATs - 0x10, 0x00, // Number of root directory entries - 3+(EEPROM_SIZE/BLOCK_SIZE), (FLASHSIZE/BLOCK_SIZE)>>8, // Total sectors - 0xf8, // Media descriptor - 0x01, 0x00, // Sectors per FAT table - 0x20, 0x00, // Sectors per track - 0x40, 0x00, // Number of heads - 0x00, 0x00, 0x00, 0x00, // Number of hidden sectors - - 0x00, 0x00, 0x00, 0x00, // Large number of sectors. - 0x00, // Physical drive number - 0x00, // Reserved - 0x29, // Extended boot signature - 0xCE, 0xFA, 0x5C, 0xD1, // Disk ID (serial number) - 0x56, 0x49, 0x52, 0x54, 0x46, 0x53, 0x20, 0x20, 0x20, 0x20, 0x20, // Volume label - 0x46, 0x41, 0x54, 0x31, 0x32, 0x20, 0x20, 0x20, // FAT file system type - 0x00, 0x00, // OS boot code - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa -}; - -#if defined(REV4a) -const char g_FAT[BLOCK_SIZE] = -{ - 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xA0, 0x00, 0x0B, - 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0xF0, 0xFF, 0x13, 0x40, 0x01, 0x15, 0x60, - 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, - 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, - 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, - 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, - 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, - 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, - 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, - 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, - 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, - 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, - 0x81, 0x20, 0x08, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xA0, 0x08, 0x8B, - 0xC0, 0x08, 0x8D, 0xE0, 0x08, 0x8F, 0x00, 0x09, 0x91, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; -#else -const char g_FAT[BLOCK_SIZE] = -{ - 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xF0, 0xFF, 0x0B, - 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60, - 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, - 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, - 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, - 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, - 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, - 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, - 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, - 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, - 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, - 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, - 0x81, 0x20, 0x08, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; -#endif - -// File Attributes -// 0 0x01 Read Only. -// 1 0x02 Hidden. -// 2 0x04 System. -// 3 0x08 Volume Label. -// 4 0x10 Subdirectory. -// 5 0x20 Archive. -// 6 0x40 Device. -// 7 0x80 Reserved. - -typedef struct -{ - uint8_t name[8]; - uint8_t ext[3]; - uint8_t attribute; - uint8_t reserved; - uint8_t create_time_ms; - uint16_t create_time; - uint16_t create_date; - uint16_t access_date; - uint16_t ea_index; - uint16_t modify_time; - uint16_t modify_date; - uint16_t start_cluster; - uint32_t file_size; -} FATDirEntry_t; - -// First 16 FAT root directory entries (1 sector) -const FATDirEntry_t g_DIRroot[16] = -{ - { - { USB_PRODUCT }, - { ' ', ' ', ' '}, - 0x08, // Volume - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { 'E', 'E', 'P', 'R', 'O', 'M', ' ', ' '}, - { 'B', 'I', 'N'}, - 0x20, // Archive - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0002, - EEPROM_SIZE - }, - { - { 'F', 'I', 'R', 'M', 'W', 'A', 'R', 'E'}, - { 'B', 'I', 'N'}, - 0x20, // Archive - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0002 + (EEPROM_SIZE/BLOCK_SIZE)/8, - FLASHSIZE - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, -}; - -// count is number of 512 byte sectors -int32_t fat12Read(uint8_t * buffer, uint16_t sector, uint16_t count) -{ - while(count) { - if (sector == 0) { - memcpy(buffer, g_FATboot, BLOCK_SIZE ) ; - } - else if (sector == 1/*Reserved sector count*/) { - // FAT table. - memcpy(buffer, g_FAT, BLOCK_SIZE); - } - else if (sector == 2) { - memcpy(buffer, g_DIRroot, BLOCK_SIZE ) ; - } - else if (sector < 3 + (EEPROM_SIZE/BLOCK_SIZE)) { - eepromReadBlock(buffer, (sector-3)*BLOCK_SIZE, BLOCK_SIZE); - } - else if (sector < 3 + (EEPROM_SIZE/BLOCK_SIZE) + (FLASHSIZE/BLOCK_SIZE)) { - uint32_t address; - address = sector - 3 - (EEPROM_SIZE/BLOCK_SIZE); - address *= BLOCK_SIZE; - address += FIRMWARE_ADDRESS; - memcpy(buffer, (uint8_t *)address, BLOCK_SIZE); - } - buffer += BLOCK_SIZE ; - sector++ ; - count-- ; - } - return 0 ; -} - -int32_t fat12Write(const uint8_t * buffer, uint16_t sector, uint16_t count) -{ - enum FatWriteOperation { - FATWRITE_NONE, - FATWRITE_EEPROM, - FATWRITE_FIRMWARE - }; - - static uint8_t operation = FATWRITE_NONE; - - TRACE("FAT12 Write(sector=%d, count=%d)", sector, count); - - if (sector < 3) { - // reserved, read-only - } - else if (sector < 3 + (EEPROM_SIZE/BLOCK_SIZE)) { - // eeprom - while (count) { - if (operation == FATWRITE_NONE && isEepromStart(buffer)) { - TRACE("EEPROM start found in sector %d", sector); - operation = FATWRITE_EEPROM; - } - if (operation == FATWRITE_EEPROM) { - eepromWriteBlock((uint8_t *)buffer, (sector-3)*BLOCK_SIZE, BLOCK_SIZE); - } - buffer += BLOCK_SIZE; - sector++; - count--; - if (sector-3 >= (EEPROM_SIZE/BLOCK_SIZE)) { - TRACE("EEPROM end written at sector %d", sector-1); - operation = FATWRITE_NONE; - } - } - } - else if (sector < 3 + (EEPROM_SIZE/BLOCK_SIZE) + (FLASHSIZE/BLOCK_SIZE)) { - // firmware - uint32_t address; - address = sector - 3 - (EEPROM_SIZE/BLOCK_SIZE); - address *= BLOCK_SIZE; - address += FIRMWARE_ADDRESS; - while (count) { - for (uint32_t i=0; i= FIRMWARE_ADDRESS+BOOTLOADER_SIZE/*protect bootloader*/ && address <= FIRMWARE_ADDRESS+FLASHSIZE-FLASH_PAGESIZE) { - if (address == FIRMWARE_ADDRESS+BOOTLOADER_SIZE && isFirmwareStart(buffer)) { - TRACE("FIRMWARE start found in sector %d", sector); - operation = FATWRITE_FIRMWARE; - } - if (operation == FATWRITE_FIRMWARE) { - flashWrite((uint32_t *)address, (uint32_t *)buffer); - } - } - address += FLASH_PAGESIZE; - buffer += FLASH_PAGESIZE; - } - sector++; - count--; - if (sector-3-(EEPROM_SIZE/BLOCK_SIZE) >= (FLASHSIZE/BLOCK_SIZE)) { - TRACE("FIRMWARE end written at sector %d", sector-1); - operation = FATWRITE_NONE; - } - } - } - return 0 ; -} -#endif +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "opentx.h" +#include "FatFs/diskio.h" + +#if defined(__cplusplus) && !defined(SIMU) +extern "C" { +#endif + +#include "usbd_msc_mem.h" +#include "usb_conf.h" + +enum MassstorageLuns { + STORAGE_SDCARD_LUN, +#if defined(EEPROM) + STORAGE_EEPROM_LUN, +#endif + STORAGE_LUN_NBR +}; + +/* USB Mass storage Standard Inquiry Data */ +const unsigned char STORAGE_Inquirydata[] = { //36 + /* LUN 0 */ + 0x00, + 0x80, + 0x02, + 0x02, + (USBD_STD_INQUIRY_LENGTH - 5), + 0x00, + 0x00, + 0x00, + USB_MANUFACTURER, /* Manufacturer : 8 bytes */ + USB_PRODUCT, /* Product : 16 Bytes */ + 'R', 'a', 'd', 'i', 'o', ' ', ' ', ' ', + '1', '.', '0', '0', /* Version : 4 Bytes */ +#if defined(EEPROM) + /* LUN 1 */ + 0x00, + 0x80, + 0x02, + 0x02, + (USBD_STD_INQUIRY_LENGTH - 5), + 0x00, + 0x00, + 0x00, + USB_MANUFACTURER, /* Manufacturer : 8 bytes */ + USB_PRODUCT, /* Product : 16 Bytes */ + 'R', 'a', 'd', 'i', 'o', ' ', ' ', ' ', + '1', '.', '0' ,'0', /* Version : 4 Bytes */ +#endif +}; + +#if defined(EEPROM) +int32_t fat12Write(const uint8_t * buffer, uint16_t sector, uint16_t count); +int32_t fat12Read(uint8_t * buffer, uint16_t sector, uint16_t count ); +#endif + +int8_t STORAGE_Init (uint8_t lun); + +int8_t STORAGE_GetCapacity (uint8_t lun, + uint32_t *block_num, + uint32_t *block_size); + +int8_t STORAGE_IsReady (uint8_t lun); + +int8_t STORAGE_IsWriteProtected (uint8_t lun); + +int8_t STORAGE_Read (uint8_t lun, + uint8_t *buf, + uint32_t blk_addr, + uint16_t blk_len); + +int8_t STORAGE_Write (uint8_t lun, + uint8_t *buf, + uint32_t blk_addr, + uint16_t blk_len); + +int8_t STORAGE_GetMaxLun (void); + +const USBD_STORAGE_cb_TypeDef USBD_MICRO_SDIO_fops = // modified my OpenTX +{ + STORAGE_Init, + STORAGE_GetCapacity, + STORAGE_IsReady, + STORAGE_IsWriteProtected, + STORAGE_Read, + STORAGE_Write, + STORAGE_GetMaxLun, + (int8_t *)STORAGE_Inquirydata, +}; + +const USBD_STORAGE_cb_TypeDef * const USBD_STORAGE_fops = &USBD_MICRO_SDIO_fops; // modified my OpenTX + +#if defined(__cplusplus) && !defined(SIMU) +} +#endif + +int8_t STORAGE_Init (uint8_t lun) +{ + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority =0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + +/* TODO if no SD ... if( SD_Init() != 0) + { + return (-1); + } +*/ + return (0); +} + +/** + * @brief return medium capacity and block size + * @param lun : logical unit number + * @param block_num : number of physical block + * @param block_size : size of a physical block + * @retval Status + */ +int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint32_t *block_size) +{ +#if defined(EEPROM) + if (lun == STORAGE_EEPROM_LUN) { + *block_size = BLOCK_SIZE; + *block_num = 3 + EEPROM_SIZE/BLOCK_SIZE + FLASHSIZE/BLOCK_SIZE; + return 0; + } +#endif + + if (!SD_CARD_PRESENT()) + return -1; + + *block_size = BLOCK_SIZE; + + static DWORD sector_count = 0; + if (sector_count == 0) { + if (disk_ioctl(0, GET_SECTOR_COUNT, §or_count) != RES_OK) { + sector_count = 0; + return -1; + } + } + + *block_num = sector_count; + + return 0; +} + +uint8_t lunReady[STORAGE_LUN_NBR]; + +void usbPluggedIn() +{ + lunReady[STORAGE_SDCARD_LUN] = 1; +#if defined(EEPROM) + lunReady[STORAGE_EEPROM_LUN] = 1; +#endif +} + +/** + * @brief check whether the medium is ready + * @param lun : logical unit number + * @retval Status + */ +int8_t STORAGE_IsReady (uint8_t lun) +{ +#if defined(EEPROM) + if (lun == STORAGE_EEPROM_LUN) { + return (lunReady[STORAGE_EEPROM_LUN] != 0) ? 0 : -1; + } +#endif + + return (lunReady[STORAGE_SDCARD_LUN] != 0 && SD_CARD_PRESENT()) ? 0 : -1; +} + +/** + * @brief check whether the medium is write-protected + * @param lun : logical unit number + * @retval Status + */ +int8_t STORAGE_IsWriteProtected (uint8_t lun) +{ + return 0; +} + +/** + * @brief Read data from the medium + * @param lun : logical unit number + * @param buf : Pointer to the buffer to save data + * @param blk_addr : address of 1st block to be read + * @param blk_len : nmber of blocks to be read + * @retval Status + */ + +int8_t STORAGE_Read (uint8_t lun, + uint8_t *buf, + uint32_t blk_addr, + uint16_t blk_len) +{ + WATCHDOG_SUSPEND(100/*1s*/); + +#if defined(EEPROM) + if (lun == STORAGE_EEPROM_LUN) { + return (fat12Read(buf, blk_addr, blk_len) == 0) ? 0 : -1; + } +#endif + + // read without cache + return (__disk_read(0, buf, blk_addr, blk_len) == RES_OK) ? 0 : -1; +} +/** + * @brief Write data to the medium + * @param lun : logical unit number + * @param buf : Pointer to the buffer to write from + * @param blk_addr : address of 1st block to be written + * @param blk_len : nmber of blocks to be read + * @retval Status + */ + +int8_t STORAGE_Write (uint8_t lun, + uint8_t *buf, + uint32_t blk_addr, + uint16_t blk_len) +{ + WATCHDOG_SUSPEND(100/*1s*/); + +#if defined(EEPROM) + if (lun == STORAGE_EEPROM_LUN) { + return (fat12Write(buf, blk_addr, blk_len) == 0) ? 0 : -1; + } +#endif + + // write without cache + return (__disk_write(0, buf, blk_addr, blk_len) == RES_OK) ? 0 : -1; +} + +/** + * @brief Return number of supported logical unit + * @param None + * @retval number of logical unit + */ + +int8_t STORAGE_GetMaxLun (void) +{ + return STORAGE_LUN_NBR - 1; +} + +#if defined(EEPROM) +//------------------------------------------------------------------------------ +/** + * FAT12 boot sector partition. + */ +const char g_FATboot[BLOCK_SIZE] = +{ + 0xeb, 0x3c, 0x90, // Jump instruction. + 0x39, 0x58, 0x20, 0x54, 0x45, 0x41, 0x4D, 0x00, // OEM Name + 0x00, 0x02, // Bytes per sector + 0x08, // Sectors per FS cluster. + 0x01, 0x00, // Reserved sector count + + 0x01, // Number of FATs + 0x10, 0x00, // Number of root directory entries + 3+(EEPROM_SIZE/BLOCK_SIZE), (FLASHSIZE/BLOCK_SIZE)>>8, // Total sectors + 0xf8, // Media descriptor + 0x01, 0x00, // Sectors per FAT table + 0x20, 0x00, // Sectors per track + 0x40, 0x00, // Number of heads + 0x00, 0x00, 0x00, 0x00, // Number of hidden sectors + + 0x00, 0x00, 0x00, 0x00, // Large number of sectors. + 0x00, // Physical drive number + 0x00, // Reserved + 0x29, // Extended boot signature + 0xCE, 0xFA, 0x5C, 0xD1, // Disk ID (serial number) + 0x56, 0x49, 0x52, 0x54, 0x46, 0x53, 0x20, 0x20, 0x20, 0x20, 0x20, // Volume label + 0x46, 0x41, 0x54, 0x31, 0x32, 0x20, 0x20, 0x20, // FAT file system type + 0x00, 0x00, // OS boot code + + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa +}; + +#if defined(REV4a) +const char g_FAT[BLOCK_SIZE] = +{ + 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xA0, 0x00, 0x0B, + 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0xF0, 0xFF, 0x13, 0x40, 0x01, 0x15, 0x60, + 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, + 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, + 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, + 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, + 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, + 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, + 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, + 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, + 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, + 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, + 0x81, 0x20, 0x08, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xA0, 0x08, 0x8B, + 0xC0, 0x08, 0x8D, 0xE0, 0x08, 0x8F, 0x00, 0x09, 0x91, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +#else +const char g_FAT[BLOCK_SIZE] = +{ + 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xF0, 0xFF, 0x0B, + 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60, + 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, + 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, + 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, + 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, + 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, + 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, + 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, + 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, + 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, + 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, + 0x81, 0x20, 0x08, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xF0, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +#endif + +// File Attributes +// 0 0x01 Read Only. +// 1 0x02 Hidden. +// 2 0x04 System. +// 3 0x08 Volume Label. +// 4 0x10 Subdirectory. +// 5 0x20 Archive. +// 6 0x40 Device. +// 7 0x80 Reserved. + +typedef struct +{ + uint8_t name[8]; + uint8_t ext[3]; + uint8_t attribute; + uint8_t reserved; + uint8_t create_time_ms; + uint16_t create_time; + uint16_t create_date; + uint16_t access_date; + uint16_t ea_index; + uint16_t modify_time; + uint16_t modify_date; + uint16_t start_cluster; + uint32_t file_size; +} FATDirEntry_t; + +// First 16 FAT root directory entries (1 sector) +const FATDirEntry_t g_DIRroot[16] = +{ + { + { USB_PRODUCT }, + { ' ', ' ', ' '}, + 0x08, // Volume + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { 'E', 'E', 'P', 'R', 'O', 'M', ' ', ' '}, + { 'B', 'I', 'N'}, + 0x20, // Archive + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0002, + EEPROM_SIZE + }, + { + { 'F', 'I', 'R', 'M', 'W', 'A', 'R', 'E'}, + { 'B', 'I', 'N'}, + 0x20, // Archive + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0002 + (EEPROM_SIZE/BLOCK_SIZE)/8, + FLASHSIZE + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, +}; + +// count is number of 512 byte sectors +int32_t fat12Read(uint8_t * buffer, uint16_t sector, uint16_t count) +{ + while(count) { + if (sector == 0) { + memcpy(buffer, g_FATboot, BLOCK_SIZE ) ; + } + else if (sector == 1/*Reserved sector count*/) { + // FAT table. + memcpy(buffer, g_FAT, BLOCK_SIZE); + } + else if (sector == 2) { + memcpy(buffer, g_DIRroot, BLOCK_SIZE ) ; + } + else if (sector < 3 + (EEPROM_SIZE/BLOCK_SIZE)) { + eepromReadBlock(buffer, (sector-3)*BLOCK_SIZE, BLOCK_SIZE); + } + else if (sector < 3 + (EEPROM_SIZE/BLOCK_SIZE) + (FLASHSIZE/BLOCK_SIZE)) { + uint32_t address; + address = sector - 3 - (EEPROM_SIZE/BLOCK_SIZE); + address *= BLOCK_SIZE; + address += FIRMWARE_ADDRESS; + memcpy(buffer, (uint8_t *)address, BLOCK_SIZE); + } + buffer += BLOCK_SIZE ; + sector++ ; + count-- ; + } + return 0 ; +} + +int32_t fat12Write(const uint8_t * buffer, uint16_t sector, uint16_t count) +{ + enum FatWriteOperation { + FATWRITE_NONE, + FATWRITE_EEPROM, + FATWRITE_FIRMWARE + }; + + static uint8_t operation = FATWRITE_NONE; + + TRACE("FAT12 Write(sector=%d, count=%d)", sector, count); + + if (sector < 3) { + // reserved, read-only + } + else if (sector < 3 + (EEPROM_SIZE/BLOCK_SIZE)) { + // eeprom + while (count) { + if (operation == FATWRITE_NONE && isEepromStart(buffer)) { + TRACE("EEPROM start found in sector %d", sector); + operation = FATWRITE_EEPROM; + } + if (operation == FATWRITE_EEPROM) { + eepromWriteBlock((uint8_t *)buffer, (sector-3)*BLOCK_SIZE, BLOCK_SIZE); + } + buffer += BLOCK_SIZE; + sector++; + count--; + if (sector-3 >= (EEPROM_SIZE/BLOCK_SIZE)) { + TRACE("EEPROM end written at sector %d", sector-1); + operation = FATWRITE_NONE; + } + } + } + else if (sector < 3 + (EEPROM_SIZE/BLOCK_SIZE) + (FLASHSIZE/BLOCK_SIZE)) { + // firmware + uint32_t address; + address = sector - 3 - (EEPROM_SIZE/BLOCK_SIZE); + address *= BLOCK_SIZE; + address += FIRMWARE_ADDRESS; + while (count) { + for (uint32_t i=0; i= FIRMWARE_ADDRESS+BOOTLOADER_SIZE/*protect bootloader*/ && address <= FIRMWARE_ADDRESS+FLASHSIZE-FLASH_PAGESIZE) { + if (address == FIRMWARE_ADDRESS+BOOTLOADER_SIZE && isFirmwareStart(buffer)) { + TRACE("FIRMWARE start found in sector %d", sector); + operation = FATWRITE_FIRMWARE; + } + if (operation == FATWRITE_FIRMWARE) { + flashWrite((uint32_t *)address, (uint32_t *)buffer); + } + } + address += FLASH_PAGESIZE; + buffer += FLASH_PAGESIZE; + } + sector++; + count--; + if (sector-3-(EEPROM_SIZE/BLOCK_SIZE) >= (FLASHSIZE/BLOCK_SIZE)) { + TRACE("FIRMWARE end written at sector %d", sector-1); + operation = FATWRITE_NONE; + } + } + } + return 0 ; +} +#endif diff --git a/radio/src/targets/common/arm/stm32/usbd_usr.cpp b/radio/src/targets/common/arm/stm32/usbd_usr.cpp index e6f317d3b..20fc57b5d 100644 --- a/radio/src/targets/common/arm/stm32/usbd_usr.cpp +++ b/radio/src/targets/common/arm/stm32/usbd_usr.cpp @@ -1,122 +1,122 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Includes ------------------------------------------------------------------*/ -#include "opentx.h" - -extern "C" { -#include "usbd_usr.h" - -/* Points to the DEVICE_PROP structure of current device */ -/* The purpose of this register is to speed up the execution */ - - -const USBD_Usr_cb_TypeDef USR_cb = -{ - USBD_USR_Init, - USBD_USR_DeviceReset, - USBD_USR_DeviceConfigured, - USBD_USR_DeviceSuspended, - USBD_USR_DeviceResumed, - - USBD_USR_DeviceConnected, - USBD_USR_DeviceDisconnected, -}; -} - -/** -* @brief Whatever the user application needs to do when USB is initialised -* @param None -* @retval None -*/ -void USBD_USR_Init(void) -{ - -} - -/** -* @brief Displays the message on LCD on device reset event -* @param speed : device speed -* @retval None -*/ -void USBD_USR_DeviceReset (uint8_t speed) -{ - -} - - -/** -* @brief Displays the message on LCD on device config event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceConfigured (void) -{ - -} -/** -* @brief Displays the message on LCD on device suspend event -* @param None -* @retval None -*/ -void USBD_USR_DeviceSuspended(void) -{ - -} - - -/** -* @brief Displays the message on LCD on device resume event -* @param None -* @retval None -*/ -void USBD_USR_DeviceResumed(void) -{ - -} - -/** -* @brief USBD_USR_DeviceConnected -* Displays the message on LCD on device connection Event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceConnected (void) -{ - -} - - -/** -* @brief USBD_USR_DeviceDisonnected -* Displays the message on LCD on device disconnection Event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceDisconnected (void) -{ -#if !defined(BOOT) && defined(USB_MASS_STORAGE) && defined(EEPROM) - // TODO is it really needed if we didn't write the EEPROM? - NVIC_SystemReset(); -#endif -} - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "opentx.h" + +extern "C" { +#include "usbd_usr.h" + +/* Points to the DEVICE_PROP structure of current device */ +/* The purpose of this register is to speed up the execution */ + + +const USBD_Usr_cb_TypeDef USR_cb = +{ + USBD_USR_Init, + USBD_USR_DeviceReset, + USBD_USR_DeviceConfigured, + USBD_USR_DeviceSuspended, + USBD_USR_DeviceResumed, + + USBD_USR_DeviceConnected, + USBD_USR_DeviceDisconnected, +}; +} + +/** +* @brief Whatever the user application needs to do when USB is initialised +* @param None +* @retval None +*/ +void USBD_USR_Init(void) +{ + +} + +/** +* @brief Displays the message on LCD on device reset event +* @param speed : device speed +* @retval None +*/ +void USBD_USR_DeviceReset (uint8_t speed) +{ + +} + + +/** +* @brief Displays the message on LCD on device config event +* @param None +* @retval Staus +*/ +void USBD_USR_DeviceConfigured (void) +{ + +} +/** +* @brief Displays the message on LCD on device suspend event +* @param None +* @retval None +*/ +void USBD_USR_DeviceSuspended(void) +{ + +} + + +/** +* @brief Displays the message on LCD on device resume event +* @param None +* @retval None +*/ +void USBD_USR_DeviceResumed(void) +{ + +} + +/** +* @brief USBD_USR_DeviceConnected +* Displays the message on LCD on device connection Event +* @param None +* @retval Staus +*/ +void USBD_USR_DeviceConnected (void) +{ + +} + + +/** +* @brief USBD_USR_DeviceDisonnected +* Displays the message on LCD on device disconnection Event +* @param None +* @retval Staus +*/ +void USBD_USR_DeviceDisconnected (void) +{ +#if !defined(BOOT) && defined(USB_MASS_STORAGE) && defined(EEPROM) + // TODO is it really needed if we didn't write the EEPROM? + NVIC_SystemReset(); +#endif +} + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/targets/gruvin9x/board.h b/radio/src/targets/gruvin9x/board.h index ad3e9bde1..99e7f709e 100644 --- a/radio/src/targets/gruvin9x/board.h +++ b/radio/src/targets/gruvin9x/board.h @@ -1,171 +1,171 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BOARD_GRUVIN9X_H_ -#define _BOARD_GRUVIN9X_H_ - -#include "../common/avr/board_avr.h" - -// Board driver -void boardInit(void); -#define boardOff() pwrOff() - -// Keys -#define KEYS_GPIO_REG_MENU pinl -#define KEYS_GPIO_PIN_MENU (1<<4) -#define KEYS_GPIO_REG_EXIT pinl -#define KEYS_GPIO_PIN_EXIT (1<<5) -#define KEYS_GPIO_REG_RIGHT pinl -#define KEYS_GPIO_PIN_RIGHT (1<<2) -#define KEYS_GPIO_REG_LEFT pinl -#define KEYS_GPIO_PIN_LEFT (1<<3) -#define KEYS_GPIO_REG_UP pinl -#define KEYS_GPIO_PIN_UP (1<<1) -#define KEYS_GPIO_REG_DOWN pinl -#define KEYS_GPIO_PIN_DOWN (1<<0) - -// Trims -#define TRIMS_GPIO_REG_LHL pinj -#define TRIMS_GPIO_REG_LVD pinj -#define TRIMS_GPIO_REG_RVU pinj -#define TRIMS_GPIO_REG_RHL pinj -#define TRIMS_GPIO_REG_LHR pinj -#define TRIMS_GPIO_REG_LVU pinj -#define TRIMS_GPIO_REG_RVD pinj -#define TRIMS_GPIO_REG_RHR pinj -#define TRIMS_GPIO_PIN_LHL (1<<0) -#define TRIMS_GPIO_PIN_LVD (1<<2) -#define TRIMS_GPIO_PIN_RVU (1<<5) -#define TRIMS_GPIO_PIN_RHL (1<<6) -#define TRIMS_GPIO_PIN_LHR (1<<1) -#define TRIMS_GPIO_PIN_LVU (1<<3) -#define TRIMS_GPIO_PIN_RVD (1<<4) -#define TRIMS_GPIO_PIN_RHR (1<<7) - -#define TIMER_16KHZ_VECT TIMER2_OVF_vect -#define COUNTER_16KHZ TCNT2 -#define TIMER_10MS_VECT TIMER2_COMPA_vect -#define TIMER_10MS_COMPVAL OCR2A -#define PAUSE_10MS_INTERRUPT() TIMSK2 &= ~(1< 0 && delta < MAX_MIXER_DELTA) return; - - nextMixerEndTime = t0 + MAX_MIXER_DELTA; - - doMixerCalculations(); - - t0 = getTmr16KHz() - t0; - lastMixerDuration = t0; - if (t0 > maxMixerDuration) maxMixerDuration = t0; -} - -#define loop_mixer_until_bit_is_set(sfr, bit) do { checkMixer(); wdt_reset(); } while (bit_is_clear(sfr, bit)) -#endif - -/*-----------------------------------------------------------------------*/ -/* Transmit a byte to MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -#define xmit_spi(dat) SPDR=(dat); loop_mixer_until_bit_is_set(SPSR,SPIF) - - - -/*-----------------------------------------------------------------------*/ -/* Receive a byte from MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -static -BYTE rcvr_spi (void) -{ - SPDR = 0xFF; - loop_mixer_until_bit_is_set(SPSR, SPIF); - return SPDR; -} - -/* Alternative macro to receive data fast */ -#define rcvr_spi_m(dst) SPDR=0xFF; loop_mixer_until_bit_is_set(SPSR,SPIF); *(dst)=SPDR - - - -/*-----------------------------------------------------------------------*/ -/* Wait for card ready */ -/*-----------------------------------------------------------------------*/ - -static -int wait_ready (void) /* 1:OK, 0:Timeout */ -{ - Timer2 = 50; /* Wait for ready in timeout of 500ms (G: now 50x16ms) */ - rcvr_spi(); - do - if (rcvr_spi() == 0xFF) return 1; - while (Timer2); - - return 0; -} - - - -/*-----------------------------------------------------------------------*/ -/* Deselect the card and release SPI bus */ -/*-----------------------------------------------------------------------*/ - -static -void deselect (void) -{ - CS_HIGH(); - rcvr_spi(); -} - - - -/*-----------------------------------------------------------------------*/ -/* Select the card and wait for ready */ -/*-----------------------------------------------------------------------*/ - -static -int select (void) /* 1:Successful, 0:Timeout */ -{ - CS_LOW(); - if (!wait_ready()) { - deselect(); - return 0; - } - return 1; -} - - - -/*-----------------------------------------------------------------------*/ -/* Power Control (Platform dependent) */ -/*-----------------------------------------------------------------------*/ -/* When the target system does not support socket power control, there */ -/* is nothing to do in these functions and chk_power always returns 1. */ - -static -int power_status(void) /* Socket power state: 0=off, 1=on */ -{ - return (PORTE & 0x80) ? 0 : 1; -} - - -static -void power_on (void) -{ - // PORTE &= ~0x80; // Socket power on -#ifndef SIMU - for (Timer1 = 2; Timer1; ); // Wait for 20ms -#endif - //PORTB = 0b10110101; // Enable drivers - //DDRB = 0b11000111; - - SPCR = 0x52; // Enable SPI function in mode 0 - SPSR = 0x00; // G: was 0x01; // SPI 2x mode -} - - -static -void power_off (void) -{ - SPCR = 0; /* Disable SPI function */ - // DDRB = 0b11000000; /* Disable drivers */ - // PORTB = 0b10110000; - - // PORTE |= 0x80; /* Socket power off */ - Stat |= STA_NOINIT; -} - - - -/*-----------------------------------------------------------------------*/ -/* Receive a data packet from MMC */ -/*-----------------------------------------------------------------------*/ - -static -int rcvr_datablock ( - BYTE *buff, /* Data buffer to store received data */ - UINT btr /* Byte count (must be multiple of 4) */ - ) -{ - BYTE token; - - - Timer1 = 20; - do { /* Wait for data packet in timeout of 200ms */ - token = rcvr_spi(); - } while ((token == 0xFF) && Timer1); - if(token != 0xFE) return 0; /* If not valid data token, retutn with error */ - - do { /* Receive the data block into buffer */ - rcvr_spi_m(buff++); - rcvr_spi_m(buff++); - rcvr_spi_m(buff++); - rcvr_spi_m(buff++); - } while (btr -= 4); - rcvr_spi(); /* Discard CRC */ - rcvr_spi(); - - return 1; /* Return with success */ -} - - - -/*-----------------------------------------------------------------------*/ -/* Send a data packet to MMC */ -/*-----------------------------------------------------------------------*/ - -static -int xmit_datablock ( - const BYTE *buff, /* 512 byte data block to be transmitted */ - BYTE token /* Data/Stop token */ - ) -{ - BYTE resp, wc; - - - if (!wait_ready()) return 0; - - xmit_spi(token); /* Xmit data token */ - if (token != 0xFD) { /* Is data token */ - wc = 0; - do { /* Xmit the 512 byte data block to MMC */ - xmit_spi(*buff++); - xmit_spi(*buff++); - } while (--wc); - xmit_spi(0xFF); /* CRC (Dummy) */ - xmit_spi(0xFF); - resp = rcvr_spi(); /* Reveive data response */ - if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ - return 0; - } - - return 1; -} - - - -/*-----------------------------------------------------------------------*/ -/* Send a command packet to MMC */ -/*-----------------------------------------------------------------------*/ - -static -BYTE send_cmd ( /* Returns R1 resp (bit7==1:Send failed) */ - BYTE cmd, /* Command index */ - DWORD arg /* Argument */ - ) -{ - BYTE n, res; - - - if (cmd & 0x80) { /* ACMD is the command sequense of CMD55-CMD */ - cmd &= 0x7F; - res = send_cmd(CMD55, 0); - if (res > 1) return res; - } - - /* Select the card and wait for ready */ - deselect(); - if (!select()) return 0xFF; - - /* Send command packet */ - xmit_spi(0x40 | cmd); /* Start + Command index */ - xmit_spi((BYTE)(arg >> 24)); /* Argument[31..24] */ - xmit_spi((BYTE)(arg >> 16)); /* Argument[23..16] */ - xmit_spi((BYTE)(arg >> 8)); /* Argument[15..8] */ - xmit_spi((BYTE)arg); /* Argument[7..0] */ - n = 0x01; /* Dummy CRC + Stop */ - if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) */ - if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) */ - xmit_spi(n); - - /* Receive command response */ - if (cmd == CMD12) rcvr_spi(); /* Skip a stuff byte when stop reading */ - n = 10; /* Wait for a valid response in timeout of 10 attempts */ - do - res = rcvr_spi(); - while ((res & 0x80) && --n); - - return res; /* Return with the response value */ -} - - - -/*-------------------------------------------------------------------------- - - Public Functions - - ---------------------------------------------------------------------------*/ - - -/*-----------------------------------------------------------------------*/ -/* Initialize Disk Drive */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_initialize ( - BYTE drv /* Physical drive nmuber (0) */ - ) -{ - BYTE n, cmd, ty, ocr[4]; - - - if (drv) return STA_NOINIT; /* Supports only single drive */ - if (Stat & STA_NODISK) return Stat; /* No card in the socket */ - - power_on(); /* Force socket power on */ - FCLK_SLOW(); - for (n = 10; n; n--) rcvr_spi(); /* 80 dummy clocks */ - - ty = 0; - if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ - Timer1 = 100; /* Initialization timeout of 1000 msec */ - if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); /* Get trailing return value of R7 resp */ - if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ - while (Timer1 && send_cmd(ACMD41, 1UL << 30)); /* Wait for leaving idle state (ACMD41 with HCS bit) */ - if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); - ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* SDv2 */ - } - } - } else { /* SDv1 or MMCv3 */ - if (send_cmd(ACMD41, 0) <= 1) { - ty = CT_SD1; cmd = ACMD41; /* SDv1 */ - } else { - ty = CT_MMC; cmd = CMD1; /* MMCv3 */ - } - while (Timer1 && send_cmd(cmd, 0)); /* Wait for leaving idle state */ - if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Set R/W block length to 512 */ - ty = 0; - } - } - CardType = ty; - deselect(); - - if (ty) { /* Initialization succeded */ - Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ - FCLK_FAST(); - } else { /* Initialization failed */ - power_off(); - } - - return Stat; -} - - - -/*-----------------------------------------------------------------------*/ -/* Get Disk Status */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_status ( - BYTE drv /* Physical drive number (0) */ - ) -{ - if (drv) return STA_NOINIT; /* Supports only single drive */ - return Stat; -} - - - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ -/*-----------------------------------------------------------------------*/ - -DRESULT disk_read ( - BYTE drv, /* Physical drive nmuber (0) */ - BYTE *buff, /* Pointer to the data buffer to store read data */ - DWORD sector, /* Start sector number (LBA) */ - UINT count /* Sector count (1..255) */ - ) -{ - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - - if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ - - if (count == 1) { /* Single block read */ - if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */ - && rcvr_datablock(buff, 512)) - count = 0; - } - else { /* Multiple block read */ - if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ - do { - if (!rcvr_datablock(buff, 512)) break; - buff += 512; - } while (--count); - send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ - } - } - deselect(); - - return count ? RES_ERROR : RES_OK; -} - - - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ -/*-----------------------------------------------------------------------*/ - -DRESULT disk_write ( - BYTE drv, /* Physical drive nmuber (0) */ - const BYTE *buff, /* Pointer to the data to be written */ - DWORD sector, /* Start sector number (LBA) */ - UINT count /* Sector count (1..255) */ - ) -{ - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - if (Stat & STA_PROTECT) return RES_WRPRT; - - if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ - - if (count == 1) { /* Single block write */ - if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ - && xmit_datablock(buff, 0xFE)) - count = 0; - } - else { /* Multiple block write */ - if (CardType & CT_SDC) send_cmd(ACMD23, count); - if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ - do { - if (!xmit_datablock(buff, 0xFC)) break; - buff += 512; - } while (--count); - if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ - count = 1; - } - } - deselect(); - - return count ? RES_ERROR : RES_OK; -} - - - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ -/*-----------------------------------------------------------------------*/ - -DRESULT disk_ioctl ( - BYTE drv, /* Physical drive nmuber (0) */ - BYTE ctrl, /* Control code */ - void *buff /* Buffer to send/receive control data */ - ) -{ - DRESULT res; - BYTE n, csd[16], *ptr = (BYTE*)buff; - WORD csize; - - - if (drv) return RES_PARERR; - - res = RES_ERROR; - - if (ctrl == CTRL_POWER) { - switch (ptr[0]) { - case 0: /* Sub control code (POWER_OFF) */ - power_off(); /* Power off */ - res = RES_OK; - break; - case 1: /* Sub control code (POWER_GET) */ - ptr[1] = (BYTE)power_status(); - res = RES_OK; - break; - default : - res = RES_PARERR; - } - } - else { - if (Stat & STA_NOINIT) return RES_NOTRDY; - - switch (ctrl) { - case CTRL_SYNC : /* Make sure that no pending write process. Do not remove this or written sector might not left updated. */ - if (select()) { - deselect(); - res = RES_OK; - } - break; - - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ - if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { - if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */ - csize = csd[9] + ((WORD)csd[8] << 8) + 1; - *(DWORD*)buff = (DWORD)csize << 10; - } else { /* SDC ver 1.XX or MMC*/ - n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; - csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; - *(DWORD*)buff = (DWORD)csize << (n - 9); - } - res = RES_OK; - } - break; - - case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ - *(WORD*)buff = 512; - res = RES_OK; - break; - - case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ - if (CardType & CT_SD2) { /* SDv2? */ - if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ - rcvr_spi(); - if (rcvr_datablock(csd, 16)) { /* Read partial block */ - for (n = 64 - 16; n; n--) rcvr_spi(); /* Purge trailing data */ - *(DWORD*)buff = 16UL << (csd[10] >> 4); - res = RES_OK; - } - } - } else { /* SDv1 or MMCv3 */ - if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ - if (CardType & CT_SD1) { /* SDv1 */ - *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); - } else { /* MMCv3 */ - *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); - } - res = RES_OK; - } - } - break; - - case MMC_GET_TYPE : /* Get card type flags (1 byte) */ - *ptr = CardType; - res = RES_OK; - break; - - case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ - if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ - if (send_cmd(CMD10, 0) == 0 /* READ_CID */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ - if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ - for (n = 4; n; n--) *ptr++ = rcvr_spi(); - res = RES_OK; - } - break; - - case MMC_GET_SDSTAT : /* Receive SD statsu as a data block (64 bytes) */ - if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ - rcvr_spi(); - if (rcvr_datablock(ptr, 64)) - res = RES_OK; - } - break; - - default: - res = RES_PARERR; - } - - deselect(); - } - - return res; -} - - - -/*-----------------------------------------------------------------------*/ -/* Device Timer Interrupt Procedure */ -/*-----------------------------------------------------------------------*/ -/* This function must be called in period of 10ms */ - -void sdPoll10ms() -{ - BYTE s; - - /* - n = Timer1; // 100Hz decrement timer - if (n) Timer1 = --n; - n = Timer2; - if (n) Timer2 = --n; - */ - if (Timer1) Timer1--; - if (Timer2) Timer2--; - - s = Stat; - - /* G: Not implemented - if (SOCKWP) // Write protected - s |= STA_PROTECT; - else // Write enabled - s &= ~STA_PROTECT; - if (SOCKINS) // Card inserted - s &= ~STA_NODISK; - else // Socket empty - s |= (STA_NODISK | STA_NOINIT); - */ - s &= ~STA_NODISK; - s &= ~STA_PROTECT; - - Stat = s; -} - -#if !defined(SIMU) -bool sdMounted() -{ - return g_FATFS_Obj.fs_type != 0; -} - -void sdMountPoll() -{ - static uint8_t mountTimer; - if (mountTimer-- == 0) { - mountTimer = 100; - if (!sdMounted()) { - f_mount(&g_FATFS_Obj, "", 1); - f_chdir(ROOT_PATH); - } - } -} -#endif - -FATFS g_FATFS_Obj; +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*-----------------------------------------------------------------------*/ +/* MMCv3/SDv1/SDv2 (in SPI mode) control module (C)ChaN, 2010 */ +/*-----------------------------------------------------------------------*/ +/* Only rcvr_spi(), xmit_spi(), sdPoll10mS() and some macros */ +/* are platform dependent. */ +/*-----------------------------------------------------------------------*/ + +#include "opentx.h" +#include "diskio.h" + +/* Definitions for MMC/SDC command */ +#define CMD0 (0) /* GO_IDLE_STATE */ +#define CMD1 (1) /* SEND_OP_COND (MMC) */ +#define ACMD41 (0x80+41) /* SEND_OP_COND (SDC) */ +#define CMD8 (8) /* SEND_IF_COND */ +#define CMD9 (9) /* SEND_CSD */ +#define CMD10 (10) /* SEND_CID */ +#define CMD12 (12) /* STOP_TRANSMISSION */ +#define ACMD13 (0x80+13) /* SD_STATUS (SDC) */ +#define CMD16 (16) /* SET_BLOCKLEN */ +#define CMD17 (17) /* READ_SINGLE_BLOCK */ +#define CMD18 (18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (23) /* SET_BLOCK_COUNT (MMC) */ +#define ACMD23 (0x80+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */ +#define CMD24 (24) /* WRITE_BLOCK */ +#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD55 (55) /* APP_CMD */ +#define CMD58 (58) /* READ_OCR */ + +/* Card type flags (CardType) */ +#define CT_MMC 0x01 /* MMC ver 3 */ +#define CT_SD1 0x02 /* SD ver 1 */ +#define CT_SD2 0x04 /* SD ver 2 */ +#define CT_SDC (CT_SD1|CT_SD2) /* SD */ +#define CT_BLOCK 0x08 /* Block addressing */ + +/* Port Controls (Platform dependent) */ +// GCC optimisation should result in a single CBI/SBI instructions here +#if defined (CPUM2560) +# define CS_LOW() PORTB &= ~0x01 /* MMC CS = L */ +# define CS_HIGH() PORTB |= 0x01 /* MMC CS = H */ +#else +# define CS_LOW() PORTB &= ~0x10 /* MMC CS = L */ +# define CS_HIGH() PORTB |= 0x10 /* MMC CS = H */ +#endif + +#define SOCKPORT PINB /* Socket contact port */ +#define SOCKWP 0x00 // not implemented /* Write protect switch */ +#define SOCKINS 0x00 // not implemented /* Card detect switch */ + +#define FCLK_SLOW() SPCR = 0x52 /* Set slow clock (100k-400k) */ +#define FCLK_FAST() SPCR = 0x50 /* Set fast clock (depends on the CSD) */ + + +/*-------------------------------------------------------------------------- + + Module Private Functions + + ---------------------------------------------------------------------------*/ + +static volatile +DSTATUS Stat = STA_NOINIT; /* Disk status */ + +volatile BYTE Timer1, Timer2; /* 100Hz decrement timer */ + +static +BYTE CardType; /* Card type flags */ + +#if defined(SIMU) +#define loop_mixer_until_bit_is_set loop_until_bit_is_set +#else +inline void checkMixer() +{ + // TODO duplicated code ... + uint16_t t0 = getTmr16KHz(); + int16_t delta = (nextMixerEndTime - lastMixerDuration) - t0; + if (delta > 0 && delta < MAX_MIXER_DELTA) return; + + nextMixerEndTime = t0 + MAX_MIXER_DELTA; + + doMixerCalculations(); + + t0 = getTmr16KHz() - t0; + lastMixerDuration = t0; + if (t0 > maxMixerDuration) maxMixerDuration = t0; +} + +#define loop_mixer_until_bit_is_set(sfr, bit) do { checkMixer(); wdt_reset(); } while (bit_is_clear(sfr, bit)) +#endif + +/*-----------------------------------------------------------------------*/ +/* Transmit a byte to MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +#define xmit_spi(dat) SPDR=(dat); loop_mixer_until_bit_is_set(SPSR,SPIF) + + + +/*-----------------------------------------------------------------------*/ +/* Receive a byte from MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +static +BYTE rcvr_spi (void) +{ + SPDR = 0xFF; + loop_mixer_until_bit_is_set(SPSR, SPIF); + return SPDR; +} + +/* Alternative macro to receive data fast */ +#define rcvr_spi_m(dst) SPDR=0xFF; loop_mixer_until_bit_is_set(SPSR,SPIF); *(dst)=SPDR + + + +/*-----------------------------------------------------------------------*/ +/* Wait for card ready */ +/*-----------------------------------------------------------------------*/ + +static +int wait_ready (void) /* 1:OK, 0:Timeout */ +{ + Timer2 = 50; /* Wait for ready in timeout of 500ms (G: now 50x16ms) */ + rcvr_spi(); + do + if (rcvr_spi() == 0xFF) return 1; + while (Timer2); + + return 0; +} + + + +/*-----------------------------------------------------------------------*/ +/* Deselect the card and release SPI bus */ +/*-----------------------------------------------------------------------*/ + +static +void deselect (void) +{ + CS_HIGH(); + rcvr_spi(); +} + + + +/*-----------------------------------------------------------------------*/ +/* Select the card and wait for ready */ +/*-----------------------------------------------------------------------*/ + +static +int select (void) /* 1:Successful, 0:Timeout */ +{ + CS_LOW(); + if (!wait_ready()) { + deselect(); + return 0; + } + return 1; +} + + + +/*-----------------------------------------------------------------------*/ +/* Power Control (Platform dependent) */ +/*-----------------------------------------------------------------------*/ +/* When the target system does not support socket power control, there */ +/* is nothing to do in these functions and chk_power always returns 1. */ + +static +int power_status(void) /* Socket power state: 0=off, 1=on */ +{ + return (PORTE & 0x80) ? 0 : 1; +} + + +static +void power_on (void) +{ + // PORTE &= ~0x80; // Socket power on +#ifndef SIMU + for (Timer1 = 2; Timer1; ); // Wait for 20ms +#endif + //PORTB = 0b10110101; // Enable drivers + //DDRB = 0b11000111; + + SPCR = 0x52; // Enable SPI function in mode 0 + SPSR = 0x00; // G: was 0x01; // SPI 2x mode +} + + +static +void power_off (void) +{ + SPCR = 0; /* Disable SPI function */ + // DDRB = 0b11000000; /* Disable drivers */ + // PORTB = 0b10110000; + + // PORTE |= 0x80; /* Socket power off */ + Stat |= STA_NOINIT; +} + + + +/*-----------------------------------------------------------------------*/ +/* Receive a data packet from MMC */ +/*-----------------------------------------------------------------------*/ + +static +int rcvr_datablock ( + BYTE *buff, /* Data buffer to store received data */ + UINT btr /* Byte count (must be multiple of 4) */ + ) +{ + BYTE token; + + + Timer1 = 20; + do { /* Wait for data packet in timeout of 200ms */ + token = rcvr_spi(); + } while ((token == 0xFF) && Timer1); + if(token != 0xFE) return 0; /* If not valid data token, retutn with error */ + + do { /* Receive the data block into buffer */ + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + } while (btr -= 4); + rcvr_spi(); /* Discard CRC */ + rcvr_spi(); + + return 1; /* Return with success */ +} + + + +/*-----------------------------------------------------------------------*/ +/* Send a data packet to MMC */ +/*-----------------------------------------------------------------------*/ + +static +int xmit_datablock ( + const BYTE *buff, /* 512 byte data block to be transmitted */ + BYTE token /* Data/Stop token */ + ) +{ + BYTE resp, wc; + + + if (!wait_ready()) return 0; + + xmit_spi(token); /* Xmit data token */ + if (token != 0xFD) { /* Is data token */ + wc = 0; + do { /* Xmit the 512 byte data block to MMC */ + xmit_spi(*buff++); + xmit_spi(*buff++); + } while (--wc); + xmit_spi(0xFF); /* CRC (Dummy) */ + xmit_spi(0xFF); + resp = rcvr_spi(); /* Reveive data response */ + if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ + return 0; + } + + return 1; +} + + + +/*-----------------------------------------------------------------------*/ +/* Send a command packet to MMC */ +/*-----------------------------------------------------------------------*/ + +static +BYTE send_cmd ( /* Returns R1 resp (bit7==1:Send failed) */ + BYTE cmd, /* Command index */ + DWORD arg /* Argument */ + ) +{ + BYTE n, res; + + + if (cmd & 0x80) { /* ACMD is the command sequense of CMD55-CMD */ + cmd &= 0x7F; + res = send_cmd(CMD55, 0); + if (res > 1) return res; + } + + /* Select the card and wait for ready */ + deselect(); + if (!select()) return 0xFF; + + /* Send command packet */ + xmit_spi(0x40 | cmd); /* Start + Command index */ + xmit_spi((BYTE)(arg >> 24)); /* Argument[31..24] */ + xmit_spi((BYTE)(arg >> 16)); /* Argument[23..16] */ + xmit_spi((BYTE)(arg >> 8)); /* Argument[15..8] */ + xmit_spi((BYTE)arg); /* Argument[7..0] */ + n = 0x01; /* Dummy CRC + Stop */ + if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) */ + if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) */ + xmit_spi(n); + + /* Receive command response */ + if (cmd == CMD12) rcvr_spi(); /* Skip a stuff byte when stop reading */ + n = 10; /* Wait for a valid response in timeout of 10 attempts */ + do + res = rcvr_spi(); + while ((res & 0x80) && --n); + + return res; /* Return with the response value */ +} + + + +/*-------------------------------------------------------------------------- + + Public Functions + + ---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* Initialize Disk Drive */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_initialize ( + BYTE drv /* Physical drive nmuber (0) */ + ) +{ + BYTE n, cmd, ty, ocr[4]; + + + if (drv) return STA_NOINIT; /* Supports only single drive */ + if (Stat & STA_NODISK) return Stat; /* No card in the socket */ + + power_on(); /* Force socket power on */ + FCLK_SLOW(); + for (n = 10; n; n--) rcvr_spi(); /* 80 dummy clocks */ + + ty = 0; + if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ + Timer1 = 100; /* Initialization timeout of 1000 msec */ + if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); /* Get trailing return value of R7 resp */ + if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ + while (Timer1 && send_cmd(ACMD41, 1UL << 30)); /* Wait for leaving idle state (ACMD41 with HCS bit) */ + if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); + ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* SDv2 */ + } + } + } else { /* SDv1 or MMCv3 */ + if (send_cmd(ACMD41, 0) <= 1) { + ty = CT_SD1; cmd = ACMD41; /* SDv1 */ + } else { + ty = CT_MMC; cmd = CMD1; /* MMCv3 */ + } + while (Timer1 && send_cmd(cmd, 0)); /* Wait for leaving idle state */ + if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Set R/W block length to 512 */ + ty = 0; + } + } + CardType = ty; + deselect(); + + if (ty) { /* Initialization succeded */ + Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ + FCLK_FAST(); + } else { /* Initialization failed */ + power_off(); + } + + return Stat; +} + + + +/*-----------------------------------------------------------------------*/ +/* Get Disk Status */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_status ( + BYTE drv /* Physical drive number (0) */ + ) +{ + if (drv) return STA_NOINIT; /* Supports only single drive */ + return Stat; +} + + + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_read ( + BYTE drv, /* Physical drive nmuber (0) */ + BYTE *buff, /* Pointer to the data buffer to store read data */ + DWORD sector, /* Start sector number (LBA) */ + UINT count /* Sector count (1..255) */ + ) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + + if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ + + if (count == 1) { /* Single block read */ + if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */ + && rcvr_datablock(buff, 512)) + count = 0; + } + else { /* Multiple block read */ + if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ + do { + if (!rcvr_datablock(buff, 512)) break; + buff += 512; + } while (--count); + send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ + } + } + deselect(); + + return count ? RES_ERROR : RES_OK; +} + + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_write ( + BYTE drv, /* Physical drive nmuber (0) */ + const BYTE *buff, /* Pointer to the data to be written */ + DWORD sector, /* Start sector number (LBA) */ + UINT count /* Sector count (1..255) */ + ) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + if (Stat & STA_PROTECT) return RES_WRPRT; + + if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ + + if (count == 1) { /* Single block write */ + if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ + && xmit_datablock(buff, 0xFE)) + count = 0; + } + else { /* Multiple block write */ + if (CardType & CT_SDC) send_cmd(ACMD23, count); + if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ + do { + if (!xmit_datablock(buff, 0xFC)) break; + buff += 512; + } while (--count); + if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ + count = 1; + } + } + deselect(); + + return count ? RES_ERROR : RES_OK; +} + + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_ioctl ( + BYTE drv, /* Physical drive nmuber (0) */ + BYTE ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ + ) +{ + DRESULT res; + BYTE n, csd[16], *ptr = (BYTE*)buff; + WORD csize; + + + if (drv) return RES_PARERR; + + res = RES_ERROR; + + if (ctrl == CTRL_POWER) { + switch (ptr[0]) { + case 0: /* Sub control code (POWER_OFF) */ + power_off(); /* Power off */ + res = RES_OK; + break; + case 1: /* Sub control code (POWER_GET) */ + ptr[1] = (BYTE)power_status(); + res = RES_OK; + break; + default : + res = RES_PARERR; + } + } + else { + if (Stat & STA_NOINIT) return RES_NOTRDY; + + switch (ctrl) { + case CTRL_SYNC : /* Make sure that no pending write process. Do not remove this or written sector might not left updated. */ + if (select()) { + deselect(); + res = RES_OK; + } + break; + + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ + if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { + if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */ + csize = csd[9] + ((WORD)csd[8] << 8) + 1; + *(DWORD*)buff = (DWORD)csize << 10; + } else { /* SDC ver 1.XX or MMC*/ + n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; + csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; + *(DWORD*)buff = (DWORD)csize << (n - 9); + } + res = RES_OK; + } + break; + + case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ + *(WORD*)buff = 512; + res = RES_OK; + break; + + case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ + if (CardType & CT_SD2) { /* SDv2? */ + if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ + rcvr_spi(); + if (rcvr_datablock(csd, 16)) { /* Read partial block */ + for (n = 64 - 16; n; n--) rcvr_spi(); /* Purge trailing data */ + *(DWORD*)buff = 16UL << (csd[10] >> 4); + res = RES_OK; + } + } + } else { /* SDv1 or MMCv3 */ + if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ + if (CardType & CT_SD1) { /* SDv1 */ + *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); + } else { /* MMCv3 */ + *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); + } + res = RES_OK; + } + } + break; + + case MMC_GET_TYPE : /* Get card type flags (1 byte) */ + *ptr = CardType; + res = RES_OK; + break; + + case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ + if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ + if (send_cmd(CMD10, 0) == 0 /* READ_CID */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ + if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ + for (n = 4; n; n--) *ptr++ = rcvr_spi(); + res = RES_OK; + } + break; + + case MMC_GET_SDSTAT : /* Receive SD statsu as a data block (64 bytes) */ + if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ + rcvr_spi(); + if (rcvr_datablock(ptr, 64)) + res = RES_OK; + } + break; + + default: + res = RES_PARERR; + } + + deselect(); + } + + return res; +} + + + +/*-----------------------------------------------------------------------*/ +/* Device Timer Interrupt Procedure */ +/*-----------------------------------------------------------------------*/ +/* This function must be called in period of 10ms */ + +void sdPoll10ms() +{ + BYTE s; + + /* + n = Timer1; // 100Hz decrement timer + if (n) Timer1 = --n; + n = Timer2; + if (n) Timer2 = --n; + */ + if (Timer1) Timer1--; + if (Timer2) Timer2--; + + s = Stat; + + /* G: Not implemented + if (SOCKWP) // Write protected + s |= STA_PROTECT; + else // Write enabled + s &= ~STA_PROTECT; + if (SOCKINS) // Card inserted + s &= ~STA_NODISK; + else // Socket empty + s |= (STA_NODISK | STA_NOINIT); + */ + s &= ~STA_NODISK; + s &= ~STA_PROTECT; + + Stat = s; +} + +#if !defined(SIMU) +bool sdMounted() +{ + return g_FATFS_Obj.fs_type != 0; +} + +void sdMountPoll() +{ + static uint8_t mountTimer; + if (mountTimer-- == 0) { + mountTimer = 100; + if (!sdMounted()) { + f_mount(&g_FATFS_Obj, "", 1); + f_chdir(ROOT_PATH); + } + } +} +#endif + +FATFS g_FATFS_Obj; diff --git a/radio/src/targets/gruvin9x/rtc_driver.cpp b/radio/src/targets/gruvin9x/rtc_driver.cpp index e1d25b2e2..7066a59af 100644 --- a/radio/src/targets/gruvin9x/rtc_driver.cpp +++ b/radio/src/targets/gruvin9x/rtc_driver.cpp @@ -1,304 +1,304 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/*--------------------------------------------------------------------------*/ -/* RTC controls */ - -#include "opentx.h" -#include "FatFs/integer.h" - -typedef struct { - WORD year; /* 2000..2099 */ - BYTE month; /* 1..12 */ - BYTE mday; /* 1.. 31 */ - BYTE wday; /* 1..7 */ - BYTE hour; /* 0..23 */ - BYTE min; /* 0..59 */ - BYTE sec; /* 0..59 */ -} RTC; - -#define SCL_LOW() DDRD |= 0x01 /* SCL = LOW */ -#define SCL_HIGH() DDRD &= ~0x01 /* SCL = High-Z */ -#define SCL_VAL ((PIND & 0x01) ? 1 : 0) /* SCL input level */ -#define SDA_LOW() DDRD |= 0x02 /* SDA = LOW */ -#define SDA_HIGH() DDRD &= ~0x02 /* SDA = High-Z */ -#define SDA_VAL ((PIND & 0x02) ? 1 : 0) /* SDA input level */ - -/*-------------------------------------------------*/ -/* I2C bus protocol */ - -static -void iic_delay (void) -{ -#ifndef SIMU - for (int n = 4; n; n--) PINB; -#endif -} - - -/* Generate start condition on the IIC bus */ -static -void iic_start (void) -{ - SDA_HIGH(); - iic_delay(); - SCL_HIGH(); - iic_delay(); - SDA_LOW(); - iic_delay(); - SCL_LOW(); - iic_delay(); -} - - -/* Generate stop condition on the IIC bus */ -static -void iic_stop (void) -{ - SDA_LOW(); - iic_delay(); - SCL_HIGH(); - iic_delay(); - SDA_HIGH(); - iic_delay(); -} - - -/* Send a byte to the IIC bus */ -static -int iic_send (BYTE dat) -{ - BYTE b = 0x80; - int ack; - - - do { - if (dat & b) { /* SDA = Z/L */ - SDA_HIGH(); - } else { - SDA_LOW(); - } - iic_delay(); - SCL_HIGH(); - iic_delay(); - SCL_LOW(); - iic_delay(); - } while (b >>= 1); - SDA_HIGH(); - iic_delay(); - SCL_HIGH(); - ack = SDA_VAL ? 0 : 1; /* Sample ACK */ - iic_delay(); - SCL_LOW(); - iic_delay(); - return ack; -} - - -/* Receive a byte from the IIC bus */ -static -BYTE iic_rcvr (int ack) -{ - UINT d = 1; - - - do { - d <<= 1; - SCL_HIGH(); - if (SDA_VAL) d++; - iic_delay(); - SCL_LOW(); - iic_delay(); - } while (d < 0x100); - if (ack) { /* SDA = ACK */ - SDA_LOW(); - } else { - SDA_HIGH(); - } - iic_delay(); - SCL_HIGH(); - iic_delay(); - SCL_LOW(); - SDA_HIGH(); - iic_delay(); - - return (BYTE)d; -} - - - -/*-------------------------------------------------*/ -/* I2C block read/write controls */ - - -int iic_read ( - BYTE dev, /* Device address */ - UINT adr, /* Read start address */ - UINT cnt, /* Read byte count */ - BYTE *buff /* Read data buffer */ -) -{ - BYTE *rbuff = buff; - int n; - - - if (!cnt) return 0; - - n = 10; - do { /* Select device */ - iic_start(); - } while (!iic_send(dev) && --n); - if (n) { - if (iic_send((BYTE)adr)) { /* Set start address */ - iic_start(); /* Reselect device in read mode */ - if (iic_send(dev | 1)) { - do { /* Receive data */ - cnt--; - *rbuff++ = iic_rcvr(cnt ? 1 : 0); - } while (cnt); - } - } - } - - iic_stop(); /* Deselect device */ - - return cnt ? 0 : 1; -} - - - -int iic_write ( - BYTE dev, /* Device address */ - UINT adr, /* Write start address */ - UINT cnt, /* Write byte count */ - const BYTE *buff /* Data to be written */ -) -{ - const BYTE *wbuff = buff; - int n; - - - if (!cnt) return 0; - - n = 10; - do { /* Select device */ - iic_start(); - } while (!iic_send(dev) && --n); - if (n) { - if (iic_send((BYTE)adr)) { /* Set start address */ - do { /* Send data */ - if (!iic_send(*wbuff++)) break; - } while (--cnt); - } - } - - iic_stop(); /* Deselect device */ - - return cnt ? 0 : 1; -} - -/*-------------------------------------------------*/ -/* RTC functions */ - -int g9x_rtcGetTime (RTC *rtc) -{ - BYTE buf[8]; - - if (!iic_read(0xD0, 0, 7, buf)) return 0; - - rtc->sec = (buf[0] & 0x0F) + ((buf[0] >> 4) & 7) * 10; - rtc->min = (buf[1] & 0x0F) + (buf[1] >> 4) * 10; - rtc->hour = (buf[2] & 0x0F) + ((buf[2] >> 4) & 3) * 10; - rtc->wday = (buf[2] & 0x07); - rtc->mday = (buf[4] & 0x0F) + ((buf[4] >> 4) & 3) * 10; - rtc->month = (buf[5] & 0x0F) + ((buf[5] >> 4) & 1) * 10; - rtc->year = 2000 + (buf[6] & 0x0F) + (buf[6] >> 4) * 10; - - return 1; -} - -int g9x_rtcSetTime (const RTC *rtc) -{ - BYTE buf[8]; - - buf[0] = rtc->sec / 10 * 16 + rtc->sec % 10; - buf[1] = rtc->min / 10 * 16 + rtc->min % 10; - buf[2] = rtc->hour / 10 * 16 + rtc->hour % 10; - buf[3] = rtc->wday & 7; - buf[4] = rtc->mday / 10 * 16 + rtc->mday % 10; - buf[5] = rtc->month / 10 * 16 + rtc->month % 10; - buf[6] = (rtc->year - 2000) / 10 * 16 + (rtc->year - 2000) % 10; - return iic_write(0xD0, 0, 7, buf); -} - -void rtcGetTime(struct gtm * utm) -{ - RTC rtc = {0,0,0,0,0,0,0}; - - g9x_rtcGetTime(&rtc); - - utm->tm_year = rtc.year - TM_YEAR_BASE; - utm->tm_mon = rtc.month - 1; - utm->tm_mday = rtc.mday; - utm->tm_hour = rtc.hour; - utm->tm_min = rtc.min; - utm->tm_sec = rtc.sec; - utm->tm_wday = rtc.wday - 1; -} - -void rtcSetTime(const struct gtm * t) -{ - g_ms100 = 0; // start of next second begins now - - RTC rtc; - rtc.year = t->tm_year + TM_YEAR_BASE; - rtc.month = t->tm_mon + 1; - rtc.mday = t->tm_mday; - rtc.hour = t->tm_hour; - rtc.min = t->tm_min; - rtc.sec = t->tm_sec; - rtc.wday = t->tm_wday + 1; - g9x_rtcSetTime(&rtc); -} - -void rtcInit (void) -{ - BYTE buf[8]; /* RTC R/W buffer */ - UINT adr; - - - /* Read RTC registers */ - if (!iic_read(0xD0, 0, 8, buf)) return; /* IIC error */ - - if (buf[7] & 0x20) { /* When data has been volatiled, set default time */ - /* Clear nv-ram. Reg[8..63] */ - memset(buf, 0, 8); - for (adr = 8; adr < 64; adr += 8) - iic_write(0x0D, adr, 8, buf); - /* Reset time to Jan 1, '08. Reg[0..7] */ - buf[4] = 1; buf[5] = 1; buf[6] = 8; - iic_write(0x0D, 0, 8, buf); - } - - struct gtm utm; - rtcGetTime(&utm); - g_rtcTime = gmktime(&utm); -} - +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------*/ +/* RTC controls */ + +#include "opentx.h" +#include "FatFs/integer.h" + +typedef struct { + WORD year; /* 2000..2099 */ + BYTE month; /* 1..12 */ + BYTE mday; /* 1.. 31 */ + BYTE wday; /* 1..7 */ + BYTE hour; /* 0..23 */ + BYTE min; /* 0..59 */ + BYTE sec; /* 0..59 */ +} RTC; + +#define SCL_LOW() DDRD |= 0x01 /* SCL = LOW */ +#define SCL_HIGH() DDRD &= ~0x01 /* SCL = High-Z */ +#define SCL_VAL ((PIND & 0x01) ? 1 : 0) /* SCL input level */ +#define SDA_LOW() DDRD |= 0x02 /* SDA = LOW */ +#define SDA_HIGH() DDRD &= ~0x02 /* SDA = High-Z */ +#define SDA_VAL ((PIND & 0x02) ? 1 : 0) /* SDA input level */ + +/*-------------------------------------------------*/ +/* I2C bus protocol */ + +static +void iic_delay (void) +{ +#ifndef SIMU + for (int n = 4; n; n--) PINB; +#endif +} + + +/* Generate start condition on the IIC bus */ +static +void iic_start (void) +{ + SDA_HIGH(); + iic_delay(); + SCL_HIGH(); + iic_delay(); + SDA_LOW(); + iic_delay(); + SCL_LOW(); + iic_delay(); +} + + +/* Generate stop condition on the IIC bus */ +static +void iic_stop (void) +{ + SDA_LOW(); + iic_delay(); + SCL_HIGH(); + iic_delay(); + SDA_HIGH(); + iic_delay(); +} + + +/* Send a byte to the IIC bus */ +static +int iic_send (BYTE dat) +{ + BYTE b = 0x80; + int ack; + + + do { + if (dat & b) { /* SDA = Z/L */ + SDA_HIGH(); + } else { + SDA_LOW(); + } + iic_delay(); + SCL_HIGH(); + iic_delay(); + SCL_LOW(); + iic_delay(); + } while (b >>= 1); + SDA_HIGH(); + iic_delay(); + SCL_HIGH(); + ack = SDA_VAL ? 0 : 1; /* Sample ACK */ + iic_delay(); + SCL_LOW(); + iic_delay(); + return ack; +} + + +/* Receive a byte from the IIC bus */ +static +BYTE iic_rcvr (int ack) +{ + UINT d = 1; + + + do { + d <<= 1; + SCL_HIGH(); + if (SDA_VAL) d++; + iic_delay(); + SCL_LOW(); + iic_delay(); + } while (d < 0x100); + if (ack) { /* SDA = ACK */ + SDA_LOW(); + } else { + SDA_HIGH(); + } + iic_delay(); + SCL_HIGH(); + iic_delay(); + SCL_LOW(); + SDA_HIGH(); + iic_delay(); + + return (BYTE)d; +} + + + +/*-------------------------------------------------*/ +/* I2C block read/write controls */ + + +int iic_read ( + BYTE dev, /* Device address */ + UINT adr, /* Read start address */ + UINT cnt, /* Read byte count */ + BYTE *buff /* Read data buffer */ +) +{ + BYTE *rbuff = buff; + int n; + + + if (!cnt) return 0; + + n = 10; + do { /* Select device */ + iic_start(); + } while (!iic_send(dev) && --n); + if (n) { + if (iic_send((BYTE)adr)) { /* Set start address */ + iic_start(); /* Reselect device in read mode */ + if (iic_send(dev | 1)) { + do { /* Receive data */ + cnt--; + *rbuff++ = iic_rcvr(cnt ? 1 : 0); + } while (cnt); + } + } + } + + iic_stop(); /* Deselect device */ + + return cnt ? 0 : 1; +} + + + +int iic_write ( + BYTE dev, /* Device address */ + UINT adr, /* Write start address */ + UINT cnt, /* Write byte count */ + const BYTE *buff /* Data to be written */ +) +{ + const BYTE *wbuff = buff; + int n; + + + if (!cnt) return 0; + + n = 10; + do { /* Select device */ + iic_start(); + } while (!iic_send(dev) && --n); + if (n) { + if (iic_send((BYTE)adr)) { /* Set start address */ + do { /* Send data */ + if (!iic_send(*wbuff++)) break; + } while (--cnt); + } + } + + iic_stop(); /* Deselect device */ + + return cnt ? 0 : 1; +} + +/*-------------------------------------------------*/ +/* RTC functions */ + +int g9x_rtcGetTime (RTC *rtc) +{ + BYTE buf[8]; + + if (!iic_read(0xD0, 0, 7, buf)) return 0; + + rtc->sec = (buf[0] & 0x0F) + ((buf[0] >> 4) & 7) * 10; + rtc->min = (buf[1] & 0x0F) + (buf[1] >> 4) * 10; + rtc->hour = (buf[2] & 0x0F) + ((buf[2] >> 4) & 3) * 10; + rtc->wday = (buf[2] & 0x07); + rtc->mday = (buf[4] & 0x0F) + ((buf[4] >> 4) & 3) * 10; + rtc->month = (buf[5] & 0x0F) + ((buf[5] >> 4) & 1) * 10; + rtc->year = 2000 + (buf[6] & 0x0F) + (buf[6] >> 4) * 10; + + return 1; +} + +int g9x_rtcSetTime (const RTC *rtc) +{ + BYTE buf[8]; + + buf[0] = rtc->sec / 10 * 16 + rtc->sec % 10; + buf[1] = rtc->min / 10 * 16 + rtc->min % 10; + buf[2] = rtc->hour / 10 * 16 + rtc->hour % 10; + buf[3] = rtc->wday & 7; + buf[4] = rtc->mday / 10 * 16 + rtc->mday % 10; + buf[5] = rtc->month / 10 * 16 + rtc->month % 10; + buf[6] = (rtc->year - 2000) / 10 * 16 + (rtc->year - 2000) % 10; + return iic_write(0xD0, 0, 7, buf); +} + +void rtcGetTime(struct gtm * utm) +{ + RTC rtc = {0,0,0,0,0,0,0}; + + g9x_rtcGetTime(&rtc); + + utm->tm_year = rtc.year - TM_YEAR_BASE; + utm->tm_mon = rtc.month - 1; + utm->tm_mday = rtc.mday; + utm->tm_hour = rtc.hour; + utm->tm_min = rtc.min; + utm->tm_sec = rtc.sec; + utm->tm_wday = rtc.wday - 1; +} + +void rtcSetTime(const struct gtm * t) +{ + g_ms100 = 0; // start of next second begins now + + RTC rtc; + rtc.year = t->tm_year + TM_YEAR_BASE; + rtc.month = t->tm_mon + 1; + rtc.mday = t->tm_mday; + rtc.hour = t->tm_hour; + rtc.min = t->tm_min; + rtc.sec = t->tm_sec; + rtc.wday = t->tm_wday + 1; + g9x_rtcSetTime(&rtc); +} + +void rtcInit (void) +{ + BYTE buf[8]; /* RTC R/W buffer */ + UINT adr; + + + /* Read RTC registers */ + if (!iic_read(0xD0, 0, 8, buf)) return; /* IIC error */ + + if (buf[7] & 0x20) { /* When data has been volatiled, set default time */ + /* Clear nv-ram. Reg[8..63] */ + memset(buf, 0, 8); + for (adr = 8; adr < 64; adr += 8) + iic_write(0x0D, adr, 8, buf); + /* Reset time to Jan 1, '08. Reg[0..7] */ + buf[4] = 1; buf[5] = 1; buf[6] = 8; + iic_write(0x0D, 0, 8, buf); + } + + struct gtm utm; + rtcGetTime(&utm); + g_rtcTime = gmktime(&utm); +} + diff --git a/radio/src/targets/horus/adc_driver.cpp b/radio/src/targets/horus/adc_driver.cpp index c1d1acb02..bfd6f63f4 100644 --- a/radio/src/targets/horus/adc_driver.cpp +++ b/radio/src/targets/horus/adc_driver.cpp @@ -1,260 +1,260 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -uint16_t adcValues[NUM_ANALOGS] __DMA; - -#define ADC_CS_HIGH() (ADC_SPI_GPIO->BSRRL = ADC_SPI_PIN_CS) -#define ADC_CS_LOW() (ADC_SPI_GPIO->BSRRH = ADC_SPI_PIN_CS) - -#define SPI_STICK1 0 -#define SPI_STICK2 1 -#define SPI_STICK3 2 -#define SPI_STICK4 3 -#define SPI_S1 4 -#define SPI_6POS 5 -#define SPI_S2 6 -#define SPI_LS 7 -#define SPI_RS 8 -#define SPI_TX_VOLTAGE 9 -#define SPI_L2 10 -#define SPI_L1 11 -#define RESETCMD 0x4000 -#define MANUAL_MODE 0x1000 // manual mode channel 0 - -#define SAMPTIME 2 // sample time = 28 cycles - -uint16_t SPIx_ReadWriteByte(uint16_t value) -{ - while (SPI_I2S_GetFlagStatus(ADC_SPI, SPI_I2S_FLAG_TXE) == RESET); - SPI_I2S_SendData(ADC_SPI, value); - - while (SPI_I2S_GetFlagStatus(ADC_SPI, SPI_I2S_FLAG_RXNE) == RESET); - return SPI_I2S_ReceiveData(ADC_SPI); -} - -static void ADS7952_Init() -{ - GPIO_InitTypeDef GPIO_InitStructure; - SPI_InitTypeDef SPI_InitStructure; - - GPIO_InitStructure.GPIO_Pin = ADC_SPI_PIN_MISO | ADC_SPI_PIN_SCK | ADC_SPI_PIN_MOSI; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(ADC_SPI_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = ADC_SPI_PIN_CS; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(ADC_SPI_GPIO, &GPIO_InitStructure); - - GPIO_PinAFConfig(ADC_SPI_GPIO, ADC_SPI_PinSource_SCK, ADC_GPIO_AF); - GPIO_PinAFConfig(ADC_SPI_GPIO, ADC_SPI_PinSource_MISO, ADC_GPIO_AF); - GPIO_PinAFConfig(ADC_SPI_GPIO, ADC_SPI_PinSource_MOSI, ADC_GPIO_AF); - - SPI_I2S_DeInit(ADC_SPI); - - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_Init(ADC_SPI, &SPI_InitStructure); - SPI_Cmd(ADC_SPI, ENABLE); - SPI_I2S_ITConfig(ADC_SPI, SPI_I2S_IT_TXE, DISABLE); - SPI_I2S_ITConfig(ADC_SPI, SPI_I2S_IT_RXNE, DISABLE); - - ADC_CS_HIGH(); - delay_01us(1); - ADC_CS_LOW(); - SPIx_ReadWriteByte(RESETCMD); - ADC_CS_HIGH(); - delay_01us(1); - ADC_CS_LOW(); - SPIx_ReadWriteByte(MANUAL_MODE); - ADC_CS_HIGH(); -} - -void adcInit() -{ - ADS7952_Init(); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = ADC_GPIO_PIN_MOUSE1 | ADC_GPIO_PIN_MOUSE2; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(ADC_GPIO_MOUSE, &GPIO_InitStructure); - - ADC3->CR1 = ADC_CR1_SCAN; - ADC3->CR2 = ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_DDS; - ADC3->SQR1 = (2-1) << 20; - ADC3->SQR2 = 0; - ADC3->SQR3 = ADC_IN_MOUSE1 + (ADC_IN_MOUSE2<<5); - ADC3->SMPR1 = 0; - ADC3->SMPR2 = (ADC_SAMPTIME<<(3*ADC_IN_MOUSE1)) + (ADC_SAMPTIME<<(3*ADC_IN_MOUSE2)); - ADC->CCR = 0; - - // Enable the DMA channel here, DMA2 stream 1, channel 2 - ADC_DMA_Stream->CR = DMA_SxCR_PL | DMA_SxCR_CHSEL_1 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC; - ADC_DMA_Stream->PAR = CONVERT_PTR_UINT(&ADC3->DR); - ADC_DMA_Stream->M0AR = CONVERT_PTR_UINT(&adcValues[MOUSE1]); - ADC_DMA_Stream->NDTR = 2; - ADC_DMA_Stream->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0; -} - -const uint16_t adcCommands[MOUSE1+2] = -{ - MANUAL_MODE | (SPI_STICK1 << 7), - MANUAL_MODE | (SPI_STICK2 << 7), - MANUAL_MODE | (SPI_STICK3 << 7), - MANUAL_MODE | (SPI_STICK4 << 7), - MANUAL_MODE | (SPI_S1 << 7), - MANUAL_MODE | (SPI_6POS << 7), - MANUAL_MODE | (SPI_S2 << 7), - MANUAL_MODE | (SPI_L1 << 7), - MANUAL_MODE | (SPI_L2 << 7), - MANUAL_MODE | (SPI_LS << 7), - MANUAL_MODE | (SPI_RS << 7), - MANUAL_MODE | (SPI_TX_VOLTAGE << 7), - MANUAL_MODE | (0 << 7), // small joystick left/right - MANUAL_MODE | (0 << 7) // small joystick up/down -}; - -void adcReadSPIDummy() -{ - // A dummy command to get things started - // (because the sampled data is lagging behind for two command cycles) - ADC_CS_LOW(); - delay_01us(1); - SPIx_ReadWriteByte(adcCommands[0]); - ADC_CS_HIGH(); - delay_01us(1); -} - -uint32_t adcReadNextSPIChannel(uint8_t index) -{ - uint32_t result = 0; - - // This delay is to allow charging of ADC input capacitor - // after the MUX changes from one channel to the other. - // It was determined experimentally. Biggest problem seems to be - // the cross-talk between A4:S1 and A5:MULTIPOS. Changing S1 for one extreme - // to the other resulted in A5 change of: - // - // delay value A5 change Time needed for adcRead() - // 1 16 0.154ms - 0.156ms - // 38 5 0.197ms - 0.199ms - // 62 0 0.225ms - 0.243ms - delay_01us(40); - - for (uint8_t i = 0; i < 4; i++) { - ADC_CS_LOW(); - delay_01us(1); - // command is changed to the next index for the last two readings - // (because the sampled data is lagging behind for two command cycles) - uint16_t val = (0x0fff & SPIx_ReadWriteByte(adcCommands[(i>1) ? index+1 : index])); -#if defined(JITTER_MEASURE) - if (JITTER_MEASURE_ACTIVE()) { - rawJitter[index].measure(val); - } -#endif - ADC_CS_HIGH(); - delay_01us(1); - result += val; - } - - return result >> 2; -} - -void adcOnChipReadStart() -{ - ADC_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA - ADC3->SR &= ~(uint32_t)(ADC_SR_EOC | ADC_SR_STRT | ADC_SR_OVR); - ADC_DMA->LIFCR = DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 | DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0; // Write ones to clear bits - ADC_DMA_Stream->M0AR = CONVERT_PTR_UINT(&adcValues[MOUSE1]); - ADC_DMA_Stream->NDTR = 2; - ADC_DMA_Stream->CR |= DMA_SxCR_EN; // Enable DMA - ADC3->CR2 |= (uint32_t)ADC_CR2_SWSTART; -} - -bool adcOnChipReadFinished() -{ - return (ADC_DMA->LISR & DMA_LISR_TCIF0); -} - -void adcRead() -{ - uint16_t temp[NUM_ANALOGS-MOUSE1] = { 0 }; - uint8_t noInternalReads = 0; - - adcOnChipReadStart(); - adcReadSPIDummy(); - adcReadSPIDummy(); - for (uint32_t index=0; index> 2; - } -} - -#if !defined(SIMU) -const int8_t ana_direction[NUM_ANALOGS] = {1,-1,1,-1, -1,1,-1, -1,-1, -1,1, 0,0,0}; - -uint16_t getAnalogValue(uint8_t index) -{ - if (ana_direction[index] < 0) - return 4095 - adcValues[index]; - else - return adcValues[index]; -} -#endif // #if !defined(SIMU) +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +uint16_t adcValues[NUM_ANALOGS] __DMA; + +#define ADC_CS_HIGH() (ADC_SPI_GPIO->BSRRL = ADC_SPI_PIN_CS) +#define ADC_CS_LOW() (ADC_SPI_GPIO->BSRRH = ADC_SPI_PIN_CS) + +#define SPI_STICK1 0 +#define SPI_STICK2 1 +#define SPI_STICK3 2 +#define SPI_STICK4 3 +#define SPI_S1 4 +#define SPI_6POS 5 +#define SPI_S2 6 +#define SPI_LS 7 +#define SPI_RS 8 +#define SPI_TX_VOLTAGE 9 +#define SPI_L2 10 +#define SPI_L1 11 +#define RESETCMD 0x4000 +#define MANUAL_MODE 0x1000 // manual mode channel 0 + +#define SAMPTIME 2 // sample time = 28 cycles + +uint16_t SPIx_ReadWriteByte(uint16_t value) +{ + while (SPI_I2S_GetFlagStatus(ADC_SPI, SPI_I2S_FLAG_TXE) == RESET); + SPI_I2S_SendData(ADC_SPI, value); + + while (SPI_I2S_GetFlagStatus(ADC_SPI, SPI_I2S_FLAG_RXNE) == RESET); + return SPI_I2S_ReceiveData(ADC_SPI); +} + +static void ADS7952_Init() +{ + GPIO_InitTypeDef GPIO_InitStructure; + SPI_InitTypeDef SPI_InitStructure; + + GPIO_InitStructure.GPIO_Pin = ADC_SPI_PIN_MISO | ADC_SPI_PIN_SCK | ADC_SPI_PIN_MOSI; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(ADC_SPI_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = ADC_SPI_PIN_CS; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(ADC_SPI_GPIO, &GPIO_InitStructure); + + GPIO_PinAFConfig(ADC_SPI_GPIO, ADC_SPI_PinSource_SCK, ADC_GPIO_AF); + GPIO_PinAFConfig(ADC_SPI_GPIO, ADC_SPI_PinSource_MISO, ADC_GPIO_AF); + GPIO_PinAFConfig(ADC_SPI_GPIO, ADC_SPI_PinSource_MOSI, ADC_GPIO_AF); + + SPI_I2S_DeInit(ADC_SPI); + + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + SPI_Init(ADC_SPI, &SPI_InitStructure); + SPI_Cmd(ADC_SPI, ENABLE); + SPI_I2S_ITConfig(ADC_SPI, SPI_I2S_IT_TXE, DISABLE); + SPI_I2S_ITConfig(ADC_SPI, SPI_I2S_IT_RXNE, DISABLE); + + ADC_CS_HIGH(); + delay_01us(1); + ADC_CS_LOW(); + SPIx_ReadWriteByte(RESETCMD); + ADC_CS_HIGH(); + delay_01us(1); + ADC_CS_LOW(); + SPIx_ReadWriteByte(MANUAL_MODE); + ADC_CS_HIGH(); +} + +void adcInit() +{ + ADS7952_Init(); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = ADC_GPIO_PIN_MOUSE1 | ADC_GPIO_PIN_MOUSE2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(ADC_GPIO_MOUSE, &GPIO_InitStructure); + + ADC3->CR1 = ADC_CR1_SCAN; + ADC3->CR2 = ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_DDS; + ADC3->SQR1 = (2-1) << 20; + ADC3->SQR2 = 0; + ADC3->SQR3 = ADC_IN_MOUSE1 + (ADC_IN_MOUSE2<<5); + ADC3->SMPR1 = 0; + ADC3->SMPR2 = (ADC_SAMPTIME<<(3*ADC_IN_MOUSE1)) + (ADC_SAMPTIME<<(3*ADC_IN_MOUSE2)); + ADC->CCR = 0; + + // Enable the DMA channel here, DMA2 stream 1, channel 2 + ADC_DMA_Stream->CR = DMA_SxCR_PL | DMA_SxCR_CHSEL_1 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC; + ADC_DMA_Stream->PAR = CONVERT_PTR_UINT(&ADC3->DR); + ADC_DMA_Stream->M0AR = CONVERT_PTR_UINT(&adcValues[MOUSE1]); + ADC_DMA_Stream->NDTR = 2; + ADC_DMA_Stream->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0; +} + +const uint16_t adcCommands[MOUSE1+2] = +{ + MANUAL_MODE | (SPI_STICK1 << 7), + MANUAL_MODE | (SPI_STICK2 << 7), + MANUAL_MODE | (SPI_STICK3 << 7), + MANUAL_MODE | (SPI_STICK4 << 7), + MANUAL_MODE | (SPI_S1 << 7), + MANUAL_MODE | (SPI_6POS << 7), + MANUAL_MODE | (SPI_S2 << 7), + MANUAL_MODE | (SPI_L1 << 7), + MANUAL_MODE | (SPI_L2 << 7), + MANUAL_MODE | (SPI_LS << 7), + MANUAL_MODE | (SPI_RS << 7), + MANUAL_MODE | (SPI_TX_VOLTAGE << 7), + MANUAL_MODE | (0 << 7), // small joystick left/right + MANUAL_MODE | (0 << 7) // small joystick up/down +}; + +void adcReadSPIDummy() +{ + // A dummy command to get things started + // (because the sampled data is lagging behind for two command cycles) + ADC_CS_LOW(); + delay_01us(1); + SPIx_ReadWriteByte(adcCommands[0]); + ADC_CS_HIGH(); + delay_01us(1); +} + +uint32_t adcReadNextSPIChannel(uint8_t index) +{ + uint32_t result = 0; + + // This delay is to allow charging of ADC input capacitor + // after the MUX changes from one channel to the other. + // It was determined experimentally. Biggest problem seems to be + // the cross-talk between A4:S1 and A5:MULTIPOS. Changing S1 for one extreme + // to the other resulted in A5 change of: + // + // delay value A5 change Time needed for adcRead() + // 1 16 0.154ms - 0.156ms + // 38 5 0.197ms - 0.199ms + // 62 0 0.225ms - 0.243ms + delay_01us(40); + + for (uint8_t i = 0; i < 4; i++) { + ADC_CS_LOW(); + delay_01us(1); + // command is changed to the next index for the last two readings + // (because the sampled data is lagging behind for two command cycles) + uint16_t val = (0x0fff & SPIx_ReadWriteByte(adcCommands[(i>1) ? index+1 : index])); +#if defined(JITTER_MEASURE) + if (JITTER_MEASURE_ACTIVE()) { + rawJitter[index].measure(val); + } +#endif + ADC_CS_HIGH(); + delay_01us(1); + result += val; + } + + return result >> 2; +} + +void adcOnChipReadStart() +{ + ADC_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA + ADC3->SR &= ~(uint32_t)(ADC_SR_EOC | ADC_SR_STRT | ADC_SR_OVR); + ADC_DMA->LIFCR = DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 | DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0; // Write ones to clear bits + ADC_DMA_Stream->M0AR = CONVERT_PTR_UINT(&adcValues[MOUSE1]); + ADC_DMA_Stream->NDTR = 2; + ADC_DMA_Stream->CR |= DMA_SxCR_EN; // Enable DMA + ADC3->CR2 |= (uint32_t)ADC_CR2_SWSTART; +} + +bool adcOnChipReadFinished() +{ + return (ADC_DMA->LISR & DMA_LISR_TCIF0); +} + +void adcRead() +{ + uint16_t temp[NUM_ANALOGS-MOUSE1] = { 0 }; + uint8_t noInternalReads = 0; + + adcOnChipReadStart(); + adcReadSPIDummy(); + adcReadSPIDummy(); + for (uint32_t index=0; index> 2; + } +} + +#if !defined(SIMU) +const int8_t ana_direction[NUM_ANALOGS] = {1,-1,1,-1, -1,1,-1, -1,-1, -1,1, 0,0,0}; + +uint16_t getAnalogValue(uint8_t index) +{ + if (ana_direction[index] < 0) + return 4095 - adcValues[index]; + else + return adcValues[index]; +} +#endif // #if !defined(SIMU) diff --git a/radio/src/targets/horus/bluetooth_driver.cpp b/radio/src/targets/horus/bluetooth_driver.cpp index af7ad255a..9ba6026f3 100644 --- a/radio/src/targets/horus/bluetooth_driver.cpp +++ b/radio/src/targets/horus/bluetooth_driver.cpp @@ -1,261 +1,261 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -Fifo btTxFifo; -Fifo btRxFifo; - -enum BluetoothState -{ - BLUETOOTH_INIT, - BLUETOOTH_WAIT_TTM, - BLUETOOTH_WAIT_BAUDRATE_CHANGE, - BLUETOOTH_OK, -}; - -enum BluetoothWriteState -{ - BLUETOOTH_WRITE_IDLE, - BLUETOOTH_WRITE_INIT, - BLUETOOTH_WRITING, - BLUETOOTH_WRITE_DONE -}; - -volatile uint8_t bluetoothState = BLUETOOTH_INIT; -volatile uint8_t bluetoothWriteState = BLUETOOTH_WRITE_IDLE; - -void bluetoothInit(uint32_t baudrate) -{ - GPIO_InitTypeDef GPIO_InitStructure; - USART_InitTypeDef USART_InitStructure; - - USART_DeInit(BT_USART); - - RCC_AHB1PeriphClockCmd(BT_RCC_AHB1Periph, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); - - GPIO_InitStructure.GPIO_Pin = BT_EN_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BT_EN_GPIO, &GPIO_InitStructure); - -#if defined(BT_BRTS_GPIO_PIN) - GPIO_InitStructure.GPIO_Pin = BT_BRTS_GPIO_PIN; - GPIO_Init(BT_BRTS_GPIO, &GPIO_InitStructure); - GPIO_SetBits(BT_BRTS_GPIO, BT_BRTS_GPIO_PIN); -#endif - -#if defined(BT_BCTS_GPIO_PIN) - GPIO_InitStructure.GPIO_Pin = BT_BCTS_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_Init(BT_BCTS_GPIO, &GPIO_InitStructure); -#endif - - GPIO_InitStructure.GPIO_Pin = BT_TX_GPIO_PIN|BT_RX_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(BT_GPIO_TXRX, &GPIO_InitStructure); - - GPIO_PinAFConfig(BT_GPIO_TXRX, BT_TX_GPIO_PinSource, BT_GPIO_AF); - GPIO_PinAFConfig(BT_GPIO_TXRX, BT_RX_GPIO_PinSource, BT_GPIO_AF); - - USART_DeInit(BT_USART); - USART_InitStructure.USART_BaudRate = baudrate; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(BT_USART, &USART_InitStructure); - - USART_Cmd(BT_USART, ENABLE); - USART_ITConfig(BT_USART, USART_IT_RXNE, ENABLE); - - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = BT_USART_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 8; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - GPIO_ResetBits(BT_EN_GPIO, BT_EN_GPIO_PIN); // open bluetooth -} - -void bluetoothDone() -{ - GPIO_SetBits(BT_EN_GPIO, BT_EN_GPIO_PIN); // close bluetooth -} - -extern "C" void USART6_IRQHandler(void) -{ - DEBUG_INTERRUPT(INT_BLUETOOTH); - if (USART_GetITStatus(BT_USART, USART_IT_RXNE) != RESET) { - USART_ClearITPendingBit(BT_USART, USART_IT_RXNE); - uint8_t byte = USART_ReceiveData(BT_USART); - btRxFifo.push(byte); - } - - if (USART_GetITStatus(BT_USART, USART_IT_TXE) != RESET) { - uint8_t byte; - bool result = btTxFifo.pop(byte); - if (result) { - USART_SendData(BT_USART, byte); - } - else { - USART_ITConfig(BT_USART, USART_IT_TXE, DISABLE); - bluetoothWriteState = BLUETOOTH_WRITE_DONE; - } - } -} - -void bluetoothWrite(const void * buffer, int len) -{ - uint8_t * data = (uint8_t *)buffer; - for (int i=0; i waitEnd) { - TRACE("bt rename"); - char ttm[] = "TTM:REN"; - int index = 0; - uint8_t c; - bool found = false; - while (btRxFifo.pop(c)) { - if (c == ttm[index]) { - index++; - if (index == sizeof(ttm)-1) { - found = true; - break; - } - } - else { - index = 0; - } - } - if (found) { - TRACE("bt OK"); - bluetoothState = BLUETOOTH_OK; - } - else { - TRACE("bt failure"); - bluetoothInit(BLUETOOTH_FACTORY_BAUDRATE); - const char btMessage[] = "TTM:BPS-115200"; - bluetoothWriteString(btMessage); - bluetoothState = BLUETOOTH_WAIT_BAUDRATE_CHANGE; - waitEnd = get_tmr10ms() + 250; // 2.5s - } - } - } - else if (bluetoothState == BLUETOOTH_WAIT_BAUDRATE_CHANGE) { - if (get_tmr10ms() > waitEnd) { - bluetoothState = BLUETOOTH_INIT; - } - } - } - - bluetoothWriteWakeup(); - } -#endif // #if defined(BLUETOOTH_CLI_PASSTHROUGH) -} - -uint8_t bluetoothReady() -{ - return (bluetoothState == BLUETOOTH_OK); -} - -int bluetoothRead(void * buffer, int len) -{ - int result = 0; - uint8_t * data = (uint8_t *)buffer; - while (result < len) { - uint8_t byte; - if (!btRxFifo.pop(byte)) { - break; - } - data[result++] = byte; - } - return result; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +Fifo btTxFifo; +Fifo btRxFifo; + +enum BluetoothState +{ + BLUETOOTH_INIT, + BLUETOOTH_WAIT_TTM, + BLUETOOTH_WAIT_BAUDRATE_CHANGE, + BLUETOOTH_OK, +}; + +enum BluetoothWriteState +{ + BLUETOOTH_WRITE_IDLE, + BLUETOOTH_WRITE_INIT, + BLUETOOTH_WRITING, + BLUETOOTH_WRITE_DONE +}; + +volatile uint8_t bluetoothState = BLUETOOTH_INIT; +volatile uint8_t bluetoothWriteState = BLUETOOTH_WRITE_IDLE; + +void bluetoothInit(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + + USART_DeInit(BT_USART); + + RCC_AHB1PeriphClockCmd(BT_RCC_AHB1Periph, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); + + GPIO_InitStructure.GPIO_Pin = BT_EN_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(BT_EN_GPIO, &GPIO_InitStructure); + +#if defined(BT_BRTS_GPIO_PIN) + GPIO_InitStructure.GPIO_Pin = BT_BRTS_GPIO_PIN; + GPIO_Init(BT_BRTS_GPIO, &GPIO_InitStructure); + GPIO_SetBits(BT_BRTS_GPIO, BT_BRTS_GPIO_PIN); +#endif + +#if defined(BT_BCTS_GPIO_PIN) + GPIO_InitStructure.GPIO_Pin = BT_BCTS_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_Init(BT_BCTS_GPIO, &GPIO_InitStructure); +#endif + + GPIO_InitStructure.GPIO_Pin = BT_TX_GPIO_PIN|BT_RX_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(BT_GPIO_TXRX, &GPIO_InitStructure); + + GPIO_PinAFConfig(BT_GPIO_TXRX, BT_TX_GPIO_PinSource, BT_GPIO_AF); + GPIO_PinAFConfig(BT_GPIO_TXRX, BT_RX_GPIO_PinSource, BT_GPIO_AF); + + USART_DeInit(BT_USART); + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(BT_USART, &USART_InitStructure); + + USART_Cmd(BT_USART, ENABLE); + USART_ITConfig(BT_USART, USART_IT_RXNE, ENABLE); + + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = BT_USART_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 8; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + GPIO_ResetBits(BT_EN_GPIO, BT_EN_GPIO_PIN); // open bluetooth +} + +void bluetoothDone() +{ + GPIO_SetBits(BT_EN_GPIO, BT_EN_GPIO_PIN); // close bluetooth +} + +extern "C" void USART6_IRQHandler(void) +{ + DEBUG_INTERRUPT(INT_BLUETOOTH); + if (USART_GetITStatus(BT_USART, USART_IT_RXNE) != RESET) { + USART_ClearITPendingBit(BT_USART, USART_IT_RXNE); + uint8_t byte = USART_ReceiveData(BT_USART); + btRxFifo.push(byte); + } + + if (USART_GetITStatus(BT_USART, USART_IT_TXE) != RESET) { + uint8_t byte; + bool result = btTxFifo.pop(byte); + if (result) { + USART_SendData(BT_USART, byte); + } + else { + USART_ITConfig(BT_USART, USART_IT_TXE, DISABLE); + bluetoothWriteState = BLUETOOTH_WRITE_DONE; + } + } +} + +void bluetoothWrite(const void * buffer, int len) +{ + uint8_t * data = (uint8_t *)buffer; + for (int i=0; i waitEnd) { + TRACE("bt rename"); + char ttm[] = "TTM:REN"; + int index = 0; + uint8_t c; + bool found = false; + while (btRxFifo.pop(c)) { + if (c == ttm[index]) { + index++; + if (index == sizeof(ttm)-1) { + found = true; + break; + } + } + else { + index = 0; + } + } + if (found) { + TRACE("bt OK"); + bluetoothState = BLUETOOTH_OK; + } + else { + TRACE("bt failure"); + bluetoothInit(BLUETOOTH_FACTORY_BAUDRATE); + const char btMessage[] = "TTM:BPS-115200"; + bluetoothWriteString(btMessage); + bluetoothState = BLUETOOTH_WAIT_BAUDRATE_CHANGE; + waitEnd = get_tmr10ms() + 250; // 2.5s + } + } + } + else if (bluetoothState == BLUETOOTH_WAIT_BAUDRATE_CHANGE) { + if (get_tmr10ms() > waitEnd) { + bluetoothState = BLUETOOTH_INIT; + } + } + } + + bluetoothWriteWakeup(); + } +#endif // #if defined(BLUETOOTH_CLI_PASSTHROUGH) +} + +uint8_t bluetoothReady() +{ + return (bluetoothState == BLUETOOTH_OK); +} + +int bluetoothRead(void * buffer, int len) +{ + int result = 0; + uint8_t * data = (uint8_t *)buffer; + while (result < len) { + uint8_t byte; + if (!btRxFifo.pop(byte)) { + break; + } + data[result++] = byte; + } + return result; +} diff --git a/radio/src/targets/horus/diskio.cpp b/radio/src/targets/horus/diskio.cpp index 47c2c9ca5..489865b5c 100644 --- a/radio/src/targets/horus/diskio.cpp +++ b/radio/src/targets/horus/diskio.cpp @@ -1,376 +1,376 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2007 */ -/*-----------------------------------------------------------------------*/ -/* This is a stub disk I/O module that acts as front end of the existing */ -/* disk I/O modules and attach it to FatFs module with common interface. */ -/*-----------------------------------------------------------------------*/ - -#include "diskio.h" -#include -#include "opentx.h" -#include "sdio_sd.h" - -/*-----------------------------------------------------------------------*/ -/* Lock / unlock functions */ -/*-----------------------------------------------------------------------*/ -#if !defined(BOOT) -static OS_MutexID ioMutex; -uint32_t ioMutexReq = 0, ioMutexRel = 0; -int ff_cre_syncobj (BYTE vol, _SYNC_t *mutex) -{ - *mutex = ioMutex; - return 1; -} - -int ff_req_grant (_SYNC_t mutex) -{ - ioMutexReq += 1; - return CoEnterMutexSection(mutex) == E_OK; -} - -void ff_rel_grant (_SYNC_t mutex) -{ - ioMutexRel += 1; - CoLeaveMutexSection(mutex); -} - -int ff_del_syncobj (_SYNC_t mutex) -{ - return 1; -} -#endif - - -/*-----------------------------------------------------------------------*/ -/* Inidialize a Drive */ - -DSTATUS disk_initialize ( - BYTE drv /* Physical drive nmuber (0..) */ -) -{ - DSTATUS stat = 0; - - /* Supports only single drive */ - if (drv) - { - stat |= STA_NOINIT; - } - - /*-------------------------- SD Init ----------------------------- */ - SD_Error res = SD_Init(); - if (res != SD_OK) - { - TRACE("SD_Init() failed: %d", res); - stat |= STA_NOINIT; - } - - TRACE("SD card info:"); - TRACE("sectors: %u", (uint32_t)(SDCardInfo.CardCapacity / 512)); - TRACE("type: %u", (uint32_t)(SDCardInfo.CardType)); - TRACE("EraseGrSize: %u", (uint32_t)(SDCardInfo.SD_csd.EraseGrSize)); - TRACE("EraseGrMul: %u", (uint32_t)(SDCardInfo.SD_csd.EraseGrMul)); - TRACE("ManufacturerID: %u", (uint32_t)(SDCardInfo.SD_cid.ManufacturerID)); - - return(stat); -} - -DWORD scratch[BLOCK_SIZE / 4] __DMA; - -/*-----------------------------------------------------------------------*/ -/* Return Disk Status */ - -DSTATUS disk_status ( - BYTE drv /* Physical drive nmuber (0..) */ -) -{ - DSTATUS stat = 0; - - if (SD_Detect() != SD_PRESENT) - stat |= STA_NODISK; - - // STA_NOTINIT - Subsystem not initailized - // STA_PROTECTED - Write protected, MMC/SD switch if available - - return(stat); -} - -uint32_t sdReadRetries = 0; - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ - - -DRESULT disk_read_dma(BYTE drv, BYTE * buff, DWORD sector, UINT count) -{ - // this functions assumes that buff is properly aligned and in the right RAM segment for DMA - DRESULT res; - SD_Error Status; - SDTransferState State; - for (int retry=0; retry<3; retry++) { - res = RES_OK; - if (count == 1) { - Status = SD_ReadBlock(buff, sector, BLOCK_SIZE); // 4GB Compliant - } - else { - Status = SD_ReadMultiBlocks(buff, sector, BLOCK_SIZE, count); // 4GB Compliant - } - if (Status == SD_OK) { - Status = SD_WaitReadOperation(200*count); // Check if the Transfer is finished - while ((State = SD_GetStatus()) == SD_TRANSFER_BUSY); // BUSY, OK (DONE), ERROR (FAIL) - if (State == SD_TRANSFER_ERROR) { - TRACE("State=SD_TRANSFER_ERROR, c: %u", sector, (uint32_t)count); - res = RES_ERROR; - } - else if (Status != SD_OK) { - TRACE("Status(WaitRead)=%d, s:%u c: %u", Status, sector, (uint32_t)count); - res = RES_ERROR; - } - } - else { - TRACE("Status(ReadBlock)=%d, s:%u c: %u", Status, sector, (uint32_t)count); - res = RES_ERROR; - } - if (res == RES_OK) break; - sdReadRetries += 1; - } - return res; -} - -DRESULT __disk_read(BYTE drv, BYTE * buff, DWORD sector, UINT count) -{ - // If unaligned, do the single block reads with a scratch buffer. - // If aligned and single sector, do a single block read. - // If aligned and multiple sectors, try multi block read. - // If multi block read fails, try single block reads without - // an intermediate buffer (move trough the provided buffer) - - // TRACE("disk_read %d %p %10d %d", drv, buff, sector, count); - if (SD_Detect() != SD_PRESENT) { - TRACE("SD_Detect() != SD_PRESENT"); - return RES_NOTRDY; - } - - DRESULT res = RES_OK; - if (count == 0) return res; - - if ((DWORD)buff < 0x20000000 || ((DWORD)buff & 3)) { - // buffer is not aligned, use scratch buffer that is aligned - TRACE("disk_read bad alignment (%p)", buff); - while (count--) { - res = disk_read_dma(drv, (BYTE *)scratch, sector++, 1); - if (res != RES_OK) break; - memcpy(buff, scratch, BLOCK_SIZE); - buff += BLOCK_SIZE; - } - return res; - } - - res = disk_read_dma(drv, buff, sector, count); - if (res != RES_OK && count > 1) { - // multi-read failed, try reading same sectors, one by one - TRACE("disk_read() multi-block failed, trying single block reads..."); - while (count--) { - res = disk_read_dma(drv, buff, sector++, 1); - if (res != RES_OK) break; - buff += BLOCK_SIZE; - } - } - return res; -} - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ - -#if _READONLY == 0 -DRESULT __disk_write( - BYTE drv, /* Physical drive nmuber (0..) */ - const BYTE *buff, /* Data to be written */ - DWORD sector, /* Sector address (LBA) */ - UINT count /* Number of sectors to write (1..255) */ -) -{ - SD_Error Status; - DRESULT res = RES_OK; - - // TRACE("disk_write %d %p %10d %d", drv, buff, sector, count); - - if (SD_Detect() != SD_PRESENT) - return(RES_NOTRDY); - - if ((DWORD)buff < 0x20000000 || ((DWORD)buff & 3)) { - TRACE("disk_write bad alignment (%p)", buff); - while(count--) { - memcpy(scratch, buff, BLOCK_SIZE); - - res = __disk_write(drv, (BYTE *)scratch, sector++, 1); - - if (res != RES_OK) - break; - - buff += BLOCK_SIZE; - } - return(res); - } - - if (count == 1) { - Status = SD_WriteBlock((uint8_t *)buff, sector, BLOCK_SIZE); // 4GB Compliant - } - else { - Status = SD_WriteMultiBlocks((uint8_t *)buff, sector, BLOCK_SIZE, count); // 4GB Compliant - } - - if (Status == SD_OK) { - SDTransferState State; - - Status = SD_WaitWriteOperation(500*count); // Check if the Transfer is finished - - while((State = SD_GetStatus()) == SD_TRANSFER_BUSY); // BUSY, OK (DONE), ERROR (FAIL) - - if ((State == SD_TRANSFER_ERROR) || (Status != SD_OK)) { - TRACE("__disk_write() err, st:%d,%d, s:%u c: %u", Status, State, sector, (uint32_t)count); - res = RES_ERROR; - } - } - else { - res = RES_ERROR; - } - - // TRACE("result=%d", res); - return res; -} -#endif /* _READONLY */ - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ - -DRESULT disk_ioctl ( - BYTE drv, /* Physical drive nmuber (0..) */ - BYTE ctrl, /* Control code */ - void *buff /* Buffer to send/receive control data */ -) -{ - DRESULT res; - - if (drv) return RES_PARERR; - - res = RES_ERROR; - - switch (ctrl) { - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ - // use 512 for sector size, SDCardInfo.CardBlockSize is not sector size and can be 1024 for 2G SD cards!!!! - *(DWORD*)buff = SDCardInfo.CardCapacity / BLOCK_SIZE; - res = RES_OK; - break; - - case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ - *(WORD*)buff = BLOCK_SIZE; // force sector size. SDCardInfo.CardBlockSize is not sector size and can be 1024 for 2G SD cards!!!! - res = RES_OK; - break; - - case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ - // TODO verify that this is the correct value - *(DWORD*)buff = (uint32_t)SDCardInfo.SD_csd.EraseGrSize * (uint32_t)SDCardInfo.SD_csd.EraseGrMul; - res = RES_OK; - break; - - case CTRL_SYNC: - while (SD_GetStatus() == SD_TRANSFER_BUSY); /* Complete pending write process (needed at _FS_READONLY == 0) */ - res = RES_OK; - break; - - default: - res = RES_OK; - break; - - } - - return res; -} - -// TODO everything here should not be in the driver layer ... - -FATFS g_FATFS_Obj __DMA; // initialized in boardInit() -#if defined(LOG_TELEMETRY) -FIL g_telemetryFile = {}; -#endif - -void sdInit() -{ - TRACE("sdInit"); - - ioMutex = CoCreateMutex(); - if (ioMutex >= CFG_MAX_MUTEX) { - // sd error - return; - } - sdMount(); -} - -void sdMount() -{ - TRACE("sdMount"); - - diskCache.clear(); - - if (f_mount(&g_FATFS_Obj, "", 1) == FR_OK) { - // call sdGetFreeSectors() now because f_getfree() takes a long time first time it's called - sdGetFreeSectors(); - -#if defined(LOG_TELEMETRY) - f_open(&g_telemetryFile, LOGS_PATH "/telemetry.log", FA_OPEN_ALWAYS | FA_WRITE); - if (f_size(&g_telemetryFile) > 0) { - f_lseek(&g_telemetryFile, f_size(&g_telemetryFile)); // append - } -#endif - } - else { - TRACE("f_mount() failed"); - } -} - -void sdDone() -{ - TRACE("sdDone"); - - if (sdMounted()) { - audioQueue.stopSD(); -#if defined(LOG_TELEMETRY) - f_close(&g_telemetryFile); -#endif - f_mount(NULL, "", 0); // unmount SD - } -} - -uint32_t sdMounted() -{ - return g_FATFS_Obj.fs_type != 0; -} - -uint32_t sdIsHC() -{ - return true; // TODO (CardType & CT_BLOCK); -} - -uint32_t sdGetSpeed() -{ - return 330000; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2007 */ +/*-----------------------------------------------------------------------*/ +/* This is a stub disk I/O module that acts as front end of the existing */ +/* disk I/O modules and attach it to FatFs module with common interface. */ +/*-----------------------------------------------------------------------*/ + +#include "diskio.h" +#include +#include "opentx.h" +#include "sdio_sd.h" + +/*-----------------------------------------------------------------------*/ +/* Lock / unlock functions */ +/*-----------------------------------------------------------------------*/ +#if !defined(BOOT) +static OS_MutexID ioMutex; +uint32_t ioMutexReq = 0, ioMutexRel = 0; +int ff_cre_syncobj (BYTE vol, _SYNC_t *mutex) +{ + *mutex = ioMutex; + return 1; +} + +int ff_req_grant (_SYNC_t mutex) +{ + ioMutexReq += 1; + return CoEnterMutexSection(mutex) == E_OK; +} + +void ff_rel_grant (_SYNC_t mutex) +{ + ioMutexRel += 1; + CoLeaveMutexSection(mutex); +} + +int ff_del_syncobj (_SYNC_t mutex) +{ + return 1; +} +#endif + + +/*-----------------------------------------------------------------------*/ +/* Inidialize a Drive */ + +DSTATUS disk_initialize ( + BYTE drv /* Physical drive nmuber (0..) */ +) +{ + DSTATUS stat = 0; + + /* Supports only single drive */ + if (drv) + { + stat |= STA_NOINIT; + } + + /*-------------------------- SD Init ----------------------------- */ + SD_Error res = SD_Init(); + if (res != SD_OK) + { + TRACE("SD_Init() failed: %d", res); + stat |= STA_NOINIT; + } + + TRACE("SD card info:"); + TRACE("sectors: %u", (uint32_t)(SDCardInfo.CardCapacity / 512)); + TRACE("type: %u", (uint32_t)(SDCardInfo.CardType)); + TRACE("EraseGrSize: %u", (uint32_t)(SDCardInfo.SD_csd.EraseGrSize)); + TRACE("EraseGrMul: %u", (uint32_t)(SDCardInfo.SD_csd.EraseGrMul)); + TRACE("ManufacturerID: %u", (uint32_t)(SDCardInfo.SD_cid.ManufacturerID)); + + return(stat); +} + +DWORD scratch[BLOCK_SIZE / 4] __DMA; + +/*-----------------------------------------------------------------------*/ +/* Return Disk Status */ + +DSTATUS disk_status ( + BYTE drv /* Physical drive nmuber (0..) */ +) +{ + DSTATUS stat = 0; + + if (SD_Detect() != SD_PRESENT) + stat |= STA_NODISK; + + // STA_NOTINIT - Subsystem not initailized + // STA_PROTECTED - Write protected, MMC/SD switch if available + + return(stat); +} + +uint32_t sdReadRetries = 0; + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ + + +DRESULT disk_read_dma(BYTE drv, BYTE * buff, DWORD sector, UINT count) +{ + // this functions assumes that buff is properly aligned and in the right RAM segment for DMA + DRESULT res; + SD_Error Status; + SDTransferState State; + for (int retry=0; retry<3; retry++) { + res = RES_OK; + if (count == 1) { + Status = SD_ReadBlock(buff, sector, BLOCK_SIZE); // 4GB Compliant + } + else { + Status = SD_ReadMultiBlocks(buff, sector, BLOCK_SIZE, count); // 4GB Compliant + } + if (Status == SD_OK) { + Status = SD_WaitReadOperation(200*count); // Check if the Transfer is finished + while ((State = SD_GetStatus()) == SD_TRANSFER_BUSY); // BUSY, OK (DONE), ERROR (FAIL) + if (State == SD_TRANSFER_ERROR) { + TRACE("State=SD_TRANSFER_ERROR, c: %u", sector, (uint32_t)count); + res = RES_ERROR; + } + else if (Status != SD_OK) { + TRACE("Status(WaitRead)=%d, s:%u c: %u", Status, sector, (uint32_t)count); + res = RES_ERROR; + } + } + else { + TRACE("Status(ReadBlock)=%d, s:%u c: %u", Status, sector, (uint32_t)count); + res = RES_ERROR; + } + if (res == RES_OK) break; + sdReadRetries += 1; + } + return res; +} + +DRESULT __disk_read(BYTE drv, BYTE * buff, DWORD sector, UINT count) +{ + // If unaligned, do the single block reads with a scratch buffer. + // If aligned and single sector, do a single block read. + // If aligned and multiple sectors, try multi block read. + // If multi block read fails, try single block reads without + // an intermediate buffer (move trough the provided buffer) + + // TRACE("disk_read %d %p %10d %d", drv, buff, sector, count); + if (SD_Detect() != SD_PRESENT) { + TRACE("SD_Detect() != SD_PRESENT"); + return RES_NOTRDY; + } + + DRESULT res = RES_OK; + if (count == 0) return res; + + if ((DWORD)buff < 0x20000000 || ((DWORD)buff & 3)) { + // buffer is not aligned, use scratch buffer that is aligned + TRACE("disk_read bad alignment (%p)", buff); + while (count--) { + res = disk_read_dma(drv, (BYTE *)scratch, sector++, 1); + if (res != RES_OK) break; + memcpy(buff, scratch, BLOCK_SIZE); + buff += BLOCK_SIZE; + } + return res; + } + + res = disk_read_dma(drv, buff, sector, count); + if (res != RES_OK && count > 1) { + // multi-read failed, try reading same sectors, one by one + TRACE("disk_read() multi-block failed, trying single block reads..."); + while (count--) { + res = disk_read_dma(drv, buff, sector++, 1); + if (res != RES_OK) break; + buff += BLOCK_SIZE; + } + } + return res; +} + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ + +#if _READONLY == 0 +DRESULT __disk_write( + BYTE drv, /* Physical drive nmuber (0..) */ + const BYTE *buff, /* Data to be written */ + DWORD sector, /* Sector address (LBA) */ + UINT count /* Number of sectors to write (1..255) */ +) +{ + SD_Error Status; + DRESULT res = RES_OK; + + // TRACE("disk_write %d %p %10d %d", drv, buff, sector, count); + + if (SD_Detect() != SD_PRESENT) + return(RES_NOTRDY); + + if ((DWORD)buff < 0x20000000 || ((DWORD)buff & 3)) { + TRACE("disk_write bad alignment (%p)", buff); + while(count--) { + memcpy(scratch, buff, BLOCK_SIZE); + + res = __disk_write(drv, (BYTE *)scratch, sector++, 1); + + if (res != RES_OK) + break; + + buff += BLOCK_SIZE; + } + return(res); + } + + if (count == 1) { + Status = SD_WriteBlock((uint8_t *)buff, sector, BLOCK_SIZE); // 4GB Compliant + } + else { + Status = SD_WriteMultiBlocks((uint8_t *)buff, sector, BLOCK_SIZE, count); // 4GB Compliant + } + + if (Status == SD_OK) { + SDTransferState State; + + Status = SD_WaitWriteOperation(500*count); // Check if the Transfer is finished + + while((State = SD_GetStatus()) == SD_TRANSFER_BUSY); // BUSY, OK (DONE), ERROR (FAIL) + + if ((State == SD_TRANSFER_ERROR) || (Status != SD_OK)) { + TRACE("__disk_write() err, st:%d,%d, s:%u c: %u", Status, State, sector, (uint32_t)count); + res = RES_ERROR; + } + } + else { + res = RES_ERROR; + } + + // TRACE("result=%d", res); + return res; +} +#endif /* _READONLY */ + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ + +DRESULT disk_ioctl ( + BYTE drv, /* Physical drive nmuber (0..) */ + BYTE ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ +) +{ + DRESULT res; + + if (drv) return RES_PARERR; + + res = RES_ERROR; + + switch (ctrl) { + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ + // use 512 for sector size, SDCardInfo.CardBlockSize is not sector size and can be 1024 for 2G SD cards!!!! + *(DWORD*)buff = SDCardInfo.CardCapacity / BLOCK_SIZE; + res = RES_OK; + break; + + case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ + *(WORD*)buff = BLOCK_SIZE; // force sector size. SDCardInfo.CardBlockSize is not sector size and can be 1024 for 2G SD cards!!!! + res = RES_OK; + break; + + case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ + // TODO verify that this is the correct value + *(DWORD*)buff = (uint32_t)SDCardInfo.SD_csd.EraseGrSize * (uint32_t)SDCardInfo.SD_csd.EraseGrMul; + res = RES_OK; + break; + + case CTRL_SYNC: + while (SD_GetStatus() == SD_TRANSFER_BUSY); /* Complete pending write process (needed at _FS_READONLY == 0) */ + res = RES_OK; + break; + + default: + res = RES_OK; + break; + + } + + return res; +} + +// TODO everything here should not be in the driver layer ... + +FATFS g_FATFS_Obj __DMA; // initialized in boardInit() +#if defined(LOG_TELEMETRY) +FIL g_telemetryFile = {}; +#endif + +void sdInit() +{ + TRACE("sdInit"); + + ioMutex = CoCreateMutex(); + if (ioMutex >= CFG_MAX_MUTEX) { + // sd error + return; + } + sdMount(); +} + +void sdMount() +{ + TRACE("sdMount"); + + diskCache.clear(); + + if (f_mount(&g_FATFS_Obj, "", 1) == FR_OK) { + // call sdGetFreeSectors() now because f_getfree() takes a long time first time it's called + sdGetFreeSectors(); + +#if defined(LOG_TELEMETRY) + f_open(&g_telemetryFile, LOGS_PATH "/telemetry.log", FA_OPEN_ALWAYS | FA_WRITE); + if (f_size(&g_telemetryFile) > 0) { + f_lseek(&g_telemetryFile, f_size(&g_telemetryFile)); // append + } +#endif + } + else { + TRACE("f_mount() failed"); + } +} + +void sdDone() +{ + TRACE("sdDone"); + + if (sdMounted()) { + audioQueue.stopSD(); +#if defined(LOG_TELEMETRY) + f_close(&g_telemetryFile); +#endif + f_mount(NULL, "", 0); // unmount SD + } +} + +uint32_t sdMounted() +{ + return g_FATFS_Obj.fs_type != 0; +} + +uint32_t sdIsHC() +{ + return true; // TODO (CardType & CT_BLOCK); +} + +uint32_t sdGetSpeed() +{ + return 330000; +} diff --git a/radio/src/targets/horus/extmodule_driver.cpp b/radio/src/targets/horus/extmodule_driver.cpp index 57a541a41..e94d1d082 100644 --- a/radio/src/targets/horus/extmodule_driver.cpp +++ b/radio/src/targets/horus/extmodule_driver.cpp @@ -1,309 +1,309 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void extmoduleSendNextFrame(); - -void extmoduleStop() -{ - EXTERNAL_MODULE_OFF(); - - NVIC_DisableIRQ(EXTMODULE_DMA_IRQn); - NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn); - - EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - EXTMODULE_TIMER->DIER &= ~(TIM_DIER_CC2IE | TIM_DIER_UDE); - EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; -} - -void extmoduleNoneStart() -{ - EXTERNAL_MODULE_OFF(); - - GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, 0); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); - GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high - - EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) - EXTMODULE_TIMER->ARR = 36000; // 18mS - EXTMODULE_TIMER->CCR2 = 32000; // Update time - EXTMODULE_TIMER->EGR = 1; // Restart - EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; - EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - - NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn); - NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); -} - -void extmodulePpmStart() -{ - EXTERNAL_MODULE_ON(); - - GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); - - // PPM generation principle: - // - // Hardware timer in PWM mode is used for PPM generation - // Output is OFF if CNTCR1 &= ~TIM_CR1_CEN; // Stop timer - EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) - EXTMODULE_TIMER->ARR = 45000; -#if PCBREV >= 13 - EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2; // PWM mode 1 - EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; - EXTMODULE_TIMER->EGR = 1; // Reloads register values now - EXTMODULE_TIMER->DIER = TIM_DIER_UDE; // Update DMA request - EXTMODULE_TIMER->CR1 = TIM_CR1_CEN; // Start timer -#else - EXTMODULE_TIMER->CCR1 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; - EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1P : 0); - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high - EXTMODULE_TIMER->EGR = 1; // Reloads register values now - EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Update DMA request - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE; // PWM mode 1 - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; // Start timer -#endif - - extmoduleSendNextFrame(); - - NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); - NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); - NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn); - NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); -} - -void extmodulePxxStart() -{ - EXTERNAL_MODULE_ON(); - - GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); - - EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) - EXTMODULE_TIMER->ARR = 18000; - -#if PCBREV >= 13 - EXTMODULE_TIMER->CCER = TIM_CCER_CC3E | TIM_CCER_CC3NE; - EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs - EXTMODULE_TIMER->CCR3 = 18; - EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0; // Force O/P high - EXTMODULE_TIMER->EGR = 1; // Restart - EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update - EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2; - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; -#else - EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP; // TIM_CCER_CC1E | TIM_CCER_CC1P; - EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs - EXTMODULE_TIMER->CCR1 = 18; - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high - EXTMODULE_TIMER->EGR = 1; // Restart - EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; -#endif - - extmoduleSendNextFrame(); - - NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); - NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); - NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn); - NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); -} - -#if defined(DSM2) -void extmoduleDsm2Start() -{ - EXTERNAL_MODULE_ON(); - - GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); - - EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) - EXTMODULE_TIMER->ARR = 44000; // 22mS - -#if PCBREV >= 13 - EXTMODULE_TIMER->CCER = TIM_CCER_CC3E | TIM_CCER_CC3P; - EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs - EXTMODULE_TIMER->CCR3 = 0; - EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0; // Force O/P high - EXTMODULE_TIMER->EGR = 1; // Restart - EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update - EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; -#else - EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P; - EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs - EXTMODULE_TIMER->CCR1 = 0; - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high - EXTMODULE_TIMER->EGR = 1; // Restart - EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0; - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; -#endif - - extmoduleSendNextFrame(); - - NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); - NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); - NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn); - NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); -} -#endif - -void extmoduleCrossfireStart() -{ - EXTERNAL_MODULE_ON(); - - GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, 0); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); - GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high - - EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) - EXTMODULE_TIMER->ARR = (2000 * CROSSFIRE_FRAME_PERIOD); - EXTMODULE_TIMER->CCR2 = (2000 * CROSSFIRE_FRAME_PERIOD) - 1000; - EXTMODULE_TIMER->EGR = 1; // Restart - EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; - EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - - NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn); - NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); -} - -void extmoduleSendNextFrame() -{ - if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) { -#if PCBREV >= 13 - EXTMODULE_TIMER->CCR3 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; - EXTMODULE_TIMER->CCER = TIM_CCER_CC3E | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC3P : 0); - EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance - EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; -#else - EXTMODULE_TIMER->CCR1 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; - EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1P : 0); - EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance - EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_1 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; -#endif - EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); - EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].ppm.pulses); - EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].ppm.ptr - modulePulsesData[EXTERNAL_MODULE].ppm.pulses; - EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA - } - else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) { - EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].pxx.ptr - 1) - 4000; // 2mS in advance - EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA -#if PCBREV >= 13 - EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; -#else - EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_1 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; -#endif - EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); - EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].pxx.pulses); - EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].pxx.ptr - modulePulsesData[EXTERNAL_MODULE].pxx.pulses; - EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA - } - else if (IS_DSM2_PROTOCOL(s_current_protocol[EXTERNAL_MODULE]) || IS_MULTIMODULE_PROTOCOL(s_current_protocol[EXTERNAL_MODULE])) { - EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - 1) - 4000; // 2mS in advance - EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA -#if PCBREV >= 13 - EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; -#else - EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_1 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; -#endif - EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); - EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses); - EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - modulePulsesData[EXTERNAL_MODULE].dsm2.pulses; - EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA - } - else { - EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; - } -} - -extern "C" void EXTMODULE_DMA_IRQHandler() -{ - if (!DMA_GetITStatus(EXTMODULE_DMA_STREAM, EXTMODULE_DMA_FLAG_TC)) - return; - - DMA_ClearITPendingBit(EXTMODULE_DMA_STREAM, EXTMODULE_DMA_FLAG_TC); - - EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag - EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt -} - -extern "C" void EXTMODULE_TIMER_IRQHandler() -{ - EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // Stop this interrupt - EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; - setupPulses(EXTERNAL_MODULE); - extmoduleSendNextFrame(); -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +void extmoduleSendNextFrame(); + +void extmoduleStop() +{ + EXTERNAL_MODULE_OFF(); + + NVIC_DisableIRQ(EXTMODULE_DMA_IRQn); + NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn); + + EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + EXTMODULE_TIMER->DIER &= ~(TIM_DIER_CC2IE | TIM_DIER_UDE); + EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; +} + +void extmoduleNoneStart() +{ + EXTERNAL_MODULE_OFF(); + + GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, 0); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); + GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high + + EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) + EXTMODULE_TIMER->ARR = 36000; // 18mS + EXTMODULE_TIMER->CCR2 = 32000; // Update time + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; + EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; + + NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn); + NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); +} + +void extmodulePpmStart() +{ + EXTERNAL_MODULE_ON(); + + GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); + + // PPM generation principle: + // + // Hardware timer in PWM mode is used for PPM generation + // Output is OFF if CNTCR1 &= ~TIM_CR1_CEN; // Stop timer + EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) + EXTMODULE_TIMER->ARR = 45000; +#if PCBREV >= 13 + EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2; // PWM mode 1 + EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; + EXTMODULE_TIMER->EGR = 1; // Reloads register values now + EXTMODULE_TIMER->DIER = TIM_DIER_UDE; // Update DMA request + EXTMODULE_TIMER->CR1 = TIM_CR1_CEN; // Start timer +#else + EXTMODULE_TIMER->CCR1 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; + EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1P : 0); + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high + EXTMODULE_TIMER->EGR = 1; // Reloads register values now + EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Update DMA request + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE; // PWM mode 1 + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; // Start timer +#endif + + extmoduleSendNextFrame(); + + NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); + NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); + NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn); + NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); +} + +void extmodulePxxStart() +{ + EXTERNAL_MODULE_ON(); + + GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); + + EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) + EXTMODULE_TIMER->ARR = 18000; + +#if PCBREV >= 13 + EXTMODULE_TIMER->CCER = TIM_CCER_CC3E | TIM_CCER_CC3NE; + EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs + EXTMODULE_TIMER->CCR3 = 18; + EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0; // Force O/P high + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update + EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2; + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; +#else + EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP; // TIM_CCER_CC1E | TIM_CCER_CC1P; + EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs + EXTMODULE_TIMER->CCR1 = 18; + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; +#endif + + extmoduleSendNextFrame(); + + NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); + NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); + NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn); + NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); +} + +#if defined(DSM2) +void extmoduleDsm2Start() +{ + EXTERNAL_MODULE_ON(); + + GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); + + EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) + EXTMODULE_TIMER->ARR = 44000; // 22mS + +#if PCBREV >= 13 + EXTMODULE_TIMER->CCER = TIM_CCER_CC3E | TIM_CCER_CC3P; + EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs + EXTMODULE_TIMER->CCR3 = 0; + EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0; // Force O/P high + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update + EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; +#else + EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P; + EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs + EXTMODULE_TIMER->CCR1 = 0; + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0; + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; +#endif + + extmoduleSendNextFrame(); + + NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); + NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); + NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn); + NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); +} +#endif + +void extmoduleCrossfireStart() +{ + EXTERNAL_MODULE_ON(); + + GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, 0); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); + GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high + + EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) + EXTMODULE_TIMER->ARR = (2000 * CROSSFIRE_FRAME_PERIOD); + EXTMODULE_TIMER->CCR2 = (2000 * CROSSFIRE_FRAME_PERIOD) - 1000; + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; + EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; + + NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn); + NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); +} + +void extmoduleSendNextFrame() +{ + if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) { +#if PCBREV >= 13 + EXTMODULE_TIMER->CCR3 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; + EXTMODULE_TIMER->CCER = TIM_CCER_CC3E | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC3P : 0); + EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance + EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#else + EXTMODULE_TIMER->CCR1 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; + EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1P : 0); + EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance + EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_1 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#endif + EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); + EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].ppm.pulses); + EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].ppm.ptr - modulePulsesData[EXTERNAL_MODULE].ppm.pulses; + EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA + } + else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) { + EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].pxx.ptr - 1) - 4000; // 2mS in advance + EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA +#if PCBREV >= 13 + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#else + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_1 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#endif + EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); + EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].pxx.pulses); + EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].pxx.ptr - modulePulsesData[EXTERNAL_MODULE].pxx.pulses; + EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA + } + else if (IS_DSM2_PROTOCOL(s_current_protocol[EXTERNAL_MODULE]) || IS_MULTIMODULE_PROTOCOL(s_current_protocol[EXTERNAL_MODULE])) { + EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - 1) - 4000; // 2mS in advance + EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA +#if PCBREV >= 13 + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#else + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_1 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#endif + EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); + EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses); + EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - modulePulsesData[EXTERNAL_MODULE].dsm2.pulses; + EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA + } + else { + EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; + } +} + +extern "C" void EXTMODULE_DMA_IRQHandler() +{ + if (!DMA_GetITStatus(EXTMODULE_DMA_STREAM, EXTMODULE_DMA_FLAG_TC)) + return; + + DMA_ClearITPendingBit(EXTMODULE_DMA_STREAM, EXTMODULE_DMA_FLAG_TC); + + EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag + EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt +} + +extern "C" void EXTMODULE_TIMER_IRQHandler() +{ + EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // Stop this interrupt + EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; + setupPulses(EXTERNAL_MODULE); + extmoduleSendNextFrame(); +} diff --git a/radio/src/targets/horus/hal.h b/radio/src/targets/horus/hal.h index b57753ed7..16d811ddf 100644 --- a/radio/src/targets/horus/hal.h +++ b/radio/src/targets/horus/hal.h @@ -1,627 +1,627 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _HAL_H_ -#define _HAL_H_ - -// Keys -#define KEYS_RCC_AHB1Periph_GPIO (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOJ) -#if defined(PCBX12S) - #define KEYS_GPIO_REG_PGUP GPIOC->IDR - #define KEYS_GPIO_PIN_PGUP GPIO_Pin_13 // PC.13 - #define KEYS_GPIO_REG_PGDN GPIOI->IDR - #define KEYS_GPIO_PIN_PGDN GPIO_Pin_8 // PI.08 - #define KEYS_GPIO_REG_LEFT GPIOI->IDR - #define KEYS_GPIO_PIN_LEFT GPIO_Pin_7 // PI.07 - #define KEYS_GPIO_REG_ENTER GPIOC->IDR - #define KEYS_GPIO_PIN_ENTER GPIO_Pin_1 // PC.01 - #define KEYS_GPIO_REG_UP GPIOG->IDR - #define KEYS_GPIO_PIN_UP GPIO_Pin_13 // PG.13 - #define KEYS_GPIO_REG_DOWN GPIOI->IDR - #define KEYS_GPIO_PIN_DOWN GPIO_Pin_6 // PI.06 - #define KEYS_GPIO_REG_RIGHT GPIOC->IDR - #define KEYS_GPIO_PIN_RIGHT GPIO_Pin_4 // PC.04 -#elif defined(PCBX10) - #define KEYS_GPIO_REG_PGDN GPIOI->IDR - #define KEYS_GPIO_PIN_PGDN GPIO_Pin_11 // PI.11 - #define KEYS_GPIO_REG_LEFT GPIOI->IDR - #define KEYS_GPIO_PIN_LEFT GPIO_Pin_7 // PI.07 - #define KEYS_GPIO_REG_ENTER GPIOI->IDR - #define KEYS_GPIO_PIN_ENTER GPIO_Pin_8 // PI.08 - #define KEYS_GPIO_REG_UP GPIOI->IDR - #define KEYS_GPIO_PIN_UP GPIO_Pin_4 // PI.04 - #define KEYS_GPIO_REG_DOWN GPIOI->IDR - #define KEYS_GPIO_PIN_DOWN GPIO_Pin_6 // PI.06 - #define KEYS_GPIO_REG_RIGHT GPIOI->IDR - #define KEYS_GPIO_PIN_RIGHT GPIO_Pin_5 // PI.05 -#endif - -// Rotary Encoder -#define ROTARY_ENCODER_GPIO GPIOH -#define ROTARY_ENCODER_GPIO_PIN_A GPIO_Pin_11 // PH.11 -#define ROTARY_ENCODER_GPIO_PIN_B GPIO_Pin_10 // PH.10 -#define ROTARY_ENCODER_POSITION() ((ROTARY_ENCODER_GPIO->IDR >> 10) & 0x03) - -// Switches -#define SWITCHES_GPIO_REG_A_H GPIOH->IDR -#define SWITCHES_GPIO_PIN_A_H GPIO_Pin_9 // PH.09 -#define SWITCHES_GPIO_REG_A_L GPIOI->IDR -#define SWITCHES_GPIO_PIN_A_L GPIO_Pin_15 // PI.15 -#define SWITCHES_GPIO_REG_B_H GPIOH->IDR -#define SWITCHES_GPIO_PIN_B_H GPIO_Pin_12 // PH.12 -#define SWITCHES_GPIO_REG_B_L GPIOB->IDR -#define SWITCHES_GPIO_PIN_B_L GPIO_Pin_12 // PB.12 -#define SWITCHES_GPIO_REG_C_H GPIOD->IDR -#define SWITCHES_GPIO_PIN_C_H GPIO_Pin_11 // PD.11 -#define SWITCHES_GPIO_REG_C_L GPIOB->IDR -#define SWITCHES_GPIO_PIN_C_L GPIO_Pin_15 // PB.15 -#define SWITCHES_GPIO_REG_D_H GPIOJ->IDR -#define SWITCHES_GPIO_PIN_D_H GPIO_Pin_7 // PJ.07 -#define SWITCHES_GPIO_REG_D_L GPIOG->IDR -#define SWITCHES_GPIO_PIN_D_L GPIO_Pin_2 // PG.02 -#define SWITCHES_GPIO_REG_E_H GPIOH->IDR -#define SWITCHES_GPIO_PIN_E_H GPIO_Pin_4 // PH.04 -#define SWITCHES_GPIO_REG_E_L GPIOE->IDR -#define SWITCHES_GPIO_PIN_E_L GPIO_Pin_3 // PE.03 -#define SWITCHES_GPIO_REG_F GPIOH->IDR -#define SWITCHES_GPIO_PIN_F GPIO_Pin_3 // PH.03 -#define SWITCHES_GPIO_REG_G_H GPIOG->IDR -#define SWITCHES_GPIO_PIN_G_H GPIO_Pin_6 // PG.06 -#define SWITCHES_GPIO_REG_G_L GPIOG->IDR -#define SWITCHES_GPIO_PIN_G_L GPIO_Pin_3 // PG.03 -#define SWITCHES_GPIO_REG_H GPIOG->IDR -#define SWITCHES_GPIO_PIN_H GPIO_Pin_7 // PG.07 - -#if defined(PCBX10) - #define SWITCHES_GPIO_REG_GMBL GPIOH->IDR - #define SWITCHES_GPIO_PIN_GMBL GPIO_Pin_14 - #define SWITCHES_GPIO_REG_GMBR GPIOH->IDR - #define SWITCHES_GPIO_PIN_GMBR GPIO_Pin_15 -#endif - -// Trims -#if defined(PCBX12S) - #define TRIMS_GPIO_REG_RHL GPIOC->IDR - #define TRIMS_GPIO_PIN_RHL GPIO_Pin_0 // PC.00 - #define TRIMS_GPIO_REG_RHR GPIOI->IDR - #define TRIMS_GPIO_PIN_RHR GPIO_Pin_4 // PI.04 - #define TRIMS_GPIO_REG_RVD GPIOG->IDR - #define TRIMS_GPIO_PIN_RVD GPIO_Pin_12 // PG.12 - #define TRIMS_GPIO_REG_RVU GPIOJ->IDR - #define TRIMS_GPIO_PIN_RVU GPIO_Pin_14 // PJ.14 - #define TRIMS_GPIO_REG_LVD GPIOJ->IDR - #define TRIMS_GPIO_PIN_LVD GPIO_Pin_13 // PJ.13 - #define TRIMS_GPIO_REG_LHL GPIOD->IDR - #define TRIMS_GPIO_PIN_LHL GPIO_Pin_3 // PD.03 - #define TRIMS_GPIO_REG_LVU GPIOJ->IDR - #define TRIMS_GPIO_PIN_LVU GPIO_Pin_12 // PJ.12 - #define TRIMS_GPIO_REG_LHR GPIOD->IDR - #define TRIMS_GPIO_PIN_LHR GPIO_Pin_7 // PD.07 - #define TRIMS_GPIO_REG_RSD GPIOJ->IDR - #define TRIMS_GPIO_PIN_RSD GPIO_Pin_8 // PJ.08 - #define TRIMS_GPIO_REG_RSU GPIOD->IDR - #define TRIMS_GPIO_PIN_RSU GPIO_Pin_13 // PD.13 - #define TRIMS_GPIO_REG_LSD GPIOB->IDR - #define TRIMS_GPIO_PIN_LSD GPIO_Pin_14 // PB.14 - #define TRIMS_GPIO_REG_LSU GPIOB->IDR - #define TRIMS_GPIO_PIN_LSU GPIO_Pin_13 // PB.13 -#elif defined(PCBX10) - #define TRIMS_GPIO_REG_LHL GPIOB->IDR - #define TRIMS_GPIO_PIN_LHL GPIO_Pin_8 // PB.08 - #define TRIMS_GPIO_REG_LHR GPIOB->IDR - #define TRIMS_GPIO_PIN_LHR GPIO_Pin_9 // PB.09 - #define TRIMS_GPIO_REG_LVD GPIOG->IDR - #define TRIMS_GPIO_PIN_LVD GPIO_Pin_12 // PG.12 - #define TRIMS_GPIO_REG_LVU GPIOJ->IDR - #define TRIMS_GPIO_PIN_LVU GPIO_Pin_14 // PJ.14 - #define TRIMS_GPIO_REG_RVD GPIOJ->IDR - #define TRIMS_GPIO_PIN_RVD GPIO_Pin_13 // PJ.13 - #define TRIMS_GPIO_REG_RHL GPIOD->IDR - #define TRIMS_GPIO_PIN_RHL GPIO_Pin_3 // PD.03 - #define TRIMS_GPIO_REG_RVU GPIOJ->IDR - #define TRIMS_GPIO_PIN_RVU GPIO_Pin_12 // PJ.12 - #define TRIMS_GPIO_REG_RHR GPIOD->IDR - #define TRIMS_GPIO_PIN_RHR GPIO_Pin_7 // PD.07 - #define TRIMS_GPIO_REG_LSU GPIOJ->IDR - #define TRIMS_GPIO_PIN_LSU GPIO_Pin_8 // PJ.08 - #define TRIMS_GPIO_REG_LSD GPIOD->IDR - #define TRIMS_GPIO_PIN_LSD GPIO_Pin_13 // PD.13 - #define TRIMS_GPIO_REG_RSU GPIOB->IDR - #define TRIMS_GPIO_PIN_RSU GPIO_Pin_14 // PB.14 - #define TRIMS_GPIO_REG_RSD GPIOB->IDR - #define TRIMS_GPIO_PIN_RSD GPIO_Pin_13 // PB.13 -#endif - -// Index of all keys -#if defined(PCBX12S) - #define KEYS_GPIOB_PINS (SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_C_L | TRIMS_GPIO_PIN_LSD | TRIMS_GPIO_PIN_LSU) - #define KEYS_GPIOC_PINS (KEYS_GPIO_PIN_PGUP | KEYS_GPIO_PIN_ENTER | KEYS_GPIO_PIN_RIGHT | TRIMS_GPIO_PIN_RHL) - #define KEYS_GPIOD_PINS (SWITCHES_GPIO_PIN_C_H | TRIMS_GPIO_PIN_LHL | TRIMS_GPIO_PIN_LHR | TRIMS_GPIO_PIN_RSU) - #define KEYS_GPIOE_PINS (SWITCHES_GPIO_PIN_E_L) - #define KEYS_GPIOG_PINS (KEYS_GPIO_PIN_UP | SWITCHES_GPIO_PIN_D_L | SWITCHES_GPIO_PIN_G_H | SWITCHES_GPIO_PIN_G_L | SWITCHES_GPIO_PIN_H | TRIMS_GPIO_PIN_RVD) - #define KEYS_GPIOH_PINS (SWITCHES_GPIO_PIN_A_H | SWITCHES_GPIO_PIN_B_H | SWITCHES_GPIO_PIN_E_H | SWITCHES_GPIO_PIN_F | ROTARY_ENCODER_GPIO_PIN_A | ROTARY_ENCODER_GPIO_PIN_B) - #define KEYS_GPIOI_PINS (KEYS_GPIO_PIN_PGDN | KEYS_GPIO_PIN_LEFT | KEYS_GPIO_PIN_DOWN | SWITCHES_GPIO_PIN_A_L | TRIMS_GPIO_PIN_RHR) - #define KEYS_GPIOJ_PINS (SWITCHES_GPIO_PIN_D_H | TRIMS_GPIO_PIN_RVU | TRIMS_GPIO_PIN_LVD | TRIMS_GPIO_PIN_LVU | TRIMS_GPIO_PIN_RSD) -#elif defined(PCBX10) - #define KEYS_GPIOB_PINS (SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_C_L | TRIMS_GPIO_PIN_RSU | TRIMS_GPIO_PIN_RSD | TRIMS_GPIO_PIN_LHL | TRIMS_GPIO_PIN_LHR) - #define KEYS_GPIOC_PINS (TRIMS_GPIO_PIN_LHL) - #define KEYS_GPIOD_PINS (SWITCHES_GPIO_PIN_C_H | TRIMS_GPIO_PIN_RHL | TRIMS_GPIO_PIN_RHR | TRIMS_GPIO_PIN_LSD) - #define KEYS_GPIOE_PINS (SWITCHES_GPIO_PIN_E_L) - #define KEYS_GPIOG_PINS (SWITCHES_GPIO_PIN_D_L | SWITCHES_GPIO_PIN_G_H | SWITCHES_GPIO_PIN_G_L | SWITCHES_GPIO_PIN_H | TRIMS_GPIO_PIN_LVD) - #define KEYS_GPIOH_PINS (SWITCHES_GPIO_PIN_A_H | SWITCHES_GPIO_PIN_B_H | SWITCHES_GPIO_PIN_E_H | SWITCHES_GPIO_PIN_F | ROTARY_ENCODER_GPIO_PIN_A | ROTARY_ENCODER_GPIO_PIN_B | SWITCHES_GPIO_PIN_GMBR | SWITCHES_GPIO_PIN_GMBL) - #define KEYS_GPIOI_PINS (KEYS_GPIO_PIN_RIGHT | KEYS_GPIO_PIN_UP | KEYS_GPIO_PIN_ENTER | KEYS_GPIO_PIN_PGDN | KEYS_GPIO_PIN_LEFT | KEYS_GPIO_PIN_DOWN | SWITCHES_GPIO_PIN_A_L) - #define KEYS_GPIOJ_PINS (SWITCHES_GPIO_PIN_D_H | TRIMS_GPIO_PIN_LVU | TRIMS_GPIO_PIN_RVD | TRIMS_GPIO_PIN_RVU | TRIMS_GPIO_PIN_LSU) -#endif - -// ADC -#if defined(PCBX12S) - #define ADC_RCC_AHB1Periph (RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_DMA2) - #define ADC_RCC_APB2Periph (RCC_APB2Periph_SPI4 | RCC_APB2Periph_ADC3) - #define ADC_SPI SPI4 - #define ADC_GPIO_AF GPIO_AF_SPI4 - #define ADC_SPI_GPIO GPIOE - #define ADC_SPI_PIN_SCK GPIO_Pin_2 // PE.02 - #define ADC_SPI_PIN_CS GPIO_Pin_4 // PE.04 - #define ADC_SPI_PIN_MOSI GPIO_Pin_6 // PE.06 - #define ADC_SPI_PIN_MISO GPIO_Pin_5 // PE.05 - #define ADC_SPI_PinSource_SCK GPIO_PinSource2 - #define ADC_SPI_PinSource_MISO GPIO_PinSource5 - #define ADC_SPI_PinSource_MOSI GPIO_PinSource6 - #define ADC_GPIO_PIN_MOUSE1 GPIO_Pin_8 // PF.08 ADC3_IN6 J5 MOUSE_X - #define ADC_GPIO_PIN_MOUSE2 GPIO_Pin_9 // PF.09 ADC3_IN7 J6 MOUSE_Y - #define ADC_GPIO_MOUSE GPIOF - #define ADC_IN_MOUSE1 6 - #define ADC_IN_MOUSE2 7 - #define ADC_DMA DMA2 - #define ADC_DMA_Stream DMA2_Stream0 - #define ADC_SAMPTIME 3 -#elif defined(PCBX10) - #define ADC_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_DMA2) - #define ADC_RCC_APB2Periph (RCC_APB2Periph_ADC3) - #define ADC_GPIO_PIN_STICK_LH GPIO_Pin_0 // PC.00 - #define ADC_GPIO_PIN_STICK_LV GPIO_Pin_1 // PC.01 - #define ADC_GPIO_PIN_STICK_RH GPIO_Pin_2 // PC.02 - #define ADC_GPIO_PIN_STICK_RV GPIO_Pin_3 // PC.03 - #define ADC_GPIO_PIN_SLIDER1 GPIO_Pin_6 // PF.06 - #define ADC_GPIO_PIN_SLIDER2 GPIO_Pin_3 // PA.03 - #define ADC_GPIO_PIN_BATT GPIO_Pin_7 // PF.07 - #define ADC_GPIO_PIN_POT3 GPIO_Pin_0 // PA.00 - #define ADC_GPIO_PIN_POT1 GPIO_Pin_2 // PA.02 - #define ADC_GPIO_PIN_POT2 GPIO_Pin_1 // PA.01 - #define ADC_GPIO_PIN_EXT1 GPIO_Pin_8 // PF.08 - #define ADC_GPIO_PIN_EXT2 GPIO_Pin_9 // PF.09 - #define ADC_GPIOA_PINS (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3) - #define ADC_GPIOC_PINS (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3) - #define ADC_GPIOF_PINS (GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9) - #define ADC_CHANNEL_STICK_LH ADC_Channel_10 // ADC1_IN10 - #define ADC_CHANNEL_STICK_LV ADC_Channel_11 // ADC1_IN11 - #define ADC_CHANNEL_STICK_RH ADC_Channel_12 // ADC1_IN12 - #define ADC_CHANNEL_STICK_RV ADC_Channel_13 // ADC1_IN13 - #define ADC_CHANNEL_SLIDER1 ADC_Channel_4 // ADC1_IN4 - #define ADC_CHANNEL_SLIDER2 ADC_Channel_3 // ADC1_IN3 - #define ADC_CHANNEL_BATT ADC_Channel_5 // ADC1_IN5 - #define ADC_CHANNEL_POT3 ADC_Channel_0 // ADC1_IN0 - #define ADC_CHANNEL_POT1 ADC_Channel_2 // ADC1_IN2 - #define ADC_CHANNEL_POT2 ADC_Channel_1 // ADC1_IN1 - #define ADC_CHANNEL_EXT1 ADC_Channel_6 // ADC1_IN6 - #define ADC_CHANNEL_EXT2 ADC_Channel_7 // ADC1_IN7 - #define ADC_MAIN ADC3 - #define ADC_SAMPTIME 3 - #define ADC_DMA DMA2 - #define ADC_DMA_SxCR_CHSEL DMA_SxCR_CHSEL_1 - #define ADC_DMA_Stream DMA2_Stream0 - #define ADC_SET_DMA_FLAGS() ADC_DMA->LIFCR = (DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 | DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0) - #define ADC_TRANSFER_COMPLETE() (ADC_DMA->LISR & DMA_LISR_TCIF0) -#endif - -// Power -#define PWR_RCC_AHB1Periph RCC_AHB1Periph_GPIOJ -#define PWR_GPIO GPIOJ -#define PWR_ON_GPIO_PIN GPIO_Pin_1 // PJ.01 -#define PWR_SWITCH_GPIO_PIN GPIO_Pin_0 // PJ.00 - -#if defined(PCBX10) - #define SPORT_PWR_RCC_AHB1Periph RCC_AHB1Periph_GPIOH - #define SPORT_PWR_GPIO GPIOH - #define SPORT_PWR_GPIO_PIN GPIO_Pin_13 // PH.13 -#endif - -// PCBREV -#define PCBREV_RCC_AHB1Periph RCC_AHB1Periph_GPIOI -#define PCBREV_GPIO GPIOI -#define PCBREV_GPIO_PIN GPIO_Pin_11 // PI.11 - -// Led -#if defined(PCBX12S) - #define LED_RCC_AHB1Periph RCC_AHB1Periph_GPIOI - #define LED_GPIO GPIOI - #define LED_GPIO_PIN GPIO_Pin_5 // PI.05 -#elif defined(PCBX10) - #define LED_RCC_AHB1Periph RCC_AHB1Periph_GPIOE - #define LED_GPIO GPIOE - #define LED_RED_GPIO_PIN GPIO_Pin_5 - #define LED_GREEN_GPIO_PIN GPIO_Pin_4 - #define LED_BLUE_GPIO_PIN GPIO_Pin_6 - #define LED_GPIO_PIN (LED_RED_GPIO_PIN | LED_GREEN_GPIO_PIN | LED_BLUE_GPIO_PIN) -#endif - -// Serial Port (DEBUG) -#define SERIAL_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) -#define SERIAL_RCC_APB1Periph RCC_APB1Periph_USART3 -#define SERIAL_GPIO GPIOB -#define SERIAL_GPIO_PIN_TX GPIO_Pin_10 // PB.10 -#define SERIAL_GPIO_PIN_RX GPIO_Pin_11 // PB.11 -#define SERIAL_GPIO_PinSource_TX GPIO_PinSource10 -#define SERIAL_GPIO_PinSource_RX GPIO_PinSource11 -#define SERIAL_GPIO_AF GPIO_AF_USART3 -#define SERIAL_USART USART3 -#define SERIAL_USART_IRQHandler USART3_IRQHandler -#define SERIAL_USART_IRQn USART3_IRQn -#define SERIAL_DMA_Stream_RX DMA1_Stream1 -#define SERIAL_DMA_Channel_RX DMA_Channel_4 - -// Telemetry -#define TELEMETRY_RCC_AHB1Periph (RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) -#define TELEMETRY_RCC_APB1Periph RCC_APB1Periph_USART2 -#define TELEMETRY_DIR_GPIO GPIOD -#define TELEMETRY_DIR_GPIO_PIN GPIO_Pin_4 // PD.04 -#define TELEMETRY_GPIO GPIOD -#define TELEMETRY_TX_GPIO_PIN GPIO_Pin_5 // PD.05 -#define TELEMETRY_RX_GPIO_PIN GPIO_Pin_6 // PD.06 -#define TELEMETRY_GPIO_PinSource_TX GPIO_PinSource5 -#define TELEMETRY_GPIO_PinSource_RX GPIO_PinSource6 -#define TELEMETRY_GPIO_AF GPIO_AF_USART2 -#define TELEMETRY_USART USART2 -#if defined(PCBX12S) -#define TELEMETRY_DMA_Stream_RX DMA1_Stream5 -#define TELEMETRY_DMA_Channel_RX DMA_Channel_4 -#endif -#define TELEMETRY_DMA_Stream_TX DMA1_Stream6 -#define TELEMETRY_DMA_Channel_TX DMA_Channel_4 -#define TELEMETRY_DMA_TX_Stream_IRQ DMA1_Stream6_IRQn -#define TELEMETRY_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler -#define TELEMETRY_DMA_TX_FLAG_TC DMA_IT_TCIF6 -#define TELEMETRY_USART_IRQHandler USART2_IRQHandler -#define TELEMETRY_USART_IRQn USART2_IRQn - -// USB -#define USB_RCC_AHB1Periph_GPIO RCC_AHB1Periph_GPIOA -#define USB_GPIO GPIOA -#define USB_GPIO_PIN_VBUS GPIO_Pin_9 // PA.09 -#define USB_GPIO_PIN_DM GPIO_Pin_11 // PA.11 -#define USB_GPIO_PIN_DP GPIO_Pin_12 // PA.12 -#define USB_GPIO_PinSource_DM GPIO_PinSource11 -#define USB_GPIO_PinSource_DP GPIO_PinSource12 -#define USB_GPIO_AF GPIO_AF_OTG1_FS - -// LCD -#define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOJ | RCC_AHB1Periph_GPIOK | RCC_AHB1Periph_DMA2D) -#define LCD_RCC_APB2Periph RCC_APB2Periph_LTDC -#if defined(PCBX12S) - #define LCD_GPIO_NRST GPIOF - #define LCD_GPIO_PIN_NRST GPIO_Pin_10 // PF.10 -#elif defined(PCBX10) - #define LCD_GPIO_NRST GPIOI - #define LCD_GPIO_PIN_NRST GPIO_Pin_10 // PI.10 -#endif -#define LTDC_IRQ_PRIO 4 -#define DMA_SCREEN_IRQ_PRIO 6 - -// Backlight -#if defined(PCBX12S) - #define BL_RCC_AHB1Periph RCC_AHB1Periph_GPIOA - #define BL_GPIO GPIOA - #if PCBREV >= 13 - #define BL_TIMER TIM5 - #define BL_GPIO_PIN GPIO_Pin_3 // PA.03 - #define BL_GPIO_PinSource GPIO_PinSource3 - #define BL_RCC_APB1Periph RCC_APB1Periph_TIM5 - #define BL_RCC_APB2Periph 0 - #define BL_GPIO_AF GPIO_AF_TIM5 - #define BL_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) - #else - #define BL_TIMER TIM8 - #define BL_GPIO_PIN GPIO_Pin_5 // PA.05 - #define BL_GPIO_PinSource GPIO_PinSource5 - #define BL_RCC_APB1Periph 0 - #define BL_RCC_APB2Periph RCC_APB2Periph_TIM8 - #define BL_GPIO_AF GPIO_AF_TIM8 - #define BL_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) - #endif -#elif defined(PCBX10) - #define BL_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define BL_GPIO GPIOB - #define BL_TIMER TIM8 - #define BL_GPIO_PIN GPIO_Pin_1 // PB.01 - #define BL_GPIO_PinSource GPIO_PinSource1 - #define BL_RCC_APB1Periph 0 - #define BL_RCC_APB2Periph RCC_APB2Periph_TIM8 - #define BL_GPIO_AF GPIO_AF_TIM8 - #define BL_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) -#endif - -// SD -#define SD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) -#define SD_PRESENT_GPIO GPIOC -#define SD_PRESENT_GPIO_PIN GPIO_Pin_5 // PC.05 -#define SD_SDIO_DMA_STREAM DMA2_Stream3 -#define SD_SDIO_DMA_CHANNEL DMA_Channel_4 -#define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF3 -#define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF3 -#define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF3 -#define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF3 -#define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF3 -#define SD_SDIO_DMA_IRQn DMA2_Stream3_IRQn -#define SD_SDIO_DMA_IRQHANDLER DMA2_Stream3_IRQHandler -#define SD_SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80) -#define SD_SDIO_CLK_DIV(fq) ((48000000 / (fq)) - 2) -#define SD_SDIO_INIT_CLK_DIV SD_SDIO_CLK_DIV(400000) -#define SD_SDIO_TRANSFER_CLK_DIV SD_SDIO_CLK_DIV(24000000) - -// EEPROM -#if defined(PCBX12S) && PCBREV >= 13 - #define EEPROM_RCC_AHB1Periph RCC_AHB1Periph_GPIOA - #define EEPROM_RCC_APB1Periph RCC_APB1Periph_SPI1 - #define EEPROM_SPI_CS_GPIO GPIOA - #define EEPROM_SPI_CS_GPIO_PIN GPIO_Pin_15 // PA.15 - #define EEPROM_SPI_SCK_GPIO GPIOA - #define EEPROM_SPI_SCK_GPIO_PIN GPIO_Pin_5 // PA.05 - #define EEPROM_SPI_SCK_GPIO_PinSource GPIO_PinSource5 - #define EEPROM_SPI_MISO_GPIO GPIOA - #define EEPROM_SPI_MISO_GPIO_PIN GPIO_Pin_6 // PA.06 - #define EEPROM_SPI_MISO_GPIO_PinSource GPIO_PinSource6 - #define EEPROM_SPI_MOSI_GPIO GPIOA - #define EEPROM_SPI_MOSI_GPIO_PIN GPIO_Pin_7 // PA.07 - #define EEPROM_SPI_MOSI_GPIO_PinSource GPIO_PinSource7 -#elif defined(PCBX10) - #define EEPROM_RCC_AHB1Periph RCC_AHB1Periph_GPIOI - #define EEPROM_RCC_APB1Periph RCC_APB1Periph_SPI2 - #define EEPROM_SPI_CS_GPIO GPIOI - #define EEPROM_SPI_CS_GPIO_PIN GPIO_Pin_0 // PI.00 - #define EEPROM_SPI_SCK_GPIO GPIOI - #define EEPROM_SPI_SCK_GPIO_PIN GPIO_Pin_1 // PI.01 - #define EEPROM_SPI_SCK_GPIO_PinSource GPIO_PinSource1 - #define EEPROM_SPI_MISO_GPIO GPIOI - #define EEPROM_SPI_MISO_GPIO_PIN GPIO_Pin_2 // PI.02 - #define EEPROM_SPI_MISO_GPIO_PinSource GPIO_PinSource2 - #define EEPROM_SPI_MOSI_GPIO GPIOI - #define EEPROM_SPI_MOSI_GPIO_PIN GPIO_Pin_3 // PI.03 - #define EEPROM_SPI_MOSI_GPIO_PinSource GPIO_PinSource3 -#endif - -// Audio -#if defined(PCBX12S) - #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOH) - #define AUDIO_RCC_APB1Periph RCC_APB1Periph_SPI2 - #define AUDIO_SHUTDOWN_GPIO GPIOI - #define AUDIO_SHUTDOWN_GPIO_PIN GPIO_Pin_9 // PI.09 - #define AUDIO_XDCS_GPIO GPIOI - #define AUDIO_XDCS_GPIO_PIN GPIO_Pin_0 // PI.00 - #define AUDIO_CS_GPIO GPIOH - #define AUDIO_CS_GPIO_PIN GPIO_Pin_13 // PH.13 - #define AUDIO_DREQ_GPIO GPIOH - #define AUDIO_DREQ_GPIO_PIN GPIO_Pin_14 // PH.14 - #define AUDIO_RST_GPIO GPIOH - #define AUDIO_RST_GPIO_PIN GPIO_Pin_15 // PH.15 - #define AUDIO_SPI SPI2 - #define AUDIO_SPI_GPIO_AF GPIO_AF_SPI2 - #define AUDIO_SPI_SCK_GPIO GPIOI - #define AUDIO_SPI_SCK_GPIO_PIN GPIO_Pin_1 // PI.01 - #define AUDIO_SPI_SCK_GPIO_PinSource GPIO_PinSource1 - #define AUDIO_SPI_MISO_GPIO GPIOI - #define AUDIO_SPI_MISO_GPIO_PIN GPIO_Pin_2 // PI.02 - #define AUDIO_SPI_MISO_GPIO_PinSource GPIO_PinSource2 - #define AUDIO_SPI_MOSI_GPIO GPIOI - #define AUDIO_SPI_MOSI_GPIO_PIN GPIO_Pin_3 // PI.03 - #define AUDIO_SPI_MOSI_GPIO_PinSource GPIO_PinSource3 -#elif defined (PCBX10) - #define AUDIO_RCC_APB1Periph (RCC_APB1Periph_TIM6 | RCC_APB1Periph_DAC) - #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1) - #define AUDIO_MUTE_GPIO GPIOA - #define AUDIO_MUTE_GPIO_PIN GPIO_Pin_7 // PA.07 - #define AUDIO_OUTPUT_GPIO GPIOA - #define AUDIO_OUTPUT_GPIO_PIN GPIO_Pin_4 // PA.04 - #define AUDIO_GPIO_AF GPIO_AF_DAC1 - #define AUDIO_GPIO_PinSource GPIO_PinSource4 - #define AUDIO_DMA_Stream DMA1_Stream5 - #define AUDIO_DMA_Stream_IRQn DMA1_Stream5_IRQn - #define AUDIO_TIM_IRQn TIM6_DAC_IRQn - #define AUDIO_TIM_IRQHandler TIM6_DAC_IRQHandler - #define AUDIO_DMA_Stream_IRQHandler DMA1_Stream5_IRQHandler - #define AUDIO_TIMER TIM6 - #define AUDIO_DMA DMA1 -#endif - -// I2C Bus -#define I2C_RCC_AHB1Periph RCC_AHB1Periph_GPIOB -#define I2C_RCC_APB1Periph RCC_APB1Periph_I2C1 -#define I2C I2C1 -#define I2C_GPIO GPIOB -#define I2C_SCL_GPIO_PIN GPIO_Pin_8 // PB.08 -#define I2C_SDA_GPIO_PIN GPIO_Pin_9 // PB.09 -#define I2C_GPIO_AF GPIO_AF_I2C1 -#define I2C_SCL_GPIO_PinSource GPIO_PinSource8 -#define I2C_SDA_GPIO_PinSource GPIO_PinSource9 -#define I2C_SPEED 400000 - -// Haptic -#if defined(PCBX12S) - #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOA - #define HAPTIC_RCC_APB2Periph RCC_APB2ENR_TIM9EN - #define HAPTIC_GPIO GPIOA - #define HAPTIC_GPIO_PIN GPIO_Pin_2 - #define HAPTIC_GPIO_TIMER TIM9 - #define HAPTIC_GPIO_AF GPIO_AF_TIM9 - #define HAPTIC_GPIO_PinSource GPIO_PinSource2 -#elif defined(PCBX10) - #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define HAPTIC_RCC_APB2Periph RCC_APB2ENR_TIM8EN - #define HAPTIC_GPIO GPIOB - #define HAPTIC_GPIO_PIN GPIO_Pin_0 // PB.00 - #define HAPTIC_GPIO_TIMER TIM8 - #define HAPTIC_GPIO_AF GPIO_AF_TIM8 - #define HAPTIC_GPIO_PinSource GPIO_PinSource0 -#endif - -// Internal Module -#define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) -#define INTMODULE_PWR_GPIO GPIOA -#define INTMODULE_PWR_GPIO_PIN GPIO_Pin_8 // PA.08 -#define INTMODULE_TX_GPIO GPIOB -#define INTMODULE_TX_GPIO_PIN GPIO_Pin_6 // PB.06 -#define INTMODULE_RX_GPIO GPIOB -#define INTMODULE_RX_GPIO_PIN GPIO_Pin_7 // PB.07 -#define INTMODULE_TX_GPIO_PinSource GPIO_PinSource6 -#define INTMODULE_RX_GPIO_PinSource GPIO_PinSource7 -#define INTMODULE_USART USART1 -#define INTMODULE_GPIO_AF GPIO_AF_USART1 -#define INTMODULE_USART_IRQn USART1_IRQn -#define INTMODULE_DMA_STREAM DMA2_Stream7 -#define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn -#define INTMODULE_DMA_STREAM_IRQHandler DMA2_Stream7_IRQHandler -#define INTMODULE_DMA_FLAG_TC DMA_IT_TCIF7 -#define INTMODULE_DMA_CHANNEL DMA_Channel_4 -#if PCBREV >= 13 - #define INTMODULE_RCC_APB1Periph RCC_APB1Periph_TIM2 - #define INTMODULE_RCC_APB2Periph RCC_APB2Periph_USART1 - #define INTMODULE_TIMER TIM2 - #define INTMODULE_TIMER_IRQn TIM2_IRQn - #define INTMODULE_TIMER_IRQHandler TIM2_IRQHandler - #define INTMODULE_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) -#else - #define INTMODULE_RCC_APB1Periph 0 - #define INTMODULE_RCC_APB2Periph (RCC_APB2Periph_TIM1 | RCC_APB2Periph_USART1) - #define INTMODULE_TIMER TIM1 - #define INTMODULE_TIMER_IRQn TIM1_CC_IRQn - #define INTMODULE_TIMER_IRQHandler TIM1_CC_IRQHandler - #define INTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) -#endif - -// External Module -#define EXTMODULE_PWR_GPIO GPIOB -#define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_3 // PB.03 -#if PCBREV >= 13 - #define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) - #define EXTMODULE_RCC_APB1Periph 0 - #define EXTMODULE_RCC_APB2Periph RCC_APB2Periph_TIM1 - #define EXTMODULE_PPM_GPIO GPIOA - #define EXTMODULE_PPM_GPIO_PIN GPIO_Pin_10 // PA.10 - #define EXTMODULE_PPM_GPIO_PinSource GPIO_PinSource10 - #define EXTMODULE_PPM_GPIO_AF GPIO_AF_TIM1 - #define EXTMODULE_TIMER TIM1 - #define EXTMODULE_TIMER_IRQn TIM1_CC_IRQn - #define EXTMODULE_TIMER_IRQHandler TIM1_CC_IRQHandler - #define EXTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) - #define EXTMODULE_DMA_CHANNEL DMA_Channel_6 - #define EXTMODULE_DMA_STREAM DMA2_Stream5 - #define EXTMODULE_DMA_IRQn DMA2_Stream5_IRQn - #define EXTMODULE_DMA_IRQHandler DMA2_Stream5_IRQHandler - #define EXTMODULE_DMA_FLAG_TC DMA_IT_TCIF5 -#else - #define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) - #define EXTMODULE_RCC_APB1Periph RCC_APB1Periph_TIM2 - #define EXTMODULE_RCC_APB2Periph 0 - #define EXTMODULE_PPM_GPIO GPIOA - #define EXTMODULE_PPM_GPIO_PIN GPIO_Pin_15 // PA.15 - #define EXTMODULE_PPM_GPIO_PinSource GPIO_PinSource15 - #define EXTMODULE_PPM_GPIO_AF GPIO_AF_TIM2 - #define EXTMODULE_TIMER TIM2 - #define EXTMODULE_TIMER_IRQn TIM2_IRQn - #define EXTMODULE_TIMER_IRQHandler TIM2_IRQHandler - #define EXTMODULE_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) - #define EXTMODULE_DMA_CHANNEL DMA_Channel_3 - #define EXTMODULE_DMA_STREAM DMA1_Stream7 - #define EXTMODULE_DMA_IRQn DMA1_Stream7_IRQn - #define EXTMODULE_DMA_IRQHandler DMA1_Stream7_IRQHandler - #define EXTMODULE_DMA_FLAG_TC DMA_IT_TCIF7 -#endif - -// Trainer Port -#define TRAINER_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_DMA1) -#define TRAINER_RCC_APB1Periph RCC_APB1Periph_TIM3 -#define TRAINER_GPIO GPIOC -#define TRAINER_IN_GPIO_PIN GPIO_Pin_6 // PC.06 -#define TRAINER_IN_GPIO_PinSource GPIO_PinSource6 -#define TRAINER_OUT_GPIO_PIN GPIO_Pin_7 // PC.07 -#define TRAINER_OUT_GPIO_PinSource GPIO_PinSource7 -#define TRAINER_DETECT_GPIO GPIOB -#define TRAINER_DETECT_GPIO_PIN GPIO_Pin_4 // PB.04 -#define TRAINER_TIMER TIM3 -#define TRAINER_TIMER_IRQn TIM3_IRQn -#define TRAINER_TIMER_IRQHandler TIM3_IRQHandler -#define TRAINER_GPIO_AF GPIO_AF_TIM3 -#define TRAINER_DMA DMA1 -#define TRAINER_DMA_CHANNEL DMA_Channel_5 -#define TRAINER_DMA_STREAM DMA1_Stream2 -#define TRAINER_DMA_IRQn DMA1_Stream2_IRQn -#define TRAINER_DMA_IRQHandler DMA1_Stream2_IRQHandler -#define TRAINER_DMA_FLAG_TC DMA_IT_TCIF2 -#define TRAINER_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) - -// 1ms Interrupt -#define INTERRUPT_1MS_RCC_APB1Periph RCC_APB1Periph_TIM14 -#define INTERRUPT_1MS_TIMER TIM14 -#define INTERRUPT_1MS_IRQn TIM8_TRG_COM_TIM14_IRQn -#define INTERRUPT_1MS_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler - -// 2MHz Timer -#define TIMER_2MHz_RCC_APB1Periph RCC_APB1Periph_TIM7 -#define TIMER_2MHz_TIMER TIM7 - -// Bluetooth -#if defined(PCBX12S) - #define BT_RCC_APB2Periph RCC_APB2Periph_USART6 - #define BT_USART USART6 - #define BT_GPIO_AF GPIO_AF_USART6 - #define BT_USART_IRQn USART6_IRQn - #define BT_GPIO_TXRX GPIOG - #define BT_TX_GPIO_PIN GPIO_Pin_14 // PG.14 - #define BT_RX_GPIO_PIN GPIO_Pin_9 // PG.09 - #if PCBREV >= 13 - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOG) - #define BT_EN_GPIO GPIOI - #define BT_EN_GPIO_PIN GPIO_Pin_10 // PI.10 - #else - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOG) - #define BT_EN_GPIO GPIOA - #define BT_EN_GPIO_PIN GPIO_Pin_6 // PA.06 - #endif - #define BT_BRTS_GPIO GPIOG - #define BT_BRTS_GPIO_PIN GPIO_Pin_10 // PG.10 - #define BT_BCTS_GPIO GPIOG - #define BT_BCTS_GPIO_PIN GPIO_Pin_11 // PG.11 - #define BT_TX_GPIO_PinSource GPIO_PinSource14 - #define BT_RX_GPIO_PinSource GPIO_PinSource9 -#endif - -// GPS -#define GPS_RCC_AHB1Periph RCC_AHB1Periph_GPIOA -#define GPS_RCC_APB1Periph RCC_APB1Periph_UART4 -#define GPS_USART UART4 -#define GPS_GPIO_AF GPIO_AF_UART4 -#define GPS_USART_IRQn UART4_IRQn -#define GPS_USART_IRQHandler UART4_IRQHandler -#define GPS_UART_GPIO GPIOA -#define GPS_TX_GPIO_PIN GPIO_Pin_0 // PA.00 -#define GPS_RX_GPIO_PIN GPIO_Pin_1 // PA.01 -#define GPS_TX_GPIO_PinSource GPIO_PinSource0 -#define GPS_RX_GPIO_PinSource GPIO_PinSource1 - -#endif // _HAL_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _HAL_H_ +#define _HAL_H_ + +// Keys +#define KEYS_RCC_AHB1Periph_GPIO (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOJ) +#if defined(PCBX12S) + #define KEYS_GPIO_REG_PGUP GPIOC->IDR + #define KEYS_GPIO_PIN_PGUP GPIO_Pin_13 // PC.13 + #define KEYS_GPIO_REG_PGDN GPIOI->IDR + #define KEYS_GPIO_PIN_PGDN GPIO_Pin_8 // PI.08 + #define KEYS_GPIO_REG_LEFT GPIOI->IDR + #define KEYS_GPIO_PIN_LEFT GPIO_Pin_7 // PI.07 + #define KEYS_GPIO_REG_ENTER GPIOC->IDR + #define KEYS_GPIO_PIN_ENTER GPIO_Pin_1 // PC.01 + #define KEYS_GPIO_REG_UP GPIOG->IDR + #define KEYS_GPIO_PIN_UP GPIO_Pin_13 // PG.13 + #define KEYS_GPIO_REG_DOWN GPIOI->IDR + #define KEYS_GPIO_PIN_DOWN GPIO_Pin_6 // PI.06 + #define KEYS_GPIO_REG_RIGHT GPIOC->IDR + #define KEYS_GPIO_PIN_RIGHT GPIO_Pin_4 // PC.04 +#elif defined(PCBX10) + #define KEYS_GPIO_REG_PGDN GPIOI->IDR + #define KEYS_GPIO_PIN_PGDN GPIO_Pin_11 // PI.11 + #define KEYS_GPIO_REG_LEFT GPIOI->IDR + #define KEYS_GPIO_PIN_LEFT GPIO_Pin_7 // PI.07 + #define KEYS_GPIO_REG_ENTER GPIOI->IDR + #define KEYS_GPIO_PIN_ENTER GPIO_Pin_8 // PI.08 + #define KEYS_GPIO_REG_UP GPIOI->IDR + #define KEYS_GPIO_PIN_UP GPIO_Pin_4 // PI.04 + #define KEYS_GPIO_REG_DOWN GPIOI->IDR + #define KEYS_GPIO_PIN_DOWN GPIO_Pin_6 // PI.06 + #define KEYS_GPIO_REG_RIGHT GPIOI->IDR + #define KEYS_GPIO_PIN_RIGHT GPIO_Pin_5 // PI.05 +#endif + +// Rotary Encoder +#define ROTARY_ENCODER_GPIO GPIOH +#define ROTARY_ENCODER_GPIO_PIN_A GPIO_Pin_11 // PH.11 +#define ROTARY_ENCODER_GPIO_PIN_B GPIO_Pin_10 // PH.10 +#define ROTARY_ENCODER_POSITION() ((ROTARY_ENCODER_GPIO->IDR >> 10) & 0x03) + +// Switches +#define SWITCHES_GPIO_REG_A_H GPIOH->IDR +#define SWITCHES_GPIO_PIN_A_H GPIO_Pin_9 // PH.09 +#define SWITCHES_GPIO_REG_A_L GPIOI->IDR +#define SWITCHES_GPIO_PIN_A_L GPIO_Pin_15 // PI.15 +#define SWITCHES_GPIO_REG_B_H GPIOH->IDR +#define SWITCHES_GPIO_PIN_B_H GPIO_Pin_12 // PH.12 +#define SWITCHES_GPIO_REG_B_L GPIOB->IDR +#define SWITCHES_GPIO_PIN_B_L GPIO_Pin_12 // PB.12 +#define SWITCHES_GPIO_REG_C_H GPIOD->IDR +#define SWITCHES_GPIO_PIN_C_H GPIO_Pin_11 // PD.11 +#define SWITCHES_GPIO_REG_C_L GPIOB->IDR +#define SWITCHES_GPIO_PIN_C_L GPIO_Pin_15 // PB.15 +#define SWITCHES_GPIO_REG_D_H GPIOJ->IDR +#define SWITCHES_GPIO_PIN_D_H GPIO_Pin_7 // PJ.07 +#define SWITCHES_GPIO_REG_D_L GPIOG->IDR +#define SWITCHES_GPIO_PIN_D_L GPIO_Pin_2 // PG.02 +#define SWITCHES_GPIO_REG_E_H GPIOH->IDR +#define SWITCHES_GPIO_PIN_E_H GPIO_Pin_4 // PH.04 +#define SWITCHES_GPIO_REG_E_L GPIOE->IDR +#define SWITCHES_GPIO_PIN_E_L GPIO_Pin_3 // PE.03 +#define SWITCHES_GPIO_REG_F GPIOH->IDR +#define SWITCHES_GPIO_PIN_F GPIO_Pin_3 // PH.03 +#define SWITCHES_GPIO_REG_G_H GPIOG->IDR +#define SWITCHES_GPIO_PIN_G_H GPIO_Pin_6 // PG.06 +#define SWITCHES_GPIO_REG_G_L GPIOG->IDR +#define SWITCHES_GPIO_PIN_G_L GPIO_Pin_3 // PG.03 +#define SWITCHES_GPIO_REG_H GPIOG->IDR +#define SWITCHES_GPIO_PIN_H GPIO_Pin_7 // PG.07 + +#if defined(PCBX10) + #define SWITCHES_GPIO_REG_GMBL GPIOH->IDR + #define SWITCHES_GPIO_PIN_GMBL GPIO_Pin_14 + #define SWITCHES_GPIO_REG_GMBR GPIOH->IDR + #define SWITCHES_GPIO_PIN_GMBR GPIO_Pin_15 +#endif + +// Trims +#if defined(PCBX12S) + #define TRIMS_GPIO_REG_RHL GPIOC->IDR + #define TRIMS_GPIO_PIN_RHL GPIO_Pin_0 // PC.00 + #define TRIMS_GPIO_REG_RHR GPIOI->IDR + #define TRIMS_GPIO_PIN_RHR GPIO_Pin_4 // PI.04 + #define TRIMS_GPIO_REG_RVD GPIOG->IDR + #define TRIMS_GPIO_PIN_RVD GPIO_Pin_12 // PG.12 + #define TRIMS_GPIO_REG_RVU GPIOJ->IDR + #define TRIMS_GPIO_PIN_RVU GPIO_Pin_14 // PJ.14 + #define TRIMS_GPIO_REG_LVD GPIOJ->IDR + #define TRIMS_GPIO_PIN_LVD GPIO_Pin_13 // PJ.13 + #define TRIMS_GPIO_REG_LHL GPIOD->IDR + #define TRIMS_GPIO_PIN_LHL GPIO_Pin_3 // PD.03 + #define TRIMS_GPIO_REG_LVU GPIOJ->IDR + #define TRIMS_GPIO_PIN_LVU GPIO_Pin_12 // PJ.12 + #define TRIMS_GPIO_REG_LHR GPIOD->IDR + #define TRIMS_GPIO_PIN_LHR GPIO_Pin_7 // PD.07 + #define TRIMS_GPIO_REG_RSD GPIOJ->IDR + #define TRIMS_GPIO_PIN_RSD GPIO_Pin_8 // PJ.08 + #define TRIMS_GPIO_REG_RSU GPIOD->IDR + #define TRIMS_GPIO_PIN_RSU GPIO_Pin_13 // PD.13 + #define TRIMS_GPIO_REG_LSD GPIOB->IDR + #define TRIMS_GPIO_PIN_LSD GPIO_Pin_14 // PB.14 + #define TRIMS_GPIO_REG_LSU GPIOB->IDR + #define TRIMS_GPIO_PIN_LSU GPIO_Pin_13 // PB.13 +#elif defined(PCBX10) + #define TRIMS_GPIO_REG_LHL GPIOB->IDR + #define TRIMS_GPIO_PIN_LHL GPIO_Pin_8 // PB.08 + #define TRIMS_GPIO_REG_LHR GPIOB->IDR + #define TRIMS_GPIO_PIN_LHR GPIO_Pin_9 // PB.09 + #define TRIMS_GPIO_REG_LVD GPIOG->IDR + #define TRIMS_GPIO_PIN_LVD GPIO_Pin_12 // PG.12 + #define TRIMS_GPIO_REG_LVU GPIOJ->IDR + #define TRIMS_GPIO_PIN_LVU GPIO_Pin_14 // PJ.14 + #define TRIMS_GPIO_REG_RVD GPIOJ->IDR + #define TRIMS_GPIO_PIN_RVD GPIO_Pin_13 // PJ.13 + #define TRIMS_GPIO_REG_RHL GPIOD->IDR + #define TRIMS_GPIO_PIN_RHL GPIO_Pin_3 // PD.03 + #define TRIMS_GPIO_REG_RVU GPIOJ->IDR + #define TRIMS_GPIO_PIN_RVU GPIO_Pin_12 // PJ.12 + #define TRIMS_GPIO_REG_RHR GPIOD->IDR + #define TRIMS_GPIO_PIN_RHR GPIO_Pin_7 // PD.07 + #define TRIMS_GPIO_REG_LSU GPIOJ->IDR + #define TRIMS_GPIO_PIN_LSU GPIO_Pin_8 // PJ.08 + #define TRIMS_GPIO_REG_LSD GPIOD->IDR + #define TRIMS_GPIO_PIN_LSD GPIO_Pin_13 // PD.13 + #define TRIMS_GPIO_REG_RSU GPIOB->IDR + #define TRIMS_GPIO_PIN_RSU GPIO_Pin_14 // PB.14 + #define TRIMS_GPIO_REG_RSD GPIOB->IDR + #define TRIMS_GPIO_PIN_RSD GPIO_Pin_13 // PB.13 +#endif + +// Index of all keys +#if defined(PCBX12S) + #define KEYS_GPIOB_PINS (SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_C_L | TRIMS_GPIO_PIN_LSD | TRIMS_GPIO_PIN_LSU) + #define KEYS_GPIOC_PINS (KEYS_GPIO_PIN_PGUP | KEYS_GPIO_PIN_ENTER | KEYS_GPIO_PIN_RIGHT | TRIMS_GPIO_PIN_RHL) + #define KEYS_GPIOD_PINS (SWITCHES_GPIO_PIN_C_H | TRIMS_GPIO_PIN_LHL | TRIMS_GPIO_PIN_LHR | TRIMS_GPIO_PIN_RSU) + #define KEYS_GPIOE_PINS (SWITCHES_GPIO_PIN_E_L) + #define KEYS_GPIOG_PINS (KEYS_GPIO_PIN_UP | SWITCHES_GPIO_PIN_D_L | SWITCHES_GPIO_PIN_G_H | SWITCHES_GPIO_PIN_G_L | SWITCHES_GPIO_PIN_H | TRIMS_GPIO_PIN_RVD) + #define KEYS_GPIOH_PINS (SWITCHES_GPIO_PIN_A_H | SWITCHES_GPIO_PIN_B_H | SWITCHES_GPIO_PIN_E_H | SWITCHES_GPIO_PIN_F | ROTARY_ENCODER_GPIO_PIN_A | ROTARY_ENCODER_GPIO_PIN_B) + #define KEYS_GPIOI_PINS (KEYS_GPIO_PIN_PGDN | KEYS_GPIO_PIN_LEFT | KEYS_GPIO_PIN_DOWN | SWITCHES_GPIO_PIN_A_L | TRIMS_GPIO_PIN_RHR) + #define KEYS_GPIOJ_PINS (SWITCHES_GPIO_PIN_D_H | TRIMS_GPIO_PIN_RVU | TRIMS_GPIO_PIN_LVD | TRIMS_GPIO_PIN_LVU | TRIMS_GPIO_PIN_RSD) +#elif defined(PCBX10) + #define KEYS_GPIOB_PINS (SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_C_L | TRIMS_GPIO_PIN_RSU | TRIMS_GPIO_PIN_RSD | TRIMS_GPIO_PIN_LHL | TRIMS_GPIO_PIN_LHR) + #define KEYS_GPIOC_PINS (TRIMS_GPIO_PIN_LHL) + #define KEYS_GPIOD_PINS (SWITCHES_GPIO_PIN_C_H | TRIMS_GPIO_PIN_RHL | TRIMS_GPIO_PIN_RHR | TRIMS_GPIO_PIN_LSD) + #define KEYS_GPIOE_PINS (SWITCHES_GPIO_PIN_E_L) + #define KEYS_GPIOG_PINS (SWITCHES_GPIO_PIN_D_L | SWITCHES_GPIO_PIN_G_H | SWITCHES_GPIO_PIN_G_L | SWITCHES_GPIO_PIN_H | TRIMS_GPIO_PIN_LVD) + #define KEYS_GPIOH_PINS (SWITCHES_GPIO_PIN_A_H | SWITCHES_GPIO_PIN_B_H | SWITCHES_GPIO_PIN_E_H | SWITCHES_GPIO_PIN_F | ROTARY_ENCODER_GPIO_PIN_A | ROTARY_ENCODER_GPIO_PIN_B | SWITCHES_GPIO_PIN_GMBR | SWITCHES_GPIO_PIN_GMBL) + #define KEYS_GPIOI_PINS (KEYS_GPIO_PIN_RIGHT | KEYS_GPIO_PIN_UP | KEYS_GPIO_PIN_ENTER | KEYS_GPIO_PIN_PGDN | KEYS_GPIO_PIN_LEFT | KEYS_GPIO_PIN_DOWN | SWITCHES_GPIO_PIN_A_L) + #define KEYS_GPIOJ_PINS (SWITCHES_GPIO_PIN_D_H | TRIMS_GPIO_PIN_LVU | TRIMS_GPIO_PIN_RVD | TRIMS_GPIO_PIN_RVU | TRIMS_GPIO_PIN_LSU) +#endif + +// ADC +#if defined(PCBX12S) + #define ADC_RCC_AHB1Periph (RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_DMA2) + #define ADC_RCC_APB2Periph (RCC_APB2Periph_SPI4 | RCC_APB2Periph_ADC3) + #define ADC_SPI SPI4 + #define ADC_GPIO_AF GPIO_AF_SPI4 + #define ADC_SPI_GPIO GPIOE + #define ADC_SPI_PIN_SCK GPIO_Pin_2 // PE.02 + #define ADC_SPI_PIN_CS GPIO_Pin_4 // PE.04 + #define ADC_SPI_PIN_MOSI GPIO_Pin_6 // PE.06 + #define ADC_SPI_PIN_MISO GPIO_Pin_5 // PE.05 + #define ADC_SPI_PinSource_SCK GPIO_PinSource2 + #define ADC_SPI_PinSource_MISO GPIO_PinSource5 + #define ADC_SPI_PinSource_MOSI GPIO_PinSource6 + #define ADC_GPIO_PIN_MOUSE1 GPIO_Pin_8 // PF.08 ADC3_IN6 J5 MOUSE_X + #define ADC_GPIO_PIN_MOUSE2 GPIO_Pin_9 // PF.09 ADC3_IN7 J6 MOUSE_Y + #define ADC_GPIO_MOUSE GPIOF + #define ADC_IN_MOUSE1 6 + #define ADC_IN_MOUSE2 7 + #define ADC_DMA DMA2 + #define ADC_DMA_Stream DMA2_Stream0 + #define ADC_SAMPTIME 3 +#elif defined(PCBX10) + #define ADC_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_DMA2) + #define ADC_RCC_APB2Periph (RCC_APB2Periph_ADC3) + #define ADC_GPIO_PIN_STICK_LH GPIO_Pin_0 // PC.00 + #define ADC_GPIO_PIN_STICK_LV GPIO_Pin_1 // PC.01 + #define ADC_GPIO_PIN_STICK_RH GPIO_Pin_2 // PC.02 + #define ADC_GPIO_PIN_STICK_RV GPIO_Pin_3 // PC.03 + #define ADC_GPIO_PIN_SLIDER1 GPIO_Pin_6 // PF.06 + #define ADC_GPIO_PIN_SLIDER2 GPIO_Pin_3 // PA.03 + #define ADC_GPIO_PIN_BATT GPIO_Pin_7 // PF.07 + #define ADC_GPIO_PIN_POT3 GPIO_Pin_0 // PA.00 + #define ADC_GPIO_PIN_POT1 GPIO_Pin_2 // PA.02 + #define ADC_GPIO_PIN_POT2 GPIO_Pin_1 // PA.01 + #define ADC_GPIO_PIN_EXT1 GPIO_Pin_8 // PF.08 + #define ADC_GPIO_PIN_EXT2 GPIO_Pin_9 // PF.09 + #define ADC_GPIOA_PINS (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3) + #define ADC_GPIOC_PINS (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3) + #define ADC_GPIOF_PINS (GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9) + #define ADC_CHANNEL_STICK_LH ADC_Channel_10 // ADC1_IN10 + #define ADC_CHANNEL_STICK_LV ADC_Channel_11 // ADC1_IN11 + #define ADC_CHANNEL_STICK_RH ADC_Channel_12 // ADC1_IN12 + #define ADC_CHANNEL_STICK_RV ADC_Channel_13 // ADC1_IN13 + #define ADC_CHANNEL_SLIDER1 ADC_Channel_4 // ADC1_IN4 + #define ADC_CHANNEL_SLIDER2 ADC_Channel_3 // ADC1_IN3 + #define ADC_CHANNEL_BATT ADC_Channel_5 // ADC1_IN5 + #define ADC_CHANNEL_POT3 ADC_Channel_0 // ADC1_IN0 + #define ADC_CHANNEL_POT1 ADC_Channel_2 // ADC1_IN2 + #define ADC_CHANNEL_POT2 ADC_Channel_1 // ADC1_IN1 + #define ADC_CHANNEL_EXT1 ADC_Channel_6 // ADC1_IN6 + #define ADC_CHANNEL_EXT2 ADC_Channel_7 // ADC1_IN7 + #define ADC_MAIN ADC3 + #define ADC_SAMPTIME 3 + #define ADC_DMA DMA2 + #define ADC_DMA_SxCR_CHSEL DMA_SxCR_CHSEL_1 + #define ADC_DMA_Stream DMA2_Stream0 + #define ADC_SET_DMA_FLAGS() ADC_DMA->LIFCR = (DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 | DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0) + #define ADC_TRANSFER_COMPLETE() (ADC_DMA->LISR & DMA_LISR_TCIF0) +#endif + +// Power +#define PWR_RCC_AHB1Periph RCC_AHB1Periph_GPIOJ +#define PWR_GPIO GPIOJ +#define PWR_ON_GPIO_PIN GPIO_Pin_1 // PJ.01 +#define PWR_SWITCH_GPIO_PIN GPIO_Pin_0 // PJ.00 + +#if defined(PCBX10) + #define SPORT_PWR_RCC_AHB1Periph RCC_AHB1Periph_GPIOH + #define SPORT_PWR_GPIO GPIOH + #define SPORT_PWR_GPIO_PIN GPIO_Pin_13 // PH.13 +#endif + +// PCBREV +#define PCBREV_RCC_AHB1Periph RCC_AHB1Periph_GPIOI +#define PCBREV_GPIO GPIOI +#define PCBREV_GPIO_PIN GPIO_Pin_11 // PI.11 + +// Led +#if defined(PCBX12S) + #define LED_RCC_AHB1Periph RCC_AHB1Periph_GPIOI + #define LED_GPIO GPIOI + #define LED_GPIO_PIN GPIO_Pin_5 // PI.05 +#elif defined(PCBX10) + #define LED_RCC_AHB1Periph RCC_AHB1Periph_GPIOE + #define LED_GPIO GPIOE + #define LED_RED_GPIO_PIN GPIO_Pin_5 + #define LED_GREEN_GPIO_PIN GPIO_Pin_4 + #define LED_BLUE_GPIO_PIN GPIO_Pin_6 + #define LED_GPIO_PIN (LED_RED_GPIO_PIN | LED_GREEN_GPIO_PIN | LED_BLUE_GPIO_PIN) +#endif + +// Serial Port (DEBUG) +#define SERIAL_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) +#define SERIAL_RCC_APB1Periph RCC_APB1Periph_USART3 +#define SERIAL_GPIO GPIOB +#define SERIAL_GPIO_PIN_TX GPIO_Pin_10 // PB.10 +#define SERIAL_GPIO_PIN_RX GPIO_Pin_11 // PB.11 +#define SERIAL_GPIO_PinSource_TX GPIO_PinSource10 +#define SERIAL_GPIO_PinSource_RX GPIO_PinSource11 +#define SERIAL_GPIO_AF GPIO_AF_USART3 +#define SERIAL_USART USART3 +#define SERIAL_USART_IRQHandler USART3_IRQHandler +#define SERIAL_USART_IRQn USART3_IRQn +#define SERIAL_DMA_Stream_RX DMA1_Stream1 +#define SERIAL_DMA_Channel_RX DMA_Channel_4 + +// Telemetry +#define TELEMETRY_RCC_AHB1Periph (RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) +#define TELEMETRY_RCC_APB1Periph RCC_APB1Periph_USART2 +#define TELEMETRY_DIR_GPIO GPIOD +#define TELEMETRY_DIR_GPIO_PIN GPIO_Pin_4 // PD.04 +#define TELEMETRY_GPIO GPIOD +#define TELEMETRY_TX_GPIO_PIN GPIO_Pin_5 // PD.05 +#define TELEMETRY_RX_GPIO_PIN GPIO_Pin_6 // PD.06 +#define TELEMETRY_GPIO_PinSource_TX GPIO_PinSource5 +#define TELEMETRY_GPIO_PinSource_RX GPIO_PinSource6 +#define TELEMETRY_GPIO_AF GPIO_AF_USART2 +#define TELEMETRY_USART USART2 +#if defined(PCBX12S) +#define TELEMETRY_DMA_Stream_RX DMA1_Stream5 +#define TELEMETRY_DMA_Channel_RX DMA_Channel_4 +#endif +#define TELEMETRY_DMA_Stream_TX DMA1_Stream6 +#define TELEMETRY_DMA_Channel_TX DMA_Channel_4 +#define TELEMETRY_DMA_TX_Stream_IRQ DMA1_Stream6_IRQn +#define TELEMETRY_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler +#define TELEMETRY_DMA_TX_FLAG_TC DMA_IT_TCIF6 +#define TELEMETRY_USART_IRQHandler USART2_IRQHandler +#define TELEMETRY_USART_IRQn USART2_IRQn + +// USB +#define USB_RCC_AHB1Periph_GPIO RCC_AHB1Periph_GPIOA +#define USB_GPIO GPIOA +#define USB_GPIO_PIN_VBUS GPIO_Pin_9 // PA.09 +#define USB_GPIO_PIN_DM GPIO_Pin_11 // PA.11 +#define USB_GPIO_PIN_DP GPIO_Pin_12 // PA.12 +#define USB_GPIO_PinSource_DM GPIO_PinSource11 +#define USB_GPIO_PinSource_DP GPIO_PinSource12 +#define USB_GPIO_AF GPIO_AF_OTG1_FS + +// LCD +#define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOJ | RCC_AHB1Periph_GPIOK | RCC_AHB1Periph_DMA2D) +#define LCD_RCC_APB2Periph RCC_APB2Periph_LTDC +#if defined(PCBX12S) + #define LCD_GPIO_NRST GPIOF + #define LCD_GPIO_PIN_NRST GPIO_Pin_10 // PF.10 +#elif defined(PCBX10) + #define LCD_GPIO_NRST GPIOI + #define LCD_GPIO_PIN_NRST GPIO_Pin_10 // PI.10 +#endif +#define LTDC_IRQ_PRIO 4 +#define DMA_SCREEN_IRQ_PRIO 6 + +// Backlight +#if defined(PCBX12S) + #define BL_RCC_AHB1Periph RCC_AHB1Periph_GPIOA + #define BL_GPIO GPIOA + #if PCBREV >= 13 + #define BL_TIMER TIM5 + #define BL_GPIO_PIN GPIO_Pin_3 // PA.03 + #define BL_GPIO_PinSource GPIO_PinSource3 + #define BL_RCC_APB1Periph RCC_APB1Periph_TIM5 + #define BL_RCC_APB2Periph 0 + #define BL_GPIO_AF GPIO_AF_TIM5 + #define BL_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) + #else + #define BL_TIMER TIM8 + #define BL_GPIO_PIN GPIO_Pin_5 // PA.05 + #define BL_GPIO_PinSource GPIO_PinSource5 + #define BL_RCC_APB1Periph 0 + #define BL_RCC_APB2Periph RCC_APB2Periph_TIM8 + #define BL_GPIO_AF GPIO_AF_TIM8 + #define BL_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) + #endif +#elif defined(PCBX10) + #define BL_RCC_AHB1Periph RCC_AHB1Periph_GPIOB + #define BL_GPIO GPIOB + #define BL_TIMER TIM8 + #define BL_GPIO_PIN GPIO_Pin_1 // PB.01 + #define BL_GPIO_PinSource GPIO_PinSource1 + #define BL_RCC_APB1Periph 0 + #define BL_RCC_APB2Periph RCC_APB2Periph_TIM8 + #define BL_GPIO_AF GPIO_AF_TIM8 + #define BL_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) +#endif + +// SD +#define SD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) +#define SD_PRESENT_GPIO GPIOC +#define SD_PRESENT_GPIO_PIN GPIO_Pin_5 // PC.05 +#define SD_SDIO_DMA_STREAM DMA2_Stream3 +#define SD_SDIO_DMA_CHANNEL DMA_Channel_4 +#define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF3 +#define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF3 +#define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF3 +#define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF3 +#define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF3 +#define SD_SDIO_DMA_IRQn DMA2_Stream3_IRQn +#define SD_SDIO_DMA_IRQHANDLER DMA2_Stream3_IRQHandler +#define SD_SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80) +#define SD_SDIO_CLK_DIV(fq) ((48000000 / (fq)) - 2) +#define SD_SDIO_INIT_CLK_DIV SD_SDIO_CLK_DIV(400000) +#define SD_SDIO_TRANSFER_CLK_DIV SD_SDIO_CLK_DIV(24000000) + +// EEPROM +#if defined(PCBX12S) && PCBREV >= 13 + #define EEPROM_RCC_AHB1Periph RCC_AHB1Periph_GPIOA + #define EEPROM_RCC_APB1Periph RCC_APB1Periph_SPI1 + #define EEPROM_SPI_CS_GPIO GPIOA + #define EEPROM_SPI_CS_GPIO_PIN GPIO_Pin_15 // PA.15 + #define EEPROM_SPI_SCK_GPIO GPIOA + #define EEPROM_SPI_SCK_GPIO_PIN GPIO_Pin_5 // PA.05 + #define EEPROM_SPI_SCK_GPIO_PinSource GPIO_PinSource5 + #define EEPROM_SPI_MISO_GPIO GPIOA + #define EEPROM_SPI_MISO_GPIO_PIN GPIO_Pin_6 // PA.06 + #define EEPROM_SPI_MISO_GPIO_PinSource GPIO_PinSource6 + #define EEPROM_SPI_MOSI_GPIO GPIOA + #define EEPROM_SPI_MOSI_GPIO_PIN GPIO_Pin_7 // PA.07 + #define EEPROM_SPI_MOSI_GPIO_PinSource GPIO_PinSource7 +#elif defined(PCBX10) + #define EEPROM_RCC_AHB1Periph RCC_AHB1Periph_GPIOI + #define EEPROM_RCC_APB1Periph RCC_APB1Periph_SPI2 + #define EEPROM_SPI_CS_GPIO GPIOI + #define EEPROM_SPI_CS_GPIO_PIN GPIO_Pin_0 // PI.00 + #define EEPROM_SPI_SCK_GPIO GPIOI + #define EEPROM_SPI_SCK_GPIO_PIN GPIO_Pin_1 // PI.01 + #define EEPROM_SPI_SCK_GPIO_PinSource GPIO_PinSource1 + #define EEPROM_SPI_MISO_GPIO GPIOI + #define EEPROM_SPI_MISO_GPIO_PIN GPIO_Pin_2 // PI.02 + #define EEPROM_SPI_MISO_GPIO_PinSource GPIO_PinSource2 + #define EEPROM_SPI_MOSI_GPIO GPIOI + #define EEPROM_SPI_MOSI_GPIO_PIN GPIO_Pin_3 // PI.03 + #define EEPROM_SPI_MOSI_GPIO_PinSource GPIO_PinSource3 +#endif + +// Audio +#if defined(PCBX12S) + #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOH) + #define AUDIO_RCC_APB1Periph RCC_APB1Periph_SPI2 + #define AUDIO_SHUTDOWN_GPIO GPIOI + #define AUDIO_SHUTDOWN_GPIO_PIN GPIO_Pin_9 // PI.09 + #define AUDIO_XDCS_GPIO GPIOI + #define AUDIO_XDCS_GPIO_PIN GPIO_Pin_0 // PI.00 + #define AUDIO_CS_GPIO GPIOH + #define AUDIO_CS_GPIO_PIN GPIO_Pin_13 // PH.13 + #define AUDIO_DREQ_GPIO GPIOH + #define AUDIO_DREQ_GPIO_PIN GPIO_Pin_14 // PH.14 + #define AUDIO_RST_GPIO GPIOH + #define AUDIO_RST_GPIO_PIN GPIO_Pin_15 // PH.15 + #define AUDIO_SPI SPI2 + #define AUDIO_SPI_GPIO_AF GPIO_AF_SPI2 + #define AUDIO_SPI_SCK_GPIO GPIOI + #define AUDIO_SPI_SCK_GPIO_PIN GPIO_Pin_1 // PI.01 + #define AUDIO_SPI_SCK_GPIO_PinSource GPIO_PinSource1 + #define AUDIO_SPI_MISO_GPIO GPIOI + #define AUDIO_SPI_MISO_GPIO_PIN GPIO_Pin_2 // PI.02 + #define AUDIO_SPI_MISO_GPIO_PinSource GPIO_PinSource2 + #define AUDIO_SPI_MOSI_GPIO GPIOI + #define AUDIO_SPI_MOSI_GPIO_PIN GPIO_Pin_3 // PI.03 + #define AUDIO_SPI_MOSI_GPIO_PinSource GPIO_PinSource3 +#elif defined (PCBX10) + #define AUDIO_RCC_APB1Periph (RCC_APB1Periph_TIM6 | RCC_APB1Periph_DAC) + #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1) + #define AUDIO_MUTE_GPIO GPIOA + #define AUDIO_MUTE_GPIO_PIN GPIO_Pin_7 // PA.07 + #define AUDIO_OUTPUT_GPIO GPIOA + #define AUDIO_OUTPUT_GPIO_PIN GPIO_Pin_4 // PA.04 + #define AUDIO_GPIO_AF GPIO_AF_DAC1 + #define AUDIO_GPIO_PinSource GPIO_PinSource4 + #define AUDIO_DMA_Stream DMA1_Stream5 + #define AUDIO_DMA_Stream_IRQn DMA1_Stream5_IRQn + #define AUDIO_TIM_IRQn TIM6_DAC_IRQn + #define AUDIO_TIM_IRQHandler TIM6_DAC_IRQHandler + #define AUDIO_DMA_Stream_IRQHandler DMA1_Stream5_IRQHandler + #define AUDIO_TIMER TIM6 + #define AUDIO_DMA DMA1 +#endif + +// I2C Bus +#define I2C_RCC_AHB1Periph RCC_AHB1Periph_GPIOB +#define I2C_RCC_APB1Periph RCC_APB1Periph_I2C1 +#define I2C I2C1 +#define I2C_GPIO GPIOB +#define I2C_SCL_GPIO_PIN GPIO_Pin_8 // PB.08 +#define I2C_SDA_GPIO_PIN GPIO_Pin_9 // PB.09 +#define I2C_GPIO_AF GPIO_AF_I2C1 +#define I2C_SCL_GPIO_PinSource GPIO_PinSource8 +#define I2C_SDA_GPIO_PinSource GPIO_PinSource9 +#define I2C_SPEED 400000 + +// Haptic +#if defined(PCBX12S) + #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOA + #define HAPTIC_RCC_APB2Periph RCC_APB2ENR_TIM9EN + #define HAPTIC_GPIO GPIOA + #define HAPTIC_GPIO_PIN GPIO_Pin_2 + #define HAPTIC_GPIO_TIMER TIM9 + #define HAPTIC_GPIO_AF GPIO_AF_TIM9 + #define HAPTIC_GPIO_PinSource GPIO_PinSource2 +#elif defined(PCBX10) + #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOB + #define HAPTIC_RCC_APB2Periph RCC_APB2ENR_TIM8EN + #define HAPTIC_GPIO GPIOB + #define HAPTIC_GPIO_PIN GPIO_Pin_0 // PB.00 + #define HAPTIC_GPIO_TIMER TIM8 + #define HAPTIC_GPIO_AF GPIO_AF_TIM8 + #define HAPTIC_GPIO_PinSource GPIO_PinSource0 +#endif + +// Internal Module +#define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) +#define INTMODULE_PWR_GPIO GPIOA +#define INTMODULE_PWR_GPIO_PIN GPIO_Pin_8 // PA.08 +#define INTMODULE_TX_GPIO GPIOB +#define INTMODULE_TX_GPIO_PIN GPIO_Pin_6 // PB.06 +#define INTMODULE_RX_GPIO GPIOB +#define INTMODULE_RX_GPIO_PIN GPIO_Pin_7 // PB.07 +#define INTMODULE_TX_GPIO_PinSource GPIO_PinSource6 +#define INTMODULE_RX_GPIO_PinSource GPIO_PinSource7 +#define INTMODULE_USART USART1 +#define INTMODULE_GPIO_AF GPIO_AF_USART1 +#define INTMODULE_USART_IRQn USART1_IRQn +#define INTMODULE_DMA_STREAM DMA2_Stream7 +#define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn +#define INTMODULE_DMA_STREAM_IRQHandler DMA2_Stream7_IRQHandler +#define INTMODULE_DMA_FLAG_TC DMA_IT_TCIF7 +#define INTMODULE_DMA_CHANNEL DMA_Channel_4 +#if PCBREV >= 13 + #define INTMODULE_RCC_APB1Periph RCC_APB1Periph_TIM2 + #define INTMODULE_RCC_APB2Periph RCC_APB2Periph_USART1 + #define INTMODULE_TIMER TIM2 + #define INTMODULE_TIMER_IRQn TIM2_IRQn + #define INTMODULE_TIMER_IRQHandler TIM2_IRQHandler + #define INTMODULE_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) +#else + #define INTMODULE_RCC_APB1Periph 0 + #define INTMODULE_RCC_APB2Periph (RCC_APB2Periph_TIM1 | RCC_APB2Periph_USART1) + #define INTMODULE_TIMER TIM1 + #define INTMODULE_TIMER_IRQn TIM1_CC_IRQn + #define INTMODULE_TIMER_IRQHandler TIM1_CC_IRQHandler + #define INTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) +#endif + +// External Module +#define EXTMODULE_PWR_GPIO GPIOB +#define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_3 // PB.03 +#if PCBREV >= 13 + #define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) + #define EXTMODULE_RCC_APB1Periph 0 + #define EXTMODULE_RCC_APB2Periph RCC_APB2Periph_TIM1 + #define EXTMODULE_PPM_GPIO GPIOA + #define EXTMODULE_PPM_GPIO_PIN GPIO_Pin_10 // PA.10 + #define EXTMODULE_PPM_GPIO_PinSource GPIO_PinSource10 + #define EXTMODULE_PPM_GPIO_AF GPIO_AF_TIM1 + #define EXTMODULE_TIMER TIM1 + #define EXTMODULE_TIMER_IRQn TIM1_CC_IRQn + #define EXTMODULE_TIMER_IRQHandler TIM1_CC_IRQHandler + #define EXTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) + #define EXTMODULE_DMA_CHANNEL DMA_Channel_6 + #define EXTMODULE_DMA_STREAM DMA2_Stream5 + #define EXTMODULE_DMA_IRQn DMA2_Stream5_IRQn + #define EXTMODULE_DMA_IRQHandler DMA2_Stream5_IRQHandler + #define EXTMODULE_DMA_FLAG_TC DMA_IT_TCIF5 +#else + #define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) + #define EXTMODULE_RCC_APB1Periph RCC_APB1Periph_TIM2 + #define EXTMODULE_RCC_APB2Periph 0 + #define EXTMODULE_PPM_GPIO GPIOA + #define EXTMODULE_PPM_GPIO_PIN GPIO_Pin_15 // PA.15 + #define EXTMODULE_PPM_GPIO_PinSource GPIO_PinSource15 + #define EXTMODULE_PPM_GPIO_AF GPIO_AF_TIM2 + #define EXTMODULE_TIMER TIM2 + #define EXTMODULE_TIMER_IRQn TIM2_IRQn + #define EXTMODULE_TIMER_IRQHandler TIM2_IRQHandler + #define EXTMODULE_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) + #define EXTMODULE_DMA_CHANNEL DMA_Channel_3 + #define EXTMODULE_DMA_STREAM DMA1_Stream7 + #define EXTMODULE_DMA_IRQn DMA1_Stream7_IRQn + #define EXTMODULE_DMA_IRQHandler DMA1_Stream7_IRQHandler + #define EXTMODULE_DMA_FLAG_TC DMA_IT_TCIF7 +#endif + +// Trainer Port +#define TRAINER_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_DMA1) +#define TRAINER_RCC_APB1Periph RCC_APB1Periph_TIM3 +#define TRAINER_GPIO GPIOC +#define TRAINER_IN_GPIO_PIN GPIO_Pin_6 // PC.06 +#define TRAINER_IN_GPIO_PinSource GPIO_PinSource6 +#define TRAINER_OUT_GPIO_PIN GPIO_Pin_7 // PC.07 +#define TRAINER_OUT_GPIO_PinSource GPIO_PinSource7 +#define TRAINER_DETECT_GPIO GPIOB +#define TRAINER_DETECT_GPIO_PIN GPIO_Pin_4 // PB.04 +#define TRAINER_TIMER TIM3 +#define TRAINER_TIMER_IRQn TIM3_IRQn +#define TRAINER_TIMER_IRQHandler TIM3_IRQHandler +#define TRAINER_GPIO_AF GPIO_AF_TIM3 +#define TRAINER_DMA DMA1 +#define TRAINER_DMA_CHANNEL DMA_Channel_5 +#define TRAINER_DMA_STREAM DMA1_Stream2 +#define TRAINER_DMA_IRQn DMA1_Stream2_IRQn +#define TRAINER_DMA_IRQHandler DMA1_Stream2_IRQHandler +#define TRAINER_DMA_FLAG_TC DMA_IT_TCIF2 +#define TRAINER_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) + +// 1ms Interrupt +#define INTERRUPT_1MS_RCC_APB1Periph RCC_APB1Periph_TIM14 +#define INTERRUPT_1MS_TIMER TIM14 +#define INTERRUPT_1MS_IRQn TIM8_TRG_COM_TIM14_IRQn +#define INTERRUPT_1MS_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler + +// 2MHz Timer +#define TIMER_2MHz_RCC_APB1Periph RCC_APB1Periph_TIM7 +#define TIMER_2MHz_TIMER TIM7 + +// Bluetooth +#if defined(PCBX12S) + #define BT_RCC_APB2Periph RCC_APB2Periph_USART6 + #define BT_USART USART6 + #define BT_GPIO_AF GPIO_AF_USART6 + #define BT_USART_IRQn USART6_IRQn + #define BT_GPIO_TXRX GPIOG + #define BT_TX_GPIO_PIN GPIO_Pin_14 // PG.14 + #define BT_RX_GPIO_PIN GPIO_Pin_9 // PG.09 + #if PCBREV >= 13 + #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOG) + #define BT_EN_GPIO GPIOI + #define BT_EN_GPIO_PIN GPIO_Pin_10 // PI.10 + #else + #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOG) + #define BT_EN_GPIO GPIOA + #define BT_EN_GPIO_PIN GPIO_Pin_6 // PA.06 + #endif + #define BT_BRTS_GPIO GPIOG + #define BT_BRTS_GPIO_PIN GPIO_Pin_10 // PG.10 + #define BT_BCTS_GPIO GPIOG + #define BT_BCTS_GPIO_PIN GPIO_Pin_11 // PG.11 + #define BT_TX_GPIO_PinSource GPIO_PinSource14 + #define BT_RX_GPIO_PinSource GPIO_PinSource9 +#endif + +// GPS +#define GPS_RCC_AHB1Periph RCC_AHB1Periph_GPIOA +#define GPS_RCC_APB1Periph RCC_APB1Periph_UART4 +#define GPS_USART UART4 +#define GPS_GPIO_AF GPIO_AF_UART4 +#define GPS_USART_IRQn UART4_IRQn +#define GPS_USART_IRQHandler UART4_IRQHandler +#define GPS_UART_GPIO GPIOA +#define GPS_TX_GPIO_PIN GPIO_Pin_0 // PA.00 +#define GPS_RX_GPIO_PIN GPIO_Pin_1 // PA.01 +#define GPS_TX_GPIO_PinSource GPIO_PinSource0 +#define GPS_RX_GPIO_PinSource GPIO_PinSource1 + +#endif // _HAL_H_ diff --git a/radio/src/targets/horus/keys_driver.cpp b/radio/src/targets/horus/keys_driver.cpp index e881727ba..9d56db031 100644 --- a/radio/src/targets/horus/keys_driver.cpp +++ b/radio/src/targets/horus/keys_driver.cpp @@ -1,217 +1,217 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -uint32_t rotencPosition; - -uint32_t readKeys() -{ - uint32_t result = 0; - -#if defined(PCBX12S) - if (~KEYS_GPIO_REG_PGUP & KEYS_GPIO_PIN_PGUP) - result |= 1 << KEY_PGUP; -#endif - if (~KEYS_GPIO_REG_PGDN & KEYS_GPIO_PIN_PGDN) - result |= 1 << KEY_PGDN; - if (~KEYS_GPIO_REG_ENTER & KEYS_GPIO_PIN_ENTER) - result |= 1 << KEY_ENTER; - if (~KEYS_GPIO_REG_UP & KEYS_GPIO_PIN_UP) - result |= 1 << KEY_MODEL; - if (~KEYS_GPIO_REG_DOWN & KEYS_GPIO_PIN_DOWN) - result |= 1 << KEY_EXIT; - if (~KEYS_GPIO_REG_RIGHT & KEYS_GPIO_PIN_RIGHT) - result |= 1 << KEY_TELEM; - if (~KEYS_GPIO_REG_LEFT & KEYS_GPIO_PIN_LEFT) - result |= 1 << KEY_RADIO; - - // TRACE("readKeys(): %x", result); - - return result; -} - -uint32_t readTrims() -{ - uint32_t result = 0; - - if (~TRIMS_GPIO_REG_LHL & TRIMS_GPIO_PIN_LHL) - result |= 0x01; - if (~TRIMS_GPIO_REG_LHR & TRIMS_GPIO_PIN_LHR) - result |= 0x02; - if (~TRIMS_GPIO_REG_LVD & TRIMS_GPIO_PIN_LVD) - result |= 0x04; - if (~TRIMS_GPIO_REG_LVU & TRIMS_GPIO_PIN_LVU) - result |= 0x08; - if (~TRIMS_GPIO_REG_RVD & TRIMS_GPIO_PIN_RVD) - result |= 0x10; - if (~TRIMS_GPIO_REG_RVU & TRIMS_GPIO_PIN_RVU) - result |= 0x20; - if (~TRIMS_GPIO_REG_RHL & TRIMS_GPIO_PIN_RHL) - result |= 0x40; - if (~TRIMS_GPIO_REG_RHR & TRIMS_GPIO_PIN_RHR) - result |= 0x80; - if (~TRIMS_GPIO_REG_LSD & TRIMS_GPIO_PIN_LSD) - result |= 0x100; - if (~TRIMS_GPIO_REG_LSU & TRIMS_GPIO_PIN_LSU) - result |= 0x200; - if (~TRIMS_GPIO_REG_RSD & TRIMS_GPIO_PIN_RSD) - result |= 0x400; - if (~TRIMS_GPIO_REG_RSU & TRIMS_GPIO_PIN_RSU) - result |= 0x800; - // TRACE("readTrims(): result=0x%04x", result); - - return result; -} - -uint16_t trimDown(uint16_t idx) -{ - return readTrims() & (1 << idx); -} - -uint8_t keyDown() -{ - return readKeys(); -} - -void checkRotaryEncoder() -{ - uint32_t newpos = ROTARY_ENCODER_POSITION(); - if (newpos != rotencPosition && !keyState(KEY_ENTER)) { - if ((rotencPosition & 0x01) ^ ((newpos & 0x02) >> 1)) { - --rotencValue[0]; - } - else { - ++rotencValue[0]; - } - rotencPosition = newpos; - } -} - -/* TODO common to ARM */ -void readKeysAndTrims() -{ - uint32_t i; - - uint8_t index = 0; - uint32_t in = readKeys(); - for (i = 0; i < TRM_BASE; i++) { - keys[index++].input(in & (1 << i)); - } - - in = readTrims(); - for (i = 1; i <= 1 << (TRM_LAST-TRM_BASE); i <<= 1) { - keys[index++].input(in & i); - } -} - -#define ADD_2POS_CASE(x) \ - case SW_S ## x ## 0: \ - xxx = SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ - break; \ - case SW_S ## x ## 2: \ - xxx = ~SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ - break -#define ADD_NEG_2POS_CASE(x) \ - case SW_S ## x ## 2: \ - xxx = SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ - break; \ - case SW_S ## x ## 0: \ - xxx = ~SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ - break -#define ADD_3POS_CASE(x, i) \ - case SW_S ## x ## 0: \ - xxx = (SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H); \ - if (IS_3POS(i)) { \ - xxx = xxx && (~SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ - } \ - break; \ - case SW_S ## x ## 1: \ - xxx = (SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H) && (SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ - break; \ - case SW_S ## x ## 2: \ - xxx = (~SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H); \ - if (IS_3POS(i)) { \ - xxx = xxx && (SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ - } \ - break - -#if !defined(BOOT) -uint8_t keyState(uint8_t index) -{ - return keys[index].state(); -} - -uint32_t switchState(uint8_t index) -{ - uint32_t xxx = 0; - - switch (index) { - ADD_3POS_CASE(A, 0); - ADD_3POS_CASE(B, 1); - ADD_3POS_CASE(C, 2); - ADD_3POS_CASE(D, 3); - ADD_3POS_CASE(E, 4); - ADD_NEG_2POS_CASE(F); - ADD_3POS_CASE(G, 6); - ADD_2POS_CASE(H); - default: - break; - } - - // TRACE("switch %d => %d", index, xxx); - return xxx; -} -#endif - -void keysInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; - - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOB_PINS; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOC_PINS; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOD_PINS; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOE_PINS; - GPIO_Init(GPIOE, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOG_PINS; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOH_PINS; - GPIO_Init(GPIOH, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOI_PINS; - GPIO_Init(GPIOI, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOJ_PINS; - GPIO_Init(GPIOJ, &GPIO_InitStructure); - - rotencPosition = ROTARY_ENCODER_POSITION(); -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +uint32_t rotencPosition; + +uint32_t readKeys() +{ + uint32_t result = 0; + +#if defined(PCBX12S) + if (~KEYS_GPIO_REG_PGUP & KEYS_GPIO_PIN_PGUP) + result |= 1 << KEY_PGUP; +#endif + if (~KEYS_GPIO_REG_PGDN & KEYS_GPIO_PIN_PGDN) + result |= 1 << KEY_PGDN; + if (~KEYS_GPIO_REG_ENTER & KEYS_GPIO_PIN_ENTER) + result |= 1 << KEY_ENTER; + if (~KEYS_GPIO_REG_UP & KEYS_GPIO_PIN_UP) + result |= 1 << KEY_MODEL; + if (~KEYS_GPIO_REG_DOWN & KEYS_GPIO_PIN_DOWN) + result |= 1 << KEY_EXIT; + if (~KEYS_GPIO_REG_RIGHT & KEYS_GPIO_PIN_RIGHT) + result |= 1 << KEY_TELEM; + if (~KEYS_GPIO_REG_LEFT & KEYS_GPIO_PIN_LEFT) + result |= 1 << KEY_RADIO; + + // TRACE("readKeys(): %x", result); + + return result; +} + +uint32_t readTrims() +{ + uint32_t result = 0; + + if (~TRIMS_GPIO_REG_LHL & TRIMS_GPIO_PIN_LHL) + result |= 0x01; + if (~TRIMS_GPIO_REG_LHR & TRIMS_GPIO_PIN_LHR) + result |= 0x02; + if (~TRIMS_GPIO_REG_LVD & TRIMS_GPIO_PIN_LVD) + result |= 0x04; + if (~TRIMS_GPIO_REG_LVU & TRIMS_GPIO_PIN_LVU) + result |= 0x08; + if (~TRIMS_GPIO_REG_RVD & TRIMS_GPIO_PIN_RVD) + result |= 0x10; + if (~TRIMS_GPIO_REG_RVU & TRIMS_GPIO_PIN_RVU) + result |= 0x20; + if (~TRIMS_GPIO_REG_RHL & TRIMS_GPIO_PIN_RHL) + result |= 0x40; + if (~TRIMS_GPIO_REG_RHR & TRIMS_GPIO_PIN_RHR) + result |= 0x80; + if (~TRIMS_GPIO_REG_LSD & TRIMS_GPIO_PIN_LSD) + result |= 0x100; + if (~TRIMS_GPIO_REG_LSU & TRIMS_GPIO_PIN_LSU) + result |= 0x200; + if (~TRIMS_GPIO_REG_RSD & TRIMS_GPIO_PIN_RSD) + result |= 0x400; + if (~TRIMS_GPIO_REG_RSU & TRIMS_GPIO_PIN_RSU) + result |= 0x800; + // TRACE("readTrims(): result=0x%04x", result); + + return result; +} + +uint16_t trimDown(uint16_t idx) +{ + return readTrims() & (1 << idx); +} + +uint8_t keyDown() +{ + return readKeys(); +} + +void checkRotaryEncoder() +{ + uint32_t newpos = ROTARY_ENCODER_POSITION(); + if (newpos != rotencPosition && !keyState(KEY_ENTER)) { + if ((rotencPosition & 0x01) ^ ((newpos & 0x02) >> 1)) { + --rotencValue[0]; + } + else { + ++rotencValue[0]; + } + rotencPosition = newpos; + } +} + +/* TODO common to ARM */ +void readKeysAndTrims() +{ + uint32_t i; + + uint8_t index = 0; + uint32_t in = readKeys(); + for (i = 0; i < TRM_BASE; i++) { + keys[index++].input(in & (1 << i)); + } + + in = readTrims(); + for (i = 1; i <= 1 << (TRM_LAST-TRM_BASE); i <<= 1) { + keys[index++].input(in & i); + } +} + +#define ADD_2POS_CASE(x) \ + case SW_S ## x ## 0: \ + xxx = SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ + break; \ + case SW_S ## x ## 2: \ + xxx = ~SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ + break +#define ADD_NEG_2POS_CASE(x) \ + case SW_S ## x ## 2: \ + xxx = SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ + break; \ + case SW_S ## x ## 0: \ + xxx = ~SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ + break +#define ADD_3POS_CASE(x, i) \ + case SW_S ## x ## 0: \ + xxx = (SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H); \ + if (IS_3POS(i)) { \ + xxx = xxx && (~SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ + } \ + break; \ + case SW_S ## x ## 1: \ + xxx = (SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H) && (SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ + break; \ + case SW_S ## x ## 2: \ + xxx = (~SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H); \ + if (IS_3POS(i)) { \ + xxx = xxx && (SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ + } \ + break + +#if !defined(BOOT) +uint8_t keyState(uint8_t index) +{ + return keys[index].state(); +} + +uint32_t switchState(uint8_t index) +{ + uint32_t xxx = 0; + + switch (index) { + ADD_3POS_CASE(A, 0); + ADD_3POS_CASE(B, 1); + ADD_3POS_CASE(C, 2); + ADD_3POS_CASE(D, 3); + ADD_3POS_CASE(E, 4); + ADD_NEG_2POS_CASE(F); + ADD_3POS_CASE(G, 6); + ADD_2POS_CASE(H); + default: + break; + } + + // TRACE("switch %d => %d", index, xxx); + return xxx; +} +#endif + +void keysInit() +{ + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOB_PINS; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOC_PINS; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOD_PINS; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOE_PINS; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOG_PINS; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOH_PINS; + GPIO_Init(GPIOH, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOI_PINS; + GPIO_Init(GPIOI, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOJ_PINS; + GPIO_Init(GPIOJ, &GPIO_InitStructure); + + rotencPosition = ROTARY_ENCODER_POSITION(); +} diff --git a/radio/src/targets/horus/lcd_driver.cpp b/radio/src/targets/horus/lcd_driver.cpp index b9a5773b3..f138a0df6 100644 --- a/radio/src/targets/horus/lcd_driver.cpp +++ b/radio/src/targets/horus/lcd_driver.cpp @@ -1,582 +1,582 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#define HBP 42 -#define VBP 12 - -#define HSW 2 -#define VSW 10 - -#define HFP 3 -#define VFP 2 - -#define LCD_FIRST_LAYER 0 -#define LCD_SECOND_LAYER 1 - -uint8_t LCD_FIRST_FRAME_BUFFER[DISPLAY_BUFFER_SIZE] __SDRAM; -uint8_t LCD_SECOND_FRAME_BUFFER[DISPLAY_BUFFER_SIZE] __SDRAM; -uint8_t LCD_BACKUP_FRAME_BUFFER[DISPLAY_BUFFER_SIZE] __SDRAM; - -uint32_t CurrentLayer = LCD_FIRST_LAYER; - -#define NRST_LOW() do { LCD_GPIO_NRST->BSRRH = LCD_GPIO_PIN_NRST; } while(0) -#define NRST_HIGH() do { LCD_GPIO_NRST->BSRRL = LCD_GPIO_PIN_NRST; } while(0) - -static void LCD_AF_GPIOConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* GPIOs Configuration */ - /* - +------------------------+-----------------------+----------------------------+ - + LCD pins assignment + - +------------------------+-----------------------+---------------------------- - | | LCD_TFT G2 <-> PJ.09 | | - | LCD_TFT R3 <-> PJ.02 | LCD_TFT G3 <-> PJ.10 | LCD_TFT B3 <-> PJ.15 | - | LCD_TFT R4 <-> PJ.03 | LCD_TFT G4 <-> PJ.11 | LCD_TFT B4 <-> PK.03 | - | LCD_TFT R5 <-> PJ.04 | LCD_TFT G5 <-> PK.00 | LCD_TFT B5 <-> PK.04 | - | LCD_TFT R6 <-> PJ.05 | LCD_TFT G6 <-> PK.01 | LCD_TFT B6 <-> PK.05 | - | LCD_TFT R7 <-> PJ.06 | LCD_TFT G7 <-> PK.02 | LCD_TFT B7 <-> PK.06 | - ------------------------------------------------------------------------------- - | LCD_TFT HSYNC <-> PI.12 | LCDTFT VSYNC <-> PI.13 | - | LCD_TFT CLK <-> PI.14 | LCD_TFT DE <-> PK.07 /// - ----------------------------------------------------- - | LCD_CS <-> PI.10 |LCD_SCK<->PI.11 - ----------------------------------------------------- - */ - // GPIOI configuration - GPIO_PinAFConfig(GPIOI, GPIO_PinSource12, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOI, GPIO_PinSource13, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOI, GPIO_PinSource14, GPIO_AF_LTDC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14; - GPIO_InitStructure.GPIO_Speed =GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_Mode =GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType =GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd =GPIO_PuPd_NOPULL; - GPIO_Init(GPIOI, &GPIO_InitStructure); - - GPIO_PinAFConfig(GPIOK, GPIO_PinSource7, GPIO_AF_LTDC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; - GPIO_Init(GPIOK, &GPIO_InitStructure); - - // GPIOJ configuration - GPIO_PinAFConfig(GPIOJ, GPIO_PinSource2, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOJ, GPIO_PinSource3, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOJ, GPIO_PinSource4, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOJ, GPIO_PinSource5, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOJ, GPIO_PinSource6, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOJ, GPIO_PinSource9, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOJ, GPIO_PinSource10, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOJ, GPIO_PinSource11, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOJ, GPIO_PinSource15, GPIO_AF_LTDC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | \ - GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_15; - - GPIO_Init(GPIOJ, &GPIO_InitStructure); - - // GPIOK configuration - GPIO_PinAFConfig(GPIOK, GPIO_PinSource0, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOK, GPIO_PinSource1, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOK, GPIO_PinSource2, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOK, GPIO_PinSource3, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOK, GPIO_PinSource4, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOK, GPIO_PinSource5, GPIO_AF_LTDC); - GPIO_PinAFConfig(GPIOK, GPIO_PinSource6, GPIO_AF_LTDC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 ; - - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOK, &GPIO_InitStructure); -} - -static void LCD_NRSTConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = LCD_GPIO_PIN_NRST; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(LCD_GPIO_NRST, &GPIO_InitStructure); -} - -// TODO delay function -static void delay3(uint32_t nCount) -{ - uint32_t index = 0; - for(index = (1000 * 100 * nCount); index != 0; --index) - { - __asm("nop\n"); - } -} - -static void lcd_reset(void) -{ - NRST_HIGH(); - delay3(1); - - NRST_LOW(); // RESET(); - delay3(20); - - NRST_HIGH(); - delay3(30); -} - -void LCD_Init_LTDC(void) -{ - LTDC_InitTypeDef LTDC_InitStruct; - - /* Configure PLLSAI prescalers for LCD */ - /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAI_N = 192 Mhz */ - /* PLLLCDCLK = PLLSAI_VCO Output/PLL_LTDC = 192/3 = 64 Mhz */ - /* LTDC clock frequency = PLLLCDCLK / RCC_PLLSAIDivR = 64/4 = 16 Mhz */ - //second pam is for audio - //third pam is for LCD - RCC_PLLSAIConfig(192, 6, 3); - RCC_LTDCCLKDivConfig(RCC_PLLSAIDivR_Div4); //Modify by Fy - /* Enable PLLSAI Clock */ - RCC_PLLSAICmd(ENABLE); - - /* Wait for PLLSAI activation */ - while(RCC_GetFlagStatus(RCC_FLAG_PLLSAIRDY) == RESET) - { - } - - /* LTDC Configuration *********************************************************/ - /* Polarity configuration */ - /* Initialize the horizontal synchronization polarity as active low */ - LTDC_InitStruct.LTDC_HSPolarity = LTDC_HSPolarity_AL; - /* Initialize the vertical synchronization polarity as active low */ - LTDC_InitStruct.LTDC_VSPolarity = LTDC_VSPolarity_AL; - /* Initialize the data enable polarity as active low */ - LTDC_InitStruct.LTDC_DEPolarity = LTDC_DEPolarity_AL; - /* Initialize the pixel clock polarity as input pixel clock */ - LTDC_InitStruct.LTDC_PCPolarity = LTDC_PCPolarity_IPC; - - /* Configure R,G,B component values for LCD background color */ - LTDC_InitStruct.LTDC_BackgroundRedValue = 0; - LTDC_InitStruct.LTDC_BackgroundGreenValue = 0; - LTDC_InitStruct.LTDC_BackgroundBlueValue = 0; - - /* Configure horizontal synchronization width */ - LTDC_InitStruct.LTDC_HorizontalSync = HSW; - /* Configure vertical synchronization height */ - LTDC_InitStruct.LTDC_VerticalSync = VSW; - /* Configure accumulated horizontal back porch */ - LTDC_InitStruct.LTDC_AccumulatedHBP = HBP; - /* Configure accumulated vertical back porch */ - LTDC_InitStruct.LTDC_AccumulatedVBP = VBP; - /* Configure accumulated active width */ - LTDC_InitStruct.LTDC_AccumulatedActiveW = LCD_W + HBP; - /* Configure accumulated active height */ - LTDC_InitStruct.LTDC_AccumulatedActiveH = LCD_H + VBP; - /* Configure total width */ - LTDC_InitStruct.LTDC_TotalWidth = LCD_W + HBP + HFP; - /* Configure total height */ - LTDC_InitStruct.LTDC_TotalHeigh = LCD_H + VBP + VFP; - -// init ltdc - LTDC_Init(<DC_InitStruct); - -#if 0 - LTDC_ITConfig(LTDC_IER_LIE, ENABLE); - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = LTDC_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = LTDC_IRQ_PRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pr e-emption priority. */; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init( &NVIC_InitStructure ); - - DMA2D_ITConfig(DMA2D_CR_TCIE, ENABLE); - NVIC_InitStructure.NVIC_IRQChannel = DMA2D_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = DMA_SCREEN_IRQ_PRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pr e-emption priority. */; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init( &NVIC_InitStructure ); - - DMA2D->IFCR = (unsigned long)DMA2D_IFSR_CTCIF; -#endif -} - -/** - * @brief Initializes the LCD Layers. - * @param None - * @retval None - */ -void LCD_LayerInit() -{ - LTDC_Layer_InitTypeDef LTDC_Layer_InitStruct; - - /* Windowing configuration */ - /* In this case all the active display area is used to display a picture then : - Horizontal start = horizontal synchronization + Horizontal back porch = 30 - Horizontal stop = Horizontal start + window width -1 = 30 + 240 -1 - Vertical start = vertical synchronization + vertical back porch = 4 - Vertical stop = Vertical start + window height -1 = 4 + 320 -1 */ - LTDC_Layer_InitStruct.LTDC_HorizontalStart = HBP + 1; - LTDC_Layer_InitStruct.LTDC_HorizontalStop = (LCD_W + HBP); - LTDC_Layer_InitStruct.LTDC_VerticalStart = VBP + 1;; - LTDC_Layer_InitStruct.LTDC_VerticalStop = (LCD_H + VBP); - - /* Pixel Format configuration*/ - LTDC_Layer_InitStruct.LTDC_PixelFormat = LTDC_Pixelformat_RGB565; - /* Alpha constant (255 totally opaque) */ - LTDC_Layer_InitStruct.LTDC_ConstantAlpha = 255; - /* Default Color configuration (configure A,R,G,B component values) */ - LTDC_Layer_InitStruct.LTDC_DefaultColorBlue = 0; - LTDC_Layer_InitStruct.LTDC_DefaultColorGreen = 0; - LTDC_Layer_InitStruct.LTDC_DefaultColorRed = 0; - LTDC_Layer_InitStruct.LTDC_DefaultColorAlpha = 0; - - /* Configure blending factors */ - LTDC_Layer_InitStruct.LTDC_BlendingFactor_1 = LTDC_BlendingFactor1_CA; - LTDC_Layer_InitStruct.LTDC_BlendingFactor_2 = LTDC_BlendingFactor2_CA; - - /* the length of one line of pixels in bytes + 3 then : - Line Lenth = Active high width x number of bytes per pixel + 3 - Active high width = LCD_W - number of bytes per pixel = 2 (pixel_format : RGB565) - */ - LTDC_Layer_InitStruct.LTDC_CFBLineLength = ((LCD_W * 2) + 3); - /* the pitch is the increment from the start of one line of pixels to the - start of the next line in bytes, then : - Pitch = Active high width x number of bytes per pixel */ - LTDC_Layer_InitStruct.LTDC_CFBPitch = (LCD_W * 2); - - /* Configure the number of lines */ - LTDC_Layer_InitStruct.LTDC_CFBLineNumber = LCD_H; - - /* Start Address configuration : the LCD Frame buffer is defined on SDRAM w/ Offset */ - LTDC_Layer_InitStruct.LTDC_CFBStartAdress = (uint32_t)LCD_FIRST_FRAME_BUFFER; - - /* Initialize LTDC layer 1 */ - LTDC_LayerInit(LTDC_Layer1, <DC_Layer_InitStruct); - - /* Configure Layer 2 */ - LTDC_Layer_InitStruct.LTDC_BlendingFactor_1 = LTDC_BlendingFactor1_PAxCA; - LTDC_Layer_InitStruct.LTDC_BlendingFactor_2 = LTDC_BlendingFactor2_PAxCA; - - /* Start Address configuration : the LCD Frame buffer is defined on SDRAM w/ Offset */ - LTDC_Layer_InitStruct.LTDC_CFBStartAdress = (uint32_t)LCD_SECOND_FRAME_BUFFER; - - /* Initialize LTDC layer 2 */ - LTDC_LayerInit(LTDC_Layer2, <DC_Layer_InitStruct); - - /* LTDC configuration reload */ - LTDC_ReloadConfig(LTDC_IMReload); - - LTDC_LayerCmd(LTDC_Layer1, ENABLE); - LTDC_LayerCmd(LTDC_Layer2, ENABLE); - - LTDC_ReloadConfig(LTDC_IMReload); - - /* dithering activation */ - LTDC_DitherCmd(ENABLE); -} - -/*********************************output****************************************/ -/** - * @brief Initializes the LCD. - * @param None - * @retval None - */ -void LCD_Init(void) -{ - /* Reset the LCD --------------------------------------------------------*/ - LCD_NRSTConfig(); - lcd_reset(); - - /* Configure the LCD Control pins */ - LCD_AF_GPIOConfig(); - - LCD_Init_LTDC(); -} - -BitmapBuffer lcdBuffer1(BMP_RGB565, LCD_W, LCD_H, (uint16_t *)LCD_FIRST_FRAME_BUFFER); -BitmapBuffer lcdBuffer2(BMP_RGB565, LCD_W, LCD_H, (uint16_t *)LCD_SECOND_FRAME_BUFFER); -BitmapBuffer * lcd = &lcdBuffer1; - -/** - * @brief Sets the LCD Layer. - * @param Layerx: specifies the Layer foreground or background. - * @retval None - */ -void LCD_SetLayer(uint32_t Layerx) -{ - if (Layerx == LCD_FIRST_LAYER) { - lcd = &lcdBuffer1; - CurrentLayer = LCD_FIRST_LAYER; - } - else { - lcd = &lcdBuffer2; - CurrentLayer = LCD_SECOND_LAYER; - } -} - -/** - * @brief Configure the transparency. - * @param transparency: specifies the transparency, - * This parameter must range from 0x00 to 0xFF. - * @retval None - */ -void LCD_SetTransparency(uint8_t transparency) -{ - if (CurrentLayer == LCD_FIRST_LAYER) { - LTDC_LayerAlpha(LTDC_Layer1, transparency); - } - else { - LTDC_LayerAlpha(LTDC_Layer2, transparency); - } - LTDC_ReloadConfig(LTDC_IMReload); -} - -void lcdInit(void) -{ - /* Initialize the LCD */ - LCD_Init(); - LCD_LayerInit(); - - /* Enable LCD display */ - LTDC_Cmd(ENABLE); - - /* Set Background layer */ - LCD_SetLayer(LCD_FIRST_LAYER); - // lcdClear(); - LCD_SetTransparency(0); - - /* Set Foreground layer */ - LCD_SetLayer(LCD_SECOND_LAYER); - lcd->clear(); - LCD_SetTransparency(255); -} - -void DMAFillRect(uint16_t * dest, uint16_t destw, uint16_t desth, uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t color) -{ -#if defined(PCBX10) - x = destw - (x + w); - y = desth - (y + h); -#endif - - DMA2D_DeInit(); - - DMA2D_InitTypeDef DMA2D_InitStruct; - DMA2D_InitStruct.DMA2D_Mode = DMA2D_R2M; - DMA2D_InitStruct.DMA2D_CMode = DMA2D_RGB565; - DMA2D_InitStruct.DMA2D_OutputGreen = (0x07E0 & color) >> 5; - DMA2D_InitStruct.DMA2D_OutputBlue = 0x001F & color; - DMA2D_InitStruct.DMA2D_OutputRed = (0xF800 & color) >> 11; - DMA2D_InitStruct.DMA2D_OutputAlpha = 0x0F; - DMA2D_InitStruct.DMA2D_OutputMemoryAdd = CONVERT_PTR_UINT(dest) + 2*(destw*y + x); - DMA2D_InitStruct.DMA2D_OutputOffset = (destw - w); - DMA2D_InitStruct.DMA2D_NumberOfLine = h; - DMA2D_InitStruct.DMA2D_PixelPerLine = w; - DMA2D_Init(&DMA2D_InitStruct); - - /* Start Transfer */ - DMA2D_StartTransfer(); - - /* Wait for CTC Flag activation */ - while (DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET); -} - -void DMACopyBitmap(uint16_t * dest, uint16_t destw, uint16_t desth, uint16_t x, uint16_t y, const uint16_t * src, uint16_t srcw, uint16_t srch, uint16_t srcx, uint16_t srcy, uint16_t w, uint16_t h) -{ -#if defined(PCBX10) - x = destw - (x + w); - y = desth - (y + h); - srcx = srcw - (srcx + w); - srcy = srch - (srcy + h); -#endif - - DMA2D_DeInit(); - - DMA2D_InitTypeDef DMA2D_InitStruct; - DMA2D_InitStruct.DMA2D_Mode = DMA2D_M2M; - DMA2D_InitStruct.DMA2D_CMode = DMA2D_RGB565; - DMA2D_InitStruct.DMA2D_OutputMemoryAdd = CONVERT_PTR_UINT(dest + y*destw + x); - DMA2D_InitStruct.DMA2D_OutputGreen = 0; - DMA2D_InitStruct.DMA2D_OutputBlue = 0; - DMA2D_InitStruct.DMA2D_OutputRed = 0; - DMA2D_InitStruct.DMA2D_OutputAlpha = 0; - DMA2D_InitStruct.DMA2D_OutputOffset = destw - w; - DMA2D_InitStruct.DMA2D_NumberOfLine = h; - DMA2D_InitStruct.DMA2D_PixelPerLine = w; - DMA2D_Init(&DMA2D_InitStruct); - - DMA2D_FG_InitTypeDef DMA2D_FG_InitStruct; - DMA2D_FG_StructInit(&DMA2D_FG_InitStruct); - DMA2D_FG_InitStruct.DMA2D_FGMA = CONVERT_PTR_UINT(src + srcy*srcw + srcx); - DMA2D_FG_InitStruct.DMA2D_FGO = srcw - w; - DMA2D_FG_InitStruct.DMA2D_FGCM = CM_RGB565; - DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; - DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_VALUE = 0; - DMA2D_FGConfig(&DMA2D_FG_InitStruct); - - /* Start Transfer */ - DMA2D_StartTransfer(); - - /* Wait for CTC Flag activation */ - while (DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET); -} - -void DMACopyAlphaBitmap(uint16_t * dest, uint16_t destw, uint16_t desth, uint16_t x, uint16_t y, const uint16_t * src, uint16_t srcw, uint16_t srch, uint16_t srcx, uint16_t srcy, uint16_t w, uint16_t h) -{ -#if defined(PCBX10) - x = destw - (x + w); - y = desth - (y + h); - srcx = srcw - (srcx + w); - srcy = srch - (srcy + h); -#endif - - DMA2D_DeInit(); - - DMA2D_InitTypeDef DMA2D_InitStruct; - DMA2D_InitStruct.DMA2D_Mode = DMA2D_M2M_BLEND; - DMA2D_InitStruct.DMA2D_CMode = DMA2D_RGB565; - DMA2D_InitStruct.DMA2D_OutputMemoryAdd = CONVERT_PTR_UINT(dest + y*destw + x); - DMA2D_InitStruct.DMA2D_OutputGreen = 0; - DMA2D_InitStruct.DMA2D_OutputBlue = 0; - DMA2D_InitStruct.DMA2D_OutputRed = 0; - DMA2D_InitStruct.DMA2D_OutputAlpha = 0; - DMA2D_InitStruct.DMA2D_OutputOffset = destw - w; - DMA2D_InitStruct.DMA2D_NumberOfLine = h; - DMA2D_InitStruct.DMA2D_PixelPerLine = w; - DMA2D_Init(&DMA2D_InitStruct); - - DMA2D_FG_InitTypeDef DMA2D_FG_InitStruct; - DMA2D_FG_StructInit(&DMA2D_FG_InitStruct); - DMA2D_FG_InitStruct.DMA2D_FGMA = CONVERT_PTR_UINT(src + srcy*srcw + srcx); - DMA2D_FG_InitStruct.DMA2D_FGO = srcw - w; - DMA2D_FG_InitStruct.DMA2D_FGCM = CM_ARGB4444; - DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; - DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_VALUE = 0; - DMA2D_FGConfig(&DMA2D_FG_InitStruct); - - DMA2D_BG_InitTypeDef DMA2D_BG_InitStruct; - DMA2D_BG_StructInit(&DMA2D_BG_InitStruct); - DMA2D_BG_InitStruct.DMA2D_BGMA = CONVERT_PTR_UINT(dest + y*destw + x); - DMA2D_BG_InitStruct.DMA2D_BGO = destw - w; - DMA2D_BG_InitStruct.DMA2D_BGCM = CM_RGB565; - DMA2D_BG_InitStruct.DMA2D_BGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; - DMA2D_BG_InitStruct.DMA2D_BGPFC_ALPHA_VALUE = 0; - DMA2D_BGConfig(&DMA2D_BG_InitStruct); - - /* Start Transfer */ - DMA2D_StartTransfer(); - - /* Wait for CTC Flag activation */ - while (DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET); -} - -void DMABitmapConvert(uint16_t * dest, const uint8_t * src, uint16_t w, uint16_t h, uint32_t format) -{ - DMA2D_DeInit(); - - DMA2D_InitTypeDef DMA2D_InitStruct; - DMA2D_InitStruct.DMA2D_Mode = DMA2D_M2M_PFC; - DMA2D_InitStruct.DMA2D_CMode = format; - DMA2D_InitStruct.DMA2D_OutputMemoryAdd = CONVERT_PTR_UINT(dest); - DMA2D_InitStruct.DMA2D_OutputGreen = 0; - DMA2D_InitStruct.DMA2D_OutputBlue = 0; - DMA2D_InitStruct.DMA2D_OutputRed = 0; - DMA2D_InitStruct.DMA2D_OutputAlpha = 0; - DMA2D_InitStruct.DMA2D_OutputOffset = 0; - DMA2D_InitStruct.DMA2D_NumberOfLine = h; - DMA2D_InitStruct.DMA2D_PixelPerLine = w; - DMA2D_Init(&DMA2D_InitStruct); - - DMA2D_FG_InitTypeDef DMA2D_FG_InitStruct; - DMA2D_FG_StructInit(&DMA2D_FG_InitStruct); - DMA2D_FG_InitStruct.DMA2D_FGMA = CONVERT_PTR_UINT(src); - DMA2D_FG_InitStruct.DMA2D_FGO = 0; - DMA2D_FG_InitStruct.DMA2D_FGCM = CM_ARGB8888; - DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_MODE = REPLACE_ALPHA_VALUE; - DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_VALUE = 0; - DMA2D_FGConfig(&DMA2D_FG_InitStruct); - - /* Start Transfer */ - DMA2D_StartTransfer(); - - /* Wait for CTC Flag activation */ - while (DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET); -} - -void DMAcopy(void * src, void * dest, int len) -{ - DMA2D_DeInit(); - - DMA2D_InitTypeDef DMA2D_InitStruct; - DMA2D_InitStruct.DMA2D_Mode = DMA2D_M2M; - DMA2D_InitStruct.DMA2D_CMode = DMA2D_RGB565; - DMA2D_InitStruct.DMA2D_OutputMemoryAdd = CONVERT_PTR_UINT(dest); - DMA2D_InitStruct.DMA2D_OutputGreen = 0; - DMA2D_InitStruct.DMA2D_OutputBlue = 0; - DMA2D_InitStruct.DMA2D_OutputRed = 0; - DMA2D_InitStruct.DMA2D_OutputAlpha = 0; - DMA2D_InitStruct.DMA2D_OutputOffset = 0; - DMA2D_InitStruct.DMA2D_NumberOfLine = LCD_H; - DMA2D_InitStruct.DMA2D_PixelPerLine = LCD_W; - DMA2D_Init(&DMA2D_InitStruct); - - DMA2D_FG_InitTypeDef DMA2D_FG_InitStruct; - DMA2D_FG_StructInit(&DMA2D_FG_InitStruct); - DMA2D_FG_InitStruct.DMA2D_FGMA = CONVERT_PTR_UINT(src); - DMA2D_FG_InitStruct.DMA2D_FGO = 0; - DMA2D_FG_InitStruct.DMA2D_FGCM = CM_RGB565; - DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; - DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_VALUE = 0; - DMA2D_FGConfig(&DMA2D_FG_InitStruct); - - /* Start Transfer */ - DMA2D_StartTransfer(); - - /* Wait for CTC Flag activation */ - while (DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET); -} - -void lcdStoreBackupBuffer() -{ - DMAcopy(lcd->getData(), LCD_BACKUP_FRAME_BUFFER, DISPLAY_BUFFER_SIZE); -} - -int lcdRestoreBackupBuffer() -{ - DMAcopy(LCD_BACKUP_FRAME_BUFFER, lcd->getData(), DISPLAY_BUFFER_SIZE); - return 1; -} - -void lcdRefresh() -{ - LCD_SetTransparency(255); - if (CurrentLayer == LCD_FIRST_LAYER) - LCD_SetLayer(LCD_SECOND_LAYER); - else - LCD_SetLayer(LCD_FIRST_LAYER); - LCD_SetTransparency(0); -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#define HBP 42 +#define VBP 12 + +#define HSW 2 +#define VSW 10 + +#define HFP 3 +#define VFP 2 + +#define LCD_FIRST_LAYER 0 +#define LCD_SECOND_LAYER 1 + +uint8_t LCD_FIRST_FRAME_BUFFER[DISPLAY_BUFFER_SIZE] __SDRAM; +uint8_t LCD_SECOND_FRAME_BUFFER[DISPLAY_BUFFER_SIZE] __SDRAM; +uint8_t LCD_BACKUP_FRAME_BUFFER[DISPLAY_BUFFER_SIZE] __SDRAM; + +uint32_t CurrentLayer = LCD_FIRST_LAYER; + +#define NRST_LOW() do { LCD_GPIO_NRST->BSRRH = LCD_GPIO_PIN_NRST; } while(0) +#define NRST_HIGH() do { LCD_GPIO_NRST->BSRRL = LCD_GPIO_PIN_NRST; } while(0) + +static void LCD_AF_GPIOConfig(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* GPIOs Configuration */ + /* + +------------------------+-----------------------+----------------------------+ + + LCD pins assignment + + +------------------------+-----------------------+---------------------------- + | | LCD_TFT G2 <-> PJ.09 | | + | LCD_TFT R3 <-> PJ.02 | LCD_TFT G3 <-> PJ.10 | LCD_TFT B3 <-> PJ.15 | + | LCD_TFT R4 <-> PJ.03 | LCD_TFT G4 <-> PJ.11 | LCD_TFT B4 <-> PK.03 | + | LCD_TFT R5 <-> PJ.04 | LCD_TFT G5 <-> PK.00 | LCD_TFT B5 <-> PK.04 | + | LCD_TFT R6 <-> PJ.05 | LCD_TFT G6 <-> PK.01 | LCD_TFT B6 <-> PK.05 | + | LCD_TFT R7 <-> PJ.06 | LCD_TFT G7 <-> PK.02 | LCD_TFT B7 <-> PK.06 | + ------------------------------------------------------------------------------- + | LCD_TFT HSYNC <-> PI.12 | LCDTFT VSYNC <-> PI.13 | + | LCD_TFT CLK <-> PI.14 | LCD_TFT DE <-> PK.07 /// + ----------------------------------------------------- + | LCD_CS <-> PI.10 |LCD_SCK<->PI.11 + ----------------------------------------------------- + */ + // GPIOI configuration + GPIO_PinAFConfig(GPIOI, GPIO_PinSource12, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOI, GPIO_PinSource13, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOI, GPIO_PinSource14, GPIO_AF_LTDC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14; + GPIO_InitStructure.GPIO_Speed =GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_Mode =GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType =GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd =GPIO_PuPd_NOPULL; + GPIO_Init(GPIOI, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOK, GPIO_PinSource7, GPIO_AF_LTDC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_Init(GPIOK, &GPIO_InitStructure); + + // GPIOJ configuration + GPIO_PinAFConfig(GPIOJ, GPIO_PinSource2, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOJ, GPIO_PinSource3, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOJ, GPIO_PinSource4, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOJ, GPIO_PinSource5, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOJ, GPIO_PinSource6, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOJ, GPIO_PinSource9, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOJ, GPIO_PinSource10, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOJ, GPIO_PinSource11, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOJ, GPIO_PinSource15, GPIO_AF_LTDC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | \ + GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_15; + + GPIO_Init(GPIOJ, &GPIO_InitStructure); + + // GPIOK configuration + GPIO_PinAFConfig(GPIOK, GPIO_PinSource0, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOK, GPIO_PinSource1, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOK, GPIO_PinSource2, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOK, GPIO_PinSource3, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOK, GPIO_PinSource4, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOK, GPIO_PinSource5, GPIO_AF_LTDC); + GPIO_PinAFConfig(GPIOK, GPIO_PinSource6, GPIO_AF_LTDC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 ; + + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOK, &GPIO_InitStructure); +} + +static void LCD_NRSTConfig(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = LCD_GPIO_PIN_NRST; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(LCD_GPIO_NRST, &GPIO_InitStructure); +} + +// TODO delay function +static void delay3(uint32_t nCount) +{ + uint32_t index = 0; + for(index = (1000 * 100 * nCount); index != 0; --index) + { + __asm("nop\n"); + } +} + +static void lcd_reset(void) +{ + NRST_HIGH(); + delay3(1); + + NRST_LOW(); // RESET(); + delay3(20); + + NRST_HIGH(); + delay3(30); +} + +void LCD_Init_LTDC(void) +{ + LTDC_InitTypeDef LTDC_InitStruct; + + /* Configure PLLSAI prescalers for LCD */ + /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAI_N = 192 Mhz */ + /* PLLLCDCLK = PLLSAI_VCO Output/PLL_LTDC = 192/3 = 64 Mhz */ + /* LTDC clock frequency = PLLLCDCLK / RCC_PLLSAIDivR = 64/4 = 16 Mhz */ + //second pam is for audio + //third pam is for LCD + RCC_PLLSAIConfig(192, 6, 3); + RCC_LTDCCLKDivConfig(RCC_PLLSAIDivR_Div4); //Modify by Fy + /* Enable PLLSAI Clock */ + RCC_PLLSAICmd(ENABLE); + + /* Wait for PLLSAI activation */ + while(RCC_GetFlagStatus(RCC_FLAG_PLLSAIRDY) == RESET) + { + } + + /* LTDC Configuration *********************************************************/ + /* Polarity configuration */ + /* Initialize the horizontal synchronization polarity as active low */ + LTDC_InitStruct.LTDC_HSPolarity = LTDC_HSPolarity_AL; + /* Initialize the vertical synchronization polarity as active low */ + LTDC_InitStruct.LTDC_VSPolarity = LTDC_VSPolarity_AL; + /* Initialize the data enable polarity as active low */ + LTDC_InitStruct.LTDC_DEPolarity = LTDC_DEPolarity_AL; + /* Initialize the pixel clock polarity as input pixel clock */ + LTDC_InitStruct.LTDC_PCPolarity = LTDC_PCPolarity_IPC; + + /* Configure R,G,B component values for LCD background color */ + LTDC_InitStruct.LTDC_BackgroundRedValue = 0; + LTDC_InitStruct.LTDC_BackgroundGreenValue = 0; + LTDC_InitStruct.LTDC_BackgroundBlueValue = 0; + + /* Configure horizontal synchronization width */ + LTDC_InitStruct.LTDC_HorizontalSync = HSW; + /* Configure vertical synchronization height */ + LTDC_InitStruct.LTDC_VerticalSync = VSW; + /* Configure accumulated horizontal back porch */ + LTDC_InitStruct.LTDC_AccumulatedHBP = HBP; + /* Configure accumulated vertical back porch */ + LTDC_InitStruct.LTDC_AccumulatedVBP = VBP; + /* Configure accumulated active width */ + LTDC_InitStruct.LTDC_AccumulatedActiveW = LCD_W + HBP; + /* Configure accumulated active height */ + LTDC_InitStruct.LTDC_AccumulatedActiveH = LCD_H + VBP; + /* Configure total width */ + LTDC_InitStruct.LTDC_TotalWidth = LCD_W + HBP + HFP; + /* Configure total height */ + LTDC_InitStruct.LTDC_TotalHeigh = LCD_H + VBP + VFP; + +// init ltdc + LTDC_Init(<DC_InitStruct); + +#if 0 + LTDC_ITConfig(LTDC_IER_LIE, ENABLE); + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = LTDC_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = LTDC_IRQ_PRIO; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pr e-emption priority. */; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init( &NVIC_InitStructure ); + + DMA2D_ITConfig(DMA2D_CR_TCIE, ENABLE); + NVIC_InitStructure.NVIC_IRQChannel = DMA2D_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = DMA_SCREEN_IRQ_PRIO; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pr e-emption priority. */; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init( &NVIC_InitStructure ); + + DMA2D->IFCR = (unsigned long)DMA2D_IFSR_CTCIF; +#endif +} + +/** + * @brief Initializes the LCD Layers. + * @param None + * @retval None + */ +void LCD_LayerInit() +{ + LTDC_Layer_InitTypeDef LTDC_Layer_InitStruct; + + /* Windowing configuration */ + /* In this case all the active display area is used to display a picture then : + Horizontal start = horizontal synchronization + Horizontal back porch = 30 + Horizontal stop = Horizontal start + window width -1 = 30 + 240 -1 + Vertical start = vertical synchronization + vertical back porch = 4 + Vertical stop = Vertical start + window height -1 = 4 + 320 -1 */ + LTDC_Layer_InitStruct.LTDC_HorizontalStart = HBP + 1; + LTDC_Layer_InitStruct.LTDC_HorizontalStop = (LCD_W + HBP); + LTDC_Layer_InitStruct.LTDC_VerticalStart = VBP + 1;; + LTDC_Layer_InitStruct.LTDC_VerticalStop = (LCD_H + VBP); + + /* Pixel Format configuration*/ + LTDC_Layer_InitStruct.LTDC_PixelFormat = LTDC_Pixelformat_RGB565; + /* Alpha constant (255 totally opaque) */ + LTDC_Layer_InitStruct.LTDC_ConstantAlpha = 255; + /* Default Color configuration (configure A,R,G,B component values) */ + LTDC_Layer_InitStruct.LTDC_DefaultColorBlue = 0; + LTDC_Layer_InitStruct.LTDC_DefaultColorGreen = 0; + LTDC_Layer_InitStruct.LTDC_DefaultColorRed = 0; + LTDC_Layer_InitStruct.LTDC_DefaultColorAlpha = 0; + + /* Configure blending factors */ + LTDC_Layer_InitStruct.LTDC_BlendingFactor_1 = LTDC_BlendingFactor1_CA; + LTDC_Layer_InitStruct.LTDC_BlendingFactor_2 = LTDC_BlendingFactor2_CA; + + /* the length of one line of pixels in bytes + 3 then : + Line Lenth = Active high width x number of bytes per pixel + 3 + Active high width = LCD_W + number of bytes per pixel = 2 (pixel_format : RGB565) + */ + LTDC_Layer_InitStruct.LTDC_CFBLineLength = ((LCD_W * 2) + 3); + /* the pitch is the increment from the start of one line of pixels to the + start of the next line in bytes, then : + Pitch = Active high width x number of bytes per pixel */ + LTDC_Layer_InitStruct.LTDC_CFBPitch = (LCD_W * 2); + + /* Configure the number of lines */ + LTDC_Layer_InitStruct.LTDC_CFBLineNumber = LCD_H; + + /* Start Address configuration : the LCD Frame buffer is defined on SDRAM w/ Offset */ + LTDC_Layer_InitStruct.LTDC_CFBStartAdress = (uint32_t)LCD_FIRST_FRAME_BUFFER; + + /* Initialize LTDC layer 1 */ + LTDC_LayerInit(LTDC_Layer1, <DC_Layer_InitStruct); + + /* Configure Layer 2 */ + LTDC_Layer_InitStruct.LTDC_BlendingFactor_1 = LTDC_BlendingFactor1_PAxCA; + LTDC_Layer_InitStruct.LTDC_BlendingFactor_2 = LTDC_BlendingFactor2_PAxCA; + + /* Start Address configuration : the LCD Frame buffer is defined on SDRAM w/ Offset */ + LTDC_Layer_InitStruct.LTDC_CFBStartAdress = (uint32_t)LCD_SECOND_FRAME_BUFFER; + + /* Initialize LTDC layer 2 */ + LTDC_LayerInit(LTDC_Layer2, <DC_Layer_InitStruct); + + /* LTDC configuration reload */ + LTDC_ReloadConfig(LTDC_IMReload); + + LTDC_LayerCmd(LTDC_Layer1, ENABLE); + LTDC_LayerCmd(LTDC_Layer2, ENABLE); + + LTDC_ReloadConfig(LTDC_IMReload); + + /* dithering activation */ + LTDC_DitherCmd(ENABLE); +} + +/*********************************output****************************************/ +/** + * @brief Initializes the LCD. + * @param None + * @retval None + */ +void LCD_Init(void) +{ + /* Reset the LCD --------------------------------------------------------*/ + LCD_NRSTConfig(); + lcd_reset(); + + /* Configure the LCD Control pins */ + LCD_AF_GPIOConfig(); + + LCD_Init_LTDC(); +} + +BitmapBuffer lcdBuffer1(BMP_RGB565, LCD_W, LCD_H, (uint16_t *)LCD_FIRST_FRAME_BUFFER); +BitmapBuffer lcdBuffer2(BMP_RGB565, LCD_W, LCD_H, (uint16_t *)LCD_SECOND_FRAME_BUFFER); +BitmapBuffer * lcd = &lcdBuffer1; + +/** + * @brief Sets the LCD Layer. + * @param Layerx: specifies the Layer foreground or background. + * @retval None + */ +void LCD_SetLayer(uint32_t Layerx) +{ + if (Layerx == LCD_FIRST_LAYER) { + lcd = &lcdBuffer1; + CurrentLayer = LCD_FIRST_LAYER; + } + else { + lcd = &lcdBuffer2; + CurrentLayer = LCD_SECOND_LAYER; + } +} + +/** + * @brief Configure the transparency. + * @param transparency: specifies the transparency, + * This parameter must range from 0x00 to 0xFF. + * @retval None + */ +void LCD_SetTransparency(uint8_t transparency) +{ + if (CurrentLayer == LCD_FIRST_LAYER) { + LTDC_LayerAlpha(LTDC_Layer1, transparency); + } + else { + LTDC_LayerAlpha(LTDC_Layer2, transparency); + } + LTDC_ReloadConfig(LTDC_IMReload); +} + +void lcdInit(void) +{ + /* Initialize the LCD */ + LCD_Init(); + LCD_LayerInit(); + + /* Enable LCD display */ + LTDC_Cmd(ENABLE); + + /* Set Background layer */ + LCD_SetLayer(LCD_FIRST_LAYER); + // lcdClear(); + LCD_SetTransparency(0); + + /* Set Foreground layer */ + LCD_SetLayer(LCD_SECOND_LAYER); + lcd->clear(); + LCD_SetTransparency(255); +} + +void DMAFillRect(uint16_t * dest, uint16_t destw, uint16_t desth, uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t color) +{ +#if defined(PCBX10) + x = destw - (x + w); + y = desth - (y + h); +#endif + + DMA2D_DeInit(); + + DMA2D_InitTypeDef DMA2D_InitStruct; + DMA2D_InitStruct.DMA2D_Mode = DMA2D_R2M; + DMA2D_InitStruct.DMA2D_CMode = DMA2D_RGB565; + DMA2D_InitStruct.DMA2D_OutputGreen = (0x07E0 & color) >> 5; + DMA2D_InitStruct.DMA2D_OutputBlue = 0x001F & color; + DMA2D_InitStruct.DMA2D_OutputRed = (0xF800 & color) >> 11; + DMA2D_InitStruct.DMA2D_OutputAlpha = 0x0F; + DMA2D_InitStruct.DMA2D_OutputMemoryAdd = CONVERT_PTR_UINT(dest) + 2*(destw*y + x); + DMA2D_InitStruct.DMA2D_OutputOffset = (destw - w); + DMA2D_InitStruct.DMA2D_NumberOfLine = h; + DMA2D_InitStruct.DMA2D_PixelPerLine = w; + DMA2D_Init(&DMA2D_InitStruct); + + /* Start Transfer */ + DMA2D_StartTransfer(); + + /* Wait for CTC Flag activation */ + while (DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET); +} + +void DMACopyBitmap(uint16_t * dest, uint16_t destw, uint16_t desth, uint16_t x, uint16_t y, const uint16_t * src, uint16_t srcw, uint16_t srch, uint16_t srcx, uint16_t srcy, uint16_t w, uint16_t h) +{ +#if defined(PCBX10) + x = destw - (x + w); + y = desth - (y + h); + srcx = srcw - (srcx + w); + srcy = srch - (srcy + h); +#endif + + DMA2D_DeInit(); + + DMA2D_InitTypeDef DMA2D_InitStruct; + DMA2D_InitStruct.DMA2D_Mode = DMA2D_M2M; + DMA2D_InitStruct.DMA2D_CMode = DMA2D_RGB565; + DMA2D_InitStruct.DMA2D_OutputMemoryAdd = CONVERT_PTR_UINT(dest + y*destw + x); + DMA2D_InitStruct.DMA2D_OutputGreen = 0; + DMA2D_InitStruct.DMA2D_OutputBlue = 0; + DMA2D_InitStruct.DMA2D_OutputRed = 0; + DMA2D_InitStruct.DMA2D_OutputAlpha = 0; + DMA2D_InitStruct.DMA2D_OutputOffset = destw - w; + DMA2D_InitStruct.DMA2D_NumberOfLine = h; + DMA2D_InitStruct.DMA2D_PixelPerLine = w; + DMA2D_Init(&DMA2D_InitStruct); + + DMA2D_FG_InitTypeDef DMA2D_FG_InitStruct; + DMA2D_FG_StructInit(&DMA2D_FG_InitStruct); + DMA2D_FG_InitStruct.DMA2D_FGMA = CONVERT_PTR_UINT(src + srcy*srcw + srcx); + DMA2D_FG_InitStruct.DMA2D_FGO = srcw - w; + DMA2D_FG_InitStruct.DMA2D_FGCM = CM_RGB565; + DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; + DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_VALUE = 0; + DMA2D_FGConfig(&DMA2D_FG_InitStruct); + + /* Start Transfer */ + DMA2D_StartTransfer(); + + /* Wait for CTC Flag activation */ + while (DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET); +} + +void DMACopyAlphaBitmap(uint16_t * dest, uint16_t destw, uint16_t desth, uint16_t x, uint16_t y, const uint16_t * src, uint16_t srcw, uint16_t srch, uint16_t srcx, uint16_t srcy, uint16_t w, uint16_t h) +{ +#if defined(PCBX10) + x = destw - (x + w); + y = desth - (y + h); + srcx = srcw - (srcx + w); + srcy = srch - (srcy + h); +#endif + + DMA2D_DeInit(); + + DMA2D_InitTypeDef DMA2D_InitStruct; + DMA2D_InitStruct.DMA2D_Mode = DMA2D_M2M_BLEND; + DMA2D_InitStruct.DMA2D_CMode = DMA2D_RGB565; + DMA2D_InitStruct.DMA2D_OutputMemoryAdd = CONVERT_PTR_UINT(dest + y*destw + x); + DMA2D_InitStruct.DMA2D_OutputGreen = 0; + DMA2D_InitStruct.DMA2D_OutputBlue = 0; + DMA2D_InitStruct.DMA2D_OutputRed = 0; + DMA2D_InitStruct.DMA2D_OutputAlpha = 0; + DMA2D_InitStruct.DMA2D_OutputOffset = destw - w; + DMA2D_InitStruct.DMA2D_NumberOfLine = h; + DMA2D_InitStruct.DMA2D_PixelPerLine = w; + DMA2D_Init(&DMA2D_InitStruct); + + DMA2D_FG_InitTypeDef DMA2D_FG_InitStruct; + DMA2D_FG_StructInit(&DMA2D_FG_InitStruct); + DMA2D_FG_InitStruct.DMA2D_FGMA = CONVERT_PTR_UINT(src + srcy*srcw + srcx); + DMA2D_FG_InitStruct.DMA2D_FGO = srcw - w; + DMA2D_FG_InitStruct.DMA2D_FGCM = CM_ARGB4444; + DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; + DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_VALUE = 0; + DMA2D_FGConfig(&DMA2D_FG_InitStruct); + + DMA2D_BG_InitTypeDef DMA2D_BG_InitStruct; + DMA2D_BG_StructInit(&DMA2D_BG_InitStruct); + DMA2D_BG_InitStruct.DMA2D_BGMA = CONVERT_PTR_UINT(dest + y*destw + x); + DMA2D_BG_InitStruct.DMA2D_BGO = destw - w; + DMA2D_BG_InitStruct.DMA2D_BGCM = CM_RGB565; + DMA2D_BG_InitStruct.DMA2D_BGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; + DMA2D_BG_InitStruct.DMA2D_BGPFC_ALPHA_VALUE = 0; + DMA2D_BGConfig(&DMA2D_BG_InitStruct); + + /* Start Transfer */ + DMA2D_StartTransfer(); + + /* Wait for CTC Flag activation */ + while (DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET); +} + +void DMABitmapConvert(uint16_t * dest, const uint8_t * src, uint16_t w, uint16_t h, uint32_t format) +{ + DMA2D_DeInit(); + + DMA2D_InitTypeDef DMA2D_InitStruct; + DMA2D_InitStruct.DMA2D_Mode = DMA2D_M2M_PFC; + DMA2D_InitStruct.DMA2D_CMode = format; + DMA2D_InitStruct.DMA2D_OutputMemoryAdd = CONVERT_PTR_UINT(dest); + DMA2D_InitStruct.DMA2D_OutputGreen = 0; + DMA2D_InitStruct.DMA2D_OutputBlue = 0; + DMA2D_InitStruct.DMA2D_OutputRed = 0; + DMA2D_InitStruct.DMA2D_OutputAlpha = 0; + DMA2D_InitStruct.DMA2D_OutputOffset = 0; + DMA2D_InitStruct.DMA2D_NumberOfLine = h; + DMA2D_InitStruct.DMA2D_PixelPerLine = w; + DMA2D_Init(&DMA2D_InitStruct); + + DMA2D_FG_InitTypeDef DMA2D_FG_InitStruct; + DMA2D_FG_StructInit(&DMA2D_FG_InitStruct); + DMA2D_FG_InitStruct.DMA2D_FGMA = CONVERT_PTR_UINT(src); + DMA2D_FG_InitStruct.DMA2D_FGO = 0; + DMA2D_FG_InitStruct.DMA2D_FGCM = CM_ARGB8888; + DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_MODE = REPLACE_ALPHA_VALUE; + DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_VALUE = 0; + DMA2D_FGConfig(&DMA2D_FG_InitStruct); + + /* Start Transfer */ + DMA2D_StartTransfer(); + + /* Wait for CTC Flag activation */ + while (DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET); +} + +void DMAcopy(void * src, void * dest, int len) +{ + DMA2D_DeInit(); + + DMA2D_InitTypeDef DMA2D_InitStruct; + DMA2D_InitStruct.DMA2D_Mode = DMA2D_M2M; + DMA2D_InitStruct.DMA2D_CMode = DMA2D_RGB565; + DMA2D_InitStruct.DMA2D_OutputMemoryAdd = CONVERT_PTR_UINT(dest); + DMA2D_InitStruct.DMA2D_OutputGreen = 0; + DMA2D_InitStruct.DMA2D_OutputBlue = 0; + DMA2D_InitStruct.DMA2D_OutputRed = 0; + DMA2D_InitStruct.DMA2D_OutputAlpha = 0; + DMA2D_InitStruct.DMA2D_OutputOffset = 0; + DMA2D_InitStruct.DMA2D_NumberOfLine = LCD_H; + DMA2D_InitStruct.DMA2D_PixelPerLine = LCD_W; + DMA2D_Init(&DMA2D_InitStruct); + + DMA2D_FG_InitTypeDef DMA2D_FG_InitStruct; + DMA2D_FG_StructInit(&DMA2D_FG_InitStruct); + DMA2D_FG_InitStruct.DMA2D_FGMA = CONVERT_PTR_UINT(src); + DMA2D_FG_InitStruct.DMA2D_FGO = 0; + DMA2D_FG_InitStruct.DMA2D_FGCM = CM_RGB565; + DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; + DMA2D_FG_InitStruct.DMA2D_FGPFC_ALPHA_VALUE = 0; + DMA2D_FGConfig(&DMA2D_FG_InitStruct); + + /* Start Transfer */ + DMA2D_StartTransfer(); + + /* Wait for CTC Flag activation */ + while (DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET); +} + +void lcdStoreBackupBuffer() +{ + DMAcopy(lcd->getData(), LCD_BACKUP_FRAME_BUFFER, DISPLAY_BUFFER_SIZE); +} + +int lcdRestoreBackupBuffer() +{ + DMAcopy(LCD_BACKUP_FRAME_BUFFER, lcd->getData(), DISPLAY_BUFFER_SIZE); + return 1; +} + +void lcdRefresh() +{ + LCD_SetTransparency(255); + if (CurrentLayer == LCD_FIRST_LAYER) + LCD_SetLayer(LCD_SECOND_LAYER); + else + LCD_SetLayer(LCD_FIRST_LAYER); + LCD_SetTransparency(0); +} diff --git a/radio/src/targets/horus/pulses_driver.cpp b/radio/src/targets/horus/pulses_driver.cpp index ae198fbd0..784e060ce 100644 --- a/radio/src/targets/horus/pulses_driver.cpp +++ b/radio/src/targets/horus/pulses_driver.cpp @@ -1,270 +1,270 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void intmoduleStop(void); -void extmoduleStop(void); - -void intmoduleNoneStart(void); -void intmodulePxxStart(void); - -void extmoduleNoneStart(void); -void extmodulePpmStart(void); -void extmodulePxxStart(void); -#if defined(DSM2) -void extmoduleDsm2Start(void); -#endif -void extmoduleCrossfireStart(void); - -void init_no_pulses(uint32_t port) -{ - if (port == INTERNAL_MODULE) - intmoduleNoneStart(); - else - extmoduleNoneStart(); -} - -void disable_no_pulses(uint32_t port) -{ - if (port == INTERNAL_MODULE) - intmoduleStop(); - else - extmoduleStop(); -} - -void init_ppm(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmodulePpmStart(); - } -} - -void disable_ppm(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmoduleStop(); - } -} - -void init_pxx(uint32_t port) -{ - if (port == INTERNAL_MODULE) - intmodulePxxStart(); - else - extmodulePxxStart(); -} - -void disable_pxx(uint32_t port) -{ - if (port == INTERNAL_MODULE) - intmoduleStop(); - else - extmoduleStop(); -} - -#if defined(DSM2) -void init_dsm2(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmoduleDsm2Start(); - } -} - -void disable_dsm2(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmoduleStop(); - } -} -#endif - -#if defined(MULTIMODULE) -void init_multimodule(uint32_t port) -{ - init_dsm2(port); -} - -void disable_multimodule(uint32_t port) -{ - disable_dsm2(port); -} -#endif - -void init_crossfire(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmoduleCrossfireStart(); - } -} - -void disable_crossfire(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmoduleStop(); - } -} - -void intmoduleStop() -{ - INTERNAL_MODULE_OFF(); - - NVIC_DisableIRQ(INTMODULE_TIMER_IRQn); - - INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; - INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; -} - -void intmoduleNoneStart() -{ - INTERNAL_MODULE_OFF(); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = INTMODULE_TX_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(INTMODULE_TX_GPIO, &GPIO_InitStructure); - GPIO_SetBits(INTMODULE_TX_GPIO, INTMODULE_TX_GPIO_PIN); // Set high - - INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - INTMODULE_TIMER->ARR = 36000; // 18mS - INTMODULE_TIMER->CCR2 = 32000; // Update time - INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) - - INTMODULE_TIMER->CCER = TIM_CCER_CC3E; - - INTMODULE_TIMER->CCMR2 = 0; - INTMODULE_TIMER->EGR = 1; // Restart - - INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p - INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag - INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt - INTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - NVIC_EnableIRQ(INTMODULE_TIMER_IRQn); - NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7); -} - -void intmodulePxxStart() -{ - NVIC_InitTypeDef NVIC_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - INTERNAL_MODULE_ON(); - - NVIC_InitStructure.NVIC_IRQChannel = INTMODULE_DMA_STREAM_IRQ; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pre-emption priority. */; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - // TX Pin - GPIO_PinAFConfig(INTMODULE_TX_GPIO, INTMODULE_TX_GPIO_PinSource, INTMODULE_GPIO_AF); - GPIO_InitStructure.GPIO_Pin = INTMODULE_TX_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(INTMODULE_TX_GPIO, &GPIO_InitStructure); - - // RX Pin - GPIO_PinAFConfig(INTMODULE_RX_GPIO, INTMODULE_RX_GPIO_PinSource, INTMODULE_GPIO_AF); - GPIO_InitStructure.GPIO_Pin = INTMODULE_RX_GPIO_PIN; - GPIO_Init(INTMODULE_RX_GPIO, &GPIO_InitStructure); - - // UART config - USART_DeInit(INTMODULE_USART); - USART_InitTypeDef USART_InitStructure; - USART_InitStructure.USART_BaudRate = 115200; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(INTMODULE_USART, &USART_InitStructure); - USART_Cmd(INTMODULE_USART, ENABLE); - - // Timer - INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - INTMODULE_TIMER->ARR = 18000; // 9mS - INTMODULE_TIMER->CCR2 = 15000; // Update time - INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) - INTMODULE_TIMER->CCER = TIM_CCER_CC3E; - INTMODULE_TIMER->CCMR2 = 0; - INTMODULE_TIMER->EGR = 1; // Restart - - INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p - INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag - INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt - INTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - - NVIC_EnableIRQ(INTMODULE_TIMER_IRQn); - NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7); -} - -extern "C" void INTMODULE_DMA_STREAM_IRQHandler(void) -{ - DEBUG_INTERRUPT(INT_DMA2S7); - if (DMA_GetITStatus(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC)) { - // TODO we could send the 8 next channels here (when needed) - DMA_ClearITPendingBit(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC); - } -} - -void intmoduleSendNextFrame() -{ - if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) { - DMA_InitTypeDef DMA_InitStructure; - DMA_DeInit(INTMODULE_DMA_STREAM); - DMA_InitStructure.DMA_Channel = INTMODULE_DMA_CHANNEL; - DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&INTMODULE_USART->DR); - DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; - DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(modulePulsesData[INTERNAL_MODULE].pxx_uart.pulses); - DMA_InitStructure.DMA_BufferSize = modulePulsesData[INTERNAL_MODULE].pxx_uart.ptr - modulePulsesData[INTERNAL_MODULE].pxx_uart.pulses; - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - DMA_Init(INTMODULE_DMA_STREAM, &DMA_InitStructure); - - DMA_Cmd(INTMODULE_DMA_STREAM, ENABLE); - USART_DMACmd(INTMODULE_USART, USART_DMAReq_Tx, ENABLE); - } -} - -extern "C" void INTMODULE_TIMER_IRQHandler() -{ - DEBUG_INTERRUPT(INT_TIM1CC); - DEBUG_TIMER_SAMPLE(debugTimerIntPulses); - DEBUG_TIMER_START(debugTimerIntPulsesDuration); - - INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag - setupPulses(INTERNAL_MODULE); - intmoduleSendNextFrame(); - - DEBUG_TIMER_STOP(debugTimerIntPulsesDuration); -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +void intmoduleStop(void); +void extmoduleStop(void); + +void intmoduleNoneStart(void); +void intmodulePxxStart(void); + +void extmoduleNoneStart(void); +void extmodulePpmStart(void); +void extmodulePxxStart(void); +#if defined(DSM2) +void extmoduleDsm2Start(void); +#endif +void extmoduleCrossfireStart(void); + +void init_no_pulses(uint32_t port) +{ + if (port == INTERNAL_MODULE) + intmoduleNoneStart(); + else + extmoduleNoneStart(); +} + +void disable_no_pulses(uint32_t port) +{ + if (port == INTERNAL_MODULE) + intmoduleStop(); + else + extmoduleStop(); +} + +void init_ppm(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmodulePpmStart(); + } +} + +void disable_ppm(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmoduleStop(); + } +} + +void init_pxx(uint32_t port) +{ + if (port == INTERNAL_MODULE) + intmodulePxxStart(); + else + extmodulePxxStart(); +} + +void disable_pxx(uint32_t port) +{ + if (port == INTERNAL_MODULE) + intmoduleStop(); + else + extmoduleStop(); +} + +#if defined(DSM2) +void init_dsm2(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmoduleDsm2Start(); + } +} + +void disable_dsm2(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmoduleStop(); + } +} +#endif + +#if defined(MULTIMODULE) +void init_multimodule(uint32_t port) +{ + init_dsm2(port); +} + +void disable_multimodule(uint32_t port) +{ + disable_dsm2(port); +} +#endif + +void init_crossfire(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmoduleCrossfireStart(); + } +} + +void disable_crossfire(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmoduleStop(); + } +} + +void intmoduleStop() +{ + INTERNAL_MODULE_OFF(); + + NVIC_DisableIRQ(INTMODULE_TIMER_IRQn); + + INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; + INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; +} + +void intmoduleNoneStart() +{ + INTERNAL_MODULE_OFF(); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = INTMODULE_TX_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(INTMODULE_TX_GPIO, &GPIO_InitStructure); + GPIO_SetBits(INTMODULE_TX_GPIO, INTMODULE_TX_GPIO_PIN); // Set high + + INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + INTMODULE_TIMER->ARR = 36000; // 18mS + INTMODULE_TIMER->CCR2 = 32000; // Update time + INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) + + INTMODULE_TIMER->CCER = TIM_CCER_CC3E; + + INTMODULE_TIMER->CCMR2 = 0; + INTMODULE_TIMER->EGR = 1; // Restart + + INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p + INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag + INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt + INTMODULE_TIMER->CR1 |= TIM_CR1_CEN; + NVIC_EnableIRQ(INTMODULE_TIMER_IRQn); + NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7); +} + +void intmodulePxxStart() +{ + NVIC_InitTypeDef NVIC_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + INTERNAL_MODULE_ON(); + + NVIC_InitStructure.NVIC_IRQChannel = INTMODULE_DMA_STREAM_IRQ; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pre-emption priority. */; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + // TX Pin + GPIO_PinAFConfig(INTMODULE_TX_GPIO, INTMODULE_TX_GPIO_PinSource, INTMODULE_GPIO_AF); + GPIO_InitStructure.GPIO_Pin = INTMODULE_TX_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(INTMODULE_TX_GPIO, &GPIO_InitStructure); + + // RX Pin + GPIO_PinAFConfig(INTMODULE_RX_GPIO, INTMODULE_RX_GPIO_PinSource, INTMODULE_GPIO_AF); + GPIO_InitStructure.GPIO_Pin = INTMODULE_RX_GPIO_PIN; + GPIO_Init(INTMODULE_RX_GPIO, &GPIO_InitStructure); + + // UART config + USART_DeInit(INTMODULE_USART); + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(INTMODULE_USART, &USART_InitStructure); + USART_Cmd(INTMODULE_USART, ENABLE); + + // Timer + INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + INTMODULE_TIMER->ARR = 18000; // 9mS + INTMODULE_TIMER->CCR2 = 15000; // Update time + INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) + INTMODULE_TIMER->CCER = TIM_CCER_CC3E; + INTMODULE_TIMER->CCMR2 = 0; + INTMODULE_TIMER->EGR = 1; // Restart + + INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p + INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag + INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt + INTMODULE_TIMER->CR1 |= TIM_CR1_CEN; + + NVIC_EnableIRQ(INTMODULE_TIMER_IRQn); + NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7); +} + +extern "C" void INTMODULE_DMA_STREAM_IRQHandler(void) +{ + DEBUG_INTERRUPT(INT_DMA2S7); + if (DMA_GetITStatus(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC)) { + // TODO we could send the 8 next channels here (when needed) + DMA_ClearITPendingBit(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC); + } +} + +void intmoduleSendNextFrame() +{ + if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) { + DMA_InitTypeDef DMA_InitStructure; + DMA_DeInit(INTMODULE_DMA_STREAM); + DMA_InitStructure.DMA_Channel = INTMODULE_DMA_CHANNEL; + DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&INTMODULE_USART->DR); + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(modulePulsesData[INTERNAL_MODULE].pxx_uart.pulses); + DMA_InitStructure.DMA_BufferSize = modulePulsesData[INTERNAL_MODULE].pxx_uart.ptr - modulePulsesData[INTERNAL_MODULE].pxx_uart.pulses; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(INTMODULE_DMA_STREAM, &DMA_InitStructure); + + DMA_Cmd(INTMODULE_DMA_STREAM, ENABLE); + USART_DMACmd(INTMODULE_USART, USART_DMAReq_Tx, ENABLE); + } +} + +extern "C" void INTMODULE_TIMER_IRQHandler() +{ + DEBUG_INTERRUPT(INT_TIM1CC); + DEBUG_TIMER_SAMPLE(debugTimerIntPulses); + DEBUG_TIMER_START(debugTimerIntPulsesDuration); + + INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag + setupPulses(INTERNAL_MODULE); + intmoduleSendNextFrame(); + + DEBUG_TIMER_STOP(debugTimerIntPulsesDuration); +} diff --git a/radio/src/targets/horus/pwr_driver.cpp b/radio/src/targets/horus/pwr_driver.cpp index 9b366a924..65e60199c 100644 --- a/radio/src/targets/horus/pwr_driver.cpp +++ b/radio/src/targets/horus/pwr_driver.cpp @@ -1,150 +1,150 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "pwr.h" -#include "board.h" - -uint32_t shutdownRequest; // Stores intentional shutdown to avoid reboot loop -uint32_t shutdownReason; // Used for detecting unexpected reboots regardless of reason -uint32_t powerupReason __NOINIT; // Stores power up reason beyond initialization for emergency mode activation - -void pwrInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = PWR_ON_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(PWR_GPIO, &GPIO_InitStructure); - - // Init Module PWR - GPIO_ResetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN); - GPIO_InitStructure.GPIO_Pin = INTMODULE_PWR_GPIO_PIN; - GPIO_Init(INTMODULE_PWR_GPIO, &GPIO_InitStructure); - - GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN); - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PWR_GPIO_PIN; - GPIO_Init(EXTMODULE_PWR_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - - // Init PWR SWITCH PIN - GPIO_InitStructure.GPIO_Pin = PWR_SWITCH_GPIO_PIN; - GPIO_Init(PWR_GPIO, &GPIO_InitStructure); - - // Init PCBREV PIN - // TODO to be removed on X10? - GPIO_ResetBits(PCBREV_GPIO, PCBREV_GPIO_PIN); - GPIO_InitStructure.GPIO_Pin = PCBREV_GPIO_PIN; - GPIO_Init(PCBREV_GPIO, &GPIO_InitStructure); - - // Init SD-DETECT PIN - GPIO_ResetBits(SD_PRESENT_GPIO, SD_PRESENT_GPIO_PIN); - GPIO_InitStructure.GPIO_Pin = SD_PRESENT_GPIO_PIN; - GPIO_Init(SD_PRESENT_GPIO, &GPIO_InitStructure); - - // Init TRAINER DETECT PIN - GPIO_InitStructure.GPIO_Pin = TRAINER_DETECT_GPIO_PIN; - GPIO_Init(TRAINER_DETECT_GPIO, &GPIO_InitStructure); - - pwrOn(); -} - -void pwrOn() -{ - GPIO_SetBits(PWR_GPIO, PWR_ON_GPIO_PIN); - shutdownRequest = NO_SHUTDOWN_REQUEST; - shutdownReason = DIRTY_SHUTDOWN; -} - -void pwrOff() -{ -#if defined(PCBX12S) - // Shutdown the Audio amp - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = AUDIO_SHUTDOWN_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(AUDIO_SHUTDOWN_GPIO, &GPIO_InitStructure); - GPIO_ResetBits(AUDIO_SHUTDOWN_GPIO, AUDIO_SHUTDOWN_GPIO_PIN); -#endif - - // Shutdown the Haptic - hapticDone(); - - shutdownRequest = SHUTDOWN_REQUEST; - shutdownReason = NORMAL_POWER_OFF; - GPIO_ResetBits(PWR_GPIO, PWR_ON_GPIO_PIN); -} - -uint32_t pwrPressed() -{ - return GPIO_ReadInputDataBit(PWR_GPIO, PWR_SWITCH_GPIO_PIN) == Bit_RESET; -} - -void pwrResetHandler() -{ - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOJEN; - - // these two NOPs are needed (see STM32F errata sheet) before the peripheral - // register can be written after the peripheral clock was enabled - __ASM volatile ("nop"); - __ASM volatile ("nop"); - - // We get here whether we are powering up normally, we had an unexpected reboot or we have just powered down normally. - // We want: - // - In the 2nd case, to power ON as soon as possible if an unexpected reboot happened - // (we get there running on remaining capacitor charge, soft power having been cut by the RESET). - // - In the 3rd case, NOT power on as that would prevent from turning the system off. - // - The 1st case does not need to be handled here, but will be as a result of the handling for the 3rd case, see below. - // - // shutdownRequest is used to handle the 3rd case. If we really powered down on purpose this will still be set to SHUTDOWN_REQUEST - // as we left it in pwrOff(). If however we had an unexpected reboot, it would be set to NO_SHUTDOWN_REQUEST as we set it in pwrOn(). - // Any other value (e.g. resulting from data corruption) would also keep power on for safety, so this variable can NOT be used - // to detect an unexpected reboot (on a normal power on the contents of the variable are random). - // - // shutdownReason is used to differentiate between an unexpected reboot and a normal power on. We set it to DIRTY_SHUTDOWN in pwrOn() - // in anticipation of a potential reboot. Should there be one the value should be preserved and signal below that we rebooted unexpectedly. - // If it is NOT set to DIRTY_SHUTDOWN we likely had a normal boot and its contents are random. Due to the need to initialize it to detect a - // potential failure ASAP we cannot use it to determine in the firmware why we got there, it has to be buffered. - // - // powerupReason is there to cater for that, and is what is used in the firmware to decide whether we have to enter emergency mode. - // This variable needs to be in a RAM section that is not initialized or zeroed, since once we exit this pwrResetHandler() function the - // C runtime would otherwise overwrite it during program init. - - if (shutdownRequest != SHUTDOWN_REQUEST) { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = PWR_ON_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(PWR_GPIO, &GPIO_InitStructure); - - if (shutdownReason == DIRTY_SHUTDOWN) { - powerupReason = DIRTY_SHUTDOWN; - } - - pwrOn(); - } -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "pwr.h" +#include "board.h" + +uint32_t shutdownRequest; // Stores intentional shutdown to avoid reboot loop +uint32_t shutdownReason; // Used for detecting unexpected reboots regardless of reason +uint32_t powerupReason __NOINIT; // Stores power up reason beyond initialization for emergency mode activation + +void pwrInit() +{ + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = PWR_ON_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(PWR_GPIO, &GPIO_InitStructure); + + // Init Module PWR + GPIO_ResetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN); + GPIO_InitStructure.GPIO_Pin = INTMODULE_PWR_GPIO_PIN; + GPIO_Init(INTMODULE_PWR_GPIO, &GPIO_InitStructure); + + GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN); + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PWR_GPIO_PIN; + GPIO_Init(EXTMODULE_PWR_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + + // Init PWR SWITCH PIN + GPIO_InitStructure.GPIO_Pin = PWR_SWITCH_GPIO_PIN; + GPIO_Init(PWR_GPIO, &GPIO_InitStructure); + + // Init PCBREV PIN + // TODO to be removed on X10? + GPIO_ResetBits(PCBREV_GPIO, PCBREV_GPIO_PIN); + GPIO_InitStructure.GPIO_Pin = PCBREV_GPIO_PIN; + GPIO_Init(PCBREV_GPIO, &GPIO_InitStructure); + + // Init SD-DETECT PIN + GPIO_ResetBits(SD_PRESENT_GPIO, SD_PRESENT_GPIO_PIN); + GPIO_InitStructure.GPIO_Pin = SD_PRESENT_GPIO_PIN; + GPIO_Init(SD_PRESENT_GPIO, &GPIO_InitStructure); + + // Init TRAINER DETECT PIN + GPIO_InitStructure.GPIO_Pin = TRAINER_DETECT_GPIO_PIN; + GPIO_Init(TRAINER_DETECT_GPIO, &GPIO_InitStructure); + + pwrOn(); +} + +void pwrOn() +{ + GPIO_SetBits(PWR_GPIO, PWR_ON_GPIO_PIN); + shutdownRequest = NO_SHUTDOWN_REQUEST; + shutdownReason = DIRTY_SHUTDOWN; +} + +void pwrOff() +{ +#if defined(PCBX12S) + // Shutdown the Audio amp + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = AUDIO_SHUTDOWN_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(AUDIO_SHUTDOWN_GPIO, &GPIO_InitStructure); + GPIO_ResetBits(AUDIO_SHUTDOWN_GPIO, AUDIO_SHUTDOWN_GPIO_PIN); +#endif + + // Shutdown the Haptic + hapticDone(); + + shutdownRequest = SHUTDOWN_REQUEST; + shutdownReason = NORMAL_POWER_OFF; + GPIO_ResetBits(PWR_GPIO, PWR_ON_GPIO_PIN); +} + +uint32_t pwrPressed() +{ + return GPIO_ReadInputDataBit(PWR_GPIO, PWR_SWITCH_GPIO_PIN) == Bit_RESET; +} + +void pwrResetHandler() +{ + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOJEN; + + // these two NOPs are needed (see STM32F errata sheet) before the peripheral + // register can be written after the peripheral clock was enabled + __ASM volatile ("nop"); + __ASM volatile ("nop"); + + // We get here whether we are powering up normally, we had an unexpected reboot or we have just powered down normally. + // We want: + // - In the 2nd case, to power ON as soon as possible if an unexpected reboot happened + // (we get there running on remaining capacitor charge, soft power having been cut by the RESET). + // - In the 3rd case, NOT power on as that would prevent from turning the system off. + // - The 1st case does not need to be handled here, but will be as a result of the handling for the 3rd case, see below. + // + // shutdownRequest is used to handle the 3rd case. If we really powered down on purpose this will still be set to SHUTDOWN_REQUEST + // as we left it in pwrOff(). If however we had an unexpected reboot, it would be set to NO_SHUTDOWN_REQUEST as we set it in pwrOn(). + // Any other value (e.g. resulting from data corruption) would also keep power on for safety, so this variable can NOT be used + // to detect an unexpected reboot (on a normal power on the contents of the variable are random). + // + // shutdownReason is used to differentiate between an unexpected reboot and a normal power on. We set it to DIRTY_SHUTDOWN in pwrOn() + // in anticipation of a potential reboot. Should there be one the value should be preserved and signal below that we rebooted unexpectedly. + // If it is NOT set to DIRTY_SHUTDOWN we likely had a normal boot and its contents are random. Due to the need to initialize it to detect a + // potential failure ASAP we cannot use it to determine in the firmware why we got there, it has to be buffered. + // + // powerupReason is there to cater for that, and is what is used in the firmware to decide whether we have to enter emergency mode. + // This variable needs to be in a RAM section that is not initialized or zeroed, since once we exit this pwrResetHandler() function the + // C runtime would otherwise overwrite it during program init. + + if (shutdownRequest != SHUTDOWN_REQUEST) { + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = PWR_ON_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(PWR_GPIO, &GPIO_InitStructure); + + if (shutdownReason == DIRTY_SHUTDOWN) { + powerupReason = DIRTY_SHUTDOWN; + } + + pwrOn(); + } +} diff --git a/radio/src/targets/horus/sdio_sd.c b/radio/src/targets/horus/sdio_sd.c index 9ff678d5d..e66d29d4e 100644 --- a/radio/src/targets/horus/sdio_sd.c +++ b/radio/src/targets/horus/sdio_sd.c @@ -1,2767 +1,2767 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "sdio_sd.h" -#include "../../debug.h" - -/** - * @brief SDIO Static flags, TimeOut, FIFO Address - */ -#define SDIO_STATIC_FLAGS ((uint32_t)0x000005FF) -#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000) - -/** - * @brief Mask for errors Card Status R1 (OCR Register) - */ -#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) -#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000) -#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000) -#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000) -#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000) -#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) -#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) -#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000) -#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000) -#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000) -#define SD_OCR_CC_ERROR ((uint32_t)0x00100000) -#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) -#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) -#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) -#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000) -#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000) -#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000) -#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000) -#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008) -#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008) - -/** - * @brief Masks for R6 Response - */ -#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000) -#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000) -#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000) - -#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000) -#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) -#define SD_STD_CAPACITY ((uint32_t)0x00000000) -#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) - -#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) -#define SD_ALLZERO ((uint32_t)0x00000000) - -#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) -#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) -#define SD_CARD_LOCKED ((uint32_t)0x02000000) - -#define SD_DATATIMEOUT ((uint32_t)1000000) -#define SD_0TO7BITS ((uint32_t)0x000000FF) -#define SD_8TO15BITS ((uint32_t)0x0000FF00) -#define SD_16TO23BITS ((uint32_t)0x00FF0000) -#define SD_24TO31BITS ((uint32_t)0xFF000000) -#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) - -#define SD_HALFFIFO ((uint32_t)0x00000008) -#define SD_HALFFIFOBYTES ((uint32_t)0x00000020) - -/** - * @brief Command Class Supported - */ -#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080) -#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040) -#define SD_CCCC_ERASE ((uint32_t)0x00000020) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SDIO_SEND_IF_COND ((uint32_t)0x00000008) - - -/** - * @brief SDIO Commands Index - */ -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) -#define SD_CMD_SEND_OP_COND ((uint8_t)1) -#define SD_CMD_ALL_SEND_CID ((uint8_t)2) -#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */ -#define SD_CMD_SET_DSR ((uint8_t)4) -#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) -#define SD_CMD_HS_SWITCH ((uint8_t)6) -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) -#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) -#define SD_CMD_SEND_CSD ((uint8_t)9) -#define SD_CMD_SEND_CID ((uint8_t)10) -#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD Card doesn't support it */ -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) -#define SD_CMD_SEND_STATUS ((uint8_t)13) -#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) -#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) -#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) -#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< SD Card doesn't support it */ -#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< SD Card doesn't support it */ -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) -#define SD_CMD_PROG_CID ((uint8_t)26) /*!< reserved for manufacturers */ -#define SD_CMD_PROG_CSD ((uint8_t)27) -#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) -#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) -#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) -#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< To set the address of the first write - block to be erased. (For SD card only) */ -#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< To set the address of the last write block of the - continuous range to be erased. (For SD card only) */ -#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< To set the address of the first write block to be erased. - (For MMC card only spec 3.31) */ - -#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< To set the address of the last write block of the - continuous range to be erased. (For MMC card only spec 3.31) */ - -#define SD_CMD_ERASE ((uint8_t)38) -#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD Card doesn't support it */ -#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD Card doesn't support it */ -#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) -#define SD_CMD_APP_CMD ((uint8_t)55) -#define SD_CMD_GEN_CMD ((uint8_t)56) -#define SD_CMD_NO_CMD ((uint8_t)64) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< For SD Card only */ -#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< For SD Card only */ -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< For SD Card only */ -#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O Card only */ -#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O Card only */ - -/** - * @brief Following commands are SD Card Specific security commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD Card only */ -#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD Card only */ - -/** - * @brief Supported SD Memory Cards - */ -#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) -#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) -#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) -#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) -#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) -#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) -#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) -#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) - - -/** - * @brief SD Card States - */ -typedef enum -{ - SD_CARD_READY = ((uint32_t)0x00000001), - SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), - SD_CARD_STANDBY = ((uint32_t)0x00000003), - SD_CARD_TRANSFER = ((uint32_t)0x00000004), - SD_CARD_SENDING = ((uint32_t)0x00000005), - SD_CARD_RECEIVING = ((uint32_t)0x00000006), - SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), - SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), - SD_CARD_ERROR = ((uint32_t)0x000000FF) -}SDCardState; - - - -static uint32_t CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; -static uint32_t CSD_Tab[4], CID_Tab[4], RCA = 0; -// static uint8_t SDSTATUS_Tab[16]; -__IO uint8_t StopCondition = 0; -__IO SD_Error TransferError = SD_OK; -__IO uint8_t TransferEnd = 0, DMAEndOfTransfer = 0; -SD_CardInfo SDCardInfo; - -SDIO_InitTypeDef SDIO_InitStructure; -SDIO_CmdInitTypeDef SDIO_CmdInitStructure; -SDIO_DataInitTypeDef SDIO_DataInitStructure; - -static SD_Error CmdError(void); -static SD_Error CmdResp1Error(uint8_t cmd); -static SD_Error CmdResp7Error(void); -static SD_Error CmdResp3Error(void); -static SD_Error CmdResp2Error(void); -static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca); -static SD_Error SDEnWideBus(FunctionalState NewState); -// static SD_Error IsCardProgramming(uint8_t *pstatus); -static SD_Error FindSCR(uint16_t rca, uint32_t *pscr); -// uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes); - -SD_Error SD_PowerON(void); -SDCardState SD_GetState(void); -SD_Error SD_InitializeCards(void); -SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo); -SD_Error SD_EnableWideBusOperation(uint32_t WideMode); -SD_Error SD_SelectDeselect(uint32_t addr); -SD_Error SD_StopTransfer(void); -SD_Error SD_SendStatus(uint32_t *pcardstatus); - - - - - - - - - - - - - - - -/** - * @brief DeInitializes the SDIO interface. - * @param None - * @retval None - */ -// void SD_LowLevel_DeInit(void) -// { -// GPIO_InitTypeDef GPIO_InitStructure; - -// /*!< Disable SDIO Clock */ -// SDIO_ClockCmd(DISABLE); - -// /*!< Set Power State to OFF */ -// SDIO_SetPowerState(SDIO_PowerState_OFF); - -// /*!< DeInitializes the SDIO peripheral */ -// SDIO_DeInit(); - -// /* Disable the SDIO APB2 Clock */ -// RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, DISABLE); - -// GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_MCO); -// GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_MCO); -// GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_MCO); -// GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_MCO); -// GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_MCO); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_MCO); - -// /* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */ -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11; -// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; -// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; -// GPIO_Init(GPIOC, &GPIO_InitStructure); - -// /* Configure PD.02 CMD line */ -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; -// GPIO_Init(GPIOD, &GPIO_InitStructure); - -// /* Configure PC.12 pin: CLK pin */ -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; -// GPIO_Init(GPIOC, &GPIO_InitStructure); -// } - -/** - * @brief Initializes the SD Card and put it into StandBy State (Ready for - * data transfer). - * @param None - * @retval None - */ -void SD_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_SDIO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_SDIO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_SDIO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_SDIO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_SDIO); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_SDIO); - - /* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /* Configure PD.02 CMD line */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* Configure PC.12 pin: CLK pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /* Enable the SDIO APB2 Clock */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE); - - // SDIO Interrupt ENABLE - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - // DMA2 STREAMx Interrupt ENABLE - NVIC_InitStructure.NVIC_IRQChannel = SD_SDIO_DMA_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; - NVIC_Init(&NVIC_InitStructure); -} - -/** - * @brief Configures the DMA2 Channel4 for SDIO Tx request. - * @param BufferSRC: pointer to the source buffer - * @param BufferSize: buffer size - * @retval None - */ -void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize) -{ - DMA_InitTypeDef SDDMA_InitStructure; - - DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF); - - /* DMA2 Stream3 or Stream6 disable */ - DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE); - - /* DMA2 Stream3 or Stream6 Config */ - DMA_DeInit(SD_SDIO_DMA_STREAM); - - SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL; - SDDMA_InitStructure.DMA_PeripheralBaseAddr = SD_SDIO_FIFO_ADDRESS; - SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferSRC; - SDDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; - SDDMA_InitStructure.DMA_BufferSize = 1; - SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; - SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; - SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; - SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4; - SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; - DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure); - DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE); - DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral); - - /* DMA2 Stream3 or Stream6 enable */ - DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE); - -} - -/** - * @brief Configures the DMA2 Channel4 for SDIO Rx request. - * @param BufferDST: pointer to the destination buffer - * @param BufferSize: buffer size - * @retval None - */ -void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize) -{ - DMA_InitTypeDef SDDMA_InitStructure; - - DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF); - - /* DMA2 Stream3 or Stream6 disable */ - DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE); - - /* DMA2 Stream3 or Stream6 Config */ - DMA_DeInit(SD_SDIO_DMA_STREAM); - - SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL; - SDDMA_InitStructure.DMA_PeripheralBaseAddr = SD_SDIO_FIFO_ADDRESS; - SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferDST; - SDDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; - SDDMA_InitStructure.DMA_BufferSize = 1; - SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; - SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; - SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; - SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4; - SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; - DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure); - DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE); - DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral); - - /* DMA2 Stream3 or Stream6 enable */ - DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE); -} - - -/** - * @} - */ - - -// /** @defgroup STM32F4_DISCOVERY_SDIO_SD_Private_Functions -// * @{ -// */ - -// * -// * @brief DeInitializes the SDIO interface. -// * @param None -// * @retval None - -// void SD_DeInit(void) -// { -// SD_LowLevel_DeInit(); -// } - -/** - * @brief Initializes the SD Card and put it into StandBy State (Ready for data - * transfer). - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_Init(void) -{ - __IO SD_Error errorstatus = SD_OK; - - /* SDIO Peripheral Low Level Init */ - SD_LowLevel_Init(); - - SDIO_DeInit(); - - errorstatus = SD_PowerON(); - if (errorstatus != SD_OK) - { - TRACE("SD_PowerON() status=%d", errorstatus); - /*!< CMD Response TimeOut (wait for CMDSENT flag) */ - return(errorstatus); - } - - errorstatus = SD_InitializeCards(); - if (errorstatus != SD_OK) - { - TRACE("SD_InitializeCards() status=%d", errorstatus); - /*!< CMD Response TimeOut (wait for CMDSENT flag) */ - return(errorstatus); - } - - /*!< Configure the SDIO peripheral */ - /*!< SDIO_CK = SDIOCLK / (SDIO_TRANSFER_CLK_DIV + 2) */ - /*!< on STM32F4xx devices, SDIOCLK is fixed to 48MHz */ - SDIO_InitStructure.SDIO_ClockDiv = SD_SDIO_TRANSFER_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - - /*----------------- Read CSD/CID MSD registers ------------------*/ - errorstatus = SD_GetCardInfo(&SDCardInfo); - - if (errorstatus == SD_OK) - { - /*----------------- Select Card --------------------------------*/ - errorstatus = SD_SelectDeselect((uint32_t) (SDCardInfo.RCA << 16)); - } - - if (errorstatus == SD_OK) - { - errorstatus = SD_EnableWideBusOperation(SDIO_BusWide_4b); - } - - return(errorstatus); -} - -/** - * @brief Gets the cuurent sd card data transfer status. - * @param None - * @retval SDTransferState: Data Transfer state. - * This value can be: - * - SD_TRANSFER_OK: No data transfer is acting - * - SD_TRANSFER_BUSY: Data transfer is acting - */ -SDTransferState SD_GetStatus(void) -{ - SDCardState cardstate = SD_CARD_TRANSFER; - - cardstate = SD_GetState(); - - if (cardstate == SD_CARD_TRANSFER) - { - return(SD_TRANSFER_OK); - } - else if(cardstate == SD_CARD_ERROR) - { - return (SD_TRANSFER_ERROR); - } - else - { - return(SD_TRANSFER_BUSY); - } -} - -/** - * @brief Returns the current card's state. - * @param None - * @retval SDCardState: SD Card Error or SD Card Current State. - */ -SDCardState SD_GetState(void) -{ - uint32_t resp1 = 0; - - if(SD_Detect()== SD_PRESENT) - { - if (SD_SendStatus(&resp1) != SD_OK) - { - return SD_CARD_ERROR; - } - else - { - return (SDCardState)((resp1 >> 9) & 0x0F); - } - } - else - { - return SD_CARD_ERROR; - } -} - -/** - * @brief Detect if SD card is correctly plugged in the memory slot. - * @param None - * @retval Return if SD is detected or not - */ -uint8_t SD_Detect(void) -{ - __IO uint8_t status = SD_PRESENT; - -#if 0 // TODO - /*!< Check GPIO to detect SD */ - if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_RESET) - { - status = SD_NOT_PRESENT; - } -#endif - - return status; -} - -//--------------------------------------------------------------------------------------- -//disable optimize -#define OPTIMIZE(level) __attribute__((optimize(level))) - -/** - * @brief Enquires cards about their operating voltage and configures - * clock controls. - * @param None - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_PowerON(void) -{ - __IO SD_Error errorstatus = SD_OK; - uint32_t response = 0, count = 0, validvoltage = 0; - uint32_t SDType = SD_STD_CAPACITY; - - /*!< Power ON Sequence -----------------------------------------------------*/ - /*!< Configure the SDIO peripheral */ - /*!< SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) */ - /*!< on STM32F4xx devices, SDIOCLK is fixed to 48MHz */ - /*!< SDIO_CK for initialization should not exceed 400 KHz */ - SDIO_InitStructure.SDIO_ClockDiv = SD_SDIO_INIT_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - - /*!< Set Power State to ON */ - SDIO_SetPowerState(SDIO_PowerState_ON); - - /*!< Enable SDIO Clock */ - SDIO_ClockCmd(ENABLE); - - /*!< CMD0: GO_IDLE_STATE ---------------------------------------------------*/ - /*!< No CMD response required */ - SDIO_CmdInitStructure.SDIO_Argument = 0x0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_GO_IDLE_STATE; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdError(); - - if (errorstatus != SD_OK) - { - TRACE("SD_CMD_GO_IDLE_STATE status=%d", errorstatus); - /*!< CMD Response TimeOut (wait for CMDSENT flag) */ - return(errorstatus); - } - - /*!< CMD8: SEND_IF_COND ----------------------------------------------------*/ - /*!< Send CMD8 to verify SD card interface operating condition */ - /*!< Argument: - [31:12]: Reserved (shall be set to '0') - - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - - [7:0]: Check Pattern (recommended 0xAA) */ - /*!< CMD Response: R7 */ - SDIO_CmdInitStructure.SDIO_Argument = SD_CHECK_PATTERN; - SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_IF_COND; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp7Error(); - - if (errorstatus == SD_OK) - { - CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; /*!< SD Card 2.0 */ - SDType = SD_HIGH_CAPACITY; - } - else - { - /*!< CMD55 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - } - /*!< CMD55 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - /*!< If errorstatus is Command TimeOut, it is a MMC card */ - /*!< If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) - or SD card 1.x */ - if (errorstatus == SD_OK) - { - /*!< SD CARD */ - /*!< Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)) - { - - /*!< SEND CMD55 APP_CMD with RCA as 0 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - TRACE("SD_CMD_APP_CMD status=%d", errorstatus); - return(errorstatus); - } - SDIO_CmdInitStructure.SDIO_Argument = SD_VOLTAGE_WINDOW_SD | SDType; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_OP_COND; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp3Error(); - if (errorstatus != SD_OK) - { - TRACE("SD_CMD_SD_APP_OP_COND status=%d", errorstatus); - return(errorstatus); - } - - response = SDIO_GetResponse(SDIO_RESP1); - validvoltage = (((response >> 31) == 1) ? 1 : 0); - count++; - } - if (count >= SD_MAX_VOLT_TRIAL) - { - errorstatus = SD_INVALID_VOLTRANGE; - return(errorstatus); - } - - if (response &= SD_HIGH_CAPACITY) - { - CardType = SDIO_HIGH_CAPACITY_SD_CARD; - } - - }/*!< else MMC Card */ - - return(errorstatus); -} - -/** - * @brief Turns the SDIO output signals off. - * @param None - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_PowerOFF(void) -{ - SD_Error errorstatus = SD_OK; - - /*!< Set Power State to OFF */ - SDIO_SetPowerState(SDIO_PowerState_OFF); - - return(errorstatus); -} - -/** - * @brief Intialises all cards or single card as the case may be Card(s) come - * into standby state. - * @param None - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_InitializeCards(void) -{ - SD_Error errorstatus = SD_OK; - uint16_t rca = 0x01; - - if (SDIO_GetPowerState() == SDIO_PowerState_OFF) - { - errorstatus = SD_REQUEST_NOT_APPLICABLE; - return(errorstatus); - } - - if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) - { - /*!< Send CMD2 ALL_SEND_CID */ - SDIO_CmdInitStructure.SDIO_Argument = 0x0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ALL_SEND_CID; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp2Error(); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - CID_Tab[0] = SDIO_GetResponse(SDIO_RESP1); - CID_Tab[1] = SDIO_GetResponse(SDIO_RESP2); - CID_Tab[2] = SDIO_GetResponse(SDIO_RESP3); - CID_Tab[3] = SDIO_GetResponse(SDIO_RESP4); - } - if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_SECURE_DIGITAL_IO_COMBO_CARD == CardType) - || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) - { - /*!< Send CMD3 SET_REL_ADDR with argument 0 */ - /*!< SD Card publishes its RCA. */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_REL_ADDR; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp6Error(SD_CMD_SET_REL_ADDR, &rca); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - } - - if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) - { - RCA = rca; - - /*!< Send CMD9 SEND_CSD with argument as card's RCA */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)(rca << 16); - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_CSD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp2Error(); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - CSD_Tab[0] = SDIO_GetResponse(SDIO_RESP1); - CSD_Tab[1] = SDIO_GetResponse(SDIO_RESP2); - CSD_Tab[2] = SDIO_GetResponse(SDIO_RESP3); - CSD_Tab[3] = SDIO_GetResponse(SDIO_RESP4); - } - - errorstatus = SD_OK; /*!< All cards get intialized */ - - return(errorstatus); -} - -/** - * @brief Returns information about specific card. - * @param cardinfo: pointer to a SD_CardInfo structure that contains all SD card - * information. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo) -{ - SD_Error errorstatus = SD_OK; - uint8_t tmp = 0; - - cardinfo->CardType = (uint8_t)CardType; - cardinfo->RCA = (uint16_t)RCA; - - /*!< Byte 0 */ - tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24); - cardinfo->SD_csd.CSDStruct = (tmp & 0xC0) >> 6; - cardinfo->SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2; - cardinfo->SD_csd.Reserved1 = tmp & 0x03; - - /*!< Byte 1 */ - tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16); - cardinfo->SD_csd.TAAC = tmp; - - /*!< Byte 2 */ - tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8); - cardinfo->SD_csd.NSAC = tmp; - - /*!< Byte 3 */ - tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF); - cardinfo->SD_csd.MaxBusClkFrec = tmp; - - /*!< Byte 4 */ - tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24); - cardinfo->SD_csd.CardComdClasses = tmp << 4; - - /*!< Byte 5 */ - tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16); - cardinfo->SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4; - cardinfo->SD_csd.RdBlockLen = tmp & 0x0F; - - /*!< Byte 6 */ - tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8); - cardinfo->SD_csd.PartBlockRead = (tmp & 0x80) >> 7; - cardinfo->SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6; - cardinfo->SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5; - cardinfo->SD_csd.DSRImpl = (tmp & 0x10) >> 4; - cardinfo->SD_csd.Reserved2 = 0; /*!< Reserved */ - - if ((CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || (CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) - { - cardinfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; - - /*!< Byte 7 */ - tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); - cardinfo->SD_csd.DeviceSize |= (tmp) << 2; - - /*!< Byte 8 */ - tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); - cardinfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; - - cardinfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; - cardinfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); - - /*!< Byte 9 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); - cardinfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; - cardinfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; - cardinfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; - /*!< Byte 10 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); - cardinfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; - - cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ; - cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2)); - cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen); - cardinfo->CardCapacity *= cardinfo->CardBlockSize; - } - else if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - /*!< Byte 7 */ - tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); - cardinfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; - - /*!< Byte 8 */ - tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); - - cardinfo->SD_csd.DeviceSize |= (tmp << 8); - - /*!< Byte 9 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); - - cardinfo->SD_csd.DeviceSize |= (tmp); - - /*!< Byte 10 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); - - cardinfo->CardCapacity = ((uint64_t)cardinfo->SD_csd.DeviceSize + 1) * 512 * 1024; - cardinfo->CardBlockSize = 512; - } - - - cardinfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; - cardinfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; - - /*!< Byte 11 */ - tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF); - cardinfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; - cardinfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); - - /*!< Byte 12 */ - tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24); - cardinfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; - cardinfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; - cardinfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; - cardinfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; - - /*!< Byte 13 */ - tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16); - cardinfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; - cardinfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; - cardinfo->SD_csd.Reserved3 = 0; - cardinfo->SD_csd.ContentProtectAppli = (tmp & 0x01); - - /*!< Byte 14 */ - tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8); - cardinfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; - cardinfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6; - cardinfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5; - cardinfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4; - cardinfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2; - cardinfo->SD_csd.ECC = (tmp & 0x03); - - /*!< Byte 15 */ - tmp = (uint8_t)(CSD_Tab[3] & 0x000000FF); - cardinfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1; - cardinfo->SD_csd.Reserved4 = 1; - - - /*!< Byte 0 */ - tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24); - cardinfo->SD_cid.ManufacturerID = tmp; - - /*!< Byte 1 */ - tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16); - cardinfo->SD_cid.OEM_AppliID = tmp << 8; - - /*!< Byte 2 */ - tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8); - cardinfo->SD_cid.OEM_AppliID |= tmp; - - /*!< Byte 3 */ - tmp = (uint8_t)(CID_Tab[0] & 0x000000FF); - cardinfo->SD_cid.ProdName1 = tmp << 24; - - /*!< Byte 4 */ - tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24); - cardinfo->SD_cid.ProdName1 |= tmp << 16; - - /*!< Byte 5 */ - tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16); - cardinfo->SD_cid.ProdName1 |= tmp << 8; - - /*!< Byte 6 */ - tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8); - cardinfo->SD_cid.ProdName1 |= tmp; - - /*!< Byte 7 */ - tmp = (uint8_t)(CID_Tab[1] & 0x000000FF); - cardinfo->SD_cid.ProdName2 = tmp; - - /*!< Byte 8 */ - tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24); - cardinfo->SD_cid.ProdRev = tmp; - - /*!< Byte 9 */ - tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16); - cardinfo->SD_cid.ProdSN = tmp << 24; - - /*!< Byte 10 */ - tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8); - cardinfo->SD_cid.ProdSN |= tmp << 16; - - /*!< Byte 11 */ - tmp = (uint8_t)(CID_Tab[2] & 0x000000FF); - cardinfo->SD_cid.ProdSN |= tmp << 8; - - /*!< Byte 12 */ - tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24); - cardinfo->SD_cid.ProdSN |= tmp; - - /*!< Byte 13 */ - tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16); - cardinfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; - cardinfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8; - - /*!< Byte 14 */ - tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8); - cardinfo->SD_cid.ManufactDate |= tmp; - - /*!< Byte 15 */ - tmp = (uint8_t)(CID_Tab[3] & 0x000000FF); - cardinfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; - cardinfo->SD_cid.Reserved2 = 1; - - return(errorstatus); -} - -/** - * @brief Enables wide bus opeartion for the requeseted card if supported by - * card. - * @param WideMode: Specifies the SD card wide bus mode. - * This parameter can be one of the following values: - * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) - * @arg SDIO_BusWide_4b: 4-bit data transfer - * @arg SDIO_BusWide_1b: 1-bit data transfer - * @retval SD_Error: SD Card Error code. - */ -// OPTIMIZE("O0") SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus) -// { -// SD_Error errorstatus = SD_OK; -// uint8_t tmp = 0; - -// errorstatus = SD_SendSDStatus((uint32_t *)SDSTATUS_Tab); - -// if (errorstatus != SD_OK) -// { -// return(errorstatus); -// } - -// /*!< Byte 0 */ -// tmp = (uint8_t)((SDSTATUS_Tab[0] & 0xC0) >> 6); -// cardstatus->DAT_BUS_WIDTH = tmp; - -// /*!< Byte 0 */ -// tmp = (uint8_t)((SDSTATUS_Tab[0] & 0x20) >> 5); -// cardstatus->SECURED_MODE = tmp; - -// /*!< Byte 2 */ -// tmp = (uint8_t)((SDSTATUS_Tab[2] & 0xFF)); -// cardstatus->SD_CARD_TYPE = tmp << 8; - -// /*!< Byte 3 */ -// tmp = (uint8_t)((SDSTATUS_Tab[3] & 0xFF)); -// cardstatus->SD_CARD_TYPE |= tmp; - -// /*!< Byte 4 */ -// tmp = (uint8_t)(SDSTATUS_Tab[4] & 0xFF); -// cardstatus->SIZE_OF_PROTECTED_AREA = tmp << 24; - -// /*!< Byte 5 */ -// tmp = (uint8_t)(SDSTATUS_Tab[5] & 0xFF); -// cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 16; - -// /*!< Byte 6 */ -// tmp = (uint8_t)(SDSTATUS_Tab[6] & 0xFF); -// cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 8; - -// /*!< Byte 7 */ -// tmp = (uint8_t)(SDSTATUS_Tab[7] & 0xFF); -// cardstatus->SIZE_OF_PROTECTED_AREA |= tmp; - -// /*!< Byte 8 */ -// tmp = (uint8_t)((SDSTATUS_Tab[8] & 0xFF)); -// cardstatus->SPEED_CLASS = tmp; - -// /*!< Byte 9 */ -// tmp = (uint8_t)((SDSTATUS_Tab[9] & 0xFF)); -// cardstatus->PERFORMANCE_MOVE = tmp; - -// /*!< Byte 10 */ -// tmp = (uint8_t)((SDSTATUS_Tab[10] & 0xF0) >> 4); -// cardstatus->AU_SIZE = tmp; - -// /*!< Byte 11 */ -// tmp = (uint8_t)(SDSTATUS_Tab[11] & 0xFF); -// cardstatus->ERASE_SIZE = tmp << 8; - -// /*!< Byte 12 */ -// tmp = (uint8_t)(SDSTATUS_Tab[12] & 0xFF); -// cardstatus->ERASE_SIZE |= tmp; - -// /*!< Byte 13 */ -// tmp = (uint8_t)((SDSTATUS_Tab[13] & 0xFC) >> 2); -// cardstatus->ERASE_TIMEOUT = tmp; - -// /*!< Byte 13 */ -// tmp = (uint8_t)((SDSTATUS_Tab[13] & 0x3)); -// cardstatus->ERASE_OFFSET = tmp; - -// return(errorstatus); -// } - -/** - * @brief Enables wide bus opeartion for the requeseted card if supported by - * card. - * @param WideMode: Specifies the SD card wide bus mode. - * This parameter can be one of the following values: - * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) - * @arg SDIO_BusWide_4b: 4-bit data transfer - * @arg SDIO_BusWide_1b: 1-bit data transfer - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_EnableWideBusOperation(uint32_t WideMode) -{ - SD_Error errorstatus = SD_OK; - - /*!< MMC Card doesn't support this feature */ - if (SDIO_MULTIMEDIA_CARD == CardType) - { - errorstatus = SD_UNSUPPORTED_FEATURE; - return(errorstatus); - } - else if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) - { - if (SDIO_BusWide_8b == WideMode) - { - errorstatus = SD_UNSUPPORTED_FEATURE; - return(errorstatus); - } - else if (SDIO_BusWide_4b == WideMode) - { - errorstatus = SDEnWideBus(ENABLE); - - if (SD_OK == errorstatus) - { - /*!< Configure the SDIO peripheral */ - SDIO_InitStructure.SDIO_ClockDiv = SD_SDIO_TRANSFER_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - } - } - else - { - errorstatus = SDEnWideBus(DISABLE); - - if (SD_OK == errorstatus) - { - /*!< Configure the SDIO peripheral */ - SDIO_InitStructure.SDIO_ClockDiv = SD_SDIO_TRANSFER_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - } - } - } - - return(errorstatus); -} - -/** - * @brief Selects od Deselects the corresponding card. - * @param addr: Address of the Card to be selected. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_SelectDeselect(uint32_t addr) -{ - SD_Error errorstatus = SD_OK; - - /*!< Send CMD7 SDIO_SEL_DESEL_CARD */ - SDIO_CmdInitStructure.SDIO_Argument = addr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEL_DESEL_CARD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SEL_DESEL_CARD); - - return(errorstatus); -} - -/** - * @brief Allows to read one block from a specified address in a card. The Data - * transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param readbuff: pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data are to be read. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize) -{ - SD_Error errorstatus = SD_OK; - - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 0; - DMAEndOfTransfer = 0; - - SDIO->DCTRL = 0x0; - - SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); - SDIO_DMACmd(ENABLE); - SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, BlockSize); - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - BlockSize = 512; - else - ReadAddr *= 512; - - /* Set Block Size for Card */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_512b; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - /*!< Send CMD17 READ_SINGLE_BLOCK */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_SINGLE_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_READ_SINGLE_BLOCK); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - return(errorstatus); -} - -/** - * @brief Allows to read blocks from a specified address in a card. The Data - * transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param readbuff: pointer to the buffer that will contain the received data. - * @param ReadAddr: Address from where data are to be read. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @param NumberOfBlocks: number of blocks to be read. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - SD_Error errorstatus = SD_OK; - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 1; - DMAEndOfTransfer = 0; - - SDIO->DCTRL = 0x0; - - SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); - SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, (NumberOfBlocks * BlockSize)); - SDIO_DMACmd(ENABLE); - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - BlockSize = 512; - else - ReadAddr *= 512; - - /*!< Set Block Size for Card */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT * NumberOfBlocks; - SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_512b; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - /*!< Send CMD18 READ_MULT_BLOCK with argument data address */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_MULT_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_READ_MULT_BLOCK); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - return(errorstatus); -} - -/** - * @brief This function waits until the SDIO DMA data transfer is finished. - * This function should be called after SDIO_ReadMultiBlocks() function - * to insure that all data sent by the card are already transferred by - * the DMA controller. - * @param None. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_WaitReadOperation(uint32_t timeout) -{ - SD_Error errorstatus = SD_OK; - - while (!DMAEndOfTransfer && !TransferEnd && (TransferError == SD_OK) && (timeout > 0)) - { - delay_ms(1); - timeout--; - } - TRACE_SD_CARD_EVENT((timeout == 0), sd_wait_read, (TransferError << 8) + (DMAEndOfTransfer << 1) + TransferEnd); - - DMAEndOfTransfer = 0; - - timeout = 100; - - while(((SDIO->STA & SDIO_FLAG_RXACT)) && (timeout > 0)) - { - delay_ms(1); - timeout--; - } - TRACE_SD_CARD_EVENT((timeout == 0), sd_wait_read, -1); - - if (StopCondition == 1) - { - errorstatus = SD_StopTransfer(); - StopCondition = 0; - } - - if ((timeout == 0) && (errorstatus == SD_OK)) - { - errorstatus = SD_DATA_TIMEOUT; - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - if (TransferError != SD_OK) - { - return(TransferError); - } - else - { - return(errorstatus); - } -} - -/** - * @brief Allows to write one block starting from a specified address in a card. - * The Data transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param writebuff: pointer to the buffer that contain the data to be transferred. - * @param WriteAddr: Address from where data are to be read. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize) -{ - SD_Error errorstatus = SD_OK; - - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 0; - - SDIO->DCTRL = 0x0; - - SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); - SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, BlockSize); - SDIO_DMACmd(ENABLE); - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - BlockSize = 512; - else - WriteAddr *= 512; - - /* Set Block Size for Card */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - /*!< Send CMD24 WRITE_SINGLE_BLOCK */ - SDIO_CmdInitStructure.SDIO_Argument = WriteAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_WRITE_SINGLE_BLOCK); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_512b; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - return(errorstatus); -} - -/** - * @brief Allows to write blocks starting from a specified address in a card. - * The Data transfer can be managed by DMA mode only. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param WriteAddr: Address from where data are to be read. - * @param writebuff: pointer to the buffer that contain the data to be transferred. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @param NumberOfBlocks: number of blocks to be written. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - SD_Error errorstatus = SD_OK; - - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 1; - - SDIO->DCTRL = 0x0; - - SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR, ENABLE); - SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, (NumberOfBlocks * BlockSize)); - SDIO_DMACmd(ENABLE); - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) { - BlockSize = 512; - } - else { - WriteAddr *= 512; - } - - /* Set Block Size for Card */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - /*!< To improve performance */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) (RCA << 16); - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - /*!< To improve performance */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)NumberOfBlocks; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCK_COUNT; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCK_COUNT); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - - /*!< Send CMD25 WRITE_MULT_BLOCK with argument data address */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)WriteAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_MULT_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_WRITE_MULT_BLOCK); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT * NumberOfBlocks; - SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_512b; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - return(errorstatus); -} - - -/** - * @brief This function waits until the SDIO DMA data transfer is finished. - * This function should be called after SDIO_WriteBlock() and - * SDIO_WriteMultiBlocks() function to insure that all data sent by the - * card are already transferred by the DMA controller. - * @param None. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_WaitWriteOperation(uint32_t timeout) -{ - SD_Error errorstatus = SD_OK; - - while (!DMAEndOfTransfer && !TransferEnd && (TransferError == SD_OK) && (timeout > 0)) - { - delay_ms(1); - timeout--; - } - TRACE_SD_CARD_EVENT((timeout == 0), sd_wait_write, (TransferError << 8) + (DMAEndOfTransfer << 1) + TransferEnd); - - DMAEndOfTransfer = 0; - - timeout = 100; - - while(((SDIO->STA & SDIO_FLAG_TXACT)) && (timeout > 0)) - { - delay_ms(1); - timeout--; - } - TRACE_SD_CARD_EVENT((timeout == 0), sd_wait_write, -1); - - if (StopCondition == 1) - { - errorstatus = SD_StopTransfer(); - StopCondition = 0; - } - - if ((timeout == 0) && (errorstatus == SD_OK)) - { - errorstatus = SD_DATA_TIMEOUT; - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - if (TransferError != SD_OK) - { - return(TransferError); - } - else - { - return(errorstatus); - } -} - -/** - * @brief Gets the cuurent data transfer state. - * @param None - * @retval SDTransferState: Data Transfer state. - * This value can be: - * - SD_TRANSFER_OK: No data transfer is acting - * - SD_TRANSFER_BUSY: Data transfer is acting - */ -OPTIMIZE("O0") SDTransferState SD_GetTransferState(void) -{ - if (SDIO->STA & (SDIO_FLAG_TXACT | SDIO_FLAG_RXACT)) - { - return(SD_TRANSFER_BUSY); - } - else - { - return(SD_TRANSFER_OK); - } -} - -/** - * @brief Aborts an ongoing data transfer. - * @param None - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_StopTransfer(void) -{ - SD_Error errorstatus = SD_OK; - - /*!< Send CMD12 STOP_TRANSMISSION */ - SDIO_CmdInitStructure.SDIO_Argument = 0x0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_STOP_TRANSMISSION; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_STOP_TRANSMISSION); - - return(errorstatus); -} - -/** - * @brief Allows to erase memory area specified for the given card. - * @param startaddr: the start address. - * @param endaddr: the end address. - * @retval SD_Error: SD Card Error code. - */ -// OPTIMIZE("O0") SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr) -// { -// SD_Error errorstatus = SD_OK; -// uint32_t delay = 0; -// __IO uint32_t maxdelay = 0; -// uint8_t cardstate = 0; - -// /*!< Check if the card coomnd class supports erase command */ -// if (((CSD_Tab[1] >> 20) & SD_CCCC_ERASE) == 0) -// { -// errorstatus = SD_REQUEST_NOT_APPLICABLE; -// return(errorstatus); -// } - -// maxdelay = 120000 / ((SDIO->CLKCR & 0xFF) + 2); - -// if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) -// { -// errorstatus = SD_LOCK_UNLOCK_FAILED; -// return(errorstatus); -// } - -// if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) -// { -// startaddr /= 512; -// endaddr /= 512; -// } - -// /*!< According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ -// if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) -// { -// /*!< Send CMD32 SD_ERASE_GRP_START with argument as addr */ -// SDIO_CmdInitStructure.SDIO_Argument = startaddr; -// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_START; -// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; -// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; -// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; -// SDIO_SendCommand(&SDIO_CmdInitStructure); - -// errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_START); -// if (errorstatus != SD_OK) -// { -// return(errorstatus); -// } - -// /*!< Send CMD33 SD_ERASE_GRP_END with argument as addr */ -// SDIO_CmdInitStructure.SDIO_Argument = endaddr; -// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_END; -// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; -// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; -// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; -// SDIO_SendCommand(&SDIO_CmdInitStructure); - -// errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_END); -// if (errorstatus != SD_OK) -// { -// return(errorstatus); -// } -// } - -// /*!< Send CMD38 ERASE */ -// SDIO_CmdInitStructure.SDIO_Argument = 0; -// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ERASE; -// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; -// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; -// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; -// SDIO_SendCommand(&SDIO_CmdInitStructure); - -// errorstatus = CmdResp1Error(SD_CMD_ERASE); - -// if (errorstatus != SD_OK) -// { -// return(errorstatus); -// } - -// for (delay = 0; delay < maxdelay; delay++) -// {} - -// /*!< Wait till the card is in programming state */ -// errorstatus = IsCardProgramming(&cardstate); -// delay = SD_DATATIMEOUT; -// while ((delay > 0) && (errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate))) -// { -// errorstatus = IsCardProgramming(&cardstate); -// delay--; -// } - -// return(errorstatus); -// } - -/** - * @brief Returns the current card's status. - * @param pcardstatus: pointer to the buffer that will contain the SD card - * status (Card Status register). - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") SD_Error SD_SendStatus(uint32_t *pcardstatus) -{ - SD_Error errorstatus = SD_OK; - - if (pcardstatus == NULL) - { - errorstatus = SD_INVALID_PARAMETER; - return(errorstatus); - } - - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SEND_STATUS); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - *pcardstatus = SDIO_GetResponse(SDIO_RESP1); - - return(errorstatus); -} - -/** - * @brief Returns the current SD card's status. - * @param psdstatus: pointer to the buffer that will contain the SD card status - * (SD Status register). - * @retval SD_Error: SD Card Error code. - */ -// OPTIMIZE("O0") SD_Error SD_SendSDStatus(uint32_t *psdstatus) -// { -// SD_Error errorstatus = SD_OK; -// uint32_t count = 0; - -// if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) -// { -// errorstatus = SD_LOCK_UNLOCK_FAILED; -// return(errorstatus); -// } - -// /*!< Set block size for card if it is not equal to current block size for card. */ -// SDIO_CmdInitStructure.SDIO_Argument = 64; -// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; -// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; -// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; -// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; -// SDIO_SendCommand(&SDIO_CmdInitStructure); - -// errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - -// if (errorstatus != SD_OK) -// { -// return(errorstatus); -// } - -// /*!< CMD55 */ -// SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; -// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; -// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; -// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; -// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; -// SDIO_SendCommand(&SDIO_CmdInitStructure); -// errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - -// if (errorstatus != SD_OK) -// { -// return(errorstatus); -// } - -// SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; -// SDIO_DataInitStructure.SDIO_DataLength = 64; -// SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b; -// SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; -// SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; -// SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; -// SDIO_DataConfig(&SDIO_DataInitStructure); - -// /*!< Send ACMD13 SD_APP_STAUS with argument as card's RCA.*/ -// SDIO_CmdInitStructure.SDIO_Argument = 0; -// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_STAUS; -// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; -// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; -// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; -// SDIO_SendCommand(&SDIO_CmdInitStructure); -// errorstatus = CmdResp1Error(SD_CMD_SD_APP_STAUS); - -// if (errorstatus != SD_OK) -// { -// return(errorstatus); -// } - -// while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) -// { -// if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) -// { -// for (count = 0; count < 8; count++) -// { -// *(psdstatus + count) = SDIO_ReadData(); -// } -// psdstatus += 8; -// } -// } - -// if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) -// { -// SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); -// errorstatus = SD_DATA_TIMEOUT; -// return(errorstatus); -// } -// else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) -// { -// SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); -// errorstatus = SD_DATA_CRC_FAIL; -// return(errorstatus); -// } -// else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) -// { -// SDIO_ClearFlag(SDIO_FLAG_RXOVERR); -// errorstatus = SD_RX_OVERRUN; -// return(errorstatus); -// } -// else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) -// { -// SDIO_ClearFlag(SDIO_FLAG_STBITERR); -// errorstatus = SD_START_BIT_ERR; -// return(errorstatus); -// } - -// count = SD_DATATIMEOUT; -// while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0)) -// { -// *psdstatus = SDIO_ReadData(); -// psdstatus++; -// count--; -// } -// /*!< Clear all the static status flags*/ -// SDIO_ClearFlag(SDIO_STATIC_FLAGS); - -// return(errorstatus); -// } - -/** - * @brief Allows to process all the interrupts that are high. - * @param None - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") void SD_ProcessIRQ(void) -{ - if (SDIO_GetITStatus(SDIO_IT_DATAEND) != RESET) - { - TransferError = SD_OK; - SDIO_ClearITPendingBit(SDIO_IT_DATAEND); - TransferEnd = 1; - } - else if (SDIO_GetITStatus(SDIO_IT_DCRCFAIL) != RESET) - { - SDIO_ClearITPendingBit(SDIO_IT_DCRCFAIL); - TransferError = SD_DATA_CRC_FAIL; - } - else if (SDIO_GetITStatus(SDIO_IT_DTIMEOUT) != RESET) - { - SDIO_ClearITPendingBit(SDIO_IT_DTIMEOUT); - TransferError = SD_DATA_TIMEOUT; - } - else if (SDIO_GetITStatus(SDIO_IT_RXOVERR) != RESET) - { - SDIO_ClearITPendingBit(SDIO_IT_RXOVERR); - TransferError = SD_RX_OVERRUN; - } - else if (SDIO_GetITStatus(SDIO_IT_TXUNDERR) != RESET) - { - SDIO_ClearITPendingBit(SDIO_IT_TXUNDERR); - TransferError = SD_TX_UNDERRUN; - } - else if (SDIO_GetITStatus(SDIO_IT_STBITERR) != RESET) - { - SDIO_ClearITPendingBit(SDIO_IT_STBITERR); - TransferError = SD_START_BIT_ERR; - } - - SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | - SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR | - SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE); - - TRACE_SD_CARD_EVENT((TransferError != SD_OK), sd_irq, TransferError); -} - -/** - * @brief This function waits until the SDIO DMA data transfer is finished. - * @param None. - * @retval None. - */ -OPTIMIZE("O0") void SD_ProcessDMAIRQ(void) -{ - if(DMA2->LISR & SD_SDIO_DMA_FLAG_TCIF) - { - DMAEndOfTransfer = 1; - DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_TCIF|SD_SDIO_DMA_FLAG_FEIF); - } -} - -/** - * @brief Checks for error conditions for CMD0. - * @param None - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") static SD_Error CmdError(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t timeout; - - timeout = SDIO_CMD0TIMEOUT; /*!< 10000 */ - - while ((timeout > 0) && (SDIO_GetFlagStatus(SDIO_FLAG_CMDSENT) == RESET)) - { - timeout--; - } - - if (timeout == 0) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R7 response. - * @param None - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") static SD_Error CmdResp7Error(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - uint32_t timeout = SDIO_CMD0TIMEOUT; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) && (timeout > 0)) - { - timeout--; - status = SDIO->STA; - } - - if ((timeout == 0) || (status & SDIO_FLAG_CTIMEOUT)) - { - /*!< Card is not V2.0 complient or card does not support the set voltage range */ - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - - if (status & SDIO_FLAG_CMDREND) - { - /*!< Card is SD V2.0 compliant */ - errorstatus = SD_OK; - SDIO_ClearFlag(SDIO_FLAG_CMDREND); - return(errorstatus); - } - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R1 response. - * @param cmd: The sent command index. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") static SD_Error CmdResp1Error(uint8_t cmd) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - uint32_t response_r1; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - else if (status & SDIO_FLAG_CCRCFAIL) - { - errorstatus = SD_CMD_CRC_FAIL; - SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); - return(errorstatus); - } - - /*!< Check response received is of desired command */ - if (SDIO_GetCommandResponse() != cmd) - { - errorstatus = SD_ILLEGAL_CMD; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - /*!< We have received response, retrieve it for analysis */ - response_r1 = SDIO_GetResponse(SDIO_RESP1); - - if ((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return(errorstatus); - } - - if (response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } - - if (response_r1 & SD_OCR_ADDR_MISALIGNED) - { - return(SD_ADDR_MISALIGNED); - } - - if (response_r1 & SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } - - if (response_r1 & SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } - - if (response_r1 & SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } - - if (response_r1 & SD_OCR_WRITE_PROT_VIOLATION) - { - return(SD_WRITE_PROT_VIOLATION); - } - - if (response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) - { - return(SD_LOCK_UNLOCK_FAILED); - } - - if (response_r1 & SD_OCR_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - if (response_r1 & SD_OCR_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if (response_r1 & SD_OCR_CARD_ECC_FAILED) - { - return(SD_CARD_ECC_FAILED); - } - - if (response_r1 & SD_OCR_CC_ERROR) - { - return(SD_CC_ERROR); - } - - if (response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if (response_r1 & SD_OCR_STREAM_READ_UNDERRUN) - { - return(SD_STREAM_READ_UNDERRUN); - } - - if (response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) - { - return(SD_STREAM_WRITE_OVERRUN); - } - - if (response_r1 & SD_OCR_CID_CSD_OVERWRIETE) - { - return(SD_CID_CSD_OVERWRITE); - } - - if (response_r1 & SD_OCR_WP_ERASE_SKIP) - { - return(SD_WP_ERASE_SKIP); - } - - if (response_r1 & SD_OCR_CARD_ECC_DISABLED) - { - return(SD_CARD_ECC_DISABLED); - } - - if (response_r1 & SD_OCR_ERASE_RESET) - { - return(SD_ERASE_RESET); - } - - if (response_r1 & SD_OCR_AKE_SEQ_ERROR) - { - return(SD_AKE_SEQ_ERROR); - } - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R3 (OCR) response. - * @param None - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") static SD_Error CmdResp3Error(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param None - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") static SD_Error CmdResp2Error(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - else if (status & SDIO_FLAG_CCRCFAIL) - { - errorstatus = SD_CMD_CRC_FAIL; - SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R6 (RCA) response. - * @param cmd: The sent command index. - * @param prca: pointer to the variable that will contain the SD card relative - * address RCA. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - uint32_t response_r1; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - else if (status & SDIO_FLAG_CCRCFAIL) - { - errorstatus = SD_CMD_CRC_FAIL; - SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); - return(errorstatus); - } - - /*!< Check response received is of desired command */ - if (SDIO_GetCommandResponse() != cmd) - { - errorstatus = SD_ILLEGAL_CMD; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - /*!< We have received response, retrieve it. */ - response_r1 = SDIO_GetResponse(SDIO_RESP1); - - if (SD_ALLZERO == (response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) - { - *prca = (uint16_t) (response_r1 >> 16); - return(errorstatus); - } - - if (response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if (response_r1 & SD_R6_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if (response_r1 & SD_R6_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - return(errorstatus); -} - -/** - * @brief Enables or disables the SDIO wide bus mode. - * @param NewState: new state of the SDIO wide bus mode. - * This parameter can be: ENABLE or DISABLE. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") static SD_Error SDEnWideBus(FunctionalState NewState) -{ - SD_Error errorstatus = SD_OK; - - uint32_t scr[2] = {0, 0}; - - if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) - { - errorstatus = SD_LOCK_UNLOCK_FAILED; - return(errorstatus); - } - - /*!< Get SCR Register */ - errorstatus = FindSCR(RCA, scr); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< If wide bus operation to be enabled */ - if (NewState == ENABLE) - { - /*!< If requested card supports wide bus operation */ - if ((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) - { - /*!< Send CMD55 APP_CMD with argument as card's RCA.*/ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - SDIO_CmdInitStructure.SDIO_Argument = 0x2; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - return(errorstatus); - } - else - { - errorstatus = SD_REQUEST_NOT_APPLICABLE; - return(errorstatus); - } - } /*!< If wide bus operation to be disabled */ - else - { - /*!< If requested card supports 1 bit mode operation */ - if ((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) - { - /*!< Send CMD55 APP_CMD with argument as card's RCA.*/ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - return(errorstatus); - } - else - { - errorstatus = SD_REQUEST_NOT_APPLICABLE; - return(errorstatus); - } - } -} - -/** - * @brief Checks if the SD card is in programming state. - * @param pstatus: pointer to the variable that will contain the SD card state. - * @retval SD_Error: SD Card Error code. - */ -// OPTIMIZE("O0") static SD_Error IsCardProgramming(uint8_t *pstatus) -// { -// SD_Error errorstatus = SD_OK; -// __IO uint32_t respR1 = 0, status = 0; - -// SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; -// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS; -// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; -// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; -// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; -// SDIO_SendCommand(&SDIO_CmdInitStructure); - -// status = SDIO->STA; -// while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) -// { -// status = SDIO->STA; -// } - -// if (status & SDIO_FLAG_CTIMEOUT) -// { -// errorstatus = SD_CMD_RSP_TIMEOUT; -// SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); -// return(errorstatus); -// } -// else if (status & SDIO_FLAG_CCRCFAIL) -// { -// errorstatus = SD_CMD_CRC_FAIL; -// SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); -// return(errorstatus); -// } - -// status = (uint32_t)SDIO_GetCommandResponse(); - -// /*!< Check response received is of desired command */ -// if (status != SD_CMD_SEND_STATUS) -// { -// errorstatus = SD_ILLEGAL_CMD; -// return(errorstatus); -// } - -// /*!< Clear all the static flags */ -// SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - -// /*!< We have received response, retrieve it for analysis */ -// respR1 = SDIO_GetResponse(SDIO_RESP1); - -// /*!< Find out card status */ -// *pstatus = (uint8_t) ((respR1 >> 9) & 0x0000000F); - -// if ((respR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) -// { -// return(errorstatus); -// } - -// if (respR1 & SD_OCR_ADDR_OUT_OF_RANGE) -// { -// return(SD_ADDR_OUT_OF_RANGE); -// } - -// if (respR1 & SD_OCR_ADDR_MISALIGNED) -// { -// return(SD_ADDR_MISALIGNED); -// } - -// if (respR1 & SD_OCR_BLOCK_LEN_ERR) -// { -// return(SD_BLOCK_LEN_ERR); -// } - -// if (respR1 & SD_OCR_ERASE_SEQ_ERR) -// { -// return(SD_ERASE_SEQ_ERR); -// } - -// if (respR1 & SD_OCR_BAD_ERASE_PARAM) -// { -// return(SD_BAD_ERASE_PARAM); -// } - -// if (respR1 & SD_OCR_WRITE_PROT_VIOLATION) -// { -// return(SD_WRITE_PROT_VIOLATION); -// } - -// if (respR1 & SD_OCR_LOCK_UNLOCK_FAILED) -// { -// return(SD_LOCK_UNLOCK_FAILED); -// } - -// if (respR1 & SD_OCR_COM_CRC_FAILED) -// { -// return(SD_COM_CRC_FAILED); -// } - -// if (respR1 & SD_OCR_ILLEGAL_CMD) -// { -// return(SD_ILLEGAL_CMD); -// } - -// if (respR1 & SD_OCR_CARD_ECC_FAILED) -// { -// return(SD_CARD_ECC_FAILED); -// } - -// if (respR1 & SD_OCR_CC_ERROR) -// { -// return(SD_CC_ERROR); -// } - -// if (respR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) -// { -// return(SD_GENERAL_UNKNOWN_ERROR); -// } - -// if (respR1 & SD_OCR_STREAM_READ_UNDERRUN) -// { -// return(SD_STREAM_READ_UNDERRUN); -// } - -// if (respR1 & SD_OCR_STREAM_WRITE_OVERRUN) -// { -// return(SD_STREAM_WRITE_OVERRUN); -// } - -// if (respR1 & SD_OCR_CID_CSD_OVERWRIETE) -// { -// return(SD_CID_CSD_OVERWRITE); -// } - -// if (respR1 & SD_OCR_WP_ERASE_SKIP) -// { -// return(SD_WP_ERASE_SKIP); -// } - -// if (respR1 & SD_OCR_CARD_ECC_DISABLED) -// { -// return(SD_CARD_ECC_DISABLED); -// } - -// if (respR1 & SD_OCR_ERASE_RESET) -// { -// return(SD_ERASE_RESET); -// } - -// if (respR1 & SD_OCR_AKE_SEQ_ERROR) -// { -// return(SD_AKE_SEQ_ERROR); -// } - -// return(errorstatus); -// } - -/** - * @brief Find the SD card SCR register value. - * @param rca: selected card address. - * @param pscr: pointer to the buffer that will contain the SCR value. - * @retval SD_Error: SD Card Error code. - */ -OPTIMIZE("O0") static SD_Error FindSCR(uint16_t rca, uint32_t *pscr) -{ - uint32_t index = 0; - SD_Error errorstatus = SD_OK; - uint32_t tempscr[2] = {0, 0}; - - /*!< Set Block Size To 8 Bytes */ - /*!< Send CMD55 APP_CMD with argument as card's RCA */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)8; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Send CMD55 APP_CMD with argument as card's RCA */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = 8; - SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_8b; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - - /*!< Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_SEND_SCR; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SD_APP_SEND_SCR); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - while (!(SDIO->STA & (SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) - { - if (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) - { - *(tempscr + index) = SDIO_ReadData(); - index++; - } - } - - if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); - errorstatus = SD_DATA_TIMEOUT; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); - errorstatus = SD_DATA_CRC_FAIL; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_RXOVERR); - errorstatus = SD_RX_OVERRUN; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_STBITERR); - errorstatus = SD_START_BIT_ERR; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - *(pscr + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); - - *(pscr) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); - - return(errorstatus); -} - -/** - * @brief Converts the number of bytes in power of two and returns the power. - * @param NumberOfBytes: number of bytes. - * @retval None - */ -// OPTIMIZE("O0") uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes) -// { -// uint8_t count = 0; - -// while (NumberOfBytes != 1) -// { -// NumberOfBytes >>= 1; -// count++; -// } -// return(count); -// } - -void SDIO_IRQHandler(void) -{ - DEBUG_INTERRUPT(INT_SDIO); - SD_ProcessIRQ(); -} - -void SD_SDIO_DMA_IRQHANDLER(void) -{ - DEBUG_INTERRUPT(INT_SDIO_DMA); - SD_ProcessDMAIRQ(); -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdio_sd.h" +#include "../../debug.h" + +/** + * @brief SDIO Static flags, TimeOut, FIFO Address + */ +#define SDIO_STATIC_FLAGS ((uint32_t)0x000005FF) +#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000) + +/** + * @brief Mask for errors Card Status R1 (OCR Register) + */ +#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) +#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000) +#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000) +#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000) +#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000) +#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) +#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) +#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000) +#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000) +#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000) +#define SD_OCR_CC_ERROR ((uint32_t)0x00100000) +#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) +#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) +#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) +#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000) +#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000) +#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000) +#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000) +#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008) +#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008) + +/** + * @brief Masks for R6 Response + */ +#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000) +#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000) +#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000) + +#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000) +#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) +#define SD_STD_CAPACITY ((uint32_t)0x00000000) +#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) + +#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) +#define SD_ALLZERO ((uint32_t)0x00000000) + +#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) +#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) +#define SD_CARD_LOCKED ((uint32_t)0x02000000) + +#define SD_DATATIMEOUT ((uint32_t)1000000) +#define SD_0TO7BITS ((uint32_t)0x000000FF) +#define SD_8TO15BITS ((uint32_t)0x0000FF00) +#define SD_16TO23BITS ((uint32_t)0x00FF0000) +#define SD_24TO31BITS ((uint32_t)0xFF000000) +#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) + +#define SD_HALFFIFO ((uint32_t)0x00000008) +#define SD_HALFFIFOBYTES ((uint32_t)0x00000020) + +/** + * @brief Command Class Supported + */ +#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080) +#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040) +#define SD_CCCC_ERASE ((uint32_t)0x00000020) + +/** + * @brief Following commands are SD Card Specific commands. + * SDIO_APP_CMD should be sent before sending these commands. + */ +#define SDIO_SEND_IF_COND ((uint32_t)0x00000008) + + +/** + * @brief SDIO Commands Index + */ +#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) +#define SD_CMD_SEND_OP_COND ((uint8_t)1) +#define SD_CMD_ALL_SEND_CID ((uint8_t)2) +#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */ +#define SD_CMD_SET_DSR ((uint8_t)4) +#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) +#define SD_CMD_HS_SWITCH ((uint8_t)6) +#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) +#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) +#define SD_CMD_SEND_CSD ((uint8_t)9) +#define SD_CMD_SEND_CID ((uint8_t)10) +#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD Card doesn't support it */ +#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) +#define SD_CMD_SEND_STATUS ((uint8_t)13) +#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) +#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) +#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) +#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) +#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) +#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) +#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< SD Card doesn't support it */ +#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< SD Card doesn't support it */ +#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) +#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) +#define SD_CMD_PROG_CID ((uint8_t)26) /*!< reserved for manufacturers */ +#define SD_CMD_PROG_CSD ((uint8_t)27) +#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) +#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) +#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) +#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< To set the address of the first write + block to be erased. (For SD card only) */ +#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< To set the address of the last write block of the + continuous range to be erased. (For SD card only) */ +#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< To set the address of the first write block to be erased. + (For MMC card only spec 3.31) */ + +#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< To set the address of the last write block of the + continuous range to be erased. (For MMC card only spec 3.31) */ + +#define SD_CMD_ERASE ((uint8_t)38) +#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD Card doesn't support it */ +#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD Card doesn't support it */ +#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) +#define SD_CMD_APP_CMD ((uint8_t)55) +#define SD_CMD_GEN_CMD ((uint8_t)56) +#define SD_CMD_NO_CMD ((uint8_t)64) + +/** + * @brief Following commands are SD Card Specific commands. + * SDIO_APP_CMD should be sent before sending these commands. + */ +#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< For SD Card only */ +#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< For SD Card only */ +#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< For SD Card only */ +#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O Card only */ +#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O Card only */ + +/** + * @brief Following commands are SD Card Specific security commands. + * SDIO_APP_CMD should be sent before sending these commands. + */ +#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD Card only */ +#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD Card only */ +#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD Card only */ +#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD Card only */ +#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD Card only */ + +/** + * @brief Supported SD Memory Cards + */ +#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) +#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) +#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) +#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) +#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) +#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) +#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) +#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) + + +/** + * @brief SD Card States + */ +typedef enum +{ + SD_CARD_READY = ((uint32_t)0x00000001), + SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), + SD_CARD_STANDBY = ((uint32_t)0x00000003), + SD_CARD_TRANSFER = ((uint32_t)0x00000004), + SD_CARD_SENDING = ((uint32_t)0x00000005), + SD_CARD_RECEIVING = ((uint32_t)0x00000006), + SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), + SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), + SD_CARD_ERROR = ((uint32_t)0x000000FF) +}SDCardState; + + + +static uint32_t CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; +static uint32_t CSD_Tab[4], CID_Tab[4], RCA = 0; +// static uint8_t SDSTATUS_Tab[16]; +__IO uint8_t StopCondition = 0; +__IO SD_Error TransferError = SD_OK; +__IO uint8_t TransferEnd = 0, DMAEndOfTransfer = 0; +SD_CardInfo SDCardInfo; + +SDIO_InitTypeDef SDIO_InitStructure; +SDIO_CmdInitTypeDef SDIO_CmdInitStructure; +SDIO_DataInitTypeDef SDIO_DataInitStructure; + +static SD_Error CmdError(void); +static SD_Error CmdResp1Error(uint8_t cmd); +static SD_Error CmdResp7Error(void); +static SD_Error CmdResp3Error(void); +static SD_Error CmdResp2Error(void); +static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca); +static SD_Error SDEnWideBus(FunctionalState NewState); +// static SD_Error IsCardProgramming(uint8_t *pstatus); +static SD_Error FindSCR(uint16_t rca, uint32_t *pscr); +// uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes); + +SD_Error SD_PowerON(void); +SDCardState SD_GetState(void); +SD_Error SD_InitializeCards(void); +SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo); +SD_Error SD_EnableWideBusOperation(uint32_t WideMode); +SD_Error SD_SelectDeselect(uint32_t addr); +SD_Error SD_StopTransfer(void); +SD_Error SD_SendStatus(uint32_t *pcardstatus); + + + + + + + + + + + + + + + +/** + * @brief DeInitializes the SDIO interface. + * @param None + * @retval None + */ +// void SD_LowLevel_DeInit(void) +// { +// GPIO_InitTypeDef GPIO_InitStructure; + +// /*!< Disable SDIO Clock */ +// SDIO_ClockCmd(DISABLE); + +// /*!< Set Power State to OFF */ +// SDIO_SetPowerState(SDIO_PowerState_OFF); + +// /*!< DeInitializes the SDIO peripheral */ +// SDIO_DeInit(); + +// /* Disable the SDIO APB2 Clock */ +// RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, DISABLE); + +// GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_MCO); +// GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_MCO); +// GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_MCO); +// GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_MCO); +// GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_MCO); +// GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_MCO); + +// /* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */ +// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11; +// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; +// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; +// GPIO_Init(GPIOC, &GPIO_InitStructure); + +// /* Configure PD.02 CMD line */ +// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; +// GPIO_Init(GPIOD, &GPIO_InitStructure); + +// /* Configure PC.12 pin: CLK pin */ +// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; +// GPIO_Init(GPIOC, &GPIO_InitStructure); +// } + +/** + * @brief Initializes the SD Card and put it into StandBy State (Ready for + * data transfer). + * @param None + * @retval None + */ +void SD_LowLevel_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_SDIO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_SDIO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_SDIO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_SDIO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_SDIO); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_SDIO); + + /* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Configure PD.02 CMD line */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* Configure PC.12 pin: CLK pin */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Enable the SDIO APB2 Clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE); + + // SDIO Interrupt ENABLE + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + // DMA2 STREAMx Interrupt ENABLE + NVIC_InitStructure.NVIC_IRQChannel = SD_SDIO_DMA_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_Init(&NVIC_InitStructure); +} + +/** + * @brief Configures the DMA2 Channel4 for SDIO Tx request. + * @param BufferSRC: pointer to the source buffer + * @param BufferSize: buffer size + * @retval None + */ +void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize) +{ + DMA_InitTypeDef SDDMA_InitStructure; + + DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF); + + /* DMA2 Stream3 or Stream6 disable */ + DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE); + + /* DMA2 Stream3 or Stream6 Config */ + DMA_DeInit(SD_SDIO_DMA_STREAM); + + SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL; + SDDMA_InitStructure.DMA_PeripheralBaseAddr = SD_SDIO_FIFO_ADDRESS; + SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferSRC; + SDDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + SDDMA_InitStructure.DMA_BufferSize = 1; + SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4; + SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; + DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure); + DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE); + DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral); + + /* DMA2 Stream3 or Stream6 enable */ + DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE); + +} + +/** + * @brief Configures the DMA2 Channel4 for SDIO Rx request. + * @param BufferDST: pointer to the destination buffer + * @param BufferSize: buffer size + * @retval None + */ +void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize) +{ + DMA_InitTypeDef SDDMA_InitStructure; + + DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF); + + /* DMA2 Stream3 or Stream6 disable */ + DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE); + + /* DMA2 Stream3 or Stream6 Config */ + DMA_DeInit(SD_SDIO_DMA_STREAM); + + SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL; + SDDMA_InitStructure.DMA_PeripheralBaseAddr = SD_SDIO_FIFO_ADDRESS; + SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferDST; + SDDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + SDDMA_InitStructure.DMA_BufferSize = 1; + SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4; + SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; + DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure); + DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE); + DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral); + + /* DMA2 Stream3 or Stream6 enable */ + DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE); +} + + +/** + * @} + */ + + +// /** @defgroup STM32F4_DISCOVERY_SDIO_SD_Private_Functions +// * @{ +// */ + +// * +// * @brief DeInitializes the SDIO interface. +// * @param None +// * @retval None + +// void SD_DeInit(void) +// { +// SD_LowLevel_DeInit(); +// } + +/** + * @brief Initializes the SD Card and put it into StandBy State (Ready for data + * transfer). + * @param None + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_Init(void) +{ + __IO SD_Error errorstatus = SD_OK; + + /* SDIO Peripheral Low Level Init */ + SD_LowLevel_Init(); + + SDIO_DeInit(); + + errorstatus = SD_PowerON(); + if (errorstatus != SD_OK) + { + TRACE("SD_PowerON() status=%d", errorstatus); + /*!< CMD Response TimeOut (wait for CMDSENT flag) */ + return(errorstatus); + } + + errorstatus = SD_InitializeCards(); + if (errorstatus != SD_OK) + { + TRACE("SD_InitializeCards() status=%d", errorstatus); + /*!< CMD Response TimeOut (wait for CMDSENT flag) */ + return(errorstatus); + } + + /*!< Configure the SDIO peripheral */ + /*!< SDIO_CK = SDIOCLK / (SDIO_TRANSFER_CLK_DIV + 2) */ + /*!< on STM32F4xx devices, SDIOCLK is fixed to 48MHz */ + SDIO_InitStructure.SDIO_ClockDiv = SD_SDIO_TRANSFER_CLK_DIV; + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + + /*----------------- Read CSD/CID MSD registers ------------------*/ + errorstatus = SD_GetCardInfo(&SDCardInfo); + + if (errorstatus == SD_OK) + { + /*----------------- Select Card --------------------------------*/ + errorstatus = SD_SelectDeselect((uint32_t) (SDCardInfo.RCA << 16)); + } + + if (errorstatus == SD_OK) + { + errorstatus = SD_EnableWideBusOperation(SDIO_BusWide_4b); + } + + return(errorstatus); +} + +/** + * @brief Gets the cuurent sd card data transfer status. + * @param None + * @retval SDTransferState: Data Transfer state. + * This value can be: + * - SD_TRANSFER_OK: No data transfer is acting + * - SD_TRANSFER_BUSY: Data transfer is acting + */ +SDTransferState SD_GetStatus(void) +{ + SDCardState cardstate = SD_CARD_TRANSFER; + + cardstate = SD_GetState(); + + if (cardstate == SD_CARD_TRANSFER) + { + return(SD_TRANSFER_OK); + } + else if(cardstate == SD_CARD_ERROR) + { + return (SD_TRANSFER_ERROR); + } + else + { + return(SD_TRANSFER_BUSY); + } +} + +/** + * @brief Returns the current card's state. + * @param None + * @retval SDCardState: SD Card Error or SD Card Current State. + */ +SDCardState SD_GetState(void) +{ + uint32_t resp1 = 0; + + if(SD_Detect()== SD_PRESENT) + { + if (SD_SendStatus(&resp1) != SD_OK) + { + return SD_CARD_ERROR; + } + else + { + return (SDCardState)((resp1 >> 9) & 0x0F); + } + } + else + { + return SD_CARD_ERROR; + } +} + +/** + * @brief Detect if SD card is correctly plugged in the memory slot. + * @param None + * @retval Return if SD is detected or not + */ +uint8_t SD_Detect(void) +{ + __IO uint8_t status = SD_PRESENT; + +#if 0 // TODO + /*!< Check GPIO to detect SD */ + if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_RESET) + { + status = SD_NOT_PRESENT; + } +#endif + + return status; +} + +//--------------------------------------------------------------------------------------- +//disable optimize +#define OPTIMIZE(level) __attribute__((optimize(level))) + +/** + * @brief Enquires cards about their operating voltage and configures + * clock controls. + * @param None + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_PowerON(void) +{ + __IO SD_Error errorstatus = SD_OK; + uint32_t response = 0, count = 0, validvoltage = 0; + uint32_t SDType = SD_STD_CAPACITY; + + /*!< Power ON Sequence -----------------------------------------------------*/ + /*!< Configure the SDIO peripheral */ + /*!< SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) */ + /*!< on STM32F4xx devices, SDIOCLK is fixed to 48MHz */ + /*!< SDIO_CK for initialization should not exceed 400 KHz */ + SDIO_InitStructure.SDIO_ClockDiv = SD_SDIO_INIT_CLK_DIV; + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + + /*!< Set Power State to ON */ + SDIO_SetPowerState(SDIO_PowerState_ON); + + /*!< Enable SDIO Clock */ + SDIO_ClockCmd(ENABLE); + + /*!< CMD0: GO_IDLE_STATE ---------------------------------------------------*/ + /*!< No CMD response required */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_GO_IDLE_STATE; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdError(); + + if (errorstatus != SD_OK) + { + TRACE("SD_CMD_GO_IDLE_STATE status=%d", errorstatus); + /*!< CMD Response TimeOut (wait for CMDSENT flag) */ + return(errorstatus); + } + + /*!< CMD8: SEND_IF_COND ----------------------------------------------------*/ + /*!< Send CMD8 to verify SD card interface operating condition */ + /*!< Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /*!< CMD Response: R7 */ + SDIO_CmdInitStructure.SDIO_Argument = SD_CHECK_PATTERN; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_IF_COND; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp7Error(); + + if (errorstatus == SD_OK) + { + CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; /*!< SD Card 2.0 */ + SDType = SD_HIGH_CAPACITY; + } + else + { + /*!< CMD55 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + } + /*!< CMD55 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + /*!< If errorstatus is Command TimeOut, it is a MMC card */ + /*!< If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) + or SD card 1.x */ + if (errorstatus == SD_OK) + { + /*!< SD CARD */ + /*!< Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)) + { + + /*!< SEND CMD55 APP_CMD with RCA as 0 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + if (errorstatus != SD_OK) + { + TRACE("SD_CMD_APP_CMD status=%d", errorstatus); + return(errorstatus); + } + SDIO_CmdInitStructure.SDIO_Argument = SD_VOLTAGE_WINDOW_SD | SDType; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_OP_COND; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp3Error(); + if (errorstatus != SD_OK) + { + TRACE("SD_CMD_SD_APP_OP_COND status=%d", errorstatus); + return(errorstatus); + } + + response = SDIO_GetResponse(SDIO_RESP1); + validvoltage = (((response >> 31) == 1) ? 1 : 0); + count++; + } + if (count >= SD_MAX_VOLT_TRIAL) + { + errorstatus = SD_INVALID_VOLTRANGE; + return(errorstatus); + } + + if (response &= SD_HIGH_CAPACITY) + { + CardType = SDIO_HIGH_CAPACITY_SD_CARD; + } + + }/*!< else MMC Card */ + + return(errorstatus); +} + +/** + * @brief Turns the SDIO output signals off. + * @param None + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_PowerOFF(void) +{ + SD_Error errorstatus = SD_OK; + + /*!< Set Power State to OFF */ + SDIO_SetPowerState(SDIO_PowerState_OFF); + + return(errorstatus); +} + +/** + * @brief Intialises all cards or single card as the case may be Card(s) come + * into standby state. + * @param None + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_InitializeCards(void) +{ + SD_Error errorstatus = SD_OK; + uint16_t rca = 0x01; + + if (SDIO_GetPowerState() == SDIO_PowerState_OFF) + { + errorstatus = SD_REQUEST_NOT_APPLICABLE; + return(errorstatus); + } + + if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) + { + /*!< Send CMD2 ALL_SEND_CID */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ALL_SEND_CID; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp2Error(); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + CID_Tab[0] = SDIO_GetResponse(SDIO_RESP1); + CID_Tab[1] = SDIO_GetResponse(SDIO_RESP2); + CID_Tab[2] = SDIO_GetResponse(SDIO_RESP3); + CID_Tab[3] = SDIO_GetResponse(SDIO_RESP4); + } + if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_SECURE_DIGITAL_IO_COMBO_CARD == CardType) + || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) + { + /*!< Send CMD3 SET_REL_ADDR with argument 0 */ + /*!< SD Card publishes its RCA. */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_REL_ADDR; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp6Error(SD_CMD_SET_REL_ADDR, &rca); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + } + + if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) + { + RCA = rca; + + /*!< Send CMD9 SEND_CSD with argument as card's RCA */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)(rca << 16); + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_CSD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp2Error(); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + CSD_Tab[0] = SDIO_GetResponse(SDIO_RESP1); + CSD_Tab[1] = SDIO_GetResponse(SDIO_RESP2); + CSD_Tab[2] = SDIO_GetResponse(SDIO_RESP3); + CSD_Tab[3] = SDIO_GetResponse(SDIO_RESP4); + } + + errorstatus = SD_OK; /*!< All cards get intialized */ + + return(errorstatus); +} + +/** + * @brief Returns information about specific card. + * @param cardinfo: pointer to a SD_CardInfo structure that contains all SD card + * information. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo) +{ + SD_Error errorstatus = SD_OK; + uint8_t tmp = 0; + + cardinfo->CardType = (uint8_t)CardType; + cardinfo->RCA = (uint16_t)RCA; + + /*!< Byte 0 */ + tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24); + cardinfo->SD_csd.CSDStruct = (tmp & 0xC0) >> 6; + cardinfo->SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2; + cardinfo->SD_csd.Reserved1 = tmp & 0x03; + + /*!< Byte 1 */ + tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16); + cardinfo->SD_csd.TAAC = tmp; + + /*!< Byte 2 */ + tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8); + cardinfo->SD_csd.NSAC = tmp; + + /*!< Byte 3 */ + tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF); + cardinfo->SD_csd.MaxBusClkFrec = tmp; + + /*!< Byte 4 */ + tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24); + cardinfo->SD_csd.CardComdClasses = tmp << 4; + + /*!< Byte 5 */ + tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16); + cardinfo->SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4; + cardinfo->SD_csd.RdBlockLen = tmp & 0x0F; + + /*!< Byte 6 */ + tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8); + cardinfo->SD_csd.PartBlockRead = (tmp & 0x80) >> 7; + cardinfo->SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6; + cardinfo->SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5; + cardinfo->SD_csd.DSRImpl = (tmp & 0x10) >> 4; + cardinfo->SD_csd.Reserved2 = 0; /*!< Reserved */ + + if ((CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || (CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) + { + cardinfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; + + /*!< Byte 7 */ + tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); + cardinfo->SD_csd.DeviceSize |= (tmp) << 2; + + /*!< Byte 8 */ + tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); + cardinfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; + + cardinfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; + cardinfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); + + /*!< Byte 9 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); + cardinfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; + cardinfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; + cardinfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; + /*!< Byte 10 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); + cardinfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; + + cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ; + cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2)); + cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen); + cardinfo->CardCapacity *= cardinfo->CardBlockSize; + } + else if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + /*!< Byte 7 */ + tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); + cardinfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; + + /*!< Byte 8 */ + tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); + + cardinfo->SD_csd.DeviceSize |= (tmp << 8); + + /*!< Byte 9 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); + + cardinfo->SD_csd.DeviceSize |= (tmp); + + /*!< Byte 10 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); + + cardinfo->CardCapacity = ((uint64_t)cardinfo->SD_csd.DeviceSize + 1) * 512 * 1024; + cardinfo->CardBlockSize = 512; + } + + + cardinfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; + cardinfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; + + /*!< Byte 11 */ + tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF); + cardinfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; + cardinfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); + + /*!< Byte 12 */ + tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24); + cardinfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; + cardinfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; + cardinfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; + cardinfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; + + /*!< Byte 13 */ + tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16); + cardinfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; + cardinfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; + cardinfo->SD_csd.Reserved3 = 0; + cardinfo->SD_csd.ContentProtectAppli = (tmp & 0x01); + + /*!< Byte 14 */ + tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8); + cardinfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; + cardinfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6; + cardinfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5; + cardinfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4; + cardinfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2; + cardinfo->SD_csd.ECC = (tmp & 0x03); + + /*!< Byte 15 */ + tmp = (uint8_t)(CSD_Tab[3] & 0x000000FF); + cardinfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1; + cardinfo->SD_csd.Reserved4 = 1; + + + /*!< Byte 0 */ + tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24); + cardinfo->SD_cid.ManufacturerID = tmp; + + /*!< Byte 1 */ + tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16); + cardinfo->SD_cid.OEM_AppliID = tmp << 8; + + /*!< Byte 2 */ + tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8); + cardinfo->SD_cid.OEM_AppliID |= tmp; + + /*!< Byte 3 */ + tmp = (uint8_t)(CID_Tab[0] & 0x000000FF); + cardinfo->SD_cid.ProdName1 = tmp << 24; + + /*!< Byte 4 */ + tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24); + cardinfo->SD_cid.ProdName1 |= tmp << 16; + + /*!< Byte 5 */ + tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16); + cardinfo->SD_cid.ProdName1 |= tmp << 8; + + /*!< Byte 6 */ + tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8); + cardinfo->SD_cid.ProdName1 |= tmp; + + /*!< Byte 7 */ + tmp = (uint8_t)(CID_Tab[1] & 0x000000FF); + cardinfo->SD_cid.ProdName2 = tmp; + + /*!< Byte 8 */ + tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24); + cardinfo->SD_cid.ProdRev = tmp; + + /*!< Byte 9 */ + tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16); + cardinfo->SD_cid.ProdSN = tmp << 24; + + /*!< Byte 10 */ + tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8); + cardinfo->SD_cid.ProdSN |= tmp << 16; + + /*!< Byte 11 */ + tmp = (uint8_t)(CID_Tab[2] & 0x000000FF); + cardinfo->SD_cid.ProdSN |= tmp << 8; + + /*!< Byte 12 */ + tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24); + cardinfo->SD_cid.ProdSN |= tmp; + + /*!< Byte 13 */ + tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16); + cardinfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; + cardinfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8; + + /*!< Byte 14 */ + tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8); + cardinfo->SD_cid.ManufactDate |= tmp; + + /*!< Byte 15 */ + tmp = (uint8_t)(CID_Tab[3] & 0x000000FF); + cardinfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; + cardinfo->SD_cid.Reserved2 = 1; + + return(errorstatus); +} + +/** + * @brief Enables wide bus opeartion for the requeseted card if supported by + * card. + * @param WideMode: Specifies the SD card wide bus mode. + * This parameter can be one of the following values: + * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) + * @arg SDIO_BusWide_4b: 4-bit data transfer + * @arg SDIO_BusWide_1b: 1-bit data transfer + * @retval SD_Error: SD Card Error code. + */ +// OPTIMIZE("O0") SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus) +// { +// SD_Error errorstatus = SD_OK; +// uint8_t tmp = 0; + +// errorstatus = SD_SendSDStatus((uint32_t *)SDSTATUS_Tab); + +// if (errorstatus != SD_OK) +// { +// return(errorstatus); +// } + +// /*!< Byte 0 */ +// tmp = (uint8_t)((SDSTATUS_Tab[0] & 0xC0) >> 6); +// cardstatus->DAT_BUS_WIDTH = tmp; + +// /*!< Byte 0 */ +// tmp = (uint8_t)((SDSTATUS_Tab[0] & 0x20) >> 5); +// cardstatus->SECURED_MODE = tmp; + +// /*!< Byte 2 */ +// tmp = (uint8_t)((SDSTATUS_Tab[2] & 0xFF)); +// cardstatus->SD_CARD_TYPE = tmp << 8; + +// /*!< Byte 3 */ +// tmp = (uint8_t)((SDSTATUS_Tab[3] & 0xFF)); +// cardstatus->SD_CARD_TYPE |= tmp; + +// /*!< Byte 4 */ +// tmp = (uint8_t)(SDSTATUS_Tab[4] & 0xFF); +// cardstatus->SIZE_OF_PROTECTED_AREA = tmp << 24; + +// /*!< Byte 5 */ +// tmp = (uint8_t)(SDSTATUS_Tab[5] & 0xFF); +// cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 16; + +// /*!< Byte 6 */ +// tmp = (uint8_t)(SDSTATUS_Tab[6] & 0xFF); +// cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 8; + +// /*!< Byte 7 */ +// tmp = (uint8_t)(SDSTATUS_Tab[7] & 0xFF); +// cardstatus->SIZE_OF_PROTECTED_AREA |= tmp; + +// /*!< Byte 8 */ +// tmp = (uint8_t)((SDSTATUS_Tab[8] & 0xFF)); +// cardstatus->SPEED_CLASS = tmp; + +// /*!< Byte 9 */ +// tmp = (uint8_t)((SDSTATUS_Tab[9] & 0xFF)); +// cardstatus->PERFORMANCE_MOVE = tmp; + +// /*!< Byte 10 */ +// tmp = (uint8_t)((SDSTATUS_Tab[10] & 0xF0) >> 4); +// cardstatus->AU_SIZE = tmp; + +// /*!< Byte 11 */ +// tmp = (uint8_t)(SDSTATUS_Tab[11] & 0xFF); +// cardstatus->ERASE_SIZE = tmp << 8; + +// /*!< Byte 12 */ +// tmp = (uint8_t)(SDSTATUS_Tab[12] & 0xFF); +// cardstatus->ERASE_SIZE |= tmp; + +// /*!< Byte 13 */ +// tmp = (uint8_t)((SDSTATUS_Tab[13] & 0xFC) >> 2); +// cardstatus->ERASE_TIMEOUT = tmp; + +// /*!< Byte 13 */ +// tmp = (uint8_t)((SDSTATUS_Tab[13] & 0x3)); +// cardstatus->ERASE_OFFSET = tmp; + +// return(errorstatus); +// } + +/** + * @brief Enables wide bus opeartion for the requeseted card if supported by + * card. + * @param WideMode: Specifies the SD card wide bus mode. + * This parameter can be one of the following values: + * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) + * @arg SDIO_BusWide_4b: 4-bit data transfer + * @arg SDIO_BusWide_1b: 1-bit data transfer + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_EnableWideBusOperation(uint32_t WideMode) +{ + SD_Error errorstatus = SD_OK; + + /*!< MMC Card doesn't support this feature */ + if (SDIO_MULTIMEDIA_CARD == CardType) + { + errorstatus = SD_UNSUPPORTED_FEATURE; + return(errorstatus); + } + else if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) + { + if (SDIO_BusWide_8b == WideMode) + { + errorstatus = SD_UNSUPPORTED_FEATURE; + return(errorstatus); + } + else if (SDIO_BusWide_4b == WideMode) + { + errorstatus = SDEnWideBus(ENABLE); + + if (SD_OK == errorstatus) + { + /*!< Configure the SDIO peripheral */ + SDIO_InitStructure.SDIO_ClockDiv = SD_SDIO_TRANSFER_CLK_DIV; + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + } + } + else + { + errorstatus = SDEnWideBus(DISABLE); + + if (SD_OK == errorstatus) + { + /*!< Configure the SDIO peripheral */ + SDIO_InitStructure.SDIO_ClockDiv = SD_SDIO_TRANSFER_CLK_DIV; + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + } + } + } + + return(errorstatus); +} + +/** + * @brief Selects od Deselects the corresponding card. + * @param addr: Address of the Card to be selected. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_SelectDeselect(uint32_t addr) +{ + SD_Error errorstatus = SD_OK; + + /*!< Send CMD7 SDIO_SEL_DESEL_CARD */ + SDIO_CmdInitStructure.SDIO_Argument = addr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEL_DESEL_CARD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SEL_DESEL_CARD); + + return(errorstatus); +} + +/** + * @brief Allows to read one block from a specified address in a card. The Data + * transfer can be managed by DMA mode or Polling mode. + * @note This operation should be followed by two functions to check if the + * DMA Controller and SD Card status. + * - SD_ReadWaitOperation(): this function insure that the DMA + * controller has finished all data transfer. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. + * @param readbuff: pointer to the buffer that will contain the received data + * @param ReadAddr: Address from where data are to be read. + * @param BlockSize: the SD card Data block size. The Block size should be 512. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize) +{ + SD_Error errorstatus = SD_OK; + + TransferError = SD_OK; + TransferEnd = 0; + StopCondition = 0; + DMAEndOfTransfer = 0; + + SDIO->DCTRL = 0x0; + + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); + SDIO_DMACmd(ENABLE); + SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, BlockSize); + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + BlockSize = 512; + else + ReadAddr *= 512; + + /* Set Block Size for Card */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_512b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + /*!< Send CMD17 READ_SINGLE_BLOCK */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_SINGLE_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_READ_SINGLE_BLOCK); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + return(errorstatus); +} + +/** + * @brief Allows to read blocks from a specified address in a card. The Data + * transfer can be managed by DMA mode or Polling mode. + * @note This operation should be followed by two functions to check if the + * DMA Controller and SD Card status. + * - SD_ReadWaitOperation(): this function insure that the DMA + * controller has finished all data transfer. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. + * @param readbuff: pointer to the buffer that will contain the received data. + * @param ReadAddr: Address from where data are to be read. + * @param BlockSize: the SD card Data block size. The Block size should be 512. + * @param NumberOfBlocks: number of blocks to be read. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) +{ + SD_Error errorstatus = SD_OK; + TransferError = SD_OK; + TransferEnd = 0; + StopCondition = 1; + DMAEndOfTransfer = 0; + + SDIO->DCTRL = 0x0; + + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); + SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, (NumberOfBlocks * BlockSize)); + SDIO_DMACmd(ENABLE); + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + BlockSize = 512; + else + ReadAddr *= 512; + + /*!< Set Block Size for Card */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT * NumberOfBlocks; + SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_512b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + /*!< Send CMD18 READ_MULT_BLOCK with argument data address */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_MULT_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_READ_MULT_BLOCK); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + return(errorstatus); +} + +/** + * @brief This function waits until the SDIO DMA data transfer is finished. + * This function should be called after SDIO_ReadMultiBlocks() function + * to insure that all data sent by the card are already transferred by + * the DMA controller. + * @param None. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_WaitReadOperation(uint32_t timeout) +{ + SD_Error errorstatus = SD_OK; + + while (!DMAEndOfTransfer && !TransferEnd && (TransferError == SD_OK) && (timeout > 0)) + { + delay_ms(1); + timeout--; + } + TRACE_SD_CARD_EVENT((timeout == 0), sd_wait_read, (TransferError << 8) + (DMAEndOfTransfer << 1) + TransferEnd); + + DMAEndOfTransfer = 0; + + timeout = 100; + + while(((SDIO->STA & SDIO_FLAG_RXACT)) && (timeout > 0)) + { + delay_ms(1); + timeout--; + } + TRACE_SD_CARD_EVENT((timeout == 0), sd_wait_read, -1); + + if (StopCondition == 1) + { + errorstatus = SD_StopTransfer(); + StopCondition = 0; + } + + if ((timeout == 0) && (errorstatus == SD_OK)) + { + errorstatus = SD_DATA_TIMEOUT; + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + if (TransferError != SD_OK) + { + return(TransferError); + } + else + { + return(errorstatus); + } +} + +/** + * @brief Allows to write one block starting from a specified address in a card. + * The Data transfer can be managed by DMA mode or Polling mode. + * @note This operation should be followed by two functions to check if the + * DMA Controller and SD Card status. + * - SD_ReadWaitOperation(): this function insure that the DMA + * controller has finished all data transfer. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. + * @param writebuff: pointer to the buffer that contain the data to be transferred. + * @param WriteAddr: Address from where data are to be read. + * @param BlockSize: the SD card Data block size. The Block size should be 512. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize) +{ + SD_Error errorstatus = SD_OK; + + TransferError = SD_OK; + TransferEnd = 0; + StopCondition = 0; + + SDIO->DCTRL = 0x0; + + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); + SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, BlockSize); + SDIO_DMACmd(ENABLE); + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + BlockSize = 512; + else + WriteAddr *= 512; + + /* Set Block Size for Card */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + /*!< Send CMD24 WRITE_SINGLE_BLOCK */ + SDIO_CmdInitStructure.SDIO_Argument = WriteAddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_WRITE_SINGLE_BLOCK); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_512b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + return(errorstatus); +} + +/** + * @brief Allows to write blocks starting from a specified address in a card. + * The Data transfer can be managed by DMA mode only. + * @note This operation should be followed by two functions to check if the + * DMA Controller and SD Card status. + * - SD_ReadWaitOperation(): this function insure that the DMA + * controller has finished all data transfer. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. + * @param WriteAddr: Address from where data are to be read. + * @param writebuff: pointer to the buffer that contain the data to be transferred. + * @param BlockSize: the SD card Data block size. The Block size should be 512. + * @param NumberOfBlocks: number of blocks to be written. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) +{ + SD_Error errorstatus = SD_OK; + + TransferError = SD_OK; + TransferEnd = 0; + StopCondition = 1; + + SDIO->DCTRL = 0x0; + + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR, ENABLE); + SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, (NumberOfBlocks * BlockSize)); + SDIO_DMACmd(ENABLE); + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) { + BlockSize = 512; + } + else { + WriteAddr *= 512; + } + + /* Set Block Size for Card */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + /*!< To improve performance */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) (RCA << 16); + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + /*!< To improve performance */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)NumberOfBlocks; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCK_COUNT; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCK_COUNT); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + + /*!< Send CMD25 WRITE_MULT_BLOCK with argument data address */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)WriteAddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_MULT_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_WRITE_MULT_BLOCK); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT * NumberOfBlocks; + SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_512b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + return(errorstatus); +} + + +/** + * @brief This function waits until the SDIO DMA data transfer is finished. + * This function should be called after SDIO_WriteBlock() and + * SDIO_WriteMultiBlocks() function to insure that all data sent by the + * card are already transferred by the DMA controller. + * @param None. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_WaitWriteOperation(uint32_t timeout) +{ + SD_Error errorstatus = SD_OK; + + while (!DMAEndOfTransfer && !TransferEnd && (TransferError == SD_OK) && (timeout > 0)) + { + delay_ms(1); + timeout--; + } + TRACE_SD_CARD_EVENT((timeout == 0), sd_wait_write, (TransferError << 8) + (DMAEndOfTransfer << 1) + TransferEnd); + + DMAEndOfTransfer = 0; + + timeout = 100; + + while(((SDIO->STA & SDIO_FLAG_TXACT)) && (timeout > 0)) + { + delay_ms(1); + timeout--; + } + TRACE_SD_CARD_EVENT((timeout == 0), sd_wait_write, -1); + + if (StopCondition == 1) + { + errorstatus = SD_StopTransfer(); + StopCondition = 0; + } + + if ((timeout == 0) && (errorstatus == SD_OK)) + { + errorstatus = SD_DATA_TIMEOUT; + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + if (TransferError != SD_OK) + { + return(TransferError); + } + else + { + return(errorstatus); + } +} + +/** + * @brief Gets the cuurent data transfer state. + * @param None + * @retval SDTransferState: Data Transfer state. + * This value can be: + * - SD_TRANSFER_OK: No data transfer is acting + * - SD_TRANSFER_BUSY: Data transfer is acting + */ +OPTIMIZE("O0") SDTransferState SD_GetTransferState(void) +{ + if (SDIO->STA & (SDIO_FLAG_TXACT | SDIO_FLAG_RXACT)) + { + return(SD_TRANSFER_BUSY); + } + else + { + return(SD_TRANSFER_OK); + } +} + +/** + * @brief Aborts an ongoing data transfer. + * @param None + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_StopTransfer(void) +{ + SD_Error errorstatus = SD_OK; + + /*!< Send CMD12 STOP_TRANSMISSION */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_STOP_TRANSMISSION; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_STOP_TRANSMISSION); + + return(errorstatus); +} + +/** + * @brief Allows to erase memory area specified for the given card. + * @param startaddr: the start address. + * @param endaddr: the end address. + * @retval SD_Error: SD Card Error code. + */ +// OPTIMIZE("O0") SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr) +// { +// SD_Error errorstatus = SD_OK; +// uint32_t delay = 0; +// __IO uint32_t maxdelay = 0; +// uint8_t cardstate = 0; + +// /*!< Check if the card coomnd class supports erase command */ +// if (((CSD_Tab[1] >> 20) & SD_CCCC_ERASE) == 0) +// { +// errorstatus = SD_REQUEST_NOT_APPLICABLE; +// return(errorstatus); +// } + +// maxdelay = 120000 / ((SDIO->CLKCR & 0xFF) + 2); + +// if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) +// { +// errorstatus = SD_LOCK_UNLOCK_FAILED; +// return(errorstatus); +// } + +// if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) +// { +// startaddr /= 512; +// endaddr /= 512; +// } + +// /*!< According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ +// if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) +// { +// /*!< Send CMD32 SD_ERASE_GRP_START with argument as addr */ +// SDIO_CmdInitStructure.SDIO_Argument = startaddr; +// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_START; +// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; +// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; +// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; +// SDIO_SendCommand(&SDIO_CmdInitStructure); + +// errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_START); +// if (errorstatus != SD_OK) +// { +// return(errorstatus); +// } + +// /*!< Send CMD33 SD_ERASE_GRP_END with argument as addr */ +// SDIO_CmdInitStructure.SDIO_Argument = endaddr; +// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_END; +// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; +// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; +// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; +// SDIO_SendCommand(&SDIO_CmdInitStructure); + +// errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_END); +// if (errorstatus != SD_OK) +// { +// return(errorstatus); +// } +// } + +// /*!< Send CMD38 ERASE */ +// SDIO_CmdInitStructure.SDIO_Argument = 0; +// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ERASE; +// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; +// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; +// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; +// SDIO_SendCommand(&SDIO_CmdInitStructure); + +// errorstatus = CmdResp1Error(SD_CMD_ERASE); + +// if (errorstatus != SD_OK) +// { +// return(errorstatus); +// } + +// for (delay = 0; delay < maxdelay; delay++) +// {} + +// /*!< Wait till the card is in programming state */ +// errorstatus = IsCardProgramming(&cardstate); +// delay = SD_DATATIMEOUT; +// while ((delay > 0) && (errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate))) +// { +// errorstatus = IsCardProgramming(&cardstate); +// delay--; +// } + +// return(errorstatus); +// } + +/** + * @brief Returns the current card's status. + * @param pcardstatus: pointer to the buffer that will contain the SD card + * status (Card Status register). + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") SD_Error SD_SendStatus(uint32_t *pcardstatus) +{ + SD_Error errorstatus = SD_OK; + + if (pcardstatus == NULL) + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SEND_STATUS); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + *pcardstatus = SDIO_GetResponse(SDIO_RESP1); + + return(errorstatus); +} + +/** + * @brief Returns the current SD card's status. + * @param psdstatus: pointer to the buffer that will contain the SD card status + * (SD Status register). + * @retval SD_Error: SD Card Error code. + */ +// OPTIMIZE("O0") SD_Error SD_SendSDStatus(uint32_t *psdstatus) +// { +// SD_Error errorstatus = SD_OK; +// uint32_t count = 0; + +// if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) +// { +// errorstatus = SD_LOCK_UNLOCK_FAILED; +// return(errorstatus); +// } + +// /*!< Set block size for card if it is not equal to current block size for card. */ +// SDIO_CmdInitStructure.SDIO_Argument = 64; +// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; +// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; +// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; +// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; +// SDIO_SendCommand(&SDIO_CmdInitStructure); + +// errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + +// if (errorstatus != SD_OK) +// { +// return(errorstatus); +// } + +// /*!< CMD55 */ +// SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; +// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; +// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; +// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; +// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; +// SDIO_SendCommand(&SDIO_CmdInitStructure); +// errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + +// if (errorstatus != SD_OK) +// { +// return(errorstatus); +// } + +// SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; +// SDIO_DataInitStructure.SDIO_DataLength = 64; +// SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b; +// SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; +// SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; +// SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; +// SDIO_DataConfig(&SDIO_DataInitStructure); + +// /*!< Send ACMD13 SD_APP_STAUS with argument as card's RCA.*/ +// SDIO_CmdInitStructure.SDIO_Argument = 0; +// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_STAUS; +// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; +// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; +// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; +// SDIO_SendCommand(&SDIO_CmdInitStructure); +// errorstatus = CmdResp1Error(SD_CMD_SD_APP_STAUS); + +// if (errorstatus != SD_OK) +// { +// return(errorstatus); +// } + +// while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) +// { +// if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) +// { +// for (count = 0; count < 8; count++) +// { +// *(psdstatus + count) = SDIO_ReadData(); +// } +// psdstatus += 8; +// } +// } + +// if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) +// { +// SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); +// errorstatus = SD_DATA_TIMEOUT; +// return(errorstatus); +// } +// else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) +// { +// SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); +// errorstatus = SD_DATA_CRC_FAIL; +// return(errorstatus); +// } +// else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) +// { +// SDIO_ClearFlag(SDIO_FLAG_RXOVERR); +// errorstatus = SD_RX_OVERRUN; +// return(errorstatus); +// } +// else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) +// { +// SDIO_ClearFlag(SDIO_FLAG_STBITERR); +// errorstatus = SD_START_BIT_ERR; +// return(errorstatus); +// } + +// count = SD_DATATIMEOUT; +// while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0)) +// { +// *psdstatus = SDIO_ReadData(); +// psdstatus++; +// count--; +// } +// /*!< Clear all the static status flags*/ +// SDIO_ClearFlag(SDIO_STATIC_FLAGS); + +// return(errorstatus); +// } + +/** + * @brief Allows to process all the interrupts that are high. + * @param None + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") void SD_ProcessIRQ(void) +{ + if (SDIO_GetITStatus(SDIO_IT_DATAEND) != RESET) + { + TransferError = SD_OK; + SDIO_ClearITPendingBit(SDIO_IT_DATAEND); + TransferEnd = 1; + } + else if (SDIO_GetITStatus(SDIO_IT_DCRCFAIL) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_DCRCFAIL); + TransferError = SD_DATA_CRC_FAIL; + } + else if (SDIO_GetITStatus(SDIO_IT_DTIMEOUT) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_DTIMEOUT); + TransferError = SD_DATA_TIMEOUT; + } + else if (SDIO_GetITStatus(SDIO_IT_RXOVERR) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_RXOVERR); + TransferError = SD_RX_OVERRUN; + } + else if (SDIO_GetITStatus(SDIO_IT_TXUNDERR) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_TXUNDERR); + TransferError = SD_TX_UNDERRUN; + } + else if (SDIO_GetITStatus(SDIO_IT_STBITERR) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_STBITERR); + TransferError = SD_START_BIT_ERR; + } + + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | + SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR | + SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE); + + TRACE_SD_CARD_EVENT((TransferError != SD_OK), sd_irq, TransferError); +} + +/** + * @brief This function waits until the SDIO DMA data transfer is finished. + * @param None. + * @retval None. + */ +OPTIMIZE("O0") void SD_ProcessDMAIRQ(void) +{ + if(DMA2->LISR & SD_SDIO_DMA_FLAG_TCIF) + { + DMAEndOfTransfer = 1; + DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_TCIF|SD_SDIO_DMA_FLAG_FEIF); + } +} + +/** + * @brief Checks for error conditions for CMD0. + * @param None + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") static SD_Error CmdError(void) +{ + SD_Error errorstatus = SD_OK; + uint32_t timeout; + + timeout = SDIO_CMD0TIMEOUT; /*!< 10000 */ + + while ((timeout > 0) && (SDIO_GetFlagStatus(SDIO_FLAG_CMDSENT) == RESET)) + { + timeout--; + } + + if (timeout == 0) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + return(errorstatus); + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + return(errorstatus); +} + +/** + * @brief Checks for error conditions for R7 response. + * @param None + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") static SD_Error CmdResp7Error(void) +{ + SD_Error errorstatus = SD_OK; + uint32_t status; + uint32_t timeout = SDIO_CMD0TIMEOUT; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) && (timeout > 0)) + { + timeout--; + status = SDIO->STA; + } + + if ((timeout == 0) || (status & SDIO_FLAG_CTIMEOUT)) + { + /*!< Card is not V2.0 complient or card does not support the set voltage range */ + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + + if (status & SDIO_FLAG_CMDREND) + { + /*!< Card is SD V2.0 compliant */ + errorstatus = SD_OK; + SDIO_ClearFlag(SDIO_FLAG_CMDREND); + return(errorstatus); + } + return(errorstatus); +} + +/** + * @brief Checks for error conditions for R1 response. + * @param cmd: The sent command index. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") static SD_Error CmdResp1Error(uint8_t cmd) +{ + SD_Error errorstatus = SD_OK; + uint32_t status; + uint32_t response_r1; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + else if (status & SDIO_FLAG_CCRCFAIL) + { + errorstatus = SD_CMD_CRC_FAIL; + SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); + return(errorstatus); + } + + /*!< Check response received is of desired command */ + if (SDIO_GetCommandResponse() != cmd) + { + errorstatus = SD_ILLEGAL_CMD; + return(errorstatus); + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + /*!< We have received response, retrieve it for analysis */ + response_r1 = SDIO_GetResponse(SDIO_RESP1); + + if ((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO) + { + return(errorstatus); + } + + if (response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) + { + return(SD_ADDR_OUT_OF_RANGE); + } + + if (response_r1 & SD_OCR_ADDR_MISALIGNED) + { + return(SD_ADDR_MISALIGNED); + } + + if (response_r1 & SD_OCR_BLOCK_LEN_ERR) + { + return(SD_BLOCK_LEN_ERR); + } + + if (response_r1 & SD_OCR_ERASE_SEQ_ERR) + { + return(SD_ERASE_SEQ_ERR); + } + + if (response_r1 & SD_OCR_BAD_ERASE_PARAM) + { + return(SD_BAD_ERASE_PARAM); + } + + if (response_r1 & SD_OCR_WRITE_PROT_VIOLATION) + { + return(SD_WRITE_PROT_VIOLATION); + } + + if (response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) + { + return(SD_LOCK_UNLOCK_FAILED); + } + + if (response_r1 & SD_OCR_COM_CRC_FAILED) + { + return(SD_COM_CRC_FAILED); + } + + if (response_r1 & SD_OCR_ILLEGAL_CMD) + { + return(SD_ILLEGAL_CMD); + } + + if (response_r1 & SD_OCR_CARD_ECC_FAILED) + { + return(SD_CARD_ECC_FAILED); + } + + if (response_r1 & SD_OCR_CC_ERROR) + { + return(SD_CC_ERROR); + } + + if (response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) + { + return(SD_GENERAL_UNKNOWN_ERROR); + } + + if (response_r1 & SD_OCR_STREAM_READ_UNDERRUN) + { + return(SD_STREAM_READ_UNDERRUN); + } + + if (response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) + { + return(SD_STREAM_WRITE_OVERRUN); + } + + if (response_r1 & SD_OCR_CID_CSD_OVERWRIETE) + { + return(SD_CID_CSD_OVERWRITE); + } + + if (response_r1 & SD_OCR_WP_ERASE_SKIP) + { + return(SD_WP_ERASE_SKIP); + } + + if (response_r1 & SD_OCR_CARD_ECC_DISABLED) + { + return(SD_CARD_ECC_DISABLED); + } + + if (response_r1 & SD_OCR_ERASE_RESET) + { + return(SD_ERASE_RESET); + } + + if (response_r1 & SD_OCR_AKE_SEQ_ERROR) + { + return(SD_AKE_SEQ_ERROR); + } + return(errorstatus); +} + +/** + * @brief Checks for error conditions for R3 (OCR) response. + * @param None + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") static SD_Error CmdResp3Error(void) +{ + SD_Error errorstatus = SD_OK; + uint32_t status; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + return(errorstatus); +} + +/** + * @brief Checks for error conditions for R2 (CID or CSD) response. + * @param None + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") static SD_Error CmdResp2Error(void) +{ + SD_Error errorstatus = SD_OK; + uint32_t status; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + else if (status & SDIO_FLAG_CCRCFAIL) + { + errorstatus = SD_CMD_CRC_FAIL; + SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); + return(errorstatus); + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + return(errorstatus); +} + +/** + * @brief Checks for error conditions for R6 (RCA) response. + * @param cmd: The sent command index. + * @param prca: pointer to the variable that will contain the SD card relative + * address RCA. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca) +{ + SD_Error errorstatus = SD_OK; + uint32_t status; + uint32_t response_r1; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + else if (status & SDIO_FLAG_CCRCFAIL) + { + errorstatus = SD_CMD_CRC_FAIL; + SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); + return(errorstatus); + } + + /*!< Check response received is of desired command */ + if (SDIO_GetCommandResponse() != cmd) + { + errorstatus = SD_ILLEGAL_CMD; + return(errorstatus); + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + /*!< We have received response, retrieve it. */ + response_r1 = SDIO_GetResponse(SDIO_RESP1); + + if (SD_ALLZERO == (response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) + { + *prca = (uint16_t) (response_r1 >> 16); + return(errorstatus); + } + + if (response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) + { + return(SD_GENERAL_UNKNOWN_ERROR); + } + + if (response_r1 & SD_R6_ILLEGAL_CMD) + { + return(SD_ILLEGAL_CMD); + } + + if (response_r1 & SD_R6_COM_CRC_FAILED) + { + return(SD_COM_CRC_FAILED); + } + + return(errorstatus); +} + +/** + * @brief Enables or disables the SDIO wide bus mode. + * @param NewState: new state of the SDIO wide bus mode. + * This parameter can be: ENABLE or DISABLE. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") static SD_Error SDEnWideBus(FunctionalState NewState) +{ + SD_Error errorstatus = SD_OK; + + uint32_t scr[2] = {0, 0}; + + if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) + { + errorstatus = SD_LOCK_UNLOCK_FAILED; + return(errorstatus); + } + + /*!< Get SCR Register */ + errorstatus = FindSCR(RCA, scr); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /*!< If wide bus operation to be enabled */ + if (NewState == ENABLE) + { + /*!< If requested card supports wide bus operation */ + if ((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) + { + /*!< Send CMD55 APP_CMD with argument as card's RCA.*/ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ + SDIO_CmdInitStructure.SDIO_Argument = 0x2; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + return(errorstatus); + } + else + { + errorstatus = SD_REQUEST_NOT_APPLICABLE; + return(errorstatus); + } + } /*!< If wide bus operation to be disabled */ + else + { + /*!< If requested card supports 1 bit mode operation */ + if ((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) + { + /*!< Send CMD55 APP_CMD with argument as card's RCA.*/ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + return(errorstatus); + } + else + { + errorstatus = SD_REQUEST_NOT_APPLICABLE; + return(errorstatus); + } + } +} + +/** + * @brief Checks if the SD card is in programming state. + * @param pstatus: pointer to the variable that will contain the SD card state. + * @retval SD_Error: SD Card Error code. + */ +// OPTIMIZE("O0") static SD_Error IsCardProgramming(uint8_t *pstatus) +// { +// SD_Error errorstatus = SD_OK; +// __IO uint32_t respR1 = 0, status = 0; + +// SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; +// SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS; +// SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; +// SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; +// SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; +// SDIO_SendCommand(&SDIO_CmdInitStructure); + +// status = SDIO->STA; +// while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) +// { +// status = SDIO->STA; +// } + +// if (status & SDIO_FLAG_CTIMEOUT) +// { +// errorstatus = SD_CMD_RSP_TIMEOUT; +// SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); +// return(errorstatus); +// } +// else if (status & SDIO_FLAG_CCRCFAIL) +// { +// errorstatus = SD_CMD_CRC_FAIL; +// SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); +// return(errorstatus); +// } + +// status = (uint32_t)SDIO_GetCommandResponse(); + +// /*!< Check response received is of desired command */ +// if (status != SD_CMD_SEND_STATUS) +// { +// errorstatus = SD_ILLEGAL_CMD; +// return(errorstatus); +// } + +// /*!< Clear all the static flags */ +// SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + +// /*!< We have received response, retrieve it for analysis */ +// respR1 = SDIO_GetResponse(SDIO_RESP1); + +// /*!< Find out card status */ +// *pstatus = (uint8_t) ((respR1 >> 9) & 0x0000000F); + +// if ((respR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) +// { +// return(errorstatus); +// } + +// if (respR1 & SD_OCR_ADDR_OUT_OF_RANGE) +// { +// return(SD_ADDR_OUT_OF_RANGE); +// } + +// if (respR1 & SD_OCR_ADDR_MISALIGNED) +// { +// return(SD_ADDR_MISALIGNED); +// } + +// if (respR1 & SD_OCR_BLOCK_LEN_ERR) +// { +// return(SD_BLOCK_LEN_ERR); +// } + +// if (respR1 & SD_OCR_ERASE_SEQ_ERR) +// { +// return(SD_ERASE_SEQ_ERR); +// } + +// if (respR1 & SD_OCR_BAD_ERASE_PARAM) +// { +// return(SD_BAD_ERASE_PARAM); +// } + +// if (respR1 & SD_OCR_WRITE_PROT_VIOLATION) +// { +// return(SD_WRITE_PROT_VIOLATION); +// } + +// if (respR1 & SD_OCR_LOCK_UNLOCK_FAILED) +// { +// return(SD_LOCK_UNLOCK_FAILED); +// } + +// if (respR1 & SD_OCR_COM_CRC_FAILED) +// { +// return(SD_COM_CRC_FAILED); +// } + +// if (respR1 & SD_OCR_ILLEGAL_CMD) +// { +// return(SD_ILLEGAL_CMD); +// } + +// if (respR1 & SD_OCR_CARD_ECC_FAILED) +// { +// return(SD_CARD_ECC_FAILED); +// } + +// if (respR1 & SD_OCR_CC_ERROR) +// { +// return(SD_CC_ERROR); +// } + +// if (respR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) +// { +// return(SD_GENERAL_UNKNOWN_ERROR); +// } + +// if (respR1 & SD_OCR_STREAM_READ_UNDERRUN) +// { +// return(SD_STREAM_READ_UNDERRUN); +// } + +// if (respR1 & SD_OCR_STREAM_WRITE_OVERRUN) +// { +// return(SD_STREAM_WRITE_OVERRUN); +// } + +// if (respR1 & SD_OCR_CID_CSD_OVERWRIETE) +// { +// return(SD_CID_CSD_OVERWRITE); +// } + +// if (respR1 & SD_OCR_WP_ERASE_SKIP) +// { +// return(SD_WP_ERASE_SKIP); +// } + +// if (respR1 & SD_OCR_CARD_ECC_DISABLED) +// { +// return(SD_CARD_ECC_DISABLED); +// } + +// if (respR1 & SD_OCR_ERASE_RESET) +// { +// return(SD_ERASE_RESET); +// } + +// if (respR1 & SD_OCR_AKE_SEQ_ERROR) +// { +// return(SD_AKE_SEQ_ERROR); +// } + +// return(errorstatus); +// } + +/** + * @brief Find the SD card SCR register value. + * @param rca: selected card address. + * @param pscr: pointer to the buffer that will contain the SCR value. + * @retval SD_Error: SD Card Error code. + */ +OPTIMIZE("O0") static SD_Error FindSCR(uint16_t rca, uint32_t *pscr) +{ + uint32_t index = 0; + SD_Error errorstatus = SD_OK; + uint32_t tempscr[2] = {0, 0}; + + /*!< Set Block Size To 8 Bytes */ + /*!< Send CMD55 APP_CMD with argument as card's RCA */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)8; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /*!< Send CMD55 APP_CMD with argument as card's RCA */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = 8; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_8b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + + /*!< Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_SEND_SCR; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SD_APP_SEND_SCR); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + while (!(SDIO->STA & (SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) + { + if (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) + { + *(tempscr + index) = SDIO_ReadData(); + index++; + } + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); + errorstatus = SD_DATA_TIMEOUT; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); + errorstatus = SD_DATA_CRC_FAIL; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_RXOVERR); + errorstatus = SD_RX_OVERRUN; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_STBITERR); + errorstatus = SD_START_BIT_ERR; + return(errorstatus); + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + *(pscr + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); + + *(pscr) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); + + return(errorstatus); +} + +/** + * @brief Converts the number of bytes in power of two and returns the power. + * @param NumberOfBytes: number of bytes. + * @retval None + */ +// OPTIMIZE("O0") uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes) +// { +// uint8_t count = 0; + +// while (NumberOfBytes != 1) +// { +// NumberOfBytes >>= 1; +// count++; +// } +// return(count); +// } + +void SDIO_IRQHandler(void) +{ + DEBUG_INTERRUPT(INT_SDIO); + SD_ProcessIRQ(); +} + +void SD_SDIO_DMA_IRQHANDLER(void) +{ + DEBUG_INTERRUPT(INT_SDIO_DMA); + SD_ProcessDMAIRQ(); +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/targets/horus/sdio_sd.h b/radio/src/targets/horus/sdio_sd.h index 5e35c7dc1..5ae6f1fb7 100644 --- a/radio/src/targets/horus/sdio_sd.h +++ b/radio/src/targets/horus/sdio_sd.h @@ -1,220 +1,220 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef _SDIO_SD_H_ -#define _SDIO_SD_H_ - -#include "board.h" - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -typedef enum -{ -/** - * @brief SDIO specific error defines - */ - SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */ - SD_DATA_CRC_FAIL = (2), /*!< Data bock sent/received (CRC check Failed) */ - SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */ - SD_DATA_TIMEOUT = (4), /*!< Data time out */ - SD_TX_UNDERRUN = (5), /*!< Transmit FIFO under-run */ - SD_RX_OVERRUN = (6), /*!< Receive FIFO over-run */ - SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in widE bus mode */ - SD_CMD_OUT_OF_RANGE = (8), /*!< CMD's argument was out of range.*/ - SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */ - SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ - SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs.*/ - SD_BAD_ERASE_PARAM = (12), /*!< An Invalid selection for erase groups */ - SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */ - SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ - SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */ - SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */ - SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */ - SD_CC_ERROR = (18), /*!< Internal card controller error */ - SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or Unknown error */ - SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */ - SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */ - SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */ - SD_WP_ERASE_SKIP = (23), /*!< only partial address space was erased */ - SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */ - SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ - SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */ - SD_INVALID_VOLTRANGE = (27), - SD_ADDR_OUT_OF_RANGE = (28), - SD_SWITCH_ERROR = (29), - SD_SDIO_DISABLED = (30), - SD_SDIO_FUNCTION_BUSY = (31), - SD_SDIO_FUNCTION_FAILED = (32), - SD_SDIO_UNKNOWN_FUNCTION = (33), - -/** - * @brief Standard error defines - */ - SD_INTERNAL_ERROR, - SD_NOT_CONFIGURED, - SD_REQUEST_PENDING, - SD_REQUEST_NOT_APPLICABLE, - SD_INVALID_PARAMETER, - SD_UNSUPPORTED_FEATURE, - SD_UNSUPPORTED_HW, - SD_ERROR, - SD_OK = 0 -} SD_Error; - -/** - * @brief SDIO Transfer state - */ -typedef enum -{ - SD_TRANSFER_OK = 0, - SD_TRANSFER_BUSY = 1, - SD_TRANSFER_ERROR -} SDTransferState; - - - -/** - * @brief Card Specific Data: CSD Register - */ -typedef struct -{ - __IO uint8_t CSDStruct; /*!< CSD structure */ - __IO uint8_t SysSpecVersion; /*!< System specification version */ - __IO uint8_t Reserved1; /*!< Reserved */ - __IO uint8_t TAAC; /*!< Data read access-time 1 */ - __IO uint8_t NSAC; /*!< Data read access-time 2 in CLK cycles */ - __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ - __IO uint16_t CardComdClasses; /*!< Card command classes */ - __IO uint8_t RdBlockLen; /*!< Max. read data block length */ - __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ - __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ - __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ - __IO uint8_t DSRImpl; /*!< DSR implemented */ - __IO uint8_t Reserved2; /*!< Reserved */ - __IO uint32_t DeviceSize; /*!< Device Size */ - __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ - __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ - __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ - __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ - __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ - __IO uint8_t EraseGrSize; /*!< Erase group size */ - __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ - __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ - __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ - __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ - __IO uint8_t WrSpeedFact; /*!< Write speed factor */ - __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ - __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ - __IO uint8_t Reserved3; /*!< Reserded */ - __IO uint8_t ContentProtectAppli; /*!< Content protection application */ - __IO uint8_t FileFormatGrouop; /*!< File format group */ - __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ - __IO uint8_t PermWrProtect; /*!< Permanent write protection */ - __IO uint8_t TempWrProtect; /*!< Temporary write protection */ - __IO uint8_t FileFormat; /*!< File Format */ - __IO uint8_t ECC; /*!< ECC code */ - __IO uint8_t CSD_CRC; /*!< CSD CRC */ - __IO uint8_t Reserved4; /*!< always 1*/ -} SD_CSD; - -/** - * @brief Card Identification Data: CID Register - */ -typedef struct -{ - __IO uint8_t ManufacturerID; /*!< ManufacturerID */ - __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ - __IO uint32_t ProdName1; /*!< Product Name part1 */ - __IO uint8_t ProdName2; /*!< Product Name part2*/ - __IO uint8_t ProdRev; /*!< Product Revision */ - __IO uint32_t ProdSN; /*!< Product Serial Number */ - __IO uint8_t Reserved1; /*!< Reserved1 */ - __IO uint16_t ManufactDate; /*!< Manufacturing Date */ - __IO uint8_t CID_CRC; /*!< CID CRC */ - __IO uint8_t Reserved2; /*!< always 1 */ -} SD_CID; - -/** - * @brief SD Card Status - */ -// typedef struct -// { -// __IO uint8_t DAT_BUS_WIDTH; -// __IO uint8_t SECURED_MODE; -// __IO uint16_t SD_CARD_TYPE; -// __IO uint32_t SIZE_OF_PROTECTED_AREA; -// __IO uint8_t SPEED_CLASS; -// __IO uint8_t PERFORMANCE_MOVE; -// __IO uint8_t AU_SIZE; -// __IO uint16_t ERASE_SIZE; -// __IO uint8_t ERASE_TIMEOUT; -// __IO uint8_t ERASE_OFFSET; -// } SD_CardStatus; - - -/** - * @brief SD Card information - */ -typedef struct -{ - SD_CSD SD_csd; - SD_CID SD_cid; - uint64_t CardCapacity; /*!< Card Capacity */ - uint32_t CardBlockSize; /*!< Card Block Size */ - uint16_t RCA; - uint8_t CardType; -} SD_CardInfo; - -/** - * @brief SD detection on its memory slot - */ -#define SD_PRESENT ((uint8_t)0x01) -#define SD_NOT_PRESENT ((uint8_t)0x00) - -// void SD_DeInit(void); -SD_Error SD_Init(void); -SDTransferState SD_GetStatus(void); -uint8_t SD_Detect(void); -SD_Error SD_PowerOFF(void); -// SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus); -SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize); -SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -// SD_Error SD_ReadMultiBlocksFIXED(uint8_t *readbuff, uint32_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize); -SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -// SD_Error SD_WriteMultiBlocksFIXED(uint8_t *writebuff, uint32_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -SDTransferState SD_GetTransferState(void); -// SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr); -// SD_Error SD_SendSDStatus(uint32_t *psdstatus); -SD_Error SD_WaitReadOperation(uint32_t timeout); -SD_Error SD_WaitWriteOperation(uint32_t timeout); - -#ifdef __cplusplus -} -#endif - -extern SD_CardInfo SDCardInfo; - -#endif // _SDIO_SD_H_ - +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _SDIO_SD_H_ +#define _SDIO_SD_H_ + +#include "board.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +typedef enum +{ +/** + * @brief SDIO specific error defines + */ + SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */ + SD_DATA_CRC_FAIL = (2), /*!< Data bock sent/received (CRC check Failed) */ + SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */ + SD_DATA_TIMEOUT = (4), /*!< Data time out */ + SD_TX_UNDERRUN = (5), /*!< Transmit FIFO under-run */ + SD_RX_OVERRUN = (6), /*!< Receive FIFO over-run */ + SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in widE bus mode */ + SD_CMD_OUT_OF_RANGE = (8), /*!< CMD's argument was out of range.*/ + SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */ + SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ + SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs.*/ + SD_BAD_ERASE_PARAM = (12), /*!< An Invalid selection for erase groups */ + SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */ + SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ + SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */ + SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */ + SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */ + SD_CC_ERROR = (18), /*!< Internal card controller error */ + SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or Unknown error */ + SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */ + SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */ + SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */ + SD_WP_ERASE_SKIP = (23), /*!< only partial address space was erased */ + SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */ + SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ + SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */ + SD_INVALID_VOLTRANGE = (27), + SD_ADDR_OUT_OF_RANGE = (28), + SD_SWITCH_ERROR = (29), + SD_SDIO_DISABLED = (30), + SD_SDIO_FUNCTION_BUSY = (31), + SD_SDIO_FUNCTION_FAILED = (32), + SD_SDIO_UNKNOWN_FUNCTION = (33), + +/** + * @brief Standard error defines + */ + SD_INTERNAL_ERROR, + SD_NOT_CONFIGURED, + SD_REQUEST_PENDING, + SD_REQUEST_NOT_APPLICABLE, + SD_INVALID_PARAMETER, + SD_UNSUPPORTED_FEATURE, + SD_UNSUPPORTED_HW, + SD_ERROR, + SD_OK = 0 +} SD_Error; + +/** + * @brief SDIO Transfer state + */ +typedef enum +{ + SD_TRANSFER_OK = 0, + SD_TRANSFER_BUSY = 1, + SD_TRANSFER_ERROR +} SDTransferState; + + + +/** + * @brief Card Specific Data: CSD Register + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access-time 1 */ + __IO uint8_t NSAC; /*!< Data read access-time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserded */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGrouop; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File Format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< always 1*/ +} SD_CSD; + +/** + * @brief Card Identification Data: CID Register + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< ManufacturerID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2*/ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< always 1 */ +} SD_CID; + +/** + * @brief SD Card Status + */ +// typedef struct +// { +// __IO uint8_t DAT_BUS_WIDTH; +// __IO uint8_t SECURED_MODE; +// __IO uint16_t SD_CARD_TYPE; +// __IO uint32_t SIZE_OF_PROTECTED_AREA; +// __IO uint8_t SPEED_CLASS; +// __IO uint8_t PERFORMANCE_MOVE; +// __IO uint8_t AU_SIZE; +// __IO uint16_t ERASE_SIZE; +// __IO uint8_t ERASE_TIMEOUT; +// __IO uint8_t ERASE_OFFSET; +// } SD_CardStatus; + + +/** + * @brief SD Card information + */ +typedef struct +{ + SD_CSD SD_csd; + SD_CID SD_cid; + uint64_t CardCapacity; /*!< Card Capacity */ + uint32_t CardBlockSize; /*!< Card Block Size */ + uint16_t RCA; + uint8_t CardType; +} SD_CardInfo; + +/** + * @brief SD detection on its memory slot + */ +#define SD_PRESENT ((uint8_t)0x01) +#define SD_NOT_PRESENT ((uint8_t)0x00) + +// void SD_DeInit(void); +SD_Error SD_Init(void); +SDTransferState SD_GetStatus(void); +uint8_t SD_Detect(void); +SD_Error SD_PowerOFF(void); +// SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus); +SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize); +SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); +// SD_Error SD_ReadMultiBlocksFIXED(uint8_t *readbuff, uint32_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); +SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize); +SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); +// SD_Error SD_WriteMultiBlocksFIXED(uint8_t *writebuff, uint32_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); +SDTransferState SD_GetTransferState(void); +// SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr); +// SD_Error SD_SendSDStatus(uint32_t *psdstatus); +SD_Error SD_WaitReadOperation(uint32_t timeout); +SD_Error SD_WaitWriteOperation(uint32_t timeout); + +#ifdef __cplusplus +} +#endif + +extern SD_CardInfo SDCardInfo; + +#endif // _SDIO_SD_H_ + diff --git a/radio/src/targets/horus/sdram_driver.c b/radio/src/targets/horus/sdram_driver.c index 0e796f390..dab91988f 100755 --- a/radio/src/targets/horus/sdram_driver.c +++ b/radio/src/targets/horus/sdram_driver.c @@ -1,466 +1,466 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "board.h" - -#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b - -#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3 - -#define SDCLOCK_PERIOD FMC_SDClock_Period_2 - -#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) - -/** - * @brief FMC SDRAM Mode definition register defines - */ -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -/** - * @brief FMC SDRAM Memory Read Burst feature - */ -#define SDRAM_READBURST FMC_Read_Burst_Disable - -static void __Delay(__IO uint32_t nCount) -{ - __IO uint32_t index = 0; - for(index = (100000 * nCount); index != 0; index--) - { - } -} - -/** - * @brief Configures all SDRAM memory I/Os pins. - * @param None. - * @retval None. - */ -void SDRAM_GPIOConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIOs clock */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | - RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOG|RCC_AHB1Periph_GPIOH, ENABLE); - - /*-- GPIOs Configuration -----------------------------------------------------*/ - /* - +-------------------+--------------------+--------------------+--------------------+ - + SDRAM pins assignment + - +-------------------+--------------------+--------------------+--------------------+ - | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | - | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | - | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK | - | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS | - | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+ - | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | - | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | - +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | - | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | - | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | - | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | - +-------------------+--------------------+--------------------+ - | PB5 <-> FMC_SDCKE1| - | PB6 <-> FMC_SDNE1 | - | PH5 <-> FMC_SDNWE |/////// - +-------------------+ - - */ - - /* Common GPIO configuration */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - - /* GPIOB configuration */ - GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 ; - - GPIO_Init(GPIOB, &GPIO_InitStructure); - - /* GPIOC configuration */ - GPIO_PinAFConfig(GPIOH, GPIO_PinSource5 , GPIO_AF_FMC); - - GPIO_PinAFConfig(GPIOH, GPIO_PinSource6 , GPIO_AF_FMC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6; - - GPIO_Init(GPIOH, &GPIO_InitStructure); - - /* GPIOD configuration */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | - GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | - GPIO_Pin_15; - - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* GPIOE configuration */ - GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | - GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15; - - GPIO_Init(GPIOE, &GPIO_InitStructure); - - /* GPIOF configuration */ - GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | - GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15; - - GPIO_Init(GPIOF, &GPIO_InitStructure); - - /* GPIOG configuration */ - GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC); - - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | - GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15; - - GPIO_Init(GPIOG, &GPIO_InitStructure); -} - -/** - * @brief Executes the SDRAM memory initialization sequence. - * @param None. - * @retval None. - */ -void SDRAM_InitSequence(void) -{ - FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; - uint32_t tmpr = 0; - uint32_t timeout = SDRAM_TIMEOUT; - - /* Step 3 --------------------------------------------------------------------*/ - /* Configure a clock configuration enable command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) - { - timeout--; - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 4 --------------------------------------------------------------------*/ - /* Insert 100 ms delay */ - __Delay(10); - - /* Step 5 --------------------------------------------------------------------*/ - /* Configure a PALL (precharge all) command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - - /* Wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) - { - timeout--; - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 6 --------------------------------------------------------------------*/ - /* Configure a Auto-Refresh command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 8; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - - /* Wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) - { - timeout--; - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 7 --------------------------------------------------------------------*/ - /* Program the external memory mode register */ - tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 | - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | - SDRAM_MODEREG_CAS_LATENCY_3 | - SDRAM_MODEREG_OPERATING_MODE_STANDARD | - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; - - /* Configure a load Mode register command*/ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; - - /* Wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) - { - timeout--; - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 8 --------------------------------------------------------------------*/ - - /* Set the refresh rate counter */ - /* (15.62 us x Freq) - 20 */ - /* Set the device refresh counter */ - FMC_SetRefreshCount(1385); - - /* Wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) - { - timeout--; - } -} - -/** - * @brief Executes the SDRAM memory initialization sequence. - * @param None. - * @retval None. - */ -void SDRAMTest_InitSequence(void) -{ - FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; - uint32_t tmpr = 0; - -/* Step 3 --------------------------------------------------------------------*/ - /* Configure a clock configuration enable command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 4 --------------------------------------------------------------------*/ - /* Insert 100 ms delay */ - __Delay(10); - -/* Step 5 --------------------------------------------------------------------*/ - /* Configure a PALL (precharge all) command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 6 --------------------------------------------------------------------*/ - /* Configure a Auto-Refresh command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the first command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the second command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 7 --------------------------------------------------------------------*/ - /* Program the external memory mode register */ - tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | - SDRAM_MODEREG_CAS_LATENCY_3 | - SDRAM_MODEREG_OPERATING_MODE_STANDARD | - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; - - /* Configure a load Mode register command*/ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 8 --------------------------------------------------------------------*/ - - /* Set the refresh rate counter */ - /* (15.62 us x Freq) - 20 */ - /* Set the device refresh counter */ - FMC_SetRefreshCount(1386); - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } -} - -void SDRAM_Init(void) -{ - FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; - FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure; - - /* GPIO configuration for FMC SDRAM bank */ - SDRAM_GPIOConfig(); - - /* Enable FMC clock */ - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); - - /* FMC Configuration ---------------------------------------------------------*/ - /* FMC SDRAM Bank configuration */ - /* Timing configuration for 90 Mhz of SD clock frequency (168Mhz/2) */ - /* TMRD: 2 Clock cycles */ - FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; - /* TXSR: min=70ns (7x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7; - /* TRAS: min=42ns (4x11.11ns) max=120k (ns) */ - FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; - /* TRC: min=70 (7x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7; - /* TWR: min=1+ 7ns (1+1x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; - /* TRP: 20ns => 2x11.11ns */ - FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; - /* TRCD: 20ns => 2x11.11ns */ - FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; - - /* FMC SDRAM control configuration */ - FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM; - /* Row addressing: [7:0] */ - FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; - /* Column addressing: [11:0] */ - FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b; - FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH; - FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; - FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY; - FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; - FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD; - FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST; - FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0; - FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; - - /* FMC SDRAM bank initialization */ - FMC_SDRAMInit(&FMC_SDRAMInitStructure); - - /* FMC SDRAM device initialization sequence */ - SDRAMTest_InitSequence(); -} - -#if 0 -void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize) -{ - __IO uint32_t write_pointer = (uint32_t)uwWriteAddress; - - FMC_SDRAMWriteProtectionConfig(FMC_Bank1_SDRAM, DISABLE); - - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - - for (; uwBufferSize != 0; uwBufferSize--) - { - - *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++; - - write_pointer += 4; - } - -} - -void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize) -{ - __IO uint32_t write_pointer = (uint32_t)uwReadAddress; - - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - - for(; uwBufferSize != 0x00; uwBufferSize--) - { - *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer ); - - write_pointer += 4; - } -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "board.h" + +#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b + +#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3 + +#define SDCLOCK_PERIOD FMC_SDClock_Period_2 + +#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) + +/** + * @brief FMC SDRAM Mode definition register defines + */ +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +/** + * @brief FMC SDRAM Memory Read Burst feature + */ +#define SDRAM_READBURST FMC_Read_Burst_Disable + +static void __Delay(__IO uint32_t nCount) +{ + __IO uint32_t index = 0; + for(index = (100000 * nCount); index != 0; index--) + { + } +} + +/** + * @brief Configures all SDRAM memory I/Os pins. + * @param None. + * @retval None. + */ +void SDRAM_GPIOConfig(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIOs clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | + RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOG|RCC_AHB1Periph_GPIOH, ENABLE); + + /*-- GPIOs Configuration -----------------------------------------------------*/ + /* + +-------------------+--------------------+--------------------+--------------------+ + + SDRAM pins assignment + + +-------------------+--------------------+--------------------+--------------------+ + | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | + | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | + | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK | + | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS | + | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+ + | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | + | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | + +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | + | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | + | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | + | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | + +-------------------+--------------------+--------------------+ + | PB5 <-> FMC_SDCKE1| + | PB6 <-> FMC_SDNE1 | + | PH5 <-> FMC_SDNWE |/////// + +-------------------+ + + */ + + /* Common GPIO configuration */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + + /* GPIOB configuration */ + GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 ; + + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* GPIOC configuration */ + GPIO_PinAFConfig(GPIOH, GPIO_PinSource5 , GPIO_AF_FMC); + + GPIO_PinAFConfig(GPIOH, GPIO_PinSource6 , GPIO_AF_FMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6; + + GPIO_Init(GPIOH, &GPIO_InitStructure); + + /* GPIOD configuration */ + GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | + GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | + GPIO_Pin_15; + + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* GPIOE configuration */ + GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | + GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | + GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15; + + GPIO_Init(GPIOE, &GPIO_InitStructure); + + /* GPIOF configuration */ + GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | + GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | + GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15; + + GPIO_Init(GPIOF, &GPIO_InitStructure); + + /* GPIOG configuration */ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC); + + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | + GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15; + + GPIO_Init(GPIOG, &GPIO_InitStructure); +} + +/** + * @brief Executes the SDRAM memory initialization sequence. + * @param None. + * @retval None. + */ +void SDRAM_InitSequence(void) +{ + FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; + uint32_t tmpr = 0; + uint32_t timeout = SDRAM_TIMEOUT; + + /* Step 3 --------------------------------------------------------------------*/ + /* Configure a clock configuration enable command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) + { + timeout--; + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + + /* Step 4 --------------------------------------------------------------------*/ + /* Insert 100 ms delay */ + __Delay(10); + + /* Step 5 --------------------------------------------------------------------*/ + /* Configure a PALL (precharge all) command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + + /* Wait until the SDRAM controller is ready */ + timeout = SDRAM_TIMEOUT; + while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) + { + timeout--; + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 6 --------------------------------------------------------------------*/ + /* Configure a Auto-Refresh command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 8; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + + /* Wait until the SDRAM controller is ready */ + timeout = SDRAM_TIMEOUT; + while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) + { + timeout--; + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 7 --------------------------------------------------------------------*/ + /* Program the external memory mode register */ + tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 | + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | + SDRAM_MODEREG_CAS_LATENCY_3 | + SDRAM_MODEREG_OPERATING_MODE_STANDARD | + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + /* Configure a load Mode register command*/ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; + + /* Wait until the SDRAM controller is ready */ + timeout = SDRAM_TIMEOUT; + while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) + { + timeout--; + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + + /* Step 8 --------------------------------------------------------------------*/ + + /* Set the refresh rate counter */ + /* (15.62 us x Freq) - 20 */ + /* Set the device refresh counter */ + FMC_SetRefreshCount(1385); + + /* Wait until the SDRAM controller is ready */ + timeout = SDRAM_TIMEOUT; + while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) + { + timeout--; + } +} + +/** + * @brief Executes the SDRAM memory initialization sequence. + * @param None. + * @retval None. + */ +void SDRAMTest_InitSequence(void) +{ + FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; + uint32_t tmpr = 0; + +/* Step 3 --------------------------------------------------------------------*/ + /* Configure a clock configuration enable command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 4 --------------------------------------------------------------------*/ + /* Insert 100 ms delay */ + __Delay(10); + +/* Step 5 --------------------------------------------------------------------*/ + /* Configure a PALL (precharge all) command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 6 --------------------------------------------------------------------*/ + /* Configure a Auto-Refresh command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the first command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the second command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 7 --------------------------------------------------------------------*/ + /* Program the external memory mode register */ + tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | + SDRAM_MODEREG_CAS_LATENCY_3 | + SDRAM_MODEREG_OPERATING_MODE_STANDARD | + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + /* Configure a load Mode register command*/ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 8 --------------------------------------------------------------------*/ + + /* Set the refresh rate counter */ + /* (15.62 us x Freq) - 20 */ + /* Set the device refresh counter */ + FMC_SetRefreshCount(1386); + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } +} + +void SDRAM_Init(void) +{ + FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; + FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure; + + /* GPIO configuration for FMC SDRAM bank */ + SDRAM_GPIOConfig(); + + /* Enable FMC clock */ + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); + + /* FMC Configuration ---------------------------------------------------------*/ + /* FMC SDRAM Bank configuration */ + /* Timing configuration for 90 Mhz of SD clock frequency (168Mhz/2) */ + /* TMRD: 2 Clock cycles */ + FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; + /* TXSR: min=70ns (7x11.11ns) */ + FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7; + /* TRAS: min=42ns (4x11.11ns) max=120k (ns) */ + FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; + /* TRC: min=70 (7x11.11ns) */ + FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7; + /* TWR: min=1+ 7ns (1+1x11.11ns) */ + FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; + /* TRP: 20ns => 2x11.11ns */ + FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; + /* TRCD: 20ns => 2x11.11ns */ + FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; + + /* FMC SDRAM control configuration */ + FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM; + /* Row addressing: [7:0] */ + FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; + /* Column addressing: [11:0] */ + FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b; + FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH; + FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; + FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY; + FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; + FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD; + FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST; + FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0; + FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; + + /* FMC SDRAM bank initialization */ + FMC_SDRAMInit(&FMC_SDRAMInitStructure); + + /* FMC SDRAM device initialization sequence */ + SDRAMTest_InitSequence(); +} + +#if 0 +void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize) +{ + __IO uint32_t write_pointer = (uint32_t)uwWriteAddress; + + FMC_SDRAMWriteProtectionConfig(FMC_Bank1_SDRAM, DISABLE); + + while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + + for (; uwBufferSize != 0; uwBufferSize--) + { + + *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++; + + write_pointer += 4; + } + +} + +void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize) +{ + __IO uint32_t write_pointer = (uint32_t)uwReadAddress; + + while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + + for(; uwBufferSize != 0x00; uwBufferSize--) + { + *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer ); + + write_pointer += 4; + } +} #endif \ No newline at end of file diff --git a/radio/src/targets/horus/startup_stm32f40_41xxx.s b/radio/src/targets/horus/startup_stm32f40_41xxx.s index 8a6579aca..899b1ab45 100644 --- a/radio/src/targets/horus/startup_stm32f40_41xxx.s +++ b/radio/src/targets/horus/startup_stm32f40_41xxx.s @@ -1,529 +1,529 @@ -/** - ****************************************************************************** - * @file startup_stm32f40_41xxx.s - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief STM32F40xxx/41xxx Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM324xG-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - - bl pwrResetHandler /*jump to WDT reset handler where soft power control pin is turned on as soon as possible */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/*Paint Main Stack */ - ldr r2, = _main_stack_start -PaintMainStack: - movs r3, #0x55555555 - str r3, [r2], #4 -LoopPaintMainStack: - ldr r3, = _estack - cmp r2, r3 - bcc PaintMainStack - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call C++ constructors for static objects */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word CRYP_IRQHandler /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CRYP_IRQHandler - .thumb_set CRYP_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file startup_stm32f40_41xxx.s + * @author MCD Application Team + * @version V1.3.0 + * @date 08-November-2013 + * @brief STM32F40xxx/41xxx Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM324xG-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2013 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + bl pwrResetHandler /*jump to WDT reset handler where soft power control pin is turned on as soon as possible */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/*Paint Main Stack */ + ldr r2, = _main_stack_start +PaintMainStack: + movs r3, #0x55555555 + str r3, [r2], #4 +LoopPaintMainStack: + ldr r3, = _estack + cmp r2, r3 + bcc PaintMainStack + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call C++ constructors for static objects */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/targets/horus/telemetry_driver.cpp b/radio/src/targets/horus/telemetry_driver.cpp index be14dd151..75e31cb81 100644 --- a/radio/src/targets/horus/telemetry_driver.cpp +++ b/radio/src/targets/horus/telemetry_driver.cpp @@ -1,232 +1,232 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -Fifo telemetryNoDMAFifo; -uint32_t telemetryErrors = 0; - -#if defined(PCBX12S) -DMAFifo telemetryDMAFifo __DMA (TELEMETRY_DMA_Stream_RX); -uint8_t telemetryFifoMode; -#endif - -void telemetryPortInit(uint32_t baudrate, uint8_t mode) -{ - if (baudrate == 0) { - USART_DeInit(TELEMETRY_USART); - return; - } - - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = TELEMETRY_DMA_TX_Stream_IRQ; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pre-emption priority. */; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - USART_InitTypeDef USART_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - GPIO_PinAFConfig(TELEMETRY_GPIO, TELEMETRY_GPIO_PinSource_RX, TELEMETRY_GPIO_AF); - GPIO_PinAFConfig(TELEMETRY_GPIO, TELEMETRY_GPIO_PinSource_TX, TELEMETRY_GPIO_AF); - - GPIO_InitStructure.GPIO_Pin = TELEMETRY_TX_GPIO_PIN | TELEMETRY_RX_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_Init(TELEMETRY_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = TELEMETRY_DIR_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(TELEMETRY_DIR_GPIO, &GPIO_InitStructure); - GPIO_ResetBits(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN); - - USART_InitStructure.USART_BaudRate = baudrate; - if (mode & TELEMETRY_SERIAL_8E2) { - USART_InitStructure.USART_WordLength = USART_WordLength_9b; - USART_InitStructure.USART_StopBits = USART_StopBits_2; - USART_InitStructure.USART_Parity = USART_Parity_Even; - } - else { - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No; - } - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; - USART_Init(TELEMETRY_USART, &USART_InitStructure); - -#if defined(PCBX12S) - telemetryFifoMode = mode; - - DMA_Cmd(TELEMETRY_DMA_Stream_RX, DISABLE); - USART_DMACmd(TELEMETRY_USART, USART_DMAReq_Rx, DISABLE); - DMA_DeInit(TELEMETRY_DMA_Stream_RX); - - if (mode & TELEMETRY_SERIAL_WITHOUT_DMA) { - USART_Cmd(TELEMETRY_USART, ENABLE); - USART_ITConfig(TELEMETRY_USART, USART_IT_RXNE, ENABLE); - NVIC_SetPriority(TELEMETRY_USART_IRQn, 6); - NVIC_EnableIRQ(TELEMETRY_USART_IRQn); - } - else { - DMA_InitTypeDef DMA_InitStructure; - telemetryDMAFifo.clear(); - - USART_ITConfig(TELEMETRY_USART, USART_IT_RXNE, DISABLE); - USART_ITConfig(TELEMETRY_USART, USART_IT_TXE, DISABLE); - NVIC_SetPriority(TELEMETRY_USART_IRQn, 6); - NVIC_EnableIRQ(TELEMETRY_USART_IRQn); - - DMA_InitStructure.DMA_Channel = TELEMETRY_DMA_Channel_RX; - DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&TELEMETRY_USART->DR); - DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(telemetryDMAFifo.buffer()); - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; - DMA_InitStructure.DMA_BufferSize = telemetryDMAFifo.size(); - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; - DMA_InitStructure.DMA_Priority = DMA_Priority_Low; - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - DMA_Init(TELEMETRY_DMA_Stream_RX, &DMA_InitStructure); - USART_DMACmd(TELEMETRY_USART, USART_DMAReq_Rx, ENABLE); - USART_Cmd(TELEMETRY_USART, ENABLE); - DMA_Cmd(TELEMETRY_DMA_Stream_RX, ENABLE); - } -#else - USART_Cmd(TELEMETRY_USART, ENABLE); - USART_ITConfig(TELEMETRY_USART, USART_IT_RXNE, ENABLE); - NVIC_SetPriority(TELEMETRY_USART_IRQn, 6); - NVIC_EnableIRQ(TELEMETRY_USART_IRQn); -#endif -} - -void telemetryPortSetDirectionOutput() -{ - TELEMETRY_DIR_GPIO->BSRRL = TELEMETRY_DIR_GPIO_PIN; // output enable - TELEMETRY_USART->CR1 &= ~USART_CR1_RE; // turn off receiver -} - -void telemetryPortSetDirectionInput() -{ - TELEMETRY_DIR_GPIO->BSRRH = TELEMETRY_DIR_GPIO_PIN; // output disable - TELEMETRY_USART->CR1 |= USART_CR1_RE; // turn on receiver -} - -void sportSendBuffer(uint8_t * buffer, uint32_t count) -{ - telemetryPortSetDirectionOutput(); - - DMA_InitTypeDef DMA_InitStructure; - DMA_DeInit(TELEMETRY_DMA_Stream_TX); - DMA_InitStructure.DMA_Channel = TELEMETRY_DMA_Channel_TX; - DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&TELEMETRY_USART->DR); - DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; - DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(buffer); - DMA_InitStructure.DMA_BufferSize = count; - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - DMA_Init(TELEMETRY_DMA_Stream_TX, &DMA_InitStructure); - DMA_Cmd(TELEMETRY_DMA_Stream_TX, ENABLE); - USART_DMACmd(TELEMETRY_USART, USART_DMAReq_Tx, ENABLE); - DMA_ITConfig(TELEMETRY_DMA_Stream_TX, DMA_IT_TC, ENABLE); - - // enable interrupt and set it's priority - NVIC_EnableIRQ(TELEMETRY_DMA_TX_Stream_IRQ) ; - NVIC_SetPriority(TELEMETRY_DMA_TX_Stream_IRQ, 7); -} - -extern "C" void TELEMETRY_DMA_TX_IRQHandler(void) -{ - DEBUG_INTERRUPT(INT_TELEM_DMA); - if (DMA_GetITStatus(TELEMETRY_DMA_Stream_TX, TELEMETRY_DMA_TX_FLAG_TC)) { - DMA_ClearITPendingBit(TELEMETRY_DMA_Stream_TX, TELEMETRY_DMA_TX_FLAG_TC); - TELEMETRY_USART->CR1 |= USART_CR1_TCIE; - if (telemetryProtocol == PROTOCOL_FRSKY_SPORT) { - outputTelemetryBufferSize = 0; - outputTelemetryBufferTrigger = 0x7E; - } - } -} - -#define USART_FLAG_ERRORS (USART_FLAG_ORE | USART_FLAG_NE | USART_FLAG_FE | USART_FLAG_PE) -extern "C" void TELEMETRY_USART_IRQHandler(void) -{ - DEBUG_INTERRUPT(INT_TELEM_USART); - uint32_t status = TELEMETRY_USART->SR; - - if ((status & USART_SR_TC) && (TELEMETRY_USART->CR1 & USART_CR1_TCIE)) { - TELEMETRY_USART->CR1 &= ~USART_CR1_TCIE; - telemetryPortSetDirectionInput(); - while (status & (USART_FLAG_RXNE)) { - status = TELEMETRY_USART->DR; - status = TELEMETRY_USART->SR; - } - } - - while (status & (USART_FLAG_RXNE | USART_FLAG_ERRORS)) { - uint8_t data = TELEMETRY_USART->DR; - if (status & USART_FLAG_ERRORS) { - telemetryErrors++; - } - else { - telemetryNoDMAFifo.push(data); -#if defined(LUA) - if (telemetryProtocol == PROTOCOL_FRSKY_SPORT) { - static uint8_t prevdata; - if (prevdata == 0x7E && outputTelemetryBufferSize > 0 && data == outputTelemetryBufferTrigger) { - sportSendBuffer(outputTelemetryBuffer, outputTelemetryBufferSize); - } - prevdata = data; - } -#endif - } - status = TELEMETRY_USART->SR; - } -} - -// TODO we should have telemetry in an higher layer, functions above should move to a sport_driver.cpp -uint8_t telemetryGetByte(uint8_t * byte) -{ -#if defined(PCBX12S) - if (telemetryFifoMode & TELEMETRY_SERIAL_WITHOUT_DMA) - return telemetryNoDMAFifo.pop(*byte); - else - return telemetryDMAFifo.pop(*byte); -#else - return telemetryNoDMAFifo.pop(*byte); -#endif -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +Fifo telemetryNoDMAFifo; +uint32_t telemetryErrors = 0; + +#if defined(PCBX12S) +DMAFifo telemetryDMAFifo __DMA (TELEMETRY_DMA_Stream_RX); +uint8_t telemetryFifoMode; +#endif + +void telemetryPortInit(uint32_t baudrate, uint8_t mode) +{ + if (baudrate == 0) { + USART_DeInit(TELEMETRY_USART); + return; + } + + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = TELEMETRY_DMA_TX_Stream_IRQ; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pre-emption priority. */; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + USART_InitTypeDef USART_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_PinAFConfig(TELEMETRY_GPIO, TELEMETRY_GPIO_PinSource_RX, TELEMETRY_GPIO_AF); + GPIO_PinAFConfig(TELEMETRY_GPIO, TELEMETRY_GPIO_PinSource_TX, TELEMETRY_GPIO_AF); + + GPIO_InitStructure.GPIO_Pin = TELEMETRY_TX_GPIO_PIN | TELEMETRY_RX_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_Init(TELEMETRY_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = TELEMETRY_DIR_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(TELEMETRY_DIR_GPIO, &GPIO_InitStructure); + GPIO_ResetBits(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN); + + USART_InitStructure.USART_BaudRate = baudrate; + if (mode & TELEMETRY_SERIAL_8E2) { + USART_InitStructure.USART_WordLength = USART_WordLength_9b; + USART_InitStructure.USART_StopBits = USART_StopBits_2; + USART_InitStructure.USART_Parity = USART_Parity_Even; + } + else { + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + } + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; + USART_Init(TELEMETRY_USART, &USART_InitStructure); + +#if defined(PCBX12S) + telemetryFifoMode = mode; + + DMA_Cmd(TELEMETRY_DMA_Stream_RX, DISABLE); + USART_DMACmd(TELEMETRY_USART, USART_DMAReq_Rx, DISABLE); + DMA_DeInit(TELEMETRY_DMA_Stream_RX); + + if (mode & TELEMETRY_SERIAL_WITHOUT_DMA) { + USART_Cmd(TELEMETRY_USART, ENABLE); + USART_ITConfig(TELEMETRY_USART, USART_IT_RXNE, ENABLE); + NVIC_SetPriority(TELEMETRY_USART_IRQn, 6); + NVIC_EnableIRQ(TELEMETRY_USART_IRQn); + } + else { + DMA_InitTypeDef DMA_InitStructure; + telemetryDMAFifo.clear(); + + USART_ITConfig(TELEMETRY_USART, USART_IT_RXNE, DISABLE); + USART_ITConfig(TELEMETRY_USART, USART_IT_TXE, DISABLE); + NVIC_SetPriority(TELEMETRY_USART_IRQn, 6); + NVIC_EnableIRQ(TELEMETRY_USART_IRQn); + + DMA_InitStructure.DMA_Channel = TELEMETRY_DMA_Channel_RX; + DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&TELEMETRY_USART->DR); + DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(telemetryDMAFifo.buffer()); + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = telemetryDMAFifo.size(); + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_Low; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(TELEMETRY_DMA_Stream_RX, &DMA_InitStructure); + USART_DMACmd(TELEMETRY_USART, USART_DMAReq_Rx, ENABLE); + USART_Cmd(TELEMETRY_USART, ENABLE); + DMA_Cmd(TELEMETRY_DMA_Stream_RX, ENABLE); + } +#else + USART_Cmd(TELEMETRY_USART, ENABLE); + USART_ITConfig(TELEMETRY_USART, USART_IT_RXNE, ENABLE); + NVIC_SetPriority(TELEMETRY_USART_IRQn, 6); + NVIC_EnableIRQ(TELEMETRY_USART_IRQn); +#endif +} + +void telemetryPortSetDirectionOutput() +{ + TELEMETRY_DIR_GPIO->BSRRL = TELEMETRY_DIR_GPIO_PIN; // output enable + TELEMETRY_USART->CR1 &= ~USART_CR1_RE; // turn off receiver +} + +void telemetryPortSetDirectionInput() +{ + TELEMETRY_DIR_GPIO->BSRRH = TELEMETRY_DIR_GPIO_PIN; // output disable + TELEMETRY_USART->CR1 |= USART_CR1_RE; // turn on receiver +} + +void sportSendBuffer(uint8_t * buffer, uint32_t count) +{ + telemetryPortSetDirectionOutput(); + + DMA_InitTypeDef DMA_InitStructure; + DMA_DeInit(TELEMETRY_DMA_Stream_TX); + DMA_InitStructure.DMA_Channel = TELEMETRY_DMA_Channel_TX; + DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&TELEMETRY_USART->DR); + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(buffer); + DMA_InitStructure.DMA_BufferSize = count; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(TELEMETRY_DMA_Stream_TX, &DMA_InitStructure); + DMA_Cmd(TELEMETRY_DMA_Stream_TX, ENABLE); + USART_DMACmd(TELEMETRY_USART, USART_DMAReq_Tx, ENABLE); + DMA_ITConfig(TELEMETRY_DMA_Stream_TX, DMA_IT_TC, ENABLE); + + // enable interrupt and set it's priority + NVIC_EnableIRQ(TELEMETRY_DMA_TX_Stream_IRQ) ; + NVIC_SetPriority(TELEMETRY_DMA_TX_Stream_IRQ, 7); +} + +extern "C" void TELEMETRY_DMA_TX_IRQHandler(void) +{ + DEBUG_INTERRUPT(INT_TELEM_DMA); + if (DMA_GetITStatus(TELEMETRY_DMA_Stream_TX, TELEMETRY_DMA_TX_FLAG_TC)) { + DMA_ClearITPendingBit(TELEMETRY_DMA_Stream_TX, TELEMETRY_DMA_TX_FLAG_TC); + TELEMETRY_USART->CR1 |= USART_CR1_TCIE; + if (telemetryProtocol == PROTOCOL_FRSKY_SPORT) { + outputTelemetryBufferSize = 0; + outputTelemetryBufferTrigger = 0x7E; + } + } +} + +#define USART_FLAG_ERRORS (USART_FLAG_ORE | USART_FLAG_NE | USART_FLAG_FE | USART_FLAG_PE) +extern "C" void TELEMETRY_USART_IRQHandler(void) +{ + DEBUG_INTERRUPT(INT_TELEM_USART); + uint32_t status = TELEMETRY_USART->SR; + + if ((status & USART_SR_TC) && (TELEMETRY_USART->CR1 & USART_CR1_TCIE)) { + TELEMETRY_USART->CR1 &= ~USART_CR1_TCIE; + telemetryPortSetDirectionInput(); + while (status & (USART_FLAG_RXNE)) { + status = TELEMETRY_USART->DR; + status = TELEMETRY_USART->SR; + } + } + + while (status & (USART_FLAG_RXNE | USART_FLAG_ERRORS)) { + uint8_t data = TELEMETRY_USART->DR; + if (status & USART_FLAG_ERRORS) { + telemetryErrors++; + } + else { + telemetryNoDMAFifo.push(data); +#if defined(LUA) + if (telemetryProtocol == PROTOCOL_FRSKY_SPORT) { + static uint8_t prevdata; + if (prevdata == 0x7E && outputTelemetryBufferSize > 0 && data == outputTelemetryBufferTrigger) { + sportSendBuffer(outputTelemetryBuffer, outputTelemetryBufferSize); + } + prevdata = data; + } +#endif + } + status = TELEMETRY_USART->SR; + } +} + +// TODO we should have telemetry in an higher layer, functions above should move to a sport_driver.cpp +uint8_t telemetryGetByte(uint8_t * byte) +{ +#if defined(PCBX12S) + if (telemetryFifoMode & TELEMETRY_SERIAL_WITHOUT_DMA) + return telemetryNoDMAFifo.pop(*byte); + else + return telemetryDMAFifo.pop(*byte); +#else + return telemetryNoDMAFifo.pop(*byte); +#endif +} diff --git a/radio/src/targets/horus/trainer_driver.cpp b/radio/src/targets/horus/trainer_driver.cpp index 66058a58d..d05648b47 100644 --- a/radio/src/targets/horus/trainer_driver.cpp +++ b/radio/src/targets/horus/trainer_driver.cpp @@ -1,154 +1,154 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void trainerSendNextFrame(); - -void init_trainer_ppm() -{ - GPIO_PinAFConfig(TRAINER_GPIO, TRAINER_OUT_GPIO_PinSource, TRAINER_GPIO_AF); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = TRAINER_OUT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(TRAINER_GPIO, &GPIO_InitStructure); - - TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; - TRAINER_TIMER->PSC = TRAINER_TIMER_FREQ / 2000000 - 1; // 0.5uS - TRAINER_TIMER->ARR = 45000; - TRAINER_TIMER->CCR2 = GET_PPM_DELAY(TRAINER_MODULE)*2; - TRAINER_TIMER->CCER = TIM_CCER_CC2E | (g_model.moduleData[TRAINER_MODULE].ppm.pulsePol ? 0 : TIM_CCER_CC2P); - TRAINER_TIMER->CCMR1 = TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_0; // Force O/P high - TRAINER_TIMER->BDTR = TIM_BDTR_MOE; - TRAINER_TIMER->EGR = 1; - TRAINER_TIMER->DIER |= TIM_DIER_UDE; - TRAINER_TIMER->CCMR1 = TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2PE; // PWM mode 1 - TRAINER_TIMER->CR1 |= TIM_CR1_CEN; - - setupPulsesPPMTrainer(); - trainerSendNextFrame(); - - NVIC_EnableIRQ(TRAINER_DMA_IRQn); - NVIC_SetPriority(TRAINER_DMA_IRQn, 7); - NVIC_EnableIRQ(TRAINER_TIMER_IRQn); - NVIC_SetPriority(TRAINER_TIMER_IRQn, 7); -} - -void stop_trainer_ppm() -{ - NVIC_DisableIRQ(TRAINER_DMA_IRQn); - NVIC_DisableIRQ(TRAINER_TIMER_IRQn); - - TRAINER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - TRAINER_TIMER->DIER = 0; // Stop Interrupt - TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; // Stop counter -} - -void init_trainer_capture() -{ - GPIO_InitTypeDef GPIO_InitStructure; - - GPIO_InitStructure.GPIO_Pin = TRAINER_IN_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(TRAINER_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(TRAINER_GPIO, TRAINER_IN_GPIO_PinSource, TRAINER_GPIO_AF); - - TRAINER_TIMER->ARR = 0xFFFF; - TRAINER_TIMER->PSC = TRAINER_TIMER_FREQ / 2000000 - 1; // 0.5uS - TRAINER_TIMER->CR2 = 0; - TRAINER_TIMER->CCMR1 = TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_CC1S_0; - TRAINER_TIMER->CCER = TIM_CCER_CC1E; - TRAINER_TIMER->SR &= ~TIM_SR_CC1IF & ~TIM_SR_CC2IF & ~TIM_SR_UIF; // Clear flags - TRAINER_TIMER->DIER |= TIM_DIER_CC1IE; - TRAINER_TIMER->CR1 = TIM_CR1_CEN; - - NVIC_EnableIRQ(TRAINER_TIMER_IRQn); - NVIC_SetPriority(TRAINER_TIMER_IRQn, 7); -} - -void stop_trainer_capture() -{ - NVIC_DisableIRQ(TRAINER_TIMER_IRQn); // Stop Interrupt - - TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; // Stop counter - TRAINER_TIMER->DIER = 0; // Stop Interrupt -} - -void trainerSendNextFrame() -{ - TRAINER_TIMER->CCR2 = GET_PPM_DELAY(TRAINER_MODULE)*2; - TRAINER_TIMER->CCER = TIM_CCER_CC2E | (g_model.moduleData[TRAINER_MODULE].ppm.pulsePol ? 0 : TIM_CCER_CC2P); - TRAINER_TIMER->CCR1 = *(trainerPulsesData.ppm.ptr - 1) - 4000; // 2mS in advance - - TRAINER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - TRAINER_DMA_STREAM->CR |= TRAINER_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; - TRAINER_DMA_STREAM->PAR = CONVERT_PTR_UINT(&TRAINER_TIMER->ARR); - TRAINER_DMA_STREAM->M0AR = CONVERT_PTR_UINT(trainerPulsesData.ppm.pulses); - TRAINER_DMA_STREAM->NDTR = trainerPulsesData.ppm.ptr - trainerPulsesData.ppm.pulses; - TRAINER_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA -} - -extern "C" void TRAINER_DMA_IRQHandler() -{ - if (!DMA_GetITStatus(TRAINER_DMA_STREAM, TRAINER_DMA_FLAG_TC)) - return; - - DMA_ClearITPendingBit(TRAINER_DMA_STREAM, TRAINER_DMA_FLAG_TC); - - TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag - TRAINER_TIMER->DIER |= TIM_DIER_CC1IE; // Enable this interrupt -} - -extern "C" void TRAINER_TIMER_IRQHandler() -{ - DEBUG_INTERRUPT(INT_TRAINER); - - uint16_t capture = 0; - bool doCapture = false; - - // What mode? in or out? - if ((TRAINER_TIMER->DIER & TIM_DIER_CC1IE) && (TRAINER_TIMER->SR & TIM_SR_CC1IF)) { - // capture mode on trainer jack - capture = TRAINER_TIMER->CCR1; - if (TRAINER_CONNECTED() && currentTrainerMode == TRAINER_MODE_MASTER_TRAINER_JACK) { - doCapture = true; - } - } - - if (doCapture) { - captureTrainerPulses(capture); - } - - // PPM out compare interrupt - if ((TRAINER_TIMER->DIER & TIM_DIER_CC1IE) && (TRAINER_TIMER->SR & TIM_SR_CC1IF)) { - // compare interrupt - TRAINER_TIMER->DIER &= ~TIM_DIER_CC1IE; // stop this interrupt - TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag - setupPulsesPPMTrainer(); - trainerSendNextFrame(); - } -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +void trainerSendNextFrame(); + +void init_trainer_ppm() +{ + GPIO_PinAFConfig(TRAINER_GPIO, TRAINER_OUT_GPIO_PinSource, TRAINER_GPIO_AF); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = TRAINER_OUT_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(TRAINER_GPIO, &GPIO_InitStructure); + + TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; + TRAINER_TIMER->PSC = TRAINER_TIMER_FREQ / 2000000 - 1; // 0.5uS + TRAINER_TIMER->ARR = 45000; + TRAINER_TIMER->CCR2 = GET_PPM_DELAY(TRAINER_MODULE)*2; + TRAINER_TIMER->CCER = TIM_CCER_CC2E | (g_model.moduleData[TRAINER_MODULE].ppm.pulsePol ? 0 : TIM_CCER_CC2P); + TRAINER_TIMER->CCMR1 = TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_0; // Force O/P high + TRAINER_TIMER->BDTR = TIM_BDTR_MOE; + TRAINER_TIMER->EGR = 1; + TRAINER_TIMER->DIER |= TIM_DIER_UDE; + TRAINER_TIMER->CCMR1 = TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2PE; // PWM mode 1 + TRAINER_TIMER->CR1 |= TIM_CR1_CEN; + + setupPulsesPPMTrainer(); + trainerSendNextFrame(); + + NVIC_EnableIRQ(TRAINER_DMA_IRQn); + NVIC_SetPriority(TRAINER_DMA_IRQn, 7); + NVIC_EnableIRQ(TRAINER_TIMER_IRQn); + NVIC_SetPriority(TRAINER_TIMER_IRQn, 7); +} + +void stop_trainer_ppm() +{ + NVIC_DisableIRQ(TRAINER_DMA_IRQn); + NVIC_DisableIRQ(TRAINER_TIMER_IRQn); + + TRAINER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + TRAINER_TIMER->DIER = 0; // Stop Interrupt + TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; // Stop counter +} + +void init_trainer_capture() +{ + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_InitStructure.GPIO_Pin = TRAINER_IN_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(TRAINER_GPIO, &GPIO_InitStructure); + GPIO_PinAFConfig(TRAINER_GPIO, TRAINER_IN_GPIO_PinSource, TRAINER_GPIO_AF); + + TRAINER_TIMER->ARR = 0xFFFF; + TRAINER_TIMER->PSC = TRAINER_TIMER_FREQ / 2000000 - 1; // 0.5uS + TRAINER_TIMER->CR2 = 0; + TRAINER_TIMER->CCMR1 = TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_CC1S_0; + TRAINER_TIMER->CCER = TIM_CCER_CC1E; + TRAINER_TIMER->SR &= ~TIM_SR_CC1IF & ~TIM_SR_CC2IF & ~TIM_SR_UIF; // Clear flags + TRAINER_TIMER->DIER |= TIM_DIER_CC1IE; + TRAINER_TIMER->CR1 = TIM_CR1_CEN; + + NVIC_EnableIRQ(TRAINER_TIMER_IRQn); + NVIC_SetPriority(TRAINER_TIMER_IRQn, 7); +} + +void stop_trainer_capture() +{ + NVIC_DisableIRQ(TRAINER_TIMER_IRQn); // Stop Interrupt + + TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; // Stop counter + TRAINER_TIMER->DIER = 0; // Stop Interrupt +} + +void trainerSendNextFrame() +{ + TRAINER_TIMER->CCR2 = GET_PPM_DELAY(TRAINER_MODULE)*2; + TRAINER_TIMER->CCER = TIM_CCER_CC2E | (g_model.moduleData[TRAINER_MODULE].ppm.pulsePol ? 0 : TIM_CCER_CC2P); + TRAINER_TIMER->CCR1 = *(trainerPulsesData.ppm.ptr - 1) - 4000; // 2mS in advance + + TRAINER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + TRAINER_DMA_STREAM->CR |= TRAINER_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; + TRAINER_DMA_STREAM->PAR = CONVERT_PTR_UINT(&TRAINER_TIMER->ARR); + TRAINER_DMA_STREAM->M0AR = CONVERT_PTR_UINT(trainerPulsesData.ppm.pulses); + TRAINER_DMA_STREAM->NDTR = trainerPulsesData.ppm.ptr - trainerPulsesData.ppm.pulses; + TRAINER_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA +} + +extern "C" void TRAINER_DMA_IRQHandler() +{ + if (!DMA_GetITStatus(TRAINER_DMA_STREAM, TRAINER_DMA_FLAG_TC)) + return; + + DMA_ClearITPendingBit(TRAINER_DMA_STREAM, TRAINER_DMA_FLAG_TC); + + TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag + TRAINER_TIMER->DIER |= TIM_DIER_CC1IE; // Enable this interrupt +} + +extern "C" void TRAINER_TIMER_IRQHandler() +{ + DEBUG_INTERRUPT(INT_TRAINER); + + uint16_t capture = 0; + bool doCapture = false; + + // What mode? in or out? + if ((TRAINER_TIMER->DIER & TIM_DIER_CC1IE) && (TRAINER_TIMER->SR & TIM_SR_CC1IF)) { + // capture mode on trainer jack + capture = TRAINER_TIMER->CCR1; + if (TRAINER_CONNECTED() && currentTrainerMode == TRAINER_MODE_MASTER_TRAINER_JACK) { + doCapture = true; + } + } + + if (doCapture) { + captureTrainerPulses(capture); + } + + // PPM out compare interrupt + if ((TRAINER_TIMER->DIER & TIM_DIER_CC1IE) && (TRAINER_TIMER->SR & TIM_SR_CC1IF)) { + // compare interrupt + TRAINER_TIMER->DIER &= ~TIM_DIER_CC1IE; // stop this interrupt + TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag + setupPulsesPPMTrainer(); + trainerSendNextFrame(); + } +} diff --git a/radio/src/targets/mega2560/00readme.txt b/radio/src/targets/mega2560/00readme.txt index af74f9829..0edafc8e2 100644 --- a/radio/src/targets/mega2560/00readme.txt +++ b/radio/src/targets/mega2560/00readme.txt @@ -1,8 +1,8 @@ -MEGA2560 board - -======================= DESCRIPTION ======================= -DIY radio wih : -- Arduino MEGA2560 or compatible -- Gruvin9x features (soft-off, SD-Card, RTC, haptic, voice, rotary encoders) -- LCD 128x64 8 bits parallel mode +MEGA2560 board + +======================= DESCRIPTION ======================= +DIY radio wih : +- Arduino MEGA2560 or compatible +- Gruvin9x features (soft-off, SD-Card, RTC, haptic, voice, rotary encoders) +- LCD 128x64 8 bits parallel mode - home made case \ No newline at end of file diff --git a/radio/src/targets/mega2560/board.h b/radio/src/targets/mega2560/board.h index a7eb37cb3..ada4b2104 100644 --- a/radio/src/targets/mega2560/board.h +++ b/radio/src/targets/mega2560/board.h @@ -1,196 +1,196 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BOARD_MEGA2560_H_ -#define _BOARD_MEGA2560_H_ - -#include "../common/avr/board_avr.h" - -// Board driver -void boardInit(void); -#define boardOff() pwrOff() - -// Keys -#define KEYS_GPIO_REG_MENU pinl -#define KEYS_GPIO_PIN_MENU (1<<4) -#define KEYS_GPIO_REG_EXIT pinl -#define KEYS_GPIO_PIN_EXIT (1<<5) -#define KEYS_GPIO_REG_RIGHT pinl -#define KEYS_GPIO_PIN_RIGHT (1<<2) -#define KEYS_GPIO_REG_LEFT pinl -#define KEYS_GPIO_PIN_LEFT (1<<3) -#define KEYS_GPIO_REG_UP pinl -#define KEYS_GPIO_PIN_UP (1<<1) -#define KEYS_GPIO_REG_DOWN pinl -#define KEYS_GPIO_PIN_DOWN (1<<0) - -// Trims -#define TRIMS_GPIO_REG_LHL pinf -#define TRIMS_GPIO_PIN_LHL (1<<7) -#define TRIMS_GPIO_REG_LVD pinf -#define TRIMS_GPIO_PIN_LVD (1<<5) -#define TRIMS_GPIO_REG_RVU pinf -#define TRIMS_GPIO_PIN_RVU (1<<2) -#define TRIMS_GPIO_REG_RHL pinf -#define TRIMS_GPIO_PIN_RHL (1<<1) -#define TRIMS_GPIO_REG_LHR pinf -#define TRIMS_GPIO_PIN_LHR (1<<6) -#define TRIMS_GPIO_REG_LVU pinf -#define TRIMS_GPIO_PIN_LVU (1<<4) -#define TRIMS_GPIO_REG_RVD pinf -#define TRIMS_GPIO_PIN_RVD (1<<3) -#define TRIMS_GPIO_REG_RHR pinf -#define TRIMS_GPIO_PIN_RHR (1<<0) - -#define TIMER_16KHZ_VECT TIMER2_OVF_vect -#define COUNTER_16KHZ TCNT2 -#define TIMER_10MS_VECT TIMER2_COMPA_vect -#define TIMER_10MS_COMPVAL OCR2A -#define PAUSE_10MS_INTERRUPT() TIMSK2 &= ~(1< -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *) value) -#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ***************************************************************************** */ -/* CMSIS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_cmsis CMSIS Definitions */ - -/*@{*/ - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 0 /**< AT91SAM3S does not provide a MPU present or not */ -#define __NVIC_PRIO_BITS 4 /**< AT91SAM3S uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** AT91SAM3S specific Interrupt Numbers *****************************************/ - - SUPC_IRQn = 0, /**< 0 AT91SAM3S Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 AT91SAM3S Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 AT91SAM3S Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 AT91SAM3S Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 AT91SAM3S Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 AT91SAM3S Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 AT91SAM3S Enhanced Flash Controller (EFC) */ - UART0_IRQn = 8, /**< 8 AT91SAM3S UART 0 (UART0) */ - UART1_IRQn = 9, /**< 9 AT91SAM3S UART 1 (UART1) */ - SMC_IRQn = 10, /**< 10 AT91SAM3S Static Memory Controller (SMC) */ - PIOA_IRQn = 11, /**< 11 AT91SAM3S Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 AT91SAM3S Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 AT91SAM3S Parallel I/O Controller C (PIOC) */ - USART0_IRQn = 14, /**< 14 AT91SAM3S USART 0 (USART0) */ - USART1_IRQn = 15, /**< 15 AT91SAM3S USART 1 (USART1) */ - HSMCI_IRQn = 18, /**< 18 AT91SAM3S Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 19, /**< 19 AT91SAM3S Two Wire Interface 0 (TWI0) */ - TWI1_IRQn = 20, /**< 20 AT91SAM3S Two Wire Interface 1 (TWI1) */ - SPI_IRQn = 21, /**< 21 AT91SAM3S Serial Peripheral Interface (SPI) */ - SSC_IRQn = 22, /**< 22 AT91SAM3S Synchronous Serial Controler (SSC) */ - TC0_IRQn = 23, /**< 23 AT91SAM3S Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 AT91SAM3S Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 AT91SAM3S Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 AT91SAM3S Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 AT91SAM3S Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 AT91SAM3S Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 AT91SAM3S Analog To Digital Converter (ADC) */ - DACC_IRQn = 30, /**< 30 AT91SAM3S Digital To Analog Converter (DACC) */ - PWM_IRQn = 31, /**< 31 AT91SAM3S Pulse Width Modulation (PWM) */ - CRCCU_IRQn = 32, /**< 32 AT91SAM3S CRC Calculation Unit (CRCCU) */ - ACC_IRQn = 33, /**< 33 AT91SAM3S Analog Comparator (ACC) */ - UDP_IRQn = 34 /**< 34 AT91SAM3S USB Device Port (UDP) */ -} IRQn_Type; -/*@}*/ - -/* ***************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_api Peripheral Software API */ -/*@{*/ -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ACC Analog Comparator Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Acc hardware registers */ -typedef struct { - WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ - RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ - RwReg Reserved1[7]; - WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ - WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ - RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ - RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[24]; - RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ - RwReg Reserved3[19]; - RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ - RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ -} Acc; -#endif /* __ASSEMBLY__ */ -/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ -#define ACC_CR_SWRST (0x1 << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ -/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ -#define ACC_MR_SELPLUS (0x7 << 0) /**< \brief (ACC_MR) SELection for PLUS comparator input */ -#define ACC_MR_SELMINUS (0x7 << 4) /**< \brief (ACC_MR) SELection for MINUS comparator input */ -#define ACC_MR_ACEN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_EN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_DIS (0x0 << 8) /**< \brief (ACC_MR) Analog Comparator Disable */ -#define ACC_MR_EDGETYP (0x3 << 9) /**< \brief (ACC_MR) EDGE TYPe */ -#define ACC_MR_EDGETYP_RISING (0x0 << 9) /**< \brief (ACC_MR) EDGE TYPe ,RISING edge*/ -#define ACC_MR_EDGETYP_FALLING (0x1 << 9) /**< \brief (ACC_MR) EDGE TYPe,falling edge */ -#define ACC_MR_EDGETYP_ANY (0x2 << 9) /**< \brief (ACC_MR) EDGE TYPe,any edge */ -#define ACC_MR_INV (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_EN (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_DIS (0x0 << 12) /**< \brief (ACC_MR) DIRECTLY */ -#define ACC_MR_SELFS (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_CF (0x0 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_OUTPUT (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_FE (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_EN (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_DIS (0x0 << 14) /**< \brief (ACC_MR) Fault Enable */ -/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ -#define ACC_IER_CE (0x1 << 0) /**< \brief (ACC_IER) Comparison Edge */ -/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ -#define ACC_IDR_CE (0x1 << 0) /**< \brief (ACC_IDR) Comparison Edge */ -/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ACC_IMR_CE (0x1 << 0) /**< \brief (ACC_IMR) Comparison Edge */ -/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ -#define ACC_ISR_CE (0x1 << 0) /**< \brief (ACC_ISR) Comparison Edge */ -#define ACC_ISR_SCO (0x1 << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ -#define ACC_ISR_MASK (0x1 << 31) /**< \brief (ACC_ISR) */ -/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ -#define ACC_ACR_ISEL (0x1 << 0) /**< \brief (ACC_ACR) Current SELection */ -#define ACC_ACR_HYST (0x3 << 1) /**< \brief (ACC_ACR) HYSTeresis selection */ -/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ACC_WPMR_WPEN (0x1 << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ -#define ACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ACC_WPMR) Write Protect KEY */ -/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ -#define ACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ADC Analog-to-digital Converter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Adc hardware registers */ -typedef struct { - WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ - RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ - RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence 1Register */ - RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence 2 Register */ - WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ - WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ - RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ - RwReg Reserved1[1]; - RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ - WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ - WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ - RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ - RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[2]; - RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ - RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ - RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ - RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ - RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ - RoReg ADC_CDR0; /**< \brief (Adc Offset: 0x50) Channel Data Register 0 */ - RoReg ADC_CDR1; /**< \brief (Adc Offset: 0x54) Channel Data Register 1 */ - RoReg ADC_CDR2; /**< \brief (Adc Offset: 0x58) Channel Data Register 2 */ - RoReg ADC_CDR3; /**< \brief (Adc Offset: 0x5C) Channel Data Register 3 */ - RoReg ADC_CDR4; /**< \brief (Adc Offset: 0x60) Channel Data Register 4 */ - RoReg ADC_CDR5; /**< \brief (Adc Offset: 0x64) Channel Data Register 5 */ - RoReg ADC_CDR6; /**< \brief (Adc Offset: 0x68) Channel Data Register 6 */ - RoReg ADC_CDR7; /**< \brief (Adc Offset: 0x6C) Channel Data Register 7 */ - RoReg ADC_CDR8; /**< \brief (Adc Offset: 0x70) Channel Data Register 8 */ - RoReg ADC_CDR9; /**< \brief (Adc Offset: 0x74) Channel Data Register 9 */ - RoReg ADC_CDR10; /**< \brief (Adc Offset: 0x78) Channel Data Register 10 */ - RoReg ADC_CDR11; /**< \brief (Adc Offset: 0x7C) Channel Data Register 11 */ - RoReg ADC_CDR12; /**< \brief (Adc Offset: 0x80) Channel Data Register 12 */ - RoReg ADC_CDR13; /**< \brief (Adc Offset: 0x84) Channel Data Register 13 */ - RoReg ADC_CDR14; /**< \brief (Adc Offset: 0x88) Channel Data Register 14 */ - RoReg ADC_CDR15; /**< \brief (Adc Offset: 0x8C) Channel Data Register 15 */ - RwReg Reserved3[1]; - RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ - RwReg Reserved4[19]; - RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ - RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ - RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ - RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */ - RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */ - RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ - RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ - RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */ - RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */ - WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ - RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ -} Adc; -#endif /* __ASSEMBLY__ */ -/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ -#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ -#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ -/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ -#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ -#define ADC_MR_TRGEN_DIS (0x0 << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.*/ -#define ADC_MR_TRGEN_EN (0x1) /**< (ADC) Hardware trigger selected by TRGSEL field is enabled.*/ -#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ -#define ADC_MR_TRGSEL_EXT (0x0 << 1) /**< \brief (ADC_MR) Selected TRGSEL = External Trigger*/ -#define ADC_MR_TRGSEL_TIOA0 (0x1 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO0*/ -#define ADC_MR_TRGSEL_TIOA1 (0x2 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO1*/ -#define ADC_MR_TRGSEL_TIOA2 (0x3 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO2*/ -#define ADC_MR_TRGSEL_PWM0_TRIG (0x4 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM trigger*/ -#define ADC_MR_TRGSEL_PWM1_TRIG (0x5 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM Trigger*/ -#define ADC_MR_TRGSEL_RESERVED (0x6 << 1) /**< \brief (ADC_MR) Selected TRGSEL = Reserved*/ -#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ -#define ADC_MR_LOWRES_12_BIT (0x0 << 4) /**< \brief (ADC_MR) 12-bit resolution*/ -#define ADC_MR_LOWRES_10_BIT (0x1 << 4) /**< \brief (ADC_MR) 10-bit resolution*/ -#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ -#define ADC_MR_SLEEP_NORMAL (0x0 << 5) /**< \brief (ADC12B) Normal Mode*/ -#define ADC_MR_FWUP (0x1 << 6) /**< \brief (ADC_MR) Fast Wake Up */ -#define ADC_MR_FREERUN (0x1 << 7) /**< \brief (ADC_MR) Free Run Mode */ -#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ -#define ADC_MR_STARTUP (0xf << 16) /**< \brief (ADC_MR) Start Up Time */ -#define ADC_MR_SETTLING (0x3 << 20) /**< \brief (ADC_MR) Analog Settling Time */ -#define ADC_MR_ANACH (0x1 << 23) /**< \brief (ADC_MR) Analog Change */ -#define ADC_MR_TRACKTIM (0xf << 24) /**< \brief (ADC_MR) Tracking Time */ -#define ADC_MR_TRANSFER (0x3 << 28) /**< \brief (ADC_MR) */ -#define ADC_MR_USEQ (0x1 << 31) /**< \brief (ADC_MR) User Sequence Enable */ -/* -------- ADC_SEQ1R : (ADC Offset: 0x08) Channel Sequence 1Register -------- */ -#define ADC_SEQ1R_USCH1 (0x7 << 0) /**< \brief (ADC_SEQ1R) User Sequence Number 1 */ -#define ADC_SEQ1R_USCH2 (0x7 << 4) /**< \brief (ADC_SEQ1R) User Sequence Number 2 */ -#define ADC_SEQ1R_USCH3 (0x7 << 8) /**< \brief (ADC_SEQ1R) User Sequence Number 3 */ -#define ADC_SEQ1R_USCH4 (0x7 << 12) /**< \brief (ADC_SEQ1R) User Sequence Number 4 */ -#define ADC_SEQ1R_USCH5 (0x7 << 16) /**< \brief (ADC_SEQ1R) User Sequence Number 5 */ -#define ADC_SEQ1R_USCH6 (0x7 << 20) /**< \brief (ADC_SEQ1R) User Sequence Number 6 */ -#define ADC_SEQ1R_USCH7 (0x7 << 24) /**< \brief (ADC_SEQ1R) User Sequence Number 7 */ -#define ADC_SEQ1R_USCH8 (0x7 << 28) /**< \brief (ADC_SEQ1R) User Sequence Number 8 */ -/* -------- ADC_SEQ2R : (ADC Offset: 0x0C) Channel Sequence 2 Register -------- */ -#define ADC_SEQ2R_USCH9 (0x7 << 0) /**< \brief (ADC_SEQ2R) User Sequence Number 9 */ -#define ADC_SEQ2R_USCH10 (0x7 << 4) /**< \brief (ADC_SEQ2R) User Sequence Number 10 */ -#define ADC_SEQ2R_USCH11 (0x7 << 8) /**< \brief (ADC_SEQ2R) User Sequence Number 11 */ -#define ADC_SEQ2R_USCH12 (0x7 << 12) /**< \brief (ADC_SEQ2R) User Sequence Number 12 */ -#define ADC_SEQ2R_USCH13 (0x7 << 16) /**< \brief (ADC_SEQ2R) User Sequence Number 13 */ -#define ADC_SEQ2R_USCH14 (0x7 << 20) /**< \brief (ADC_SEQ2R) User Sequence Number 14 */ -#define ADC_SEQ2R_USCH15 (0x7 << 24) /**< \brief (ADC_SEQ2R) User Sequence Number 15 */ -#define ADC_SEQ2R_USCH16 (0x7 << 28) /**< \brief (ADC_SEQ2R) User Sequence Number 16 */ -/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ -#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ -#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ -#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ -#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ -#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ -#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ -#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ -#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ -#define ADC_CHER_CH8 (0x1 << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ -#define ADC_CHER_CH9 (0x1 << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ -#define ADC_CHER_CH10 (0x1 << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ -#define ADC_CHER_CH11 (0x1 << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ -#define ADC_CHER_CH12 (0x1 << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ -#define ADC_CHER_CH13 (0x1 << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ -#define ADC_CHER_CH14 (0x1 << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ -#define ADC_CHER_CH15 (0x1 << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ -/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ -#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ -#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ -#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ -#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ -#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ -#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ -#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ -#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ -#define ADC_CHDR_CH8 (0x1 << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ -#define ADC_CHDR_CH9 (0x1 << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ -#define ADC_CHDR_CH10 (0x1 << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ -#define ADC_CHDR_CH11 (0x1 << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ -#define ADC_CHDR_CH12 (0x1 << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ -#define ADC_CHDR_CH13 (0x1 << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ -#define ADC_CHDR_CH14 (0x1 << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ -#define ADC_CHDR_CH15 (0x1 << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ -/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ -#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ -#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ -#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ -#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ -#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ -#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ -#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ -#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ -#define ADC_CHSR_CH8 (0x1 << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ -#define ADC_CHSR_CH9 (0x1 << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ -#define ADC_CHSR_CH10 (0x1 << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ -#define ADC_CHSR_CH11 (0x1 << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ -#define ADC_CHSR_CH12 (0x1 << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ -#define ADC_CHSR_CH13 (0x1 << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ -#define ADC_CHSR_CH14 (0x1 << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ -#define ADC_CHSR_CH15 (0x1 << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ -/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ -#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ -#define ADC_LCDR_CHNB (0xf << 12) /**< \brief (ADC_LCDR) Channel Number */ -/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ -#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ -#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ -#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ -#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ -#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ -#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ -#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ -#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ -#define ADC_IER_EOC8 (0x1 << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ -#define ADC_IER_EOC9 (0x1 << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ -#define ADC_IER_EOC10 (0x1 << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ -#define ADC_IER_EOC11 (0x1 << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ -#define ADC_IER_EOC12 (0x1 << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ -#define ADC_IER_EOC13 (0x1 << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ -#define ADC_IER_EOC14 (0x1 << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ -#define ADC_IER_EOC15 (0x1 << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ -#define ADC_IER_DRDY (0x1 << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ -#define ADC_IER_GOVRE (0x1 << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ -#define ADC_IER_COMPE (0x1 << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ -#define ADC_IER_ENDRX (0x1 << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ -#define ADC_IER_RXBUFF (0x1 << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ -/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ -#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ -#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ -#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ -#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ -#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ -#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ -#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ -#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ -#define ADC_IDR_EOC8 (0x1 << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ -#define ADC_IDR_EOC9 (0x1 << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ -#define ADC_IDR_EOC10 (0x1 << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ -#define ADC_IDR_EOC11 (0x1 << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ -#define ADC_IDR_EOC12 (0x1 << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ -#define ADC_IDR_EOC13 (0x1 << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ -#define ADC_IDR_EOC14 (0x1 << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ -#define ADC_IDR_EOC15 (0x1 << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ -#define ADC_IDR_DRDY (0x1 << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ -#define ADC_IDR_GOVRE (0x1 << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ -#define ADC_IDR_COMPE (0x1 << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ -#define ADC_IDR_ENDRX (0x1 << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ -#define ADC_IDR_RXBUFF (0x1 << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ -/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ -#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ -#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ -#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ -#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ -#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ -#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ -#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ -#define ADC_IMR_EOC8 (0x1 << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ -#define ADC_IMR_EOC9 (0x1 << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ -#define ADC_IMR_EOC10 (0x1 << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ -#define ADC_IMR_EOC11 (0x1 << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ -#define ADC_IMR_EOC12 (0x1 << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ -#define ADC_IMR_EOC13 (0x1 << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ -#define ADC_IMR_EOC14 (0x1 << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ -#define ADC_IMR_EOC15 (0x1 << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ -#define ADC_IMR_DRDY (0x1 << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ -#define ADC_IMR_GOVRE (0x1 << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ -#define ADC_IMR_COMPE (0x1 << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ -#define ADC_IMR_ENDRX (0x1 << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ -#define ADC_IMR_RXBUFF (0x1 << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ -/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ -#define ADC_ISR_EOC0 (0x1 << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ -#define ADC_ISR_EOC1 (0x1 << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ -#define ADC_ISR_EOC2 (0x1 << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ -#define ADC_ISR_EOC3 (0x1 << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ -#define ADC_ISR_EOC4 (0x1 << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ -#define ADC_ISR_EOC5 (0x1 << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ -#define ADC_ISR_EOC6 (0x1 << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ -#define ADC_ISR_EOC7 (0x1 << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ -#define ADC_ISR_EOC8 (0x1 << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ -#define ADC_ISR_EOC9 (0x1 << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ -#define ADC_ISR_EOC10 (0x1 << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ -#define ADC_ISR_EOC11 (0x1 << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ -#define ADC_ISR_EOC12 (0x1 << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ -#define ADC_ISR_EOC13 (0x1 << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ -#define ADC_ISR_EOC14 (0x1 << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ -#define ADC_ISR_EOC15 (0x1 << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ -#define ADC_ISR_DRDY (0x1 << 24) /**< \brief (ADC_ISR) Data Ready */ -#define ADC_ISR_GOVRE (0x1 << 25) /**< \brief (ADC_ISR) General Overrun Error */ -#define ADC_ISR_COMPE (0x1 << 26) /**< \brief (ADC_ISR) Comparison Error */ -#define ADC_ISR_ENDRX (0x1 << 27) /**< \brief (ADC_ISR) End of RX Buffer */ -#define ADC_ISR_RXBUFF (0x1 << 28) /**< \brief (ADC_ISR) RX Buffer Full */ -/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ -#define ADC_OVER_OVRE0 (0x1 << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ -#define ADC_OVER_OVRE1 (0x1 << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ -#define ADC_OVER_OVRE2 (0x1 << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ -#define ADC_OVER_OVRE3 (0x1 << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ -#define ADC_OVER_OVRE4 (0x1 << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ -#define ADC_OVER_OVRE5 (0x1 << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ -#define ADC_OVER_OVRE6 (0x1 << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ -#define ADC_OVER_OVRE7 (0x1 << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ -#define ADC_OVER_OVRE8 (0x1 << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ -#define ADC_OVER_OVRE9 (0x1 << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ -#define ADC_OVER_OVRE10 (0x1 << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ -#define ADC_OVER_OVRE11 (0x1 << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ -#define ADC_OVER_OVRE12 (0x1 << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ -#define ADC_OVER_OVRE13 (0x1 << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ -#define ADC_OVER_OVRE14 (0x1 << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ -#define ADC_OVER_OVRE15 (0x1 << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ -/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ -#define ADC_EMR_CMPMODE (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode */ -#define ADC_EMR_CMPMODE_LOW (0x0 << 0) /**< \brief (ADC_EMR) Comparison Mode,lower than low threshold */ -#define ADC_EMR_CMPMODE_HIGH (0x1 << 0) /**< \brief (ADC_EMR) Comparison Mode,higher than high threshold */ -#define ADC_EMR_CMPMODE_IN (0x2 << 0) /**< \brief (ADC_EMR) Comparison Mode, in the comparison window */ -#define ADC_EMR_CMPMODE_OUT (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode, out of the comparison window */ -#define ADC_EMR_CMPSEL (0xf << 4) /**< \brief (ADC_EMR) Comparison Selected Channel */ -#define ADC_EMR_CMPALL (0x1 << 9) /**< \brief (ADC_EMR) Compare All Channels */ -#define ADC_EMR_TAG (0x1 << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ -/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ -#define ADC_CWR_LOWTHRES (0xfff << 0) /**< \brief (ADC_CWR) Low Threshold */ -#define ADC_CWR_HIGHTHRES (0xfff << 16) /**< \brief (ADC_CWR) High Threshold */ -/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ -#define ADC_CGR_GAIN0 (0x3 << 0) /**< \brief (ADC_CGR) Gain for channel 0 */ -#define ADC_CGR_GAIN1 (0x3 << 2) /**< \brief (ADC_CGR) Gain for channel 1 */ -#define ADC_CGR_GAIN2 (0x3 << 4) /**< \brief (ADC_CGR) Gain for channel 2 */ -#define ADC_CGR_GAIN3 (0x3 << 6) /**< \brief (ADC_CGR) Gain for channel 3 */ -#define ADC_CGR_GAIN4 (0x3 << 8) /**< \brief (ADC_CGR) Gain for channel 4 */ -#define ADC_CGR_GAIN5 (0x3 << 10) /**< \brief (ADC_CGR) Gain for channel 5 */ -#define ADC_CGR_GAIN6 (0x3 << 12) /**< \brief (ADC_CGR) Gain for channel 6 */ -#define ADC_CGR_GAIN7 (0x3 << 14) /**< \brief (ADC_CGR) Gain for channel 7 */ -#define ADC_CGR_GAIN8 (0x3 << 16) /**< \brief (ADC_CGR) Gain for channel 8 */ -#define ADC_CGR_GAIN9 (0x3 << 18) /**< \brief (ADC_CGR) Gain for channel 9 */ -#define ADC_CGR_GAIN10 (0x3 << 20) /**< \brief (ADC_CGR) Gain for channel 10 */ -#define ADC_CGR_GAIN11 (0x3 << 22) /**< \brief (ADC_CGR) Gain for channel 11 */ -#define ADC_CGR_GAIN12 (0x3 << 24) /**< \brief (ADC_CGR) Gain for channel 12 */ -#define ADC_CGR_GAIN13 (0x3 << 26) /**< \brief (ADC_CGR) Gain for channel 13 */ -#define ADC_CGR_GAIN14 (0x3 << 28) /**< \brief (ADC_CGR) Gain for channel 14 */ -#define ADC_CGR_GAIN15 (0x3 << 30) /**< \brief (ADC_CGR) Gain for channel 15 */ -/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ -#define ADC_COR_OFF0 (0x1 << 0) /**< \brief (ADC_COR) Offset for channel 0 */ -#define ADC_COR_OFF1 (0x1 << 1) /**< \brief (ADC_COR) Offset for channel 1 */ -#define ADC_COR_OFF2 (0x1 << 2) /**< \brief (ADC_COR) Offset for channel 2 */ -#define ADC_COR_OFF3 (0x1 << 3) /**< \brief (ADC_COR) Offset for channel 3 */ -#define ADC_COR_OFF4 (0x1 << 4) /**< \brief (ADC_COR) Offset for channel 4 */ -#define ADC_COR_OFF5 (0x1 << 5) /**< \brief (ADC_COR) Offset for channel 5 */ -#define ADC_COR_OFF6 (0x1 << 6) /**< \brief (ADC_COR) Offset for channel 6 */ -#define ADC_COR_OFF7 (0x1 << 7) /**< \brief (ADC_COR) Offset for channel 7 */ -#define ADC_COR_OFF8 (0x1 << 8) /**< \brief (ADC_COR) Offset for channel 8 */ -#define ADC_COR_OFF9 (0x1 << 9) /**< \brief (ADC_COR) Offset for channel 9 */ -#define ADC_COR_OFF10 (0x1 << 10) /**< \brief (ADC_COR) Offset for channel 10 */ -#define ADC_COR_OFF11 (0x1 << 11) /**< \brief (ADC_COR) Offset for channel 11 */ -#define ADC_COR_OFF12 (0x1 << 12) /**< \brief (ADC_COR) Offset for channel 12 */ -#define ADC_COR_OFF13 (0x1 << 13) /**< \brief (ADC_COR) Offset for channel 13 */ -#define ADC_COR_OFF14 (0x1 << 14) /**< \brief (ADC_COR) Offset for channel 14 */ -#define ADC_COR_OFF15 (0x1 << 15) /**< \brief (ADC_COR) Offset for channel 15 */ -#define ADC_COR_DIFF0 (0x1 << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ -#define ADC_COR_DIFF1 (0x1 << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ -#define ADC_COR_DIFF2 (0x1 << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ -#define ADC_COR_DIFF3 (0x1 << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ -#define ADC_COR_DIFF4 (0x1 << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ -#define ADC_COR_DIFF5 (0x1 << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ -#define ADC_COR_DIFF6 (0x1 << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ -#define ADC_COR_DIFF7 (0x1 << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ -#define ADC_COR_DIFF8 (0x1 << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ -#define ADC_COR_DIFF9 (0x1 << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ -#define ADC_COR_DIFF10 (0x1 << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ -#define ADC_COR_DIFF11 (0x1 << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ -#define ADC_COR_DIFF12 (0x1 << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ -#define ADC_COR_DIFF13 (0x1 << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ -#define ADC_COR_DIFF14 (0x1 << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ -#define ADC_COR_DIFF15 (0x1 << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ -/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */ -#define ADC_CDR0_DATA (0x3ff << 0) /**< \brief (ADC_CDR0) Converted Data */ -/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */ -#define ADC_CDR1_DATA (0x3ff << 0) /**< \brief (ADC_CDR1) Converted Data */ -/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */ -#define ADC_CDR2_DATA (0x3ff << 0) /**< \brief (ADC_CDR2) Converted Data */ -/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */ -#define ADC_CDR3_DATA (0x3ff << 0) /**< \brief (ADC_CDR3) Converted Data */ -/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */ -#define ADC_CDR4_DATA (0x3ff << 0) /**< \brief (ADC_CDR4) Converted Data */ -/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */ -#define ADC_CDR5_DATA (0x3ff << 0) /**< \brief (ADC_CDR5) Converted Data */ -/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */ -#define ADC_CDR6_DATA (0x3ff << 0) /**< \brief (ADC_CDR6) Converted Data */ -/* -------- ADC_CDR15 : (ADC Offset: 0x6C) Channel Data Register 15 -------- */ -#define ADC_CDR15_DATA (0x3ff << 0) /**< \brief (ADC_CDR15) Converted Data */ -/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ -#define ADC_ACR_TSON (0x1 << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ -#define ADC_ACR_IBCTL (0x3 << 8) /**< \brief (ADC_ACR) ADC Bias Current Control */ -/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ADC_WPMR_WPEN (0x1 << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ -#define ADC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ADC_WPMR) Write Protect KEY */ -/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ -#define ADC_WPSR_WPVS (0x1 << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ -#define ADC_WPSR_WPVSRC (0xffff << 8) /**< \brief (ADC_WPSR) Write Protect Violation Source */ -/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ -#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ -/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ -#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ -/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ -#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ -/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ -#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ -/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ -#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ -/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ -#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ -/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ -/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ -/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ -#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ -#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ -#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ -#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ -/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ -#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ -#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Chip Identifier */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CHIPID Chip Identifier */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Chipid hardware registers */ -typedef struct { - RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ - RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ -} Chipid; -#endif /* __ASSEMBLY__ */ -/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ -#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ -#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ -#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ -#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ -#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ -#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ -/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ -#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Crccu hardware registers */ -typedef struct { - RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ - RwReg Reserved1[1]; - WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ - WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ - RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ - WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ - WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ - RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ - RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ - RwReg Reserved2[4]; - WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ - RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ - RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ - WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ - WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ - RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ - RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ -} Crccu; -#endif /* __ASSEMBLY__ */ -/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ -#define CRCCU_DSCR_DSCR (0x7fffff << 9) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ -/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ -#define CRCCU_DMA_EN_DMAEN (0x1 << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ -/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ -#define CRCCU_DMA_DIS_DMADIS (0x1 << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ -/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ -#define CRCCU_DMA_SR_DMASR (0x1 << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ -/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ -#define CRCCU_DMA_IER_DMAIER (0x1 << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ -/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ -#define CRCCU_DMA_IDR_DMAIDR (0x1 << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ -/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ -#define CRCCU_DMA_IMR_DMAIMR (0x1 << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ -/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ -#define CRCCU_DMA_ISR_DMAISR (0x1 << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ -/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ -#define CRCCU_CR_RESET (0x1 << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ -/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ -#define CRCCU_MR_ENABLE (0x1 << 0) /**< \brief (CRCCU_MR) CRC Enable */ -#define CRCCU_MR_COMPARE (0x1 << 1) /**< \brief (CRCCU_MR) CRC Compare */ -#define CRCCU_MR_PTYPE (0x3 << 2) /**< \brief (CRCCU_MR) Primitive Polynomial */ -#define CRCCU_MR_PTYPE_CCIT8023 (0x0 << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ -#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1 << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ -#define CRCCU_MR_PTYPE_CCIT16 (0x2 << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ -#define CRCCU_MR_DIVIDER (0xf << 4) /**< \brief (CRCCU_MR) Request Divider */ -/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ -#define CRCCU_SR_CRC (0xffffffff << 0) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ -/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ -#define CRCCU_IER_ERRIER (0x1 << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ -/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ -#define CRCCU_IDR_ERRIDR (0x1 << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ -/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ -#define CRCCU_IMR_ERRIMR (0x1 << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ -/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ -#define CRCCU_ISR_ERRISR (0x1 << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_DACC Digital-to-Analog Converter Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Dacc hardware registers */ -typedef struct { - WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ - RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ - RwReg Reserved1[2]; - WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ - WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ - RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ - RwReg Reserved2[1]; - WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ - WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ - WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ - RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ - RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved3[24]; - RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ - RwReg Reserved4[19]; - RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ - RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ - RwReg Reserved5[5]; - RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */ - RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */ - RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ - RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ - RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */ - RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */ - RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ - RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ - WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ - RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ -} Dacc; -#endif /* __ASSEMBLY__ */ -/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ -#define DACC_CR_SWRST (0x1 << 0) /**< \brief (DACC_CR) Software Reset */ -/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ -#define DACC_MR_TRGEN (0x1 << 0) /**< \brief (DACC_MR) Trigger Enable */ -#define DACC_MR_TRGEN_DIS (0x0 << 0) // (DACC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. -#define DACC_MR_TRGEN_EN (0x1 << 0) // (DACC_MR) Hardware trigger selected by TRGSEL field is enabled. - -#define DACC_MR_TRGSEL (0x7 << 1) /**< \brief (DACC_MR) Trigger Selection */ -#define DACC_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (DACC_MR) External trigger -#define DACC_MR_TRGSEL_TIOA_0 (0x1 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 0 -#define DACC_MR_TRGSEL_TIOA_1 (0x2 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 1 -#define DACC_MR_TRGSEL_TIOA_2 (0x3 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 2 -#define DACC_MR_TRGSEL_PWM_0 (0x4 << 1) // (DACC_MR) PWM Event Line 0 -#define DACC_MR_TRGSEL_PWM_1 (0x5 << 1) // (DACC_MR) PWM Event Line 1 -#define DACC_MR_WORD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_WORD_HALF (0x0 << 4) /**< \brief (DACC_MR) Half-Word Transfer */ -#define DACC_MR_WORD_WORLD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_SLEEP (0x1 << 5) /**< \brief (DACC_MR) Sleep Mode */ -#define DACC_MR_SLEEP_NORMAL (0x0 << 5) // (DACC_MR) Normal Mode -#define DACC_MR_SLEEP_SLEEP (0x1 << 5) // (DACC_MR) Sleep Modes -#define DACC_MR_FASTWKUP (0x1 << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ -#define DACC_MR_REFRESH (0xff << 8) /**< \brief (DACC_MR) Refresh Period */ -#define DACC_MR_USER_SEL (0x3 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_0 (0x0 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_1 (0x1 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_TAG (0x1 << 20) /**< \brief (DACC_MR) Tag Selection Mode */ -#define DACC_MR_MAXS (0x1 << 21) /**< \brief (DACC_MR) Max Speed Mode */ -#define DACC_MR_STARTUP (0x3f << 24) /**< \brief (DACC_MR) Startup Time Selection */ -/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ -#define DACC_CHER_CH0 (0x1 << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ -#define DACC_CHER_CH1 (0x1 << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ -#define DACC_CHER_CH2 (0x1 << 2) /**< \brief (DACC_CHER) Channel 2 Enable */ -/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ -#define DACC_CHDR_CH0 (0x1 << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ -#define DACC_CHDR_CH1 (0x1 << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ -#define DACC_CHDR_CH2 (0x1 << 2) /**< \brief (DACC_CHDR) Channel 2 Disable */ -/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ -#define DACC_CHSR_CH0 (0x1 << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ -#define DACC_CHSR_CH1 (0x1 << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ -#define DACC_CHSR_CH2 (0x1 << 2) /**< \brief (DACC_CHSR) Channel 2 Status */ -/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ -#define DACC_CDR_DATA (0xffffffff << 0) /**< \brief (DACC_CDR) Data to Convert */ -/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ -#define DACC_IER_TXRDY (0x1 << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ -#define DACC_IER_EOC (0x1 << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ -#define DACC_IER_ENDTX (0x1 << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ -#define DACC_IER_TXBUFE (0x1 << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ -#define DACC_IDR_TXRDY (0x1 << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ -#define DACC_IDR_EOC (0x1 << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ -#define DACC_IDR_ENDTX (0x1 << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ -#define DACC_IDR_TXBUFE (0x1 << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define DACC_IMR_TXRDY (0x1 << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ -#define DACC_IMR_EOC (0x1 << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ -#define DACC_IMR_ENDTX (0x1 << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ -#define DACC_IMR_TXBUFE (0x1 << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ -#define DACC_ISR_TXRDY (0x1 << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ -#define DACC_ISR_EOC (0x1 << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ -#define DACC_ISR_ENDTX (0x1 << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ -#define DACC_ISR_TXBUFE (0x1 << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ -/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ -#define DACC_ACR_IBCTLCH0 (0x3 << 0) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLCH1 (0x3 << 2) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLDACCORE (0x3 << 8) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ -/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ -#define DACC_WPMR_WPEN (0x1 << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ -#define DACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (DACC_WPMR) Write Protect KEY */ -/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ -#define DACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (DACC_WPSR) Write protection error */ -#define DACC_WPSR_WPROTADDR (0xff << 8) /**< \brief (DACC_WPSR) Write protection error address */ -/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ -#define DACC_RPR_RXPTR (0xffffffff << 0) /**< \brief (DACC_RPR) Receive Pointer Register */ -/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ -#define DACC_RCR_RXCTR (0xffff << 0) /**< \brief (DACC_RCR) Receive Counter Register */ -/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ -#define DACC_TPR_TXPTR (0xffffffff << 0) /**< \brief (DACC_TPR) Transmit Counter Register */ -/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ -#define DACC_TCR_TXCTR (0xffff << 0) /**< \brief (DACC_TCR) Transmit Counter Register */ -/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ -#define DACC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (DACC_RNPR) Receive Next Pointer */ -/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ -#define DACC_RNCR_RXNCTR (0xffff << 0) /**< \brief (DACC_RNCR) Receive Next Counter */ -/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define DACC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (DACC_TNPR) Transmit Next Pointer */ -/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define DACC_TNCR_TXNCTR (0xffff << 0) /**< \brief (DACC_TNCR) Transmit Counter Next */ -/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ -#define DACC_PTCR_RXTEN (0x1 << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ -#define DACC_PTCR_RXTDIS (0x1 << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ -#define DACC_PTCR_TXTEN (0x1 << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ -#define DACC_PTCR_TXTDIS (0x1 << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ -/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ -#define DACC_PTSR_RXTEN (0x1 << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ -#define DACC_PTSR_TXTEN (0x1 << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_EFC Embedded Flash Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Efc hardware registers */ -typedef struct { - RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ - WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ - RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ - RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ -} Efc; -#endif /* __ASSEMBLY__ */ -/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ -#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ -#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ -#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ -/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ -#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ -#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ -#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ -/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ -#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ -#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ -/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ -#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_GPBR General Purpose Backup Register */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Gpbr hardware registers */ -typedef struct { - RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ - RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ - RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ - RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ -} Gpbr; -#endif /* __ASSEMBLY__ */ -/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ -#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ -/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ -#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ -/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ -#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ -/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ -#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_HSMCI High Speed MultiMedia Card Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Hsmci hardware registers */ -typedef struct { - WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ - RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ - RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ - RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ - RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ - WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ - RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ - RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ - RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ - RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ - WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ - RwReg Reserved1[2]; - RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ - WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ - WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ - RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved2[1]; - RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ - RwReg Reserved3[35]; - RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ - RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved4[5]; - RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ - RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ - RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ - RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ - RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ - RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ - RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ - RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ - WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ - RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ -} Hsmci; -#endif /* __ASSEMBLY__ */ -/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ -#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ -#define HSMCI_CR_MCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ -#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ -#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ -#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ -/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ -#define HSMCI_MR_CLKDIV (0xff << 0) /**< \brief (HSMCI_MR) Clock Divider */ -#define HSMCI_MR_PWSDIV (0x7 << 8) /**< \brief (HSMCI_MR) Power Saving Divider */ -#define HSMCI_MR_RDPROOF (0x1 << 11) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_WRPROOF (0x1 << 12) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_FBYTE (0x1 << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ -#define HSMCI_MR_PADV (0x1 << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_PDCMODE (0x1 << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ -#define HSMCI_MR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_MR) Data Block Length */ -/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ -#define HSMCI_DTOR_DTOCYC (0xf << 0) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ -#define HSMCI_DTOR_DTOMUL (0x7 << 4) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ -/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ -#define HSMCI_SDCR_SDCSEL (0x3 << 0) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ -#define HSMCI_SDCR_SDCBUS (0x3 << 6) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ -/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ -#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ -/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ -#define HSMCI_CMDR_CMDNB (0x3f << 0) /**< \brief (HSMCI_CMDR) Command Number */ -#define HSMCI_CMDR_RSPTYP (0x3 << 6) /**< \brief (HSMCI_CMDR) Response Type */ -#define HSMCI_CMDR_SPCMD (0x7 << 8) /**< \brief (HSMCI_CMDR) Special Command */ -#define HSMCI_CMDR_OPDCMD (0x1 << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ -#define HSMCI_CMDR_MAXLAT (0x1 << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ -#define HSMCI_CMDR_TRCMD (0x3 << 16) /**< \brief (HSMCI_CMDR) Transfer Command */ -#define HSMCI_CMDR_TRDIR (0x1 << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ -#define HSMCI_CMDR_TRTYP (0x7 << 19) /**< \brief (HSMCI_CMDR) Transfer Type */ -#define HSMCI_CMDR_IOSPCMD (0x3 << 24) /**< \brief (HSMCI_CMDR) SDIO Special Command */ -#define HSMCI_CMDR_ATACS (0x1 << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ -#define HSMCI_CMDR_BOOT_ACK (0x1 << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ -/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ -#define HSMCI_BLKR_BCNT (0xffff << 0) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ -#define HSMCI_BLKR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_BLKR) Data Block Length */ -/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ -#define HSMCI_CSTOR_CSTOCYC (0xf << 0) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ -#define HSMCI_CSTOR_CSTOMUL (0x7 << 4) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ -/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ -#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ -/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ -#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ -/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ -#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ -/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ -#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ -#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ -#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ -#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ -#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ -#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ -#define HSMCI_SR_ENDRX (0x1 << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ -#define HSMCI_SR_ENDTX (0x1 << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ -#define HSMCI_SR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ -#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ -#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ -#define HSMCI_SR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ -#define HSMCI_SR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ -#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ -#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ -#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ -#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ -#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ -#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ -#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ -#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ -#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ -#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ -#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ -#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ -#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ -#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ -/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ -#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ -#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ -#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ -#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ -#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ -#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ -#define HSMCI_IER_ENDRX (0x1 << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ -#define HSMCI_IER_ENDTX (0x1 << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ -#define HSMCI_IER_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ -#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ -#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ -#define HSMCI_IER_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ -#define HSMCI_IER_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ -#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ -#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ -#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ -#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ -#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ -#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ -#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ -#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ -#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ -#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ -#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ -#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ -#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ -#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ -/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ -#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ -#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ -#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ -#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ -#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ -#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ -#define HSMCI_IDR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ -#define HSMCI_IDR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ -#define HSMCI_IDR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ -#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ -#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ -#define HSMCI_IDR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ -#define HSMCI_IDR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ -#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ -#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ -#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ -#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ -#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ -#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ -#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ -#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ -#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ -#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ -#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ -#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ -#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ -/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ -#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ -#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ -#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ -#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ -#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ -#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ -#define HSMCI_IMR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ -#define HSMCI_IMR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ -#define HSMCI_IMR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ -#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ -#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ -#define HSMCI_IMR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ -#define HSMCI_IMR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ -#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ -#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ -#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ -#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ -#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ -#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ -#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ -#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ -#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ -#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ -#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ -#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ -#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ -/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ -#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ -#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ -#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ -#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ -/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ -#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ -#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ -/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ -#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ -/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ -#define HSMCI_RPR_RXPTR (0xffffffff << 0) /**< \brief (HSMCI_RPR) Receive Pointer Register */ -/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ -#define HSMCI_RCR_RXCTR (0xffff << 0) /**< \brief (HSMCI_RCR) Receive Counter Register */ -/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ -#define HSMCI_TPR_TXPTR (0xffffffff << 0) /**< \brief (HSMCI_TPR) Transmit Counter Register */ -/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ -#define HSMCI_TCR_TXCTR (0xffff << 0) /**< \brief (HSMCI_TCR) Transmit Counter Register */ -/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ -#define HSMCI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ -/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ -#define HSMCI_RNCR_RXNCTR (0xffff << 0) /**< \brief (HSMCI_RNCR) Receive Next Counter */ -/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define HSMCI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ -/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define HSMCI_TNCR_TXNCTR (0xffff << 0) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ -/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ -#define HSMCI_PTCR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ -#define HSMCI_PTCR_RXTDIS (0x1 << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ -#define HSMCI_PTCR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ -#define HSMCI_PTCR_TXTDIS (0x1 << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ -/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ -#define HSMCI_PTSR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ -#define HSMCI_PTSR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_MATRIX AHB Bus Matrix */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Matrix hardware registers */ -typedef struct { - RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ - RwReg Reserved1[12]; - RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ - RwReg Reserved2[11]; - RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ - RwReg Reserved3[1]; - RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ - RwReg Reserved4[1]; - RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ - RwReg Reserved5[1]; - RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ - RwReg Reserved6[1]; - RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ - RwReg Reserved7[28]; - RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System IO Configuration register */ - RwReg Reserved8[1]; - RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ - RwReg Reserved9[49]; - RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ - RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ -} Matrix; -#endif /* __ASSEMBLY__ */ -/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ -#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ -/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ -#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ -#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ -#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ -#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ -/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ -#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ -#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ -#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ -#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ -#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ -/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ -#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ -#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ -#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ -#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ -#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ -/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ -#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ -#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ -#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ -#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ -#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ -/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ -#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ -#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ -#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ -#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ -#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ -/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ -#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ -#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ -#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ -#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ -#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ -/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System IO Configuration register -------- */ -#define CCFG_SYSIO_SYSIO4 (0x1 << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ -#define CCFG_SYSIO_SYSIO5 (0x1 << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ -#define CCFG_SYSIO_SYSIO6 (0x1 << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ -#define CCFG_SYSIO_SYSIO7 (0x1 << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ -#define CCFG_SYSIO_SYSIO10 (0x1 << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ -#define CCFG_SYSIO_SYSIO11 (0x1 << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ -#define CCFG_SYSIO_SYSIO12 (0x1 << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ -/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ -#define CCFG_SMCNFCS_SMC_NFCS0 (0x1 << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS1 (0x1 << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS2 (0x1 << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS3 (0x1 << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ -/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ -#define MATRIX_WPMR_WPEN (0x1 << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ -#define MATRIX_WPMR_WPKEY (0xffffff << 8) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ -/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ -#define MATRIX_WPSR_WPVS (0x1 << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ -#define MATRIX_WPSR_WPVSRC (0xffff << 8) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PDC Peripheral DMA Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pdc hardware registers */ -typedef struct { - RwReg Reserved1[64]; - RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ - RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ - RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ - RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ - RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ - RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ - RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ - RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ - WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ - RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ -} Pdc; -#endif /* __ASSEMBLY__ */ -/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ -#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ -/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ -#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ -/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ -#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ -/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ -#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ -/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ -#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ -/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ -#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ -/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ -/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ -/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ -#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ -#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ -#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ -#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ -/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ -#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PIO Parallel Input/Output */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pio hardware registers */ -typedef struct { - WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ - WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ - RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ - RwReg Reserved1[1]; - WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ - WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ - RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ - RwReg Reserved2[1]; - WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ - WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ - RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ - RwReg Reserved3[1]; - WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ - WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ - RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ - RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ - WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ - WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ - RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ - RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ - WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ - WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ - RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ - RwReg Reserved4[1]; - WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ - WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ - RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ - RwReg Reserved5[1]; - RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ - RwReg Reserved6[2]; - WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ - WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ - RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ - RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ - WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ - WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ - RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ - RwReg Reserved7[1]; - WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ - WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ - RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ - RwReg Reserved8[1]; - WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ - WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ - RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ - RwReg Reserved9[1]; - WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ - WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ - RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ - RwReg Reserved10[1]; - WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ - WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ - RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ - RwReg Reserved11[1]; - RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ - RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ - RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved12[5]; - RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ - RwReg Reserved13[19]; - RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ - WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ - WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ - RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ - RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ - RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ - RwReg Reserved14[38]; -} Pio; -#endif /* __ASSEMBLY__ */ -/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ -#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ -/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ -#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ -/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ -#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ -/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ -#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ -/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ -#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ -/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ -#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ -/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ -#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ -/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ -#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ -/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ -#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ -/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ -#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ -/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ -#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ -/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ -#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ -/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ -#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ -/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ -#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ -#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ -#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ -#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ -#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ -/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ -#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ -#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ -/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ -#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ -/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ -#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ -/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ -#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ -/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ -#define PIO_ABCDSR_P0 (0x1 << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P1 (0x1 << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P2 (0x1 << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P3 (0x1 << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P4 (0x1 << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P5 (0x1 << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P6 (0x1 << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P7 (0x1 << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P8 (0x1 << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P9 (0x1 << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P10 (0x1 << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P11 (0x1 << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P12 (0x1 << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P13 (0x1 << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P14 (0x1 << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P15 (0x1 << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P16 (0x1 << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P17 (0x1 << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P18 (0x1 << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P19 (0x1 << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P20 (0x1 << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P21 (0x1 << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P22 (0x1 << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P23 (0x1 << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P24 (0x1 << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P25 (0x1 << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P26 (0x1 << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P27 (0x1 << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P28 (0x1 << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P29 (0x1 << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P30 (0x1 << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P31 (0x1 << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ -#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ -#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ -#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ -#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ -#define PIO_PPDDR_P0 (0x1 << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P1 (0x1 << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P2 (0x1 << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P3 (0x1 << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P4 (0x1 << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P5 (0x1 << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P6 (0x1 << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P7 (0x1 << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P8 (0x1 << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P9 (0x1 << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P10 (0x1 << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P11 (0x1 << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P12 (0x1 << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P13 (0x1 << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P14 (0x1 << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P15 (0x1 << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P16 (0x1 << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P17 (0x1 << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P18 (0x1 << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P19 (0x1 << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P20 (0x1 << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P21 (0x1 << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P22 (0x1 << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P23 (0x1 << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P24 (0x1 << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P25 (0x1 << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P26 (0x1 << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P27 (0x1 << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P28 (0x1 << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P29 (0x1 << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P30 (0x1 << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P31 (0x1 << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ -#define PIO_PPDER_P0 (0x1 << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P1 (0x1 << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P2 (0x1 << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P3 (0x1 << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P4 (0x1 << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P5 (0x1 << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P6 (0x1 << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P7 (0x1 << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P8 (0x1 << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P9 (0x1 << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P10 (0x1 << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P11 (0x1 << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P12 (0x1 << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P13 (0x1 << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P14 (0x1 << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P15 (0x1 << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P16 (0x1 << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P17 (0x1 << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P18 (0x1 << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P19 (0x1 << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P20 (0x1 << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P21 (0x1 << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P22 (0x1 << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P23 (0x1 << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P24 (0x1 << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P25 (0x1 << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P26 (0x1 << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P27 (0x1 << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P28 (0x1 << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P29 (0x1 << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P30 (0x1 << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P31 (0x1 << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ -/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ -#define PIO_PPDSR_P0 (0x1 << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P1 (0x1 << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P2 (0x1 << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P3 (0x1 << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P4 (0x1 << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P5 (0x1 << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P6 (0x1 << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P7 (0x1 << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P8 (0x1 << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P9 (0x1 << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P10 (0x1 << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P11 (0x1 << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P12 (0x1 << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P13 (0x1 << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P14 (0x1 << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P15 (0x1 << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P16 (0x1 << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P17 (0x1 << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P18 (0x1 << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P19 (0x1 << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P20 (0x1 << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P21 (0x1 << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P22 (0x1 << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P23 (0x1 << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P24 (0x1 << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P25 (0x1 << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P26 (0x1 << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P27 (0x1 << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P28 (0x1 << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P29 (0x1 << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P30 (0x1 << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P31 (0x1 << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ -/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ -#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ -/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ -#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ -/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ -#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ -/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ -#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ -#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ -#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ -#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ -#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ -#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ -#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ -#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ -#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ -#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ -/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ -#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ -/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ -#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ -/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ -#define PIO_SCHMITT_SCHMITT0 (0x1 << 0) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT1 (0x1 << 1) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT2 (0x1 << 2) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT3 (0x1 << 3) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT4 (0x1 << 4) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT5 (0x1 << 5) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT6 (0x1 << 6) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT7 (0x1 << 7) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT8 (0x1 << 8) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT9 (0x1 << 9) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT10 (0x1 << 10) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT11 (0x1 << 11) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT12 (0x1 << 12) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT13 (0x1 << 13) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT14 (0x1 << 14) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT15 (0x1 << 15) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT16 (0x1 << 16) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT17 (0x1 << 17) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT18 (0x1 << 18) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT19 (0x1 << 19) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT20 (0x1 << 20) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT21 (0x1 << 21) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT22 (0x1 << 22) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT23 (0x1 << 23) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT24 (0x1 << 24) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT25 (0x1 << 25) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT26 (0x1 << 26) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT27 (0x1 << 27) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT28 (0x1 << 28) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT29 (0x1 << 29) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT30 (0x1 << 30) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT31 (0x1 << 31) /**< \brief (PIO_SCHMITT) */ -/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ -#define PIO_PCMR_PCEN (0x1 << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ -#define PIO_PCMR_DSIZE (0x3 << 4) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ -#define PIO_PCMR_ALWYS (0x1 << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ -#define PIO_PCMR_HALFS (0x1 << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ -#define PIO_PCMR_FRSTS (0x1 << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ -/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ -#define PIO_PCIER_DRDY (0x1 << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ -#define PIO_PCIER_OVRE (0x1 << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ -#define PIO_PCIER_ENDRX (0x1 << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ -#define PIO_PCIER_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ -/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ -#define PIO_PCIDR_DRDY (0x1 << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ -#define PIO_PCIDR_OVRE (0x1 << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ -#define PIO_PCIDR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ -#define PIO_PCIDR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ -/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ -#define PIO_PCIMR_DRDY (0x1 << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ -#define PIO_PCIMR_OVRE (0x1 << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ -#define PIO_PCIMR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ -#define PIO_PCIMR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ -/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ -#define PIO_PCISR_DRDY (0x1 << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ -#define PIO_PCISR_OVRE (0x1 << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ -#define PIO_PCISR_ENDRX (0x1 << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ -#define PIO_PCISR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ -/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ -#define PIO_PCRHR_RDATA (0xffffffff << 0) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Power Management Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PMC Power Management Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pmc hardware registers */ -typedef struct { - WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ - WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ - RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ - RwReg Reserved1[1]; - WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ - WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ - RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ - RwReg Reserved2[1]; - RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ - RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ - RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ - RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ - RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ - RwReg Reserved3[1]; - RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ - RwReg Reserved4[1]; - RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ - RwReg Reserved5[5]; - WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ - WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ - RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ - RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ - RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ - RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ - WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ - RwReg Reserved6[26]; - RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ - RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved7[5]; - WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ - WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ - RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ - RwReg Reserved8[1]; - RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ -} Pmc; -#endif /* __ASSEMBLY__ */ -/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ -#define PMC_SCER_UDP (0x1 << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ -#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ -#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ -#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ -/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ -#define PMC_SCDR_UDP (0x1 << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ -#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ -#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ -#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ -/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ -#define PMC_SCSR_UDP (0x1 << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ -#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ -#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ -#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ -/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ -#define PMC_PCER0_PID2 (0x1 << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ -#define PMC_PCER0_PID3 (0x1 << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ -#define PMC_PCER0_PID4 (0x1 << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ -#define PMC_PCER0_PID5 (0x1 << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ -#define PMC_PCER0_PID6 (0x1 << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ -#define PMC_PCER0_PID7 (0x1 << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ -#define PMC_PCER0_PID8 (0x1 << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ -#define PMC_PCER0_PID9 (0x1 << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ -#define PMC_PCER0_PID10 (0x1 << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ -#define PMC_PCER0_PID11 (0x1 << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ -#define PMC_PCER0_PID12 (0x1 << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ -#define PMC_PCER0_PID13 (0x1 << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ -#define PMC_PCER0_PID14 (0x1 << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ -#define PMC_PCER0_PID15 (0x1 << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ -#define PMC_PCER0_PID16 (0x1 << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1 << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ -#define PMC_PCER0_PID18 (0x1 << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ -#define PMC_PCER0_PID19 (0x1 << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ -#define PMC_PCER0_PID20 (0x1 << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ -#define PMC_PCER0_PID21 (0x1 << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ -#define PMC_PCER0_PID22 (0x1 << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ -#define PMC_PCER0_PID23 (0x1 << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ -#define PMC_PCER0_PID24 (0x1 << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ -#define PMC_PCER0_PID25 (0x1 << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ -#define PMC_PCER0_PID26 (0x1 << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ -#define PMC_PCER0_PID27 (0x1 << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ -#define PMC_PCER0_PID28 (0x1 << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ -#define PMC_PCER0_PID29 (0x1 << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ -#define PMC_PCER0_PID30 (0x1 << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ -#define PMC_PCER0_PID31 (0x1 << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ -/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ -#define PMC_PCDR0_PID2 (0x1 << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ -#define PMC_PCDR0_PID3 (0x1 << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ -#define PMC_PCDR0_PID4 (0x1 << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ -#define PMC_PCDR0_PID5 (0x1 << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ -#define PMC_PCDR0_PID6 (0x1 << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ -#define PMC_PCDR0_PID7 (0x1 << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ -#define PMC_PCDR0_PID8 (0x1 << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ -#define PMC_PCDR0_PID9 (0x1 << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ -#define PMC_PCDR0_PID10 (0x1 << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ -#define PMC_PCDR0_PID11 (0x1 << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ -#define PMC_PCDR0_PID12 (0x1 << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ -#define PMC_PCDR0_PID13 (0x1 << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ -#define PMC_PCDR0_PID14 (0x1 << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ -#define PMC_PCDR0_PID15 (0x1 << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ -#define PMC_PCDR0_PID16 (0x1 << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1 << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ -#define PMC_PCDR0_PID18 (0x1 << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ -#define PMC_PCDR0_PID19 (0x1 << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ -#define PMC_PCDR0_PID20 (0x1 << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ -#define PMC_PCDR0_PID21 (0x1 << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ -#define PMC_PCDR0_PID22 (0x1 << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ -#define PMC_PCDR0_PID23 (0x1 << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ -#define PMC_PCDR0_PID24 (0x1 << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ -#define PMC_PCDR0_PID25 (0x1 << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ -#define PMC_PCDR0_PID26 (0x1 << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ -#define PMC_PCDR0_PID27 (0x1 << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ -#define PMC_PCDR0_PID28 (0x1 << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ -#define PMC_PCDR0_PID29 (0x1 << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ -#define PMC_PCDR0_PID30 (0x1 << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ -#define PMC_PCDR0_PID31 (0x1 << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ -/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ -#define PMC_PCSR0_PID2 (0x1 << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ -#define PMC_PCSR0_PID3 (0x1 << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ -#define PMC_PCSR0_PID4 (0x1 << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ -#define PMC_PCSR0_PID5 (0x1 << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ -#define PMC_PCSR0_PID6 (0x1 << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ -#define PMC_PCSR0_PID7 (0x1 << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ -#define PMC_PCSR0_PID8 (0x1 << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ -#define PMC_PCSR0_PID9 (0x1 << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ -#define PMC_PCSR0_PID10 (0x1 << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ -#define PMC_PCSR0_PID11 (0x1 << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ -#define PMC_PCSR0_PID12 (0x1 << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ -#define PMC_PCSR0_PID13 (0x1 << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ -#define PMC_PCSR0_PID14 (0x1 << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ -#define PMC_PCSR0_PID15 (0x1 << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ -#define PMC_PCSR0_PID16 (0x1 << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1 << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ -#define PMC_PCSR0_PID18 (0x1 << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ -#define PMC_PCSR0_PID19 (0x1 << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ -#define PMC_PCSR0_PID20 (0x1 << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ -#define PMC_PCSR0_PID21 (0x1 << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ -#define PMC_PCSR0_PID22 (0x1 << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ -#define PMC_PCSR0_PID23 (0x1 << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ -#define PMC_PCSR0_PID24 (0x1 << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ -#define PMC_PCSR0_PID25 (0x1 << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ -#define PMC_PCSR0_PID26 (0x1 << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ -#define PMC_PCSR0_PID27 (0x1 << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ -#define PMC_PCSR0_PID28 (0x1 << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ -#define PMC_PCSR0_PID29 (0x1 << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ -#define PMC_PCSR0_PID30 (0x1 << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ -#define PMC_PCSR0_PID31 (0x1 << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ -/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ -#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ -#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ -/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ -#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ -#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ -/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ -#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ -#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ -#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ -#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ -/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ -#define CKGR_PLLBR_DIVB (0xff << 0) /**< \brief (CKGR_PLLBR) Divider */ -#define CKGR_PLLBR_PLLBCOUNT (0x3f << 8) /**< \brief (CKGR_PLLBR) PLLB Counter */ -#define CKGR_PLLBR_MULB (0x7ff << 16) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ -/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ -#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ -#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ -#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ -#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */ -#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ -#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ -#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ -#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ -#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ -#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ -#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ -#define PMC_MCKR_PLLADIV2 (0x1 << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ -#define PMC_MCKR_PLLBDIV2 (0x1 << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ -/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ -#define PMC_USB_USBS (0x1 << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ -#define PMC_USB_USBDIV (0xf << 8) /**< \brief (PMC_USB) Divider for USB Clock. */ -/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ -#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ -#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ -/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ -#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ -#define PMC_IER_LOCKB (0x1 << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ -#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ -/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ -#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ -#define PMC_IDR_LOCKB (0x1 << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ -/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ -#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ -#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLLA Lock Status */ -#define PMC_SR_LOCKB (0x1 << 2) /**< \brief (PMC_SR) PLLB Lock Status */ -#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ -#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ -#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ -#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ -#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ -#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ -#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ -/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ -#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ -#define PMC_IMR_LOCKB (0x1 << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ -/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ -#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ -#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ -#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ -#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ -#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ -#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ -#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ -#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ -#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ -#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ -#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ -#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ -#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ -#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ -#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ -#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ -#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ -#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ -#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ -#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ -/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ -#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ -#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ -/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PMC_WPMR_WPEN (0x1 << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ -#define PMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (PMC_WPMR) Write Protect KEY */ -/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ -#define PMC_WPSR_WPVS (0x1 << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (PMC_WPSR) Write Protect Violation Source */ -/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ -#define PMC_PCER1_PID32 (0x1 << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ -#define PMC_PCER1_PID33 (0x1 << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ -#define PMC_PCER1_PID34 (0x1 << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ -#define PMC_PCER1_PID35 (0x1 << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ -#define PMC_PCER1_PID36 (0x1 << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ -#define PMC_PCER1_PID37 (0x1 << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ -#define PMC_PCER1_PID38 (0x1 << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ -#define PMC_PCER1_PID39 (0x1 << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ -#define PMC_PCER1_PID40 (0x1 << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ -#define PMC_PCER1_PID41 (0x1 << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ -#define PMC_PCER1_PID42 (0x1 << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ -#define PMC_PCER1_PID43 (0x1 << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ -#define PMC_PCER1_PID44 (0x1 << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ -#define PMC_PCER1_PID45 (0x1 << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ -#define PMC_PCER1_PID46 (0x1 << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ -#define PMC_PCER1_PID47 (0x1 << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ -#define PMC_PCER1_PID48 (0x1 << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ -#define PMC_PCER1_PID49 (0x1 << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ -#define PMC_PCER1_PID50 (0x1 << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ -#define PMC_PCER1_PID51 (0x1 << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ -#define PMC_PCER1_PID52 (0x1 << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ -#define PMC_PCER1_PID53 (0x1 << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ -#define PMC_PCER1_PID54 (0x1 << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ -#define PMC_PCER1_PID55 (0x1 << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ -#define PMC_PCER1_PID56 (0x1 << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ -#define PMC_PCER1_PID57 (0x1 << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ -#define PMC_PCER1_PID58 (0x1 << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ -#define PMC_PCER1_PID59 (0x1 << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ -#define PMC_PCER1_PID60 (0x1 << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ -#define PMC_PCER1_PID61 (0x1 << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ -#define PMC_PCER1_PID62 (0x1 << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ -#define PMC_PCER1_PID63 (0x1 << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ -/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ -#define PMC_PCDR1_PID32 (0x1 << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ -#define PMC_PCDR1_PID33 (0x1 << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ -#define PMC_PCDR1_PID34 (0x1 << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ -#define PMC_PCDR1_PID35 (0x1 << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ -#define PMC_PCDR1_PID36 (0x1 << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ -#define PMC_PCDR1_PID37 (0x1 << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ -#define PMC_PCDR1_PID38 (0x1 << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ -#define PMC_PCDR1_PID39 (0x1 << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ -#define PMC_PCDR1_PID40 (0x1 << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ -#define PMC_PCDR1_PID41 (0x1 << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ -#define PMC_PCDR1_PID42 (0x1 << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ -#define PMC_PCDR1_PID43 (0x1 << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ -#define PMC_PCDR1_PID44 (0x1 << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ -#define PMC_PCDR1_PID45 (0x1 << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ -#define PMC_PCDR1_PID46 (0x1 << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ -#define PMC_PCDR1_PID47 (0x1 << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ -#define PMC_PCDR1_PID48 (0x1 << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ -#define PMC_PCDR1_PID49 (0x1 << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ -#define PMC_PCDR1_PID50 (0x1 << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ -#define PMC_PCDR1_PID51 (0x1 << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ -#define PMC_PCDR1_PID52 (0x1 << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ -#define PMC_PCDR1_PID53 (0x1 << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ -#define PMC_PCDR1_PID54 (0x1 << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ -#define PMC_PCDR1_PID55 (0x1 << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ -#define PMC_PCDR1_PID56 (0x1 << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ -#define PMC_PCDR1_PID57 (0x1 << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ -#define PMC_PCDR1_PID58 (0x1 << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ -#define PMC_PCDR1_PID59 (0x1 << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ -#define PMC_PCDR1_PID60 (0x1 << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ -#define PMC_PCDR1_PID61 (0x1 << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ -#define PMC_PCDR1_PID62 (0x1 << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ -#define PMC_PCDR1_PID63 (0x1 << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ -/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ -#define PMC_PCSR1_PID32 (0x1 << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ -#define PMC_PCSR1_PID33 (0x1 << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ -#define PMC_PCSR1_PID34 (0x1 << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ -#define PMC_PCSR1_PID35 (0x1 << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ -#define PMC_PCSR1_PID36 (0x1 << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ -#define PMC_PCSR1_PID37 (0x1 << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ -#define PMC_PCSR1_PID38 (0x1 << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ -#define PMC_PCSR1_PID39 (0x1 << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ -#define PMC_PCSR1_PID40 (0x1 << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ -#define PMC_PCSR1_PID41 (0x1 << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ -#define PMC_PCSR1_PID42 (0x1 << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ -#define PMC_PCSR1_PID43 (0x1 << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ -#define PMC_PCSR1_PID44 (0x1 << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ -#define PMC_PCSR1_PID45 (0x1 << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ -#define PMC_PCSR1_PID46 (0x1 << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ -#define PMC_PCSR1_PID47 (0x1 << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ -#define PMC_PCSR1_PID48 (0x1 << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ -#define PMC_PCSR1_PID49 (0x1 << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ -#define PMC_PCSR1_PID50 (0x1 << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ -#define PMC_PCSR1_PID51 (0x1 << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ -#define PMC_PCSR1_PID52 (0x1 << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ -#define PMC_PCSR1_PID53 (0x1 << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ -#define PMC_PCSR1_PID54 (0x1 << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ -#define PMC_PCSR1_PID55 (0x1 << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ -#define PMC_PCSR1_PID56 (0x1 << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ -#define PMC_PCSR1_PID57 (0x1 << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ -#define PMC_PCSR1_PID58 (0x1 << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ -#define PMC_PCSR1_PID59 (0x1 << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ -#define PMC_PCSR1_PID60 (0x1 << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ -#define PMC_PCSR1_PID61 (0x1 << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ -#define PMC_PCSR1_PID62 (0x1 << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ -#define PMC_PCSR1_PID63 (0x1 << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ -/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ -#define PMC_OCR_CAL4 (0x7f << 0) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_SEL4 (0x1 << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_CAL8 (0x7f << 8) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_SEL8 (0x1 << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_CAL12 (0x7f << 16) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ -#define PMC_OCR_SEL12 (0x1 << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PWM Pulse Width Modulation Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief PwmCh_num hardware registers */ -typedef struct { - RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ - RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ - RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ - RwReg PWM_CPDR; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ - RwReg PWM_CPDRUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ - RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ - RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ - RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ -} PwmCh_num; -/** \brief Pwm hardware registers */ -typedef struct { - RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ - WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ - WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ - RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ - WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ - WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ - RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ - RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ - RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ - RwReg Reserved1[1]; - RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ - RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ - WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ - WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ - WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ - RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ - RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ - RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ - RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ - WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ - WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ - WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ - WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ - RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ - RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ - WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ - RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ - RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ - RwReg Reserved2[3]; - RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ - RwReg Reserved3[11]; - RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ - RwReg Reserved4[12]; - WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ - RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ - RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ - RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ - RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ - RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ - RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ - RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ - RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ - WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ - RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ - RwReg Reserved6[2]; - RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ - WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ - RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ - WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ - RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ - WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ - RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ - WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ - RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ - WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ - RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ - WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ - RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ - WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ - RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ - WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ - RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ - WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ - RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ - WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ - RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ - WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ - RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ - WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ - RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ - WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ - RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ - WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ - RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ - WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ - RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ - WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ - RwReg Reserved7[20]; - PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ -} Pwm; -#endif /* __ASSEMBLY__ */ -/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ -#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ -#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ -/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ -#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ -/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ -#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ -/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ -#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ -#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ -#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ -#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ -#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ -#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ -#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ -#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ -/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ -#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ -#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ -#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ -#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ -#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ -#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ -#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ -#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ -/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ -#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ -#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ -#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ -#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ -#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ -#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ -#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ -#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ -/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ -#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ -#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ -#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ -#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ -#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ -#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ -#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ -#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ -/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ -#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ -#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ -#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ -#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ -#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ -#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ -#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ -/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ -#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ -/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ -#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ -#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ -/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ -#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ -/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ -#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ -#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ -#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ -#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ -#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ -#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ -#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ -#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ -#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ -#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ -#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ -#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ -#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ -#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ -#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ -#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ -#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ -#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ -#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ -#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ -/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ -#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ -#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ -#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ -#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ -#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ -#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ -#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ -#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ -#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ -#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ -#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ -#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ -#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ -#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ -#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ -#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ -#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ -#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ -#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ -#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ -/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ -#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ -#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ -#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ -#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ -#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ -#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ -#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ -#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ -#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ -#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ -#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ -#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ -#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ -#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ -#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ -#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ -#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ -#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ -#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ -#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ -/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ -#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ -#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ -#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ -#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ -#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ -#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ -#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ -#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ -#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ -#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ -#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ -#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ -#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ -#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ -#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ -#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ -#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ -#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ -#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ -#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ -/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ -#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ -#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ -#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ -#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ -#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ -#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ -#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ -#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ -/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ -#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ -#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ -#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ -#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ -#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ -#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ -#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ -#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ -/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ -#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ -#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ -#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ -#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ -#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ -#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ -#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ -#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ -#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ -#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ -#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ -#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ -#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ -#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ -#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ -#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ -/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ -#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ -#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ -#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ -#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ -#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ -#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ -#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ -#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ -/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ -#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ -#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ -#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ -#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ -/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ -#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ -#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ -#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ -#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ -#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ -#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ -#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ -#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ -/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ -#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ -#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ -#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ -#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ -/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ -#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ -#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ -#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ -#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ -#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ -#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ -#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ -#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ -/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ -#define PWM_SMMR_GCEN0 (0x1 << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_GCEN1 (0x1 << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_DOWN0 (0x1 << 16) /**< \brief (PWM_SMMR) DOWN Count */ -#define PWM_SMMR_DOWN1 (0x1 << 17) /**< \brief (PWM_SMMR) DOWN Count */ -/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ -#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ -#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ -#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ -#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ -#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ -#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ -#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ -#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ -/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ -#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ -#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ -/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ -#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ -/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ -#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ -/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ -#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ -/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ -#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ -/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ -#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ -/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ -#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ -/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ -/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ -/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ -#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ -#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ -#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ -#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ -/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ -#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ -#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ -/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ -#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ -#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ -/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ -#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ -#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ -#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ -#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ -#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ -#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ -#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ -#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ -/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ -#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ -#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ -#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ -#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ -#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ -#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ -/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ -#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ -#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ -#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ -#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ -#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ -#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ -#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ -#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ -/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ -#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ -#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ -#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ -#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ -#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ -#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ -/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ -#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ -#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ -#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ -#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ -#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ -#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ -#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ -#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ -/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ -#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ -#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ -#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ -#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ -#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ -#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ -/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ -#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ -#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ -#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ -#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ -#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ -#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ -#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ -#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ -/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ -#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ -#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ -#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ -#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ -#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ -#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ -/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ -#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ -#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ -#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ -#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ -#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ -#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ -#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ -#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ -/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ -#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ -#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ -#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ -#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ -#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ -#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ -/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ -#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ -#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ -#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ -#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ -#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ -#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ -#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ -#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ -/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ -#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ -#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ -#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ -#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ -#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ -#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ -/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ -#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ -#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ -#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ -#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ -#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ -#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ -#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ -#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ -/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ -#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ -#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ -#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ -#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ -#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ -#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ -/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ -#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ -#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ -#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ -#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ -#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ -#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ -#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ -#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ -/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ -#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ -#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ -#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ -#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ -#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ -#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ -#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ -#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ -#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ -#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ -#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ -#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ -#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ -/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ -#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ -/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ -#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ -/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ -#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ -#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ -#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ -#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ -#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ -#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ -#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ -#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ -#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ -#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ -#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ -#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ -/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ -#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ -/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ -#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ -/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ -#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ -#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ -#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ -#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ -#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ -#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ -#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ -#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ -#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ -#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ -#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ -#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ -/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ -#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ -/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ -#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ -/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ -#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ -#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ -#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ -#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ -#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ -#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ -#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ -#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ -#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ -#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ -#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ -#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ -/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ -#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ -/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ -#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ -/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ -#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ -#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ -#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reset Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RSTC Reset Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rstc hardware registers */ -typedef struct { - WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ - RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ - RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ -} Rstc; -#endif /* __ASSEMBLY__ */ -/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ -#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ -#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ -#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ -#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ -/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ -#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ -#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ -#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ -#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ -/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ -#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ -#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ -#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Clock */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTC Real-time Clock */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtc hardware registers */ -typedef struct { - RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ - RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ - RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ - RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ - RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ - RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ - RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ - WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ - WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ - WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ - RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ - RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ -} Rtc; -#endif /* __ASSEMBLY__ */ -/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ -#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ -#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ -#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ -#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ -#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ -#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ -#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ -#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ -#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ -/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ -#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ -/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ -#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ -#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ -#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ -#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ -/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ -#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ -#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ -#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ -#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ -#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ -/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ -#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ -#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ -#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ -#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ -#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ -#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ -/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ -#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ -#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ -#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ -#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ -/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ -#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ -#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ -#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ -#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ -#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ -/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ -#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ -#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ -#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ -#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ -/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ -#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ -#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ -#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ -/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ -#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ -/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ -#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ -#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ -#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ -#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ -/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ -#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ -#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ -#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTT Real-time Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtt hardware registers */ -typedef struct { - RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ - RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ - RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ - RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ -} Rtt; -#endif /* __ASSEMBLY__ */ -/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ -#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ -#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ -#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ -/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ -#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ -/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ -#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ -/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ -#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ -#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Static Memory Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SMC Static Memory Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief SmcCs_number hardware registers */ -typedef struct { - RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ - RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ - RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ - RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ -} SmcCs_number; -/** \brief Smc hardware registers */ -typedef struct { - SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */ - RwReg Reserved1[12]; - RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ - WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ - WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ - RwReg Reserved2[22]; - RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ - RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ -} Smc; -#endif /* __ASSEMBLY__ */ -/* -------- SMC_SETUP0 : (SMC Offset: 0x0) SMC Setup Register (CS_number = 0) -------- */ -#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup Length */ -#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup Length in WRITE Access */ -#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup Length */ -#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE0 : (SMC Offset: 0x4) SMC Pulse Register (CS_number = 0) -------- */ -#define SMC_PULSE0_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ -#define SMC_PULSE0_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE0_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ -#define SMC_PULSE0_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE0 : (SMC Offset: 0x8) SMC Cycle Register (CS_number = 0) -------- */ -#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ -#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ -/* -------- SMC_MODE0 : (SMC Offset: 0xC) SMC Mode Register (CS_number = 0) -------- */ -#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ -#define SMC_MODE0_DBW (0x3 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ -#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ -#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ -#define SMC_MODE0_PMEN (0x1 << 24) /**< \brief (SMC_MODE0) Page Mode Enabled */ -#define SMC_MODE0_PS (0x3 << 28) /**< \brief (SMC_MODE0) Page Size */ -/* -------- SMC_SETUP1 : (SMC Offset: 0x10) SMC Setup Register (CS_number = 1) -------- */ -#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup Length */ -#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup Length in WRITE Access */ -#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup Length */ -#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE1 : (SMC Offset: 0x14) SMC Pulse Register (CS_number = 1) -------- */ -#define SMC_PULSE1_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ -#define SMC_PULSE1_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE1_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ -#define SMC_PULSE1_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE1 : (SMC Offset: 0x18) SMC Cycle Register (CS_number = 1) -------- */ -#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ -#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ -/* -------- SMC_MODE1 : (SMC Offset: 0x1C) SMC Mode Register (CS_number = 1) -------- */ -#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ -#define SMC_MODE1_DBW (0x3 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ -#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ -#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ -#define SMC_MODE1_PMEN (0x1 << 24) /**< \brief (SMC_MODE1) Page Mode Enabled */ -#define SMC_MODE1_PS (0x3 << 28) /**< \brief (SMC_MODE1) Page Size */ -/* -------- SMC_SETUP2 : (SMC Offset: 0x20) SMC Setup Register (CS_number = 2) -------- */ -#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup Length */ -#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup Length in WRITE Access */ -#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup Length */ -#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE2 : (SMC Offset: 0x24) SMC Pulse Register (CS_number = 2) -------- */ -#define SMC_PULSE2_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ -#define SMC_PULSE2_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE2_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ -#define SMC_PULSE2_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE2 : (SMC Offset: 0x28) SMC Cycle Register (CS_number = 2) -------- */ -#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ -#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ -/* -------- SMC_MODE2 : (SMC Offset: 0x2C) SMC Mode Register (CS_number = 2) -------- */ -#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ -#define SMC_MODE2_DBW (0x3 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ -#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ -#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ -#define SMC_MODE2_PMEN (0x1 << 24) /**< \brief (SMC_MODE2) Page Mode Enabled */ -#define SMC_MODE2_PS (0x3 << 28) /**< \brief (SMC_MODE2) Page Size */ -/* -------- SMC_SETUP3 : (SMC Offset: 0x30) SMC Setup Register (CS_number = 3) -------- */ -#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup Length */ -#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup Length in WRITE Access */ -#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup Length */ -#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE3 : (SMC Offset: 0x34) SMC Pulse Register (CS_number = 3) -------- */ -#define SMC_PULSE3_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ -#define SMC_PULSE3_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE3_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ -#define SMC_PULSE3_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE3 : (SMC Offset: 0x38) SMC Cycle Register (CS_number = 3) -------- */ -#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ -#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ -/* -------- SMC_MODE3 : (SMC Offset: 0x3C) SMC Mode Register (CS_number = 3) -------- */ -#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ -#define SMC_MODE3_DBW (0x3 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ -#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ -#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ -#define SMC_MODE3_PMEN (0x1 << 24) /**< \brief (SMC_MODE3) Page Mode Enabled */ -#define SMC_MODE3_PS (0x3 << 28) /**< \brief (SMC_MODE3) Page Size */ -/* -------- SMC_SETUP4 : (SMC Offset: 0x40) SMC Setup Register (CS_number = 4) -------- */ -#define SMC_SETUP4_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP4) NWE Setup Length */ -#define SMC_SETUP4_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP4) NCS Setup Length in WRITE Access */ -#define SMC_SETUP4_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP4) NRD Setup Length */ -#define SMC_SETUP4_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP4) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE4 : (SMC Offset: 0x44) SMC Pulse Register (CS_number = 4) -------- */ -#define SMC_PULSE4_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE4) NWE Pulse Length */ -#define SMC_PULSE4_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE4) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE4_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE4) NRD Pulse Length */ -#define SMC_PULSE4_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE4) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE4 : (SMC Offset: 0x48) SMC Cycle Register (CS_number = 4) -------- */ -#define SMC_CYCLE4_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE4) Total Write Cycle Length */ -#define SMC_CYCLE4_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE4) Total Read Cycle Length */ -/* -------- SMC_MODE4 : (SMC Offset: 0x4C) SMC Mode Register (CS_number = 4) -------- */ -#define SMC_MODE4_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE4) NWAIT Mode */ -#define SMC_MODE4_DBW (0x3 << 12) /**< \brief (SMC_MODE4) Data Bus Width */ -#define SMC_MODE4_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE4) Data Float Time */ -#define SMC_MODE4_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE4) TDF Optimization */ -#define SMC_MODE4_PMEN (0x1 << 24) /**< \brief (SMC_MODE4) Page Mode Enabled */ -#define SMC_MODE4_PS (0x3 << 28) /**< \brief (SMC_MODE4) Page Size */ -/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ -#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_CS0SE (0x1 << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS1SE (0x1 << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS2SE (0x1 << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS3SE (0x1 << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ -#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ -/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ -#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ -/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ -#define SMC_WPMR_WPEN (0x1 << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ -#define SMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SMC_WPMR) Write Protect KEY */ -/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ -#define SMC_WPSR_WPVS (0x1 << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ -#define SMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SPI Serial Peripheral Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Spi hardware registers */ -typedef struct { - WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ - RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ - RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ - WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ - RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ - WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ - WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ - RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ - RwReg Reserved1[4]; - RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ - RwReg Reserved2[41]; - RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ - RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved3[5]; - RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ - RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ - RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ - RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ - RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ - RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ - RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ - RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ - WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ - RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ -} Spi; -#endif /* __ASSEMBLY__ */ -/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ -#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ -#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ -#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ -#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ -/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ -#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ -#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ -#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ -#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ -#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ -#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ -#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ -#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ -#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ -#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ -/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ -#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ -#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ -/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ -#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ -#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ -#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ -#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ -#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ -#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ -#define SPI_SR_ENDRX (0x1 << 4) /**< \brief (SPI_SR) End of RX buffer */ -#define SPI_SR_ENDTX (0x1 << 5) /**< \brief (SPI_SR) End of TX buffer */ -#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) RX Buffer Full */ -#define SPI_SR_TXBUFE (0x1 << 7) /**< \brief (SPI_SR) TX Buffer Empty */ -#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ -#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ -#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ -#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ -#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ -#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ -#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ -#define SPI_IER_ENDRX (0x1 << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ -#define SPI_IER_ENDTX (0x1 << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ -#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ -#define SPI_IER_TXBUFE (0x1 << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ -#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ -#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ -#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ -#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ -#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ -#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ -#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ -#define SPI_IDR_ENDRX (0x1 << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ -#define SPI_IDR_ENDTX (0x1 << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ -#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ -#define SPI_IDR_TXBUFE (0x1 << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ -#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ -#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ -/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ -#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ -#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ -#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ -#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ -#define SPI_IMR_ENDRX (0x1 << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ -#define SPI_IMR_ENDTX (0x1 << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ -#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ -#define SPI_IMR_TXBUFE (0x1 << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ -#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ -#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ -/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ -#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ -#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ -#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 35.) */ -#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ -#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ -#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ -#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ -#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ -#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ -#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ -#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ -#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ -#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ -#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ -#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ -/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ -#define SPI_WPMR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */ -#define SPI_WPMR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */ -/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ -#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ -/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ -#define SPI_RPR_RXPTR (0xffffffff << 0) /**< \brief (SPI_RPR) Receive Pointer Register */ -/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ -#define SPI_RCR_RXCTR (0xffff << 0) /**< \brief (SPI_RCR) Receive Counter Register */ -/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ -#define SPI_TPR_TXPTR (0xffffffff << 0) /**< \brief (SPI_TPR) Transmit Counter Register */ -/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ -#define SPI_TCR_TXCTR (0xffff << 0) /**< \brief (SPI_TCR) Transmit Counter Register */ -/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ -#define SPI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SPI_RNPR) Receive Next Pointer */ -/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ -#define SPI_RNCR_RXNCTR (0xffff << 0) /**< \brief (SPI_RNCR) Receive Next Counter */ -/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SPI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SPI_TNPR) Transmit Next Pointer */ -/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SPI_TNCR_TXNCTR (0xffff << 0) /**< \brief (SPI_TNCR) Transmit Counter Next */ -/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ -#define SPI_PTCR_RXTEN (0x1 << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ -#define SPI_PTCR_RXTDIS (0x1 << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ -#define SPI_PTCR_TXTEN (0x1 << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ -#define SPI_PTCR_TXTDIS (0x1 << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ -/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ -#define SPI_PTSR_RXTEN (0x1 << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ -#define SPI_PTSR_TXTEN (0x1 << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SSC Synchronous Serial Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Ssc hardware registers */ -typedef struct { - WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ - RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ - RwReg Reserved1[2]; - RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ - RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ - RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ - RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ - RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ - WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ - RwReg Reserved2[2]; - RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ - RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ - RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ - RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ - RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ - WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ - WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ - RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved3[37]; - RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ - RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[5]; - RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ - RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ - RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ - RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ - RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ - RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ - RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ - RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ - WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ - RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ -} Ssc; -#endif /* __ASSEMBLY__ */ -/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ -#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ -#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ -#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ -#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ -#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ -/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ -#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ -/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ -#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ -#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ -#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ -#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ -#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ -#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ -#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ -#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ -#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ -#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ -#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ -#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ -#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ -#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ -/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ -#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ -#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ -#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ -#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ -#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ -#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ -#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ -#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ -/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ -#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ -#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ -#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ -#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ -#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ -#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ -#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ -/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ -#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ -#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ -#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ -#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ -#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ -#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ -#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ -#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ -#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ -/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ -#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ -/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ -#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ -/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ -#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ -/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ -#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ -/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ -#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ -/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ -#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ -/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ -#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ -#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ -#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ -#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ -#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ -#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ -#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ -#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ -#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ -#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ -#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ -#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ -#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ -#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ -/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ -#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ -#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ -#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ -#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ -#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ -#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ -#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ -#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ -#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ -#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ -#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ -#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ -/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ -#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ -#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ -#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ -#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ -#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ -#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ -#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ -#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ -#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ -#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ -#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ -/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ -#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ -#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ -#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ -#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ -#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ -#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ -#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ -#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ -#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ -#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ -#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ -/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ -#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ -#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ -/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ -#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ -#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ -/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ -#define SSC_RPR_RXPTR (0xffffffff << 0) /**< \brief (SSC_RPR) Receive Pointer Register */ -/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ -#define SSC_RCR_RXCTR (0xffff << 0) /**< \brief (SSC_RCR) Receive Counter Register */ -/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ -#define SSC_TPR_TXPTR (0xffffffff << 0) /**< \brief (SSC_TPR) Transmit Counter Register */ -/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ -#define SSC_TCR_TXCTR (0xffff << 0) /**< \brief (SSC_TCR) Transmit Counter Register */ -/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ -#define SSC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SSC_RNPR) Receive Next Pointer */ -/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ -#define SSC_RNCR_RXNCTR (0xffff << 0) /**< \brief (SSC_RNCR) Receive Next Counter */ -/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SSC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SSC_TNPR) Transmit Next Pointer */ -/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SSC_TNCR_TXNCTR (0xffff << 0) /**< \brief (SSC_TNCR) Transmit Counter Next */ -/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ -#define SSC_PTCR_RXTEN (0x1 << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ -#define SSC_PTCR_RXTDIS (0x1 << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ -#define SSC_PTCR_TXTEN (0x1 << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ -#define SSC_PTCR_TXTDIS (0x1 << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ -/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ -#define SSC_PTSR_RXTEN (0x1 << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ -#define SSC_PTSR_TXTEN (0x1 << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Supply Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SUPC Supply Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Supc hardware registers */ -typedef struct { - WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ - RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ - RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ - RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ - RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ - RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ -} Supc; -#endif /* __ASSEMBLY__ */ -/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ -#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ -#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ -#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ -#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ -#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ -/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ -#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ -#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ -#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ -#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ -#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ -#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ -#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ -#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ -#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ -#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ -#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ -#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ -#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ -#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ -#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ -#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ -#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ -#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ -#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ -#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ -#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ -#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ -/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ -#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ -#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ -#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ -#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ -#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ -#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ -#define SUPC_MR_ONREG (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ -#define SUPC_MR_ONREG_ONREG_UNUSED (0x0 << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ -#define SUPC_MR_ONREG_ONREG_USED (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ -#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ -#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ -#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ -#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ -/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ -#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ -#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ -/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ -#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ -#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ -#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ -#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ -#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ -#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ -#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ -#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ -#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ -#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ -#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ -#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ -#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ -#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ -#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ -#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ -#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ -#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ -#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ -#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ -#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ -#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ -#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ -#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ -#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ -#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ -#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ -#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ -#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ -#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ -#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ -#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ -#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ -#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ -#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ -#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ -#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ -#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ -#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ -#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ -#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ -#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ -#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ -#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ -#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ -#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ -#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ -#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ -#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ -#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ -#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ -#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ -#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ -#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ -#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ -#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ -#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ -#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ -#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ -#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ -#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Timer Counter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TC Timer Counter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief TcChannel hardware registers */ -typedef struct { - RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ - RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ - RwReg Reserved1[2]; - RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ - RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ - RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ - RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ - RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ - RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ - RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ - RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ - RwReg Reserved2[4]; -} TcChannel; -/** \brief Tc hardware registers */ -typedef struct { - TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ - WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ - RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ - WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ - WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ - RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ - RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ - RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ - RwReg Reserved1[2]; - RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ - RwReg Reserved2[5]; - RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ -} Tc; -#endif /* __ASSEMBLY__ */ -/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ -#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ -#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ -#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ -/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ -#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ -#define TC_CM0_TCCLKS_TIMER_DIV1_CLOCK (0x0 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV1_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV2_CLOCK (0x1 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV2_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV3_CLOCK (0x2 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV3_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV4_CLOCK (0x3 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV4_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV5_CLOCK (0x4 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV5_CLOCK*/ -#define TC_CM0_TCCLKS_XC0 (0x5 << 0) /**< (TC_CMR0) Clock selected: XC0*/ -#define TC_CM0_TCCLKS_XC1 (0x6 << 0) /**< (TC_CMR0) Clock selected: XC1*/ -#define TC_CM0_TCCLKS_XC2 (0x7 << 0) /**< (TC_CMR0) Clock selected: XC2*/ -#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ -#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ -#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ -#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ -#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ -#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ -#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ -#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ -#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ -#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ -#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ -#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ -#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ -#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ -#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ -#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ -#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ - -#define TC_CMR0_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define TC_CMR0_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define TC_CMR0_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define TC_CMR0_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle - -#define TC_CMR0_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define TC_CMR0_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define TC_CMR0_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define TC_CMR0_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ -#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ -/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ -#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ -/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ -#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ -/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ -#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ -/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ -#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ -#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ -#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ -#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ -#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ -#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ -#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ -#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ -#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ -#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ -#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ -/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ -#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ -#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ -#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ -#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ -#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ -#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ -#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ -#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ -/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ -#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ -#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ -#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ -#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ -#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ -#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ -#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ -#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ -/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ -#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ -#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ -#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ -#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ -#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ -#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ -#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ -#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ -/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ -#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ -#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ -#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ -/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ -#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ -#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ -#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ -#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ -#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ -#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ -#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ -#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ -#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ -#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ -#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ -#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ -#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ -#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ -#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ -#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ -#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ -#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ -/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ -#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ -/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ -#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ -/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ -#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ -/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ -#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ -/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ -#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ -#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ -#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ -#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ -#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ -#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ -#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ -#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ -#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ -#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ -#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ -/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ -#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ -#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ -#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ -#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ -#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ -#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ -#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ -#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ -/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ -#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ -#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ -#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ -#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ -#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ -#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ -#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ -#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ -/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ -#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ -#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ -#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ -#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ -#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ -#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ -#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ -#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ -/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ -#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ -#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ -#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ -/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ -#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ -#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ -#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ -#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ -#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ -#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ -#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ -#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ -#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ -#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ -#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ -#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ -#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ -#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ -#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ -#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ -#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ -#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ -/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ -#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ -/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ -#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ -/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ -#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ -/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ -#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ -/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ -#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ -#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ -#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ -#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ -#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ -#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ -#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ -#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ -#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ -#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ -#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ -/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ -#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ -#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ -#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ -#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ -#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ -#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ -#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ -#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ -/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ -#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ -#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ -#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ -#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ -#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ -#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ -#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ -#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ -/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ -#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ -#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ -#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ -#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ -#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ -#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ -#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ -#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ -/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ -#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ -/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ -#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ -#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ -#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ -#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ -#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ -#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ -#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ -#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ -#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ -#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ -#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ -#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ -#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ -#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ -#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ -/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ -#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ -#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ -#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ -/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ -#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ -#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ -#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ -/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ -#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ -#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ -#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ -/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ -#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ -#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ -#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ -#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ -/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ -#define TC_FMR_ENCF0 (0x1 << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ -#define TC_FMR_ENCF1 (0x1 << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ -/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ -#define TC_WPMR_WPEN (0x1 << 0) /**< \brief (TC_WPMR) Write Protect Enable */ -#define TC_WPMR_WPKEY (0xffffff << 8) /**< \brief (TC_WPMR) Write Protect KEY */ -/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ -#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ -#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TWI Two-wire Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Twi hardware registers */ -typedef struct { - WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ - RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ - RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ - RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ - RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ - RwReg Reserved1[3]; - RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ - WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ - WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ - RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ - RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ - WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ - RwReg Reserved2[50]; - RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ - RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ - RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ - RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ - RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ - RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ - RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ - RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ - WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ - RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ -} Twi; -#endif /* __ASSEMBLY__ */ -/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ -#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ -#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ -#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ -#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ -#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ -#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ -#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ -#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ -#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ -#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ -#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ -#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */ -/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ -#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */ -/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ -#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */ -/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ -#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */ -#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */ -#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */ -/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ -#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ -#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ -#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ -#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ -#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ -#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ -#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ -#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ -#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ -#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ -#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ -#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ -#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ -#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ -#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ -/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ -#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ -#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ -#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ -#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ -#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ -#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ -#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ -#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ -#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ -#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ -#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ -#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ -#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ -#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ -#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ -#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ -#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ -#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ -#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ -#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ -#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ -#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ -#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ -#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ -#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ -#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ -#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ -#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ -#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ -#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ -#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ -#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ -#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ -#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ -#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ -#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ -#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ -#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ -#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ -#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ -#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ -#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ -#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ -/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ -#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ -/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ -#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ -/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ -#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ -/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ -#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ -/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ -#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ -/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ -#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ -/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ -#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ -/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ -/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ -/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ -#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ -#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ -#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ -#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ -/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ -#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UART Universal Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Uart hardware registers */ -typedef struct { - WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ - RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ - WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ - WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ - RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ - RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ - RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ - WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ - RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ - RwReg Reserved1[55]; - RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ - RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ - RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ - RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ - RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ - RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ - RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ - RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ - WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ - RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ -} Uart; -#endif /* __ASSEMBLY__ */ -/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ -#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ -#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ -#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ -#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ -#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ -#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ -#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ -/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ -#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ -#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ -/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ -#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ -#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ -#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ -#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ -#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ -#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ -#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ -#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ -#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ -#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ -/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ -#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ -#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ -#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ -#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ -#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ -#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ -#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ -#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ -#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ -#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ -/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ -#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ -#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ -#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ -#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ -#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ -#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ -#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ -#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ -#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ -#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ -/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ -#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ -#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ -#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ -#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ -#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ -#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ -#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ -#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ -#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ -#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ -/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ -#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ -/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ -#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ -/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ -/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ -#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ -/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ -#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ -/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ -#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ -/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ -#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ -/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ -#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ -/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ -#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ -/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ -/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ -/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ -#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ -#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ -#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ -#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ -/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ -#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ -#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB Device Port */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UDP USB Device Port */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Udp hardware registers */ -typedef struct { - RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ - RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ - RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ - RwReg Reserved1[1]; - WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ - WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ - RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ - RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ - WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ - RwReg Reserved2[1]; - RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ - RwReg Reserved3[1]; - RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x30) Endpoint Control and Status Register (ept_num = 0) */ - RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x50) Endpoint FIFO Data Register (ept_num = 0) */ - RwReg Reserved4[1]; - RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ -} Udp; -#endif /* __ASSEMBLY__ */ -/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ -#define UDP_FRM_NUM_FRM_NUM (0x7ff << 0) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ -#define UDP_FRM_NUM_FRM_ERR (0x1 << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ -#define UDP_FRM_NUM_FRM_OK (0x1 << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ -/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ -#define UDP_GLB_STAT_FADDEN (0x1 << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ -#define UDP_GLB_STAT_CONFG (0x1 << 1) /**< \brief (UDP_GLB_STAT) Configured */ -#define UDP_GLB_STAT_ESR (0x1 << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ -#define UDP_GLB_STAT_RSMINPR (0x1 << 3) /**< \brief (UDP_GLB_STAT) */ -#define UDP_GLB_STAT_RMWUPE (0x1 << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ -/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ -#define UDP_FADDR_FADD (0x7f << 0) /**< \brief (UDP_FADDR) Function Address Value */ -#define UDP_FADDR_FEN (0x1 << 8) /**< \brief (UDP_FADDR) Function Enable */ -/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ -#define UDP_IER_EP0INT (0x1 << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ -#define UDP_IER_EP1INT (0x1 << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ -#define UDP_IER_EP2INT (0x1 << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ -#define UDP_IER_EP3INT (0x1 << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ -#define UDP_IER_EP4INT (0x1 << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ -#define UDP_IER_EP5INT (0x1 << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ -#define UDP_IER_EP6INT (0x1 << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ -#define UDP_IER_EP7INT (0x1 << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ -#define UDP_IER_RXSUSP (0x1 << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ -#define UDP_IER_RXRSM (0x1 << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ -#define UDP_IER_EXTRSM (0x1 << 10) /**< \brief (UDP_IER) */ -#define UDP_IER_SOFINT (0x1 << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ -#define UDP_IER_WAKEUP (0x1 << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ -/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ -#define UDP_IDR_EP0INT (0x1 << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ -#define UDP_IDR_EP1INT (0x1 << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ -#define UDP_IDR_EP2INT (0x1 << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ -#define UDP_IDR_EP3INT (0x1 << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ -#define UDP_IDR_EP4INT (0x1 << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ -#define UDP_IDR_EP5INT (0x1 << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ -#define UDP_IDR_EP6INT (0x1 << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ -#define UDP_IDR_EP7INT (0x1 << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ -#define UDP_IDR_RXSUSP (0x1 << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ -#define UDP_IDR_RXRSM (0x1 << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ -#define UDP_IDR_EXTRSM (0x1 << 10) /**< \brief (UDP_IDR) */ -#define UDP_IDR_SOFINT (0x1 << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ -#define UDP_IDR_WAKEUP (0x1 << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ -/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ -#define UDP_IMR_EP0INT (0x1 << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ -#define UDP_IMR_EP1INT (0x1 << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ -#define UDP_IMR_EP2INT (0x1 << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ -#define UDP_IMR_EP3INT (0x1 << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ -#define UDP_IMR_EP4INT (0x1 << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ -#define UDP_IMR_EP5INT (0x1 << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ -#define UDP_IMR_EP6INT (0x1 << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ -#define UDP_IMR_EP7INT (0x1 << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ -#define UDP_IMR_RXSUSP (0x1 << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ -#define UDP_IMR_RXRSM (0x1 << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ -#define UDP_IMR_EXTRSM (0x1 << 10) /**< \brief (UDP_IMR) */ -#define UDP_IMR_SOFINT (0x1 << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ -#define UDP_IMR_BIT12 (0x1 << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ -#define UDP_IMR_WAKEUP (0x1 << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ -/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ -#define UDP_ISR_EP0INT (0x1 << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ -#define UDP_ISR_EP1INT (0x1 << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ -#define UDP_ISR_EP2INT (0x1 << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ -#define UDP_ISR_EP3INT (0x1 << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ -#define UDP_ISR_EP4INT (0x1 << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ -#define UDP_ISR_EP5INT (0x1 << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ -#define UDP_ISR_EP6INT (0x1 << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ -#define UDP_ISR_EP7INT (0x1 << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ -#define UDP_ISR_RXSUSP (0x1 << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ -#define UDP_ISR_RXRSM (0x1 << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -#define UDP_ISR_EXTRSM (0x1 << 10) /**< \brief (UDP_ISR) */ -#define UDP_ISR_SOFINT (0x1 << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ -#define UDP_ISR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ -#define UDP_ISR_WAKEUP (0x1 << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ -#define UDP_ICR_RXSUSP (0x1 << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ -#define UDP_ICR_RXRSM (0x1 << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ -#define UDP_ICR_EXTRSM (0x1 << 10) /**< \brief (UDP_ICR) */ -#define UDP_ICR_SOFINT (0x1 << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ -#define UDP_ICR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ -#define UDP_ICR_WAKEUP (0x1 << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ -/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ -#define UDP_RST_EP_EP0 (0x1 << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ -#define UDP_RST_EP_EP1 (0x1 << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ -#define UDP_RST_EP_EP2 (0x1 << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ -#define UDP_RST_EP_EP3 (0x1 << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ -#define UDP_RST_EP_EP4 (0x1 << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ -#define UDP_RST_EP_EP5 (0x1 << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ -#define UDP_RST_EP_EP6 (0x1 << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ -#define UDP_RST_EP_EP7 (0x1 << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ -/* -------- UDP_CSR[8] : (UDP Offset: 0x2C) Endpoint Control and Status Register (ept_num = 0) -------- */ -#define UDP_CSR_TXCOMP (0x1 << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ -#define UDP_CSR_RX_DATA_BK0 (0x1 << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ -#define UDP_CSR_RXSETUP (0x1 << 2) /**< \brief (UDP_CSR[8]) Received Setup */ -#define UDP_CSR_STALLSENTISOERROR (0x1 << 3) /**< \brief (UDP_CSR[8]) */ -#define UDP_CSR_TXPKTRDY (0x1 << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ -#define UDP_CSR_FORCESTALL (0x1 << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ -#define UDP_CSR_RX_DATA_BK1 (0x1 << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ -#define UDP_CSR_DIR (0x1 << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ -#define UDP_CSR_EPTYPE (0x7 << 8) /**< \brief (UDP_CSR[8]) Endpoint Type */ -#define UDP_CSR_EPTYPE_CTRL (0x0 << 8) /**< \brief (UDP_CSR[8]) Control */ -#define UDP_CSR_EPTYPE_ISO_OUT (0x1 << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ -#define UDP_CSR_EPTYPE_BULK_OUT (0x2 << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ -#define UDP_CSR_EPTYPE_INT_OUT (0x3 << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ -#define UDP_CSR_EPTYPE_ISO_IN (0x5 << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ -#define UDP_CSR_EPTYPE_BULK_IN (0x6 << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ -#define UDP_CSR_EPTYPE_INT_IN (0x7 << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ -#define UDP_CSR_DTGLE (0x1 << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ -#define UDP_CSR_EPEDS (0x1 << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ -#define UDP_CSR_RXBYTECNT (0x7ff << 16) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ -/* -------- UDP_FDR[8] : (UDP Offset: 0x4C) Endpoint FIFO Data Register (ept_num = 0) -------- */ -#define UDP_FDR_FIFO_DATA (0xff << 0) /**< \brief (UDP_FDR[8]) FIFO Data Value */ -/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ -#define UDP_TXVC_TXVDIS (0x1 << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ -#define UDP_TXVC_PUON (0x1 << 9) /**< \brief (UDP_TXVC) Pullup On */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Usart hardware registers */ -typedef struct { - WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ - RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ - WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ - WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ - RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ - RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ - RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ - WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ - RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ - RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ - RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ - RwReg Reserved1[5]; - RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ - RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ - RwReg Reserved2[1]; - RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ - RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ - RwReg Reserved3[36]; - RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ - RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[4]; - RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ - RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ - RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ - RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ - RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ - RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ - RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ - RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ - RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ - WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ - RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ -} Usart; -#endif /* __ASSEMBLY__ */ -/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ -#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ -#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ -#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ -#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ -#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ -#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ -#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ -#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ -#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ -#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ -#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ -#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ -#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ -#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ -#define US_CR_DTREN (0x1 << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ -#define US_CR_DTRDIS (0x1 << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ -#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ -#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ -/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ -#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ -#define US_MR_USART_MODE_NORMAL (0x0) /**< (USART) Normal*/ -#define US_MR_USART_MODE_RS485 (0x1) /**< (USART) RS485*/ -#define US_MR_USART_MODE_HWHSH (0x2) /**< (USART) Hardware Handshaking*/ -#define US_MR_USART_MODE_ISO7816_0 (0x4) /**< (USART) ISO7816 protocol: T = 0*/ -#define US_MR_USART_MODE_ISO7816_1 (0x6) /**< (USART) ISO7816 protocol: T = 1*/ -#define US_MR_USART_MODE_IRDA (0x8) /**< (USART) IrDA*/ -#define US_MR_USART_MODE_SPIM (0xE) /**< (USART) SPI Master*/ -#define US_MR_USART_MODE_SPIS (0xF) /**< (USART) SPI Slave*/ -#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ -#define US_MR_USCLKS_CLOCK (0x0 << 4) /**< (USART) MCK*/ -#define US_MR_USCLKS_FDIV1 (0x1 << 4) /**< (USART) MCK/DIV(DIV=8)*/ -#define US_MR_USCLKS_SLOW (0x2 << 4) /**< (USART) Reserved*/ -#define US_MR_USCLKS_EXT (0x3 << 4) /**< (USART) SCK*/ -#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ -#define US_MR_CHRL_5_BITS (0x0 << 6) /**< (USART) Character Length: 5 bits*/ -#define US_MR_CHRL_6_BITS (0x1 << 6) /**< (USART) Character Length: 6 bits*/ -#define US_MR_CHRL_7_BITS (0x2 << 6) /**< (USART) Character Length: 7 bits*/ -#define US_MR_CHRL_8_BITS (0x3 << 6) /**< (USART) Character Length: 8 bits*/ -#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ -#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ -#define US_MR_PAR_EVEN (0x0 << 9) /**< (USART) Even Parity*/ -#define US_MR_PAR_ODD (0x1 << 9) /**< (USART) Odd Parity*/ -#define US_MR_PAR_SPACE (0x2 << 9) /**< (USART) Parity forced to 0 (Space)*/ -#define US_MR_PAR_MARK (0x3 << 9) /**< (USART) Parity forced to 1 (Mark)*/ -#define US_MR_PAR_NONE (0x4 << 9) /**< (USART) No Parity*/ -#define US_MR_PAR_MULTI_DROP (0x6 << 9) /**< (USART) Multi-drop mode*/ -#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ -#define US_MR_NBSTOP_1_BIT (0x0 << 12) /**< (USART) 1 stop bit*/ -#define US_MR_NBSTOP_15_BIT (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits*/ -#define US_MR_NBSTOP_2_BIT (0x2 << 12) /**< (USART) 2 stop bits*/ -#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ -#define US_MR_CHMODE_NORMAL (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART.*/ -#define US_MR_CHMODE_AUTO (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/ -#define US_MR_CHMODE_LOCAL (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/ -#define US_MR_CHMODE_REMOTE (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin.*/ -#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ -#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ -#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ -#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ -#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ -#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ -#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ -#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ -#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ -#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ -#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ -#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ -#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ -/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ -#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ -#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ -#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ -#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ -#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ -#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ -#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ -#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ -#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ -#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ -#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ -#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ -#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ -#define US_IER_RIIC (0x1 << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ -#define US_IER_DSRIC (0x1 << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ -#define US_IER_DCDIC (0x1 << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ -#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ -#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ -/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ -#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ -#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ -#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ -#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ -#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ -#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ -#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ -#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ -#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ -#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ -#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ -#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ -#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ -#define US_IDR_RIIC (0x1 << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ -#define US_IDR_DSRIC (0x1 << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ -#define US_IDR_DCDIC (0x1 << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ -#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ -#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ -/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ -#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ -#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ -#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ -#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ -#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ -#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ -#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ -#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ -#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ -#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ -#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ -#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ -#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ -#define US_IMR_RIIC (0x1 << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ -#define US_IMR_DSRIC (0x1 << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ -#define US_IMR_DCDIC (0x1 << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ -#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ -#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ -/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ -#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ -#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ -#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ -#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ -#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ -#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ -#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ -#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ -#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ -#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ -#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ -#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ -#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ -#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ -#define US_CSR_RIIC (0x1 << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ -#define US_CSR_DSRIC (0x1 << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ -#define US_CSR_DCDIC (0x1 << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ -#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ -#define US_CSR_RI (0x1 << 20) /**< \brief (US_CSR) Image of RI Input */ -#define US_CSR_DSR (0x1 << 21) /**< \brief (US_CSR) Image of DSR Input */ -#define US_CSR_DCD (0x1 << 22) /**< \brief (US_CSR) Image of DCD Input */ -#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ -#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ -/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ -#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ -#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ -/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ -#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ -#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ -/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ -#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ -/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ -#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ -/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ -#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ -/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ -#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ -/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ -#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ -/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ -#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ -/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ -#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ -#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ -#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ -#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ -#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ -#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ -#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ -#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ -/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ -#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ -#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ -/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ -#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ -#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ -/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ -#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ -#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ -/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ -#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ -/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ -#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ -/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ -#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ -/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ -#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ -/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ -#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ -/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ -#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ -/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ -/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ -/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ -#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ -#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ -#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ -#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ -/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ -#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_WDT Watchdog Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Wdt hardware registers */ -typedef struct { - WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ - RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ - RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ -} Wdt; -#endif /* __ASSEMBLY__ */ -/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ -#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ -#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ -/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ -#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ -#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ -#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ -#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ -#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ -/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ -#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ -#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ - -/*@}*/ - -/*@}*/ - -/* ***************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_reg Registers Access Definitions */ -/*@{*/ - -/* ========== Register definition for HSMCI peripheral ========== */ -#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ -#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ -#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ -#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ -#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ -#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ -#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ -#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ -#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ -#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ -#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ -#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ -#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ -#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ -#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ -#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ -#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ -#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ -#define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ -#define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ -#define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ -#define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ -#define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ -#define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ -#define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ -#define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ -#define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ -#define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ -/* ========== Register definition for SSC peripheral ========== */ -#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ -#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ -#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ -#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ -#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ -#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ -#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ -#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ -#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ -#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ -#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ -#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ -#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ -#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ -#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ -#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ -#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ -#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ -#define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */ -#define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */ -#define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ -#define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ -#define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ -#define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ -#define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ -#define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ -#define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */ -#define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */ -/* ========== Register definition for SPI peripheral ========== */ -#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ -#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ -#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ -#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ -#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ -#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ -#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ -#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ -#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ -#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ -#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ -#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */ -#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */ -#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ -#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ -#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ -#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ -#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ -#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ -#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */ -#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */ -/* ========== Register definition for TC0 peripheral ========== */ -#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ -#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ -#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ -#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ -#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */ -#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ -#define REG_TC0_VER REG_ACCESS(RoReg, 0x400100FCU) /**< \brief (TC0) Version Register */ -/* ========== Register definition for TC1 peripheral ========== */ -#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ -#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ -#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ -#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ -#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ -#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ -#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ -#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ -#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ -#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ -#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ -#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ -#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ -#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ -#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ -#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ -#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ -#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ -#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ -#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ -#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ -#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ -#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ -#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ -#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ -#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ -#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ -#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ -#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ -#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ -#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */ -#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */ -#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ -#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ -#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ -#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ -#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */ -#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ -#define REG_TC1_VER REG_ACCESS(RoReg, 0x400140FCU) /**< \brief (TC1) Version Register */ -/* ========== Register definition for TWI0 peripheral ========== */ -#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */ -#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */ -#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */ -#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */ -#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ -#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */ -#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ -#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ -#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ -#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */ -#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ -#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */ -/* ========== Register definition for TWI1 peripheral ========== */ -#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */ -#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */ -#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ -#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ -#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ -#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */ -#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ -#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ -#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ -#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ -#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ -#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ -/* ========== Register definition for PWM peripheral ========== */ -#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */ -#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */ -#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */ -#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */ -#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ -#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ -#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ -#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ -#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ -#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ -#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ -#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ -#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ -#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ -#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ -#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ -#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ -#define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ -#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ -#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ -#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ -#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ -#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ -#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ -#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ -#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ -#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ -#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ -#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ -#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ -#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ -#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */ -#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */ -#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ -#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ -#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */ -#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */ -#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ -#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ -#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */ -#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */ -#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ -#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ -#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ -#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ -#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ -#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ -#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ -#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ -#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ -#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ -#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ -#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ -#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ -#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ -#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ -#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ -#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ -#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ -#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ -#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ -#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ -#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ -#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ -#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ -#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ -#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ -#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ -#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ -#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ -#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ -#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ -#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ -#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ -#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ -#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ -#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ -#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ -#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ -#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ -#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ -#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ -#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ -#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ -#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ -#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ -#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ -#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ -#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ -#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ -#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ -#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ -#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ -#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ -#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ -#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ -#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ -#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ -#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ -#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ -#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ -#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ -#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ -#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ -#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ -/* ========== Register definition for USART0 peripheral ========== */ -#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */ -#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */ -#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ -#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ -#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ -#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */ -#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ -#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ -#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ -#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ -#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ -#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ -#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */ -#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ -#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ -#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ -#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ -#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */ -#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */ -/* ========== Register definition for USART1 peripheral ========== */ -#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */ -#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */ -#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ -#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ -#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ -#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */ -#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ -#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ -#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ -#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ -#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ -#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ -#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */ -#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ -#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ -#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ -#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ -#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */ -#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */ -/* ========== Register definition for UDP peripheral ========== */ -#define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */ -#define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */ -#define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */ -#define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ -#define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ -#define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ -#define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ -#define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ -#define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ -#define REG_UDP_CSR REG_ACCESS(RwReg, 0x4003402CU) /**< \brief (UDP) Endpoint Control and Status Register (ept_num = 0) */ -#define REG_UDP_FDR REG_ACCESS(RwReg, 0x4003404CU) /**< \brief (UDP) Endpoint FIFO Data Register (ept_num = 0) */ -#define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */ -/* ========== Register definition for ADC peripheral ========== */ -#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */ -#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */ -#define REG_ADC_SEQ1R REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence 1Register */ -#define REG_ADC_SEQ2R REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence 2 Register */ -#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */ -#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */ -#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */ -#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */ -#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ -#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ -#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ -#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */ -#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */ -#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */ -#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */ -#define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */ -#define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */ -#define REG_ADC_CDR0 REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register 0 */ -#define REG_ADC_CDR1 REG_ACCESS(RoReg, 0x40038054U) /**< \brief (ADC) Channel Data Register 1 */ -#define REG_ADC_CDR2 REG_ACCESS(RoReg, 0x40038058U) /**< \brief (ADC) Channel Data Register 2 */ -#define REG_ADC_CDR3 REG_ACCESS(RoReg, 0x4003805CU) /**< \brief (ADC) Channel Data Register 3 */ -#define REG_ADC_CDR4 REG_ACCESS(RoReg, 0x40038060U) /**< \brief (ADC) Channel Data Register 4 */ -#define REG_ADC_CDR5 REG_ACCESS(RoReg, 0x40038064U) /**< \brief (ADC) Channel Data Register 5 */ -#define REG_ADC_CDR6 REG_ACCESS(RoReg, 0x40038068U) /**< \brief (ADC) Channel Data Register 6 */ -#define REG_ADC_CDR15 REG_ACCESS(RoReg, 0x4003806CU) /**< \brief (ADC) Channel Data Register 15 */ -#define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */ -#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ -#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ -#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */ -#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */ -#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */ -#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */ -#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ -#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ -#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */ -#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */ -#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */ -#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */ -/* ========== Register definition for DACC peripheral ========== */ -#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */ -#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */ -#define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */ -#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */ -#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */ -#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */ -#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ -#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ -#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ -#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ -#define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */ -#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ -#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ -#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */ -#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */ -#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ -#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ -#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */ -#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */ -#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ -#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ -#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */ -#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */ -/* ========== Register definition for ACC peripheral ========== */ -#define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */ -#define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */ -#define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ -#define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ -#define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ -#define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */ -#define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */ -#define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ -#define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ -/* ========== Register definition for CRCCU peripheral ========== */ -#define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ -#define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ -#define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ -#define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ -#define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ -#define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ -#define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ -#define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ -#define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ -#define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ -#define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ -#define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ -#define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ -#define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ -#define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ -/* ========== Register definition for SMC peripheral ========== */ -#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ -#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ -#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ -#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ -#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ -#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ -#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ -#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ -#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ -#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ -#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ -#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ -#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ -#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ -#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ -#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ -#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ -#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ -#define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ -#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ -/* ========== Register definition for MATRIX peripheral ========== */ -#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ -#define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System IO Configuration register */ -#define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ -#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ -#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ -/* ========== Register definition for PMC peripheral ========== */ -#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ -#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ -#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ -#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */ -#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */ -#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ -#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ -#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ -#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ -#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ -#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ -#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ -/* ========== Register definition for UART0 peripheral ========== */ -#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */ -#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */ -#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ -#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ -#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ -#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */ -#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */ -#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ -#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ -#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ -#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */ -#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ -#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ -#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ -#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ -#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ -#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ -#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */ -#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */ -/* ========== Register definition for CHIPID peripheral ========== */ -#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -/* ========== Register definition for UART1 peripheral ========== */ -#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */ -#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */ -#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ -#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ -#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ -#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */ -#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */ -#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ -#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ -#define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ -#define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */ -#define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ -#define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ -#define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ -#define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ -#define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ -#define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ -#define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */ -#define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */ -/* ========== Register definition for EFC peripheral ========== */ -#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ -#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ -#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ -#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ -/* ========== Register definition for PIOA peripheral ========== */ -#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ -#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ -#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ -#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ -#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ -#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ -#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ -#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ -#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ -#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */ -#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ -#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ -#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ -#define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ -#define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ -#define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ -#define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ -#define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ -#define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOB peripheral ========== */ -#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ -#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ -#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ -#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ -#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ -#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ -#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ -#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ -#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ -#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */ -#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ -#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ -#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ -#define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ -#define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ -#define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ -#define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ -#define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ -#define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOC peripheral ========== */ -#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ -#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ -#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */ -#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */ -#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */ -#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */ -#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ -#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ -#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ -#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ -#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ -#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ -#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ -#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ -#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ -#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ -#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ -#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ -#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ -#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ -#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ -#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ -#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ -#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ -#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ -#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ -#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ -#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ -#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ -#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ -#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ -#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ -#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ -#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ -#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ -#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ -#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ -#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */ -#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ -#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ -#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ -#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ -#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */ -#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ -#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ -#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ -#define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ -#define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ -#define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ -#define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ -#define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ -#define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ -/* ========== Register definition for RSTC peripheral ========== */ -#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */ -/* ========== Register definition for SUPC peripheral ========== */ -#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ -#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ -#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ -/* ========== Register definition for RTT peripheral ========== */ -#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */ -/* ========== Register definition for WDT peripheral ========== */ -#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */ -/* ========== Register definition for RTC peripheral ========== */ -#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */ -/* ========== Register definition for GPBR peripheral ========== */ -#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */ -#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */ -#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */ -#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ -/*@}*/ - -/* ***************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ -#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ -#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ -#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ -#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ -#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ -#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ -#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ -#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ -#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ -/*@}*/ - -/* ***************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_base Peripheral Base Address Definitions */ -/*@{*/ - -#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ -#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */ -#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */ -#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */ -#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */ -#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */ -#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */ -#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ -#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ -#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */ - -// indices for three pio structures -#define iPIOA 0 -#define iPIOB 1 -#define iPIOC 2 -/*@}*/ - -/* ***************************************************************************** */ -/* PIO DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_pio Peripheral Pio Definitions */ -/*@{*/ - -#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA28C_MCCDA (1 << 28) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA29C_MCCK (1 << 29) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA30C_MCDA0 (1 << 30) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA31C_MCDA1 (1 << 31) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA26C_MCDA2 (1 << 26) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA27C_MCDA3 (1 << 27) /**< \brief Hsmci signal: MCDA3 */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PA18A_RD (1 << 18) /**< \brief Ssc signal: RD */ -#define PIO_PA20A_RF (1 << 20) /**< \brief Ssc signal: RF */ -#define PIO_PA19A_RK (1 << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA17A_TD (1 << 17) /**< \brief Ssc signal: TD */ -#define PIO_PA15A_TF (1 << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA16A_TK (1 << 16) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA12A_MISO (1 << 12) /**< \brief Spi signal: MISO */ -#define PIO_PA13A_MOSI (1 << 13) /**< \brief Spi signal: MOSI */ -#define PIO_PA11A_NPCS0 (1 << 11) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA31A_NPCS1 (1 << 31) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA9B_NPCS1 (1 << 9) /**< \brief Spi signal: NPCS1 */ -#define PIO_PB14A_NPCS1 (1 << 14) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC4B_NPCS1 (1 << 4) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA10B_NPCS2 (1 << 10) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA30B_NPCS2 (1 << 30) /**< \brief Spi signal: NPCS2 */ -#define PIO_PB2B_NPCS2 (1 << 2) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA22B_NPCS3 (1 << 22) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA3B_NPCS3 (1 << 3) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA14A_SPCK (1 << 14) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA4B_TCLK0 (1 << 4) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA28B_TCLK1 (1 << 28) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA29B_TCLK2 (1 << 29) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1 << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA15B_TIOA1 (1 << 15) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA26B_TIOA2 (1 << 26) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1 << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1 << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA27B_TIOB2 (1 << 27) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PC25B_TCLK3 (1 << 25) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PC28B_TCLK4 (1 << 28) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PC31B_TCLK5 (1 << 31) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PC23B_TIOA3 (1 << 23) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PC26B_TIOA4 (1 << 26) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PC29B_TIOA5 (1 << 29) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PC24B_TIOB3 (1 << 24) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PC27B_TIOB4 (1 << 27) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PC30B_TIOB5 (1 << 30) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA4A_TWCK0 (1 << 4) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA3A_TWD0 (1 << 3) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB5A_TWCK1 (1 << 5) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB4A_TWD1 (1 << 4) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA9C_PWMFI0 (1 << 9) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA11B_PWMH0 (1 << 11) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA23B_PWMH0 (1 << 23) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC18B_PWMH0 (1 << 18) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA12B_PWMH1 (1 << 12) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA24B_PWMH1 (1 << 24) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC19B_PWMH1 (1 << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1 << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA25B_PWMH2 (1 << 25) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB4B_PWMH2 (1 << 4) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC20B_PWMH2 (1 << 20) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA17C_PWMH3 (1 << 17) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA7B_PWMH3 (1 << 7) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC21B_PWMH3 (1 << 21) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA19B_PWML0 (1 << 19) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB5B_PWML0 (1 << 5) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC0B_PWML0 (1 << 0) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC13B_PWML0 (1 << 13) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA20B_PWML1 (1 << 20) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB12A_PWML1 (1 << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC1B_PWML1 (1 << 1) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC15B_PWML1 (1 << 15) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA16C_PWML2 (1 << 16) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA30A_PWML2 (1 << 30) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB13A_PWML2 (1 << 13) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC2B_PWML2 (1 << 2) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA15C_PWML3 (1 << 15) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC22B_PWML3 (1 << 22) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC3B_PWML3 (1 << 3) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PA7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA5A_RXD0 (1 << 5) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA2B_SCK0 (1 << 2) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA6A_TXD0 (1 << 6) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA25A_CTS1 (1 << 25) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA26A_DCD1 (1 << 26) /**< \brief Usart1 signal: DCD1 */ -#define PIO_PA28A_DSR1 (1 << 28) /**< \brief Usart1 signal: DSR1 */ -#define PIO_PA27A_DTR1 (1 << 27) /**< \brief Usart1 signal: DTR1 */ -#define PIO_PA29A_RI1 (1 << 29) /**< \brief Usart1 signal: RI1 */ -#define PIO_PA24A_RTS1 (1 << 24) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA23A_SCK1 (1 << 23) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA22A_TXD1 (1 << 22) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1 << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1 << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PC13X1_AD10 (1 << 13) /**< \brief Adc signal: AD10 */ -#define PIO_PC15X1_AD11 (1 << 15) /**< \brief Adc signal: AD11 */ -#define PIO_PC12X1_AD12 (1 << 12) /**< \brief Adc signal: AD12 */ -#define PIO_PC29X1_AD13 (1 << 29) /**< \brief Adc signal: AD13 */ -#define PIO_PC30X1_AD14 (1 << 30) /**< \brief Adc signal: AD14 */ -#define PIO_PA19X1_AD2 (1 << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1 << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1 << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1 << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1 << 2) /**< \brief Adc signal: AD6 */ -#define PIO_PB3X1_AD7 (1 << 3) /**< \brief Adc signal: AD7 */ -#define PIO_PA21X1_AD8 (1 << 21) /**< \brief Adc signal: AD8 */ -#define PIO_PA22X1_AD9 (1 << 22) /**< \brief Adc signal: AD9 */ -#define PIO_PA8B_ADTRG (1 << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB13X1_DAC0 (1 << 13) /**< \brief Dacc signal: DAC0 */ -#define PIO_PB14X1_DAC1 (1 << 14) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA2C_DATRG (1 << 2) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1 << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB13B_PCK0 (1 << 13) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1 << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1 << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1 << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1 << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1 << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for UART0 peripheral ========== */ -#define PIO_PA9A_URXD0 (1 << 9) /**< \brief Uart0 signal: URXD0 */ -#define PIO_PA10A_UTXD0 (1 << 10) /**< \brief Uart0 signal: UTXD0 */ -/* ========== Pio definition for UART1 peripheral ========== */ -#define PIO_PB2A_URXD1 (1 << 2) /**< \brief Uart1 signal: URXD1 */ -#define PIO_PB3A_UTXD1 (1 << 3) /**< \brief Uart1 signal: UTXD1 */ -/* ========== Pio definition for PIOA peripheral ========== */ -#define PIO_PA24X1_PIODC0 (1 << 24) /**< \brief Pioa signal: PIODC0 */ -#define PIO_PA25X1_PIODC1 (1 << 25) /**< \brief Pioa signal: PIODC1 */ -#define PIO_PA26X1_PIODC2 (1 << 26) /**< \brief Pioa signal: PIODC2 */ -#define PIO_PA27X1_PIODC3 (1 << 27) /**< \brief Pioa signal: PIODC3 */ -#define PIO_PA28X1_PIODC4 (1 << 28) /**< \brief Pioa signal: PIODC4 */ -#define PIO_PA29X1_PIODC5 (1 << 29) /**< \brief Pioa signal: PIODC5 */ -#define PIO_PA30X1_PIODC6 (1 << 30) /**< \brief Pioa signal: PIODC6 */ -#define PIO_PA31X1_PIODC7 (1 << 31) /**< \brief Pioa signal: PIODC7 */ -#define PIO_PA23X1_PIODCCLK (1 << 23) /**< \brief Pioa signal: PIODCCLK */ -#define PIO_PA15X1_PIODCEN1 (1 << 15) /**< \brief Pioa signal: PIODCEN1 */ -#define PIO_PA16X1_PIODCEN2 (1 << 16) /**< \brief Pioa signal: PIODCEN2 */ -/*@}*/ - -/* ***************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ - -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_IFLASH (0x00400000) /**< Internal Flash base address */ -#define AT91C_IROM (0x00800000) /**< Internal ROM base address */ -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_EBI_CS0 (0x60000000) /**< EBI Chip Select 0 base address */ -#define AT91C_EBI_CS1 (0x61000000) /**< EBI Chip Select 1 base address */ -#define AT91C_EBI_CS2 (0x62000000) /**< EBI Chip Select 2 base address */ -#define AT91C_EBI_CS3 (0x63000000) /**< EBI Chip Select 3 base address */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - + +/** \addtogroup AT91SAM3S_definitions AT91SAM3S definitions + This file defines all structures and symbols for AT91SAM3S: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __ASSEMBLY__ +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *) value) +#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ***************************************************************************** */ +/* CMSIS DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_cmsis CMSIS Definitions */ + +/*@{*/ + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __MPU_PRESENT 0 /**< AT91SAM3S does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 4 /**< AT91SAM3S uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** AT91SAM3S specific Interrupt Numbers *****************************************/ + + SUPC_IRQn = 0, /**< 0 AT91SAM3S Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 AT91SAM3S Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 AT91SAM3S Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 AT91SAM3S Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 AT91SAM3S Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 AT91SAM3S Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 AT91SAM3S Enhanced Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 AT91SAM3S UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 AT91SAM3S UART 1 (UART1) */ + SMC_IRQn = 10, /**< 10 AT91SAM3S Static Memory Controller (SMC) */ + PIOA_IRQn = 11, /**< 11 AT91SAM3S Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 AT91SAM3S Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 13, /**< 13 AT91SAM3S Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 14, /**< 14 AT91SAM3S USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 AT91SAM3S USART 1 (USART1) */ + HSMCI_IRQn = 18, /**< 18 AT91SAM3S Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 AT91SAM3S Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 AT91SAM3S Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 AT91SAM3S Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 AT91SAM3S Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 AT91SAM3S Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 AT91SAM3S Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 AT91SAM3S Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 AT91SAM3S Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 AT91SAM3S Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 AT91SAM3S Timer/Counter 5 (TC5) */ + ADC_IRQn = 29, /**< 29 AT91SAM3S Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 AT91SAM3S Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 AT91SAM3S Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 AT91SAM3S CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 AT91SAM3S Analog Comparator (ACC) */ + UDP_IRQn = 34 /**< 34 AT91SAM3S USB Device Port (UDP) */ +} IRQn_Type; +/*@}*/ + +/* ***************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_api Peripheral Software API */ +/*@{*/ +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_ACC Analog Comparator Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Acc hardware registers */ +typedef struct { + WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + RwReg Reserved1[7]; + WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + RwReg Reserved2[24]; + RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + RwReg Reserved3[19]; + RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ + RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ +} Acc; +#endif /* __ASSEMBLY__ */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1 << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELPLUS (0x7 << 0) /**< \brief (ACC_MR) SELection for PLUS comparator input */ +#define ACC_MR_SELMINUS (0x7 << 4) /**< \brief (ACC_MR) SELection for MINUS comparator input */ +#define ACC_MR_ACEN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ +#define ACC_MR_ACEN_EN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ +#define ACC_MR_ACEN_DIS (0x0 << 8) /**< \brief (ACC_MR) Analog Comparator Disable */ +#define ACC_MR_EDGETYP (0x3 << 9) /**< \brief (ACC_MR) EDGE TYPe */ +#define ACC_MR_EDGETYP_RISING (0x0 << 9) /**< \brief (ACC_MR) EDGE TYPe ,RISING edge*/ +#define ACC_MR_EDGETYP_FALLING (0x1 << 9) /**< \brief (ACC_MR) EDGE TYPe,falling edge */ +#define ACC_MR_EDGETYP_ANY (0x2 << 9) /**< \brief (ACC_MR) EDGE TYPe,any edge */ +#define ACC_MR_INV (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ +#define ACC_MR_INV_EN (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ +#define ACC_MR_INV_DIS (0x0 << 12) /**< \brief (ACC_MR) DIRECTLY */ +#define ACC_MR_SELFS (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ +#define ACC_MR_SELFS_CF (0x0 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ +#define ACC_MR_SELFS_OUTPUT (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ +#define ACC_MR_FE (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_EN (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0 << 14) /**< \brief (ACC_MR) Fault Enable */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1 << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1 << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1 << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1 << 0) /**< \brief (ACC_ISR) Comparison Edge */ +#define ACC_ISR_SCO (0x1 << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1 << 31) /**< \brief (ACC_ISR) */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1 << 0) /**< \brief (ACC_ACR) Current SELection */ +#define ACC_ACR_HYST (0x3 << 1) /**< \brief (ACC_ACR) HYSTeresis selection */ +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1 << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ +#define ACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ACC_WPMR) Write Protect KEY */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ +#define ACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_ADC Analog-to-digital Converter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Adc hardware registers */ +typedef struct { + WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ + RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ + RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence 1Register */ + RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence 2 Register */ + WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ + WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ + RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ + RwReg Reserved1[1]; + RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ + WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ + WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ + RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ + RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ + RwReg Reserved2[2]; + RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ + RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ + RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ + RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ + RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ + RoReg ADC_CDR0; /**< \brief (Adc Offset: 0x50) Channel Data Register 0 */ + RoReg ADC_CDR1; /**< \brief (Adc Offset: 0x54) Channel Data Register 1 */ + RoReg ADC_CDR2; /**< \brief (Adc Offset: 0x58) Channel Data Register 2 */ + RoReg ADC_CDR3; /**< \brief (Adc Offset: 0x5C) Channel Data Register 3 */ + RoReg ADC_CDR4; /**< \brief (Adc Offset: 0x60) Channel Data Register 4 */ + RoReg ADC_CDR5; /**< \brief (Adc Offset: 0x64) Channel Data Register 5 */ + RoReg ADC_CDR6; /**< \brief (Adc Offset: 0x68) Channel Data Register 6 */ + RoReg ADC_CDR7; /**< \brief (Adc Offset: 0x6C) Channel Data Register 7 */ + RoReg ADC_CDR8; /**< \brief (Adc Offset: 0x70) Channel Data Register 8 */ + RoReg ADC_CDR9; /**< \brief (Adc Offset: 0x74) Channel Data Register 9 */ + RoReg ADC_CDR10; /**< \brief (Adc Offset: 0x78) Channel Data Register 10 */ + RoReg ADC_CDR11; /**< \brief (Adc Offset: 0x7C) Channel Data Register 11 */ + RoReg ADC_CDR12; /**< \brief (Adc Offset: 0x80) Channel Data Register 12 */ + RoReg ADC_CDR13; /**< \brief (Adc Offset: 0x84) Channel Data Register 13 */ + RoReg ADC_CDR14; /**< \brief (Adc Offset: 0x88) Channel Data Register 14 */ + RoReg ADC_CDR15; /**< \brief (Adc Offset: 0x8C) Channel Data Register 15 */ + RwReg Reserved3[1]; + RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ + RwReg Reserved4[19]; + RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ + RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ + RwReg Reserved5[5]; + RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ + RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ + RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */ + RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */ + RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ + RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ + RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */ + RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */ + WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ + RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ +} Adc; +#endif /* __ASSEMBLY__ */ +/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ +#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ +#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ +#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ +#define ADC_MR_TRGEN_DIS (0x0 << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.*/ +#define ADC_MR_TRGEN_EN (0x1) /**< (ADC) Hardware trigger selected by TRGSEL field is enabled.*/ +#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ +#define ADC_MR_TRGSEL_EXT (0x0 << 1) /**< \brief (ADC_MR) Selected TRGSEL = External Trigger*/ +#define ADC_MR_TRGSEL_TIOA0 (0x1 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO0*/ +#define ADC_MR_TRGSEL_TIOA1 (0x2 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO1*/ +#define ADC_MR_TRGSEL_TIOA2 (0x3 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO2*/ +#define ADC_MR_TRGSEL_PWM0_TRIG (0x4 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM trigger*/ +#define ADC_MR_TRGSEL_PWM1_TRIG (0x5 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM Trigger*/ +#define ADC_MR_TRGSEL_RESERVED (0x6 << 1) /**< \brief (ADC_MR) Selected TRGSEL = Reserved*/ +#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ +#define ADC_MR_LOWRES_12_BIT (0x0 << 4) /**< \brief (ADC_MR) 12-bit resolution*/ +#define ADC_MR_LOWRES_10_BIT (0x1 << 4) /**< \brief (ADC_MR) 10-bit resolution*/ +#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ +#define ADC_MR_SLEEP_NORMAL (0x0 << 5) /**< \brief (ADC12B) Normal Mode*/ +#define ADC_MR_FWUP (0x1 << 6) /**< \brief (ADC_MR) Fast Wake Up */ +#define ADC_MR_FREERUN (0x1 << 7) /**< \brief (ADC_MR) Free Run Mode */ +#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ +#define ADC_MR_STARTUP (0xf << 16) /**< \brief (ADC_MR) Start Up Time */ +#define ADC_MR_SETTLING (0x3 << 20) /**< \brief (ADC_MR) Analog Settling Time */ +#define ADC_MR_ANACH (0x1 << 23) /**< \brief (ADC_MR) Analog Change */ +#define ADC_MR_TRACKTIM (0xf << 24) /**< \brief (ADC_MR) Tracking Time */ +#define ADC_MR_TRANSFER (0x3 << 28) /**< \brief (ADC_MR) */ +#define ADC_MR_USEQ (0x1 << 31) /**< \brief (ADC_MR) User Sequence Enable */ +/* -------- ADC_SEQ1R : (ADC Offset: 0x08) Channel Sequence 1Register -------- */ +#define ADC_SEQ1R_USCH1 (0x7 << 0) /**< \brief (ADC_SEQ1R) User Sequence Number 1 */ +#define ADC_SEQ1R_USCH2 (0x7 << 4) /**< \brief (ADC_SEQ1R) User Sequence Number 2 */ +#define ADC_SEQ1R_USCH3 (0x7 << 8) /**< \brief (ADC_SEQ1R) User Sequence Number 3 */ +#define ADC_SEQ1R_USCH4 (0x7 << 12) /**< \brief (ADC_SEQ1R) User Sequence Number 4 */ +#define ADC_SEQ1R_USCH5 (0x7 << 16) /**< \brief (ADC_SEQ1R) User Sequence Number 5 */ +#define ADC_SEQ1R_USCH6 (0x7 << 20) /**< \brief (ADC_SEQ1R) User Sequence Number 6 */ +#define ADC_SEQ1R_USCH7 (0x7 << 24) /**< \brief (ADC_SEQ1R) User Sequence Number 7 */ +#define ADC_SEQ1R_USCH8 (0x7 << 28) /**< \brief (ADC_SEQ1R) User Sequence Number 8 */ +/* -------- ADC_SEQ2R : (ADC Offset: 0x0C) Channel Sequence 2 Register -------- */ +#define ADC_SEQ2R_USCH9 (0x7 << 0) /**< \brief (ADC_SEQ2R) User Sequence Number 9 */ +#define ADC_SEQ2R_USCH10 (0x7 << 4) /**< \brief (ADC_SEQ2R) User Sequence Number 10 */ +#define ADC_SEQ2R_USCH11 (0x7 << 8) /**< \brief (ADC_SEQ2R) User Sequence Number 11 */ +#define ADC_SEQ2R_USCH12 (0x7 << 12) /**< \brief (ADC_SEQ2R) User Sequence Number 12 */ +#define ADC_SEQ2R_USCH13 (0x7 << 16) /**< \brief (ADC_SEQ2R) User Sequence Number 13 */ +#define ADC_SEQ2R_USCH14 (0x7 << 20) /**< \brief (ADC_SEQ2R) User Sequence Number 14 */ +#define ADC_SEQ2R_USCH15 (0x7 << 24) /**< \brief (ADC_SEQ2R) User Sequence Number 15 */ +#define ADC_SEQ2R_USCH16 (0x7 << 28) /**< \brief (ADC_SEQ2R) User Sequence Number 16 */ +/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ +#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ +#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ +#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ +#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ +#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ +#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ +#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ +#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ +#define ADC_CHER_CH8 (0x1 << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ +#define ADC_CHER_CH9 (0x1 << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ +#define ADC_CHER_CH10 (0x1 << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ +#define ADC_CHER_CH11 (0x1 << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ +#define ADC_CHER_CH12 (0x1 << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ +#define ADC_CHER_CH13 (0x1 << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ +#define ADC_CHER_CH14 (0x1 << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ +#define ADC_CHER_CH15 (0x1 << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ +#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ +#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ +#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ +#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ +#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ +#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ +#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ +#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ +#define ADC_CHDR_CH8 (0x1 << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ +#define ADC_CHDR_CH9 (0x1 << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ +#define ADC_CHDR_CH10 (0x1 << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ +#define ADC_CHDR_CH11 (0x1 << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ +#define ADC_CHDR_CH12 (0x1 << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ +#define ADC_CHDR_CH13 (0x1 << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ +#define ADC_CHDR_CH14 (0x1 << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ +#define ADC_CHDR_CH15 (0x1 << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ +#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ +#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ +#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ +#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ +#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ +#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ +#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ +#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ +#define ADC_CHSR_CH8 (0x1 << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ +#define ADC_CHSR_CH9 (0x1 << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ +#define ADC_CHSR_CH10 (0x1 << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ +#define ADC_CHSR_CH11 (0x1 << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ +#define ADC_CHSR_CH12 (0x1 << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ +#define ADC_CHSR_CH13 (0x1 << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ +#define ADC_CHSR_CH14 (0x1 << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ +#define ADC_CHSR_CH15 (0x1 << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ +#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ +#define ADC_LCDR_CHNB (0xf << 12) /**< \brief (ADC_LCDR) Channel Number */ +/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ +#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ +#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ +#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ +#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ +#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ +#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ +#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ +#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ +#define ADC_IER_EOC8 (0x1 << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ +#define ADC_IER_EOC9 (0x1 << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ +#define ADC_IER_EOC10 (0x1 << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ +#define ADC_IER_EOC11 (0x1 << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ +#define ADC_IER_EOC12 (0x1 << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ +#define ADC_IER_EOC13 (0x1 << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ +#define ADC_IER_EOC14 (0x1 << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ +#define ADC_IER_EOC15 (0x1 << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ +#define ADC_IER_DRDY (0x1 << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ +#define ADC_IER_GOVRE (0x1 << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ +#define ADC_IER_COMPE (0x1 << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ +#define ADC_IER_ENDRX (0x1 << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ +#define ADC_IER_RXBUFF (0x1 << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ +/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ +#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ +#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ +#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ +#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ +#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ +#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ +#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ +#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ +#define ADC_IDR_EOC8 (0x1 << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ +#define ADC_IDR_EOC9 (0x1 << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ +#define ADC_IDR_EOC10 (0x1 << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ +#define ADC_IDR_EOC11 (0x1 << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ +#define ADC_IDR_EOC12 (0x1 << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ +#define ADC_IDR_EOC13 (0x1 << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ +#define ADC_IDR_EOC14 (0x1 << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ +#define ADC_IDR_EOC15 (0x1 << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ +#define ADC_IDR_DRDY (0x1 << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ +#define ADC_IDR_GOVRE (0x1 << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ +#define ADC_IDR_COMPE (0x1 << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ +#define ADC_IDR_ENDRX (0x1 << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ +#define ADC_IDR_RXBUFF (0x1 << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ +/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ +#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ +#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ +#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ +#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ +#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ +#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ +#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ +#define ADC_IMR_EOC8 (0x1 << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ +#define ADC_IMR_EOC9 (0x1 << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ +#define ADC_IMR_EOC10 (0x1 << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ +#define ADC_IMR_EOC11 (0x1 << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ +#define ADC_IMR_EOC12 (0x1 << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ +#define ADC_IMR_EOC13 (0x1 << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ +#define ADC_IMR_EOC14 (0x1 << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ +#define ADC_IMR_EOC15 (0x1 << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ +#define ADC_IMR_DRDY (0x1 << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ +#define ADC_IMR_GOVRE (0x1 << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ +#define ADC_IMR_COMPE (0x1 << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ +#define ADC_IMR_ENDRX (0x1 << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ +#define ADC_IMR_RXBUFF (0x1 << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ +/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ +#define ADC_ISR_EOC0 (0x1 << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ +#define ADC_ISR_EOC1 (0x1 << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ +#define ADC_ISR_EOC2 (0x1 << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ +#define ADC_ISR_EOC3 (0x1 << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ +#define ADC_ISR_EOC4 (0x1 << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ +#define ADC_ISR_EOC5 (0x1 << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ +#define ADC_ISR_EOC6 (0x1 << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ +#define ADC_ISR_EOC7 (0x1 << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ +#define ADC_ISR_EOC8 (0x1 << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ +#define ADC_ISR_EOC9 (0x1 << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ +#define ADC_ISR_EOC10 (0x1 << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ +#define ADC_ISR_EOC11 (0x1 << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ +#define ADC_ISR_EOC12 (0x1 << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ +#define ADC_ISR_EOC13 (0x1 << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ +#define ADC_ISR_EOC14 (0x1 << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ +#define ADC_ISR_EOC15 (0x1 << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ +#define ADC_ISR_DRDY (0x1 << 24) /**< \brief (ADC_ISR) Data Ready */ +#define ADC_ISR_GOVRE (0x1 << 25) /**< \brief (ADC_ISR) General Overrun Error */ +#define ADC_ISR_COMPE (0x1 << 26) /**< \brief (ADC_ISR) Comparison Error */ +#define ADC_ISR_ENDRX (0x1 << 27) /**< \brief (ADC_ISR) End of RX Buffer */ +#define ADC_ISR_RXBUFF (0x1 << 28) /**< \brief (ADC_ISR) RX Buffer Full */ +/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ +#define ADC_OVER_OVRE0 (0x1 << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ +#define ADC_OVER_OVRE1 (0x1 << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ +#define ADC_OVER_OVRE2 (0x1 << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ +#define ADC_OVER_OVRE3 (0x1 << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ +#define ADC_OVER_OVRE4 (0x1 << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ +#define ADC_OVER_OVRE5 (0x1 << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ +#define ADC_OVER_OVRE6 (0x1 << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ +#define ADC_OVER_OVRE7 (0x1 << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ +#define ADC_OVER_OVRE8 (0x1 << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ +#define ADC_OVER_OVRE9 (0x1 << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ +#define ADC_OVER_OVRE10 (0x1 << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ +#define ADC_OVER_OVRE11 (0x1 << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ +#define ADC_OVER_OVRE12 (0x1 << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ +#define ADC_OVER_OVRE13 (0x1 << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ +#define ADC_OVER_OVRE14 (0x1 << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ +#define ADC_OVER_OVRE15 (0x1 << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ +/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ +#define ADC_EMR_CMPMODE (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode */ +#define ADC_EMR_CMPMODE_LOW (0x0 << 0) /**< \brief (ADC_EMR) Comparison Mode,lower than low threshold */ +#define ADC_EMR_CMPMODE_HIGH (0x1 << 0) /**< \brief (ADC_EMR) Comparison Mode,higher than high threshold */ +#define ADC_EMR_CMPMODE_IN (0x2 << 0) /**< \brief (ADC_EMR) Comparison Mode, in the comparison window */ +#define ADC_EMR_CMPMODE_OUT (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode, out of the comparison window */ +#define ADC_EMR_CMPSEL (0xf << 4) /**< \brief (ADC_EMR) Comparison Selected Channel */ +#define ADC_EMR_CMPALL (0x1 << 9) /**< \brief (ADC_EMR) Compare All Channels */ +#define ADC_EMR_TAG (0x1 << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ +/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ +#define ADC_CWR_LOWTHRES (0xfff << 0) /**< \brief (ADC_CWR) Low Threshold */ +#define ADC_CWR_HIGHTHRES (0xfff << 16) /**< \brief (ADC_CWR) High Threshold */ +/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ +#define ADC_CGR_GAIN0 (0x3 << 0) /**< \brief (ADC_CGR) Gain for channel 0 */ +#define ADC_CGR_GAIN1 (0x3 << 2) /**< \brief (ADC_CGR) Gain for channel 1 */ +#define ADC_CGR_GAIN2 (0x3 << 4) /**< \brief (ADC_CGR) Gain for channel 2 */ +#define ADC_CGR_GAIN3 (0x3 << 6) /**< \brief (ADC_CGR) Gain for channel 3 */ +#define ADC_CGR_GAIN4 (0x3 << 8) /**< \brief (ADC_CGR) Gain for channel 4 */ +#define ADC_CGR_GAIN5 (0x3 << 10) /**< \brief (ADC_CGR) Gain for channel 5 */ +#define ADC_CGR_GAIN6 (0x3 << 12) /**< \brief (ADC_CGR) Gain for channel 6 */ +#define ADC_CGR_GAIN7 (0x3 << 14) /**< \brief (ADC_CGR) Gain for channel 7 */ +#define ADC_CGR_GAIN8 (0x3 << 16) /**< \brief (ADC_CGR) Gain for channel 8 */ +#define ADC_CGR_GAIN9 (0x3 << 18) /**< \brief (ADC_CGR) Gain for channel 9 */ +#define ADC_CGR_GAIN10 (0x3 << 20) /**< \brief (ADC_CGR) Gain for channel 10 */ +#define ADC_CGR_GAIN11 (0x3 << 22) /**< \brief (ADC_CGR) Gain for channel 11 */ +#define ADC_CGR_GAIN12 (0x3 << 24) /**< \brief (ADC_CGR) Gain for channel 12 */ +#define ADC_CGR_GAIN13 (0x3 << 26) /**< \brief (ADC_CGR) Gain for channel 13 */ +#define ADC_CGR_GAIN14 (0x3 << 28) /**< \brief (ADC_CGR) Gain for channel 14 */ +#define ADC_CGR_GAIN15 (0x3 << 30) /**< \brief (ADC_CGR) Gain for channel 15 */ +/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ +#define ADC_COR_OFF0 (0x1 << 0) /**< \brief (ADC_COR) Offset for channel 0 */ +#define ADC_COR_OFF1 (0x1 << 1) /**< \brief (ADC_COR) Offset for channel 1 */ +#define ADC_COR_OFF2 (0x1 << 2) /**< \brief (ADC_COR) Offset for channel 2 */ +#define ADC_COR_OFF3 (0x1 << 3) /**< \brief (ADC_COR) Offset for channel 3 */ +#define ADC_COR_OFF4 (0x1 << 4) /**< \brief (ADC_COR) Offset for channel 4 */ +#define ADC_COR_OFF5 (0x1 << 5) /**< \brief (ADC_COR) Offset for channel 5 */ +#define ADC_COR_OFF6 (0x1 << 6) /**< \brief (ADC_COR) Offset for channel 6 */ +#define ADC_COR_OFF7 (0x1 << 7) /**< \brief (ADC_COR) Offset for channel 7 */ +#define ADC_COR_OFF8 (0x1 << 8) /**< \brief (ADC_COR) Offset for channel 8 */ +#define ADC_COR_OFF9 (0x1 << 9) /**< \brief (ADC_COR) Offset for channel 9 */ +#define ADC_COR_OFF10 (0x1 << 10) /**< \brief (ADC_COR) Offset for channel 10 */ +#define ADC_COR_OFF11 (0x1 << 11) /**< \brief (ADC_COR) Offset for channel 11 */ +#define ADC_COR_OFF12 (0x1 << 12) /**< \brief (ADC_COR) Offset for channel 12 */ +#define ADC_COR_OFF13 (0x1 << 13) /**< \brief (ADC_COR) Offset for channel 13 */ +#define ADC_COR_OFF14 (0x1 << 14) /**< \brief (ADC_COR) Offset for channel 14 */ +#define ADC_COR_OFF15 (0x1 << 15) /**< \brief (ADC_COR) Offset for channel 15 */ +#define ADC_COR_DIFF0 (0x1 << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ +#define ADC_COR_DIFF1 (0x1 << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ +#define ADC_COR_DIFF2 (0x1 << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ +#define ADC_COR_DIFF3 (0x1 << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ +#define ADC_COR_DIFF4 (0x1 << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ +#define ADC_COR_DIFF5 (0x1 << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ +#define ADC_COR_DIFF6 (0x1 << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ +#define ADC_COR_DIFF7 (0x1 << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ +#define ADC_COR_DIFF8 (0x1 << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ +#define ADC_COR_DIFF9 (0x1 << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ +#define ADC_COR_DIFF10 (0x1 << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ +#define ADC_COR_DIFF11 (0x1 << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ +#define ADC_COR_DIFF12 (0x1 << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ +#define ADC_COR_DIFF13 (0x1 << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ +#define ADC_COR_DIFF14 (0x1 << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ +#define ADC_COR_DIFF15 (0x1 << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ +/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */ +#define ADC_CDR0_DATA (0x3ff << 0) /**< \brief (ADC_CDR0) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */ +#define ADC_CDR1_DATA (0x3ff << 0) /**< \brief (ADC_CDR1) Converted Data */ +/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */ +#define ADC_CDR2_DATA (0x3ff << 0) /**< \brief (ADC_CDR2) Converted Data */ +/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */ +#define ADC_CDR3_DATA (0x3ff << 0) /**< \brief (ADC_CDR3) Converted Data */ +/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */ +#define ADC_CDR4_DATA (0x3ff << 0) /**< \brief (ADC_CDR4) Converted Data */ +/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */ +#define ADC_CDR5_DATA (0x3ff << 0) /**< \brief (ADC_CDR5) Converted Data */ +/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */ +#define ADC_CDR6_DATA (0x3ff << 0) /**< \brief (ADC_CDR6) Converted Data */ +/* -------- ADC_CDR15 : (ADC Offset: 0x6C) Channel Data Register 15 -------- */ +#define ADC_CDR15_DATA (0x3ff << 0) /**< \brief (ADC_CDR15) Converted Data */ +/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ +#define ADC_ACR_TSON (0x1 << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ +#define ADC_ACR_IBCTL (0x3 << 8) /**< \brief (ADC_ACR) ADC Bias Current Control */ +/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ADC_WPMR_WPEN (0x1 << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ +#define ADC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ADC_WPMR) Write Protect KEY */ +/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ +#define ADC_WPSR_WPVS (0x1 << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ +#define ADC_WPSR_WPVSRC (0xffff << 8) /**< \brief (ADC_WPSR) Write Protect Violation Source */ +/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ +#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ +/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ +#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ +/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ +#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ +/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ +#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ +/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ +#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ +/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ +#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ +/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ +/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ +/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ +#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ +#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ +#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ +#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ +/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ +#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ +#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_CHIPID Chip Identifier */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Chipid hardware registers */ +typedef struct { + RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* __ASSEMBLY__ */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ +#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Crccu hardware registers */ +typedef struct { + RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ + RwReg Reserved1[1]; + WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ + WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ + RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ + WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ + WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ + RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ + RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ + RwReg Reserved2[4]; + WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ + RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ + RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ + WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ + WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ + RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ + RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ +} Crccu; +#endif /* __ASSEMBLY__ */ +/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ +#define CRCCU_DSCR_DSCR (0x7fffff << 9) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ +/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ +#define CRCCU_DMA_EN_DMAEN (0x1 << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ +/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ +#define CRCCU_DMA_DIS_DMADIS (0x1 << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ +/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ +#define CRCCU_DMA_SR_DMASR (0x1 << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ +/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ +#define CRCCU_DMA_IER_DMAIER (0x1 << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ +/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ +#define CRCCU_DMA_IDR_DMAIDR (0x1 << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ +/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ +#define CRCCU_DMA_IMR_DMAIMR (0x1 << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ +/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ +#define CRCCU_DMA_ISR_DMAISR (0x1 << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ +/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ +#define CRCCU_CR_RESET (0x1 << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ +/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ +#define CRCCU_MR_ENABLE (0x1 << 0) /**< \brief (CRCCU_MR) CRC Enable */ +#define CRCCU_MR_COMPARE (0x1 << 1) /**< \brief (CRCCU_MR) CRC Compare */ +#define CRCCU_MR_PTYPE (0x3 << 2) /**< \brief (CRCCU_MR) Primitive Polynomial */ +#define CRCCU_MR_PTYPE_CCIT8023 (0x0 << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ +#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1 << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ +#define CRCCU_MR_PTYPE_CCIT16 (0x2 << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ +#define CRCCU_MR_DIVIDER (0xf << 4) /**< \brief (CRCCU_MR) Request Divider */ +/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ +#define CRCCU_SR_CRC (0xffffffff << 0) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ +/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ +#define CRCCU_IER_ERRIER (0x1 << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ +/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ +#define CRCCU_IDR_ERRIDR (0x1 << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ +/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ +#define CRCCU_IMR_ERRIMR (0x1 << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ +/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ +#define CRCCU_ISR_ERRISR (0x1 << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Dacc hardware registers */ +typedef struct { + WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + RwReg Reserved1[2]; + WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + RwReg Reserved2[1]; + WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ + WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + RwReg Reserved3[24]; + RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + RwReg Reserved4[19]; + RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ + RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ + RwReg Reserved5[5]; + RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */ + RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */ + RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ + RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ + RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */ + RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */ + RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ + RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ + WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ + RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ +} Dacc; +#endif /* __ASSEMBLY__ */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1 << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_TRGEN (0x1 << 0) /**< \brief (DACC_MR) Trigger Enable */ +#define DACC_MR_TRGEN_DIS (0x0 << 0) // (DACC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. +#define DACC_MR_TRGEN_EN (0x1 << 0) // (DACC_MR) Hardware trigger selected by TRGSEL field is enabled. + +#define DACC_MR_TRGSEL (0x7 << 1) /**< \brief (DACC_MR) Trigger Selection */ +#define DACC_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (DACC_MR) External trigger +#define DACC_MR_TRGSEL_TIOA_0 (0x1 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 0 +#define DACC_MR_TRGSEL_TIOA_1 (0x2 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 1 +#define DACC_MR_TRGSEL_TIOA_2 (0x3 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 2 +#define DACC_MR_TRGSEL_PWM_0 (0x4 << 1) // (DACC_MR) PWM Event Line 0 +#define DACC_MR_TRGSEL_PWM_1 (0x5 << 1) // (DACC_MR) PWM Event Line 1 +#define DACC_MR_WORD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_WORD_HALF (0x0 << 4) /**< \brief (DACC_MR) Half-Word Transfer */ +#define DACC_MR_WORD_WORLD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_SLEEP (0x1 << 5) /**< \brief (DACC_MR) Sleep Mode */ +#define DACC_MR_SLEEP_NORMAL (0x0 << 5) // (DACC_MR) Normal Mode +#define DACC_MR_SLEEP_SLEEP (0x1 << 5) // (DACC_MR) Sleep Modes +#define DACC_MR_FASTWKUP (0x1 << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ +#define DACC_MR_REFRESH (0xff << 8) /**< \brief (DACC_MR) Refresh Period */ +#define DACC_MR_USER_SEL (0x3 << 16) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_USER_SEL_0 (0x0 << 16) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_USER_SEL_1 (0x1 << 16) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_TAG (0x1 << 20) /**< \brief (DACC_MR) Tag Selection Mode */ +#define DACC_MR_MAXS (0x1 << 21) /**< \brief (DACC_MR) Max Speed Mode */ +#define DACC_MR_STARTUP (0x3f << 24) /**< \brief (DACC_MR) Startup Time Selection */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1 << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1 << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +#define DACC_CHER_CH2 (0x1 << 2) /**< \brief (DACC_CHER) Channel 2 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1 << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1 << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +#define DACC_CHDR_CH2 (0x1 << 2) /**< \brief (DACC_CHDR) Channel 2 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1 << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1 << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_CH2 (0x1 << 2) /**< \brief (DACC_CHSR) Channel 2 Status */ +/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ +#define DACC_CDR_DATA (0xffffffff << 0) /**< \brief (DACC_CDR) Data to Convert */ +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY (0x1 << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ +#define DACC_IER_EOC (0x1 << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ +#define DACC_IER_ENDTX (0x1 << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ +#define DACC_IER_TXBUFE (0x1 << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY (0x1 << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ +#define DACC_IDR_EOC (0x1 << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ +#define DACC_IDR_ENDTX (0x1 << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ +#define DACC_IDR_TXBUFE (0x1 << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY (0x1 << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ +#define DACC_IMR_EOC (0x1 << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ +#define DACC_IMR_ENDTX (0x1 << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ +#define DACC_IMR_TXBUFE (0x1 << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY (0x1 << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ +#define DACC_ISR_EOC (0x1 << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ +#define DACC_ISR_ENDTX (0x1 << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ +#define DACC_ISR_TXBUFE (0x1 << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0 (0x3 << 0) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1 (0x3 << 2) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLDACCORE (0x3 << 8) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ +#define DACC_WPMR_WPEN (0x1 << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ +#define DACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (DACC_WPMR) Write Protect KEY */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ +#define DACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (DACC_WPSR) Write protection error */ +#define DACC_WPSR_WPROTADDR (0xff << 8) /**< \brief (DACC_WPSR) Write protection error address */ +/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ +#define DACC_RPR_RXPTR (0xffffffff << 0) /**< \brief (DACC_RPR) Receive Pointer Register */ +/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ +#define DACC_RCR_RXCTR (0xffff << 0) /**< \brief (DACC_RCR) Receive Counter Register */ +/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ +#define DACC_TPR_TXPTR (0xffffffff << 0) /**< \brief (DACC_TPR) Transmit Counter Register */ +/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ +#define DACC_TCR_TXCTR (0xffff << 0) /**< \brief (DACC_TCR) Transmit Counter Register */ +/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ +#define DACC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (DACC_RNPR) Receive Next Pointer */ +/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ +#define DACC_RNCR_RXNCTR (0xffff << 0) /**< \brief (DACC_RNCR) Receive Next Counter */ +/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define DACC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (DACC_TNPR) Transmit Next Pointer */ +/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define DACC_TNCR_TXNCTR (0xffff << 0) /**< \brief (DACC_TNCR) Transmit Counter Next */ +/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ +#define DACC_PTCR_RXTEN (0x1 << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ +#define DACC_PTCR_RXTDIS (0x1 << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ +#define DACC_PTCR_TXTEN (0x1 << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ +#define DACC_PTCR_TXTDIS (0x1 << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ +/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ +#define DACC_PTSR_RXTEN (0x1 << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ +#define DACC_PTSR_TXTEN (0x1 << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_EFC Embedded Flash Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Efc hardware registers */ +typedef struct { + RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ +} Efc; +#endif /* __ASSEMBLY__ */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ +#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ +#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ +#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_GPBR General Purpose Backup Register */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Gpbr hardware registers */ +typedef struct { + RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ + RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ + RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ + RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ +} Gpbr; +#endif /* __ASSEMBLY__ */ +/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ +#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ +/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ +#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ +/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ +#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ +/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ +#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Hsmci hardware registers */ +typedef struct { + WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + RwReg Reserved1[2]; + RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + RwReg Reserved2[1]; + RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + RwReg Reserved3[35]; + RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + RwReg Reserved4[5]; + RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ + RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ + RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ + RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ + RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ + RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ + RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ + RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ + WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ + RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ +} Hsmci; +#endif /* __ASSEMBLY__ */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV (0xff << 0) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_PWSDIV (0x7 << 8) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_RDPROOF (0x1 << 11) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_WRPROOF (0x1 << 12) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_FBYTE (0x1 << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1 << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_PDCMODE (0x1 << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ +#define HSMCI_MR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_MR) Data Block Length */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC (0xf << 0) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOMUL (0x7 << 4) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL (0x3 << 0) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCBUS (0x3 << 6) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB (0x3f << 0) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_RSPTYP (0x3 << 6) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_SPCMD (0x7 << 8) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_OPDCMD (0x1 << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_MAXLAT (0x1 << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_TRCMD (0x3 << 16) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRDIR (0x1 << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRTYP (0x7 << 19) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_IOSPCMD (0x3 << 24) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_ATACS (0x1 << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_BOOT_ACK (0x1 << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT (0xffff << 0) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_BLKR) Data Block Length */ +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC (0xf << 0) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOMUL (0x7 << 4) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ +#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ +#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ +#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ +#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ +#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_ENDRX (0x1 << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ +#define HSMCI_SR_ENDTX (0x1 << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ +#define HSMCI_SR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ +#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ +#define HSMCI_SR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ +#define HSMCI_SR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ +#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ +#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ +#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ +#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ +#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ +#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ +#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ +#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ +#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ +#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ +#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ +#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_ENDRX (0x1 << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ +#define HSMCI_IER_ENDTX (0x1 << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ +#define HSMCI_IER_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ +#define HSMCI_IDR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ +#define HSMCI_IDR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ +#define HSMCI_IMR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ +#define HSMCI_IMR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ +#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ +/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ +#define HSMCI_RPR_RXPTR (0xffffffff << 0) /**< \brief (HSMCI_RPR) Receive Pointer Register */ +/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ +#define HSMCI_RCR_RXCTR (0xffff << 0) /**< \brief (HSMCI_RCR) Receive Counter Register */ +/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ +#define HSMCI_TPR_TXPTR (0xffffffff << 0) /**< \brief (HSMCI_TPR) Transmit Counter Register */ +/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ +#define HSMCI_TCR_TXCTR (0xffff << 0) /**< \brief (HSMCI_TCR) Transmit Counter Register */ +/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ +#define HSMCI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ +/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ +#define HSMCI_RNCR_RXNCTR (0xffff << 0) /**< \brief (HSMCI_RNCR) Receive Next Counter */ +/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define HSMCI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ +/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define HSMCI_TNCR_TXNCTR (0xffff << 0) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ +/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ +#define HSMCI_PTCR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ +#define HSMCI_PTCR_RXTDIS (0x1 << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ +#define HSMCI_PTCR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ +#define HSMCI_PTCR_TXTDIS (0x1 << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ +/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ +#define HSMCI_PTSR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ +#define HSMCI_PTSR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_MATRIX AHB Bus Matrix */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Matrix hardware registers */ +typedef struct { + RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ + RwReg Reserved1[12]; + RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + RwReg Reserved2[11]; + RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ + RwReg Reserved3[1]; + RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ + RwReg Reserved4[1]; + RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ + RwReg Reserved5[1]; + RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ + RwReg Reserved6[1]; + RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ + RwReg Reserved7[28]; + RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System IO Configuration register */ + RwReg Reserved8[1]; + RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ + RwReg Reserved9[49]; + RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ + RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ +} Matrix; +#endif /* __ASSEMBLY__ */ +/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ +#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ +/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ +#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ +#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ +#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ +/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ +#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ +#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ +#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ +#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ +/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ +#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ +#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ +#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ +#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ +#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ +/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ +#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ +#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ +#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ +#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ +#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ +/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ +#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ +#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ +#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ +#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ +#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ +/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ +#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ +#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ +#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ +#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ +#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System IO Configuration register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1 << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1 << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1 << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1 << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO10 (0x1 << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ +#define CCFG_SYSIO_SYSIO11 (0x1 << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1 << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1 << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1 << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1 << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1 << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1 << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ +#define MATRIX_WPMR_WPKEY (0xffffff << 8) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1 << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ +#define MATRIX_WPSR_WPVSRC (0xffff << 8) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PDC Peripheral DMA Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Pdc hardware registers */ +typedef struct { + RwReg Reserved1[64]; + RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ + RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ + RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ + RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ + RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ + RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ + RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ + RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ + WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ + RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ +} Pdc; +#endif /* __ASSEMBLY__ */ +/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ +#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ +/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ +#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ +/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ +#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ +/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ +#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ +/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ +#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ +/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ +#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ +/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ +/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ +/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ +#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ +#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ +#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ +#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ +/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ +#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ +#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PIO Parallel Input/Output */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Pio hardware registers */ +typedef struct { + WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + RwReg Reserved1[1]; + WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + RwReg Reserved2[1]; + WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + RwReg Reserved3[1]; + WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + RwReg Reserved4[1]; + WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + RwReg Reserved5[1]; + RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + RwReg Reserved6[2]; + WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ + WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ + RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ + RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + RwReg Reserved7[1]; + WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + RwReg Reserved8[1]; + WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ + RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + RwReg Reserved9[1]; + WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + RwReg Reserved10[1]; + WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ + WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ + RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + RwReg Reserved11[1]; + RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ + RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ + RwReg Reserved12[5]; + RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + RwReg Reserved13[19]; + RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ + WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ + WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ + RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ + RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ + RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ + RwReg Reserved14[38]; +} Pio; +#endif /* __ASSEMBLY__ */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1 << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P1 (0x1 << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P2 (0x1 << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P3 (0x1 << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P4 (0x1 << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P5 (0x1 << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P6 (0x1 << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P7 (0x1 << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P8 (0x1 << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P9 (0x1 << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P10 (0x1 << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P11 (0x1 << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P12 (0x1 << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P13 (0x1 << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P14 (0x1 << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P15 (0x1 << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P16 (0x1 << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P17 (0x1 << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P18 (0x1 << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P19 (0x1 << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P20 (0x1 << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P21 (0x1 << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P22 (0x1 << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P23 (0x1 << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P24 (0x1 << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P25 (0x1 << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P26 (0x1 << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P27 (0x1 << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P28 (0x1 << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P29 (0x1 << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P30 (0x1 << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P31 (0x1 << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ +#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ +#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ +#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1 << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P1 (0x1 << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P2 (0x1 << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P3 (0x1 << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P4 (0x1 << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P5 (0x1 << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P6 (0x1 << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P7 (0x1 << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P8 (0x1 << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P9 (0x1 << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P10 (0x1 << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P11 (0x1 << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P12 (0x1 << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P13 (0x1 << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P14 (0x1 << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P15 (0x1 << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P16 (0x1 << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P17 (0x1 << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P18 (0x1 << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P19 (0x1 << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P20 (0x1 << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P21 (0x1 << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P22 (0x1 << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P23 (0x1 << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P24 (0x1 << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P25 (0x1 << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P26 (0x1 << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P27 (0x1 << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P28 (0x1 << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P29 (0x1 << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P30 (0x1 << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P31 (0x1 << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1 << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P1 (0x1 << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P2 (0x1 << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P3 (0x1 << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P4 (0x1 << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P5 (0x1 << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P6 (0x1 << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P7 (0x1 << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P8 (0x1 << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P9 (0x1 << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P10 (0x1 << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P11 (0x1 << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P12 (0x1 << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P13 (0x1 << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P14 (0x1 << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P15 (0x1 << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P16 (0x1 << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P17 (0x1 << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P18 (0x1 << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P19 (0x1 << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P20 (0x1 << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P21 (0x1 << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P22 (0x1 << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P23 (0x1 << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P24 (0x1 << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P25 (0x1 << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P26 (0x1 << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P27 (0x1 << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P28 (0x1 << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P29 (0x1 << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P30 (0x1 << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P31 (0x1 << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1 << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P1 (0x1 << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P2 (0x1 << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P3 (0x1 << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P4 (0x1 << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P5 (0x1 << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P6 (0x1 << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P7 (0x1 << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P8 (0x1 << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P9 (0x1 << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P10 (0x1 << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P11 (0x1 << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P12 (0x1 << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P13 (0x1 << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P14 (0x1 << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P15 (0x1 << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P16 (0x1 << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P17 (0x1 << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P18 (0x1 << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P19 (0x1 << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P20 (0x1 << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P21 (0x1 << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P22 (0x1 << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P23 (0x1 << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P24 (0x1 << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P25 (0x1 << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P26 (0x1 << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P27 (0x1 << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P28 (0x1 << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P29 (0x1 << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P30 (0x1 << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P31 (0x1 << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ +#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ +#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ +#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1 << 0) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT1 (0x1 << 1) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT2 (0x1 << 2) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT3 (0x1 << 3) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT4 (0x1 << 4) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT5 (0x1 << 5) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT6 (0x1 << 6) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT7 (0x1 << 7) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT8 (0x1 << 8) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT9 (0x1 << 9) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT10 (0x1 << 10) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT11 (0x1 << 11) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT12 (0x1 << 12) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT13 (0x1 << 13) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT14 (0x1 << 14) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT15 (0x1 << 15) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT16 (0x1 << 16) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT17 (0x1 << 17) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT18 (0x1 << 18) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT19 (0x1 << 19) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT20 (0x1 << 20) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT21 (0x1 << 21) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT22 (0x1 << 22) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT23 (0x1 << 23) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT24 (0x1 << 24) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT25 (0x1 << 25) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT26 (0x1 << 26) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT27 (0x1 << 27) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT28 (0x1 << 28) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT29 (0x1 << 29) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT30 (0x1 << 30) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT31 (0x1 << 31) /**< \brief (PIO_SCHMITT) */ +/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1 << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE (0x3 << 4) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_ALWYS (0x1 << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1 << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1 << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1 << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1 << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1 << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1 << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1 << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1 << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1 << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1 << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1 << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ +#define PIO_PCISR_ENDRX (0x1 << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ +#define PIO_PCISR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ +/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA (0xffffffff << 0) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PMC Power Management Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Pmc hardware registers */ +typedef struct { + WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + RwReg Reserved1[1]; + WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + RwReg Reserved2[1]; + RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ + RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + RwReg Reserved3[1]; + RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + RwReg Reserved4[1]; + RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + RwReg Reserved5[5]; + WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + RwReg Reserved6[26]; + RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ + RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ + RwReg Reserved7[5]; + WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + RwReg Reserved8[1]; + RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ +} Pmc; +#endif /* __ASSEMBLY__ */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_UDP (0x1 << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ +#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_UDP (0x1 << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ +#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_UDP (0x1 << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ +#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID2 (0x1 << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ +#define PMC_PCER0_PID3 (0x1 << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ +#define PMC_PCER0_PID4 (0x1 << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ +#define PMC_PCER0_PID5 (0x1 << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ +#define PMC_PCER0_PID6 (0x1 << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ +#define PMC_PCER0_PID7 (0x1 << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1 << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1 << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1 << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1 << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1 << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1 << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1 << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1 << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1 << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1 << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1 << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1 << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1 << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1 << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1 << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1 << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1 << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1 << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1 << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1 << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1 << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1 << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1 << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1 << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID2 (0x1 << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ +#define PMC_PCDR0_PID3 (0x1 << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ +#define PMC_PCDR0_PID4 (0x1 << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ +#define PMC_PCDR0_PID5 (0x1 << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ +#define PMC_PCDR0_PID6 (0x1 << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ +#define PMC_PCDR0_PID7 (0x1 << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1 << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1 << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1 << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1 << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1 << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1 << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1 << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1 << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1 << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1 << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1 << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1 << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1 << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1 << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1 << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1 << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1 << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1 << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1 << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1 << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1 << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1 << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1 << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1 << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID2 (0x1 << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ +#define PMC_PCSR0_PID3 (0x1 << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ +#define PMC_PCSR0_PID4 (0x1 << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ +#define PMC_PCSR0_PID5 (0x1 << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ +#define PMC_PCSR0_PID6 (0x1 << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ +#define PMC_PCSR0_PID7 (0x1 << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1 << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1 << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1 << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1 << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1 << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1 << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1 << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1 << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1 << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1 << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1 << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1 << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1 << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1 << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1 << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1 << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1 << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1 << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1 << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1 << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1 << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1 << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1 << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1 << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ +#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ +#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ +#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ +/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ +#define CKGR_PLLBR_DIVB (0xff << 0) /**< \brief (CKGR_PLLBR) Divider */ +#define CKGR_PLLBR_PLLBCOUNT (0x3f << 8) /**< \brief (CKGR_PLLBR) PLLB Counter */ +#define CKGR_PLLBR_MULB (0x7ff << 16) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */ +#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PLLADIV2 (0x1 << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ +#define PMC_MCKR_PLLBDIV2 (0x1 << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1 << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV (0xf << 8) /**< \brief (PMC_USB) Divider for USB Clock. */ +/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ +#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_LOCKB (0x1 << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_LOCKB (0x1 << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ +#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_LOCKB (0x1 << 2) /**< \brief (PMC_SR) PLLB Lock Status */ +#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_LOCKB (0x1 << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1 << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ +#define PMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (PMC_WPMR) Write Protect KEY */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ +#define PMC_WPSR_WPVS (0x1 << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (PMC_WPSR) Write Protect Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1 << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1 << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1 << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1 << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID36 (0x1 << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ +#define PMC_PCER1_PID37 (0x1 << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID38 (0x1 << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ +#define PMC_PCER1_PID39 (0x1 << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1 << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1 << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1 << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1 << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1 << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1 << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1 << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1 << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1 << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1 << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1 << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1 << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1 << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1 << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID54 (0x1 << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ +#define PMC_PCER1_PID55 (0x1 << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ +#define PMC_PCER1_PID56 (0x1 << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1 << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1 << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1 << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1 << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +#define PMC_PCER1_PID61 (0x1 << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ +#define PMC_PCER1_PID62 (0x1 << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ +#define PMC_PCER1_PID63 (0x1 << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1 << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1 << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1 << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1 << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID36 (0x1 << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ +#define PMC_PCDR1_PID37 (0x1 << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID38 (0x1 << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ +#define PMC_PCDR1_PID39 (0x1 << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1 << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1 << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1 << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1 << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1 << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1 << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1 << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1 << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1 << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1 << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1 << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1 << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1 << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1 << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID54 (0x1 << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ +#define PMC_PCDR1_PID55 (0x1 << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ +#define PMC_PCDR1_PID56 (0x1 << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1 << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1 << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1 << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1 << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +#define PMC_PCDR1_PID61 (0x1 << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ +#define PMC_PCDR1_PID62 (0x1 << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ +#define PMC_PCDR1_PID63 (0x1 << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1 << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1 << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1 << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1 << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID36 (0x1 << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ +#define PMC_PCSR1_PID37 (0x1 << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID38 (0x1 << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ +#define PMC_PCSR1_PID39 (0x1 << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1 << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1 << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1 << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1 << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1 << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1 << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1 << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1 << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1 << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1 << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1 << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1 << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1 << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1 << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID54 (0x1 << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ +#define PMC_PCSR1_PID55 (0x1 << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ +#define PMC_PCSR1_PID56 (0x1 << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1 << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1 << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1 << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1 << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +#define PMC_PCSR1_PID61 (0x1 << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ +#define PMC_PCSR1_PID62 (0x1 << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ +#define PMC_PCSR1_PID63 (0x1 << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4 (0x7f << 0) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ +#define PMC_OCR_SEL4 (0x1 << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ +#define PMC_OCR_CAL8 (0x7f << 8) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ +#define PMC_OCR_SEL8 (0x1 << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ +#define PMC_OCR_CAL12 (0x7f << 16) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ +#define PMC_OCR_SEL12 (0x1 << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief PwmCh_num hardware registers */ +typedef struct { + RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + RwReg PWM_CPDR; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + RwReg PWM_CPDRUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief Pwm hardware registers */ +typedef struct { + RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + RwReg Reserved1[1]; + RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ + RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + RwReg Reserved2[3]; + RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + RwReg Reserved3[11]; + RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + RwReg Reserved4[12]; + WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ + RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ + RwReg Reserved5[5]; + RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ + RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ + RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ + RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ + RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ + RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ + RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ + RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ + WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ + RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ + RwReg Reserved6[2]; + RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ + WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ + RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ + WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ + RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ + WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ + RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ + WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ + RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ + WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ + RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ + WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ + RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ + WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ + RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ + WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ + RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ + WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ + RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ + WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ + RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ + WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ + RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ + WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ + RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ + WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ + RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ + WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ + RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ + WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ + RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ + WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ + RwReg Reserved7[20]; + PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ +} Pwm; +#endif /* __ASSEMBLY__ */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ +#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ +#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ +#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ +#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ +#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ +#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ +#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ +#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ +#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ +#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ +#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ +#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ +#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ +#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ +#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ +#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ +#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ +#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ +#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ +#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ +#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ +#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ +#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ +#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ +#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ +#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ +#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ +#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ +/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ +#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ +#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ +#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ +#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ +/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ +#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ +#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ +#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ +#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ +#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ +#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ +#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1 << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1 << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1 << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1 << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ +#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ +#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ +#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ +#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ +/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ +#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ +/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ +#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ +/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ +#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ +/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ +#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ +/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ +#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ +/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ +#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ +/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ +#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ +/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ +#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ +#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ +#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ +#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ +/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ +#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ +#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ +/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ +#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ +#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ +/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ +#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ +#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ +#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ +#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ +#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ +#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ +/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ +#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ +#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ +#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ +#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ +#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ +/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ +#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ +#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ +#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ +#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ +#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ +#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ +#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ +#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ +/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ +#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ +#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ +#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ +#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ +#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ +#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ +/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ +#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ +#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ +#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ +#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ +#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ +#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ +#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ +#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ +/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ +#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ +#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ +#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ +#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ +#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ +#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ +/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ +#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ +#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ +#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ +#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ +#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ +#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ +#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ +#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ +/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ +#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ +#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ +#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ +#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ +#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ +#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ +/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ +#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ +#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ +#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ +#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ +#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ +#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ +#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ +#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ +/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ +#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ +#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ +#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ +#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ +#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ +#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ +/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ +#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ +#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ +#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ +#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ +#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ +#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ +#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ +#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ +/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ +#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ +#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ +#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ +#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ +#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ +#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ +/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ +#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ +#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ +#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ +#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ +#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ +#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ +#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ +#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ +/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ +#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ +#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ +#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ +#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ +#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ +#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ +/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ +#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ +#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ +#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ +#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ +#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ +#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ +#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ +#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ +/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ +#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ +#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ +#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ +#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ +#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ +#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ +#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ +#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ +#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ +#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ +#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ +#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ +#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ +/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ +#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ +/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ +#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ +/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ +#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ +#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ +#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ +/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ +#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ +#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ +#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ +#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ +#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ +#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ +#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ +#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ +#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ +/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ +#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ +/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ +#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ +/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ +#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ +#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ +#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ +/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ +#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ +#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ +#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ +#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ +#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ +#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ +#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ +#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ +#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ +/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ +#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ +/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ +#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ +/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ +#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ +#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ +#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ +/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ +#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ +#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ +#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ +#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ +#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ +#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ +#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ +#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ +#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ +/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ +#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ +/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ +#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ +/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ +#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ +#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ +#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_RSTC Reset Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Rstc hardware registers */ +typedef struct { + WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* __ASSEMBLY__ */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ +#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_RTC Real-time Clock */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Rtc hardware registers */ +typedef struct { + RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ +} Rtc; +#endif /* __ASSEMBLY__ */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ +#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ +#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ +#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ +#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ +#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_RTT Real-time Timer */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Rtt hardware registers */ +typedef struct { + RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* __ASSEMBLY__ */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ +#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SMC Static Memory Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief SmcCs_number hardware registers */ +typedef struct { + RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +typedef struct { + SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */ + RwReg Reserved1[12]; + RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + RwReg Reserved2[22]; + RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ + RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ +} Smc; +#endif /* __ASSEMBLY__ */ +/* -------- SMC_SETUP0 : (SMC Offset: 0x0) SMC Setup Register (CS_number = 0) -------- */ +#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup Length */ +#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup Length in WRITE Access */ +#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup Length */ +#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE0 : (SMC Offset: 0x4) SMC Pulse Register (CS_number = 0) -------- */ +#define SMC_PULSE0_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ +#define SMC_PULSE0_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE0_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ +#define SMC_PULSE0_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE0 : (SMC Offset: 0x8) SMC Cycle Register (CS_number = 0) -------- */ +#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ +#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ +/* -------- SMC_MODE0 : (SMC Offset: 0xC) SMC Mode Register (CS_number = 0) -------- */ +#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ +#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ +#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ +#define SMC_MODE0_DBW (0x3 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ +#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ +#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ +#define SMC_MODE0_PMEN (0x1 << 24) /**< \brief (SMC_MODE0) Page Mode Enabled */ +#define SMC_MODE0_PS (0x3 << 28) /**< \brief (SMC_MODE0) Page Size */ +/* -------- SMC_SETUP1 : (SMC Offset: 0x10) SMC Setup Register (CS_number = 1) -------- */ +#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup Length */ +#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup Length in WRITE Access */ +#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup Length */ +#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE1 : (SMC Offset: 0x14) SMC Pulse Register (CS_number = 1) -------- */ +#define SMC_PULSE1_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ +#define SMC_PULSE1_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE1_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ +#define SMC_PULSE1_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE1 : (SMC Offset: 0x18) SMC Cycle Register (CS_number = 1) -------- */ +#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ +#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ +/* -------- SMC_MODE1 : (SMC Offset: 0x1C) SMC Mode Register (CS_number = 1) -------- */ +#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ +#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ +#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ +#define SMC_MODE1_DBW (0x3 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ +#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ +#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ +#define SMC_MODE1_PMEN (0x1 << 24) /**< \brief (SMC_MODE1) Page Mode Enabled */ +#define SMC_MODE1_PS (0x3 << 28) /**< \brief (SMC_MODE1) Page Size */ +/* -------- SMC_SETUP2 : (SMC Offset: 0x20) SMC Setup Register (CS_number = 2) -------- */ +#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup Length */ +#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup Length in WRITE Access */ +#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup Length */ +#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE2 : (SMC Offset: 0x24) SMC Pulse Register (CS_number = 2) -------- */ +#define SMC_PULSE2_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ +#define SMC_PULSE2_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE2_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ +#define SMC_PULSE2_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE2 : (SMC Offset: 0x28) SMC Cycle Register (CS_number = 2) -------- */ +#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ +#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ +/* -------- SMC_MODE2 : (SMC Offset: 0x2C) SMC Mode Register (CS_number = 2) -------- */ +#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ +#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ +#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ +#define SMC_MODE2_DBW (0x3 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ +#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ +#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ +#define SMC_MODE2_PMEN (0x1 << 24) /**< \brief (SMC_MODE2) Page Mode Enabled */ +#define SMC_MODE2_PS (0x3 << 28) /**< \brief (SMC_MODE2) Page Size */ +/* -------- SMC_SETUP3 : (SMC Offset: 0x30) SMC Setup Register (CS_number = 3) -------- */ +#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup Length */ +#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup Length in WRITE Access */ +#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup Length */ +#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE3 : (SMC Offset: 0x34) SMC Pulse Register (CS_number = 3) -------- */ +#define SMC_PULSE3_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ +#define SMC_PULSE3_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE3_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ +#define SMC_PULSE3_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE3 : (SMC Offset: 0x38) SMC Cycle Register (CS_number = 3) -------- */ +#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ +#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ +/* -------- SMC_MODE3 : (SMC Offset: 0x3C) SMC Mode Register (CS_number = 3) -------- */ +#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ +#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ +#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ +#define SMC_MODE3_DBW (0x3 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ +#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ +#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ +#define SMC_MODE3_PMEN (0x1 << 24) /**< \brief (SMC_MODE3) Page Mode Enabled */ +#define SMC_MODE3_PS (0x3 << 28) /**< \brief (SMC_MODE3) Page Size */ +/* -------- SMC_SETUP4 : (SMC Offset: 0x40) SMC Setup Register (CS_number = 4) -------- */ +#define SMC_SETUP4_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP4) NWE Setup Length */ +#define SMC_SETUP4_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP4) NCS Setup Length in WRITE Access */ +#define SMC_SETUP4_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP4) NRD Setup Length */ +#define SMC_SETUP4_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP4) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE4 : (SMC Offset: 0x44) SMC Pulse Register (CS_number = 4) -------- */ +#define SMC_PULSE4_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE4) NWE Pulse Length */ +#define SMC_PULSE4_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE4) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE4_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE4) NRD Pulse Length */ +#define SMC_PULSE4_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE4) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE4 : (SMC Offset: 0x48) SMC Cycle Register (CS_number = 4) -------- */ +#define SMC_CYCLE4_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE4) Total Write Cycle Length */ +#define SMC_CYCLE4_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE4) Total Read Cycle Length */ +/* -------- SMC_MODE4 : (SMC Offset: 0x4C) SMC Mode Register (CS_number = 4) -------- */ +#define SMC_MODE4_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE4) */ +#define SMC_MODE4_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE4) */ +#define SMC_MODE4_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE4) NWAIT Mode */ +#define SMC_MODE4_DBW (0x3 << 12) /**< \brief (SMC_MODE4) Data Bus Width */ +#define SMC_MODE4_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE4) Data Float Time */ +#define SMC_MODE4_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE4) TDF Optimization */ +#define SMC_MODE4_PMEN (0x1 << 24) /**< \brief (SMC_MODE4) Page Mode Enabled */ +#define SMC_MODE4_PS (0x3 << 28) /**< \brief (SMC_MODE4) Page Size */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_CS0SE (0x1 << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS1SE (0x1 << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS2SE (0x1 << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS3SE (0x1 << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1 << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SMC_WPMR) Write Protect KEY */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ +#define SMC_WPSR_WPVS (0x1 << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ +#define SMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protect Violation Source */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SPI Serial Peripheral Interface */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Spi hardware registers */ +typedef struct { + WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + RwReg Reserved1[4]; + RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + RwReg Reserved2[41]; + RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ + RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ + RwReg Reserved3[5]; + RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ + RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ + RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ + RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ + RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ + RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ + RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ + RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ + WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ + RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ +} Spi; +#endif /* __ASSEMBLY__ */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ +#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ +#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ +#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ +#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ +#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ +#define SPI_SR_ENDRX (0x1 << 4) /**< \brief (SPI_SR) End of RX buffer */ +#define SPI_SR_ENDTX (0x1 << 5) /**< \brief (SPI_SR) End of TX buffer */ +#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) RX Buffer Full */ +#define SPI_SR_TXBUFE (0x1 << 7) /**< \brief (SPI_SR) TX Buffer Empty */ +#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ +#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ +#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ +#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_ENDRX (0x1 << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ +#define SPI_IER_ENDTX (0x1 << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ +#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ +#define SPI_IER_TXBUFE (0x1 << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ +#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_ENDRX (0x1 << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ +#define SPI_IDR_ENDTX (0x1 << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ +#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ +#define SPI_IDR_TXBUFE (0x1 << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ +#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_ENDRX (0x1 << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ +#define SPI_IMR_ENDTX (0x1 << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ +#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ +#define SPI_IMR_TXBUFE (0x1 << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ +#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 35.) */ +#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ +#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ +#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ +#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ +#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ +#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ +#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ +#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ +#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ +#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ +#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ +#define SPI_WPMR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */ +#define SPI_WPMR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ +#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ +/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ +#define SPI_RPR_RXPTR (0xffffffff << 0) /**< \brief (SPI_RPR) Receive Pointer Register */ +/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ +#define SPI_RCR_RXCTR (0xffff << 0) /**< \brief (SPI_RCR) Receive Counter Register */ +/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ +#define SPI_TPR_TXPTR (0xffffffff << 0) /**< \brief (SPI_TPR) Transmit Counter Register */ +/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ +#define SPI_TCR_TXCTR (0xffff << 0) /**< \brief (SPI_TCR) Transmit Counter Register */ +/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ +#define SPI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SPI_RNPR) Receive Next Pointer */ +/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ +#define SPI_RNCR_RXNCTR (0xffff << 0) /**< \brief (SPI_RNCR) Receive Next Counter */ +/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define SPI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SPI_TNPR) Transmit Next Pointer */ +/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define SPI_TNCR_TXNCTR (0xffff << 0) /**< \brief (SPI_TNCR) Transmit Counter Next */ +/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ +#define SPI_PTCR_RXTEN (0x1 << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ +#define SPI_PTCR_RXTDIS (0x1 << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ +#define SPI_PTCR_TXTEN (0x1 << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ +#define SPI_PTCR_TXTDIS (0x1 << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ +/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ +#define SPI_PTSR_RXTEN (0x1 << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ +#define SPI_PTSR_TXTEN (0x1 << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SSC Synchronous Serial Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Ssc hardware registers */ +typedef struct { + WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + RwReg Reserved1[2]; + RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + RwReg Reserved2[2]; + RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + RwReg Reserved3[37]; + RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ + RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ + RwReg Reserved4[5]; + RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ + RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ + RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ + RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ + RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ + RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ + RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ + RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ + WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ + RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ +} Ssc; +#endif /* __ASSEMBLY__ */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ +#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ +#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ +#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ +#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ +#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ +#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ +#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ +#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ +#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ +#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ +#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ +#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ +#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ +#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ +#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ +#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ +#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ +#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ +#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ +/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ +#define SSC_RPR_RXPTR (0xffffffff << 0) /**< \brief (SSC_RPR) Receive Pointer Register */ +/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ +#define SSC_RCR_RXCTR (0xffff << 0) /**< \brief (SSC_RCR) Receive Counter Register */ +/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ +#define SSC_TPR_TXPTR (0xffffffff << 0) /**< \brief (SSC_TPR) Transmit Counter Register */ +/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ +#define SSC_TCR_TXCTR (0xffff << 0) /**< \brief (SSC_TCR) Transmit Counter Register */ +/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ +#define SSC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SSC_RNPR) Receive Next Pointer */ +/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ +#define SSC_RNCR_RXNCTR (0xffff << 0) /**< \brief (SSC_RNCR) Receive Next Counter */ +/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define SSC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SSC_TNPR) Transmit Next Pointer */ +/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define SSC_TNCR_TXNCTR (0xffff << 0) /**< \brief (SSC_TNCR) Transmit Counter Next */ +/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ +#define SSC_PTCR_RXTEN (0x1 << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ +#define SSC_PTCR_RXTDIS (0x1 << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ +#define SSC_PTCR_TXTEN (0x1 << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ +#define SSC_PTCR_TXTDIS (0x1 << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ +/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ +#define SSC_PTSR_RXTEN (0x1 << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ +#define SSC_PTSR_TXTEN (0x1 << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SUPC Supply Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Supc hardware registers */ +typedef struct { + WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ + RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ + RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* __ASSEMBLY__ */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ +#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ +#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ +#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ +#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ +#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ +#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ +#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ +#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ +#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ +#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ +#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ +#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ +#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ +#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ +#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ +#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0 << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ +#define SUPC_MR_ONREG_ONREG_USED (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ +#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ +#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ +#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ +#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ +#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ +#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ +#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ +#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ +#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ +#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ +#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ +#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ +#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ +#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ +#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ +#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ +#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ +#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ +#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ +#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ +#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ +#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ +#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ +#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ +#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ +#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ +#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ +#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ +#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ +#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ +#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ +#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ +#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ +#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ +#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ +#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ +#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ +#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ +#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ +#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ +#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ +#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ +#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ +#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ +#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ +#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ +#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ +#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ +#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ +#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ +#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ +#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ +#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ +#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ +#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ +#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ +#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ +#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_TC Timer Counter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief TcChannel hardware registers */ +typedef struct { + RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + RwReg Reserved1[2]; + RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + RwReg Reserved2[4]; +} TcChannel; +/** \brief Tc hardware registers */ +typedef struct { + TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + RwReg Reserved1[2]; + RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ + RwReg Reserved2[5]; + RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ +} Tc; +#endif /* __ASSEMBLY__ */ +/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ +#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ +#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ +#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ +/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ +#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ +#define TC_CM0_TCCLKS_TIMER_DIV1_CLOCK (0x0 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV1_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV2_CLOCK (0x1 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV2_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV3_CLOCK (0x2 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV3_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV4_CLOCK (0x3 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV4_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV5_CLOCK (0x4 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV5_CLOCK*/ +#define TC_CM0_TCCLKS_XC0 (0x5 << 0) /**< (TC_CMR0) Clock selected: XC0*/ +#define TC_CM0_TCCLKS_XC1 (0x6 << 0) /**< (TC_CMR0) Clock selected: XC1*/ +#define TC_CM0_TCCLKS_XC2 (0x7 << 0) /**< (TC_CMR0) Clock selected: XC2*/ +#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ +#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ +#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ +#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ +#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ +#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ +#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ +#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ +#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ +#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ +#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ +#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ +#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ +#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ +#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ +#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ +#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ +#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ +#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ +#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ +#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ +#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ +#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ +#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ +#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ +#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ + +#define TC_CMR0_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define TC_CMR0_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define TC_CMR0_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define TC_CMR0_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle + +#define TC_CMR0_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define TC_CMR0_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define TC_CMR0_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define TC_CMR0_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ +#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ +/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ +#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ +/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ +#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ +/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ +#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ +/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ +#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ +#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ +#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ +#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ +#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ +#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ +#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ +#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ +#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ +#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ +#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ +/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ +#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ +#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ +#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ +#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ +#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ +#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ +#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ +#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ +/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ +#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ +#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ +#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ +#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ +#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ +#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ +#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ +#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ +/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ +#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ +#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ +#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ +#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ +#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ +#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ +#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ +#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ +/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ +#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ +#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ +#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ +/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ +#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ +#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ +#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ +#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ +#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ +#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ +#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ +#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ +#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ +#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ +#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ +#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ +#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ +#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ +#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ +#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ +#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ +#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ +#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ +#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ +#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ +#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ +#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ +#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ +#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ +#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ +#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ +/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ +#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ +/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ +#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ +/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ +#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ +/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ +#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ +/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ +#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ +#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ +#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ +#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ +#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ +#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ +#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ +#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ +#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ +#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ +#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ +/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ +#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ +#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ +#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ +#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ +#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ +#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ +#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ +#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ +/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ +#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ +#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ +#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ +#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ +#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ +#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ +#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ +#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ +/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ +#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ +#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ +#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ +#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ +#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ +#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ +#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ +#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ +/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ +#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ +#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ +#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ +/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ +#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ +#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ +#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ +#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ +#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ +#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ +#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ +#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ +#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ +#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ +#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ +#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ +#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ +#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ +#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ +#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ +#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ +#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ +#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ +#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ +#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ +#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ +#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ +#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ +#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ +#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ +#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ +/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ +#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ +/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ +#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ +/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ +#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ +/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ +#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ +/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ +#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ +#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ +#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ +#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ +#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ +#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ +#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ +#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ +#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ +#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ +#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ +/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ +#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ +#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ +#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ +#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ +#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ +#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ +#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ +#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ +/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ +#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ +#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ +#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ +#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ +#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ +#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ +#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ +#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ +/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ +#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ +#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ +#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ +#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ +#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ +#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ +#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ +#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ +#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ +#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ +#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ +#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ +#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ +#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ +#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ +#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ +#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ +#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ +#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ +#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ +#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ +#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ +#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ +#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ +#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ +#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ +#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ +#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ +#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ +#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ +#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ +#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ +#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ +#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1 << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1 << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ +#define TC_WPMR_WPEN (0x1 << 0) /**< \brief (TC_WPMR) Write Protect Enable */ +#define TC_WPMR_WPKEY (0xffffff << 8) /**< \brief (TC_WPMR) Write Protect KEY */ +/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ +#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ +#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_TWI Two-wire Interface */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Twi hardware registers */ +typedef struct { + WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ + RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ + RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ + RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ + RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ + RwReg Reserved1[3]; + RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ + WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ + WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ + RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ + RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ + WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ + RwReg Reserved2[50]; + RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ + RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ + RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ + RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ + RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ + RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ + RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ + RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ + WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ + RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ +} Twi; +#endif /* __ASSEMBLY__ */ +/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ +#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ +#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ +#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ +#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ +#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ +#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ +#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ +#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ +#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ +#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ +#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ +#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */ +/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ +#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */ +/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ +#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */ +#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */ +#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ +#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ +#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ +#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ +#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ +#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ +#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ +#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ +#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ +#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ +#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ +#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ +#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ +#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ +#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ +#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ +/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ +#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ +#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ +#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ +#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ +#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ +#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ +#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ +#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ +#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ +#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ +#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ +#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ +#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ +#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ +#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ +#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ +#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ +#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ +#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ +#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ +#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ +#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ +#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ +#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ +#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ +#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ +#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ +#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ +#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ +#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ +#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ +#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ +#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ +#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ +#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ +#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ +/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ +#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ +/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ +#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ +/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ +#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ +/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ +#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ +/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ +#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ +/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ +#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ +/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ +#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ +/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ +/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ +/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ +#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ +#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ +#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ +#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ +/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ +#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ +#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Uart hardware registers */ +typedef struct { + WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + RwReg Reserved1[55]; + RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ + RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ + RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ + RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ + RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ + RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ + RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ + RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ + WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ + RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ +} Uart; +#endif /* __ASSEMBLY__ */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ +#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ +#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ +#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ +#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ +#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ +#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ +#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ +#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ +#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ +#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ +#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ +#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ +/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ +#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ +/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ +#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ +/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ +#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ +/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ +#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ +/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ +#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ +/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ +#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ +/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ +/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ +/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ +#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ +#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ +#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ +#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ +/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ +#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ +#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Device Port */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_UDP USB Device Port */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Udp hardware registers */ +typedef struct { + RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ + RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ + RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ + RwReg Reserved1[1]; + WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ + WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ + RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ + RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ + WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ + RwReg Reserved2[1]; + RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ + RwReg Reserved3[1]; + RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x30) Endpoint Control and Status Register (ept_num = 0) */ + RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x50) Endpoint FIFO Data Register (ept_num = 0) */ + RwReg Reserved4[1]; + RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ +} Udp; +#endif /* __ASSEMBLY__ */ +/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ +#define UDP_FRM_NUM_FRM_NUM (0x7ff << 0) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ +#define UDP_FRM_NUM_FRM_ERR (0x1 << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ +#define UDP_FRM_NUM_FRM_OK (0x1 << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ +/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ +#define UDP_GLB_STAT_FADDEN (0x1 << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ +#define UDP_GLB_STAT_CONFG (0x1 << 1) /**< \brief (UDP_GLB_STAT) Configured */ +#define UDP_GLB_STAT_ESR (0x1 << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ +#define UDP_GLB_STAT_RSMINPR (0x1 << 3) /**< \brief (UDP_GLB_STAT) */ +#define UDP_GLB_STAT_RMWUPE (0x1 << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ +#define UDP_FADDR_FADD (0x7f << 0) /**< \brief (UDP_FADDR) Function Address Value */ +#define UDP_FADDR_FEN (0x1 << 8) /**< \brief (UDP_FADDR) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ +#define UDP_IER_EP0INT (0x1 << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ +#define UDP_IER_EP1INT (0x1 << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ +#define UDP_IER_EP2INT (0x1 << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ +#define UDP_IER_EP3INT (0x1 << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ +#define UDP_IER_EP4INT (0x1 << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ +#define UDP_IER_EP5INT (0x1 << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ +#define UDP_IER_EP6INT (0x1 << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ +#define UDP_IER_EP7INT (0x1 << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ +#define UDP_IER_RXSUSP (0x1 << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ +#define UDP_IER_RXRSM (0x1 << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ +#define UDP_IER_EXTRSM (0x1 << 10) /**< \brief (UDP_IER) */ +#define UDP_IER_SOFINT (0x1 << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ +#define UDP_IER_WAKEUP (0x1 << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ +#define UDP_IDR_EP0INT (0x1 << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ +#define UDP_IDR_EP1INT (0x1 << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ +#define UDP_IDR_EP2INT (0x1 << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ +#define UDP_IDR_EP3INT (0x1 << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ +#define UDP_IDR_EP4INT (0x1 << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ +#define UDP_IDR_EP5INT (0x1 << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ +#define UDP_IDR_EP6INT (0x1 << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ +#define UDP_IDR_EP7INT (0x1 << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ +#define UDP_IDR_RXSUSP (0x1 << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ +#define UDP_IDR_RXRSM (0x1 << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ +#define UDP_IDR_EXTRSM (0x1 << 10) /**< \brief (UDP_IDR) */ +#define UDP_IDR_SOFINT (0x1 << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ +#define UDP_IDR_WAKEUP (0x1 << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ +/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ +#define UDP_IMR_EP0INT (0x1 << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ +#define UDP_IMR_EP1INT (0x1 << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ +#define UDP_IMR_EP2INT (0x1 << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ +#define UDP_IMR_EP3INT (0x1 << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ +#define UDP_IMR_EP4INT (0x1 << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ +#define UDP_IMR_EP5INT (0x1 << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ +#define UDP_IMR_EP6INT (0x1 << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ +#define UDP_IMR_EP7INT (0x1 << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ +#define UDP_IMR_RXSUSP (0x1 << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ +#define UDP_IMR_RXRSM (0x1 << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ +#define UDP_IMR_EXTRSM (0x1 << 10) /**< \brief (UDP_IMR) */ +#define UDP_IMR_SOFINT (0x1 << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ +#define UDP_IMR_BIT12 (0x1 << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ +#define UDP_IMR_WAKEUP (0x1 << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ +/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ +#define UDP_ISR_EP0INT (0x1 << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ +#define UDP_ISR_EP1INT (0x1 << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ +#define UDP_ISR_EP2INT (0x1 << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ +#define UDP_ISR_EP3INT (0x1 << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ +#define UDP_ISR_EP4INT (0x1 << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ +#define UDP_ISR_EP5INT (0x1 << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ +#define UDP_ISR_EP6INT (0x1 << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ +#define UDP_ISR_EP7INT (0x1 << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ +#define UDP_ISR_RXSUSP (0x1 << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ +#define UDP_ISR_RXRSM (0x1 << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ +#define UDP_ISR_EXTRSM (0x1 << 10) /**< \brief (UDP_ISR) */ +#define UDP_ISR_SOFINT (0x1 << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ +#define UDP_ISR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ +#define UDP_ISR_WAKEUP (0x1 << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ +/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ +#define UDP_ICR_RXSUSP (0x1 << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ +#define UDP_ICR_RXRSM (0x1 << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ +#define UDP_ICR_EXTRSM (0x1 << 10) /**< \brief (UDP_ICR) */ +#define UDP_ICR_SOFINT (0x1 << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ +#define UDP_ICR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ +#define UDP_ICR_WAKEUP (0x1 << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ +/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ +#define UDP_RST_EP_EP0 (0x1 << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ +#define UDP_RST_EP_EP1 (0x1 << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ +#define UDP_RST_EP_EP2 (0x1 << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ +#define UDP_RST_EP_EP3 (0x1 << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ +#define UDP_RST_EP_EP4 (0x1 << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ +#define UDP_RST_EP_EP5 (0x1 << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ +#define UDP_RST_EP_EP6 (0x1 << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ +#define UDP_RST_EP_EP7 (0x1 << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ +/* -------- UDP_CSR[8] : (UDP Offset: 0x2C) Endpoint Control and Status Register (ept_num = 0) -------- */ +#define UDP_CSR_TXCOMP (0x1 << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ +#define UDP_CSR_RX_DATA_BK0 (0x1 << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ +#define UDP_CSR_RXSETUP (0x1 << 2) /**< \brief (UDP_CSR[8]) Received Setup */ +#define UDP_CSR_STALLSENTISOERROR (0x1 << 3) /**< \brief (UDP_CSR[8]) */ +#define UDP_CSR_TXPKTRDY (0x1 << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ +#define UDP_CSR_FORCESTALL (0x1 << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ +#define UDP_CSR_RX_DATA_BK1 (0x1 << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ +#define UDP_CSR_DIR (0x1 << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ +#define UDP_CSR_EPTYPE (0x7 << 8) /**< \brief (UDP_CSR[8]) Endpoint Type */ +#define UDP_CSR_EPTYPE_CTRL (0x0 << 8) /**< \brief (UDP_CSR[8]) Control */ +#define UDP_CSR_EPTYPE_ISO_OUT (0x1 << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ +#define UDP_CSR_EPTYPE_BULK_OUT (0x2 << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ +#define UDP_CSR_EPTYPE_INT_OUT (0x3 << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ +#define UDP_CSR_EPTYPE_ISO_IN (0x5 << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ +#define UDP_CSR_EPTYPE_BULK_IN (0x6 << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ +#define UDP_CSR_EPTYPE_INT_IN (0x7 << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ +#define UDP_CSR_DTGLE (0x1 << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ +#define UDP_CSR_EPEDS (0x1 << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ +#define UDP_CSR_RXBYTECNT (0x7ff << 16) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ +/* -------- UDP_FDR[8] : (UDP Offset: 0x4C) Endpoint FIFO Data Register (ept_num = 0) -------- */ +#define UDP_FDR_FIFO_DATA (0xff << 0) /**< \brief (UDP_FDR[8]) FIFO Data Value */ +/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ +#define UDP_TXVC_TXVDIS (0x1 << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ +#define UDP_TXVC_PUON (0x1 << 9) /**< \brief (UDP_TXVC) Pullup On */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Usart hardware registers */ +typedef struct { + WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ + WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ + RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + RwReg Reserved1[5]; + RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + RwReg Reserved2[1]; + RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ + RwReg Reserved3[36]; + RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ + RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ + RwReg Reserved4[4]; + RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ + RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ + RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ + RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ + RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ + RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ + RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ + RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ + RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ + WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ + RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ +} Usart; +#endif /* __ASSEMBLY__ */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ +#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ +#define US_CR_DTREN (0x1 << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1 << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ +#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ +#define US_MR_USART_MODE_NORMAL (0x0) /**< (USART) Normal*/ +#define US_MR_USART_MODE_RS485 (0x1) /**< (USART) RS485*/ +#define US_MR_USART_MODE_HWHSH (0x2) /**< (USART) Hardware Handshaking*/ +#define US_MR_USART_MODE_ISO7816_0 (0x4) /**< (USART) ISO7816 protocol: T = 0*/ +#define US_MR_USART_MODE_ISO7816_1 (0x6) /**< (USART) ISO7816 protocol: T = 1*/ +#define US_MR_USART_MODE_IRDA (0x8) /**< (USART) IrDA*/ +#define US_MR_USART_MODE_SPIM (0xE) /**< (USART) SPI Master*/ +#define US_MR_USART_MODE_SPIS (0xF) /**< (USART) SPI Slave*/ +#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS_CLOCK (0x0 << 4) /**< (USART) MCK*/ +#define US_MR_USCLKS_FDIV1 (0x1 << 4) /**< (USART) MCK/DIV(DIV=8)*/ +#define US_MR_USCLKS_SLOW (0x2 << 4) /**< (USART) Reserved*/ +#define US_MR_USCLKS_EXT (0x3 << 4) /**< (USART) SCK*/ +#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ +#define US_MR_CHRL_5_BITS (0x0 << 6) /**< (USART) Character Length: 5 bits*/ +#define US_MR_CHRL_6_BITS (0x1 << 6) /**< (USART) Character Length: 6 bits*/ +#define US_MR_CHRL_7_BITS (0x2 << 6) /**< (USART) Character Length: 7 bits*/ +#define US_MR_CHRL_8_BITS (0x3 << 6) /**< (USART) Character Length: 8 bits*/ +#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ +#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR_EVEN (0x0 << 9) /**< (USART) Even Parity*/ +#define US_MR_PAR_ODD (0x1 << 9) /**< (USART) Odd Parity*/ +#define US_MR_PAR_SPACE (0x2 << 9) /**< (USART) Parity forced to 0 (Space)*/ +#define US_MR_PAR_MARK (0x3 << 9) /**< (USART) Parity forced to 1 (Mark)*/ +#define US_MR_PAR_NONE (0x4 << 9) /**< (USART) No Parity*/ +#define US_MR_PAR_MULTI_DROP (0x6 << 9) /**< (USART) Multi-drop mode*/ +#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP_1_BIT (0x0 << 12) /**< (USART) 1 stop bit*/ +#define US_MR_NBSTOP_15_BIT (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits*/ +#define US_MR_NBSTOP_2_BIT (0x2 << 12) /**< (USART) 2 stop bits*/ +#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE_NORMAL (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART.*/ +#define US_MR_CHMODE_AUTO (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/ +#define US_MR_CHMODE_LOCAL (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/ +#define US_MR_CHMODE_REMOTE (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin.*/ +#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ +#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ +#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ +#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ +#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ +#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ +#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ +#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ +#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ +#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ +#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_RIIC (0x1 << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1 << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1 << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ +#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ +#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ +#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ +#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ +#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ +#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_RIIC (0x1 << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1 << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1 << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ +#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ +#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ +#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ +#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ +#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_RIIC (0x1 << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1 << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1 << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ +#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ +#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ +#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ +#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ +#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ +#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ +#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ +#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ +#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ +#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ +#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ +#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ +#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ +#define US_CSR_RIIC (0x1 << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ +#define US_CSR_DSRIC (0x1 << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ +#define US_CSR_DCDIC (0x1 << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ +#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ +#define US_CSR_RI (0x1 << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1 << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1 << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ +/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ +#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ +#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ +#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ +#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ +/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ +#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ +#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ +/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ +#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ +#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ +/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ +#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ +#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ +/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ +#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ +/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ +#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ +/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ +#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ +/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ +#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ +/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ +#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ +/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ +#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ +/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ +/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ +/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ +#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ +#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ +#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ +#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ +/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ +#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ +#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_WDT Watchdog Timer */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Wdt hardware registers */ +typedef struct { + WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* __ASSEMBLY__ */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ +#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ +#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ + +/*@}*/ + +/*@}*/ + +/* ***************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_reg Registers Access Definitions */ +/*@{*/ + +/* ========== Register definition for HSMCI peripheral ========== */ +#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ +#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ +#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ +#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ +#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ +#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ +#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ +#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ +#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ +#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ +#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ +#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ +#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ +#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ +#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ +#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ +#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ +#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ +#define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ +#define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ +#define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ +#define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ +#define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ +#define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ +#define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ +#define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ +#define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ +#define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ +#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ +#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ +#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ +#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ +#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ +#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ +#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ +#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ +#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ +#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ +#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ +#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ +#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ +#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ +#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ +#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ +#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ +#define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */ +#define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */ +#define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ +#define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ +#define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ +#define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ +#define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ +#define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ +#define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */ +#define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */ +/* ========== Register definition for SPI peripheral ========== */ +#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ +#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ +#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ +#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ +#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ +#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ +#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ +#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ +#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ +#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ +#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ +#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */ +#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */ +#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ +#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ +#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ +#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ +#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ +#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ +#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */ +#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */ +#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ +#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ +#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ +#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ +#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */ +#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ +#define REG_TC0_VER REG_ACCESS(RoReg, 0x400100FCU) /**< \brief (TC0) Version Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */ +#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ +#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ +#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ +#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ +#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */ +#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ +#define REG_TC1_VER REG_ACCESS(RoReg, 0x400140FCU) /**< \brief (TC1) Version Register */ +/* ========== Register definition for TWI0 peripheral ========== */ +#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ +#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */ +#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ +#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ +#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ +#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ +#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ +#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ +#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */ +#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */ +/* ========== Register definition for TWI1 peripheral ========== */ +#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ +#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ +#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ +#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ +#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ +#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ +#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ +#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ +#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ +#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ +/* ========== Register definition for PWM peripheral ========== */ +#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ +#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ +#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ +#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */ +#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */ +#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ +#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ +#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */ +#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */ +#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ +#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ +#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */ +#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */ +#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +/* ========== Register definition for USART0 peripheral ========== */ +#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ +#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */ +#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */ +#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */ +#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ +#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ +#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ +#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ +#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ +#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ +#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */ +#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */ +/* ========== Register definition for USART1 peripheral ========== */ +#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ +#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */ +#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */ +#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */ +#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ +#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ +#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ +#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ +#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ +#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ +#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */ +#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */ +#define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */ +#define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */ +#define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ +#define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ +#define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ +#define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ +#define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ +#define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ +#define REG_UDP_CSR REG_ACCESS(RwReg, 0x4003402CU) /**< \brief (UDP) Endpoint Control and Status Register (ept_num = 0) */ +#define REG_UDP_FDR REG_ACCESS(RwReg, 0x4003404CU) /**< \brief (UDP) Endpoint FIFO Data Register (ept_num = 0) */ +#define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQ1R REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence 1Register */ +#define REG_ADC_SEQ2R REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence 2 Register */ +#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */ +#define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR0 REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register 0 */ +#define REG_ADC_CDR1 REG_ACCESS(RoReg, 0x40038054U) /**< \brief (ADC) Channel Data Register 1 */ +#define REG_ADC_CDR2 REG_ACCESS(RoReg, 0x40038058U) /**< \brief (ADC) Channel Data Register 2 */ +#define REG_ADC_CDR3 REG_ACCESS(RoReg, 0x4003805CU) /**< \brief (ADC) Channel Data Register 3 */ +#define REG_ADC_CDR4 REG_ACCESS(RoReg, 0x40038060U) /**< \brief (ADC) Channel Data Register 4 */ +#define REG_ADC_CDR5 REG_ACCESS(RoReg, 0x40038064U) /**< \brief (ADC) Channel Data Register 5 */ +#define REG_ADC_CDR6 REG_ACCESS(RoReg, 0x40038068U) /**< \brief (ADC) Channel Data Register 6 */ +#define REG_ADC_CDR15 REG_ACCESS(RoReg, 0x4003806CU) /**< \brief (ADC) Channel Data Register 15 */ +#define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */ +#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ +#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ +#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */ +#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */ +#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */ +#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */ +#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ +#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ +#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */ +#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */ +#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */ +#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */ +/* ========== Register definition for DACC peripheral ========== */ +#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */ +#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */ +#define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */ +#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */ +#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */ +#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */ +#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ +#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ +#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ +#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ +#define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */ +#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ +#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ +#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */ +#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */ +#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ +#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ +#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */ +#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */ +#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ +#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ +#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */ +#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */ +/* ========== Register definition for ACC peripheral ========== */ +#define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */ +#define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */ +#define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ +#define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ +#define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ +#define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */ +#define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */ +#define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ +#define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ +/* ========== Register definition for CRCCU peripheral ========== */ +#define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ +#define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ +#define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ +#define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ +#define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ +#define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ +#define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ +#define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ +#define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ +#define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ +#define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ +#define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ +#define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ +#define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ +#define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ +/* ========== Register definition for SMC peripheral ========== */ +#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ +#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ +#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ +#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ +#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ +#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ +#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ +/* ========== Register definition for MATRIX peripheral ========== */ +#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System IO Configuration register */ +#define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ +#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */ +#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ +#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ +/* ========== Register definition for UART0 peripheral ========== */ +#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */ +#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */ +#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ +#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ +#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ +#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */ +#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */ +#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ +#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ +#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ +#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */ +#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ +#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ +#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ +#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ +#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ +#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ +#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */ +#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */ +/* ========== Register definition for CHIPID peripheral ========== */ +#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ +/* ========== Register definition for UART1 peripheral ========== */ +#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */ +#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */ +#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ +#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ +#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ +#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */ +#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */ +#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ +#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ +#define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ +#define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */ +#define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ +#define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ +#define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ +#define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ +#define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ +#define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ +#define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */ +#define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */ +/* ========== Register definition for EFC peripheral ========== */ +#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ +#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ +#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ +#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ +#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ +#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ +#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ +#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ +#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ +#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ +#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ +#define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ +#define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ +#define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ +#define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ +#define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ +#define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ +#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ +#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ +#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ +#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ +#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ +#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ +#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ +#define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ +#define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ +#define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ +#define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ +#define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ +#define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +/* ========== Register definition for PIOC peripheral ========== */ +#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ +#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ +#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ +#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ +#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ +#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ +#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ +#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ +#define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ +#define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ +#define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ +#define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ +#define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ +#define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */ +/* ========== Register definition for SUPC peripheral ========== */ +#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ +#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ +#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ +/* ========== Register definition for RTT peripheral ========== */ +#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */ +#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */ +#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */ +#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */ +/* ========== Register definition for WDT peripheral ========== */ +#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */ +/* ========== Register definition for RTC peripheral ========== */ +#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */ +/* ========== Register definition for GPBR peripheral ========== */ +#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */ +#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */ +#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */ +#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ +/*@}*/ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ +/*@}*/ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_base Peripheral Base Address Definitions */ +/*@{*/ + +#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */ + +// indices for three pio structures +#define iPIOA 0 +#define iPIOB 1 +#define iPIOC 2 +/*@}*/ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_pio Peripheral Pio Definitions */ +/*@{*/ + +#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1 << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1 << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1 << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1 << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1 << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1 << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1 << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1 << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1 << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1 << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1 << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1 << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1 << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1 << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1 << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA31A_NPCS1 (1 << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA9B_NPCS1 (1 << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1 << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1 << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1 << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1 << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1 << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA22B_NPCS3 (1 << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA3B_NPCS3 (1 << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1 << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1 << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1 << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1 << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1 << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1 << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1 << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1 << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1 << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1 << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1 << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1 << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1 << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1 << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1 << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1 << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1 << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1 << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1 << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1 << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1 << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1 << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1 << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1 << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1 << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1 << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1 << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1 << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1 << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1 << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA13B_PWMH2 (1 << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1 << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1 << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1 << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1 << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA7B_PWMH3 (1 << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1 << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1 << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1 << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1 << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1 << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1 << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1 << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1 << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1 << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1 << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1 << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1 << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1 << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1 << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1 << 22) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1 << 3) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1 << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1 << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1 << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1 << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1 << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1 << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1 << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1 << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1 << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1 << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1 << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1 << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1 << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1 << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1 << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1 << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1 << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1 << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1 << 19) /**< \brief Adc signal: AD2 */ +#define PIO_PA20X1_AD3 (1 << 20) /**< \brief Adc signal: AD3 */ +#define PIO_PB0X1_AD4 (1 << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1 << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1 << 2) /**< \brief Adc signal: AD6 */ +#define PIO_PB3X1_AD7 (1 << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1 << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1 << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1 << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1 << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1 << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1 << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1 << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1 << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1 << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1 << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1 << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1 << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1 << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1 << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1 << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1 << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1 << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24X1_PIODC0 (1 << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25X1_PIODC1 (1 << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26X1_PIODC2 (1 << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27X1_PIODC3 (1 << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28X1_PIODC4 (1 << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29X1_PIODC5 (1 << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30X1_PIODC6 (1 << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31X1_PIODC7 (1 << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23X1_PIODCCLK (1 << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15X1_PIODCEN1 (1 << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16X1_PIODCEN2 (1 << 16) /**< \brief Pioa signal: PIODCEN2 */ +/*@}*/ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ + +#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ +#define AT91C_IFLASH (0x00400000) /**< Internal Flash base address */ +#define AT91C_IROM (0x00800000) /**< Internal ROM base address */ +#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ +#define AT91C_EBI_CS0 (0x60000000) /**< EBI Chip Select 0 base address */ +#define AT91C_EBI_CS1 (0x61000000) /**< EBI Chip Select 1 base address */ +#define AT91C_EBI_CS2 (0x62000000) /**< EBI Chip Select 2 base address */ +#define AT91C_EBI_CS3 (0x63000000) /**< EBI Chip Select 3 base address */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + #endif // _AT91SAM3S2_H_ diff --git a/radio/src/targets/sky9x/AT91SAM3S4.h b/radio/src/targets/sky9x/AT91SAM3S4.h index 5f13e995c..010a02629 100644 --- a/radio/src/targets/sky9x/AT91SAM3S4.h +++ b/radio/src/targets/sky9x/AT91SAM3S4.h @@ -18,5328 +18,5328 @@ * GNU General Public License for more details. */ -/* Atmel Microcontroller Software Support */ -/* ---------------------------------------------------------------------------- */ -/* Copyright (c) 2009, Atmel Corporation */ -/* */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following condition is met: */ -/* */ -/* - Redistributions of source code must retain the above copyright notice, */ -/* this list of conditions and the disclaimer below. */ -/* */ -/* Atmel's name may not be used to endorse or promote products derived from */ -/* this software without specific prior written permission. */ -/* */ -/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ -/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ -/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ -/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ -/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ -/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ -/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ -/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ---------------------------------------------------------------------------- */ -/* */ -/* File Name : AT91SAM3S.h */ -/* Object : AT91SAM3S definitions */ -/* Generated by : AT91 SW Application Group */ -/* Generated on : 2009-10-26 */ - +/* Atmel Microcontroller Software Support */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2009, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* */ +/* File Name : AT91SAM3S.h */ +/* Object : AT91SAM3S definitions */ +/* Generated by : AT91 SW Application Group */ +/* Generated on : 2009-10-26 */ + #ifndef _AT91SAM3S4_H_ #define _AT91SAM3S4_H_ - -/** \addtogroup AT91SAM3S_definitions AT91SAM3S definitions - This file defines all structures and symbols for AT91SAM3S: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *) value) -#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ***************************************************************************** */ -/* CMSIS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_cmsis CMSIS Definitions */ - -/*@{*/ - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 0 /**< AT91SAM3S does not provide a MPU present or not */ -#define __NVIC_PRIO_BITS 4 /**< AT91SAM3S uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** AT91SAM3S specific Interrupt Numbers *****************************************/ - - SUPC_IRQn = 0, /**< 0 AT91SAM3S Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 AT91SAM3S Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 AT91SAM3S Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 AT91SAM3S Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 AT91SAM3S Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 AT91SAM3S Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 AT91SAM3S Enhanced Flash Controller (EFC) */ - UART0_IRQn = 8, /**< 8 AT91SAM3S UART 0 (UART0) */ - UART1_IRQn = 9, /**< 9 AT91SAM3S UART 1 (UART1) */ - SMC_IRQn = 10, /**< 10 AT91SAM3S Static Memory Controller (SMC) */ - PIOA_IRQn = 11, /**< 11 AT91SAM3S Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 AT91SAM3S Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 AT91SAM3S Parallel I/O Controller C (PIOC) */ - USART0_IRQn = 14, /**< 14 AT91SAM3S USART 0 (USART0) */ - USART1_IRQn = 15, /**< 15 AT91SAM3S USART 1 (USART1) */ - HSMCI_IRQn = 18, /**< 18 AT91SAM3S Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 19, /**< 19 AT91SAM3S Two Wire Interface 0 (TWI0) */ - TWI1_IRQn = 20, /**< 20 AT91SAM3S Two Wire Interface 1 (TWI1) */ - SPI_IRQn = 21, /**< 21 AT91SAM3S Serial Peripheral Interface (SPI) */ - SSC_IRQn = 22, /**< 22 AT91SAM3S Synchronous Serial Controler (SSC) */ - TC0_IRQn = 23, /**< 23 AT91SAM3S Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 AT91SAM3S Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 AT91SAM3S Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 AT91SAM3S Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 AT91SAM3S Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 AT91SAM3S Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 AT91SAM3S Analog To Digital Converter (ADC) */ - DACC_IRQn = 30, /**< 30 AT91SAM3S Digital To Analog Converter (DACC) */ - PWM_IRQn = 31, /**< 31 AT91SAM3S Pulse Width Modulation (PWM) */ - CRCCU_IRQn = 32, /**< 32 AT91SAM3S CRC Calculation Unit (CRCCU) */ - ACC_IRQn = 33, /**< 33 AT91SAM3S Analog Comparator (ACC) */ - UDP_IRQn = 34 /**< 34 AT91SAM3S USB Device Port (UDP) */ -} IRQn_Type; -/*@}*/ - -/* ***************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_api Peripheral Software API */ -/*@{*/ -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ACC Analog Comparator Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Acc hardware registers */ -typedef struct { - WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ - RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ - RwReg Reserved1[7]; - WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ - WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ - RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ - RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[24]; - RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ - RwReg Reserved3[19]; - RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ - RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ -} Acc; -#endif /* __ASSEMBLY__ */ -/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ -#define ACC_CR_SWRST (0x1 << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ -/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ -#define ACC_MR_SELPLUS (0x7 << 0) /**< \brief (ACC_MR) SELection for PLUS comparator input */ -#define ACC_MR_SELMINUS (0x7 << 4) /**< \brief (ACC_MR) SELection for MINUS comparator input */ -#define ACC_MR_ACEN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_EN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_DIS (0x0 << 8) /**< \brief (ACC_MR) Analog Comparator Disable */ -#define ACC_MR_EDGETYP (0x3 << 9) /**< \brief (ACC_MR) EDGE TYPe */ -#define ACC_MR_EDGETYP_RISING (0x0 << 9) /**< \brief (ACC_MR) EDGE TYPe ,RISING edge*/ -#define ACC_MR_EDGETYP_FALLING (0x1 << 9) /**< \brief (ACC_MR) EDGE TYPe,falling edge */ -#define ACC_MR_EDGETYP_ANY (0x2 << 9) /**< \brief (ACC_MR) EDGE TYPe,any edge */ -#define ACC_MR_INV (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_EN (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_DIS (0x0 << 12) /**< \brief (ACC_MR) DIRECTLY */ -#define ACC_MR_SELFS (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_CF (0x0 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_OUTPUT (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_FE (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_EN (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_DIS (0x0 << 14) /**< \brief (ACC_MR) Fault Enable */ -/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ -#define ACC_IER_CE (0x1 << 0) /**< \brief (ACC_IER) Comparison Edge */ -/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ -#define ACC_IDR_CE (0x1 << 0) /**< \brief (ACC_IDR) Comparison Edge */ -/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ACC_IMR_CE (0x1 << 0) /**< \brief (ACC_IMR) Comparison Edge */ -/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ -#define ACC_ISR_CE (0x1 << 0) /**< \brief (ACC_ISR) Comparison Edge */ -#define ACC_ISR_SCO (0x1 << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ -#define ACC_ISR_MASK (0x1 << 31) /**< \brief (ACC_ISR) */ -/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ -#define ACC_ACR_ISEL (0x1 << 0) /**< \brief (ACC_ACR) Current SELection */ -#define ACC_ACR_HYST (0x3 << 1) /**< \brief (ACC_ACR) HYSTeresis selection */ -/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ACC_WPMR_WPEN (0x1 << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ -#define ACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ACC_WPMR) Write Protect KEY */ -/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ -#define ACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ADC Analog-to-digital Converter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Adc hardware registers */ -typedef struct { - WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ - RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ - RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence 1Register */ - RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence 2 Register */ - WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ - WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ - RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ - RwReg Reserved1[1]; - RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ - WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ - WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ - RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ - RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[2]; - RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ - RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ - RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ - RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ - RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ - RoReg ADC_CDR0; /**< \brief (Adc Offset: 0x50) Channel Data Register 0 */ - RoReg ADC_CDR1; /**< \brief (Adc Offset: 0x54) Channel Data Register 1 */ - RoReg ADC_CDR2; /**< \brief (Adc Offset: 0x58) Channel Data Register 2 */ - RoReg ADC_CDR3; /**< \brief (Adc Offset: 0x5C) Channel Data Register 3 */ - RoReg ADC_CDR4; /**< \brief (Adc Offset: 0x60) Channel Data Register 4 */ - RoReg ADC_CDR5; /**< \brief (Adc Offset: 0x64) Channel Data Register 5 */ - RoReg ADC_CDR6; /**< \brief (Adc Offset: 0x68) Channel Data Register 6 */ - RoReg ADC_CDR7; /**< \brief (Adc Offset: 0x6C) Channel Data Register 7 */ - RoReg ADC_CDR8; /**< \brief (Adc Offset: 0x70) Channel Data Register 8 */ - RoReg ADC_CDR9; /**< \brief (Adc Offset: 0x74) Channel Data Register 9 */ - RoReg ADC_CDR10; /**< \brief (Adc Offset: 0x78) Channel Data Register 10 */ - RoReg ADC_CDR11; /**< \brief (Adc Offset: 0x7C) Channel Data Register 11 */ - RoReg ADC_CDR12; /**< \brief (Adc Offset: 0x80) Channel Data Register 12 */ - RoReg ADC_CDR13; /**< \brief (Adc Offset: 0x84) Channel Data Register 13 */ - RoReg ADC_CDR14; /**< \brief (Adc Offset: 0x88) Channel Data Register 14 */ - RoReg ADC_CDR15; /**< \brief (Adc Offset: 0x8C) Channel Data Register 15 */ - RwReg Reserved3[1]; - RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ - RwReg Reserved4[19]; - RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ - RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ - RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ - RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */ - RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */ - RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ - RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ - RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */ - RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */ - WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ - RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ -} Adc; -#endif /* __ASSEMBLY__ */ -/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ -#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ -#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ -/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ -#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ -#define ADC_MR_TRGEN_DIS (0x0 << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.*/ -#define ADC_MR_TRGEN_EN (0x1) /**< (ADC) Hardware trigger selected by TRGSEL field is enabled.*/ -#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ -#define ADC_MR_TRGSEL_EXT (0x0 << 1) /**< \brief (ADC_MR) Selected TRGSEL = External Trigger*/ -#define ADC_MR_TRGSEL_TIOA0 (0x1 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO0*/ -#define ADC_MR_TRGSEL_TIOA1 (0x2 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO1*/ -#define ADC_MR_TRGSEL_TIOA2 (0x3 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO2*/ -#define ADC_MR_TRGSEL_PWM0_TRIG (0x4 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM trigger*/ -#define ADC_MR_TRGSEL_PWM1_TRIG (0x5 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM Trigger*/ -#define ADC_MR_TRGSEL_RESERVED (0x6 << 1) /**< \brief (ADC_MR) Selected TRGSEL = Reserved*/ -#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ -#define ADC_MR_LOWRES_12_BIT (0x0 << 4) /**< \brief (ADC_MR) 12-bit resolution*/ -#define ADC_MR_LOWRES_10_BIT (0x1 << 4) /**< \brief (ADC_MR) 10-bit resolution*/ -#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ -#define ADC_MR_SLEEP_NORMAL (0x0 << 5) /**< \brief (ADC12B) Normal Mode*/ -#define ADC_MR_FWUP (0x1 << 6) /**< \brief (ADC_MR) Fast Wake Up */ -#define ADC_MR_FREERUN (0x1 << 7) /**< \brief (ADC_MR) Free Run Mode */ -#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ -#define ADC_MR_STARTUP (0xf << 16) /**< \brief (ADC_MR) Start Up Time */ -#define ADC_MR_SETTLING (0x3 << 20) /**< \brief (ADC_MR) Analog Settling Time */ -#define ADC_MR_ANACH (0x1 << 23) /**< \brief (ADC_MR) Analog Change */ -#define ADC_MR_TRACKTIM (0xf << 24) /**< \brief (ADC_MR) Tracking Time */ -#define ADC_MR_TRANSFER (0x3 << 28) /**< \brief (ADC_MR) */ -#define ADC_MR_USEQ (0x1 << 31) /**< \brief (ADC_MR) User Sequence Enable */ -/* -------- ADC_SEQ1R : (ADC Offset: 0x08) Channel Sequence 1Register -------- */ -#define ADC_SEQ1R_USCH1 (0x7 << 0) /**< \brief (ADC_SEQ1R) User Sequence Number 1 */ -#define ADC_SEQ1R_USCH2 (0x7 << 4) /**< \brief (ADC_SEQ1R) User Sequence Number 2 */ -#define ADC_SEQ1R_USCH3 (0x7 << 8) /**< \brief (ADC_SEQ1R) User Sequence Number 3 */ -#define ADC_SEQ1R_USCH4 (0x7 << 12) /**< \brief (ADC_SEQ1R) User Sequence Number 4 */ -#define ADC_SEQ1R_USCH5 (0x7 << 16) /**< \brief (ADC_SEQ1R) User Sequence Number 5 */ -#define ADC_SEQ1R_USCH6 (0x7 << 20) /**< \brief (ADC_SEQ1R) User Sequence Number 6 */ -#define ADC_SEQ1R_USCH7 (0x7 << 24) /**< \brief (ADC_SEQ1R) User Sequence Number 7 */ -#define ADC_SEQ1R_USCH8 (0x7 << 28) /**< \brief (ADC_SEQ1R) User Sequence Number 8 */ -/* -------- ADC_SEQ2R : (ADC Offset: 0x0C) Channel Sequence 2 Register -------- */ -#define ADC_SEQ2R_USCH9 (0x7 << 0) /**< \brief (ADC_SEQ2R) User Sequence Number 9 */ -#define ADC_SEQ2R_USCH10 (0x7 << 4) /**< \brief (ADC_SEQ2R) User Sequence Number 10 */ -#define ADC_SEQ2R_USCH11 (0x7 << 8) /**< \brief (ADC_SEQ2R) User Sequence Number 11 */ -#define ADC_SEQ2R_USCH12 (0x7 << 12) /**< \brief (ADC_SEQ2R) User Sequence Number 12 */ -#define ADC_SEQ2R_USCH13 (0x7 << 16) /**< \brief (ADC_SEQ2R) User Sequence Number 13 */ -#define ADC_SEQ2R_USCH14 (0x7 << 20) /**< \brief (ADC_SEQ2R) User Sequence Number 14 */ -#define ADC_SEQ2R_USCH15 (0x7 << 24) /**< \brief (ADC_SEQ2R) User Sequence Number 15 */ -#define ADC_SEQ2R_USCH16 (0x7 << 28) /**< \brief (ADC_SEQ2R) User Sequence Number 16 */ -/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ -#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ -#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ -#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ -#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ -#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ -#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ -#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ -#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ -#define ADC_CHER_CH8 (0x1 << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ -#define ADC_CHER_CH9 (0x1 << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ -#define ADC_CHER_CH10 (0x1 << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ -#define ADC_CHER_CH11 (0x1 << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ -#define ADC_CHER_CH12 (0x1 << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ -#define ADC_CHER_CH13 (0x1 << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ -#define ADC_CHER_CH14 (0x1 << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ -#define ADC_CHER_CH15 (0x1 << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ -/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ -#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ -#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ -#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ -#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ -#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ -#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ -#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ -#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ -#define ADC_CHDR_CH8 (0x1 << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ -#define ADC_CHDR_CH9 (0x1 << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ -#define ADC_CHDR_CH10 (0x1 << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ -#define ADC_CHDR_CH11 (0x1 << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ -#define ADC_CHDR_CH12 (0x1 << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ -#define ADC_CHDR_CH13 (0x1 << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ -#define ADC_CHDR_CH14 (0x1 << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ -#define ADC_CHDR_CH15 (0x1 << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ -/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ -#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ -#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ -#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ -#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ -#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ -#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ -#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ -#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ -#define ADC_CHSR_CH8 (0x1 << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ -#define ADC_CHSR_CH9 (0x1 << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ -#define ADC_CHSR_CH10 (0x1 << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ -#define ADC_CHSR_CH11 (0x1 << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ -#define ADC_CHSR_CH12 (0x1 << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ -#define ADC_CHSR_CH13 (0x1 << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ -#define ADC_CHSR_CH14 (0x1 << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ -#define ADC_CHSR_CH15 (0x1 << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ -/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ -#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ -#define ADC_LCDR_CHNB (0xf << 12) /**< \brief (ADC_LCDR) Channel Number */ -/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ -#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ -#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ -#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ -#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ -#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ -#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ -#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ -#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ -#define ADC_IER_EOC8 (0x1 << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ -#define ADC_IER_EOC9 (0x1 << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ -#define ADC_IER_EOC10 (0x1 << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ -#define ADC_IER_EOC11 (0x1 << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ -#define ADC_IER_EOC12 (0x1 << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ -#define ADC_IER_EOC13 (0x1 << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ -#define ADC_IER_EOC14 (0x1 << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ -#define ADC_IER_EOC15 (0x1 << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ -#define ADC_IER_DRDY (0x1 << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ -#define ADC_IER_GOVRE (0x1 << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ -#define ADC_IER_COMPE (0x1 << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ -#define ADC_IER_ENDRX (0x1 << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ -#define ADC_IER_RXBUFF (0x1 << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ -/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ -#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ -#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ -#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ -#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ -#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ -#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ -#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ -#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ -#define ADC_IDR_EOC8 (0x1 << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ -#define ADC_IDR_EOC9 (0x1 << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ -#define ADC_IDR_EOC10 (0x1 << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ -#define ADC_IDR_EOC11 (0x1 << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ -#define ADC_IDR_EOC12 (0x1 << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ -#define ADC_IDR_EOC13 (0x1 << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ -#define ADC_IDR_EOC14 (0x1 << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ -#define ADC_IDR_EOC15 (0x1 << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ -#define ADC_IDR_DRDY (0x1 << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ -#define ADC_IDR_GOVRE (0x1 << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ -#define ADC_IDR_COMPE (0x1 << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ -#define ADC_IDR_ENDRX (0x1 << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ -#define ADC_IDR_RXBUFF (0x1 << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ -/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ -#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ -#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ -#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ -#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ -#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ -#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ -#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ -#define ADC_IMR_EOC8 (0x1 << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ -#define ADC_IMR_EOC9 (0x1 << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ -#define ADC_IMR_EOC10 (0x1 << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ -#define ADC_IMR_EOC11 (0x1 << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ -#define ADC_IMR_EOC12 (0x1 << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ -#define ADC_IMR_EOC13 (0x1 << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ -#define ADC_IMR_EOC14 (0x1 << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ -#define ADC_IMR_EOC15 (0x1 << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ -#define ADC_IMR_DRDY (0x1 << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ -#define ADC_IMR_GOVRE (0x1 << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ -#define ADC_IMR_COMPE (0x1 << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ -#define ADC_IMR_ENDRX (0x1 << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ -#define ADC_IMR_RXBUFF (0x1 << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ -/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ -#define ADC_ISR_EOC0 (0x1 << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ -#define ADC_ISR_EOC1 (0x1 << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ -#define ADC_ISR_EOC2 (0x1 << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ -#define ADC_ISR_EOC3 (0x1 << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ -#define ADC_ISR_EOC4 (0x1 << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ -#define ADC_ISR_EOC5 (0x1 << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ -#define ADC_ISR_EOC6 (0x1 << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ -#define ADC_ISR_EOC7 (0x1 << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ -#define ADC_ISR_EOC8 (0x1 << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ -#define ADC_ISR_EOC9 (0x1 << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ -#define ADC_ISR_EOC10 (0x1 << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ -#define ADC_ISR_EOC11 (0x1 << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ -#define ADC_ISR_EOC12 (0x1 << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ -#define ADC_ISR_EOC13 (0x1 << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ -#define ADC_ISR_EOC14 (0x1 << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ -#define ADC_ISR_EOC15 (0x1 << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ -#define ADC_ISR_DRDY (0x1 << 24) /**< \brief (ADC_ISR) Data Ready */ -#define ADC_ISR_GOVRE (0x1 << 25) /**< \brief (ADC_ISR) General Overrun Error */ -#define ADC_ISR_COMPE (0x1 << 26) /**< \brief (ADC_ISR) Comparison Error */ -#define ADC_ISR_ENDRX (0x1 << 27) /**< \brief (ADC_ISR) End of RX Buffer */ -#define ADC_ISR_RXBUFF (0x1 << 28) /**< \brief (ADC_ISR) RX Buffer Full */ -/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ -#define ADC_OVER_OVRE0 (0x1 << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ -#define ADC_OVER_OVRE1 (0x1 << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ -#define ADC_OVER_OVRE2 (0x1 << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ -#define ADC_OVER_OVRE3 (0x1 << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ -#define ADC_OVER_OVRE4 (0x1 << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ -#define ADC_OVER_OVRE5 (0x1 << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ -#define ADC_OVER_OVRE6 (0x1 << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ -#define ADC_OVER_OVRE7 (0x1 << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ -#define ADC_OVER_OVRE8 (0x1 << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ -#define ADC_OVER_OVRE9 (0x1 << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ -#define ADC_OVER_OVRE10 (0x1 << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ -#define ADC_OVER_OVRE11 (0x1 << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ -#define ADC_OVER_OVRE12 (0x1 << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ -#define ADC_OVER_OVRE13 (0x1 << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ -#define ADC_OVER_OVRE14 (0x1 << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ -#define ADC_OVER_OVRE15 (0x1 << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ -/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ -#define ADC_EMR_CMPMODE (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode */ -#define ADC_EMR_CMPMODE_LOW (0x0 << 0) /**< \brief (ADC_EMR) Comparison Mode,lower than low threshold */ -#define ADC_EMR_CMPMODE_HIGH (0x1 << 0) /**< \brief (ADC_EMR) Comparison Mode,higher than high threshold */ -#define ADC_EMR_CMPMODE_IN (0x2 << 0) /**< \brief (ADC_EMR) Comparison Mode, in the comparison window */ -#define ADC_EMR_CMPMODE_OUT (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode, out of the comparison window */ -#define ADC_EMR_CMPSEL (0xf << 4) /**< \brief (ADC_EMR) Comparison Selected Channel */ -#define ADC_EMR_CMPALL (0x1 << 9) /**< \brief (ADC_EMR) Compare All Channels */ -#define ADC_EMR_TAG (0x1 << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ -/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ -#define ADC_CWR_LOWTHRES (0xfff << 0) /**< \brief (ADC_CWR) Low Threshold */ -#define ADC_CWR_HIGHTHRES (0xfff << 16) /**< \brief (ADC_CWR) High Threshold */ -/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ -#define ADC_CGR_GAIN0 (0x3 << 0) /**< \brief (ADC_CGR) Gain for channel 0 */ -#define ADC_CGR_GAIN1 (0x3 << 2) /**< \brief (ADC_CGR) Gain for channel 1 */ -#define ADC_CGR_GAIN2 (0x3 << 4) /**< \brief (ADC_CGR) Gain for channel 2 */ -#define ADC_CGR_GAIN3 (0x3 << 6) /**< \brief (ADC_CGR) Gain for channel 3 */ -#define ADC_CGR_GAIN4 (0x3 << 8) /**< \brief (ADC_CGR) Gain for channel 4 */ -#define ADC_CGR_GAIN5 (0x3 << 10) /**< \brief (ADC_CGR) Gain for channel 5 */ -#define ADC_CGR_GAIN6 (0x3 << 12) /**< \brief (ADC_CGR) Gain for channel 6 */ -#define ADC_CGR_GAIN7 (0x3 << 14) /**< \brief (ADC_CGR) Gain for channel 7 */ -#define ADC_CGR_GAIN8 (0x3 << 16) /**< \brief (ADC_CGR) Gain for channel 8 */ -#define ADC_CGR_GAIN9 (0x3 << 18) /**< \brief (ADC_CGR) Gain for channel 9 */ -#define ADC_CGR_GAIN10 (0x3 << 20) /**< \brief (ADC_CGR) Gain for channel 10 */ -#define ADC_CGR_GAIN11 (0x3 << 22) /**< \brief (ADC_CGR) Gain for channel 11 */ -#define ADC_CGR_GAIN12 (0x3 << 24) /**< \brief (ADC_CGR) Gain for channel 12 */ -#define ADC_CGR_GAIN13 (0x3 << 26) /**< \brief (ADC_CGR) Gain for channel 13 */ -#define ADC_CGR_GAIN14 (0x3 << 28) /**< \brief (ADC_CGR) Gain for channel 14 */ -#define ADC_CGR_GAIN15 (0x3 << 30) /**< \brief (ADC_CGR) Gain for channel 15 */ -/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ -#define ADC_COR_OFF0 (0x1 << 0) /**< \brief (ADC_COR) Offset for channel 0 */ -#define ADC_COR_OFF1 (0x1 << 1) /**< \brief (ADC_COR) Offset for channel 1 */ -#define ADC_COR_OFF2 (0x1 << 2) /**< \brief (ADC_COR) Offset for channel 2 */ -#define ADC_COR_OFF3 (0x1 << 3) /**< \brief (ADC_COR) Offset for channel 3 */ -#define ADC_COR_OFF4 (0x1 << 4) /**< \brief (ADC_COR) Offset for channel 4 */ -#define ADC_COR_OFF5 (0x1 << 5) /**< \brief (ADC_COR) Offset for channel 5 */ -#define ADC_COR_OFF6 (0x1 << 6) /**< \brief (ADC_COR) Offset for channel 6 */ -#define ADC_COR_OFF7 (0x1 << 7) /**< \brief (ADC_COR) Offset for channel 7 */ -#define ADC_COR_OFF8 (0x1 << 8) /**< \brief (ADC_COR) Offset for channel 8 */ -#define ADC_COR_OFF9 (0x1 << 9) /**< \brief (ADC_COR) Offset for channel 9 */ -#define ADC_COR_OFF10 (0x1 << 10) /**< \brief (ADC_COR) Offset for channel 10 */ -#define ADC_COR_OFF11 (0x1 << 11) /**< \brief (ADC_COR) Offset for channel 11 */ -#define ADC_COR_OFF12 (0x1 << 12) /**< \brief (ADC_COR) Offset for channel 12 */ -#define ADC_COR_OFF13 (0x1 << 13) /**< \brief (ADC_COR) Offset for channel 13 */ -#define ADC_COR_OFF14 (0x1 << 14) /**< \brief (ADC_COR) Offset for channel 14 */ -#define ADC_COR_OFF15 (0x1 << 15) /**< \brief (ADC_COR) Offset for channel 15 */ -#define ADC_COR_DIFF0 (0x1 << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ -#define ADC_COR_DIFF1 (0x1 << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ -#define ADC_COR_DIFF2 (0x1 << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ -#define ADC_COR_DIFF3 (0x1 << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ -#define ADC_COR_DIFF4 (0x1 << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ -#define ADC_COR_DIFF5 (0x1 << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ -#define ADC_COR_DIFF6 (0x1 << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ -#define ADC_COR_DIFF7 (0x1 << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ -#define ADC_COR_DIFF8 (0x1 << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ -#define ADC_COR_DIFF9 (0x1 << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ -#define ADC_COR_DIFF10 (0x1 << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ -#define ADC_COR_DIFF11 (0x1 << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ -#define ADC_COR_DIFF12 (0x1 << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ -#define ADC_COR_DIFF13 (0x1 << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ -#define ADC_COR_DIFF14 (0x1 << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ -#define ADC_COR_DIFF15 (0x1 << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ -/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */ -#define ADC_CDR0_DATA (0x3ff << 0) /**< \brief (ADC_CDR0) Converted Data */ -/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */ -#define ADC_CDR1_DATA (0x3ff << 0) /**< \brief (ADC_CDR1) Converted Data */ -/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */ -#define ADC_CDR2_DATA (0x3ff << 0) /**< \brief (ADC_CDR2) Converted Data */ -/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */ -#define ADC_CDR3_DATA (0x3ff << 0) /**< \brief (ADC_CDR3) Converted Data */ -/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */ -#define ADC_CDR4_DATA (0x3ff << 0) /**< \brief (ADC_CDR4) Converted Data */ -/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */ -#define ADC_CDR5_DATA (0x3ff << 0) /**< \brief (ADC_CDR5) Converted Data */ -/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */ -#define ADC_CDR6_DATA (0x3ff << 0) /**< \brief (ADC_CDR6) Converted Data */ -/* -------- ADC_CDR15 : (ADC Offset: 0x6C) Channel Data Register 15 -------- */ -#define ADC_CDR15_DATA (0x3ff << 0) /**< \brief (ADC_CDR15) Converted Data */ -/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ -#define ADC_ACR_TSON (0x1 << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ -#define ADC_ACR_IBCTL (0x3 << 8) /**< \brief (ADC_ACR) ADC Bias Current Control */ -/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ADC_WPMR_WPEN (0x1 << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ -#define ADC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ADC_WPMR) Write Protect KEY */ -/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ -#define ADC_WPSR_WPVS (0x1 << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ -#define ADC_WPSR_WPVSRC (0xffff << 8) /**< \brief (ADC_WPSR) Write Protect Violation Source */ -/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ -#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ -/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ -#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ -/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ -#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ -/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ -#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ -/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ -#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ -/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ -#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ -/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ -/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ -/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ -#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ -#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ -#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ -#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ -/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ -#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ -#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Chip Identifier */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CHIPID Chip Identifier */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Chipid hardware registers */ -typedef struct { - RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ - RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ -} Chipid; -#endif /* __ASSEMBLY__ */ -/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ -#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ -#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ -#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ -#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ -#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ -#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ -/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ -#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Crccu hardware registers */ -typedef struct { - RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ - RwReg Reserved1[1]; - WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ - WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ - RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ - WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ - WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ - RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ - RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ - RwReg Reserved2[4]; - WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ - RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ - RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ - WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ - WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ - RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ - RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ -} Crccu; -#endif /* __ASSEMBLY__ */ -/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ -#define CRCCU_DSCR_DSCR (0x7fffff << 9) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ -/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ -#define CRCCU_DMA_EN_DMAEN (0x1 << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ -/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ -#define CRCCU_DMA_DIS_DMADIS (0x1 << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ -/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ -#define CRCCU_DMA_SR_DMASR (0x1 << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ -/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ -#define CRCCU_DMA_IER_DMAIER (0x1 << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ -/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ -#define CRCCU_DMA_IDR_DMAIDR (0x1 << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ -/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ -#define CRCCU_DMA_IMR_DMAIMR (0x1 << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ -/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ -#define CRCCU_DMA_ISR_DMAISR (0x1 << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ -/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ -#define CRCCU_CR_RESET (0x1 << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ -/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ -#define CRCCU_MR_ENABLE (0x1 << 0) /**< \brief (CRCCU_MR) CRC Enable */ -#define CRCCU_MR_COMPARE (0x1 << 1) /**< \brief (CRCCU_MR) CRC Compare */ -#define CRCCU_MR_PTYPE (0x3 << 2) /**< \brief (CRCCU_MR) Primitive Polynomial */ -#define CRCCU_MR_PTYPE_CCIT8023 (0x0 << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ -#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1 << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ -#define CRCCU_MR_PTYPE_CCIT16 (0x2 << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ -#define CRCCU_MR_DIVIDER (0xf << 4) /**< \brief (CRCCU_MR) Request Divider */ -/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ -#define CRCCU_SR_CRC (0xffffffff << 0) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ -/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ -#define CRCCU_IER_ERRIER (0x1 << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ -/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ -#define CRCCU_IDR_ERRIDR (0x1 << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ -/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ -#define CRCCU_IMR_ERRIMR (0x1 << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ -/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ -#define CRCCU_ISR_ERRISR (0x1 << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_DACC Digital-to-Analog Converter Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Dacc hardware registers */ -typedef struct { - WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ - RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ - RwReg Reserved1[2]; - WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ - WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ - RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ - RwReg Reserved2[1]; - WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ - WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ - WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ - RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ - RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved3[24]; - RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ - RwReg Reserved4[19]; - RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ - RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ - RwReg Reserved5[5]; - RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */ - RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */ - RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ - RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ - RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */ - RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */ - RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ - RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ - WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ - RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ -} Dacc; -#endif /* __ASSEMBLY__ */ -/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ -#define DACC_CR_SWRST (0x1 << 0) /**< \brief (DACC_CR) Software Reset */ -/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ -#define DACC_MR_TRGEN (0x1 << 0) /**< \brief (DACC_MR) Trigger Enable */ -#define DACC_MR_TRGEN_DIS (0x0 << 0) // (DACC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. -#define DACC_MR_TRGEN_EN (0x1 << 0) // (DACC_MR) Hardware trigger selected by TRGSEL field is enabled. - -#define DACC_MR_TRGSEL (0x7 << 1) /**< \brief (DACC_MR) Trigger Selection */ -#define DACC_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (DACC_MR) External trigger -#define DACC_MR_TRGSEL_TIOA_0 (0x1 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 0 -#define DACC_MR_TRGSEL_TIOA_1 (0x2 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 1 -#define DACC_MR_TRGSEL_TIOA_2 (0x3 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 2 -#define DACC_MR_TRGSEL_PWM_0 (0x4 << 1) // (DACC_MR) PWM Event Line 0 -#define DACC_MR_TRGSEL_PWM_1 (0x5 << 1) // (DACC_MR) PWM Event Line 1 -#define DACC_MR_WORD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_WORD_HALF (0x0 << 4) /**< \brief (DACC_MR) Half-Word Transfer */ -#define DACC_MR_WORD_WORLD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_SLEEP (0x1 << 5) /**< \brief (DACC_MR) Sleep Mode */ -#define DACC_MR_SLEEP_NORMAL (0x0 << 5) // (DACC_MR) Normal Mode -#define DACC_MR_SLEEP_SLEEP (0x1 << 5) // (DACC_MR) Sleep Modes -#define DACC_MR_FASTWKUP (0x1 << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ -#define DACC_MR_REFRESH (0xff << 8) /**< \brief (DACC_MR) Refresh Period */ -#define DACC_MR_USER_SEL (0x3 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_0 (0x0 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_1 (0x1 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_TAG (0x1 << 20) /**< \brief (DACC_MR) Tag Selection Mode */ -#define DACC_MR_MAXS (0x1 << 21) /**< \brief (DACC_MR) Max Speed Mode */ -#define DACC_MR_STARTUP (0x3f << 24) /**< \brief (DACC_MR) Startup Time Selection */ -/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ -#define DACC_CHER_CH0 (0x1 << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ -#define DACC_CHER_CH1 (0x1 << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ -#define DACC_CHER_CH2 (0x1 << 2) /**< \brief (DACC_CHER) Channel 2 Enable */ -/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ -#define DACC_CHDR_CH0 (0x1 << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ -#define DACC_CHDR_CH1 (0x1 << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ -#define DACC_CHDR_CH2 (0x1 << 2) /**< \brief (DACC_CHDR) Channel 2 Disable */ -/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ -#define DACC_CHSR_CH0 (0x1 << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ -#define DACC_CHSR_CH1 (0x1 << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ -#define DACC_CHSR_CH2 (0x1 << 2) /**< \brief (DACC_CHSR) Channel 2 Status */ -/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ -#define DACC_CDR_DATA (0xffffffff << 0) /**< \brief (DACC_CDR) Data to Convert */ -/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ -#define DACC_IER_TXRDY (0x1 << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ -#define DACC_IER_EOC (0x1 << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ -#define DACC_IER_ENDTX (0x1 << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ -#define DACC_IER_TXBUFE (0x1 << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ -#define DACC_IDR_TXRDY (0x1 << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ -#define DACC_IDR_EOC (0x1 << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ -#define DACC_IDR_ENDTX (0x1 << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ -#define DACC_IDR_TXBUFE (0x1 << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define DACC_IMR_TXRDY (0x1 << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ -#define DACC_IMR_EOC (0x1 << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ -#define DACC_IMR_ENDTX (0x1 << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ -#define DACC_IMR_TXBUFE (0x1 << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ -#define DACC_ISR_TXRDY (0x1 << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ -#define DACC_ISR_EOC (0x1 << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ -#define DACC_ISR_ENDTX (0x1 << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ -#define DACC_ISR_TXBUFE (0x1 << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ -/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ -#define DACC_ACR_IBCTLCH0 (0x3 << 0) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLCH1 (0x3 << 2) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLDACCORE (0x3 << 8) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ -/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ -#define DACC_WPMR_WPEN (0x1 << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ -#define DACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (DACC_WPMR) Write Protect KEY */ -/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ -#define DACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (DACC_WPSR) Write protection error */ -#define DACC_WPSR_WPROTADDR (0xff << 8) /**< \brief (DACC_WPSR) Write protection error address */ -/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ -#define DACC_RPR_RXPTR (0xffffffff << 0) /**< \brief (DACC_RPR) Receive Pointer Register */ -/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ -#define DACC_RCR_RXCTR (0xffff << 0) /**< \brief (DACC_RCR) Receive Counter Register */ -/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ -#define DACC_TPR_TXPTR (0xffffffff << 0) /**< \brief (DACC_TPR) Transmit Counter Register */ -/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ -#define DACC_TCR_TXCTR (0xffff << 0) /**< \brief (DACC_TCR) Transmit Counter Register */ -/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ -#define DACC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (DACC_RNPR) Receive Next Pointer */ -/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ -#define DACC_RNCR_RXNCTR (0xffff << 0) /**< \brief (DACC_RNCR) Receive Next Counter */ -/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define DACC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (DACC_TNPR) Transmit Next Pointer */ -/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define DACC_TNCR_TXNCTR (0xffff << 0) /**< \brief (DACC_TNCR) Transmit Counter Next */ -/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ -#define DACC_PTCR_RXTEN (0x1 << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ -#define DACC_PTCR_RXTDIS (0x1 << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ -#define DACC_PTCR_TXTEN (0x1 << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ -#define DACC_PTCR_TXTDIS (0x1 << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ -/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ -#define DACC_PTSR_RXTEN (0x1 << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ -#define DACC_PTSR_TXTEN (0x1 << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_EFC Embedded Flash Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Efc hardware registers */ -typedef struct { - RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ - WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ - RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ - RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ -} Efc; -#endif /* __ASSEMBLY__ */ -/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ -#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ -#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ -#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ -/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ -#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ -#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ -#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ -/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ -#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ -#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ -/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ -#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_GPBR General Purpose Backup Register */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Gpbr hardware registers */ -typedef struct { - RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ - RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ - RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ - RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ -} Gpbr; -#endif /* __ASSEMBLY__ */ -/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ -#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ -/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ -#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ -/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ -#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ -/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ -#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_HSMCI High Speed MultiMedia Card Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Hsmci hardware registers */ -typedef struct { - WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ - RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ - RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ - RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ - RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ - WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ - RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ - RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ - RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ - RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ - WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ - RwReg Reserved1[2]; - RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ - WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ - WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ - RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved2[1]; - RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ - RwReg Reserved3[35]; - RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ - RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved4[5]; - RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ - RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ - RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ - RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ - RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ - RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ - RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ - RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ - WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ - RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ -} Hsmci; -#endif /* __ASSEMBLY__ */ -/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ -#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ -#define HSMCI_CR_MCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ -#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ -#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ -#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ -/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ -#define HSMCI_MR_CLKDIV_Pos 0 -#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ -#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) -#define HSMCI_MR_PWSDIV_Pos 8 -#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ -#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) -#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ -#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ -#define HSMCI_MR_BLKLEN_Pos 16 -#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */ -#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos))) -/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ -#define HSMCI_DTOR_DTOCYC_Pos 0 -#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ -#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) -#define HSMCI_DTOR_DTOMUL_Pos 4 -#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ -#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ -#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ -#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ -#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ -#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ -#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ -#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ -#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ -/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ -#define HSMCI_SDCR_SDCSEL_Pos 0 -#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ -#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ -#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCBUS_Pos 6 -#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ -#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ -#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ -#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ -/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ -#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ -/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ -#define HSMCI_CMDR_CMDNB_Pos 0 -#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ -#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) -#define HSMCI_CMDR_RSPTYP_Pos 6 -#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ -#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ -#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ -#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ -#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ -#define HSMCI_CMDR_SPCMD_Pos 8 -#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ -#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ -#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD:74 clock cycles for initialization sequence. */ -#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD:Wait for the end of the current data block transfer before sending the pending command. */ -#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command.The host cancels the ability for the device to return a command completion signal on the command line. */ -#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command:Corresponds to the Interrupt Mode (CMD40). */ -#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response:Corresponds to the Interrupt Mode (CMD40). */ -#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request.Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ -#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation.This command allows the host processor to terminate the boot operation mode. */ -#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ -#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ -#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ -#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ -#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ -#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ -#define HSMCI_CMDR_TRCMD_Pos 16 -#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ -#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ -#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ -#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ -#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ -#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ -#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ -#define HSMCI_CMDR_TRTYP_Pos 19 -#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ -#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */ -#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */ -#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ -#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ -#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ -#define HSMCI_CMDR_IOSPCMD_Pos 24 -#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ -#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ -#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ -#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ -#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ -#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ -#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ -#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ -/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ -#define HSMCI_BLKR_BCNT_Pos 0 -#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ -#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */ -#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */ -#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */ -#define HSMCI_BLKR_BLKLEN_Pos 16 -#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ -#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) -/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ -#define HSMCI_CSTOR_CSTOCYC_Pos 0 -#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ -#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) -#define HSMCI_CSTOR_CSTOMUL_Pos 4 -#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ -#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ -#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ -#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ -#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ -#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ -#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ -#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ -#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ -/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ -#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ -/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ -#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ -/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ -#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ -/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ -#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ -#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ -#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ -#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ -#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ -#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ -#define HSMCI_SR_ENDRX (0x1 << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ -#define HSMCI_SR_ENDTX (0x1 << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ -#define HSMCI_SR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ -#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ -#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ -#define HSMCI_SR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ -#define HSMCI_SR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ -#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ -#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ -#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ -#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ -#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ -#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ -#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ -#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ -#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ -#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ -#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ -#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ -#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ -#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ -/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ -#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ -#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ -#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ -#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ -#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ -#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ -#define HSMCI_IER_ENDRX (0x1 << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ -#define HSMCI_IER_ENDTX (0x1 << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ -#define HSMCI_IER_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ -#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ -#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ -#define HSMCI_IER_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ -#define HSMCI_IER_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ -#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ -#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ -#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ -#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ -#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ -#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ -#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ -#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ -#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ -#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ -#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ -#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ -#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ -#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ -/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ -#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ -#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ -#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ -#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ -#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ -#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ -#define HSMCI_IDR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ -#define HSMCI_IDR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ -#define HSMCI_IDR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ -#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ -#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ -#define HSMCI_IDR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ -#define HSMCI_IDR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ -#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ -#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ -#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ -#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ -#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ -#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ -#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ -#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ -#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ -#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ -#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ -#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ -#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ -/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ -#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ -#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ -#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ -#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ -#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ -#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ -#define HSMCI_IMR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ -#define HSMCI_IMR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ -#define HSMCI_IMR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ -#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ -#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ -#define HSMCI_IMR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ -#define HSMCI_IMR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ -#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ -#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ -#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ -#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ -#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ -#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ -#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ -#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ -#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ -#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ -#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ -#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ -#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ -/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ -#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ -#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ -#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ -#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ -/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ -#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ -#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ -/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ -#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ -/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ -#define HSMCI_RPR_RXPTR (0xffffffff << 0) /**< \brief (HSMCI_RPR) Receive Pointer Register */ -/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ -#define HSMCI_RCR_RXCTR (0xffff << 0) /**< \brief (HSMCI_RCR) Receive Counter Register */ -/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ -#define HSMCI_TPR_TXPTR (0xffffffff << 0) /**< \brief (HSMCI_TPR) Transmit Counter Register */ -/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ -#define HSMCI_TCR_TXCTR (0xffff << 0) /**< \brief (HSMCI_TCR) Transmit Counter Register */ -/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ -#define HSMCI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ -/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ -#define HSMCI_RNCR_RXNCTR (0xffff << 0) /**< \brief (HSMCI_RNCR) Receive Next Counter */ -/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define HSMCI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ -/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define HSMCI_TNCR_TXNCTR (0xffff << 0) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ -/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ -#define HSMCI_PTCR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ -#define HSMCI_PTCR_RXTDIS (0x1 << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ -#define HSMCI_PTCR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ -#define HSMCI_PTCR_TXTDIS (0x1 << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ -/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ -#define HSMCI_PTSR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ -#define HSMCI_PTSR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_MATRIX AHB Bus Matrix */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Matrix hardware registers */ -typedef struct { - RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ - RwReg Reserved1[12]; - RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ - RwReg Reserved2[11]; - RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ - RwReg Reserved3[1]; - RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ - RwReg Reserved4[1]; - RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ - RwReg Reserved5[1]; - RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ - RwReg Reserved6[1]; - RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ - RwReg Reserved7[28]; - RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System IO Configuration register */ - RwReg Reserved8[1]; - RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ - RwReg Reserved9[49]; - RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ - RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ -} Matrix; -#endif /* __ASSEMBLY__ */ -/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ -#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ -/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ -#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ -#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ -#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ -#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ -/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ -#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ -#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ -#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ -#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ -#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ -/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ -#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ -#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ -#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ -#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ -#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ -/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ -#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ -#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ -#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ -#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ -#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ -/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ -#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ -#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ -#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ -#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ -#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ -/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ -#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ -#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ -#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ -#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ -#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ -/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System IO Configuration register -------- */ -#define CCFG_SYSIO_SYSIO4 (0x1 << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ -#define CCFG_SYSIO_SYSIO5 (0x1 << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ -#define CCFG_SYSIO_SYSIO6 (0x1 << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ -#define CCFG_SYSIO_SYSIO7 (0x1 << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ -#define CCFG_SYSIO_SYSIO10 (0x1 << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ -#define CCFG_SYSIO_SYSIO11 (0x1 << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ -#define CCFG_SYSIO_SYSIO12 (0x1 << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ -/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ -#define CCFG_SMCNFCS_SMC_NFCS0 (0x1 << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS1 (0x1 << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS2 (0x1 << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS3 (0x1 << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ -/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ -#define MATRIX_WPMR_WPEN (0x1 << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ -#define MATRIX_WPMR_WPKEY (0xffffff << 8) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ -/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ -#define MATRIX_WPSR_WPVS (0x1 << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ -#define MATRIX_WPSR_WPVSRC (0xffff << 8) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PDC Peripheral DMA Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pdc hardware registers */ -typedef struct { - RwReg Reserved1[64]; - RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ - RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ - RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ - RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ - RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ - RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ - RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ - RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ - WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ - RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ -} Pdc; -#endif /* __ASSEMBLY__ */ -/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ -#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ -/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ -#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ -/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ -#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ -/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ -#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ -/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ -#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ -/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ -#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ -/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ -/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ -/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ -#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ -#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ -#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ -#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ -/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ -#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PIO Parallel Input/Output */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pio hardware registers */ -typedef struct { - WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ - WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ - RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ - RwReg Reserved1[1]; - WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ - WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ - RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ - RwReg Reserved2[1]; - WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ - WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ - RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ - RwReg Reserved3[1]; - WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ - WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ - RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ - RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ - WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ - WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ - RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ - RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ - WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ - WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ - RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ - RwReg Reserved4[1]; - WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ - WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ - RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ - RwReg Reserved5[1]; - RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ - RwReg Reserved6[2]; - WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ - WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ - RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ - RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ - WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ - WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ - RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ - RwReg Reserved7[1]; - WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ - WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ - RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ - RwReg Reserved8[1]; - WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ - WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ - RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ - RwReg Reserved9[1]; - WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ - WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ - RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ - RwReg Reserved10[1]; - WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ - WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ - RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ - RwReg Reserved11[1]; - RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ - RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ - RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved12[5]; - RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ - RwReg Reserved13[19]; - RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ - WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ - WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ - RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ - RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ - RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ - RwReg Reserved14[38]; -} Pio; -#endif /* __ASSEMBLY__ */ -/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ -#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ -/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ -#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ -/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ -#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ -/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ -#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ -/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ -#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ -/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ -#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ -/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ -#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ -/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ -#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ -/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ -#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ -/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ -#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ -/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ -#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ -/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ -#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ -/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ -#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ -/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ -#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ -#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ -#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ -#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ -#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ -/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ -#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ -#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ -/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ -#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ -/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ -#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ -/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ -#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ -/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ -#define PIO_ABCDSR_P0 (0x1 << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P1 (0x1 << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P2 (0x1 << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P3 (0x1 << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P4 (0x1 << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P5 (0x1 << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P6 (0x1 << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P7 (0x1 << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P8 (0x1 << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P9 (0x1 << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P10 (0x1 << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P11 (0x1 << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P12 (0x1 << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P13 (0x1 << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P14 (0x1 << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P15 (0x1 << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P16 (0x1 << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P17 (0x1 << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P18 (0x1 << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P19 (0x1 << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P20 (0x1 << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P21 (0x1 << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P22 (0x1 << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P23 (0x1 << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P24 (0x1 << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P25 (0x1 << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P26 (0x1 << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P27 (0x1 << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P28 (0x1 << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P29 (0x1 << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P30 (0x1 << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P31 (0x1 << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ -#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ -#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ -#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ -#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ -#define PIO_PPDDR_P0 (0x1 << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P1 (0x1 << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P2 (0x1 << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P3 (0x1 << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P4 (0x1 << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P5 (0x1 << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P6 (0x1 << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P7 (0x1 << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P8 (0x1 << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P9 (0x1 << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P10 (0x1 << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P11 (0x1 << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P12 (0x1 << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P13 (0x1 << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P14 (0x1 << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P15 (0x1 << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P16 (0x1 << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P17 (0x1 << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P18 (0x1 << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P19 (0x1 << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P20 (0x1 << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P21 (0x1 << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P22 (0x1 << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P23 (0x1 << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P24 (0x1 << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P25 (0x1 << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P26 (0x1 << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P27 (0x1 << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P28 (0x1 << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P29 (0x1 << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P30 (0x1 << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P31 (0x1 << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ -#define PIO_PPDER_P0 (0x1 << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P1 (0x1 << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P2 (0x1 << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P3 (0x1 << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P4 (0x1 << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P5 (0x1 << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P6 (0x1 << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P7 (0x1 << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P8 (0x1 << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P9 (0x1 << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P10 (0x1 << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P11 (0x1 << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P12 (0x1 << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P13 (0x1 << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P14 (0x1 << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P15 (0x1 << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P16 (0x1 << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P17 (0x1 << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P18 (0x1 << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P19 (0x1 << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P20 (0x1 << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P21 (0x1 << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P22 (0x1 << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P23 (0x1 << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P24 (0x1 << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P25 (0x1 << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P26 (0x1 << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P27 (0x1 << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P28 (0x1 << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P29 (0x1 << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P30 (0x1 << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P31 (0x1 << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ -/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ -#define PIO_PPDSR_P0 (0x1 << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P1 (0x1 << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P2 (0x1 << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P3 (0x1 << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P4 (0x1 << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P5 (0x1 << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P6 (0x1 << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P7 (0x1 << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P8 (0x1 << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P9 (0x1 << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P10 (0x1 << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P11 (0x1 << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P12 (0x1 << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P13 (0x1 << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P14 (0x1 << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P15 (0x1 << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P16 (0x1 << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P17 (0x1 << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P18 (0x1 << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P19 (0x1 << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P20 (0x1 << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P21 (0x1 << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P22 (0x1 << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P23 (0x1 << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P24 (0x1 << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P25 (0x1 << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P26 (0x1 << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P27 (0x1 << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P28 (0x1 << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P29 (0x1 << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P30 (0x1 << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P31 (0x1 << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ -/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ -#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ -/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ -#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ -/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ -#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ -/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ -#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ -#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ -#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ -#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ -#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ -#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ -#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ -#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ -#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ -#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ -/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ -#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ -/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ -#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ -/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ -#define PIO_SCHMITT_SCHMITT0 (0x1 << 0) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT1 (0x1 << 1) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT2 (0x1 << 2) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT3 (0x1 << 3) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT4 (0x1 << 4) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT5 (0x1 << 5) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT6 (0x1 << 6) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT7 (0x1 << 7) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT8 (0x1 << 8) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT9 (0x1 << 9) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT10 (0x1 << 10) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT11 (0x1 << 11) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT12 (0x1 << 12) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT13 (0x1 << 13) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT14 (0x1 << 14) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT15 (0x1 << 15) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT16 (0x1 << 16) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT17 (0x1 << 17) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT18 (0x1 << 18) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT19 (0x1 << 19) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT20 (0x1 << 20) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT21 (0x1 << 21) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT22 (0x1 << 22) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT23 (0x1 << 23) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT24 (0x1 << 24) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT25 (0x1 << 25) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT26 (0x1 << 26) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT27 (0x1 << 27) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT28 (0x1 << 28) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT29 (0x1 << 29) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT30 (0x1 << 30) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT31 (0x1 << 31) /**< \brief (PIO_SCHMITT) */ -/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ -#define PIO_PCMR_PCEN (0x1 << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ -#define PIO_PCMR_DSIZE (0x3 << 4) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ -#define PIO_PCMR_ALWYS (0x1 << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ -#define PIO_PCMR_HALFS (0x1 << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ -#define PIO_PCMR_FRSTS (0x1 << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ -/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ -#define PIO_PCIER_DRDY (0x1 << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ -#define PIO_PCIER_OVRE (0x1 << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ -#define PIO_PCIER_ENDRX (0x1 << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ -#define PIO_PCIER_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ -/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ -#define PIO_PCIDR_DRDY (0x1 << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ -#define PIO_PCIDR_OVRE (0x1 << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ -#define PIO_PCIDR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ -#define PIO_PCIDR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ -/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ -#define PIO_PCIMR_DRDY (0x1 << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ -#define PIO_PCIMR_OVRE (0x1 << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ -#define PIO_PCIMR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ -#define PIO_PCIMR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ -/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ -#define PIO_PCISR_DRDY (0x1 << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ -#define PIO_PCISR_OVRE (0x1 << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ -#define PIO_PCISR_ENDRX (0x1 << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ -#define PIO_PCISR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ -/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ -#define PIO_PCRHR_RDATA (0xffffffff << 0) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Power Management Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PMC Power Management Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pmc hardware registers */ -typedef struct { - WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ - WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ - RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ - RwReg Reserved1[1]; - WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ - WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ - RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ - RwReg Reserved2[1]; - RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ - RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ - RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ - RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ - RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ - RwReg Reserved3[1]; - RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ - RwReg Reserved4[1]; - RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ - RwReg Reserved5[5]; - WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ - WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ - RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ - RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ - RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ - RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ - WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ - RwReg Reserved6[26]; - RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ - RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved7[5]; - WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ - WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ - RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ - RwReg Reserved8[1]; - RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ -} Pmc; -#endif /* __ASSEMBLY__ */ -/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ -#define PMC_SCER_UDP (0x1 << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ -#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ -#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ -#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ -/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ -#define PMC_SCDR_UDP (0x1 << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ -#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ -#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ -#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ -/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ -#define PMC_SCSR_UDP (0x1 << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ -#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ -#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ -#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ -/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ -#define PMC_PCER0_PID2 (0x1 << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ -#define PMC_PCER0_PID3 (0x1 << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ -#define PMC_PCER0_PID4 (0x1 << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ -#define PMC_PCER0_PID5 (0x1 << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ -#define PMC_PCER0_PID6 (0x1 << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ -#define PMC_PCER0_PID7 (0x1 << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ -#define PMC_PCER0_PID8 (0x1 << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ -#define PMC_PCER0_PID9 (0x1 << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ -#define PMC_PCER0_PID10 (0x1 << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ -#define PMC_PCER0_PID11 (0x1 << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ -#define PMC_PCER0_PID12 (0x1 << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ -#define PMC_PCER0_PID13 (0x1 << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ -#define PMC_PCER0_PID14 (0x1 << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ -#define PMC_PCER0_PID15 (0x1 << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ -#define PMC_PCER0_PID16 (0x1 << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1 << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ -#define PMC_PCER0_PID18 (0x1 << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ -#define PMC_PCER0_PID19 (0x1 << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ -#define PMC_PCER0_PID20 (0x1 << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ -#define PMC_PCER0_PID21 (0x1 << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ -#define PMC_PCER0_PID22 (0x1 << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ -#define PMC_PCER0_PID23 (0x1 << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ -#define PMC_PCER0_PID24 (0x1 << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ -#define PMC_PCER0_PID25 (0x1 << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ -#define PMC_PCER0_PID26 (0x1 << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ -#define PMC_PCER0_PID27 (0x1 << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ -#define PMC_PCER0_PID28 (0x1 << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ -#define PMC_PCER0_PID29 (0x1 << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ -#define PMC_PCER0_PID30 (0x1 << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ -#define PMC_PCER0_PID31 (0x1 << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ -/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ -#define PMC_PCDR0_PID2 (0x1 << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ -#define PMC_PCDR0_PID3 (0x1 << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ -#define PMC_PCDR0_PID4 (0x1 << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ -#define PMC_PCDR0_PID5 (0x1 << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ -#define PMC_PCDR0_PID6 (0x1 << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ -#define PMC_PCDR0_PID7 (0x1 << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ -#define PMC_PCDR0_PID8 (0x1 << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ -#define PMC_PCDR0_PID9 (0x1 << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ -#define PMC_PCDR0_PID10 (0x1 << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ -#define PMC_PCDR0_PID11 (0x1 << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ -#define PMC_PCDR0_PID12 (0x1 << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ -#define PMC_PCDR0_PID13 (0x1 << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ -#define PMC_PCDR0_PID14 (0x1 << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ -#define PMC_PCDR0_PID15 (0x1 << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ -#define PMC_PCDR0_PID16 (0x1 << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1 << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ -#define PMC_PCDR0_PID18 (0x1 << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ -#define PMC_PCDR0_PID19 (0x1 << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ -#define PMC_PCDR0_PID20 (0x1 << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ -#define PMC_PCDR0_PID21 (0x1 << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ -#define PMC_PCDR0_PID22 (0x1 << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ -#define PMC_PCDR0_PID23 (0x1 << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ -#define PMC_PCDR0_PID24 (0x1 << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ -#define PMC_PCDR0_PID25 (0x1 << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ -#define PMC_PCDR0_PID26 (0x1 << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ -#define PMC_PCDR0_PID27 (0x1 << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ -#define PMC_PCDR0_PID28 (0x1 << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ -#define PMC_PCDR0_PID29 (0x1 << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ -#define PMC_PCDR0_PID30 (0x1 << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ -#define PMC_PCDR0_PID31 (0x1 << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ -/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ -#define PMC_PCSR0_PID2 (0x1 << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ -#define PMC_PCSR0_PID3 (0x1 << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ -#define PMC_PCSR0_PID4 (0x1 << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ -#define PMC_PCSR0_PID5 (0x1 << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ -#define PMC_PCSR0_PID6 (0x1 << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ -#define PMC_PCSR0_PID7 (0x1 << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ -#define PMC_PCSR0_PID8 (0x1 << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ -#define PMC_PCSR0_PID9 (0x1 << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ -#define PMC_PCSR0_PID10 (0x1 << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ -#define PMC_PCSR0_PID11 (0x1 << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ -#define PMC_PCSR0_PID12 (0x1 << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ -#define PMC_PCSR0_PID13 (0x1 << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ -#define PMC_PCSR0_PID14 (0x1 << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ -#define PMC_PCSR0_PID15 (0x1 << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ -#define PMC_PCSR0_PID16 (0x1 << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1 << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ -#define PMC_PCSR0_PID18 (0x1 << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ -#define PMC_PCSR0_PID19 (0x1 << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ -#define PMC_PCSR0_PID20 (0x1 << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ -#define PMC_PCSR0_PID21 (0x1 << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ -#define PMC_PCSR0_PID22 (0x1 << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ -#define PMC_PCSR0_PID23 (0x1 << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ -#define PMC_PCSR0_PID24 (0x1 << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ -#define PMC_PCSR0_PID25 (0x1 << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ -#define PMC_PCSR0_PID26 (0x1 << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ -#define PMC_PCSR0_PID27 (0x1 << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ -#define PMC_PCSR0_PID28 (0x1 << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ -#define PMC_PCSR0_PID29 (0x1 << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ -#define PMC_PCSR0_PID30 (0x1 << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ -#define PMC_PCSR0_PID31 (0x1 << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ -/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ -#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ -#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ -/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ -#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ -#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ -/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ -#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ -#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ -#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ -#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ -/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ -#define CKGR_PLLBR_DIVB_Pos 0 -#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */ -#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos))) -#define CKGR_PLLBR_PLLBCOUNT_Pos 8 -#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */ -#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos))) -#define CKGR_PLLBR_MULB_Pos 16 -#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ -#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos))) -/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ -#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ -#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ -#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ -#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */ -#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ -#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ -#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ -#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ -#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ -#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ -#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ -#define PMC_MCKR_PLLADIV2 (0x1 << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ -#define PMC_MCKR_PLLBDIV2 (0x1 << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ -/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ -#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ -#define PMC_USB_USBDIV_Pos 8 -#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */ -#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) -/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ -#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ -#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ -/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ -#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ -#define PMC_IER_LOCKB (0x1 << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ -#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ -/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ -#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ -#define PMC_IDR_LOCKB (0x1 << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ -/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ -#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ -#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLLA Lock Status */ -#define PMC_SR_LOCKB (0x1 << 2) /**< \brief (PMC_SR) PLLB Lock Status */ -#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ -#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ -#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ -#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ -#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ -#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ -#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ -/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ -#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ -#define PMC_IMR_LOCKB (0x1 << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ -/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ -#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ -#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ -#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ -#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ -#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ -#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ -#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ -#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ -#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ -#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ -#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ -#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ -#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ -#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ -#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ -#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ -#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ -#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ -#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ -#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ -/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ -#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ -#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ -/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PMC_WPMR_WPEN (0x1 << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ -#define PMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (PMC_WPMR) Write Protect KEY */ -/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ -#define PMC_WPSR_WPVS (0x1 << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (PMC_WPSR) Write Protect Violation Source */ -/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ -#define PMC_PCER1_PID32 (0x1 << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ -#define PMC_PCER1_PID33 (0x1 << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ -#define PMC_PCER1_PID34 (0x1 << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ -#define PMC_PCER1_PID35 (0x1 << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ -#define PMC_PCER1_PID36 (0x1 << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ -#define PMC_PCER1_PID37 (0x1 << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ -#define PMC_PCER1_PID38 (0x1 << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ -#define PMC_PCER1_PID39 (0x1 << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ -#define PMC_PCER1_PID40 (0x1 << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ -#define PMC_PCER1_PID41 (0x1 << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ -#define PMC_PCER1_PID42 (0x1 << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ -#define PMC_PCER1_PID43 (0x1 << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ -#define PMC_PCER1_PID44 (0x1 << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ -#define PMC_PCER1_PID45 (0x1 << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ -#define PMC_PCER1_PID46 (0x1 << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ -#define PMC_PCER1_PID47 (0x1 << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ -#define PMC_PCER1_PID48 (0x1 << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ -#define PMC_PCER1_PID49 (0x1 << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ -#define PMC_PCER1_PID50 (0x1 << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ -#define PMC_PCER1_PID51 (0x1 << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ -#define PMC_PCER1_PID52 (0x1 << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ -#define PMC_PCER1_PID53 (0x1 << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ -#define PMC_PCER1_PID54 (0x1 << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ -#define PMC_PCER1_PID55 (0x1 << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ -#define PMC_PCER1_PID56 (0x1 << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ -#define PMC_PCER1_PID57 (0x1 << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ -#define PMC_PCER1_PID58 (0x1 << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ -#define PMC_PCER1_PID59 (0x1 << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ -#define PMC_PCER1_PID60 (0x1 << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ -#define PMC_PCER1_PID61 (0x1 << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ -#define PMC_PCER1_PID62 (0x1 << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ -#define PMC_PCER1_PID63 (0x1 << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ -/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ -#define PMC_PCDR1_PID32 (0x1 << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ -#define PMC_PCDR1_PID33 (0x1 << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ -#define PMC_PCDR1_PID34 (0x1 << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ -#define PMC_PCDR1_PID35 (0x1 << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ -#define PMC_PCDR1_PID36 (0x1 << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ -#define PMC_PCDR1_PID37 (0x1 << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ -#define PMC_PCDR1_PID38 (0x1 << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ -#define PMC_PCDR1_PID39 (0x1 << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ -#define PMC_PCDR1_PID40 (0x1 << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ -#define PMC_PCDR1_PID41 (0x1 << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ -#define PMC_PCDR1_PID42 (0x1 << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ -#define PMC_PCDR1_PID43 (0x1 << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ -#define PMC_PCDR1_PID44 (0x1 << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ -#define PMC_PCDR1_PID45 (0x1 << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ -#define PMC_PCDR1_PID46 (0x1 << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ -#define PMC_PCDR1_PID47 (0x1 << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ -#define PMC_PCDR1_PID48 (0x1 << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ -#define PMC_PCDR1_PID49 (0x1 << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ -#define PMC_PCDR1_PID50 (0x1 << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ -#define PMC_PCDR1_PID51 (0x1 << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ -#define PMC_PCDR1_PID52 (0x1 << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ -#define PMC_PCDR1_PID53 (0x1 << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ -#define PMC_PCDR1_PID54 (0x1 << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ -#define PMC_PCDR1_PID55 (0x1 << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ -#define PMC_PCDR1_PID56 (0x1 << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ -#define PMC_PCDR1_PID57 (0x1 << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ -#define PMC_PCDR1_PID58 (0x1 << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ -#define PMC_PCDR1_PID59 (0x1 << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ -#define PMC_PCDR1_PID60 (0x1 << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ -#define PMC_PCDR1_PID61 (0x1 << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ -#define PMC_PCDR1_PID62 (0x1 << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ -#define PMC_PCDR1_PID63 (0x1 << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ -/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ -#define PMC_PCSR1_PID32 (0x1 << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ -#define PMC_PCSR1_PID33 (0x1 << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ -#define PMC_PCSR1_PID34 (0x1 << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ -#define PMC_PCSR1_PID35 (0x1 << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ -#define PMC_PCSR1_PID36 (0x1 << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ -#define PMC_PCSR1_PID37 (0x1 << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ -#define PMC_PCSR1_PID38 (0x1 << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ -#define PMC_PCSR1_PID39 (0x1 << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ -#define PMC_PCSR1_PID40 (0x1 << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ -#define PMC_PCSR1_PID41 (0x1 << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ -#define PMC_PCSR1_PID42 (0x1 << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ -#define PMC_PCSR1_PID43 (0x1 << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ -#define PMC_PCSR1_PID44 (0x1 << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ -#define PMC_PCSR1_PID45 (0x1 << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ -#define PMC_PCSR1_PID46 (0x1 << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ -#define PMC_PCSR1_PID47 (0x1 << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ -#define PMC_PCSR1_PID48 (0x1 << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ -#define PMC_PCSR1_PID49 (0x1 << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ -#define PMC_PCSR1_PID50 (0x1 << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ -#define PMC_PCSR1_PID51 (0x1 << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ -#define PMC_PCSR1_PID52 (0x1 << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ -#define PMC_PCSR1_PID53 (0x1 << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ -#define PMC_PCSR1_PID54 (0x1 << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ -#define PMC_PCSR1_PID55 (0x1 << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ -#define PMC_PCSR1_PID56 (0x1 << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ -#define PMC_PCSR1_PID57 (0x1 << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ -#define PMC_PCSR1_PID58 (0x1 << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ -#define PMC_PCSR1_PID59 (0x1 << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ -#define PMC_PCSR1_PID60 (0x1 << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ -#define PMC_PCSR1_PID61 (0x1 << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ -#define PMC_PCSR1_PID62 (0x1 << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ -#define PMC_PCSR1_PID63 (0x1 << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ -/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ -#define PMC_OCR_CAL4 (0x7f << 0) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_SEL4 (0x1 << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_CAL8 (0x7f << 8) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_SEL8 (0x1 << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_CAL12 (0x7f << 16) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ -#define PMC_OCR_SEL12 (0x1 << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PWM Pulse Width Modulation Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief PwmCh_num hardware registers */ -typedef struct { - RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ - RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ - RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ - RwReg PWM_CPDR; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ - RwReg PWM_CPDRUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ - RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ - RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ - RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ -} PwmCh_num; -/** \brief Pwm hardware registers */ -typedef struct { - RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ - WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ - WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ - RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ - WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ - WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ - RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ - RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ - RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ - RwReg Reserved1[1]; - RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ - RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ - WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ - WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ - WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ - RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ - RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ - RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ - RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ - WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ - WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ - WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ - WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ - RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ - RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ - WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ - RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ - RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ - RwReg Reserved2[3]; - RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ - RwReg Reserved3[11]; - RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ - RwReg Reserved4[12]; - WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ - RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ - RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ - RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ - RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ - RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ - RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ - RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ - RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ - WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ - RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ - RwReg Reserved6[2]; - RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ - WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ - RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ - WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ - RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ - WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ - RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ - WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ - RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ - WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ - RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ - WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ - RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ - WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ - RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ - WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ - RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ - WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ - RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ - WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ - RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ - WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ - RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ - WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ - RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ - WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ - RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ - WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ - RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ - WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ - RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ - WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ - RwReg Reserved7[20]; - PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ -} Pwm; -#endif /* __ASSEMBLY__ */ -/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ -#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ -#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ -/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ -#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ -/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ -#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ -/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ -#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ -#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ -#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ -#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ -#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ -#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ -#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ -#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ -/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ -#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ -#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ -#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ -#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ -#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ -#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ -#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ -#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ -/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ -#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ -#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ -#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ -#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ -#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ -#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ -#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ -#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ -/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ -#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ -#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ -#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ -#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ -#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ -#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ -#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ -#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ -/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ -#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ -#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ -#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ -#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ -#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ -#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ -#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ -/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ -#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ -/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ -#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ -#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ -/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ -#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ -/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ -#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ -#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ -#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ -#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ -#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ -#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ -#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ -#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ -#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ -#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ -#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ -#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ -#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ -#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ -#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ -#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ -#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ -#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ -#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ -#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ -/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ -#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ -#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ -#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ -#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ -#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ -#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ -#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ -#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ -#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ -#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ -#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ -#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ -#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ -#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ -#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ -#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ -#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ -#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ -#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ -#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ -/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ -#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ -#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ -#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ -#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ -#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ -#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ -#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ -#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ -#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ -#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ -#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ -#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ -#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ -#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ -#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ -#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ -#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ -#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ -#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ -#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ -/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ -#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ -#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ -#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ -#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ -#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ -#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ -#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ -#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ -#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ -#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ -#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ -#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ -#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ -#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ -#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ -#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ -#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ -#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ -#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ -#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ -/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ -#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ -#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ -#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ -#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ -#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ -#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ -#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ -#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ -/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ -#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ -#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ -#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ -#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ -#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ -#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ -#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ -#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ -/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ -#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ -#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ -#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ -#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ -#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ -#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ -#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ -#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ -#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ -#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ -#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ -#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ -#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ -#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ -#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ -#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ -/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ -#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ -#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ -#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ -#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ -#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ -#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ -#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ -#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ -/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ -#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ -#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ -#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ -#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ -/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ -#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ -#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ -#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ -#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ -#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ -#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ -#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ -#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ -/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ -#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ -#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ -#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ -#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ -/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ -#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ -#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ -#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ -#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ -#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ -#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ -#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ -#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ -/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ -#define PWM_SMMR_GCEN0 (0x1 << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_GCEN1 (0x1 << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_DOWN0 (0x1 << 16) /**< \brief (PWM_SMMR) DOWN Count */ -#define PWM_SMMR_DOWN1 (0x1 << 17) /**< \brief (PWM_SMMR) DOWN Count */ -/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ -#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ -#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ -#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ -#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ -#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ -#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ -#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ -#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ -/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ -#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ -#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ -/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ -#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ -/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ -#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ -/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ -#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ -/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ -#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ -/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ -#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ -/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ -#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ -/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ -/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ -/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ -#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ -#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ -#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ -#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ -/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ -#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ -#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ -/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ -#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ -#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ -/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ -#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ -#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ -#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ -#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ -#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ -#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ -#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ -#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ -/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ -#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ -#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ -#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ -#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ -#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ -#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ -/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ -#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ -#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ -#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ -#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ -#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ -#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ -#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ -#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ -/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ -#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ -#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ -#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ -#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ -#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ -#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ -/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ -#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ -#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ -#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ -#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ -#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ -#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ -#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ -#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ -/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ -#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ -#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ -#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ -#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ -#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ -#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ -/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ -#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ -#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ -#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ -#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ -#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ -#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ -#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ -#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ -/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ -#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ -#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ -#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ -#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ -#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ -#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ -/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ -#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ -#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ -#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ -#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ -#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ -#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ -#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ -#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ -/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ -#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ -#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ -#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ -#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ -#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ -#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ -/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ -#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ -#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ -#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ -#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ -#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ -#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ -#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ -#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ -/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ -#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ -#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ -#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ -#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ -#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ -#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ -/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ -#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ -#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ -#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ -#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ -#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ -#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ -#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ -#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ -/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ -#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ -#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ -#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ -#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ -#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ -#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ -/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ -#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ -#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ -#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ -#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ -#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ -#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ -#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ -#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ -/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ -#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ -#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ -#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ -#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ -#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ -#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ -#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ -#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ -#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ -#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ -#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ -#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ -#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ -/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ -#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ -/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ -#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ -/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ -#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ -#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ -#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ -#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ -#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ -#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ -#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ -#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ -#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ -#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ -#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ -#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ -/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ -#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ -/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ -#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ -/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ -#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ -#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ -#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ -#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ -#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ -#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ -#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ -#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ -#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ -#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ -#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ -#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ -/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ -#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ -/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ -#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ -/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ -#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ -#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ -#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ -#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ -#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ -#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ -#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ -#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ -#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ -#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ -#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ -#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ -/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ -#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ -/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ -#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ -/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ -#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ -#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ -#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reset Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RSTC Reset Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rstc hardware registers */ -typedef struct { - WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ - RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ - RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ -} Rstc; -#endif /* __ASSEMBLY__ */ -/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ -#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ -#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ -#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ -#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ -/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ -#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ -#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ -#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ -#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ -/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ -#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ -#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ -#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Clock */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTC Real-time Clock */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtc hardware registers */ -typedef struct { - RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ - RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ - RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ - RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ - RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ - RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ - RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ - WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ - WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ - WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ - RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ - RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ -} Rtc; -#endif /* __ASSEMBLY__ */ -/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ -#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ -#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ -#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ -#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ -#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ -#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ -#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ -#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ -#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ -/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ -#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ -/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ -#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ -#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ -#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ -#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ -/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ -#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ -#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ -#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ -#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ -#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ -/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ -#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ -#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ -#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ -#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ -#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ -#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ -/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ -#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ -#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ -#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ -#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ -/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ -#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ -#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ -#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ -#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ -#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ -/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ -#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ -#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ -#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ -#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ -/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ -#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ -#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ -#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ -/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ -#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ -/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ -#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ -#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ -#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ -#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ -/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ -#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ -#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ -#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTT Real-time Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtt hardware registers */ -typedef struct { - RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ - RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ - RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ - RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ -} Rtt; -#endif /* __ASSEMBLY__ */ -/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ -#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ -#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ -#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ -/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ -#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ -/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ -#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ -/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ -#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ -#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Static Memory Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SMC Static Memory Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief SmcCs_number hardware registers */ -typedef struct { - RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ - RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ - RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ - RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ -} SmcCs_number; -/** \brief Smc hardware registers */ -typedef struct { - SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */ - RwReg Reserved1[12]; - RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ - WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ - WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ - RwReg Reserved2[22]; - RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ - RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ -} Smc; -#endif /* __ASSEMBLY__ */ -/* -------- SMC_SETUP0 : (SMC Offset: 0x0) SMC Setup Register (CS_number = 0) -------- */ -#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup Length */ -#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup Length in WRITE Access */ -#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup Length */ -#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE0 : (SMC Offset: 0x4) SMC Pulse Register (CS_number = 0) -------- */ -#define SMC_PULSE0_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ -#define SMC_PULSE0_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE0_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ -#define SMC_PULSE0_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE0 : (SMC Offset: 0x8) SMC Cycle Register (CS_number = 0) -------- */ -#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ -#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ -/* -------- SMC_MODE0 : (SMC Offset: 0xC) SMC Mode Register (CS_number = 0) -------- */ -#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ -#define SMC_MODE0_DBW (0x3 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ -#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ -#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ -#define SMC_MODE0_PMEN (0x1 << 24) /**< \brief (SMC_MODE0) Page Mode Enabled */ -#define SMC_MODE0_PS (0x3 << 28) /**< \brief (SMC_MODE0) Page Size */ -/* -------- SMC_SETUP1 : (SMC Offset: 0x10) SMC Setup Register (CS_number = 1) -------- */ -#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup Length */ -#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup Length in WRITE Access */ -#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup Length */ -#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE1 : (SMC Offset: 0x14) SMC Pulse Register (CS_number = 1) -------- */ -#define SMC_PULSE1_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ -#define SMC_PULSE1_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE1_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ -#define SMC_PULSE1_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE1 : (SMC Offset: 0x18) SMC Cycle Register (CS_number = 1) -------- */ -#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ -#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ -/* -------- SMC_MODE1 : (SMC Offset: 0x1C) SMC Mode Register (CS_number = 1) -------- */ -#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ -#define SMC_MODE1_DBW (0x3 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ -#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ -#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ -#define SMC_MODE1_PMEN (0x1 << 24) /**< \brief (SMC_MODE1) Page Mode Enabled */ -#define SMC_MODE1_PS (0x3 << 28) /**< \brief (SMC_MODE1) Page Size */ -/* -------- SMC_SETUP2 : (SMC Offset: 0x20) SMC Setup Register (CS_number = 2) -------- */ -#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup Length */ -#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup Length in WRITE Access */ -#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup Length */ -#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE2 : (SMC Offset: 0x24) SMC Pulse Register (CS_number = 2) -------- */ -#define SMC_PULSE2_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ -#define SMC_PULSE2_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE2_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ -#define SMC_PULSE2_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE2 : (SMC Offset: 0x28) SMC Cycle Register (CS_number = 2) -------- */ -#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ -#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ -/* -------- SMC_MODE2 : (SMC Offset: 0x2C) SMC Mode Register (CS_number = 2) -------- */ -#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ -#define SMC_MODE2_DBW (0x3 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ -#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ -#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ -#define SMC_MODE2_PMEN (0x1 << 24) /**< \brief (SMC_MODE2) Page Mode Enabled */ -#define SMC_MODE2_PS (0x3 << 28) /**< \brief (SMC_MODE2) Page Size */ -/* -------- SMC_SETUP3 : (SMC Offset: 0x30) SMC Setup Register (CS_number = 3) -------- */ -#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup Length */ -#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup Length in WRITE Access */ -#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup Length */ -#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE3 : (SMC Offset: 0x34) SMC Pulse Register (CS_number = 3) -------- */ -#define SMC_PULSE3_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ -#define SMC_PULSE3_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE3_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ -#define SMC_PULSE3_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE3 : (SMC Offset: 0x38) SMC Cycle Register (CS_number = 3) -------- */ -#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ -#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ -/* -------- SMC_MODE3 : (SMC Offset: 0x3C) SMC Mode Register (CS_number = 3) -------- */ -#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ -#define SMC_MODE3_DBW (0x3 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ -#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ -#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ -#define SMC_MODE3_PMEN (0x1 << 24) /**< \brief (SMC_MODE3) Page Mode Enabled */ -#define SMC_MODE3_PS (0x3 << 28) /**< \brief (SMC_MODE3) Page Size */ -/* -------- SMC_SETUP4 : (SMC Offset: 0x40) SMC Setup Register (CS_number = 4) -------- */ -#define SMC_SETUP4_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP4) NWE Setup Length */ -#define SMC_SETUP4_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP4) NCS Setup Length in WRITE Access */ -#define SMC_SETUP4_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP4) NRD Setup Length */ -#define SMC_SETUP4_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP4) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE4 : (SMC Offset: 0x44) SMC Pulse Register (CS_number = 4) -------- */ -#define SMC_PULSE4_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE4) NWE Pulse Length */ -#define SMC_PULSE4_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE4) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE4_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE4) NRD Pulse Length */ -#define SMC_PULSE4_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE4) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE4 : (SMC Offset: 0x48) SMC Cycle Register (CS_number = 4) -------- */ -#define SMC_CYCLE4_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE4) Total Write Cycle Length */ -#define SMC_CYCLE4_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE4) Total Read Cycle Length */ -/* -------- SMC_MODE4 : (SMC Offset: 0x4C) SMC Mode Register (CS_number = 4) -------- */ -#define SMC_MODE4_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE4) NWAIT Mode */ -#define SMC_MODE4_DBW (0x3 << 12) /**< \brief (SMC_MODE4) Data Bus Width */ -#define SMC_MODE4_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE4) Data Float Time */ -#define SMC_MODE4_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE4) TDF Optimization */ -#define SMC_MODE4_PMEN (0x1 << 24) /**< \brief (SMC_MODE4) Page Mode Enabled */ -#define SMC_MODE4_PS (0x3 << 28) /**< \brief (SMC_MODE4) Page Size */ -/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ -#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_CS0SE (0x1 << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS1SE (0x1 << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS2SE (0x1 << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS3SE (0x1 << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ -#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ -/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ -#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ -/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ -#define SMC_WPMR_WPEN (0x1 << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ -#define SMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SMC_WPMR) Write Protect KEY */ -/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ -#define SMC_WPSR_WPVS (0x1 << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ -#define SMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SPI Serial Peripheral Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Spi hardware registers */ -typedef struct { - WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ - RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ - RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ - WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ - RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ - WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ - WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ - RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ - RwReg Reserved1[4]; - RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ - RwReg Reserved2[41]; - RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ - RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved3[5]; - RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ - RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ - RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ - RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ - RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ - RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ - RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ - RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ - WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ - RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ -} Spi, AT91S_SPI, *AT91PS_SPI; -#endif /* __ASSEMBLY__ */ -/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ -#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ -#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ -#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ -#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ -/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ -#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ -#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ -#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ -#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ -#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ -#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ -#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ -#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ -#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ -#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ -/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ -#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ -#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ -/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ -#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ -#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ -#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ -#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ -#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ -#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ -#define SPI_SR_ENDRX (0x1 << 4) /**< \brief (SPI_SR) End of RX buffer */ -#define SPI_SR_ENDTX (0x1 << 5) /**< \brief (SPI_SR) End of TX buffer */ -#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) RX Buffer Full */ -#define SPI_SR_TXBUFE (0x1 << 7) /**< \brief (SPI_SR) TX Buffer Empty */ -#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ -#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ -#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ -#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ -#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ -#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ -#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ -#define SPI_IER_ENDRX (0x1 << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ -#define SPI_IER_ENDTX (0x1 << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ -#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ -#define SPI_IER_TXBUFE (0x1 << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ -#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ -#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ -#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ -#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ -#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ -#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ -#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ -#define SPI_IDR_ENDRX (0x1 << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ -#define SPI_IDR_ENDTX (0x1 << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ -#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ -#define SPI_IDR_TXBUFE (0x1 << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ -#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ -#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ -/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ -#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ -#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ -#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ -#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ -#define SPI_IMR_ENDRX (0x1 << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ -#define SPI_IMR_ENDTX (0x1 << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ -#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ -#define SPI_IMR_TXBUFE (0x1 << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ -#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ -#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ -/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ -#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ -#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ -#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 35.) */ -#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ -#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ -#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ -#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ -#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ -#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ -#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ -#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ -#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ -#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ -#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ -#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ -/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ -#define SPI_WPMR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */ -#define SPI_WPMR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */ -/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ -#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ -/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ -#define SPI_RPR_RXPTR (0xffffffff << 0) /**< \brief (SPI_RPR) Receive Pointer Register */ -/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ -#define SPI_RCR_RXCTR (0xffff << 0) /**< \brief (SPI_RCR) Receive Counter Register */ -/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ -#define SPI_TPR_TXPTR (0xffffffff << 0) /**< \brief (SPI_TPR) Transmit Counter Register */ -/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ -#define SPI_TCR_TXCTR (0xffff << 0) /**< \brief (SPI_TCR) Transmit Counter Register */ -/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ -#define SPI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SPI_RNPR) Receive Next Pointer */ -/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ -#define SPI_RNCR_RXNCTR (0xffff << 0) /**< \brief (SPI_RNCR) Receive Next Counter */ -/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SPI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SPI_TNPR) Transmit Next Pointer */ -/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SPI_TNCR_TXNCTR (0xffff << 0) /**< \brief (SPI_TNCR) Transmit Counter Next */ -/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ -#define SPI_PTCR_RXTEN (0x1 << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ -#define SPI_PTCR_RXTDIS (0x1 << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ -#define SPI_PTCR_TXTEN (0x1 << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ -#define SPI_PTCR_TXTDIS (0x1 << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ -/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ -#define SPI_PTSR_RXTEN (0x1 << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ -#define SPI_PTSR_TXTEN (0x1 << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SSC Synchronous Serial Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Ssc hardware registers */ -typedef struct { - WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ - RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ - RwReg Reserved1[2]; - RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ - RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ - RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ - RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ - RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ - WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ - RwReg Reserved2[2]; - RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ - RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ - RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ - RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ - RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ - WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ - WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ - RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved3[37]; - RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ - RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[5]; - RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ - RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ - RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ - RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ - RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ - RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ - RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ - RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ - WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ - RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ -} Ssc; -#endif /* __ASSEMBLY__ */ -/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ -#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ -#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ -#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ -#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ -#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ -/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ -#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ -/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ -#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ -#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ -#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ -#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ -#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ -#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ -#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ -#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ -#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ -#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ -#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ -#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ -#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ -#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ -/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ -#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ -#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ -#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ -#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ -#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ -#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ -#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ -#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ -/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ -#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ -#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ -#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ -#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ -#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ -#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ -#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ -/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ -#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ -#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ -#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ -#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ -#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ -#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ -#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ -#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ -#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ -/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ -#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ -/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ -#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ -/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ -#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ -/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ -#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ -/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ -#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ -/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ -#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ -/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ -#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ -#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ -#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ -#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ -#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ -#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ -#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ -#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ -#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ -#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ -#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ -#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ -#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ -#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ -/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ -#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ -#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ -#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ -#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ -#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ -#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ -#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ -#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ -#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ -#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ -#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ -#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ -/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ -#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ -#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ -#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ -#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ -#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ -#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ -#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ -#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ -#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ -#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ -#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ -/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ -#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ -#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ -#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ -#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ -#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ -#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ -#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ -#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ -#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ -#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ -#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ -/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ -#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ -#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ -/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ -#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ -#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ -/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ -#define SSC_RPR_RXPTR (0xffffffff << 0) /**< \brief (SSC_RPR) Receive Pointer Register */ -/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ -#define SSC_RCR_RXCTR (0xffff << 0) /**< \brief (SSC_RCR) Receive Counter Register */ -/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ -#define SSC_TPR_TXPTR (0xffffffff << 0) /**< \brief (SSC_TPR) Transmit Counter Register */ -/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ -#define SSC_TCR_TXCTR (0xffff << 0) /**< \brief (SSC_TCR) Transmit Counter Register */ -/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ -#define SSC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SSC_RNPR) Receive Next Pointer */ -/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ -#define SSC_RNCR_RXNCTR (0xffff << 0) /**< \brief (SSC_RNCR) Receive Next Counter */ -/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SSC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SSC_TNPR) Transmit Next Pointer */ -/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SSC_TNCR_TXNCTR (0xffff << 0) /**< \brief (SSC_TNCR) Transmit Counter Next */ -/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ -#define SSC_PTCR_RXTEN (0x1 << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ -#define SSC_PTCR_RXTDIS (0x1 << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ -#define SSC_PTCR_TXTEN (0x1 << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ -#define SSC_PTCR_TXTDIS (0x1 << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ -/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ -#define SSC_PTSR_RXTEN (0x1 << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ -#define SSC_PTSR_TXTEN (0x1 << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Supply Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SUPC Supply Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Supc hardware registers */ -typedef struct { - WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ - RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ - RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ - RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ - RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ - RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ -} Supc; -#endif /* __ASSEMBLY__ */ -/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ -#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ -#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ -#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ -#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ -#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ -/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ -#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ -#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ -#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ -#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ -#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ -#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ -#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ -#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ -#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ -#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ -#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ -#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ -#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ -#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ -#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ -#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ -#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ -#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ -#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ -#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ -#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ -#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ -/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ -#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ -#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ -#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ -#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ -#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ -#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ -#define SUPC_MR_ONREG (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ -#define SUPC_MR_ONREG_ONREG_UNUSED (0x0 << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ -#define SUPC_MR_ONREG_ONREG_USED (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ -#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ -#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ -#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ -#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ -/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ -#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ -#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ -/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ -#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ -#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ -#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ -#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ -#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ -#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ -#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ -#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ -#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ -#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ -#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ -#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ -#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ -#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ -#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ -#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ -#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ -#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ -#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ -#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ -#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ -#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ -#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ -#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ -#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ -#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ -#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ -#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ -#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ -#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ -#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ -#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ -#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ -#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ -#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ -#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ -#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ -#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ -#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ -#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ -#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ -#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ -#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ -#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ -#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ -#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ -#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ -#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ -#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ -#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ -#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ -#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ -#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ -#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ -#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ -#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ -#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ -#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ -#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ -#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ -#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Timer Counter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TC Timer Counter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief TcChannel hardware registers */ -typedef struct { - RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ - RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ - RwReg Reserved1[2]; - RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ - RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ - RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ - RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ - RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ - RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ - RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ - RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ - RwReg Reserved2[4]; -} TcChannel; -/** \brief Tc hardware registers */ -typedef struct { - TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ - WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ - RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ - WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ - WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ - RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ - RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ - RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ - RwReg Reserved1[2]; - RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ - RwReg Reserved2[5]; - RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ -} Tc; -#endif /* __ASSEMBLY__ */ -/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ - -#define TC_CCR_CLKEN TC_CCR0_CLKEN /**< \brief (TC_CCR) Counter Clock Enable Command */ -#define TC_CCR_CLKDIS TC_CCR0_CLKDIS /**< \brief (TC_CCR) Counter Clock Disable Command */ -#define TC_CCR_SWTRG TC_CCR0_SWTRG /**< \brief (TC_CCR) Software Trigger Command */ - -#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ -#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ -#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ -/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ -#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ -#define TC_CM0_TCCLKS_TIMER_DIV1_CLOCK (0x0 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV1_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV2_CLOCK (0x1 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV2_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV3_CLOCK (0x2 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV3_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV4_CLOCK (0x3 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV4_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV5_CLOCK (0x4 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV5_CLOCK*/ -#define TC_CM0_TCCLKS_XC0 (0x5 << 0) /**< (TC_CMR0) Clock selected: XC0*/ -#define TC_CM0_TCCLKS_XC1 (0x6 << 0) /**< (TC_CMR0) Clock selected: XC1*/ -#define TC_CM0_TCCLKS_XC2 (0x7 << 0) /**< (TC_CMR0) Clock selected: XC2*/ -#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ -#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ -#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ -#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ -#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ -#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ -#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ -#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ -#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ -#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ -#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ - -#define TC_CMR_CPCTRG TC_CMR0_CPCTRG -#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ -#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ -#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ -#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ -#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ -#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ - -#define TC_CMR0_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define TC_CMR0_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define TC_CMR0_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define TC_CMR0_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle - -#define TC_CMR0_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define TC_CMR0_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define TC_CMR0_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define TC_CMR0_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ -#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ -/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ -#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ -/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ -#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ -/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ -#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ -/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ -#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ -#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ -#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ -#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ -#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ -#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ -#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ -#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ -#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ -#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ -#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ -/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ -#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ -#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ -#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ -#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ - -#define TC_IER_CPCS TC_IER0_CPCS -#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ -#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ -#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ -#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ -/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ -#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ -#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ -#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ -#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ -#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ -#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ -#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ -#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ -/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ -#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ -#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ -#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ -#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ -#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ -#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ -#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ -#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ -/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ -#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ -#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ -#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ -/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ -#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ -#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ -#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ -#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ -#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ -#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ -#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ -#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ -#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ -#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ -#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ -#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ -#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ -#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ -#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ -#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ -#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ -#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ -/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ -#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ -/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ -#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ -/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ -#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ -/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ -#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ -/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ -#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ -#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ -#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ -#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ -#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ -#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ -#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ -#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ -#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ -#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ -#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ -/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ -#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ -#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ -#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ -#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ -#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ -#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ -#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ -#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ -/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ -#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ -#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ -#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ -#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ -#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ -#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ -#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ -#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ -/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ -#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ -#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ -#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ -#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ -#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ -#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ -#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ -#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ -/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ -#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ -#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ -#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ -/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ -#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ -#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ -#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ -#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ -#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ -#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ -#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ -#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ -#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ -#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ -#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ -#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ -#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ -#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ -#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ -#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ -#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ -#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ -/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ -#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ -/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ -#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ -/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ -#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ -/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ -#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ -/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ -#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ -#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ -#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ -#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ -#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ -#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ -#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ -#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ -#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ -#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ -#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ -/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ -#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ -#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ -#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ -#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ -#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ -#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ -#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ -#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ -/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ -#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ -#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ -#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ -#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ -#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ -#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ -#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ -#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ -/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ -#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ -#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ -#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ -#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ -#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ -#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ -#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ -#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ -/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ -#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ -/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ -#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ -#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ -#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ -#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ -#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ -#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ -#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ -#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ -#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ -#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ -#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ -#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ -#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ -#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ -#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ -/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ -#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ -#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ -#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ -/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ -#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ -#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ -#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ -/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ -#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ -#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ -#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ -/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ -#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ -#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ -#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ -#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ -/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ -#define TC_FMR_ENCF0 (0x1 << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ -#define TC_FMR_ENCF1 (0x1 << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ -/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ -#define TC_WPMR_WPEN (0x1 << 0) /**< \brief (TC_WPMR) Write Protect Enable */ -#define TC_WPMR_WPKEY (0xffffff << 8) /**< \brief (TC_WPMR) Write Protect KEY */ -/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ -#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ -#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TWI Two-wire Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Twi hardware registers */ -typedef struct { - WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ - RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ - RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ - RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ - RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ - RwReg Reserved1[3]; - RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ - WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ - WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ - RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ - RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ - WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ - RwReg Reserved2[50]; - RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ - RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ - RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ - RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ - RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ - RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ - RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ - RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ - WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ - RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ -} Twi; -#endif /* __ASSEMBLY__ */ -/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ -#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ -#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ -#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ -#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ -#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ -#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ -#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ -#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ -#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ + +/** \addtogroup AT91SAM3S_definitions AT91SAM3S definitions + This file defines all structures and symbols for AT91SAM3S: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __ASSEMBLY__ +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *) value) +#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ***************************************************************************** */ +/* CMSIS DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_cmsis CMSIS Definitions */ + +/*@{*/ + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __MPU_PRESENT 0 /**< AT91SAM3S does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 4 /**< AT91SAM3S uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** AT91SAM3S specific Interrupt Numbers *****************************************/ + + SUPC_IRQn = 0, /**< 0 AT91SAM3S Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 AT91SAM3S Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 AT91SAM3S Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 AT91SAM3S Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 AT91SAM3S Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 AT91SAM3S Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 AT91SAM3S Enhanced Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 AT91SAM3S UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 AT91SAM3S UART 1 (UART1) */ + SMC_IRQn = 10, /**< 10 AT91SAM3S Static Memory Controller (SMC) */ + PIOA_IRQn = 11, /**< 11 AT91SAM3S Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 AT91SAM3S Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 13, /**< 13 AT91SAM3S Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 14, /**< 14 AT91SAM3S USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 AT91SAM3S USART 1 (USART1) */ + HSMCI_IRQn = 18, /**< 18 AT91SAM3S Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 AT91SAM3S Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 AT91SAM3S Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 AT91SAM3S Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 AT91SAM3S Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 AT91SAM3S Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 AT91SAM3S Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 AT91SAM3S Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 AT91SAM3S Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 AT91SAM3S Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 AT91SAM3S Timer/Counter 5 (TC5) */ + ADC_IRQn = 29, /**< 29 AT91SAM3S Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 AT91SAM3S Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 AT91SAM3S Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 AT91SAM3S CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 AT91SAM3S Analog Comparator (ACC) */ + UDP_IRQn = 34 /**< 34 AT91SAM3S USB Device Port (UDP) */ +} IRQn_Type; +/*@}*/ + +/* ***************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_api Peripheral Software API */ +/*@{*/ +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_ACC Analog Comparator Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Acc hardware registers */ +typedef struct { + WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + RwReg Reserved1[7]; + WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + RwReg Reserved2[24]; + RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + RwReg Reserved3[19]; + RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ + RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ +} Acc; +#endif /* __ASSEMBLY__ */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1 << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELPLUS (0x7 << 0) /**< \brief (ACC_MR) SELection for PLUS comparator input */ +#define ACC_MR_SELMINUS (0x7 << 4) /**< \brief (ACC_MR) SELection for MINUS comparator input */ +#define ACC_MR_ACEN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ +#define ACC_MR_ACEN_EN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ +#define ACC_MR_ACEN_DIS (0x0 << 8) /**< \brief (ACC_MR) Analog Comparator Disable */ +#define ACC_MR_EDGETYP (0x3 << 9) /**< \brief (ACC_MR) EDGE TYPe */ +#define ACC_MR_EDGETYP_RISING (0x0 << 9) /**< \brief (ACC_MR) EDGE TYPe ,RISING edge*/ +#define ACC_MR_EDGETYP_FALLING (0x1 << 9) /**< \brief (ACC_MR) EDGE TYPe,falling edge */ +#define ACC_MR_EDGETYP_ANY (0x2 << 9) /**< \brief (ACC_MR) EDGE TYPe,any edge */ +#define ACC_MR_INV (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ +#define ACC_MR_INV_EN (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ +#define ACC_MR_INV_DIS (0x0 << 12) /**< \brief (ACC_MR) DIRECTLY */ +#define ACC_MR_SELFS (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ +#define ACC_MR_SELFS_CF (0x0 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ +#define ACC_MR_SELFS_OUTPUT (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ +#define ACC_MR_FE (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_EN (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0 << 14) /**< \brief (ACC_MR) Fault Enable */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1 << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1 << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1 << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1 << 0) /**< \brief (ACC_ISR) Comparison Edge */ +#define ACC_ISR_SCO (0x1 << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1 << 31) /**< \brief (ACC_ISR) */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1 << 0) /**< \brief (ACC_ACR) Current SELection */ +#define ACC_ACR_HYST (0x3 << 1) /**< \brief (ACC_ACR) HYSTeresis selection */ +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1 << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ +#define ACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ACC_WPMR) Write Protect KEY */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ +#define ACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_ADC Analog-to-digital Converter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Adc hardware registers */ +typedef struct { + WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ + RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ + RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence 1Register */ + RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence 2 Register */ + WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ + WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ + RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ + RwReg Reserved1[1]; + RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ + WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ + WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ + RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ + RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ + RwReg Reserved2[2]; + RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ + RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ + RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ + RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ + RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ + RoReg ADC_CDR0; /**< \brief (Adc Offset: 0x50) Channel Data Register 0 */ + RoReg ADC_CDR1; /**< \brief (Adc Offset: 0x54) Channel Data Register 1 */ + RoReg ADC_CDR2; /**< \brief (Adc Offset: 0x58) Channel Data Register 2 */ + RoReg ADC_CDR3; /**< \brief (Adc Offset: 0x5C) Channel Data Register 3 */ + RoReg ADC_CDR4; /**< \brief (Adc Offset: 0x60) Channel Data Register 4 */ + RoReg ADC_CDR5; /**< \brief (Adc Offset: 0x64) Channel Data Register 5 */ + RoReg ADC_CDR6; /**< \brief (Adc Offset: 0x68) Channel Data Register 6 */ + RoReg ADC_CDR7; /**< \brief (Adc Offset: 0x6C) Channel Data Register 7 */ + RoReg ADC_CDR8; /**< \brief (Adc Offset: 0x70) Channel Data Register 8 */ + RoReg ADC_CDR9; /**< \brief (Adc Offset: 0x74) Channel Data Register 9 */ + RoReg ADC_CDR10; /**< \brief (Adc Offset: 0x78) Channel Data Register 10 */ + RoReg ADC_CDR11; /**< \brief (Adc Offset: 0x7C) Channel Data Register 11 */ + RoReg ADC_CDR12; /**< \brief (Adc Offset: 0x80) Channel Data Register 12 */ + RoReg ADC_CDR13; /**< \brief (Adc Offset: 0x84) Channel Data Register 13 */ + RoReg ADC_CDR14; /**< \brief (Adc Offset: 0x88) Channel Data Register 14 */ + RoReg ADC_CDR15; /**< \brief (Adc Offset: 0x8C) Channel Data Register 15 */ + RwReg Reserved3[1]; + RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ + RwReg Reserved4[19]; + RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ + RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ + RwReg Reserved5[5]; + RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ + RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ + RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */ + RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */ + RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ + RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ + RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */ + RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */ + WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ + RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ +} Adc; +#endif /* __ASSEMBLY__ */ +/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ +#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ +#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ +#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ +#define ADC_MR_TRGEN_DIS (0x0 << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.*/ +#define ADC_MR_TRGEN_EN (0x1) /**< (ADC) Hardware trigger selected by TRGSEL field is enabled.*/ +#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ +#define ADC_MR_TRGSEL_EXT (0x0 << 1) /**< \brief (ADC_MR) Selected TRGSEL = External Trigger*/ +#define ADC_MR_TRGSEL_TIOA0 (0x1 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO0*/ +#define ADC_MR_TRGSEL_TIOA1 (0x2 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO1*/ +#define ADC_MR_TRGSEL_TIOA2 (0x3 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO2*/ +#define ADC_MR_TRGSEL_PWM0_TRIG (0x4 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM trigger*/ +#define ADC_MR_TRGSEL_PWM1_TRIG (0x5 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM Trigger*/ +#define ADC_MR_TRGSEL_RESERVED (0x6 << 1) /**< \brief (ADC_MR) Selected TRGSEL = Reserved*/ +#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ +#define ADC_MR_LOWRES_12_BIT (0x0 << 4) /**< \brief (ADC_MR) 12-bit resolution*/ +#define ADC_MR_LOWRES_10_BIT (0x1 << 4) /**< \brief (ADC_MR) 10-bit resolution*/ +#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ +#define ADC_MR_SLEEP_NORMAL (0x0 << 5) /**< \brief (ADC12B) Normal Mode*/ +#define ADC_MR_FWUP (0x1 << 6) /**< \brief (ADC_MR) Fast Wake Up */ +#define ADC_MR_FREERUN (0x1 << 7) /**< \brief (ADC_MR) Free Run Mode */ +#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ +#define ADC_MR_STARTUP (0xf << 16) /**< \brief (ADC_MR) Start Up Time */ +#define ADC_MR_SETTLING (0x3 << 20) /**< \brief (ADC_MR) Analog Settling Time */ +#define ADC_MR_ANACH (0x1 << 23) /**< \brief (ADC_MR) Analog Change */ +#define ADC_MR_TRACKTIM (0xf << 24) /**< \brief (ADC_MR) Tracking Time */ +#define ADC_MR_TRANSFER (0x3 << 28) /**< \brief (ADC_MR) */ +#define ADC_MR_USEQ (0x1 << 31) /**< \brief (ADC_MR) User Sequence Enable */ +/* -------- ADC_SEQ1R : (ADC Offset: 0x08) Channel Sequence 1Register -------- */ +#define ADC_SEQ1R_USCH1 (0x7 << 0) /**< \brief (ADC_SEQ1R) User Sequence Number 1 */ +#define ADC_SEQ1R_USCH2 (0x7 << 4) /**< \brief (ADC_SEQ1R) User Sequence Number 2 */ +#define ADC_SEQ1R_USCH3 (0x7 << 8) /**< \brief (ADC_SEQ1R) User Sequence Number 3 */ +#define ADC_SEQ1R_USCH4 (0x7 << 12) /**< \brief (ADC_SEQ1R) User Sequence Number 4 */ +#define ADC_SEQ1R_USCH5 (0x7 << 16) /**< \brief (ADC_SEQ1R) User Sequence Number 5 */ +#define ADC_SEQ1R_USCH6 (0x7 << 20) /**< \brief (ADC_SEQ1R) User Sequence Number 6 */ +#define ADC_SEQ1R_USCH7 (0x7 << 24) /**< \brief (ADC_SEQ1R) User Sequence Number 7 */ +#define ADC_SEQ1R_USCH8 (0x7 << 28) /**< \brief (ADC_SEQ1R) User Sequence Number 8 */ +/* -------- ADC_SEQ2R : (ADC Offset: 0x0C) Channel Sequence 2 Register -------- */ +#define ADC_SEQ2R_USCH9 (0x7 << 0) /**< \brief (ADC_SEQ2R) User Sequence Number 9 */ +#define ADC_SEQ2R_USCH10 (0x7 << 4) /**< \brief (ADC_SEQ2R) User Sequence Number 10 */ +#define ADC_SEQ2R_USCH11 (0x7 << 8) /**< \brief (ADC_SEQ2R) User Sequence Number 11 */ +#define ADC_SEQ2R_USCH12 (0x7 << 12) /**< \brief (ADC_SEQ2R) User Sequence Number 12 */ +#define ADC_SEQ2R_USCH13 (0x7 << 16) /**< \brief (ADC_SEQ2R) User Sequence Number 13 */ +#define ADC_SEQ2R_USCH14 (0x7 << 20) /**< \brief (ADC_SEQ2R) User Sequence Number 14 */ +#define ADC_SEQ2R_USCH15 (0x7 << 24) /**< \brief (ADC_SEQ2R) User Sequence Number 15 */ +#define ADC_SEQ2R_USCH16 (0x7 << 28) /**< \brief (ADC_SEQ2R) User Sequence Number 16 */ +/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ +#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ +#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ +#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ +#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ +#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ +#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ +#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ +#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ +#define ADC_CHER_CH8 (0x1 << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ +#define ADC_CHER_CH9 (0x1 << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ +#define ADC_CHER_CH10 (0x1 << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ +#define ADC_CHER_CH11 (0x1 << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ +#define ADC_CHER_CH12 (0x1 << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ +#define ADC_CHER_CH13 (0x1 << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ +#define ADC_CHER_CH14 (0x1 << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ +#define ADC_CHER_CH15 (0x1 << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ +#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ +#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ +#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ +#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ +#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ +#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ +#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ +#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ +#define ADC_CHDR_CH8 (0x1 << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ +#define ADC_CHDR_CH9 (0x1 << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ +#define ADC_CHDR_CH10 (0x1 << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ +#define ADC_CHDR_CH11 (0x1 << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ +#define ADC_CHDR_CH12 (0x1 << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ +#define ADC_CHDR_CH13 (0x1 << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ +#define ADC_CHDR_CH14 (0x1 << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ +#define ADC_CHDR_CH15 (0x1 << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ +#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ +#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ +#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ +#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ +#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ +#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ +#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ +#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ +#define ADC_CHSR_CH8 (0x1 << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ +#define ADC_CHSR_CH9 (0x1 << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ +#define ADC_CHSR_CH10 (0x1 << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ +#define ADC_CHSR_CH11 (0x1 << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ +#define ADC_CHSR_CH12 (0x1 << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ +#define ADC_CHSR_CH13 (0x1 << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ +#define ADC_CHSR_CH14 (0x1 << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ +#define ADC_CHSR_CH15 (0x1 << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ +#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ +#define ADC_LCDR_CHNB (0xf << 12) /**< \brief (ADC_LCDR) Channel Number */ +/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ +#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ +#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ +#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ +#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ +#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ +#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ +#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ +#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ +#define ADC_IER_EOC8 (0x1 << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ +#define ADC_IER_EOC9 (0x1 << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ +#define ADC_IER_EOC10 (0x1 << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ +#define ADC_IER_EOC11 (0x1 << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ +#define ADC_IER_EOC12 (0x1 << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ +#define ADC_IER_EOC13 (0x1 << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ +#define ADC_IER_EOC14 (0x1 << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ +#define ADC_IER_EOC15 (0x1 << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ +#define ADC_IER_DRDY (0x1 << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ +#define ADC_IER_GOVRE (0x1 << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ +#define ADC_IER_COMPE (0x1 << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ +#define ADC_IER_ENDRX (0x1 << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ +#define ADC_IER_RXBUFF (0x1 << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ +/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ +#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ +#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ +#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ +#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ +#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ +#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ +#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ +#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ +#define ADC_IDR_EOC8 (0x1 << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ +#define ADC_IDR_EOC9 (0x1 << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ +#define ADC_IDR_EOC10 (0x1 << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ +#define ADC_IDR_EOC11 (0x1 << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ +#define ADC_IDR_EOC12 (0x1 << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ +#define ADC_IDR_EOC13 (0x1 << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ +#define ADC_IDR_EOC14 (0x1 << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ +#define ADC_IDR_EOC15 (0x1 << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ +#define ADC_IDR_DRDY (0x1 << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ +#define ADC_IDR_GOVRE (0x1 << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ +#define ADC_IDR_COMPE (0x1 << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ +#define ADC_IDR_ENDRX (0x1 << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ +#define ADC_IDR_RXBUFF (0x1 << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ +/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ +#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ +#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ +#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ +#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ +#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ +#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ +#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ +#define ADC_IMR_EOC8 (0x1 << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ +#define ADC_IMR_EOC9 (0x1 << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ +#define ADC_IMR_EOC10 (0x1 << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ +#define ADC_IMR_EOC11 (0x1 << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ +#define ADC_IMR_EOC12 (0x1 << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ +#define ADC_IMR_EOC13 (0x1 << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ +#define ADC_IMR_EOC14 (0x1 << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ +#define ADC_IMR_EOC15 (0x1 << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ +#define ADC_IMR_DRDY (0x1 << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ +#define ADC_IMR_GOVRE (0x1 << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ +#define ADC_IMR_COMPE (0x1 << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ +#define ADC_IMR_ENDRX (0x1 << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ +#define ADC_IMR_RXBUFF (0x1 << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ +/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ +#define ADC_ISR_EOC0 (0x1 << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ +#define ADC_ISR_EOC1 (0x1 << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ +#define ADC_ISR_EOC2 (0x1 << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ +#define ADC_ISR_EOC3 (0x1 << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ +#define ADC_ISR_EOC4 (0x1 << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ +#define ADC_ISR_EOC5 (0x1 << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ +#define ADC_ISR_EOC6 (0x1 << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ +#define ADC_ISR_EOC7 (0x1 << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ +#define ADC_ISR_EOC8 (0x1 << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ +#define ADC_ISR_EOC9 (0x1 << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ +#define ADC_ISR_EOC10 (0x1 << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ +#define ADC_ISR_EOC11 (0x1 << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ +#define ADC_ISR_EOC12 (0x1 << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ +#define ADC_ISR_EOC13 (0x1 << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ +#define ADC_ISR_EOC14 (0x1 << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ +#define ADC_ISR_EOC15 (0x1 << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ +#define ADC_ISR_DRDY (0x1 << 24) /**< \brief (ADC_ISR) Data Ready */ +#define ADC_ISR_GOVRE (0x1 << 25) /**< \brief (ADC_ISR) General Overrun Error */ +#define ADC_ISR_COMPE (0x1 << 26) /**< \brief (ADC_ISR) Comparison Error */ +#define ADC_ISR_ENDRX (0x1 << 27) /**< \brief (ADC_ISR) End of RX Buffer */ +#define ADC_ISR_RXBUFF (0x1 << 28) /**< \brief (ADC_ISR) RX Buffer Full */ +/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ +#define ADC_OVER_OVRE0 (0x1 << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ +#define ADC_OVER_OVRE1 (0x1 << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ +#define ADC_OVER_OVRE2 (0x1 << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ +#define ADC_OVER_OVRE3 (0x1 << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ +#define ADC_OVER_OVRE4 (0x1 << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ +#define ADC_OVER_OVRE5 (0x1 << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ +#define ADC_OVER_OVRE6 (0x1 << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ +#define ADC_OVER_OVRE7 (0x1 << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ +#define ADC_OVER_OVRE8 (0x1 << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ +#define ADC_OVER_OVRE9 (0x1 << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ +#define ADC_OVER_OVRE10 (0x1 << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ +#define ADC_OVER_OVRE11 (0x1 << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ +#define ADC_OVER_OVRE12 (0x1 << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ +#define ADC_OVER_OVRE13 (0x1 << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ +#define ADC_OVER_OVRE14 (0x1 << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ +#define ADC_OVER_OVRE15 (0x1 << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ +/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ +#define ADC_EMR_CMPMODE (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode */ +#define ADC_EMR_CMPMODE_LOW (0x0 << 0) /**< \brief (ADC_EMR) Comparison Mode,lower than low threshold */ +#define ADC_EMR_CMPMODE_HIGH (0x1 << 0) /**< \brief (ADC_EMR) Comparison Mode,higher than high threshold */ +#define ADC_EMR_CMPMODE_IN (0x2 << 0) /**< \brief (ADC_EMR) Comparison Mode, in the comparison window */ +#define ADC_EMR_CMPMODE_OUT (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode, out of the comparison window */ +#define ADC_EMR_CMPSEL (0xf << 4) /**< \brief (ADC_EMR) Comparison Selected Channel */ +#define ADC_EMR_CMPALL (0x1 << 9) /**< \brief (ADC_EMR) Compare All Channels */ +#define ADC_EMR_TAG (0x1 << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ +/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ +#define ADC_CWR_LOWTHRES (0xfff << 0) /**< \brief (ADC_CWR) Low Threshold */ +#define ADC_CWR_HIGHTHRES (0xfff << 16) /**< \brief (ADC_CWR) High Threshold */ +/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ +#define ADC_CGR_GAIN0 (0x3 << 0) /**< \brief (ADC_CGR) Gain for channel 0 */ +#define ADC_CGR_GAIN1 (0x3 << 2) /**< \brief (ADC_CGR) Gain for channel 1 */ +#define ADC_CGR_GAIN2 (0x3 << 4) /**< \brief (ADC_CGR) Gain for channel 2 */ +#define ADC_CGR_GAIN3 (0x3 << 6) /**< \brief (ADC_CGR) Gain for channel 3 */ +#define ADC_CGR_GAIN4 (0x3 << 8) /**< \brief (ADC_CGR) Gain for channel 4 */ +#define ADC_CGR_GAIN5 (0x3 << 10) /**< \brief (ADC_CGR) Gain for channel 5 */ +#define ADC_CGR_GAIN6 (0x3 << 12) /**< \brief (ADC_CGR) Gain for channel 6 */ +#define ADC_CGR_GAIN7 (0x3 << 14) /**< \brief (ADC_CGR) Gain for channel 7 */ +#define ADC_CGR_GAIN8 (0x3 << 16) /**< \brief (ADC_CGR) Gain for channel 8 */ +#define ADC_CGR_GAIN9 (0x3 << 18) /**< \brief (ADC_CGR) Gain for channel 9 */ +#define ADC_CGR_GAIN10 (0x3 << 20) /**< \brief (ADC_CGR) Gain for channel 10 */ +#define ADC_CGR_GAIN11 (0x3 << 22) /**< \brief (ADC_CGR) Gain for channel 11 */ +#define ADC_CGR_GAIN12 (0x3 << 24) /**< \brief (ADC_CGR) Gain for channel 12 */ +#define ADC_CGR_GAIN13 (0x3 << 26) /**< \brief (ADC_CGR) Gain for channel 13 */ +#define ADC_CGR_GAIN14 (0x3 << 28) /**< \brief (ADC_CGR) Gain for channel 14 */ +#define ADC_CGR_GAIN15 (0x3 << 30) /**< \brief (ADC_CGR) Gain for channel 15 */ +/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ +#define ADC_COR_OFF0 (0x1 << 0) /**< \brief (ADC_COR) Offset for channel 0 */ +#define ADC_COR_OFF1 (0x1 << 1) /**< \brief (ADC_COR) Offset for channel 1 */ +#define ADC_COR_OFF2 (0x1 << 2) /**< \brief (ADC_COR) Offset for channel 2 */ +#define ADC_COR_OFF3 (0x1 << 3) /**< \brief (ADC_COR) Offset for channel 3 */ +#define ADC_COR_OFF4 (0x1 << 4) /**< \brief (ADC_COR) Offset for channel 4 */ +#define ADC_COR_OFF5 (0x1 << 5) /**< \brief (ADC_COR) Offset for channel 5 */ +#define ADC_COR_OFF6 (0x1 << 6) /**< \brief (ADC_COR) Offset for channel 6 */ +#define ADC_COR_OFF7 (0x1 << 7) /**< \brief (ADC_COR) Offset for channel 7 */ +#define ADC_COR_OFF8 (0x1 << 8) /**< \brief (ADC_COR) Offset for channel 8 */ +#define ADC_COR_OFF9 (0x1 << 9) /**< \brief (ADC_COR) Offset for channel 9 */ +#define ADC_COR_OFF10 (0x1 << 10) /**< \brief (ADC_COR) Offset for channel 10 */ +#define ADC_COR_OFF11 (0x1 << 11) /**< \brief (ADC_COR) Offset for channel 11 */ +#define ADC_COR_OFF12 (0x1 << 12) /**< \brief (ADC_COR) Offset for channel 12 */ +#define ADC_COR_OFF13 (0x1 << 13) /**< \brief (ADC_COR) Offset for channel 13 */ +#define ADC_COR_OFF14 (0x1 << 14) /**< \brief (ADC_COR) Offset for channel 14 */ +#define ADC_COR_OFF15 (0x1 << 15) /**< \brief (ADC_COR) Offset for channel 15 */ +#define ADC_COR_DIFF0 (0x1 << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ +#define ADC_COR_DIFF1 (0x1 << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ +#define ADC_COR_DIFF2 (0x1 << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ +#define ADC_COR_DIFF3 (0x1 << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ +#define ADC_COR_DIFF4 (0x1 << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ +#define ADC_COR_DIFF5 (0x1 << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ +#define ADC_COR_DIFF6 (0x1 << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ +#define ADC_COR_DIFF7 (0x1 << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ +#define ADC_COR_DIFF8 (0x1 << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ +#define ADC_COR_DIFF9 (0x1 << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ +#define ADC_COR_DIFF10 (0x1 << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ +#define ADC_COR_DIFF11 (0x1 << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ +#define ADC_COR_DIFF12 (0x1 << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ +#define ADC_COR_DIFF13 (0x1 << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ +#define ADC_COR_DIFF14 (0x1 << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ +#define ADC_COR_DIFF15 (0x1 << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ +/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */ +#define ADC_CDR0_DATA (0x3ff << 0) /**< \brief (ADC_CDR0) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */ +#define ADC_CDR1_DATA (0x3ff << 0) /**< \brief (ADC_CDR1) Converted Data */ +/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */ +#define ADC_CDR2_DATA (0x3ff << 0) /**< \brief (ADC_CDR2) Converted Data */ +/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */ +#define ADC_CDR3_DATA (0x3ff << 0) /**< \brief (ADC_CDR3) Converted Data */ +/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */ +#define ADC_CDR4_DATA (0x3ff << 0) /**< \brief (ADC_CDR4) Converted Data */ +/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */ +#define ADC_CDR5_DATA (0x3ff << 0) /**< \brief (ADC_CDR5) Converted Data */ +/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */ +#define ADC_CDR6_DATA (0x3ff << 0) /**< \brief (ADC_CDR6) Converted Data */ +/* -------- ADC_CDR15 : (ADC Offset: 0x6C) Channel Data Register 15 -------- */ +#define ADC_CDR15_DATA (0x3ff << 0) /**< \brief (ADC_CDR15) Converted Data */ +/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ +#define ADC_ACR_TSON (0x1 << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ +#define ADC_ACR_IBCTL (0x3 << 8) /**< \brief (ADC_ACR) ADC Bias Current Control */ +/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ADC_WPMR_WPEN (0x1 << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ +#define ADC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ADC_WPMR) Write Protect KEY */ +/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ +#define ADC_WPSR_WPVS (0x1 << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ +#define ADC_WPSR_WPVSRC (0xffff << 8) /**< \brief (ADC_WPSR) Write Protect Violation Source */ +/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ +#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ +/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ +#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ +/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ +#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ +/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ +#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ +/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ +#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ +/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ +#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ +/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ +/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ +/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ +#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ +#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ +#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ +#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ +/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ +#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ +#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_CHIPID Chip Identifier */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Chipid hardware registers */ +typedef struct { + RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* __ASSEMBLY__ */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ +#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Crccu hardware registers */ +typedef struct { + RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ + RwReg Reserved1[1]; + WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ + WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ + RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ + WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ + WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ + RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ + RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ + RwReg Reserved2[4]; + WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ + RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ + RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ + WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ + WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ + RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ + RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ +} Crccu; +#endif /* __ASSEMBLY__ */ +/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ +#define CRCCU_DSCR_DSCR (0x7fffff << 9) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ +/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ +#define CRCCU_DMA_EN_DMAEN (0x1 << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ +/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ +#define CRCCU_DMA_DIS_DMADIS (0x1 << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ +/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ +#define CRCCU_DMA_SR_DMASR (0x1 << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ +/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ +#define CRCCU_DMA_IER_DMAIER (0x1 << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ +/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ +#define CRCCU_DMA_IDR_DMAIDR (0x1 << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ +/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ +#define CRCCU_DMA_IMR_DMAIMR (0x1 << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ +/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ +#define CRCCU_DMA_ISR_DMAISR (0x1 << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ +/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ +#define CRCCU_CR_RESET (0x1 << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ +/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ +#define CRCCU_MR_ENABLE (0x1 << 0) /**< \brief (CRCCU_MR) CRC Enable */ +#define CRCCU_MR_COMPARE (0x1 << 1) /**< \brief (CRCCU_MR) CRC Compare */ +#define CRCCU_MR_PTYPE (0x3 << 2) /**< \brief (CRCCU_MR) Primitive Polynomial */ +#define CRCCU_MR_PTYPE_CCIT8023 (0x0 << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ +#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1 << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ +#define CRCCU_MR_PTYPE_CCIT16 (0x2 << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ +#define CRCCU_MR_DIVIDER (0xf << 4) /**< \brief (CRCCU_MR) Request Divider */ +/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ +#define CRCCU_SR_CRC (0xffffffff << 0) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ +/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ +#define CRCCU_IER_ERRIER (0x1 << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ +/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ +#define CRCCU_IDR_ERRIDR (0x1 << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ +/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ +#define CRCCU_IMR_ERRIMR (0x1 << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ +/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ +#define CRCCU_ISR_ERRISR (0x1 << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Dacc hardware registers */ +typedef struct { + WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + RwReg Reserved1[2]; + WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + RwReg Reserved2[1]; + WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ + WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + RwReg Reserved3[24]; + RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + RwReg Reserved4[19]; + RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ + RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ + RwReg Reserved5[5]; + RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */ + RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */ + RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ + RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ + RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */ + RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */ + RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ + RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ + WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ + RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ +} Dacc; +#endif /* __ASSEMBLY__ */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1 << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_TRGEN (0x1 << 0) /**< \brief (DACC_MR) Trigger Enable */ +#define DACC_MR_TRGEN_DIS (0x0 << 0) // (DACC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. +#define DACC_MR_TRGEN_EN (0x1 << 0) // (DACC_MR) Hardware trigger selected by TRGSEL field is enabled. + +#define DACC_MR_TRGSEL (0x7 << 1) /**< \brief (DACC_MR) Trigger Selection */ +#define DACC_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (DACC_MR) External trigger +#define DACC_MR_TRGSEL_TIOA_0 (0x1 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 0 +#define DACC_MR_TRGSEL_TIOA_1 (0x2 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 1 +#define DACC_MR_TRGSEL_TIOA_2 (0x3 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 2 +#define DACC_MR_TRGSEL_PWM_0 (0x4 << 1) // (DACC_MR) PWM Event Line 0 +#define DACC_MR_TRGSEL_PWM_1 (0x5 << 1) // (DACC_MR) PWM Event Line 1 +#define DACC_MR_WORD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_WORD_HALF (0x0 << 4) /**< \brief (DACC_MR) Half-Word Transfer */ +#define DACC_MR_WORD_WORLD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_SLEEP (0x1 << 5) /**< \brief (DACC_MR) Sleep Mode */ +#define DACC_MR_SLEEP_NORMAL (0x0 << 5) // (DACC_MR) Normal Mode +#define DACC_MR_SLEEP_SLEEP (0x1 << 5) // (DACC_MR) Sleep Modes +#define DACC_MR_FASTWKUP (0x1 << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ +#define DACC_MR_REFRESH (0xff << 8) /**< \brief (DACC_MR) Refresh Period */ +#define DACC_MR_USER_SEL (0x3 << 16) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_USER_SEL_0 (0x0 << 16) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_USER_SEL_1 (0x1 << 16) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_TAG (0x1 << 20) /**< \brief (DACC_MR) Tag Selection Mode */ +#define DACC_MR_MAXS (0x1 << 21) /**< \brief (DACC_MR) Max Speed Mode */ +#define DACC_MR_STARTUP (0x3f << 24) /**< \brief (DACC_MR) Startup Time Selection */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1 << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1 << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +#define DACC_CHER_CH2 (0x1 << 2) /**< \brief (DACC_CHER) Channel 2 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1 << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1 << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +#define DACC_CHDR_CH2 (0x1 << 2) /**< \brief (DACC_CHDR) Channel 2 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1 << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1 << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_CH2 (0x1 << 2) /**< \brief (DACC_CHSR) Channel 2 Status */ +/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ +#define DACC_CDR_DATA (0xffffffff << 0) /**< \brief (DACC_CDR) Data to Convert */ +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY (0x1 << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ +#define DACC_IER_EOC (0x1 << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ +#define DACC_IER_ENDTX (0x1 << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ +#define DACC_IER_TXBUFE (0x1 << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY (0x1 << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ +#define DACC_IDR_EOC (0x1 << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ +#define DACC_IDR_ENDTX (0x1 << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ +#define DACC_IDR_TXBUFE (0x1 << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY (0x1 << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ +#define DACC_IMR_EOC (0x1 << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ +#define DACC_IMR_ENDTX (0x1 << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ +#define DACC_IMR_TXBUFE (0x1 << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY (0x1 << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ +#define DACC_ISR_EOC (0x1 << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ +#define DACC_ISR_ENDTX (0x1 << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ +#define DACC_ISR_TXBUFE (0x1 << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0 (0x3 << 0) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1 (0x3 << 2) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLDACCORE (0x3 << 8) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ +#define DACC_WPMR_WPEN (0x1 << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ +#define DACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (DACC_WPMR) Write Protect KEY */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ +#define DACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (DACC_WPSR) Write protection error */ +#define DACC_WPSR_WPROTADDR (0xff << 8) /**< \brief (DACC_WPSR) Write protection error address */ +/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ +#define DACC_RPR_RXPTR (0xffffffff << 0) /**< \brief (DACC_RPR) Receive Pointer Register */ +/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ +#define DACC_RCR_RXCTR (0xffff << 0) /**< \brief (DACC_RCR) Receive Counter Register */ +/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ +#define DACC_TPR_TXPTR (0xffffffff << 0) /**< \brief (DACC_TPR) Transmit Counter Register */ +/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ +#define DACC_TCR_TXCTR (0xffff << 0) /**< \brief (DACC_TCR) Transmit Counter Register */ +/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ +#define DACC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (DACC_RNPR) Receive Next Pointer */ +/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ +#define DACC_RNCR_RXNCTR (0xffff << 0) /**< \brief (DACC_RNCR) Receive Next Counter */ +/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define DACC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (DACC_TNPR) Transmit Next Pointer */ +/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define DACC_TNCR_TXNCTR (0xffff << 0) /**< \brief (DACC_TNCR) Transmit Counter Next */ +/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ +#define DACC_PTCR_RXTEN (0x1 << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ +#define DACC_PTCR_RXTDIS (0x1 << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ +#define DACC_PTCR_TXTEN (0x1 << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ +#define DACC_PTCR_TXTDIS (0x1 << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ +/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ +#define DACC_PTSR_RXTEN (0x1 << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ +#define DACC_PTSR_TXTEN (0x1 << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_EFC Embedded Flash Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Efc hardware registers */ +typedef struct { + RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ +} Efc; +#endif /* __ASSEMBLY__ */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ +#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ +#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ +#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_GPBR General Purpose Backup Register */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Gpbr hardware registers */ +typedef struct { + RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ + RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ + RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ + RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ +} Gpbr; +#endif /* __ASSEMBLY__ */ +/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ +#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ +/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ +#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ +/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ +#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ +/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ +#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Hsmci hardware registers */ +typedef struct { + WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + RwReg Reserved1[2]; + RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + RwReg Reserved2[1]; + RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + RwReg Reserved3[35]; + RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + RwReg Reserved4[5]; + RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ + RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ + RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ + RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ + RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ + RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ + RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ + RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ + WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ + RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ +} Hsmci; +#endif /* __ASSEMBLY__ */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ +#define HSMCI_MR_BLKLEN_Pos 16 +#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */ +#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos))) +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD:74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD:Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command.The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command:Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response:Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request.Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation.This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */ +#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */ +#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */ +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ +#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ +#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ +#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ +#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ +#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_ENDRX (0x1 << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ +#define HSMCI_SR_ENDTX (0x1 << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ +#define HSMCI_SR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ +#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ +#define HSMCI_SR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ +#define HSMCI_SR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ +#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ +#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ +#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ +#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ +#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ +#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ +#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ +#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ +#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ +#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ +#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ +#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_ENDRX (0x1 << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ +#define HSMCI_IER_ENDTX (0x1 << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ +#define HSMCI_IER_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ +#define HSMCI_IDR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ +#define HSMCI_IDR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ +#define HSMCI_IMR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ +#define HSMCI_IMR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ +#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ +/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ +#define HSMCI_RPR_RXPTR (0xffffffff << 0) /**< \brief (HSMCI_RPR) Receive Pointer Register */ +/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ +#define HSMCI_RCR_RXCTR (0xffff << 0) /**< \brief (HSMCI_RCR) Receive Counter Register */ +/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ +#define HSMCI_TPR_TXPTR (0xffffffff << 0) /**< \brief (HSMCI_TPR) Transmit Counter Register */ +/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ +#define HSMCI_TCR_TXCTR (0xffff << 0) /**< \brief (HSMCI_TCR) Transmit Counter Register */ +/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ +#define HSMCI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ +/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ +#define HSMCI_RNCR_RXNCTR (0xffff << 0) /**< \brief (HSMCI_RNCR) Receive Next Counter */ +/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define HSMCI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ +/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define HSMCI_TNCR_TXNCTR (0xffff << 0) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ +/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ +#define HSMCI_PTCR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ +#define HSMCI_PTCR_RXTDIS (0x1 << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ +#define HSMCI_PTCR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ +#define HSMCI_PTCR_TXTDIS (0x1 << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ +/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ +#define HSMCI_PTSR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ +#define HSMCI_PTSR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_MATRIX AHB Bus Matrix */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Matrix hardware registers */ +typedef struct { + RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ + RwReg Reserved1[12]; + RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + RwReg Reserved2[11]; + RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ + RwReg Reserved3[1]; + RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ + RwReg Reserved4[1]; + RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ + RwReg Reserved5[1]; + RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ + RwReg Reserved6[1]; + RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ + RwReg Reserved7[28]; + RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System IO Configuration register */ + RwReg Reserved8[1]; + RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ + RwReg Reserved9[49]; + RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ + RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ +} Matrix; +#endif /* __ASSEMBLY__ */ +/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ +#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ +/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ +#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ +#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ +#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ +/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ +#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ +#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ +#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ +#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ +/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ +#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ +#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ +#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ +#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ +#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ +/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ +#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ +#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ +#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ +#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ +#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ +/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ +#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ +#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ +#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ +#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ +#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ +/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ +#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ +#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ +#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ +#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ +#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System IO Configuration register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1 << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1 << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1 << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1 << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO10 (0x1 << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ +#define CCFG_SYSIO_SYSIO11 (0x1 << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1 << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1 << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1 << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1 << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1 << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1 << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ +#define MATRIX_WPMR_WPKEY (0xffffff << 8) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1 << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ +#define MATRIX_WPSR_WPVSRC (0xffff << 8) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PDC Peripheral DMA Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Pdc hardware registers */ +typedef struct { + RwReg Reserved1[64]; + RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ + RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ + RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ + RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ + RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ + RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ + RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ + RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ + WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ + RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ +} Pdc; +#endif /* __ASSEMBLY__ */ +/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ +#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ +/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ +#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ +/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ +#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ +/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ +#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ +/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ +#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ +/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ +#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ +/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ +/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ +/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ +#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ +#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ +#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ +#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ +/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ +#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ +#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PIO Parallel Input/Output */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Pio hardware registers */ +typedef struct { + WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + RwReg Reserved1[1]; + WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + RwReg Reserved2[1]; + WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + RwReg Reserved3[1]; + WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + RwReg Reserved4[1]; + WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + RwReg Reserved5[1]; + RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + RwReg Reserved6[2]; + WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ + WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ + RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ + RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + RwReg Reserved7[1]; + WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + RwReg Reserved8[1]; + WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ + RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + RwReg Reserved9[1]; + WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + RwReg Reserved10[1]; + WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ + WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ + RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + RwReg Reserved11[1]; + RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ + RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ + RwReg Reserved12[5]; + RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + RwReg Reserved13[19]; + RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ + WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ + WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ + RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ + RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ + RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ + RwReg Reserved14[38]; +} Pio; +#endif /* __ASSEMBLY__ */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1 << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P1 (0x1 << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P2 (0x1 << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P3 (0x1 << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P4 (0x1 << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P5 (0x1 << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P6 (0x1 << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P7 (0x1 << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P8 (0x1 << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P9 (0x1 << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P10 (0x1 << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P11 (0x1 << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P12 (0x1 << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P13 (0x1 << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P14 (0x1 << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P15 (0x1 << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P16 (0x1 << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P17 (0x1 << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P18 (0x1 << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P19 (0x1 << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P20 (0x1 << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P21 (0x1 << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P22 (0x1 << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P23 (0x1 << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P24 (0x1 << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P25 (0x1 << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P26 (0x1 << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P27 (0x1 << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P28 (0x1 << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P29 (0x1 << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P30 (0x1 << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P31 (0x1 << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ +#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ +#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ +#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1 << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P1 (0x1 << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P2 (0x1 << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P3 (0x1 << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P4 (0x1 << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P5 (0x1 << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P6 (0x1 << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P7 (0x1 << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P8 (0x1 << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P9 (0x1 << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P10 (0x1 << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P11 (0x1 << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P12 (0x1 << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P13 (0x1 << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P14 (0x1 << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P15 (0x1 << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P16 (0x1 << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P17 (0x1 << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P18 (0x1 << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P19 (0x1 << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P20 (0x1 << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P21 (0x1 << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P22 (0x1 << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P23 (0x1 << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P24 (0x1 << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P25 (0x1 << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P26 (0x1 << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P27 (0x1 << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P28 (0x1 << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P29 (0x1 << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P30 (0x1 << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P31 (0x1 << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1 << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P1 (0x1 << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P2 (0x1 << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P3 (0x1 << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P4 (0x1 << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P5 (0x1 << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P6 (0x1 << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P7 (0x1 << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P8 (0x1 << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P9 (0x1 << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P10 (0x1 << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P11 (0x1 << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P12 (0x1 << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P13 (0x1 << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P14 (0x1 << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P15 (0x1 << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P16 (0x1 << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P17 (0x1 << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P18 (0x1 << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P19 (0x1 << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P20 (0x1 << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P21 (0x1 << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P22 (0x1 << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P23 (0x1 << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P24 (0x1 << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P25 (0x1 << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P26 (0x1 << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P27 (0x1 << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P28 (0x1 << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P29 (0x1 << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P30 (0x1 << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P31 (0x1 << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1 << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P1 (0x1 << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P2 (0x1 << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P3 (0x1 << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P4 (0x1 << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P5 (0x1 << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P6 (0x1 << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P7 (0x1 << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P8 (0x1 << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P9 (0x1 << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P10 (0x1 << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P11 (0x1 << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P12 (0x1 << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P13 (0x1 << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P14 (0x1 << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P15 (0x1 << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P16 (0x1 << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P17 (0x1 << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P18 (0x1 << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P19 (0x1 << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P20 (0x1 << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P21 (0x1 << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P22 (0x1 << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P23 (0x1 << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P24 (0x1 << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P25 (0x1 << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P26 (0x1 << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P27 (0x1 << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P28 (0x1 << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P29 (0x1 << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P30 (0x1 << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P31 (0x1 << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ +#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ +#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ +#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1 << 0) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT1 (0x1 << 1) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT2 (0x1 << 2) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT3 (0x1 << 3) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT4 (0x1 << 4) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT5 (0x1 << 5) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT6 (0x1 << 6) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT7 (0x1 << 7) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT8 (0x1 << 8) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT9 (0x1 << 9) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT10 (0x1 << 10) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT11 (0x1 << 11) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT12 (0x1 << 12) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT13 (0x1 << 13) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT14 (0x1 << 14) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT15 (0x1 << 15) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT16 (0x1 << 16) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT17 (0x1 << 17) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT18 (0x1 << 18) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT19 (0x1 << 19) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT20 (0x1 << 20) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT21 (0x1 << 21) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT22 (0x1 << 22) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT23 (0x1 << 23) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT24 (0x1 << 24) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT25 (0x1 << 25) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT26 (0x1 << 26) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT27 (0x1 << 27) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT28 (0x1 << 28) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT29 (0x1 << 29) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT30 (0x1 << 30) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT31 (0x1 << 31) /**< \brief (PIO_SCHMITT) */ +/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1 << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE (0x3 << 4) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_ALWYS (0x1 << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1 << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1 << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1 << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1 << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1 << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1 << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1 << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1 << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1 << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1 << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1 << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ +#define PIO_PCISR_ENDRX (0x1 << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ +#define PIO_PCISR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ +/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA (0xffffffff << 0) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PMC Power Management Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Pmc hardware registers */ +typedef struct { + WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + RwReg Reserved1[1]; + WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + RwReg Reserved2[1]; + RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ + RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + RwReg Reserved3[1]; + RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + RwReg Reserved4[1]; + RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + RwReg Reserved5[5]; + WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + RwReg Reserved6[26]; + RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ + RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ + RwReg Reserved7[5]; + WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + RwReg Reserved8[1]; + RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ +} Pmc; +#endif /* __ASSEMBLY__ */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_UDP (0x1 << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ +#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_UDP (0x1 << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ +#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_UDP (0x1 << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ +#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID2 (0x1 << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ +#define PMC_PCER0_PID3 (0x1 << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ +#define PMC_PCER0_PID4 (0x1 << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ +#define PMC_PCER0_PID5 (0x1 << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ +#define PMC_PCER0_PID6 (0x1 << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ +#define PMC_PCER0_PID7 (0x1 << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1 << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1 << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1 << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1 << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1 << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1 << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1 << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1 << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1 << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1 << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1 << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1 << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1 << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1 << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1 << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1 << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1 << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1 << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1 << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1 << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1 << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1 << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1 << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1 << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID2 (0x1 << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ +#define PMC_PCDR0_PID3 (0x1 << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ +#define PMC_PCDR0_PID4 (0x1 << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ +#define PMC_PCDR0_PID5 (0x1 << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ +#define PMC_PCDR0_PID6 (0x1 << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ +#define PMC_PCDR0_PID7 (0x1 << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1 << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1 << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1 << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1 << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1 << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1 << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1 << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1 << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1 << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1 << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1 << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1 << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1 << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1 << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1 << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1 << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1 << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1 << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1 << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1 << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1 << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1 << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1 << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1 << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID2 (0x1 << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ +#define PMC_PCSR0_PID3 (0x1 << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ +#define PMC_PCSR0_PID4 (0x1 << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ +#define PMC_PCSR0_PID5 (0x1 << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ +#define PMC_PCSR0_PID6 (0x1 << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ +#define PMC_PCSR0_PID7 (0x1 << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1 << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1 << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1 << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1 << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1 << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1 << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1 << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1 << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1 << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1 << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1 << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1 << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1 << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1 << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1 << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1 << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1 << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1 << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1 << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1 << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1 << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1 << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1 << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1 << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ +#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ +#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ +#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ +/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ +#define CKGR_PLLBR_DIVB_Pos 0 +#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */ +#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos))) +#define CKGR_PLLBR_PLLBCOUNT_Pos 8 +#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */ +#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos))) +#define CKGR_PLLBR_MULB_Pos 16 +#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ +#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos))) +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */ +#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PLLADIV2 (0x1 << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ +#define PMC_MCKR_PLLBDIV2 (0x1 << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ +#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_LOCKB (0x1 << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_LOCKB (0x1 << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ +#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_LOCKB (0x1 << 2) /**< \brief (PMC_SR) PLLB Lock Status */ +#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_LOCKB (0x1 << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1 << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ +#define PMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (PMC_WPMR) Write Protect KEY */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ +#define PMC_WPSR_WPVS (0x1 << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (PMC_WPSR) Write Protect Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1 << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1 << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1 << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1 << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID36 (0x1 << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ +#define PMC_PCER1_PID37 (0x1 << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID38 (0x1 << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ +#define PMC_PCER1_PID39 (0x1 << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1 << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1 << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1 << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1 << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1 << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1 << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1 << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1 << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1 << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1 << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1 << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1 << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1 << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1 << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID54 (0x1 << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ +#define PMC_PCER1_PID55 (0x1 << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ +#define PMC_PCER1_PID56 (0x1 << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1 << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1 << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1 << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1 << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +#define PMC_PCER1_PID61 (0x1 << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ +#define PMC_PCER1_PID62 (0x1 << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ +#define PMC_PCER1_PID63 (0x1 << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1 << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1 << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1 << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1 << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID36 (0x1 << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ +#define PMC_PCDR1_PID37 (0x1 << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID38 (0x1 << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ +#define PMC_PCDR1_PID39 (0x1 << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1 << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1 << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1 << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1 << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1 << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1 << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1 << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1 << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1 << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1 << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1 << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1 << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1 << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1 << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID54 (0x1 << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ +#define PMC_PCDR1_PID55 (0x1 << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ +#define PMC_PCDR1_PID56 (0x1 << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1 << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1 << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1 << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1 << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +#define PMC_PCDR1_PID61 (0x1 << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ +#define PMC_PCDR1_PID62 (0x1 << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ +#define PMC_PCDR1_PID63 (0x1 << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1 << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1 << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1 << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1 << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID36 (0x1 << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ +#define PMC_PCSR1_PID37 (0x1 << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID38 (0x1 << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ +#define PMC_PCSR1_PID39 (0x1 << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1 << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1 << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1 << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1 << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1 << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1 << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1 << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1 << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1 << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1 << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1 << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1 << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1 << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1 << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID54 (0x1 << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ +#define PMC_PCSR1_PID55 (0x1 << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ +#define PMC_PCSR1_PID56 (0x1 << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1 << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1 << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1 << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1 << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +#define PMC_PCSR1_PID61 (0x1 << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ +#define PMC_PCSR1_PID62 (0x1 << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ +#define PMC_PCSR1_PID63 (0x1 << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4 (0x7f << 0) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ +#define PMC_OCR_SEL4 (0x1 << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ +#define PMC_OCR_CAL8 (0x7f << 8) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ +#define PMC_OCR_SEL8 (0x1 << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ +#define PMC_OCR_CAL12 (0x7f << 16) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ +#define PMC_OCR_SEL12 (0x1 << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief PwmCh_num hardware registers */ +typedef struct { + RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + RwReg PWM_CPDR; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + RwReg PWM_CPDRUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief Pwm hardware registers */ +typedef struct { + RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + RwReg Reserved1[1]; + RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ + RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + RwReg Reserved2[3]; + RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + RwReg Reserved3[11]; + RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + RwReg Reserved4[12]; + WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ + RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ + RwReg Reserved5[5]; + RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ + RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ + RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ + RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ + RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ + RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ + RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ + RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ + WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ + RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ + RwReg Reserved6[2]; + RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ + WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ + RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ + WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ + RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ + WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ + RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ + WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ + RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ + WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ + RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ + WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ + RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ + WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ + RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ + WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ + RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ + WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ + RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ + WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ + RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ + WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ + RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ + WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ + RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ + WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ + RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ + WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ + RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ + WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ + RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ + WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ + RwReg Reserved7[20]; + PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ +} Pwm; +#endif /* __ASSEMBLY__ */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ +#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ +#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ +#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ +#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ +#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ +#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ +#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ +#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ +#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ +#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ +#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ +#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ +#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ +#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ +#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ +#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ +#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ +#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ +#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ +#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ +#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ +#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ +#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ +#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ +#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ +#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ +#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ +#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ +/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ +#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ +#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ +#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ +#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ +/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ +#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ +#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ +#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ +#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ +#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ +#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ +#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1 << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1 << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1 << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1 << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ +#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ +#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ +#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ +#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ +/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ +#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ +/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ +#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ +/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ +#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ +/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ +#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ +/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ +#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ +/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ +#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ +/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ +#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ +/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ +#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ +#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ +#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ +#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ +/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ +#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ +#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ +/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ +#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ +#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ +/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ +#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ +#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ +#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ +#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ +#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ +#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ +/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ +#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ +#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ +#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ +#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ +#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ +/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ +#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ +#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ +#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ +#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ +#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ +#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ +#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ +#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ +/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ +#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ +#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ +#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ +#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ +#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ +#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ +/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ +#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ +#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ +#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ +#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ +#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ +#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ +#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ +#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ +/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ +#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ +#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ +#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ +#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ +#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ +#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ +/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ +#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ +#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ +#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ +#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ +#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ +#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ +#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ +#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ +/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ +#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ +#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ +#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ +#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ +#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ +#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ +/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ +#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ +#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ +#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ +#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ +#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ +#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ +#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ +#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ +/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ +#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ +#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ +#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ +#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ +#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ +#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ +/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ +#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ +#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ +#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ +#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ +#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ +#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ +#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ +#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ +/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ +#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ +#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ +#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ +#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ +#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ +#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ +/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ +#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ +#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ +#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ +#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ +#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ +#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ +#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ +#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ +/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ +#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ +#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ +#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ +#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ +#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ +#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ +/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ +#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ +#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ +#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ +#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ +#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ +#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ +#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ +#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ +/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ +#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ +#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ +#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ +#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ +#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ +#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ +#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ +#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ +#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ +#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ +#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ +#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ +#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ +/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ +#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ +/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ +#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ +/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ +#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ +#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ +#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ +/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ +#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ +#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ +#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ +#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ +#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ +#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ +#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ +#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ +#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ +/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ +#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ +/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ +#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ +/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ +#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ +#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ +#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ +/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ +#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ +#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ +#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ +#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ +#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ +#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ +#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ +#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ +#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ +/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ +#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ +/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ +#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ +/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ +#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ +#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ +#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ +/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ +#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ +#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ +#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ +#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ +#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ +#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ +#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ +#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ +#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ +/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ +#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ +/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ +#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ +/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ +#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ +#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ +#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_RSTC Reset Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Rstc hardware registers */ +typedef struct { + WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* __ASSEMBLY__ */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ +#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_RTC Real-time Clock */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Rtc hardware registers */ +typedef struct { + RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ +} Rtc; +#endif /* __ASSEMBLY__ */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ +#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ +#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ +#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ +#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ +#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_RTT Real-time Timer */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Rtt hardware registers */ +typedef struct { + RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* __ASSEMBLY__ */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ +#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SMC Static Memory Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief SmcCs_number hardware registers */ +typedef struct { + RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +typedef struct { + SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */ + RwReg Reserved1[12]; + RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + RwReg Reserved2[22]; + RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ + RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ +} Smc; +#endif /* __ASSEMBLY__ */ +/* -------- SMC_SETUP0 : (SMC Offset: 0x0) SMC Setup Register (CS_number = 0) -------- */ +#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup Length */ +#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup Length in WRITE Access */ +#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup Length */ +#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE0 : (SMC Offset: 0x4) SMC Pulse Register (CS_number = 0) -------- */ +#define SMC_PULSE0_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ +#define SMC_PULSE0_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE0_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ +#define SMC_PULSE0_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE0 : (SMC Offset: 0x8) SMC Cycle Register (CS_number = 0) -------- */ +#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ +#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ +/* -------- SMC_MODE0 : (SMC Offset: 0xC) SMC Mode Register (CS_number = 0) -------- */ +#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ +#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ +#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ +#define SMC_MODE0_DBW (0x3 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ +#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ +#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ +#define SMC_MODE0_PMEN (0x1 << 24) /**< \brief (SMC_MODE0) Page Mode Enabled */ +#define SMC_MODE0_PS (0x3 << 28) /**< \brief (SMC_MODE0) Page Size */ +/* -------- SMC_SETUP1 : (SMC Offset: 0x10) SMC Setup Register (CS_number = 1) -------- */ +#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup Length */ +#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup Length in WRITE Access */ +#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup Length */ +#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE1 : (SMC Offset: 0x14) SMC Pulse Register (CS_number = 1) -------- */ +#define SMC_PULSE1_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ +#define SMC_PULSE1_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE1_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ +#define SMC_PULSE1_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE1 : (SMC Offset: 0x18) SMC Cycle Register (CS_number = 1) -------- */ +#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ +#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ +/* -------- SMC_MODE1 : (SMC Offset: 0x1C) SMC Mode Register (CS_number = 1) -------- */ +#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ +#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ +#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ +#define SMC_MODE1_DBW (0x3 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ +#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ +#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ +#define SMC_MODE1_PMEN (0x1 << 24) /**< \brief (SMC_MODE1) Page Mode Enabled */ +#define SMC_MODE1_PS (0x3 << 28) /**< \brief (SMC_MODE1) Page Size */ +/* -------- SMC_SETUP2 : (SMC Offset: 0x20) SMC Setup Register (CS_number = 2) -------- */ +#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup Length */ +#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup Length in WRITE Access */ +#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup Length */ +#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE2 : (SMC Offset: 0x24) SMC Pulse Register (CS_number = 2) -------- */ +#define SMC_PULSE2_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ +#define SMC_PULSE2_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE2_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ +#define SMC_PULSE2_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE2 : (SMC Offset: 0x28) SMC Cycle Register (CS_number = 2) -------- */ +#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ +#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ +/* -------- SMC_MODE2 : (SMC Offset: 0x2C) SMC Mode Register (CS_number = 2) -------- */ +#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ +#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ +#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ +#define SMC_MODE2_DBW (0x3 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ +#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ +#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ +#define SMC_MODE2_PMEN (0x1 << 24) /**< \brief (SMC_MODE2) Page Mode Enabled */ +#define SMC_MODE2_PS (0x3 << 28) /**< \brief (SMC_MODE2) Page Size */ +/* -------- SMC_SETUP3 : (SMC Offset: 0x30) SMC Setup Register (CS_number = 3) -------- */ +#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup Length */ +#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup Length in WRITE Access */ +#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup Length */ +#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE3 : (SMC Offset: 0x34) SMC Pulse Register (CS_number = 3) -------- */ +#define SMC_PULSE3_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ +#define SMC_PULSE3_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE3_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ +#define SMC_PULSE3_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE3 : (SMC Offset: 0x38) SMC Cycle Register (CS_number = 3) -------- */ +#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ +#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ +/* -------- SMC_MODE3 : (SMC Offset: 0x3C) SMC Mode Register (CS_number = 3) -------- */ +#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ +#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ +#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ +#define SMC_MODE3_DBW (0x3 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ +#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ +#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ +#define SMC_MODE3_PMEN (0x1 << 24) /**< \brief (SMC_MODE3) Page Mode Enabled */ +#define SMC_MODE3_PS (0x3 << 28) /**< \brief (SMC_MODE3) Page Size */ +/* -------- SMC_SETUP4 : (SMC Offset: 0x40) SMC Setup Register (CS_number = 4) -------- */ +#define SMC_SETUP4_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP4) NWE Setup Length */ +#define SMC_SETUP4_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP4) NCS Setup Length in WRITE Access */ +#define SMC_SETUP4_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP4) NRD Setup Length */ +#define SMC_SETUP4_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP4) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE4 : (SMC Offset: 0x44) SMC Pulse Register (CS_number = 4) -------- */ +#define SMC_PULSE4_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE4) NWE Pulse Length */ +#define SMC_PULSE4_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE4) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE4_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE4) NRD Pulse Length */ +#define SMC_PULSE4_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE4) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE4 : (SMC Offset: 0x48) SMC Cycle Register (CS_number = 4) -------- */ +#define SMC_CYCLE4_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE4) Total Write Cycle Length */ +#define SMC_CYCLE4_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE4) Total Read Cycle Length */ +/* -------- SMC_MODE4 : (SMC Offset: 0x4C) SMC Mode Register (CS_number = 4) -------- */ +#define SMC_MODE4_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE4) */ +#define SMC_MODE4_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE4) */ +#define SMC_MODE4_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE4) NWAIT Mode */ +#define SMC_MODE4_DBW (0x3 << 12) /**< \brief (SMC_MODE4) Data Bus Width */ +#define SMC_MODE4_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE4) Data Float Time */ +#define SMC_MODE4_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE4) TDF Optimization */ +#define SMC_MODE4_PMEN (0x1 << 24) /**< \brief (SMC_MODE4) Page Mode Enabled */ +#define SMC_MODE4_PS (0x3 << 28) /**< \brief (SMC_MODE4) Page Size */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_CS0SE (0x1 << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS1SE (0x1 << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS2SE (0x1 << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS3SE (0x1 << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1 << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SMC_WPMR) Write Protect KEY */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ +#define SMC_WPSR_WPVS (0x1 << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ +#define SMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protect Violation Source */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SPI Serial Peripheral Interface */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Spi hardware registers */ +typedef struct { + WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + RwReg Reserved1[4]; + RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + RwReg Reserved2[41]; + RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ + RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ + RwReg Reserved3[5]; + RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ + RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ + RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ + RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ + RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ + RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ + RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ + RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ + WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ + RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ +} Spi, AT91S_SPI, *AT91PS_SPI; +#endif /* __ASSEMBLY__ */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ +#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ +#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ +#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ +#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ +#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ +#define SPI_SR_ENDRX (0x1 << 4) /**< \brief (SPI_SR) End of RX buffer */ +#define SPI_SR_ENDTX (0x1 << 5) /**< \brief (SPI_SR) End of TX buffer */ +#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) RX Buffer Full */ +#define SPI_SR_TXBUFE (0x1 << 7) /**< \brief (SPI_SR) TX Buffer Empty */ +#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ +#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ +#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ +#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_ENDRX (0x1 << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ +#define SPI_IER_ENDTX (0x1 << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ +#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ +#define SPI_IER_TXBUFE (0x1 << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ +#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_ENDRX (0x1 << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ +#define SPI_IDR_ENDTX (0x1 << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ +#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ +#define SPI_IDR_TXBUFE (0x1 << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ +#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_ENDRX (0x1 << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ +#define SPI_IMR_ENDTX (0x1 << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ +#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ +#define SPI_IMR_TXBUFE (0x1 << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ +#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 35.) */ +#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ +#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ +#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ +#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ +#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ +#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ +#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ +#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ +#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ +#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ +#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ +#define SPI_WPMR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */ +#define SPI_WPMR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ +#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ +/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ +#define SPI_RPR_RXPTR (0xffffffff << 0) /**< \brief (SPI_RPR) Receive Pointer Register */ +/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ +#define SPI_RCR_RXCTR (0xffff << 0) /**< \brief (SPI_RCR) Receive Counter Register */ +/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ +#define SPI_TPR_TXPTR (0xffffffff << 0) /**< \brief (SPI_TPR) Transmit Counter Register */ +/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ +#define SPI_TCR_TXCTR (0xffff << 0) /**< \brief (SPI_TCR) Transmit Counter Register */ +/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ +#define SPI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SPI_RNPR) Receive Next Pointer */ +/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ +#define SPI_RNCR_RXNCTR (0xffff << 0) /**< \brief (SPI_RNCR) Receive Next Counter */ +/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define SPI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SPI_TNPR) Transmit Next Pointer */ +/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define SPI_TNCR_TXNCTR (0xffff << 0) /**< \brief (SPI_TNCR) Transmit Counter Next */ +/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ +#define SPI_PTCR_RXTEN (0x1 << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ +#define SPI_PTCR_RXTDIS (0x1 << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ +#define SPI_PTCR_TXTEN (0x1 << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ +#define SPI_PTCR_TXTDIS (0x1 << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ +/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ +#define SPI_PTSR_RXTEN (0x1 << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ +#define SPI_PTSR_TXTEN (0x1 << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SSC Synchronous Serial Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Ssc hardware registers */ +typedef struct { + WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + RwReg Reserved1[2]; + RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + RwReg Reserved2[2]; + RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + RwReg Reserved3[37]; + RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ + RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ + RwReg Reserved4[5]; + RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ + RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ + RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ + RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ + RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ + RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ + RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ + RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ + WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ + RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ +} Ssc; +#endif /* __ASSEMBLY__ */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ +#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ +#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ +#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ +#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ +#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ +#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ +#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ +#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ +#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ +#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ +#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ +#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ +#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ +#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ +#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ +#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ +#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ +#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ +#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ +/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ +#define SSC_RPR_RXPTR (0xffffffff << 0) /**< \brief (SSC_RPR) Receive Pointer Register */ +/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ +#define SSC_RCR_RXCTR (0xffff << 0) /**< \brief (SSC_RCR) Receive Counter Register */ +/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ +#define SSC_TPR_TXPTR (0xffffffff << 0) /**< \brief (SSC_TPR) Transmit Counter Register */ +/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ +#define SSC_TCR_TXCTR (0xffff << 0) /**< \brief (SSC_TCR) Transmit Counter Register */ +/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ +#define SSC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SSC_RNPR) Receive Next Pointer */ +/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ +#define SSC_RNCR_RXNCTR (0xffff << 0) /**< \brief (SSC_RNCR) Receive Next Counter */ +/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define SSC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SSC_TNPR) Transmit Next Pointer */ +/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define SSC_TNCR_TXNCTR (0xffff << 0) /**< \brief (SSC_TNCR) Transmit Counter Next */ +/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ +#define SSC_PTCR_RXTEN (0x1 << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ +#define SSC_PTCR_RXTDIS (0x1 << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ +#define SSC_PTCR_TXTEN (0x1 << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ +#define SSC_PTCR_TXTDIS (0x1 << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ +/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ +#define SSC_PTSR_RXTEN (0x1 << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ +#define SSC_PTSR_TXTEN (0x1 << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SUPC Supply Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Supc hardware registers */ +typedef struct { + WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ + RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ + RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* __ASSEMBLY__ */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ +#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ +#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ +#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ +#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ +#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ +#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ +#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ +#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ +#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ +#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ +#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ +#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ +#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ +#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ +#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ +#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0 << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ +#define SUPC_MR_ONREG_ONREG_USED (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ +#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ +#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ +#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ +#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ +#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ +#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ +#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ +#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ +#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ +#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ +#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ +#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ +#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ +#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ +#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ +#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ +#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ +#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ +#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ +#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ +#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ +#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ +#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ +#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ +#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ +#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ +#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ +#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ +#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ +#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ +#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ +#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ +#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ +#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ +#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ +#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ +#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ +#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ +#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ +#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ +#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ +#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ +#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ +#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ +#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ +#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ +#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ +#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ +#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ +#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ +#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ +#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ +#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ +#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ +#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ +#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ +#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ +#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_TC Timer Counter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief TcChannel hardware registers */ +typedef struct { + RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + RwReg Reserved1[2]; + RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + RwReg Reserved2[4]; +} TcChannel; +/** \brief Tc hardware registers */ +typedef struct { + TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + RwReg Reserved1[2]; + RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ + RwReg Reserved2[5]; + RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ +} Tc; +#endif /* __ASSEMBLY__ */ +/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ + +#define TC_CCR_CLKEN TC_CCR0_CLKEN /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS TC_CCR0_CLKDIS /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG TC_CCR0_SWTRG /**< \brief (TC_CCR) Software Trigger Command */ + +#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ +#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ +#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ +/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ +#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ +#define TC_CM0_TCCLKS_TIMER_DIV1_CLOCK (0x0 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV1_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV2_CLOCK (0x1 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV2_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV3_CLOCK (0x2 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV3_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV4_CLOCK (0x3 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV4_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV5_CLOCK (0x4 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV5_CLOCK*/ +#define TC_CM0_TCCLKS_XC0 (0x5 << 0) /**< (TC_CMR0) Clock selected: XC0*/ +#define TC_CM0_TCCLKS_XC1 (0x6 << 0) /**< (TC_CMR0) Clock selected: XC1*/ +#define TC_CM0_TCCLKS_XC2 (0x7 << 0) /**< (TC_CMR0) Clock selected: XC2*/ +#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ +#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ +#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ +#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ +#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ +#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ +#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ +#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ +#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ +#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ +#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ +#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ +#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ +#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ + +#define TC_CMR_CPCTRG TC_CMR0_CPCTRG +#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ +#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ +#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ +#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ +#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ +#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ +#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ +#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ +#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ +#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ +#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ +#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ + +#define TC_CMR0_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define TC_CMR0_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define TC_CMR0_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define TC_CMR0_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle + +#define TC_CMR0_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define TC_CMR0_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define TC_CMR0_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define TC_CMR0_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ +#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ +/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ +#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ +/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ +#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ +/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ +#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ +/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ +#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ +#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ +#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ +#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ +#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ +#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ +#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ +#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ +#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ +#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ +#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ +/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ +#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ +#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ +#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ +#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ + +#define TC_IER_CPCS TC_IER0_CPCS +#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ +#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ +#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ +#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ +/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ +#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ +#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ +#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ +#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ +#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ +#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ +#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ +#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ +/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ +#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ +#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ +#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ +#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ +#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ +#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ +#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ +#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ +/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ +#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ +#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ +#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ +/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ +#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ +#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ +#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ +#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ +#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ +#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ +#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ +#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ +#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ +#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ +#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ +#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ +#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ +#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ +#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ +#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ +#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ +#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ +#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ +#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ +#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ +#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ +#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ +#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ +#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ +#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ +#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ +/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ +#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ +/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ +#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ +/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ +#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ +/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ +#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ +/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ +#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ +#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ +#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ +#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ +#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ +#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ +#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ +#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ +#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ +#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ +#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ +/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ +#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ +#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ +#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ +#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ +#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ +#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ +#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ +#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ +/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ +#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ +#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ +#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ +#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ +#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ +#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ +#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ +#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ +/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ +#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ +#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ +#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ +#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ +#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ +#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ +#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ +#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ +/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ +#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ +#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ +#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ +/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ +#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ +#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ +#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ +#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ +#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ +#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ +#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ +#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ +#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ +#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ +#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ +#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ +#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ +#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ +#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ +#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ +#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ +#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ +#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ +#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ +#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ +#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ +#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ +#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ +#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ +#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ +#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ +/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ +#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ +/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ +#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ +/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ +#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ +/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ +#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ +/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ +#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ +#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ +#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ +#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ +#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ +#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ +#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ +#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ +#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ +#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ +#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ +/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ +#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ +#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ +#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ +#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ +#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ +#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ +#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ +#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ +/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ +#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ +#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ +#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ +#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ +#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ +#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ +#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ +#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ +/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ +#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ +#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ +#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ +#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ +#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ +#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ +#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ +#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ +#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ +#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ +#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ +#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ +#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ +#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ +#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ +#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ +#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ +#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ +#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ +#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ +#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ +#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ +#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ +#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ +#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ +#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ +#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ +#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ +#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ +#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ +#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ +#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ +#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ +#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1 << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1 << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ +#define TC_WPMR_WPEN (0x1 << 0) /**< \brief (TC_WPMR) Write Protect Enable */ +#define TC_WPMR_WPKEY (0xffffff << 8) /**< \brief (TC_WPMR) Write Protect KEY */ +/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ +#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ +#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_TWI Two-wire Interface */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Twi hardware registers */ +typedef struct { + WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ + RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ + RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ + RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ + RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ + RwReg Reserved1[3]; + RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ + WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ + WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ + RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ + RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ + WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ + RwReg Reserved2[50]; + RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ + RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ + RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ + RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ + RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ + RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ + RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ + RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ + WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ + RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ +} Twi; +#endif /* __ASSEMBLY__ */ +/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ +#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ +#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ +#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ +#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ +#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ +#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ +#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ +#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ +#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ #define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ #define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) -#define TWI_MMR_IADRSZ_Pos 8 -#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ +#define TWI_MMR_IADRSZ_Pos 8 +#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ #define TWI_MMR_DADR_Pos 16 #define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ -#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) -/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ +#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) +/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ #define TWI_SMR_SADR_Pos 16 #define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ -#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) -/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ +#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) +/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ #define TWI_IADR_IADR_Pos 0 #define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ -#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) -/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) +/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ #define TWI_CWGR_CLDIV_Pos 0 #define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ #define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) @@ -5348,1805 +5348,1805 @@ typedef struct { #define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) #define TWI_CWGR_CKDIV_Pos 16 #define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ -#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) -/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ -#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ -#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ -#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ -#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ -#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ -#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ -#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ -#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ -#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ -#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ -#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ -#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ -#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ -#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ -#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ -/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ -#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ -#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ -#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ -#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ -#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ -#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ -#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ -#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ -#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ -#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ -#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ -#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ -#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ -#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ -#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ -#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ -#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ -#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ -#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ -#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ -#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ -#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ -#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ -#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ -#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ -#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ -#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ -#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ -#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ -#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ -#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ -#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ -#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ -#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ -#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ -#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ -#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ -#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ -#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ -#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ -#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ -#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ -#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ -/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ -#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ -/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ -#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ -/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ -#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ -/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ -#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ -/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ -#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ -/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ -#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ -/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ -#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ -/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ -/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ -/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ -#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ -#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ -#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ -#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ -/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ -#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UART Universal Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Uart hardware registers */ -typedef struct { - WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ - RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ - WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ - WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ - RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ - RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ - RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ - WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ - RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ - RwReg Reserved1[55]; - RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ - RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ - RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ - RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ - RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ - RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ - RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ - RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ - WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ - RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ -} Uart; -#endif /* __ASSEMBLY__ */ -/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ -#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ -#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ -#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ -#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ -#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ -#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ -#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ -/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ -#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ -#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ -/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ -#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ -#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ -#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ -#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ -#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ -#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ -#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ -#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ -#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ -#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ -/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ -#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ -#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ -#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ -#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ -#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ -#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ -#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ -#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ -#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ -#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ -/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ -#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ -#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ -#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ -#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ -#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ -#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ -#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ -#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ -#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ -#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ -/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ -#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ -#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ -#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ -#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ -#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ -#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ -#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ -#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ -#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ -#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ -/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ -#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ -/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ -#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ -/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ -/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ -#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ -/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ -#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ -/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ -#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ -/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ -#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ -/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ -#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ -/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ -#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ -/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ -/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ -/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ -#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ -#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ -#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ -#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ -/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ -#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ -#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB Device Port */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UDP USB Device Port */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Udp hardware registers */ -typedef struct { - RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ - RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ - RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ - RwReg Reserved1[1]; - WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ - WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ - RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ - RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ - WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ - RwReg Reserved2[1]; - RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ - RwReg Reserved3[1]; - RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x30) Endpoint Control and Status Register (ept_num = 0) */ - RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x50) Endpoint FIFO Data Register (ept_num = 0) */ - RwReg Reserved4[1]; - RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ -} Udp; -#endif /* __ASSEMBLY__ */ -/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ -#define UDP_FRM_NUM_FRM_NUM (0x7ff << 0) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ -#define UDP_FRM_NUM_FRM_ERR (0x1 << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ -#define UDP_FRM_NUM_FRM_OK (0x1 << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ -/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ -#define UDP_GLB_STAT_FADDEN (0x1 << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ -#define UDP_GLB_STAT_CONFG (0x1 << 1) /**< \brief (UDP_GLB_STAT) Configured */ -#define UDP_GLB_STAT_ESR (0x1 << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ -#define UDP_GLB_STAT_RSMINPR (0x1 << 3) /**< \brief (UDP_GLB_STAT) */ -#define UDP_GLB_STAT_RMWUPE (0x1 << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ -/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ -#define UDP_FADDR_FADD_Pos 0 -#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */ -#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos))) -#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */ -/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ -#define UDP_IER_EP0INT (0x1 << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ -#define UDP_IER_EP1INT (0x1 << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ -#define UDP_IER_EP2INT (0x1 << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ -#define UDP_IER_EP3INT (0x1 << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ -#define UDP_IER_EP4INT (0x1 << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ -#define UDP_IER_EP5INT (0x1 << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ -#define UDP_IER_EP6INT (0x1 << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ -#define UDP_IER_EP7INT (0x1 << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ -#define UDP_IER_RXSUSP (0x1 << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ -#define UDP_IER_RXRSM (0x1 << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ -#define UDP_IER_EXTRSM (0x1 << 10) /**< \brief (UDP_IER) */ -#define UDP_IER_SOFINT (0x1 << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ -#define UDP_IER_WAKEUP (0x1 << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ -/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ -#define UDP_IDR_EP0INT (0x1 << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ -#define UDP_IDR_EP1INT (0x1 << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ -#define UDP_IDR_EP2INT (0x1 << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ -#define UDP_IDR_EP3INT (0x1 << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ -#define UDP_IDR_EP4INT (0x1 << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ -#define UDP_IDR_EP5INT (0x1 << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ -#define UDP_IDR_EP6INT (0x1 << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ -#define UDP_IDR_EP7INT (0x1 << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ -#define UDP_IDR_RXSUSP (0x1 << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ -#define UDP_IDR_RXRSM (0x1 << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ -#define UDP_IDR_EXTRSM (0x1 << 10) /**< \brief (UDP_IDR) */ -#define UDP_IDR_SOFINT (0x1 << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ -#define UDP_IDR_WAKEUP (0x1 << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ -/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ -#define UDP_IMR_EP0INT (0x1 << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ -#define UDP_IMR_EP1INT (0x1 << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ -#define UDP_IMR_EP2INT (0x1 << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ -#define UDP_IMR_EP3INT (0x1 << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ -#define UDP_IMR_EP4INT (0x1 << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ -#define UDP_IMR_EP5INT (0x1 << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ -#define UDP_IMR_EP6INT (0x1 << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ -#define UDP_IMR_EP7INT (0x1 << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ -#define UDP_IMR_RXSUSP (0x1 << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ -#define UDP_IMR_RXRSM (0x1 << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ -#define UDP_IMR_EXTRSM (0x1 << 10) /**< \brief (UDP_IMR) */ -#define UDP_IMR_SOFINT (0x1 << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ -#define UDP_IMR_BIT12 (0x1 << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ -#define UDP_IMR_WAKEUP (0x1 << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ -/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ -#define UDP_ISR_EP0INT (0x1 << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ -#define UDP_ISR_EP1INT (0x1 << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ -#define UDP_ISR_EP2INT (0x1 << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ -#define UDP_ISR_EP3INT (0x1 << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ -#define UDP_ISR_EP4INT (0x1 << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ -#define UDP_ISR_EP5INT (0x1 << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ -#define UDP_ISR_EP6INT (0x1 << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ -#define UDP_ISR_EP7INT (0x1 << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ -#define UDP_ISR_RXSUSP (0x1 << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ -#define UDP_ISR_RXRSM (0x1 << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -#define UDP_ISR_EXTRSM (0x1 << 10) /**< \brief (UDP_ISR) */ -#define UDP_ISR_SOFINT (0x1 << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ -#define UDP_ISR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ -#define UDP_ISR_WAKEUP (0x1 << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ -#define UDP_ICR_RXSUSP (0x1 << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ -#define UDP_ICR_RXRSM (0x1 << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ -#define UDP_ICR_EXTRSM (0x1 << 10) /**< \brief (UDP_ICR) */ -#define UDP_ICR_SOFINT (0x1 << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ -#define UDP_ICR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ -#define UDP_ICR_WAKEUP (0x1 << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ -/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ -#define UDP_RST_EP_EP0 (0x1 << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ -#define UDP_RST_EP_EP1 (0x1 << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ -#define UDP_RST_EP_EP2 (0x1 << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ -#define UDP_RST_EP_EP3 (0x1 << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ -#define UDP_RST_EP_EP4 (0x1 << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ -#define UDP_RST_EP_EP5 (0x1 << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ -#define UDP_RST_EP_EP6 (0x1 << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ -#define UDP_RST_EP_EP7 (0x1 << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ -/* -------- UDP_CSR[8] : (UDP Offset: 0x2C) Endpoint Control and Status Register (ept_num = 0) -------- */ -#define UDP_CSR_TXCOMP (0x1 << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ -#define UDP_CSR_RX_DATA_BK0 (0x1 << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ -#define UDP_CSR_RXSETUP (0x1 << 2) /**< \brief (UDP_CSR[8]) Received Setup */ -#define UDP_CSR_STALLSENTISOERROR (0x1 << 3) /**< \brief (UDP_CSR[8]) */ -#define UDP_CSR_TXPKTRDY (0x1 << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ -#define UDP_CSR_FORCESTALL (0x1 << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ -#define UDP_CSR_RX_DATA_BK1 (0x1 << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ -#define UDP_CSR_DIR (0x1 << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ -#define UDP_CSR_EPTYPE_Pos 8 -#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */ -#define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */ -#define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ -#define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ -#define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ -#define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ -#define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ -#define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ -#define UDP_CSR_DTGLE (0x1 << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ -#define UDP_CSR_EPEDS (0x1 << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ -#define UDP_CSR_RXBYTECNT_Pos 16 -#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ -#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos))) -/* -------- UDP_FDR[8] : (UDP Offset: 0x4C) Endpoint FIFO Data Register (ept_num = 0) -------- */ -#define UDP_FDR_FIFO_DATA (0xff << 0) /**< \brief (UDP_FDR[8]) FIFO Data Value */ -/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ -#define UDP_TXVC_TXVDIS (0x1 << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ -#define UDP_TXVC_PUON (0x1 << 9) /**< \brief (UDP_TXVC) Pullup On */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Usart hardware registers */ -typedef struct { - WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ - RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ - WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ - WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ - RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ - RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ - RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ - WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ - RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ - RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ - RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ - RwReg Reserved1[5]; - RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ - RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ - RwReg Reserved2[1]; - RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ - RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ - RwReg Reserved3[36]; - RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ - RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[4]; - RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ - RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ - RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ - RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ - RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ - RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ - RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ - RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ - RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ - WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ - RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ -} Usart; -#endif /* __ASSEMBLY__ */ -/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ -#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ -#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ -#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ -#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ -#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ -#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ -#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ -#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ -#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ -#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ -#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ -#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ -#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ -#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ -#define US_CR_DTREN (0x1 << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ -#define US_CR_DTRDIS (0x1 << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ -#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ -#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ -/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ -#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ -#define US_MR_USART_MODE_NORMAL (0x0) /**< (USART) Normal*/ -#define US_MR_USART_MODE_RS485 (0x1) /**< (USART) RS485*/ -#define US_MR_USART_MODE_HWHSH (0x2) /**< (USART) Hardware Handshaking*/ -#define US_MR_USART_MODE_ISO7816_0 (0x4) /**< (USART) ISO7816 protocol: T = 0*/ -#define US_MR_USART_MODE_ISO7816_1 (0x6) /**< (USART) ISO7816 protocol: T = 1*/ -#define US_MR_USART_MODE_IRDA (0x8) /**< (USART) IrDA*/ -#define US_MR_USART_MODE_SPIM (0xE) /**< (USART) SPI Master*/ -#define US_MR_USART_MODE_SPIS (0xF) /**< (USART) SPI Slave*/ -#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ -#define US_MR_USCLKS_CLOCK (0x0 << 4) /**< (USART) MCK*/ -#define US_MR_USCLKS_FDIV1 (0x1 << 4) /**< (USART) MCK/DIV(DIV=8)*/ -#define US_MR_USCLKS_SLOW (0x2 << 4) /**< (USART) Reserved*/ -#define US_MR_USCLKS_EXT (0x3 << 4) /**< (USART) SCK*/ -#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ -#define US_MR_CHRL_5_BITS (0x0 << 6) /**< (USART) Character Length: 5 bits*/ -#define US_MR_CHRL_6_BITS (0x1 << 6) /**< (USART) Character Length: 6 bits*/ -#define US_MR_CHRL_7_BITS (0x2 << 6) /**< (USART) Character Length: 7 bits*/ -#define US_MR_CHRL_8_BITS (0x3 << 6) /**< (USART) Character Length: 8 bits*/ -#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ -#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ -#define US_MR_PAR_EVEN (0x0 << 9) /**< (USART) Even Parity*/ -#define US_MR_PAR_ODD (0x1 << 9) /**< (USART) Odd Parity*/ -#define US_MR_PAR_SPACE (0x2 << 9) /**< (USART) Parity forced to 0 (Space)*/ -#define US_MR_PAR_MARK (0x3 << 9) /**< (USART) Parity forced to 1 (Mark)*/ -#define US_MR_PAR_NONE (0x4 << 9) /**< (USART) No Parity*/ -#define US_MR_PAR_MULTI_DROP (0x6 << 9) /**< (USART) Multi-drop mode*/ -#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ -#define US_MR_NBSTOP_1_BIT (0x0 << 12) /**< (USART) 1 stop bit*/ -#define US_MR_NBSTOP_15_BIT (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits*/ -#define US_MR_NBSTOP_2_BIT (0x2 << 12) /**< (USART) 2 stop bits*/ -#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ -#define US_MR_CHMODE_NORMAL (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART.*/ -#define US_MR_CHMODE_AUTO (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/ -#define US_MR_CHMODE_LOCAL (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/ -#define US_MR_CHMODE_REMOTE (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin.*/ -#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ -#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ -#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ -#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ -#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ -#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ -#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ -#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ -#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ -#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ -#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ -#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ -#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ -/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ -#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ -#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ -#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ -#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ -#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ -#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ -#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ -#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ -#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ -#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ -#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ -#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ -#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ -#define US_IER_RIIC (0x1 << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ -#define US_IER_DSRIC (0x1 << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ -#define US_IER_DCDIC (0x1 << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ -#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ -#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ -/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ -#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ -#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ -#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ -#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ -#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ -#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ -#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ -#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ -#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ -#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ -#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ -#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ -#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ -#define US_IDR_RIIC (0x1 << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ -#define US_IDR_DSRIC (0x1 << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ -#define US_IDR_DCDIC (0x1 << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ -#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ -#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ -/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ -#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ -#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ -#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ -#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ -#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ -#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ -#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ -#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ -#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ -#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ -#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ -#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ -#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ -#define US_IMR_RIIC (0x1 << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ -#define US_IMR_DSRIC (0x1 << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ -#define US_IMR_DCDIC (0x1 << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ -#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ -#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ -/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ -#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ -#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ -#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ -#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ -#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ -#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ -#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ -#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ -#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ -#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ -#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ -#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ -#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ -#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ -#define US_CSR_RIIC (0x1 << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ -#define US_CSR_DSRIC (0x1 << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ -#define US_CSR_DCDIC (0x1 << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ -#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ -#define US_CSR_RI (0x1 << 20) /**< \brief (US_CSR) Image of RI Input */ -#define US_CSR_DSR (0x1 << 21) /**< \brief (US_CSR) Image of DSR Input */ -#define US_CSR_DCD (0x1 << 22) /**< \brief (US_CSR) Image of DCD Input */ -#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ -#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ -/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ -#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ -#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ -/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ -#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ -#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ -/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ -#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ -/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ -#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ -/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ -#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ -/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ -#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ -/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ -#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ -/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ -#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ -/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ -#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ -#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ -#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ -#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ -#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ -#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ -#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ -#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ -/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ -#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ -#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ -/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ -#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ -#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ -/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ -#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ -#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ -/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ -#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ -/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ -#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ -/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ -#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ -/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ -#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ -/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ -#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ -/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ -#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ -/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ -/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ -/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ -#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ -#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ -#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ -#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ -/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ -#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_WDT Watchdog Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Wdt hardware registers */ -typedef struct { - WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ - RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ - RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ -} Wdt; -#endif /* __ASSEMBLY__ */ -/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ -#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ -#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ -/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ -#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ -#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ -#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ -#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ -#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ -/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ -#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ -#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ - -/*@}*/ - -/*@}*/ - -/* ***************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_reg Registers Access Definitions */ -/*@{*/ - -/* ========== Register definition for HSMCI peripheral ========== */ -#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ -#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ -#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ -#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ -#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ -#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ -#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ -#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ -#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ -#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ -#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ -#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ -#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ -#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ -#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ -#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ -#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ -#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ -#define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ -#define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ -#define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ -#define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ -#define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ -#define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ -#define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ -#define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ -#define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ -#define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ -/* ========== Register definition for SSC peripheral ========== */ -#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ -#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ -#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ -#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ -#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ -#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ -#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ -#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ -#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ -#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ -#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ -#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ -#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ -#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ -#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ -#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ -#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ -#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ -#define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */ -#define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */ -#define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ -#define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ -#define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ -#define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ -#define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ -#define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ -#define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */ -#define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */ -/* ========== Register definition for SPI peripheral ========== */ -#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ -#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ -#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ -#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ -#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ -#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ -#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ -#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ -#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ -#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ -#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ -#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */ -#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */ -#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ -#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ -#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ -#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ -#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ -#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ -#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */ -#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */ -/* ========== Register definition for TC0 peripheral ========== */ -#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ -#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ -#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ -#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ -#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */ -#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ -#define REG_TC0_VER REG_ACCESS(RoReg, 0x400100FCU) /**< \brief (TC0) Version Register */ -/* ========== Register definition for TC1 peripheral ========== */ -#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ -#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ -#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ -#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ -#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ -#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ -#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ -#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ -#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ -#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ -#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ -#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ -#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ -#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ -#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ -#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ -#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ -#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ -#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ -#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ -#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ -#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ -#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ -#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ -#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ -#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ -#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ -#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ -#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ -#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ -#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */ -#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */ -#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ -#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ -#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ -#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ -#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */ -#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ -#define REG_TC1_VER REG_ACCESS(RoReg, 0x400140FCU) /**< \brief (TC1) Version Register */ -/* ========== Register definition for TWI0 peripheral ========== */ -#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */ -#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */ -#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */ -#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */ -#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ -#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */ -#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ -#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ -#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ -#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */ -#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ -#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */ -/* ========== Register definition for TWI1 peripheral ========== */ -#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */ -#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */ -#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ -#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ -#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ -#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */ -#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ -#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ -#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ -#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ -#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ -#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ -/* ========== Register definition for PWM peripheral ========== */ -#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */ -#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */ -#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */ -#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */ -#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ -#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ -#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ -#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ -#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ -#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ -#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ -#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ -#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ -#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ -#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ -#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ -#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ -#define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ -#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ -#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ -#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ -#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ -#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ -#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ -#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ -#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ -#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ -#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ -#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ -#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ -#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ -#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */ -#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */ -#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ -#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ -#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */ -#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */ -#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ -#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ -#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */ -#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */ -#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ -#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ -#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ -#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ -#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ -#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ -#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ -#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ -#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ -#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ -#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ -#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ -#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ -#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ -#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ -#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ -#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ -#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ -#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ -#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ -#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ -#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ -#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ -#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ -#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ -#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ -#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ -#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ -#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ -#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ -#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ -#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ -#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ -#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ -#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ -#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ -#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ -#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ -#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ -#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ -#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ -#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ -#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ -#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ -#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ -#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ -#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ -#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ -#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ -#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ -#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ -#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ -#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ -#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ -#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ -#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ -#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ -#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ -#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ -#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ -#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ -#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ -#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ -#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ -/* ========== Register definition for USART0 peripheral ========== */ -#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */ -#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */ -#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ -#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ -#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ -#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */ -#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ -#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ -#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ -#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ -#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ -#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ -#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */ -#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ -#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ -#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ -#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ -#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */ -#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */ -/* ========== Register definition for USART1 peripheral ========== */ -#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */ -#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */ -#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ -#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ -#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ -#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */ -#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ -#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ -#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ -#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ -#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ -#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ -#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */ -#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ -#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ -#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ -#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ -#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */ -#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */ -/* ========== Register definition for UDP peripheral ========== */ -#define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */ -#define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */ -#define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */ -#define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ -#define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ -#define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ -#define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ -#define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ -#define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ -#define REG_UDP_CSR REG_ACCESS(RwReg, 0x4003402CU) /**< \brief (UDP) Endpoint Control and Status Register (ept_num = 0) */ -#define REG_UDP_FDR REG_ACCESS(RwReg, 0x4003404CU) /**< \brief (UDP) Endpoint FIFO Data Register (ept_num = 0) */ -#define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */ -/* ========== Register definition for ADC peripheral ========== */ -#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */ -#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */ -#define REG_ADC_SEQ1R REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence 1Register */ -#define REG_ADC_SEQ2R REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence 2 Register */ -#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */ -#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */ -#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */ -#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */ -#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ -#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ -#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ -#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */ -#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */ -#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */ -#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */ -#define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */ -#define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */ -#define REG_ADC_CDR0 REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register 0 */ -#define REG_ADC_CDR1 REG_ACCESS(RoReg, 0x40038054U) /**< \brief (ADC) Channel Data Register 1 */ -#define REG_ADC_CDR2 REG_ACCESS(RoReg, 0x40038058U) /**< \brief (ADC) Channel Data Register 2 */ -#define REG_ADC_CDR3 REG_ACCESS(RoReg, 0x4003805CU) /**< \brief (ADC) Channel Data Register 3 */ -#define REG_ADC_CDR4 REG_ACCESS(RoReg, 0x40038060U) /**< \brief (ADC) Channel Data Register 4 */ -#define REG_ADC_CDR5 REG_ACCESS(RoReg, 0x40038064U) /**< \brief (ADC) Channel Data Register 5 */ -#define REG_ADC_CDR6 REG_ACCESS(RoReg, 0x40038068U) /**< \brief (ADC) Channel Data Register 6 */ -#define REG_ADC_CDR15 REG_ACCESS(RoReg, 0x4003806CU) /**< \brief (ADC) Channel Data Register 15 */ -#define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */ -#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ -#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ -#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */ -#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */ -#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */ -#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */ -#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ -#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ -#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */ -#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */ -#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */ -#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */ -/* ========== Register definition for DACC peripheral ========== */ -#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */ -#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */ -#define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */ -#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */ -#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */ -#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */ -#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ -#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ -#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ -#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ -#define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */ -#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ -#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ -#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */ -#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */ -#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ -#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ -#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */ -#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */ -#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ -#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ -#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */ -#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */ -/* ========== Register definition for ACC peripheral ========== */ -#define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */ -#define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */ -#define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ -#define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ -#define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ -#define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */ -#define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */ -#define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ -#define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ -/* ========== Register definition for CRCCU peripheral ========== */ -#define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ -#define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ -#define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ -#define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ -#define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ -#define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ -#define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ -#define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ -#define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ -#define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ -#define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ -#define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ -#define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ -#define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ -#define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ -/* ========== Register definition for SMC peripheral ========== */ -#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ -#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ -#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ -#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ -#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ -#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ -#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ -#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ -#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ -#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ -#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ -#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ -#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ -#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ -#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ -#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ -#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ -#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ -#define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ -#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ -/* ========== Register definition for MATRIX peripheral ========== */ -#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ -#define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System IO Configuration register */ -#define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ -#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ -#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ -/* ========== Register definition for PMC peripheral ========== */ -#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ -#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ -#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ -#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */ -#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */ -#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ -#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ -#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ -#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ -#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ -#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ -#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ -/* ========== Register definition for UART0 peripheral ========== */ -#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */ -#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */ -#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ -#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ -#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ -#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */ -#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */ -#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ -#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ -#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ -#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */ -#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ -#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ -#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ -#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ -#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ -#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ -#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */ -#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */ -/* ========== Register definition for CHIPID peripheral ========== */ -#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -/* ========== Register definition for UART1 peripheral ========== */ -#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */ -#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */ -#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ -#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ -#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ -#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */ -#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */ -#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ -#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ -#define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ -#define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */ -#define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ -#define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ -#define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ -#define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ -#define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ -#define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ -#define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */ -#define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */ -/* ========== Register definition for EFC peripheral ========== */ -#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ -#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ -#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ -#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ -/* ========== Register definition for PIOA peripheral ========== */ -#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ -#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ -#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ -#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ -#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ -#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ -#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ -#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ -#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ -#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */ -#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ -#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ -#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ -#define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ -#define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ -#define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ -#define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ -#define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ -#define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOB peripheral ========== */ -#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ -#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ -#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ -#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ -#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ -#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ -#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ -#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ -#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ -#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */ -#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ -#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ -#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ -#define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ -#define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ -#define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ -#define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ -#define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ -#define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOC peripheral ========== */ -#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ -#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ -#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */ -#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */ -#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */ -#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */ -#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ -#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ -#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ -#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ -#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ -#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ -#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ -#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ -#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ -#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ -#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ -#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ -#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ -#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ -#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ -#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ -#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ -#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ -#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ -#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ -#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ -#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ -#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ -#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ -#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ -#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ -#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ -#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ -#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ -#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ -#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ -#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */ -#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ -#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ -#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ -#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ -#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */ -#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ -#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ -#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ -#define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ -#define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ -#define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ -#define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ -#define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ -#define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ -/* ========== Register definition for RSTC peripheral ========== */ -#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */ -/* ========== Register definition for SUPC peripheral ========== */ -#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ -#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ -#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ -/* ========== Register definition for RTT peripheral ========== */ -#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */ -/* ========== Register definition for WDT peripheral ========== */ -#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */ -/* ========== Register definition for RTC peripheral ========== */ -#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */ -/* ========== Register definition for GPBR peripheral ========== */ -#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */ -#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */ -#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */ -#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ -/*@}*/ - -/* ***************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ -#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ -#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ -#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ -#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ -#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ -#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ -#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ -#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ -#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ -/*@}*/ - -/* ***************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_base Peripheral Base Address Definitions */ -/*@{*/ - -#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ -#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */ -#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */ -#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */ -#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */ -#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */ -#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */ -#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ -#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ -#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */ - -// indices for three pio structures -#define iPIOA 0 -#define iPIOB 1 -#define iPIOC 2 -/*@}*/ - -/* ***************************************************************************** */ -/* PIO DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_pio Peripheral Pio Definitions */ -/*@{*/ - -#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA28C_MCCDA (1 << 28) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA29C_MCCK (1 << 29) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA30C_MCDA0 (1 << 30) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA31C_MCDA1 (1 << 31) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA26C_MCDA2 (1 << 26) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA27C_MCDA3 (1 << 27) /**< \brief Hsmci signal: MCDA3 */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PA18A_RD (1 << 18) /**< \brief Ssc signal: RD */ -#define PIO_PA20A_RF (1 << 20) /**< \brief Ssc signal: RF */ -#define PIO_PA19A_RK (1 << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA17A_TD (1 << 17) /**< \brief Ssc signal: TD */ -#define PIO_PA15A_TF (1 << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA16A_TK (1 << 16) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA12A_MISO (1 << 12) /**< \brief Spi signal: MISO */ -#define PIO_PA13A_MOSI (1 << 13) /**< \brief Spi signal: MOSI */ -#define PIO_PA11A_NPCS0 (1 << 11) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA31A_NPCS1 (1 << 31) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA9B_NPCS1 (1 << 9) /**< \brief Spi signal: NPCS1 */ -#define PIO_PB14A_NPCS1 (1 << 14) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC4B_NPCS1 (1 << 4) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA10B_NPCS2 (1 << 10) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA30B_NPCS2 (1 << 30) /**< \brief Spi signal: NPCS2 */ -#define PIO_PB2B_NPCS2 (1 << 2) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA22B_NPCS3 (1 << 22) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA3B_NPCS3 (1 << 3) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA14A_SPCK (1 << 14) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA4B_TCLK0 (1 << 4) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA28B_TCLK1 (1 << 28) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA29B_TCLK2 (1 << 29) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1 << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA15B_TIOA1 (1 << 15) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA26B_TIOA2 (1 << 26) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1 << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1 << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA27B_TIOB2 (1 << 27) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PC25B_TCLK3 (1 << 25) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PC28B_TCLK4 (1 << 28) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PC31B_TCLK5 (1 << 31) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PC23B_TIOA3 (1 << 23) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PC26B_TIOA4 (1 << 26) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PC29B_TIOA5 (1 << 29) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PC24B_TIOB3 (1 << 24) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PC27B_TIOB4 (1 << 27) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PC30B_TIOB5 (1 << 30) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA4A_TWCK0 (1 << 4) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA3A_TWD0 (1 << 3) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB5A_TWCK1 (1 << 5) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB4A_TWD1 (1 << 4) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA9C_PWMFI0 (1 << 9) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA11B_PWMH0 (1 << 11) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA23B_PWMH0 (1 << 23) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC18B_PWMH0 (1 << 18) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA12B_PWMH1 (1 << 12) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA24B_PWMH1 (1 << 24) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC19B_PWMH1 (1 << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1 << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA25B_PWMH2 (1 << 25) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB4B_PWMH2 (1 << 4) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC20B_PWMH2 (1 << 20) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA17C_PWMH3 (1 << 17) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA7B_PWMH3 (1 << 7) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC21B_PWMH3 (1 << 21) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA19B_PWML0 (1 << 19) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB5B_PWML0 (1 << 5) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC0B_PWML0 (1 << 0) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC13B_PWML0 (1 << 13) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA20B_PWML1 (1 << 20) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB12A_PWML1 (1 << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC1B_PWML1 (1 << 1) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC15B_PWML1 (1 << 15) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA16C_PWML2 (1 << 16) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA30A_PWML2 (1 << 30) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB13A_PWML2 (1 << 13) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC2B_PWML2 (1 << 2) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA15C_PWML3 (1 << 15) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC22B_PWML3 (1 << 22) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC3B_PWML3 (1 << 3) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PA7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA5A_RXD0 (1 << 5) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA2B_SCK0 (1 << 2) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA6A_TXD0 (1 << 6) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA25A_CTS1 (1 << 25) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA26A_DCD1 (1 << 26) /**< \brief Usart1 signal: DCD1 */ -#define PIO_PA28A_DSR1 (1 << 28) /**< \brief Usart1 signal: DSR1 */ -#define PIO_PA27A_DTR1 (1 << 27) /**< \brief Usart1 signal: DTR1 */ -#define PIO_PA29A_RI1 (1 << 29) /**< \brief Usart1 signal: RI1 */ -#define PIO_PA24A_RTS1 (1 << 24) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA23A_SCK1 (1 << 23) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA22A_TXD1 (1 << 22) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1 << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1 << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PC13X1_AD10 (1 << 13) /**< \brief Adc signal: AD10 */ -#define PIO_PC15X1_AD11 (1 << 15) /**< \brief Adc signal: AD11 */ -#define PIO_PC12X1_AD12 (1 << 12) /**< \brief Adc signal: AD12 */ -#define PIO_PC29X1_AD13 (1 << 29) /**< \brief Adc signal: AD13 */ -#define PIO_PC30X1_AD14 (1 << 30) /**< \brief Adc signal: AD14 */ -#define PIO_PA19X1_AD2 (1 << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1 << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1 << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1 << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1 << 2) /**< \brief Adc signal: AD6 */ -#define PIO_PB3X1_AD7 (1 << 3) /**< \brief Adc signal: AD7 */ -#define PIO_PA21X1_AD8 (1 << 21) /**< \brief Adc signal: AD8 */ -#define PIO_PA22X1_AD9 (1 << 22) /**< \brief Adc signal: AD9 */ -#define PIO_PA8B_ADTRG (1 << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB13X1_DAC0 (1 << 13) /**< \brief Dacc signal: DAC0 */ -#define PIO_PB14X1_DAC1 (1 << 14) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA2C_DATRG (1 << 2) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1 << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB13B_PCK0 (1 << 13) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1 << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1 << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1 << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1 << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1 << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for UART0 peripheral ========== */ -#define PIO_PA9A_URXD0 (1 << 9) /**< \brief Uart0 signal: URXD0 */ -#define PIO_PA10A_UTXD0 (1 << 10) /**< \brief Uart0 signal: UTXD0 */ -/* ========== Pio definition for UART1 peripheral ========== */ -#define PIO_PB2A_URXD1 (1 << 2) /**< \brief Uart1 signal: URXD1 */ -#define PIO_PB3A_UTXD1 (1 << 3) /**< \brief Uart1 signal: UTXD1 */ -/* ========== Pio definition for PIOA peripheral ========== */ -#define PIO_PA24X1_PIODC0 (1 << 24) /**< \brief Pioa signal: PIODC0 */ -#define PIO_PA25X1_PIODC1 (1 << 25) /**< \brief Pioa signal: PIODC1 */ -#define PIO_PA26X1_PIODC2 (1 << 26) /**< \brief Pioa signal: PIODC2 */ -#define PIO_PA27X1_PIODC3 (1 << 27) /**< \brief Pioa signal: PIODC3 */ -#define PIO_PA28X1_PIODC4 (1 << 28) /**< \brief Pioa signal: PIODC4 */ -#define PIO_PA29X1_PIODC5 (1 << 29) /**< \brief Pioa signal: PIODC5 */ -#define PIO_PA30X1_PIODC6 (1 << 30) /**< \brief Pioa signal: PIODC6 */ -#define PIO_PA31X1_PIODC7 (1 << 31) /**< \brief Pioa signal: PIODC7 */ -#define PIO_PA23X1_PIODCCLK (1 << 23) /**< \brief Pioa signal: PIODCCLK */ -#define PIO_PA15X1_PIODCEN1 (1 << 15) /**< \brief Pioa signal: PIODCEN1 */ -#define PIO_PA16X1_PIODCEN2 (1 << 16) /**< \brief Pioa signal: PIODCEN2 */ -/*@}*/ - -/* ***************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ - -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_IFLASH (0x00400000) /**< Internal Flash base address */ -#define AT91C_IROM (0x00800000) /**< Internal ROM base address */ -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_EBI_CS0 (0x60000000) /**< EBI Chip Select 0 base address */ -#define AT91C_EBI_CS1 (0x61000000) /**< EBI Chip Select 1 base address */ -#define AT91C_EBI_CS2 (0x62000000) /**< EBI Chip Select 2 base address */ -#define AT91C_EBI_CS3 (0x63000000) /**< EBI Chip Select 3 base address */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - +#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) +/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ +#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ +#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ +#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ +#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ +#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ +#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ +#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ +#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ +#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ +#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ +#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ +#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ +#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ +#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ +#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ +/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ +#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ +#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ +#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ +#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ +#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ +#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ +#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ +#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ +#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ +#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ +#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ +#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ +#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ +#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ +#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ +#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ +#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ +#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ +#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ +#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ +#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ +#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ +#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ +#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ +#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ +#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ +#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ +#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ +#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ +#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ +#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ +#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ +#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ +#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ +#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ +#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ +/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ +#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ +/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ +#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ +/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ +#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ +/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ +#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ +/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ +#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ +/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ +#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ +/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ +#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ +/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ +/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ +/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ +#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ +#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ +#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ +#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ +/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ +#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ +#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Uart hardware registers */ +typedef struct { + WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + RwReg Reserved1[55]; + RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ + RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ + RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ + RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ + RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ + RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ + RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ + RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ + WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ + RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ +} Uart; +#endif /* __ASSEMBLY__ */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ +#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ +#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ +#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ +#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ +#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ +#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ +#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ +#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ +#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ +#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ +#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ +#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ +/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ +#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ +/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ +#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ +/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ +#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ +/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ +#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ +/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ +#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ +/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ +#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ +/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ +/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ +/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ +#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ +#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ +#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ +#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ +/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ +#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ +#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Device Port */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_UDP USB Device Port */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Udp hardware registers */ +typedef struct { + RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ + RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ + RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ + RwReg Reserved1[1]; + WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ + WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ + RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ + RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ + WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ + RwReg Reserved2[1]; + RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ + RwReg Reserved3[1]; + RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x30) Endpoint Control and Status Register (ept_num = 0) */ + RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x50) Endpoint FIFO Data Register (ept_num = 0) */ + RwReg Reserved4[1]; + RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ +} Udp; +#endif /* __ASSEMBLY__ */ +/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ +#define UDP_FRM_NUM_FRM_NUM (0x7ff << 0) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ +#define UDP_FRM_NUM_FRM_ERR (0x1 << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ +#define UDP_FRM_NUM_FRM_OK (0x1 << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ +/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ +#define UDP_GLB_STAT_FADDEN (0x1 << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ +#define UDP_GLB_STAT_CONFG (0x1 << 1) /**< \brief (UDP_GLB_STAT) Configured */ +#define UDP_GLB_STAT_ESR (0x1 << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ +#define UDP_GLB_STAT_RSMINPR (0x1 << 3) /**< \brief (UDP_GLB_STAT) */ +#define UDP_GLB_STAT_RMWUPE (0x1 << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ +#define UDP_FADDR_FADD_Pos 0 +#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */ +#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos))) +#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ +#define UDP_IER_EP0INT (0x1 << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ +#define UDP_IER_EP1INT (0x1 << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ +#define UDP_IER_EP2INT (0x1 << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ +#define UDP_IER_EP3INT (0x1 << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ +#define UDP_IER_EP4INT (0x1 << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ +#define UDP_IER_EP5INT (0x1 << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ +#define UDP_IER_EP6INT (0x1 << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ +#define UDP_IER_EP7INT (0x1 << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ +#define UDP_IER_RXSUSP (0x1 << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ +#define UDP_IER_RXRSM (0x1 << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ +#define UDP_IER_EXTRSM (0x1 << 10) /**< \brief (UDP_IER) */ +#define UDP_IER_SOFINT (0x1 << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ +#define UDP_IER_WAKEUP (0x1 << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ +#define UDP_IDR_EP0INT (0x1 << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ +#define UDP_IDR_EP1INT (0x1 << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ +#define UDP_IDR_EP2INT (0x1 << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ +#define UDP_IDR_EP3INT (0x1 << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ +#define UDP_IDR_EP4INT (0x1 << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ +#define UDP_IDR_EP5INT (0x1 << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ +#define UDP_IDR_EP6INT (0x1 << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ +#define UDP_IDR_EP7INT (0x1 << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ +#define UDP_IDR_RXSUSP (0x1 << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ +#define UDP_IDR_RXRSM (0x1 << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ +#define UDP_IDR_EXTRSM (0x1 << 10) /**< \brief (UDP_IDR) */ +#define UDP_IDR_SOFINT (0x1 << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ +#define UDP_IDR_WAKEUP (0x1 << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ +/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ +#define UDP_IMR_EP0INT (0x1 << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ +#define UDP_IMR_EP1INT (0x1 << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ +#define UDP_IMR_EP2INT (0x1 << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ +#define UDP_IMR_EP3INT (0x1 << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ +#define UDP_IMR_EP4INT (0x1 << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ +#define UDP_IMR_EP5INT (0x1 << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ +#define UDP_IMR_EP6INT (0x1 << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ +#define UDP_IMR_EP7INT (0x1 << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ +#define UDP_IMR_RXSUSP (0x1 << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ +#define UDP_IMR_RXRSM (0x1 << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ +#define UDP_IMR_EXTRSM (0x1 << 10) /**< \brief (UDP_IMR) */ +#define UDP_IMR_SOFINT (0x1 << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ +#define UDP_IMR_BIT12 (0x1 << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ +#define UDP_IMR_WAKEUP (0x1 << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ +/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ +#define UDP_ISR_EP0INT (0x1 << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ +#define UDP_ISR_EP1INT (0x1 << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ +#define UDP_ISR_EP2INT (0x1 << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ +#define UDP_ISR_EP3INT (0x1 << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ +#define UDP_ISR_EP4INT (0x1 << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ +#define UDP_ISR_EP5INT (0x1 << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ +#define UDP_ISR_EP6INT (0x1 << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ +#define UDP_ISR_EP7INT (0x1 << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ +#define UDP_ISR_RXSUSP (0x1 << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ +#define UDP_ISR_RXRSM (0x1 << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ +#define UDP_ISR_EXTRSM (0x1 << 10) /**< \brief (UDP_ISR) */ +#define UDP_ISR_SOFINT (0x1 << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ +#define UDP_ISR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ +#define UDP_ISR_WAKEUP (0x1 << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ +/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ +#define UDP_ICR_RXSUSP (0x1 << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ +#define UDP_ICR_RXRSM (0x1 << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ +#define UDP_ICR_EXTRSM (0x1 << 10) /**< \brief (UDP_ICR) */ +#define UDP_ICR_SOFINT (0x1 << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ +#define UDP_ICR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ +#define UDP_ICR_WAKEUP (0x1 << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ +/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ +#define UDP_RST_EP_EP0 (0x1 << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ +#define UDP_RST_EP_EP1 (0x1 << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ +#define UDP_RST_EP_EP2 (0x1 << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ +#define UDP_RST_EP_EP3 (0x1 << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ +#define UDP_RST_EP_EP4 (0x1 << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ +#define UDP_RST_EP_EP5 (0x1 << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ +#define UDP_RST_EP_EP6 (0x1 << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ +#define UDP_RST_EP_EP7 (0x1 << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ +/* -------- UDP_CSR[8] : (UDP Offset: 0x2C) Endpoint Control and Status Register (ept_num = 0) -------- */ +#define UDP_CSR_TXCOMP (0x1 << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ +#define UDP_CSR_RX_DATA_BK0 (0x1 << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ +#define UDP_CSR_RXSETUP (0x1 << 2) /**< \brief (UDP_CSR[8]) Received Setup */ +#define UDP_CSR_STALLSENTISOERROR (0x1 << 3) /**< \brief (UDP_CSR[8]) */ +#define UDP_CSR_TXPKTRDY (0x1 << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ +#define UDP_CSR_FORCESTALL (0x1 << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ +#define UDP_CSR_RX_DATA_BK1 (0x1 << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ +#define UDP_CSR_DIR (0x1 << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ +#define UDP_CSR_EPTYPE_Pos 8 +#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */ +#define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */ +#define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ +#define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ +#define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ +#define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ +#define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ +#define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ +#define UDP_CSR_DTGLE (0x1 << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ +#define UDP_CSR_EPEDS (0x1 << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ +#define UDP_CSR_RXBYTECNT_Pos 16 +#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ +#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos))) +/* -------- UDP_FDR[8] : (UDP Offset: 0x4C) Endpoint FIFO Data Register (ept_num = 0) -------- */ +#define UDP_FDR_FIFO_DATA (0xff << 0) /**< \brief (UDP_FDR[8]) FIFO Data Value */ +/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ +#define UDP_TXVC_TXVDIS (0x1 << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ +#define UDP_TXVC_PUON (0x1 << 9) /**< \brief (UDP_TXVC) Pullup On */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Usart hardware registers */ +typedef struct { + WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ + WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ + RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + RwReg Reserved1[5]; + RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + RwReg Reserved2[1]; + RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ + RwReg Reserved3[36]; + RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ + RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ + RwReg Reserved4[4]; + RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ + RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ + RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ + RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ + RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ + RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ + RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ + RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ + RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ + WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ + RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ +} Usart; +#endif /* __ASSEMBLY__ */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ +#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ +#define US_CR_DTREN (0x1 << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1 << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ +#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ +#define US_MR_USART_MODE_NORMAL (0x0) /**< (USART) Normal*/ +#define US_MR_USART_MODE_RS485 (0x1) /**< (USART) RS485*/ +#define US_MR_USART_MODE_HWHSH (0x2) /**< (USART) Hardware Handshaking*/ +#define US_MR_USART_MODE_ISO7816_0 (0x4) /**< (USART) ISO7816 protocol: T = 0*/ +#define US_MR_USART_MODE_ISO7816_1 (0x6) /**< (USART) ISO7816 protocol: T = 1*/ +#define US_MR_USART_MODE_IRDA (0x8) /**< (USART) IrDA*/ +#define US_MR_USART_MODE_SPIM (0xE) /**< (USART) SPI Master*/ +#define US_MR_USART_MODE_SPIS (0xF) /**< (USART) SPI Slave*/ +#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS_CLOCK (0x0 << 4) /**< (USART) MCK*/ +#define US_MR_USCLKS_FDIV1 (0x1 << 4) /**< (USART) MCK/DIV(DIV=8)*/ +#define US_MR_USCLKS_SLOW (0x2 << 4) /**< (USART) Reserved*/ +#define US_MR_USCLKS_EXT (0x3 << 4) /**< (USART) SCK*/ +#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ +#define US_MR_CHRL_5_BITS (0x0 << 6) /**< (USART) Character Length: 5 bits*/ +#define US_MR_CHRL_6_BITS (0x1 << 6) /**< (USART) Character Length: 6 bits*/ +#define US_MR_CHRL_7_BITS (0x2 << 6) /**< (USART) Character Length: 7 bits*/ +#define US_MR_CHRL_8_BITS (0x3 << 6) /**< (USART) Character Length: 8 bits*/ +#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ +#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR_EVEN (0x0 << 9) /**< (USART) Even Parity*/ +#define US_MR_PAR_ODD (0x1 << 9) /**< (USART) Odd Parity*/ +#define US_MR_PAR_SPACE (0x2 << 9) /**< (USART) Parity forced to 0 (Space)*/ +#define US_MR_PAR_MARK (0x3 << 9) /**< (USART) Parity forced to 1 (Mark)*/ +#define US_MR_PAR_NONE (0x4 << 9) /**< (USART) No Parity*/ +#define US_MR_PAR_MULTI_DROP (0x6 << 9) /**< (USART) Multi-drop mode*/ +#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP_1_BIT (0x0 << 12) /**< (USART) 1 stop bit*/ +#define US_MR_NBSTOP_15_BIT (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits*/ +#define US_MR_NBSTOP_2_BIT (0x2 << 12) /**< (USART) 2 stop bits*/ +#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE_NORMAL (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART.*/ +#define US_MR_CHMODE_AUTO (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/ +#define US_MR_CHMODE_LOCAL (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/ +#define US_MR_CHMODE_REMOTE (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin.*/ +#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ +#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ +#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ +#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ +#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ +#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ +#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ +#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ +#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ +#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ +#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_RIIC (0x1 << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1 << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1 << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ +#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ +#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ +#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ +#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ +#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ +#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_RIIC (0x1 << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1 << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1 << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ +#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ +#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ +#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ +#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ +#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_RIIC (0x1 << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1 << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1 << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ +#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ +#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ +#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ +#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ +#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ +#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ +#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ +#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ +#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ +#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ +#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ +#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ +#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ +#define US_CSR_RIIC (0x1 << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ +#define US_CSR_DSRIC (0x1 << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ +#define US_CSR_DCDIC (0x1 << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ +#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ +#define US_CSR_RI (0x1 << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1 << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1 << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ +/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ +#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ +#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ +#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ +#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ +/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ +#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ +#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ +/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ +#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ +#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ +/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ +#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ +#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ +/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ +#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ +/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ +#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ +/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ +#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ +/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ +#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ +/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ +#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ +/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ +#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ +/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ +/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ +/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ +#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ +#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ +#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ +#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ +/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ +#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ +#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_WDT Watchdog Timer */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Wdt hardware registers */ +typedef struct { + WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* __ASSEMBLY__ */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ +#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ +#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ + +/*@}*/ + +/*@}*/ + +/* ***************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_reg Registers Access Definitions */ +/*@{*/ + +/* ========== Register definition for HSMCI peripheral ========== */ +#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ +#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ +#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ +#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ +#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ +#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ +#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ +#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ +#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ +#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ +#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ +#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ +#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ +#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ +#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ +#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ +#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ +#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ +#define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ +#define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ +#define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ +#define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ +#define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ +#define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ +#define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ +#define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ +#define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ +#define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ +#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ +#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ +#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ +#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ +#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ +#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ +#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ +#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ +#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ +#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ +#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ +#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ +#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ +#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ +#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ +#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ +#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ +#define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */ +#define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */ +#define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ +#define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ +#define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ +#define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ +#define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ +#define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ +#define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */ +#define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */ +/* ========== Register definition for SPI peripheral ========== */ +#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ +#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ +#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ +#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ +#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ +#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ +#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ +#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ +#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ +#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ +#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ +#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */ +#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */ +#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ +#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ +#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ +#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ +#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ +#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ +#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */ +#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */ +#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ +#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ +#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ +#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ +#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */ +#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ +#define REG_TC0_VER REG_ACCESS(RoReg, 0x400100FCU) /**< \brief (TC0) Version Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */ +#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ +#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ +#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ +#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ +#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */ +#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ +#define REG_TC1_VER REG_ACCESS(RoReg, 0x400140FCU) /**< \brief (TC1) Version Register */ +/* ========== Register definition for TWI0 peripheral ========== */ +#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ +#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */ +#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ +#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ +#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ +#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ +#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ +#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ +#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */ +#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */ +/* ========== Register definition for TWI1 peripheral ========== */ +#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ +#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ +#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ +#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ +#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ +#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ +#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ +#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ +#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ +#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ +/* ========== Register definition for PWM peripheral ========== */ +#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ +#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ +#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ +#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */ +#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */ +#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ +#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ +#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */ +#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */ +#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ +#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ +#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */ +#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */ +#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +/* ========== Register definition for USART0 peripheral ========== */ +#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ +#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */ +#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */ +#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */ +#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ +#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ +#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ +#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ +#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ +#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ +#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */ +#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */ +/* ========== Register definition for USART1 peripheral ========== */ +#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ +#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */ +#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */ +#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */ +#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ +#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ +#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ +#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ +#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ +#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ +#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */ +#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */ +#define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */ +#define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */ +#define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ +#define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ +#define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ +#define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ +#define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ +#define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ +#define REG_UDP_CSR REG_ACCESS(RwReg, 0x4003402CU) /**< \brief (UDP) Endpoint Control and Status Register (ept_num = 0) */ +#define REG_UDP_FDR REG_ACCESS(RwReg, 0x4003404CU) /**< \brief (UDP) Endpoint FIFO Data Register (ept_num = 0) */ +#define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQ1R REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence 1Register */ +#define REG_ADC_SEQ2R REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence 2 Register */ +#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */ +#define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR0 REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register 0 */ +#define REG_ADC_CDR1 REG_ACCESS(RoReg, 0x40038054U) /**< \brief (ADC) Channel Data Register 1 */ +#define REG_ADC_CDR2 REG_ACCESS(RoReg, 0x40038058U) /**< \brief (ADC) Channel Data Register 2 */ +#define REG_ADC_CDR3 REG_ACCESS(RoReg, 0x4003805CU) /**< \brief (ADC) Channel Data Register 3 */ +#define REG_ADC_CDR4 REG_ACCESS(RoReg, 0x40038060U) /**< \brief (ADC) Channel Data Register 4 */ +#define REG_ADC_CDR5 REG_ACCESS(RoReg, 0x40038064U) /**< \brief (ADC) Channel Data Register 5 */ +#define REG_ADC_CDR6 REG_ACCESS(RoReg, 0x40038068U) /**< \brief (ADC) Channel Data Register 6 */ +#define REG_ADC_CDR15 REG_ACCESS(RoReg, 0x4003806CU) /**< \brief (ADC) Channel Data Register 15 */ +#define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */ +#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ +#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ +#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */ +#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */ +#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */ +#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */ +#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ +#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ +#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */ +#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */ +#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */ +#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */ +/* ========== Register definition for DACC peripheral ========== */ +#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */ +#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */ +#define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */ +#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */ +#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */ +#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */ +#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ +#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ +#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ +#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ +#define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */ +#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ +#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ +#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */ +#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */ +#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ +#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ +#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */ +#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */ +#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ +#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ +#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */ +#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */ +/* ========== Register definition for ACC peripheral ========== */ +#define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */ +#define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */ +#define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ +#define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ +#define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ +#define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */ +#define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */ +#define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ +#define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ +/* ========== Register definition for CRCCU peripheral ========== */ +#define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ +#define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ +#define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ +#define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ +#define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ +#define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ +#define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ +#define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ +#define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ +#define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ +#define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ +#define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ +#define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ +#define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ +#define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ +/* ========== Register definition for SMC peripheral ========== */ +#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ +#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ +#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ +#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ +#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ +#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ +#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ +/* ========== Register definition for MATRIX peripheral ========== */ +#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System IO Configuration register */ +#define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ +#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */ +#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ +#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ +/* ========== Register definition for UART0 peripheral ========== */ +#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */ +#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */ +#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ +#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ +#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ +#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */ +#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */ +#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ +#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ +#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ +#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */ +#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ +#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ +#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ +#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ +#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ +#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ +#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */ +#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */ +/* ========== Register definition for CHIPID peripheral ========== */ +#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ +/* ========== Register definition for UART1 peripheral ========== */ +#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */ +#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */ +#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ +#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ +#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ +#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */ +#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */ +#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ +#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ +#define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ +#define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */ +#define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ +#define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ +#define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ +#define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ +#define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ +#define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ +#define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */ +#define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */ +/* ========== Register definition for EFC peripheral ========== */ +#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ +#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ +#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ +#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ +#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ +#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ +#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ +#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ +#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ +#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ +#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ +#define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ +#define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ +#define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ +#define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ +#define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ +#define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ +#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ +#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ +#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ +#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ +#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ +#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ +#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ +#define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ +#define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ +#define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ +#define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ +#define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ +#define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +/* ========== Register definition for PIOC peripheral ========== */ +#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ +#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ +#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ +#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ +#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ +#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ +#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ +#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ +#define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ +#define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ +#define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ +#define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ +#define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ +#define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */ +/* ========== Register definition for SUPC peripheral ========== */ +#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ +#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ +#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ +/* ========== Register definition for RTT peripheral ========== */ +#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */ +#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */ +#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */ +#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */ +/* ========== Register definition for WDT peripheral ========== */ +#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */ +/* ========== Register definition for RTC peripheral ========== */ +#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */ +/* ========== Register definition for GPBR peripheral ========== */ +#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */ +#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */ +#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */ +#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ +/*@}*/ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ +/*@}*/ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_base Peripheral Base Address Definitions */ +/*@{*/ + +#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */ + +// indices for three pio structures +#define iPIOA 0 +#define iPIOB 1 +#define iPIOC 2 +/*@}*/ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_pio Peripheral Pio Definitions */ +/*@{*/ + +#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1 << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1 << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1 << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1 << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1 << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1 << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1 << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1 << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1 << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1 << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1 << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1 << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1 << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1 << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1 << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA31A_NPCS1 (1 << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA9B_NPCS1 (1 << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1 << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1 << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1 << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1 << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1 << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA22B_NPCS3 (1 << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA3B_NPCS3 (1 << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1 << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1 << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1 << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1 << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1 << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1 << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1 << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1 << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1 << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1 << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1 << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1 << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1 << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1 << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1 << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1 << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1 << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1 << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1 << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1 << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1 << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1 << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1 << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1 << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1 << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1 << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1 << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1 << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1 << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1 << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA13B_PWMH2 (1 << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1 << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1 << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1 << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1 << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA7B_PWMH3 (1 << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1 << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1 << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1 << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1 << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1 << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1 << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1 << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1 << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1 << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1 << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1 << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1 << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1 << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1 << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1 << 22) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1 << 3) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1 << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1 << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1 << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1 << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1 << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1 << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1 << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1 << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1 << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1 << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1 << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1 << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1 << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1 << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1 << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1 << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1 << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1 << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1 << 19) /**< \brief Adc signal: AD2 */ +#define PIO_PA20X1_AD3 (1 << 20) /**< \brief Adc signal: AD3 */ +#define PIO_PB0X1_AD4 (1 << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1 << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1 << 2) /**< \brief Adc signal: AD6 */ +#define PIO_PB3X1_AD7 (1 << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1 << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1 << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1 << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1 << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1 << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1 << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1 << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1 << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1 << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1 << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1 << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1 << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1 << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1 << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1 << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1 << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1 << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24X1_PIODC0 (1 << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25X1_PIODC1 (1 << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26X1_PIODC2 (1 << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27X1_PIODC3 (1 << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28X1_PIODC4 (1 << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29X1_PIODC5 (1 << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30X1_PIODC6 (1 << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31X1_PIODC7 (1 << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23X1_PIODCCLK (1 << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15X1_PIODCEN1 (1 << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16X1_PIODCEN2 (1 << 16) /**< \brief Pioa signal: PIODCEN2 */ +/*@}*/ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ + +#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ +#define AT91C_IFLASH (0x00400000) /**< Internal Flash base address */ +#define AT91C_IROM (0x00800000) /**< Internal ROM base address */ +#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ +#define AT91C_EBI_CS0 (0x60000000) /**< EBI Chip Select 0 base address */ +#define AT91C_EBI_CS1 (0x61000000) /**< EBI Chip Select 1 base address */ +#define AT91C_EBI_CS2 (0x62000000) /**< EBI Chip Select 2 base address */ +#define AT91C_EBI_CS3 (0x63000000) /**< EBI Chip Select 3 base address */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + #endif // _AT91SAM3S4_H_ diff --git a/radio/src/targets/sky9x/MEDSdcard.c b/radio/src/targets/sky9x/MEDSdcard.c index 77c7a414d..07324917d 100644 --- a/radio/src/targets/sky9x/MEDSdcard.c +++ b/radio/src/targets/sky9x/MEDSdcard.c @@ -1,246 +1,246 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include "debug.h" -#include "diskio.h" -#include "board_lowlevel.h" -#include "Media.h" - -//------------------------------------------------------------------------------ -// Constants -//------------------------------------------------------------------------------ - -/// Number of SD Slots -#define NUM_SD_SLOTS 1 - -//------------------------------------------------------------------------------ -/// Checks if the device is write protected. -/// \return 1 if protected. -//------------------------------------------------------------------------------ -#if 0 -static unsigned char CardIsProtected(unsigned char slot) -{ - if (slot == 0) { - #ifdef BOARD_SD_PIN_WP - PIO_Configure(&pinMciWriteProtect, 1); - return (PIO_Get(&pinMciWriteProtect) != 0); - #else - return 0; - #endif - } - - if (slot == 1) { - #ifdef BOARD_SD_MCI1_PIN_WP - PIO_Configure(&pinMciWriteProtect1, 1); - return (PIO_Get(&pinMciWriteProtect1) != 0); - #else - return 0; - #endif - } - - return 0; -} -#endif - -//------------------------------------------------------------------------------ -/// Configure the PIO for SD -//------------------------------------------------------------------------------ -#if 0 -static void ConfigurePIO(unsigned char mciID) -{ - #ifdef BOARD_SD_PINS - const Pin pinSd0[] = {BOARD_SD_PINS}; - #endif - - #ifdef BOARD_SD_MCI1_PINS - const Pin pinSd1[] = {BOARD_SD_MCI1_PINS}; - #endif - - if(mciID == 0) { - #ifdef BOARD_SD_PINS - PIO_Configure(pinSd0, PIO_LISTSIZE(pinSd0)); - #endif - } else { - #ifdef BOARD_SD_MCI1_PINS - PIO_Configure(pinSd1, PIO_LISTSIZE(pinSd1)); - #endif - } -} -#endif - -//------------------------------------------------------------------------------ -//! \brief Reads a specified amount of data from a SDCARD memory -//! \param media Pointer to a Media instance -//! \param address Address of the data to read -//! \param data Pointer to the buffer in which to store the retrieved -//! data -//! \param length Length of the buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the operation is finished -//! \param argument Optional pointer to an argument for the callback -//! \return Operation result code -//------------------------------------------------------------------------------ -static unsigned char MEDSdcard_Read(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - TRACE_DEBUG("MEDSdcard_Read(address=%d length=%d)\n\r", address, length); - - // Check that the media is ready - if (media->state != MED_STATE_READY) { - - TRACE_INFO("Media busy\n\r"); - return MED_STATUS_BUSY; - } - - // Check that the data to read is not too big - if ((length + address) > media->size) { - - TRACE_WARNING("MEDSdcard_Read: Data too big: %d, %d\n\r", - (int)length, (int)address); - return MED_STATUS_ERROR; - } - - // Enter Busy state - media->state = MED_STATE_BUSY; - - disk_read (0, data, address, length); - - // Leave the Busy state - media->state = MED_STATE_READY; - - // Invoke callback - if (callback != 0) { - - callback(argument, MED_STATUS_SUCCESS, 0, 0); - } - - return MED_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -//! \brief Writes data on a SDRAM media -//! \param media Pointer to a Media instance -//! \param address Address at which to write -//! \param data Pointer to the data to write -//! \param length Size of the data buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the write operation terminates -//! \param argument Optional argument for the callback function -//! \return Operation result code -//! \see Media -//! \see MediaCallback -//------------------------------------------------------------------------------ -static unsigned char MEDSdcard_Write(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - - TRACE_DEBUG("MEDSdcard_Write(address=%d length=%d)\n\r", address, length); - - // Check that the media if ready - if (media->state != MED_STATE_READY) { - - TRACE_WARNING("MEDSdcard_Write: Media is busy\n\r"); - return MED_STATUS_BUSY; - } - - // Check that the data to write is not too big - if ((length + address) > media->size) { - - TRACE_WARNING("MEDSdcard_Write: Data too big\n\r"); - return MED_STATUS_ERROR; - } - - // Put the media in Busy state - media->state = MED_STATE_BUSY; - - disk_write(0, data, address, length); - - // Leave the Busy state - media->state = MED_STATE_READY; - - // Invoke the callback if it exists - if (callback != 0) { - - callback(argument, MED_STATUS_SUCCESS, 0, 0); - } - - return MED_STATUS_SUCCESS; -} - - -//------------------------------------------------------------------------------ -/// Initializes a Media instance and the associated physical interface -/// \param media Pointer to the Media instance to initialize -/// \return 1 if success. -//------------------------------------------------------------------------------ - -unsigned char MEDSdcard_Initialize(Media *media, unsigned char mciID) -{ - TRACE_INFO("MEDSdcard init\n\r"); - - // Initialize SDcard - //-------------------------------------------------------------------------- - - if ( !SD_CARD_PRESENT( ) ) - { - return 0; - } - - media->write = MEDSdcard_Write; - media->read = MEDSdcard_Read; - media->lock = 0; - media->unlock = 0; - media->handler = 0; - media->flush = 0; - - media->blockSize = BLOCK_SIZE; - media->baseAddress = 0; - - media->size = SD_GET_BLOCKNR(); - - media->mappedRD = 0; - media->mappedWR = 0; - media->protected = 0; - media->removable = 1; - - media->state = MED_STATE_READY; - - media->transfer.data = 0; - media->transfer.address = 0; - media->transfer.length = 0; - media->transfer.callback = 0; - media->transfer.argument = 0; - - return 1; -} - +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include +#include "debug.h" +#include "diskio.h" +#include "board_lowlevel.h" +#include "Media.h" + +//------------------------------------------------------------------------------ +// Constants +//------------------------------------------------------------------------------ + +/// Number of SD Slots +#define NUM_SD_SLOTS 1 + +//------------------------------------------------------------------------------ +/// Checks if the device is write protected. +/// \return 1 if protected. +//------------------------------------------------------------------------------ +#if 0 +static unsigned char CardIsProtected(unsigned char slot) +{ + if (slot == 0) { + #ifdef BOARD_SD_PIN_WP + PIO_Configure(&pinMciWriteProtect, 1); + return (PIO_Get(&pinMciWriteProtect) != 0); + #else + return 0; + #endif + } + + if (slot == 1) { + #ifdef BOARD_SD_MCI1_PIN_WP + PIO_Configure(&pinMciWriteProtect1, 1); + return (PIO_Get(&pinMciWriteProtect1) != 0); + #else + return 0; + #endif + } + + return 0; +} +#endif + +//------------------------------------------------------------------------------ +/// Configure the PIO for SD +//------------------------------------------------------------------------------ +#if 0 +static void ConfigurePIO(unsigned char mciID) +{ + #ifdef BOARD_SD_PINS + const Pin pinSd0[] = {BOARD_SD_PINS}; + #endif + + #ifdef BOARD_SD_MCI1_PINS + const Pin pinSd1[] = {BOARD_SD_MCI1_PINS}; + #endif + + if(mciID == 0) { + #ifdef BOARD_SD_PINS + PIO_Configure(pinSd0, PIO_LISTSIZE(pinSd0)); + #endif + } else { + #ifdef BOARD_SD_MCI1_PINS + PIO_Configure(pinSd1, PIO_LISTSIZE(pinSd1)); + #endif + } +} +#endif + +//------------------------------------------------------------------------------ +//! \brief Reads a specified amount of data from a SDCARD memory +//! \param media Pointer to a Media instance +//! \param address Address of the data to read +//! \param data Pointer to the buffer in which to store the retrieved +//! data +//! \param length Length of the buffer +//! \param callback Optional pointer to a callback function to invoke when +//! the operation is finished +//! \param argument Optional pointer to an argument for the callback +//! \return Operation result code +//------------------------------------------------------------------------------ +static unsigned char MEDSdcard_Read(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument) +{ + TRACE_DEBUG("MEDSdcard_Read(address=%d length=%d)\n\r", address, length); + + // Check that the media is ready + if (media->state != MED_STATE_READY) { + + TRACE_INFO("Media busy\n\r"); + return MED_STATUS_BUSY; + } + + // Check that the data to read is not too big + if ((length + address) > media->size) { + + TRACE_WARNING("MEDSdcard_Read: Data too big: %d, %d\n\r", + (int)length, (int)address); + return MED_STATUS_ERROR; + } + + // Enter Busy state + media->state = MED_STATE_BUSY; + + disk_read (0, data, address, length); + + // Leave the Busy state + media->state = MED_STATE_READY; + + // Invoke callback + if (callback != 0) { + + callback(argument, MED_STATUS_SUCCESS, 0, 0); + } + + return MED_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +//! \brief Writes data on a SDRAM media +//! \param media Pointer to a Media instance +//! \param address Address at which to write +//! \param data Pointer to the data to write +//! \param length Size of the data buffer +//! \param callback Optional pointer to a callback function to invoke when +//! the write operation terminates +//! \param argument Optional argument for the callback function +//! \return Operation result code +//! \see Media +//! \see MediaCallback +//------------------------------------------------------------------------------ +static unsigned char MEDSdcard_Write(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument) +{ + + TRACE_DEBUG("MEDSdcard_Write(address=%d length=%d)\n\r", address, length); + + // Check that the media if ready + if (media->state != MED_STATE_READY) { + + TRACE_WARNING("MEDSdcard_Write: Media is busy\n\r"); + return MED_STATUS_BUSY; + } + + // Check that the data to write is not too big + if ((length + address) > media->size) { + + TRACE_WARNING("MEDSdcard_Write: Data too big\n\r"); + return MED_STATUS_ERROR; + } + + // Put the media in Busy state + media->state = MED_STATE_BUSY; + + disk_write(0, data, address, length); + + // Leave the Busy state + media->state = MED_STATE_READY; + + // Invoke the callback if it exists + if (callback != 0) { + + callback(argument, MED_STATUS_SUCCESS, 0, 0); + } + + return MED_STATUS_SUCCESS; +} + + +//------------------------------------------------------------------------------ +/// Initializes a Media instance and the associated physical interface +/// \param media Pointer to the Media instance to initialize +/// \return 1 if success. +//------------------------------------------------------------------------------ + +unsigned char MEDSdcard_Initialize(Media *media, unsigned char mciID) +{ + TRACE_INFO("MEDSdcard init\n\r"); + + // Initialize SDcard + //-------------------------------------------------------------------------- + + if ( !SD_CARD_PRESENT( ) ) + { + return 0; + } + + media->write = MEDSdcard_Write; + media->read = MEDSdcard_Read; + media->lock = 0; + media->unlock = 0; + media->handler = 0; + media->flush = 0; + + media->blockSize = BLOCK_SIZE; + media->baseAddress = 0; + + media->size = SD_GET_BLOCKNR(); + + media->mappedRD = 0; + media->mappedWR = 0; + media->protected = 0; + media->removable = 1; + + media->state = MED_STATE_READY; + + media->transfer.data = 0; + media->transfer.address = 0; + media->transfer.length = 0; + media->transfer.callback = 0; + media->transfer.argument = 0; + + return 1; +} + diff --git a/radio/src/targets/sky9x/Media.h b/radio/src/targets/sky9x/Media.h index 8635ffe03..7cbcbed52 100644 --- a/radio/src/targets/sky9x/Media.h +++ b/radio/src/targets/sky9x/Media.h @@ -18,262 +18,262 @@ * GNU General Public License for more details. */ -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Generic Media type, which provides transparent access to all types of -/// memories. -/// -/// \note The physical or HW related media operations (physical device -/// connection & protection detecting, PIO configurations and interface -/// driver initialization) are excluded. -/// -/// !Usage -/// -# Do PIO initialization for peripheral interfaces. -/// -# Initialize peripheral interface driver & device driver. -/// -# Initialize specific media interface and link to this initialized driver. -/// -//------------------------------------------------------------------------------ - +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Generic Media type, which provides transparent access to all types of +/// memories. +/// +/// \note The physical or HW related media operations (physical device +/// connection & protection detecting, PIO configurations and interface +/// driver initialization) are excluded. +/// +/// !Usage +/// -# Do PIO initialization for peripheral interfaces. +/// -# Initialize peripheral interface driver & device driver. +/// -# Initialize specific media interface and link to this initialized driver. +/// +//------------------------------------------------------------------------------ + #ifndef _MEDIA_H_ #define _MEDIA_H_ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//! \brief Operation result code returned by media methods -#define MED_STATUS_SUCCESS 0x00 -#define MED_STATUS_ERROR 0x01 -#define MED_STATUS_BUSY 0x02 -#define MED_STATUS_PROTECTED 0x04 - -//! \brief Media statuses -#define MED_STATE_READY 0x00 /// Media is ready for access -#define MED_STATE_BUSY 0x01 /// Media is busy - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ -typedef struct _Media Media; - -typedef void (*MediaCallback)(void *argument, - unsigned char status, - unsigned int transferred, - unsigned int remaining); - -typedef unsigned char (*Media_write)(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument); - -typedef unsigned char (*Media_read)(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument); - -typedef unsigned char (*Media_cancelIo)(Media *media); - -typedef unsigned char (*Media_lock)(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd); - -typedef unsigned char (*Media_unlock)(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd); - -typedef unsigned char (*Media_ioctl)(Media *media, - unsigned char ctrl, - void *buff); - -typedef unsigned char (*Media_flush)(Media *media); - -typedef void (*Media_handler)(Media *media); - -//! \brief Media transfer -//! \see TransferCallback -typedef struct { - - void *data; //!< Pointer to the data buffer - unsigned int address; //!< Address where to read/write the data - unsigned int length; //!< Size of the data to read/write - MediaCallback callback; //!< Callback to invoke when the transfer done - void *argument; //!< Callback argument - -} MEDTransfer; - -//! \brief Media object -//! \see MEDTransfer -struct _Media { - - Media_write write; //!< Write method - Media_read read; //!< Read method - Media_cancelIo cancelIo; //!< Cancel pending IO method - Media_lock lock; //!< lock method if possible - Media_unlock unlock; //!< unlock method if possible - Media_flush flush; //!< Flush method - Media_handler handler; //!< Interrupt handler - unsigned int blockSize; //!< Block size in bytes (1, 512, 1K, 2K ...) - unsigned int baseAddress; //!< Base address of media in number of blocks - unsigned int size; //!< Size of media in number of blocks - MEDTransfer transfer; //!< Current transfer operation - void *interface; //!< Pointer to the physical interface used - unsigned char bReserved:4, - mappedRD:1, //!< Mapped to memory space to read - mappedWR:1, //!< Mapped to memory space to write -#ifdef __cplusplus - protectd:1, //!< Protected media? -#else - protected:1, //!< Protected media? -#endif - removable:1; //!< Removable/Fixed media? - unsigned char state; //!< Status of media - unsigned short reserved; -}; - -/// Available medias. -extern Media medias[]; - -/// Number of medias which are effectively used. -/// Defined by Media, shared usage by USB MSD & FS ... -extern unsigned int numMedias; - -//------------------------------------------------------------------------------ -// Inline Functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -//! \brief Writes data on a media -//! \param media Pointer to a Media instance -//! \param address Address at which to write -//! \param data Pointer to the data to write -//! \param length Size of the data buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the write operation terminates -//! \param argument Optional argument for the callback function -//! \return Operation result code -//! \see TransferCallback -//------------------------------------------------------------------------------ -static inline unsigned char MED_Write(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - return media->write(media, address, data, length, callback, argument); -} - -//------------------------------------------------------------------------------ -//! \brief Reads a specified amount of data from a media -//! \param media Pointer to a Media instance -//! \param address Address of the data to read -//! \param data Pointer to the buffer in which to store the retrieved -//! data -//! \param length Length of the buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the operation is finished -//! \param argument Optional pointer to an argument for the callback -//! \return Operation result code -//! \see TransferCallback -//------------------------------------------------------------------------------ -static inline unsigned char MED_Read(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - return media->read(media, address, data, length, callback, argument); -} - -//------------------------------------------------------------------------------ -//! \brief Locks all the regions in the given address range. -//! \param media Pointer to a Media instance -/// \param start Start address of lock range. -/// \param end End address of lock range. -/// \param pActualStart Start address of the actual lock range (optional). -/// \param pActualEnd End address of the actual lock range (optional). -/// \return 0 if successful; otherwise returns an error code. -//------------------------------------------------------------------------------ -static inline unsigned char MED_Lock(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd) -{ - if( media->lock ) { - return media->lock(media, start, end, pActualStart, pActualEnd); - } - else { - return MED_STATUS_SUCCESS; - } -} - -//------------------------------------------------------------------------------ -//! \brief Unlocks all the regions in the given address range -//! \param media Pointer to a Media instance -/// \param start Start address of unlock range. -/// \param end End address of unlock range. -/// \param pActualStart Start address of the actual unlock range (optional). -/// \param pActualEnd End address of the actual unlock range (optional). -/// \return 0 if successful; otherwise returns an error code. -//------------------------------------------------------------------------------ -static inline unsigned char MED_Unlock(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd) -{ - if( media->unlock ) { - return media->unlock(media, start, end, pActualStart, pActualEnd); - } - else { - return MED_STATUS_SUCCESS; - } -} - -//------------------------------------------------------------------------------ -//! \brief -//! \param media Pointer to the Media instance to use -//------------------------------------------------------------------------------ -static inline unsigned char MED_Flush(Media *media) -{ - if (media->flush) { - - return media->flush(media); - } - else { - - return MED_STATUS_SUCCESS; - } -} - -//------------------------------------------------------------------------------ -//! \brief Invokes the interrupt handler of the specified media -//! \param media Pointer to the Media instance to use -//------------------------------------------------------------------------------ -static inline void MED_Handler(Media *media) -{ - if (media->handler) { - - media->handler(media); - } -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void MED_HandleAll(Media *medias, unsigned char numMedias); - + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//! \brief Operation result code returned by media methods +#define MED_STATUS_SUCCESS 0x00 +#define MED_STATUS_ERROR 0x01 +#define MED_STATUS_BUSY 0x02 +#define MED_STATUS_PROTECTED 0x04 + +//! \brief Media statuses +#define MED_STATE_READY 0x00 /// Media is ready for access +#define MED_STATE_BUSY 0x01 /// Media is busy + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ +typedef struct _Media Media; + +typedef void (*MediaCallback)(void *argument, + unsigned char status, + unsigned int transferred, + unsigned int remaining); + +typedef unsigned char (*Media_write)(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument); + +typedef unsigned char (*Media_read)(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument); + +typedef unsigned char (*Media_cancelIo)(Media *media); + +typedef unsigned char (*Media_lock)(Media *media, + unsigned int start, + unsigned int end, + unsigned int *pActualStart, + unsigned int *pActualEnd); + +typedef unsigned char (*Media_unlock)(Media *media, + unsigned int start, + unsigned int end, + unsigned int *pActualStart, + unsigned int *pActualEnd); + +typedef unsigned char (*Media_ioctl)(Media *media, + unsigned char ctrl, + void *buff); + +typedef unsigned char (*Media_flush)(Media *media); + +typedef void (*Media_handler)(Media *media); + +//! \brief Media transfer +//! \see TransferCallback +typedef struct { + + void *data; //!< Pointer to the data buffer + unsigned int address; //!< Address where to read/write the data + unsigned int length; //!< Size of the data to read/write + MediaCallback callback; //!< Callback to invoke when the transfer done + void *argument; //!< Callback argument + +} MEDTransfer; + +//! \brief Media object +//! \see MEDTransfer +struct _Media { + + Media_write write; //!< Write method + Media_read read; //!< Read method + Media_cancelIo cancelIo; //!< Cancel pending IO method + Media_lock lock; //!< lock method if possible + Media_unlock unlock; //!< unlock method if possible + Media_flush flush; //!< Flush method + Media_handler handler; //!< Interrupt handler + unsigned int blockSize; //!< Block size in bytes (1, 512, 1K, 2K ...) + unsigned int baseAddress; //!< Base address of media in number of blocks + unsigned int size; //!< Size of media in number of blocks + MEDTransfer transfer; //!< Current transfer operation + void *interface; //!< Pointer to the physical interface used + unsigned char bReserved:4, + mappedRD:1, //!< Mapped to memory space to read + mappedWR:1, //!< Mapped to memory space to write +#ifdef __cplusplus + protectd:1, //!< Protected media? +#else + protected:1, //!< Protected media? +#endif + removable:1; //!< Removable/Fixed media? + unsigned char state; //!< Status of media + unsigned short reserved; +}; + +/// Available medias. +extern Media medias[]; + +/// Number of medias which are effectively used. +/// Defined by Media, shared usage by USB MSD & FS ... +extern unsigned int numMedias; + +//------------------------------------------------------------------------------ +// Inline Functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +//! \brief Writes data on a media +//! \param media Pointer to a Media instance +//! \param address Address at which to write +//! \param data Pointer to the data to write +//! \param length Size of the data buffer +//! \param callback Optional pointer to a callback function to invoke when +//! the write operation terminates +//! \param argument Optional argument for the callback function +//! \return Operation result code +//! \see TransferCallback +//------------------------------------------------------------------------------ +static inline unsigned char MED_Write(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument) +{ + return media->write(media, address, data, length, callback, argument); +} + +//------------------------------------------------------------------------------ +//! \brief Reads a specified amount of data from a media +//! \param media Pointer to a Media instance +//! \param address Address of the data to read +//! \param data Pointer to the buffer in which to store the retrieved +//! data +//! \param length Length of the buffer +//! \param callback Optional pointer to a callback function to invoke when +//! the operation is finished +//! \param argument Optional pointer to an argument for the callback +//! \return Operation result code +//! \see TransferCallback +//------------------------------------------------------------------------------ +static inline unsigned char MED_Read(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument) +{ + return media->read(media, address, data, length, callback, argument); +} + +//------------------------------------------------------------------------------ +//! \brief Locks all the regions in the given address range. +//! \param media Pointer to a Media instance +/// \param start Start address of lock range. +/// \param end End address of lock range. +/// \param pActualStart Start address of the actual lock range (optional). +/// \param pActualEnd End address of the actual lock range (optional). +/// \return 0 if successful; otherwise returns an error code. +//------------------------------------------------------------------------------ +static inline unsigned char MED_Lock(Media *media, + unsigned int start, + unsigned int end, + unsigned int *pActualStart, + unsigned int *pActualEnd) +{ + if( media->lock ) { + return media->lock(media, start, end, pActualStart, pActualEnd); + } + else { + return MED_STATUS_SUCCESS; + } +} + +//------------------------------------------------------------------------------ +//! \brief Unlocks all the regions in the given address range +//! \param media Pointer to a Media instance +/// \param start Start address of unlock range. +/// \param end End address of unlock range. +/// \param pActualStart Start address of the actual unlock range (optional). +/// \param pActualEnd End address of the actual unlock range (optional). +/// \return 0 if successful; otherwise returns an error code. +//------------------------------------------------------------------------------ +static inline unsigned char MED_Unlock(Media *media, + unsigned int start, + unsigned int end, + unsigned int *pActualStart, + unsigned int *pActualEnd) +{ + if( media->unlock ) { + return media->unlock(media, start, end, pActualStart, pActualEnd); + } + else { + return MED_STATUS_SUCCESS; + } +} + +//------------------------------------------------------------------------------ +//! \brief +//! \param media Pointer to the Media instance to use +//------------------------------------------------------------------------------ +static inline unsigned char MED_Flush(Media *media) +{ + if (media->flush) { + + return media->flush(media); + } + else { + + return MED_STATUS_SUCCESS; + } +} + +//------------------------------------------------------------------------------ +//! \brief Invokes the interrupt handler of the specified media +//! \param media Pointer to the Media instance to use +//------------------------------------------------------------------------------ +static inline void MED_Handler(Media *media) +{ + if (media->handler) { + + media->handler(media); + } +} + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void MED_HandleAll(Media *medias, unsigned char numMedias); + #endif // _MEDIA_H_ - + diff --git a/radio/src/targets/sky9x/adc_driver.cpp b/radio/src/targets/sky9x/adc_driver.cpp index 7270e5110..ed193bc9f 100644 --- a/radio/src/targets/sky9x/adc_driver.cpp +++ b/radio/src/targets/sky9x/adc_driver.cpp @@ -1,148 +1,148 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -uint16_t adcValues[NUM_ANALOGS]; - -#if defined(FRSKY_STICKS) -const char ana_direction[NUM_ANALOGS] = {1, 1, 0, 1 ,0 ,1 ,0, 0, 0}; -#endif - - -// Settings for mode register ADC_MR -// USEQ off - silicon problem, doesn't work -// TRANSFER = 3 -// TRACKTIM = 15 (16 clock periods) -// ANACH = 1 -// SETTLING = 6 (not used if ANACH = 0) -// STARTUP = 6 (96 clock periods) -// PRESCAL = 9.0 MHz clock (between 1 and 20MHz) -// FREERUN = 0 -// FWUP = 0 -// SLEEP = 0 -// LOWRES = 0 -// TRGSEL = 0 -// TRGEN = 0 (software trigger only) -void adcInit() -{ - Adc *padc ; - uint32_t timer ; - - timer = ( Master_frequency / (3600000*2) ) << 8 ; - // Enable peripheral clock ADC = bit 29 - PMC->PMC_PCER0 |= 0x20000000L ; // Enable peripheral clock to ADC - padc = ADC ; - padc->ADC_MR = 0x3FB60000 | timer ; // 0011 1111 1011 0110 xxxx xxxx 0000 0000 - padc->ADC_ACR = ADC_ACR_TSON ; // Turn on temp sensor -#if defined(REVA) - padc->ADC_CHER = 0x0000E23E ; // channels 1,2,3,4,5,9,13,14,15 -#else - padc->ADC_CHER = 0x0000E33E ; // channels 1,2,3,4,5,8,9,13,14,15 -#endif - padc->ADC_CGR = 0 ; // Gain = 1, all channels - padc->ADC_COR = 0 ; // Single ended, 0 offset, all channels -} - -// Read 8 (9 for REVB) ADC channels -// Documented bug, must do them 1 by 1 -void adcSingleRead() -{ - Adc *padc; - uint32_t y; - uint32_t x; - - for (uint8_t i=0; i<4; i++) - padc = ADC; - y = padc->ADC_ISR; // Clear EOC flags - for (y = NUM_ANALOGS+1; --y > 0;) { - padc->ADC_CR = 2; // Start conversion - x = 0; - while ((padc->ADC_ISR & 0x01000000) == 0) { - // wait for DRDY flag - if (++x > 1000000) { - break; // Software timeout - } - } - x = padc->ADC_LCDR; // Clear DRSY flag - } - // Next bit may be done using the PDC - adcValues[0] = ADC->ADC_CDR1; - adcValues[1] = ADC->ADC_CDR2; - adcValues[2] = ADC->ADC_CDR3; - adcValues[3] = ADC->ADC_CDR4; - adcValues[4] = ADC->ADC_CDR5; - adcValues[5] = ADC->ADC_CDR9; - adcValues[6] = ADC->ADC_CDR13; - adcValues[7] = ADC->ADC_CDR14; - -#if !defined(REVA) - adcValues[8] = ADC->ADC_CDR8 ; -#endif - - temperature = (((int32_t)temperature * 7) + ((((int32_t)ADC->ADC_CDR15 - 838) * 621) >> 11)) >> 3; // Filter it - if (get_tmr10ms() >= 100 && temperature > maxTemperature) { - maxTemperature = temperature; - } - - // adc direction correct -#if defined(FRSKY_STICKS) - uint32_t i ; - for (i=0; i> 2; - } -} - - -#if !defined(SIMU) -uint16_t getAnalogValue(uint8_t index) -{ -#if defined(PCBSKY9X) && !defined(REVA) - static const uint8_t mapping[] = {1,5,7,0,4,6,2,3}; - index = mapping[index]; -#endif - return adcValues[index]; -} -#endif // #if !defined(SIMU) +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +uint16_t adcValues[NUM_ANALOGS]; + +#if defined(FRSKY_STICKS) +const char ana_direction[NUM_ANALOGS] = {1, 1, 0, 1 ,0 ,1 ,0, 0, 0}; +#endif + + +// Settings for mode register ADC_MR +// USEQ off - silicon problem, doesn't work +// TRANSFER = 3 +// TRACKTIM = 15 (16 clock periods) +// ANACH = 1 +// SETTLING = 6 (not used if ANACH = 0) +// STARTUP = 6 (96 clock periods) +// PRESCAL = 9.0 MHz clock (between 1 and 20MHz) +// FREERUN = 0 +// FWUP = 0 +// SLEEP = 0 +// LOWRES = 0 +// TRGSEL = 0 +// TRGEN = 0 (software trigger only) +void adcInit() +{ + Adc *padc ; + uint32_t timer ; + + timer = ( Master_frequency / (3600000*2) ) << 8 ; + // Enable peripheral clock ADC = bit 29 + PMC->PMC_PCER0 |= 0x20000000L ; // Enable peripheral clock to ADC + padc = ADC ; + padc->ADC_MR = 0x3FB60000 | timer ; // 0011 1111 1011 0110 xxxx xxxx 0000 0000 + padc->ADC_ACR = ADC_ACR_TSON ; // Turn on temp sensor +#if defined(REVA) + padc->ADC_CHER = 0x0000E23E ; // channels 1,2,3,4,5,9,13,14,15 +#else + padc->ADC_CHER = 0x0000E33E ; // channels 1,2,3,4,5,8,9,13,14,15 +#endif + padc->ADC_CGR = 0 ; // Gain = 1, all channels + padc->ADC_COR = 0 ; // Single ended, 0 offset, all channels +} + +// Read 8 (9 for REVB) ADC channels +// Documented bug, must do them 1 by 1 +void adcSingleRead() +{ + Adc *padc; + uint32_t y; + uint32_t x; + + for (uint8_t i=0; i<4; i++) + padc = ADC; + y = padc->ADC_ISR; // Clear EOC flags + for (y = NUM_ANALOGS+1; --y > 0;) { + padc->ADC_CR = 2; // Start conversion + x = 0; + while ((padc->ADC_ISR & 0x01000000) == 0) { + // wait for DRDY flag + if (++x > 1000000) { + break; // Software timeout + } + } + x = padc->ADC_LCDR; // Clear DRSY flag + } + // Next bit may be done using the PDC + adcValues[0] = ADC->ADC_CDR1; + adcValues[1] = ADC->ADC_CDR2; + adcValues[2] = ADC->ADC_CDR3; + adcValues[3] = ADC->ADC_CDR4; + adcValues[4] = ADC->ADC_CDR5; + adcValues[5] = ADC->ADC_CDR9; + adcValues[6] = ADC->ADC_CDR13; + adcValues[7] = ADC->ADC_CDR14; + +#if !defined(REVA) + adcValues[8] = ADC->ADC_CDR8 ; +#endif + + temperature = (((int32_t)temperature * 7) + ((((int32_t)ADC->ADC_CDR15 - 838) * 621) >> 11)) >> 3; // Filter it + if (get_tmr10ms() >= 100 && temperature > maxTemperature) { + maxTemperature = temperature; + } + + // adc direction correct +#if defined(FRSKY_STICKS) + uint32_t i ; + for (i=0; i> 2; + } +} + + +#if !defined(SIMU) +uint16_t getAnalogValue(uint8_t index) +{ +#if defined(PCBSKY9X) && !defined(REVA) + static const uint8_t mapping[] = {1,5,7,0,4,6,2,3}; + index = mapping[index]; +#endif + return adcValues[index]; +} +#endif // #if !defined(SIMU) diff --git a/radio/src/targets/sky9x/audio_driver.cpp b/radio/src/targets/sky9x/audio_driver.cpp index ace46b80e..797b1df63 100644 --- a/radio/src/targets/sky9x/audio_driver.cpp +++ b/radio/src/targets/sky9x/audio_driver.cpp @@ -1,195 +1,195 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -volatile uint8_t dacStarted = false; - -#if !defined(SIMU) - -#if !defined(SOFTWARE_VOLUME) -const int8_t volumeScale[VOLUME_LEVEL_MAX+1] = -{ - 0, 2, 4, 6, 8, 10, 13, 17, 22, 27, 33, 40, - 64, 82, 96, 105, 112, 117, 120, 122, 124, 125, 126, 127 -} ; -#endif - -void setSampleRate(uint32_t frequency) -{ - Tc *ptc ; - uint32_t timer ; - - timer = Master_frequency / (8 * frequency) ; // MCK/8 and 100 000 Hz - if (timer > 65535) - timer = 65535 ; - if (timer < 2) - timer = 2 ; - - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_CHANNEL[1].TC_CCR = TC_CCR0_CLKDIS ; // Stop clock - ptc->TC_CHANNEL[1].TC_RC = timer ; // 100 000 Hz - ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ; - ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) -} - -// Start TIMER1 at 100000Hz, used for DACC trigger -void dacTimerStart() -{ - Tc *ptc ; - uint32_t timer ; - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x01000000L ; // Enable peripheral clock to TC1 - - timer = Master_frequency / 800000 ; // MCK/8 and 100 000 Hz - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 0 ; - ptc->TC_CHANNEL[1].TC_CMR = 0x00008000 ; // Waveform mode - ptc->TC_CHANNEL[1].TC_RC = timer ; // 100 000 Hz - ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ; - ptc->TC_CHANNEL[1].TC_CMR = 0x0009C001 ; // 0000 0000 0000 1001 1100 0000 0000 0001 - // MCK/8, set @ RA, Clear @ RC waveform - ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - // Sound_g.Frequency = 1000 ; -} - -// Configure DAC0 (or DAC1 for REVA) -// Not sure why PB14 has not be allocated to the DAC, although it is an EXTRA function -// So maybe it is automatically done -void dacInit() -{ - dacTimerStart() ; - - PMC->PMC_PCER0 |= 0x40000000L ; // Enable peripheral clock to DAC - - Dacc *dacptr = DACC; - -#if defined(REVA) - dacptr->DACC_MR = 0x0B010215L ; // 0000 1011 0000 0001 0000 0010 0001 0101 - dacptr->DACC_CHER = 2 ; // Enable channel 1 -#else - dacptr->DACC_MR = 0x0B000215L ; // 0000 1011 0000 0001 0000 0010 0001 0101 - dacptr->DACC_CHER = 1 ; // Enable channel 0 -#endif - - dacptr->DACC_CDR = 2048 ; // Half amplitude - - dacptr->DACC_PTCR = DACC_PTCR_TXTEN ; - NVIC_EnableIRQ(DACC_IRQn) ; -} - -inline void dacStart() -{ - PMC->PMC_PCER0 |= 0x40000000L ; // Enable peripheral clock to DAC - DACC->DACC_IER = DACC_IER_ENDTX ; - dacStarted = true; -} - -inline void dacStop() -{ - DACC->DACC_IDR = DACC_IDR_ENDTX ; // Disable interrupt - dacStarted = false; -} - -void audioConsumeCurrentBuffer() -{ - if (!dacStarted) { - dacStart(); - } -} - - -extern "C" void DAC_IRQHandler() -{ - uint32_t sr = DACC->DACC_ISR; - if (sr & DACC_ISR_ENDTX) { - audioQueue.buffersFifo.freeNextFilledBuffer(); - const AudioBuffer * nextBuffer = audioQueue.buffersFifo.getNextFilledBuffer(); - if (nextBuffer) { - // Try the first PDC buffer - if ((DACC->DACC_TCR == 0) && (DACC->DACC_TNCR == 0)) { - DACC->DACC_TPR = CONVERT_PTR_UINT(nextBuffer->data); - DACC->DACC_TCR = nextBuffer->size/2; - DACC->DACC_PTCR = DACC_PTCR_TXTEN; - return; - } - // Try the second PDC buffer - if (DACC->DACC_TNCR == 0) { - DACC->DACC_TNPR = CONVERT_PTR_UINT(nextBuffer->data); - DACC->DACC_TNCR = nextBuffer->size/2; - DACC->DACC_PTCR = DACC_PTCR_TXTEN; - return; - } - } - else { - dacStop(); - } - } -} - -// Sound routines -void audioInit() -{ - Pio * pioptr ; - - dacInit() ; - - pioptr = PIOA ; -#if defined(REVA) - pioptr->PIO_CODR = 0x00010000L ; // Set bit A16 OFF - pioptr->PIO_PER = 0x00010000L ; // Enable bit A16 (Stock buzzer) - pioptr->PIO_OER = 0x00010000L ; // Set bit A16 as output -#else - pioptr->PIO_CODR = 0x02000000L ; // Set bit A25 OFF - pioptr->PIO_PER = 0x02000000L ; // Enable bit A25 (Stock buzzer) - pioptr->PIO_OER = 0x02000000L ; // Set bit A25 as output -#endif - -#if defined(REVX) - configure_pins( PIO_PC26, PIN_ENABLE | PIN_LOW | PIN_OUTPUT | PIN_PORTC | PIN_NO_PULLUP ) ; - PIOC->PIO_CODR = PIO_PC26 ; -#endif -} - -void audioEnd() -{ - DACC->DACC_IDR = DACC_IDR_ENDTX ; - DACC->DACC_IDR = DACC_IDR_TXBUFE ; - NVIC_DisableIRQ(DACC_IRQn) ; - TWI0->TWI_IDR = TWI_IDR_TXCOMP ; - NVIC_DisableIRQ(TWI0_IRQn) ; - PMC->PMC_PCER0 &= ~0x00080000L ; // Disable peripheral clock to TWI0 - PMC->PMC_PCER0 &= ~0x40000000L ; // Disable peripheral clock to DAC -} - -#if !defined(SOFTWARE_VOLUME) -void setScaledVolume(uint8_t volume) -{ - volumeRequired = volumeScale[min(volume, VOLUME_LEVEL_MAX)]; - __disable_irq() ; - i2cCheck() ; - __enable_irq() ; -} -#endif - -#endif // #if !defined(SIMU) - +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +volatile uint8_t dacStarted = false; + +#if !defined(SIMU) + +#if !defined(SOFTWARE_VOLUME) +const int8_t volumeScale[VOLUME_LEVEL_MAX+1] = +{ + 0, 2, 4, 6, 8, 10, 13, 17, 22, 27, 33, 40, + 64, 82, 96, 105, 112, 117, 120, 122, 124, 125, 126, 127 +} ; +#endif + +void setSampleRate(uint32_t frequency) +{ + Tc *ptc ; + uint32_t timer ; + + timer = Master_frequency / (8 * frequency) ; // MCK/8 and 100 000 Hz + if (timer > 65535) + timer = 65535 ; + if (timer < 2) + timer = 2 ; + + ptc = TC0 ; // Tc block 0 (TC0-2) + ptc->TC_CHANNEL[1].TC_CCR = TC_CCR0_CLKDIS ; // Stop clock + ptc->TC_CHANNEL[1].TC_RC = timer ; // 100 000 Hz + ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ; + ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) +} + +// Start TIMER1 at 100000Hz, used for DACC trigger +void dacTimerStart() +{ + Tc *ptc ; + uint32_t timer ; + + // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 + PMC->PMC_PCER0 |= 0x01000000L ; // Enable peripheral clock to TC1 + + timer = Master_frequency / 800000 ; // MCK/8 and 100 000 Hz + ptc = TC0 ; // Tc block 0 (TC0-2) + ptc->TC_BCR = 0 ; // No sync + ptc->TC_BMR = 0 ; + ptc->TC_CHANNEL[1].TC_CMR = 0x00008000 ; // Waveform mode + ptc->TC_CHANNEL[1].TC_RC = timer ; // 100 000 Hz + ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ; + ptc->TC_CHANNEL[1].TC_CMR = 0x0009C001 ; // 0000 0000 0000 1001 1100 0000 0000 0001 + // MCK/8, set @ RA, Clear @ RC waveform + ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + // Sound_g.Frequency = 1000 ; +} + +// Configure DAC0 (or DAC1 for REVA) +// Not sure why PB14 has not be allocated to the DAC, although it is an EXTRA function +// So maybe it is automatically done +void dacInit() +{ + dacTimerStart() ; + + PMC->PMC_PCER0 |= 0x40000000L ; // Enable peripheral clock to DAC + + Dacc *dacptr = DACC; + +#if defined(REVA) + dacptr->DACC_MR = 0x0B010215L ; // 0000 1011 0000 0001 0000 0010 0001 0101 + dacptr->DACC_CHER = 2 ; // Enable channel 1 +#else + dacptr->DACC_MR = 0x0B000215L ; // 0000 1011 0000 0001 0000 0010 0001 0101 + dacptr->DACC_CHER = 1 ; // Enable channel 0 +#endif + + dacptr->DACC_CDR = 2048 ; // Half amplitude + + dacptr->DACC_PTCR = DACC_PTCR_TXTEN ; + NVIC_EnableIRQ(DACC_IRQn) ; +} + +inline void dacStart() +{ + PMC->PMC_PCER0 |= 0x40000000L ; // Enable peripheral clock to DAC + DACC->DACC_IER = DACC_IER_ENDTX ; + dacStarted = true; +} + +inline void dacStop() +{ + DACC->DACC_IDR = DACC_IDR_ENDTX ; // Disable interrupt + dacStarted = false; +} + +void audioConsumeCurrentBuffer() +{ + if (!dacStarted) { + dacStart(); + } +} + + +extern "C" void DAC_IRQHandler() +{ + uint32_t sr = DACC->DACC_ISR; + if (sr & DACC_ISR_ENDTX) { + audioQueue.buffersFifo.freeNextFilledBuffer(); + const AudioBuffer * nextBuffer = audioQueue.buffersFifo.getNextFilledBuffer(); + if (nextBuffer) { + // Try the first PDC buffer + if ((DACC->DACC_TCR == 0) && (DACC->DACC_TNCR == 0)) { + DACC->DACC_TPR = CONVERT_PTR_UINT(nextBuffer->data); + DACC->DACC_TCR = nextBuffer->size/2; + DACC->DACC_PTCR = DACC_PTCR_TXTEN; + return; + } + // Try the second PDC buffer + if (DACC->DACC_TNCR == 0) { + DACC->DACC_TNPR = CONVERT_PTR_UINT(nextBuffer->data); + DACC->DACC_TNCR = nextBuffer->size/2; + DACC->DACC_PTCR = DACC_PTCR_TXTEN; + return; + } + } + else { + dacStop(); + } + } +} + +// Sound routines +void audioInit() +{ + Pio * pioptr ; + + dacInit() ; + + pioptr = PIOA ; +#if defined(REVA) + pioptr->PIO_CODR = 0x00010000L ; // Set bit A16 OFF + pioptr->PIO_PER = 0x00010000L ; // Enable bit A16 (Stock buzzer) + pioptr->PIO_OER = 0x00010000L ; // Set bit A16 as output +#else + pioptr->PIO_CODR = 0x02000000L ; // Set bit A25 OFF + pioptr->PIO_PER = 0x02000000L ; // Enable bit A25 (Stock buzzer) + pioptr->PIO_OER = 0x02000000L ; // Set bit A25 as output +#endif + +#if defined(REVX) + configure_pins( PIO_PC26, PIN_ENABLE | PIN_LOW | PIN_OUTPUT | PIN_PORTC | PIN_NO_PULLUP ) ; + PIOC->PIO_CODR = PIO_PC26 ; +#endif +} + +void audioEnd() +{ + DACC->DACC_IDR = DACC_IDR_ENDTX ; + DACC->DACC_IDR = DACC_IDR_TXBUFE ; + NVIC_DisableIRQ(DACC_IRQn) ; + TWI0->TWI_IDR = TWI_IDR_TXCOMP ; + NVIC_DisableIRQ(TWI0_IRQn) ; + PMC->PMC_PCER0 &= ~0x00080000L ; // Disable peripheral clock to TWI0 + PMC->PMC_PCER0 &= ~0x40000000L ; // Disable peripheral clock to DAC +} + +#if !defined(SOFTWARE_VOLUME) +void setScaledVolume(uint8_t volume) +{ + volumeRequired = volumeScale[min(volume, VOLUME_LEVEL_MAX)]; + __disable_irq() ; + i2cCheck() ; + __enable_irq() ; +} +#endif + +#endif // #if !defined(SIMU) + diff --git a/radio/src/targets/sky9x/board.cpp b/radio/src/targets/sky9x/board.cpp index b778a6a47..359559c61 100644 --- a/radio/src/targets/sky9x/board.cpp +++ b/radio/src/targets/sky9x/board.cpp @@ -1,609 +1,609 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#if defined(AR9X) -#include "i2c_driver.h" -#endif - -uint16_t ResetReason; -uint32_t Master_frequency ; -volatile uint32_t Tenms ; -volatile uint8_t lcdLock; -volatile uint32_t lcdInputs; - -#if !defined(REVA) -uint16_t Current_analogue; -uint16_t Current_max; -uint32_t Current_accumulator; -uint32_t Current_used; -#endif - -extern "C" void sam_boot( void ) ; - -// Prototype -// Free pins (PA16 is stock buzzer) -// PA23, PA24, PA25, PB7, PB13 -// PC20, PC21(labelled 17), PC22, PC24 -// REVB -// PA25, use for stock buzzer -// PB14, PB6 -// PC21, PC19, PC15 (PPM2 output) -inline void config_free_pins() -{ -#if defined(REVA) - Pio * pioptr = PIOA ; - pioptr->PIO_PER = 0x03800000L ; // Enable bits A25,24,23 - pioptr->PIO_ODR = 0x03800000L ; // Set as input - pioptr->PIO_PUER = 0x03800000L ; // Enable pullups - - pioptr = PIOB ; - pioptr->PIO_PER = 0x00002080L ; // Enable bits B13, 7 - pioptr->PIO_ODR = 0x00002080L ; // Set as input - pioptr->PIO_PUER = 0x00002080L ; // Enable pullups - - pioptr = PIOC ; - pioptr->PIO_PER = 0x01700000L ; // Enable bits C24,22,21,20 - pioptr->PIO_ODR = 0x01700000L ; // Set as input - pioptr->PIO_PUER = 0x01700000L ; // Enable pullups -#else - configure_pins( PIO_PB14, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; -#endif -} - -// Assumes PMC has already enabled clocks to ports -inline void setup_switches() -{ -#if defined(REVA) - Pio *pioptr = PIOA ; - pioptr->PIO_PER = 0xF8008184 ; // Enable bits - pioptr->PIO_ODR = 0xF8008184 ; // Set bits input - pioptr->PIO_PUER = 0xF8008184 ; // Set bits with pullups - - pioptr = PIOB ; - pioptr->PIO_PER = 0x00000010 ; // Enable bits - pioptr->PIO_ODR = 0x00000010 ; // Set bits input - pioptr->PIO_PUER = 0x00000010 ; // Set bits with pullups - - pioptr = PIOC ; - pioptr->PIO_PER = 0x10014900 ; // Enable bits - pioptr->PIO_ODR = 0x10014900 ; // Set bits input - pioptr->PIO_PUER = 0x10014900 ; // Set bits with pullups -#else - configure_pins( 0x01808087, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP ) ; - configure_pins( 0x00000030, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; - configure_pins( 0x91114900, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_PULLUP ) ; -#endif -} - -#if !defined(SIMU) -inline void UART3_Configure(uint32_t baudrate, uint32_t masterClock) -{ - Uart *pUart = BT_USART; - - /* Configure PIO */ - configure_pins( (PIO_PB2 | PIO_PB3), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTB | PIN_NO_PULLUP ) ; - - /* Configure PMC */ - PMC->PMC_PCER0 = 1 << BT_ID; - - /* Reset and disable receiver & transmitter */ - pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX - | UART_CR_RXDIS | UART_CR_TXDIS; - - /* Configure mode */ - pUart->UART_MR = 0x800 ; // NORMAL, No Parity - - /* Configure baudrate */ - /* Asynchronous, no oversampling */ - pUart->UART_BRGR = ( (masterClock / baudrate) + 8 ) / 16; - - /* Disable PDC channel */ - pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; - - /* Enable receiver and transmitter */ - pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; - -#if 0 - pUart->UART_IER = UART_IER_RXRDY ; - NVIC_EnableIRQ(UART1_IRQn) ; -#endif -} - -void UART3_Stop() -{ - BT_USART->UART_IDR = UART_IDR_RXRDY ; - NVIC_DisableIRQ(UART1_IRQn) ; -} - -// Starts TIMER0 at full speed (MCK/2) for delay timing -// @ 36MHz this is 18MHz -// This was 6 MHz, we may need to slow it to TIMER_CLOCK2 (MCK/8=4.5 MHz) -inline void start_timer0() -{ - Tc *ptc ; - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x00800000L ; // Enable peripheral clock to TC0 - - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 2 ; - ptc->TC_CHANNEL[0].TC_CMR = 0x00008001 ; // Waveform mode MCK/8 for 36MHz osc. - ptc->TC_CHANNEL[0].TC_RC = 0xFFF0 ; - ptc->TC_CHANNEL[0].TC_RA = 0 ; - ptc->TC_CHANNEL[0].TC_CMR = 0x00008040 ; // 0000 0000 0000 0000 1000 0000 0100 0000, stop at regC - ptc->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) -} - -// TIMER2 at 200Hz, provides 5mS for sound and 10mS tick on interrupt -// Starts TIMER2 at 200Hz, commentd out drive of TIOA2 (A26, EXT2) -inline void start_timer2() -{ - Tc *ptc ; - uint32_t timer ; - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x02000000L ; // Enable peripheral clock to TC2 - - timer = Master_frequency / 12800 / 2; // MCK/128 and 200 Hz - - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 0 ; - ptc->TC_CHANNEL[2].TC_CMR = 0x00008000 ; // Waveform mode - ptc->TC_CHANNEL[2].TC_RC = timer ; // 10 Hz - ptc->TC_CHANNEL[2].TC_RA = timer >> 1 ; - ptc->TC_CHANNEL[2].TC_CMR = 0x0009C003 ; // 0000 0000 0000 1001 1100 0000 0000 0011 - ptc->TC_CHANNEL[2].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - - NVIC_EnableIRQ(TC2_IRQn) ; - TC0->TC_CHANNEL[2].TC_IER = TC_IER0_CPCS ; -} - -void interrupt5ms() -{ - static uint32_t pre_scale ; // Used to get 10 Hz counter - - HAPTIC_HEARTBEAT(); - AUDIO_HEARTBEAT(); - - if ( ++pre_scale >= 2 ) { - BUZZER_HEARTBEAT(); - pre_scale = 0 ; - per10ms(); - } -} - -extern "C" void TC2_IRQHandler() -{ - uint32_t dummy; - - /* Clear status bit to acknowledge interrupt */ - dummy = TC0->TC_CHANNEL[2].TC_SR; - (void) dummy ; // Discard value - prevents compiler warning - - interrupt5ms(); -} - -// PWM used for PPM generation, and LED Backlight -// Output pin PB5 not used, PA17 used as PWMH3 peripheral C -// PWM peripheral ID = 31 (0x80000000) -// Ensure PB5 is three state/input, used on REVB for MENU KEY - -// Configure PWM3 as PPM drive, -// PWM0 is LED backlight PWM on PWMH0 -// This is PC18 peripheral B, Also enable PC22 peripheral B, this is PPM-JACK (PWML3) -// -// REVB board: -// PWML2, output as peripheral C on PA16, is for HAPTIC -// For testing, just drive it out with PWM -// PWML1 for PPM2 output as peripheral B on PC15 -// For testing, just drive it out with PWM -void init_pwm() -{ - Pwm *pwmptr ; - uint32_t timer ; - - PMC->PMC_PCER0 |= ( 1 << ID_PWM ) ; // Enable peripheral clock to PWM - - MATRIX->CCFG_SYSIO |= 0x00000020L ; // Disable TDO let PB5 work! - - /* Configure PIO */ -#if defined(REVA) - Pio *pioptr = PIOB ; - pioptr->PIO_PER = 0x00000020L ; // Enable bit B5 - pioptr->PIO_ODR = 0x00000020L ; // set as input -#else - configure_pins( PIO_PA16, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_C | PIN_PORTA | PIN_NO_PULLUP ) ; -#endif - - configure_pins( PIO_PC18, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; - -#if !defined(REVA) - configure_pins( PIO_PC22, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; -#endif - - // Configure clock - depends on MCK frequency - timer = Master_frequency / 2000000 ; - timer |= ( Master_frequency / ( 32* 10000 ) ) << 16 ; - timer &= 0x00FF00FF ; - - pwmptr = PWM ; - pwmptr->PWM_CLK = 0x05000000 | timer ; // MCK for DIVA, DIVA = 18 gives 0.5uS clock period @35MHz // MCK/32 / timer = 10000Hz for CLKB - - // PWM0 for LED backlight - pwmptr->PWM_CH_NUM[0].PWM_CMR = 0x0000000C ; // CLKB - pwmptr->PWM_CH_NUM[0].PWM_CPDR = 100 ; // Period - pwmptr->PWM_CH_NUM[0].PWM_CPDRUPD = 100 ; // Period - pwmptr->PWM_CH_NUM[0].PWM_CDTY = 40 ; // Duty - pwmptr->PWM_CH_NUM[0].PWM_CDTYUPD = 40 ; // Duty - pwmptr->PWM_ENA = PWM_ENA_CHID0 ; // Enable channel 0 - -#if !defined(REVA) - // PWM2 for HAPTIC drive 100Hz test - pwmptr->PWM_CH_NUM[2].PWM_CMR = 0x0000000C ; // CLKB - pwmptr->PWM_CH_NUM[2].PWM_CPDR = 100 ; // Period - pwmptr->PWM_CH_NUM[2].PWM_CPDRUPD = 100 ; // Period - pwmptr->PWM_CH_NUM[2].PWM_CDTY = 40 ; // Duty - pwmptr->PWM_CH_NUM[2].PWM_CDTYUPD = 40 ; // Duty - pwmptr->PWM_OOV &= ~0x00040000 ; // Force low - pwmptr->PWM_OSS = 0x00040000 ; // Force low - // pwmptr->PWM_ENA = PWM_ENA_CHID2 ; // Enable channel 2 // TODO on REVA? -#endif -} - -// LCD i/o pins -// LCD_RES PC27 -// LCD_CS1 PC26 -// LCD_E PC12 -// LCD_RnW PC13 -// LCD_A0 PC15 -// LCD_D0 PC0 -// LCD_D1 PC7 -// LCD_D2 PC6 -// LCD_D3 PC5 -// LCD_D4 PC4 -// LCD_D5 PC3 -// LCD_D6 PC2 -// LCD_D7 PC1 - -#define LCD_DATA 0x000000FFL -#if defined(REVA) -#define LCD_A0 0x00008000L -#else -#define LCD_A0 0x00000080L -#endif -#define LCD_RnW 0x00002000L -#define LCD_E 0x00001000L -#define LCD_CS1 0x04000000L -#define LCD_RES 0x08000000L - -void configure_pins( uint32_t pins, uint16_t config ) -{ - Pio *pioptr ; - - pioptr = PIOA + ( ( config & PIN_PORT_MASK ) >> 6) ; - if ( config & PIN_PULLUP ) - { - pioptr->PIO_PPDDR = pins ; - pioptr->PIO_PUER = pins ; - } - else - { - pioptr->PIO_PUDR = pins ; - } - - if ( config & PIN_PULLDOWN ) - { - pioptr->PIO_PUDR = pins ; - pioptr->PIO_PPDER = pins ; - } - else - { - pioptr->PIO_PPDDR = pins ; - } - - if ( config & PIN_HIGH ) - { - pioptr->PIO_SODR = pins ; - } - else - { - pioptr->PIO_CODR = pins ; - } - - if ( config & PIN_INPUT ) - { - pioptr->PIO_ODR = pins ; - } - else - { - pioptr->PIO_OER = pins ; - } - - if ( config & PIN_PERI_MASK_L ) - { - pioptr->PIO_ABCDSR[0] |= pins ; - } - else - { - pioptr->PIO_ABCDSR[0] &= ~pins ; - } - if ( config & PIN_PERI_MASK_H ) - { - pioptr->PIO_ABCDSR[1] |= pins ; - } - else - { - pioptr->PIO_ABCDSR[1] &= ~pins ; - } - - if ( config & PIN_ENABLE ) - { - pioptr->PIO_PER = pins ; - } - else - { - pioptr->PIO_PDR = pins ; - } -} - -void opentxBootloader(); - -// Set up for volume control (TWI0) -// Need PA3 and PA4 set to peripheral A -#if !defined(AR9X) -void i2cInit() -{ - Pio *pioptr; - uint32_t timing; - - PMC->PMC_PCER0 |= 0x00080000L ; // Enable peripheral clock to TWI0 - - TWI0->TWI_CR = TWI_CR_SWRST ; // Reset in case we are restarting - - /* Configure PIO */ - pioptr = PIOA ; - pioptr->PIO_ABCDSR[0] &= ~0x00000018 ; // Peripheral A - pioptr->PIO_ABCDSR[1] &= ~0x00000018 ; // Peripheral A - pioptr->PIO_PDR = 0x00000018 ; // Assign to peripheral - - timing = Master_frequency * 5 / 1000000 ; // 5uS high and low - timing += 15 - 4 ; - timing /= 16 ; - timing |= timing << 8 ; - - TWI0->TWI_CWGR = 0x00040000 | timing ; // TWI clock set - TWI0->TWI_CR = TWI_CR_MSEN | TWI_CR_SVDIS ; // Master mode enable - TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing - NVIC_EnableIRQ(TWI0_IRQn) ; -} -#endif - -void boardInit() -{ - // TODO this is not clean, completely unuseful, but prevents the bootloader from being optimized away... - uint8_t dummy[3]; - memcpy(&dummy, BootCode, sizeof(dummy)); - for (unsigned int i=0; iRSTC_SR; - - MATRIX->CCFG_SYSIO |= 0x000000F0L ; // Disable syspins, enable B4,5,6,7 - - PMC->PMC_PCER0 = (1<PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) - -#if defined(REVA) - // On REVB, PA21 is used as AD8, and measures current consumption. - pioptr = PIOA ; - pioptr->PIO_PER = PIO_PA21 ; // Enable bit A21 (EXT3) - pioptr->PIO_OER = PIO_PA21 ; // Set bit A21 as output - pioptr->PIO_SODR = PIO_PA21 ; // Set bit A21 ON - - // Configure RF_power (PC17) and PPM-jack-in (PC19), neither need pullups - pioptr->PIO_PER = 0x000A0000L ; // Enable bit C19, C17 - pioptr->PIO_ODR = 0x000A0000L ; // Set bits C19 and C17 as input -#endif - -#if !defined(REVA) - pwrInit() ; -#endif - - config_free_pins() ; - - // Next section configures the key inputs on the LCD data - pioptr = PIOC; -#if defined(REVA) - pioptr->PIO_PER = 0x0000003DL ; // Enable bits 2,3,4,5, 0 - pioptr->PIO_OER = PIO_PC0 ; // Set bit 0 output - pioptr->PIO_ODR = 0x0000003CL ; // Set bits 2, 3, 4, 5 input - pioptr->PIO_PUER = 0x0000003CL ; // Set bits 2, 3, 4, 5 with pullups -#else - pioptr->PIO_PER = 0x0000003BL ; // Enable bits 1,3,4,5, 0 - pioptr->PIO_OER = PIO_PC0 ; // Set bit 0 output - pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input - pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups -#endif - - pioptr = PIOB ; -#if defined(REVA) - pioptr->PIO_PUER = PIO_PB6 ; // Enable pullup on bit B6 (MENU) - pioptr->PIO_PER = PIO_PB6 ; // Enable bit B6 -#else - pioptr->PIO_PUER = PIO_PB5 ; // Enable pullup on bit B5 (MENU) - pioptr->PIO_PER = PIO_PB5 ; // Enable bit B5 -#endif - - setup_switches() ; - - // Enable PCK2 on PB3, This is for testing of Timer 2 working - // It will be used as serial data to the Bluetooth module - pioptr->PIO_ABCDSR[0] |= PIO_PB3 ; // Peripheral B - pioptr->PIO_ABCDSR[1] &= ~PIO_PB3 ; // Peripheral B - pioptr->PIO_PDR = PIO_PB3 ; // Assign to peripheral - PMC->PMC_SCER |= 0x0400 ; // PCK2 enabled - PMC->PMC_PCK[2] = 2 ; // PCK2 is PLLA - - start_timer2() ; - start_timer0() ; - adcInit() ; - init_pwm() ; - - __enable_irq(); - - audioInit(); - - i2cInit(); - - eepromInit(); - -#if defined(ROTARY_ENCODERS) - rotencInit(); -#endif - - init_SDcard(); -} -#else -void boardInit() -{ -} -#endif - -uint8_t temperature = 0; // Raw temp reading -uint8_t maxTemperature = 0 ; // Raw temp reading - -void end_bt_tx_interrupt() -{ - Uart *pUart = BT_USART ; - pUart->UART_IDR = UART_IDR_TXBUFE ; - NVIC_DisableIRQ(UART1_IRQn) ; -} - -#if !defined(REVA) -uint16_t getCurrent() -{ - static uint16_t Current ; - static uint32_t Current_sum ; - static uint8_t Current_count ; - - Current_sum += anaIn(8); // TODO enum - if (++Current_count >= 50) { - Current = Current_sum / 5 ; - Current_sum = 0 ; - Current_count = 0 ; - } - - uint32_t current_scale = 488 + g_eeGeneral.txCurrentCalibration ; - return (current_scale * Current) / 8192; -} -#endif - -uint8_t getTemperature() -{ - return temperature + g_eeGeneral.temperatureCalib; -} - -#define STICK_LV_GAIN 0x01 -#define STICK_LH_GAIN 0x02 -#define STICK_RV_GAIN 0x04 -#define STICK_RH_GAIN 0x08 - -#define GAIN_LV 0x00080000 -#define GAIN_LH 0x00000020 -#define GAIN_RV 0x20000000 -#define GAIN_RH 0x00000008 - -#define OFF_LV 0x00000200 -#define OFF_LH 0x00000004 -#define OFF_RV 0x00004000 -#define OFF_RH 0x00000002 - -void setSticksGain(uint8_t gains) -{ - Adc *padc ; - uint32_t gain ; - uint32_t offset ; - - gain = 0 ; - offset = 0 ; - padc = ADC ; - - if ( gains & STICK_LV_GAIN ) { - gain |= GAIN_LV ; - offset |= OFF_LV ; - } - if ( gains & STICK_LH_GAIN ) { - gain |= GAIN_LH ; - offset |= OFF_LH ; - } - if ( gains & STICK_RV_GAIN ) { - gain |= GAIN_RV ; - offset |= OFF_RV ; - } - if ( gains & STICK_RH_GAIN ) { - gain |= GAIN_RH ; - offset |= OFF_RH ; - } - - padc->ADC_CGR = gain; - padc->ADC_COR = offset; -} - - -#if !defined(REVA) -void calcConsumption() -{ - Current_accumulator += Current_analogue ; - static uint32_t OneSecTimer; - if (++OneSecTimer >= 100) { - OneSecTimer -= 100 ; - Current_used += Current_accumulator / 100 ; // milliAmpSeconds (but scaled) - Current_accumulator = 0 ; - } -} -#endif - -void checkTrainerSettings() -{ - if (SLAVE_MODE()) { - PIOC->PIO_PDR = PIO_PC22; - } - else { - PIOC->PIO_PER = PIO_PC22; - } -} - -uint16_t getBatteryVoltage() -{ - int32_t instant_vbat = anaIn(TX_VOLTAGE); // using filtered ADC value on purpose - instant_vbat = (instant_vbat + instant_vbat*(g_eeGeneral.txVoltageCalibration)/128) * 4191; - instant_vbat /= 5530; - return (uint16_t)instant_vbat; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#if defined(AR9X) +#include "i2c_driver.h" +#endif + +uint16_t ResetReason; +uint32_t Master_frequency ; +volatile uint32_t Tenms ; +volatile uint8_t lcdLock; +volatile uint32_t lcdInputs; + +#if !defined(REVA) +uint16_t Current_analogue; +uint16_t Current_max; +uint32_t Current_accumulator; +uint32_t Current_used; +#endif + +extern "C" void sam_boot( void ) ; + +// Prototype +// Free pins (PA16 is stock buzzer) +// PA23, PA24, PA25, PB7, PB13 +// PC20, PC21(labelled 17), PC22, PC24 +// REVB +// PA25, use for stock buzzer +// PB14, PB6 +// PC21, PC19, PC15 (PPM2 output) +inline void config_free_pins() +{ +#if defined(REVA) + Pio * pioptr = PIOA ; + pioptr->PIO_PER = 0x03800000L ; // Enable bits A25,24,23 + pioptr->PIO_ODR = 0x03800000L ; // Set as input + pioptr->PIO_PUER = 0x03800000L ; // Enable pullups + + pioptr = PIOB ; + pioptr->PIO_PER = 0x00002080L ; // Enable bits B13, 7 + pioptr->PIO_ODR = 0x00002080L ; // Set as input + pioptr->PIO_PUER = 0x00002080L ; // Enable pullups + + pioptr = PIOC ; + pioptr->PIO_PER = 0x01700000L ; // Enable bits C24,22,21,20 + pioptr->PIO_ODR = 0x01700000L ; // Set as input + pioptr->PIO_PUER = 0x01700000L ; // Enable pullups +#else + configure_pins( PIO_PB14, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; +#endif +} + +// Assumes PMC has already enabled clocks to ports +inline void setup_switches() +{ +#if defined(REVA) + Pio *pioptr = PIOA ; + pioptr->PIO_PER = 0xF8008184 ; // Enable bits + pioptr->PIO_ODR = 0xF8008184 ; // Set bits input + pioptr->PIO_PUER = 0xF8008184 ; // Set bits with pullups + + pioptr = PIOB ; + pioptr->PIO_PER = 0x00000010 ; // Enable bits + pioptr->PIO_ODR = 0x00000010 ; // Set bits input + pioptr->PIO_PUER = 0x00000010 ; // Set bits with pullups + + pioptr = PIOC ; + pioptr->PIO_PER = 0x10014900 ; // Enable bits + pioptr->PIO_ODR = 0x10014900 ; // Set bits input + pioptr->PIO_PUER = 0x10014900 ; // Set bits with pullups +#else + configure_pins( 0x01808087, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP ) ; + configure_pins( 0x00000030, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; + configure_pins( 0x91114900, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_PULLUP ) ; +#endif +} + +#if !defined(SIMU) +inline void UART3_Configure(uint32_t baudrate, uint32_t masterClock) +{ + Uart *pUart = BT_USART; + + /* Configure PIO */ + configure_pins( (PIO_PB2 | PIO_PB3), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTB | PIN_NO_PULLUP ) ; + + /* Configure PMC */ + PMC->PMC_PCER0 = 1 << BT_ID; + + /* Reset and disable receiver & transmitter */ + pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS; + + /* Configure mode */ + pUart->UART_MR = 0x800 ; // NORMAL, No Parity + + /* Configure baudrate */ + /* Asynchronous, no oversampling */ + pUart->UART_BRGR = ( (masterClock / baudrate) + 8 ) / 16; + + /* Disable PDC channel */ + pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; + + /* Enable receiver and transmitter */ + pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; + +#if 0 + pUart->UART_IER = UART_IER_RXRDY ; + NVIC_EnableIRQ(UART1_IRQn) ; +#endif +} + +void UART3_Stop() +{ + BT_USART->UART_IDR = UART_IDR_RXRDY ; + NVIC_DisableIRQ(UART1_IRQn) ; +} + +// Starts TIMER0 at full speed (MCK/2) for delay timing +// @ 36MHz this is 18MHz +// This was 6 MHz, we may need to slow it to TIMER_CLOCK2 (MCK/8=4.5 MHz) +inline void start_timer0() +{ + Tc *ptc ; + + // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 + PMC->PMC_PCER0 |= 0x00800000L ; // Enable peripheral clock to TC0 + + ptc = TC0 ; // Tc block 0 (TC0-2) + ptc->TC_BCR = 0 ; // No sync + ptc->TC_BMR = 2 ; + ptc->TC_CHANNEL[0].TC_CMR = 0x00008001 ; // Waveform mode MCK/8 for 36MHz osc. + ptc->TC_CHANNEL[0].TC_RC = 0xFFF0 ; + ptc->TC_CHANNEL[0].TC_RA = 0 ; + ptc->TC_CHANNEL[0].TC_CMR = 0x00008040 ; // 0000 0000 0000 0000 1000 0000 0100 0000, stop at regC + ptc->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) +} + +// TIMER2 at 200Hz, provides 5mS for sound and 10mS tick on interrupt +// Starts TIMER2 at 200Hz, commentd out drive of TIOA2 (A26, EXT2) +inline void start_timer2() +{ + Tc *ptc ; + uint32_t timer ; + + // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 + PMC->PMC_PCER0 |= 0x02000000L ; // Enable peripheral clock to TC2 + + timer = Master_frequency / 12800 / 2; // MCK/128 and 200 Hz + + ptc = TC0 ; // Tc block 0 (TC0-2) + ptc->TC_BCR = 0 ; // No sync + ptc->TC_BMR = 0 ; + ptc->TC_CHANNEL[2].TC_CMR = 0x00008000 ; // Waveform mode + ptc->TC_CHANNEL[2].TC_RC = timer ; // 10 Hz + ptc->TC_CHANNEL[2].TC_RA = timer >> 1 ; + ptc->TC_CHANNEL[2].TC_CMR = 0x0009C003 ; // 0000 0000 0000 1001 1100 0000 0000 0011 + ptc->TC_CHANNEL[2].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + + NVIC_EnableIRQ(TC2_IRQn) ; + TC0->TC_CHANNEL[2].TC_IER = TC_IER0_CPCS ; +} + +void interrupt5ms() +{ + static uint32_t pre_scale ; // Used to get 10 Hz counter + + HAPTIC_HEARTBEAT(); + AUDIO_HEARTBEAT(); + + if ( ++pre_scale >= 2 ) { + BUZZER_HEARTBEAT(); + pre_scale = 0 ; + per10ms(); + } +} + +extern "C" void TC2_IRQHandler() +{ + uint32_t dummy; + + /* Clear status bit to acknowledge interrupt */ + dummy = TC0->TC_CHANNEL[2].TC_SR; + (void) dummy ; // Discard value - prevents compiler warning + + interrupt5ms(); +} + +// PWM used for PPM generation, and LED Backlight +// Output pin PB5 not used, PA17 used as PWMH3 peripheral C +// PWM peripheral ID = 31 (0x80000000) +// Ensure PB5 is three state/input, used on REVB for MENU KEY + +// Configure PWM3 as PPM drive, +// PWM0 is LED backlight PWM on PWMH0 +// This is PC18 peripheral B, Also enable PC22 peripheral B, this is PPM-JACK (PWML3) +// +// REVB board: +// PWML2, output as peripheral C on PA16, is for HAPTIC +// For testing, just drive it out with PWM +// PWML1 for PPM2 output as peripheral B on PC15 +// For testing, just drive it out with PWM +void init_pwm() +{ + Pwm *pwmptr ; + uint32_t timer ; + + PMC->PMC_PCER0 |= ( 1 << ID_PWM ) ; // Enable peripheral clock to PWM + + MATRIX->CCFG_SYSIO |= 0x00000020L ; // Disable TDO let PB5 work! + + /* Configure PIO */ +#if defined(REVA) + Pio *pioptr = PIOB ; + pioptr->PIO_PER = 0x00000020L ; // Enable bit B5 + pioptr->PIO_ODR = 0x00000020L ; // set as input +#else + configure_pins( PIO_PA16, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_C | PIN_PORTA | PIN_NO_PULLUP ) ; +#endif + + configure_pins( PIO_PC18, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; + +#if !defined(REVA) + configure_pins( PIO_PC22, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; +#endif + + // Configure clock - depends on MCK frequency + timer = Master_frequency / 2000000 ; + timer |= ( Master_frequency / ( 32* 10000 ) ) << 16 ; + timer &= 0x00FF00FF ; + + pwmptr = PWM ; + pwmptr->PWM_CLK = 0x05000000 | timer ; // MCK for DIVA, DIVA = 18 gives 0.5uS clock period @35MHz // MCK/32 / timer = 10000Hz for CLKB + + // PWM0 for LED backlight + pwmptr->PWM_CH_NUM[0].PWM_CMR = 0x0000000C ; // CLKB + pwmptr->PWM_CH_NUM[0].PWM_CPDR = 100 ; // Period + pwmptr->PWM_CH_NUM[0].PWM_CPDRUPD = 100 ; // Period + pwmptr->PWM_CH_NUM[0].PWM_CDTY = 40 ; // Duty + pwmptr->PWM_CH_NUM[0].PWM_CDTYUPD = 40 ; // Duty + pwmptr->PWM_ENA = PWM_ENA_CHID0 ; // Enable channel 0 + +#if !defined(REVA) + // PWM2 for HAPTIC drive 100Hz test + pwmptr->PWM_CH_NUM[2].PWM_CMR = 0x0000000C ; // CLKB + pwmptr->PWM_CH_NUM[2].PWM_CPDR = 100 ; // Period + pwmptr->PWM_CH_NUM[2].PWM_CPDRUPD = 100 ; // Period + pwmptr->PWM_CH_NUM[2].PWM_CDTY = 40 ; // Duty + pwmptr->PWM_CH_NUM[2].PWM_CDTYUPD = 40 ; // Duty + pwmptr->PWM_OOV &= ~0x00040000 ; // Force low + pwmptr->PWM_OSS = 0x00040000 ; // Force low + // pwmptr->PWM_ENA = PWM_ENA_CHID2 ; // Enable channel 2 // TODO on REVA? +#endif +} + +// LCD i/o pins +// LCD_RES PC27 +// LCD_CS1 PC26 +// LCD_E PC12 +// LCD_RnW PC13 +// LCD_A0 PC15 +// LCD_D0 PC0 +// LCD_D1 PC7 +// LCD_D2 PC6 +// LCD_D3 PC5 +// LCD_D4 PC4 +// LCD_D5 PC3 +// LCD_D6 PC2 +// LCD_D7 PC1 + +#define LCD_DATA 0x000000FFL +#if defined(REVA) +#define LCD_A0 0x00008000L +#else +#define LCD_A0 0x00000080L +#endif +#define LCD_RnW 0x00002000L +#define LCD_E 0x00001000L +#define LCD_CS1 0x04000000L +#define LCD_RES 0x08000000L + +void configure_pins( uint32_t pins, uint16_t config ) +{ + Pio *pioptr ; + + pioptr = PIOA + ( ( config & PIN_PORT_MASK ) >> 6) ; + if ( config & PIN_PULLUP ) + { + pioptr->PIO_PPDDR = pins ; + pioptr->PIO_PUER = pins ; + } + else + { + pioptr->PIO_PUDR = pins ; + } + + if ( config & PIN_PULLDOWN ) + { + pioptr->PIO_PUDR = pins ; + pioptr->PIO_PPDER = pins ; + } + else + { + pioptr->PIO_PPDDR = pins ; + } + + if ( config & PIN_HIGH ) + { + pioptr->PIO_SODR = pins ; + } + else + { + pioptr->PIO_CODR = pins ; + } + + if ( config & PIN_INPUT ) + { + pioptr->PIO_ODR = pins ; + } + else + { + pioptr->PIO_OER = pins ; + } + + if ( config & PIN_PERI_MASK_L ) + { + pioptr->PIO_ABCDSR[0] |= pins ; + } + else + { + pioptr->PIO_ABCDSR[0] &= ~pins ; + } + if ( config & PIN_PERI_MASK_H ) + { + pioptr->PIO_ABCDSR[1] |= pins ; + } + else + { + pioptr->PIO_ABCDSR[1] &= ~pins ; + } + + if ( config & PIN_ENABLE ) + { + pioptr->PIO_PER = pins ; + } + else + { + pioptr->PIO_PDR = pins ; + } +} + +void opentxBootloader(); + +// Set up for volume control (TWI0) +// Need PA3 and PA4 set to peripheral A +#if !defined(AR9X) +void i2cInit() +{ + Pio *pioptr; + uint32_t timing; + + PMC->PMC_PCER0 |= 0x00080000L ; // Enable peripheral clock to TWI0 + + TWI0->TWI_CR = TWI_CR_SWRST ; // Reset in case we are restarting + + /* Configure PIO */ + pioptr = PIOA ; + pioptr->PIO_ABCDSR[0] &= ~0x00000018 ; // Peripheral A + pioptr->PIO_ABCDSR[1] &= ~0x00000018 ; // Peripheral A + pioptr->PIO_PDR = 0x00000018 ; // Assign to peripheral + + timing = Master_frequency * 5 / 1000000 ; // 5uS high and low + timing += 15 - 4 ; + timing /= 16 ; + timing |= timing << 8 ; + + TWI0->TWI_CWGR = 0x00040000 | timing ; // TWI clock set + TWI0->TWI_CR = TWI_CR_MSEN | TWI_CR_SVDIS ; // Master mode enable + TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing + NVIC_EnableIRQ(TWI0_IRQn) ; +} +#endif + +void boardInit() +{ + // TODO this is not clean, completely unuseful, but prevents the bootloader from being optimized away... + uint8_t dummy[3]; + memcpy(&dummy, BootCode, sizeof(dummy)); + for (unsigned int i=0; iRSTC_SR; + + MATRIX->CCFG_SYSIO |= 0x000000F0L ; // Disable syspins, enable B4,5,6,7 + + PMC->PMC_PCER0 = (1<PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) + +#if defined(REVA) + // On REVB, PA21 is used as AD8, and measures current consumption. + pioptr = PIOA ; + pioptr->PIO_PER = PIO_PA21 ; // Enable bit A21 (EXT3) + pioptr->PIO_OER = PIO_PA21 ; // Set bit A21 as output + pioptr->PIO_SODR = PIO_PA21 ; // Set bit A21 ON + + // Configure RF_power (PC17) and PPM-jack-in (PC19), neither need pullups + pioptr->PIO_PER = 0x000A0000L ; // Enable bit C19, C17 + pioptr->PIO_ODR = 0x000A0000L ; // Set bits C19 and C17 as input +#endif + +#if !defined(REVA) + pwrInit() ; +#endif + + config_free_pins() ; + + // Next section configures the key inputs on the LCD data + pioptr = PIOC; +#if defined(REVA) + pioptr->PIO_PER = 0x0000003DL ; // Enable bits 2,3,4,5, 0 + pioptr->PIO_OER = PIO_PC0 ; // Set bit 0 output + pioptr->PIO_ODR = 0x0000003CL ; // Set bits 2, 3, 4, 5 input + pioptr->PIO_PUER = 0x0000003CL ; // Set bits 2, 3, 4, 5 with pullups +#else + pioptr->PIO_PER = 0x0000003BL ; // Enable bits 1,3,4,5, 0 + pioptr->PIO_OER = PIO_PC0 ; // Set bit 0 output + pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input + pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups +#endif + + pioptr = PIOB ; +#if defined(REVA) + pioptr->PIO_PUER = PIO_PB6 ; // Enable pullup on bit B6 (MENU) + pioptr->PIO_PER = PIO_PB6 ; // Enable bit B6 +#else + pioptr->PIO_PUER = PIO_PB5 ; // Enable pullup on bit B5 (MENU) + pioptr->PIO_PER = PIO_PB5 ; // Enable bit B5 +#endif + + setup_switches() ; + + // Enable PCK2 on PB3, This is for testing of Timer 2 working + // It will be used as serial data to the Bluetooth module + pioptr->PIO_ABCDSR[0] |= PIO_PB3 ; // Peripheral B + pioptr->PIO_ABCDSR[1] &= ~PIO_PB3 ; // Peripheral B + pioptr->PIO_PDR = PIO_PB3 ; // Assign to peripheral + PMC->PMC_SCER |= 0x0400 ; // PCK2 enabled + PMC->PMC_PCK[2] = 2 ; // PCK2 is PLLA + + start_timer2() ; + start_timer0() ; + adcInit() ; + init_pwm() ; + + __enable_irq(); + + audioInit(); + + i2cInit(); + + eepromInit(); + +#if defined(ROTARY_ENCODERS) + rotencInit(); +#endif + + init_SDcard(); +} +#else +void boardInit() +{ +} +#endif + +uint8_t temperature = 0; // Raw temp reading +uint8_t maxTemperature = 0 ; // Raw temp reading + +void end_bt_tx_interrupt() +{ + Uart *pUart = BT_USART ; + pUart->UART_IDR = UART_IDR_TXBUFE ; + NVIC_DisableIRQ(UART1_IRQn) ; +} + +#if !defined(REVA) +uint16_t getCurrent() +{ + static uint16_t Current ; + static uint32_t Current_sum ; + static uint8_t Current_count ; + + Current_sum += anaIn(8); // TODO enum + if (++Current_count >= 50) { + Current = Current_sum / 5 ; + Current_sum = 0 ; + Current_count = 0 ; + } + + uint32_t current_scale = 488 + g_eeGeneral.txCurrentCalibration ; + return (current_scale * Current) / 8192; +} +#endif + +uint8_t getTemperature() +{ + return temperature + g_eeGeneral.temperatureCalib; +} + +#define STICK_LV_GAIN 0x01 +#define STICK_LH_GAIN 0x02 +#define STICK_RV_GAIN 0x04 +#define STICK_RH_GAIN 0x08 + +#define GAIN_LV 0x00080000 +#define GAIN_LH 0x00000020 +#define GAIN_RV 0x20000000 +#define GAIN_RH 0x00000008 + +#define OFF_LV 0x00000200 +#define OFF_LH 0x00000004 +#define OFF_RV 0x00004000 +#define OFF_RH 0x00000002 + +void setSticksGain(uint8_t gains) +{ + Adc *padc ; + uint32_t gain ; + uint32_t offset ; + + gain = 0 ; + offset = 0 ; + padc = ADC ; + + if ( gains & STICK_LV_GAIN ) { + gain |= GAIN_LV ; + offset |= OFF_LV ; + } + if ( gains & STICK_LH_GAIN ) { + gain |= GAIN_LH ; + offset |= OFF_LH ; + } + if ( gains & STICK_RV_GAIN ) { + gain |= GAIN_RV ; + offset |= OFF_RV ; + } + if ( gains & STICK_RH_GAIN ) { + gain |= GAIN_RH ; + offset |= OFF_RH ; + } + + padc->ADC_CGR = gain; + padc->ADC_COR = offset; +} + + +#if !defined(REVA) +void calcConsumption() +{ + Current_accumulator += Current_analogue ; + static uint32_t OneSecTimer; + if (++OneSecTimer >= 100) { + OneSecTimer -= 100 ; + Current_used += Current_accumulator / 100 ; // milliAmpSeconds (but scaled) + Current_accumulator = 0 ; + } +} +#endif + +void checkTrainerSettings() +{ + if (SLAVE_MODE()) { + PIOC->PIO_PDR = PIO_PC22; + } + else { + PIOC->PIO_PER = PIO_PC22; + } +} + +uint16_t getBatteryVoltage() +{ + int32_t instant_vbat = anaIn(TX_VOLTAGE); // using filtered ADC value on purpose + instant_vbat = (instant_vbat + instant_vbat*(g_eeGeneral.txVoltageCalibration)/128) * 4191; + instant_vbat /= 5530; + return (uint16_t)instant_vbat; +} diff --git a/radio/src/targets/sky9x/board.h b/radio/src/targets/sky9x/board.h index 7b79bc491..44b49deb0 100644 --- a/radio/src/targets/sky9x/board.h +++ b/radio/src/targets/sky9x/board.h @@ -1,414 +1,414 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BOARD_SKY9X_H_ -#define _BOARD_SKY9X_H_ - -#include -#include "board_lowlevel.h" -#include "audio_driver.h" - -extern uint16_t ResetReason; - -#define BOOTLOADER_SIZE 0x8000 -#define FIRMWARE_SIZE (256*1024) -#define FIRMWARE_ADDRESS 0x00400000 - -// Board driver -void boardInit(void); -#define boardOff() pwrOff() - -// Rotary Encoder driver -void rotencInit(); -void rotencEnd(); - -#if !defined(REVX) && !defined(AR9X) - #define ROTARY_ENCODERS 1 - #define ROTARY_ENCODER_NAVIGATION - #define REA_DOWN() (!(PIOB->PIO_PDSR & 0x40)) -#else - #define REA_DOWN() (0) -#endif - -// Keys driver -#define NUM_SWITCHES 7 -enum EnumKeys -{ - KEY_MENU, - KEY_ENTER=KEY_MENU, - KEY_EXIT, - KEY_DOWN, - KEY_MINUS = KEY_DOWN, - KEY_UP, - KEY_PLUS = KEY_UP, - KEY_RIGHT, - KEY_LEFT, - - TRM_BASE, - TRM_LH_DWN = TRM_BASE, - TRM_LH_UP, - TRM_LV_DWN, - TRM_LV_UP, - TRM_RV_DWN, - TRM_RV_UP, - TRM_RH_DWN, - TRM_RH_UP, - TRM_LAST = TRM_RH_UP, - -#if defined(ROTARY_ENCODERS) - BTN_REa, -#endif - - NUM_KEYS -}; - -enum EnumSwitches -{ - SW_ID0, - SW_ID1, - SW_ID2, - SW_THR, - SW_RUD, - SW_ELE, - SW_AIL, - SW_GEA, - SW_TRN, -}; -#define IS_3POS(sw) ((sw) == 0) -#define IS_TOGGLE(sw) ((sw) == SWSRC_TRN) - -#if defined(REVA) - #define KEYS_GPIO_REG_MENU PIOB->PIO_PDSR - #define KEYS_GPIO_REG_EXIT PIOA->PIO_PDSR - #define KEYS_GPIO_REG_UP PIOC->PIO_PDSR - #define KEYS_GPIO_REG_DOWN PIOC->PIO_PDSR - #define KEYS_GPIO_REG_RIGHT PIOC->PIO_PDSR - #define KEYS_GPIO_REG_LEFT PIOC->PIO_PDSR - #define KEYS_GPIO_PIN_MENU 0x00000040 - #define KEYS_GPIO_PIN_EXIT 0x80000000 - #define KEYS_GPIO_PIN_UP 0x00000004 - #define KEYS_GPIO_PIN_DOWN 0x00000008 - #define KEYS_GPIO_PIN_RIGHT 0x00000010 - #define KEYS_GPIO_PIN_LEFT 0x00000020 -#else - #define KEYS_GPIO_REG_MENU PIOB->PIO_PDSR - #define KEYS_GPIO_REG_EXIT PIOC->PIO_PDSR - #define KEYS_GPIO_REG_UP PIOC->PIO_PDSR - #define KEYS_GPIO_REG_DOWN PIOC->PIO_PDSR - #define KEYS_GPIO_REG_RIGHT PIOC->PIO_PDSR - #define KEYS_GPIO_REG_LEFT PIOC->PIO_PDSR - #define KEYS_GPIO_PIN_MENU 0x00000020 - #define KEYS_GPIO_PIN_EXIT 0x01000000 - #define KEYS_GPIO_PIN_UP 0x00000002 - #define KEYS_GPIO_PIN_DOWN 0x00000020 - #define KEYS_GPIO_PIN_RIGHT 0x00000010 - #define KEYS_GPIO_PIN_LEFT 0x00000008 -#endif - -#if defined(REVX) - #define TRIMS_GPIO_REG_LHL PIOB->PIO_PDSR - #define TRIMS_GPIO_REG_LVD PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_RVU PIOC->PIO_PDSR - #define TRIMS_GPIO_REG_RHL PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_LHR PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_LVU PIOC->PIO_PDSR - #define TRIMS_GPIO_REG_RVD PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_RHR PIOC->PIO_PDSR -#else - #define TRIMS_GPIO_REG_LHL PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_LVD PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_RVU PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_RHL PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_LHR PIOB->PIO_PDSR - #define TRIMS_GPIO_REG_LVU PIOC->PIO_PDSR - #define TRIMS_GPIO_REG_RVD PIOC->PIO_PDSR - #define TRIMS_GPIO_REG_RHR PIOC->PIO_PDSR -#endif - -#if defined(REVX) - #define TRIMS_GPIO_PIN_LHL 0x00000010 - #define TRIMS_GPIO_PIN_LVD 0x01000000 - #define TRIMS_GPIO_PIN_RVU 0x00000400 - #define TRIMS_GPIO_PIN_RHL 0x00000001 - #define TRIMS_GPIO_PIN_LHR 0x00800000 - #define TRIMS_GPIO_PIN_LVU 0x10000000 - #define TRIMS_GPIO_PIN_RVD 0x00000002 - #define TRIMS_GPIO_PIN_RHR 0x00000200 -#elif defined(REVA) - #define TRIMS_GPIO_PIN_LHL 0x00000080 - #define TRIMS_GPIO_PIN_LVD 0x08000000 - #define TRIMS_GPIO_PIN_RVU 0x40000000 - #define TRIMS_GPIO_PIN_RHL 0x20000000 - #define TRIMS_GPIO_PIN_LHR 0x00000010 - #define TRIMS_GPIO_PIN_LVU 0x10000000 - #define TRIMS_GPIO_PIN_RVD 0x00000400 - #define TRIMS_GPIO_PIN_RHR 0x00000200 -#else - #define TRIMS_GPIO_PIN_LHL 0x00800000 - #define TRIMS_GPIO_PIN_LVD 0x01000000 - #define TRIMS_GPIO_PIN_RVU 0x00000002 - #define TRIMS_GPIO_PIN_RHL 0x00000001 - #define TRIMS_GPIO_PIN_LHR 0x00000010 - #define TRIMS_GPIO_PIN_LVU 0x10000000 - #define TRIMS_GPIO_PIN_RVD 0x00000400 - #define TRIMS_GPIO_PIN_RHR 0x00000200 -#endif - -// LCD driver -#define LCD_W 128 -#define LCD_H 64 -#define LCD_DEPTH 1 -#define LCD_CONTRAST_MIN 10 -#define LCD_CONTRAST_MAX 45 -#define LCD_CONTRAST_DEFAULT 25 -void lcdInit(void); -void lcdRefresh(void); -#define lcdRefreshWait() -void lcdSetRefVolt(uint8_t val); -void lcdSetContrast(void); - -// USB driver -void usbMassStorage(); - -#define PIN_ENABLE 0x001 -#define PIN_PERIPHERAL 0x000 -#define PIN_INPUT 0x002 -#define PIN_OUTPUT 0x000 -#define PIN_PULLUP 0x004 -#define PIN_NO_PULLUP 0x000 -#define PIN_PULLDOWN 0x008 -#define PIN_NO_PULLDOWN 0x000 -#define PIN_PERI_MASK_L 0x010 -#define PIN_PERI_MASK_H 0x020 -#define PIN_PER_A 0x000 -#define PIN_PER_B 0x010 -#define PIN_PER_C 0x020 -#define PIN_PER_D 0x030 -#define PIN_PORT_MASK 0x0C0 -#define PIN_PORTA 0x000 -#define PIN_PORTB 0x040 -#define PIN_PORTC 0x080 -#define PIN_LOW 0x000 -#define PIN_HIGH 0x100 - -// Telemetry port -#define SECOND_USART USART0 -#define SECOND_ID ID_USART0 -#define SECOND_PINS { PINS_USART0 } - -void configure_pins( uint32_t pins, uint16_t config ); -uint16_t getCurrent(); - -extern uint8_t temperature ; // Raw temp reading -extern uint8_t maxTemperature ; // Raw temp reading -uint8_t getTemperature(); - -#define strcpy_P strcpy -#define strcat_P strcat - -#if !defined(REVA) -extern uint16_t Current_analogue; -extern uint16_t Current_max; -extern uint32_t Current_accumulator; -extern uint32_t Current_used; -extern uint16_t sessionTimer; -void calcConsumption(); -#endif - -// Trainer driver -#define SLAVE_MODE() (pwrCheck() == e_power_trainer) -#define TRAINER_CONNECTED() (PIOA->PIO_PDSR & PIO_PA8) -void checkTrainerSettings(); -void init_trainer_capture(); - -// Write Flash driver -#define FLASH_PAGESIZE 256 -void flashWrite(uint32_t * address, uint32_t * buffer); - -// Keys driver -uint8_t keyState(uint8_t index); -uint32_t switchState(uint8_t index); -uint32_t readKeys(void); -uint32_t readTrims(void); -#define TRIMS_PRESSED() readTrims() -#define KEYS_PRESSED() readKeys() - -// Pulses driver -void init_no_pulses(uint32_t port); -void disable_no_pulses(uint32_t port); -void init_ppm(uint32_t port); -void disable_ppm(uint32_t port); -void init_pxx(uint32_t port); -void disable_pxx(uint32_t port); -void init_dsm2(uint32_t port); -void disable_dsm2(uint32_t port); - -#if defined(MULTIMODULE) -void init_multimodule(uint32_t module_index); -void disable_multimodule(uint32_t module_index); -#endif - -// SD driver -#if defined(SIMU) -#define sdInit() -#define sdDone() -#else -#define sdPoll10ms() -#if defined(__cplusplus) -extern "C" { -#endif - void init_SDcard(); - void sdInit(); - void sdDone(); - uint32_t sd_card_ready(); - uint32_t sdMounted(); -#if defined(__cplusplus) -} -#endif -#endif - -// WDT driver -#if defined(WATCHDOG_DISABLED) || defined(SIMU) - #define wdt_disable() - #define wdt_enable(x) - #define wdt_reset() -#else - #define wdt_disable() - #define wdt_enable(x) WDT->WDT_MR = 0x3FFF207F - #define wdt_reset() WDT->WDT_CR = 0xA5000001 -#endif - -// Backlight driver -#define backlightEnable() (PWM->PWM_CH_NUM[0].PWM_CDTY = g_eeGeneral.backlightBright) -#define backlightDisable() (PWM->PWM_CH_NUM[0].PWM_CDTY = 100) -#define isBacklightEnabled() (PWM->PWM_CH_NUM[0].PWM_CDTY != 100) -#define BACKLIGHT_ENABLE() backlightEnable() -#define BACKLIGHT_DISABLE() backlightDisable() - -// ADC driver -#define NUM_POTS 3 -#define NUM_SLIDERS 0 -#define NUM_XPOTS 0 -enum Analogs { - STICK1, - STICK2, - STICK3, - STICK4, - POT_FIRST, - POT1 = POT_FIRST, - POT2, - POT3, - POT_LAST = POT3, - TX_VOLTAGE, -#if !defined(REVA) - TX_CURRENT, -#endif - NUM_ANALOGS -}; -enum CalibratedAnalogs { - CALIBRATED_STICK1, - CALIBRATED_STICK2, - CALIBRATED_STICK3, - CALIBRATED_STICK4, - CALIBRATED_POT_FIRST, - CALIBRATED_POT1 = CALIBRATED_POT_FIRST, - CALIBRATED_POT2, - CALIBRATED_POT3, - CALIBRATED_POT_LAST = CALIBRATED_POT3, - NUM_CALIBRATED_ANALOGS -}; -#define IS_POT(x) ((x)>=POT_FIRST && (x)<=POT_LAST) -#define IS_SLIDER(x) false -void adcInit(); -void adcRead(void); -uint16_t getAnalogValue(uint8_t index); -uint16_t getBatteryVoltage(); // returns current battery voltage in 10mV steps -void setSticksGain(uint8_t gains); - -// Buzzer driver -void buzzerSound(uint8_t duration); -void buzzerHeartbeat(); -#define BUZZER_HEARTBEAT buzzerHeartbeat - -// i2c driver -void i2cCheck(); - -// Coproc driver -void coprocInit(); -void coprocWriteData(uint8_t *data, uint32_t size); -#if defined(__cplusplus) -void coprocReadData(bool onlytemp=false); -#endif -extern int8_t volumeRequired; -extern uint8_t Coproc_read; -extern int8_t Coproc_valid; -extern int8_t Coproc_temp; -extern int8_t Coproc_maxtemp; - -// Haptic driver -void hapticOff(void); -void hapticOn(uint32_t pwmPercent); - -// BlueTooth driver -#if defined(BLUETOOTH) -void btInit(); -void btTask(void* pdata); -void btPushByte(uint8_t data); -#endif - -// Power driver -#define TRAINER_PWR -#if !defined(REVA) -#define SOFT_PWR_CTRL -#endif -void pwrInit(); -void pwrOff(); -uint32_t pwrCheck(); -uint32_t pwrPressed(); -#define UNEXPECTED_SHUTDOWN() (g_eeGeneral.unexpectedShutdown) - -// EEPROM driver -#define EEPROM_SIZE (4*1024*1024/8) -#define EEPROM_BLOCK_SIZE (4*1024) -void eepromInit(); -uint8_t eepromReadStatus(); -uint8_t eepromIsTransferComplete(void); -void eepromBlockErase(uint32_t address); -void eepromStartRead(uint8_t * buffer, size_t address, size_t size); -void eepromStartWrite(uint8_t * buffer, size_t address, size_t size); - -// Debug driver -void debugPutc(const char c); - -// Telemetry driver -void telemetryPortInit(uint32_t baudrate, uint8_t mode); -uint32_t telemetryTransmitPending(); -void telemetryTransmitBuffer(uint8_t * buffer, uint32_t size); -void rxPdcUsart( void (*pChProcess)(uint8_t x) ); - -// Second UART driver -void serial2TelemetryInit(unsigned int protocol); -#if defined(__cplusplus) -bool telemetrySecondPortReceive(uint8_t & data); -#endif - -extern const uint8_t BootCode[]; - -#endif // _BOARD_SKY9X_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BOARD_SKY9X_H_ +#define _BOARD_SKY9X_H_ + +#include +#include "board_lowlevel.h" +#include "audio_driver.h" + +extern uint16_t ResetReason; + +#define BOOTLOADER_SIZE 0x8000 +#define FIRMWARE_SIZE (256*1024) +#define FIRMWARE_ADDRESS 0x00400000 + +// Board driver +void boardInit(void); +#define boardOff() pwrOff() + +// Rotary Encoder driver +void rotencInit(); +void rotencEnd(); + +#if !defined(REVX) && !defined(AR9X) + #define ROTARY_ENCODERS 1 + #define ROTARY_ENCODER_NAVIGATION + #define REA_DOWN() (!(PIOB->PIO_PDSR & 0x40)) +#else + #define REA_DOWN() (0) +#endif + +// Keys driver +#define NUM_SWITCHES 7 +enum EnumKeys +{ + KEY_MENU, + KEY_ENTER=KEY_MENU, + KEY_EXIT, + KEY_DOWN, + KEY_MINUS = KEY_DOWN, + KEY_UP, + KEY_PLUS = KEY_UP, + KEY_RIGHT, + KEY_LEFT, + + TRM_BASE, + TRM_LH_DWN = TRM_BASE, + TRM_LH_UP, + TRM_LV_DWN, + TRM_LV_UP, + TRM_RV_DWN, + TRM_RV_UP, + TRM_RH_DWN, + TRM_RH_UP, + TRM_LAST = TRM_RH_UP, + +#if defined(ROTARY_ENCODERS) + BTN_REa, +#endif + + NUM_KEYS +}; + +enum EnumSwitches +{ + SW_ID0, + SW_ID1, + SW_ID2, + SW_THR, + SW_RUD, + SW_ELE, + SW_AIL, + SW_GEA, + SW_TRN, +}; +#define IS_3POS(sw) ((sw) == 0) +#define IS_TOGGLE(sw) ((sw) == SWSRC_TRN) + +#if defined(REVA) + #define KEYS_GPIO_REG_MENU PIOB->PIO_PDSR + #define KEYS_GPIO_REG_EXIT PIOA->PIO_PDSR + #define KEYS_GPIO_REG_UP PIOC->PIO_PDSR + #define KEYS_GPIO_REG_DOWN PIOC->PIO_PDSR + #define KEYS_GPIO_REG_RIGHT PIOC->PIO_PDSR + #define KEYS_GPIO_REG_LEFT PIOC->PIO_PDSR + #define KEYS_GPIO_PIN_MENU 0x00000040 + #define KEYS_GPIO_PIN_EXIT 0x80000000 + #define KEYS_GPIO_PIN_UP 0x00000004 + #define KEYS_GPIO_PIN_DOWN 0x00000008 + #define KEYS_GPIO_PIN_RIGHT 0x00000010 + #define KEYS_GPIO_PIN_LEFT 0x00000020 +#else + #define KEYS_GPIO_REG_MENU PIOB->PIO_PDSR + #define KEYS_GPIO_REG_EXIT PIOC->PIO_PDSR + #define KEYS_GPIO_REG_UP PIOC->PIO_PDSR + #define KEYS_GPIO_REG_DOWN PIOC->PIO_PDSR + #define KEYS_GPIO_REG_RIGHT PIOC->PIO_PDSR + #define KEYS_GPIO_REG_LEFT PIOC->PIO_PDSR + #define KEYS_GPIO_PIN_MENU 0x00000020 + #define KEYS_GPIO_PIN_EXIT 0x01000000 + #define KEYS_GPIO_PIN_UP 0x00000002 + #define KEYS_GPIO_PIN_DOWN 0x00000020 + #define KEYS_GPIO_PIN_RIGHT 0x00000010 + #define KEYS_GPIO_PIN_LEFT 0x00000008 +#endif + +#if defined(REVX) + #define TRIMS_GPIO_REG_LHL PIOB->PIO_PDSR + #define TRIMS_GPIO_REG_LVD PIOA->PIO_PDSR + #define TRIMS_GPIO_REG_RVU PIOC->PIO_PDSR + #define TRIMS_GPIO_REG_RHL PIOA->PIO_PDSR + #define TRIMS_GPIO_REG_LHR PIOA->PIO_PDSR + #define TRIMS_GPIO_REG_LVU PIOC->PIO_PDSR + #define TRIMS_GPIO_REG_RVD PIOA->PIO_PDSR + #define TRIMS_GPIO_REG_RHR PIOC->PIO_PDSR +#else + #define TRIMS_GPIO_REG_LHL PIOA->PIO_PDSR + #define TRIMS_GPIO_REG_LVD PIOA->PIO_PDSR + #define TRIMS_GPIO_REG_RVU PIOA->PIO_PDSR + #define TRIMS_GPIO_REG_RHL PIOA->PIO_PDSR + #define TRIMS_GPIO_REG_LHR PIOB->PIO_PDSR + #define TRIMS_GPIO_REG_LVU PIOC->PIO_PDSR + #define TRIMS_GPIO_REG_RVD PIOC->PIO_PDSR + #define TRIMS_GPIO_REG_RHR PIOC->PIO_PDSR +#endif + +#if defined(REVX) + #define TRIMS_GPIO_PIN_LHL 0x00000010 + #define TRIMS_GPIO_PIN_LVD 0x01000000 + #define TRIMS_GPIO_PIN_RVU 0x00000400 + #define TRIMS_GPIO_PIN_RHL 0x00000001 + #define TRIMS_GPIO_PIN_LHR 0x00800000 + #define TRIMS_GPIO_PIN_LVU 0x10000000 + #define TRIMS_GPIO_PIN_RVD 0x00000002 + #define TRIMS_GPIO_PIN_RHR 0x00000200 +#elif defined(REVA) + #define TRIMS_GPIO_PIN_LHL 0x00000080 + #define TRIMS_GPIO_PIN_LVD 0x08000000 + #define TRIMS_GPIO_PIN_RVU 0x40000000 + #define TRIMS_GPIO_PIN_RHL 0x20000000 + #define TRIMS_GPIO_PIN_LHR 0x00000010 + #define TRIMS_GPIO_PIN_LVU 0x10000000 + #define TRIMS_GPIO_PIN_RVD 0x00000400 + #define TRIMS_GPIO_PIN_RHR 0x00000200 +#else + #define TRIMS_GPIO_PIN_LHL 0x00800000 + #define TRIMS_GPIO_PIN_LVD 0x01000000 + #define TRIMS_GPIO_PIN_RVU 0x00000002 + #define TRIMS_GPIO_PIN_RHL 0x00000001 + #define TRIMS_GPIO_PIN_LHR 0x00000010 + #define TRIMS_GPIO_PIN_LVU 0x10000000 + #define TRIMS_GPIO_PIN_RVD 0x00000400 + #define TRIMS_GPIO_PIN_RHR 0x00000200 +#endif + +// LCD driver +#define LCD_W 128 +#define LCD_H 64 +#define LCD_DEPTH 1 +#define LCD_CONTRAST_MIN 10 +#define LCD_CONTRAST_MAX 45 +#define LCD_CONTRAST_DEFAULT 25 +void lcdInit(void); +void lcdRefresh(void); +#define lcdRefreshWait() +void lcdSetRefVolt(uint8_t val); +void lcdSetContrast(void); + +// USB driver +void usbMassStorage(); + +#define PIN_ENABLE 0x001 +#define PIN_PERIPHERAL 0x000 +#define PIN_INPUT 0x002 +#define PIN_OUTPUT 0x000 +#define PIN_PULLUP 0x004 +#define PIN_NO_PULLUP 0x000 +#define PIN_PULLDOWN 0x008 +#define PIN_NO_PULLDOWN 0x000 +#define PIN_PERI_MASK_L 0x010 +#define PIN_PERI_MASK_H 0x020 +#define PIN_PER_A 0x000 +#define PIN_PER_B 0x010 +#define PIN_PER_C 0x020 +#define PIN_PER_D 0x030 +#define PIN_PORT_MASK 0x0C0 +#define PIN_PORTA 0x000 +#define PIN_PORTB 0x040 +#define PIN_PORTC 0x080 +#define PIN_LOW 0x000 +#define PIN_HIGH 0x100 + +// Telemetry port +#define SECOND_USART USART0 +#define SECOND_ID ID_USART0 +#define SECOND_PINS { PINS_USART0 } + +void configure_pins( uint32_t pins, uint16_t config ); +uint16_t getCurrent(); + +extern uint8_t temperature ; // Raw temp reading +extern uint8_t maxTemperature ; // Raw temp reading +uint8_t getTemperature(); + +#define strcpy_P strcpy +#define strcat_P strcat + +#if !defined(REVA) +extern uint16_t Current_analogue; +extern uint16_t Current_max; +extern uint32_t Current_accumulator; +extern uint32_t Current_used; +extern uint16_t sessionTimer; +void calcConsumption(); +#endif + +// Trainer driver +#define SLAVE_MODE() (pwrCheck() == e_power_trainer) +#define TRAINER_CONNECTED() (PIOA->PIO_PDSR & PIO_PA8) +void checkTrainerSettings(); +void init_trainer_capture(); + +// Write Flash driver +#define FLASH_PAGESIZE 256 +void flashWrite(uint32_t * address, uint32_t * buffer); + +// Keys driver +uint8_t keyState(uint8_t index); +uint32_t switchState(uint8_t index); +uint32_t readKeys(void); +uint32_t readTrims(void); +#define TRIMS_PRESSED() readTrims() +#define KEYS_PRESSED() readKeys() + +// Pulses driver +void init_no_pulses(uint32_t port); +void disable_no_pulses(uint32_t port); +void init_ppm(uint32_t port); +void disable_ppm(uint32_t port); +void init_pxx(uint32_t port); +void disable_pxx(uint32_t port); +void init_dsm2(uint32_t port); +void disable_dsm2(uint32_t port); + +#if defined(MULTIMODULE) +void init_multimodule(uint32_t module_index); +void disable_multimodule(uint32_t module_index); +#endif + +// SD driver +#if defined(SIMU) +#define sdInit() +#define sdDone() +#else +#define sdPoll10ms() +#if defined(__cplusplus) +extern "C" { +#endif + void init_SDcard(); + void sdInit(); + void sdDone(); + uint32_t sd_card_ready(); + uint32_t sdMounted(); +#if defined(__cplusplus) +} +#endif +#endif + +// WDT driver +#if defined(WATCHDOG_DISABLED) || defined(SIMU) + #define wdt_disable() + #define wdt_enable(x) + #define wdt_reset() +#else + #define wdt_disable() + #define wdt_enable(x) WDT->WDT_MR = 0x3FFF207F + #define wdt_reset() WDT->WDT_CR = 0xA5000001 +#endif + +// Backlight driver +#define backlightEnable() (PWM->PWM_CH_NUM[0].PWM_CDTY = g_eeGeneral.backlightBright) +#define backlightDisable() (PWM->PWM_CH_NUM[0].PWM_CDTY = 100) +#define isBacklightEnabled() (PWM->PWM_CH_NUM[0].PWM_CDTY != 100) +#define BACKLIGHT_ENABLE() backlightEnable() +#define BACKLIGHT_DISABLE() backlightDisable() + +// ADC driver +#define NUM_POTS 3 +#define NUM_SLIDERS 0 +#define NUM_XPOTS 0 +enum Analogs { + STICK1, + STICK2, + STICK3, + STICK4, + POT_FIRST, + POT1 = POT_FIRST, + POT2, + POT3, + POT_LAST = POT3, + TX_VOLTAGE, +#if !defined(REVA) + TX_CURRENT, +#endif + NUM_ANALOGS +}; +enum CalibratedAnalogs { + CALIBRATED_STICK1, + CALIBRATED_STICK2, + CALIBRATED_STICK3, + CALIBRATED_STICK4, + CALIBRATED_POT_FIRST, + CALIBRATED_POT1 = CALIBRATED_POT_FIRST, + CALIBRATED_POT2, + CALIBRATED_POT3, + CALIBRATED_POT_LAST = CALIBRATED_POT3, + NUM_CALIBRATED_ANALOGS +}; +#define IS_POT(x) ((x)>=POT_FIRST && (x)<=POT_LAST) +#define IS_SLIDER(x) false +void adcInit(); +void adcRead(void); +uint16_t getAnalogValue(uint8_t index); +uint16_t getBatteryVoltage(); // returns current battery voltage in 10mV steps +void setSticksGain(uint8_t gains); + +// Buzzer driver +void buzzerSound(uint8_t duration); +void buzzerHeartbeat(); +#define BUZZER_HEARTBEAT buzzerHeartbeat + +// i2c driver +void i2cCheck(); + +// Coproc driver +void coprocInit(); +void coprocWriteData(uint8_t *data, uint32_t size); +#if defined(__cplusplus) +void coprocReadData(bool onlytemp=false); +#endif +extern int8_t volumeRequired; +extern uint8_t Coproc_read; +extern int8_t Coproc_valid; +extern int8_t Coproc_temp; +extern int8_t Coproc_maxtemp; + +// Haptic driver +void hapticOff(void); +void hapticOn(uint32_t pwmPercent); + +// BlueTooth driver +#if defined(BLUETOOTH) +void btInit(); +void btTask(void* pdata); +void btPushByte(uint8_t data); +#endif + +// Power driver +#define TRAINER_PWR +#if !defined(REVA) +#define SOFT_PWR_CTRL +#endif +void pwrInit(); +void pwrOff(); +uint32_t pwrCheck(); +uint32_t pwrPressed(); +#define UNEXPECTED_SHUTDOWN() (g_eeGeneral.unexpectedShutdown) + +// EEPROM driver +#define EEPROM_SIZE (4*1024*1024/8) +#define EEPROM_BLOCK_SIZE (4*1024) +void eepromInit(); +uint8_t eepromReadStatus(); +uint8_t eepromIsTransferComplete(void); +void eepromBlockErase(uint32_t address); +void eepromStartRead(uint8_t * buffer, size_t address, size_t size); +void eepromStartWrite(uint8_t * buffer, size_t address, size_t size); + +// Debug driver +void debugPutc(const char c); + +// Telemetry driver +void telemetryPortInit(uint32_t baudrate, uint8_t mode); +uint32_t telemetryTransmitPending(); +void telemetryTransmitBuffer(uint8_t * buffer, uint32_t size); +void rxPdcUsart( void (*pChProcess)(uint8_t x) ); + +// Second UART driver +void serial2TelemetryInit(unsigned int protocol); +#if defined(__cplusplus) +bool telemetrySecondPortReceive(uint8_t & data); +#endif + +extern const uint8_t BootCode[]; + +#endif // _BOARD_SKY9X_H_ diff --git a/radio/src/targets/sky9x/board_lowlevel.c b/radio/src/targets/sky9x/board_lowlevel.c index 3d01a54ff..15d47661a 100644 --- a/radio/src/targets/sky9x/board_lowlevel.c +++ b/radio/src/targets/sky9x/board_lowlevel.c @@ -1,253 +1,253 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * \file - * - * \par Purpose - * - * Provides the low-level initialization function that gets called on chip startup. - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "board_lowlevel.h" - -/*---------------------------------------------------------------------------- - * Local definitions - *----------------------------------------------------------------------------*/ -/** Define clock timeout */ -#define CLOCK_TIMEOUT 5000 -/** Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.*/ -#define PMC_PLLA_SET_BIT29 (0x1 << 29) -/** Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.*/ -#define PMC_PLLA_COUNT (0xBF << 8) -/** The PLLA Clock frequency is the PLLA input frequency multiplied by 8*/ -#define PMC_PLLA_MULTIPIER (0x07 << 16) -/** PLLA Divider is bypassed.*/ -#define PMC_PLLA_DIV (0x01) - -void revert_osc( void ) ; - - -/*---------------------------------------------------------------------------- - * Local functions - * returns master_frequency - *----------------------------------------------------------------------------*/ - -// *** WARNING, this is called BEFORE .data and .bss have been initialised -// *** GLOBAL variables are NOT useable - -static uint32_t BOARD_ConfigurePmc(void) -{ -/* TODO: configurate PLL in new way */ -//#if 0 -// uint32_t timeout = 0; -// /** 1: Checking the Main Oscillator Frequency (Optional) and Initialize main oscillator */ -// /** 1.1 Initialize main oscillator */ -// // TODO: - -// /** 2. Setting PLL and Divider*/ -// /** 2.1 Initialize PLLA*/ -// PMC->CKGR_PLLAR = ( PMC_PLLA_SET_BIT29 | -// PMC_PLLA_MULTIPIER | -// PMC_PLLA_COUNT | -// PMC_PLLA_DIV -// ); -// timeout = 0; -// /** 2.2 Wait for the LOCKA bit to be set by polling the status register.*/ -// while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT)); -// /** 2.3 wait for the MCKRDY bit to be set by polling the status register*/ -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - -// /** 3. Selection of Master Clock and Processor Clock*/ -// PMC->PMC_MCKR |= PMC_MCKR_PRES_CLK_2; - -// /** 3.1 wait for the MCKRDY bit to be set by polling the status register*/ -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - -// /** 3.2 PLLA Clock is selected */ -// PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK; - -// /** 3.3 wait for the MCKRDY bit to be set by polling the status register*/ -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); -//#endif - -#if 1 // old as sam3u -#define AT91C_CKGR_MUL_SHIFT 16 -//#define AT91C_CKGR_OUT_SHIFT 14 -#define AT91C_CKGR_PLLCOUNT_SHIFT 8 -#define AT91C_CKGR_DIV_SHIFT 0 - -// Settings at 72MHz/2 = 36MHz -#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST & (0x8 << 8)) -#define BOARD_PLLR ((1 << 29) | (0x5 << AT91C_CKGR_MUL_SHIFT) \ - | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x2 << AT91C_CKGR_DIV_SHIFT)) -#define BOARD_MCKR (PMC_MCKR_CSS_PLLA_CLK) - -// Define clock timeout -#undef CLOCK_TIMEOUT -#define CLOCK_TIMEOUT 0xFFFFFFFF - - uint32_t timeout = 0 ; - Pmc *pmcptr ; - - pmcptr = PMC ; - - /* Enable NRST reset - ************************************/ - //AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN; - - /* Select external slow clock - ****************************/ - - -// if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST) { -// SUPC->SUPC_CR = SUPC_CR_XTALSEL_CRYSTAL_SEL | ((uint32_t)0xA5 << 24); -// timeout = 0; -// while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) ); -// } - - - /* Initialize main oscillator - ****************************/ - if(!(pmcptr->CKGR_MOR & CKGR_MOR_MOSCSEL)) - { - - pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MOSCXTS) && (++timeout < CLOCK_TIMEOUT)); - - } - - /* Switch to 3-20MHz Xtal oscillator */ - pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); - - pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); - - /* Initialize PLLA 72 MHz */ - pmcptr->CKGR_PLLAR = BOARD_PLLR; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_LOCKA) && (++timeout < CLOCK_TIMEOUT)); - - - /* Initialize UTMI for USB usage, can be disabled if not using USB for the sake of saving power*/ - //AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; - //timeout = 0; - //while (!(PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT)); - - /* Switch to fast clock - **********************/ -// PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - - // Switch to PLLA as main clock 36MHz - PMC->PMC_MCKR = BOARD_MCKR; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - -#endif - return 36000000L; // Master_frequency -} - -void revert_osc() -{ - uint32_t timeout = 0; - Pmc *pmcptr; - - pmcptr = PMC; - - // Switch back to the internal oscillator - pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); - - pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_SLOW_CLK; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); - - pmcptr->CKGR_PLLAR = 1 << 29; // Stop PLLA -} - -#if defined(BOOT) -// extern void sam_bootx( void ) ; -// extern void dispUSB( void ) ; -// extern uint32_t init -// ReadTrims( void ) ; -// extern void run_application( void ) ; - -static void lowLevelUsbCheck( void ) -{ - PMC->PMC_PCER0 = (1<PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) - - uint32_t i ; - for ( i = 0 ; i < 50 ; i += 1 ) { - __asm("nop") ; - } - - for ( i = 0 ; i < 10 ; i += 1 ) { - if ( PIOC->PIO_PDSR & 0x02000000 ) { - PMC->PMC_PCDR0 = (1<EEFC_FMR = (1 << 8) ; - - // Configure PMC - return BOARD_ConfigurePmc(); -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * \file + * + * \par Purpose + * + * Provides the low-level initialization function that gets called on chip startup. + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board_lowlevel.h" + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ +/** Define clock timeout */ +#define CLOCK_TIMEOUT 5000 +/** Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.*/ +#define PMC_PLLA_SET_BIT29 (0x1 << 29) +/** Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.*/ +#define PMC_PLLA_COUNT (0xBF << 8) +/** The PLLA Clock frequency is the PLLA input frequency multiplied by 8*/ +#define PMC_PLLA_MULTIPIER (0x07 << 16) +/** PLLA Divider is bypassed.*/ +#define PMC_PLLA_DIV (0x01) + +void revert_osc( void ) ; + + +/*---------------------------------------------------------------------------- + * Local functions + * returns master_frequency + *----------------------------------------------------------------------------*/ + +// *** WARNING, this is called BEFORE .data and .bss have been initialised +// *** GLOBAL variables are NOT useable + +static uint32_t BOARD_ConfigurePmc(void) +{ +/* TODO: configurate PLL in new way */ +//#if 0 +// uint32_t timeout = 0; +// /** 1: Checking the Main Oscillator Frequency (Optional) and Initialize main oscillator */ +// /** 1.1 Initialize main oscillator */ +// // TODO: + +// /** 2. Setting PLL and Divider*/ +// /** 2.1 Initialize PLLA*/ +// PMC->CKGR_PLLAR = ( PMC_PLLA_SET_BIT29 | +// PMC_PLLA_MULTIPIER | +// PMC_PLLA_COUNT | +// PMC_PLLA_DIV +// ); +// timeout = 0; +// /** 2.2 Wait for the LOCKA bit to be set by polling the status register.*/ +// while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT)); +// /** 2.3 wait for the MCKRDY bit to be set by polling the status register*/ +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + +// /** 3. Selection of Master Clock and Processor Clock*/ +// PMC->PMC_MCKR |= PMC_MCKR_PRES_CLK_2; + +// /** 3.1 wait for the MCKRDY bit to be set by polling the status register*/ +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + +// /** 3.2 PLLA Clock is selected */ +// PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK; + +// /** 3.3 wait for the MCKRDY bit to be set by polling the status register*/ +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); +//#endif + +#if 1 // old as sam3u +#define AT91C_CKGR_MUL_SHIFT 16 +//#define AT91C_CKGR_OUT_SHIFT 14 +#define AT91C_CKGR_PLLCOUNT_SHIFT 8 +#define AT91C_CKGR_DIV_SHIFT 0 + +// Settings at 72MHz/2 = 36MHz +#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST & (0x8 << 8)) +#define BOARD_PLLR ((1 << 29) | (0x5 << AT91C_CKGR_MUL_SHIFT) \ + | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x2 << AT91C_CKGR_DIV_SHIFT)) +#define BOARD_MCKR (PMC_MCKR_CSS_PLLA_CLK) + +// Define clock timeout +#undef CLOCK_TIMEOUT +#define CLOCK_TIMEOUT 0xFFFFFFFF + + uint32_t timeout = 0 ; + Pmc *pmcptr ; + + pmcptr = PMC ; + + /* Enable NRST reset + ************************************/ + //AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN; + + /* Select external slow clock + ****************************/ + + +// if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST) { +// SUPC->SUPC_CR = SUPC_CR_XTALSEL_CRYSTAL_SEL | ((uint32_t)0xA5 << 24); +// timeout = 0; +// while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) ); +// } + + + /* Initialize main oscillator + ****************************/ + if(!(pmcptr->CKGR_MOR & CKGR_MOR_MOSCSEL)) + { + + pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MOSCXTS) && (++timeout < CLOCK_TIMEOUT)); + + } + + /* Switch to 3-20MHz Xtal oscillator */ + pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); + + pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); + + /* Initialize PLLA 72 MHz */ + pmcptr->CKGR_PLLAR = BOARD_PLLR; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_LOCKA) && (++timeout < CLOCK_TIMEOUT)); + + + /* Initialize UTMI for USB usage, can be disabled if not using USB for the sake of saving power*/ + //AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; + //timeout = 0; + //while (!(PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT)); + + /* Switch to fast clock + **********************/ +// PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + + // Switch to PLLA as main clock 36MHz + PMC->PMC_MCKR = BOARD_MCKR; + timeout = 0; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + +#endif + return 36000000L; // Master_frequency +} + +void revert_osc() +{ + uint32_t timeout = 0; + Pmc *pmcptr; + + pmcptr = PMC; + + // Switch back to the internal oscillator + pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); + + pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_SLOW_CLK; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); + + pmcptr->CKGR_PLLAR = 1 << 29; // Stop PLLA +} + +#if defined(BOOT) +// extern void sam_bootx( void ) ; +// extern void dispUSB( void ) ; +// extern uint32_t init +// ReadTrims( void ) ; +// extern void run_application( void ) ; + +static void lowLevelUsbCheck( void ) +{ + PMC->PMC_PCER0 = (1<PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) + + uint32_t i ; + for ( i = 0 ; i < 50 ; i += 1 ) { + __asm("nop") ; + } + + for ( i = 0 ; i < 10 ; i += 1 ) { + if ( PIOC->PIO_PDSR & 0x02000000 ) { + PMC->PMC_PCDR0 = (1<EEFC_FMR = (1 << 8) ; + + // Configure PMC + return BOARD_ConfigurePmc(); +} diff --git a/radio/src/targets/sky9x/board_lowlevel.h b/radio/src/targets/sky9x/board_lowlevel.h index 4930fba43..e9e10e088 100644 --- a/radio/src/targets/sky9x/board_lowlevel.h +++ b/radio/src/targets/sky9x/board_lowlevel.h @@ -1,639 +1,639 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// TODO merge this file with board_sky9x.h - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#include - -#include "chip.h" - -#if defined(REVA) -#include "AT91SAM3S2.h" -#else -#include "AT91SAM3S4.h" -#endif - -#if !defined(SIMU) -#include "core_cm3.h" -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par -/// This page lists several definition related to the board description. -/// -/// Definitions -/// - BOARD_NAME - -/// Name of the board. -#define BOARD_NAME "AT91SAM3S-EK" -/// Board definition. -#define at91sam3sek -/// Family definition (already defined). -#define at91sam3s -/// Core definition -#define cortexm3 - -// TODO remove these definitions -//#define BOARD_REV_A -#define BOARD_REV_B - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_opfreq "SAM3S-EK - Operating frequencies" -/// This page lists several definition related to the board operating frequency -/// (when using the initialization done by board_lowlevel.c). -/// -/// !Definitions -/// - BOARD_MAINOSC -/// - BOARD_MCK - -/// Frequency of the board main oscillator. -#define BOARD_MAINOSC 12000000 - -/// Master clock frequency (when using board_lowlevel.c). -// #define BOARD_MCK 64000000 - -//------------------------------------------------------------------------------ -// ADC -//------------------------------------------------------------------------------ - -/// Startup time max, return from Idle mode (in �s) -#define ADC_STARTUP_TIME_MAX 15 -/// Track and hold Acquisition Time min (in ns) -#define ADC_TRACK_HOLD_TIME_MIN 1200 - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// USB attributes configuration descriptor (bus or self powered, remote wakeup) -//#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP -#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_piodef "SAM3S-EK - PIO definitions" -/// This pages lists all the pio definitions contained in board.h. The constants -/// are named using the following convention: PIN_* for a constant which defines -/// a single Pin instance (but may include several PIOs sharing the same -/// controller), and PINS_* for a list of Pin instances. -/// -/// !ADC -/// - PIN_ADC0_AD0 -/// - PIN_ADC0_AD1 -/// - PIN_ADC0_AD2 -/// - PIN_ADC0_AD3 -/// - PIN_ADC0_AD4 -/// - PIN_ADC0_AD5 -/// - PIN_ADC0_AD6 -/// - PIN_ADC0_AD7 -/// - PINS_ADC0 -/// -/// !UART -/// - PINS_UART -/// -/// !EBI -/// - PIN_EBI_DATA_BUS -/// - PIN_EBI_NCS0 -/// - PIN_EBI_NRD -/// - PIN_EBI_NWE -/// - PIN_EBI_ADDR_BUS -/// - PIN_EBI_PSRAM_NBS -/// - PIN_EBI_A1 -/// - PIN_EBI_LCD_RS -/// -/// !LEDs -/// - PIN_LED_0 -/// - PIN_LED_1 -/// - PIN_LED_2 -/// - PINS_LEDS -/// -/// !MCI -/// - PINS_MCI -/// -/// !Push buttons -/// - PIN_PUSHBUTTON_1 -/// - PIN_PUSHBUTTON_2 -/// - PINS_PUSHBUTTONS -/// - PUSHBUTTON_BP1 -/// - PUSHBUTTON_BP2 -/// -/// !PWMC -/// - PIN_PWMC_PWMH0 -/// - PIN_PWMC_PWML0 -/// - PIN_PWMC_PWMH1 -/// - PIN_PWMC_PWML1 -/// - PIN_PWMC_PWMH2 -/// - PIN_PWMC_PWML2 -/// - PIN_PWMC_PWMH3 -/// - PIN_PWMC_PWML3 -/// - PIN_PWM_LED0 -/// - PIN_PWM_LED1 -/// - PIN_PWM_LED2 -/// - CHANNEL_PWM_LED0 -/// - CHANNEL_PWM_LED1 -/// - CHANNEL_PWM_LED2 -/// -/// !SPI -/// - PIN_SPI_MISO -/// - PIN_SPI_MOSI -/// - PIN_SPI_SPCK -/// - PINS_SPI -/// - PIN_SPI_NPCS0_PA11 -/// -/// ! SSC -/// - PIN_SSC_TD -/// - PIN_SSC_TK -/// - PIN_SSC_TF -/// - PINS_SSC_CODEC -/// -/// ! PCK0 -/// - PIN_PCK0 -/// -/// !TWI -/// - PIN_TWI_TWD0 -/// - PIN_TWI_TWCK0 -/// - PINS_TWI -/// -/// !USART0 -/// - PIN_USART0_RXD -/// - PIN_USART0_TXD -/// - PIN_USART0_CTS -/// - PIN_USART0_RTS -/// - PIN_USART0_SCK -/// -/// !USB -/// - PIN_USB_PULLUP -/// - -/// ADC_AD0 pin definition. -#define PIN_ADC0_AD0 {1 << 21, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD1 pin definition. -#define PIN_ADC0_AD1 {1 << 30, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD2 pin definition. -#define PIN_ADC0_AD2 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD3 pin definition. -#define PIN_ADC0_AD3 {1 << 4, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD4 pin definition. -#define PIN_ADC0_AD4 {1 << 15, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD5 pin definition. -#define PIN_ADC0_AD5 {1 << 16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD6 pin definition. -#define PIN_ADC0_AD6 {1 << 17, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD7 pin definition. -#define PIN_ADC0_AD7 {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} - -/// Pins ADC -#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7 - -/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */ -#define PINS_UART {0x00000600, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// EBI -#define PIN_EBI_DATA_BUS {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NRD {1 << 11, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NWE {1 << 8, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -#define PIN_EBI_NCS0 {1 << 20, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_PSRAM_ADDR_BUS {0x3f00fff, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_PSRAM_NBS {1 << 7, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}, \ - {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_A1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -#define PIN_EBI_NCS1 {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD CS pin */ -#define PIN_EBI_LCD_RS {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD RS pin */ - -#ifdef BOARD_REV_A -/** LED #0 pin definition. */ -#define PIN_LED_0 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #1 pin definition. */ -#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #2 pin definition. */ -#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#endif -#ifdef BOARD_REV_B -/** LED #0 pin definition. */ -#define PIN_LED_0 {1 << 19, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #1 pin definition. */ -#define PIN_LED_1 {1 << 20, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #2 pin definition. */ -#define PIN_LED_2 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#endif - -/** List of all LEDs definitions. */ -#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2 - -/** MCI pins definition. */ -#define PINS_MCI {0x3fUL << 26, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP} -/** MCI pin Card Detect. */ -#define PIN_MCI_CD {PIO_PB7, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP} - -/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ -#define PIN_PUSHBUTTON_1 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} -/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on falling edge. */ -#define PIN_PUSHBUTTON_2 {1 << 12, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} -/** List of all push button definitions. */ -#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 - -/** Push button #1 index. */ -#define PUSHBUTTON_BP1 0 -/** Push button #2 index. */ -#define PUSHBUTTON_BP2 1 - -/// Simulated joystick LEFT index. -#define JOYSTICK_LEFT 0 -/// Simulated joystick RIGHT index. -#define JOYSTICK_RIGHT 1 - -/** PWMC PWM0 pin definition. */ -#define PIN_PWMC_PWMH0 {1 << 18, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML0 {1 << 19, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} -/** PWMC PWM1 pin definition. */ -#define PIN_PWMC_PWMH1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML1 {1 << 20, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} -/** PWMC PWM2 pin definition. */ -#define PIN_PWMC_PWMH2 {1 << 20, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML2 {1 << 16, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} -/** PWMC PWM3 pin definition. */ -#define PIN_PWMC_PWMH3 {1 << 21, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML3 {1 << 15, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} -/** PWM pin definition for LED0 */ -#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0 -/** PWM pin definition for LED1 */ -#define PIN_PWM_LED1 PIN_PWMC_PWMH2, PIN_PWMC_PWML2 -/** PWM pin definition for LED2 */ -#define PIN_PWM_LED2 PIN_PWMC_PWMH3, PIN_PWMC_PWML3 -/** PWM channel for LED0 */ -#define CHANNEL_PWM_LED0 0 -/** PWM channel for LED1 */ -#define CHANNEL_PWM_LED1 2 -/** PWM channel for LED2 */ -#define CHANNEL_PWM_LED2 3 - -/** SPI MISO pin definition. */ -#define PIN_SPI_MISO {1 << 12, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI MOSI pin definition. */ -#define PIN_SPI_MOSI {1 << 13, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI SPCK pin definition. */ -#define PIN_SPI_SPCK {1 << 14, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI chip select pin definition. */ -#define PIN_SPI_NPCS0_PA11 {1 << 11, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** List of SPI pin definitions (MISO, MOSI & SPCK). */ -#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK - -/// SSC pins definition. -#define PIN_SSC_TD {0x1 << 26, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_SSC_TK {0x1 << 28, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_SSC_TF {0x1 << 30, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF - -/// PCK0 -#define PIN_PCK0 {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} - -/// TWI pins definition. -#define TWI_V3XX -#define PIN_TWI_TWD0 {0x1 << 9, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_TWI_TWCK0 {0x1 << 10, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0 -#define PIN_TWI_TWD1 {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_TWI_TWCK1 {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1 - -/// USART0 -#define PIN_USART0_RXD {0x1 << 19, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_TXD {0x1 << 18, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_CTS {0x1 << 8, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_RTS {0x1 << 7, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_SCK {0x1 << 17, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// USART1 -#define PIN_USART1_RXD {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_TXD {0x1 << 22, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_CTS {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_RTS {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_EN {0x1 << 23, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} - -/// USB VBus monitoring pin definition. -#ifdef BOARD_REV_A -#define PIN_USB_VBUS {1 << 23, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -#endif -#ifdef BOARD_REV_B -#define PIN_USB_VBUS {1 << 21, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -#endif - -#define usbPlugged() (PIOC->PIO_PDSR & PIO_PC25) - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_extcomp "SAM3S-EK - External components" -/// This page lists the definitions related to external on-board components -/// located in the board.h file for the AT91SAM3S-EK. -/// -/// !AT45 Dataflash Card -/// - BOARD_AT45_A_SPI_BASE -/// - BOARD_AT45_A_SPI_ID -/// - BOARD_AT45_A_SPI_PINS -/// - BOARD_AT45_A_SPI -/// - BOARD_AT45_A_NPCS -/// - BOARD_AT45_A_NPCS_PIN -/// -/// !AT45 Dataflash (serial onboard DataFlash) -/// - BOARD_AT45_B_SPI_BASE -/// - BOARD_AT45_B_SPI_ID -/// - BOARD_AT45_B_SPI_PINS -/// - BOARD_AT45_B_SPI -/// - BOARD_AT45_B_NPCS -/// - BOARD_AT45_B_NPCS_PIN -/// -/// !AT26 Serial Flash -/// - BOARD_AT26_A_SPI_BASE -/// - BOARD_AT26_A_SPI_ID -/// - BOARD_AT26_A_SPI_PINS -/// - BOARD_AT26_A_SPI -/// - BOARD_AT26_A_NPCS -/// - BOARD_AT26_A_NPCS_PIN -/// -/// !SD Card -/// - MCI2_INTERFACE -/// - BOARD_SD_MCI_BASE -/// - BOARD_SD_MCI_ID -/// - BOARD_SD_PINS -/// - BOARD_SD_SLOT -/// -/// !PSRAM -/// - BOARD_PSRAM_PINS -/// -/// !LCD -/// - BOARD_LCD_ILI9325 -/// - BOARD_LCD_PINS -/// - BOARD_BACKLIGHT_PIN -/// - BOARD_LCD_BASE -/// - BOARD_LCD_RS -/// - BOARD_LCD_WIDTH -/// - BOARD_LCD_HEIGHT -/// -/// !TouchScreen -/// - BOARD_TSC_ADS7843 -/// - PIN_TCS_IRQ -/// - PIN_TCS_BUSY -/// - BOARD_TSC_SPI_BASE -/// - BOARD_TSC_SPI_ID -/// - BOARD_TSC_SPI_PINS -/// - BOARD_TSC_NPCS -/// - BOARD_TSC_NPCS_PIN -/// -/// Base address of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_BASE SPI0 -///// Identifier of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_ID ID_SPI0 -///// Pins of the SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_PINS PINS_SPI0 -///// Dataflahs SPI number. -//#define BOARD_AT45_A_SPI 0 -///// Chip select connected to the dataflash. -//#define BOARD_AT45_A_NPCS 3 -///// Chip select pin connected to the dataflash. -//#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS3 - -/// Base address of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_BASE SPI1 -///// Identifier of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_ID ID_SPI1 -///// Pins of the SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_PINS PINS_SPI1 -///// Dataflahs SPI number. -//#define BOARD_AT45_B_SPI 1 -///// Chip select connected to the dataflash. -//#define BOARD_AT45_B_NPCS 3 -///// Chip select pin connected to the dataflash. -//#define BOARD_AT45_B_NPCS_PIN PIN_SPI1_NPCS3 - -/// Base address of SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_BASE SPI0 -///// Identifier of SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_ID ID_SPI0 -///// Pins of the SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_PINS PINS_SPI0 -///// Serialflash SPI number. -//#define BOARD_AT26_A_SPI 0 -///// Chip select connected to the serialflash. -//#define BOARD_AT26_A_NPCS 3 -///// Chip select pin connected to the serialflash. -//#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS3 - -/// ISO7816 -/// - PIN_SMARTCARD_CONNECT -/// - PIN_ISO7816_RSTMC -/// - PINS_ISO7816 - -/// Smartcard detection pin -//#define PIN_SMARTCARD_CONNECT {1 << 5, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// PIN used for reset the smartcard -//#define PIN_ISO7816_RSTMC {1 << 7, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} -/// Pins used for connect the smartcard -//#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK, PIN_ISO7816_RSTMC - -/// Dma channel number -#define BOARD_MCI_DMA_CHANNEL 0 -/// MCI0 DMA hardware handshaking ID -#define DMA_HW_SRC_REQ_ID_MCI0 AT91C_HDMA_SRC_PER_0 -#define DMA_HW_DEST_REQ_ID_MCI0 AT91C_HDMA_DST_PER_0 -/// MCI1 DMA hardware handshaking ID -#define DMA_HW_SRC_REQ_ID_MCI1 AT91C_HDMA_SRC_PER_13 -#define DMA_HW_DEST_REQ_ID_MCI1 AT91C_HDMA_DST_PER_13 -/// SD DMA hardware handshaking ID -#define BOARD_SD_DMA_HW_SRC_REQ_ID DMA_HW_SRC_REQ_ID_MCI0 -#define BOARD_SD_DMA_HW_DEST_REQ_ID DMA_HW_DEST_REQ_ID_MCI0 - - -/// HS MCI interface -#define MCI2_INTERFACE -/// Base address of the MCI peripheral connected to the SD card. -#define BOARD_SD_MCI_BASE MCI0//MCI -///// Peripheral identifier of the MCI connected to the SD card. -#define BOARD_SD_MCI_ID AT91C_ID_MCI0 ID_MCI0 //ID_MCI -///// MCI pins that shall be configured to access the SD card. -#define BOARD_SD_PINS PINS_MCI -///// MCI slot to which the SD card is connected to. -#define BOARD_SD_SLOT MCI_SD_SLOTA -///// MCI Card Detect pin. -#define BOARD_SD_PIN_CD PIN_MCI_CD - -#define BLOCK_SIZE 512 -#define MSD_BUFFER_SIZE (12*BLOCK_SIZE) // Size of the MSD IO buffer in bytes (6K, more the better) -#define SD_CARD_PRESENT() ( (PIOB->PIO_PDSR & PIO_PB7) == 0 ) - -// States for initialising card -#define SD_ST_ERR -1 -#define SD_ST_STARTUP 0 -#define SD_ST_EMPTY 1 -#define SD_ST_INIT1 2 -#define SD_ST_INIT2 3 -#define SD_ST_IDLE 4 -#define SD_ST_READY 5 -#define SD_ST_IDENT 6 -#define SD_ST_STBY 7 -#define SD_ST_TRAN 8 -#define SD_ST_DATA 9 -#define SD_ST_MOUNTED 10 - -extern uint32_t Cmd_A41_resp; -extern int32_t Card_state; -extern volatile uint32_t Card_initialized; -extern uint32_t Card_CSD[4]; -extern uint32_t transSpeed; - -#define OCR_SD_CCS (1UL << 30) - -#define SD_CSD(csd, bitfield, bits) ((csd[3-(bitfield)/32] >> ((bitfield)%32)) & ((1 << (bits)) - 1)) - -#define SD_CSD_TRAN_SPEED(pSd) SD_CSD(pSd, 96, 8) ///< Max. data transfer rate - -#define SD_CSD_C_SIZE(pSd) ((SD_CSD(pSd, 72, 2) << 10) + \ - (SD_CSD(pSd, 64, 8) << 2) + \ - SD_CSD(pSd, 62, 2)) ///< Device size - -#define SD_CSD_C_SIZE_HC(csd) ((SD_CSD(csd, 64, 6) << 16) + \ - (SD_CSD(csd, 56, 8) << 8) + \ - SD_CSD(csd, 48, 8)) ///< Device size v2.0 High Capacity - -#define SD_CSD_C_SIZE_MULT(pSd) SD_CSD(pSd, 47, 3) ///< Device size multiplier - -#define SD_CSD_MULT(pSd) (1 << (SD_CSD_C_SIZE_MULT(pSd) + 2)) - -#define SD_CSD_READ_BL_LEN(pSd) SD_CSD(pSd, 80, 4) ///< Max. read data block length - -#define SD_CSD_BLKLEN(pSd) (1 << (SD_CSD_READ_BL_LEN(pSd) - 9)) - -#define SD_CSD_BLOCKNR(pSd) ((SD_CSD_C_SIZE(pSd) + 1) * SD_CSD_MULT(pSd)) * SD_CSD_BLKLEN(pSd) - -#define SD_CSD_BLOCKNR_HC(pSd) ((SD_CSD_C_SIZE_HC(pSd) + 1) * 1024) - -#if !defined(SIMU) - #define SD_IS_HC() (Cmd_A41_resp & OCR_SD_CCS) - #define SD_GET_BLOCKNR() (SD_IS_HC() ? (SD_CSD_BLOCKNR_HC(Card_CSD)) : (SD_CSD_BLOCKNR(Card_CSD))) - #define SD_GET_SPEED() (transSpeed) -#else - #define SD_IS_HC() (0) - #define SD_GET_BLOCKNR() (0) - #define SD_GET_SPEED() (0) -#endif - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_mem "SAM3S-EK - Memories" -/// This page lists definitions related to internal & external on-board memories. -/// -/// !Embedded Flash -/// - BOARD_FLASH_EFC - -/// Internal SRAM address -#define AT91C_ISRAM AT91C_IRAM -#define AT91C_ISRAM_SIZE 0x00008000 - -#define AT91C_IFLASH_SIZE (0x40000) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH 0 Page Size: 256 bytes -#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH 0 Number of Pages: 512 -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH 0 Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH 0 Number of Lock Bits: 16 - -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \section sam3s_ek_extcomp "SAM3S-EK - External components" -/// This page lists the definitions related to external on-board components -/// located in the board.h file for the SAM3S-EK. -/// -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_chipdef "SAM3S-EK - Individual chip definition" -/// This page lists the definitions related to different chip's definition -/// located in the board.h file for the SAM3S-EK. - -/// DBGU -#define BOARD_DBGU_ID ID_DBGU - -/// Rtc -#define BOARD_RTC_ID ID_RTC - -/// Twi eeprom -#define BOARD_ID_TWI_EEPROM ID_TWI1 -#define BOARD_BASE_TWI_EEPROM TWI1 -#define BOARD_PINS_TWI_EEPROM PINS_TWI1 - -/// USART -#define BOARD_PIN_USART_RXD PIN_USART1_RXD -#define BOARD_PIN_USART_TXD PIN_USART1_TXD -#define BOARD_PIN_USART_CTS PIN_USART1_CTS -#define BOARD_PIN_USART_RTS PIN_USART1_RTS -#define BOARD_PIN_USART_EN PIN_USART1_EN -#define BOARD_USART_BASE USART1 -#define BOARD_ID_USART ID_USART1 - -// BlueTooth -#define BT_USART UART1 -#define BT_ID ID_UART1 - -//------------------------------------------------------------------------------ - - -#define PIN_EBI_NANDOE {1 << 9, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDWE {1 << 10, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDCLE {1 << 17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDALE {1 << 16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDIO {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -/// Nandflash chip enable pin definition. -#define BOARD_NF_CE_PIN {1 << 14, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/// Nandflash ready/busy pin definition. -#define BOARD_NF_RB_PIN {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP} - -/// Nandflash controller peripheral pins definition. -#define PINS_NANDFLASH PIN_EBI_NANDIO, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, \ - PIN_EBI_NANDWE, PIN_EBI_NANDCLE, PIN_EBI_NANDALE - -/// Address for transferring command bytes to the nandflash. -#define BOARD_NF_COMMAND_ADDR 0x60400000 -/// Address for transferring address bytes to the nandflash. -#define BOARD_NF_ADDRESS_ADDR 0x60200000 -/// Address for transferring data bytes to the nandflash. -#define BOARD_NF_DATA_ADDR 0x60000000 - -extern uint32_t Master_frequency ; - -struct t_serial_tx -{ - uint8_t *buffer ; - uint16_t size ; - volatile uint16_t ready ; -}; - -#endif // _BOARD_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// TODO merge this file with board_sky9x.h + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include + +#include "chip.h" + +#if defined(REVA) +#include "AT91SAM3S2.h" +#else +#include "AT91SAM3S4.h" +#endif + +#if !defined(SIMU) +#include "core_cm3.h" +#endif + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par +/// This page lists several definition related to the board description. +/// +/// Definitions +/// - BOARD_NAME + +/// Name of the board. +#define BOARD_NAME "AT91SAM3S-EK" +/// Board definition. +#define at91sam3sek +/// Family definition (already defined). +#define at91sam3s +/// Core definition +#define cortexm3 + +// TODO remove these definitions +//#define BOARD_REV_A +#define BOARD_REV_B + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_opfreq "SAM3S-EK - Operating frequencies" +/// This page lists several definition related to the board operating frequency +/// (when using the initialization done by board_lowlevel.c). +/// +/// !Definitions +/// - BOARD_MAINOSC +/// - BOARD_MCK + +/// Frequency of the board main oscillator. +#define BOARD_MAINOSC 12000000 + +/// Master clock frequency (when using board_lowlevel.c). +// #define BOARD_MCK 64000000 + +//------------------------------------------------------------------------------ +// ADC +//------------------------------------------------------------------------------ + +/// Startup time max, return from Idle mode (in �s) +#define ADC_STARTUP_TIME_MAX 15 +/// Track and hold Acquisition Time min (in ns) +#define ADC_TRACK_HOLD_TIME_MIN 1200 + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// USB attributes configuration descriptor (bus or self powered, remote wakeup) +//#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP +#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_piodef "SAM3S-EK - PIO definitions" +/// This pages lists all the pio definitions contained in board.h. The constants +/// are named using the following convention: PIN_* for a constant which defines +/// a single Pin instance (but may include several PIOs sharing the same +/// controller), and PINS_* for a list of Pin instances. +/// +/// !ADC +/// - PIN_ADC0_AD0 +/// - PIN_ADC0_AD1 +/// - PIN_ADC0_AD2 +/// - PIN_ADC0_AD3 +/// - PIN_ADC0_AD4 +/// - PIN_ADC0_AD5 +/// - PIN_ADC0_AD6 +/// - PIN_ADC0_AD7 +/// - PINS_ADC0 +/// +/// !UART +/// - PINS_UART +/// +/// !EBI +/// - PIN_EBI_DATA_BUS +/// - PIN_EBI_NCS0 +/// - PIN_EBI_NRD +/// - PIN_EBI_NWE +/// - PIN_EBI_ADDR_BUS +/// - PIN_EBI_PSRAM_NBS +/// - PIN_EBI_A1 +/// - PIN_EBI_LCD_RS +/// +/// !LEDs +/// - PIN_LED_0 +/// - PIN_LED_1 +/// - PIN_LED_2 +/// - PINS_LEDS +/// +/// !MCI +/// - PINS_MCI +/// +/// !Push buttons +/// - PIN_PUSHBUTTON_1 +/// - PIN_PUSHBUTTON_2 +/// - PINS_PUSHBUTTONS +/// - PUSHBUTTON_BP1 +/// - PUSHBUTTON_BP2 +/// +/// !PWMC +/// - PIN_PWMC_PWMH0 +/// - PIN_PWMC_PWML0 +/// - PIN_PWMC_PWMH1 +/// - PIN_PWMC_PWML1 +/// - PIN_PWMC_PWMH2 +/// - PIN_PWMC_PWML2 +/// - PIN_PWMC_PWMH3 +/// - PIN_PWMC_PWML3 +/// - PIN_PWM_LED0 +/// - PIN_PWM_LED1 +/// - PIN_PWM_LED2 +/// - CHANNEL_PWM_LED0 +/// - CHANNEL_PWM_LED1 +/// - CHANNEL_PWM_LED2 +/// +/// !SPI +/// - PIN_SPI_MISO +/// - PIN_SPI_MOSI +/// - PIN_SPI_SPCK +/// - PINS_SPI +/// - PIN_SPI_NPCS0_PA11 +/// +/// ! SSC +/// - PIN_SSC_TD +/// - PIN_SSC_TK +/// - PIN_SSC_TF +/// - PINS_SSC_CODEC +/// +/// ! PCK0 +/// - PIN_PCK0 +/// +/// !TWI +/// - PIN_TWI_TWD0 +/// - PIN_TWI_TWCK0 +/// - PINS_TWI +/// +/// !USART0 +/// - PIN_USART0_RXD +/// - PIN_USART0_TXD +/// - PIN_USART0_CTS +/// - PIN_USART0_RTS +/// - PIN_USART0_SCK +/// +/// !USB +/// - PIN_USB_PULLUP +/// + +/// ADC_AD0 pin definition. +#define PIN_ADC0_AD0 {1 << 21, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD1 pin definition. +#define PIN_ADC0_AD1 {1 << 30, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD2 pin definition. +#define PIN_ADC0_AD2 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD3 pin definition. +#define PIN_ADC0_AD3 {1 << 4, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD4 pin definition. +#define PIN_ADC0_AD4 {1 << 15, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD5 pin definition. +#define PIN_ADC0_AD5 {1 << 16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD6 pin definition. +#define PIN_ADC0_AD6 {1 << 17, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD7 pin definition. +#define PIN_ADC0_AD7 {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} + +/// Pins ADC +#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7 + +/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */ +#define PINS_UART {0x00000600, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// EBI +#define PIN_EBI_DATA_BUS {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NRD {1 << 11, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NWE {1 << 8, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} + +#define PIN_EBI_NCS0 {1 << 20, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_PSRAM_ADDR_BUS {0x3f00fff, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_PSRAM_NBS {1 << 7, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}, \ + {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_A1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} + +#define PIN_EBI_NCS1 {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD CS pin */ +#define PIN_EBI_LCD_RS {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD RS pin */ + +#ifdef BOARD_REV_A +/** LED #0 pin definition. */ +#define PIN_LED_0 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #1 pin definition. */ +#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #2 pin definition. */ +#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#endif +#ifdef BOARD_REV_B +/** LED #0 pin definition. */ +#define PIN_LED_0 {1 << 19, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #1 pin definition. */ +#define PIN_LED_1 {1 << 20, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #2 pin definition. */ +#define PIN_LED_2 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#endif + +/** List of all LEDs definitions. */ +#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2 + +/** MCI pins definition. */ +#define PINS_MCI {0x3fUL << 26, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP} +/** MCI pin Card Detect. */ +#define PIN_MCI_CD {PIO_PB7, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP} + +/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ +#define PIN_PUSHBUTTON_1 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} +/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on falling edge. */ +#define PIN_PUSHBUTTON_2 {1 << 12, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} +/** List of all push button definitions. */ +#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 + +/** Push button #1 index. */ +#define PUSHBUTTON_BP1 0 +/** Push button #2 index. */ +#define PUSHBUTTON_BP2 1 + +/// Simulated joystick LEFT index. +#define JOYSTICK_LEFT 0 +/// Simulated joystick RIGHT index. +#define JOYSTICK_RIGHT 1 + +/** PWMC PWM0 pin definition. */ +#define PIN_PWMC_PWMH0 {1 << 18, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML0 {1 << 19, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} +/** PWMC PWM1 pin definition. */ +#define PIN_PWMC_PWMH1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML1 {1 << 20, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} +/** PWMC PWM2 pin definition. */ +#define PIN_PWMC_PWMH2 {1 << 20, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML2 {1 << 16, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} +/** PWMC PWM3 pin definition. */ +#define PIN_PWMC_PWMH3 {1 << 21, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML3 {1 << 15, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} +/** PWM pin definition for LED0 */ +#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0 +/** PWM pin definition for LED1 */ +#define PIN_PWM_LED1 PIN_PWMC_PWMH2, PIN_PWMC_PWML2 +/** PWM pin definition for LED2 */ +#define PIN_PWM_LED2 PIN_PWMC_PWMH3, PIN_PWMC_PWML3 +/** PWM channel for LED0 */ +#define CHANNEL_PWM_LED0 0 +/** PWM channel for LED1 */ +#define CHANNEL_PWM_LED1 2 +/** PWM channel for LED2 */ +#define CHANNEL_PWM_LED2 3 + +/** SPI MISO pin definition. */ +#define PIN_SPI_MISO {1 << 12, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI MOSI pin definition. */ +#define PIN_SPI_MOSI {1 << 13, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI SPCK pin definition. */ +#define PIN_SPI_SPCK {1 << 14, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI chip select pin definition. */ +#define PIN_SPI_NPCS0_PA11 {1 << 11, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** List of SPI pin definitions (MISO, MOSI & SPCK). */ +#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK + +/// SSC pins definition. +#define PIN_SSC_TD {0x1 << 26, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SSC_TK {0x1 << 28, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SSC_TF {0x1 << 30, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF + +/// PCK0 +#define PIN_PCK0 {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} + +/// TWI pins definition. +#define TWI_V3XX +#define PIN_TWI_TWD0 {0x1 << 9, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_TWI_TWCK0 {0x1 << 10, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0 +#define PIN_TWI_TWD1 {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_TWI_TWCK1 {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1 + +/// USART0 +#define PIN_USART0_RXD {0x1 << 19, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_TXD {0x1 << 18, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_CTS {0x1 << 8, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_RTS {0x1 << 7, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_SCK {0x1 << 17, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// USART1 +#define PIN_USART1_RXD {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_TXD {0x1 << 22, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_CTS {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_RTS {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_EN {0x1 << 23, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} + +/// USB VBus monitoring pin definition. +#ifdef BOARD_REV_A +#define PIN_USB_VBUS {1 << 23, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +#endif +#ifdef BOARD_REV_B +#define PIN_USB_VBUS {1 << 21, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +#endif + +#define usbPlugged() (PIOC->PIO_PDSR & PIO_PC25) + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_extcomp "SAM3S-EK - External components" +/// This page lists the definitions related to external on-board components +/// located in the board.h file for the AT91SAM3S-EK. +/// +/// !AT45 Dataflash Card +/// - BOARD_AT45_A_SPI_BASE +/// - BOARD_AT45_A_SPI_ID +/// - BOARD_AT45_A_SPI_PINS +/// - BOARD_AT45_A_SPI +/// - BOARD_AT45_A_NPCS +/// - BOARD_AT45_A_NPCS_PIN +/// +/// !AT45 Dataflash (serial onboard DataFlash) +/// - BOARD_AT45_B_SPI_BASE +/// - BOARD_AT45_B_SPI_ID +/// - BOARD_AT45_B_SPI_PINS +/// - BOARD_AT45_B_SPI +/// - BOARD_AT45_B_NPCS +/// - BOARD_AT45_B_NPCS_PIN +/// +/// !AT26 Serial Flash +/// - BOARD_AT26_A_SPI_BASE +/// - BOARD_AT26_A_SPI_ID +/// - BOARD_AT26_A_SPI_PINS +/// - BOARD_AT26_A_SPI +/// - BOARD_AT26_A_NPCS +/// - BOARD_AT26_A_NPCS_PIN +/// +/// !SD Card +/// - MCI2_INTERFACE +/// - BOARD_SD_MCI_BASE +/// - BOARD_SD_MCI_ID +/// - BOARD_SD_PINS +/// - BOARD_SD_SLOT +/// +/// !PSRAM +/// - BOARD_PSRAM_PINS +/// +/// !LCD +/// - BOARD_LCD_ILI9325 +/// - BOARD_LCD_PINS +/// - BOARD_BACKLIGHT_PIN +/// - BOARD_LCD_BASE +/// - BOARD_LCD_RS +/// - BOARD_LCD_WIDTH +/// - BOARD_LCD_HEIGHT +/// +/// !TouchScreen +/// - BOARD_TSC_ADS7843 +/// - PIN_TCS_IRQ +/// - PIN_TCS_BUSY +/// - BOARD_TSC_SPI_BASE +/// - BOARD_TSC_SPI_ID +/// - BOARD_TSC_SPI_PINS +/// - BOARD_TSC_NPCS +/// - BOARD_TSC_NPCS_PIN +/// +/// Base address of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_A_SPI_BASE SPI0 +///// Identifier of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_A_SPI_ID ID_SPI0 +///// Pins of the SPI peripheral connected to the dataflash. +//#define BOARD_AT45_A_SPI_PINS PINS_SPI0 +///// Dataflahs SPI number. +//#define BOARD_AT45_A_SPI 0 +///// Chip select connected to the dataflash. +//#define BOARD_AT45_A_NPCS 3 +///// Chip select pin connected to the dataflash. +//#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS3 + +/// Base address of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_B_SPI_BASE SPI1 +///// Identifier of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_B_SPI_ID ID_SPI1 +///// Pins of the SPI peripheral connected to the dataflash. +//#define BOARD_AT45_B_SPI_PINS PINS_SPI1 +///// Dataflahs SPI number. +//#define BOARD_AT45_B_SPI 1 +///// Chip select connected to the dataflash. +//#define BOARD_AT45_B_NPCS 3 +///// Chip select pin connected to the dataflash. +//#define BOARD_AT45_B_NPCS_PIN PIN_SPI1_NPCS3 + +/// Base address of SPI peripheral connected to the serialflash. +//#define BOARD_AT26_A_SPI_BASE SPI0 +///// Identifier of SPI peripheral connected to the serialflash. +//#define BOARD_AT26_A_SPI_ID ID_SPI0 +///// Pins of the SPI peripheral connected to the serialflash. +//#define BOARD_AT26_A_SPI_PINS PINS_SPI0 +///// Serialflash SPI number. +//#define BOARD_AT26_A_SPI 0 +///// Chip select connected to the serialflash. +//#define BOARD_AT26_A_NPCS 3 +///// Chip select pin connected to the serialflash. +//#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS3 + +/// ISO7816 +/// - PIN_SMARTCARD_CONNECT +/// - PIN_ISO7816_RSTMC +/// - PINS_ISO7816 + +/// Smartcard detection pin +//#define PIN_SMARTCARD_CONNECT {1 << 5, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// PIN used for reset the smartcard +//#define PIN_ISO7816_RSTMC {1 << 7, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} +/// Pins used for connect the smartcard +//#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK, PIN_ISO7816_RSTMC + +/// Dma channel number +#define BOARD_MCI_DMA_CHANNEL 0 +/// MCI0 DMA hardware handshaking ID +#define DMA_HW_SRC_REQ_ID_MCI0 AT91C_HDMA_SRC_PER_0 +#define DMA_HW_DEST_REQ_ID_MCI0 AT91C_HDMA_DST_PER_0 +/// MCI1 DMA hardware handshaking ID +#define DMA_HW_SRC_REQ_ID_MCI1 AT91C_HDMA_SRC_PER_13 +#define DMA_HW_DEST_REQ_ID_MCI1 AT91C_HDMA_DST_PER_13 +/// SD DMA hardware handshaking ID +#define BOARD_SD_DMA_HW_SRC_REQ_ID DMA_HW_SRC_REQ_ID_MCI0 +#define BOARD_SD_DMA_HW_DEST_REQ_ID DMA_HW_DEST_REQ_ID_MCI0 + + +/// HS MCI interface +#define MCI2_INTERFACE +/// Base address of the MCI peripheral connected to the SD card. +#define BOARD_SD_MCI_BASE MCI0//MCI +///// Peripheral identifier of the MCI connected to the SD card. +#define BOARD_SD_MCI_ID AT91C_ID_MCI0 ID_MCI0 //ID_MCI +///// MCI pins that shall be configured to access the SD card. +#define BOARD_SD_PINS PINS_MCI +///// MCI slot to which the SD card is connected to. +#define BOARD_SD_SLOT MCI_SD_SLOTA +///// MCI Card Detect pin. +#define BOARD_SD_PIN_CD PIN_MCI_CD + +#define BLOCK_SIZE 512 +#define MSD_BUFFER_SIZE (12*BLOCK_SIZE) // Size of the MSD IO buffer in bytes (6K, more the better) +#define SD_CARD_PRESENT() ( (PIOB->PIO_PDSR & PIO_PB7) == 0 ) + +// States for initialising card +#define SD_ST_ERR -1 +#define SD_ST_STARTUP 0 +#define SD_ST_EMPTY 1 +#define SD_ST_INIT1 2 +#define SD_ST_INIT2 3 +#define SD_ST_IDLE 4 +#define SD_ST_READY 5 +#define SD_ST_IDENT 6 +#define SD_ST_STBY 7 +#define SD_ST_TRAN 8 +#define SD_ST_DATA 9 +#define SD_ST_MOUNTED 10 + +extern uint32_t Cmd_A41_resp; +extern int32_t Card_state; +extern volatile uint32_t Card_initialized; +extern uint32_t Card_CSD[4]; +extern uint32_t transSpeed; + +#define OCR_SD_CCS (1UL << 30) + +#define SD_CSD(csd, bitfield, bits) ((csd[3-(bitfield)/32] >> ((bitfield)%32)) & ((1 << (bits)) - 1)) + +#define SD_CSD_TRAN_SPEED(pSd) SD_CSD(pSd, 96, 8) ///< Max. data transfer rate + +#define SD_CSD_C_SIZE(pSd) ((SD_CSD(pSd, 72, 2) << 10) + \ + (SD_CSD(pSd, 64, 8) << 2) + \ + SD_CSD(pSd, 62, 2)) ///< Device size + +#define SD_CSD_C_SIZE_HC(csd) ((SD_CSD(csd, 64, 6) << 16) + \ + (SD_CSD(csd, 56, 8) << 8) + \ + SD_CSD(csd, 48, 8)) ///< Device size v2.0 High Capacity + +#define SD_CSD_C_SIZE_MULT(pSd) SD_CSD(pSd, 47, 3) ///< Device size multiplier + +#define SD_CSD_MULT(pSd) (1 << (SD_CSD_C_SIZE_MULT(pSd) + 2)) + +#define SD_CSD_READ_BL_LEN(pSd) SD_CSD(pSd, 80, 4) ///< Max. read data block length + +#define SD_CSD_BLKLEN(pSd) (1 << (SD_CSD_READ_BL_LEN(pSd) - 9)) + +#define SD_CSD_BLOCKNR(pSd) ((SD_CSD_C_SIZE(pSd) + 1) * SD_CSD_MULT(pSd)) * SD_CSD_BLKLEN(pSd) + +#define SD_CSD_BLOCKNR_HC(pSd) ((SD_CSD_C_SIZE_HC(pSd) + 1) * 1024) + +#if !defined(SIMU) + #define SD_IS_HC() (Cmd_A41_resp & OCR_SD_CCS) + #define SD_GET_BLOCKNR() (SD_IS_HC() ? (SD_CSD_BLOCKNR_HC(Card_CSD)) : (SD_CSD_BLOCKNR(Card_CSD))) + #define SD_GET_SPEED() (transSpeed) +#else + #define SD_IS_HC() (0) + #define SD_GET_BLOCKNR() (0) + #define SD_GET_SPEED() (0) +#endif + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_mem "SAM3S-EK - Memories" +/// This page lists definitions related to internal & external on-board memories. +/// +/// !Embedded Flash +/// - BOARD_FLASH_EFC + +/// Internal SRAM address +#define AT91C_ISRAM AT91C_IRAM +#define AT91C_ISRAM_SIZE 0x00008000 + +#define AT91C_IFLASH_SIZE (0x40000) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH 0 Page Size: 256 bytes +#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH 0 Number of Pages: 512 +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH 0 Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH 0 Number of Lock Bits: 16 + +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +/// \section sam3s_ek_extcomp "SAM3S-EK - External components" +/// This page lists the definitions related to external on-board components +/// located in the board.h file for the SAM3S-EK. +/// +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_chipdef "SAM3S-EK - Individual chip definition" +/// This page lists the definitions related to different chip's definition +/// located in the board.h file for the SAM3S-EK. + +/// DBGU +#define BOARD_DBGU_ID ID_DBGU + +/// Rtc +#define BOARD_RTC_ID ID_RTC + +/// Twi eeprom +#define BOARD_ID_TWI_EEPROM ID_TWI1 +#define BOARD_BASE_TWI_EEPROM TWI1 +#define BOARD_PINS_TWI_EEPROM PINS_TWI1 + +/// USART +#define BOARD_PIN_USART_RXD PIN_USART1_RXD +#define BOARD_PIN_USART_TXD PIN_USART1_TXD +#define BOARD_PIN_USART_CTS PIN_USART1_CTS +#define BOARD_PIN_USART_RTS PIN_USART1_RTS +#define BOARD_PIN_USART_EN PIN_USART1_EN +#define BOARD_USART_BASE USART1 +#define BOARD_ID_USART ID_USART1 + +// BlueTooth +#define BT_USART UART1 +#define BT_ID ID_UART1 + +//------------------------------------------------------------------------------ + + +#define PIN_EBI_NANDOE {1 << 9, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDWE {1 << 10, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDCLE {1 << 17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDALE {1 << 16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDIO {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} + +/// Nandflash chip enable pin definition. +#define BOARD_NF_CE_PIN {1 << 14, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/// Nandflash ready/busy pin definition. +#define BOARD_NF_RB_PIN {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP} + +/// Nandflash controller peripheral pins definition. +#define PINS_NANDFLASH PIN_EBI_NANDIO, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, \ + PIN_EBI_NANDWE, PIN_EBI_NANDCLE, PIN_EBI_NANDALE + +/// Address for transferring command bytes to the nandflash. +#define BOARD_NF_COMMAND_ADDR 0x60400000 +/// Address for transferring address bytes to the nandflash. +#define BOARD_NF_ADDRESS_ADDR 0x60200000 +/// Address for transferring data bytes to the nandflash. +#define BOARD_NF_DATA_ADDR 0x60000000 + +extern uint32_t Master_frequency ; + +struct t_serial_tx +{ + uint8_t *buffer ; + uint16_t size ; + volatile uint16_t ready ; +}; + +#endif // _BOARD_H_ diff --git a/radio/src/targets/sky9x/buzzer_driver.cpp b/radio/src/targets/sky9x/buzzer_driver.cpp index eb96067be..04f2797e9 100644 --- a/radio/src/targets/sky9x/buzzer_driver.cpp +++ b/radio/src/targets/sky9x/buzzer_driver.cpp @@ -1,59 +1,59 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -volatile uint8_t buzzerCount ; - -#if defined(REVA) -void buzzerOn() -{ - PIOA->PIO_SODR = 0x00010000L ; // Set bit A16 ON -} - -void buzzerOff() -{ - PIOA->PIO_CODR = 0x00010000L ; // Set bit A16 ON -} -#else -void buzzerOn() -{ - PIOA->PIO_SODR = 0x02000000L ; // Set bit A25 ON -} - -void buzzerOff() -{ - PIOA->PIO_CODR = 0x02000000L ; // Set bit A25 ON -} -#endif - -void buzzerSound(uint8_t duration) -{ - buzzerOn(); - buzzerCount = duration; -} - -void buzzerHeartbeat() -{ - if (buzzerCount) { - if (--buzzerCount == 0) - buzzerOff(); - } -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +volatile uint8_t buzzerCount ; + +#if defined(REVA) +void buzzerOn() +{ + PIOA->PIO_SODR = 0x00010000L ; // Set bit A16 ON +} + +void buzzerOff() +{ + PIOA->PIO_CODR = 0x00010000L ; // Set bit A16 ON +} +#else +void buzzerOn() +{ + PIOA->PIO_SODR = 0x02000000L ; // Set bit A25 ON +} + +void buzzerOff() +{ + PIOA->PIO_CODR = 0x02000000L ; // Set bit A25 ON +} +#endif + +void buzzerSound(uint8_t duration) +{ + buzzerOn(); + buzzerCount = duration; +} + +void buzzerHeartbeat() +{ + if (buzzerCount) { + if (--buzzerCount == 0) + buzzerOff(); + } +} diff --git a/radio/src/targets/sky9x/chip.h b/radio/src/targets/sky9x/chip.h index 545c4bc6d..40e3f4c56 100644 --- a/radio/src/targets/sky9x/chip.h +++ b/radio/src/targets/sky9x/chip.h @@ -18,104 +18,104 @@ * GNU General Public License for more details. */ -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definition of AT91SAM3S4 characteristics and features -/// -/// !Usage -/// -# For ARM core feature, see "AT91SAM3S4 - ARM core features". -/// -# For IP features, see "AT91SAM3S4 - IP features". -/// -# For misc, see "AT91SAM3S4 - Misc". -//------------------------------------------------------------------------------ - +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Definition of AT91SAM3S4 characteristics and features +/// +/// !Usage +/// -# For ARM core feature, see "AT91SAM3S4 - ARM core features". +/// -# For IP features, see "AT91SAM3S4 - IP features". +/// -# For misc, see "AT91SAM3S4 - Misc". +//------------------------------------------------------------------------------ + #ifndef _CHIP_H_ #define _CHIP_H_ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - ARM core features" -/// This page lists several characteristics related to the ARM core -/// - -//ARM core features - -/// ARM core definition. -#define cortexm3 - -/// family definition. -#define at91sam3s - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - IP features" -/// This page lists several characteristics related to the embedded IP -/// - -//IP FEATURES - -// EFC GPNVM number -#define CHIP_EFC_NUM_GPNVMS 3 - -/// Indicates chip has an Enhanced EFC. -#define CHIP_FLASH_EEFC - -// DMA channels number -#define CHIP_DMA_CHANNEL_NUM 4 - -// Indicate chip's MCI interface. -#define MCI2_INTERFACE - -// Indicate chip SSC has DMA interface. -#define CHIP_SSC_DMA - -// Indicate chip SPI has DMA interface. -#define CHIP_SPI_DMA - -/// Indicates chip has an UDP Full Speed. -#define CHIP_USB_UDP - -/// Indicates chip has an internal pull-up. -#define CHIP_USB_PULLUP_INTERNAL - -/// Number of USB endpoints -#define CHIP_USB_NUMENDPOINTS 8 - -/// Endpoints max paxcket size -#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \ - ((i == 0) ? 64 : \ - ((i == 1) ? 64 : \ - ((i == 2) ? 64 : \ - ((i == 3) ? 64 : \ - ((i == 4) ? 512 : \ - ((i == 5) ? 512 : \ - ((i == 6) ? 64 : \ - ((i == 7) ? 64 : 0 )))))))) - -/// Endpoints Number of Bank -#define CHIP_USB_ENDPOINTS_BANKS(i) \ - ((i == 0) ? 1 : \ - ((i == 1) ? 2 : \ - ((i == 2) ? 2 : \ - ((i == 3) ? 1 : \ - ((i == 4) ? 2 : \ - ((i == 5) ? 2 : \ - ((i == 6) ? 2 : \ - ((i == 7) ? 2 : 0 )))))))) - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - Misc " -/// This page lists misc features -/// - -//Misc - + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "AT91SAM3S4 - ARM core features" +/// This page lists several characteristics related to the ARM core +/// + +//ARM core features + +/// ARM core definition. +#define cortexm3 + +/// family definition. +#define at91sam3s + +//------------------------------------------------------------------------------ +/// \page "AT91SAM3S4 - IP features" +/// This page lists several characteristics related to the embedded IP +/// + +//IP FEATURES + +// EFC GPNVM number +#define CHIP_EFC_NUM_GPNVMS 3 + +/// Indicates chip has an Enhanced EFC. +#define CHIP_FLASH_EEFC + +// DMA channels number +#define CHIP_DMA_CHANNEL_NUM 4 + +// Indicate chip's MCI interface. +#define MCI2_INTERFACE + +// Indicate chip SSC has DMA interface. +#define CHIP_SSC_DMA + +// Indicate chip SPI has DMA interface. +#define CHIP_SPI_DMA + +/// Indicates chip has an UDP Full Speed. +#define CHIP_USB_UDP + +/// Indicates chip has an internal pull-up. +#define CHIP_USB_PULLUP_INTERNAL + +/// Number of USB endpoints +#define CHIP_USB_NUMENDPOINTS 8 + +/// Endpoints max paxcket size +#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \ + ((i == 0) ? 64 : \ + ((i == 1) ? 64 : \ + ((i == 2) ? 64 : \ + ((i == 3) ? 64 : \ + ((i == 4) ? 512 : \ + ((i == 5) ? 512 : \ + ((i == 6) ? 64 : \ + ((i == 7) ? 64 : 0 )))))))) + +/// Endpoints Number of Bank +#define CHIP_USB_ENDPOINTS_BANKS(i) \ + ((i == 0) ? 1 : \ + ((i == 1) ? 2 : \ + ((i == 2) ? 2 : \ + ((i == 3) ? 1 : \ + ((i == 4) ? 2 : \ + ((i == 5) ? 2 : \ + ((i == 6) ? 2 : \ + ((i == 7) ? 2 : 0 )))))))) + +//------------------------------------------------------------------------------ +/// \page "AT91SAM3S4 - Misc " +/// This page lists misc features +/// + +//Misc + #endif // _CHIP_H_ - + diff --git a/radio/src/targets/sky9x/coproc_driver.cpp b/radio/src/targets/sky9x/coproc_driver.cpp index d94106cdc..cf5ab1be3 100644 --- a/radio/src/targets/sky9x/coproc_driver.cpp +++ b/radio/src/targets/sky9x/coproc_driver.cpp @@ -1,205 +1,205 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -int8_t volumeRequired ; -uint8_t coprocReadDataPending ; -uint8_t coprocWriteDataPending ; -uint8_t CoProc_appgo_pending ; -uint8_t Volume_read ; -uint8_t Coproc_read ; -int8_t Coproc_temp ; -int8_t Coproc_maxtemp=-127 ; -int8_t Coproc_valid ; -bool get_onlytemp; -#if !defined(SIMU) -// TODO not used? static uint8_t *Twi_read_address ; -#endif -static uint8_t TwiOperation ; - -#define TWI_NONE 0 -#define TWI_WRITE_VOL 2 -#define TWI_READ_COPROC 3 -#define TWI_COPROC_APPGO 4 -#define TWI_WAIT_STOP 5 -#define TWI_WRITE_COPROC 6 - -// Commands to the coprocessor bootloader/application -#define TWI_CMD_PAGEUPDATE 0x01 // TWI Command to program a flash page -#define TWI_CMD_EXECUTEAPP 0x02 // TWI Command to jump to the application program -#define TWI_CMD_SETREAD_ADDRESS 0x03 // TWI Command to set address to read from -#define TWI_CMD_WRITE_DATA 0x04 // TWI Command send data to the application -#define COPROC_RX_BUXSIZE 22 -uint8_t Co_proc_status[COPROC_RX_BUXSIZE] ; -uint8_t *coprocWriteDataPtr ; -uint32_t coprocWriteDataSize ; - - -// This is called from an interrupt routine, or -// interrupts must be disabled while it is called -// from elsewhere. -void i2cCheck() -{ - if ( TWI0->TWI_IMR & TWI_IMR_TXCOMP ) { - return ; // Busy - } - - if ( volumeRequired >= 0 ) { // Set volume to this value - TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing - TwiOperation = TWI_WRITE_VOL ; - TWI0->TWI_THR = volumeRequired ; // Send data - volumeRequired = -1 ; - TWI0->TWI_IER = TWI_IER_TXCOMP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - } - else if (coprocReadDataPending) { - Coproc_valid = 0 ; - coprocReadDataPending = 0 ; - TWI0->TWI_MMR = 0x00351000 ; // Device 35 and master is reading - TwiOperation = TWI_READ_COPROC ; -#ifndef SIMU - TWI0->TWI_RPR = (uint32_t)&Co_proc_status[0] ; -#endif - TWI0->TWI_RCR = COPROC_RX_BUXSIZE - 1 ; - if ( TWI0->TWI_SR & TWI_SR_RXRDY ) { - (void) TWI0->TWI_RHR ; - } - TWI0->TWI_PTCR = TWI_PTCR_RXTEN ; // Start transfers - TWI0->TWI_CR = TWI_CR_START ; // Start Rx - TWI0->TWI_IER = TWI_IER_RXBUFF | TWI_IER_TXCOMP ; - } - else if ( CoProc_appgo_pending ) { - CoProc_appgo_pending = 0 ; - TWI0->TWI_MMR = 0x00350000 ; // Device 35 and master is writing - TwiOperation = TWI_COPROC_APPGO ; - TWI0->TWI_THR = TWI_CMD_EXECUTEAPP ; // Send appgo command - TWI0->TWI_IER = TWI_IER_TXCOMP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - } - else if ( coprocWriteDataPending ) { - coprocWriteDataPending = 0 ; - TWI0->TWI_MMR = 0x00350000 ; // Device 35 and master is writing - TwiOperation = TWI_WRITE_COPROC ; -#ifndef SIMU - TWI0->TWI_TPR = (uint32_t)coprocWriteDataPtr ; -#endif - TWI0->TWI_TCR = coprocWriteDataSize ; - TWI0->TWI_THR = TWI_CMD_WRITE_DATA ; // Send write command - TWI0->TWI_PTCR = TWI_PTCR_TXTEN ; // Start data transfer - TWI0->TWI_IER = TWI_IER_TXBUFE | TWI_IER_TXCOMP ; - } -} - -void coprocReadData(bool onlytemp) -{ - get_onlytemp = onlytemp; - coprocReadDataPending = 1 ; - __disable_irq() ; - i2cCheck() ; - __enable_irq() ; -} - -void coprocWriteData(uint8_t *data, uint32_t size) -{ - coprocWriteDataPtr = data; - coprocWriteDataSize = size; - coprocWriteDataPending = 1; - __disable_irq(); - i2cCheck(); - __enable_irq(); -} - -#if !defined(SIMU) -extern "C" void TWI0_IRQHandler() -{ - if ( TwiOperation == TWI_READ_COPROC ) - { - if ( TWI0->TWI_SR & TWI_SR_RXBUFF ) - { - TWI0->TWI_IDR = TWI_IDR_RXBUFF ; - TwiOperation = TWI_WAIT_STOP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Rx - TWI0->TWI_RCR = 1 ; // Last byte - return ; - } - else - { - Coproc_valid = -1 ; - } - } - - if ( TwiOperation == TWI_WAIT_STOP ) - { - Coproc_valid = 1 ; - Coproc_read = Co_proc_status[0] ; - if ( Coproc_read & 0x80 ) { - // Bootloader - CoProc_appgo_pending = 1 ; // Action application - } - else { - // Got data from tiny app - // Set the date and time - struct gtm utm; - if (!get_onlytemp) { - utm.tm_sec = Co_proc_status[1] ; - utm.tm_min = Co_proc_status[2] ; - utm.tm_hour = Co_proc_status[3] ; - utm.tm_mday = Co_proc_status[4] ; - utm.tm_mon = Co_proc_status[5] - 1; - utm.tm_year = (Co_proc_status[6] + ( Co_proc_status[7] << 8 )) - TM_YEAR_BASE; - g_rtcTime = gmktime(&utm); - } - Coproc_temp = Co_proc_status[8]; - if (Coproc_temp > Coproc_maxtemp) - Coproc_maxtemp=Coproc_temp; - } - TWI0->TWI_PTCR = TWI_PTCR_RXTDIS ; // Stop transfers - if ( TWI0->TWI_SR & TWI_SR_RXRDY ) { - (void) TWI0->TWI_RHR ; // Discard any rubbish data - } - } - -// if ( TwiOperation == TWI_WRITE_VOL ) -// { - -// } - - if ( TwiOperation == TWI_WRITE_COPROC ) - { - if ( TWI0->TWI_SR & TWI_SR_TXBUFE ) - { - TWI0->TWI_IDR = TWI_IDR_TXBUFE ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - TWI0->TWI_PTCR = TWI_PTCR_TXTDIS ; // Stop transfers - TwiOperation = TWI_NONE ; - return ; - } - } - - TWI0->TWI_IDR = TWI_IDR_TXCOMP | TWI_IDR_TXBUFE | TWI_IDR_RXBUFF ; - TWI0->TWI_PTCR = TWI_PTCR_TXTDIS | TWI_PTCR_RXTDIS ; // Stop transfers - if ( TWI0->TWI_SR & TWI_SR_NACK ) - { - } - TwiOperation = TWI_NONE ; - i2cCheck() ; -} -#endif +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +int8_t volumeRequired ; +uint8_t coprocReadDataPending ; +uint8_t coprocWriteDataPending ; +uint8_t CoProc_appgo_pending ; +uint8_t Volume_read ; +uint8_t Coproc_read ; +int8_t Coproc_temp ; +int8_t Coproc_maxtemp=-127 ; +int8_t Coproc_valid ; +bool get_onlytemp; +#if !defined(SIMU) +// TODO not used? static uint8_t *Twi_read_address ; +#endif +static uint8_t TwiOperation ; + +#define TWI_NONE 0 +#define TWI_WRITE_VOL 2 +#define TWI_READ_COPROC 3 +#define TWI_COPROC_APPGO 4 +#define TWI_WAIT_STOP 5 +#define TWI_WRITE_COPROC 6 + +// Commands to the coprocessor bootloader/application +#define TWI_CMD_PAGEUPDATE 0x01 // TWI Command to program a flash page +#define TWI_CMD_EXECUTEAPP 0x02 // TWI Command to jump to the application program +#define TWI_CMD_SETREAD_ADDRESS 0x03 // TWI Command to set address to read from +#define TWI_CMD_WRITE_DATA 0x04 // TWI Command send data to the application +#define COPROC_RX_BUXSIZE 22 +uint8_t Co_proc_status[COPROC_RX_BUXSIZE] ; +uint8_t *coprocWriteDataPtr ; +uint32_t coprocWriteDataSize ; + + +// This is called from an interrupt routine, or +// interrupts must be disabled while it is called +// from elsewhere. +void i2cCheck() +{ + if ( TWI0->TWI_IMR & TWI_IMR_TXCOMP ) { + return ; // Busy + } + + if ( volumeRequired >= 0 ) { // Set volume to this value + TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing + TwiOperation = TWI_WRITE_VOL ; + TWI0->TWI_THR = volumeRequired ; // Send data + volumeRequired = -1 ; + TWI0->TWI_IER = TWI_IER_TXCOMP ; + TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx + } + else if (coprocReadDataPending) { + Coproc_valid = 0 ; + coprocReadDataPending = 0 ; + TWI0->TWI_MMR = 0x00351000 ; // Device 35 and master is reading + TwiOperation = TWI_READ_COPROC ; +#ifndef SIMU + TWI0->TWI_RPR = (uint32_t)&Co_proc_status[0] ; +#endif + TWI0->TWI_RCR = COPROC_RX_BUXSIZE - 1 ; + if ( TWI0->TWI_SR & TWI_SR_RXRDY ) { + (void) TWI0->TWI_RHR ; + } + TWI0->TWI_PTCR = TWI_PTCR_RXTEN ; // Start transfers + TWI0->TWI_CR = TWI_CR_START ; // Start Rx + TWI0->TWI_IER = TWI_IER_RXBUFF | TWI_IER_TXCOMP ; + } + else if ( CoProc_appgo_pending ) { + CoProc_appgo_pending = 0 ; + TWI0->TWI_MMR = 0x00350000 ; // Device 35 and master is writing + TwiOperation = TWI_COPROC_APPGO ; + TWI0->TWI_THR = TWI_CMD_EXECUTEAPP ; // Send appgo command + TWI0->TWI_IER = TWI_IER_TXCOMP ; + TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx + } + else if ( coprocWriteDataPending ) { + coprocWriteDataPending = 0 ; + TWI0->TWI_MMR = 0x00350000 ; // Device 35 and master is writing + TwiOperation = TWI_WRITE_COPROC ; +#ifndef SIMU + TWI0->TWI_TPR = (uint32_t)coprocWriteDataPtr ; +#endif + TWI0->TWI_TCR = coprocWriteDataSize ; + TWI0->TWI_THR = TWI_CMD_WRITE_DATA ; // Send write command + TWI0->TWI_PTCR = TWI_PTCR_TXTEN ; // Start data transfer + TWI0->TWI_IER = TWI_IER_TXBUFE | TWI_IER_TXCOMP ; + } +} + +void coprocReadData(bool onlytemp) +{ + get_onlytemp = onlytemp; + coprocReadDataPending = 1 ; + __disable_irq() ; + i2cCheck() ; + __enable_irq() ; +} + +void coprocWriteData(uint8_t *data, uint32_t size) +{ + coprocWriteDataPtr = data; + coprocWriteDataSize = size; + coprocWriteDataPending = 1; + __disable_irq(); + i2cCheck(); + __enable_irq(); +} + +#if !defined(SIMU) +extern "C" void TWI0_IRQHandler() +{ + if ( TwiOperation == TWI_READ_COPROC ) + { + if ( TWI0->TWI_SR & TWI_SR_RXBUFF ) + { + TWI0->TWI_IDR = TWI_IDR_RXBUFF ; + TwiOperation = TWI_WAIT_STOP ; + TWI0->TWI_CR = TWI_CR_STOP ; // Stop Rx + TWI0->TWI_RCR = 1 ; // Last byte + return ; + } + else + { + Coproc_valid = -1 ; + } + } + + if ( TwiOperation == TWI_WAIT_STOP ) + { + Coproc_valid = 1 ; + Coproc_read = Co_proc_status[0] ; + if ( Coproc_read & 0x80 ) { + // Bootloader + CoProc_appgo_pending = 1 ; // Action application + } + else { + // Got data from tiny app + // Set the date and time + struct gtm utm; + if (!get_onlytemp) { + utm.tm_sec = Co_proc_status[1] ; + utm.tm_min = Co_proc_status[2] ; + utm.tm_hour = Co_proc_status[3] ; + utm.tm_mday = Co_proc_status[4] ; + utm.tm_mon = Co_proc_status[5] - 1; + utm.tm_year = (Co_proc_status[6] + ( Co_proc_status[7] << 8 )) - TM_YEAR_BASE; + g_rtcTime = gmktime(&utm); + } + Coproc_temp = Co_proc_status[8]; + if (Coproc_temp > Coproc_maxtemp) + Coproc_maxtemp=Coproc_temp; + } + TWI0->TWI_PTCR = TWI_PTCR_RXTDIS ; // Stop transfers + if ( TWI0->TWI_SR & TWI_SR_RXRDY ) { + (void) TWI0->TWI_RHR ; // Discard any rubbish data + } + } + +// if ( TwiOperation == TWI_WRITE_VOL ) +// { + +// } + + if ( TwiOperation == TWI_WRITE_COPROC ) + { + if ( TWI0->TWI_SR & TWI_SR_TXBUFE ) + { + TWI0->TWI_IDR = TWI_IDR_TXBUFE ; + TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx + TWI0->TWI_PTCR = TWI_PTCR_TXTDIS ; // Stop transfers + TwiOperation = TWI_NONE ; + return ; + } + } + + TWI0->TWI_IDR = TWI_IDR_TXCOMP | TWI_IDR_TXBUFE | TWI_IDR_RXBUFF ; + TWI0->TWI_PTCR = TWI_PTCR_TXTDIS | TWI_PTCR_RXTDIS ; // Stop transfers + if ( TWI0->TWI_SR & TWI_SR_NACK ) + { + } + TwiOperation = TWI_NONE ; + i2cCheck() ; +} +#endif diff --git a/radio/src/targets/sky9x/core_cm3.c b/radio/src/targets/sky9x/core_cm3.c index ea46ebb6d..0137855da 100644 --- a/radio/src/targets/sky9x/core_cm3.c +++ b/radio/src/targets/sky9x/core_cm3.c @@ -18,851 +18,851 @@ * GNU General Public License for more details. */ -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -uint32_t __get_PSP(void) ; -void __set_PSP(uint32_t topOfProcStack) ; -uint32_t __get_MSP(void) ; -void __set_MSP(uint32_t mainStackPointer) ; -uint32_t __REV16(uint16_t value) ; -int32_t __REVSH(int16_t value) ; -uint32_t __RBIT(uint32_t value) ; -uint8_t __LDREXB(uint8_t *addr) ; -uint16_t __LDREXH(uint16_t *addr) ; -uint32_t __LDREXW(uint32_t *addr) ; -uint32_t __STREXB(uint8_t value, uint8_t *addr) ; -uint32_t __STREXH(uint16_t value, uint16_t *addr) ; -uint32_t __STREXW(uint32_t value, uint32_t *addr) ; - -uint32_t __get_BASEPRI(void) ; -void __set_BASEPRI(uint32_t basePri) ; -uint32_t __get_PRIMASK(void) ; -void __set_PRIMASK(uint32_t priMask) ; -uint32_t __get_FAULTMASK(void) ; -void __set_FAULTMASK(uint32_t faultMask) ; -uint32_t __get_CONTROL(void) ; -void __set_CONTROL(uint32_t control) ; -uint32_t __REV(uint32_t value) ; - -void revert_osc( void ) ; -void sam_boot( void ) ; -void sam_bootx( void ) ; -void run_application( void ) ; - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -#if !defined(BOOT) -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -/*extern uint32_t __get_PSP(void) __attribute__( ( naked ) ); */ -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -/*void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -/*uint32_t __get_MSP(void) __attribute__( ( naked ) ); */ -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -/*void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} -#endif - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#if !defined(BOOT) -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} -#endif - -#if defined(BOOT) -void run_application() -{ - __ASM(" mov.w r1, #4227072"); // 0x408000 - __ASM(" movw r0, #60680"); // 0xED08 - __ASM(" movt r0, #57344"); // 0xE000 - __ASM(" str r1, [r0, #0]"); // Set the VTOR - __ASM("ldr r0, [r1, #0]"); // Stack pointer value - __ASM("msr msp, r0"); // Set it - __ASM("ldr r0, [r1, #4]"); // Reset address - __ASM("mov.w r1, #1"); - __ASM("orr r0, r1"); // Set lsbit - __ASM("bx r0"); // Execute application -} -#endif - -#if !defined(BOOT) -void sam_boot() -{ - revert_osc() ; - - __ASM(" mov.w r1, #8388608"); - __ASM(" movw r0, #60680"); - __ASM(" movt r0, #57344"); - __ASM(" str r1, [r0, #0]"); // Set the VTOR - - __ASM("mov.w r3, #0"); - __ASM("movt r3, #128"); - __ASM("ldr r0, [r3, #0]"); - __ASM("msr msp, r0"); - __ASM("ldr r0, [r3, #4]"); - __ASM("mov.w r3, #1"); - __ASM("orr r0, r3"); - __ASM("bx r0"); -} -#endif - -#if defined(BOOT) -void sam_bootx() -{ - __ASM(" mov.w r1, #8388608"); - __ASM(" movw r0, #60680"); - __ASM(" movt r0, #57344"); - __ASM(" str r1, [r0, #0]"); // Set the VTOR - - __ASM("mov.w r3, #0"); - __ASM("movt r3, #128"); - __ASM("ldr r0, [r3, #0]"); - __ASM("msr msp, r0"); - __ASM("ldr r0, [r3, #4]"); - __ASM("mov.w r3, #1"); - __ASM("orr r0, r3"); - __ASM("bx r0"); -} -#endif - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +uint32_t __get_PSP(void) ; +void __set_PSP(uint32_t topOfProcStack) ; +uint32_t __get_MSP(void) ; +void __set_MSP(uint32_t mainStackPointer) ; +uint32_t __REV16(uint16_t value) ; +int32_t __REVSH(int16_t value) ; +uint32_t __RBIT(uint32_t value) ; +uint8_t __LDREXB(uint8_t *addr) ; +uint16_t __LDREXH(uint16_t *addr) ; +uint32_t __LDREXW(uint32_t *addr) ; +uint32_t __STREXB(uint8_t value, uint8_t *addr) ; +uint32_t __STREXH(uint16_t value, uint16_t *addr) ; +uint32_t __STREXW(uint32_t value, uint32_t *addr) ; + +uint32_t __get_BASEPRI(void) ; +void __set_BASEPRI(uint32_t basePri) ; +uint32_t __get_PRIMASK(void) ; +void __set_PRIMASK(uint32_t priMask) ; +uint32_t __get_FAULTMASK(void) ; +void __set_FAULTMASK(uint32_t faultMask) ; +uint32_t __get_CONTROL(void) ; +void __set_CONTROL(uint32_t control) ; +uint32_t __REV(uint32_t value) ; + +void revert_osc( void ) ; +void sam_boot( void ) ; +void sam_bootx( void ) ; +void run_application( void ) ; + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +#if !defined(BOOT) +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +/*extern uint32_t __get_PSP(void) __attribute__( ( naked ) ); */ +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +/*void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +/*uint32_t __get_MSP(void) __attribute__( ( naked ) ); */ +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +/*void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} +#endif + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#if !defined(BOOT) +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} +#endif + +#if defined(BOOT) +void run_application() +{ + __ASM(" mov.w r1, #4227072"); // 0x408000 + __ASM(" movw r0, #60680"); // 0xED08 + __ASM(" movt r0, #57344"); // 0xE000 + __ASM(" str r1, [r0, #0]"); // Set the VTOR + __ASM("ldr r0, [r1, #0]"); // Stack pointer value + __ASM("msr msp, r0"); // Set it + __ASM("ldr r0, [r1, #4]"); // Reset address + __ASM("mov.w r1, #1"); + __ASM("orr r0, r1"); // Set lsbit + __ASM("bx r0"); // Execute application +} +#endif + +#if !defined(BOOT) +void sam_boot() +{ + revert_osc() ; + + __ASM(" mov.w r1, #8388608"); + __ASM(" movw r0, #60680"); + __ASM(" movt r0, #57344"); + __ASM(" str r1, [r0, #0]"); // Set the VTOR + + __ASM("mov.w r3, #0"); + __ASM("movt r3, #128"); + __ASM("ldr r0, [r3, #0]"); + __ASM("msr msp, r0"); + __ASM("ldr r0, [r3, #4]"); + __ASM("mov.w r3, #1"); + __ASM("orr r0, r3"); + __ASM("bx r0"); +} +#endif + +#if defined(BOOT) +void sam_bootx() +{ + __ASM(" mov.w r1, #8388608"); + __ASM(" movw r0, #60680"); + __ASM(" movt r0, #57344"); + __ASM(" str r1, [r0, #0]"); // Set the VTOR + + __ASM("mov.w r3, #0"); + __ASM("movt r3, #128"); + __ASM("ldr r0, [r3, #0]"); + __ASM("msr msp, r0"); + __ASM("ldr r0, [r3, #4]"); + __ASM("mov.w r3, #1"); + __ASM("orr r0, r3"); + __ASM("bx r0"); +} +#endif + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/radio/src/targets/sky9x/core_cm3.h b/radio/src/targets/sky9x/core_cm3.h index 557e36514..e529c63a4 100644 --- a/radio/src/targets/sky9x/core_cm3.h +++ b/radio/src/targets/sky9x/core_cm3.h @@ -20,1796 +20,1796 @@ #ifndef _CORE_CM3_H_ #define _CORE_CM3_H_ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - Error 10: \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' - * . - * - Error 530: \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized - * . - * - Error 550: \n - * __regBasePri = (basePri & 0x1ff); \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed - * . - * - Error 754: \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced - * . - * - Error 750: \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced - * . - * - Error 528: \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced - * . - * - Error 751: \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1ul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq( void ) { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq( void ) { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI( void ) { __ASM ("wfi"); } -static __INLINE void __WFE( void ) { __ASM ("wfe"); } -static __INLINE void __SEV( void ) { __ASM ("sev"); } -static __INLINE void __CLREX( void ) { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP(void) { __ASM volatile ("nop"); } -static __INLINE void __WFI(void) { __ASM volatile ("wfi"); } -static __INLINE void __WFE(void) { __ASM volatile ("wfe"); } -static __INLINE void __SEV(void) { __ASM volatile ("sev"); } -static __INLINE void __ISB(void) { __ASM volatile ("isb"); } -static __INLINE void __DSB(void) { __ASM volatile ("dsb"); } -static __INLINE void __DMB(void) { __ASM volatile ("dmb"); } -static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1ul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq( void ) { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq( void ) { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI( void ) { __ASM ("wfi"); } +static __INLINE void __WFE( void ) { __ASM ("wfe"); } +static __INLINE void __SEV( void ) { __ASM ("sev"); } +static __INLINE void __CLREX( void ) { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP(void) { __ASM volatile ("nop"); } +static __INLINE void __WFI(void) { __ASM volatile ("wfi"); } +static __INLINE void __WFE(void) { __ASM volatile ("wfe"); } +static __INLINE void __SEV(void) { __ASM volatile ("sev"); } +static __INLINE void __ISB(void) { __ASM volatile ("isb"); } +static __INLINE void __DSB(void) { __ASM volatile ("dsb"); } +static __INLINE void __DMB(void) { __ASM volatile ("dmb"); } +static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + #endif // _CORE_CM3_H_ - -/*lint -restore */ + +/*lint -restore */ diff --git a/radio/src/targets/sky9x/crt.c b/radio/src/targets/sky9x/crt.c index a9e8640a1..48784b6e3 100644 --- a/radio/src/targets/sky9x/crt.c +++ b/radio/src/targets/sky9x/crt.c @@ -1,131 +1,131 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __CRT_C__ - -#include - -/*=========================================================================*/ -/* DEFINE: All extern Data */ -/*=========================================================================*/ -/* - * The next data are defined by the linker script. - */ -extern unsigned long _stext; -extern unsigned long _etext; -extern unsigned long _sdata; -extern unsigned long _edata; -extern unsigned long _sbss; -extern unsigned long _ebss; -extern unsigned long _estack; - -/* This is the main */ -extern int main (void); - -/*=========================================================================*/ -/* DEFINE: Prototypes */ -/*=========================================================================*/ -extern uint32_t SystemInit (void) ; // __attribute__((weak)); - -/*=========================================================================*/ -/* DEFINE: All code exported */ -/*=========================================================================*/ - -/***************************************************************************/ -/* SystemInit */ -/* */ -/* SystemInit is a function which is provided by the CMSIS interface. */ -/* If this function is not available, we need a function here to prevent */ -/* an error of the linker. Therefore this function is declared as weak. */ -/***************************************************************************/ -//uint32_t SystemInit (void) -//{ - -//} /* SystemInit */ - -extern uint32_t Master_frequency ; - -/***************************************************************************/ -/* ResetHandler */ -/* */ -/* This function is used for the C runtime initialisation, */ -/* for handling the .data and .bss segments. */ -/***************************************************************************/ -void ResetHandler (void) -{ - { - uint32_t *pSrc; - uint32_t *pDest; - uint32_t m_freq ; - - /* - * Call the SystemInit code from CMSIS interface if available. - * SystemInit is a week function which can be override - * by an external function. - */ - m_freq = SystemInit(); - - /* - * Set the "Vector Table Offset Register". From the ARM - * documentation, we got the following information: - * - * Use the Vector Table Offset Register to determine: - * - if the vector table is in RAM or code memory - * - the vector table offset. - */ - *((uint32_t*)0xE000ED08) = (uint32_t)&_stext; - - /* - * Copy the initialized data of the ".data" segment - * from the flash to the are in the ram. - */ - pSrc = &_etext; - pDest = &_sdata; - while(pDest < &_edata) - { - *pDest++ = *pSrc++; - } - - /* - * Clear the ".bss" segment. - */ - pDest = &_sbss; - while(pDest < &_ebss) - { - *pDest++ = 0; - } - Master_frequency = m_freq ; - } - - /* - * And now the main function can be called. - * Scotty, energie... - */ - main(); - - /* - * In case there are problems with the - * "warp drive", stop here. - */ - while(1) {}; - -} /* ResetHandler */ - -/*** EOF ***/ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __CRT_C__ + +#include + +/*=========================================================================*/ +/* DEFINE: All extern Data */ +/*=========================================================================*/ +/* + * The next data are defined by the linker script. + */ +extern unsigned long _stext; +extern unsigned long _etext; +extern unsigned long _sdata; +extern unsigned long _edata; +extern unsigned long _sbss; +extern unsigned long _ebss; +extern unsigned long _estack; + +/* This is the main */ +extern int main (void); + +/*=========================================================================*/ +/* DEFINE: Prototypes */ +/*=========================================================================*/ +extern uint32_t SystemInit (void) ; // __attribute__((weak)); + +/*=========================================================================*/ +/* DEFINE: All code exported */ +/*=========================================================================*/ + +/***************************************************************************/ +/* SystemInit */ +/* */ +/* SystemInit is a function which is provided by the CMSIS interface. */ +/* If this function is not available, we need a function here to prevent */ +/* an error of the linker. Therefore this function is declared as weak. */ +/***************************************************************************/ +//uint32_t SystemInit (void) +//{ + +//} /* SystemInit */ + +extern uint32_t Master_frequency ; + +/***************************************************************************/ +/* ResetHandler */ +/* */ +/* This function is used for the C runtime initialisation, */ +/* for handling the .data and .bss segments. */ +/***************************************************************************/ +void ResetHandler (void) +{ + { + uint32_t *pSrc; + uint32_t *pDest; + uint32_t m_freq ; + + /* + * Call the SystemInit code from CMSIS interface if available. + * SystemInit is a week function which can be override + * by an external function. + */ + m_freq = SystemInit(); + + /* + * Set the "Vector Table Offset Register". From the ARM + * documentation, we got the following information: + * + * Use the Vector Table Offset Register to determine: + * - if the vector table is in RAM or code memory + * - the vector table offset. + */ + *((uint32_t*)0xE000ED08) = (uint32_t)&_stext; + + /* + * Copy the initialized data of the ".data" segment + * from the flash to the are in the ram. + */ + pSrc = &_etext; + pDest = &_sdata; + while(pDest < &_edata) + { + *pDest++ = *pSrc++; + } + + /* + * Clear the ".bss" segment. + */ + pDest = &_sbss; + while(pDest < &_ebss) + { + *pDest++ = 0; + } + Master_frequency = m_freq ; + } + + /* + * And now the main function can be called. + * Scotty, energie... + */ + main(); + + /* + * In case there are problems with the + * "warp drive", stop here. + */ + while(1) {}; + +} /* ResetHandler */ + +/*** EOF ***/ diff --git a/radio/src/targets/sky9x/diskio.cpp b/radio/src/targets/sky9x/diskio.cpp index 25dc41ee0..161d90adc 100644 --- a/radio/src/targets/sky9x/diskio.cpp +++ b/radio/src/targets/sky9x/diskio.cpp @@ -1,1380 +1,1380 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/*-----------------------------------------------------------------------*/ -/* MMCv3/SDv1/SDv2 (in SPI mode) control module (C)ChaN, 2010 */ -/*-----------------------------------------------------------------------*/ -/* Only rcvr_spi(), xmit_spi(), sdPoll10ms() and some macros */ -/* are platform dependent. */ -/*-----------------------------------------------------------------------*/ - -#include "opentx.h" -#include "diskio.h" - -#define CARD_TYPE_bmHC (1 << 0) /**< Bit for High-Capacity(Density) */ -#define CARD_TYPE_bmSDMMC (0x3 << 1) /**< Bits mask for SD/MMC */ -#define CARD_TYPE_bmUNKNOWN (0x0 << 1) /**< Bits for Unknown card */ -#define CARD_TYPE_bmSD (0x1 << 1) /**< Bits for SD */ -#define CARD_TYPE_bmMMC (0x2 << 1) /**< Bits for MMC */ -#define CARD_TYPE_bmSDIO (1 << 3) /**< Bit for SDIO */ -/** Card can not be identified */ -#define CARD_UNKNOWN (0) -/** SD Card (0x2) */ -#define CARD_SD (CARD_TYPE_bmSD) -/** SD High Capacity Card (0x3) */ -#define CARD_SDHC (CARD_TYPE_bmSD|CARD_TYPE_bmHC) -/** MMC Card (0x4) */ -#define CARD_MMC (CARD_TYPE_bmMMC) -/** MMC High-Density Card (0x5) */ -#define CARD_MMCHD (CARD_TYPE_bmMMC|CARD_TYPE_bmHC) -/** SDIO only card (0x8) */ -#define CARD_SDIO (CARD_TYPE_bmSDIO) -/** SDIO Combo, with SD embedded (0xA) */ -#define CARD_SDCOMBO (CARD_TYPE_bmSDIO|CARD_SD) -/** SDIO Combo, with SDHC embedded (0xB) */ -#define CARD_SDHCCOMBO (CARD_TYPE_bmSDIO|CARD_SDHC) - -#define STATUS_READY_FOR_DATA (1UL << 8) -#define STATUS_TRAN (4UL << 9) -#define STATUS_STATE (0xFUL << 9) - -/** Bit mask for data errors */ -#define STATUS_ERRORS_DATA ((uint32_t)(HSMCI_SR_UNRE \ - | HSMCI_SR_OVRE \ - /*| HSMCI_SR_BLKOVRE*/ \ - /*| HSMCI_SR_CSTOE*/ \ - | HSMCI_SR_DTOE \ - | HSMCI_SR_DCRCE)) - - -uint32_t Card_ID[4] ; -uint32_t Card_SCR[2] ; -uint32_t Card_CSD[4] ; -int32_t Card_state = SD_ST_STARTUP ; -volatile uint32_t Card_initialized = 0; -uint32_t Sd_rca ; -uint32_t Cmd_A41_resp ; -uint8_t cardType; -uint32_t transSpeed; - -/*-----------------------------------------------------------------------*/ -/* Lock / unlock functions */ -/*-----------------------------------------------------------------------*/ - -#if !defined(BOOT) -static OS_MutexID ioMutex; -volatile int mutexCheck = 0; -int ff_cre_syncobj (BYTE vol, _SYNC_t *mutex) -{ - *mutex = ioMutex; - return 1; -} - -int ff_req_grant (_SYNC_t mutex) -{ - CoEnterMutexSection(mutex); - return 1; -} - -void ff_rel_grant (_SYNC_t mutex) -{ - CoLeaveMutexSection(mutex); -} - -int ff_del_syncobj (_SYNC_t mutex) -{ - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Get Trans Speed Value (Kbit/s) -/// \param tranSpeed The TRAN_SPEED value from SD(IO)/MMC enum information. -/// \param unitList Transfer rate units (Kbit/s), 4 units listed. -/// \param nbUnits Transfer rate units list size. -/// \param codeList Time value codes list, 16 codes listed. -//------------------------------------------------------------------------------ -static unsigned int MmcGetTranSpeed(unsigned int tranSpeed, - const unsigned int* unitList, unsigned int nbUnits, - const unsigned int* codeList) -{ - unsigned int unit, value; - unit = tranSpeed & 0x7; - if (unit < nbUnits) unit = unitList[unit]; - else return 0; - value = (tranSpeed >> 3) & 0xF; - if (value < 16) value = codeList[value]; - else return 0; - return (unit * value); -} - -//------------------------------------------------------------------------------ -/// Get Trans Speed Value -/// \param pSd -//------------------------------------------------------------------------------ -uint32_t GetTransSpeedValue() -{ - // CSD register, TRANS_SPEED bit - const unsigned int units[4] = {10, 100, 1000, 10000 }; // *Kbit/s -/* const unsigned int values_emmc[16] = {0, 10, 12, 13, 15, 20, - 26, 30, 35, 40, 45, 52, - 55, 60, 70, 80}; */ - const unsigned int values_sdmmc[16] = {0, 10, 12, 13, 15, 20, - 25, 30, 35, 40, 45, 50, - 55, 60, 70, 80}; - #if 0 - unsigned int unit, value; - unit = (SD_CSD_TRAN_SPEED(pSd) & 0x7); - if(unit < 4) unit = units[unit]; - else return; - value = (SD_CSD_TRAN_SPEED(pSd) >> 3) & 0xF; - if (value < 16) { - if (pSd->cardType >= CARD_MMC && SD_CID_BGA(pSd) == 1) { - value = values_emmc[value]; - } - else - value = values_sdmmc[value]; - } - else return; - pSd->transSpeed = (unit * value); - #else - transSpeed = MmcGetTranSpeed(SD_CSD_TRAN_SPEED(Card_CSD), - units, 4, - values_sdmmc); - #endif - /*if (pSd->cardType >= CARD_MMC && SD_EXTCSD_HS_TIMING(pSd)) { - pSd->transSpeed *= 2; - }*/ - TRACE_ERROR("-I- SD/MMC TRANS SPEED %d KBit/s\r\n", transSpeed); - transSpeed *= 1000; - return transSpeed; -} - -/** - * Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is - * MCK/2 and corresponds to CLKDIV = 0 - * \param mciSpeed MCI clock speed in Hz, 0 will not change current speed. - * \return The actual speed used, 0 for fail. - */ -uint32_t sdSetSpeed(uint32_t mciSpeed ) -{ - uint32_t mciMr; - uint32_t clkdiv, divLimit; - - mciMr = HSMCI->HSMCI_MR & (~(uint32_t)HSMCI_MR_CLKDIV_Msk); - /* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) - * divided by (2*(CLKDIV+1)) - * mciSpeed = MCK / (2*(CLKDIV+1)) */ - if (mciSpeed > 0) { - -#if 1 - divLimit = (Master_frequency / 2 / mciSpeed); - if ((Master_frequency / 2) % mciSpeed) divLimit ++; - - clkdiv = (Master_frequency / 2 / mciSpeed); - if (mciSpeed && clkdiv < divLimit) - clkdiv = divLimit; - if (clkdiv > 0) - clkdiv -= 1; -#else - clkdiv = (Master_frequency / 2 / mciSpeed); - /* Speed should not bigger than expired one */ - if (mciSpeed < Master_frequency / 2 / clkdiv) { - clkdiv++; - } - if (clkdiv > 0) { - clkdiv -= 1; - } -#endif - } - else { - clkdiv = 0; - } - - /* Actual MCI speed */ - mciSpeed = Master_frequency / 2 / (clkdiv + 1); - /* Modify MR */ - HSMCI->HSMCI_MR = mciMr | clkdiv; - - return mciSpeed; -} - -#if 0 -void SD_SetBlklen( uint32_t blklen ) -{ - uint32_t mciMr; - uint32_t clkdiv; - - mciMr = HSMCI->HSMCI_MR & (~(uint32_t)HSMCI_MR_BLKLEN); - /* Modify MR */ - HSMCI->HSMCI_MR = mciMr | blklen << 16 ; -} -#endif - -#if 0 -/** - * Reset MCI HW interface and disable it. - * \param keepSettings Keep old register settings, including - * _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG. - */ -void SD_Reset( uint8_t keepSettings) -{ - Hsmci *pMciHw = HSMCI ; - - if (keepSettings) - { - uint32_t mr, sdcr, dtor, cstor; - uint32_t cfg; - mr = pMciHw->HSMCI_MR; - sdcr = pMciHw->HSMCI_SDCR; - dtor = pMciHw->HSMCI_DTOR; - cstor = pMciHw->HSMCI_CSTOR; - cfg = pMciHw->HSMCI_CFG; - pMciHw->HSMCI_CR = HSMCI_CR_SWRST ; // Reset - pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS; // Disable - pMciHw->HSMCI_MR = mr; - pMciHw->HSMCI_SDCR = sdcr; - pMciHw->HSMCI_DTOR = dtor; - pMciHw->HSMCI_CSTOR = cstor; - pMciHw->HSMCI_CFG = cfg; - } - else - { - pMciHw->HSMCI_CR = HSMCI_CR_SWRST ; // Reset - pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS; // Disable - } -} -#endif - -const char SD_NORESPONSE[] = "No response"; - -const char * sdCommand(uint32_t cmd, uint32_t arg) -{ - uint32_t i; - Hsmci *phsmci = HSMCI; - - if (SD_CARD_PRESENT()) { - phsmci->HSMCI_ARGR = arg; - phsmci->HSMCI_CMDR = cmd; - - for (i = 0; i < 50000; i += 1) { - if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) { - return 0; - } - } - return SD_NORESPONSE; - } - else { - return "No Sdcard"; - } -} - -#define SDMMC_POWER_ON_INIT (0 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_INIT \ - | HSMCI_CMDR_OPDCMD ) - -const char * sdPowerOn() -{ - return sdCommand(SDMMC_POWER_ON_INIT, 0); -} - -#define SDMMC_GO_IDLE_STATE (0 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD ) - -const char * sdCmd0() -{ - return sdCommand(SDMMC_GO_IDLE_STATE, 0); -} - -#if 0 -#define SDIO_SEND_OP_COND (5 | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_OPDCMD ) - -const char * sdCmd5(uint32_t *pIo) -{ - const char * result = sdCommand(SDIO_SEND_OP_COND, *pIo); - if (result) - return result; - *pIo = HSMCI->HSMCI_RSPR[0]; - return 0; -} -#endif - -#define SD_SEND_IF_COND (8 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_OPDCMD /* BSS difference */ \ - | HSMCI_CMDR_MAXLAT ) - -const char * sdCmd8(uint8_t supplyVoltage) -{ - return sdCommand(SD_SEND_IF_COND, (supplyVoltage << 8) | (0xAA)); -} - -#define SDMMC_APP_CMD (55| HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_MAXLAT) - -const char * sdCmd55() -{ - return sdCommand(SDMMC_APP_CMD, Sd_rca); -} - -#define SDMMC_SEND_STATUS_CMD (13 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_MAXLAT ) - -const char * sdCmd13(unsigned int *status) -{ - const char *result = sdCommand(SDMMC_SEND_STATUS_CMD, Sd_rca); - if (result) - return result; - *status = HSMCI->HSMCI_RSPR[0]; - return 0; -} - -#define SDMMC_SET_BLOCKLEN (16 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_MAXLAT_64 ) - -uint32_t sdCmd16() -{ - Hsmci *phsmci = HSMCI; - - if (SD_CARD_PRESENT()) { - phsmci->HSMCI_BLKR = ( ( 512 ) << 16 ) | 1 ; - phsmci->HSMCI_ARGR = 512; - phsmci->HSMCI_CMDR = SDMMC_SET_BLOCKLEN; - - while(1) { - if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) { - break; - } - } - return phsmci->HSMCI_RSPR[0]; - } - else { - return 0; - } -} - -#define SD_SD_SEND_OP_COND (41| HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_NO_DATA \ - /*| HSMCI_CMDR_OPDCMD_OPENDRAIN */ ) - -const char * sdCmd41(uint32_t arg, uint32_t * status) -{ - const char * result = sdCommand(SD_SD_SEND_OP_COND, arg); - if (result) - return result; - *status = HSMCI->HSMCI_RSPR[0]; - return 0; -} - -#define OCR_VDD_27_28 ((uint32_t)(1 << 15)) -#define OCR_VDD_28_29 ((uint32_t)(1 << 16)) -#define OCR_VDD_29_30 ((uint32_t)(1 << 17)) -#define OCR_VDD_30_31 ((uint32_t)(1 << 18)) -#define OCR_VDD_31_32 ((uint32_t)(1 << 19)) -#define OCR_VDD_32_33 ((uint32_t)(1 << 20)) -#define OCR_VDD_33_34 ((uint32_t)(1 << 21)) - -#define SDMMC_HOST_VOLTAGE_RANGE (OCR_VDD_27_28 +\ - OCR_VDD_28_29 +\ - OCR_VDD_29_30 +\ - OCR_VDD_30_31 +\ - OCR_VDD_31_32 +\ - OCR_VDD_32_33 +\ - OCR_VDD_32_33) /* not in SAM3S reference code */ - -#define OCR_POWER_UP_BUSY (1UL << 31) - -const char * sdMemInit(uint8_t hcs, uint32_t *pCCS) -{ - const char * result; - uint32_t arg; - uint32_t status; - do { - result = sdCmd55(); - if (result) - return result; - arg = SDMMC_HOST_VOLTAGE_RANGE; - if (hcs) arg |= OCR_SD_CCS; - result = sdCmd41(arg, &status); - if (result) - return result; - *pCCS = (status & OCR_SD_CCS); - } while ((status & OCR_POWER_UP_BUSY) != OCR_POWER_UP_BUSY); - return 0; -} - -// Get Card ID -const char * sdCmd2() -{ - const char * result = sdCommand(0x00001082, 0); - if (result) - return result; - - Hsmci *phsmci = HSMCI ; - Card_ID[0] = phsmci->HSMCI_RSPR[0] ; - Card_ID[1] = phsmci->HSMCI_RSPR[1] ; - Card_ID[2] = phsmci->HSMCI_RSPR[2] ; - Card_ID[3] = phsmci->HSMCI_RSPR[3] ; - return 0; -} - -// Get new RCA -const char * sdCmd3() -{ - const char * result = sdCommand(0x00001043, 0); - if (result) - return result; - Sd_rca = HSMCI->HSMCI_RSPR[0]; - return 0; -} - -// Get CSD -const char * sdCmd9() -{ - const char * result = sdCommand(0x00001089, Sd_rca); - if (result) - return result; - - Hsmci *phsmci = HSMCI ; - Card_CSD[0] = phsmci->HSMCI_RSPR[0] ; - Card_CSD[1] = phsmci->HSMCI_RSPR[1] ; - Card_CSD[2] = phsmci->HSMCI_RSPR[2] ; - Card_CSD[3] = phsmci->HSMCI_RSPR[3] ; - return 0; -} - -/** Cmd7 MCI, ac, R1/R1b */ -#define SDMMC_SELECT_CARD (7 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_R1B \ - | HSMCI_CMDR_MAXLAT ) - -const char * sdCmd7() -{ - return sdCommand(SDMMC_SELECT_CARD, Sd_rca); -} - -#define SD_SEND_SCR (51 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ \ - | HSMCI_CMDR_TRTYP_SINGLE | HSMCI_CMDR_MAXLAT) - -#define SD_READ_SINGLE_BLOCK (17 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ \ - | HSMCI_CMDR_TRTYP_SINGLE | HSMCI_CMDR_MAXLAT) - -#define SD_WRITE_SINGLE_BLOCK (24 | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_START_DATA \ - | HSMCI_CMDR_TRDIR_WRITE \ - | HSMCI_CMDR_TRTYP_SINGLE \ - | HSMCI_CMDR_MAXLAT) - -// Get SCR -const char * sdAcmd51() -{ - const char * result; - result = sdCmd55(); - if (result) - return result; - - Hsmci *phsmci = HSMCI ; - // Block size = 64/ 8, nblocks = 1 - phsmci->HSMCI_BLKR = ( ( 64 / 8 ) << 16 ) | 1 ; - phsmci->HSMCI_ARGR = 0 ; - phsmci->HSMCI_CMDR = SD_SEND_SCR ; - - uint8_t scrLen = 0; - uint32_t i; - for ( i = 0 ; i < 50000 ; i += 1 ) { - if ( phsmci->HSMCI_SR & HSMCI_SR_RXRDY ) - Card_SCR[scrLen++] = __REV(phsmci->HSMCI_RDR) ; - if ( ( phsmci->HSMCI_SR & ( HSMCI_SR_CMDRDY | HSMCI_SR_XFRDONE ) ) == ( HSMCI_SR_CMDRDY | HSMCI_SR_XFRDONE ) ) - return 0; - } - return "No response"; -} - -#define SD_SET_BUS_WIDTH (6 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_MAXLAT) - -void sdEnableHsMode(uint8_t enable) -{ - Hsmci *phsmci = HSMCI; - if (enable) - phsmci->HSMCI_CFG |= HSMCI_CFG_HSMODE; - else - phsmci->HSMCI_CFG &= ~HSMCI_CFG_HSMODE; -} - -void sdSetBusWidth(uint32_t busWidth) -{ - Hsmci *phsmci = HSMCI; - phsmci->HSMCI_SDCR = (HSMCI->HSMCI_SDCR & ~HSMCI_SDCR_SDCBUS_Msk) | busWidth; -} - -// Set bus width to 4 bits, set speed to 9 MHz -const char * sdAcmd6() -{ - const char * result; - result = sdCmd55() ; - if (result) - return result; - - result = sdCommand(SD_SET_BUS_WIDTH, 2); - if (result) - return result; - - sdSetBusWidth( HSMCI_SDCR_SDCBUS_4 ) ; - - GetTransSpeedValue(); - sdSetSpeed(transSpeed/*9000000*/); - - // TODO + Cmd6? sdEnableHsMode(1); - - if (Cmd_A41_resp & OCR_SD_CCS) - sdCmd16(); - - return 0; -} - -#if 0 -/** SDIO CMD52, R5 */ -#define SDIO_IO_RW_DIRECT (52| HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_MAXLAT) - -static const char * sdCmd52(uint8_t wrFlag, - uint8_t funcNb, - uint8_t rdAfterWr, - uint32_t addr, - uint32_t *status) -{ - typedef struct - { - uint32_t data:8, /**< [ 7: 0] data for writing */ - stuff0:1, /**< [ 8] reserved */ - regAddress:17, /**< [25: 9] register address */ - stuff1:1, /**< [ 26] reserved */ - rawFlag:1, /**< [ 27] Read after Write flag */ - functionNum:3, /**< [30:28] Number of the function */ - rwFlag:1; /**< [ 31] Direction, 1:write, 0:read. */ - } SdioCmd52Arg; - - SdioCmd52Arg pArg52; - pArg52.rwFlag = wrFlag; - pArg52.functionNum = funcNb; - pArg52.rawFlag = rdAfterWr; - pArg52.regAddress = addr; - - const char * result = sdCommand(SDIO_IO_RW_DIRECT, *(uint32_t*)&pArg52); - if (result) - return result; - *status = HSMCI->HSMCI_RSPR[0]; - return 0; -} - -const char * sdSwReset(uint32_t retry) -{ - uint32_t i; - const char * result = 0; - - for (i = 0; i < retry; i++) { - result = sdCmd0(0); - if (result != SD_NORESPONSE) - break; - } - return result; -} -#endif - -/** - * \brief Run the SD/MMC/SDIO Mode initialization sequence. - * This function runs the initialization procedure and the identification - * process. Then it leaves the card in ready state. The following procedure must - * check the card type and continue to put the card into tran(for memory card) - * or cmd(for io card) state for data exchange. - * \param pSd Pointer to a SD card driver instance. - * \return 0 if successful; otherwise returns an \ref sdmmc_rc "SD_ERROR code". - */ - -#define SDIO_CIA 0 /**< SDIO Function 0 (CIA) */ -#define SDIO_IOA_REG 0x06 /**< I/O Abort */ - -/** SDIO state (in R5) */ -#define SDIO_R5_ERROR (1UL << 11)/**< General error */ -#define SDIO_R5_FUNC_NUM (1UL << 10)/**< Invalid function number */ -#define SDIO_R5_OUT_OF_RANGE (1UL << 9) /**< Argument out of range */ - -/** Status bits mask for SDIO R5 */ -#define STATUS_SDIO_R5 (0/*SDIO_R5_STATE*/ \ - | SDIO_R5_ERROR \ - | SDIO_R5_FUNC_NUM \ - | SDIO_R5_OUT_OF_RANGE) - - -#define OCR_SDIO_MP (1UL << 27) -#define OCR_SDIO_NF (7UL << 28) - -#if 0 -const char * sdIdentify() -{ - uint8_t mem = 0, io = 0, f8 = 0, mp = 1; - uint32_t status, ccs=0; - const char * result; - - /* Reset HC to default HS and BusMode */ - sdEnableHsMode(0); - sdSetBusWidth(HSMCI_SDCR_SDCBUS_1); - -#if 0 - /* Reset SDIO: CMD52, write 1 to RES bit in CCCR (bit 3 of register 6) */ - result = sdCmd52(1, SDIO_CIA, 0, SDIO_IOA_REG, &status); - if (result) - return result; - if (status & STATUS_SDIO_R5) - return "Identify.52 error"; -#endif - - /* Reset MEM: CMD0 */ - result = sdSwReset(1); - if (result) - return result; - - /* CMD8 is newly added in the Physical Layer Specification Version 2.00 to - * support multiple voltage ranges and used to check whether the card - * supports supplied voltage. The version 2.00 host shall issue CMD8 and - * verify voltage before card initialization. - * The host that does not support CMD8 shall supply high voltage range... */ - result = sdCmd8(1); - if (result == 0) f8 = 1; - else if (result == SD_NORESPONSE) CoTickDelay(1); /* 2ms delay after "no response" */ - else return "Identify.8 error"; - -#if 0 - /* CMD5 is newly added for SDIO initialize & power on */ - status = 0; - result = sdCmd5(&status); - if (!result && (status & OCR_SDIO_NF) > 0) { - unsigned int cmd5Retries = 10000; - do { - status &= SDMMC_HOST_VOLTAGE_RANGE; - result = sdCmd5(&status); - if (status & OCR_POWER_UP_BUSY) break; - } while(!result && cmd5Retries --); - if (result) - return "Identify.5 error"; - io = 1; - /* IO only ?*/ - mp = ((status & OCR_SDIO_MP) > 0); - } -#endif - - /* Has memory: SD/MMC/COMBO */ - /*if (mp) */ - { - /* Try SD memory initialize */ - result = sdMemInit(f8, &ccs); - if (result) { - //unsigned int cmd1Retries = 10000; - /* Try MMC initialize */ - result = sdSwReset(10); - if (result) - return "Reset error"; - /* TODO ccs = 1; - do { result = sdCmd1(&ccs); } while(result && cmd1Retries -- > 0); - if (error) { - TRACE_ERROR("SdMmcIdentify.Cmd1: %u\n\r", error); - return SDMMC_ERROR; - } - else if (ccs) cardType = CARD_MMCHD; - else cardType = CARD_MMC; - */ - return "TODO error"; - /* MMC card identification OK */ - return 0; - } - // mem = 1; - } - /* SD(IO) + MEM ? */ - /* if (!mem) { - if (io) cardType = CARD_SDIO; - else - return "Unknown SD"; - } */ - /* SD(HC) combo */ - /*else if (io) - cardType = ccs ? CARD_SDHCCOMBO : CARD_SDCOMBO;*/ - /* SD(HC) */ - //else - cardType = ccs ? CARD_SDHC : CARD_SD; - - return 0; -} - -const char * sdEnum() -{ - uint8_t mem , io; - const char * result; - uint32_t ioSpeed = 0, memSpeed = 0; - uint8_t hsExec = 0, bwExec = 0; - - /* - has Memory/IO/High-Capacity - */ - mem = ((cardType & CARD_TYPE_bmSDMMC) > 0); - io = ((cardType & CARD_TYPE_bmSDIO) > 0); - - /* For MEMORY cards: - * The host then issues the command ALL_SEND_CID (CMD2) to the card to get - * its unique card identification (CID) number. - * Card that is unidentified (i.e. which is in Ready State) sends its CID - * number as the response (on the CMD line). */ - if (mem) { - result = sdCmd2(); - if (result) - return result; - } - - /* For MEMORY and SDIO cards: - * Thereafter, the host issues CMD3 (SEND_RELATIVE_ADDR) asks the - * card to publish a new relative card address (RCA), which is shorter than - * CID and which is used to address the card in the future data transfer - * mode. Once the RCA is received the card state changes to the Stand-by - * State. At this point, if the host wants to assign another RCA number, it - * can ask the card to publish a new number by sending another CMD3 command - * to the card. The last published RCA is the actual RCA number of the - * card. */ - result = sdCmd3(); - if (result) - return result; - - /* For MEMORY cards: - * SEND_CSD (CMD9) to obtain the Card Specific Data (CSD register), - * e.g. block length, card storage capacity, etc... */ - if (mem) { - result = sdCmd9(); - if (result) - return result; - } - - /* Now select the card, to TRAN state */ - error = MmcSelectCard(pSd, pSd->cardAddress, 0); - if (error) { - TRACE_ERROR("SdMmcInit.SelCard(%d)\n\r", error); - return error; - } - - /* - Now in TRAN, obtain extended setup information - */ - - /* If the card support EXT_CSD, read it! */ - TRACE_INFO("Card Type %d, CSD_STRUCTURE %d\n\r", - pSd->cardType, SD_CSD_STRUCTURE(pSd)); - - /* Get extended information of the card */ - SdMmcUpdateInformation(pSd, 0, 1); - - /* Calculate transfer speed */ - if (io) ioSpeed = SdioGetMaxSpeed(pSd); - if (mem) memSpeed = SdmmcGetMaxSpeed(pSd); - /* Combo, min speed */ - if (io && mem) { - pSd->transSpeed = (ioSpeed > memSpeed) ? memSpeed : ioSpeed; - } - /* SDIO only */ - else if (io) { - pSd->transSpeed = ioSpeed; - } - /* Memory card only */ - else if (mem) { - pSd->transSpeed = memSpeed; - } - pSd->transSpeed *= 1000; - - /* Enable more bus width Mode */ - error = SdMmcDesideBuswidth(pSd); - if (!error) bwExec = 1; - else if (error != SDMMC_ERROR_NOT_SUPPORT) { - TRACE_ERROR("SdmmcEnum.DesideBusWidth: %u\n\r", error); - return SDMMC_ERROR; - } - - /* Enable High-Speed Mode */ - error = SdMmcEnableHighSpeed(pSd); - if (!error) hsExec = 1; - else if (error != SDMMC_ERROR_NOT_SUPPORT) { - TRACE_ERROR("SdmmcEnum.EnableHS: %u\n\r", error); - return SDMMC_ERROR; - } - - /* In HS mode transfer speed *2 */ - if (hsExec) pSd->transSpeed *= 2; - - /* Update card information since status changed */ - if (bwExec || hsExec) SdMmcUpdateInformation(pSd, hsExec, 1); - return 0; -} - -void sdInit() -{ - TRACE("sdInit"); - - const char * result; - uint8_t i; - - /* Clear CID, CSD, EXT_CSD data */ - for (i = 0; i < 4; i++) Card_ID[i] = 0; - for (i = 0; i < 4; i++) Card_CSD[i] = 0; - // TODO for (i = 0; i < 512/4; i++) pSd->extData[i] = 0; - - /* Set low speed for device identification (LS device max speed) */ - sdSetSpeed(400000); - - /* Initialization delay: The maximum of 1 msec, 74 clock cycles and supply - * ramp up time. Supply ramp up time provides the time that the power is - * built up to the operating level (the bus master supply voltage) and the - * time to wait until the SD card can accept the first command. - */ - - /* Power On Init Special Command */ - result = sdPowerOn(); - if (result) - return; - - /* After power-on or CMD0, all cards? - * CMD lines are in input mode, waiting for start bit of the next command. - * The cards are initialized with a default relative card address - * (RCA=0x0000) and with a default driver stage register setting - * (lowest speed, highest driving current capability). - */ - result = sdIdentify(); - if (result) { - return; - } - -#if 0 - result = sdEnum(); - if (result) { - return; - } - - /* In the case of a Standard Capacity SD Memory Card, this command sets the - * block length (in bytes) for all following block commands - * (read, write, lock). - * Default block length is fixed to 512 Bytes. - * Set length is valid for memory access commands only if partial block read - * operation are allowed in CSD. - * In the case of a High Capacity SD Memory Card, block length set by CMD16 - * command does not affect the memory read and write commands. Always 512 - * Bytes fixed block length is used. This command is effective for - * LOCK_UNLOCK command. - * In both cases, if block length is set larger than 512Bytes, the card sets - * the BLOCK_LEN_ERROR bit. */ - if (pSd->cardType == CARD_SD) { - error = Cmd16(pSd, SDMMC_BLOCK_SIZE); - if (error) { - pSd->optCmdBitMap &= ~SD_CMD16_SUPPORT; - TRACE_INFO("SD_Init.Cmd16 (%d)\n\r", error); - TRACE_INFO("Fail to set BLK_LEN, default is 512\n\r"); - } - } - - /* Reset status for R/W */ - pSd->state = SD_STATE_READY; - - /* If MMC Card & get size from EXT_CSD */ - if ((pSd->cardType & CARD_TYPE_bmSDMMC) == CARD_TYPE_bmMMC - && SD_CSD_C_SIZE(pSd) == 0xFFF) { - pSd->blockNr = SD_EXTCSD_BLOCKNR(pSd); - /* Block number less than 0x100000000/512 */ - if (pSd->blockNr > 0x800000) - pSd->totalSize = 0xFFFFFFFF; - else - pSd->totalSize = SD_EXTCSD_TOTAL_SIZE(pSd); - } - /* If SD CSD v2.0 */ - else if((pSd->cardType & CARD_TYPE_bmSDMMC) == CARD_TYPE_bmSD - && SD_CSD_STRUCTURE(pSd) >= 1) { - pSd->blockNr = SD_CSD_BLOCKNR_HC(pSd); - pSd->totalSize = 0xFFFFFFFF; - } - /* Normal SD/MMC card */ - else if (pSd->cardType & CARD_TYPE_bmSDMMC) { - pSd->totalSize = SD_CSD_TOTAL_SIZE(pSd); - pSd->blockNr = SD_CSD_BLOCKNR(pSd); - } - - if (pSd->cardType == CARD_UNKNOWN) { - return SDMMC_ERROR_NOT_INITIALIZED; - } - /* Automatically select the max clock */ - clock = SdmmcSetSpeed(pSd, pSd->transSpeed); - TRACE_WARNING_WP("-I- Set SD/MMC clock to %dK\n\r", clock/1000); - pSd->accSpeed = clock; -#endif -} -#endif - -uint8_t sdErrorCount = 0; -FATFS g_FATFS_Obj = { 0 }; - -void sdInit() -{ - Sd_rca = 0; - sdErrorCount = 0; - - if (!SD_CARD_PRESENT()) { - Card_state = SD_ST_EMPTY; - Card_initialized = 1; - return; - } - - sdCmd0(); - CoTickDelay(5); // 10ms - sdCmd8(1); - -#if 0 - uint8_t i; - uint32_t status; - for (i=0; i<100; i++) - sdCmd5(&status); -#endif - - sdMemInit(1, &Cmd_A41_resp); - - uint8_t retry; - for (retry=0; retry<10; retry++) { - if (!sdCmd2()) break; - CoTickDelay(1); // 2ms - } - - if (retry == 10) { - Card_state = SD_ST_READY; - Card_initialized = 1; - return; - } - - for (retry=0; retry<10; retry++) { - if (!sdCmd3()) break; - CoTickDelay(1); // 2ms - } - - if (retry == 10) { - Card_state = SD_ST_IDENT; - Card_initialized = 1; - return; - } - - sdCmd9(); - sdCmd7(); // Select Card - - sdAcmd51(); - sdAcmd6(); // Set bus width to 4 bits, and speed to 9 MHz - - // Should check the card can do this **** - Card_state = SD_ST_DATA; - - if (f_mount(&g_FATFS_Obj, "", 1) == FR_OK) { - // call sdGetFreeSectors() now because f_getfree() takes a long time first time it's called - sdGetFreeSectors(); - Card_state = SD_ST_MOUNTED; - } - - Card_initialized = 1; -} - -void sdDone() -{ - if (sdMounted()) { - audioQueue.stopSD(); - f_mount(NULL, "", 0); // unmount SD - } -} - -// Checks for card ready for read/write -// returns 1 for YES, 0 for NO -uint32_t sd_card_ready( void ) -{ - return SD_CARD_PRESENT() && Card_state >= SD_ST_DATA; -} - -uint32_t sdMounted( void ) -{ - return SD_CARD_PRESENT() && Card_state == SD_ST_MOUNTED; -} - -uint32_t sd_read_block(uint32_t block_no, uint32_t *data) -{ - unsigned int status = 0; - - // TRACE_ERROR("read block %d", block_no); - - if (sd_card_ready()) { - - // Wait for card to be ready for data transfers - do { - sdCmd13(&status); - } - while (((status & STATUS_READY_FOR_DATA) == 0) - || ((status & STATUS_STATE) != STATUS_TRAN) ); - - // Block size = 512, nblocks = 1 - HSMCI->HSMCI_BLKR = ((512) << 16) | 1; - HSMCI->HSMCI_MR = (HSMCI->HSMCI_MR & (~(HSMCI_MR_BLKLEN_Msk|HSMCI_MR_FBYTE))) | (HSMCI_MR_PDCMODE|HSMCI_MR_WRPROOF|HSMCI_MR_RDPROOF) | (512 << 16); - HSMCI->HSMCI_ARGR = (Cmd_A41_resp & OCR_SD_CCS ? block_no : (block_no << 9)); - HSMCI->HSMCI_RPR = (uint32_t)data; - HSMCI->HSMCI_RCR = 512 / 4; - HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTEN; - HSMCI->HSMCI_CMDR = SD_READ_SINGLE_BLOCK; - - while (!(HSMCI->HSMCI_SR & HSMCI_SR_CMDRDY)); - - (void) HSMCI->HSMCI_RSPR[0]; - - while (1) { - if ((HSMCI->HSMCI_SR & (HSMCI_SR_ENDRX|HSMCI_SR_XFRDONE)) == (HSMCI_SR_ENDRX|HSMCI_SR_XFRDONE)) { - break; - } - } - - /* Disable PDC */ - HSMCI->HSMCI_MR &= ~(uint32_t)HSMCI_MR_PDCMODE; - HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS; - - return 1; - } - - // TRACE_ERROR("ok %.2X %.4Xd\n\r", HSMCI->HSMCI_SR, HSMCI->HSMCI_RSPR[0]); - - return 0; -} - -uint32_t sd_write_block( uint32_t block_no, uint32_t *data ) -{ - unsigned int status = 0; - - if (sd_card_ready()) { - -// TRACE_ERROR("write block %d", block_no); - - // Wait for card to be ready for data transfers - do { - sdCmd13(&status); - } while ((status & STATUS_READY_FOR_DATA) == 0); - - // Block size = 512, nblocks = 1 - HSMCI->HSMCI_BLKR = ((512) << 16) | 1; - HSMCI->HSMCI_MR = (HSMCI->HSMCI_MR & (~(HSMCI_MR_BLKLEN_Msk|HSMCI_MR_FBYTE))) | (HSMCI_MR_PDCMODE|HSMCI_MR_WRPROOF) | (512 << 16); - HSMCI->HSMCI_ARGR = (Cmd_A41_resp & OCR_SD_CCS ? block_no : (block_no << 9)); - HSMCI->HSMCI_TPR = (uint32_t)data; - HSMCI->HSMCI_TCR = 512 / 4; - HSMCI->HSMCI_CMDR = SD_WRITE_SINGLE_BLOCK; - - while (!(HSMCI->HSMCI_SR & HSMCI_SR_CMDRDY)); - - (void) HSMCI->HSMCI_RSPR[0]; - - HSMCI->HSMCI_PTCR = HSMCI_PTCR_TXTEN; - - while (1) { - if ((HSMCI->HSMCI_SR & (HSMCI_SR_NOTBUSY|HSMCI_SR_XFRDONE)) == (HSMCI_SR_NOTBUSY|HSMCI_SR_XFRDONE)) { - break; - } - } - - /* Disable PDC */ - HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS; - HSMCI->HSMCI_MR &= ~(uint32_t)HSMCI_MR_PDCMODE; - - return 1; - } - - return 0; -} - -/* - Notes on SD card: - -1) CMD8 fails and CMD58 fails: must be MMC, thus initialize using CMD1 -2) CMD8 fails and CMD58 passes: must be Ver1.x Standard Capacity SD Memory Card -3) CMD8 passes and CMD58 passes (CCS = 0): must be Ver2.00 or later Standard Capacity SD Memory Card -4) CMD8 passes and CMD58 passes (CCS = 1): must be Ver2.00 or later High Capacity SD Memory Card -5) CMD8 passes and CMD58 passes but indicates non compatible voltage range: unusable card - -On card present -1. Send CMD 55 (resp 48bit) - followed by ACMD41 (resp48bit) - until bit 31 of response is '1' - -2. Send CMD 2 (resp 136bit) - card ID - -3. Send CMD 3 (resp 48 bit) - new RCA returned - -4. Send CMD 9 (resp 136) - CSD - -5. Send CMD 7 (resp 48) - - -6. Send CMD 55 (resp 48bit) - followed by ACMD51 (resp48bit) - SCR stored as 2 32 bit values - -Now decide what the card can do! - -7. Set block length - -8. Set bus width - -9. Read block 0 - -*/ - -/*-----------------------------------------------------------------------*/ -/* Initialize Disk Drive */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_initialize ( - BYTE drv /* Physical drive nmuber (0) */ - ) -{ - if (drv) return STA_NOINIT; /* Supports only single drive */ - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - return RES_OK; -} - -/*-----------------------------------------------------------------------*/ -/* Get Disk Status */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_status ( - BYTE drv /* Physical drive number (0) */ - ) -{ - if (drv) return STA_NOINIT; /* Supports only single drive */ - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - return RES_OK; -} - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ -/*-----------------------------------------------------------------------*/ - -uint32_t dma_sd_buffer[512/4]; - -DRESULT disk_read ( - BYTE drv, /* Physical drive nmuber (0) */ - BYTE *buff, /* Pointer to the data buffer to store read data */ - DWORD sector, /* Start sector number (LBA) */ - UINT count /* Sector count (1..255) */ - ) -{ - uint32_t result ; - - if (drv || !count) return RES_PARERR; - - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - - do { - result = sd_read_block(sector, dma_sd_buffer) ; - if (result) { - memcpy(buff, dma_sd_buffer, 512); - sector += 1 ; - buff += 512 ; - count -= 1 ; - } - else { - count = 1 ; // Flag error - break ; - } - } while ( count ) ; - - if (!count) - return RES_OK; - - if (++sdErrorCount > 3) - Card_state = SD_ST_ERR; - - return RES_ERROR; -} - - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ -/*-----------------------------------------------------------------------*/ - -extern const char * warningText; - -DRESULT disk_write ( - BYTE drv, /* Physical drive nmuber (0) */ - const BYTE *buff, /* Pointer to the data to be written */ - DWORD sector, /* Start sector number (LBA) */ - UINT count /* Sector count (1..255) */ - ) -{ - uint32_t result ; - - if (drv || !count) return RES_PARERR; - - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - - do { - - while (1) { - - memcpy(dma_sd_buffer, buff, 512); - - result = sd_write_block(sector, dma_sd_buffer) ; - - sd_read_block(sector, dma_sd_buffer) ; - - if (!memcmp(dma_sd_buffer, buff, 512)) - break; - else { - TRACE_ERROR("Block %d ko SR=%.2X\r\n", sector, HSMCI->HSMCI_SR); - // DUMP(buff, 512); - // DUMP(copy, 512); - } - } - - if (result) { - sector += 1 ; - buff += 512 ; - count -= 1 ; - } - else { - count = 1 ; // Flag error - break ; - } - } while ( count ) ; - - if (!count) { - return RES_OK; - } - - if (++sdErrorCount > 3) - Card_state = SD_ST_ERR; - - return RES_ERROR; -} - - - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ -/*-----------------------------------------------------------------------*/ - -DRESULT disk_ioctl ( - BYTE drv, /* Physical drive nmuber (0) */ - BYTE ctrl, /* Control code */ - void *buff /* Buffer to send/receive control data */ - ) -{ - DRESULT res; - - if (drv) return RES_PARERR; - - res = RES_ERROR; - - if (ctrl == CTRL_POWER) { -#if 0 - switch (ptr[0]) { - case 0: /* Sub control code (POWER_OFF) */ - power_off(); /* Power off */ - res = RES_OK; - break; - case 1: /* Sub control code (POWER_GET) */ - ptr[1] = (BYTE)power_status(); - res = RES_OK; - break; - default : - res = RES_PARERR; - } -#endif - } - else { - switch (ctrl) { - case CTRL_SYNC : /* Make sure that no pending write process. Do not remove this or written sector might not left updated. */ - res = RES_OK; - break; - - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ - *(DWORD*)buff = SD_GET_BLOCKNR(); - res = RES_OK; - break; - - case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ - *(WORD*)buff = 512; - res = RES_OK; - break; - - case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ - *(WORD*)buff = 1; - res = RES_OK; - break; - -#if 0 - case MMC_GET_TYPE : /* Get card type flags (1 byte) */ - *ptr = CardType; - res = RES_OK; - break; - - case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ - if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ - if (send_cmd(CMD10, 0) == 0 /* READ_CID */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ - if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ - for (n = 4; n; n--) *ptr++ = rcvr_spi(); - res = RES_OK; - } - break; - - case MMC_GET_SDSTAT : /* Receive SD statsu as a data block (64 bytes) */ - if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ - rcvr_spi(); - if (rcvr_datablock(ptr, 64)) - res = RES_OK; - } - break; -#endif - default: - res = RES_PARERR; - break; - } - // BSS deselect(); - } - - return res; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*-----------------------------------------------------------------------*/ +/* MMCv3/SDv1/SDv2 (in SPI mode) control module (C)ChaN, 2010 */ +/*-----------------------------------------------------------------------*/ +/* Only rcvr_spi(), xmit_spi(), sdPoll10ms() and some macros */ +/* are platform dependent. */ +/*-----------------------------------------------------------------------*/ + +#include "opentx.h" +#include "diskio.h" + +#define CARD_TYPE_bmHC (1 << 0) /**< Bit for High-Capacity(Density) */ +#define CARD_TYPE_bmSDMMC (0x3 << 1) /**< Bits mask for SD/MMC */ +#define CARD_TYPE_bmUNKNOWN (0x0 << 1) /**< Bits for Unknown card */ +#define CARD_TYPE_bmSD (0x1 << 1) /**< Bits for SD */ +#define CARD_TYPE_bmMMC (0x2 << 1) /**< Bits for MMC */ +#define CARD_TYPE_bmSDIO (1 << 3) /**< Bit for SDIO */ +/** Card can not be identified */ +#define CARD_UNKNOWN (0) +/** SD Card (0x2) */ +#define CARD_SD (CARD_TYPE_bmSD) +/** SD High Capacity Card (0x3) */ +#define CARD_SDHC (CARD_TYPE_bmSD|CARD_TYPE_bmHC) +/** MMC Card (0x4) */ +#define CARD_MMC (CARD_TYPE_bmMMC) +/** MMC High-Density Card (0x5) */ +#define CARD_MMCHD (CARD_TYPE_bmMMC|CARD_TYPE_bmHC) +/** SDIO only card (0x8) */ +#define CARD_SDIO (CARD_TYPE_bmSDIO) +/** SDIO Combo, with SD embedded (0xA) */ +#define CARD_SDCOMBO (CARD_TYPE_bmSDIO|CARD_SD) +/** SDIO Combo, with SDHC embedded (0xB) */ +#define CARD_SDHCCOMBO (CARD_TYPE_bmSDIO|CARD_SDHC) + +#define STATUS_READY_FOR_DATA (1UL << 8) +#define STATUS_TRAN (4UL << 9) +#define STATUS_STATE (0xFUL << 9) + +/** Bit mask for data errors */ +#define STATUS_ERRORS_DATA ((uint32_t)(HSMCI_SR_UNRE \ + | HSMCI_SR_OVRE \ + /*| HSMCI_SR_BLKOVRE*/ \ + /*| HSMCI_SR_CSTOE*/ \ + | HSMCI_SR_DTOE \ + | HSMCI_SR_DCRCE)) + + +uint32_t Card_ID[4] ; +uint32_t Card_SCR[2] ; +uint32_t Card_CSD[4] ; +int32_t Card_state = SD_ST_STARTUP ; +volatile uint32_t Card_initialized = 0; +uint32_t Sd_rca ; +uint32_t Cmd_A41_resp ; +uint8_t cardType; +uint32_t transSpeed; + +/*-----------------------------------------------------------------------*/ +/* Lock / unlock functions */ +/*-----------------------------------------------------------------------*/ + +#if !defined(BOOT) +static OS_MutexID ioMutex; +volatile int mutexCheck = 0; +int ff_cre_syncobj (BYTE vol, _SYNC_t *mutex) +{ + *mutex = ioMutex; + return 1; +} + +int ff_req_grant (_SYNC_t mutex) +{ + CoEnterMutexSection(mutex); + return 1; +} + +void ff_rel_grant (_SYNC_t mutex) +{ + CoLeaveMutexSection(mutex); +} + +int ff_del_syncobj (_SYNC_t mutex) +{ + return 1; +} +#endif + +//------------------------------------------------------------------------------ +/// Get Trans Speed Value (Kbit/s) +/// \param tranSpeed The TRAN_SPEED value from SD(IO)/MMC enum information. +/// \param unitList Transfer rate units (Kbit/s), 4 units listed. +/// \param nbUnits Transfer rate units list size. +/// \param codeList Time value codes list, 16 codes listed. +//------------------------------------------------------------------------------ +static unsigned int MmcGetTranSpeed(unsigned int tranSpeed, + const unsigned int* unitList, unsigned int nbUnits, + const unsigned int* codeList) +{ + unsigned int unit, value; + unit = tranSpeed & 0x7; + if (unit < nbUnits) unit = unitList[unit]; + else return 0; + value = (tranSpeed >> 3) & 0xF; + if (value < 16) value = codeList[value]; + else return 0; + return (unit * value); +} + +//------------------------------------------------------------------------------ +/// Get Trans Speed Value +/// \param pSd +//------------------------------------------------------------------------------ +uint32_t GetTransSpeedValue() +{ + // CSD register, TRANS_SPEED bit + const unsigned int units[4] = {10, 100, 1000, 10000 }; // *Kbit/s +/* const unsigned int values_emmc[16] = {0, 10, 12, 13, 15, 20, + 26, 30, 35, 40, 45, 52, + 55, 60, 70, 80}; */ + const unsigned int values_sdmmc[16] = {0, 10, 12, 13, 15, 20, + 25, 30, 35, 40, 45, 50, + 55, 60, 70, 80}; + #if 0 + unsigned int unit, value; + unit = (SD_CSD_TRAN_SPEED(pSd) & 0x7); + if(unit < 4) unit = units[unit]; + else return; + value = (SD_CSD_TRAN_SPEED(pSd) >> 3) & 0xF; + if (value < 16) { + if (pSd->cardType >= CARD_MMC && SD_CID_BGA(pSd) == 1) { + value = values_emmc[value]; + } + else + value = values_sdmmc[value]; + } + else return; + pSd->transSpeed = (unit * value); + #else + transSpeed = MmcGetTranSpeed(SD_CSD_TRAN_SPEED(Card_CSD), + units, 4, + values_sdmmc); + #endif + /*if (pSd->cardType >= CARD_MMC && SD_EXTCSD_HS_TIMING(pSd)) { + pSd->transSpeed *= 2; + }*/ + TRACE_ERROR("-I- SD/MMC TRANS SPEED %d KBit/s\r\n", transSpeed); + transSpeed *= 1000; + return transSpeed; +} + +/** + * Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is + * MCK/2 and corresponds to CLKDIV = 0 + * \param mciSpeed MCI clock speed in Hz, 0 will not change current speed. + * \return The actual speed used, 0 for fail. + */ +uint32_t sdSetSpeed(uint32_t mciSpeed ) +{ + uint32_t mciMr; + uint32_t clkdiv, divLimit; + + mciMr = HSMCI->HSMCI_MR & (~(uint32_t)HSMCI_MR_CLKDIV_Msk); + /* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) + * divided by (2*(CLKDIV+1)) + * mciSpeed = MCK / (2*(CLKDIV+1)) */ + if (mciSpeed > 0) { + +#if 1 + divLimit = (Master_frequency / 2 / mciSpeed); + if ((Master_frequency / 2) % mciSpeed) divLimit ++; + + clkdiv = (Master_frequency / 2 / mciSpeed); + if (mciSpeed && clkdiv < divLimit) + clkdiv = divLimit; + if (clkdiv > 0) + clkdiv -= 1; +#else + clkdiv = (Master_frequency / 2 / mciSpeed); + /* Speed should not bigger than expired one */ + if (mciSpeed < Master_frequency / 2 / clkdiv) { + clkdiv++; + } + if (clkdiv > 0) { + clkdiv -= 1; + } +#endif + } + else { + clkdiv = 0; + } + + /* Actual MCI speed */ + mciSpeed = Master_frequency / 2 / (clkdiv + 1); + /* Modify MR */ + HSMCI->HSMCI_MR = mciMr | clkdiv; + + return mciSpeed; +} + +#if 0 +void SD_SetBlklen( uint32_t blklen ) +{ + uint32_t mciMr; + uint32_t clkdiv; + + mciMr = HSMCI->HSMCI_MR & (~(uint32_t)HSMCI_MR_BLKLEN); + /* Modify MR */ + HSMCI->HSMCI_MR = mciMr | blklen << 16 ; +} +#endif + +#if 0 +/** + * Reset MCI HW interface and disable it. + * \param keepSettings Keep old register settings, including + * _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG. + */ +void SD_Reset( uint8_t keepSettings) +{ + Hsmci *pMciHw = HSMCI ; + + if (keepSettings) + { + uint32_t mr, sdcr, dtor, cstor; + uint32_t cfg; + mr = pMciHw->HSMCI_MR; + sdcr = pMciHw->HSMCI_SDCR; + dtor = pMciHw->HSMCI_DTOR; + cstor = pMciHw->HSMCI_CSTOR; + cfg = pMciHw->HSMCI_CFG; + pMciHw->HSMCI_CR = HSMCI_CR_SWRST ; // Reset + pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS; // Disable + pMciHw->HSMCI_MR = mr; + pMciHw->HSMCI_SDCR = sdcr; + pMciHw->HSMCI_DTOR = dtor; + pMciHw->HSMCI_CSTOR = cstor; + pMciHw->HSMCI_CFG = cfg; + } + else + { + pMciHw->HSMCI_CR = HSMCI_CR_SWRST ; // Reset + pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS; // Disable + } +} +#endif + +const char SD_NORESPONSE[] = "No response"; + +const char * sdCommand(uint32_t cmd, uint32_t arg) +{ + uint32_t i; + Hsmci *phsmci = HSMCI; + + if (SD_CARD_PRESENT()) { + phsmci->HSMCI_ARGR = arg; + phsmci->HSMCI_CMDR = cmd; + + for (i = 0; i < 50000; i += 1) { + if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) { + return 0; + } + } + return SD_NORESPONSE; + } + else { + return "No Sdcard"; + } +} + +#define SDMMC_POWER_ON_INIT (0 | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_SPCMD_INIT \ + | HSMCI_CMDR_OPDCMD ) + +const char * sdPowerOn() +{ + return sdCommand(SDMMC_POWER_ON_INIT, 0); +} + +#define SDMMC_GO_IDLE_STATE (0 | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_SPCMD_STD ) + +const char * sdCmd0() +{ + return sdCommand(SDMMC_GO_IDLE_STATE, 0); +} + +#if 0 +#define SDIO_SEND_OP_COND (5 | HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_OPDCMD ) + +const char * sdCmd5(uint32_t *pIo) +{ + const char * result = sdCommand(SDIO_SEND_OP_COND, *pIo); + if (result) + return result; + *pIo = HSMCI->HSMCI_RSPR[0]; + return 0; +} +#endif + +#define SD_SEND_IF_COND (8 | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_OPDCMD /* BSS difference */ \ + | HSMCI_CMDR_MAXLAT ) + +const char * sdCmd8(uint8_t supplyVoltage) +{ + return sdCommand(SD_SEND_IF_COND, (supplyVoltage << 8) | (0xAA)); +} + +#define SDMMC_APP_CMD (55| HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_MAXLAT) + +const char * sdCmd55() +{ + return sdCommand(SDMMC_APP_CMD, Sd_rca); +} + +#define SDMMC_SEND_STATUS_CMD (13 | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_MAXLAT ) + +const char * sdCmd13(unsigned int *status) +{ + const char *result = sdCommand(SDMMC_SEND_STATUS_CMD, Sd_rca); + if (result) + return result; + *status = HSMCI->HSMCI_RSPR[0]; + return 0; +} + +#define SDMMC_SET_BLOCKLEN (16 | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_MAXLAT_64 ) + +uint32_t sdCmd16() +{ + Hsmci *phsmci = HSMCI; + + if (SD_CARD_PRESENT()) { + phsmci->HSMCI_BLKR = ( ( 512 ) << 16 ) | 1 ; + phsmci->HSMCI_ARGR = 512; + phsmci->HSMCI_CMDR = SDMMC_SET_BLOCKLEN; + + while(1) { + if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) { + break; + } + } + return phsmci->HSMCI_RSPR[0]; + } + else { + return 0; + } +} + +#define SD_SD_SEND_OP_COND (41| HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_TRCMD_NO_DATA \ + /*| HSMCI_CMDR_OPDCMD_OPENDRAIN */ ) + +const char * sdCmd41(uint32_t arg, uint32_t * status) +{ + const char * result = sdCommand(SD_SD_SEND_OP_COND, arg); + if (result) + return result; + *status = HSMCI->HSMCI_RSPR[0]; + return 0; +} + +#define OCR_VDD_27_28 ((uint32_t)(1 << 15)) +#define OCR_VDD_28_29 ((uint32_t)(1 << 16)) +#define OCR_VDD_29_30 ((uint32_t)(1 << 17)) +#define OCR_VDD_30_31 ((uint32_t)(1 << 18)) +#define OCR_VDD_31_32 ((uint32_t)(1 << 19)) +#define OCR_VDD_32_33 ((uint32_t)(1 << 20)) +#define OCR_VDD_33_34 ((uint32_t)(1 << 21)) + +#define SDMMC_HOST_VOLTAGE_RANGE (OCR_VDD_27_28 +\ + OCR_VDD_28_29 +\ + OCR_VDD_29_30 +\ + OCR_VDD_30_31 +\ + OCR_VDD_31_32 +\ + OCR_VDD_32_33 +\ + OCR_VDD_32_33) /* not in SAM3S reference code */ + +#define OCR_POWER_UP_BUSY (1UL << 31) + +const char * sdMemInit(uint8_t hcs, uint32_t *pCCS) +{ + const char * result; + uint32_t arg; + uint32_t status; + do { + result = sdCmd55(); + if (result) + return result; + arg = SDMMC_HOST_VOLTAGE_RANGE; + if (hcs) arg |= OCR_SD_CCS; + result = sdCmd41(arg, &status); + if (result) + return result; + *pCCS = (status & OCR_SD_CCS); + } while ((status & OCR_POWER_UP_BUSY) != OCR_POWER_UP_BUSY); + return 0; +} + +// Get Card ID +const char * sdCmd2() +{ + const char * result = sdCommand(0x00001082, 0); + if (result) + return result; + + Hsmci *phsmci = HSMCI ; + Card_ID[0] = phsmci->HSMCI_RSPR[0] ; + Card_ID[1] = phsmci->HSMCI_RSPR[1] ; + Card_ID[2] = phsmci->HSMCI_RSPR[2] ; + Card_ID[3] = phsmci->HSMCI_RSPR[3] ; + return 0; +} + +// Get new RCA +const char * sdCmd3() +{ + const char * result = sdCommand(0x00001043, 0); + if (result) + return result; + Sd_rca = HSMCI->HSMCI_RSPR[0]; + return 0; +} + +// Get CSD +const char * sdCmd9() +{ + const char * result = sdCommand(0x00001089, Sd_rca); + if (result) + return result; + + Hsmci *phsmci = HSMCI ; + Card_CSD[0] = phsmci->HSMCI_RSPR[0] ; + Card_CSD[1] = phsmci->HSMCI_RSPR[1] ; + Card_CSD[2] = phsmci->HSMCI_RSPR[2] ; + Card_CSD[3] = phsmci->HSMCI_RSPR[3] ; + return 0; +} + +/** Cmd7 MCI, ac, R1/R1b */ +#define SDMMC_SELECT_CARD (7 | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_R1B \ + | HSMCI_CMDR_MAXLAT ) + +const char * sdCmd7() +{ + return sdCommand(SDMMC_SELECT_CARD, Sd_rca); +} + +#define SD_SEND_SCR (51 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ \ + | HSMCI_CMDR_TRTYP_SINGLE | HSMCI_CMDR_MAXLAT) + +#define SD_READ_SINGLE_BLOCK (17 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ \ + | HSMCI_CMDR_TRTYP_SINGLE | HSMCI_CMDR_MAXLAT) + +#define SD_WRITE_SINGLE_BLOCK (24 | HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_TRCMD_START_DATA \ + | HSMCI_CMDR_TRDIR_WRITE \ + | HSMCI_CMDR_TRTYP_SINGLE \ + | HSMCI_CMDR_MAXLAT) + +// Get SCR +const char * sdAcmd51() +{ + const char * result; + result = sdCmd55(); + if (result) + return result; + + Hsmci *phsmci = HSMCI ; + // Block size = 64/ 8, nblocks = 1 + phsmci->HSMCI_BLKR = ( ( 64 / 8 ) << 16 ) | 1 ; + phsmci->HSMCI_ARGR = 0 ; + phsmci->HSMCI_CMDR = SD_SEND_SCR ; + + uint8_t scrLen = 0; + uint32_t i; + for ( i = 0 ; i < 50000 ; i += 1 ) { + if ( phsmci->HSMCI_SR & HSMCI_SR_RXRDY ) + Card_SCR[scrLen++] = __REV(phsmci->HSMCI_RDR) ; + if ( ( phsmci->HSMCI_SR & ( HSMCI_SR_CMDRDY | HSMCI_SR_XFRDONE ) ) == ( HSMCI_SR_CMDRDY | HSMCI_SR_XFRDONE ) ) + return 0; + } + return "No response"; +} + +#define SD_SET_BUS_WIDTH (6 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_MAXLAT) + +void sdEnableHsMode(uint8_t enable) +{ + Hsmci *phsmci = HSMCI; + if (enable) + phsmci->HSMCI_CFG |= HSMCI_CFG_HSMODE; + else + phsmci->HSMCI_CFG &= ~HSMCI_CFG_HSMODE; +} + +void sdSetBusWidth(uint32_t busWidth) +{ + Hsmci *phsmci = HSMCI; + phsmci->HSMCI_SDCR = (HSMCI->HSMCI_SDCR & ~HSMCI_SDCR_SDCBUS_Msk) | busWidth; +} + +// Set bus width to 4 bits, set speed to 9 MHz +const char * sdAcmd6() +{ + const char * result; + result = sdCmd55() ; + if (result) + return result; + + result = sdCommand(SD_SET_BUS_WIDTH, 2); + if (result) + return result; + + sdSetBusWidth( HSMCI_SDCR_SDCBUS_4 ) ; + + GetTransSpeedValue(); + sdSetSpeed(transSpeed/*9000000*/); + + // TODO + Cmd6? sdEnableHsMode(1); + + if (Cmd_A41_resp & OCR_SD_CCS) + sdCmd16(); + + return 0; +} + +#if 0 +/** SDIO CMD52, R5 */ +#define SDIO_IO_RW_DIRECT (52| HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_MAXLAT) + +static const char * sdCmd52(uint8_t wrFlag, + uint8_t funcNb, + uint8_t rdAfterWr, + uint32_t addr, + uint32_t *status) +{ + typedef struct + { + uint32_t data:8, /**< [ 7: 0] data for writing */ + stuff0:1, /**< [ 8] reserved */ + regAddress:17, /**< [25: 9] register address */ + stuff1:1, /**< [ 26] reserved */ + rawFlag:1, /**< [ 27] Read after Write flag */ + functionNum:3, /**< [30:28] Number of the function */ + rwFlag:1; /**< [ 31] Direction, 1:write, 0:read. */ + } SdioCmd52Arg; + + SdioCmd52Arg pArg52; + pArg52.rwFlag = wrFlag; + pArg52.functionNum = funcNb; + pArg52.rawFlag = rdAfterWr; + pArg52.regAddress = addr; + + const char * result = sdCommand(SDIO_IO_RW_DIRECT, *(uint32_t*)&pArg52); + if (result) + return result; + *status = HSMCI->HSMCI_RSPR[0]; + return 0; +} + +const char * sdSwReset(uint32_t retry) +{ + uint32_t i; + const char * result = 0; + + for (i = 0; i < retry; i++) { + result = sdCmd0(0); + if (result != SD_NORESPONSE) + break; + } + return result; +} +#endif + +/** + * \brief Run the SD/MMC/SDIO Mode initialization sequence. + * This function runs the initialization procedure and the identification + * process. Then it leaves the card in ready state. The following procedure must + * check the card type and continue to put the card into tran(for memory card) + * or cmd(for io card) state for data exchange. + * \param pSd Pointer to a SD card driver instance. + * \return 0 if successful; otherwise returns an \ref sdmmc_rc "SD_ERROR code". + */ + +#define SDIO_CIA 0 /**< SDIO Function 0 (CIA) */ +#define SDIO_IOA_REG 0x06 /**< I/O Abort */ + +/** SDIO state (in R5) */ +#define SDIO_R5_ERROR (1UL << 11)/**< General error */ +#define SDIO_R5_FUNC_NUM (1UL << 10)/**< Invalid function number */ +#define SDIO_R5_OUT_OF_RANGE (1UL << 9) /**< Argument out of range */ + +/** Status bits mask for SDIO R5 */ +#define STATUS_SDIO_R5 (0/*SDIO_R5_STATE*/ \ + | SDIO_R5_ERROR \ + | SDIO_R5_FUNC_NUM \ + | SDIO_R5_OUT_OF_RANGE) + + +#define OCR_SDIO_MP (1UL << 27) +#define OCR_SDIO_NF (7UL << 28) + +#if 0 +const char * sdIdentify() +{ + uint8_t mem = 0, io = 0, f8 = 0, mp = 1; + uint32_t status, ccs=0; + const char * result; + + /* Reset HC to default HS and BusMode */ + sdEnableHsMode(0); + sdSetBusWidth(HSMCI_SDCR_SDCBUS_1); + +#if 0 + /* Reset SDIO: CMD52, write 1 to RES bit in CCCR (bit 3 of register 6) */ + result = sdCmd52(1, SDIO_CIA, 0, SDIO_IOA_REG, &status); + if (result) + return result; + if (status & STATUS_SDIO_R5) + return "Identify.52 error"; +#endif + + /* Reset MEM: CMD0 */ + result = sdSwReset(1); + if (result) + return result; + + /* CMD8 is newly added in the Physical Layer Specification Version 2.00 to + * support multiple voltage ranges and used to check whether the card + * supports supplied voltage. The version 2.00 host shall issue CMD8 and + * verify voltage before card initialization. + * The host that does not support CMD8 shall supply high voltage range... */ + result = sdCmd8(1); + if (result == 0) f8 = 1; + else if (result == SD_NORESPONSE) CoTickDelay(1); /* 2ms delay after "no response" */ + else return "Identify.8 error"; + +#if 0 + /* CMD5 is newly added for SDIO initialize & power on */ + status = 0; + result = sdCmd5(&status); + if (!result && (status & OCR_SDIO_NF) > 0) { + unsigned int cmd5Retries = 10000; + do { + status &= SDMMC_HOST_VOLTAGE_RANGE; + result = sdCmd5(&status); + if (status & OCR_POWER_UP_BUSY) break; + } while(!result && cmd5Retries --); + if (result) + return "Identify.5 error"; + io = 1; + /* IO only ?*/ + mp = ((status & OCR_SDIO_MP) > 0); + } +#endif + + /* Has memory: SD/MMC/COMBO */ + /*if (mp) */ + { + /* Try SD memory initialize */ + result = sdMemInit(f8, &ccs); + if (result) { + //unsigned int cmd1Retries = 10000; + /* Try MMC initialize */ + result = sdSwReset(10); + if (result) + return "Reset error"; + /* TODO ccs = 1; + do { result = sdCmd1(&ccs); } while(result && cmd1Retries -- > 0); + if (error) { + TRACE_ERROR("SdMmcIdentify.Cmd1: %u\n\r", error); + return SDMMC_ERROR; + } + else if (ccs) cardType = CARD_MMCHD; + else cardType = CARD_MMC; + */ + return "TODO error"; + /* MMC card identification OK */ + return 0; + } + // mem = 1; + } + /* SD(IO) + MEM ? */ + /* if (!mem) { + if (io) cardType = CARD_SDIO; + else + return "Unknown SD"; + } */ + /* SD(HC) combo */ + /*else if (io) + cardType = ccs ? CARD_SDHCCOMBO : CARD_SDCOMBO;*/ + /* SD(HC) */ + //else + cardType = ccs ? CARD_SDHC : CARD_SD; + + return 0; +} + +const char * sdEnum() +{ + uint8_t mem , io; + const char * result; + uint32_t ioSpeed = 0, memSpeed = 0; + uint8_t hsExec = 0, bwExec = 0; + + /* - has Memory/IO/High-Capacity - */ + mem = ((cardType & CARD_TYPE_bmSDMMC) > 0); + io = ((cardType & CARD_TYPE_bmSDIO) > 0); + + /* For MEMORY cards: + * The host then issues the command ALL_SEND_CID (CMD2) to the card to get + * its unique card identification (CID) number. + * Card that is unidentified (i.e. which is in Ready State) sends its CID + * number as the response (on the CMD line). */ + if (mem) { + result = sdCmd2(); + if (result) + return result; + } + + /* For MEMORY and SDIO cards: + * Thereafter, the host issues CMD3 (SEND_RELATIVE_ADDR) asks the + * card to publish a new relative card address (RCA), which is shorter than + * CID and which is used to address the card in the future data transfer + * mode. Once the RCA is received the card state changes to the Stand-by + * State. At this point, if the host wants to assign another RCA number, it + * can ask the card to publish a new number by sending another CMD3 command + * to the card. The last published RCA is the actual RCA number of the + * card. */ + result = sdCmd3(); + if (result) + return result; + + /* For MEMORY cards: + * SEND_CSD (CMD9) to obtain the Card Specific Data (CSD register), + * e.g. block length, card storage capacity, etc... */ + if (mem) { + result = sdCmd9(); + if (result) + return result; + } + + /* Now select the card, to TRAN state */ + error = MmcSelectCard(pSd, pSd->cardAddress, 0); + if (error) { + TRACE_ERROR("SdMmcInit.SelCard(%d)\n\r", error); + return error; + } + + /* - Now in TRAN, obtain extended setup information - */ + + /* If the card support EXT_CSD, read it! */ + TRACE_INFO("Card Type %d, CSD_STRUCTURE %d\n\r", + pSd->cardType, SD_CSD_STRUCTURE(pSd)); + + /* Get extended information of the card */ + SdMmcUpdateInformation(pSd, 0, 1); + + /* Calculate transfer speed */ + if (io) ioSpeed = SdioGetMaxSpeed(pSd); + if (mem) memSpeed = SdmmcGetMaxSpeed(pSd); + /* Combo, min speed */ + if (io && mem) { + pSd->transSpeed = (ioSpeed > memSpeed) ? memSpeed : ioSpeed; + } + /* SDIO only */ + else if (io) { + pSd->transSpeed = ioSpeed; + } + /* Memory card only */ + else if (mem) { + pSd->transSpeed = memSpeed; + } + pSd->transSpeed *= 1000; + + /* Enable more bus width Mode */ + error = SdMmcDesideBuswidth(pSd); + if (!error) bwExec = 1; + else if (error != SDMMC_ERROR_NOT_SUPPORT) { + TRACE_ERROR("SdmmcEnum.DesideBusWidth: %u\n\r", error); + return SDMMC_ERROR; + } + + /* Enable High-Speed Mode */ + error = SdMmcEnableHighSpeed(pSd); + if (!error) hsExec = 1; + else if (error != SDMMC_ERROR_NOT_SUPPORT) { + TRACE_ERROR("SdmmcEnum.EnableHS: %u\n\r", error); + return SDMMC_ERROR; + } + + /* In HS mode transfer speed *2 */ + if (hsExec) pSd->transSpeed *= 2; + + /* Update card information since status changed */ + if (bwExec || hsExec) SdMmcUpdateInformation(pSd, hsExec, 1); + return 0; +} + +void sdInit() +{ + TRACE("sdInit"); + + const char * result; + uint8_t i; + + /* Clear CID, CSD, EXT_CSD data */ + for (i = 0; i < 4; i++) Card_ID[i] = 0; + for (i = 0; i < 4; i++) Card_CSD[i] = 0; + // TODO for (i = 0; i < 512/4; i++) pSd->extData[i] = 0; + + /* Set low speed for device identification (LS device max speed) */ + sdSetSpeed(400000); + + /* Initialization delay: The maximum of 1 msec, 74 clock cycles and supply + * ramp up time. Supply ramp up time provides the time that the power is + * built up to the operating level (the bus master supply voltage) and the + * time to wait until the SD card can accept the first command. + */ + + /* Power On Init Special Command */ + result = sdPowerOn(); + if (result) + return; + + /* After power-on or CMD0, all cards? + * CMD lines are in input mode, waiting for start bit of the next command. + * The cards are initialized with a default relative card address + * (RCA=0x0000) and with a default driver stage register setting + * (lowest speed, highest driving current capability). + */ + result = sdIdentify(); + if (result) { + return; + } + +#if 0 + result = sdEnum(); + if (result) { + return; + } + + /* In the case of a Standard Capacity SD Memory Card, this command sets the + * block length (in bytes) for all following block commands + * (read, write, lock). + * Default block length is fixed to 512 Bytes. + * Set length is valid for memory access commands only if partial block read + * operation are allowed in CSD. + * In the case of a High Capacity SD Memory Card, block length set by CMD16 + * command does not affect the memory read and write commands. Always 512 + * Bytes fixed block length is used. This command is effective for + * LOCK_UNLOCK command. + * In both cases, if block length is set larger than 512Bytes, the card sets + * the BLOCK_LEN_ERROR bit. */ + if (pSd->cardType == CARD_SD) { + error = Cmd16(pSd, SDMMC_BLOCK_SIZE); + if (error) { + pSd->optCmdBitMap &= ~SD_CMD16_SUPPORT; + TRACE_INFO("SD_Init.Cmd16 (%d)\n\r", error); + TRACE_INFO("Fail to set BLK_LEN, default is 512\n\r"); + } + } + + /* Reset status for R/W */ + pSd->state = SD_STATE_READY; + + /* If MMC Card & get size from EXT_CSD */ + if ((pSd->cardType & CARD_TYPE_bmSDMMC) == CARD_TYPE_bmMMC + && SD_CSD_C_SIZE(pSd) == 0xFFF) { + pSd->blockNr = SD_EXTCSD_BLOCKNR(pSd); + /* Block number less than 0x100000000/512 */ + if (pSd->blockNr > 0x800000) + pSd->totalSize = 0xFFFFFFFF; + else + pSd->totalSize = SD_EXTCSD_TOTAL_SIZE(pSd); + } + /* If SD CSD v2.0 */ + else if((pSd->cardType & CARD_TYPE_bmSDMMC) == CARD_TYPE_bmSD + && SD_CSD_STRUCTURE(pSd) >= 1) { + pSd->blockNr = SD_CSD_BLOCKNR_HC(pSd); + pSd->totalSize = 0xFFFFFFFF; + } + /* Normal SD/MMC card */ + else if (pSd->cardType & CARD_TYPE_bmSDMMC) { + pSd->totalSize = SD_CSD_TOTAL_SIZE(pSd); + pSd->blockNr = SD_CSD_BLOCKNR(pSd); + } + + if (pSd->cardType == CARD_UNKNOWN) { + return SDMMC_ERROR_NOT_INITIALIZED; + } + /* Automatically select the max clock */ + clock = SdmmcSetSpeed(pSd, pSd->transSpeed); + TRACE_WARNING_WP("-I- Set SD/MMC clock to %dK\n\r", clock/1000); + pSd->accSpeed = clock; +#endif +} +#endif + +uint8_t sdErrorCount = 0; +FATFS g_FATFS_Obj = { 0 }; + +void sdInit() +{ + Sd_rca = 0; + sdErrorCount = 0; + + if (!SD_CARD_PRESENT()) { + Card_state = SD_ST_EMPTY; + Card_initialized = 1; + return; + } + + sdCmd0(); + CoTickDelay(5); // 10ms + sdCmd8(1); + +#if 0 + uint8_t i; + uint32_t status; + for (i=0; i<100; i++) + sdCmd5(&status); +#endif + + sdMemInit(1, &Cmd_A41_resp); + + uint8_t retry; + for (retry=0; retry<10; retry++) { + if (!sdCmd2()) break; + CoTickDelay(1); // 2ms + } + + if (retry == 10) { + Card_state = SD_ST_READY; + Card_initialized = 1; + return; + } + + for (retry=0; retry<10; retry++) { + if (!sdCmd3()) break; + CoTickDelay(1); // 2ms + } + + if (retry == 10) { + Card_state = SD_ST_IDENT; + Card_initialized = 1; + return; + } + + sdCmd9(); + sdCmd7(); // Select Card + + sdAcmd51(); + sdAcmd6(); // Set bus width to 4 bits, and speed to 9 MHz + + // Should check the card can do this **** + Card_state = SD_ST_DATA; + + if (f_mount(&g_FATFS_Obj, "", 1) == FR_OK) { + // call sdGetFreeSectors() now because f_getfree() takes a long time first time it's called + sdGetFreeSectors(); + Card_state = SD_ST_MOUNTED; + } + + Card_initialized = 1; +} + +void sdDone() +{ + if (sdMounted()) { + audioQueue.stopSD(); + f_mount(NULL, "", 0); // unmount SD + } +} + +// Checks for card ready for read/write +// returns 1 for YES, 0 for NO +uint32_t sd_card_ready( void ) +{ + return SD_CARD_PRESENT() && Card_state >= SD_ST_DATA; +} + +uint32_t sdMounted( void ) +{ + return SD_CARD_PRESENT() && Card_state == SD_ST_MOUNTED; +} + +uint32_t sd_read_block(uint32_t block_no, uint32_t *data) +{ + unsigned int status = 0; + + // TRACE_ERROR("read block %d", block_no); + + if (sd_card_ready()) { + + // Wait for card to be ready for data transfers + do { + sdCmd13(&status); + } + while (((status & STATUS_READY_FOR_DATA) == 0) + || ((status & STATUS_STATE) != STATUS_TRAN) ); + + // Block size = 512, nblocks = 1 + HSMCI->HSMCI_BLKR = ((512) << 16) | 1; + HSMCI->HSMCI_MR = (HSMCI->HSMCI_MR & (~(HSMCI_MR_BLKLEN_Msk|HSMCI_MR_FBYTE))) | (HSMCI_MR_PDCMODE|HSMCI_MR_WRPROOF|HSMCI_MR_RDPROOF) | (512 << 16); + HSMCI->HSMCI_ARGR = (Cmd_A41_resp & OCR_SD_CCS ? block_no : (block_no << 9)); + HSMCI->HSMCI_RPR = (uint32_t)data; + HSMCI->HSMCI_RCR = 512 / 4; + HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTEN; + HSMCI->HSMCI_CMDR = SD_READ_SINGLE_BLOCK; + + while (!(HSMCI->HSMCI_SR & HSMCI_SR_CMDRDY)); + + (void) HSMCI->HSMCI_RSPR[0]; + + while (1) { + if ((HSMCI->HSMCI_SR & (HSMCI_SR_ENDRX|HSMCI_SR_XFRDONE)) == (HSMCI_SR_ENDRX|HSMCI_SR_XFRDONE)) { + break; + } + } + + /* Disable PDC */ + HSMCI->HSMCI_MR &= ~(uint32_t)HSMCI_MR_PDCMODE; + HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS; + + return 1; + } + + // TRACE_ERROR("ok %.2X %.4Xd\n\r", HSMCI->HSMCI_SR, HSMCI->HSMCI_RSPR[0]); + + return 0; +} + +uint32_t sd_write_block( uint32_t block_no, uint32_t *data ) +{ + unsigned int status = 0; + + if (sd_card_ready()) { + +// TRACE_ERROR("write block %d", block_no); + + // Wait for card to be ready for data transfers + do { + sdCmd13(&status); + } while ((status & STATUS_READY_FOR_DATA) == 0); + + // Block size = 512, nblocks = 1 + HSMCI->HSMCI_BLKR = ((512) << 16) | 1; + HSMCI->HSMCI_MR = (HSMCI->HSMCI_MR & (~(HSMCI_MR_BLKLEN_Msk|HSMCI_MR_FBYTE))) | (HSMCI_MR_PDCMODE|HSMCI_MR_WRPROOF) | (512 << 16); + HSMCI->HSMCI_ARGR = (Cmd_A41_resp & OCR_SD_CCS ? block_no : (block_no << 9)); + HSMCI->HSMCI_TPR = (uint32_t)data; + HSMCI->HSMCI_TCR = 512 / 4; + HSMCI->HSMCI_CMDR = SD_WRITE_SINGLE_BLOCK; + + while (!(HSMCI->HSMCI_SR & HSMCI_SR_CMDRDY)); + + (void) HSMCI->HSMCI_RSPR[0]; + + HSMCI->HSMCI_PTCR = HSMCI_PTCR_TXTEN; + + while (1) { + if ((HSMCI->HSMCI_SR & (HSMCI_SR_NOTBUSY|HSMCI_SR_XFRDONE)) == (HSMCI_SR_NOTBUSY|HSMCI_SR_XFRDONE)) { + break; + } + } + + /* Disable PDC */ + HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS; + HSMCI->HSMCI_MR &= ~(uint32_t)HSMCI_MR_PDCMODE; + + return 1; + } + + return 0; +} + +/* + Notes on SD card: + +1) CMD8 fails and CMD58 fails: must be MMC, thus initialize using CMD1 +2) CMD8 fails and CMD58 passes: must be Ver1.x Standard Capacity SD Memory Card +3) CMD8 passes and CMD58 passes (CCS = 0): must be Ver2.00 or later Standard Capacity SD Memory Card +4) CMD8 passes and CMD58 passes (CCS = 1): must be Ver2.00 or later High Capacity SD Memory Card +5) CMD8 passes and CMD58 passes but indicates non compatible voltage range: unusable card + +On card present +1. Send CMD 55 (resp 48bit) + followed by ACMD41 (resp48bit) + until bit 31 of response is '1' + +2. Send CMD 2 (resp 136bit) - card ID + +3. Send CMD 3 (resp 48 bit) - new RCA returned + +4. Send CMD 9 (resp 136) - CSD + +5. Send CMD 7 (resp 48) - + +6. Send CMD 55 (resp 48bit) + followed by ACMD51 (resp48bit) - SCR stored as 2 32 bit values + +Now decide what the card can do! + +7. Set block length + +8. Set bus width + +9. Read block 0 + +*/ + +/*-----------------------------------------------------------------------*/ +/* Initialize Disk Drive */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_initialize ( + BYTE drv /* Physical drive nmuber (0) */ + ) +{ + if (drv) return STA_NOINIT; /* Supports only single drive */ + if ( sd_card_ready() == 0 ) return RES_NOTRDY; + return RES_OK; +} + +/*-----------------------------------------------------------------------*/ +/* Get Disk Status */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_status ( + BYTE drv /* Physical drive number (0) */ + ) +{ + if (drv) return STA_NOINIT; /* Supports only single drive */ + if ( sd_card_ready() == 0 ) return RES_NOTRDY; + return RES_OK; +} + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ +/*-----------------------------------------------------------------------*/ + +uint32_t dma_sd_buffer[512/4]; + +DRESULT disk_read ( + BYTE drv, /* Physical drive nmuber (0) */ + BYTE *buff, /* Pointer to the data buffer to store read data */ + DWORD sector, /* Start sector number (LBA) */ + UINT count /* Sector count (1..255) */ + ) +{ + uint32_t result ; + + if (drv || !count) return RES_PARERR; + + if ( sd_card_ready() == 0 ) return RES_NOTRDY; + + do { + result = sd_read_block(sector, dma_sd_buffer) ; + if (result) { + memcpy(buff, dma_sd_buffer, 512); + sector += 1 ; + buff += 512 ; + count -= 1 ; + } + else { + count = 1 ; // Flag error + break ; + } + } while ( count ) ; + + if (!count) + return RES_OK; + + if (++sdErrorCount > 3) + Card_state = SD_ST_ERR; + + return RES_ERROR; +} + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ +/*-----------------------------------------------------------------------*/ + +extern const char * warningText; + +DRESULT disk_write ( + BYTE drv, /* Physical drive nmuber (0) */ + const BYTE *buff, /* Pointer to the data to be written */ + DWORD sector, /* Start sector number (LBA) */ + UINT count /* Sector count (1..255) */ + ) +{ + uint32_t result ; + + if (drv || !count) return RES_PARERR; + + if ( sd_card_ready() == 0 ) return RES_NOTRDY; + + do { + + while (1) { + + memcpy(dma_sd_buffer, buff, 512); + + result = sd_write_block(sector, dma_sd_buffer) ; + + sd_read_block(sector, dma_sd_buffer) ; + + if (!memcmp(dma_sd_buffer, buff, 512)) + break; + else { + TRACE_ERROR("Block %d ko SR=%.2X\r\n", sector, HSMCI->HSMCI_SR); + // DUMP(buff, 512); + // DUMP(copy, 512); + } + } + + if (result) { + sector += 1 ; + buff += 512 ; + count -= 1 ; + } + else { + count = 1 ; // Flag error + break ; + } + } while ( count ) ; + + if (!count) { + return RES_OK; + } + + if (++sdErrorCount > 3) + Card_state = SD_ST_ERR; + + return RES_ERROR; +} + + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_ioctl ( + BYTE drv, /* Physical drive nmuber (0) */ + BYTE ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ + ) +{ + DRESULT res; + + if (drv) return RES_PARERR; + + res = RES_ERROR; + + if (ctrl == CTRL_POWER) { +#if 0 + switch (ptr[0]) { + case 0: /* Sub control code (POWER_OFF) */ + power_off(); /* Power off */ + res = RES_OK; + break; + case 1: /* Sub control code (POWER_GET) */ + ptr[1] = (BYTE)power_status(); + res = RES_OK; + break; + default : + res = RES_PARERR; + } +#endif + } + else { + switch (ctrl) { + case CTRL_SYNC : /* Make sure that no pending write process. Do not remove this or written sector might not left updated. */ + res = RES_OK; + break; + + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ + *(DWORD*)buff = SD_GET_BLOCKNR(); + res = RES_OK; + break; + + case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ + *(WORD*)buff = 512; + res = RES_OK; + break; + + case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ + *(WORD*)buff = 1; + res = RES_OK; + break; + +#if 0 + case MMC_GET_TYPE : /* Get card type flags (1 byte) */ + *ptr = CardType; + res = RES_OK; + break; + + case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ + if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ + if (send_cmd(CMD10, 0) == 0 /* READ_CID */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ + if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ + for (n = 4; n; n--) *ptr++ = rcvr_spi(); + res = RES_OK; + } + break; + + case MMC_GET_SDSTAT : /* Receive SD statsu as a data block (64 bytes) */ + if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ + rcvr_spi(); + if (rcvr_datablock(ptr, 64)) + res = RES_OK; + } + break; +#endif + default: + res = RES_PARERR; + break; + } + // BSS deselect(); + } + + return res; +} diff --git a/radio/src/targets/sky9x/eeprom_driver.cpp b/radio/src/targets/sky9x/eeprom_driver.cpp index 2951573f1..de70c503a 100644 --- a/radio/src/targets/sky9x/eeprom_driver.cpp +++ b/radio/src/targets/sky9x/eeprom_driver.cpp @@ -1,200 +1,200 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -volatile uint8_t Spi_complete = 1; -uint8_t Spi_tx_buf[24]; - -uint8_t eepromIsTransferComplete() -{ - return Spi_complete; -} - -uint32_t eepromTransmitData(uint8_t *command, uint8_t *tx, uint8_t *rx, uint32_t comlen, uint32_t count) -{ - Spi * spiptr = SPI; - uint32_t condition; - static uint8_t discard_rx_command[4]; - - if (comlen > 4) { - return 0x4FFFF; - } - - Spi_complete = 0; - condition = SPI_SR_TXEMPTY; - spiptr->SPI_CR = 1; // Enable - (void) spiptr->SPI_RDR; // Dump any rx data - (void) spiptr->SPI_SR; // Clear error flags - spiptr->SPI_RPR = (uint32_t)discard_rx_command; - spiptr->SPI_RCR = comlen; - if (rx) { - spiptr->SPI_RNPR = (uint32_t)rx; - spiptr->SPI_RNCR = count; - condition = SPI_SR_RXBUFF; - } - spiptr->SPI_TPR = (uint32_t)command; - spiptr->SPI_TCR = comlen; - if (tx) { - spiptr->SPI_TNPR = (uint32_t)tx; - } - else { - spiptr->SPI_TNPR = (uint32_t)rx; - } - spiptr->SPI_TNCR = count; - - spiptr->SPI_PTCR = SPI_PTCR_RXTEN | SPI_PTCR_TXTEN; // Start transfers - - // Wait for things to get started, avoids early interrupt - for (count = 0; count < 1000; count += 1) { - if ((spiptr->SPI_SR & SPI_SR_TXEMPTY) == 0) - { - break; - } - } - spiptr->SPI_IER = condition; - - return 0; -} - -uint8_t eepromTransmitByte(uint8_t out, bool skipFirst) -{ - Spi * spiptr = SPI; - uint32_t delay; - - spiptr->SPI_CR = 1; // Enable - (void) spiptr->SPI_RDR; // Dump any rx data - - spiptr->SPI_TDR = out; - - delay = 0; - while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { - // wait for received - if (++delay > 10000) { - break; - } - } - - if (skipFirst) { - (void) spiptr->SPI_RDR; // Dump the rx data - spiptr->SPI_TDR = 0; - delay = 0; - while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { - // wait for received - if (++delay > 10000) { - break; - } - } - } - - spiptr->SPI_CR = 2; // Disable - return spiptr->SPI_RDR; -} - -enum EepromCommand { - COMMAND_WRITE_STATUS_REGISTER = 0x01, - COMMAND_BYTE_PROGRAM = 0x02, - COMMAND_READ_ARRAY = 0x03, - COMMAND_READ_STATUS = 0x05, - COMMAND_WRITE_ENABLE = 0x06, - COMMAND_BLOCK_ERASE = 0x20, -}; - -void eepromPrepareCommand(EepromCommand command, uint32_t address) -{ - uint8_t * p = Spi_tx_buf; - *p = command; - *(p+1) = address >> 16; - *(p+2) = address >> 8; - *(p+3) = address; -} - -uint8_t eepromReadStatus() -{ - uint8_t read_status = eepromTransmitByte(COMMAND_READ_STATUS, true); - return !(read_status & 1); -} - -void eepromWriteStatusRegister() -{ - eepromTransmitByte(COMMAND_WRITE_STATUS_REGISTER, true); -} - -void eepromWriteEnable() -{ - eepromTransmitByte(COMMAND_WRITE_ENABLE, false); -} - -void eepromStartWrite(uint8_t * buffer, size_t address, size_t size) -{ - eepromWriteEnable(); - eepromPrepareCommand(COMMAND_BYTE_PROGRAM, address); - eepromTransmitData(Spi_tx_buf, buffer, 0, 4, size); -} - -void eepromStartRead(uint8_t * buffer, size_t address, size_t size) -{ - eepromPrepareCommand(COMMAND_READ_ARRAY, address); - eepromTransmitData(Spi_tx_buf, 0, buffer, 4, size); -} - -void eepromBlockErase(uint32_t address) -{ - eepromWriteEnable(); - eepromPrepareCommand(COMMAND_BLOCK_ERASE, address); - eepromTransmitData(Spi_tx_buf, 0, 0, 4, 0); -} - -// SPI i/f to EEPROM (4Mb) -// Peripheral ID 21 (0x00200000) -// Connections: -// SS PA11 (peripheral A) -// MISO PA12 (peripheral A) -// MOSI PA13 (peripheral A) -// SCK PA14 (peripheral A) -// Set clock to 3 MHz, AT25 device is rated to 70MHz, 18MHz would be better -void eepromInit() -{ - Spi * spiptr = SPI; - uint32_t timer; - - PMC->PMC_PCER0 |= 0x00200000L; // Enable peripheral clock to SPI - /* Configure PIO */ - configure_pins(0x00007800, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP); - - timer = (Master_frequency / 3000000) << 8; // Baud rate 3Mb/s - spiptr->SPI_MR = 0x14000011; // 0001 0100 0000 0000 0000 0000 0001 0001 Master - spiptr->SPI_CSR[0] = 0x01180009 | timer; // 0000 0001 0001 1000 xxxx xxxx 0000 1001 - NVIC_EnableIRQ(SPI_IRQn); - - eepromWriteEnable(); - eepromWriteStatusRegister(); -} - -extern "C" void SPI_IRQHandler() -{ - Spi * spiptr = SPI; - SPI->SPI_IDR = 0x07FF; // All interrupts off - spiptr->SPI_CR = 2; // Disable - (void) spiptr->SPI_RDR; // Dump any rx data - (void) spiptr->SPI_SR; // Clear error flags - spiptr->SPI_PTCR = SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS; // Stop tramsfers - Spi_complete = 1; // Indicate completion -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +volatile uint8_t Spi_complete = 1; +uint8_t Spi_tx_buf[24]; + +uint8_t eepromIsTransferComplete() +{ + return Spi_complete; +} + +uint32_t eepromTransmitData(uint8_t *command, uint8_t *tx, uint8_t *rx, uint32_t comlen, uint32_t count) +{ + Spi * spiptr = SPI; + uint32_t condition; + static uint8_t discard_rx_command[4]; + + if (comlen > 4) { + return 0x4FFFF; + } + + Spi_complete = 0; + condition = SPI_SR_TXEMPTY; + spiptr->SPI_CR = 1; // Enable + (void) spiptr->SPI_RDR; // Dump any rx data + (void) spiptr->SPI_SR; // Clear error flags + spiptr->SPI_RPR = (uint32_t)discard_rx_command; + spiptr->SPI_RCR = comlen; + if (rx) { + spiptr->SPI_RNPR = (uint32_t)rx; + spiptr->SPI_RNCR = count; + condition = SPI_SR_RXBUFF; + } + spiptr->SPI_TPR = (uint32_t)command; + spiptr->SPI_TCR = comlen; + if (tx) { + spiptr->SPI_TNPR = (uint32_t)tx; + } + else { + spiptr->SPI_TNPR = (uint32_t)rx; + } + spiptr->SPI_TNCR = count; + + spiptr->SPI_PTCR = SPI_PTCR_RXTEN | SPI_PTCR_TXTEN; // Start transfers + + // Wait for things to get started, avoids early interrupt + for (count = 0; count < 1000; count += 1) { + if ((spiptr->SPI_SR & SPI_SR_TXEMPTY) == 0) + { + break; + } + } + spiptr->SPI_IER = condition; + + return 0; +} + +uint8_t eepromTransmitByte(uint8_t out, bool skipFirst) +{ + Spi * spiptr = SPI; + uint32_t delay; + + spiptr->SPI_CR = 1; // Enable + (void) spiptr->SPI_RDR; // Dump any rx data + + spiptr->SPI_TDR = out; + + delay = 0; + while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { + // wait for received + if (++delay > 10000) { + break; + } + } + + if (skipFirst) { + (void) spiptr->SPI_RDR; // Dump the rx data + spiptr->SPI_TDR = 0; + delay = 0; + while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { + // wait for received + if (++delay > 10000) { + break; + } + } + } + + spiptr->SPI_CR = 2; // Disable + return spiptr->SPI_RDR; +} + +enum EepromCommand { + COMMAND_WRITE_STATUS_REGISTER = 0x01, + COMMAND_BYTE_PROGRAM = 0x02, + COMMAND_READ_ARRAY = 0x03, + COMMAND_READ_STATUS = 0x05, + COMMAND_WRITE_ENABLE = 0x06, + COMMAND_BLOCK_ERASE = 0x20, +}; + +void eepromPrepareCommand(EepromCommand command, uint32_t address) +{ + uint8_t * p = Spi_tx_buf; + *p = command; + *(p+1) = address >> 16; + *(p+2) = address >> 8; + *(p+3) = address; +} + +uint8_t eepromReadStatus() +{ + uint8_t read_status = eepromTransmitByte(COMMAND_READ_STATUS, true); + return !(read_status & 1); +} + +void eepromWriteStatusRegister() +{ + eepromTransmitByte(COMMAND_WRITE_STATUS_REGISTER, true); +} + +void eepromWriteEnable() +{ + eepromTransmitByte(COMMAND_WRITE_ENABLE, false); +} + +void eepromStartWrite(uint8_t * buffer, size_t address, size_t size) +{ + eepromWriteEnable(); + eepromPrepareCommand(COMMAND_BYTE_PROGRAM, address); + eepromTransmitData(Spi_tx_buf, buffer, 0, 4, size); +} + +void eepromStartRead(uint8_t * buffer, size_t address, size_t size) +{ + eepromPrepareCommand(COMMAND_READ_ARRAY, address); + eepromTransmitData(Spi_tx_buf, 0, buffer, 4, size); +} + +void eepromBlockErase(uint32_t address) +{ + eepromWriteEnable(); + eepromPrepareCommand(COMMAND_BLOCK_ERASE, address); + eepromTransmitData(Spi_tx_buf, 0, 0, 4, 0); +} + +// SPI i/f to EEPROM (4Mb) +// Peripheral ID 21 (0x00200000) +// Connections: +// SS PA11 (peripheral A) +// MISO PA12 (peripheral A) +// MOSI PA13 (peripheral A) +// SCK PA14 (peripheral A) +// Set clock to 3 MHz, AT25 device is rated to 70MHz, 18MHz would be better +void eepromInit() +{ + Spi * spiptr = SPI; + uint32_t timer; + + PMC->PMC_PCER0 |= 0x00200000L; // Enable peripheral clock to SPI + /* Configure PIO */ + configure_pins(0x00007800, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP); + + timer = (Master_frequency / 3000000) << 8; // Baud rate 3Mb/s + spiptr->SPI_MR = 0x14000011; // 0001 0100 0000 0000 0000 0000 0001 0001 Master + spiptr->SPI_CSR[0] = 0x01180009 | timer; // 0000 0001 0001 1000 xxxx xxxx 0000 1001 + NVIC_EnableIRQ(SPI_IRQn); + + eepromWriteEnable(); + eepromWriteStatusRegister(); +} + +extern "C" void SPI_IRQHandler() +{ + Spi * spiptr = SPI; + SPI->SPI_IDR = 0x07FF; // All interrupts off + spiptr->SPI_CR = 2; // Disable + (void) spiptr->SPI_RDR; // Dump any rx data + (void) spiptr->SPI_SR; // Clear error flags + spiptr->SPI_PTCR = SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS; // Stop tramsfers + Spi_complete = 1; // Indicate completion +} diff --git a/radio/src/targets/sky9x/haptic_driver.cpp b/radio/src/targets/sky9x/haptic_driver.cpp index f6b50b2e1..efa42730e 100644 --- a/radio/src/targets/sky9x/haptic_driver.cpp +++ b/radio/src/targets/sky9x/haptic_driver.cpp @@ -1,44 +1,44 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void hapticOff() -{ - PWM->PWM_DIS = PWM_DIS_CHID2 ; // Disable channel 2 - PWM->PWM_OOV &= ~0x00040000 ; // Force low - PWM->PWM_OSS |= 0x00040000 ; // Force low -} - -// pwmPercent 0-100 -void hapticOn( uint32_t pwmPercent ) -{ - Pwm *pwmptr ; - - pwmptr = PWM ; - - if (pwmPercent > 100) { - pwmPercent = 100 ; - } - - pwmptr->PWM_CH_NUM[2].PWM_CDTYUPD = pwmPercent ; // Duty - pwmptr->PWM_ENA = PWM_ENA_CHID2 ; // Enable channel 2 - pwmptr->PWM_OSC = 0x00040000 ; // Enable output -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +void hapticOff() +{ + PWM->PWM_DIS = PWM_DIS_CHID2 ; // Disable channel 2 + PWM->PWM_OOV &= ~0x00040000 ; // Force low + PWM->PWM_OSS |= 0x00040000 ; // Force low +} + +// pwmPercent 0-100 +void hapticOn( uint32_t pwmPercent ) +{ + Pwm *pwmptr ; + + pwmptr = PWM ; + + if (pwmPercent > 100) { + pwmPercent = 100 ; + } + + pwmptr->PWM_CH_NUM[2].PWM_CDTYUPD = pwmPercent ; // Duty + pwmptr->PWM_ENA = PWM_ENA_CHID2 ; // Enable channel 2 + pwmptr->PWM_OSC = 0x00040000 ; // Enable output +} diff --git a/radio/src/targets/sky9x/keys_driver.cpp b/radio/src/targets/sky9x/keys_driver.cpp index 9d999d33f..6ef1efabf 100644 --- a/radio/src/targets/sky9x/keys_driver.cpp +++ b/radio/src/targets/sky9x/keys_driver.cpp @@ -1,197 +1,197 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - - -// keys: -// KEY_EXIT PA31 (PC24) -// KEY_MENU PB6 (PB5) -// KEY_DOWN LCD5 PC3 (PC5) -// KEY_UP LCD6 PC2 (PC1) -// KEY_RIGHT LCD4 PC4 (PC4) -// KEY_LEFT LCD3 PC5 (PC3) -// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU -// LCD pins 5 DOWN, 4 RIGHT, 3 LEFT, 1 UP -uint32_t readKeys() -{ - uint32_t x; - uint32_t result = 0; - - x = lcdLock ? lcdInputs : PIOC->PIO_PDSR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - x = ~x; - -#if defined(REVA) - if (x & KEYS_GPIO_PIN_RIGHT) - result |= 0x02 << KEY_RIGHT; - if (x & KEYS_GPIO_PIN_LEFT) - result |= 0x02 << KEY_LEFT; - if (x & KEYS_GPIO_PIN_UP) - result |= 0x02 << KEY_UP; - if (x & KEYS_GPIO_PIN_DOWN) - result |= 0x02 << KEY_DOWN; - if (~KEYS_GPIO_REG_EXIT & KEYS_GPIO_PIN_EXIT) - result |= 0x02 << KEY_EXIT; - if (~KEYS_GPIO_REG_MENU & KEYS_GPIO_PIN_MENU) - result |= 0x02 << KEY_MENU; -#else - if (x & KEYS_GPIO_PIN_RIGHT) - result |= 0x02 << KEY_RIGHT; - if (x & KEYS_GPIO_PIN_UP) - result |= 0x02 << KEY_UP; - if (x & KEYS_GPIO_PIN_LEFT) - result |= 0x02 << KEY_LEFT; - if (x & KEYS_GPIO_PIN_DOWN) - result |= 0x02 << KEY_DOWN; - if (x & KEYS_GPIO_PIN_EXIT) - result |= 0x02 << KEY_EXIT; - if (~KEYS_GPIO_REG_MENU & KEYS_GPIO_PIN_MENU) - result |= 0x02 << KEY_MENU; -#endif - - // TRACE("readKeys(): %x => %x", x, result); - - return result; -} - -uint32_t readTrims() -{ - uint32_t result = 0; - - if (~TRIMS_GPIO_REG_LHL & TRIMS_GPIO_PIN_LHL) - result |= 0x01; - if (~TRIMS_GPIO_REG_LVD & TRIMS_GPIO_PIN_LVD) - result |= 0x04; - if (~TRIMS_GPIO_REG_RVU & TRIMS_GPIO_PIN_RVU) - result |= 0x20; - if (~TRIMS_GPIO_REG_RHL & TRIMS_GPIO_PIN_RHL) - result |= 0x40; - if (~TRIMS_GPIO_REG_LHR & TRIMS_GPIO_PIN_LHR) - result |= 0x02; - if (~TRIMS_GPIO_REG_LVU & TRIMS_GPIO_PIN_LVU) - result |= 0x08; - if (~TRIMS_GPIO_REG_RVD & TRIMS_GPIO_PIN_RVD) - result |= 0x10; - if (~TRIMS_GPIO_REG_RHR & TRIMS_GPIO_PIN_RHR) - result |= 0x80; - - return result; -} - -uint8_t trimDown(uint8_t idx) -{ - return readTrims() & (1 << idx); -} - -uint8_t keyDown() -{ - return readKeys() || REA_DOWN(); -} - -void readKeysAndTrims() -{ - uint32_t i; - -#if ROTARY_ENCODERS > 0 - keys[BTN_REa].input(REA_DOWN()); -#endif - - uint8_t index = KEY_MENU; - uint8_t in = readKeys(); - for (i = 1; i < 7; i++) { - keys[index].input(in & (1 << i)); - ++index; - } - - in = readTrims(); - - for (i = 1; i < 256; i <<= 1) { - keys[index].input(in & i); - ++index; - } -} - -uint8_t keyState(uint8_t index) -{ - return keys[index].state(); -} - -uint32_t switchState(uint8_t index) -{ - uint32_t a = PIOA->PIO_PDSR; - uint32_t c = PIOC->PIO_PDSR; - - uint32_t xxx = 0; - - switch (index) { -#if defined(REVA) - case SW_ELE: - xxx = a & 0x00000100; // ELE_DR PA8 -#else - case SW_ELE: - xxx = c & 0x80000000; // ELE_DR PC31 -#endif - break; - - case SW_AIL: - xxx = a & 0x00000004; // AIL-DR PA2 - break; - - case SW_RUD: - xxx = a & 0x00008000; // RUN_DR PA15 - break; - // INP_G_ID1 INP_E_ID2 - // id0 0 1 - // id1 1 1 - // id2 1 0 - case SW_ID0: - xxx = ~c & 0x00004000; // SW_IDL1 PC14 - break; - case SW_ID1: - xxx = (c & 0x00004000); - if (xxx) xxx = (c & 0x00000800); - break; - case SW_ID2: - xxx = ~c & 0x00000800; // SW_IDL2 PC11 - break; - - case SW_GEA: - xxx = c & 0x00010000; // SW_GEAR PC16 - break; - -#if defined(REVA) - case SW_THR: - xxx = a & 0x10000000; // SW_TCUT PA28 -#else - case SW_THR: - xxx = c & 0x00100000; // SW_TCUT PC20 -#endif - break; - - case SW_TRN: - xxx = c & 0x00000100; // SW-TRAIN PC8 - break; - - default: - break; - } - - return xxx; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + + +// keys: +// KEY_EXIT PA31 (PC24) +// KEY_MENU PB6 (PB5) +// KEY_DOWN LCD5 PC3 (PC5) +// KEY_UP LCD6 PC2 (PC1) +// KEY_RIGHT LCD4 PC4 (PC4) +// KEY_LEFT LCD3 PC5 (PC3) +// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU +// LCD pins 5 DOWN, 4 RIGHT, 3 LEFT, 1 UP +uint32_t readKeys() +{ + uint32_t x; + uint32_t result = 0; + + x = lcdLock ? lcdInputs : PIOC->PIO_PDSR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () + x = ~x; + +#if defined(REVA) + if (x & KEYS_GPIO_PIN_RIGHT) + result |= 0x02 << KEY_RIGHT; + if (x & KEYS_GPIO_PIN_LEFT) + result |= 0x02 << KEY_LEFT; + if (x & KEYS_GPIO_PIN_UP) + result |= 0x02 << KEY_UP; + if (x & KEYS_GPIO_PIN_DOWN) + result |= 0x02 << KEY_DOWN; + if (~KEYS_GPIO_REG_EXIT & KEYS_GPIO_PIN_EXIT) + result |= 0x02 << KEY_EXIT; + if (~KEYS_GPIO_REG_MENU & KEYS_GPIO_PIN_MENU) + result |= 0x02 << KEY_MENU; +#else + if (x & KEYS_GPIO_PIN_RIGHT) + result |= 0x02 << KEY_RIGHT; + if (x & KEYS_GPIO_PIN_UP) + result |= 0x02 << KEY_UP; + if (x & KEYS_GPIO_PIN_LEFT) + result |= 0x02 << KEY_LEFT; + if (x & KEYS_GPIO_PIN_DOWN) + result |= 0x02 << KEY_DOWN; + if (x & KEYS_GPIO_PIN_EXIT) + result |= 0x02 << KEY_EXIT; + if (~KEYS_GPIO_REG_MENU & KEYS_GPIO_PIN_MENU) + result |= 0x02 << KEY_MENU; +#endif + + // TRACE("readKeys(): %x => %x", x, result); + + return result; +} + +uint32_t readTrims() +{ + uint32_t result = 0; + + if (~TRIMS_GPIO_REG_LHL & TRIMS_GPIO_PIN_LHL) + result |= 0x01; + if (~TRIMS_GPIO_REG_LVD & TRIMS_GPIO_PIN_LVD) + result |= 0x04; + if (~TRIMS_GPIO_REG_RVU & TRIMS_GPIO_PIN_RVU) + result |= 0x20; + if (~TRIMS_GPIO_REG_RHL & TRIMS_GPIO_PIN_RHL) + result |= 0x40; + if (~TRIMS_GPIO_REG_LHR & TRIMS_GPIO_PIN_LHR) + result |= 0x02; + if (~TRIMS_GPIO_REG_LVU & TRIMS_GPIO_PIN_LVU) + result |= 0x08; + if (~TRIMS_GPIO_REG_RVD & TRIMS_GPIO_PIN_RVD) + result |= 0x10; + if (~TRIMS_GPIO_REG_RHR & TRIMS_GPIO_PIN_RHR) + result |= 0x80; + + return result; +} + +uint8_t trimDown(uint8_t idx) +{ + return readTrims() & (1 << idx); +} + +uint8_t keyDown() +{ + return readKeys() || REA_DOWN(); +} + +void readKeysAndTrims() +{ + uint32_t i; + +#if ROTARY_ENCODERS > 0 + keys[BTN_REa].input(REA_DOWN()); +#endif + + uint8_t index = KEY_MENU; + uint8_t in = readKeys(); + for (i = 1; i < 7; i++) { + keys[index].input(in & (1 << i)); + ++index; + } + + in = readTrims(); + + for (i = 1; i < 256; i <<= 1) { + keys[index].input(in & i); + ++index; + } +} + +uint8_t keyState(uint8_t index) +{ + return keys[index].state(); +} + +uint32_t switchState(uint8_t index) +{ + uint32_t a = PIOA->PIO_PDSR; + uint32_t c = PIOC->PIO_PDSR; + + uint32_t xxx = 0; + + switch (index) { +#if defined(REVA) + case SW_ELE: + xxx = a & 0x00000100; // ELE_DR PA8 +#else + case SW_ELE: + xxx = c & 0x80000000; // ELE_DR PC31 +#endif + break; + + case SW_AIL: + xxx = a & 0x00000004; // AIL-DR PA2 + break; + + case SW_RUD: + xxx = a & 0x00008000; // RUN_DR PA15 + break; + // INP_G_ID1 INP_E_ID2 + // id0 0 1 + // id1 1 1 + // id2 1 0 + case SW_ID0: + xxx = ~c & 0x00004000; // SW_IDL1 PC14 + break; + case SW_ID1: + xxx = (c & 0x00004000); + if (xxx) xxx = (c & 0x00000800); + break; + case SW_ID2: + xxx = ~c & 0x00000800; // SW_IDL2 PC11 + break; + + case SW_GEA: + xxx = c & 0x00010000; // SW_GEAR PC16 + break; + +#if defined(REVA) + case SW_THR: + xxx = a & 0x10000000; // SW_TCUT PA28 +#else + case SW_THR: + xxx = c & 0x00100000; // SW_TCUT PC20 +#endif + break; + + case SW_TRN: + xxx = c & 0x00000100; // SW-TRAIN PC8 + break; + + default: + break; + } + + return xxx; +} diff --git a/radio/src/targets/sky9x/massstorage.cpp b/radio/src/targets/sky9x/massstorage.cpp index ce18cca83..613bc2a73 100644 --- a/radio/src/targets/sky9x/massstorage.cpp +++ b/radio/src/targets/sky9x/massstorage.cpp @@ -1,208 +1,208 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#ifndef SIMU - -extern "C" { -#include "usb/device/massstorage/MSDDriver.h" -extern unsigned char MEDSdcard_Initialize(Media *media, unsigned char mciID); -} - -/** LUN read/write buffer. */ -unsigned char msdBuffer[MSD_BUFFER_SIZE]; - -unsigned int msdReadTotal=0, msdWriteTotal=0; - -static void ConfigureUsbClock(void) -{ - /* Enable PLLB for USB */ - PMC->CKGR_PLLBR = CKGR_PLLBR_DIVB(1) - | CKGR_PLLBR_MULB(7) - | CKGR_PLLBR_PLLBCOUNT_Msk; - while((PMC->PMC_SR & PMC_SR_LOCKB) == 0); // TODO && (timeout++ < CLOCK_TIMEOUT)); - /* USB Clock uses PLLB */ - PMC->PMC_USB = PMC_USB_USBDIV(1) /* /2 */ - | PMC_USB_USBS; /* PLLB */ -} - -/** Maximum number of LUNs which can be defined. */ -#define MAX_LUNS 1 - -/** Media index for different disks */ -#define DRV_SDMMC 0 /** SD card */ - -Media medias[MAX_LUNS]; - -/*---------------------------------------------------------------------------- - * Local variables - *----------------------------------------------------------------------------*/ - -/** Device LUNs. */ -MSDLun luns[MAX_LUNS]; - -int itoa(int val, char* buf) -{ - const unsigned int radix = 10; - - char* p; - unsigned int a; //every digit - int len; - char* b; //start of the digit char - char temp; - unsigned int u; - - p = buf; - -#if 0 - if (val < 0) - { - *p++ = '-'; - val = 0 - val; - } -#endif - - u = (unsigned int)val; - - b = p; - - do - { - a = u % radix; - u /= radix; - - *p++ = a + '0'; - - } while (u > 0); - - len = (int)(p - buf); - - *p-- = 0; - - //swap - do - { - temp = *p; - *p = *b; - *b = temp; - --p; - ++b; - - } while (b < p); - - return len; -} - -uint8_t write_bytes(char *str, uint32_t bytes) -{ - uint8_t len; - if (bytes < 1024*100) { - len = itoa(bytes / 1024, str); - str[len] = '.'; - str[len+1] = '0' + ((bytes % 1024) / 103); - str[len+2] = 'K'; - str[len+3] = '\0'; - len += 3; - } - else if (bytes < 1024*1024) { - len = itoa(bytes / 1024, str); - str[len] = 'K'; - str[len+1] = '\0'; - len += 1; - } - else if (bytes < 1024*1024*100) { - len = itoa(bytes / (1024*1024), str); - str[len] = '.'; - str[len+1] = '0' + ((bytes % (1024*1024)) / 104858); - str[len+2] = 'M'; - str[len+3] = '\0'; - len += 3; - } - else { - len = itoa(bytes / (1024*1024), str); - str[len] = 'M'; - str[len+1] = '\0'; - len += 1; - } - return len; -} - -static void MSDCallbacks_Data( unsigned char flowDirection, unsigned int dataLength, - unsigned int fifoNullCount, unsigned int fifoFullCount ) -{ - if (flowDirection) - msdReadTotal += dataLength; - else - msdWriteTotal += dataLength; - - strcpy(statusLineMsg, "USB Rd:"); - uint8_t len = write_bytes(statusLineMsg+7, msdReadTotal); - strcpy(statusLineMsg+7+len, " Wr:"); - write_bytes(statusLineMsg+7+len+4, msdWriteTotal); - showStatusLine(); -} - -void usbMassStorage() -{ - static bool initialized = false; - - if (usbPlugged() && sd_card_ready()) { - TRACE_DEBUG("usbMassStorage\n\r"); - - if (sdMounted()) { - Card_state = SD_ST_DATA; - audioQueue.stopSD(); - logsClose(); - f_mount(NULL, "", 0); // unmount SD - } - - if (!initialized) { - - ConfigureUsbClock(); - - /* Initialize LUN */ - MEDSdcard_Initialize(&(medias[DRV_SDMMC]), 0); - - LUN_Init(&(luns[DRV_SDMMC]), &(medias[DRV_SDMMC]), - msdBuffer, MSD_BUFFER_SIZE, - 0, 0, 0, 0, - MSDCallbacks_Data); - - /* BOT driver initialization */ - MSDDriver_Initialize(luns, 1); - - // VBus_Configure(); - USBD_Connect(); - - initialized = true; - } - - /* Mass storage state machine */ - for (uint8_t i=0; i<50; i++) - MSDDriver_StateMachine(); - } - else { - msdReadTotal = 0; - msdWriteTotal = 0; - } -} - -#endif +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#ifndef SIMU + +extern "C" { +#include "usb/device/massstorage/MSDDriver.h" +extern unsigned char MEDSdcard_Initialize(Media *media, unsigned char mciID); +} + +/** LUN read/write buffer. */ +unsigned char msdBuffer[MSD_BUFFER_SIZE]; + +unsigned int msdReadTotal=0, msdWriteTotal=0; + +static void ConfigureUsbClock(void) +{ + /* Enable PLLB for USB */ + PMC->CKGR_PLLBR = CKGR_PLLBR_DIVB(1) + | CKGR_PLLBR_MULB(7) + | CKGR_PLLBR_PLLBCOUNT_Msk; + while((PMC->PMC_SR & PMC_SR_LOCKB) == 0); // TODO && (timeout++ < CLOCK_TIMEOUT)); + /* USB Clock uses PLLB */ + PMC->PMC_USB = PMC_USB_USBDIV(1) /* /2 */ + | PMC_USB_USBS; /* PLLB */ +} + +/** Maximum number of LUNs which can be defined. */ +#define MAX_LUNS 1 + +/** Media index for different disks */ +#define DRV_SDMMC 0 /** SD card */ + +Media medias[MAX_LUNS]; + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/** Device LUNs. */ +MSDLun luns[MAX_LUNS]; + +int itoa(int val, char* buf) +{ + const unsigned int radix = 10; + + char* p; + unsigned int a; //every digit + int len; + char* b; //start of the digit char + char temp; + unsigned int u; + + p = buf; + +#if 0 + if (val < 0) + { + *p++ = '-'; + val = 0 - val; + } +#endif + + u = (unsigned int)val; + + b = p; + + do + { + a = u % radix; + u /= radix; + + *p++ = a + '0'; + + } while (u > 0); + + len = (int)(p - buf); + + *p-- = 0; + + //swap + do + { + temp = *p; + *p = *b; + *b = temp; + --p; + ++b; + + } while (b < p); + + return len; +} + +uint8_t write_bytes(char *str, uint32_t bytes) +{ + uint8_t len; + if (bytes < 1024*100) { + len = itoa(bytes / 1024, str); + str[len] = '.'; + str[len+1] = '0' + ((bytes % 1024) / 103); + str[len+2] = 'K'; + str[len+3] = '\0'; + len += 3; + } + else if (bytes < 1024*1024) { + len = itoa(bytes / 1024, str); + str[len] = 'K'; + str[len+1] = '\0'; + len += 1; + } + else if (bytes < 1024*1024*100) { + len = itoa(bytes / (1024*1024), str); + str[len] = '.'; + str[len+1] = '0' + ((bytes % (1024*1024)) / 104858); + str[len+2] = 'M'; + str[len+3] = '\0'; + len += 3; + } + else { + len = itoa(bytes / (1024*1024), str); + str[len] = 'M'; + str[len+1] = '\0'; + len += 1; + } + return len; +} + +static void MSDCallbacks_Data( unsigned char flowDirection, unsigned int dataLength, + unsigned int fifoNullCount, unsigned int fifoFullCount ) +{ + if (flowDirection) + msdReadTotal += dataLength; + else + msdWriteTotal += dataLength; + + strcpy(statusLineMsg, "USB Rd:"); + uint8_t len = write_bytes(statusLineMsg+7, msdReadTotal); + strcpy(statusLineMsg+7+len, " Wr:"); + write_bytes(statusLineMsg+7+len+4, msdWriteTotal); + showStatusLine(); +} + +void usbMassStorage() +{ + static bool initialized = false; + + if (usbPlugged() && sd_card_ready()) { + TRACE_DEBUG("usbMassStorage\n\r"); + + if (sdMounted()) { + Card_state = SD_ST_DATA; + audioQueue.stopSD(); + logsClose(); + f_mount(NULL, "", 0); // unmount SD + } + + if (!initialized) { + + ConfigureUsbClock(); + + /* Initialize LUN */ + MEDSdcard_Initialize(&(medias[DRV_SDMMC]), 0); + + LUN_Init(&(luns[DRV_SDMMC]), &(medias[DRV_SDMMC]), + msdBuffer, MSD_BUFFER_SIZE, + 0, 0, 0, 0, + MSDCallbacks_Data); + + /* BOT driver initialization */ + MSDDriver_Initialize(luns, 1); + + // VBus_Configure(); + USBD_Connect(); + + initialized = true; + } + + /* Mass storage state machine */ + for (uint8_t i=0; i<50; i++) + MSDDriver_StateMachine(); + } + else { + msdReadTotal = 0; + msdWriteTotal = 0; + } +} + +#endif diff --git a/radio/src/targets/sky9x/pulses_driver.cpp b/radio/src/targets/sky9x/pulses_driver.cpp index 08ea1f630..3557ab906 100644 --- a/radio/src/targets/sky9x/pulses_driver.cpp +++ b/radio/src/targets/sky9x/pulses_driver.cpp @@ -1,367 +1,367 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void setExternalModulePolarity() -{ - Pwm * pwmptr = PWM; - pwmptr->PWM_CH_NUM[3].PWM_CDTYUPD = GET_PPM_DELAY(EXTERNAL_MODULE) * 2; // Duty in half uS - if (GET_PPM_POLARITY(EXTERNAL_MODULE)) - pwmptr->PWM_CH_NUM[3].PWM_CMR &= ~0x00000200; // CPOL - else - pwmptr->PWM_CH_NUM[3].PWM_CMR |= 0x00000200; // CPOL -} - -void setExtraModulePolarity() -{ - Pwm * pwmptr = PWM; - pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = GET_PPM_DELAY(EXTRA_MODULE) * 2; // Duty in half uS - if (GET_PPM_POLARITY(EXTRA_MODULE)) - pwmptr->PWM_CH_NUM[1].PWM_CMR &= ~0x00000200; // CPOL - else - pwmptr->PWM_CH_NUM[1].PWM_CMR |= 0x00000200; // CPOL -} - -void module_output_active() -{ - Pio *pioptr = PIOA; - pioptr->PIO_ABCDSR[0] &= ~PIO_PA17; // Peripheral C - pioptr->PIO_ABCDSR[1] |= PIO_PA17; // Peripheral C - pioptr->PIO_PDR = PIO_PA17; // Disable bit A17 Assign to peripheral -#if defined(REVX) - if (g_model.moduleData[EXTERNAL_MODULE].ppm.outputType) { - pioptr->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 - } - else { +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +void setExternalModulePolarity() +{ + Pwm * pwmptr = PWM; + pwmptr->PWM_CH_NUM[3].PWM_CDTYUPD = GET_PPM_DELAY(EXTERNAL_MODULE) * 2; // Duty in half uS + if (GET_PPM_POLARITY(EXTERNAL_MODULE)) + pwmptr->PWM_CH_NUM[3].PWM_CMR &= ~0x00000200; // CPOL + else + pwmptr->PWM_CH_NUM[3].PWM_CMR |= 0x00000200; // CPOL +} + +void setExtraModulePolarity() +{ + Pwm * pwmptr = PWM; + pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = GET_PPM_DELAY(EXTRA_MODULE) * 2; // Duty in half uS + if (GET_PPM_POLARITY(EXTRA_MODULE)) + pwmptr->PWM_CH_NUM[1].PWM_CMR &= ~0x00000200; // CPOL + else + pwmptr->PWM_CH_NUM[1].PWM_CMR |= 0x00000200; // CPOL +} + +void module_output_active() +{ + Pio *pioptr = PIOA; + pioptr->PIO_ABCDSR[0] &= ~PIO_PA17; // Peripheral C + pioptr->PIO_ABCDSR[1] |= PIO_PA17; // Peripheral C + pioptr->PIO_PDR = PIO_PA17; // Disable bit A17 Assign to peripheral +#if defined(REVX) + if (g_model.moduleData[EXTERNAL_MODULE].ppm.outputType) { + pioptr->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 + } + else { pioptr->PIO_MDER = PIO_PA17; // Open Drain O/p in A17 - } -#else - pioptr->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 -#endif - pioptr->PIO_PUER = PIO_PA17; // With pull up -} - -void init_main_ppm(uint32_t period, uint32_t out_enable) -{ - Pwm * pwmptr; - - setupPulsesPPMModule(EXTERNAL_MODULE); - - if (out_enable) { - module_output_active(); - } - - pwmptr = PWM; - // PWM3 for PPM output - pwmptr->PWM_CH_NUM[3].PWM_CMR = 0x0004000B; // CLKA - pwmptr->PWM_CH_NUM[3].PWM_CPDR = period; // Period in half uS - pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS - pwmptr->PWM_CH_NUM[3].PWM_CDTY = GET_PPM_DELAY(EXTERNAL_MODULE) * 2; // Duty in half uS - pwmptr->PWM_ENA = PWM_ENA_CHID3; // Enable channel 3 - pwmptr->PWM_IER1 = PWM_IER1_CHID3; - - setExternalModulePolarity(); - - NVIC_SetPriority(PWM_IRQn, 3); - NVIC_EnableIRQ(PWM_IRQn); -} - -void disable_main_ppm() -{ - Pio * pioptr = PIOA; - pioptr->PIO_PER = PIO_PA17; // Assign A17 to PIO - PWM->PWM_IDR1 = PWM_IDR1_CHID3; -} - -void init_second_ppm(uint32_t period) -{ -#if !defined(REVA) - // PWM1 for PPM2 - Pwm * pwmptr = PWM; - configure_pins(PIO_PC15, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP); - pwmptr->PWM_CH_NUM[1].PWM_CMR = 0x0000000B; // CLKB - if (!GET_PPM_POLARITY(EXTRA_MODULE)) { - pwmptr->PWM_CH_NUM[1].PWM_CMR |= 0x00000200; // CPOL - } - pwmptr->PWM_CH_NUM[1].PWM_CPDR = period; // Period - pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = period; // Period - pwmptr->PWM_CH_NUM[1].PWM_CDTY = GET_PPM_DELAY(EXTRA_MODULE)*2; // Duty - pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = GET_PPM_DELAY(EXTRA_MODULE)*2; // Duty - pwmptr->PWM_ENA = PWM_ENA_CHID1; // Enable channel 1 - pwmptr->PWM_IER1 = PWM_IER1_CHID1; -#endif -} - -void disable_second_ppm() -{ -#if !defined(REVA) - Pio * pioptr = PIOC; - pioptr->PIO_PER = PIO_PC15; // Assign C17 to PIO - PWM->PWM_IDR1 = PWM_IDR1_CHID1; -#endif -} - -void init_no_pulses(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - init_main_ppm(3000, 0); - } - else { - // TODO - } -} - -void disable_no_pulses(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - disable_ppm(EXTERNAL_MODULE); - } - else { - // TODO - } -} - -void init_ppm(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - init_main_ppm(3000, 1); - } - else { - init_second_ppm(3000); - } -} - -void disable_ppm(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - disable_main_ppm(); - } - else { - disable_second_ppm(); - } -} - -// Initialise the SSC to allow PXX output. -// TD is on PA17, peripheral A -void init_ssc(uint8_t baudrateDiv1000) -{ - Ssc *sscptr; - - PMC->PMC_PCER0 |= 0x00400000L; // Enable peripheral clock to SSC - - configure_pins(PIO_PA17, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA); - - sscptr = SSC; - sscptr->SSC_THR = 0xFF; // Make the output high. - sscptr->SSC_TFMR = 0x00000027; // 0000 0000 0000 0000 0000 0000 1010 0111 (8 bit data, lsb) - sscptr->SSC_CMR = Master_frequency / (1000 * baudrateDiv1000 * 2); - sscptr->SSC_TCMR = 0; - sscptr->SSC_CR = SSC_CR_TXEN; - -#if defined(REVX) - if (IS_MODULE_MULTIMODULE(EXTERNAL_MODULE)) { - PIOA->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 - } else { - PIOA->PIO_MDER = PIO_PA17; // Open Drain O/p in A17 - } -#else - PIOA->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 -#endif -} - -void disable_ssc() -{ - Pio *pioptr; - Ssc *sscptr; - - // Revert back to pwm output - pioptr = PIOA; - pioptr->PIO_PER = PIO_PA17; // Assign A17 to PIO - - sscptr = SSC; - sscptr->SSC_CR = SSC_CR_TXDIS; -} - -void init_pxx(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - init_main_ppm(2500 * 2, 0); - init_ssc(125); // 8us per bit - } - else { - // TODO - } -} - -void disable_pxx(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - disable_ssc(); - disable_ppm(EXTERNAL_MODULE); - } - else { - // TODO - } -} - -void init_dsm2(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - init_main_ppm(2500 * 2, 0); - init_ssc(125); - } - else { - // TODO - } -} - -void disable_dsm2(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - disable_ssc(); - disable_ppm(EXTERNAL_MODULE); - } - else { - // TODO - } -} - -#if defined(MULTIMODULE) -void init_multimodule(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - init_main_ppm(3500 * 2, 0); - init_ssc(100); - } - else { - // TODO - } -} - -void disable_multimodule(uint32_t port) -{ - disable_dsm2(port); -} -#endif - -#if !defined(SIMU) -extern "C" void PWM_IRQHandler(void) -{ - Pwm * pwmptr = PWM; - uint32_t reason = pwmptr->PWM_ISR1; - uint32_t period; - - if (reason & PWM_ISR1_CHID3) { - // Use the current protocol, don't switch until set_up_pulses - switch (s_current_protocol[EXTERNAL_MODULE]) { - case PROTO_PXX: - // Alternate periods of 6.5mS and 2.5 mS - period = pwmptr->PWM_CH_NUM[3].PWM_CPDR; - if (period == 2500 * 2) { - period = 6500 * 2; - } - else { - period = 2500 * 2; - } - pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS - if (period != 2500 * 2) { - setupPulses(EXTERNAL_MODULE); - setExternalModulePolarity(); - } - else { - // Kick off serial output here - Ssc * sscptr = SSC; - sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].pxx.pulses); - sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].pxx.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].pxx.pulses; - sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers - } - break; - - case PROTO_DSM2_LP45: - case PROTO_DSM2_DSM2: - case PROTO_DSM2_DSMX: - // Alternate periods of 19.5mS and 2.5 mS - period = pwmptr->PWM_CH_NUM[3].PWM_CPDR; - if (period == 2500 * 2) { - period = 19500 * 2; - } - else { - period = 2500 * 2; - } - pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS - if (period != 2500 * 2) { - setupPulses(EXTERNAL_MODULE); - } - else { - // Kick off serial output here - Ssc * sscptr = SSC; - sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses); - sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.pulses; - sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers - } - break; - -#if defined(MULTIMODULE) - case PROTO_MULTIMODULE: - // Alternate periods of 5.5mS and 3.5 mS - period = pwmptr->PWM_CH_NUM[3].PWM_CPDR; - if (period == 3500 * 2) { - period = 5500 * 2; - } - else { - period = 3500 * 2; - } - pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS - if (period != 3500 * 2) { - setupPulses(EXTERNAL_MODULE); - } - else { - // Kick off serial output here - Ssc * sscptr = SSC; - sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses); - sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.pulses; - sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers - } - break; -#endif - - default: - pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++; - if (*modulePulsesData[EXTERNAL_MODULE].ppm.ptr == 0) { - setExternalModulePolarity(); - setupPulses(EXTERNAL_MODULE); - } - break; - - } - } - -#if !defined(REVA) - if (reason & PWM_ISR1_CHID1) { - pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = *modulePulsesData[EXTRA_MODULE].ppm.ptr++; - if (*modulePulsesData[EXTRA_MODULE].ppm.ptr == 0) { - setupPulsesPPMModule(EXTRA_MODULE); - setExtraModulePolarity(); - } - } -#endif -} -#endif + } +#else + pioptr->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 +#endif + pioptr->PIO_PUER = PIO_PA17; // With pull up +} + +void init_main_ppm(uint32_t period, uint32_t out_enable) +{ + Pwm * pwmptr; + + setupPulsesPPMModule(EXTERNAL_MODULE); + + if (out_enable) { + module_output_active(); + } + + pwmptr = PWM; + // PWM3 for PPM output + pwmptr->PWM_CH_NUM[3].PWM_CMR = 0x0004000B; // CLKA + pwmptr->PWM_CH_NUM[3].PWM_CPDR = period; // Period in half uS + pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS + pwmptr->PWM_CH_NUM[3].PWM_CDTY = GET_PPM_DELAY(EXTERNAL_MODULE) * 2; // Duty in half uS + pwmptr->PWM_ENA = PWM_ENA_CHID3; // Enable channel 3 + pwmptr->PWM_IER1 = PWM_IER1_CHID3; + + setExternalModulePolarity(); + + NVIC_SetPriority(PWM_IRQn, 3); + NVIC_EnableIRQ(PWM_IRQn); +} + +void disable_main_ppm() +{ + Pio * pioptr = PIOA; + pioptr->PIO_PER = PIO_PA17; // Assign A17 to PIO + PWM->PWM_IDR1 = PWM_IDR1_CHID3; +} + +void init_second_ppm(uint32_t period) +{ +#if !defined(REVA) + // PWM1 for PPM2 + Pwm * pwmptr = PWM; + configure_pins(PIO_PC15, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP); + pwmptr->PWM_CH_NUM[1].PWM_CMR = 0x0000000B; // CLKB + if (!GET_PPM_POLARITY(EXTRA_MODULE)) { + pwmptr->PWM_CH_NUM[1].PWM_CMR |= 0x00000200; // CPOL + } + pwmptr->PWM_CH_NUM[1].PWM_CPDR = period; // Period + pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = period; // Period + pwmptr->PWM_CH_NUM[1].PWM_CDTY = GET_PPM_DELAY(EXTRA_MODULE)*2; // Duty + pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = GET_PPM_DELAY(EXTRA_MODULE)*2; // Duty + pwmptr->PWM_ENA = PWM_ENA_CHID1; // Enable channel 1 + pwmptr->PWM_IER1 = PWM_IER1_CHID1; +#endif +} + +void disable_second_ppm() +{ +#if !defined(REVA) + Pio * pioptr = PIOC; + pioptr->PIO_PER = PIO_PC15; // Assign C17 to PIO + PWM->PWM_IDR1 = PWM_IDR1_CHID1; +#endif +} + +void init_no_pulses(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + init_main_ppm(3000, 0); + } + else { + // TODO + } +} + +void disable_no_pulses(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + disable_ppm(EXTERNAL_MODULE); + } + else { + // TODO + } +} + +void init_ppm(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + init_main_ppm(3000, 1); + } + else { + init_second_ppm(3000); + } +} + +void disable_ppm(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + disable_main_ppm(); + } + else { + disable_second_ppm(); + } +} + +// Initialise the SSC to allow PXX output. +// TD is on PA17, peripheral A +void init_ssc(uint8_t baudrateDiv1000) +{ + Ssc *sscptr; + + PMC->PMC_PCER0 |= 0x00400000L; // Enable peripheral clock to SSC + + configure_pins(PIO_PA17, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA); + + sscptr = SSC; + sscptr->SSC_THR = 0xFF; // Make the output high. + sscptr->SSC_TFMR = 0x00000027; // 0000 0000 0000 0000 0000 0000 1010 0111 (8 bit data, lsb) + sscptr->SSC_CMR = Master_frequency / (1000 * baudrateDiv1000 * 2); + sscptr->SSC_TCMR = 0; + sscptr->SSC_CR = SSC_CR_TXEN; + +#if defined(REVX) + if (IS_MODULE_MULTIMODULE(EXTERNAL_MODULE)) { + PIOA->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 + } else { + PIOA->PIO_MDER = PIO_PA17; // Open Drain O/p in A17 + } +#else + PIOA->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 +#endif +} + +void disable_ssc() +{ + Pio *pioptr; + Ssc *sscptr; + + // Revert back to pwm output + pioptr = PIOA; + pioptr->PIO_PER = PIO_PA17; // Assign A17 to PIO + + sscptr = SSC; + sscptr->SSC_CR = SSC_CR_TXDIS; +} + +void init_pxx(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + init_main_ppm(2500 * 2, 0); + init_ssc(125); // 8us per bit + } + else { + // TODO + } +} + +void disable_pxx(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + disable_ssc(); + disable_ppm(EXTERNAL_MODULE); + } + else { + // TODO + } +} + +void init_dsm2(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + init_main_ppm(2500 * 2, 0); + init_ssc(125); + } + else { + // TODO + } +} + +void disable_dsm2(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + disable_ssc(); + disable_ppm(EXTERNAL_MODULE); + } + else { + // TODO + } +} + +#if defined(MULTIMODULE) +void init_multimodule(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + init_main_ppm(3500 * 2, 0); + init_ssc(100); + } + else { + // TODO + } +} + +void disable_multimodule(uint32_t port) +{ + disable_dsm2(port); +} +#endif + +#if !defined(SIMU) +extern "C" void PWM_IRQHandler(void) +{ + Pwm * pwmptr = PWM; + uint32_t reason = pwmptr->PWM_ISR1; + uint32_t period; + + if (reason & PWM_ISR1_CHID3) { + // Use the current protocol, don't switch until set_up_pulses + switch (s_current_protocol[EXTERNAL_MODULE]) { + case PROTO_PXX: + // Alternate periods of 6.5mS and 2.5 mS + period = pwmptr->PWM_CH_NUM[3].PWM_CPDR; + if (period == 2500 * 2) { + period = 6500 * 2; + } + else { + period = 2500 * 2; + } + pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS + if (period != 2500 * 2) { + setupPulses(EXTERNAL_MODULE); + setExternalModulePolarity(); + } + else { + // Kick off serial output here + Ssc * sscptr = SSC; + sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].pxx.pulses); + sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].pxx.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].pxx.pulses; + sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers + } + break; + + case PROTO_DSM2_LP45: + case PROTO_DSM2_DSM2: + case PROTO_DSM2_DSMX: + // Alternate periods of 19.5mS and 2.5 mS + period = pwmptr->PWM_CH_NUM[3].PWM_CPDR; + if (period == 2500 * 2) { + period = 19500 * 2; + } + else { + period = 2500 * 2; + } + pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS + if (period != 2500 * 2) { + setupPulses(EXTERNAL_MODULE); + } + else { + // Kick off serial output here + Ssc * sscptr = SSC; + sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses); + sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.pulses; + sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers + } + break; + +#if defined(MULTIMODULE) + case PROTO_MULTIMODULE: + // Alternate periods of 5.5mS and 3.5 mS + period = pwmptr->PWM_CH_NUM[3].PWM_CPDR; + if (period == 3500 * 2) { + period = 5500 * 2; + } + else { + period = 3500 * 2; + } + pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS + if (period != 3500 * 2) { + setupPulses(EXTERNAL_MODULE); + } + else { + // Kick off serial output here + Ssc * sscptr = SSC; + sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses); + sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.pulses; + sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers + } + break; +#endif + + default: + pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++; + if (*modulePulsesData[EXTERNAL_MODULE].ppm.ptr == 0) { + setExternalModulePolarity(); + setupPulses(EXTERNAL_MODULE); + } + break; + + } + } + +#if !defined(REVA) + if (reason & PWM_ISR1_CHID1) { + pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = *modulePulsesData[EXTRA_MODULE].ppm.ptr++; + if (*modulePulsesData[EXTRA_MODULE].ppm.ptr == 0) { + setupPulsesPPMModule(EXTRA_MODULE); + setExtraModulePolarity(); + } + } +#endif +} +#endif diff --git a/radio/src/targets/sky9x/pwr_driver.cpp b/radio/src/targets/sky9x/pwr_driver.cpp index 72dc140c4..3768f8478 100644 --- a/radio/src/targets/sky9x/pwr_driver.cpp +++ b/radio/src/targets/sky9x/pwr_driver.cpp @@ -1,47 +1,47 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -uint32_t pwrPressed() -{ -#if defined(SIMU) || defined(REVA) - return true; -#else - return PIOC->PIO_PDSR & PIO_PC17; -#endif -} - -// turn off soft power -void pwrOff() -{ -#if !defined(REVA) - configure_pins(PIO_PA8, PIN_ENABLE | PIN_OUTPUT | PIN_LOW | PIN_PORTA | PIN_NO_PULLUP); -#endif -} - -#if !defined(REVA) -void pwrInit() -{ - // Configure RF_power (PC17) - configure_pins(PIO_PC17, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_NO_PULLUP | PIN_PULLDOWN); - configure_pins(PIO_PA8, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP); // Enable bit A8 (Soft Power) -} -#endif +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +uint32_t pwrPressed() +{ +#if defined(SIMU) || defined(REVA) + return true; +#else + return PIOC->PIO_PDSR & PIO_PC17; +#endif +} + +// turn off soft power +void pwrOff() +{ +#if !defined(REVA) + configure_pins(PIO_PA8, PIN_ENABLE | PIN_OUTPUT | PIN_LOW | PIN_PORTA | PIN_NO_PULLUP); +#endif +} + +#if !defined(REVA) +void pwrInit() +{ + // Configure RF_power (PC17) + configure_pins(PIO_PC17, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_NO_PULLUP | PIN_PULLDOWN); + configure_pins(PIO_PA8, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP); // Enable bit A8 (Soft Power) +} +#endif diff --git a/radio/src/targets/sky9x/rotenc_driver.cpp b/radio/src/targets/sky9x/rotenc_driver.cpp index b4b66f63c..5bf1dbdd6 100644 --- a/radio/src/targets/sky9x/rotenc_driver.cpp +++ b/radio/src/targets/sky9x/rotenc_driver.cpp @@ -1,57 +1,57 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void rotencInit() -{ - configure_pins( PIO_PC19 | PIO_PC21, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_PULLUP ) ; // 19 and 21 are rotary encoder - configure_pins( PIO_PB6, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; // rotary encoder switch - PIOC->PIO_IER = PIO_PC19 | PIO_PC21 ; - NVIC_EnableIRQ(PIOC_IRQn) ; -} - -void rotencEnd() -{ - NVIC_DisableIRQ(PIOC_IRQn) ; - PIOC->PIO_IDR = PIO_PC19 | PIO_PC21 ; -} - -volatile uint32_t Rotary_position ; -extern "C" void PIOC_IRQHandler() -{ - uint32_t dummy; - - dummy = PIOC->PIO_ISR ; // Read and clear status register - (void) dummy ; // Discard value - prevents compiler warning - - dummy = PIOC->PIO_PDSR ; // Read Rotary encoder (PC19, PC21) - dummy >>= 19 ; - dummy &= 0x05 ; // pick out the three bits - if ( dummy != ( Rotary_position & 0x05 ) ) { - if ( ( Rotary_position & 0x01 ) ^ ( ( dummy & 0x04) >> 2 ) ) - incRotaryEncoder(0, -1); - else - incRotaryEncoder(0, +1); - - Rotary_position &= ~0x45 ; - Rotary_position |= dummy ; - } -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +void rotencInit() +{ + configure_pins( PIO_PC19 | PIO_PC21, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_PULLUP ) ; // 19 and 21 are rotary encoder + configure_pins( PIO_PB6, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; // rotary encoder switch + PIOC->PIO_IER = PIO_PC19 | PIO_PC21 ; + NVIC_EnableIRQ(PIOC_IRQn) ; +} + +void rotencEnd() +{ + NVIC_DisableIRQ(PIOC_IRQn) ; + PIOC->PIO_IDR = PIO_PC19 | PIO_PC21 ; +} + +volatile uint32_t Rotary_position ; +extern "C" void PIOC_IRQHandler() +{ + uint32_t dummy; + + dummy = PIOC->PIO_ISR ; // Read and clear status register + (void) dummy ; // Discard value - prevents compiler warning + + dummy = PIOC->PIO_PDSR ; // Read Rotary encoder (PC19, PC21) + dummy >>= 19 ; + dummy &= 0x05 ; // pick out the three bits + if ( dummy != ( Rotary_position & 0x05 ) ) { + if ( ( Rotary_position & 0x01 ) ^ ( ( dummy & 0x04) >> 2 ) ) + incRotaryEncoder(0, -1); + else + incRotaryEncoder(0, +1); + + Rotary_position &= ~0x45 ; + Rotary_position |= dummy ; + } +} diff --git a/radio/src/targets/sky9x/rtc_driver.cpp b/radio/src/targets/sky9x/rtc_driver.cpp index a70a6cdf7..717c49d27 100644 --- a/radio/src/targets/sky9x/rtc_driver.cpp +++ b/radio/src/targets/sky9x/rtc_driver.cpp @@ -1,287 +1,287 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#if defined(REVX) -// TODO change this, not the right place -#define TWI_NONE 0 -#define TWI_WRITE_VOL 2 -#define TWI_WAIT_COMP 7 -#define TWI_READ_RTC 8 -#define TWI_WRITE_RTC 9 -#define TWI_WAIT_RTCSTOP 10 -#define TWI_WRITE_MFP 11 -int8_t volumeRequired ; -int8_t Rtc_read_pending; -uint8_t Rtc_write_pending ; -int8_t Rtc_valid ; -uint8_t MFPsetting = 0 ; -uint8_t CALsetting = 0 ; -uint8_t *Twi_read_address ; -uint8_t TwiOperation ; -#define RTC_RX_BUXSIZE 10 -#define RTC_SIZE 7 -uint8_t Rtc_status[RTC_RX_BUXSIZE] ; -uint8_t *Rtc_write_ptr ; -uint32_t Rtc_write_count ; -uint8_t RtcConfig[8] ; // For initial config and writing to RTC -// 0x80, 0, 0, 0x08, 0, 0, 0, 0x80 - -uint32_t fromBCD(uint8_t bcd_value) -{ - return (((bcd_value & 0xF0) * 10) >> 4) + (bcd_value & 0x0F); -} - -uint32_t toBCD(uint32_t value) -{ - div_t qr = div(value, 10); - return (qr.quot << 4) + qr.rem; -} - -// This is called from an interrupt routine, or -// interrupts must be disabled while it is called -// from elsewhere. -void i2cCheck() -{ - if ( TWI0->TWI_IMR & TWI_IMR_TXCOMP ) { - return ; // Busy - } - - if ( volumeRequired >= 0 ) // Set volume to this value - { - TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing - TwiOperation = TWI_WRITE_VOL ; - TWI0->TWI_THR = volumeRequired ; // Send data - volumeRequired = -1 ; - TWI0->TWI_IER = TWI_IER_TXCOMP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - } - else if ( Rtc_read_pending ) - { - Rtc_valid = 0 ; - Rtc_read_pending = 0 ; - TWI0->TWI_MMR = 0x006F1100 ; // Device 6F and master is reading, 1 byte addr - TWI0->TWI_IADR = 0 ; - TwiOperation = TWI_READ_RTC ; -#ifndef SIMU - TWI0->TWI_RPR = (uint32_t)&Rtc_status[0] ; -#endif - TWI0->TWI_RCR = RTC_SIZE - 1 ; - if ( TWI0->TWI_SR & TWI_SR_RXRDY ) - { - (void) TWI0->TWI_RHR ; - } - - TWI0->TWI_PTCR = TWI_PTCR_RXTEN ; // Start transfers - TWI0->TWI_CR = TWI_CR_START ; // Start Rx - TWI0->TWI_IER = TWI_IER_RXBUFF | TWI_IER_TXCOMP ; - } - else if ( Rtc_write_pending ) - { - if ( Rtc_write_pending & (2|4) ) - { - TWI0->TWI_MMR = 0x006F0100 ; // Device 6F and master is writing, 1 byte addr - TwiOperation = TWI_WRITE_MFP ; - if ( Rtc_write_pending & 2 ) - { - TWI0->TWI_IADR = 7 ; - TWI0->TWI_THR = MFPsetting ; // Send data - Rtc_write_pending &= ~2 ; - } - else - { - TWI0->TWI_IADR = 8 ; - TWI0->TWI_THR = CALsetting ; // Send data - Rtc_write_pending &= ~4 ; - } - TWI0->TWI_IER = TWI_IER_TXCOMP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - } - else - { - Rtc_write_pending &= ~1 ; - TWI0->TWI_MMR = 0x006F0100 ; // Device 6F and master is writing, 1 byte addr - TWI0->TWI_IADR = 0 ; - TwiOperation = TWI_WRITE_RTC ; -#ifndef SIMU - TWI0->TWI_TPR = (uint32_t)Rtc_write_ptr+1 ; -#endif - TWI0->TWI_TCR = Rtc_write_count-1 ; - TWI0->TWI_THR = *Rtc_write_ptr ; // First byte - TWI0->TWI_PTCR = TWI_PTCR_TXTEN ; // Start data transfer - TWI0->TWI_IER = TWI_IER_TXBUFE | TWI_IER_TXCOMP ; - } - } -} - -void writeRTC(uint8_t *ptr) -{ - uint32_t year; - RtcConfig[0] = 0x80 | toBCD(*ptr++); - RtcConfig[1] = toBCD(*ptr++); - RtcConfig[2] = toBCD(*ptr++); - RtcConfig[3] = 0x08; - RtcConfig[4] = toBCD(*ptr++); - RtcConfig[5] = toBCD( *ptr++); - year = *ptr++; - year |= *ptr << 8; - RtcConfig[6] = toBCD(year - 2000); - RtcConfig[7] = MFPsetting; - Rtc_write_ptr = RtcConfig; - Rtc_write_count = 8; - __disable_irq(); - Rtc_write_pending |= 1; - i2cCheck(); - __enable_irq(); -} - -void readRTC() -{ - Rtc_read_pending = 1 ; - __disable_irq() ; - i2cCheck() ; - __enable_irq() ; -} - -// TODO should be inside an i2c_driver.cpp -#ifndef SIMU -extern "C" void TWI0_IRQHandler() -{ - uint32_t status ; - status = TWI0->TWI_SR ; // Read only once, some bits cleared on read - - if ( TwiOperation == TWI_READ_RTC ) - { - if ( status & TWI_SR_RXBUFF ) - { - TWI0->TWI_IDR = TWI_IDR_RXBUFF ; - TwiOperation = TWI_WAIT_RTCSTOP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Rx - TWI0->TWI_RCR = 1 ; // Last byte - return ; - } - else - { - // must be TXCOMP, prob. NAK in data - if ( TWI0->TWI_RCR > 0 ) - { - Rtc_valid = -1 ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Rx - } - } - } - - if ( TwiOperation == TWI_WAIT_RTCSTOP ) - { - Rtc_valid = 1 ; - // Set the date and time - struct gtm utm; - - utm.tm_sec = fromBCD( Rtc_status[0] & 0x7F ) ; - utm.tm_min = fromBCD( Rtc_status[1] & 0x7F ) ; - utm.tm_hour = fromBCD( Rtc_status[2] & 0x3F ) ; - utm.tm_mday = fromBCD( Rtc_status[4] & 0x3F ) ; - utm.tm_mon = fromBCD( Rtc_status[5] & 0x1F ) - 1; - utm.tm_year = fromBCD( Rtc_status[6] ) + 100 ; - g_rtcTime = gmktime(&utm); - - TWI0->TWI_PTCR = TWI_PTCR_RXTDIS ; // Stop transfers - if ( status & TWI_SR_RXRDY ) - { - (void) TWI0->TWI_RHR ; // Discard any rubbish data - } - } - - if ( status & TWI_SR_NACK ) - { - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - } - - TWI0->TWI_IDR = TWI_IDR_TXCOMP | TWI_IDR_TXBUFE | TWI_IDR_RXBUFF ; - TWI0->TWI_PTCR = TWI_PTCR_TXTDIS | TWI_PTCR_RXTDIS ; // Stop transfers - if ( ( status & TWI_SR_TXCOMP ) == 0 ) - { - TWI0->TWI_IER = TWI_IER_TXCOMP ; - TwiOperation = TWI_WAIT_COMP ; - return ; - } - - TwiOperation = TWI_NONE ; - i2cCheck() ; -} -#endif -#endif - -struct t_i2cTime -{ - uint8_t setCode ; - uint8_t Time[7] ; -} I2CTime ; - -void rtcSetTime(const struct gtm * t) -{ - g_ms100 = 0; // start of next second begins now - - I2CTime.setCode = 0x74 ; // Tiny SET TIME CODE command - I2CTime.Time[0] = t->tm_sec ; - I2CTime.Time[1] = t->tm_min ; - I2CTime.Time[2] = t->tm_hour ; - I2CTime.Time[3] = t->tm_mday ; - I2CTime.Time[4] = t->tm_mon+1 ; - I2CTime.Time[5] = (uint8_t) (t->tm_year+TM_YEAR_BASE); - I2CTime.Time[6] = (t->tm_year+TM_YEAR_BASE) >> 8; -#if defined(REVX) - writeRTC((uint8_t *)&I2CTime.Time[0]) ; -#elif defined(COPROCESSOR) - coprocWriteData((uint8_t *) &I2CTime, 8); -#endif -} - -void rtcInit() -{ -#if defined(REVX) - readRTC(); -#elif defined(COPROCESSOR) - coprocReadData(); -#endif -} - -#if defined(REVX) -void writeMFP() -{ - __disable_irq(); - Rtc_write_pending |= 2; - i2cCheck(); - __enable_irq(); -} - -void setMFP() -{ - MFPsetting = 0x80; - writeMFP(); -} - -void clearMFP() -{ - MFPsetting = 0; - writeMFP(); -} -#endif +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#if defined(REVX) +// TODO change this, not the right place +#define TWI_NONE 0 +#define TWI_WRITE_VOL 2 +#define TWI_WAIT_COMP 7 +#define TWI_READ_RTC 8 +#define TWI_WRITE_RTC 9 +#define TWI_WAIT_RTCSTOP 10 +#define TWI_WRITE_MFP 11 +int8_t volumeRequired ; +int8_t Rtc_read_pending; +uint8_t Rtc_write_pending ; +int8_t Rtc_valid ; +uint8_t MFPsetting = 0 ; +uint8_t CALsetting = 0 ; +uint8_t *Twi_read_address ; +uint8_t TwiOperation ; +#define RTC_RX_BUXSIZE 10 +#define RTC_SIZE 7 +uint8_t Rtc_status[RTC_RX_BUXSIZE] ; +uint8_t *Rtc_write_ptr ; +uint32_t Rtc_write_count ; +uint8_t RtcConfig[8] ; // For initial config and writing to RTC +// 0x80, 0, 0, 0x08, 0, 0, 0, 0x80 + +uint32_t fromBCD(uint8_t bcd_value) +{ + return (((bcd_value & 0xF0) * 10) >> 4) + (bcd_value & 0x0F); +} + +uint32_t toBCD(uint32_t value) +{ + div_t qr = div(value, 10); + return (qr.quot << 4) + qr.rem; +} + +// This is called from an interrupt routine, or +// interrupts must be disabled while it is called +// from elsewhere. +void i2cCheck() +{ + if ( TWI0->TWI_IMR & TWI_IMR_TXCOMP ) { + return ; // Busy + } + + if ( volumeRequired >= 0 ) // Set volume to this value + { + TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing + TwiOperation = TWI_WRITE_VOL ; + TWI0->TWI_THR = volumeRequired ; // Send data + volumeRequired = -1 ; + TWI0->TWI_IER = TWI_IER_TXCOMP ; + TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx + } + else if ( Rtc_read_pending ) + { + Rtc_valid = 0 ; + Rtc_read_pending = 0 ; + TWI0->TWI_MMR = 0x006F1100 ; // Device 6F and master is reading, 1 byte addr + TWI0->TWI_IADR = 0 ; + TwiOperation = TWI_READ_RTC ; +#ifndef SIMU + TWI0->TWI_RPR = (uint32_t)&Rtc_status[0] ; +#endif + TWI0->TWI_RCR = RTC_SIZE - 1 ; + if ( TWI0->TWI_SR & TWI_SR_RXRDY ) + { + (void) TWI0->TWI_RHR ; + } + + TWI0->TWI_PTCR = TWI_PTCR_RXTEN ; // Start transfers + TWI0->TWI_CR = TWI_CR_START ; // Start Rx + TWI0->TWI_IER = TWI_IER_RXBUFF | TWI_IER_TXCOMP ; + } + else if ( Rtc_write_pending ) + { + if ( Rtc_write_pending & (2|4) ) + { + TWI0->TWI_MMR = 0x006F0100 ; // Device 6F and master is writing, 1 byte addr + TwiOperation = TWI_WRITE_MFP ; + if ( Rtc_write_pending & 2 ) + { + TWI0->TWI_IADR = 7 ; + TWI0->TWI_THR = MFPsetting ; // Send data + Rtc_write_pending &= ~2 ; + } + else + { + TWI0->TWI_IADR = 8 ; + TWI0->TWI_THR = CALsetting ; // Send data + Rtc_write_pending &= ~4 ; + } + TWI0->TWI_IER = TWI_IER_TXCOMP ; + TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx + } + else + { + Rtc_write_pending &= ~1 ; + TWI0->TWI_MMR = 0x006F0100 ; // Device 6F and master is writing, 1 byte addr + TWI0->TWI_IADR = 0 ; + TwiOperation = TWI_WRITE_RTC ; +#ifndef SIMU + TWI0->TWI_TPR = (uint32_t)Rtc_write_ptr+1 ; +#endif + TWI0->TWI_TCR = Rtc_write_count-1 ; + TWI0->TWI_THR = *Rtc_write_ptr ; // First byte + TWI0->TWI_PTCR = TWI_PTCR_TXTEN ; // Start data transfer + TWI0->TWI_IER = TWI_IER_TXBUFE | TWI_IER_TXCOMP ; + } + } +} + +void writeRTC(uint8_t *ptr) +{ + uint32_t year; + RtcConfig[0] = 0x80 | toBCD(*ptr++); + RtcConfig[1] = toBCD(*ptr++); + RtcConfig[2] = toBCD(*ptr++); + RtcConfig[3] = 0x08; + RtcConfig[4] = toBCD(*ptr++); + RtcConfig[5] = toBCD( *ptr++); + year = *ptr++; + year |= *ptr << 8; + RtcConfig[6] = toBCD(year - 2000); + RtcConfig[7] = MFPsetting; + Rtc_write_ptr = RtcConfig; + Rtc_write_count = 8; + __disable_irq(); + Rtc_write_pending |= 1; + i2cCheck(); + __enable_irq(); +} + +void readRTC() +{ + Rtc_read_pending = 1 ; + __disable_irq() ; + i2cCheck() ; + __enable_irq() ; +} + +// TODO should be inside an i2c_driver.cpp +#ifndef SIMU +extern "C" void TWI0_IRQHandler() +{ + uint32_t status ; + status = TWI0->TWI_SR ; // Read only once, some bits cleared on read + + if ( TwiOperation == TWI_READ_RTC ) + { + if ( status & TWI_SR_RXBUFF ) + { + TWI0->TWI_IDR = TWI_IDR_RXBUFF ; + TwiOperation = TWI_WAIT_RTCSTOP ; + TWI0->TWI_CR = TWI_CR_STOP ; // Stop Rx + TWI0->TWI_RCR = 1 ; // Last byte + return ; + } + else + { + // must be TXCOMP, prob. NAK in data + if ( TWI0->TWI_RCR > 0 ) + { + Rtc_valid = -1 ; + TWI0->TWI_CR = TWI_CR_STOP ; // Stop Rx + } + } + } + + if ( TwiOperation == TWI_WAIT_RTCSTOP ) + { + Rtc_valid = 1 ; + // Set the date and time + struct gtm utm; + + utm.tm_sec = fromBCD( Rtc_status[0] & 0x7F ) ; + utm.tm_min = fromBCD( Rtc_status[1] & 0x7F ) ; + utm.tm_hour = fromBCD( Rtc_status[2] & 0x3F ) ; + utm.tm_mday = fromBCD( Rtc_status[4] & 0x3F ) ; + utm.tm_mon = fromBCD( Rtc_status[5] & 0x1F ) - 1; + utm.tm_year = fromBCD( Rtc_status[6] ) + 100 ; + g_rtcTime = gmktime(&utm); + + TWI0->TWI_PTCR = TWI_PTCR_RXTDIS ; // Stop transfers + if ( status & TWI_SR_RXRDY ) + { + (void) TWI0->TWI_RHR ; // Discard any rubbish data + } + } + + if ( status & TWI_SR_NACK ) + { + TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx + } + + TWI0->TWI_IDR = TWI_IDR_TXCOMP | TWI_IDR_TXBUFE | TWI_IDR_RXBUFF ; + TWI0->TWI_PTCR = TWI_PTCR_TXTDIS | TWI_PTCR_RXTDIS ; // Stop transfers + if ( ( status & TWI_SR_TXCOMP ) == 0 ) + { + TWI0->TWI_IER = TWI_IER_TXCOMP ; + TwiOperation = TWI_WAIT_COMP ; + return ; + } + + TwiOperation = TWI_NONE ; + i2cCheck() ; +} +#endif +#endif + +struct t_i2cTime +{ + uint8_t setCode ; + uint8_t Time[7] ; +} I2CTime ; + +void rtcSetTime(const struct gtm * t) +{ + g_ms100 = 0; // start of next second begins now + + I2CTime.setCode = 0x74 ; // Tiny SET TIME CODE command + I2CTime.Time[0] = t->tm_sec ; + I2CTime.Time[1] = t->tm_min ; + I2CTime.Time[2] = t->tm_hour ; + I2CTime.Time[3] = t->tm_mday ; + I2CTime.Time[4] = t->tm_mon+1 ; + I2CTime.Time[5] = (uint8_t) (t->tm_year+TM_YEAR_BASE); + I2CTime.Time[6] = (t->tm_year+TM_YEAR_BASE) >> 8; +#if defined(REVX) + writeRTC((uint8_t *)&I2CTime.Time[0]) ; +#elif defined(COPROCESSOR) + coprocWriteData((uint8_t *) &I2CTime, 8); +#endif +} + +void rtcInit() +{ +#if defined(REVX) + readRTC(); +#elif defined(COPROCESSOR) + coprocReadData(); +#endif +} + +#if defined(REVX) +void writeMFP() +{ + __disable_irq(); + Rtc_write_pending |= 2; + i2cCheck(); + __enable_irq(); +} + +void setMFP() +{ + MFPsetting = 0x80; + writeMFP(); +} + +void clearMFP() +{ + MFPsetting = 0; + writeMFP(); +} +#endif diff --git a/radio/src/targets/sky9x/sam3s2c_flash.ld b/radio/src/targets/sky9x/sam3s2c_flash.ld index 965328c0e..cef58ff00 100644 --- a/radio/src/targets/sky9x/sam3s2c_flash.ld +++ b/radio/src/targets/sky9x/sam3s2c_flash.ld @@ -1,150 +1,150 @@ -/**************************************************************************** -* Copyright (c) 2011 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -***************************************************************************** -* History: -* -* 22.05.2011 mifi First Version -****************************************************************************/ - - -/* - * In this linker script there is no heap available. - * The stack start at the end of the ram segment. - */ - - -/* - * Take a look in the "The GNU linker" manual, here you get - * the following information about the "MEMORY": - * - * "The MEMORY command describes the location and size of - * blocks of memory in the target." - */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 128K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 32K -} - - -/* - * And the "SECTION" is used for: - * - * "The SECTIONS command tells the linker how to map input - * sections into output sections, and how to place the output - * sections in memory. - */ -SECTIONS -{ - - /* - * The ".text" section is used for the code, and - * read only (.rodata) data. Even the vectors (.vectors) - * MUST be saved at the start of this section. - */ - .text : - { - _stext = .; /* Provide the name for the start of this section */ - - CREATE_OBJECT_SYMBOLS - KEEP(*(.vectors)) - - *(.text) - *(.text.*) - - . = ALIGN(4); /* Align the start of the exidx part */ - *(.ARM.exidx) - *(.ARM.exidx.*) - - . = ALIGN(4); /* Align the start of the rodata part */ - *(.rodata) - *(.rodata.*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); /* Align the end of the section */ - } > FLASH = 0 - _etext = .; /* Provide the name for the end of this section */ - - - /* - * The ".data" section is used for initialized data - * and for functions (.fastrun) which should be copied - * from flash to ram. This functions will later be - * executed from ram instead of flash. - */ - .data : AT (_etext) - { - . = ALIGN(4); /* Align the start of the section */ - _sdata = .; /* Provide the name for the start of this section */ - - *(.data) - *(.data.*) - - . = ALIGN(4); /* Align the start of the fastrun part */ - *(.fastrun) - *(.fastrun.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _edata = .; /* Provide the name for the end of this section */ - - - /* - * The ".bss" section is used for uninitialized data. - * This section will be cleared by the startup code. - */ - .bss : - { - . = ALIGN(4); /* Align the start of the section */ - _sbss = .; /* Provide the name for the start of this section */ - - *(.bss) - *(.bss.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _ebss = .; /* Provide the name for the end of this section */ - - . = ALIGN(4); /* Align the end of the section */ - __end = .; - _end = .; - - /* - * The ".stack" section is our stack. - * Here this section starts at the end of the ram segment. - */ - _estack = ORIGIN(RAM) + LENGTH(RAM); - -} - -/*** EOF **/ - +/**************************************************************************** +* Copyright (c) 2011 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +***************************************************************************** +* History: +* +* 22.05.2011 mifi First Version +****************************************************************************/ + + +/* + * In this linker script there is no heap available. + * The stack start at the end of the ram segment. + */ + + +/* + * Take a look in the "The GNU linker" manual, here you get + * the following information about the "MEMORY": + * + * "The MEMORY command describes the location and size of + * blocks of memory in the target." + */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 128K + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 32K +} + + +/* + * And the "SECTION" is used for: + * + * "The SECTIONS command tells the linker how to map input + * sections into output sections, and how to place the output + * sections in memory. + */ +SECTIONS +{ + + /* + * The ".text" section is used for the code, and + * read only (.rodata) data. Even the vectors (.vectors) + * MUST be saved at the start of this section. + */ + .text : + { + _stext = .; /* Provide the name for the start of this section */ + + CREATE_OBJECT_SYMBOLS + KEEP(*(.vectors)) + + *(.text) + *(.text.*) + + . = ALIGN(4); /* Align the start of the exidx part */ + *(.ARM.exidx) + *(.ARM.exidx.*) + + . = ALIGN(4); /* Align the start of the rodata part */ + *(.rodata) + *(.rodata.*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); /* Align the end of the section */ + } > FLASH = 0 + _etext = .; /* Provide the name for the end of this section */ + + + /* + * The ".data" section is used for initialized data + * and for functions (.fastrun) which should be copied + * from flash to ram. This functions will later be + * executed from ram instead of flash. + */ + .data : AT (_etext) + { + . = ALIGN(4); /* Align the start of the section */ + _sdata = .; /* Provide the name for the start of this section */ + + *(.data) + *(.data.*) + + . = ALIGN(4); /* Align the start of the fastrun part */ + *(.fastrun) + *(.fastrun.*) + + . = ALIGN(4); /* Align the end of the section */ + } > RAM + _edata = .; /* Provide the name for the end of this section */ + + + /* + * The ".bss" section is used for uninitialized data. + * This section will be cleared by the startup code. + */ + .bss : + { + . = ALIGN(4); /* Align the start of the section */ + _sbss = .; /* Provide the name for the start of this section */ + + *(.bss) + *(.bss.*) + + . = ALIGN(4); /* Align the end of the section */ + } > RAM + _ebss = .; /* Provide the name for the end of this section */ + + . = ALIGN(4); /* Align the end of the section */ + __end = .; + _end = .; + + /* + * The ".stack" section is our stack. + * Here this section starts at the end of the ram segment. + */ + _estack = ORIGIN(RAM) + LENGTH(RAM); + +} + +/*** EOF **/ + diff --git a/radio/src/targets/sky9x/sam3s4c_flash.ld b/radio/src/targets/sky9x/sam3s4c_flash.ld index 743bcc97c..1a7c11041 100644 --- a/radio/src/targets/sky9x/sam3s4c_flash.ld +++ b/radio/src/targets/sky9x/sam3s4c_flash.ld @@ -1,154 +1,154 @@ -/**************************************************************************** -* Copyright (c) 2011 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -***************************************************************************** -* History: -* -* 22.05.2011 mifi First Version -****************************************************************************/ - - -/* - * In this linker script there is no heap available. - * The stack start at the end of the ram segment. - */ - - -/* - * Take a look in the "The GNU linker" manual, here you get - * the following information about the "MEMORY": - * - * "The MEMORY command describes the location and size of - * blocks of memory in the target." - */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 256K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 48K -} - - -/* - * And the "SECTION" is used for: - * - * "The SECTIONS command tells the linker how to map input - * sections into output sections, and how to place the output - * sections in memory. - */ -SECTIONS -{ - - /* - * The ".text" section is used for the code, and - * read only (.rodata) data. Even the vectors (.vectors) - * MUST be saved at the start of this section. - */ - .text : - { - FILL(0xFFFF) - - CREATE_OBJECT_SYMBOLS - - *(.bootrodata) - *(.bootrodata.*) - - . = ALIGN(32768); /* Align the start of the exidx part */ - _stext = .; /* Provide the name for the start of this section */ - - KEEP(*(.vectors)) - - *(.text) - *(.text.*) - - . = ALIGN(4); /* Align the start of the exidx part */ - *(.ARM.exidx) - *(.ARM.exidx.*) - - . = ALIGN(4); /* Align the start of the rodata part */ - *(.rodata) - *(.rodata.*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); /* Align the end of the section */ - } > FLASH = 0 - _etext = .; /* Provide the name for the end of this section */ - - - /* - * The ".data" section is used for initialized data - * and for functions (.fastrun) which should be copied - * from flash to ram. This functions will later be - * executed from ram instead of flash. - */ - .data : AT (_etext) - { - . = ALIGN(4); /* Align the start of the section */ - _sdata = .; /* Provide the name for the start of this section */ - - *(.data) - *(.data.*) - - . = ALIGN(4); /* Align the start of the fastrun part */ - *(.fastrun) - *(.fastrun.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _edata = .; /* Provide the name for the end of this section */ - - - /* - * The ".bss" section is used for uninitialized data. - * This section will be cleared by the startup code. - */ - .bss : - { - . = ALIGN(4); /* Align the start of the section */ - _sbss = .; /* Provide the name for the start of this section */ - - *(.bss) - *(.bss.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _ebss = .; /* Provide the name for the end of this section */ - - - /* - * The ".stack" section is our stack. - * Here this section starts at the end of the ram segment. - */ - _estack = ORIGIN(RAM) + LENGTH(RAM); - -} - -/*** EOF **/ - +/**************************************************************************** +* Copyright (c) 2011 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +***************************************************************************** +* History: +* +* 22.05.2011 mifi First Version +****************************************************************************/ + + +/* + * In this linker script there is no heap available. + * The stack start at the end of the ram segment. + */ + + +/* + * Take a look in the "The GNU linker" manual, here you get + * the following information about the "MEMORY": + * + * "The MEMORY command describes the location and size of + * blocks of memory in the target." + */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 256K + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 48K +} + + +/* + * And the "SECTION" is used for: + * + * "The SECTIONS command tells the linker how to map input + * sections into output sections, and how to place the output + * sections in memory. + */ +SECTIONS +{ + + /* + * The ".text" section is used for the code, and + * read only (.rodata) data. Even the vectors (.vectors) + * MUST be saved at the start of this section. + */ + .text : + { + FILL(0xFFFF) + + CREATE_OBJECT_SYMBOLS + + *(.bootrodata) + *(.bootrodata.*) + + . = ALIGN(32768); /* Align the start of the exidx part */ + _stext = .; /* Provide the name for the start of this section */ + + KEEP(*(.vectors)) + + *(.text) + *(.text.*) + + . = ALIGN(4); /* Align the start of the exidx part */ + *(.ARM.exidx) + *(.ARM.exidx.*) + + . = ALIGN(4); /* Align the start of the rodata part */ + *(.rodata) + *(.rodata.*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); /* Align the end of the section */ + } > FLASH = 0 + _etext = .; /* Provide the name for the end of this section */ + + + /* + * The ".data" section is used for initialized data + * and for functions (.fastrun) which should be copied + * from flash to ram. This functions will later be + * executed from ram instead of flash. + */ + .data : AT (_etext) + { + . = ALIGN(4); /* Align the start of the section */ + _sdata = .; /* Provide the name for the start of this section */ + + *(.data) + *(.data.*) + + . = ALIGN(4); /* Align the start of the fastrun part */ + *(.fastrun) + *(.fastrun.*) + + . = ALIGN(4); /* Align the end of the section */ + } > RAM + _edata = .; /* Provide the name for the end of this section */ + + + /* + * The ".bss" section is used for uninitialized data. + * This section will be cleared by the startup code. + */ + .bss : + { + . = ALIGN(4); /* Align the start of the section */ + _sbss = .; /* Provide the name for the start of this section */ + + *(.bss) + *(.bss.*) + + . = ALIGN(4); /* Align the end of the section */ + } > RAM + _ebss = .; /* Provide the name for the end of this section */ + + + /* + * The ".stack" section is our stack. + * Here this section starts at the end of the ram segment. + */ + _estack = ORIGIN(RAM) + LENGTH(RAM); + +} + +/*** EOF **/ + diff --git a/radio/src/targets/sky9x/sam3s8c_flash.ld b/radio/src/targets/sky9x/sam3s8c_flash.ld index fa7227a9b..833e56e69 100644 --- a/radio/src/targets/sky9x/sam3s8c_flash.ld +++ b/radio/src/targets/sky9x/sam3s8c_flash.ld @@ -1,156 +1,156 @@ -/**************************************************************************** -* Copyright (c) 2011 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -***************************************************************************** -* History: -* -* 22.05.2011 mifi First Version -****************************************************************************/ - - -/* - * In this linker script there is no heap available. - * The stack start at the end of the ram segment. - */ - - -/* - * Take a look in the "The GNU linker" manual, here you get - * the following information about the "MEMORY": - * - * "The MEMORY command describes the location and size of - * blocks of memory in the target." - */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 512K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - - -/* - * And the "SECTION" is used for: - * - * "The SECTIONS command tells the linker how to map input - * sections into output sections, and how to place the output - * sections in memory. - */ -SECTIONS -{ - - /* - * The ".text" section is used for the code, and - * read only (.rodata) data. Even the vectors (.vectors) - * MUST be saved at the start of this section. - */ - .text : - { - FILL(0xFFFF) - - CREATE_OBJECT_SYMBOLS - - *(.bootrodata) - *(.bootrodata.*) - - . = ALIGN(32768); /* Align the start of the exidx part */ - _stext = .; /* Provide the name for the start of this section */ - KEEP(*(.vectors)) - - *(.text) - *(.text.*) - - . = ALIGN(4); /* Align the start of the exidx part */ - *(.ARM.exidx) - *(.ARM.exidx.*) - - . = ALIGN(4); /* Align the start of the rodata part */ - *(.rodata) - *(.rodata.*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); /* Align the end of the section */ - } > FLASH = 0 - _etext = .; /* Provide the name for the end of this section */ - - - /* - * The ".data" section is used for initialized data - * and for functions (.fastrun) which should be copied - * from flash to ram. This functions will later be - * executed from ram instead of flash. - */ - .data : AT (_etext) - { - . = ALIGN(4); /* Align the start of the section */ - _sdata = .; /* Provide the name for the start of this section */ - - *(.data) - *(.data.*) - - . = ALIGN(4); /* Align the start of the fastrun part */ - *(.fastrun) - *(.fastrun.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _edata = .; /* Provide the name for the end of this section */ - - - /* - * The ".bss" section is used for uninitialized data. - * This section will be cleared by the startup code. - */ - .bss : - { - . = ALIGN(4); /* Align the start of the section */ - _sbss = .; /* Provide the name for the start of this section */ - - *(.bss) - *(.bss.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _ebss = .; /* Provide the name for the end of this section */ - - . = ALIGN(4); /* Align the end of the section */ - __end = .; - _end = .; - - /* - * The ".stack" section is our stack. - * Here this section starts at the end of the ram segment. - */ - _estack = ORIGIN(RAM) + LENGTH(RAM); - -} - -/*** EOF **/ - +/**************************************************************************** +* Copyright (c) 2011 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +***************************************************************************** +* History: +* +* 22.05.2011 mifi First Version +****************************************************************************/ + + +/* + * In this linker script there is no heap available. + * The stack start at the end of the ram segment. + */ + + +/* + * Take a look in the "The GNU linker" manual, here you get + * the following information about the "MEMORY": + * + * "The MEMORY command describes the location and size of + * blocks of memory in the target." + */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 512K + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + + +/* + * And the "SECTION" is used for: + * + * "The SECTIONS command tells the linker how to map input + * sections into output sections, and how to place the output + * sections in memory. + */ +SECTIONS +{ + + /* + * The ".text" section is used for the code, and + * read only (.rodata) data. Even the vectors (.vectors) + * MUST be saved at the start of this section. + */ + .text : + { + FILL(0xFFFF) + + CREATE_OBJECT_SYMBOLS + + *(.bootrodata) + *(.bootrodata.*) + + . = ALIGN(32768); /* Align the start of the exidx part */ + _stext = .; /* Provide the name for the start of this section */ + KEEP(*(.vectors)) + + *(.text) + *(.text.*) + + . = ALIGN(4); /* Align the start of the exidx part */ + *(.ARM.exidx) + *(.ARM.exidx.*) + + . = ALIGN(4); /* Align the start of the rodata part */ + *(.rodata) + *(.rodata.*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); /* Align the end of the section */ + } > FLASH = 0 + _etext = .; /* Provide the name for the end of this section */ + + + /* + * The ".data" section is used for initialized data + * and for functions (.fastrun) which should be copied + * from flash to ram. This functions will later be + * executed from ram instead of flash. + */ + .data : AT (_etext) + { + . = ALIGN(4); /* Align the start of the section */ + _sdata = .; /* Provide the name for the start of this section */ + + *(.data) + *(.data.*) + + . = ALIGN(4); /* Align the start of the fastrun part */ + *(.fastrun) + *(.fastrun.*) + + . = ALIGN(4); /* Align the end of the section */ + } > RAM + _edata = .; /* Provide the name for the end of this section */ + + + /* + * The ".bss" section is used for uninitialized data. + * This section will be cleared by the startup code. + */ + .bss : + { + . = ALIGN(4); /* Align the start of the section */ + _sbss = .; /* Provide the name for the start of this section */ + + *(.bss) + *(.bss.*) + + . = ALIGN(4); /* Align the end of the section */ + } > RAM + _ebss = .; /* Provide the name for the end of this section */ + + . = ALIGN(4); /* Align the end of the section */ + __end = .; + _end = .; + + /* + * The ".stack" section is our stack. + * Here this section starts at the end of the ram segment. + */ + _estack = ORIGIN(RAM) + LENGTH(RAM); + +} + +/*** EOF **/ + diff --git a/radio/src/targets/sky9x/sdcard_driver.cpp b/radio/src/targets/sky9x/sdcard_driver.cpp index ea821800c..2f7ae355d 100644 --- a/radio/src/targets/sky9x/sdcard_driver.cpp +++ b/radio/src/targets/sky9x/sdcard_driver.cpp @@ -1,52 +1,52 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#define MCI_INITIAL_SPEED 400000 - -void init_SDcard() -{ -#ifndef SIMU - configure_pins( 0xFC000000, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_C | PIN_PORTA | PIN_NO_PULLUP ) ; - configure_pins( PIO_PB7, PIN_INPUT | PIN_PORTB | PIN_NO_PULLUP | PIN_NO_PULLDOWN ) ; - - unsigned short clkDiv; - Hsmci *pMciHw = HSMCI ; - - /* Enable the MCI peripheral */ - PMC->PMC_PCER0 |= 1 << ID_HSMCI ; // Enable peripheral clock to HSMCI - pMciHw->HSMCI_CR = HSMCI_CR_SWRST; /* Reset the MCI */ - pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS | HSMCI_CR_PWSDIS; /* Disable the MCI */ - pMciHw->HSMCI_IDR = 0xFFFFFFFF; /* Disable all the interrupts */ - pMciHw->HSMCI_DTOR = HSMCI_DTOR_DTOCYC_Msk | HSMCI_DTOR_DTOMUL_Msk ; /* Set the Data Timeout Register */ - pMciHw->HSMCI_CSTOR = HSMCI_CSTOR_CSTOCYC_Msk | HSMCI_CSTOR_CSTOMUL_Msk ; /* CSTOR ? */ - /* Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58) */ - clkDiv = 45; // (Master_frequency / (MCI_INITIAL_SPEED * 2)) - 1; - pMciHw->HSMCI_MR = clkDiv | (7 << 8) ; - - /* Set the SDCard Register 1-bit, slot A */ - pMciHw->HSMCI_SDCR = HSMCI_SDCR_SDCSEL_SLOTA | HSMCI_SDCR_SDCBUS_1 ; - /* Enable the MCI and the Power Saving */ - pMciHw->HSMCI_CR = HSMCI_CR_MCIEN/* | HSMCI_CR_PWSEN */; - /* Configure MCI */ - pMciHw->HSMCI_CFG = HSMCI_CFG_FIFOMODE | HSMCI_CFG_FERRCTRL; -#endif -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#define MCI_INITIAL_SPEED 400000 + +void init_SDcard() +{ +#ifndef SIMU + configure_pins( 0xFC000000, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_C | PIN_PORTA | PIN_NO_PULLUP ) ; + configure_pins( PIO_PB7, PIN_INPUT | PIN_PORTB | PIN_NO_PULLUP | PIN_NO_PULLDOWN ) ; + + unsigned short clkDiv; + Hsmci *pMciHw = HSMCI ; + + /* Enable the MCI peripheral */ + PMC->PMC_PCER0 |= 1 << ID_HSMCI ; // Enable peripheral clock to HSMCI + pMciHw->HSMCI_CR = HSMCI_CR_SWRST; /* Reset the MCI */ + pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS | HSMCI_CR_PWSDIS; /* Disable the MCI */ + pMciHw->HSMCI_IDR = 0xFFFFFFFF; /* Disable all the interrupts */ + pMciHw->HSMCI_DTOR = HSMCI_DTOR_DTOCYC_Msk | HSMCI_DTOR_DTOMUL_Msk ; /* Set the Data Timeout Register */ + pMciHw->HSMCI_CSTOR = HSMCI_CSTOR_CSTOCYC_Msk | HSMCI_CSTOR_CSTOMUL_Msk ; /* CSTOR ? */ + /* Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58) */ + clkDiv = 45; // (Master_frequency / (MCI_INITIAL_SPEED * 2)) - 1; + pMciHw->HSMCI_MR = clkDiv | (7 << 8) ; + + /* Set the SDCard Register 1-bit, slot A */ + pMciHw->HSMCI_SDCR = HSMCI_SDCR_SDCSEL_SLOTA | HSMCI_SDCR_SDCBUS_1 ; + /* Enable the MCI and the Power Saving */ + pMciHw->HSMCI_CR = HSMCI_CR_MCIEN/* | HSMCI_CR_PWSEN */; + /* Configure MCI */ + pMciHw->HSMCI_CFG = HSMCI_CFG_FIFOMODE | HSMCI_CFG_FERRCTRL; +#endif +} diff --git a/radio/src/targets/sky9x/serial2_driver.cpp b/radio/src/targets/sky9x/serial2_driver.cpp index e3243188a..3f2153f1a 100644 --- a/radio/src/targets/sky9x/serial2_driver.cpp +++ b/radio/src/targets/sky9x/serial2_driver.cpp @@ -1,119 +1,119 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" -#include - -/** Usart Hw interface used by the console (UART0). */ -#define SECOND_SERIAL_UART UART0 -/** Usart Hw ID used by the console (UART0). */ -#define SECOND_SERIAL_ID ID_UART0 -/** Pins description corresponding to Rxd,Txd, (UART pins) */ -#define SECOND_SERIAL_PINS {PINS_UART} - -Fifo serial2RxFifo; - -#if !defined(SIMU) -/* - * Outputs a character on the UART line. - * - * This function is synchronous (i.e. uses polling). - * c Character to send. - */ -void serial2Putc(const char c) -{ - Uart *pUart = SECOND_SERIAL_UART; - - /* Wait for the transmitter to be ready */ - while ( (pUart->UART_SR & UART_SR_TXEMPTY) == 0 ) ; - - /* Send character */ - pUart->UART_THR = c; -} - -uint8_t serial2TracesEnabled() -{ - return false; -} - -/** - * Configures a UART peripheral with the specified parameters. - * - * baudrate Baudrate at which the UART should operate (in Hz). - * masterClock Frequency of the system master clock (in Hz). - * uses PA9 and PA10, RXD2 and TXD2 - */ -void SECOND_UART_Configure(uint32_t baudrate, uint32_t masterClock) -{ - Uart *pUart = SECOND_SERIAL_UART; - - /* Configure PIO */ - configure_pins( (PIO_PA9 | PIO_PA10), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ; - - /* Configure PMC */ - PMC->PMC_PCER0 = 1 << SECOND_SERIAL_ID; - - /* Reset and disable receiver & transmitter */ - pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX - | UART_CR_RXDIS | UART_CR_TXDIS; - - /* Configure mode */ - pUart->UART_MR = 0x800 ; // NORMAL, No Parity - - /* Configure baudrate */ - /* Asynchronous, no oversampling */ - pUart->UART_BRGR = (masterClock / baudrate) / 16; - - /* Disable PDC channel */ - pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; - - /* Enable receiver and transmitter */ - pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; - - pUart->UART_IER = UART_IER_RXRDY; - NVIC_EnableIRQ(UART0_IRQn); -} - -void SECOND_UART_Stop() -{ - SECOND_SERIAL_UART->UART_IDR = UART_IDR_RXRDY ; - NVIC_DisableIRQ(UART0_IRQn) ; -} - -extern "C" void UART0_IRQHandler() -{ - serial2RxFifo.push(SECOND_SERIAL_UART->UART_RHR); -} -#else -#define SECOND_UART_Configure(...) -#endif - -#if defined(TELEMETRY_FRSKY) -void serial2TelemetryInit(unsigned int /*protocol*/) -{ - SECOND_UART_Configure(FRSKY_D_BAUDRATE, Master_frequency); - // startPdcUsartReceive(); -} - -bool telemetrySecondPortReceive(uint8_t & data) -{ - return serial2RxFifo.pop(data); -} -#endif +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" +#include + +/** Usart Hw interface used by the console (UART0). */ +#define SECOND_SERIAL_UART UART0 +/** Usart Hw ID used by the console (UART0). */ +#define SECOND_SERIAL_ID ID_UART0 +/** Pins description corresponding to Rxd,Txd, (UART pins) */ +#define SECOND_SERIAL_PINS {PINS_UART} + +Fifo serial2RxFifo; + +#if !defined(SIMU) +/* + * Outputs a character on the UART line. + * + * This function is synchronous (i.e. uses polling). + * c Character to send. + */ +void serial2Putc(const char c) +{ + Uart *pUart = SECOND_SERIAL_UART; + + /* Wait for the transmitter to be ready */ + while ( (pUart->UART_SR & UART_SR_TXEMPTY) == 0 ) ; + + /* Send character */ + pUart->UART_THR = c; +} + +uint8_t serial2TracesEnabled() +{ + return false; +} + +/** + * Configures a UART peripheral with the specified parameters. + * + * baudrate Baudrate at which the UART should operate (in Hz). + * masterClock Frequency of the system master clock (in Hz). + * uses PA9 and PA10, RXD2 and TXD2 + */ +void SECOND_UART_Configure(uint32_t baudrate, uint32_t masterClock) +{ + Uart *pUart = SECOND_SERIAL_UART; + + /* Configure PIO */ + configure_pins( (PIO_PA9 | PIO_PA10), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ; + + /* Configure PMC */ + PMC->PMC_PCER0 = 1 << SECOND_SERIAL_ID; + + /* Reset and disable receiver & transmitter */ + pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS; + + /* Configure mode */ + pUart->UART_MR = 0x800 ; // NORMAL, No Parity + + /* Configure baudrate */ + /* Asynchronous, no oversampling */ + pUart->UART_BRGR = (masterClock / baudrate) / 16; + + /* Disable PDC channel */ + pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; + + /* Enable receiver and transmitter */ + pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; + + pUart->UART_IER = UART_IER_RXRDY; + NVIC_EnableIRQ(UART0_IRQn); +} + +void SECOND_UART_Stop() +{ + SECOND_SERIAL_UART->UART_IDR = UART_IDR_RXRDY ; + NVIC_DisableIRQ(UART0_IRQn) ; +} + +extern "C" void UART0_IRQHandler() +{ + serial2RxFifo.push(SECOND_SERIAL_UART->UART_RHR); +} +#else +#define SECOND_UART_Configure(...) +#endif + +#if defined(TELEMETRY_FRSKY) +void serial2TelemetryInit(unsigned int /*protocol*/) +{ + SECOND_UART_Configure(FRSKY_D_BAUDRATE, Master_frequency); + // startPdcUsartReceive(); +} + +bool telemetrySecondPortReceive(uint8_t & data) +{ + return serial2RxFifo.pop(data); +} +#endif diff --git a/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.c b/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.c index 91f6d4116..e812682d1 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.c +++ b/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.c @@ -1,162 +1,162 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBConfigurationDescriptor implementation - - About: Purpose - Implementation of the USBConfigurationDescriptor class. -*/ - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "../../../usb/common/core/USBConfigurationDescriptor.h" - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Returns the total length of a configuration, i.e. including the -/// descriptors following it. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return Total length (in bytes) of the configuration. -//----------------------------------------------------------------------------- -unsigned int USBConfigurationDescriptor_GetTotalLength( - const USBConfigurationDescriptor *configuration) -{ - return configuration->wTotalLength; -} - -//----------------------------------------------------------------------------- -/// Returns the number of interfaces in a configuration. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return Number of interfaces in configuration. -//----------------------------------------------------------------------------- -unsigned char USBConfigurationDescriptor_GetNumInterfaces( - const USBConfigurationDescriptor *configuration) -{ - return configuration->bNumInterfaces; -} - -//----------------------------------------------------------------------------- -/// Indicates if the device is self-powered when in a given configuration. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return 1 if the device is self-powered when in the given configuration; -/// otherwise 0. -//----------------------------------------------------------------------------- -unsigned char USBConfigurationDescriptor_IsSelfPowered( - const USBConfigurationDescriptor *configuration) -{ - if ((configuration->bmAttributes & (1 << 6)) != 0) { - - return 1; - } - else { - - return 0; - } -} - -//----------------------------------------------------------------------------- -/// Parses the given Configuration descriptor (followed by relevant -/// interface, endpoint and class-specific descriptors) into three arrays. -/// *Each array must have its size equal or greater to the number of -/// descriptors it stores plus one*. A null-value is inserted after the last -/// descriptor of each type to indicate the array end. -/// -/// Note that if the pointer to an array is null (0), nothing is stored in -/// it. -/// \param configuration Pointer to the start of the whole Configuration -/// descriptor. -/// \param interfaces Pointer to the Interface descriptor array. -/// \param endpoints Pointer to the Endpoint descriptor array. -/// \param others Pointer to the class-specific descriptor array. -//----------------------------------------------------------------------------- -void USBConfigurationDescriptor_Parse( - const USBConfigurationDescriptor *configuration, - USBInterfaceDescriptor **interfaces, - USBEndpointDescriptor **endpoints, - USBGenericDescriptor **others) -{ - // Get size of configuration to parse - int size = USBConfigurationDescriptor_GetTotalLength(configuration); - size -= sizeof(USBConfigurationDescriptor); - - // Start parsing descriptors - USBGenericDescriptor *descriptor = (USBGenericDescriptor *) configuration; - while (size > 0) { - - // Get next descriptor - descriptor = USBGenericDescriptor_GetNextDescriptor(descriptor); - size -= USBGenericDescriptor_GetLength(descriptor); - - // Store descriptor in correponding array - if (USBGenericDescriptor_GetType(descriptor) - == USBGenericDescriptor_INTERFACE) { - - if (interfaces) { - - *interfaces = (USBInterfaceDescriptor *) descriptor; - interfaces++; - } - } - else if (USBGenericDescriptor_GetType(descriptor) - == USBGenericDescriptor_ENDPOINT) { - - if (endpoints) { - - *endpoints = (USBEndpointDescriptor *) descriptor; - endpoints++; - } - } - else if (others) { - - *others = descriptor; - others++; - } - } - - // Null-terminate arrays - if (interfaces) { - - *interfaces = 0; - } - if (endpoints) { - - *endpoints = 0; - } - if (others) { - - *others = 0; - } -} - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBConfigurationDescriptor implementation + + About: Purpose + Implementation of the USBConfigurationDescriptor class. +*/ + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- + +#include "../../../usb/common/core/USBConfigurationDescriptor.h" + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Returns the total length of a configuration, i.e. including the +/// descriptors following it. +/// \param configuration Pointer to a USBConfigurationDescriptor instance. +/// \return Total length (in bytes) of the configuration. +//----------------------------------------------------------------------------- +unsigned int USBConfigurationDescriptor_GetTotalLength( + const USBConfigurationDescriptor *configuration) +{ + return configuration->wTotalLength; +} + +//----------------------------------------------------------------------------- +/// Returns the number of interfaces in a configuration. +/// \param configuration Pointer to a USBConfigurationDescriptor instance. +/// \return Number of interfaces in configuration. +//----------------------------------------------------------------------------- +unsigned char USBConfigurationDescriptor_GetNumInterfaces( + const USBConfigurationDescriptor *configuration) +{ + return configuration->bNumInterfaces; +} + +//----------------------------------------------------------------------------- +/// Indicates if the device is self-powered when in a given configuration. +/// \param configuration Pointer to a USBConfigurationDescriptor instance. +/// \return 1 if the device is self-powered when in the given configuration; +/// otherwise 0. +//----------------------------------------------------------------------------- +unsigned char USBConfigurationDescriptor_IsSelfPowered( + const USBConfigurationDescriptor *configuration) +{ + if ((configuration->bmAttributes & (1 << 6)) != 0) { + + return 1; + } + else { + + return 0; + } +} + +//----------------------------------------------------------------------------- +/// Parses the given Configuration descriptor (followed by relevant +/// interface, endpoint and class-specific descriptors) into three arrays. +/// *Each array must have its size equal or greater to the number of +/// descriptors it stores plus one*. A null-value is inserted after the last +/// descriptor of each type to indicate the array end. +/// +/// Note that if the pointer to an array is null (0), nothing is stored in +/// it. +/// \param configuration Pointer to the start of the whole Configuration +/// descriptor. +/// \param interfaces Pointer to the Interface descriptor array. +/// \param endpoints Pointer to the Endpoint descriptor array. +/// \param others Pointer to the class-specific descriptor array. +//----------------------------------------------------------------------------- +void USBConfigurationDescriptor_Parse( + const USBConfigurationDescriptor *configuration, + USBInterfaceDescriptor **interfaces, + USBEndpointDescriptor **endpoints, + USBGenericDescriptor **others) +{ + // Get size of configuration to parse + int size = USBConfigurationDescriptor_GetTotalLength(configuration); + size -= sizeof(USBConfigurationDescriptor); + + // Start parsing descriptors + USBGenericDescriptor *descriptor = (USBGenericDescriptor *) configuration; + while (size > 0) { + + // Get next descriptor + descriptor = USBGenericDescriptor_GetNextDescriptor(descriptor); + size -= USBGenericDescriptor_GetLength(descriptor); + + // Store descriptor in correponding array + if (USBGenericDescriptor_GetType(descriptor) + == USBGenericDescriptor_INTERFACE) { + + if (interfaces) { + + *interfaces = (USBInterfaceDescriptor *) descriptor; + interfaces++; + } + } + else if (USBGenericDescriptor_GetType(descriptor) + == USBGenericDescriptor_ENDPOINT) { + + if (endpoints) { + + *endpoints = (USBEndpointDescriptor *) descriptor; + endpoints++; + } + } + else if (others) { + + *others = descriptor; + others++; + } + } + + // Null-terminate arrays + if (interfaces) { + + *interfaces = 0; + } + if (endpoints) { + + *endpoints = 0; + } + if (others) { + + *others = 0; + } +} + diff --git a/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.h index ba9006b04..445ff4b9a 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.h +++ b/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.h @@ -1,150 +1,150 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - !!!Purpose - - Definitions and methods for USB configuration descriptor structures - described by the USB specification. - - !!!Usage - - -# Declare USBConfigurationDescriptor instance as a part - of the configuration descriptors of a USB device. - -# To get useful information (field values) from the defined USB device - configuration descriptor, use - - USBConfigurationDescriptor_GetTotalLength - - USBConfigurationDescriptor_GetNumInterfaces - - USBConfigurationDescriptor_IsSelfPowered - -# To pase the defined USB device configuration descriptor, use - - USBConfigurationDescriptor_Parse -*/ - -#ifndef USBCONFIGURATIONDESCRIPTOR_H -#define USBCONFIGURATIONDESCRIPTOR_H - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "../../../usb/common/core/USBEndpointDescriptor.h" -#include "../../../usb/common/core/USBGenericDescriptor.h" -#include "../../../usb/common/core/USBInterfaceDescriptor.h" - -//----------------------------------------------------------------------------- -// Definitions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// \page "USB device Attributes" -/// -/// This page lists the codes of the usb attributes. -/// -/// !Attributes -/// - USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP -/// - USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP -/// - USBConfigurationDescriptor_BUSPOWERED_RWAKEUP -/// - USBConfigurationDescriptor_SELFPOWERED_RWAKEUP -/// - USBConfigurationDescriptor_POWER - -/// Device is bus-powered and not support remote wake-up. -#define USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP 0x80 -/// Device is self-powered and not support remote wake-up. -#define USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP 0xC0 -/// Device is bus-powered and supports remote wake-up. -#define USBConfigurationDescriptor_BUSPOWERED_RWAKEUP 0xA0 -/// Device is self-powered and supports remote wake-up. -#define USBConfigurationDescriptor_SELFPOWERED_RWAKEUP 0xE0 - -/// Calculates the value of the power consumption field given the value in mA. -/// \param power The power consumption value in mA -/// \return The value that should be set to the field in descriptor -#define USBConfigurationDescriptor_POWER(power) (power / 2) -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -// Types -//----------------------------------------------------------------------------- - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//----------------------------------------------------------------------------- -/// USB standard configuration descriptor structure. -//----------------------------------------------------------------------------- -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBDESC_CONFIGURATION of "USB Descriptor types"). - unsigned char bDescriptorType; - /// Length of all descriptors returned along with this configuration - /// descriptor. - unsigned short wTotalLength; - /// Number of interfaces in this configuration. - unsigned char bNumInterfaces; - /// Value for selecting this configuration. - unsigned char bConfigurationValue; - /// Index of the configuration string descriptor. - unsigned char iConfiguration; - /// Configuration characteristics. - unsigned char bmAttributes; - /// Maximum power consumption of the device when in this configuration. - unsigned char bMaxPower; - -} __attribute__ ((packed)) USBConfigurationDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -extern unsigned int USBConfigurationDescriptor_GetTotalLength( - const USBConfigurationDescriptor *configuration); - -extern unsigned char USBConfigurationDescriptor_GetNumInterfaces( - const USBConfigurationDescriptor *configuration); - -extern unsigned char USBConfigurationDescriptor_IsSelfPowered( - const USBConfigurationDescriptor *configuration); - -extern void USBConfigurationDescriptor_Parse( - const USBConfigurationDescriptor *configuration, - USBInterfaceDescriptor **interfaces, - USBEndpointDescriptor **endpoints, - USBGenericDescriptor **others); - -#endif //#ifndef USBCONFIGURATIONDESCRIPTOR_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + !!!Purpose + + Definitions and methods for USB configuration descriptor structures + described by the USB specification. + + !!!Usage + + -# Declare USBConfigurationDescriptor instance as a part + of the configuration descriptors of a USB device. + -# To get useful information (field values) from the defined USB device + configuration descriptor, use + - USBConfigurationDescriptor_GetTotalLength + - USBConfigurationDescriptor_GetNumInterfaces + - USBConfigurationDescriptor_IsSelfPowered + -# To pase the defined USB device configuration descriptor, use + - USBConfigurationDescriptor_Parse +*/ + +#ifndef USBCONFIGURATIONDESCRIPTOR_H +#define USBCONFIGURATIONDESCRIPTOR_H + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- + +#include "../../../usb/common/core/USBEndpointDescriptor.h" +#include "../../../usb/common/core/USBGenericDescriptor.h" +#include "../../../usb/common/core/USBInterfaceDescriptor.h" + +//----------------------------------------------------------------------------- +// Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// \page "USB device Attributes" +/// +/// This page lists the codes of the usb attributes. +/// +/// !Attributes +/// - USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP +/// - USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP +/// - USBConfigurationDescriptor_BUSPOWERED_RWAKEUP +/// - USBConfigurationDescriptor_SELFPOWERED_RWAKEUP +/// - USBConfigurationDescriptor_POWER + +/// Device is bus-powered and not support remote wake-up. +#define USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP 0x80 +/// Device is self-powered and not support remote wake-up. +#define USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP 0xC0 +/// Device is bus-powered and supports remote wake-up. +#define USBConfigurationDescriptor_BUSPOWERED_RWAKEUP 0xA0 +/// Device is self-powered and supports remote wake-up. +#define USBConfigurationDescriptor_SELFPOWERED_RWAKEUP 0xE0 + +/// Calculates the value of the power consumption field given the value in mA. +/// \param power The power consumption value in mA +/// \return The value that should be set to the field in descriptor +#define USBConfigurationDescriptor_POWER(power) (power / 2) +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Types +//----------------------------------------------------------------------------- + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//----------------------------------------------------------------------------- +/// USB standard configuration descriptor structure. +//----------------------------------------------------------------------------- +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBDESC_CONFIGURATION of "USB Descriptor types"). + unsigned char bDescriptorType; + /// Length of all descriptors returned along with this configuration + /// descriptor. + unsigned short wTotalLength; + /// Number of interfaces in this configuration. + unsigned char bNumInterfaces; + /// Value for selecting this configuration. + unsigned char bConfigurationValue; + /// Index of the configuration string descriptor. + unsigned char iConfiguration; + /// Configuration characteristics. + unsigned char bmAttributes; + /// Maximum power consumption of the device when in this configuration. + unsigned char bMaxPower; + +} __attribute__ ((packed)) USBConfigurationDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +extern unsigned int USBConfigurationDescriptor_GetTotalLength( + const USBConfigurationDescriptor *configuration); + +extern unsigned char USBConfigurationDescriptor_GetNumInterfaces( + const USBConfigurationDescriptor *configuration); + +extern unsigned char USBConfigurationDescriptor_IsSelfPowered( + const USBConfigurationDescriptor *configuration); + +extern void USBConfigurationDescriptor_Parse( + const USBConfigurationDescriptor *configuration, + USBInterfaceDescriptor **interfaces, + USBEndpointDescriptor **endpoints, + USBGenericDescriptor **others); + +#endif //#ifndef USBCONFIGURATIONDESCRIPTOR_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBDeviceDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBDeviceDescriptor.h index 22fc1a410..8a8186ce7 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBDeviceDescriptor.h +++ b/radio/src/targets/sky9x/usb/common/core/USBDeviceDescriptor.h @@ -1,125 +1,125 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - !!!Purpose - - Class for manipulating USB device descriptors. - - !!!Usage - - - Declare a USBDeviceDescriptor instance as the device descriptor of a - USB device. -*/ - -#ifndef USBDEVICEDESCRIPTOR_H -#define USBDEVICEDESCRIPTOR_H - -#include "board_lowlevel.h" -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB release numbers" -/// -/// This page lists the codes of USB release numbers. -/// -/// !Code -/// - USBDeviceDescriptor_USB2_00 - -/// The device supports USB 2.00. -#define USBDeviceDescriptor_USB2_00 0x0200 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard device descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of this descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_DEVICE). - unsigned char bDescriptorType; - /// USB specification release number in BCD format. - unsigned short bcdUSB; - /// Device class code. - unsigned char bDeviceClass; - /// Device subclass code. - unsigned char bDeviceSubClass; - /// Device protocol code. - unsigned char bDeviceProtocol; - /// Maximum packet size of endpoint 0 (in bytes). - unsigned char bMaxPacketSize0; - /// Vendor ID. - unsigned short idVendor; - /// Product ID. - unsigned short idProduct; - /// Device release number in BCD format. - unsigned short bcdDevice; - /// Index of the manufacturer string descriptor. - unsigned char iManufacturer; - /// Index of the product string descriptor. - unsigned char iProduct; - /// Index of the serial number string descriptor. - unsigned char iSerialNumber; - /// Number of possible configurations for the device. - unsigned char bNumConfigurations; - -} __attribute__ ((packed)) USBDeviceDescriptor; // GCC - -#if defined(CHIP_USB_OTGHS) -typedef struct { - - /// Size of this descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_OTG). - unsigned char bDescriptorType; - /// Attribute Fields D7�2: Reserved D1: HNP support D0: SRP support - unsigned char bmAttributes; - -} __attribute__ ((packed)) USBOtgDescriptor; // GCC -#endif - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDEVICEDESCRIPTOR_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + !!!Purpose + + Class for manipulating USB device descriptors. + + !!!Usage + + - Declare a USBDeviceDescriptor instance as the device descriptor of a + USB device. +*/ + +#ifndef USBDEVICEDESCRIPTOR_H +#define USBDEVICEDESCRIPTOR_H + +#include "board_lowlevel.h" +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB release numbers" +/// +/// This page lists the codes of USB release numbers. +/// +/// !Code +/// - USBDeviceDescriptor_USB2_00 + +/// The device supports USB 2.00. +#define USBDeviceDescriptor_USB2_00 0x0200 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// USB standard device descriptor structure. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of this descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBGenericDescriptor_DEVICE). + unsigned char bDescriptorType; + /// USB specification release number in BCD format. + unsigned short bcdUSB; + /// Device class code. + unsigned char bDeviceClass; + /// Device subclass code. + unsigned char bDeviceSubClass; + /// Device protocol code. + unsigned char bDeviceProtocol; + /// Maximum packet size of endpoint 0 (in bytes). + unsigned char bMaxPacketSize0; + /// Vendor ID. + unsigned short idVendor; + /// Product ID. + unsigned short idProduct; + /// Device release number in BCD format. + unsigned short bcdDevice; + /// Index of the manufacturer string descriptor. + unsigned char iManufacturer; + /// Index of the product string descriptor. + unsigned char iProduct; + /// Index of the serial number string descriptor. + unsigned char iSerialNumber; + /// Number of possible configurations for the device. + unsigned char bNumConfigurations; + +} __attribute__ ((packed)) USBDeviceDescriptor; // GCC + +#if defined(CHIP_USB_OTGHS) +typedef struct { + + /// Size of this descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBGenericDescriptor_OTG). + unsigned char bDescriptorType; + /// Attribute Fields D7�2: Reserved D1: HNP support D0: SRP support + unsigned char bmAttributes; + +} __attribute__ ((packed)) USBOtgDescriptor; // GCC +#endif + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef USBDEVICEDESCRIPTOR_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBDeviceQualifierDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBDeviceQualifierDescriptor.h index 3728865de..5632e18c5 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBDeviceQualifierDescriptor.h +++ b/radio/src/targets/sky9x/usb/common/core/USBDeviceQualifierDescriptor.h @@ -1,89 +1,89 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Class for manipulating USB device qualifier descriptors. - - !!!Usage - - - Declare a USBDeviceQualifierDescriptor instance as the device qualifier - descriptor of a USB device. -*/ - -#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H -#define USBDEVICEQUALIFIERDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// Alternate device descriptor indicating the capabilities of the device -/// in full-speed, if currently in high-speed; or in high-speed, if it is -/// currently in full-speed. Only relevant for devices supporting the -/// high-speed mode. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBDESC_DEVICE_QUALIFIER or "USB device types"). - unsigned char bDescriptorType; - /// USB specification release number (in BCD format). - unsigned short bcdUSB; - /// Device class code. - unsigned char bDeviceClass; - /// Device subclass code. - unsigned char bDeviceSubClass; - /// Device protocol code. - unsigned char bDeviceProtocol; - /// Maximum packet size of endpoint 0. - unsigned char bMaxPacketSize0; - /// Number of possible configurations for the device. - unsigned char bNumConfigurations; - /// Reserved. - unsigned char bReserved; - -} __attribute__ ((packed)) USBDeviceQualifierDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Class for manipulating USB device qualifier descriptors. + + !!!Usage + + - Declare a USBDeviceQualifierDescriptor instance as the device qualifier + descriptor of a USB device. +*/ + +#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H +#define USBDEVICEQUALIFIERDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// Alternate device descriptor indicating the capabilities of the device +/// in full-speed, if currently in high-speed; or in high-speed, if it is +/// currently in full-speed. Only relevant for devices supporting the +/// high-speed mode. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBDESC_DEVICE_QUALIFIER or "USB device types"). + unsigned char bDescriptorType; + /// USB specification release number (in BCD format). + unsigned short bcdUSB; + /// Device class code. + unsigned char bDeviceClass; + /// Device subclass code. + unsigned char bDeviceSubClass; + /// Device protocol code. + unsigned char bDeviceProtocol; + /// Maximum packet size of endpoint 0. + unsigned char bMaxPacketSize0; + /// Number of possible configurations for the device. + unsigned char bNumConfigurations; + /// Reserved. + unsigned char bReserved; + +} __attribute__ ((packed)) USBDeviceQualifierDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.c b/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.c index 5cae1bc5c..e20176d3c 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.c +++ b/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.c @@ -1,109 +1,109 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBEndpointDescriptor implementation - - About: Purpose - Implementation of the USBEndpointDescriptor class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBEndpointDescriptor.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the number of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint number. -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetNumber( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bEndpointAddress & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the direction of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint direction (see ). -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetDirection( - const USBEndpointDescriptor *endpoint) -{ - if ((endpoint->bEndpointAddress & 0x80) != 0) { - - return USBEndpointDescriptor_IN; - } - else { - - return USBEndpointDescriptor_OUT; - } -} - -//------------------------------------------------------------------------------ -/// Returns the type of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint type (see ). -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetType( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bmAttributes & 0x3; -} - -//------------------------------------------------------------------------------ -/// Returns the maximum size of a packet (in bytes) on an endpoint given -/// its descriptor. -/// \param endpoint - Pointer to a USBEndpointDescriptor instance. -/// \return Maximum packet size of endpoint. -//------------------------------------------------------------------------------ -unsigned short USBEndpointDescriptor_GetMaxPacketSize( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->wMaxPacketSize; -} - -//------------------------------------------------------------------------------ -/// Returns the polling interval on an endpoint given its descriptor. -/// \param endpoint - Pointer to a USBEndpointDescriptor instance. -/// \return Polling interval of endpoint. -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetInterval( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bInterval; -} - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBEndpointDescriptor implementation + + About: Purpose + Implementation of the USBEndpointDescriptor class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBEndpointDescriptor.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the number of an endpoint given its descriptor. +/// \param endpoint Pointer to a USBEndpointDescriptor instance. +/// \return Endpoint number. +//------------------------------------------------------------------------------ +unsigned char USBEndpointDescriptor_GetNumber( + const USBEndpointDescriptor *endpoint) +{ + return endpoint->bEndpointAddress & 0xF; +} + +//------------------------------------------------------------------------------ +/// Returns the direction of an endpoint given its descriptor. +/// \param endpoint Pointer to a USBEndpointDescriptor instance. +/// \return Endpoint direction (see ). +//------------------------------------------------------------------------------ +unsigned char USBEndpointDescriptor_GetDirection( + const USBEndpointDescriptor *endpoint) +{ + if ((endpoint->bEndpointAddress & 0x80) != 0) { + + return USBEndpointDescriptor_IN; + } + else { + + return USBEndpointDescriptor_OUT; + } +} + +//------------------------------------------------------------------------------ +/// Returns the type of an endpoint given its descriptor. +/// \param endpoint Pointer to a USBEndpointDescriptor instance. +/// \return Endpoint type (see ). +//------------------------------------------------------------------------------ +unsigned char USBEndpointDescriptor_GetType( + const USBEndpointDescriptor *endpoint) +{ + return endpoint->bmAttributes & 0x3; +} + +//------------------------------------------------------------------------------ +/// Returns the maximum size of a packet (in bytes) on an endpoint given +/// its descriptor. +/// \param endpoint - Pointer to a USBEndpointDescriptor instance. +/// \return Maximum packet size of endpoint. +//------------------------------------------------------------------------------ +unsigned short USBEndpointDescriptor_GetMaxPacketSize( + const USBEndpointDescriptor *endpoint) +{ + return endpoint->wMaxPacketSize; +} + +//------------------------------------------------------------------------------ +/// Returns the polling interval on an endpoint given its descriptor. +/// \param endpoint - Pointer to a USBEndpointDescriptor instance. +/// \return Polling interval of endpoint. +//------------------------------------------------------------------------------ +unsigned char USBEndpointDescriptor_GetInterval( + const USBEndpointDescriptor *endpoint) +{ + return endpoint->bInterval; +} + diff --git a/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.h index d49e02868..8a691eec2 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.h +++ b/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.h @@ -1,224 +1,224 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for handling USB endpoint descriptors. - - !!!Usage - - -# Declare USBEndpointDescriptor instance as a part of the - configuration descriptors of a USB device. - -# To get useful information (field values) from the defined USB device - endpoint descriptor (to configure hardware for endpoints, etc), use - - USBEndpointDescriptor_GetNumber - - USBEndpointDescriptor_GetDirection - - USBEndpointDescriptor_GetType - - USBEndpointDescriptor_GetMaxPacketSize -*/ - -#ifndef USBENDPOINTDESCRIPTOR_H -#define USBENDPOINTDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint definitions" -/// -/// This page lists definitions and macro for endpoint descriptors. -/// -/// - USB Endpoint directions -/// - USBEndpointDescriptor_OUT -/// - USBEndpointDescriptor_IN -/// -/// - USB Endpoint types -/// - USBEndpointDescriptor_CONTROL -/// - USBEndpointDescriptor_ISOCHRONOUS -/// - USBEndpointDescriptor_BULK -/// - USBEndpointDescriptor_INTERRUPT -/// -/// - USB Endpoint maximun sizes -/// - USBEndpointDescriptor_MAXCTRLSIZE_FS -/// - USBEndpointDescriptor_MAXCTRLSIZE_HS -/// - USBEndpointDescriptor_MAXBULKSIZE_FS -/// - USBEndpointDescriptor_MAXBULKSIZE_HS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS -/// -/// - USB Endpoint address define -/// - USBEndpointDescriptor_ADDRESS -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint directions" -/// -/// This page lists definitions of USB endpoint directions. -/// -/// !Directions -/// - USBEndpointDescriptor_OUT -/// - USBEndpointDescriptor_IN - -/// Endpoint receives data from the host. -#define USBEndpointDescriptor_OUT 0 -/// Endpoint sends data to the host. -#define USBEndpointDescriptor_IN 1 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint types" -/// -/// This page lists definitions of USB endpoint types. -/// -/// !Types -/// - USBEndpointDescriptor_CONTROL -/// - USBEndpointDescriptor_ISOCHRONOUS -/// - USBEndpointDescriptor_BULK -/// - USBEndpointDescriptor_INTERRUPT - -/// Control endpoint type. -#define USBEndpointDescriptor_CONTROL 0 -/// Isochronous endpoint type. -#define USBEndpointDescriptor_ISOCHRONOUS 1 -/// Bulk endpoint type. -#define USBEndpointDescriptor_BULK 2 -/// Interrupt endpoint type. -#define USBEndpointDescriptor_INTERRUPT 3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint maximun sizes" -/// -/// This page lists definitions of USB endpoint maximun sizes. -/// -/// !Sizes -/// - USBEndpointDescriptor_MAXCTRLSIZE_FS -/// - USBEndpointDescriptor_MAXCTRLSIZE_HS -/// - USBEndpointDescriptor_MAXBULKSIZE_FS -/// - USBEndpointDescriptor_MAXBULKSIZE_HS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS - -/// Maximum size for a full-speed control endpoint. -#define USBEndpointDescriptor_MAXCTRLSIZE_FS 64 -/// Maximum size for a high-speed control endpoint. -#define USBEndpointDescriptor_MAXCTRLSIZE_HS 64 -/// Maximum size for a full-speed bulk endpoint. -#define USBEndpointDescriptor_MAXBULKSIZE_FS 64 -/// Maximum size for a high-speed bulk endpoint. -#define USBEndpointDescriptor_MAXBULKSIZE_HS 512 -/// Maximum size for a full-speed interrupt endpoint. -#define USBEndpointDescriptor_MAXINTERRUPTSIZE_FS 64 -/// Maximum size for a high-speed interrupt endpoint. -#define USBEndpointDescriptor_MAXINTERRUPTSIZE_HS 1024 -/// Maximum size for a full-speed isochronous endpoint. -#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS 1023 -/// Maximum size for a high-speed isochronous endpoint. -#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS 1024 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint address define" -/// -/// This page lists macro for USB endpoint address definition. -/// -/// !Macro -/// - USBEndpointDescriptor_ADDRESS - -/// Calculates the address of an endpoint given its number and direction -/// \param direction USB endpoint direction definition -/// \param number USB endpoint number -/// \return The value used to set the endpoint descriptor based on input number -/// and direction -#define USBEndpointDescriptor_ADDRESS(direction, number) \ - (((direction & 0x01) << 7) | (number & 0xF)) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard endpoint descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (). - unsigned char bDescriptorType; - /// Address and direction of the endpoint. - unsigned char bEndpointAddress; - /// Endpoint type and additional characteristics (for isochronous endpoints). - unsigned char bmAttributes; - /// Maximum packet size (in bytes) of the endpoint. - unsigned short wMaxPacketSize; - /// Polling rate of the endpoint. - unsigned char bInterval; - -} __attribute__ ((packed)) USBEndpointDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBEndpointDescriptor_GetNumber( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetDirection( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetType( - const USBEndpointDescriptor *endpoint); - -extern unsigned short USBEndpointDescriptor_GetMaxPacketSize( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetInterval( - const USBEndpointDescriptor *endpoint); - -#endif //#ifndef USBENDPOINTDESCRIPTOR_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for handling USB endpoint descriptors. + + !!!Usage + + -# Declare USBEndpointDescriptor instance as a part of the + configuration descriptors of a USB device. + -# To get useful information (field values) from the defined USB device + endpoint descriptor (to configure hardware for endpoints, etc), use + - USBEndpointDescriptor_GetNumber + - USBEndpointDescriptor_GetDirection + - USBEndpointDescriptor_GetType + - USBEndpointDescriptor_GetMaxPacketSize +*/ + +#ifndef USBENDPOINTDESCRIPTOR_H +#define USBENDPOINTDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint definitions" +/// +/// This page lists definitions and macro for endpoint descriptors. +/// +/// - USB Endpoint directions +/// - USBEndpointDescriptor_OUT +/// - USBEndpointDescriptor_IN +/// +/// - USB Endpoint types +/// - USBEndpointDescriptor_CONTROL +/// - USBEndpointDescriptor_ISOCHRONOUS +/// - USBEndpointDescriptor_BULK +/// - USBEndpointDescriptor_INTERRUPT +/// +/// - USB Endpoint maximun sizes +/// - USBEndpointDescriptor_MAXCTRLSIZE_FS +/// - USBEndpointDescriptor_MAXCTRLSIZE_HS +/// - USBEndpointDescriptor_MAXBULKSIZE_FS +/// - USBEndpointDescriptor_MAXBULKSIZE_HS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS +/// +/// - USB Endpoint address define +/// - USBEndpointDescriptor_ADDRESS +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint directions" +/// +/// This page lists definitions of USB endpoint directions. +/// +/// !Directions +/// - USBEndpointDescriptor_OUT +/// - USBEndpointDescriptor_IN + +/// Endpoint receives data from the host. +#define USBEndpointDescriptor_OUT 0 +/// Endpoint sends data to the host. +#define USBEndpointDescriptor_IN 1 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint types" +/// +/// This page lists definitions of USB endpoint types. +/// +/// !Types +/// - USBEndpointDescriptor_CONTROL +/// - USBEndpointDescriptor_ISOCHRONOUS +/// - USBEndpointDescriptor_BULK +/// - USBEndpointDescriptor_INTERRUPT + +/// Control endpoint type. +#define USBEndpointDescriptor_CONTROL 0 +/// Isochronous endpoint type. +#define USBEndpointDescriptor_ISOCHRONOUS 1 +/// Bulk endpoint type. +#define USBEndpointDescriptor_BULK 2 +/// Interrupt endpoint type. +#define USBEndpointDescriptor_INTERRUPT 3 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint maximun sizes" +/// +/// This page lists definitions of USB endpoint maximun sizes. +/// +/// !Sizes +/// - USBEndpointDescriptor_MAXCTRLSIZE_FS +/// - USBEndpointDescriptor_MAXCTRLSIZE_HS +/// - USBEndpointDescriptor_MAXBULKSIZE_FS +/// - USBEndpointDescriptor_MAXBULKSIZE_HS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS + +/// Maximum size for a full-speed control endpoint. +#define USBEndpointDescriptor_MAXCTRLSIZE_FS 64 +/// Maximum size for a high-speed control endpoint. +#define USBEndpointDescriptor_MAXCTRLSIZE_HS 64 +/// Maximum size for a full-speed bulk endpoint. +#define USBEndpointDescriptor_MAXBULKSIZE_FS 64 +/// Maximum size for a high-speed bulk endpoint. +#define USBEndpointDescriptor_MAXBULKSIZE_HS 512 +/// Maximum size for a full-speed interrupt endpoint. +#define USBEndpointDescriptor_MAXINTERRUPTSIZE_FS 64 +/// Maximum size for a high-speed interrupt endpoint. +#define USBEndpointDescriptor_MAXINTERRUPTSIZE_HS 1024 +/// Maximum size for a full-speed isochronous endpoint. +#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS 1023 +/// Maximum size for a high-speed isochronous endpoint. +#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS 1024 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint address define" +/// +/// This page lists macro for USB endpoint address definition. +/// +/// !Macro +/// - USBEndpointDescriptor_ADDRESS + +/// Calculates the address of an endpoint given its number and direction +/// \param direction USB endpoint direction definition +/// \param number USB endpoint number +/// \return The value used to set the endpoint descriptor based on input number +/// and direction +#define USBEndpointDescriptor_ADDRESS(direction, number) \ + (((direction & 0x01) << 7) | (number & 0xF)) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// USB standard endpoint descriptor structure. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (). + unsigned char bDescriptorType; + /// Address and direction of the endpoint. + unsigned char bEndpointAddress; + /// Endpoint type and additional characteristics (for isochronous endpoints). + unsigned char bmAttributes; + /// Maximum packet size (in bytes) of the endpoint. + unsigned short wMaxPacketSize; + /// Polling rate of the endpoint. + unsigned char bInterval; + +} __attribute__ ((packed)) USBEndpointDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBEndpointDescriptor_GetNumber( + const USBEndpointDescriptor *endpoint); + +extern unsigned char USBEndpointDescriptor_GetDirection( + const USBEndpointDescriptor *endpoint); + +extern unsigned char USBEndpointDescriptor_GetType( + const USBEndpointDescriptor *endpoint); + +extern unsigned short USBEndpointDescriptor_GetMaxPacketSize( + const USBEndpointDescriptor *endpoint); + +extern unsigned char USBEndpointDescriptor_GetInterval( + const USBEndpointDescriptor *endpoint); + +#endif //#ifndef USBENDPOINTDESCRIPTOR_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.c b/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.c index ec2ea8ae1..55d6cba48 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.c +++ b/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.c @@ -1,70 +1,70 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBFeatureRequest implementation - - About: Purpose - Implementation of the USBFeatureRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBFeatureRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the feature selector of a given CLEAR_FEATURE or SET_FEATURE -/// request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Feature selector. -//------------------------------------------------------------------------------ -unsigned char USBFeatureRequest_GetFeatureSelector( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request); -} - -//------------------------------------------------------------------------------ -/// Indicates the test that the device must undertake following a -/// SET_FEATURE request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Test selector. -//------------------------------------------------------------------------------ -unsigned char USBFeatureRequest_GetTestSelector( - const USBGenericRequest *request) -{ - return (USBGenericRequest_GetIndex(request) >> 8) & 0xFF; -} - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBFeatureRequest implementation + + About: Purpose + Implementation of the USBFeatureRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBFeatureRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the feature selector of a given CLEAR_FEATURE or SET_FEATURE +/// request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Feature selector. +//------------------------------------------------------------------------------ +unsigned char USBFeatureRequest_GetFeatureSelector( + const USBGenericRequest *request) +{ + return USBGenericRequest_GetValue(request); +} + +//------------------------------------------------------------------------------ +/// Indicates the test that the device must undertake following a +/// SET_FEATURE request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Test selector. +//------------------------------------------------------------------------------ +unsigned char USBFeatureRequest_GetTestSelector( + const USBGenericRequest *request) +{ + return (USBGenericRequest_GetIndex(request) >> 8) & 0xFF; +} + diff --git a/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.h b/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.h index 4c1f3640e..16fbbc318 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.h +++ b/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.h @@ -1,146 +1,146 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating CLEAR_FEATURE and SET_FEATURE - requests. - - !!!Usage - - - To get USB feature request information (field values) from the - USBGenericRequest instance, use - - USBFeatureRequest_GetFeatureSelector - - USBFeatureRequest_GetTestSelector -*/ - -#ifndef USBFEATUREREQUEST_H -#define USBFEATUREREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Feature Request definitions" -/// -/// This page lists codes of USB Feature Request -/// -/// - USB Feature selectors -/// - USBFeatureRequest_ENDPOINTHALT -/// - USBFeatureRequest_DEVICEREMOTEWAKEUP -/// - USBFeatureRequest_TESTMODE -/// -/// - USB Test mode selectors -/// - USBFeatureRequest_TESTJ -/// - USBFeatureRequest_TESTK -/// - USBFeatureRequest_TESTSE0NAK -/// - USBFeatureRequest_TESTPACKET -/// - USBFeatureRequest_TESTFORCEENABLE -/// - USBFeatureRequest_TESTSENDZLP -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Feature selectors" -/// -/// This page lists codes of USB feature selectors. -/// -/// !Selectors -/// - USBFeatureRequest_ENDPOINTHALT -/// - USBFeatureRequest_DEVICEREMOTEWAKEUP -/// - USBFeatureRequest_TESTMODE - -/// Halt feature of an endpoint. -#define USBFeatureRequest_ENDPOINTHALT 0 -/// Remote wake-up feature of the device. -#define USBFeatureRequest_DEVICEREMOTEWAKEUP 1 -/// Test mode of the device. -#define USBFeatureRequest_TESTMODE 2 -/// OTG set feature -#define USBFeatureRequest_OTG 0x0B -//------------------------------------------------------------------------------ - -/// On The Go Feature Selectors -/// b_hnp_enable 3 -/// a_hnp_support 4 -/// a_alt_hnp_support 5 -#define USBFeatureRequest_OTG_B_HNP_ENABLE 3 -#define USBFeatureRequest_OTG_A_HNP_SUPPORT 4 -#define USBFeatureRequest_OTG_A_ALT_HNP_SUPPORT 5 - -//------------------------------------------------------------------------------ -/// \page "USB Test mode selectors" -/// -/// This page lists codes of USB high speed test mode selectors. -/// -/// !Selectors -/// - USBFeatureRequest_TESTJ -/// - USBFeatureRequest_TESTK -/// - USBFeatureRequest_TESTSE0NAK -/// - USBFeatureRequest_TESTPACKET -/// - USBFeatureRequest_TESTFORCEENABLE -/// - USBFeatureRequest_TESTSENDZLP - -/// Tests the high-output drive level on the D+ line. -#define USBFeatureRequest_TESTJ 1 -/// Tests the high-output drive level on the D- line. -#define USBFeatureRequest_TESTK 2 -/// Tests the output impedance, low-level output voltage and loading -/// characteristics. -#define USBFeatureRequest_TESTSE0NAK 3 -/// Tests rise and fall times, eye patterns and jitter. -#define USBFeatureRequest_TESTPACKET 4 -/// Tests the hub disconnect detection. -#define USBFeatureRequest_TESTFORCEENABLE 5 -/// Send a ZLP in Test Mode. -#define USBFeatureRequest_TESTSENDZLP 6 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBFeatureRequest_GetFeatureSelector( - const USBGenericRequest *request); - - -extern unsigned char USBFeatureRequest_GetTestSelector( - const USBGenericRequest *request); - -#endif //#ifndef USBFEATUREREQUEST_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating CLEAR_FEATURE and SET_FEATURE + requests. + + !!!Usage + + - To get USB feature request information (field values) from the + USBGenericRequest instance, use + - USBFeatureRequest_GetFeatureSelector + - USBFeatureRequest_GetTestSelector +*/ + +#ifndef USBFEATUREREQUEST_H +#define USBFEATUREREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Feature Request definitions" +/// +/// This page lists codes of USB Feature Request +/// +/// - USB Feature selectors +/// - USBFeatureRequest_ENDPOINTHALT +/// - USBFeatureRequest_DEVICEREMOTEWAKEUP +/// - USBFeatureRequest_TESTMODE +/// +/// - USB Test mode selectors +/// - USBFeatureRequest_TESTJ +/// - USBFeatureRequest_TESTK +/// - USBFeatureRequest_TESTSE0NAK +/// - USBFeatureRequest_TESTPACKET +/// - USBFeatureRequest_TESTFORCEENABLE +/// - USBFeatureRequest_TESTSENDZLP +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Feature selectors" +/// +/// This page lists codes of USB feature selectors. +/// +/// !Selectors +/// - USBFeatureRequest_ENDPOINTHALT +/// - USBFeatureRequest_DEVICEREMOTEWAKEUP +/// - USBFeatureRequest_TESTMODE + +/// Halt feature of an endpoint. +#define USBFeatureRequest_ENDPOINTHALT 0 +/// Remote wake-up feature of the device. +#define USBFeatureRequest_DEVICEREMOTEWAKEUP 1 +/// Test mode of the device. +#define USBFeatureRequest_TESTMODE 2 +/// OTG set feature +#define USBFeatureRequest_OTG 0x0B +//------------------------------------------------------------------------------ + +/// On The Go Feature Selectors +/// b_hnp_enable 3 +/// a_hnp_support 4 +/// a_alt_hnp_support 5 +#define USBFeatureRequest_OTG_B_HNP_ENABLE 3 +#define USBFeatureRequest_OTG_A_HNP_SUPPORT 4 +#define USBFeatureRequest_OTG_A_ALT_HNP_SUPPORT 5 + +//------------------------------------------------------------------------------ +/// \page "USB Test mode selectors" +/// +/// This page lists codes of USB high speed test mode selectors. +/// +/// !Selectors +/// - USBFeatureRequest_TESTJ +/// - USBFeatureRequest_TESTK +/// - USBFeatureRequest_TESTSE0NAK +/// - USBFeatureRequest_TESTPACKET +/// - USBFeatureRequest_TESTFORCEENABLE +/// - USBFeatureRequest_TESTSENDZLP + +/// Tests the high-output drive level on the D+ line. +#define USBFeatureRequest_TESTJ 1 +/// Tests the high-output drive level on the D- line. +#define USBFeatureRequest_TESTK 2 +/// Tests the output impedance, low-level output voltage and loading +/// characteristics. +#define USBFeatureRequest_TESTSE0NAK 3 +/// Tests rise and fall times, eye patterns and jitter. +#define USBFeatureRequest_TESTPACKET 4 +/// Tests the hub disconnect detection. +#define USBFeatureRequest_TESTFORCEENABLE 5 +/// Send a ZLP in Test Mode. +#define USBFeatureRequest_TESTSENDZLP 6 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBFeatureRequest_GetFeatureSelector( + const USBGenericRequest *request); + + +extern unsigned char USBFeatureRequest_GetTestSelector( + const USBGenericRequest *request); + +#endif //#ifndef USBFEATUREREQUEST_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.c b/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.c index e22a1d4cc..acda2a413 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.c +++ b/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.c @@ -1,80 +1,80 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGenericDescriptor implementation - - About: Purpose - Implementation of the USBGenericDescriptor class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericDescriptor.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the length of a descriptor. -/// \param descriptor Pointer to a USBGenericDescriptor instance. -/// \return Length of descriptor in bytes. -//------------------------------------------------------------------------------ -unsigned int USBGenericDescriptor_GetLength( - const USBGenericDescriptor *descriptor) -{ - return descriptor->bLength; -} - -//------------------------------------------------------------------------------ -/// Returns the type of a descriptor. -/// \param descriptor Pointer to a USBGenericDescriptor instance. -/// \return Type of descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGenericDescriptor_GetType( - const USBGenericDescriptor *descriptor) -{ - return descriptor->bDescriptorType; -} - -//------------------------------------------------------------------------------ -/// Returns a pointer to the descriptor right after the given one, when -/// parsing a Configuration descriptor. -/// \param descriptor - Pointer to a USBGenericDescriptor instance. -/// \return Pointer to the next descriptor. -//------------------------------------------------------------------------------ -USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( - const USBGenericDescriptor *descriptor) -{ - return (USBGenericDescriptor *) - (((char *) descriptor) + USBGenericDescriptor_GetLength(descriptor)); -} +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBGenericDescriptor implementation + + About: Purpose + Implementation of the USBGenericDescriptor class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBGenericDescriptor.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the length of a descriptor. +/// \param descriptor Pointer to a USBGenericDescriptor instance. +/// \return Length of descriptor in bytes. +//------------------------------------------------------------------------------ +unsigned int USBGenericDescriptor_GetLength( + const USBGenericDescriptor *descriptor) +{ + return descriptor->bLength; +} + +//------------------------------------------------------------------------------ +/// Returns the type of a descriptor. +/// \param descriptor Pointer to a USBGenericDescriptor instance. +/// \return Type of descriptor. +//------------------------------------------------------------------------------ +unsigned char USBGenericDescriptor_GetType( + const USBGenericDescriptor *descriptor) +{ + return descriptor->bDescriptorType; +} + +//------------------------------------------------------------------------------ +/// Returns a pointer to the descriptor right after the given one, when +/// parsing a Configuration descriptor. +/// \param descriptor - Pointer to a USBGenericDescriptor instance. +/// \return Pointer to the next descriptor. +//------------------------------------------------------------------------------ +USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( + const USBGenericDescriptor *descriptor) +{ + return (USBGenericDescriptor *) + (((char *) descriptor) + USBGenericDescriptor_GetLength(descriptor)); +} diff --git a/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.h index b1237ae9d..01318f431 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.h +++ b/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.h @@ -1,133 +1,133 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Definition of a generic USB descriptor class. -/// -/// !!!Usage -/// -/// -# Declare or access USB descriptors by USBGenericDescriptor instance. -/// -# To get usful information (field values) from the USB descriptors, use -/// - USBGenericDescriptor_GetLength -/// - USBGenericDescriptor_GetType -/// -# To scan the descriptors, use -/// - USBGenericDescriptor_GetNextDescriptor -//------------------------------------------------------------------------------ - -#ifndef USBGENERICDESCRIPTOR_H -#define USBGENERICDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Descriptor types" -/// -/// This page lists the codes of the usb descriptor types -/// -/// !Types -/// - USBGenericDescriptor_DEVICE -/// - USBGenericDescriptor_CONFIGURATION -/// - USBGenericDescriptor_STRING -/// - USBGenericDescriptor_INTERFACE -/// - USBGenericDescriptor_ENDPOINT -/// - USBGenericDescriptor_DEVICEQUALIFIER -/// - USBGenericDescriptor_OTHERSPEEDCONFIGURATION -/// - USBGenericDescriptor_INTERFACEPOWER -/// - USBGenericDescriptor_OTG -/// - USBGenericDescriptor_DEBUG -/// - USBGenericDescriptor_INTERFACEASSOCIATION - -/// Device descriptor type. -#define USBGenericDescriptor_DEVICE 1 -/// Configuration descriptor type. -#define USBGenericDescriptor_CONFIGURATION 2 -/// String descriptor type. -#define USBGenericDescriptor_STRING 3 -/// Interface descriptor type. -#define USBGenericDescriptor_INTERFACE 4 -/// Endpoint descriptor type. -#define USBGenericDescriptor_ENDPOINT 5 -/// Device qualifier descriptor type. -#define USBGenericDescriptor_DEVICEQUALIFIER 6 -/// Other speed configuration descriptor type. -#define USBGenericDescriptor_OTHERSPEEDCONFIGURATION 7 -/// Interface power descriptor type. -#define USBGenericDescriptor_INTERFACEPOWER 8 -/// On-The-Go descriptor type. -#define USBGenericDescriptor_OTG 9 -/// Debug descriptor type. -#define USBGenericDescriptor_DEBUG 10 -/// Interface association descriptor type. -#define USBGenericDescriptor_INTERFACEASSOCIATION 11 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -/// Holds the few fields shared by all USB descriptors. -typedef struct { - - /// Length of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type. - unsigned char bDescriptorType; - -} __attribute__ ((packed)) USBGenericDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned int USBGenericDescriptor_GetLength( - const USBGenericDescriptor *descriptor); - -extern unsigned char USBGenericDescriptor_GetType( - const USBGenericDescriptor *descriptor); - -extern USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( - const USBGenericDescriptor *descriptor); - -#endif //#ifndef USBGENERICDESCRIPTOR_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !!!Purpose +/// +/// Definition of a generic USB descriptor class. +/// +/// !!!Usage +/// +/// -# Declare or access USB descriptors by USBGenericDescriptor instance. +/// -# To get usful information (field values) from the USB descriptors, use +/// - USBGenericDescriptor_GetLength +/// - USBGenericDescriptor_GetType +/// -# To scan the descriptors, use +/// - USBGenericDescriptor_GetNextDescriptor +//------------------------------------------------------------------------------ + +#ifndef USBGENERICDESCRIPTOR_H +#define USBGENERICDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Descriptor types" +/// +/// This page lists the codes of the usb descriptor types +/// +/// !Types +/// - USBGenericDescriptor_DEVICE +/// - USBGenericDescriptor_CONFIGURATION +/// - USBGenericDescriptor_STRING +/// - USBGenericDescriptor_INTERFACE +/// - USBGenericDescriptor_ENDPOINT +/// - USBGenericDescriptor_DEVICEQUALIFIER +/// - USBGenericDescriptor_OTHERSPEEDCONFIGURATION +/// - USBGenericDescriptor_INTERFACEPOWER +/// - USBGenericDescriptor_OTG +/// - USBGenericDescriptor_DEBUG +/// - USBGenericDescriptor_INTERFACEASSOCIATION + +/// Device descriptor type. +#define USBGenericDescriptor_DEVICE 1 +/// Configuration descriptor type. +#define USBGenericDescriptor_CONFIGURATION 2 +/// String descriptor type. +#define USBGenericDescriptor_STRING 3 +/// Interface descriptor type. +#define USBGenericDescriptor_INTERFACE 4 +/// Endpoint descriptor type. +#define USBGenericDescriptor_ENDPOINT 5 +/// Device qualifier descriptor type. +#define USBGenericDescriptor_DEVICEQUALIFIER 6 +/// Other speed configuration descriptor type. +#define USBGenericDescriptor_OTHERSPEEDCONFIGURATION 7 +/// Interface power descriptor type. +#define USBGenericDescriptor_INTERFACEPOWER 8 +/// On-The-Go descriptor type. +#define USBGenericDescriptor_OTG 9 +/// Debug descriptor type. +#define USBGenericDescriptor_DEBUG 10 +/// Interface association descriptor type. +#define USBGenericDescriptor_INTERFACEASSOCIATION 11 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +/// Holds the few fields shared by all USB descriptors. +typedef struct { + + /// Length of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type. + unsigned char bDescriptorType; + +} __attribute__ ((packed)) USBGenericDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned int USBGenericDescriptor_GetLength( + const USBGenericDescriptor *descriptor); + +extern unsigned char USBGenericDescriptor_GetType( + const USBGenericDescriptor *descriptor); + +extern USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( + const USBGenericDescriptor *descriptor); + +#endif //#ifndef USBGENERICDESCRIPTOR_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.c b/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.c index dfc47227a..9017a8ac3 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.c +++ b/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.c @@ -1,138 +1,138 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGenericRequest implementation - - About: Purpose - Implementation of the USBGenericRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Returns the type of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return "USB Request Types" -//------------------------------------------------------------------------------ -extern unsigned char USBGenericRequest_GetType(const USBGenericRequest *request) -{ - return ((request->bmRequestType >> 5) & 0x3); -} - -//------------------------------------------------------------------------------ -/// Returns the request code of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request code. -/// \sa "USB Request Codes" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetRequest(const USBGenericRequest *request) -{ - return request->bRequest; -} - -//------------------------------------------------------------------------------ -/// Returns the wValue field of the given request. -/// \param request - Pointer to a USBGenericRequest instance. -/// \return Request value. -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetValue(const USBGenericRequest *request) -{ - return request->wValue; -} - -//------------------------------------------------------------------------------ -/// Returns the wIndex field of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request index; -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetIndex(const USBGenericRequest *request) -{ - return request->wIndex; -} - -//------------------------------------------------------------------------------ -/// Returns the expected length of the data phase following a request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Length of data phase. -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetLength(const USBGenericRequest *request) -{ - return request->wLength; -} - -//------------------------------------------------------------------------------ -/// Returns the endpoint number targetted by a given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Endpoint number. -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetEndpointNumber( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetIndex(request) & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the intended recipient of a given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request recipient. -/// \sa "USB Request Recipients" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetRecipient(const USBGenericRequest *request) -{ - // Recipient is in bits [0..4] of the bmRequestType field - return request->bmRequestType & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the direction of the data transfer following the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Transfer direction. -/// \sa "USB Request Directions" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetDirection(const USBGenericRequest *request) -{ - // Transfer direction is located in bit D7 of the bmRequestType field - if ((request->bmRequestType & 0x80) != 0) { - - return USBGenericRequest_IN; - } - else { - - return USBGenericRequest_OUT; - } -} - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBGenericRequest implementation + + About: Purpose + Implementation of the USBGenericRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Returns the type of the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return "USB Request Types" +//------------------------------------------------------------------------------ +extern unsigned char USBGenericRequest_GetType(const USBGenericRequest *request) +{ + return ((request->bmRequestType >> 5) & 0x3); +} + +//------------------------------------------------------------------------------ +/// Returns the request code of the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Request code. +/// \sa "USB Request Codes" +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetRequest(const USBGenericRequest *request) +{ + return request->bRequest; +} + +//------------------------------------------------------------------------------ +/// Returns the wValue field of the given request. +/// \param request - Pointer to a USBGenericRequest instance. +/// \return Request value. +//------------------------------------------------------------------------------ +unsigned short USBGenericRequest_GetValue(const USBGenericRequest *request) +{ + return request->wValue; +} + +//------------------------------------------------------------------------------ +/// Returns the wIndex field of the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Request index; +//------------------------------------------------------------------------------ +unsigned short USBGenericRequest_GetIndex(const USBGenericRequest *request) +{ + return request->wIndex; +} + +//------------------------------------------------------------------------------ +/// Returns the expected length of the data phase following a request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Length of data phase. +//------------------------------------------------------------------------------ +unsigned short USBGenericRequest_GetLength(const USBGenericRequest *request) +{ + return request->wLength; +} + +//------------------------------------------------------------------------------ +/// Returns the endpoint number targetted by a given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Endpoint number. +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetEndpointNumber( + const USBGenericRequest *request) +{ + return USBGenericRequest_GetIndex(request) & 0xF; +} + +//------------------------------------------------------------------------------ +/// Returns the intended recipient of a given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Request recipient. +/// \sa "USB Request Recipients" +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetRecipient(const USBGenericRequest *request) +{ + // Recipient is in bits [0..4] of the bmRequestType field + return request->bmRequestType & 0xF; +} + +//------------------------------------------------------------------------------ +/// Returns the direction of the data transfer following the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Transfer direction. +/// \sa "USB Request Directions" +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetDirection(const USBGenericRequest *request) +{ + // Transfer direction is located in bit D7 of the bmRequestType field + if ((request->bmRequestType & 0x80) != 0) { + + return USBGenericRequest_IN; + } + else { + + return USBGenericRequest_OUT; + } +} + diff --git a/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.h b/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.h index 77f8ca506..0e7895436 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.h +++ b/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.h @@ -1,244 +1,244 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of the USBGenericRequest class and its methods. - - !!!Usage - - -# Declare or access USB requests by USBGenericRequest instance. - -# To get usful information (field values) from the USB requests, use - - USBGenericRequest_GetType - - USBGenericRequest_GetRequest - - USBGenericRequest_GetValue - - USBGenericRequest_GetIndex - - USBGenericRequest_GetLength - - USBGenericRequest_GetEndpointNumber - - USBGenericRequest_GetRecipient - - USBGenericRequest_GetDirection -*/ - -#ifndef USBGENERICREQUEST_H -#define USBGENERICREQUEST_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Generic Request definitions" -/// -/// This page lists the codes of USB generic request. -/// -/// - USB Request codes -/// - USBGenericRequest_GETSTATUS -/// - USBGenericRequest_CLEARFEATURE -/// - USBGenericRequest_SETFEATURE -/// - USBGenericRequest_SETADDRESS -/// - USBGenericRequest_GETDESCRIPTOR -/// - USBGenericRequest_SETDESCRIPTOR -/// - USBGenericRequest_GETCONFIGURATION -/// - USBGenericRequest_SETCONFIGURATION -/// - USBGenericRequest_GETINTERFACE -/// - USBGenericRequest_SETINTERFACE -/// - USBGenericRequest_SYNCHFRAME -/// -/// - USB Request Recipients -/// - USBGenericRequest_DEVICE -/// - USBGenericRequest_INTERFACE -/// - USBGenericRequest_ENDPOINT -/// - USBGenericRequest_OTHER -/// -/// - USB Request Types -/// - USBGenericRequest_STANDARD -/// - USBGenericRequest_CLASS -/// - USBGenericRequest_VENDOR -/// -/// - USB Request Directions -/// - USBGenericRequest_IN -/// - USBGenericRequest_OUT -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request codes" -/// -/// This page lists the USB generic request codes. -/// -/// !Codes -/// - USBGenericRequest_GETSTATUS -/// - USBGenericRequest_CLEARFEATURE -/// - USBGenericRequest_SETFEATURE -/// - USBGenericRequest_SETADDRESS -/// - USBGenericRequest_GETDESCRIPTOR -/// - USBGenericRequest_SETDESCRIPTOR -/// - USBGenericRequest_GETCONFIGURATION -/// - USBGenericRequest_SETCONFIGURATION -/// - USBGenericRequest_GETINTERFACE -/// - USBGenericRequest_SETINTERFACE -/// - USBGenericRequest_SYNCHFRAME - -/// GET_STATUS request code. -#define USBGenericRequest_GETSTATUS 0 -/// CLEAR_FEATURE request code. -#define USBGenericRequest_CLEARFEATURE 1 -/// SET_FEATURE request code. -#define USBGenericRequest_SETFEATURE 3 -/// SET_ADDRESS request code. -#define USBGenericRequest_SETADDRESS 5 -/// GET_DESCRIPTOR request code. -#define USBGenericRequest_GETDESCRIPTOR 6 -/// SET_DESCRIPTOR request code. -#define USBGenericRequest_SETDESCRIPTOR 7 -/// GET_CONFIGURATION request code. -#define USBGenericRequest_GETCONFIGURATION 8 -/// SET_CONFIGURATION request code. -#define USBGenericRequest_SETCONFIGURATION 9 -/// GET_INTERFACE request code. -#define USBGenericRequest_GETINTERFACE 10 -/// SET_INTERFACE request code. -#define USBGenericRequest_SETINTERFACE 11 -/// SYNCH_FRAME request code. -#define USBGenericRequest_SYNCHFRAME 12 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Recipients" -/// -/// This page lists codes of USB request recipients. -/// -/// !Recipients -/// - USBGenericRequest_DEVICE -/// - USBGenericRequest_INTERFACE -/// - USBGenericRequest_ENDPOINT -/// - USBGenericRequest_OTHER - -/// Recipient is the whole device. -#define USBGenericRequest_DEVICE 0 -/// Recipient is an interface. -#define USBGenericRequest_INTERFACE 1 -/// Recipient is an endpoint. -#define USBGenericRequest_ENDPOINT 2 -/// Recipient is another entity. -#define USBGenericRequest_OTHER 3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Types" -/// -/// This page lists codes of USB request types. -/// -/// !Types -/// - USBGenericRequest_STANDARD -/// - USBGenericRequest_CLASS -/// - USBGenericRequest_VENDOR - -/// Request is standard. -#define USBGenericRequest_STANDARD 0 -/// Request is class-specific. -#define USBGenericRequest_CLASS 1 -/// Request is vendor-specific. -#define USBGenericRequest_VENDOR 2 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Directions" -/// -/// This page lists codes of USB request directions. -/// -/// !Directions -/// - USBGenericRequest_IN -/// - USBGenericRequest_OUT - -/// Transfer occurs from device to the host. -#define USBGenericRequest_OUT 0 -/// Transfer occurs from the host to the device. -#define USBGenericRequest_IN 1 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Generic USB SETUP request sent over Control endpoints. -//------------------------------------------------------------------------------ -typedef struct { - - /// Type of request - /// \sa "USB Request Recipients" - /// \sa "USB Request Types" - /// \sa "USB Request Directions" - unsigned char bmRequestType:8; - /// Request code - /// \sa "USB Request Codes" - unsigned char bRequest:8; - /// Request-specific value parameter. - unsigned short wValue:16; - /// Request-specific index parameter. - unsigned short wIndex:16; - /// Expected length (in bytes) of the data phase. - unsigned short wLength:16; - -} USBGenericRequest; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBGenericRequest_GetType( - const USBGenericRequest *request); - - -extern unsigned char USBGenericRequest_GetRequest( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetValue( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetIndex( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetLength( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetEndpointNumber( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetRecipient( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetDirection( - const USBGenericRequest *request); - -#endif //#ifndef USBGENERICREQUEST_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of the USBGenericRequest class and its methods. + + !!!Usage + + -# Declare or access USB requests by USBGenericRequest instance. + -# To get usful information (field values) from the USB requests, use + - USBGenericRequest_GetType + - USBGenericRequest_GetRequest + - USBGenericRequest_GetValue + - USBGenericRequest_GetIndex + - USBGenericRequest_GetLength + - USBGenericRequest_GetEndpointNumber + - USBGenericRequest_GetRecipient + - USBGenericRequest_GetDirection +*/ + +#ifndef USBGENERICREQUEST_H +#define USBGENERICREQUEST_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Generic Request definitions" +/// +/// This page lists the codes of USB generic request. +/// +/// - USB Request codes +/// - USBGenericRequest_GETSTATUS +/// - USBGenericRequest_CLEARFEATURE +/// - USBGenericRequest_SETFEATURE +/// - USBGenericRequest_SETADDRESS +/// - USBGenericRequest_GETDESCRIPTOR +/// - USBGenericRequest_SETDESCRIPTOR +/// - USBGenericRequest_GETCONFIGURATION +/// - USBGenericRequest_SETCONFIGURATION +/// - USBGenericRequest_GETINTERFACE +/// - USBGenericRequest_SETINTERFACE +/// - USBGenericRequest_SYNCHFRAME +/// +/// - USB Request Recipients +/// - USBGenericRequest_DEVICE +/// - USBGenericRequest_INTERFACE +/// - USBGenericRequest_ENDPOINT +/// - USBGenericRequest_OTHER +/// +/// - USB Request Types +/// - USBGenericRequest_STANDARD +/// - USBGenericRequest_CLASS +/// - USBGenericRequest_VENDOR +/// +/// - USB Request Directions +/// - USBGenericRequest_IN +/// - USBGenericRequest_OUT +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request codes" +/// +/// This page lists the USB generic request codes. +/// +/// !Codes +/// - USBGenericRequest_GETSTATUS +/// - USBGenericRequest_CLEARFEATURE +/// - USBGenericRequest_SETFEATURE +/// - USBGenericRequest_SETADDRESS +/// - USBGenericRequest_GETDESCRIPTOR +/// - USBGenericRequest_SETDESCRIPTOR +/// - USBGenericRequest_GETCONFIGURATION +/// - USBGenericRequest_SETCONFIGURATION +/// - USBGenericRequest_GETINTERFACE +/// - USBGenericRequest_SETINTERFACE +/// - USBGenericRequest_SYNCHFRAME + +/// GET_STATUS request code. +#define USBGenericRequest_GETSTATUS 0 +/// CLEAR_FEATURE request code. +#define USBGenericRequest_CLEARFEATURE 1 +/// SET_FEATURE request code. +#define USBGenericRequest_SETFEATURE 3 +/// SET_ADDRESS request code. +#define USBGenericRequest_SETADDRESS 5 +/// GET_DESCRIPTOR request code. +#define USBGenericRequest_GETDESCRIPTOR 6 +/// SET_DESCRIPTOR request code. +#define USBGenericRequest_SETDESCRIPTOR 7 +/// GET_CONFIGURATION request code. +#define USBGenericRequest_GETCONFIGURATION 8 +/// SET_CONFIGURATION request code. +#define USBGenericRequest_SETCONFIGURATION 9 +/// GET_INTERFACE request code. +#define USBGenericRequest_GETINTERFACE 10 +/// SET_INTERFACE request code. +#define USBGenericRequest_SETINTERFACE 11 +/// SYNCH_FRAME request code. +#define USBGenericRequest_SYNCHFRAME 12 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request Recipients" +/// +/// This page lists codes of USB request recipients. +/// +/// !Recipients +/// - USBGenericRequest_DEVICE +/// - USBGenericRequest_INTERFACE +/// - USBGenericRequest_ENDPOINT +/// - USBGenericRequest_OTHER + +/// Recipient is the whole device. +#define USBGenericRequest_DEVICE 0 +/// Recipient is an interface. +#define USBGenericRequest_INTERFACE 1 +/// Recipient is an endpoint. +#define USBGenericRequest_ENDPOINT 2 +/// Recipient is another entity. +#define USBGenericRequest_OTHER 3 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request Types" +/// +/// This page lists codes of USB request types. +/// +/// !Types +/// - USBGenericRequest_STANDARD +/// - USBGenericRequest_CLASS +/// - USBGenericRequest_VENDOR + +/// Request is standard. +#define USBGenericRequest_STANDARD 0 +/// Request is class-specific. +#define USBGenericRequest_CLASS 1 +/// Request is vendor-specific. +#define USBGenericRequest_VENDOR 2 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request Directions" +/// +/// This page lists codes of USB request directions. +/// +/// !Directions +/// - USBGenericRequest_IN +/// - USBGenericRequest_OUT + +/// Transfer occurs from device to the host. +#define USBGenericRequest_OUT 0 +/// Transfer occurs from the host to the device. +#define USBGenericRequest_IN 1 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Generic USB SETUP request sent over Control endpoints. +//------------------------------------------------------------------------------ +typedef struct { + + /// Type of request + /// \sa "USB Request Recipients" + /// \sa "USB Request Types" + /// \sa "USB Request Directions" + unsigned char bmRequestType:8; + /// Request code + /// \sa "USB Request Codes" + unsigned char bRequest:8; + /// Request-specific value parameter. + unsigned short wValue:16; + /// Request-specific index parameter. + unsigned short wIndex:16; + /// Expected length (in bytes) of the data phase. + unsigned short wLength:16; + +} USBGenericRequest; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBGenericRequest_GetType( + const USBGenericRequest *request); + + +extern unsigned char USBGenericRequest_GetRequest( + const USBGenericRequest *request); + +extern unsigned short USBGenericRequest_GetValue( + const USBGenericRequest *request); + +extern unsigned short USBGenericRequest_GetIndex( + const USBGenericRequest *request); + +extern unsigned short USBGenericRequest_GetLength( + const USBGenericRequest *request); + +extern unsigned char USBGenericRequest_GetEndpointNumber( + const USBGenericRequest *request); + +extern unsigned char USBGenericRequest_GetRecipient( + const USBGenericRequest *request); + +extern unsigned char USBGenericRequest_GetDirection( + const USBGenericRequest *request); + +#endif //#ifndef USBGENERICREQUEST_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.c b/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.c index a4022f2b5..c5416dbee 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.c +++ b/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.c @@ -1,72 +1,72 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGetDescriptorRequest implementation - - About: Purpose - Implementation of the USBGetDescriptorRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGetDescriptorRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the type of the descriptor requested by the host given the -/// corresponding GET_DESCRIPTOR request. -/// \param request Pointer to a USBGenericDescriptor instance. -/// \return Type of the requested descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGetDescriptorRequest_GetDescriptorType( - const USBGenericRequest *request) -{ - // Requested descriptor type is in the high-byte of the wValue field - return (USBGenericRequest_GetValue(request) >> 8) & 0xFF; -} - -//------------------------------------------------------------------------------ -/// Returns the index of the requested descriptor, given the corresponding -/// GET_DESCRIPTOR request. -/// \param request Pointer to a USBGenericDescriptor instance. -/// \return Index of the requested descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGetDescriptorRequest_GetDescriptorIndex( - const USBGenericRequest *request) -{ - // Requested descriptor index if in the low byte of the wValue field - return USBGenericRequest_GetValue(request) & 0xFF; -} - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBGetDescriptorRequest implementation + + About: Purpose + Implementation of the USBGetDescriptorRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBGetDescriptorRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the type of the descriptor requested by the host given the +/// corresponding GET_DESCRIPTOR request. +/// \param request Pointer to a USBGenericDescriptor instance. +/// \return Type of the requested descriptor. +//------------------------------------------------------------------------------ +unsigned char USBGetDescriptorRequest_GetDescriptorType( + const USBGenericRequest *request) +{ + // Requested descriptor type is in the high-byte of the wValue field + return (USBGenericRequest_GetValue(request) >> 8) & 0xFF; +} + +//------------------------------------------------------------------------------ +/// Returns the index of the requested descriptor, given the corresponding +/// GET_DESCRIPTOR request. +/// \param request Pointer to a USBGenericDescriptor instance. +/// \return Index of the requested descriptor. +//------------------------------------------------------------------------------ +unsigned char USBGetDescriptorRequest_GetDescriptorIndex( + const USBGenericRequest *request) +{ + // Requested descriptor index if in the low byte of the wValue field + return USBGenericRequest_GetValue(request) & 0xFF; +} + diff --git a/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.h b/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.h index 1f56ceb71..af5c4edc8 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.h +++ b/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.h @@ -1,67 +1,67 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of the USBGetDescriptorRequest class. - - !!!Usage - - - After a GET_DESCRIPTOR request has been received, retrive the useful - values with following functions: - - USBGetDescriptorRequest_GetDescriptorType: the descriptor type - - USBGetDescriptorRequest_GetDescriptorIndex: the index of the requested - descriptor - -*/ - -#ifndef USBGETDESCRIPTORREQUEST_H -#define USBGETDESCRIPTORREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBGetDescriptorRequest_GetDescriptorType( - const USBGenericRequest *request); - -extern unsigned char USBGetDescriptorRequest_GetDescriptorIndex( - const USBGenericRequest *request); - -#endif //#ifndef USBGETDESCRIPTORREQUEST_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of the USBGetDescriptorRequest class. + + !!!Usage + + - After a GET_DESCRIPTOR request has been received, retrive the useful + values with following functions: + - USBGetDescriptorRequest_GetDescriptorType: the descriptor type + - USBGetDescriptorRequest_GetDescriptorIndex: the index of the requested + descriptor + +*/ + +#ifndef USBGETDESCRIPTORREQUEST_H +#define USBGETDESCRIPTORREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBGetDescriptorRequest_GetDescriptorType( + const USBGenericRequest *request); + +extern unsigned char USBGetDescriptorRequest_GetDescriptorIndex( + const USBGenericRequest *request); + +#endif //#ifndef USBGETDESCRIPTORREQUEST_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBInterfaceAssociationDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBInterfaceAssociationDescriptor.h index 5f3dd21d2..7f3376d01 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBInterfaceAssociationDescriptor.h +++ b/radio/src/targets/sky9x/usb/common/core/USBInterfaceAssociationDescriptor.h @@ -1,86 +1,86 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \page USBInterfaceAssociateDescriptor - * !!!Purpose - * - * Class for manipulating USB IAD descriptors. - * - * !!!Usage - * - * -# Test - */ - -#ifndef USBDIADDESCRIPTOR_H -#define USBDIADDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -/* - Type: USBDeviceDescriptor - USB standard device descriptor structure. - - Variables: - bLength - Size of this descriptor in bytes. - bDescriptorType - Descriptor type (). - bFirstInterface - Interface number of the first interface that is - associated with this function. - bInterfaceCount - Number of contiguous interfaces that are - associated with this function. - bFunctionClass - Class code (assigned by USB-IF). - bFunctionSubClass - Subclass code (assigned by USB-IF). - bFunctionProtocol - Protocol code (assigned by USB-IF) - iFunction - Index of string descriptor describing this function. -*/ -typedef struct { - - unsigned char bLength; - unsigned char bDescriptorType; - unsigned char bFirstInterface; - unsigned char bInterfaceCount; - unsigned char bFunctionClass; - unsigned char bFunctionSubClass; - unsigned char bFunctionProtocol; - unsigned char iFunction; -} __attribute__ ((packed)) USBInterfaceAssociationDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDIADDESCRIPTOR_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \page USBInterfaceAssociateDescriptor + * !!!Purpose + * + * Class for manipulating USB IAD descriptors. + * + * !!!Usage + * + * -# Test + */ + +#ifndef USBDIADDESCRIPTOR_H +#define USBDIADDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +/* + Type: USBDeviceDescriptor + USB standard device descriptor structure. + + Variables: + bLength - Size of this descriptor in bytes. + bDescriptorType - Descriptor type (). + bFirstInterface - Interface number of the first interface that is + associated with this function. + bInterfaceCount - Number of contiguous interfaces that are + associated with this function. + bFunctionClass - Class code (assigned by USB-IF). + bFunctionSubClass - Subclass code (assigned by USB-IF). + bFunctionProtocol - Protocol code (assigned by USB-IF) + iFunction - Index of string descriptor describing this function. +*/ +typedef struct { + + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bFirstInterface; + unsigned char bInterfaceCount; + unsigned char bFunctionClass; + unsigned char bFunctionSubClass; + unsigned char bFunctionProtocol; + unsigned char iFunction; +} __attribute__ ((packed)) USBInterfaceAssociationDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef USBDIADDESCRIPTOR_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBInterfaceDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBInterfaceDescriptor.h index 63910bfb3..0d897a865 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBInterfaceDescriptor.h +++ b/radio/src/targets/sky9x/usb/common/core/USBInterfaceDescriptor.h @@ -1,87 +1,87 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating USB interface descriptors. - - !!!Usage - - - Declare USBInterfaceDescriptor instance as a part of the configuration - descriptors of a USB device. - -*/ - -#ifndef USBINTERFACEDESCRIPTOR_H -#define USBINTERFACEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard interface descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_INTERFACE). - unsigned char bDescriptorType; - /// Number of the interface in its configuration. - unsigned char bInterfaceNumber; - /// Value to select this alternate interface setting. - unsigned char bAlternateSetting; - /// Number of endpoints used by the inteface (excluding endpoint 0). - unsigned char bNumEndpoints; - /// Interface class code. - unsigned char bInterfaceClass; - /// Interface subclass code. - unsigned char bInterfaceSubClass; - /// Interface protocol code. - unsigned char bInterfaceProtocol; - /// Index of the interface string descriptor. - unsigned char iInterface; - -} __attribute__ ((packed)) USBInterfaceDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBINTERFACEDESCRIPTOR_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating USB interface descriptors. + + !!!Usage + + - Declare USBInterfaceDescriptor instance as a part of the configuration + descriptors of a USB device. + +*/ + +#ifndef USBINTERFACEDESCRIPTOR_H +#define USBINTERFACEDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// USB standard interface descriptor structure. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBGenericDescriptor_INTERFACE). + unsigned char bDescriptorType; + /// Number of the interface in its configuration. + unsigned char bInterfaceNumber; + /// Value to select this alternate interface setting. + unsigned char bAlternateSetting; + /// Number of endpoints used by the inteface (excluding endpoint 0). + unsigned char bNumEndpoints; + /// Interface class code. + unsigned char bInterfaceClass; + /// Interface subclass code. + unsigned char bInterfaceSubClass; + /// Interface protocol code. + unsigned char bInterfaceProtocol; + /// Index of the interface string descriptor. + unsigned char iInterface; + +} __attribute__ ((packed)) USBInterfaceDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef USBINTERFACEDESCRIPTOR_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.c b/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.c index 00a95f43e..280d8c54e 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.c +++ b/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.c @@ -1,69 +1,69 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBInterfaceRequest - - About: Purpose - Implementation of USBInterfaceRequest class methods. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBInterfaceRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Indicates which interface is targetted by a GET_INTERFACE or -/// SET_INTERFACE request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Interface number. -//------------------------------------------------------------------------------ -unsigned char USBInterfaceRequest_GetInterface(const USBGenericRequest *request) -{ - return (USBGenericRequest_GetIndex(request) & 0xFF); -} - -//------------------------------------------------------------------------------ -/// Indicates the new alternate setting that the interface targetted by a -/// SET_INTERFACE request should use. -/// \param request Pointer to a USBGenericRequest instance. -/// \return New active setting for the interface. -//------------------------------------------------------------------------------ -unsigned char USBInterfaceRequest_GetAlternateSetting( - const USBGenericRequest *request) -{ - return (USBGenericRequest_GetValue(request) & 0xFF); -} - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBInterfaceRequest + + About: Purpose + Implementation of USBInterfaceRequest class methods. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBInterfaceRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Indicates which interface is targetted by a GET_INTERFACE or +/// SET_INTERFACE request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Interface number. +//------------------------------------------------------------------------------ +unsigned char USBInterfaceRequest_GetInterface(const USBGenericRequest *request) +{ + return (USBGenericRequest_GetIndex(request) & 0xFF); +} + +//------------------------------------------------------------------------------ +/// Indicates the new alternate setting that the interface targetted by a +/// SET_INTERFACE request should use. +/// \param request Pointer to a USBGenericRequest instance. +/// \return New active setting for the interface. +//------------------------------------------------------------------------------ +unsigned char USBInterfaceRequest_GetAlternateSetting( + const USBGenericRequest *request) +{ + return (USBGenericRequest_GetValue(request) & 0xFF); +} + diff --git a/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.h b/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.h index cfd97a683..8805a80ff 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.h +++ b/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.h @@ -1,68 +1,68 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definitions for manipulating SET_INTERFACE and GET_INTERFACE request. - - !!!Usage - - -# After a SET_INTERFACE request has been received, retrieve the - target interface using USBInterfaceRequest_GetInterface and its - new alternate setting with USBInterfaceRequest_GetAlternateSetting. - -# After a GET_INTERFACE request has been received, retrieve the target - interface using USBInterfaceRequest_GetInterface. - -*/ - -#ifndef USBINTERFACEREQUEST_H -#define USBINTERFACEREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBInterfaceRequest_GetInterface( - const USBGenericRequest *request); - - -extern unsigned char USBInterfaceRequest_GetAlternateSetting( - const USBGenericRequest *request); - -#endif //#ifndef USBINTERFACEREQUEST_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definitions for manipulating SET_INTERFACE and GET_INTERFACE request. + + !!!Usage + + -# After a SET_INTERFACE request has been received, retrieve the + target interface using USBInterfaceRequest_GetInterface and its + new alternate setting with USBInterfaceRequest_GetAlternateSetting. + -# After a GET_INTERFACE request has been received, retrieve the target + interface using USBInterfaceRequest_GetInterface. + +*/ + +#ifndef USBINTERFACEREQUEST_H +#define USBINTERFACEREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBInterfaceRequest_GetInterface( + const USBGenericRequest *request); + + +extern unsigned char USBInterfaceRequest_GetAlternateSetting( + const USBGenericRequest *request); + +#endif //#ifndef USBINTERFACEREQUEST_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.c b/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.c index 09a2a4709..5a8a943ab 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.c +++ b/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.c @@ -1,62 +1,62 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBIrqHandler implementation - - About: Purpose - Implementation of the USB Interrupt Handler. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include - -#include "radio/src/targets/sky9x/board_lowlevel.h" -#include "../../../usb/device/core/USBD.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Call Arbitrer, device and host interrupt handler. -/// The IRQ functions are defined with weak and can be surcharged if needed. -//------------------------------------------------------------------------------ -void USB_IrqHandler( void ) -{ - // Most arbitrer interrupt - usb_general_interrupt(); - // Device interrupt - USBD_IrqHandler(); - // Host interrupt - usb_pipe_interrupt(); -} - - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBIrqHandler implementation + + About: Purpose + Implementation of the USB Interrupt Handler. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ +#include + +#include "radio/src/targets/sky9x/board_lowlevel.h" +#include "../../../usb/device/core/USBD.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Call Arbitrer, device and host interrupt handler. +/// The IRQ functions are defined with weak and can be surcharged if needed. +//------------------------------------------------------------------------------ +void USB_IrqHandler( void ) +{ + // Most arbitrer interrupt + usb_general_interrupt(); + // Device interrupt + USBD_IrqHandler(); + // Host interrupt + usb_pipe_interrupt(); +} + + diff --git a/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.h b/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.h index 77d26794d..3e6771ddc 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.h +++ b/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.h @@ -1,52 +1,52 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Implementation of the USB Interrupt Handler. - - !!!Usage - - -# The IRQ functions are defined with weak and can be surcharged if needed. - -*/ - -#ifndef USBIRQHANDLER_H -#define USBIRQHANDLER_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void USB_IrqHandler( void ); - -#endif //#ifndef USBIRQHANDLER_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Implementation of the USB Interrupt Handler. + + !!!Usage + + -# The IRQ functions are defined with weak and can be surcharged if needed. + +*/ + +#ifndef USBIRQHANDLER_H +#define USBIRQHANDLER_H + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern void USB_IrqHandler( void ); + +#endif //#ifndef USBIRQHANDLER_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.c b/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.c index 643560e00..2e548abe6 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.c +++ b/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.c @@ -1,56 +1,56 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBSetAddressRequest implementation - - About: Purpose - Implementation of the USBSetAddressRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBSetAddressRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Returns the address that the device must take in response to a -/// SET_ADDRESS request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return New device address. -//------------------------------------------------------------------------------ -unsigned char USBSetAddressRequest_GetAddress(const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request) & 0x7F; -} - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBSetAddressRequest implementation + + About: Purpose + Implementation of the USBSetAddressRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBSetAddressRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Returns the address that the device must take in response to a +/// SET_ADDRESS request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return New device address. +//------------------------------------------------------------------------------ +unsigned char USBSetAddressRequest_GetAddress(const USBGenericRequest *request) +{ + return USBGenericRequest_GetValue(request) & 0x7F; +} + diff --git a/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.h b/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.h index 2f8e2ed2b..e3dab7ee1 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.h +++ b/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.h @@ -1,60 +1,60 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating SET_ADDRESS USB requests. - - !!!Usage - - - After a SET_ADDRESS request has been received, retrive the new address - value with USBSetAddressRequest_GetAddress. -*/ - -#ifndef USBSETADDRESSREQUEST_H -#define USBSETADDRESSREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBSetAddressRequest_GetAddress( - const USBGenericRequest *request); - -#endif //#ifndef USBSETADDRESSREQUEST_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating SET_ADDRESS USB requests. + + !!!Usage + + - After a SET_ADDRESS request has been received, retrive the new address + value with USBSetAddressRequest_GetAddress. +*/ + +#ifndef USBSETADDRESSREQUEST_H +#define USBSETADDRESSREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBSetAddressRequest_GetAddress( + const USBGenericRequest *request); + +#endif //#ifndef USBSETADDRESSREQUEST_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.c b/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.c index be8756142..269d03cf1 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.c +++ b/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.c @@ -1,58 +1,58 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBSetConfigurationRequest implementation - - About: Purpose - Implementation of the USBSetConfigurationRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBSetConfigurationRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the number of the configuration that should be set in response -/// to the given SET_CONFIGURATION request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Number of the requested configuration. -//------------------------------------------------------------------------------ -unsigned char USBSetConfigurationRequest_GetConfiguration( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request); -} - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBSetConfigurationRequest implementation + + About: Purpose + Implementation of the USBSetConfigurationRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBSetConfigurationRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the number of the configuration that should be set in response +/// to the given SET_CONFIGURATION request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Number of the requested configuration. +//------------------------------------------------------------------------------ +unsigned char USBSetConfigurationRequest_GetConfiguration( + const USBGenericRequest *request) +{ + return USBGenericRequest_GetValue(request); +} + diff --git a/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.h b/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.h index 784d1cfb7..d69f3ae65 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.h +++ b/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.h @@ -1,61 +1,61 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for the Set Configuration request. - - !!!Usage - - - After a SET_CONFIGURATION request has been received, retrive the new - configuration value with USBSetConfigurationRequest_GetConfiguration. - -*/ - -#ifndef USBSETCONFIGURATIONREQUEST_H -#define USBSETCONFIGURATIONREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBSetConfigurationRequest_GetConfiguration( - const USBGenericRequest *request); - -#endif //#ifndef USBSETCONFIGURATIONREQUEST_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for the Set Configuration request. + + !!!Usage + + - After a SET_CONFIGURATION request has been received, retrive the new + configuration value with USBSetConfigurationRequest_GetConfiguration. + +*/ + +#ifndef USBSETCONFIGURATIONREQUEST_H +#define USBSETCONFIGURATIONREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/common/core/USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBSetConfigurationRequest_GetConfiguration( + const USBGenericRequest *request); + +#endif //#ifndef USBSETCONFIGURATIONREQUEST_H + diff --git a/radio/src/targets/sky9x/usb/common/core/USBStringDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBStringDescriptor.h index bcf4b8379..e3da4b405 100644 --- a/radio/src/targets/sky9x/usb/common/core/USBStringDescriptor.h +++ b/radio/src/targets/sky9x/usb/common/core/USBStringDescriptor.h @@ -1,74 +1,74 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Definition of a class for manipulating String descriptors. -//------------------------------------------------------------------------------ - -#ifndef USBSTRINGDESCRIPTOR_H -#define USBSTRINGDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB String Descriptor definitions" -/// -/// This page lists the codes and macros for USB string descriptor definition. -/// -/// !Language IDs -/// - USBStringDescriptor_ENGLISH_US -/// -/// !String Descriptor Length -/// - USBStringDescriptor_LENGTH -/// -/// !ASCII to UNICODE convertion -/// - USBStringDescriptor_UNICODE - -/// Language ID for US english. -#define USBStringDescriptor_ENGLISH_US 0x09, 0x04 - -/// Calculates the length of a string descriptor given the number of ascii -/// characters/language IDs in it. -/// \param length The ascii format string length. -/// \return The actual data length in bytes. -#define USBStringDescriptor_LENGTH(length) ((length) * 2 + 2) -/// Converts an ascii character to its unicode representation. -/// \param ascii The ASCII character to convert -/// \return A 2-byte-array for the UNICODE based on given ASCII -#define USBStringDescriptor_UNICODE(ascii) (ascii), 0 -//------------------------------------------------------------------------------ - -#endif //#ifndef USBSTRINGDESCRIPTOR_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !!!Purpose +/// +/// Definition of a class for manipulating String descriptors. +//------------------------------------------------------------------------------ + +#ifndef USBSTRINGDESCRIPTOR_H +#define USBSTRINGDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB String Descriptor definitions" +/// +/// This page lists the codes and macros for USB string descriptor definition. +/// +/// !Language IDs +/// - USBStringDescriptor_ENGLISH_US +/// +/// !String Descriptor Length +/// - USBStringDescriptor_LENGTH +/// +/// !ASCII to UNICODE convertion +/// - USBStringDescriptor_UNICODE + +/// Language ID for US english. +#define USBStringDescriptor_ENGLISH_US 0x09, 0x04 + +/// Calculates the length of a string descriptor given the number of ascii +/// characters/language IDs in it. +/// \param length The ascii format string length. +/// \return The actual data length in bytes. +#define USBStringDescriptor_LENGTH(length) ((length) * 2 + 2) +/// Converts an ascii character to its unicode representation. +/// \param ascii The ASCII character to convert +/// \return A 2-byte-array for the UNICODE based on given ASCII +#define USBStringDescriptor_UNICODE(ascii) (ascii), 0 +//------------------------------------------------------------------------------ + +#endif //#ifndef USBSTRINGDESCRIPTOR_H + diff --git a/radio/src/targets/sky9x/usb/common/massstorage/MSDeviceDescriptor.h b/radio/src/targets/sky9x/usb/common/massstorage/MSDeviceDescriptor.h index 9f4f700c4..f85833ee0 100644 --- a/radio/src/targets/sky9x/usb/common/massstorage/MSDeviceDescriptor.h +++ b/radio/src/targets/sky9x/usb/common/massstorage/MSDeviceDescriptor.h @@ -1,73 +1,73 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Declaration of constants for using Device Descriptors with a Mass Storage -/// driver. -/// -/// !Usage -/// -/// - For a USB device: -/// -# When declaring a USBDeviceDescriptor instance, use the Mass Storage -/// codes defined in this file (see "MS device codes"). -//------------------------------------------------------------------------------ - -#ifndef MSDEVICEDESCRIPTOR_H -#define MSDEVICEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MS device codes" -/// This page lists the class, subclass & protocol codes used by a device with -/// a Mass Storage driver. -/// -/// !Codes -/// -/// - MSDeviceDescriptor_CLASS -/// - MSDeviceDescriptor_SUBCLASS -/// - MSDeviceDescriptor_PROTOCOL - -/// Class code for a Mass Storage device. -#define MSDeviceDescriptor_CLASS 0 - -/// Subclass code for a Mass Storage device. -#define MSDeviceDescriptor_SUBCLASS 0 - -/// Protocol code for a Mass Storage device. -#define MSDeviceDescriptor_PROTOCOL 0 -//------------------------------------------------------------------------------ - -#endif //#ifndef MSDEVICEDESCRIPTOR_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Declaration of constants for using Device Descriptors with a Mass Storage +/// driver. +/// +/// !Usage +/// +/// - For a USB device: +/// -# When declaring a USBDeviceDescriptor instance, use the Mass Storage +/// codes defined in this file (see "MS device codes"). +//------------------------------------------------------------------------------ + +#ifndef MSDEVICEDESCRIPTOR_H +#define MSDEVICEDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MS device codes" +/// This page lists the class, subclass & protocol codes used by a device with +/// a Mass Storage driver. +/// +/// !Codes +/// +/// - MSDeviceDescriptor_CLASS +/// - MSDeviceDescriptor_SUBCLASS +/// - MSDeviceDescriptor_PROTOCOL + +/// Class code for a Mass Storage device. +#define MSDeviceDescriptor_CLASS 0 + +/// Subclass code for a Mass Storage device. +#define MSDeviceDescriptor_SUBCLASS 0 + +/// Protocol code for a Mass Storage device. +#define MSDeviceDescriptor_PROTOCOL 0 +//------------------------------------------------------------------------------ + +#endif //#ifndef MSDEVICEDESCRIPTOR_H + diff --git a/radio/src/targets/sky9x/usb/common/massstorage/MSInterfaceDescriptor.h b/radio/src/targets/sky9x/usb/common/massstorage/MSInterfaceDescriptor.h index e51dba6e4..b5033e24e 100644 --- a/radio/src/targets/sky9x/usb/common/massstorage/MSInterfaceDescriptor.h +++ b/radio/src/targets/sky9x/usb/common/massstorage/MSInterfaceDescriptor.h @@ -1,75 +1,75 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definition of several constants used when manipulating Mass Storage interface -/// descriptors. -/// -/// !Usage -/// -/// - For a USB device: -/// -# When declaring an interface descriptor for a Mass Storage device, use -/// the class, subclass and protocol codes defined here (see -/// "MS interface codes"). -//------------------------------------------------------------------------------ - -#ifndef MSINTERFACEDESCRIPTOR_H -#define MSINTERFACEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MS interface codes" -/// This page lists the available class, subclass & protocol codes for a Mass -/// Storage interface. -/// -/// !Codes -/// -/// - MSInterfaceDescriptor_CLASS -/// - MSInterfaceDescriptor_SCSI -/// - MSInterfaceDescriptor_BULKONLY - -/// Class code for a Mass Storage interface. -#define MSInterfaceDescriptor_CLASS 0x08 - -/// Subclass code for a Mass Storage interface using the SCSI protocol. -#define MSInterfaceDescriptor_SCSI 0x06 - -/// Protocol code for a Mass Storage interface using Bulk-Only Transport. -#define MSInterfaceDescriptor_BULKONLY 0x50 -//------------------------------------------------------------------------------ - - -#endif //#ifndef MSINTERFACEDESCRIPTOR_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Definition of several constants used when manipulating Mass Storage interface +/// descriptors. +/// +/// !Usage +/// +/// - For a USB device: +/// -# When declaring an interface descriptor for a Mass Storage device, use +/// the class, subclass and protocol codes defined here (see +/// "MS interface codes"). +//------------------------------------------------------------------------------ + +#ifndef MSINTERFACEDESCRIPTOR_H +#define MSINTERFACEDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MS interface codes" +/// This page lists the available class, subclass & protocol codes for a Mass +/// Storage interface. +/// +/// !Codes +/// +/// - MSInterfaceDescriptor_CLASS +/// - MSInterfaceDescriptor_SCSI +/// - MSInterfaceDescriptor_BULKONLY + +/// Class code for a Mass Storage interface. +#define MSInterfaceDescriptor_CLASS 0x08 + +/// Subclass code for a Mass Storage interface using the SCSI protocol. +#define MSInterfaceDescriptor_SCSI 0x06 + +/// Protocol code for a Mass Storage interface using Bulk-Only Transport. +#define MSInterfaceDescriptor_BULKONLY 0x50 +//------------------------------------------------------------------------------ + + +#endif //#ifndef MSINTERFACEDESCRIPTOR_H + diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSD.h b/radio/src/targets/sky9x/usb/device/massstorage/MSD.h index decab4afd..23a934d35 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSD.h +++ b/radio/src/targets/sky9x/usb/device/massstorage/MSD.h @@ -1,233 +1,233 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Mass Storage class definitions. -/// -/// See -/// - -/// USB Mass Storage Class Spec. Overview -/// - -/// USB Mass Storage Class Bulk-Only Transport -/// -/// !Usage -/// -/// -# Uses "MSD Requests" to check incoming requests from USB Host. -/// -# Uses "MSD Subclass Codes" and "MSD Protocol Codes" to fill %device -/// interface descriptors for a MSD %device. -/// -# Handle the incoming Bulk data with "MSD CBW Definitions" and MSCbw -/// structure. -/// -# Prepare the outgoing Bulk data with "MSD CSW Definitions" and MSCsw -/// structure. -//------------------------------------------------------------------------------ - -#ifndef MSD_H -#define MSD_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Requests" -/// This page lists MSD-specific requests ( Actually for Bulk-only protocol ). -/// -/// !Requests -/// - MSD_BULK_ONLY_RESET -/// - MSD_GET_MAX_LUN - -/// Reset the mass storage %device and its associated interface. -#define MSD_BULK_ONLY_RESET 0xFF -/// Return the maximum LUN number supported by the %device. -#define MSD_GET_MAX_LUN 0xFE -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Subclass Codes" -/// This page lists the Subclass Codes for bInterfaceSubClass field. -/// (Table 2.1, USB Mass Storage Class Spec. Overview) -/// -/// !SubClasses -/// - MSD_SUBCLASS_RBC -/// - MSD_SUBCLASS_SFF_MCC -/// - MSD_SUBCLASS_QIC -/// - MSD_SUBCLASS_UFI -/// - MSD_SUBCLASS_SFF -/// - MSD_SUBCLASS_SCSI - -/// Reduced Block Commands (RBC) T10 -#define MSD_SUBCLASS_RBC 0x01 -/// C/DVD devices -#define MSD_SUBCLASS_SFF_MCC 0x02 -/// Tape device -#define MSD_SUBCLASS_QIC 0x03 -/// Floppy disk drive (FDD) device -#define MSD_SUBCLASS_UFI 0x04 -/// Floppy disk drive (FDD) device -#define MSD_SUBCLASS_SFF 0x05 -/// SCSI transparent command set -#define MSD_SUBCLASS_SCSI 0x06 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \page "MSD Protocol Codes" -/// This page lists the Transport Protocol codes for MSD. -/// (Table 3.1, USB Mass Storage Class Spec. Overview) -/// -/// !Protocols -/// - MSD_PROTOCOL_CBI_COMPLETION -/// - MSD_PROTOCOL_CBI -/// - MSD_PROTOCOL_BULK_ONLY - -/// Control/Bulk/Interrupt (CBI) Transport (with command complete interrupt) -#define MSD_PROTOCOL_CBI_COMPLETION 0x00 -/// Control/Bulk/Interrupt (CBI) Transport (no command complete interrupt) -#define MSD_PROTOCOL_CBI 0x01 -/// Bulk-Only Transport -#define MSD_PROTOCOL_BULK_ONLY 0x50 -//------------------------------------------------------------------------------ - -/// Test unit control: -#define CTRL_NOT_READY 0x00 -#define CTRL_GOOD 0x01 -#define CTRL_BUSY 0x02 - -//------------------------------------------------------------------------------ -/// \page "MSD CBW Definitions" -/// This page lists the Command Block Wrapper (CBW) definitions. -/// -/// !Constants -/// - MSD_CBW_SIZE -/// - MSD_CBW_SIGNATURE -/// -/// !Fields -/// - MSD_CBW_DEVICE_TO_HOST - -/// Command Block Wrapper Size -#define MSD_CBW_SIZE 31 -/// 'USBC' 0x43425355 -#define MSD_CBW_SIGNATURE 0x43425355 - -/// CBW bmCBWFlags field -#define MSD_CBW_DEVICE_TO_HOST (1 << 7) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD CSW Definitions" -/// This page lists the Command Status Wrapper (CSW) definitions. -/// -/// !Constants -/// - MSD_CSW_SIZE -/// - MSD_CSW_SIGNATURE -/// -/// !Command Block Status Values -/// (Table 5.3 , USB Mass Storage Class Bulk-Only Transport) -/// - MSD_CSW_COMMAND_PASSED -/// - MSD_CSW_COMMAND_FAILED -/// - MSD_CSW_PHASE_ERROR - -/// Command Status Wrapper Size -#define MSD_CSW_SIZE 13 -/// 'USBS' 0x53425355 -#define MSD_CSW_SIGNATURE 0x53425355 - -/// Command Passed (good status) -#define MSD_CSW_COMMAND_PASSED 0 -/// Command Failed -#define MSD_CSW_COMMAND_FAILED 1 -/// Phase Error -#define MSD_CSW_PHASE_ERROR 2 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Command Block Wrapper (CBW), -/// See Table 5.1, USB Mass Storage Class Bulk-Only Transport. -/// -/// The CBW shall start on a packet boundary and shall end as a -/// short packet with exactly 31 (1Fh) bytes transferred. -//------------------------------------------------------------------------------ -typedef struct { - - /// 'USBC' 0x43425355 (little endian) - unsigned int dCBWSignature; - /// Must be the same as dCSWTag - unsigned int dCBWTag; - /// Number of bytes transfer - unsigned int dCBWDataTransferLength; - /// Indicates the directin of the transfer: - /// 0x80=IN=device-to-host, - /// 0x00=OUT=host-to-device - unsigned char bmCBWFlags; - /// bits 0->3: bCBWLUN - unsigned char bCBWLUN :4, - bReserved1:4; /// reserved - /// bits 0->4: bCBWCBLength - unsigned char bCBWCBLength:5, - bReserved2 :3; /// reserved - /// Command block - unsigned char pCommand[16]; - -} MSCbw; - -//------------------------------------------------------------------------------ -/// Command Status Wrapper (CSW), -/// See Table 5.2, USB Mass Storage Class Bulk-Only Transport. -//------------------------------------------------------------------------------ -typedef struct -{ - /// 'USBS' 0x53425355 (little endian) - unsigned int dCSWSignature; - /// Must be the same as dCBWTag - unsigned int dCSWTag; - /// For Data-Out the device shall report in the dCSWDataResidue the - /// difference between the amount of data expected as stated in the - /// dCBWDataTransferLength, and the actual amount of data processed by - /// the device. For Data-In the device shall report in the dCSWDataResidue - /// the difference between the amount of data expected as stated in the - /// dCBWDataTransferLength and the actual amount of relevant data sent by - /// the device. The dCSWDataResidue shall not exceed the value sent in the - /// dCBWDataTransferLength. - unsigned int dCSWDataResidue; - /// Indicates the success or failure of the command. - unsigned char bCSWStatus; - -} MSCsw; - -#endif //#ifndef MSD_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Mass Storage class definitions. +/// +/// See +/// - +/// USB Mass Storage Class Spec. Overview +/// - +/// USB Mass Storage Class Bulk-Only Transport +/// +/// !Usage +/// +/// -# Uses "MSD Requests" to check incoming requests from USB Host. +/// -# Uses "MSD Subclass Codes" and "MSD Protocol Codes" to fill %device +/// interface descriptors for a MSD %device. +/// -# Handle the incoming Bulk data with "MSD CBW Definitions" and MSCbw +/// structure. +/// -# Prepare the outgoing Bulk data with "MSD CSW Definitions" and MSCsw +/// structure. +//------------------------------------------------------------------------------ + +#ifndef MSD_H +#define MSD_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Requests" +/// This page lists MSD-specific requests ( Actually for Bulk-only protocol ). +/// +/// !Requests +/// - MSD_BULK_ONLY_RESET +/// - MSD_GET_MAX_LUN + +/// Reset the mass storage %device and its associated interface. +#define MSD_BULK_ONLY_RESET 0xFF +/// Return the maximum LUN number supported by the %device. +#define MSD_GET_MAX_LUN 0xFE +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Subclass Codes" +/// This page lists the Subclass Codes for bInterfaceSubClass field. +/// (Table 2.1, USB Mass Storage Class Spec. Overview) +/// +/// !SubClasses +/// - MSD_SUBCLASS_RBC +/// - MSD_SUBCLASS_SFF_MCC +/// - MSD_SUBCLASS_QIC +/// - MSD_SUBCLASS_UFI +/// - MSD_SUBCLASS_SFF +/// - MSD_SUBCLASS_SCSI + +/// Reduced Block Commands (RBC) T10 +#define MSD_SUBCLASS_RBC 0x01 +/// C/DVD devices +#define MSD_SUBCLASS_SFF_MCC 0x02 +/// Tape device +#define MSD_SUBCLASS_QIC 0x03 +/// Floppy disk drive (FDD) device +#define MSD_SUBCLASS_UFI 0x04 +/// Floppy disk drive (FDD) device +#define MSD_SUBCLASS_SFF 0x05 +/// SCSI transparent command set +#define MSD_SUBCLASS_SCSI 0x06 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +/// \page "MSD Protocol Codes" +/// This page lists the Transport Protocol codes for MSD. +/// (Table 3.1, USB Mass Storage Class Spec. Overview) +/// +/// !Protocols +/// - MSD_PROTOCOL_CBI_COMPLETION +/// - MSD_PROTOCOL_CBI +/// - MSD_PROTOCOL_BULK_ONLY + +/// Control/Bulk/Interrupt (CBI) Transport (with command complete interrupt) +#define MSD_PROTOCOL_CBI_COMPLETION 0x00 +/// Control/Bulk/Interrupt (CBI) Transport (no command complete interrupt) +#define MSD_PROTOCOL_CBI 0x01 +/// Bulk-Only Transport +#define MSD_PROTOCOL_BULK_ONLY 0x50 +//------------------------------------------------------------------------------ + +/// Test unit control: +#define CTRL_NOT_READY 0x00 +#define CTRL_GOOD 0x01 +#define CTRL_BUSY 0x02 + +//------------------------------------------------------------------------------ +/// \page "MSD CBW Definitions" +/// This page lists the Command Block Wrapper (CBW) definitions. +/// +/// !Constants +/// - MSD_CBW_SIZE +/// - MSD_CBW_SIGNATURE +/// +/// !Fields +/// - MSD_CBW_DEVICE_TO_HOST + +/// Command Block Wrapper Size +#define MSD_CBW_SIZE 31 +/// 'USBC' 0x43425355 +#define MSD_CBW_SIGNATURE 0x43425355 + +/// CBW bmCBWFlags field +#define MSD_CBW_DEVICE_TO_HOST (1 << 7) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD CSW Definitions" +/// This page lists the Command Status Wrapper (CSW) definitions. +/// +/// !Constants +/// - MSD_CSW_SIZE +/// - MSD_CSW_SIGNATURE +/// +/// !Command Block Status Values +/// (Table 5.3 , USB Mass Storage Class Bulk-Only Transport) +/// - MSD_CSW_COMMAND_PASSED +/// - MSD_CSW_COMMAND_FAILED +/// - MSD_CSW_PHASE_ERROR + +/// Command Status Wrapper Size +#define MSD_CSW_SIZE 13 +/// 'USBS' 0x53425355 +#define MSD_CSW_SIGNATURE 0x53425355 + +/// Command Passed (good status) +#define MSD_CSW_COMMAND_PASSED 0 +/// Command Failed +#define MSD_CSW_COMMAND_FAILED 1 +/// Phase Error +#define MSD_CSW_PHASE_ERROR 2 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Command Block Wrapper (CBW), +/// See Table 5.1, USB Mass Storage Class Bulk-Only Transport. +/// +/// The CBW shall start on a packet boundary and shall end as a +/// short packet with exactly 31 (1Fh) bytes transferred. +//------------------------------------------------------------------------------ +typedef struct { + + /// 'USBC' 0x43425355 (little endian) + unsigned int dCBWSignature; + /// Must be the same as dCSWTag + unsigned int dCBWTag; + /// Number of bytes transfer + unsigned int dCBWDataTransferLength; + /// Indicates the directin of the transfer: + /// 0x80=IN=device-to-host, + /// 0x00=OUT=host-to-device + unsigned char bmCBWFlags; + /// bits 0->3: bCBWLUN + unsigned char bCBWLUN :4, + bReserved1:4; /// reserved + /// bits 0->4: bCBWCBLength + unsigned char bCBWCBLength:5, + bReserved2 :3; /// reserved + /// Command block + unsigned char pCommand[16]; + +} MSCbw; + +//------------------------------------------------------------------------------ +/// Command Status Wrapper (CSW), +/// See Table 5.2, USB Mass Storage Class Bulk-Only Transport. +//------------------------------------------------------------------------------ +typedef struct +{ + /// 'USBS' 0x53425355 (little endian) + unsigned int dCSWSignature; + /// Must be the same as dCBWTag + unsigned int dCSWTag; + /// For Data-Out the device shall report in the dCSWDataResidue the + /// difference between the amount of data expected as stated in the + /// dCBWDataTransferLength, and the actual amount of data processed by + /// the device. For Data-In the device shall report in the dCSWDataResidue + /// the difference between the amount of data expected as stated in the + /// dCBWDataTransferLength and the actual amount of relevant data sent by + /// the device. The dCSWDataResidue shall not exceed the value sent in the + /// dCBWDataTransferLength. + unsigned int dCSWDataResidue; + /// Indicates the success or failure of the command. + unsigned char bCSWStatus; + +} MSCsw; + +#endif //#ifndef MSD_H + diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.c b/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.c index 3bc094d59..ff385949e 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.c +++ b/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.c @@ -1,610 +1,610 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//----------------------------------------------------------------------------- -// Includes -//----------------------------------------------------------------------------- - -#include "../../../usb/device/massstorage/MSDDStateMachine.h" - -#include "../../../usb/device/massstorage/SBCMethods.h" - -//----------------------------------------------------------------------------- -// Internal functions -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// Returns the expected transfer length and direction (IN, OUT or don't care) -/// from the host point-of-view. -/// \param cbw Pointer to the CBW to examinate -/// \param pLength Expected length of command -/// \param pType Expected direction of command -//----------------------------------------------------------------------------- -static void MSDD_GetCommandInformation(MSCbw *cbw, - unsigned int *length, - unsigned char *type) -{ - // Expected host transfer direction and length - (*length) = cbw->dCBWDataTransferLength; - - if (*length == 0) { - - (*type) = MSDD_NO_TRANSFER; - } - else if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) != 0) { - - (*type) = MSDD_DEVICE_TO_HOST; - } - else { - - (*type) = MSDD_HOST_TO_DEVICE; - } -} - -//----------------------------------------------------------------------------- -/// Pre-processes a command by checking the differences between the host and -/// device expectations in term of transfer type and length. -/// Once one of the thirteen cases is identified, the actions to do during the -/// post-processing phase are stored in the dCase variable of the command -/// state. -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return 1 if the command is supported, false otherwise -//----------------------------------------------------------------------------- -static unsigned char MSDD_PreProcessCommand(MSDDriver *pMsdDriver) -{ - unsigned int hostLength = 0; - unsigned int deviceLength = 0; - unsigned char hostType; - unsigned char deviceType; - unsigned char isCommandSupported; - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCsw *csw = &(commandState->csw); - MSCbw *cbw = &(commandState->cbw); - MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); - - // Get information about the command - // Host-side - MSDD_GetCommandInformation(cbw, &hostLength, &hostType); - - // Device-side - isCommandSupported = SBC_GetCommandInformation(cbw->pCommand, - &deviceLength, - &deviceType, - lun); - - // Initialize data residue and result status - csw->dCSWDataResidue = 0; - csw->bCSWStatus = MSD_CSW_COMMAND_PASSED; - - // Check if the command is supported - if (isCommandSupported) { - - // Identify the command case - if(hostType == MSDD_NO_TRANSFER) { - - // Case 1 (Hn = Dn) - if(deviceType == MSDD_NO_TRANSFER) { - - //TRACE_WARNING("Case 1\n\r"); - commandState->postprocess = 0; - commandState->length = 0; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - // Case 2 (Hn < Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 2\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - // Case 3 (Hn < Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 3\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - } - - // Case 4 (Hi > Dn) - else if(hostType == MSDD_DEVICE_TO_HOST) { - - if(deviceType == MSDD_NO_TRANSFER) { - - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 4\n\r"); - commandState->postprocess = MSDD_CASE_STALL_IN; - commandState->length = 0; - csw->dCSWDataResidue = hostLength; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - TRACE_ERROR("cmd=0x%0x h=%d d=%d", cbw->pCommand[0], hostLength, deviceLength); - - if(hostLength > deviceLength) { - - // Case 5 (Hi > Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 5\n\r"); - commandState->postprocess = MSDD_CASE_STALL_IN; - commandState->length = deviceLength; - csw->dCSWDataResidue = hostLength - deviceLength; - } - else if(hostLength == deviceLength) { - - // Case 6 (Hi = Di) - commandState->postprocess = 0; - commandState->length = deviceLength; - } - else { //if(hostLength < deviceLength) { - - // Case 7 (Hi < Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 7\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = hostLength; - } - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - // Case 8 (Hi <> Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 8\n\r"); - commandState->postprocess = - MSDD_CASE_STALL_IN | MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - } - else if(hostType == MSDD_HOST_TO_DEVICE) { - - if(deviceType == MSDD_NO_TRANSFER) { - - // Case 9 (Ho > Dn) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 9\n\r"); - commandState->postprocess = MSDD_CASE_STALL_OUT; - commandState->length = 0; - csw->dCSWDataResidue = hostLength; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - // Case 10 (Ho <> Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 10\n\r"); - commandState->postprocess = - MSDD_CASE_STALL_OUT | MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - if(hostLength > deviceLength) { - - // Case 11 (Ho > Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 11\n\r"); - commandState->postprocess = MSDD_CASE_STALL_OUT; -// commandState->length = deviceLength; -// csw->dCSWDataResidue = hostLength - deviceLength; - commandState->length = 0; - csw->dCSWDataResidue = deviceLength; - } - else if(hostLength == deviceLength) { - - // Case 12 (Ho = Do) - //TRACE_WARNING( - // "MSDD_PreProcessCommand: Case 12\n\r"); - commandState->postprocess = 0; - commandState->length = deviceLength; - } - else { //if(hostLength < deviceLength) { - - // Case 13 (Ho < Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 13\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = hostLength; - } - } - } - } - - return isCommandSupported; -} - -//----------------------------------------------------------------------------- -/// Post-processes a command given the case identified during the -/// pre-processing step. -/// Depending on the case, one of the following actions can be done: -/// - Bulk IN endpoint is stalled -/// - Bulk OUT endpoint is stalled -/// - CSW status set to phase error -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return If the device is halted -//----------------------------------------------------------------------------- -static unsigned char MSDD_PostProcessCommand(MSDDriver *pMsdDriver) -{ - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCsw *csw = &(commandState->csw); - unsigned char haltStatus = 0; - - // STALL Bulk IN endpoint ? - if ((commandState->postprocess & MSDD_CASE_STALL_IN) != 0) { - - TRACE_INFO_WP("StallIn "); - MSDD_Halt(MSDD_CASE_STALL_IN); - haltStatus = 1; - } - - // STALL Bulk OUT endpoint ? - if ((commandState->postprocess & MSDD_CASE_STALL_OUT) != 0) { - - TRACE_INFO_WP("StallOut "); - MSDD_Halt(MSDD_CASE_STALL_OUT); - haltStatus = 1; - } - - // Set CSW status code to phase error ? - if ((commandState->postprocess & MSDD_CASE_PHASE_ERROR) != 0) { - - TRACE_INFO_WP("PhaseErr "); - csw->bCSWStatus = MSD_CSW_PHASE_ERROR; - } - - return haltStatus; -} - -//----------------------------------------------------------------------------- -/// Processes the latest command received by the %device. -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return 1 if the command has been completed, false otherwise. -//----------------------------------------------------------------------------- -static unsigned char MSDD_ProcessCommand(MSDDriver * pMsdDriver) -{ - unsigned char status; - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCbw *cbw = &(commandState->cbw); - MSCsw *csw = &(commandState->csw); - MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); - unsigned char isCommandComplete = 0; - - // Check if LUN is valid - if (cbw->bCBWLUN > pMsdDriver->maxLun) { - - TRACE_WARNING( - "MSDD_ProcessCommand: LUN %d not exist\n\r", cbw->bCBWLUN); - status = MSDD_STATUS_ERROR; - } - else { - - // Process command - if (pMsdDriver->maxLun > 0) { - - TRACE_INFO_WP("LUN%d ", cbw->bCBWLUN); - } - - status = SBC_ProcessCommand(lun, commandState); - } - - // Check command result code - if (status == MSDD_STATUS_PARAMETER) { - - TRACE_WARNING( - "MSDD_ProcessCommand: Unknown cmd 0x%02X\n\r", - cbw->pCommand[0]); - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_ILLEGAL_REQUEST, - SBC_ASC_INVALID_FIELD_IN_CDB, - 0); - - // Result codes - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - - // stall the request, IN or OUT - if (((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) - && (cbw->dCBWDataTransferLength > 0)) { - - // Stall the OUT endpoint : host to device - // MSDD_Halt(MSDD_CASE_STALL_OUT); - commandState->postprocess = MSDD_CASE_STALL_OUT; - TRACE_INFO_WP("StaOUT "); - } - else { - - // Stall the IN endpoint : device to host - // MSDD_Halt(MSDD_CASE_STALL_IN); - commandState->postprocess = MSDD_CASE_STALL_IN; - TRACE_INFO_WP("StaIN "); - } - } - else if (status == MSDD_STATUS_ERROR) { - - TRACE_WARNING("MSD_ProcessCommand: Cmd %x fail\n\r", - ((SBCCommand*)commandState->cbw.pCommand)->bOperationCode); - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_MEDIUM_ERROR, - SBC_ASC_INVALID_FIELD_IN_CDB, - 0); - - // Result codes - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - } - else if (status == MSDD_STATUS_RW) { - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - } - else { - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NO_SENSE, - 0, - 0); - - // Is command complete ? - if (status == MSDD_STATUS_SUCCESS) { - - isCommandComplete = 1; - } - } - - // Check if command has been completed - if (isCommandComplete) { - - TRACE_INFO_WP("Cplt "); - - // Adjust data residue - if (commandState->length != 0) { - - csw->dCSWDataResidue += commandState->length; - - // STALL the endpoint waiting for data - if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) { - - // Stall the OUT endpoint : host to device - // MSDD_Halt(MSDD_CASE_STALL_OUT); - commandState->postprocess = MSDD_CASE_STALL_OUT; - TRACE_INFO_WP("StaOUT "); - } - else { - - // Stall the IN endpoint : device to host - // MSDD_Halt(MSDD_CASE_STALL_IN); - commandState->postprocess = MSDD_CASE_STALL_IN; - TRACE_INFO_WP("StaIN "); - } - } - - // Reset command state - commandState->state = 0; - } - - return isCommandComplete; -} - -//----------------------------------------------------------------------------- -/// State machine for the MSD %device driver -/// \param pMsdDriver Pointer to a MSDDriver instance -//----------------------------------------------------------------------------- -void MSDD_StateMachine(MSDDriver * pMsdDriver) -{ - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCbw *cbw = &(commandState->cbw); - MSCsw *csw = &(commandState->csw); - MSDTransfer *transfer = &(commandState->transfer); - unsigned char status; - - // Identify current driver state - switch (pMsdDriver->state) { - //---------------------- - case MSDD_STATE_READ_CBW: - //---------------------- - // Start the CBW read operation - transfer->semaphore = 0; - status = MSDD_Read(cbw, - MSD_CBW_SIZE, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status == USBD_STATUS_SUCCESS) { - - // If the command was successful, wait for transfer - pMsdDriver->state = MSDD_STATE_WAIT_CBW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_CBW: - //---------------------- - // Check transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and terminate transfer - transfer->semaphore--; - - // Check if transfer was successful - if (transfer->status == USBD_STATUS_SUCCESS) { - - TRACE_INFO_WP("------------------------------\n\r"); - - // Process received command - pMsdDriver->state = MSDD_STATE_PROCESS_CBW; - } - else if (transfer->status == USBD_STATUS_RESET) { - - TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - else { - - TRACE_WARNING( - "MSDD_StateMachine: Failed to read CBW\n\r"); - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - } - break; - - //------------------------- - case MSDD_STATE_PROCESS_CBW: - //------------------------- - // Check if this is a new command - if (commandState->state == 0) { - - // Copy the CBW tag - csw->dCSWTag = cbw->dCBWTag; - - // Check that the CBW is 31 bytes long - if ((transfer->transferred != MSD_CBW_SIZE) || - (transfer->remaining != 0)) { - - TRACE_WARNING( - "MSDD_StateMachine: Invalid CBW (len %d)\n\r", - (int)transfer->transferred); - - // Wait for a reset recovery - pMsdDriver->waitResetRecovery = 1; - - // Halt the Bulk-IN and Bulk-OUT pipes - MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - pMsdDriver->state = MSDD_STATE_READ_CBW; - - } - // Check the CBW Signature - else if (cbw->dCBWSignature != MSD_CBW_SIGNATURE) { - - TRACE_WARNING( - "MSD_BOTStateMachine: Invalid CBW (Bad signature)\n\r"); - - // Wait for a reset recovery - pMsdDriver->waitResetRecovery = 1; - - // Halt the Bulk-IN and Bulk-OUT pipes - MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - else { - - // Pre-process command - MSDD_PreProcessCommand(pMsdDriver); - } - } - - // Process command - if (csw->bCSWStatus == MSDD_STATUS_SUCCESS) { - - if (MSDD_ProcessCommand(pMsdDriver)) { - - // Post-process command if it is finished - if (MSDD_PostProcessCommand(pMsdDriver)) { - - TRACE_INFO_WP("WaitHALT "); - pMsdDriver->state = MSDD_STATE_WAIT_HALT; - } - else { - - pMsdDriver->state = MSDD_STATE_SEND_CSW; - } - } - TRACE_INFO_WP("\n\r"); - } - - break; - - //---------------------- - case MSDD_STATE_SEND_CSW: - //---------------------- - // Set signature - csw->dCSWSignature = MSD_CSW_SIGNATURE; - - // Start the CSW write operation - status = MSDD_Write(csw, - MSD_CSW_SIZE, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status == USBD_STATUS_SUCCESS) { - - TRACE_INFO_WP("SendCSW "); - - // Wait for end of transfer - pMsdDriver->state = MSDD_STATE_WAIT_CSW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_CSW: - //---------------------- - // Check transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and terminate transfer - transfer->semaphore--; - - // Check if transfer was successful - if (transfer->status == USBD_STATUS_RESET) { - - TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); - } - else if (transfer->status == USBD_STATUS_ABORTED) { - - TRACE_WARNING( - "MSDD_StateMachine: Failed to send CSW\n\r"); - } - else { - - TRACE_INFO_WP("ok"); - } - - // Read new CBW - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_HALT: - //---------------------- - if (MSDD_IsHalted() == 0) { - - pMsdDriver->state = MSDD_STATE_SEND_CSW; - } - break; - } -} +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- + +#include "../../../usb/device/massstorage/MSDDStateMachine.h" + +#include "../../../usb/device/massstorage/SBCMethods.h" + +//----------------------------------------------------------------------------- +// Internal functions +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +/// Returns the expected transfer length and direction (IN, OUT or don't care) +/// from the host point-of-view. +/// \param cbw Pointer to the CBW to examinate +/// \param pLength Expected length of command +/// \param pType Expected direction of command +//----------------------------------------------------------------------------- +static void MSDD_GetCommandInformation(MSCbw *cbw, + unsigned int *length, + unsigned char *type) +{ + // Expected host transfer direction and length + (*length) = cbw->dCBWDataTransferLength; + + if (*length == 0) { + + (*type) = MSDD_NO_TRANSFER; + } + else if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) != 0) { + + (*type) = MSDD_DEVICE_TO_HOST; + } + else { + + (*type) = MSDD_HOST_TO_DEVICE; + } +} + +//----------------------------------------------------------------------------- +/// Pre-processes a command by checking the differences between the host and +/// device expectations in term of transfer type and length. +/// Once one of the thirteen cases is identified, the actions to do during the +/// post-processing phase are stored in the dCase variable of the command +/// state. +/// \param pMsdDriver Pointer to a MSDDriver instance +/// \return 1 if the command is supported, false otherwise +//----------------------------------------------------------------------------- +static unsigned char MSDD_PreProcessCommand(MSDDriver *pMsdDriver) +{ + unsigned int hostLength = 0; + unsigned int deviceLength = 0; + unsigned char hostType; + unsigned char deviceType; + unsigned char isCommandSupported; + MSDCommandState *commandState = &(pMsdDriver->commandState); + MSCsw *csw = &(commandState->csw); + MSCbw *cbw = &(commandState->cbw); + MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); + + // Get information about the command + // Host-side + MSDD_GetCommandInformation(cbw, &hostLength, &hostType); + + // Device-side + isCommandSupported = SBC_GetCommandInformation(cbw->pCommand, + &deviceLength, + &deviceType, + lun); + + // Initialize data residue and result status + csw->dCSWDataResidue = 0; + csw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + + // Check if the command is supported + if (isCommandSupported) { + + // Identify the command case + if(hostType == MSDD_NO_TRANSFER) { + + // Case 1 (Hn = Dn) + if(deviceType == MSDD_NO_TRANSFER) { + + //TRACE_WARNING("Case 1\n\r"); + commandState->postprocess = 0; + commandState->length = 0; + } + else if(deviceType == MSDD_DEVICE_TO_HOST) { + + // Case 2 (Hn < Di) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 2\n\r"); + commandState->postprocess = MSDD_CASE_PHASE_ERROR; + commandState->length = 0; + } + else { //if(deviceType == MSDD_HOST_TO_DEVICE) { + + // Case 3 (Hn < Do) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 3\n\r"); + commandState->postprocess = MSDD_CASE_PHASE_ERROR; + commandState->length = 0; + } + } + + // Case 4 (Hi > Dn) + else if(hostType == MSDD_DEVICE_TO_HOST) { + + if(deviceType == MSDD_NO_TRANSFER) { + + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 4\n\r"); + commandState->postprocess = MSDD_CASE_STALL_IN; + commandState->length = 0; + csw->dCSWDataResidue = hostLength; + } + else if(deviceType == MSDD_DEVICE_TO_HOST) { + + TRACE_ERROR("cmd=0x%0x h=%d d=%d", cbw->pCommand[0], hostLength, deviceLength); + + if(hostLength > deviceLength) { + + // Case 5 (Hi > Di) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 5\n\r"); + commandState->postprocess = MSDD_CASE_STALL_IN; + commandState->length = deviceLength; + csw->dCSWDataResidue = hostLength - deviceLength; + } + else if(hostLength == deviceLength) { + + // Case 6 (Hi = Di) + commandState->postprocess = 0; + commandState->length = deviceLength; + } + else { //if(hostLength < deviceLength) { + + // Case 7 (Hi < Di) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 7\n\r"); + commandState->postprocess = MSDD_CASE_PHASE_ERROR; + commandState->length = hostLength; + } + } + else { //if(deviceType == MSDD_HOST_TO_DEVICE) { + + // Case 8 (Hi <> Do) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 8\n\r"); + commandState->postprocess = + MSDD_CASE_STALL_IN | MSDD_CASE_PHASE_ERROR; + commandState->length = 0; + } + } + else if(hostType == MSDD_HOST_TO_DEVICE) { + + if(deviceType == MSDD_NO_TRANSFER) { + + // Case 9 (Ho > Dn) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 9\n\r"); + commandState->postprocess = MSDD_CASE_STALL_OUT; + commandState->length = 0; + csw->dCSWDataResidue = hostLength; + } + else if(deviceType == MSDD_DEVICE_TO_HOST) { + + // Case 10 (Ho <> Di) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 10\n\r"); + commandState->postprocess = + MSDD_CASE_STALL_OUT | MSDD_CASE_PHASE_ERROR; + commandState->length = 0; + } + else { //if(deviceType == MSDD_HOST_TO_DEVICE) { + + if(hostLength > deviceLength) { + + // Case 11 (Ho > Do) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 11\n\r"); + commandState->postprocess = MSDD_CASE_STALL_OUT; +// commandState->length = deviceLength; +// csw->dCSWDataResidue = hostLength - deviceLength; + commandState->length = 0; + csw->dCSWDataResidue = deviceLength; + } + else if(hostLength == deviceLength) { + + // Case 12 (Ho = Do) + //TRACE_WARNING( + // "MSDD_PreProcessCommand: Case 12\n\r"); + commandState->postprocess = 0; + commandState->length = deviceLength; + } + else { //if(hostLength < deviceLength) { + + // Case 13 (Ho < Do) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 13\n\r"); + commandState->postprocess = MSDD_CASE_PHASE_ERROR; + commandState->length = hostLength; + } + } + } + } + + return isCommandSupported; +} + +//----------------------------------------------------------------------------- +/// Post-processes a command given the case identified during the +/// pre-processing step. +/// Depending on the case, one of the following actions can be done: +/// - Bulk IN endpoint is stalled +/// - Bulk OUT endpoint is stalled +/// - CSW status set to phase error +/// \param pMsdDriver Pointer to a MSDDriver instance +/// \return If the device is halted +//----------------------------------------------------------------------------- +static unsigned char MSDD_PostProcessCommand(MSDDriver *pMsdDriver) +{ + MSDCommandState *commandState = &(pMsdDriver->commandState); + MSCsw *csw = &(commandState->csw); + unsigned char haltStatus = 0; + + // STALL Bulk IN endpoint ? + if ((commandState->postprocess & MSDD_CASE_STALL_IN) != 0) { + + TRACE_INFO_WP("StallIn "); + MSDD_Halt(MSDD_CASE_STALL_IN); + haltStatus = 1; + } + + // STALL Bulk OUT endpoint ? + if ((commandState->postprocess & MSDD_CASE_STALL_OUT) != 0) { + + TRACE_INFO_WP("StallOut "); + MSDD_Halt(MSDD_CASE_STALL_OUT); + haltStatus = 1; + } + + // Set CSW status code to phase error ? + if ((commandState->postprocess & MSDD_CASE_PHASE_ERROR) != 0) { + + TRACE_INFO_WP("PhaseErr "); + csw->bCSWStatus = MSD_CSW_PHASE_ERROR; + } + + return haltStatus; +} + +//----------------------------------------------------------------------------- +/// Processes the latest command received by the %device. +/// \param pMsdDriver Pointer to a MSDDriver instance +/// \return 1 if the command has been completed, false otherwise. +//----------------------------------------------------------------------------- +static unsigned char MSDD_ProcessCommand(MSDDriver * pMsdDriver) +{ + unsigned char status; + MSDCommandState *commandState = &(pMsdDriver->commandState); + MSCbw *cbw = &(commandState->cbw); + MSCsw *csw = &(commandState->csw); + MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); + unsigned char isCommandComplete = 0; + + // Check if LUN is valid + if (cbw->bCBWLUN > pMsdDriver->maxLun) { + + TRACE_WARNING( + "MSDD_ProcessCommand: LUN %d not exist\n\r", cbw->bCBWLUN); + status = MSDD_STATUS_ERROR; + } + else { + + // Process command + if (pMsdDriver->maxLun > 0) { + + TRACE_INFO_WP("LUN%d ", cbw->bCBWLUN); + } + + status = SBC_ProcessCommand(lun, commandState); + } + + // Check command result code + if (status == MSDD_STATUS_PARAMETER) { + + TRACE_WARNING( + "MSDD_ProcessCommand: Unknown cmd 0x%02X\n\r", + cbw->pCommand[0]); + + // Update sense data + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_ILLEGAL_REQUEST, + SBC_ASC_INVALID_FIELD_IN_CDB, + 0); + + // Result codes + csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + isCommandComplete = 1; + + // stall the request, IN or OUT + if (((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) + && (cbw->dCBWDataTransferLength > 0)) { + + // Stall the OUT endpoint : host to device + // MSDD_Halt(MSDD_CASE_STALL_OUT); + commandState->postprocess = MSDD_CASE_STALL_OUT; + TRACE_INFO_WP("StaOUT "); + } + else { + + // Stall the IN endpoint : device to host + // MSDD_Halt(MSDD_CASE_STALL_IN); + commandState->postprocess = MSDD_CASE_STALL_IN; + TRACE_INFO_WP("StaIN "); + } + } + else if (status == MSDD_STATUS_ERROR) { + + TRACE_WARNING("MSD_ProcessCommand: Cmd %x fail\n\r", + ((SBCCommand*)commandState->cbw.pCommand)->bOperationCode); + + // Update sense data + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_MEDIUM_ERROR, + SBC_ASC_INVALID_FIELD_IN_CDB, + 0); + + // Result codes + csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + isCommandComplete = 1; + } + else if (status == MSDD_STATUS_RW) { + + csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + isCommandComplete = 1; + } + else { + + // Update sense data + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_NO_SENSE, + 0, + 0); + + // Is command complete ? + if (status == MSDD_STATUS_SUCCESS) { + + isCommandComplete = 1; + } + } + + // Check if command has been completed + if (isCommandComplete) { + + TRACE_INFO_WP("Cplt "); + + // Adjust data residue + if (commandState->length != 0) { + + csw->dCSWDataResidue += commandState->length; + + // STALL the endpoint waiting for data + if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) { + + // Stall the OUT endpoint : host to device + // MSDD_Halt(MSDD_CASE_STALL_OUT); + commandState->postprocess = MSDD_CASE_STALL_OUT; + TRACE_INFO_WP("StaOUT "); + } + else { + + // Stall the IN endpoint : device to host + // MSDD_Halt(MSDD_CASE_STALL_IN); + commandState->postprocess = MSDD_CASE_STALL_IN; + TRACE_INFO_WP("StaIN "); + } + } + + // Reset command state + commandState->state = 0; + } + + return isCommandComplete; +} + +//----------------------------------------------------------------------------- +/// State machine for the MSD %device driver +/// \param pMsdDriver Pointer to a MSDDriver instance +//----------------------------------------------------------------------------- +void MSDD_StateMachine(MSDDriver * pMsdDriver) +{ + MSDCommandState *commandState = &(pMsdDriver->commandState); + MSCbw *cbw = &(commandState->cbw); + MSCsw *csw = &(commandState->csw); + MSDTransfer *transfer = &(commandState->transfer); + unsigned char status; + + // Identify current driver state + switch (pMsdDriver->state) { + //---------------------- + case MSDD_STATE_READ_CBW: + //---------------------- + // Start the CBW read operation + transfer->semaphore = 0; + status = MSDD_Read(cbw, + MSD_CBW_SIZE, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check operation result code + if (status == USBD_STATUS_SUCCESS) { + + // If the command was successful, wait for transfer + pMsdDriver->state = MSDD_STATE_WAIT_CBW; + } + break; + + //---------------------- + case MSDD_STATE_WAIT_CBW: + //---------------------- + // Check transfer semaphore + if (transfer->semaphore > 0) { + + // Take semaphore and terminate transfer + transfer->semaphore--; + + // Check if transfer was successful + if (transfer->status == USBD_STATUS_SUCCESS) { + + TRACE_INFO_WP("------------------------------\n\r"); + + // Process received command + pMsdDriver->state = MSDD_STATE_PROCESS_CBW; + } + else if (transfer->status == USBD_STATUS_RESET) { + + TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); + pMsdDriver->state = MSDD_STATE_READ_CBW; + } + else { + + TRACE_WARNING( + "MSDD_StateMachine: Failed to read CBW\n\r"); + pMsdDriver->state = MSDD_STATE_READ_CBW; + } + } + break; + + //------------------------- + case MSDD_STATE_PROCESS_CBW: + //------------------------- + // Check if this is a new command + if (commandState->state == 0) { + + // Copy the CBW tag + csw->dCSWTag = cbw->dCBWTag; + + // Check that the CBW is 31 bytes long + if ((transfer->transferred != MSD_CBW_SIZE) || + (transfer->remaining != 0)) { + + TRACE_WARNING( + "MSDD_StateMachine: Invalid CBW (len %d)\n\r", + (int)transfer->transferred); + + // Wait for a reset recovery + pMsdDriver->waitResetRecovery = 1; + + // Halt the Bulk-IN and Bulk-OUT pipes + MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); + + csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + pMsdDriver->state = MSDD_STATE_READ_CBW; + + } + // Check the CBW Signature + else if (cbw->dCBWSignature != MSD_CBW_SIGNATURE) { + + TRACE_WARNING( + "MSD_BOTStateMachine: Invalid CBW (Bad signature)\n\r"); + + // Wait for a reset recovery + pMsdDriver->waitResetRecovery = 1; + + // Halt the Bulk-IN and Bulk-OUT pipes + MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); + + csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + pMsdDriver->state = MSDD_STATE_READ_CBW; + } + else { + + // Pre-process command + MSDD_PreProcessCommand(pMsdDriver); + } + } + + // Process command + if (csw->bCSWStatus == MSDD_STATUS_SUCCESS) { + + if (MSDD_ProcessCommand(pMsdDriver)) { + + // Post-process command if it is finished + if (MSDD_PostProcessCommand(pMsdDriver)) { + + TRACE_INFO_WP("WaitHALT "); + pMsdDriver->state = MSDD_STATE_WAIT_HALT; + } + else { + + pMsdDriver->state = MSDD_STATE_SEND_CSW; + } + } + TRACE_INFO_WP("\n\r"); + } + + break; + + //---------------------- + case MSDD_STATE_SEND_CSW: + //---------------------- + // Set signature + csw->dCSWSignature = MSD_CSW_SIGNATURE; + + // Start the CSW write operation + status = MSDD_Write(csw, + MSD_CSW_SIZE, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check operation result code + if (status == USBD_STATUS_SUCCESS) { + + TRACE_INFO_WP("SendCSW "); + + // Wait for end of transfer + pMsdDriver->state = MSDD_STATE_WAIT_CSW; + } + break; + + //---------------------- + case MSDD_STATE_WAIT_CSW: + //---------------------- + // Check transfer semaphore + if (transfer->semaphore > 0) { + + // Take semaphore and terminate transfer + transfer->semaphore--; + + // Check if transfer was successful + if (transfer->status == USBD_STATUS_RESET) { + + TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); + } + else if (transfer->status == USBD_STATUS_ABORTED) { + + TRACE_WARNING( + "MSDD_StateMachine: Failed to send CSW\n\r"); + } + else { + + TRACE_INFO_WP("ok"); + } + + // Read new CBW + pMsdDriver->state = MSDD_STATE_READ_CBW; + } + break; + + //---------------------- + case MSDD_STATE_WAIT_HALT: + //---------------------- + if (MSDD_IsHalted() == 0) { + + pMsdDriver->state = MSDD_STATE_SEND_CSW; + } + break; + } +} diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.h b/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.h index b55e0bf66..f8961c339 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.h +++ b/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.h @@ -1,264 +1,264 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//----------------------------------------------------------------------------- -/// \unit -/// !Purpose -/// -/// Definitions, structs, functions required by a Mass Storage device driver -/// state machine.. -/// -/// !Usage -/// -/// - For a USB device: -/// -# MSDD_Write, MSDD_Read, MSDD_Halt should be defined for -/// usage in the state machine procedure. -/// -/// -# MSDD_StateMachine is invoked to run the MSD state machine. -/// -//----------------------------------------------------------------------------- - -#ifndef MSDDSTATEMACHINE_H -#define MSDDSTATEMACHINE_H - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "../../../usb/device/massstorage/MSD.h" -#include "../../../usb/device/massstorage/MSDLun.h" -#include "debug.h" - -//----------------------------------------------------------------------------- -// Definitions -//----------------------------------------------------------------------------- - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Possible states" -/// ... -/// -/// !States -/// - MSDD_STATE_READ_CBW -/// - MSDD_STATE_WAIT_CBW -/// - MSDD_STATE_PROCESS_CBW -/// - MSDD_STATE_WAIT_HALT -/// - MSDD_STATE_SEND_CSW -/// - MSDD_STATE_WAIT_CSW -/// - MSDD_STATE_WAIT_RESET - -//! \brief Driver is expecting a command block wrapper -#define MSDD_STATE_READ_CBW (1 << 0) - -//! \brief Driver is waiting for the transfer to finish -#define MSDD_STATE_WAIT_CBW (1 << 1) - -//! \brief Driver is processing the received command -#define MSDD_STATE_PROCESS_CBW (1 << 2) - -//! \brief Driver is halted because pipe halt or wait reset -#define MSDD_STATE_WAIT_HALT (1 << 3) - -//! \brief Driver is starting the transmission of a command status wrapper -#define MSDD_STATE_SEND_CSW (1 << 4) - -//! \brief Driver is waiting for the CSW transmission to finish -#define MSDD_STATE_WAIT_CSW (1 << 5) - -//! \brief Driver is waiting for the MassStorageReset -#define MSDD_STATE_WAIT_RESET (1 << 6) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Result Codes" -/// This page lists result codes for MSD functions. -/// -/// !Codes -/// - MSDD_STATUS_SUCCESS -/// - MSDD_STATUS_ERROR -/// - MSDD_STATUS_INCOMPLETE -/// - MSDD_STATUS_PARAMETER -/// - MSDD_STATUS_RW - -//! \brief Method was successful -#define MSDD_STATUS_SUCCESS 0x00 - -//! \brief There was an error when trying to perform a method -#define MSDD_STATUS_ERROR 0x01 - -//! \brief No error was encountered but the application should call the -//! method again to continue the operation -#define MSDD_STATUS_INCOMPLETE 0x02 - -//! \brief A wrong parameter has been passed to the method -#define MSDD_STATUS_PARAMETER 0x03 - -//! \brief An error when reading/writing disk (protected or not present) -#define MSDD_STATUS_RW 0x04 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Action Cases" -/// This page lists actions to perform during the post-processing phase of a -/// command. -/// -/// !Actions -/// - MSDD_CASE_PHASE_ERROR -/// - MSDD_CASE_STALL_IN -/// - MSDD_CASE_STALL_OUT - -//! \brief Indicates that the CSW should report a phase error -#define MSDD_CASE_PHASE_ERROR (1 << 0) - -//! \brief The driver should halt the Bulk IN pipe after the transfer -#define MSDD_CASE_STALL_IN (1 << 1) - -//! \brief The driver should halt the Bulk OUT pipe after the transfer -#define MSDD_CASE_STALL_OUT (1 << 2) - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Xfr Directions" -/// This page lists possible direction values for a data transfer -/// -/// !Directions -/// - MSDD_DEVICE_TO_HOST -/// - MSDD_HOST_TO_DEVICE -/// - MSDD_NO_TRANSFER - -#define MSDD_DEVICE_TO_HOST 0 -#define MSDD_HOST_TO_DEVICE 1 -#define MSDD_NO_TRANSFER 2 -//------------------------------------------------------------------------------ - -//----------------------------------------------------------------------------- -// Types -//----------------------------------------------------------------------------- - -//------------------------------------------------------------------------------ -//! \brief Structure for holding the result of a USB transfer -//! \see MSDDriver_Callback -//------------------------------------------------------------------------------ -typedef struct { - - volatile unsigned int transferred; /// Number of bytes transferred - volatile unsigned int remaining; /// Number of bytes not transferred - volatile unsigned short semaphore; /// Semaphore to indicate transfer completion - volatile unsigned short status; /// Operation result code - -} MSDTransfer; - -//------------------------------------------------------------------------------ -//! \brief Status of an executing command -//! \see MSDCbw -//! \see MSDCsw -//! \see MSDTransfer -//------------------------------------------------------------------------------ -typedef struct { - - MSDTransfer transfer; /// Current transfer status (USB) - MSDTransfer disktransfer;/// Current transfer status (Disk) - unsigned int length; /// Remaining length of command - MSCbw cbw; /// Received CBW (31 bytes) - unsigned char state; /// Current command state - MSCsw csw; /// CSW to send (13 bytes) - unsigned char postprocess; /// Actions to perform when command is complete - -} MSDCommandState; - -//------------------------------------------------------------------------------ -/// \brief MSD driver state variables -/// \see MSDCommandState -/// \see MSDLun -//------------------------------------------------------------------------------ -typedef struct { - - /// LUN list for the %device. - MSDLun *luns; - /// State of the currently executing command - MSDCommandState commandState; - /// Maximum LUN index - unsigned char maxLun; - /// Current state of the driver - unsigned char state; - /// Indicates if the driver is waiting for a reset recovery - unsigned char waitResetRecovery; - -} MSDDriver; - -//----------------------------------------------------------------------------- -// Inline functions -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// This function is to be used as a callback for USB or LUN transfers. -/// \param transfer Pointer to the transfer structure to update -/// \param status Operation result code -/// \param transferred Number of bytes transferred by the command -/// \param remaining Number of bytes not transferred -//----------------------------------------------------------------------------- -static inline void MSDDriver_Callback(MSDTransfer *transfer, - unsigned char status, - unsigned int transferred, - unsigned int remaining) -{ - TRACE_DEBUG("Cbk "); - transfer->semaphore++; - transfer->status = status; - transfer->transferred = transferred; - transfer->remaining = remaining; -} - -//----------------------------------------------------------------------------- -// Driver functions -//----------------------------------------------------------------------------- -//- MSD General support function -extern char MSDD_Read( - void* pData, - unsigned int dLength, - TransferCallback fCallback, - void* pArgument); - -extern char MSDD_Write( - void* pData, - unsigned int dLength, - TransferCallback fCallback, - void* pArgument); - -extern void MSDD_Halt(unsigned int stallCase); - -extern unsigned int MSDD_IsHalted(void); - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -extern void MSDD_StateMachine(MSDDriver * pMsdDriver); - -#endif // #define MSDDSTATEMACHINE_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//----------------------------------------------------------------------------- +/// \unit +/// !Purpose +/// +/// Definitions, structs, functions required by a Mass Storage device driver +/// state machine.. +/// +/// !Usage +/// +/// - For a USB device: +/// -# MSDD_Write, MSDD_Read, MSDD_Halt should be defined for +/// usage in the state machine procedure. +/// +/// -# MSDD_StateMachine is invoked to run the MSD state machine. +/// +//----------------------------------------------------------------------------- + +#ifndef MSDDSTATEMACHINE_H +#define MSDDSTATEMACHINE_H + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- + +#include "../../../usb/device/massstorage/MSD.h" +#include "../../../usb/device/massstorage/MSDLun.h" +#include "debug.h" + +//----------------------------------------------------------------------------- +// Definitions +//----------------------------------------------------------------------------- + +//------------------------------------------------------------------------------ +/// \page "MSD Driver Possible states" +/// ... +/// +/// !States +/// - MSDD_STATE_READ_CBW +/// - MSDD_STATE_WAIT_CBW +/// - MSDD_STATE_PROCESS_CBW +/// - MSDD_STATE_WAIT_HALT +/// - MSDD_STATE_SEND_CSW +/// - MSDD_STATE_WAIT_CSW +/// - MSDD_STATE_WAIT_RESET + +//! \brief Driver is expecting a command block wrapper +#define MSDD_STATE_READ_CBW (1 << 0) + +//! \brief Driver is waiting for the transfer to finish +#define MSDD_STATE_WAIT_CBW (1 << 1) + +//! \brief Driver is processing the received command +#define MSDD_STATE_PROCESS_CBW (1 << 2) + +//! \brief Driver is halted because pipe halt or wait reset +#define MSDD_STATE_WAIT_HALT (1 << 3) + +//! \brief Driver is starting the transmission of a command status wrapper +#define MSDD_STATE_SEND_CSW (1 << 4) + +//! \brief Driver is waiting for the CSW transmission to finish +#define MSDD_STATE_WAIT_CSW (1 << 5) + +//! \brief Driver is waiting for the MassStorageReset +#define MSDD_STATE_WAIT_RESET (1 << 6) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Driver Result Codes" +/// This page lists result codes for MSD functions. +/// +/// !Codes +/// - MSDD_STATUS_SUCCESS +/// - MSDD_STATUS_ERROR +/// - MSDD_STATUS_INCOMPLETE +/// - MSDD_STATUS_PARAMETER +/// - MSDD_STATUS_RW + +//! \brief Method was successful +#define MSDD_STATUS_SUCCESS 0x00 + +//! \brief There was an error when trying to perform a method +#define MSDD_STATUS_ERROR 0x01 + +//! \brief No error was encountered but the application should call the +//! method again to continue the operation +#define MSDD_STATUS_INCOMPLETE 0x02 + +//! \brief A wrong parameter has been passed to the method +#define MSDD_STATUS_PARAMETER 0x03 + +//! \brief An error when reading/writing disk (protected or not present) +#define MSDD_STATUS_RW 0x04 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Driver Action Cases" +/// This page lists actions to perform during the post-processing phase of a +/// command. +/// +/// !Actions +/// - MSDD_CASE_PHASE_ERROR +/// - MSDD_CASE_STALL_IN +/// - MSDD_CASE_STALL_OUT + +//! \brief Indicates that the CSW should report a phase error +#define MSDD_CASE_PHASE_ERROR (1 << 0) + +//! \brief The driver should halt the Bulk IN pipe after the transfer +#define MSDD_CASE_STALL_IN (1 << 1) + +//! \brief The driver should halt the Bulk OUT pipe after the transfer +#define MSDD_CASE_STALL_OUT (1 << 2) + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Driver Xfr Directions" +/// This page lists possible direction values for a data transfer +/// +/// !Directions +/// - MSDD_DEVICE_TO_HOST +/// - MSDD_HOST_TO_DEVICE +/// - MSDD_NO_TRANSFER + +#define MSDD_DEVICE_TO_HOST 0 +#define MSDD_HOST_TO_DEVICE 1 +#define MSDD_NO_TRANSFER 2 +//------------------------------------------------------------------------------ + +//----------------------------------------------------------------------------- +// Types +//----------------------------------------------------------------------------- + +//------------------------------------------------------------------------------ +//! \brief Structure for holding the result of a USB transfer +//! \see MSDDriver_Callback +//------------------------------------------------------------------------------ +typedef struct { + + volatile unsigned int transferred; /// Number of bytes transferred + volatile unsigned int remaining; /// Number of bytes not transferred + volatile unsigned short semaphore; /// Semaphore to indicate transfer completion + volatile unsigned short status; /// Operation result code + +} MSDTransfer; + +//------------------------------------------------------------------------------ +//! \brief Status of an executing command +//! \see MSDCbw +//! \see MSDCsw +//! \see MSDTransfer +//------------------------------------------------------------------------------ +typedef struct { + + MSDTransfer transfer; /// Current transfer status (USB) + MSDTransfer disktransfer;/// Current transfer status (Disk) + unsigned int length; /// Remaining length of command + MSCbw cbw; /// Received CBW (31 bytes) + unsigned char state; /// Current command state + MSCsw csw; /// CSW to send (13 bytes) + unsigned char postprocess; /// Actions to perform when command is complete + +} MSDCommandState; + +//------------------------------------------------------------------------------ +/// \brief MSD driver state variables +/// \see MSDCommandState +/// \see MSDLun +//------------------------------------------------------------------------------ +typedef struct { + + /// LUN list for the %device. + MSDLun *luns; + /// State of the currently executing command + MSDCommandState commandState; + /// Maximum LUN index + unsigned char maxLun; + /// Current state of the driver + unsigned char state; + /// Indicates if the driver is waiting for a reset recovery + unsigned char waitResetRecovery; + +} MSDDriver; + +//----------------------------------------------------------------------------- +// Inline functions +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +/// This function is to be used as a callback for USB or LUN transfers. +/// \param transfer Pointer to the transfer structure to update +/// \param status Operation result code +/// \param transferred Number of bytes transferred by the command +/// \param remaining Number of bytes not transferred +//----------------------------------------------------------------------------- +static inline void MSDDriver_Callback(MSDTransfer *transfer, + unsigned char status, + unsigned int transferred, + unsigned int remaining) +{ + TRACE_DEBUG("Cbk "); + transfer->semaphore++; + transfer->status = status; + transfer->transferred = transferred; + transfer->remaining = remaining; +} + +//----------------------------------------------------------------------------- +// Driver functions +//----------------------------------------------------------------------------- +//- MSD General support function +extern char MSDD_Read( + void* pData, + unsigned int dLength, + TransferCallback fCallback, + void* pArgument); + +extern char MSDD_Write( + void* pData, + unsigned int dLength, + TransferCallback fCallback, + void* pArgument); + +extern void MSDD_Halt(unsigned int stallCase); + +extern unsigned int MSDD_IsHalted(void); + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +extern void MSDD_StateMachine(MSDDriver * pMsdDriver); + +#endif // #define MSDDSTATEMACHINE_H + diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.c b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.c index 6ae50b133..b05c43c2a 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.c +++ b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.c @@ -1,342 +1,342 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "../../../usb/device/massstorage/MSDDriver.h" - -#include "../../../usb/common/core/USBFeatureRequest.h" -#include "../../../usb/device/core/USBDDriver.h" -#include "../../../usb/device/massstorage/MSDDriverDescriptors.h" -#include "../../../usb/device/massstorage/SBCMethods.h" -#include "../../../Media.h" -#include "../../../usb/common/core/USBGenericRequest.h" -#include "../../../usb/device/core/USBD.h" -#include "debug.h" - -//----------------------------------------------------------------------------- -// Internal variables -//----------------------------------------------------------------------------- - -/// Mass storage device driver instance. -static MSDDriver msdDriver; - -/// Standard device driver instance. -static USBDDriver usbdDriver; - -//----------------------------------------------------------------------------- -// Internal functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Resets the state of the MSD driver -//----------------------------------------------------------------------------- -static void MSDDriver_Reset(void) -{ - TRACE_INFO_WP("MSDReset "); - - msdDriver.state = MSDD_STATE_READ_CBW; - msdDriver.waitResetRecovery = 0; - msdDriver.commandState.state = 0; -} - -//----------------------------------------------------------------------------- -// Callback re-implementation -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// Invoked when a new SETUP request is received from the host. Forwards the -/// request to the Mass Storage device driver handler function. -/// \param request Pointer to a USBGenericRequest instance. -//----------------------------------------------------------------------------- -void USBDCallbacks_RequestReceived(const USBGenericRequest *request) -{ - MSDDriver_RequestHandler(request); -} - -//----------------------------------------------------------------------------- -/// Invoked when the configuration of the device changes. Resets the mass -/// storage driver. -/// \param cfgnum New configuration number. -//----------------------------------------------------------------------------- -void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) -{ - if (cfgnum > 0) { - - MSDDriver_Reset(); - } -} - -//----------------------------------------------------------------------------- -// Driver functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Reads from host through MSD defined bulk OUT pipe. Act as USBD_Read but by -/// a fixed OUT endpoint. -/// \param data Pointer to the data buffer that contains data read from host. -/// \param size The number of bytes should be read (buffer size). -/// \param callback Pointer to the function invoked on end of reading. -/// \param argument Pointer to additional argument data struct. -//----------------------------------------------------------------------------- -char MSDD_Read(void *data, - unsigned int size, - TransferCallback callback, - void *argument) - -{ - return USBD_Read(MSDDriverDescriptors_BULKOUT, - data, - size, - callback, - argument); -} - -//----------------------------------------------------------------------------- -/// Writes to host through MSD defined bulk IN pipe. Act as USBD_Write but by -/// a fixed IN endpoint. -/// \param data Pointer to the data that writes to the host. -/// \param size The number of bytes should be write. -/// \param callback Pointer to the function invoked on end of writing. -/// \param argument Pointer to additional argument data struct. -//----------------------------------------------------------------------------- -char MSDD_Write(void *data, - unsigned int size, - TransferCallback callback, - void *argument) -{ - return USBD_Write(MSDDriverDescriptors_BULKIN, - data, - size, - callback, - argument); -} - -//----------------------------------------------------------------------------- -/// HALT Specified USB pipe. -/// \param stallCASE Case of the stall condition (Bulk In/Out/Both). -//----------------------------------------------------------------------------- -void MSDD_Halt(unsigned int stallCASE) -{ - if (stallCASE & MSDD_CASE_STALL_OUT) { - - USBD_Halt(MSDDriverDescriptors_BULKOUT); - } - - if (stallCASE & MSDD_CASE_STALL_IN) { - - USBD_Halt(MSDDriverDescriptors_BULKIN); - } -} - -//----------------------------------------------------------------------------- -/// Return halted status -/// \return stallCASE bitmap, case of the stall condition -/// (bit: MSDD_CASE_STALL_OUT or MSDD_CASE_STALL_IN) -//----------------------------------------------------------------------------- -unsigned int MSDD_IsHalted(void) -{ - unsigned int stallCASE = 0; - if (USBD_IsHalted(MSDDriverDescriptors_BULKOUT)) { - - stallCASE |= MSDD_CASE_STALL_OUT; - } - if (USBD_IsHalted(MSDDriverDescriptors_BULKIN)) { - - stallCASE |= MSDD_CASE_STALL_IN; - } - return stallCASE; -} - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Initializes the MSD driver and the associated USB driver. -/// \param luns Pointer to a list of LUNs -/// \param numLuns Number of LUN in list -/// \see MSDLun -//----------------------------------------------------------------------------- -void MSDDriver_Initialize(MSDLun *defLuns, unsigned char numLuns) -{ - - TRACE_INFO("MSD init\n\r"); - - // Command state initialization - msdDriver.commandState.state = 0; - msdDriver.commandState.postprocess = 0; - msdDriver.commandState.length = 0; - msdDriver.commandState.transfer.semaphore = 0; - - // LUNs - msdDriver.luns = defLuns; - msdDriver.maxLun = (unsigned char) (numLuns - 1); - - // Reset BOT driver - MSDDriver_Reset(); - - // Init the USB driver - USBDDriver_Initialize(&usbdDriver, &msdDriverDescriptors, 0); - USBD_Init(); -} - -//----------------------------------------------------------------------------- -/// Handler for incoming SETUP requests on default Control endpoint 0. -/// -/// Standard requests are forwarded to the USBDDriver_RequestHandler -/// method. -/// \param request Pointer to a USBGenericRequest instance -//----------------------------------------------------------------------------- -void MSDDriver_RequestHandler(const USBGenericRequest *request) -{ - TRACE_INFO_WP("NewReq "); - - // Handle requests - switch (USBGenericRequest_GetRequest(request)) { - //--------------------- - case USBGenericRequest_CLEARFEATURE: - //--------------------- - TRACE_INFO_WP("ClrFeat "); - - switch (USBFeatureRequest_GetFeatureSelector(request)) { - - //--------------------- - case USBFeatureRequest_ENDPOINTHALT: - //--------------------- - TRACE_INFO_WP("Hlt "); - - // Do not clear the endpoint halt status if the device is waiting - // for a reset recovery sequence - if (!msdDriver.waitResetRecovery) { - - // Forward the request to the standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - } - else { - - TRACE_INFO_WP("No "); - } - - USBD_Write(0, 0, 0, 0, 0); - break; - - //------ - default: - //------ - // Forward the request to the standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - } - break; - - //------------------- - case MSD_GET_MAX_LUN: - //------------------- - TRACE_INFO_WP("gMaxLun "); - - // Check request parameters - if ((request->wValue == 0) - && (request->wIndex == 0) - && (request->wLength == 1)) { - - USBD_Write(0, &(msdDriver.maxLun), 1, 0, 0); - - } - else { - - TRACE_WARNING( - "MSDDriver_RequestHandler: GetMaxLUN(%d,%d,%d)\n\r", - request->wValue, request->wIndex, request->wLength); - USBD_Stall(0); - } - break; - - //----------------------- - case MSD_BULK_ONLY_RESET: - //----------------------- - TRACE_INFO_WP("Rst "); - - // Check parameters - if ((request->wValue == 0) - && (request->wIndex == 0) - && (request->wLength == 0)) { - - // Reset the MSD driver - MSDDriver_Reset(); - USBD_Write(0, 0, 0, 0, 0); - } - else { - - TRACE_WARNING( - "MSDDriver_RequestHandler: Reset(%d,%d,%d)\n\r", - request->wValue, request->wIndex, request->wLength); - USBD_Stall(0); - } - break; - - //------ - default: - //------ - // Forward request to standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - - break; - } -} - -//----------------------------------------------------------------------------- -/// State machine for the MSD driver -//----------------------------------------------------------------------------- -void MSDDriver_StateMachine(void) -{ - if (USBD_GetState() < USBD_STATE_CONFIGURED){} - else MSDD_StateMachine(&msdDriver); - -} - -//----------------------------------------------------------------------------- -/// Starts a remote wake-up sequence if the host has explicitely enabled it -/// by sending the appropriate SET_FEATURE request. -//----------------------------------------------------------------------------- -void MSDDriver_RemoteWakeUp(void) -{ - // Remote wake-up has been enabled - if (USBDDriver_IsRemoteWakeUpEnabled(&usbdDriver)) { - - USBD_RemoteWakeUp(); - } - // Remote wake-up NOT enabled - else { - - TRACE_WARNING( - "MSD..RemoteWakeUp: Host has not enabled remote wake-up\n\r"); - } -} - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include "../../../usb/device/massstorage/MSDDriver.h" + +#include "../../../usb/common/core/USBFeatureRequest.h" +#include "../../../usb/device/core/USBDDriver.h" +#include "../../../usb/device/massstorage/MSDDriverDescriptors.h" +#include "../../../usb/device/massstorage/SBCMethods.h" +#include "../../../Media.h" +#include "../../../usb/common/core/USBGenericRequest.h" +#include "../../../usb/device/core/USBD.h" +#include "debug.h" + +//----------------------------------------------------------------------------- +// Internal variables +//----------------------------------------------------------------------------- + +/// Mass storage device driver instance. +static MSDDriver msdDriver; + +/// Standard device driver instance. +static USBDDriver usbdDriver; + +//----------------------------------------------------------------------------- +// Internal functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Resets the state of the MSD driver +//----------------------------------------------------------------------------- +static void MSDDriver_Reset(void) +{ + TRACE_INFO_WP("MSDReset "); + + msdDriver.state = MSDD_STATE_READ_CBW; + msdDriver.waitResetRecovery = 0; + msdDriver.commandState.state = 0; +} + +//----------------------------------------------------------------------------- +// Callback re-implementation +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +/// Invoked when a new SETUP request is received from the host. Forwards the +/// request to the Mass Storage device driver handler function. +/// \param request Pointer to a USBGenericRequest instance. +//----------------------------------------------------------------------------- +void USBDCallbacks_RequestReceived(const USBGenericRequest *request) +{ + MSDDriver_RequestHandler(request); +} + +//----------------------------------------------------------------------------- +/// Invoked when the configuration of the device changes. Resets the mass +/// storage driver. +/// \param cfgnum New configuration number. +//----------------------------------------------------------------------------- +void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) +{ + if (cfgnum > 0) { + + MSDDriver_Reset(); + } +} + +//----------------------------------------------------------------------------- +// Driver functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Reads from host through MSD defined bulk OUT pipe. Act as USBD_Read but by +/// a fixed OUT endpoint. +/// \param data Pointer to the data buffer that contains data read from host. +/// \param size The number of bytes should be read (buffer size). +/// \param callback Pointer to the function invoked on end of reading. +/// \param argument Pointer to additional argument data struct. +//----------------------------------------------------------------------------- +char MSDD_Read(void *data, + unsigned int size, + TransferCallback callback, + void *argument) + +{ + return USBD_Read(MSDDriverDescriptors_BULKOUT, + data, + size, + callback, + argument); +} + +//----------------------------------------------------------------------------- +/// Writes to host through MSD defined bulk IN pipe. Act as USBD_Write but by +/// a fixed IN endpoint. +/// \param data Pointer to the data that writes to the host. +/// \param size The number of bytes should be write. +/// \param callback Pointer to the function invoked on end of writing. +/// \param argument Pointer to additional argument data struct. +//----------------------------------------------------------------------------- +char MSDD_Write(void *data, + unsigned int size, + TransferCallback callback, + void *argument) +{ + return USBD_Write(MSDDriverDescriptors_BULKIN, + data, + size, + callback, + argument); +} + +//----------------------------------------------------------------------------- +/// HALT Specified USB pipe. +/// \param stallCASE Case of the stall condition (Bulk In/Out/Both). +//----------------------------------------------------------------------------- +void MSDD_Halt(unsigned int stallCASE) +{ + if (stallCASE & MSDD_CASE_STALL_OUT) { + + USBD_Halt(MSDDriverDescriptors_BULKOUT); + } + + if (stallCASE & MSDD_CASE_STALL_IN) { + + USBD_Halt(MSDDriverDescriptors_BULKIN); + } +} + +//----------------------------------------------------------------------------- +/// Return halted status +/// \return stallCASE bitmap, case of the stall condition +/// (bit: MSDD_CASE_STALL_OUT or MSDD_CASE_STALL_IN) +//----------------------------------------------------------------------------- +unsigned int MSDD_IsHalted(void) +{ + unsigned int stallCASE = 0; + if (USBD_IsHalted(MSDDriverDescriptors_BULKOUT)) { + + stallCASE |= MSDD_CASE_STALL_OUT; + } + if (USBD_IsHalted(MSDDriverDescriptors_BULKIN)) { + + stallCASE |= MSDD_CASE_STALL_IN; + } + return stallCASE; +} + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Initializes the MSD driver and the associated USB driver. +/// \param luns Pointer to a list of LUNs +/// \param numLuns Number of LUN in list +/// \see MSDLun +//----------------------------------------------------------------------------- +void MSDDriver_Initialize(MSDLun *defLuns, unsigned char numLuns) +{ + + TRACE_INFO("MSD init\n\r"); + + // Command state initialization + msdDriver.commandState.state = 0; + msdDriver.commandState.postprocess = 0; + msdDriver.commandState.length = 0; + msdDriver.commandState.transfer.semaphore = 0; + + // LUNs + msdDriver.luns = defLuns; + msdDriver.maxLun = (unsigned char) (numLuns - 1); + + // Reset BOT driver + MSDDriver_Reset(); + + // Init the USB driver + USBDDriver_Initialize(&usbdDriver, &msdDriverDescriptors, 0); + USBD_Init(); +} + +//----------------------------------------------------------------------------- +/// Handler for incoming SETUP requests on default Control endpoint 0. +/// +/// Standard requests are forwarded to the USBDDriver_RequestHandler +/// method. +/// \param request Pointer to a USBGenericRequest instance +//----------------------------------------------------------------------------- +void MSDDriver_RequestHandler(const USBGenericRequest *request) +{ + TRACE_INFO_WP("NewReq "); + + // Handle requests + switch (USBGenericRequest_GetRequest(request)) { + //--------------------- + case USBGenericRequest_CLEARFEATURE: + //--------------------- + TRACE_INFO_WP("ClrFeat "); + + switch (USBFeatureRequest_GetFeatureSelector(request)) { + + //--------------------- + case USBFeatureRequest_ENDPOINTHALT: + //--------------------- + TRACE_INFO_WP("Hlt "); + + // Do not clear the endpoint halt status if the device is waiting + // for a reset recovery sequence + if (!msdDriver.waitResetRecovery) { + + // Forward the request to the standard handler + USBDDriver_RequestHandler(&usbdDriver, request); + } + else { + + TRACE_INFO_WP("No "); + } + + USBD_Write(0, 0, 0, 0, 0); + break; + + //------ + default: + //------ + // Forward the request to the standard handler + USBDDriver_RequestHandler(&usbdDriver, request); + } + break; + + //------------------- + case MSD_GET_MAX_LUN: + //------------------- + TRACE_INFO_WP("gMaxLun "); + + // Check request parameters + if ((request->wValue == 0) + && (request->wIndex == 0) + && (request->wLength == 1)) { + + USBD_Write(0, &(msdDriver.maxLun), 1, 0, 0); + + } + else { + + TRACE_WARNING( + "MSDDriver_RequestHandler: GetMaxLUN(%d,%d,%d)\n\r", + request->wValue, request->wIndex, request->wLength); + USBD_Stall(0); + } + break; + + //----------------------- + case MSD_BULK_ONLY_RESET: + //----------------------- + TRACE_INFO_WP("Rst "); + + // Check parameters + if ((request->wValue == 0) + && (request->wIndex == 0) + && (request->wLength == 0)) { + + // Reset the MSD driver + MSDDriver_Reset(); + USBD_Write(0, 0, 0, 0, 0); + } + else { + + TRACE_WARNING( + "MSDDriver_RequestHandler: Reset(%d,%d,%d)\n\r", + request->wValue, request->wIndex, request->wLength); + USBD_Stall(0); + } + break; + + //------ + default: + //------ + // Forward request to standard handler + USBDDriver_RequestHandler(&usbdDriver, request); + + break; + } +} + +//----------------------------------------------------------------------------- +/// State machine for the MSD driver +//----------------------------------------------------------------------------- +void MSDDriver_StateMachine(void) +{ + if (USBD_GetState() < USBD_STATE_CONFIGURED){} + else MSDD_StateMachine(&msdDriver); + +} + +//----------------------------------------------------------------------------- +/// Starts a remote wake-up sequence if the host has explicitely enabled it +/// by sending the appropriate SET_FEATURE request. +//----------------------------------------------------------------------------- +void MSDDriver_RemoteWakeUp(void) +{ + // Remote wake-up has been enabled + if (USBDDriver_IsRemoteWakeUpEnabled(&usbdDriver)) { + + USBD_RemoteWakeUp(); + } + // Remote wake-up NOT enabled + else { + + TRACE_WARNING( + "MSD..RemoteWakeUp: Host has not enabled remote wake-up\n\r"); + } +} + diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.h b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.h index cc3204c74..a1ac1e990 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.h +++ b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.h @@ -1,75 +1,75 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Mass storage %device driver implementation. -/// -/// !Usage -/// -/// -# Enable and setup USB related pins (see pio & board.h). -/// -# Configure the memory interfaces used for Mass Storage LUNs -/// (see memories, MSDLun.h). -/// -# Configure the USB MSD %driver using MSDDriver_Initialize. -/// -# Invoke MSDDriver_StateMachine in main loop to handle all Mass Storage -/// operations. -//------------------------------------------------------------------------------ - -#ifndef MSDDRIVER_H -#define MSDDRIVER_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/device/massstorage/MSD.h" -#include "../../../usb/device/massstorage/MSDLun.h" -// #include - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -extern void MSDDriver_Initialize(MSDLun *luns, unsigned char numLuns); - -extern void MSDDriver_RequestHandler(const USBGenericRequest *request); - -extern void MSDDriver_StateMachine(void); - -extern void MSDDriver_RemoteWakeUp(void); - -extern void MSDDriver_DataCallback(unsigned char isRead, - unsigned int dataLength, - unsigned int nullCnt, - unsigned int fullCnt); - -#endif // #ifndef MSDDRIVER_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Mass storage %device driver implementation. +/// +/// !Usage +/// +/// -# Enable and setup USB related pins (see pio & board.h). +/// -# Configure the memory interfaces used for Mass Storage LUNs +/// (see memories, MSDLun.h). +/// -# Configure the USB MSD %driver using MSDDriver_Initialize. +/// -# Invoke MSDDriver_StateMachine in main loop to handle all Mass Storage +/// operations. +//------------------------------------------------------------------------------ + +#ifndef MSDDRIVER_H +#define MSDDRIVER_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/device/massstorage/MSD.h" +#include "../../../usb/device/massstorage/MSDLun.h" +// #include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void MSDDriver_Initialize(MSDLun *luns, unsigned char numLuns); + +extern void MSDDriver_RequestHandler(const USBGenericRequest *request); + +extern void MSDDriver_StateMachine(void); + +extern void MSDDriver_RemoteWakeUp(void); + +extern void MSDDriver_DataCallback(unsigned char isRead, + unsigned int dataLength, + unsigned int nullCnt, + unsigned int fullCnt); + +#endif // #ifndef MSDDRIVER_H + diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.c b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.c index 11b01d368..47a25d7c6 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.c +++ b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.c @@ -1,469 +1,469 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/device/massstorage/MSDDriverDescriptors.h" - -#include "../../../usb/common/core/USBStringDescriptor.h" -#include "../../../usb/common/massstorage/MSDeviceDescriptor.h" -#include "../../../usb/common/massstorage/MSInterfaceDescriptor.h" -#include "board_lowlevel.h" -#include "../../../usb/common/core/USBConfigurationDescriptor.h" -#include "../../../usb/common/core/USBDeviceDescriptor.h" -#include "../../../usb/common/core/USBEndpointDescriptor.h" -#include "../../../usb/common/core/USBGenericDescriptor.h" -#include "../../../usb/common/core/USBInterfaceDescriptor.h" - -//------------------------------------------------------------------------------ -// Internal definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Device Descriptor IDs" -/// ... -/// !IDs -/// - MSDDriverDescriptors_VENDORID -/// - MSDDriverDescriptors_PRODUCTID -/// - MSDDriverDescriptors_RELEASE - -/// Vendor ID for the Mass Storage device driver. -#define MSDDriverDescriptors_VENDORID 0x03EB -/// Product ID for the Mass Storage device driver. -#define MSDDriverDescriptors_PRODUCTID 0x6129 -/// Device release number for the Mass Storage device driver. -#define MSDDriverDescriptors_RELEASE 0x0100 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Macros -//------------------------------------------------------------------------------ - -/// Returns the minimum between two values. -#define MIN(a, b) ((a < b) ? a : b) - -//------------------------------------------------------------------------------ -// Internal types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// List of configuration descriptors used by a Mass Storage device driver. -//------------------------------------------------------------------------------ -typedef struct { - - /// Standard configuration descriptor. - USBConfigurationDescriptor configuration; -#if defined(CHIP_USB_OTGHS) - // OTG descriptor - USBOtgDescriptor otgDescriptor; -#endif - /// Mass storage interface descriptor. - USBInterfaceDescriptor interface; - /// Bulk-out endpoint descriptor. - USBEndpointDescriptor bulkOut; - /// Bulk-in endpoint descriptor. - USBEndpointDescriptor bulkIn; - -} __attribute__ ((packed)) MSDConfigurationDescriptors; - -//------------------------------------------------------------------------------ -// Local variables -//------------------------------------------------------------------------------ - -/// Mass storage driver device descriptor. -static const USBDeviceDescriptor deviceDescriptor = { - - sizeof(USBDeviceDescriptor), - USBGenericDescriptor_DEVICE, - USBDeviceDescriptor_USB2_00, - MSDeviceDescriptor_CLASS, - MSDeviceDescriptor_SUBCLASS, - MSDeviceDescriptor_PROTOCOL, - CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), - MSDDriverDescriptors_VENDORID, - MSDDriverDescriptors_PRODUCTID, - MSDDriverDescriptors_RELEASE, - 1, // Manufacturer string descriptor index. - 2, // Product string descriptor index. - 3, // Serial number string descriptor index. - 1 // Device has one possible configuration. -}; - -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) -/// Device qualifier descriptor. -static const USBDeviceQualifierDescriptor qualifierDescriptor = { - - sizeof(USBDeviceQualifierDescriptor), - USBGenericDescriptor_DEVICEQUALIFIER, - USBDeviceDescriptor_USB2_00, - MSDeviceDescriptor_CLASS, - MSDeviceDescriptor_SUBCLASS, - MSDeviceDescriptor_PROTOCOL, - CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), - 1, // Device has one possible configuration. - 0x00 -}; -#endif - -/// Full-speed configuration descriptor. -static const MSDConfigurationDescriptors configurationDescriptorsFS = { - - // Standard configuration descriptor. - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_CONFIGURATION, - sizeof(MSDConfigurationDescriptors), - 1, // Configuration has one interface. - 1, // This is configuration #1. - 0, // No string descriptor for configuration. - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, -#if defined(CHIP_USB_OTGHS) - // OTG descriptor - { - sizeof(USBOtgDescriptor), - USBGenericDescriptor_OTG, - USBOTGDescriptor_HNP_SRP - }, -#endif - // Mass Storage interface descriptor. - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - 0, // This is interface #0. - 0, // This is alternate setting #0. - 2, // Interface uses two endpoints. - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 // No string descriptor for interface. - }, - // Bulk-OUT endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // Must be 0 for full-speed Bulk endpoints. - }, - // Bulk-IN endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // Must be 0 for full-speed Bulk endpoints. - } -}; - -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) -/// Full-speed other speed configuration descriptor. -static const MSDConfigurationDescriptors otherSpeedDescriptorsFS = { - - // Standard configuration descriptor. - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_OTHERSPEEDCONFIGURATION, - sizeof(MSDConfigurationDescriptors), - 1, // Configuration has one interface. - 1, // This is configuration #1. - 0, // No string descriptor for configuration. - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, -#if defined(CHIP_USB_OTGHS) - // OTG descriptor - { - sizeof(USBOtgDescriptor), - USBGenericDescriptor_OTG, - USBOTGDescriptor_HNP_SRP - }, -#endif - // Mass Storage interface descriptor. - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - 0, // This is interface #0. - 0, // This is alternate setting #0. - 2, // Interface uses two endpoints. - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 // No string descriptor for interface. - }, - // Bulk-OUT endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_MAXBULKSIZE_HS), - 0 // No string descriptor for endpoint. - }, - // Bulk-IN endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_MAXBULKSIZE_HS), - 0 // No string descriptor for endpoint. - } -}; - -/// High-speed configuration descriptor. -static const MSDConfigurationDescriptors configurationDescriptorsHS = { - - // Standard configuration descriptor. - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_CONFIGURATION, - sizeof(MSDConfigurationDescriptors), - 1, // Configuration has one interface. - 1, // This is configuration #1. - 0, // No string descriptor for configuration. - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, -#if defined(CHIP_USB_OTGHS) - // OTG descriptor - { - sizeof(USBOtgDescriptor), - USBGenericDescriptor_OTG, - USBOTGDescriptor_HNP_SRP - }, -#endif - // Mass Storage interface descriptor. - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - 0, // This is interface #0. - 0, // This is alternate setting #0. - 2, // Interface uses two endpoints. - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 // No string descriptor for interface. - }, - // Bulk-OUT endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_MAXBULKSIZE_HS), - 0 // No string descriptor for endpoint. - }, - // Bulk-IN endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_MAXBULKSIZE_HS), - 0 // No string descriptor for endpoint. - } -}; - -/// High-speed other speed configuration descriptor. -static const MSDConfigurationDescriptors otherSpeedDescriptorsHS = { - - // Standard configuration descriptor. - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_OTHERSPEEDCONFIGURATION, - sizeof(MSDConfigurationDescriptors), - 1, // Configuration has one interface. - 1, // This is configuration #1. - 0, // No string descriptor for configuration. - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, -#if defined(CHIP_USB_OTGHS) - // OTG descriptor - { - sizeof(USBOtgDescriptor), - USBGenericDescriptor_OTG, - USBOTGDescriptor_HNP_SRP - }, -#endif - // Mass Storage interface descriptor. - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - 0, // This is interface #0. - 0, // This is alternate setting #0. - 2, // Interface uses two endpoints. - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 // No string descriptor for interface. - }, - // Bulk-OUT endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // No string descriptor for endpoint. - }, - // Bulk-IN endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // No string descriptor for endpoint. - } -}; -#endif - -/// Language ID string descriptor. -static const unsigned char languageIdDescriptor[] = { - - USBStringDescriptor_LENGTH(1), - USBGenericDescriptor_STRING, - USBStringDescriptor_ENGLISH_US -}; - -/// Manufacturer string descriptor. -static const unsigned char manufacturerDescriptor[] = { - - USBStringDescriptor_LENGTH(7), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('X'), - USBStringDescriptor_UNICODE(' '), - USBStringDescriptor_UNICODE('T'), - USBStringDescriptor_UNICODE('E'), - USBStringDescriptor_UNICODE('A'), - USBStringDescriptor_UNICODE('M'), -}; - -/// Product string descriptor. -static const unsigned char productDescriptor[] = { - - USBStringDescriptor_LENGTH(5), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('S'), - USBStringDescriptor_UNICODE('K'), - USBStringDescriptor_UNICODE('Y'), - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('X'), -}; - -/// Serial number string descriptor. The serial number must be at least 12 -/// characters long and made up of only letters & numbers to be compliant with -/// the MSD specification. -static const unsigned char serialNumberDescriptor[] = { - - USBStringDescriptor_LENGTH(12), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('0'), - USBStringDescriptor_UNICODE('1'), - USBStringDescriptor_UNICODE('2'), - USBStringDescriptor_UNICODE('3'), - USBStringDescriptor_UNICODE('4'), - USBStringDescriptor_UNICODE('5'), - USBStringDescriptor_UNICODE('6'), - USBStringDescriptor_UNICODE('7'), - USBStringDescriptor_UNICODE('8'), - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('A'), - USBStringDescriptor_UNICODE('B') -}; - -/// List of all string descriptors used. -static const unsigned char *stringDescriptors[] = { - - languageIdDescriptor, - manufacturerDescriptor, - productDescriptor, - serialNumberDescriptor -}; - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -/// List of the standard descriptors used by the Mass Storage driver. -const USBDDriverDescriptors msdDriverDescriptors = { - - &deviceDescriptor, - (USBConfigurationDescriptor *) &configurationDescriptorsFS, -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) - &qualifierDescriptor, - (USBConfigurationDescriptor *) &otherSpeedDescriptorsFS, - &deviceDescriptor, - (USBConfigurationDescriptor *) &configurationDescriptorsHS, - &qualifierDescriptor, - (USBConfigurationDescriptor *) &otherSpeedDescriptorsHS, -#else - 0, // No full-speed device qualifier descriptor - 0, // No full-speed other speed configuration - 0, // No high-speed device descriptor - 0, // No high-speed configuration descriptor - 0, // No high-speed device qualifier descriptor - 0, // No high-speed other speed configuration descriptor -#endif - stringDescriptors, - 4 // Four string descriptors in array -}; - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/device/massstorage/MSDDriverDescriptors.h" + +#include "../../../usb/common/core/USBStringDescriptor.h" +#include "../../../usb/common/massstorage/MSDeviceDescriptor.h" +#include "../../../usb/common/massstorage/MSInterfaceDescriptor.h" +#include "board_lowlevel.h" +#include "../../../usb/common/core/USBConfigurationDescriptor.h" +#include "../../../usb/common/core/USBDeviceDescriptor.h" +#include "../../../usb/common/core/USBEndpointDescriptor.h" +#include "../../../usb/common/core/USBGenericDescriptor.h" +#include "../../../usb/common/core/USBInterfaceDescriptor.h" + +//------------------------------------------------------------------------------ +// Internal definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Device Descriptor IDs" +/// ... +/// !IDs +/// - MSDDriverDescriptors_VENDORID +/// - MSDDriverDescriptors_PRODUCTID +/// - MSDDriverDescriptors_RELEASE + +/// Vendor ID for the Mass Storage device driver. +#define MSDDriverDescriptors_VENDORID 0x03EB +/// Product ID for the Mass Storage device driver. +#define MSDDriverDescriptors_PRODUCTID 0x6129 +/// Device release number for the Mass Storage device driver. +#define MSDDriverDescriptors_RELEASE 0x0100 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Macros +//------------------------------------------------------------------------------ + +/// Returns the minimum between two values. +#define MIN(a, b) ((a < b) ? a : b) + +//------------------------------------------------------------------------------ +// Internal types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// List of configuration descriptors used by a Mass Storage device driver. +//------------------------------------------------------------------------------ +typedef struct { + + /// Standard configuration descriptor. + USBConfigurationDescriptor configuration; +#if defined(CHIP_USB_OTGHS) + // OTG descriptor + USBOtgDescriptor otgDescriptor; +#endif + /// Mass storage interface descriptor. + USBInterfaceDescriptor interface; + /// Bulk-out endpoint descriptor. + USBEndpointDescriptor bulkOut; + /// Bulk-in endpoint descriptor. + USBEndpointDescriptor bulkIn; + +} __attribute__ ((packed)) MSDConfigurationDescriptors; + +//------------------------------------------------------------------------------ +// Local variables +//------------------------------------------------------------------------------ + +/// Mass storage driver device descriptor. +static const USBDeviceDescriptor deviceDescriptor = { + + sizeof(USBDeviceDescriptor), + USBGenericDescriptor_DEVICE, + USBDeviceDescriptor_USB2_00, + MSDeviceDescriptor_CLASS, + MSDeviceDescriptor_SUBCLASS, + MSDeviceDescriptor_PROTOCOL, + CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), + MSDDriverDescriptors_VENDORID, + MSDDriverDescriptors_PRODUCTID, + MSDDriverDescriptors_RELEASE, + 1, // Manufacturer string descriptor index. + 2, // Product string descriptor index. + 3, // Serial number string descriptor index. + 1 // Device has one possible configuration. +}; + +#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) +/// Device qualifier descriptor. +static const USBDeviceQualifierDescriptor qualifierDescriptor = { + + sizeof(USBDeviceQualifierDescriptor), + USBGenericDescriptor_DEVICEQUALIFIER, + USBDeviceDescriptor_USB2_00, + MSDeviceDescriptor_CLASS, + MSDeviceDescriptor_SUBCLASS, + MSDeviceDescriptor_PROTOCOL, + CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), + 1, // Device has one possible configuration. + 0x00 +}; +#endif + +/// Full-speed configuration descriptor. +static const MSDConfigurationDescriptors configurationDescriptorsFS = { + + // Standard configuration descriptor. + { + sizeof(USBConfigurationDescriptor), + USBGenericDescriptor_CONFIGURATION, + sizeof(MSDConfigurationDescriptors), + 1, // Configuration has one interface. + 1, // This is configuration #1. + 0, // No string descriptor for configuration. + BOARD_USB_BMATTRIBUTES, + USBConfigurationDescriptor_POWER(100) + }, +#if defined(CHIP_USB_OTGHS) + // OTG descriptor + { + sizeof(USBOtgDescriptor), + USBGenericDescriptor_OTG, + USBOTGDescriptor_HNP_SRP + }, +#endif + // Mass Storage interface descriptor. + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 0, // This is interface #0. + 0, // This is alternate setting #0. + 2, // Interface uses two endpoints. + MSInterfaceDescriptor_CLASS, + MSInterfaceDescriptor_SCSI, + MSInterfaceDescriptor_BULKONLY, + 0 // No string descriptor for interface. + }, + // Bulk-OUT endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_OUT, + MSDDriverDescriptors_BULKOUT), + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 // Must be 0 for full-speed Bulk endpoints. + }, + // Bulk-IN endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_IN, + MSDDriverDescriptors_BULKIN), + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 // Must be 0 for full-speed Bulk endpoints. + } +}; + +#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) +/// Full-speed other speed configuration descriptor. +static const MSDConfigurationDescriptors otherSpeedDescriptorsFS = { + + // Standard configuration descriptor. + { + sizeof(USBConfigurationDescriptor), + USBGenericDescriptor_OTHERSPEEDCONFIGURATION, + sizeof(MSDConfigurationDescriptors), + 1, // Configuration has one interface. + 1, // This is configuration #1. + 0, // No string descriptor for configuration. + BOARD_USB_BMATTRIBUTES, + USBConfigurationDescriptor_POWER(100) + }, +#if defined(CHIP_USB_OTGHS) + // OTG descriptor + { + sizeof(USBOtgDescriptor), + USBGenericDescriptor_OTG, + USBOTGDescriptor_HNP_SRP + }, +#endif + // Mass Storage interface descriptor. + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 0, // This is interface #0. + 0, // This is alternate setting #0. + 2, // Interface uses two endpoints. + MSInterfaceDescriptor_CLASS, + MSInterfaceDescriptor_SCSI, + MSInterfaceDescriptor_BULKONLY, + 0 // No string descriptor for interface. + }, + // Bulk-OUT endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_OUT, + MSDDriverDescriptors_BULKOUT), + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), + USBEndpointDescriptor_MAXBULKSIZE_HS), + 0 // No string descriptor for endpoint. + }, + // Bulk-IN endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_IN, + MSDDriverDescriptors_BULKIN), + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), + USBEndpointDescriptor_MAXBULKSIZE_HS), + 0 // No string descriptor for endpoint. + } +}; + +/// High-speed configuration descriptor. +static const MSDConfigurationDescriptors configurationDescriptorsHS = { + + // Standard configuration descriptor. + { + sizeof(USBConfigurationDescriptor), + USBGenericDescriptor_CONFIGURATION, + sizeof(MSDConfigurationDescriptors), + 1, // Configuration has one interface. + 1, // This is configuration #1. + 0, // No string descriptor for configuration. + BOARD_USB_BMATTRIBUTES, + USBConfigurationDescriptor_POWER(100) + }, +#if defined(CHIP_USB_OTGHS) + // OTG descriptor + { + sizeof(USBOtgDescriptor), + USBGenericDescriptor_OTG, + USBOTGDescriptor_HNP_SRP + }, +#endif + // Mass Storage interface descriptor. + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 0, // This is interface #0. + 0, // This is alternate setting #0. + 2, // Interface uses two endpoints. + MSInterfaceDescriptor_CLASS, + MSInterfaceDescriptor_SCSI, + MSInterfaceDescriptor_BULKONLY, + 0 // No string descriptor for interface. + }, + // Bulk-OUT endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_OUT, + MSDDriverDescriptors_BULKOUT), + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), + USBEndpointDescriptor_MAXBULKSIZE_HS), + 0 // No string descriptor for endpoint. + }, + // Bulk-IN endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_IN, + MSDDriverDescriptors_BULKIN), + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), + USBEndpointDescriptor_MAXBULKSIZE_HS), + 0 // No string descriptor for endpoint. + } +}; + +/// High-speed other speed configuration descriptor. +static const MSDConfigurationDescriptors otherSpeedDescriptorsHS = { + + // Standard configuration descriptor. + { + sizeof(USBConfigurationDescriptor), + USBGenericDescriptor_OTHERSPEEDCONFIGURATION, + sizeof(MSDConfigurationDescriptors), + 1, // Configuration has one interface. + 1, // This is configuration #1. + 0, // No string descriptor for configuration. + BOARD_USB_BMATTRIBUTES, + USBConfigurationDescriptor_POWER(100) + }, +#if defined(CHIP_USB_OTGHS) + // OTG descriptor + { + sizeof(USBOtgDescriptor), + USBGenericDescriptor_OTG, + USBOTGDescriptor_HNP_SRP + }, +#endif + // Mass Storage interface descriptor. + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 0, // This is interface #0. + 0, // This is alternate setting #0. + 2, // Interface uses two endpoints. + MSInterfaceDescriptor_CLASS, + MSInterfaceDescriptor_SCSI, + MSInterfaceDescriptor_BULKONLY, + 0 // No string descriptor for interface. + }, + // Bulk-OUT endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_OUT, + MSDDriverDescriptors_BULKOUT), + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 // No string descriptor for endpoint. + }, + // Bulk-IN endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_IN, + MSDDriverDescriptors_BULKIN), + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 // No string descriptor for endpoint. + } +}; +#endif + +/// Language ID string descriptor. +static const unsigned char languageIdDescriptor[] = { + + USBStringDescriptor_LENGTH(1), + USBGenericDescriptor_STRING, + USBStringDescriptor_ENGLISH_US +}; + +/// Manufacturer string descriptor. +static const unsigned char manufacturerDescriptor[] = { + + USBStringDescriptor_LENGTH(7), + USBGenericDescriptor_STRING, + USBStringDescriptor_UNICODE('9'), + USBStringDescriptor_UNICODE('X'), + USBStringDescriptor_UNICODE(' '), + USBStringDescriptor_UNICODE('T'), + USBStringDescriptor_UNICODE('E'), + USBStringDescriptor_UNICODE('A'), + USBStringDescriptor_UNICODE('M'), +}; + +/// Product string descriptor. +static const unsigned char productDescriptor[] = { + + USBStringDescriptor_LENGTH(5), + USBGenericDescriptor_STRING, + USBStringDescriptor_UNICODE('S'), + USBStringDescriptor_UNICODE('K'), + USBStringDescriptor_UNICODE('Y'), + USBStringDescriptor_UNICODE('9'), + USBStringDescriptor_UNICODE('X'), +}; + +/// Serial number string descriptor. The serial number must be at least 12 +/// characters long and made up of only letters & numbers to be compliant with +/// the MSD specification. +static const unsigned char serialNumberDescriptor[] = { + + USBStringDescriptor_LENGTH(12), + USBGenericDescriptor_STRING, + USBStringDescriptor_UNICODE('0'), + USBStringDescriptor_UNICODE('1'), + USBStringDescriptor_UNICODE('2'), + USBStringDescriptor_UNICODE('3'), + USBStringDescriptor_UNICODE('4'), + USBStringDescriptor_UNICODE('5'), + USBStringDescriptor_UNICODE('6'), + USBStringDescriptor_UNICODE('7'), + USBStringDescriptor_UNICODE('8'), + USBStringDescriptor_UNICODE('9'), + USBStringDescriptor_UNICODE('A'), + USBStringDescriptor_UNICODE('B') +}; + +/// List of all string descriptors used. +static const unsigned char *stringDescriptors[] = { + + languageIdDescriptor, + manufacturerDescriptor, + productDescriptor, + serialNumberDescriptor +}; + +//------------------------------------------------------------------------------ +// Global variables +//------------------------------------------------------------------------------ + +/// List of the standard descriptors used by the Mass Storage driver. +const USBDDriverDescriptors msdDriverDescriptors = { + + &deviceDescriptor, + (USBConfigurationDescriptor *) &configurationDescriptorsFS, +#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) + &qualifierDescriptor, + (USBConfigurationDescriptor *) &otherSpeedDescriptorsFS, + &deviceDescriptor, + (USBConfigurationDescriptor *) &configurationDescriptorsHS, + &qualifierDescriptor, + (USBConfigurationDescriptor *) &otherSpeedDescriptorsHS, +#else + 0, // No full-speed device qualifier descriptor + 0, // No full-speed other speed configuration + 0, // No high-speed device descriptor + 0, // No high-speed configuration descriptor + 0, // No high-speed device qualifier descriptor + 0, // No high-speed other speed configuration descriptor +#endif + stringDescriptors, + 4 // Four string descriptors in array +}; + diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.h b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.h index b2e5e295b..11480a900 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.h +++ b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.h @@ -1,83 +1,83 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definitions of the descriptors required by a Mass Storage device driver. -/// -/// !Usage -/// -/// - For a USB %device: -/// -# When initializing a USBDDriver instance, use msdDriverDescriptors as -/// the list of standard descriptors. -//------------------------------------------------------------------------------ - -#ifndef MSDDRIVERDESCRIPTORS_H -#define MSDDRIVERDESCRIPTORS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/device/core/USBDDriverDescriptors.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD endpoint addresses" -/// This page lists the addresses used by the Mass Storage driver %endpoints. -/// -/// !Addresses -/// -/// - MSDDriverDescriptors_BULKOUT -/// - MSDDriverDescriptors_BULKIN - -/// Address of the Mass Storage bulk-out endpoint. -#define MSDDriverDescriptors_BULKOUT 1 - -/// Address of the Mass Storage bulk-in endpoint. -#if defined(at91sam9m10) - #define MSDDriverDescriptors_BULKIN 6 -#else - #define MSDDriverDescriptors_BULKIN 2 -#endif -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported variables -//------------------------------------------------------------------------------ - -extern const USBDDriverDescriptors msdDriverDescriptors; - -#endif //#ifndef MSDDRIVERDESCRIPTORS_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Definitions of the descriptors required by a Mass Storage device driver. +/// +/// !Usage +/// +/// - For a USB %device: +/// -# When initializing a USBDDriver instance, use msdDriverDescriptors as +/// the list of standard descriptors. +//------------------------------------------------------------------------------ + +#ifndef MSDDRIVERDESCRIPTORS_H +#define MSDDRIVERDESCRIPTORS_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/device/core/USBDDriverDescriptors.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD endpoint addresses" +/// This page lists the addresses used by the Mass Storage driver %endpoints. +/// +/// !Addresses +/// +/// - MSDDriverDescriptors_BULKOUT +/// - MSDDriverDescriptors_BULKIN + +/// Address of the Mass Storage bulk-out endpoint. +#define MSDDriverDescriptors_BULKOUT 1 + +/// Address of the Mass Storage bulk-in endpoint. +#if defined(at91sam9m10) + #define MSDDriverDescriptors_BULKIN 6 +#else + #define MSDDriverDescriptors_BULKIN 2 +#endif +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported variables +//------------------------------------------------------------------------------ + +extern const USBDDriverDescriptors msdDriverDescriptors; + +#endif //#ifndef MSDDRIVERDESCRIPTORS_H + diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDIOFifo.h b/radio/src/targets/sky9x/usb/device/massstorage/MSDIOFifo.h index 2a5f060c6..5f7b7fba5 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDIOFifo.h +++ b/radio/src/targets/sky9x/usb/device/massstorage/MSDIOFifo.h @@ -1,135 +1,135 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _MSDIOFIFO_H -#define _MSDIOFIFO_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -/// Idle state, do nothing -#define MSDIO_IDLE 0 -/// Start, to start IO operation -#define MSDIO_START 1 -/// Wait, waiting for IO operation done -#define MSDIO_WAIT 2 -/// Next, to check if the next block can be performed -#define MSDIO_NEXT 3 -/// Pause, to pause the process for buffer full or null -#define MSDIO_PAUSE 4 -/// Abort, to abort the process -#define MSDIO_ABORT 5 -/// Done, finish without error -#define MSDIO_DONE 6 -/// Error, any error happens -#define MSDIO_ERROR 7 - -/// FIFO offset before USB transmit start -//#define MSDIO_FIFO_OFFSET (4*512) - -/// FIFO trunk size (in each transfer, large amount of data) -#if !defined(MSD_OP_BUFFER) -#define MSDIO_READ10_CHUNK_SIZE (4*512) -#define MSDIO_WRITE10_CHUNK_SIZE (4*512) -#endif - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -/// FIFO buffer for READ/WRITE (disk) operation of a mass storage device -typedef struct _MSDIOFifo { - - /// Pointer to the ring buffer allocated for read/write - unsigned char * pBuffer; - /// The size of the buffer allocated - unsigned int bufferSize; -#ifdef MSDIO_FIFO_OFFSET - /// The offset to start USB transfer (READ10) - unsigned int bufferOffset; -#endif - /// The index of input data (loaded to fifo buffer) - unsigned int inputNdx; - /// The total size of the loaded data - unsigned int inputTotal; - /// The index of output data (sent from the fifo buffer) - unsigned int outputNdx; - /// The total size of the output data - unsigned int outputTotal; - - /// The total size of the data - unsigned int dataTotal; - /// The size of the block in bytes - unsigned short blockSize; -#if defined(MSDIO_READ10_CHUNK_SIZE) || defined(MSDIO_WRITE10_CHUNK_SIZE) - /// The size of one chunk - /// (1 block, or several blocks for large amount data R/W) - unsigned int chunkSize; -#endif - /// State of input & output - unsigned char inputState; - unsigned char outputState; - - //- Statistics - /// Times when fifo has no data to send - unsigned short nullCnt; - /// Times when fifo can not load more input data - unsigned short fullCnt; -} MSDIOFifo, *PMSDIOFifo; - -//------------------------------------------------------------------------------ -// MACROS -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Increase the index, by defined block size, in the ring buffer -/// \param ndx The index to be increased -/// \param sectSize The defined block size -/// \param bufSize The ring buffer size -//------------------------------------------------------------------------------ -#define MSDIOFifo_IncNdx(ndx, sectSize, bufSize) \ - if ((ndx) >= (bufSize) - (sectSize)) (ndx) = 0; \ - else (ndx) += (sectSize) - - -//------------------------------------------------------------------------------ -// Exported Functions -//------------------------------------------------------------------------------ - - -extern void MSDIOFifo_Init(MSDIOFifo *pFifo, - void * pBuffer, unsigned short bufferSize); - -#endif // _MSDIOFIFO_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _MSDIOFIFO_H +#define _MSDIOFIFO_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +/// Idle state, do nothing +#define MSDIO_IDLE 0 +/// Start, to start IO operation +#define MSDIO_START 1 +/// Wait, waiting for IO operation done +#define MSDIO_WAIT 2 +/// Next, to check if the next block can be performed +#define MSDIO_NEXT 3 +/// Pause, to pause the process for buffer full or null +#define MSDIO_PAUSE 4 +/// Abort, to abort the process +#define MSDIO_ABORT 5 +/// Done, finish without error +#define MSDIO_DONE 6 +/// Error, any error happens +#define MSDIO_ERROR 7 + +/// FIFO offset before USB transmit start +//#define MSDIO_FIFO_OFFSET (4*512) + +/// FIFO trunk size (in each transfer, large amount of data) +#if !defined(MSD_OP_BUFFER) +#define MSDIO_READ10_CHUNK_SIZE (4*512) +#define MSDIO_WRITE10_CHUNK_SIZE (4*512) +#endif + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +/// FIFO buffer for READ/WRITE (disk) operation of a mass storage device +typedef struct _MSDIOFifo { + + /// Pointer to the ring buffer allocated for read/write + unsigned char * pBuffer; + /// The size of the buffer allocated + unsigned int bufferSize; +#ifdef MSDIO_FIFO_OFFSET + /// The offset to start USB transfer (READ10) + unsigned int bufferOffset; +#endif + /// The index of input data (loaded to fifo buffer) + unsigned int inputNdx; + /// The total size of the loaded data + unsigned int inputTotal; + /// The index of output data (sent from the fifo buffer) + unsigned int outputNdx; + /// The total size of the output data + unsigned int outputTotal; + + /// The total size of the data + unsigned int dataTotal; + /// The size of the block in bytes + unsigned short blockSize; +#if defined(MSDIO_READ10_CHUNK_SIZE) || defined(MSDIO_WRITE10_CHUNK_SIZE) + /// The size of one chunk + /// (1 block, or several blocks for large amount data R/W) + unsigned int chunkSize; +#endif + /// State of input & output + unsigned char inputState; + unsigned char outputState; + + //- Statistics + /// Times when fifo has no data to send + unsigned short nullCnt; + /// Times when fifo can not load more input data + unsigned short fullCnt; +} MSDIOFifo, *PMSDIOFifo; + +//------------------------------------------------------------------------------ +// MACROS +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Increase the index, by defined block size, in the ring buffer +/// \param ndx The index to be increased +/// \param sectSize The defined block size +/// \param bufSize The ring buffer size +//------------------------------------------------------------------------------ +#define MSDIOFifo_IncNdx(ndx, sectSize, bufSize) \ + if ((ndx) >= (bufSize) - (sectSize)) (ndx) = 0; \ + else (ndx) += (sectSize) + + +//------------------------------------------------------------------------------ +// Exported Functions +//------------------------------------------------------------------------------ + + +extern void MSDIOFifo_Init(MSDIOFifo *pFifo, + void * pBuffer, unsigned short bufferSize); + +#endif // _MSDIOFIFO_H + diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.c b/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.c index 3e8b3ba9e..d39f9cc3c 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.c +++ b/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.c @@ -1,367 +1,367 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - - -#include "../../../usb/device/massstorage/MSDLun.h" -#include "board_lowlevel.h" -#include "../../../usb/device/core/USBD.h" -#include "debug.h" - -//------------------------------------------------------------------------------ -// Constants -//------------------------------------------------------------------------------ - -/// Default LUN block size in bytes -#define DEFAULT_LUN_BLOCK_SIZE BLOCK_SIZE - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -/// Inquiry data to return to the host for the Lun. -static SBCInquiryData inquiryData = { - - SBC_DIRECT_ACCESS_BLOCK_DEVICE, // Direct-access block device - SBC_PERIPHERAL_DEVICE_CONNECTED,// Peripheral device is connected - 0x00, // Reserved bits - 0x01, // Media is removable - 0x02, // SBC_SPC_VERSION_4, // SPC-4 supported - 0x2, // Response data format, must be 0x2 - 0, // Hierarchical addressing not supported - 0, // ACA not supported - 0x0, // Obsolete bits - sizeof(SBCInquiryData) - 5, // Additional length - 0, // No embedded SCC - 0, // No access control coordinator - SBC_TPGS_NONE, // No target port support group - 0, // Third-party copy not supported - 0x0, // Reserved bits - 0, // Protection information not supported - 0x0, // Obsolete bit - 0, // No embedded enclosure service component - 0x0, // ??? - 0, // Device is not multi-port - 0x0, // Obsolete bits - 0x0, // Unused feature - 0x0, // Unused features - 0, // Task management model not supported - 0x0, // ??? - {'A','T','M','E','L',' ',' ',' '}, - {'M','a','s','s',' ', - 'S','t','o','r','a','g','e',' ', - 'M','S','D'}, - {'0','.','0','1'}, - {'M','a','s','s',' ', - 'S','t','o','r','a','g','e',' ', - 'E','x','a','m','p','l','e'}, - 0x00, // Unused features - 0x00, // Reserved bits - {SBC_VERSION_DESCRIPTOR_SBC_3}, // SBC-3 compliant device - {0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0} // Reserved -}; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -//! \brief Initializes a LUN instance. Must be invoked at least once even no -//! Media is linked. -//! \param lun Pointer to the MSDLun instance to initialize -//! \param media Media on which the LUN is constructed, set to 0 to -//! disconnect the Media or initialize an ejected LUN. -//! \param ioBuffer Pointer to a buffer used for read/write operation and -//! which must be blockSize bytes long. -//! \param ioBufferSize Size of the allocated IO buffer. -//! \param baseAddress Base address of the LUN in number of media blocks -//! \param size Total size of the LUN in number of media blocks -//! \param blockSize One block of the LUN in number of media blocks -//! \param protected The LUN area is forced to readonly even the media -//! is writable -//! \param dataMonitor Pointer to a Monitor Function to analyze the flow of -//! this LUN. -//------------------------------------------------------------------------------ -void LUN_Init(MSDLun *lun, - Media *media, - unsigned char *ioBuffer, - unsigned int ioBufferSize, - unsigned int baseAddress, - unsigned int size, - unsigned short blockSize, - unsigned char protected, - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount)) -{ - unsigned int logicalBlockAddress; - TRACE_INFO("LUN init\n\r"); - - // Initialize inquiry data - lun->inquiryData = &inquiryData; - - // Initialize request sense data - lun->requestSenseData.bResponseCode = SBC_SENSE_DATA_FIXED_CURRENT; - lun->requestSenseData.isValid = 1; - lun->requestSenseData.bObsolete1 = 0; - lun->requestSenseData.bSenseKey = SBC_SENSE_KEY_NO_SENSE; - lun->requestSenseData.bReserved1 = 0; - lun->requestSenseData.isILI = 0; - lun->requestSenseData.isEOM = 0; - lun->requestSenseData.isFilemark = 0; - lun->requestSenseData.pInformation[0] = 0; - lun->requestSenseData.pInformation[1] = 0; - lun->requestSenseData.pInformation[2] = 0; - lun->requestSenseData.pInformation[3] = 0; - lun->requestSenseData.bAdditionalSenseLength - = sizeof(SBCRequestSenseData) - 8; - lun->requestSenseData.bAdditionalSenseCode = 0; - lun->requestSenseData.bAdditionalSenseCodeQualifier = 0; - lun->requestSenseData.bFieldReplaceableUnitCode = 0; - lun->requestSenseData.bSenseKeySpecific = 0; - lun->requestSenseData.pSenseKeySpecific[0] = 0; - lun->requestSenseData.pSenseKeySpecific[0] = 0; - lun->requestSenseData.isSKSV = 0; - - STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockAddress); - STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockLength); - - // Initialize LUN - lun->media = media; - if (media == 0) { - lun->status = LUN_NOT_PRESENT; - return; - } - - lun->baseAddress = baseAddress; - - // Customized block size - if (blockSize) { - lun->blockSize = blockSize; - } - else { - if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) - lun->blockSize = DEFAULT_LUN_BLOCK_SIZE / media->blockSize; - else - lun->blockSize = 1; - } - - if (size) { - lun->size = size; - } - else { - lun->size = media->size; - //if (blockSize) - // lun->size = media->size / blockSize; - //else { - // if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) - // lun->size = media->size / lun->blockSize; - // else - // lun->size = media->size; - //} - } - - TRACE_INFO("LUN: blkSize %d, size %d\n\r", (int)lun->blockSize, (int)lun->size); - if (protected) lun->protected = 1; - else lun->protected = media->protected; - - lun->ioFifo.pBuffer = ioBuffer; - lun->ioFifo.bufferSize = ioBufferSize; - - lun->dataMonitor = dataMonitor; - - // Initialize read capacity data - logicalBlockAddress = lun->size / lun->blockSize - 1; - STORE_DWORDB(logicalBlockAddress, - lun->readCapacityData.pLogicalBlockAddress); - STORE_DWORDB(lun->blockSize * media->blockSize, - lun->readCapacityData.pLogicalBlockLength); - - // Indicate media change - lun->status = LUN_CHANGED; -} - -//------------------------------------------------------------------------------ -//! \brief Eject the media from a LUN -//! \param lun Pointer to the MSDLun instance to initialize -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Eject(MSDLun *lun) -{ - if (lun->media) { - - // Avoid any LUN R/W in progress - if (lun->media->state == MED_STATE_BUSY) { - - return USBD_STATUS_LOCKED; - } - - // Remove the link of the media - lun->media = 0; - } - // LUN is removed - lun->status = LUN_NOT_PRESENT; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -//! \brief Writes data on the a LUN starting at the specified block address. -//! \param lun Pointer to a MSDLun instance -//! \param blockAddress First block address to write -//! \param data Pointer to the data to write -//! \param length Number of blocks to write -//! \param callback Optional callback to invoke when the write finishes -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Write(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument) -{ - unsigned int medBlk, medLen; - unsigned char status; - - TRACE_INFO_WP("LUNWrite(%u) ", blockAddress); - - // Check that the data is not too big - if ((length + blockAddress) * lun->blockSize > lun->size) { - - TRACE_WARNING("LUN_Write: Data too big\n\r"); - status = USBD_STATUS_ABORTED; - } - else if (lun->media == 0 || lun->status != LUN_READY) { - - TRACE_WARNING("LUN_Write: Media not ready\n\r"); - status = USBD_STATUS_ABORTED; - } - else if (lun->protected) { - TRACE_WARNING("LUN_Write: LUN is readonly\n\r"); - status = USBD_STATUS_ABORTED; - } - else { - - // Compute write start address - medBlk = lun->baseAddress + blockAddress * lun->blockSize; - medLen = length * lun->blockSize; - - // Start write operation - status = MED_Write(lun->media, - medBlk, - data, - medLen, - (MediaCallback) callback, - argument); - - // Check operation result code - if (status == MED_STATUS_SUCCESS) { - - status = USBD_STATUS_SUCCESS; - } - else { - - TRACE_WARNING("LUN_Write: Cannot write media\n\r"); - status = USBD_STATUS_ABORTED; - } - } - - return status; -} - -//------------------------------------------------------------------------------ -//! \brief Reads data from a LUN, starting at the specified block address. -//! \param lun Pointer to a MSDLun instance -//! \param blockAddress First block address to read -//! \param data Pointer to a data buffer in which to store the data -//! \param length Number of blocks to read -//! \param callback Optional callback to invoke when the read finishes -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Read(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument) -{ - unsigned int medBlk, medLen; - unsigned char status; - - // Check that the data is not too big - if ((length + blockAddress) * lun->blockSize > lun->size) { - - TRACE_WARNING("LUN_Read: Area: (%d + %d)*%d > %d\n\r", - (int)length, (int)blockAddress, (int)lun->blockSize, (int)lun->size); - status = USBD_STATUS_ABORTED; - } - else if (lun->media == 0 || lun->status != LUN_READY) { - - TRACE_WARNING("LUN_Read: Media not present\n\r"); - status = USBD_STATUS_ABORTED; - } - else { - - TRACE_INFO_WP("LUNRead(%u) ", blockAddress); - - // Compute read start address - medBlk = lun->baseAddress + (blockAddress * lun->blockSize); - medLen = length * lun->blockSize; - - // Start write operation - status = MED_Read(lun->media, - medBlk, - data, - medLen, - (MediaCallback) callback, - argument); - - // Check result code - if (status == MED_STATUS_SUCCESS) { - - status = USBD_STATUS_SUCCESS; - } - else { - - TRACE_WARNING("LUN_Read: Cannot read media\n\r"); - status = USBD_STATUS_ABORTED; - } - } - - return status; -} +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + + +#include "../../../usb/device/massstorage/MSDLun.h" +#include "board_lowlevel.h" +#include "../../../usb/device/core/USBD.h" +#include "debug.h" + +//------------------------------------------------------------------------------ +// Constants +//------------------------------------------------------------------------------ + +/// Default LUN block size in bytes +#define DEFAULT_LUN_BLOCK_SIZE BLOCK_SIZE + +//------------------------------------------------------------------------------ +// Internal variables +//------------------------------------------------------------------------------ + +/// Inquiry data to return to the host for the Lun. +static SBCInquiryData inquiryData = { + + SBC_DIRECT_ACCESS_BLOCK_DEVICE, // Direct-access block device + SBC_PERIPHERAL_DEVICE_CONNECTED,// Peripheral device is connected + 0x00, // Reserved bits + 0x01, // Media is removable + 0x02, // SBC_SPC_VERSION_4, // SPC-4 supported + 0x2, // Response data format, must be 0x2 + 0, // Hierarchical addressing not supported + 0, // ACA not supported + 0x0, // Obsolete bits + sizeof(SBCInquiryData) - 5, // Additional length + 0, // No embedded SCC + 0, // No access control coordinator + SBC_TPGS_NONE, // No target port support group + 0, // Third-party copy not supported + 0x0, // Reserved bits + 0, // Protection information not supported + 0x0, // Obsolete bit + 0, // No embedded enclosure service component + 0x0, // ??? + 0, // Device is not multi-port + 0x0, // Obsolete bits + 0x0, // Unused feature + 0x0, // Unused features + 0, // Task management model not supported + 0x0, // ??? + {'A','T','M','E','L',' ',' ',' '}, + {'M','a','s','s',' ', + 'S','t','o','r','a','g','e',' ', + 'M','S','D'}, + {'0','.','0','1'}, + {'M','a','s','s',' ', + 'S','t','o','r','a','g','e',' ', + 'E','x','a','m','p','l','e'}, + 0x00, // Unused features + 0x00, // Reserved bits + {SBC_VERSION_DESCRIPTOR_SBC_3}, // SBC-3 compliant device + {0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0} // Reserved +}; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +//! \brief Initializes a LUN instance. Must be invoked at least once even no +//! Media is linked. +//! \param lun Pointer to the MSDLun instance to initialize +//! \param media Media on which the LUN is constructed, set to 0 to +//! disconnect the Media or initialize an ejected LUN. +//! \param ioBuffer Pointer to a buffer used for read/write operation and +//! which must be blockSize bytes long. +//! \param ioBufferSize Size of the allocated IO buffer. +//! \param baseAddress Base address of the LUN in number of media blocks +//! \param size Total size of the LUN in number of media blocks +//! \param blockSize One block of the LUN in number of media blocks +//! \param protected The LUN area is forced to readonly even the media +//! is writable +//! \param dataMonitor Pointer to a Monitor Function to analyze the flow of +//! this LUN. +//------------------------------------------------------------------------------ +void LUN_Init(MSDLun *lun, + Media *media, + unsigned char *ioBuffer, + unsigned int ioBufferSize, + unsigned int baseAddress, + unsigned int size, + unsigned short blockSize, + unsigned char protected, + void (*dataMonitor)(unsigned char flowDirection, + unsigned int dataLength, + unsigned int fifoNullCount, + unsigned int fifoFullCount)) +{ + unsigned int logicalBlockAddress; + TRACE_INFO("LUN init\n\r"); + + // Initialize inquiry data + lun->inquiryData = &inquiryData; + + // Initialize request sense data + lun->requestSenseData.bResponseCode = SBC_SENSE_DATA_FIXED_CURRENT; + lun->requestSenseData.isValid = 1; + lun->requestSenseData.bObsolete1 = 0; + lun->requestSenseData.bSenseKey = SBC_SENSE_KEY_NO_SENSE; + lun->requestSenseData.bReserved1 = 0; + lun->requestSenseData.isILI = 0; + lun->requestSenseData.isEOM = 0; + lun->requestSenseData.isFilemark = 0; + lun->requestSenseData.pInformation[0] = 0; + lun->requestSenseData.pInformation[1] = 0; + lun->requestSenseData.pInformation[2] = 0; + lun->requestSenseData.pInformation[3] = 0; + lun->requestSenseData.bAdditionalSenseLength + = sizeof(SBCRequestSenseData) - 8; + lun->requestSenseData.bAdditionalSenseCode = 0; + lun->requestSenseData.bAdditionalSenseCodeQualifier = 0; + lun->requestSenseData.bFieldReplaceableUnitCode = 0; + lun->requestSenseData.bSenseKeySpecific = 0; + lun->requestSenseData.pSenseKeySpecific[0] = 0; + lun->requestSenseData.pSenseKeySpecific[0] = 0; + lun->requestSenseData.isSKSV = 0; + + STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockAddress); + STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockLength); + + // Initialize LUN + lun->media = media; + if (media == 0) { + lun->status = LUN_NOT_PRESENT; + return; + } + + lun->baseAddress = baseAddress; + + // Customized block size + if (blockSize) { + lun->blockSize = blockSize; + } + else { + if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) + lun->blockSize = DEFAULT_LUN_BLOCK_SIZE / media->blockSize; + else + lun->blockSize = 1; + } + + if (size) { + lun->size = size; + } + else { + lun->size = media->size; + //if (blockSize) + // lun->size = media->size / blockSize; + //else { + // if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) + // lun->size = media->size / lun->blockSize; + // else + // lun->size = media->size; + //} + } + + TRACE_INFO("LUN: blkSize %d, size %d\n\r", (int)lun->blockSize, (int)lun->size); + if (protected) lun->protected = 1; + else lun->protected = media->protected; + + lun->ioFifo.pBuffer = ioBuffer; + lun->ioFifo.bufferSize = ioBufferSize; + + lun->dataMonitor = dataMonitor; + + // Initialize read capacity data + logicalBlockAddress = lun->size / lun->blockSize - 1; + STORE_DWORDB(logicalBlockAddress, + lun->readCapacityData.pLogicalBlockAddress); + STORE_DWORDB(lun->blockSize * media->blockSize, + lun->readCapacityData.pLogicalBlockLength); + + // Indicate media change + lun->status = LUN_CHANGED; +} + +//------------------------------------------------------------------------------ +//! \brief Eject the media from a LUN +//! \param lun Pointer to the MSDLun instance to initialize +//! \return Operation result code +//------------------------------------------------------------------------------ +unsigned char LUN_Eject(MSDLun *lun) +{ + if (lun->media) { + + // Avoid any LUN R/W in progress + if (lun->media->state == MED_STATE_BUSY) { + + return USBD_STATUS_LOCKED; + } + + // Remove the link of the media + lun->media = 0; + } + // LUN is removed + lun->status = LUN_NOT_PRESENT; + + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +//! \brief Writes data on the a LUN starting at the specified block address. +//! \param lun Pointer to a MSDLun instance +//! \param blockAddress First block address to write +//! \param data Pointer to the data to write +//! \param length Number of blocks to write +//! \param callback Optional callback to invoke when the write finishes +//! \return Operation result code +//------------------------------------------------------------------------------ +unsigned char LUN_Write(MSDLun *lun, + unsigned int blockAddress, + void *data, + unsigned int length, + TransferCallback callback, + void *argument) +{ + unsigned int medBlk, medLen; + unsigned char status; + + TRACE_INFO_WP("LUNWrite(%u) ", blockAddress); + + // Check that the data is not too big + if ((length + blockAddress) * lun->blockSize > lun->size) { + + TRACE_WARNING("LUN_Write: Data too big\n\r"); + status = USBD_STATUS_ABORTED; + } + else if (lun->media == 0 || lun->status != LUN_READY) { + + TRACE_WARNING("LUN_Write: Media not ready\n\r"); + status = USBD_STATUS_ABORTED; + } + else if (lun->protected) { + TRACE_WARNING("LUN_Write: LUN is readonly\n\r"); + status = USBD_STATUS_ABORTED; + } + else { + + // Compute write start address + medBlk = lun->baseAddress + blockAddress * lun->blockSize; + medLen = length * lun->blockSize; + + // Start write operation + status = MED_Write(lun->media, + medBlk, + data, + medLen, + (MediaCallback) callback, + argument); + + // Check operation result code + if (status == MED_STATUS_SUCCESS) { + + status = USBD_STATUS_SUCCESS; + } + else { + + TRACE_WARNING("LUN_Write: Cannot write media\n\r"); + status = USBD_STATUS_ABORTED; + } + } + + return status; +} + +//------------------------------------------------------------------------------ +//! \brief Reads data from a LUN, starting at the specified block address. +//! \param lun Pointer to a MSDLun instance +//! \param blockAddress First block address to read +//! \param data Pointer to a data buffer in which to store the data +//! \param length Number of blocks to read +//! \param callback Optional callback to invoke when the read finishes +//! \return Operation result code +//------------------------------------------------------------------------------ +unsigned char LUN_Read(MSDLun *lun, + unsigned int blockAddress, + void *data, + unsigned int length, + TransferCallback callback, + void *argument) +{ + unsigned int medBlk, medLen; + unsigned char status; + + // Check that the data is not too big + if ((length + blockAddress) * lun->blockSize > lun->size) { + + TRACE_WARNING("LUN_Read: Area: (%d + %d)*%d > %d\n\r", + (int)length, (int)blockAddress, (int)lun->blockSize, (int)lun->size); + status = USBD_STATUS_ABORTED; + } + else if (lun->media == 0 || lun->status != LUN_READY) { + + TRACE_WARNING("LUN_Read: Media not present\n\r"); + status = USBD_STATUS_ABORTED; + } + else { + + TRACE_INFO_WP("LUNRead(%u) ", blockAddress); + + // Compute read start address + medBlk = lun->baseAddress + (blockAddress * lun->blockSize); + medLen = length * lun->blockSize; + + // Start write operation + status = MED_Read(lun->media, + medBlk, + data, + medLen, + (MediaCallback) callback, + argument); + + // Check result code + if (status == MED_STATUS_SUCCESS) { + + status = USBD_STATUS_SUCCESS; + } + else { + + TRACE_WARNING("LUN_Read: Cannot read media\n\r"); + status = USBD_STATUS_ABORTED; + } + } + + return status; +} diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.h b/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.h index 51584ea47..92c9120cc 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.h +++ b/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.h @@ -1,161 +1,161 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Logical Unit Number (LUN) used by the Mass Storage driver and the SCSI -/// protocol. Represents a logical hard-drive. -/// -/// !Usage -/// -# Initialize Memory related pins (see pio & board.h). -/// -# Initialize a Media instance for the LUN (see memories). -/// -# Initlalize the LUN with LUN_Init, and link to the initialized Media. -/// -# To read data from the LUN linked media, uses LUN_Read. -/// -# To write data to the LUN linked media, uses LUN_Write. -/// -# To unlink the media, uses LUN_Eject. -//------------------------------------------------------------------------------ - -#ifndef MSDLUN_H -#define MSDLUN_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../Media.h" -#include "../../../usb/device/core/USBD.h" -#include "../../../usb/device/massstorage/MSDIOFifo.h" -#include "../../../usb/device/massstorage/SBC.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -/// LUN RC: success -#define LUN_STATUS_SUCCESS 0x00 -/// LUN RC: error -#define LUN_STATUS_ERROR 0x02 - -/// Media of LUN is removed -#define LUN_NOT_PRESENT 0x00 -/// LUN is ejected by host -#define LUN_EJECTED 0x01 -/// Media of LUN is changed -#define LUN_CHANGED 0x10 -/// LUN Not Ready to Ready transition -#define LUN_TRANS_READY LUN_CHANGED -/// Media of LUN is ready -#define LUN_READY 0x11 - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -/// LUN structure -typedef struct { - - /// Pointer to a SBCInquiryData instance. - SBCInquiryData *inquiryData; - /// Fifo for USB transfer, must be assigned. - MSDIOFifo ioFifo; - /// Pointer to Media instance for the LUN. - Media *media; - /// Pointer to a Monitor Function to analyze the flow of LUN. - /// \param flowDirection 1 - device to host (READ10) - /// 0 - host to device (WRITE10) - /// \param dataLength Length of data transferred in bytes. - /// \param fifoNullCount Times that FIFO is NULL to wait - /// \param fifoFullCount Times that FIFO is filled to wait - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount); - /// The start position of the media (blocks) allocated to the LUN. - unsigned int baseAddress; - /// The size of the media (blocks) allocated to the LUN. - unsigned int size; - /// Sector size of the media in number of media blocks - unsigned short blockSize; - /// The LUN can be readonly even the media is writable -#ifdef __cplusplus - unsigned char protectd; -#else - unsigned char protected; -#endif - - /// The LUN status (Ejected/Changed/) - unsigned char status; - - /// Data for the RequestSense command. - SBCRequestSenseData requestSenseData; - /// Data for the ReadCapacity command. - SBCReadCapacity10Data readCapacityData; - -} MSDLun; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void LUN_Init(MSDLun *lun, - Media *media, - unsigned char *ioBuffer, - unsigned int ioBufferSize, - unsigned int baseAddress, - unsigned int size, - unsigned short blockSize, -#ifdef __cplusplus - unsigned char protectd, -#else - unsigned char protected, -#endif - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount)); - -extern unsigned char LUN_Eject(MSDLun *lun); - -extern unsigned char LUN_Write(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument); - -extern unsigned char LUN_Read(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument); - -#endif //#ifndef MSDLUN_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Logical Unit Number (LUN) used by the Mass Storage driver and the SCSI +/// protocol. Represents a logical hard-drive. +/// +/// !Usage +/// -# Initialize Memory related pins (see pio & board.h). +/// -# Initialize a Media instance for the LUN (see memories). +/// -# Initlalize the LUN with LUN_Init, and link to the initialized Media. +/// -# To read data from the LUN linked media, uses LUN_Read. +/// -# To write data to the LUN linked media, uses LUN_Write. +/// -# To unlink the media, uses LUN_Eject. +//------------------------------------------------------------------------------ + +#ifndef MSDLUN_H +#define MSDLUN_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../Media.h" +#include "../../../usb/device/core/USBD.h" +#include "../../../usb/device/massstorage/MSDIOFifo.h" +#include "../../../usb/device/massstorage/SBC.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +/// LUN RC: success +#define LUN_STATUS_SUCCESS 0x00 +/// LUN RC: error +#define LUN_STATUS_ERROR 0x02 + +/// Media of LUN is removed +#define LUN_NOT_PRESENT 0x00 +/// LUN is ejected by host +#define LUN_EJECTED 0x01 +/// Media of LUN is changed +#define LUN_CHANGED 0x10 +/// LUN Not Ready to Ready transition +#define LUN_TRANS_READY LUN_CHANGED +/// Media of LUN is ready +#define LUN_READY 0x11 + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ + +/// LUN structure +typedef struct { + + /// Pointer to a SBCInquiryData instance. + SBCInquiryData *inquiryData; + /// Fifo for USB transfer, must be assigned. + MSDIOFifo ioFifo; + /// Pointer to Media instance for the LUN. + Media *media; + /// Pointer to a Monitor Function to analyze the flow of LUN. + /// \param flowDirection 1 - device to host (READ10) + /// 0 - host to device (WRITE10) + /// \param dataLength Length of data transferred in bytes. + /// \param fifoNullCount Times that FIFO is NULL to wait + /// \param fifoFullCount Times that FIFO is filled to wait + void (*dataMonitor)(unsigned char flowDirection, + unsigned int dataLength, + unsigned int fifoNullCount, + unsigned int fifoFullCount); + /// The start position of the media (blocks) allocated to the LUN. + unsigned int baseAddress; + /// The size of the media (blocks) allocated to the LUN. + unsigned int size; + /// Sector size of the media in number of media blocks + unsigned short blockSize; + /// The LUN can be readonly even the media is writable +#ifdef __cplusplus + unsigned char protectd; +#else + unsigned char protected; +#endif + + /// The LUN status (Ejected/Changed/) + unsigned char status; + + /// Data for the RequestSense command. + SBCRequestSenseData requestSenseData; + /// Data for the ReadCapacity command. + SBCReadCapacity10Data readCapacityData; + +} MSDLun; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern void LUN_Init(MSDLun *lun, + Media *media, + unsigned char *ioBuffer, + unsigned int ioBufferSize, + unsigned int baseAddress, + unsigned int size, + unsigned short blockSize, +#ifdef __cplusplus + unsigned char protectd, +#else + unsigned char protected, +#endif + void (*dataMonitor)(unsigned char flowDirection, + unsigned int dataLength, + unsigned int fifoNullCount, + unsigned int fifoFullCount)); + +extern unsigned char LUN_Eject(MSDLun *lun); + +extern unsigned char LUN_Write(MSDLun *lun, + unsigned int blockAddress, + void *data, + unsigned int length, + TransferCallback callback, + void *argument); + +extern unsigned char LUN_Read(MSDLun *lun, + unsigned int blockAddress, + void *data, + unsigned int length, + TransferCallback callback, + void *argument); + +#endif //#ifndef MSDLUN_H + diff --git a/radio/src/targets/sky9x/usb/device/massstorage/SBC.h b/radio/src/targets/sky9x/usb/device/massstorage/SBC.h index 1aed2b5b9..a8b39820e 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/SBC.h +++ b/radio/src/targets/sky9x/usb/device/massstorage/SBC.h @@ -1,671 +1,671 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// SCSI definitions. -/// -/// !Usage -/// -/// -# After command block received, Access and decode the SCSI command block -/// with SBCCommand structure. -//------------------------------------------------------------------------------ - -#ifndef SBC_H -#define SBC_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Operation Codes" -/// This page lists operation codes of commands described in the SBC-3 -/// standard. -/// -/// \note That most commands are actually defined in other standards, -/// like SPC-4. Optional commands are not included here. -/// -/// \see sbc3r07.pdf - Section 5.1 - Table 12 -/// \see spc4r06.pdf -/// \see SBCCommand -/// -/// !Codes -/// - SBC_INQUIRY -/// - SBC_READ_10 -/// - SBC_READ_CAPACITY_10 -/// - SBC_REQUEST_SENSE -/// - SBC_TEST_UNIT_READY -/// - SBC_WRITE_10 -/// -/// !Optional Codes but required by Windows -/// - SBC_PREVENT_ALLOW_MEDIUM_REMOVAL -/// - SBC_MODE_SENSE_6 -/// - SBC_VERIFY_10 -/// - SBC_READ_FORMAT_CAPACITIES - -/// Request information regarding parameters of the target and Logical Unit. -#define SBC_INQUIRY 0x12 -/// Request the transfer data to the host. -#define SBC_READ_10 0x28 -/// Request capacities of the currently installed medium. -#define SBC_READ_CAPACITY_10 0x25 -/// Request that the device server transfer sense data. -#define SBC_REQUEST_SENSE 0x03 -/// Check if the LUN is ready -#define SBC_TEST_UNIT_READY 0x00 -/// Request that the device write the data transferred by the host. -#define SBC_WRITE_10 0x2A - -/// Request that the target enable or disable the removal of the medium in -/// the Logical Unit. -#define SBC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -/// Report parameters. -#define SBC_MODE_SENSE_6 0x1A -/// Request that the %device verify the data on the medium. -#define SBC_VERIFY_10 0x2F -/// Request a list of the possible capacities that can be formatted on medium -#define SBC_READ_FORMAT_CAPACITIES 0x23 - -#define SBC_START_STOP 0x19 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Periph. Qualifiers" -/// This page lists the peripheral qualifier values specified in the INQUIRY -/// data -/// \see spc4r06.pdf - Section 6.4.2 - Table 83 -/// \see SBCInquiryData -/// -/// !Qualifiers -/// - SBC_PERIPHERAL_DEVICE_CONNECTED -/// - SBC_PERIPHERAL_DEVICE_NOT_CONNECTED -/// - SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED - -#define SBC_PERIPHERAL_DEVICE_CONNECTED 0x00 -#define SBC_PERIPHERAL_DEVICE_NOT_CONNECTED 0x01 -#define SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED 0x03 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Periph. Types" -/// This page lists peripheral device types specified in the INQUIRY data -/// \see spc4r06.pdf - Section 6.4.2 - Table 84 -/// \see SBCInquiryData -/// -/// !Types -/// - SBC_DIRECT_ACCESS_BLOCK_DEVICE -/// - SBC_SEQUENTIAL_ACCESS_DEVICE -/// - SBC_PRINTER_DEVICE -/// - SBC_PROCESSOR_DEVICE -/// - SBC_WRITE_ONCE_DEVICE -/// - SBC_CD_DVD_DEVICE -/// - SBC_SCANNER_DEVICE -/// - SBC_OPTICAL_MEMORY_DEVICE -/// - SBC_MEDIA_CHANGER_DEVICE -/// - SBC_COMMUNICATION_DEVICE -/// - SBC_STORAGE_ARRAY_CONTROLLER_DEVICE -/// - SBC_ENCLOSURE_SERVICES_DEVICE -/// - SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE -/// - SBC_OPTICAL_CARD_READER_WRITER_DEVICE -/// - SBC_BRIDGE_CONTROLLER_COMMANDS -/// - SBC_OBJECT_BASED_STORAGE_DEVICE - -#define SBC_DIRECT_ACCESS_BLOCK_DEVICE 0x00 -#define SBC_SEQUENTIAL_ACCESS_DEVICE 0x01 -#define SBC_PRINTER_DEVICE 0x02 -#define SBC_PROCESSOR_DEVICE 0x03 -#define SBC_WRITE_ONCE_DEVICE 0x04 -#define SBC_CD_DVD_DEVICE 0x05 -#define SBC_SCANNER_DEVICE 0x06 -#define SBC_OPTICAL_MEMORY_DEVICE 0x07 -#define SBC_MEDIA_CHANGER_DEVICE 0x08 -#define SBC_COMMUNICATION_DEVICE 0x09 -#define SBC_STORAGE_ARRAY_CONTROLLER_DEVICE 0x0C -#define SBC_ENCLOSURE_SERVICES_DEVICE 0x0D -#define SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE 0x0E -#define SBC_OPTICAL_CARD_READER_WRITER_DEVICE 0x0F -#define SBC_BRIDGE_CONTROLLER_COMMANDS 0x10 -#define SBC_OBJECT_BASED_STORAGE_DEVICE 0x11 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Version value for the SBC-3 specification -/// \see spc4r06.pdf - Section 6.4.2 - Table 85 -#define SBC_SPC_VERSION_4 0x06 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Values for the TPGS field returned in INQUIRY data -/// \see spc4r06.pdf - Section 6.4.2 - Table 86 -#define SBC_TPGS_NONE 0x0 -#define SBC_TPGS_ASYMMETRIC 0x1 -#define SBC_TPGS_SYMMETRIC 0x2 -#define SBC_TPGS_BOTH 0x3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Version descriptor value for the SBC-3 specification -/// \see spc4r06.pdf - Section 6.4.2 - Table 87 -#define SBC_VERSION_DESCRIPTOR_SBC_3 0x04C0 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Response Codes" -/// This page lists sense data response codes returned in REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.1 - Table 12 -/// -/// !Codes -/// - SBC_SENSE_DATA_FIXED_CURRENT -/// - SBC_SENSE_DATA_FIXED_DEFERRED -/// - SBC_SENSE_DATA_DESCRIPTOR_CURRENT -/// - SBC_SENSE_DATA_DESCRIPTOR_DEFERRED - -#define SBC_SENSE_DATA_FIXED_CURRENT 0x70 -#define SBC_SENSE_DATA_FIXED_DEFERRED 0x71 -#define SBC_SENSE_DATA_DESCRIPTOR_CURRENT 0x72 -#define SBC_SENSE_DATA_DESCRIPTOR_DEFERRED 0x73 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Keys" -/// This page lists sense key values returned in the REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.6 - Table 27 -/// -/// !Keys -/// - SBC_SENSE_KEY_NO_SENSE -/// - SBC_SENSE_KEY_RECOVERED_ERROR -/// - SBC_SENSE_KEY_NOT_READY -/// - SBC_SENSE_KEY_MEDIUM_ERROR -/// - SBC_SENSE_KEY_HARDWARE_ERROR -/// - SBC_SENSE_KEY_ILLEGAL_REQUEST -/// - SBC_SENSE_KEY_UNIT_ATTENTION -/// - SBC_SENSE_KEY_DATA_PROTECT -/// - SBC_SENSE_KEY_BLANK_CHECK -/// - SBC_SENSE_KEY_VENDOR_SPECIFIC -/// - SBC_SENSE_KEY_COPY_ABORTED -/// - SBC_SENSE_KEY_ABORTED_COMMAND -/// - SBC_SENSE_KEY_VOLUME_OVERFLOW -/// - SBC_SENSE_KEY_MISCOMPARE - -/// No specific sense key. Successful command. -#define SBC_SENSE_KEY_NO_SENSE 0x00 -/// Command completed succesfully with some recovery action by the %device. -#define SBC_SENSE_KEY_RECOVERED_ERROR 0x01 -/// The device can not be accessed. -#define SBC_SENSE_KEY_NOT_READY 0x02 -/// Command terminated with a error condition that was probably caused by a -/// flaw in the medium or an error in the recorded data. -#define SBC_SENSE_KEY_MEDIUM_ERROR 0x03 -/// Hardware failure while performing the command or during a self test. -#define SBC_SENSE_KEY_HARDWARE_ERROR 0x04 -/// Illegal parameter found in the command or additional parameters. -#define SBC_SENSE_KEY_ILLEGAL_REQUEST 0x05 -/// Removable medium may have been changed or the %device has been reset. -#define SBC_SENSE_KEY_UNIT_ATTENTION 0x06 -/// Write on a block that is protected. -#define SBC_SENSE_KEY_DATA_PROTECT 0x07 -/// Indicates that a write-once device or a sequential-access device -/// encountered blank medium or format-defined end-of-data indication while -/// reading or a write-once device encountered a non-blank medium while writing. -#define SBC_SENSE_KEY_BLANK_CHECK 0x08 -/// Reporting vendor specific conditions. -#define SBC_SENSE_KEY_VENDOR_SPECIFIC 0x09 -/// EXTENDED COPY command was aborted. -#define SBC_SENSE_KEY_COPY_ABORTED 0x0A -/// Device aborted the command. -#define SBC_SENSE_KEY_ABORTED_COMMAND 0x0B -/// A buffered peripheral device is overflow. -#define SBC_SENSE_KEY_VOLUME_OVERFLOW 0x0D -/// The source data did not match the data read from the medium. -#define SBC_SENSE_KEY_MISCOMPARE 0x0E -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Additionals" -/// This page lists additional sense code values returned in REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.6 - Table 28 -/// -/// !Additional Codes -/// - SBC_ASC_LOGICAL_UNIT_NOT_READY -/// - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE -/// - SBC_ASC_INVALID_FIELD_IN_CDB -/// - SBC_ASC_WRITE_PROTECTED -/// - SBC_ASC_FORMAT_CORRUPTED -/// - SBC_ASC_INVALID_COMMAND_OPERATION_CODE -/// - SBC_ASC_TOO_MUCH_WRITE_DATA -/// - SBC_ASC_NOT_READY_TO_READY_CHANGE -/// - SBC_ASC_MEDIUM_NOT_PRESENT - -#define SBC_ASC_LOGICAL_UNIT_NOT_READY 0x04 -#define SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 -#define SBC_ASC_INVALID_FIELD_IN_CDB 0x24 -#define SBC_ASC_WRITE_PROTECTED 0x27 -#define SBC_ASC_FORMAT_CORRUPTED 0x31 -#define SBC_ASC_INVALID_COMMAND_OPERATION_CODE 0x20 -#define SBC_ASC_TOO_MUCH_WRITE_DATA 0x26 -#define SBC_ASC_NOT_READY_TO_READY_CHANGE 0x28 -#define SBC_ASC_MEDIUM_NOT_PRESENT 0x3A -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief MEDIUM TYPE field value for direct-access block devices -/// \see sbc3r06.pdf - Section 6.3.1 -#define SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE 0x00 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief MRIE field values -/// \see sbc3r06.pdf - Section 7.4.11 - Table 286 -#define SBC_MRIE_NO_REPORTING 0x00 -#define SBC_MRIE_ASYNCHRONOUS 0x01 -#define SBC_MRIE_GENERATE_UNIT_ATTENTION 0x02 -#define SBC_MRIE_COND_GENERATE_RECOVERED_ERROR 0x03 -#define SBC_MRIE_UNCOND_GENERATE_RECOVERED_ERROR 0x04 -#define SBC_MRIE_GENERATE_NO_SENSE 0x05 -#define SBC_MRIE_ON_REQUEST 0x06 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Supported mode pages -/// \see sbc3r06.pdf - Section 6.3.1 - Table 115 -#define SBC_PAGE_READ_WRITE_ERROR_RECOVERY 0x01 -#define SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL 0x1C -#define SBC_PAGE_RETURN_ALL 0x3F -#define SBC_PAGE_VENDOR_SPECIFIC 0x00 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Endian Macros" -/// This page lists the macros for endianness conversion. -/// -/// !Macros -/// - WORDB -/// - DWORDB -/// - STORE_DWORDB -/// - STORE_WORDB -/// \brief Converts a byte array to a word value using the big endian format -#define WORDB(bytes) ((unsigned short) ((bytes[0] << 8) | bytes[1])) - -/// \brief Converts a byte array to a dword value using the big endian format -#define DWORDB(bytes) ((unsigned int) ((bytes[0] << 24) | (bytes[1] << 16) \ - | (bytes[2] << 8) | bytes[3])) - -/// \brief Stores a dword value in a byte array, in big endian format -#define STORE_DWORDB(dword, bytes) \ - bytes[0] = (unsigned char) (((dword) >> 24) & 0xFF); \ - bytes[1] = (unsigned char) (((dword) >> 16) & 0xFF); \ - bytes[2] = (unsigned char) (((dword) >> 8) & 0xFF); \ - bytes[3] = (unsigned char) ((dword) & 0xFF); - -/// \brief Stores a word value in a byte array, in big endian format -#define STORE_WORDB(word, bytes) \ - bytes[0] = (unsigned char) (((word) >> 8) & 0xFF); \ - bytes[1] = (unsigned char) ((word) & 0xFF); -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// \brief Structure for the INQUIRY command -/// \see spc4r06.pdf - Section 6.4.1 - Table 81 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x12 : SBC_INQUIRY - unsigned char isEVPD:1, //!< Type of requested data - bReserved1:7; //!< Reserved bits - unsigned char bPageCode; //!< Specifies the VPD to return - unsigned char pAllocationLength[2]; //!< Size of host buffer - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCInquiry; // GCC - -//------------------------------------------------------------------------------ -/// \brief Standard INQUIRY data format returned by the device -/// \see spc4r06.pdf - Section 6.4.2 - Table 82 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPeripheralDeviceType:5, //!< Peripheral device type - bPeripheralQualifier :3; //!< Peripheral qualifier - unsigned char bReserved1:7, //!< Reserved bits - isRMB :1; //!< Is media removable ? - unsigned char bVersion; //!< SPC version used - unsigned char bResponseDataFormat:4, //!< Must be 0x2 - isHIGHSUP :1, //!< Hierarchical addressing used ? - isNORMACA :1, //!< ACA attribute supported ? - bObsolete1 :2; //!< Obsolete bits - unsigned char bAdditionalLength; //!< Length of remaining INQUIRY data - unsigned char isSCCS :1, //!< Embedded SCC ? - isACC :1, //!< Access control coordinator ? - bTPGS :2, //!< Target port support group - is3PC :1, //!< Third-party copy supported ? - bReserved2:2, //!< Reserved bits - isProtect :1; //!< Protection info supported ? - unsigned char bObsolete2:1, //!< Obsolete bit - isEncServ :1, //!< Embedded enclosure service comp? - isVS :1, //!< ??? - isMultiP :1, //!< Multi-port device ? - bObsolete3:3, //!< Obsolete bits - bUnused1 :1; //!< Unused feature - unsigned char bUnused2:6, //!< Unused features - isCmdQue:1, //!< Task management model supported ? - isVS2 :1; //!< ??? - unsigned char pVendorID[8]; //!< T10 vendor identification - unsigned char pProductID[16]; //!< Vendor-defined product ID - unsigned char pProductRevisionLevel[4];//!< Vendor-defined product revision - unsigned char pVendorSpecific[20]; //!< Vendor-specific data - unsigned char bUnused3; //!< Unused features - unsigned char bReserved3; //!< Reserved bits - unsigned short pVersionDescriptors[8]; //!< Standards the device complies to - unsigned char pReserved4[22]; //!< Reserved bytes - -} __attribute__ ((packed)) SBCInquiryData; // GCC - -//------------------------------------------------------------------------------ -/// \brief Data structure for the READ (10) command -/// \see sbc3r07.pdf - Section 5.7 - Table 34 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x28 : SBC_READ_10 - unsigned char bObsolete1:1, //!< Obsolete bit - isFUA_NV:1, //!< Cache control bit - bReserved1:1, //!< Reserved bit - isFUA:1, //!< Cache control bit - isDPO:1, //!< Cache control bit - bRdProtect:3; //!< Protection information to send - unsigned char pLogicalBlockAddress[4]; //!< Index of first block to read - unsigned char bGroupNumber:5, //!< Information grouping - bReserved2:3; //!< Reserved bits - unsigned char pTransferLength[2]; //!< Number of blocks to transmit - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCRead10; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the READ CAPACITY (10) command -/// \see sbc3r07.pdf - Section 5.11.1 - Table 40 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x25 : RBC_READ_CAPACITY - unsigned char bObsolete1:1, //!< Obsolete bit - bReserved1:7; //!< Reserved bits - unsigned char pLogicalBlockAddress[4]; //!< Block to evaluate if PMI is set - unsigned char pReserved2[2]; //!< Reserved bytes - unsigned char isPMI:1, //!< Partial medium indicator bit - bReserved3:7; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCReadCapacity10; - -//------------------------------------------------------------------------------ -/// \brief Data returned by the device after a READ CAPACITY (10) command -/// \see sbc3r07.pdf - Section 5.11.2 - Table 41 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char pLogicalBlockAddress[4]; //!< Address of last logical block - unsigned char pLogicalBlockLength[4]; //!< Length of each logical block - -} __attribute__ ((packed)) SBCReadCapacity10Data; - -//------------------------------------------------------------------------------ -/// \brief Structure for the REQUEST SENSE command -/// \see spc4r06.pdf - Section 6.26 - Table 170 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x03 : SBC_REQUEST_SENSE - unsigned char isDesc :1, //!< Type of information expected - bReserved1:7; //!< Reserved bits - unsigned char pReserved2[2]; //!< Reserved bytes - unsigned char bAllocationLength; //!< Size of host buffer - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCRequestSense; - -//------------------------------------------------------------------------------ -/// \brief Fixed format sense data returned after a REQUEST SENSE command has -/// been received with a DESC bit cleared. -/// \see spc4r06.pdf - Section 4.5.3 - Table 26 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bResponseCode:7, //!< Sense data format - isValid :1; //!< Information field is standard - unsigned char bObsolete1; //!< Obsolete byte - unsigned char bSenseKey :4, //!< Generic error information - bReserved1:1, //!< Reserved bit - isILI :1, //!< SSC - isEOM :1, //!< SSC - isFilemark:1; //!< SSC - unsigned char pInformation[4]; //!< Command-specific - unsigned char bAdditionalSenseLength; //!< sizeof(SBCRequestSense_data)-8 - unsigned char pCommandSpecificInformation[4]; //!< Command-specific - unsigned char bAdditionalSenseCode; //!< Additional error information - unsigned char bAdditionalSenseCodeQualifier; //!< Further error information - unsigned char bFieldReplaceableUnitCode; //!< Specific component code - unsigned char bSenseKeySpecific:7, //!< Additional exception info - isSKSV :1; //!< Is sense key specific valid? - unsigned char pSenseKeySpecific[2]; //!< Additional exception info - -} __attribute__ ((packed)) SBCRequestSenseData; - -//------------------------------------------------------------------------------ -/// \brief Data structure for the TEST UNIT READY command -/// \see spc4r06.pdf - Section 6.34 - Table 192 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x00 : SBC_TEST_UNIT_READY - unsigned char pReserved1[4]; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCTestUnitReady; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the WRITE (10) command -/// \see sbc3r07.pdf - Section 5.26 - Table 70 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x2A : SBC_WRITE_10 - unsigned char bObsolete1:1, //!< Obsolete bit - isFUA_NV:1, //!< Cache control bit - bReserved1:1, //!< Reserved bit - isFUA:1, //!< Cache control bit - isDPO:1, //!< Cache control bit - bWrProtect:3; //!< Protection information to send - unsigned char pLogicalBlockAddress[4]; //!< First block to write - unsigned char bGroupNumber:5, //!< Information grouping - bReserved2:3; //!< Reserved bits - unsigned char pTransferLength[2]; //!< Number of blocks to write - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCWrite10; - -//------------------------------------------------------------------------------ -/// \brief Structure for the PREVENT/ALLOW MEDIUM REMOVAL command -/// \see sbc3r07.pdf - Section 5.5 - Table 30 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x1E : SBC_PREVENT_ALLOW_MEDIUM_REMOVAL - unsigned char pReserved1[3]; //!< Reserved bytes - unsigned char bPrevent:2, //!< Accept/prohibit removal - bReserved2:6; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCMediumRemoval; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the MODE SENSE (6) command -/// \see spc4r06 - Section 6.9.1 - Table 98 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x1A : SBC_MODE_SENSE_6 - unsigned char bReserved1:3, //!< Reserved bits - isDBD:1, //!< Disable block descriptors bit - bReserved2:4; //!< Reserved bits - unsigned char bPageCode:6, //!< Mode page to return - bPC:2; //!< Type of parameter values to return - unsigned char bSubpageCode; //!< Mode subpage to return - unsigned char bAllocationLength; //!< Host buffer allocated size - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCModeSense6; // GCC - -//------------------------------------------------------------------------------ -/// \brief Header for the data returned after a MODE SENSE (6) command -/// \see spc4r06.pdf - Section 7.4.3 - Table 268 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bModeDataLength; //!< Length of mode data to follow - unsigned char bMediumType; //!< Type of medium (SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE) - unsigned char bReserved1:4, //!< Reserved bits - isDPOFUA:1, //!< DPO/FUA bits supported ? - bReserved2:2, //!< Reserved bits - isWP:1; //!< Is medium write-protected ? - unsigned char bBlockDescriptorLength; //!< Length of all block descriptors - -} __attribute__ ((packed)) SBCModeParameterHeader6; // GCC - -//------------------------------------------------------------------------------ -/// \brief Informational exceptions control mode page -/// \see spc4r06.pdf - Section 7.4.11 - Table 285 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPageCode:6, //!< 0x1C : SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL - isSPF:1, //!< Page or subpage data format - isPS:1; //!< Parameters saveable ? - unsigned char bPageLength; //!< Length of page data (0x0A) - unsigned char isLogErr:1, //!< Should informational exceptions be logged ? - isEBackErr:1, //!< Enable background error bit - isTest:1, //!< Create a device test failure ? - isDExcpt:1, //!< Disable exception control bit - isEWasc:1, //!< Report warnings ? - isEBF:1, //!< Enable background function bit - bReserved1:1, //!< Reserved bit - isPerf:1; //!< Delay acceptable when treating exceptions ? - unsigned char bMRIE:4, //!< Method of reporting informational exceptions - bReserved2:4; //!< Reserved bits - unsigned char pIntervalTimer[4]; //!< Error reporting period - unsigned char pReportCount[4]; //!< Maximum number of time a report can be issued - -} __attribute__ ((packed)) SBCInformationalExceptionsControl; // GCC - -//------------------------------------------------------------------------------ -/// \brief Read/write error recovery mode page -/// \see sbc3r07.pdf - Section 6.3.5 - Table 122 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPageCode:6, //!< 0x01 : SBC_PAGE_READ_WRITE_ERROR_RECOVERY - isSPF:1, //!< Page or subpage data format - isPS:1; //!< Parameters saveable ? - unsigned char bPageLength; //!< Length of page data (0x0A) - unsigned char isDCR:1, //!< Disable correction bit - isDTE:1, //!< Data terminate on error bit - isPER:1, //!< Post error bit - isEER:1, //!< Enable early recovery bit - isRC:1, //!< Read continuous bit - isTB:1, //!< Transfer block bit - isARRE:1, //!< Automatic read reallocation enabled bit - isAWRE:1; //!< Automatic write reallocation enabled bit - unsigned char bReadRetryCount; //!< Number of retries when reading - unsigned char pObsolete1[3]; //!< Obsolete bytes - unsigned char bReserved1; //!< Reserved byte - unsigned char bWriteRetryCount; //!< Number of retries when writing - unsigned char bReserved2; //!< Reserved byte - unsigned char pRecoveryTimeLimit[2]; //!< Maximum time duration for error recovery - -} __attribute__ ((packed)) SBCReadWriteErrorRecovery; // GCC - -//------------------------------------------------------------------------------ -/// \brief start/stop command -/// \see -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bModeDataLength; //!< Length of mode data to follow - unsigned char bImmediate:1, //!< - bReserved1:7; //!< Reserved bits - unsigned char pReserved[2]; //!< Reserved bytes - unsigned char startStop:1, //!< DPO/FUA bits supported ? - eject:1, //!< Reserved bits - bReserved2:6; //!< Is medium write-protected ? -} __attribute__ ((packed)) SBCStartStop; // GCC - -//------------------------------------------------------------------------------ -/// \brief Generic structure for holding information about SBC commands -/// \see SBCInquiry -/// \see SBCRead10 -/// \see SBCReadCapacity10 -/// \see SBCRequestSense -/// \see SBCTestUnitReady -/// \see SBCWrite10 -/// \see SBCMediumRemoval -/// \see SBCModeSense6 -//------------------------------------------------------------------------------ -typedef union { - - unsigned char bOperationCode; //!< Operation code of the command - SBCInquiry inquiry; //!< INQUIRY command - SBCRead10 read10; //!< READ (10) command - SBCReadCapacity10 readCapacity10; //!< READ CAPACITY (10) command - SBCRequestSense requestSense; //!< REQUEST SENSE command - SBCTestUnitReady testUnitReady; //!< TEST UNIT READY command - SBCWrite10 write10; //!< WRITE (10) command - SBCMediumRemoval mediumRemoval; //!< PREVENT/ALLOW MEDIUM REMOVAL command - SBCModeSense6 modeSense6; //!< MODE SENSE (6) command - SBCStartStop startStopCmd; //!< START-STOP command - -} SBCCommand; - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef SBC_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// SCSI definitions. +/// +/// !Usage +/// +/// -# After command block received, Access and decode the SCSI command block +/// with SBCCommand structure. +//------------------------------------------------------------------------------ + +#ifndef SBC_H +#define SBC_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Operation Codes" +/// This page lists operation codes of commands described in the SBC-3 +/// standard. +/// +/// \note That most commands are actually defined in other standards, +/// like SPC-4. Optional commands are not included here. +/// +/// \see sbc3r07.pdf - Section 5.1 - Table 12 +/// \see spc4r06.pdf +/// \see SBCCommand +/// +/// !Codes +/// - SBC_INQUIRY +/// - SBC_READ_10 +/// - SBC_READ_CAPACITY_10 +/// - SBC_REQUEST_SENSE +/// - SBC_TEST_UNIT_READY +/// - SBC_WRITE_10 +/// +/// !Optional Codes but required by Windows +/// - SBC_PREVENT_ALLOW_MEDIUM_REMOVAL +/// - SBC_MODE_SENSE_6 +/// - SBC_VERIFY_10 +/// - SBC_READ_FORMAT_CAPACITIES + +/// Request information regarding parameters of the target and Logical Unit. +#define SBC_INQUIRY 0x12 +/// Request the transfer data to the host. +#define SBC_READ_10 0x28 +/// Request capacities of the currently installed medium. +#define SBC_READ_CAPACITY_10 0x25 +/// Request that the device server transfer sense data. +#define SBC_REQUEST_SENSE 0x03 +/// Check if the LUN is ready +#define SBC_TEST_UNIT_READY 0x00 +/// Request that the device write the data transferred by the host. +#define SBC_WRITE_10 0x2A + +/// Request that the target enable or disable the removal of the medium in +/// the Logical Unit. +#define SBC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E +/// Report parameters. +#define SBC_MODE_SENSE_6 0x1A +/// Request that the %device verify the data on the medium. +#define SBC_VERIFY_10 0x2F +/// Request a list of the possible capacities that can be formatted on medium +#define SBC_READ_FORMAT_CAPACITIES 0x23 + +#define SBC_START_STOP 0x19 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Periph. Qualifiers" +/// This page lists the peripheral qualifier values specified in the INQUIRY +/// data +/// \see spc4r06.pdf - Section 6.4.2 - Table 83 +/// \see SBCInquiryData +/// +/// !Qualifiers +/// - SBC_PERIPHERAL_DEVICE_CONNECTED +/// - SBC_PERIPHERAL_DEVICE_NOT_CONNECTED +/// - SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED + +#define SBC_PERIPHERAL_DEVICE_CONNECTED 0x00 +#define SBC_PERIPHERAL_DEVICE_NOT_CONNECTED 0x01 +#define SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED 0x03 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Periph. Types" +/// This page lists peripheral device types specified in the INQUIRY data +/// \see spc4r06.pdf - Section 6.4.2 - Table 84 +/// \see SBCInquiryData +/// +/// !Types +/// - SBC_DIRECT_ACCESS_BLOCK_DEVICE +/// - SBC_SEQUENTIAL_ACCESS_DEVICE +/// - SBC_PRINTER_DEVICE +/// - SBC_PROCESSOR_DEVICE +/// - SBC_WRITE_ONCE_DEVICE +/// - SBC_CD_DVD_DEVICE +/// - SBC_SCANNER_DEVICE +/// - SBC_OPTICAL_MEMORY_DEVICE +/// - SBC_MEDIA_CHANGER_DEVICE +/// - SBC_COMMUNICATION_DEVICE +/// - SBC_STORAGE_ARRAY_CONTROLLER_DEVICE +/// - SBC_ENCLOSURE_SERVICES_DEVICE +/// - SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE +/// - SBC_OPTICAL_CARD_READER_WRITER_DEVICE +/// - SBC_BRIDGE_CONTROLLER_COMMANDS +/// - SBC_OBJECT_BASED_STORAGE_DEVICE + +#define SBC_DIRECT_ACCESS_BLOCK_DEVICE 0x00 +#define SBC_SEQUENTIAL_ACCESS_DEVICE 0x01 +#define SBC_PRINTER_DEVICE 0x02 +#define SBC_PROCESSOR_DEVICE 0x03 +#define SBC_WRITE_ONCE_DEVICE 0x04 +#define SBC_CD_DVD_DEVICE 0x05 +#define SBC_SCANNER_DEVICE 0x06 +#define SBC_OPTICAL_MEMORY_DEVICE 0x07 +#define SBC_MEDIA_CHANGER_DEVICE 0x08 +#define SBC_COMMUNICATION_DEVICE 0x09 +#define SBC_STORAGE_ARRAY_CONTROLLER_DEVICE 0x0C +#define SBC_ENCLOSURE_SERVICES_DEVICE 0x0D +#define SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE 0x0E +#define SBC_OPTICAL_CARD_READER_WRITER_DEVICE 0x0F +#define SBC_BRIDGE_CONTROLLER_COMMANDS 0x10 +#define SBC_OBJECT_BASED_STORAGE_DEVICE 0x11 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Version value for the SBC-3 specification +/// \see spc4r06.pdf - Section 6.4.2 - Table 85 +#define SBC_SPC_VERSION_4 0x06 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Values for the TPGS field returned in INQUIRY data +/// \see spc4r06.pdf - Section 6.4.2 - Table 86 +#define SBC_TPGS_NONE 0x0 +#define SBC_TPGS_ASYMMETRIC 0x1 +#define SBC_TPGS_SYMMETRIC 0x2 +#define SBC_TPGS_BOTH 0x3 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Version descriptor value for the SBC-3 specification +/// \see spc4r06.pdf - Section 6.4.2 - Table 87 +#define SBC_VERSION_DESCRIPTOR_SBC_3 0x04C0 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Sense Response Codes" +/// This page lists sense data response codes returned in REQUEST SENSE data +/// \see spc4r06.pdf - Section 4.5.1 - Table 12 +/// +/// !Codes +/// - SBC_SENSE_DATA_FIXED_CURRENT +/// - SBC_SENSE_DATA_FIXED_DEFERRED +/// - SBC_SENSE_DATA_DESCRIPTOR_CURRENT +/// - SBC_SENSE_DATA_DESCRIPTOR_DEFERRED + +#define SBC_SENSE_DATA_FIXED_CURRENT 0x70 +#define SBC_SENSE_DATA_FIXED_DEFERRED 0x71 +#define SBC_SENSE_DATA_DESCRIPTOR_CURRENT 0x72 +#define SBC_SENSE_DATA_DESCRIPTOR_DEFERRED 0x73 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Sense Keys" +/// This page lists sense key values returned in the REQUEST SENSE data +/// \see spc4r06.pdf - Section 4.5.6 - Table 27 +/// +/// !Keys +/// - SBC_SENSE_KEY_NO_SENSE +/// - SBC_SENSE_KEY_RECOVERED_ERROR +/// - SBC_SENSE_KEY_NOT_READY +/// - SBC_SENSE_KEY_MEDIUM_ERROR +/// - SBC_SENSE_KEY_HARDWARE_ERROR +/// - SBC_SENSE_KEY_ILLEGAL_REQUEST +/// - SBC_SENSE_KEY_UNIT_ATTENTION +/// - SBC_SENSE_KEY_DATA_PROTECT +/// - SBC_SENSE_KEY_BLANK_CHECK +/// - SBC_SENSE_KEY_VENDOR_SPECIFIC +/// - SBC_SENSE_KEY_COPY_ABORTED +/// - SBC_SENSE_KEY_ABORTED_COMMAND +/// - SBC_SENSE_KEY_VOLUME_OVERFLOW +/// - SBC_SENSE_KEY_MISCOMPARE + +/// No specific sense key. Successful command. +#define SBC_SENSE_KEY_NO_SENSE 0x00 +/// Command completed succesfully with some recovery action by the %device. +#define SBC_SENSE_KEY_RECOVERED_ERROR 0x01 +/// The device can not be accessed. +#define SBC_SENSE_KEY_NOT_READY 0x02 +/// Command terminated with a error condition that was probably caused by a +/// flaw in the medium or an error in the recorded data. +#define SBC_SENSE_KEY_MEDIUM_ERROR 0x03 +/// Hardware failure while performing the command or during a self test. +#define SBC_SENSE_KEY_HARDWARE_ERROR 0x04 +/// Illegal parameter found in the command or additional parameters. +#define SBC_SENSE_KEY_ILLEGAL_REQUEST 0x05 +/// Removable medium may have been changed or the %device has been reset. +#define SBC_SENSE_KEY_UNIT_ATTENTION 0x06 +/// Write on a block that is protected. +#define SBC_SENSE_KEY_DATA_PROTECT 0x07 +/// Indicates that a write-once device or a sequential-access device +/// encountered blank medium or format-defined end-of-data indication while +/// reading or a write-once device encountered a non-blank medium while writing. +#define SBC_SENSE_KEY_BLANK_CHECK 0x08 +/// Reporting vendor specific conditions. +#define SBC_SENSE_KEY_VENDOR_SPECIFIC 0x09 +/// EXTENDED COPY command was aborted. +#define SBC_SENSE_KEY_COPY_ABORTED 0x0A +/// Device aborted the command. +#define SBC_SENSE_KEY_ABORTED_COMMAND 0x0B +/// A buffered peripheral device is overflow. +#define SBC_SENSE_KEY_VOLUME_OVERFLOW 0x0D +/// The source data did not match the data read from the medium. +#define SBC_SENSE_KEY_MISCOMPARE 0x0E +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Sense Additionals" +/// This page lists additional sense code values returned in REQUEST SENSE data +/// \see spc4r06.pdf - Section 4.5.6 - Table 28 +/// +/// !Additional Codes +/// - SBC_ASC_LOGICAL_UNIT_NOT_READY +/// - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE +/// - SBC_ASC_INVALID_FIELD_IN_CDB +/// - SBC_ASC_WRITE_PROTECTED +/// - SBC_ASC_FORMAT_CORRUPTED +/// - SBC_ASC_INVALID_COMMAND_OPERATION_CODE +/// - SBC_ASC_TOO_MUCH_WRITE_DATA +/// - SBC_ASC_NOT_READY_TO_READY_CHANGE +/// - SBC_ASC_MEDIUM_NOT_PRESENT + +#define SBC_ASC_LOGICAL_UNIT_NOT_READY 0x04 +#define SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 +#define SBC_ASC_INVALID_FIELD_IN_CDB 0x24 +#define SBC_ASC_WRITE_PROTECTED 0x27 +#define SBC_ASC_FORMAT_CORRUPTED 0x31 +#define SBC_ASC_INVALID_COMMAND_OPERATION_CODE 0x20 +#define SBC_ASC_TOO_MUCH_WRITE_DATA 0x26 +#define SBC_ASC_NOT_READY_TO_READY_CHANGE 0x28 +#define SBC_ASC_MEDIUM_NOT_PRESENT 0x3A +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief MEDIUM TYPE field value for direct-access block devices +/// \see sbc3r06.pdf - Section 6.3.1 +#define SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE 0x00 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief MRIE field values +/// \see sbc3r06.pdf - Section 7.4.11 - Table 286 +#define SBC_MRIE_NO_REPORTING 0x00 +#define SBC_MRIE_ASYNCHRONOUS 0x01 +#define SBC_MRIE_GENERATE_UNIT_ATTENTION 0x02 +#define SBC_MRIE_COND_GENERATE_RECOVERED_ERROR 0x03 +#define SBC_MRIE_UNCOND_GENERATE_RECOVERED_ERROR 0x04 +#define SBC_MRIE_GENERATE_NO_SENSE 0x05 +#define SBC_MRIE_ON_REQUEST 0x06 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Supported mode pages +/// \see sbc3r06.pdf - Section 6.3.1 - Table 115 +#define SBC_PAGE_READ_WRITE_ERROR_RECOVERY 0x01 +#define SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL 0x1C +#define SBC_PAGE_RETURN_ALL 0x3F +#define SBC_PAGE_VENDOR_SPECIFIC 0x00 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Endian Macros" +/// This page lists the macros for endianness conversion. +/// +/// !Macros +/// - WORDB +/// - DWORDB +/// - STORE_DWORDB +/// - STORE_WORDB +/// \brief Converts a byte array to a word value using the big endian format +#define WORDB(bytes) ((unsigned short) ((bytes[0] << 8) | bytes[1])) + +/// \brief Converts a byte array to a dword value using the big endian format +#define DWORDB(bytes) ((unsigned int) ((bytes[0] << 24) | (bytes[1] << 16) \ + | (bytes[2] << 8) | bytes[3])) + +/// \brief Stores a dword value in a byte array, in big endian format +#define STORE_DWORDB(dword, bytes) \ + bytes[0] = (unsigned char) (((dword) >> 24) & 0xFF); \ + bytes[1] = (unsigned char) (((dword) >> 16) & 0xFF); \ + bytes[2] = (unsigned char) (((dword) >> 8) & 0xFF); \ + bytes[3] = (unsigned char) ((dword) & 0xFF); + +/// \brief Stores a word value in a byte array, in big endian format +#define STORE_WORDB(word, bytes) \ + bytes[0] = (unsigned char) (((word) >> 8) & 0xFF); \ + bytes[1] = (unsigned char) ((word) & 0xFF); +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// \brief Structure for the INQUIRY command +/// \see spc4r06.pdf - Section 6.4.1 - Table 81 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x12 : SBC_INQUIRY + unsigned char isEVPD:1, //!< Type of requested data + bReserved1:7; //!< Reserved bits + unsigned char bPageCode; //!< Specifies the VPD to return + unsigned char pAllocationLength[2]; //!< Size of host buffer + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCInquiry; // GCC + +//------------------------------------------------------------------------------ +/// \brief Standard INQUIRY data format returned by the device +/// \see spc4r06.pdf - Section 6.4.2 - Table 82 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bPeripheralDeviceType:5, //!< Peripheral device type + bPeripheralQualifier :3; //!< Peripheral qualifier + unsigned char bReserved1:7, //!< Reserved bits + isRMB :1; //!< Is media removable ? + unsigned char bVersion; //!< SPC version used + unsigned char bResponseDataFormat:4, //!< Must be 0x2 + isHIGHSUP :1, //!< Hierarchical addressing used ? + isNORMACA :1, //!< ACA attribute supported ? + bObsolete1 :2; //!< Obsolete bits + unsigned char bAdditionalLength; //!< Length of remaining INQUIRY data + unsigned char isSCCS :1, //!< Embedded SCC ? + isACC :1, //!< Access control coordinator ? + bTPGS :2, //!< Target port support group + is3PC :1, //!< Third-party copy supported ? + bReserved2:2, //!< Reserved bits + isProtect :1; //!< Protection info supported ? + unsigned char bObsolete2:1, //!< Obsolete bit + isEncServ :1, //!< Embedded enclosure service comp? + isVS :1, //!< ??? + isMultiP :1, //!< Multi-port device ? + bObsolete3:3, //!< Obsolete bits + bUnused1 :1; //!< Unused feature + unsigned char bUnused2:6, //!< Unused features + isCmdQue:1, //!< Task management model supported ? + isVS2 :1; //!< ??? + unsigned char pVendorID[8]; //!< T10 vendor identification + unsigned char pProductID[16]; //!< Vendor-defined product ID + unsigned char pProductRevisionLevel[4];//!< Vendor-defined product revision + unsigned char pVendorSpecific[20]; //!< Vendor-specific data + unsigned char bUnused3; //!< Unused features + unsigned char bReserved3; //!< Reserved bits + unsigned short pVersionDescriptors[8]; //!< Standards the device complies to + unsigned char pReserved4[22]; //!< Reserved bytes + +} __attribute__ ((packed)) SBCInquiryData; // GCC + +//------------------------------------------------------------------------------ +/// \brief Data structure for the READ (10) command +/// \see sbc3r07.pdf - Section 5.7 - Table 34 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x28 : SBC_READ_10 + unsigned char bObsolete1:1, //!< Obsolete bit + isFUA_NV:1, //!< Cache control bit + bReserved1:1, //!< Reserved bit + isFUA:1, //!< Cache control bit + isDPO:1, //!< Cache control bit + bRdProtect:3; //!< Protection information to send + unsigned char pLogicalBlockAddress[4]; //!< Index of first block to read + unsigned char bGroupNumber:5, //!< Information grouping + bReserved2:3; //!< Reserved bits + unsigned char pTransferLength[2]; //!< Number of blocks to transmit + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCRead10; // GCC + +//------------------------------------------------------------------------------ +/// \brief Structure for the READ CAPACITY (10) command +/// \see sbc3r07.pdf - Section 5.11.1 - Table 40 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x25 : RBC_READ_CAPACITY + unsigned char bObsolete1:1, //!< Obsolete bit + bReserved1:7; //!< Reserved bits + unsigned char pLogicalBlockAddress[4]; //!< Block to evaluate if PMI is set + unsigned char pReserved2[2]; //!< Reserved bytes + unsigned char isPMI:1, //!< Partial medium indicator bit + bReserved3:7; //!< Reserved bits + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCReadCapacity10; + +//------------------------------------------------------------------------------ +/// \brief Data returned by the device after a READ CAPACITY (10) command +/// \see sbc3r07.pdf - Section 5.11.2 - Table 41 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char pLogicalBlockAddress[4]; //!< Address of last logical block + unsigned char pLogicalBlockLength[4]; //!< Length of each logical block + +} __attribute__ ((packed)) SBCReadCapacity10Data; + +//------------------------------------------------------------------------------ +/// \brief Structure for the REQUEST SENSE command +/// \see spc4r06.pdf - Section 6.26 - Table 170 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x03 : SBC_REQUEST_SENSE + unsigned char isDesc :1, //!< Type of information expected + bReserved1:7; //!< Reserved bits + unsigned char pReserved2[2]; //!< Reserved bytes + unsigned char bAllocationLength; //!< Size of host buffer + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCRequestSense; + +//------------------------------------------------------------------------------ +/// \brief Fixed format sense data returned after a REQUEST SENSE command has +/// been received with a DESC bit cleared. +/// \see spc4r06.pdf - Section 4.5.3 - Table 26 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bResponseCode:7, //!< Sense data format + isValid :1; //!< Information field is standard + unsigned char bObsolete1; //!< Obsolete byte + unsigned char bSenseKey :4, //!< Generic error information + bReserved1:1, //!< Reserved bit + isILI :1, //!< SSC + isEOM :1, //!< SSC + isFilemark:1; //!< SSC + unsigned char pInformation[4]; //!< Command-specific + unsigned char bAdditionalSenseLength; //!< sizeof(SBCRequestSense_data)-8 + unsigned char pCommandSpecificInformation[4]; //!< Command-specific + unsigned char bAdditionalSenseCode; //!< Additional error information + unsigned char bAdditionalSenseCodeQualifier; //!< Further error information + unsigned char bFieldReplaceableUnitCode; //!< Specific component code + unsigned char bSenseKeySpecific:7, //!< Additional exception info + isSKSV :1; //!< Is sense key specific valid? + unsigned char pSenseKeySpecific[2]; //!< Additional exception info + +} __attribute__ ((packed)) SBCRequestSenseData; + +//------------------------------------------------------------------------------ +/// \brief Data structure for the TEST UNIT READY command +/// \see spc4r06.pdf - Section 6.34 - Table 192 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x00 : SBC_TEST_UNIT_READY + unsigned char pReserved1[4]; //!< Reserved bits + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCTestUnitReady; // GCC + +//------------------------------------------------------------------------------ +/// \brief Structure for the WRITE (10) command +/// \see sbc3r07.pdf - Section 5.26 - Table 70 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x2A : SBC_WRITE_10 + unsigned char bObsolete1:1, //!< Obsolete bit + isFUA_NV:1, //!< Cache control bit + bReserved1:1, //!< Reserved bit + isFUA:1, //!< Cache control bit + isDPO:1, //!< Cache control bit + bWrProtect:3; //!< Protection information to send + unsigned char pLogicalBlockAddress[4]; //!< First block to write + unsigned char bGroupNumber:5, //!< Information grouping + bReserved2:3; //!< Reserved bits + unsigned char pTransferLength[2]; //!< Number of blocks to write + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCWrite10; + +//------------------------------------------------------------------------------ +/// \brief Structure for the PREVENT/ALLOW MEDIUM REMOVAL command +/// \see sbc3r07.pdf - Section 5.5 - Table 30 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x1E : SBC_PREVENT_ALLOW_MEDIUM_REMOVAL + unsigned char pReserved1[3]; //!< Reserved bytes + unsigned char bPrevent:2, //!< Accept/prohibit removal + bReserved2:6; //!< Reserved bits + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCMediumRemoval; // GCC + +//------------------------------------------------------------------------------ +/// \brief Structure for the MODE SENSE (6) command +/// \see spc4r06 - Section 6.9.1 - Table 98 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x1A : SBC_MODE_SENSE_6 + unsigned char bReserved1:3, //!< Reserved bits + isDBD:1, //!< Disable block descriptors bit + bReserved2:4; //!< Reserved bits + unsigned char bPageCode:6, //!< Mode page to return + bPC:2; //!< Type of parameter values to return + unsigned char bSubpageCode; //!< Mode subpage to return + unsigned char bAllocationLength; //!< Host buffer allocated size + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCModeSense6; // GCC + +//------------------------------------------------------------------------------ +/// \brief Header for the data returned after a MODE SENSE (6) command +/// \see spc4r06.pdf - Section 7.4.3 - Table 268 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bModeDataLength; //!< Length of mode data to follow + unsigned char bMediumType; //!< Type of medium (SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE) + unsigned char bReserved1:4, //!< Reserved bits + isDPOFUA:1, //!< DPO/FUA bits supported ? + bReserved2:2, //!< Reserved bits + isWP:1; //!< Is medium write-protected ? + unsigned char bBlockDescriptorLength; //!< Length of all block descriptors + +} __attribute__ ((packed)) SBCModeParameterHeader6; // GCC + +//------------------------------------------------------------------------------ +/// \brief Informational exceptions control mode page +/// \see spc4r06.pdf - Section 7.4.11 - Table 285 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bPageCode:6, //!< 0x1C : SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL + isSPF:1, //!< Page or subpage data format + isPS:1; //!< Parameters saveable ? + unsigned char bPageLength; //!< Length of page data (0x0A) + unsigned char isLogErr:1, //!< Should informational exceptions be logged ? + isEBackErr:1, //!< Enable background error bit + isTest:1, //!< Create a device test failure ? + isDExcpt:1, //!< Disable exception control bit + isEWasc:1, //!< Report warnings ? + isEBF:1, //!< Enable background function bit + bReserved1:1, //!< Reserved bit + isPerf:1; //!< Delay acceptable when treating exceptions ? + unsigned char bMRIE:4, //!< Method of reporting informational exceptions + bReserved2:4; //!< Reserved bits + unsigned char pIntervalTimer[4]; //!< Error reporting period + unsigned char pReportCount[4]; //!< Maximum number of time a report can be issued + +} __attribute__ ((packed)) SBCInformationalExceptionsControl; // GCC + +//------------------------------------------------------------------------------ +/// \brief Read/write error recovery mode page +/// \see sbc3r07.pdf - Section 6.3.5 - Table 122 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bPageCode:6, //!< 0x01 : SBC_PAGE_READ_WRITE_ERROR_RECOVERY + isSPF:1, //!< Page or subpage data format + isPS:1; //!< Parameters saveable ? + unsigned char bPageLength; //!< Length of page data (0x0A) + unsigned char isDCR:1, //!< Disable correction bit + isDTE:1, //!< Data terminate on error bit + isPER:1, //!< Post error bit + isEER:1, //!< Enable early recovery bit + isRC:1, //!< Read continuous bit + isTB:1, //!< Transfer block bit + isARRE:1, //!< Automatic read reallocation enabled bit + isAWRE:1; //!< Automatic write reallocation enabled bit + unsigned char bReadRetryCount; //!< Number of retries when reading + unsigned char pObsolete1[3]; //!< Obsolete bytes + unsigned char bReserved1; //!< Reserved byte + unsigned char bWriteRetryCount; //!< Number of retries when writing + unsigned char bReserved2; //!< Reserved byte + unsigned char pRecoveryTimeLimit[2]; //!< Maximum time duration for error recovery + +} __attribute__ ((packed)) SBCReadWriteErrorRecovery; // GCC + +//------------------------------------------------------------------------------ +/// \brief start/stop command +/// \see +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bModeDataLength; //!< Length of mode data to follow + unsigned char bImmediate:1, //!< + bReserved1:7; //!< Reserved bits + unsigned char pReserved[2]; //!< Reserved bytes + unsigned char startStop:1, //!< DPO/FUA bits supported ? + eject:1, //!< Reserved bits + bReserved2:6; //!< Is medium write-protected ? +} __attribute__ ((packed)) SBCStartStop; // GCC + +//------------------------------------------------------------------------------ +/// \brief Generic structure for holding information about SBC commands +/// \see SBCInquiry +/// \see SBCRead10 +/// \see SBCReadCapacity10 +/// \see SBCRequestSense +/// \see SBCTestUnitReady +/// \see SBCWrite10 +/// \see SBCMediumRemoval +/// \see SBCModeSense6 +//------------------------------------------------------------------------------ +typedef union { + + unsigned char bOperationCode; //!< Operation code of the command + SBCInquiry inquiry; //!< INQUIRY command + SBCRead10 read10; //!< READ (10) command + SBCReadCapacity10 readCapacity10; //!< READ CAPACITY (10) command + SBCRequestSense requestSense; //!< REQUEST SENSE command + SBCTestUnitReady testUnitReady; //!< TEST UNIT READY command + SBCWrite10 write10; //!< WRITE (10) command + SBCMediumRemoval mediumRemoval; //!< PREVENT/ALLOW MEDIUM REMOVAL command + SBCModeSense6 modeSense6; //!< MODE SENSE (6) command + SBCStartStop startStopCmd; //!< START-STOP command + +} SBCCommand; + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef SBC_H + diff --git a/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.c b/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.c index af1a1b836..f06454e1b 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.c +++ b/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.c @@ -1,1635 +1,1635 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/device/massstorage/SBCMethods.h" - -#include "../../../usb/device/core/USBD.h" -#include "../../../usb/device/massstorage/MSDDStateMachine.h" -#include "../../../usb/device/massstorage/MSDIOFifo.h" - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Macros -//------------------------------------------------------------------------------ - -#ifdef MSDIO_READ10_CHUNK_SIZE -/// READ10 - Read data from specific LUN to FIFO -#define SBC_READ_CHUNK(pLun, lba, pFifo, pCb, pArg) \ - LUN_Read((pLun), (lba), \ - &(pFifo)->pBuffer[(pFifo)->inputNdx], \ - ((pFifo)->chunkSize/(pFifo)->blockSize), \ - (TransferCallback)(pCb), (void*)pArg) -/// READ10 - Transfer data from FIFO to USB -#define SBC_TX_CHUNK(pFifo, pCb, pArg) \ - MSDD_Write(&(pFifo)->pBuffer[(pFifo)->outputNdx], \ - (pFifo)->chunkSize, \ - (TransferCallback)(pCb), (void*)(pArg)) -#endif - -#ifdef MSDIO_WRITE10_CHUNK_SIZE -/// WRITE10 - Read data from USB to FIFO -#define SBC_RX_CHUNK(pFifo,pCb,pArg) \ - MSDD_Read(&(pFifo)->pBuffer[(pFifo)->inputNdx], \ - (pFifo)->chunkSize, \ - (TransferCallback)(pCb), (void*)(pArg)) -/// WRITE10 - Write data from FIFO to LUN -#define SBC_WRITE_CHUNK(pLun, lba, pFifo, pCb, pArg) \ - LUN_Write((pLun), (lba), \ - &(pFifo)->pBuffer[(pFifo)->outputNdx], \ - ((pFifo)->chunkSize/(pFifo)->blockSize), \ - (TransferCallback)(pCb), (void*)(pArg)) -#endif - - -//------------------------------------------------------------------------------ -//! \brief Header for the mode pages data -//! \see SBCModeParameterHeader6 -//------------------------------------------------------------------------------ -static const SBCModeParameterHeader6 modeParameterHeader6 = { - - sizeof(SBCModeParameterHeader6) - 1, //! Length is 0x03 - SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE, //! Direct-access block device - 0, //! Reserved bits - 0, //! DPO/FUA not supported - 0, //! Reserved bits - 0, //! not write-protected - 0 //! No block descriptor -}; - -//------------------------------------------------------------------------------ -// Internal functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -//! \brief Check if the LUN is ready. -//! \param lun Pointer to the LUN affected by the command -//! \return 1 if the LUN is ready to be written -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBCLunIsReady(MSDLun *lun) -{ - unsigned char lunIsReady = 0; - Media *media = lun->media; - - if (media == 0 || lun->status < LUN_CHANGED) { - TRACE_INFO("SBCLunIsReady: Not Present!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - SBC_ASC_MEDIUM_NOT_PRESENT, - 0); - - } - else if (lun->status < LUN_READY) { - TRACE_INFO("SBCLunIsReady: Changing!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_UNIT_ATTENTION, - SBC_ASC_NOT_READY_TO_READY_CHANGE, - 0); - lun->status = LUN_READY; - } - else { - - lunIsReady = 1; - } - - return lunIsReady; -} -//------------------------------------------------------------------------------ -//! \brief Check if the LUN can write. -//! \param lun Pointer to the LUN affected by the command -//! \return 1 if the LUN is ready to be written -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBCLunCanBeWritten(MSDLun *lun) -{ - unsigned char canBeWritten = 0; - - if (!SBCLunIsReady(lun)) { - - TRACE_WARNING("SBCLunCanBeWritten: Not Ready!\n\r"); - } - else if (lun->protected) { - - TRACE_WARNING("SBCLunCanBeWritten: Protected!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_DATA_PROTECT, - SBC_ASC_WRITE_PROTECTED, - 0); - } - else { - - canBeWritten = 1; - } - - return canBeWritten; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a WRITE (10) command on the specified LUN. -//! -//! The data to write is first received from the USB host and then -//! actually written on the media. -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Write10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char status; - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; - MSDTransfer *transfer = &(commandState->transfer); - MSDTransfer *disktransfer = &(commandState->disktransfer); - MSDIOFifo *fifo = &lun->ioFifo; - Media *media = lun->media; - - // Init command state - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - - // The command should not be proceeded if READONLY - if (!SBCLunCanBeWritten(lun)) { - - return MSDD_STATUS_RW; - } - else { - - - // Initialize FIFO - fifo->dataTotal = commandState->length; - fifo->blockSize = lun->blockSize * media->blockSize; - #ifdef MSDIO_WRITE10_CHUNK_SIZE - if ( fifo->dataTotal >= 64 * 1024 - && fifo->blockSize < MSDIO_WRITE10_CHUNK_SIZE) - fifo->chunkSize = MSDIO_WRITE10_CHUNK_SIZE; - else - fifo->chunkSize = fifo->blockSize; - #endif - fifo->fullCnt = 0; - fifo->nullCnt = 0; - - // Initialize FIFO output (Disk) - fifo->outputNdx = 0; - fifo->outputTotal = 0; - fifo->outputState = MSDIO_IDLE; - transfer->semaphore = 0; - - // Initialize FIFO input (USB) - fifo->inputNdx = 0; - fifo->inputTotal = 0; - fifo->inputState = MSDIO_START; - disktransfer->semaphore = 0; - } - - } - - if (commandState->length == 0) { - - // Perform the callback! - if (lun->dataMonitor) { - - lun->dataMonitor(0, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); - } - return MSDD_STATUS_SUCCESS; - } - - // USB receive task - switch(fifo->inputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->inputTotal < fifo->dataTotal && - fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { - - fifo->inputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Should not start if there is any disk error - if (fifo->outputState == MSDIO_ERROR) { - - TRACE_INFO_WP("udErr "); - fifo->inputState = MSDIO_ERROR; - break; - } - - // Read one block of data sent by the host - if (media->mappedWR) { - - // Directly read to memory - status = MSDD_Read((void*) - ((media->baseAddress - + (lun->baseAddress - + DWORDB(command->pLogicalBlockAddress) - * lun->blockSize - ) - ) * media->blockSize - ), - fifo->dataTotal, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - } - else { - #ifdef MSDIO_WRITE10_CHUNK_SIZE - status = SBC_RX_CHUNK(fifo, MSDDriver_Callback, transfer); - #else - // Read block to buffer - status = MSDD_Read((void*)&fifo->pBuffer[fifo->inputNdx], - fifo->blockSize, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - #endif - } - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to start receiving\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uRx "); - - // Prepare next device state - fifo->inputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - TRACE_INFO_WP("uWait "); - - // Check semaphore - if (transfer->semaphore > 0) { - - transfer->semaphore--; - fifo->inputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check the result code of the read operation - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to received\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uNxt "); - - // Mapped read, all data done - if (media->mappedWR) { - - fifo->inputTotal = fifo->dataTotal; - fifo->inputState = MSDIO_IDLE; - } - else { - - // Update input index - #ifdef MSDIO_WRITE10_CHUNK_SIZE - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->inputTotal += fifo->chunkSize; - #else - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->inputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All Data done? - if (fifo->inputTotal >= fifo->dataTotal) { - - fifo->inputState = MSDIO_IDLE; - } - // - Buffer full? - else if (fifo->inputNdx == fifo->outputNdx) { - fifo->inputState = MSDIO_IDLE; - fifo->fullCnt ++; - - TRACE_DEBUG_WP("ufFull%d ", fifo->inputNdx); - } - // - More data to transfer? - else if (fifo->inputTotal < fifo->dataTotal) { - fifo->inputState = MSDIO_START; - - TRACE_INFO_WP("uStart "); - } - // never executed ! - //else { - // fifo->inputState = MSDIO_IDLE; - // TRACE_INFO_WP("uDone "); - //} - } - - } - break; // MSDIO_NEXT - - //------------------ - case MSDIO_ERROR: - //------------------ - - TRACE_WARNING_WP("uErr "); - commandState->length -= fifo->inputTotal; - return MSDD_STATUS_RW; - - } - - // Disk write task - switch(fifo->outputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->outputTotal < fifo->inputTotal) { - - fifo->outputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - - // Write the block to the media - if (media->mappedWR) { - - MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); - status = LUN_STATUS_SUCCESS; - } - else { - #ifdef MSDIO_WRITE10_CHUNK_SIZE - status = SBC_WRITE_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), - fifo, MSDDriver_Callback, disktransfer); - #else - status = LUN_Write(lun, - DWORDB(command->pLogicalBlockAddress), - &fifo->pBuffer[fifo->outputNdx], - 1, - (TransferCallback) MSDDriver_Callback, - (void *) disktransfer); - #endif - } - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to start write - "); - - if (!SBCLunCanBeWritten(lun)) { - - TRACE_WARNING("?\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - 0, - 0); - } - - fifo->outputState = MSDIO_ERROR; - } - else { - - // Prepare next state - fifo->outputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - TRACE_INFO_WP("dWait "); - - // Check semaphore value - if (disktransfer->semaphore > 0) { - - // Take semaphore and move to next state - disktransfer->semaphore--; - fifo->outputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check operation result code - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to write\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_RECOVERED_ERROR, - SBC_ASC_TOO_MUCH_WRITE_DATA, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("dNxt "); - - // Update transfer length and block address - - // Mapped memory, done - if (media->mappedWR) { - - commandState->length = 0; - fifo->outputState = MSDIO_IDLE; - } - else { - - // Update output index - #ifdef MSDIO_WRITE10_CHUNK_SIZE - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) - + fifo->chunkSize/fifo->blockSize, - command->pLogicalBlockAddress); - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->outputTotal += fifo->chunkSize; - #else - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, - command->pLogicalBlockAddress); - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->outputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All data done? - if (fifo->outputTotal >= fifo->dataTotal) { - - fifo->outputState = MSDIO_IDLE; - commandState->length = 0; - TRACE_INFO_WP("dDone "); - } - // - Send next? - else if (fifo->outputTotal < fifo->inputTotal) { - - fifo->outputState = MSDIO_START; - TRACE_INFO_WP("dStart "); - } - // - Buffer Null? - else { - fifo->outputState = MSDIO_IDLE; - fifo->nullCnt ++; - - TRACE_DEBUG_WP("dfNull%d ", fifo->outputNdx); - } - } - } - break; // MSDIO_NEXT - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a READ (10) command on specified LUN. -//! -//! The data is first read from the media and then sent to the USB host. -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Read10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char status; - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; - MSDTransfer *transfer = &(commandState->transfer); - MSDTransfer *disktransfer = &(commandState->disktransfer); - MSDIOFifo *fifo = &lun->ioFifo; - Media *media = lun->media; - - // Init command state - if (commandState->state == 0) { - - commandState->state = SBC_STATE_READ; - - if (!SBCLunIsReady(lun)) { - - return MSDD_STATUS_RW; - } - else { - - // Initialize FIFO - fifo->dataTotal = commandState->length; - fifo->blockSize = lun->blockSize * media->blockSize; - #ifdef MSDIO_READ10_CHUNK_SIZE - if ( fifo->dataTotal >= 64*1024 - && fifo->blockSize < MSDIO_READ10_CHUNK_SIZE) - fifo->chunkSize = MSDIO_READ10_CHUNK_SIZE; - else - fifo->chunkSize = fifo->blockSize; - #endif - fifo->fullCnt = 0; - fifo->nullCnt = 0; - - #ifdef MSDIO_FIFO_OFFSET - // Enable offset if total size >= 2*bufferSize - if (fifo->dataTotal / fifo->bufferSize >= 2) - fifo->bufferOffset = MSDIO_FIFO_OFFSET; - else - fifo->bufferOffset = 0; - #endif - - // Initialize FIFO output (USB) - fifo->outputNdx = 0; - fifo->outputTotal = 0; - fifo->outputState = MSDIO_IDLE; - transfer->semaphore = 0; - - // Initialize FIFO input (Disk) - fifo->inputNdx = 0; - fifo->inputTotal = 0; - fifo->inputState = MSDIO_START; - disktransfer->semaphore = 0; - } - } - - // Check length - if (commandState->length == 0) { - - // Perform the callback! - if (lun->dataMonitor) { - - lun->dataMonitor(1, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); - } - return MSDD_STATUS_SUCCESS; - } - - // Disk reading task - switch(fifo->inputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->inputTotal < fifo->dataTotal && - fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { - - fifo->inputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Read one block of data from the media - if (media->mappedRD) { - - // Directly write, no read needed - MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); - status = LUN_STATUS_SUCCESS; - } - else { - #ifdef MSDIO_READ10_CHUNK_SIZE - status = SBC_READ_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), - fifo, MSDDriver_Callback, disktransfer); - #else - status = LUN_Read(lun, - DWORDB(command->pLogicalBlockAddress), - &fifo->pBuffer[fifo->inputNdx], - 1, - (TransferCallback) MSDDriver_Callback, - (void *)disktransfer); - #endif - } - - // Check operation result code - if (status != LUN_STATUS_SUCCESS) { - - TRACE_WARNING("RBC_Read10: Failed to start reading\n\r"); - - if (SBCLunIsReady(lun)) { - - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - SBC_ASC_LOGICAL_UNIT_NOT_READY, - 0); - } - - fifo->inputState = MSDIO_ERROR; - } - else { - - TRACE_INFO_WP("dRd "); - - // Move to next command state - fifo->inputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - // Check semaphore value - if (disktransfer->semaphore > 0) { - - TRACE_INFO_WP("dOk "); - - // Take semaphore and move to next state - disktransfer->semaphore--; - fifo->inputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check the operation result code - if (disktransfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to read media\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_RECOVERED_ERROR, - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("dNxt "); - - if (media->mappedRD) { - - // All data is ready - fifo->inputState = MSDIO_IDLE; - fifo->inputTotal = fifo->dataTotal; - } - else { - - // Update block address - #ifdef MSDIO_READ10_CHUNK_SIZE - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) - + fifo->chunkSize/fifo->blockSize, - command->pLogicalBlockAddress); - - // Update input index - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->inputTotal += fifo->chunkSize; - #else - // Update block address - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, - command->pLogicalBlockAddress); - - // Update input index - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->inputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All Data done? - if (fifo->inputTotal >= fifo->dataTotal) { - - TRACE_INFO_WP("dDone "); - fifo->inputState = MSDIO_IDLE; - } - // - Buffer full? - else if (fifo->inputNdx == fifo->outputNdx) { - - TRACE_INFO_WP("dfFull%d ", (int)fifo->inputNdx); - fifo->inputState = MSDIO_IDLE; - fifo->fullCnt ++; - } - // - More data to transfer? - else if (fifo->inputTotal < fifo->dataTotal) { - - TRACE_DEBUG_WP("dStart "); - fifo->inputState = MSDIO_START; - } - } - - } - - break; - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - // USB sending task - switch(fifo->outputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->outputTotal < fifo->inputTotal) { - - #ifdef MSDIO_FIFO_OFFSET - // Offset buffer the input data - if (fifo->bufferOffset) { - if (fifo->inputTotal < fifo->bufferOffset) { - break; - } - fifo->bufferOffset = 0; - } - #endif - fifo->outputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Should not start if there is any disk error - if (fifo->outputState == MSDIO_ERROR) { - - fifo->inputState = MSDIO_ERROR; - break; - } - - // Send the block to the host - if (media->mappedRD) { - - status = MSDD_Write((void*) - ((media->baseAddress - + (lun->baseAddress - + DWORDB(command->pLogicalBlockAddress) - * lun->blockSize - ) - ) * media->blockSize - ), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - } - else { - #ifdef MSDIO_READ10_CHUNK_SIZE - status = SBC_TX_CHUNK(fifo, MSDDriver_Callback, transfer); - #else - status = MSDD_Write(&fifo->pBuffer[fifo->outputNdx], - fifo->blockSize, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - #endif - } - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to start to send\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uTx "); - - // Move to next command state - fifo->outputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - // Check semaphore value - if (transfer->semaphore > 0) { - - TRACE_INFO_WP("uOk "); - - // Take semaphore and move to next state - transfer->semaphore--; - fifo->outputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check operation result code - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to send data\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uNxt "); - - if (media->mappedRD) { - - commandState->length = 0; - } - else { - - // Update output index - #ifdef MSDIO_READ10_CHUNK_SIZE - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->outputTotal += fifo->chunkSize; - #else - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->outputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All data done? - if (fifo->outputTotal >= fifo->dataTotal) { - - fifo->outputState = MSDIO_IDLE; - commandState->length = 0; - TRACE_INFO_WP("uDone "); - } - // - Buffer Null? - else if (fifo->inputNdx == fifo->outputNdx) { - - TRACE_INFO_WP("ufNull%d ", (int)fifo->outputNdx); - fifo->outputState = MSDIO_IDLE; - fifo->nullCnt ++; - } - // - Send next? - else if (fifo->outputTotal < fifo->inputTotal) { - - TRACE_DEBUG_WP("uStart "); - fifo->outputState = MSDIO_START; - } - } - - } - break; - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a READ CAPACITY (10) command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDD_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_ReadCapacity10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - if (!SBCLunIsReady(lun)) { - - TRACE_INFO("SBC_ReadCapacity10: Not Ready!\n\r"); - return MSDD_STATUS_RW; - } - - // Initialize command state if needed - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start the write operation - status = MSDD_Write(&(lun->readCapacityData), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_ReadCapacity: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next command state - TRACE_INFO_WP("Sending "); - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING("RBC_ReadCapacity: Cannot send data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("Sent "); - result = MSDD_STATUS_SUCCESS; - } - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Handles an INQUIRY command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Inquiry(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - // Check if required length is 0 - if (commandState->length == 0) { - - // Nothing to do - result = MSDD_STATUS_SUCCESS; - } - // Initialize command state if needed - else if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - - // Change additional length field of inquiry data - lun->inquiryData->bAdditionalLength - = (unsigned char) (commandState->length - 5); - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start write operation - status = MSDD_Write((void *) lun->inquiryData, - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_Inquiry: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next state - TRACE_INFO_WP("Sending "); - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check the semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_Inquiry: Data transfer failed\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("Sent "); - result = MSDD_STATUS_SUCCESS; - } - - // Update length field - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a REQUEST SENSE command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_RequestSense(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - // Check if requested length is zero - if (commandState->length == 0) { - - // Nothing to do - result = MSDD_STATUS_SUCCESS; - } - // Initialize command state if needed - else if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start transfer - status = MSDD_Write(&(lun->requestSenseData), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_RequestSense: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Change state - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check the transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and finish command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - result = MSDD_STATUS_ERROR; - } - else { - - result = MSDD_STATUS_SUCCESS; - } - - // Update length - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a MODE SENSE (6) command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_ModeSense6(MSDLun *lun, MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - if (!SBCLunIsReady(lun)) { - - TRACE_INFO("SBC_ModeSense6: Not Ready!\n\r"); - return MSDD_STATUS_RW; - } - - // Check if mode page is supported - if (((SBCCommand *) commandState->cbw.pCommand)->modeSense6.bPageCode - != SBC_PAGE_RETURN_ALL) { - - return MSDD_STATUS_PARAMETER; - } - - // Initialize command state if needed - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Check current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start transfer - status = MSDD_Write((void *) &modeParameterHeader6, - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_ModeSense6: Cannot start data transfer\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next state - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - TRACE_INFO_WP("Wait "); - - // Check semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_ModeSense6: Data transfer failed\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - result = MSDD_STATUS_SUCCESS; - } - - // Update length field - commandState->length -= transfer->transferred; - - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a TEST UNIT READY COMMAND command. -//! \param lun Pointer to the LUN affected by the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBC_TestUnitReady(MSDLun *lun) -{ - unsigned char result = MSDD_STATUS_RW; - unsigned char senseKey = SBC_SENSE_KEY_NO_SENSE, - addSenseCode = 0, - addSenseCodeQual = 0; - Media *media = lun->media; - - // Check current media state - if (lun->status < LUN_CHANGED) { - - TRACE_INFO_WP("Ejc "); - senseKey = SBC_SENSE_KEY_NOT_READY; - addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; - } - else if (lun->status == LUN_CHANGED) { - - TRACE_INFO_WP("Chg "); - senseKey = SBC_SENSE_KEY_UNIT_ATTENTION; - addSenseCode = SBC_ASC_NOT_READY_TO_READY_CHANGE; - lun->status = LUN_READY; - } - else { - - switch(media->state) { - //------------------- - case MED_STATE_READY: - //------------------- - // Nothing to do - TRACE_INFO_WP("Rdy "); - result = MSDD_STATUS_SUCCESS; - break; - - //------------------ - case MED_STATE_BUSY: - //------------------ - TRACE_INFO_WP("Bsy "); - senseKey = SBC_SENSE_KEY_NOT_READY; - break; - - //------ - default: - //------ - TRACE_INFO_WP("? "); - senseKey = SBC_SENSE_KEY_NOT_READY; - addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; - break; - } - } - SBC_UpdateSenseData(&(lun->requestSenseData), - senseKey, - addSenseCode, - addSenseCodeQual); - - return result; -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -//! \brief Updates the sense data of a LUN with the given key and codes -//! \param requestSenseData Pointer to the sense data to update -//! \param senseKey Sense key -//! \param additionalSenseCode Additional sense code -//! \param additionalSenseCodeQualifier Additional sense code qualifier -//------------------------------------------------------------------------------ -void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, - unsigned char senseKey, - unsigned char additionalSenseCode, - unsigned char additionalSenseCodeQualifier) -{ - requestSenseData->bSenseKey = senseKey; - requestSenseData->bAdditionalSenseCode = additionalSenseCode; - requestSenseData->bAdditionalSenseCodeQualifier - = additionalSenseCodeQualifier; -} - -//------------------------------------------------------------------------------ -//! \brief Return information about the transfer length and direction expected -//! by the device for a particular command. -//! \param command Pointer to a buffer holding the command to evaluate -//! \param length Expected length of the data transfer -//! \param type Expected direction of data transfer -//! \param lun Pointer to the LUN affected by the command -//------------------------------------------------------------------------------ -unsigned char SBC_GetCommandInformation(void *command, - unsigned int *length, - unsigned char *type, - MSDLun *lun) -{ - SBCCommand *sbcCommand = (SBCCommand *) command; - unsigned char isCommandSupported = 1; - Media *media = lun->media; - - // Identify command - switch (sbcCommand->bOperationCode) { - //--------------- - case SBC_INQUIRY: - //--------------- - (*type) = MSDD_DEVICE_TO_HOST; - - // Allocation length is stored in big-endian format - (*length) = WORDB(sbcCommand->inquiry.pAllocationLength); - break; - - //-------------------- - case SBC_MODE_SENSE_6: - //-------------------- - (*type) = MSDD_DEVICE_TO_HOST; - if (sbcCommand->modeSense6.bAllocationLength > - sizeof(SBCModeParameterHeader6)) { - - *length = sizeof(SBCModeParameterHeader6); - } - else { - - *length = sbcCommand->modeSense6.bAllocationLength; - } - break; - - //------------------------------------ - case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: - case SBC_START_STOP: - //------------------------------------ - (*type) = MSDD_NO_TRANSFER; - break; - - //--------------------- - case SBC_REQUEST_SENSE: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = sbcCommand->requestSense.bAllocationLength; - break; - - //----------------------- - case SBC_TEST_UNIT_READY: - //----------------------- - (*type) = MSDD_NO_TRANSFER; - break; - - //--------------------- - case SBC_READ_CAPACITY_10: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = sizeof(SBCReadCapacity10Data); - break; - - //--------------- - case SBC_READ_10: - //--------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = WORDB(sbcCommand->read10.pTransferLength) - * lun->blockSize * media->blockSize; - break; - - //---------------- - case SBC_WRITE_10: - //---------------- - (*type) = MSDD_HOST_TO_DEVICE; - (*length) = WORDB(sbcCommand->write10.pTransferLength) - * lun->blockSize * media->blockSize; - break; - - //----------------- - case SBC_VERIFY_10: - //----------------- - (*type) = MSDD_NO_TRANSFER; - break; - #if 0 - //--------------------- - case SBC_READ_FORMAT_CAPACITIES: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = 1; - break; - #endif - //------ - default: - //------ - isCommandSupported = 0; - } - - // If length is 0, no transfer is expected - if ((*length) == 0) { - - (*type) = MSDD_NO_TRANSFER; - } - - return isCommandSupported; -} - -//------------------------------------------------------------------------------ -//! \brief Processes a SBC command by dispatching it to a subfunction. -//! \param lun Pointer to the affected LUN -//! \param commandState Pointer to the current command state -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char SBC_ProcessCommand(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCCommand *command = (SBCCommand *) commandState->cbw.pCommand; - Media *media = lun->media; - - // Identify command - switch (command->bOperationCode) { - //--------------- - case SBC_READ_10: - //--------------- - TRACE_DEBUG_WP("Read(10) "); - - // Perform the Read10 command - result = SBC_Read10(lun, commandState); - break; - - //---------------- - case SBC_WRITE_10: - //---------------- - TRACE_DEBUG_WP("Write(10) "); - - // Perform the Write10 command - result = SBC_Write10(lun, commandState); - break; - - //--------------------- - case SBC_READ_CAPACITY_10: - //--------------------- - TRACE_INFO_WP("RdCapacity(10) "); - - // Perform the ReadCapacity command - result = SBC_ReadCapacity10(lun, commandState); - break; - - //--------------------- - case SBC_VERIFY_10: - //--------------------- - TRACE_INFO_WP("Verify(10) "); - - // Flush media - MED_Flush(media); - result = MSDD_STATUS_SUCCESS; - break; - - //--------------- - case SBC_INQUIRY: - //--------------- - TRACE_INFO_WP("Inquiry "); - - // Process Inquiry command - result = SBC_Inquiry(lun, commandState); - break; - - //-------------------- - case SBC_MODE_SENSE_6: - //-------------------- - TRACE_INFO_WP("ModeSense(6) "); - - // Process ModeSense6 command - result = SBC_ModeSense6(lun, commandState); - break; - - //----------------------- - case SBC_TEST_UNIT_READY: - //----------------------- - TRACE_INFO_WP("TstUnitRdy "); - - // Process TestUnitReady command - //MED_Flush(media); - result = SBC_TestUnitReady(lun); - break; - - //--------------------- - case SBC_REQUEST_SENSE: - //--------------------- - TRACE_INFO_WP("ReqSense "); - - // Perform the RequestSense command - result = SBC_RequestSense(lun, commandState); - break; - - //------------------------------------ - case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: - //------------------------------------ - TRACE_INFO_WP("PrevAllowRem "); - - // Check parameter - result = command->mediumRemoval.bPrevent ? - MSDD_STATUS_PARAMETER : MSDD_STATUS_SUCCESS; - result = MSDD_STATUS_SUCCESS; - break; - - case SBC_START_STOP: - TRACE_INFO_WP("StartStop "); - - result = command->startStopCmd.startStop ; - if (result == 0) { - lun->status = LUN_EJECTED ; - } - else { - lun->status = LUN_CHANGED ; - } - result = MSDD_STATUS_SUCCESS; - break; - - #if 0 - //------------------------------------ - case SBC_READ_FORMAT_CAPACITIES: - //------------------------------------ - TRACE_INFO_WP("RdFmtCap "); - result = MSDD_STATUS_RW; - break; - /* TODO BSS Added if (!SBCLunIsReady(lun)) { - - result = MSDD_STATUS_RW; - break; - } */ - #endif - //------ - default: - //------ - result = MSDD_STATUS_PARAMETER; - } - - return result; -} +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/device/massstorage/SBCMethods.h" + +#include "../../../usb/device/core/USBD.h" +#include "../../../usb/device/massstorage/MSDDStateMachine.h" +#include "../../../usb/device/massstorage/MSDIOFifo.h" + +//------------------------------------------------------------------------------ +// Global variables +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Macros +//------------------------------------------------------------------------------ + +#ifdef MSDIO_READ10_CHUNK_SIZE +/// READ10 - Read data from specific LUN to FIFO +#define SBC_READ_CHUNK(pLun, lba, pFifo, pCb, pArg) \ + LUN_Read((pLun), (lba), \ + &(pFifo)->pBuffer[(pFifo)->inputNdx], \ + ((pFifo)->chunkSize/(pFifo)->blockSize), \ + (TransferCallback)(pCb), (void*)pArg) +/// READ10 - Transfer data from FIFO to USB +#define SBC_TX_CHUNK(pFifo, pCb, pArg) \ + MSDD_Write(&(pFifo)->pBuffer[(pFifo)->outputNdx], \ + (pFifo)->chunkSize, \ + (TransferCallback)(pCb), (void*)(pArg)) +#endif + +#ifdef MSDIO_WRITE10_CHUNK_SIZE +/// WRITE10 - Read data from USB to FIFO +#define SBC_RX_CHUNK(pFifo,pCb,pArg) \ + MSDD_Read(&(pFifo)->pBuffer[(pFifo)->inputNdx], \ + (pFifo)->chunkSize, \ + (TransferCallback)(pCb), (void*)(pArg)) +/// WRITE10 - Write data from FIFO to LUN +#define SBC_WRITE_CHUNK(pLun, lba, pFifo, pCb, pArg) \ + LUN_Write((pLun), (lba), \ + &(pFifo)->pBuffer[(pFifo)->outputNdx], \ + ((pFifo)->chunkSize/(pFifo)->blockSize), \ + (TransferCallback)(pCb), (void*)(pArg)) +#endif + + +//------------------------------------------------------------------------------ +//! \brief Header for the mode pages data +//! \see SBCModeParameterHeader6 +//------------------------------------------------------------------------------ +static const SBCModeParameterHeader6 modeParameterHeader6 = { + + sizeof(SBCModeParameterHeader6) - 1, //! Length is 0x03 + SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE, //! Direct-access block device + 0, //! Reserved bits + 0, //! DPO/FUA not supported + 0, //! Reserved bits + 0, //! not write-protected + 0 //! No block descriptor +}; + +//------------------------------------------------------------------------------ +// Internal functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +//! \brief Check if the LUN is ready. +//! \param lun Pointer to the LUN affected by the command +//! \return 1 if the LUN is ready to be written +//! \see MSDLun +//------------------------------------------------------------------------------ +static unsigned char SBCLunIsReady(MSDLun *lun) +{ + unsigned char lunIsReady = 0; + Media *media = lun->media; + + if (media == 0 || lun->status < LUN_CHANGED) { + TRACE_INFO("SBCLunIsReady: Not Present!\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_NOT_READY, + SBC_ASC_MEDIUM_NOT_PRESENT, + 0); + + } + else if (lun->status < LUN_READY) { + TRACE_INFO("SBCLunIsReady: Changing!\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_UNIT_ATTENTION, + SBC_ASC_NOT_READY_TO_READY_CHANGE, + 0); + lun->status = LUN_READY; + } + else { + + lunIsReady = 1; + } + + return lunIsReady; +} +//------------------------------------------------------------------------------ +//! \brief Check if the LUN can write. +//! \param lun Pointer to the LUN affected by the command +//! \return 1 if the LUN is ready to be written +//! \see MSDLun +//------------------------------------------------------------------------------ +static unsigned char SBCLunCanBeWritten(MSDLun *lun) +{ + unsigned char canBeWritten = 0; + + if (!SBCLunIsReady(lun)) { + + TRACE_WARNING("SBCLunCanBeWritten: Not Ready!\n\r"); + } + else if (lun->protected) { + + TRACE_WARNING("SBCLunCanBeWritten: Protected!\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_DATA_PROTECT, + SBC_ASC_WRITE_PROTECTED, + 0); + } + else { + + canBeWritten = 1; + } + + return canBeWritten; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a WRITE (10) command on the specified LUN. +//! +//! The data to write is first received from the USB host and then +//! actually written on the media. +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_Write10(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char status; + unsigned char result = MSDD_STATUS_INCOMPLETE; + SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; + MSDTransfer *transfer = &(commandState->transfer); + MSDTransfer *disktransfer = &(commandState->disktransfer); + MSDIOFifo *fifo = &lun->ioFifo; + Media *media = lun->media; + + // Init command state + if (commandState->state == 0) { + + commandState->state = SBC_STATE_WRITE; + + // The command should not be proceeded if READONLY + if (!SBCLunCanBeWritten(lun)) { + + return MSDD_STATUS_RW; + } + else { + + + // Initialize FIFO + fifo->dataTotal = commandState->length; + fifo->blockSize = lun->blockSize * media->blockSize; + #ifdef MSDIO_WRITE10_CHUNK_SIZE + if ( fifo->dataTotal >= 64 * 1024 + && fifo->blockSize < MSDIO_WRITE10_CHUNK_SIZE) + fifo->chunkSize = MSDIO_WRITE10_CHUNK_SIZE; + else + fifo->chunkSize = fifo->blockSize; + #endif + fifo->fullCnt = 0; + fifo->nullCnt = 0; + + // Initialize FIFO output (Disk) + fifo->outputNdx = 0; + fifo->outputTotal = 0; + fifo->outputState = MSDIO_IDLE; + transfer->semaphore = 0; + + // Initialize FIFO input (USB) + fifo->inputNdx = 0; + fifo->inputTotal = 0; + fifo->inputState = MSDIO_START; + disktransfer->semaphore = 0; + } + + } + + if (commandState->length == 0) { + + // Perform the callback! + if (lun->dataMonitor) { + + lun->dataMonitor(0, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); + } + return MSDD_STATUS_SUCCESS; + } + + // USB receive task + switch(fifo->inputState) { + + //------------------ + case MSDIO_IDLE: + //------------------ + if (fifo->inputTotal < fifo->dataTotal && + fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { + + fifo->inputState = MSDIO_START; + } + break; + + //------------------ + case MSDIO_START: + //------------------ + // Should not start if there is any disk error + if (fifo->outputState == MSDIO_ERROR) { + + TRACE_INFO_WP("udErr "); + fifo->inputState = MSDIO_ERROR; + break; + } + + // Read one block of data sent by the host + if (media->mappedWR) { + + // Directly read to memory + status = MSDD_Read((void*) + ((media->baseAddress + + (lun->baseAddress + + DWORDB(command->pLogicalBlockAddress) + * lun->blockSize + ) + ) * media->blockSize + ), + fifo->dataTotal, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + } + else { + #ifdef MSDIO_WRITE10_CHUNK_SIZE + status = SBC_RX_CHUNK(fifo, MSDDriver_Callback, transfer); + #else + // Read block to buffer + status = MSDD_Read((void*)&fifo->pBuffer[fifo->inputNdx], + fifo->blockSize, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + #endif + } + + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Write10: Failed to start receiving\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_HARDWARE_ERROR, + 0, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("uRx "); + + // Prepare next device state + fifo->inputState = MSDIO_WAIT; + } + break; // MSDIO_START + + //------------------ + case MSDIO_WAIT: + //------------------ + TRACE_INFO_WP("uWait "); + + // Check semaphore + if (transfer->semaphore > 0) { + + transfer->semaphore--; + fifo->inputState = MSDIO_NEXT; + } + break; + + //------------------ + case MSDIO_NEXT: + //------------------ + // Check the result code of the read operation + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Write10: Failed to received\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_HARDWARE_ERROR, + 0, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("uNxt "); + + // Mapped read, all data done + if (media->mappedWR) { + + fifo->inputTotal = fifo->dataTotal; + fifo->inputState = MSDIO_IDLE; + } + else { + + // Update input index + #ifdef MSDIO_WRITE10_CHUNK_SIZE + MSDIOFifo_IncNdx(fifo->inputNdx, + fifo->chunkSize, + fifo->bufferSize); + fifo->inputTotal += fifo->chunkSize; + #else + MSDIOFifo_IncNdx(fifo->inputNdx, + fifo->blockSize, + fifo->bufferSize); + fifo->inputTotal += fifo->blockSize; + #endif + + // Start Next block + // - All Data done? + if (fifo->inputTotal >= fifo->dataTotal) { + + fifo->inputState = MSDIO_IDLE; + } + // - Buffer full? + else if (fifo->inputNdx == fifo->outputNdx) { + fifo->inputState = MSDIO_IDLE; + fifo->fullCnt ++; + + TRACE_DEBUG_WP("ufFull%d ", fifo->inputNdx); + } + // - More data to transfer? + else if (fifo->inputTotal < fifo->dataTotal) { + fifo->inputState = MSDIO_START; + + TRACE_INFO_WP("uStart "); + } + // never executed ! + //else { + // fifo->inputState = MSDIO_IDLE; + // TRACE_INFO_WP("uDone "); + //} + } + + } + break; // MSDIO_NEXT + + //------------------ + case MSDIO_ERROR: + //------------------ + + TRACE_WARNING_WP("uErr "); + commandState->length -= fifo->inputTotal; + return MSDD_STATUS_RW; + + } + + // Disk write task + switch(fifo->outputState) { + + //------------------ + case MSDIO_IDLE: + //------------------ + if (fifo->outputTotal < fifo->inputTotal) { + + fifo->outputState = MSDIO_START; + } + break; + + //------------------ + case MSDIO_START: + //------------------ + + // Write the block to the media + if (media->mappedWR) { + + MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); + status = LUN_STATUS_SUCCESS; + } + else { + #ifdef MSDIO_WRITE10_CHUNK_SIZE + status = SBC_WRITE_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), + fifo, MSDDriver_Callback, disktransfer); + #else + status = LUN_Write(lun, + DWORDB(command->pLogicalBlockAddress), + &fifo->pBuffer[fifo->outputNdx], + 1, + (TransferCallback) MSDDriver_Callback, + (void *) disktransfer); + #endif + } + + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Write10: Failed to start write - "); + + if (!SBCLunCanBeWritten(lun)) { + + TRACE_WARNING("?\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_NOT_READY, + 0, + 0); + } + + fifo->outputState = MSDIO_ERROR; + } + else { + + // Prepare next state + fifo->outputState = MSDIO_WAIT; + } + break; // MSDIO_START + + //------------------ + case MSDIO_WAIT: + //------------------ + TRACE_INFO_WP("dWait "); + + // Check semaphore value + if (disktransfer->semaphore > 0) { + + // Take semaphore and move to next state + disktransfer->semaphore--; + fifo->outputState = MSDIO_NEXT; + } + break; + + //------------------ + case MSDIO_NEXT: + //------------------ + // Check operation result code + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Write10: Failed to write\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_RECOVERED_ERROR, + SBC_ASC_TOO_MUCH_WRITE_DATA, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("dNxt "); + + // Update transfer length and block address + + // Mapped memory, done + if (media->mappedWR) { + + commandState->length = 0; + fifo->outputState = MSDIO_IDLE; + } + else { + + // Update output index + #ifdef MSDIO_WRITE10_CHUNK_SIZE + STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + + fifo->chunkSize/fifo->blockSize, + command->pLogicalBlockAddress); + MSDIOFifo_IncNdx(fifo->outputNdx, + fifo->chunkSize, + fifo->bufferSize); + fifo->outputTotal += fifo->chunkSize; + #else + STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, + command->pLogicalBlockAddress); + MSDIOFifo_IncNdx(fifo->outputNdx, + fifo->blockSize, + fifo->bufferSize); + fifo->outputTotal += fifo->blockSize; + #endif + + // Start Next block + // - All data done? + if (fifo->outputTotal >= fifo->dataTotal) { + + fifo->outputState = MSDIO_IDLE; + commandState->length = 0; + TRACE_INFO_WP("dDone "); + } + // - Send next? + else if (fifo->outputTotal < fifo->inputTotal) { + + fifo->outputState = MSDIO_START; + TRACE_INFO_WP("dStart "); + } + // - Buffer Null? + else { + fifo->outputState = MSDIO_IDLE; + fifo->nullCnt ++; + + TRACE_DEBUG_WP("dfNull%d ", fifo->outputNdx); + } + } + } + break; // MSDIO_NEXT + + //------------------ + case MSDIO_ERROR: + //------------------ + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a READ (10) command on specified LUN. +//! +//! The data is first read from the media and then sent to the USB host. +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_Read10(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char status; + unsigned char result = MSDD_STATUS_INCOMPLETE; + SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; + MSDTransfer *transfer = &(commandState->transfer); + MSDTransfer *disktransfer = &(commandState->disktransfer); + MSDIOFifo *fifo = &lun->ioFifo; + Media *media = lun->media; + + // Init command state + if (commandState->state == 0) { + + commandState->state = SBC_STATE_READ; + + if (!SBCLunIsReady(lun)) { + + return MSDD_STATUS_RW; + } + else { + + // Initialize FIFO + fifo->dataTotal = commandState->length; + fifo->blockSize = lun->blockSize * media->blockSize; + #ifdef MSDIO_READ10_CHUNK_SIZE + if ( fifo->dataTotal >= 64*1024 + && fifo->blockSize < MSDIO_READ10_CHUNK_SIZE) + fifo->chunkSize = MSDIO_READ10_CHUNK_SIZE; + else + fifo->chunkSize = fifo->blockSize; + #endif + fifo->fullCnt = 0; + fifo->nullCnt = 0; + + #ifdef MSDIO_FIFO_OFFSET + // Enable offset if total size >= 2*bufferSize + if (fifo->dataTotal / fifo->bufferSize >= 2) + fifo->bufferOffset = MSDIO_FIFO_OFFSET; + else + fifo->bufferOffset = 0; + #endif + + // Initialize FIFO output (USB) + fifo->outputNdx = 0; + fifo->outputTotal = 0; + fifo->outputState = MSDIO_IDLE; + transfer->semaphore = 0; + + // Initialize FIFO input (Disk) + fifo->inputNdx = 0; + fifo->inputTotal = 0; + fifo->inputState = MSDIO_START; + disktransfer->semaphore = 0; + } + } + + // Check length + if (commandState->length == 0) { + + // Perform the callback! + if (lun->dataMonitor) { + + lun->dataMonitor(1, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); + } + return MSDD_STATUS_SUCCESS; + } + + // Disk reading task + switch(fifo->inputState) { + + //------------------ + case MSDIO_IDLE: + //------------------ + if (fifo->inputTotal < fifo->dataTotal && + fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { + + fifo->inputState = MSDIO_START; + } + break; + + //------------------ + case MSDIO_START: + //------------------ + // Read one block of data from the media + if (media->mappedRD) { + + // Directly write, no read needed + MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); + status = LUN_STATUS_SUCCESS; + } + else { + #ifdef MSDIO_READ10_CHUNK_SIZE + status = SBC_READ_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), + fifo, MSDDriver_Callback, disktransfer); + #else + status = LUN_Read(lun, + DWORDB(command->pLogicalBlockAddress), + &fifo->pBuffer[fifo->inputNdx], + 1, + (TransferCallback) MSDDriver_Callback, + (void *)disktransfer); + #endif + } + + // Check operation result code + if (status != LUN_STATUS_SUCCESS) { + + TRACE_WARNING("RBC_Read10: Failed to start reading\n\r"); + + if (SBCLunIsReady(lun)) { + + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_NOT_READY, + SBC_ASC_LOGICAL_UNIT_NOT_READY, + 0); + } + + fifo->inputState = MSDIO_ERROR; + } + else { + + TRACE_INFO_WP("dRd "); + + // Move to next command state + fifo->inputState = MSDIO_WAIT; + } + break; // MSDIO_START + + //------------------ + case MSDIO_WAIT: + //------------------ + // Check semaphore value + if (disktransfer->semaphore > 0) { + + TRACE_INFO_WP("dOk "); + + // Take semaphore and move to next state + disktransfer->semaphore--; + fifo->inputState = MSDIO_NEXT; + } + break; + + //------------------ + case MSDIO_NEXT: + //------------------ + // Check the operation result code + if (disktransfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Read10: Failed to read media\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_RECOVERED_ERROR, + SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("dNxt "); + + if (media->mappedRD) { + + // All data is ready + fifo->inputState = MSDIO_IDLE; + fifo->inputTotal = fifo->dataTotal; + } + else { + + // Update block address + #ifdef MSDIO_READ10_CHUNK_SIZE + STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + + fifo->chunkSize/fifo->blockSize, + command->pLogicalBlockAddress); + + // Update input index + MSDIOFifo_IncNdx(fifo->inputNdx, + fifo->chunkSize, + fifo->bufferSize); + fifo->inputTotal += fifo->chunkSize; + #else + // Update block address + STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, + command->pLogicalBlockAddress); + + // Update input index + MSDIOFifo_IncNdx(fifo->inputNdx, + fifo->blockSize, + fifo->bufferSize); + fifo->inputTotal += fifo->blockSize; + #endif + + // Start Next block + // - All Data done? + if (fifo->inputTotal >= fifo->dataTotal) { + + TRACE_INFO_WP("dDone "); + fifo->inputState = MSDIO_IDLE; + } + // - Buffer full? + else if (fifo->inputNdx == fifo->outputNdx) { + + TRACE_INFO_WP("dfFull%d ", (int)fifo->inputNdx); + fifo->inputState = MSDIO_IDLE; + fifo->fullCnt ++; + } + // - More data to transfer? + else if (fifo->inputTotal < fifo->dataTotal) { + + TRACE_DEBUG_WP("dStart "); + fifo->inputState = MSDIO_START; + } + } + + } + + break; + + //------------------ + case MSDIO_ERROR: + //------------------ + break; + } + + // USB sending task + switch(fifo->outputState) { + + //------------------ + case MSDIO_IDLE: + //------------------ + if (fifo->outputTotal < fifo->inputTotal) { + + #ifdef MSDIO_FIFO_OFFSET + // Offset buffer the input data + if (fifo->bufferOffset) { + if (fifo->inputTotal < fifo->bufferOffset) { + break; + } + fifo->bufferOffset = 0; + } + #endif + fifo->outputState = MSDIO_START; + } + break; + + //------------------ + case MSDIO_START: + //------------------ + // Should not start if there is any disk error + if (fifo->outputState == MSDIO_ERROR) { + + fifo->inputState = MSDIO_ERROR; + break; + } + + // Send the block to the host + if (media->mappedRD) { + + status = MSDD_Write((void*) + ((media->baseAddress + + (lun->baseAddress + + DWORDB(command->pLogicalBlockAddress) + * lun->blockSize + ) + ) * media->blockSize + ), + commandState->length, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + } + else { + #ifdef MSDIO_READ10_CHUNK_SIZE + status = SBC_TX_CHUNK(fifo, MSDDriver_Callback, transfer); + #else + status = MSDD_Write(&fifo->pBuffer[fifo->outputNdx], + fifo->blockSize, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + #endif + } + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Read10: Failed to start to send\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_HARDWARE_ERROR, + 0, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("uTx "); + + // Move to next command state + fifo->outputState = MSDIO_WAIT; + } + break; // MSDIO_START + + //------------------ + case MSDIO_WAIT: + //------------------ + // Check semaphore value + if (transfer->semaphore > 0) { + + TRACE_INFO_WP("uOk "); + + // Take semaphore and move to next state + transfer->semaphore--; + fifo->outputState = MSDIO_NEXT; + } + break; + + //------------------ + case MSDIO_NEXT: + //------------------ + // Check operation result code + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Read10: Failed to send data\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_HARDWARE_ERROR, + 0, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("uNxt "); + + if (media->mappedRD) { + + commandState->length = 0; + } + else { + + // Update output index + #ifdef MSDIO_READ10_CHUNK_SIZE + MSDIOFifo_IncNdx(fifo->outputNdx, + fifo->chunkSize, + fifo->bufferSize); + fifo->outputTotal += fifo->chunkSize; + #else + MSDIOFifo_IncNdx(fifo->outputNdx, + fifo->blockSize, + fifo->bufferSize); + fifo->outputTotal += fifo->blockSize; + #endif + + // Start Next block + // - All data done? + if (fifo->outputTotal >= fifo->dataTotal) { + + fifo->outputState = MSDIO_IDLE; + commandState->length = 0; + TRACE_INFO_WP("uDone "); + } + // - Buffer Null? + else if (fifo->inputNdx == fifo->outputNdx) { + + TRACE_INFO_WP("ufNull%d ", (int)fifo->outputNdx); + fifo->outputState = MSDIO_IDLE; + fifo->nullCnt ++; + } + // - Send next? + else if (fifo->outputTotal < fifo->inputTotal) { + + TRACE_DEBUG_WP("uStart "); + fifo->outputState = MSDIO_START; + } + } + + } + break; + + //------------------ + case MSDIO_ERROR: + //------------------ + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a READ CAPACITY (10) command. +//! +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDD_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_ReadCapacity10(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char result = MSDD_STATUS_INCOMPLETE; + unsigned char status; + MSDTransfer *transfer = &(commandState->transfer); + + if (!SBCLunIsReady(lun)) { + + TRACE_INFO("SBC_ReadCapacity10: Not Ready!\n\r"); + return MSDD_STATUS_RW; + } + + // Initialize command state if needed + if (commandState->state == 0) { + + commandState->state = SBC_STATE_WRITE; + } + + // Identify current command state + switch (commandState->state) { + //------------------- + case SBC_STATE_WRITE: + //------------------- + // Start the write operation + status = MSDD_Write(&(lun->readCapacityData), + commandState->length, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_ReadCapacity: Cannot start sending data\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + // Proceed to next command state + TRACE_INFO_WP("Sending "); + commandState->state = SBC_STATE_WAIT_WRITE; + } + break; + + //------------------------ + case SBC_STATE_WAIT_WRITE: + //------------------------ + // Check semaphore value + if (transfer->semaphore > 0) { + + // Take semaphore and terminate command + transfer->semaphore--; + + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING("RBC_ReadCapacity: Cannot send data\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("Sent "); + result = MSDD_STATUS_SUCCESS; + } + commandState->length -= transfer->transferred; + } + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Handles an INQUIRY command. +//! +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_Inquiry(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char result = MSDD_STATUS_INCOMPLETE; + unsigned char status; + MSDTransfer *transfer = &(commandState->transfer); + + // Check if required length is 0 + if (commandState->length == 0) { + + // Nothing to do + result = MSDD_STATUS_SUCCESS; + } + // Initialize command state if needed + else if (commandState->state == 0) { + + commandState->state = SBC_STATE_WRITE; + + // Change additional length field of inquiry data + lun->inquiryData->bAdditionalLength + = (unsigned char) (commandState->length - 5); + } + + // Identify current command state + switch (commandState->state) { + //------------------- + case SBC_STATE_WRITE: + //------------------- + // Start write operation + status = MSDD_Write((void *) lun->inquiryData, + commandState->length, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "SPC_Inquiry: Cannot start sending data\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + // Proceed to next state + TRACE_INFO_WP("Sending "); + commandState->state = SBC_STATE_WAIT_WRITE; + } + break; + + //------------------------ + case SBC_STATE_WAIT_WRITE: + //------------------------ + // Check the semaphore value + if (transfer->semaphore > 0) { + + // Take semaphore and terminate command + transfer->semaphore--; + + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "SPC_Inquiry: Data transfer failed\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("Sent "); + result = MSDD_STATUS_SUCCESS; + } + + // Update length field + commandState->length -= transfer->transferred; + } + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a REQUEST SENSE command. +//! +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_RequestSense(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char result = MSDD_STATUS_INCOMPLETE; + unsigned char status; + MSDTransfer *transfer = &(commandState->transfer); + + // Check if requested length is zero + if (commandState->length == 0) { + + // Nothing to do + result = MSDD_STATUS_SUCCESS; + } + // Initialize command state if needed + else if (commandState->state == 0) { + + commandState->state = SBC_STATE_WRITE; + } + + // Identify current command state + switch (commandState->state) { + //------------------- + case SBC_STATE_WRITE: + //------------------- + // Start transfer + status = MSDD_Write(&(lun->requestSenseData), + commandState->length, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_RequestSense: Cannot start sending data\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + // Change state + commandState->state = SBC_STATE_WAIT_WRITE; + } + break; + + //------------------------ + case SBC_STATE_WAIT_WRITE: + //------------------------ + // Check the transfer semaphore + if (transfer->semaphore > 0) { + + // Take semaphore and finish command + transfer->semaphore--; + + if (transfer->status != USBD_STATUS_SUCCESS) { + + result = MSDD_STATUS_ERROR; + } + else { + + result = MSDD_STATUS_SUCCESS; + } + + // Update length + commandState->length -= transfer->transferred; + } + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a MODE SENSE (6) command. +//! +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_ModeSense6(MSDLun *lun, MSDCommandState *commandState) +{ + unsigned char result = MSDD_STATUS_INCOMPLETE; + unsigned char status; + MSDTransfer *transfer = &(commandState->transfer); + + if (!SBCLunIsReady(lun)) { + + TRACE_INFO("SBC_ModeSense6: Not Ready!\n\r"); + return MSDD_STATUS_RW; + } + + // Check if mode page is supported + if (((SBCCommand *) commandState->cbw.pCommand)->modeSense6.bPageCode + != SBC_PAGE_RETURN_ALL) { + + return MSDD_STATUS_PARAMETER; + } + + // Initialize command state if needed + if (commandState->state == 0) { + + commandState->state = SBC_STATE_WRITE; + } + + // Check current command state + switch (commandState->state) { + //------------------- + case SBC_STATE_WRITE: + //------------------- + // Start transfer + status = MSDD_Write((void *) &modeParameterHeader6, + commandState->length, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "SPC_ModeSense6: Cannot start data transfer\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + // Proceed to next state + commandState->state = SBC_STATE_WAIT_WRITE; + } + break; + + //------------------------ + case SBC_STATE_WAIT_WRITE: + //------------------------ + TRACE_INFO_WP("Wait "); + + // Check semaphore value + if (transfer->semaphore > 0) { + + // Take semaphore and terminate command + transfer->semaphore--; + + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "SPC_ModeSense6: Data transfer failed\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + result = MSDD_STATUS_SUCCESS; + } + + // Update length field + commandState->length -= transfer->transferred; + + } + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a TEST UNIT READY COMMAND command. +//! \param lun Pointer to the LUN affected by the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//------------------------------------------------------------------------------ +static unsigned char SBC_TestUnitReady(MSDLun *lun) +{ + unsigned char result = MSDD_STATUS_RW; + unsigned char senseKey = SBC_SENSE_KEY_NO_SENSE, + addSenseCode = 0, + addSenseCodeQual = 0; + Media *media = lun->media; + + // Check current media state + if (lun->status < LUN_CHANGED) { + + TRACE_INFO_WP("Ejc "); + senseKey = SBC_SENSE_KEY_NOT_READY; + addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; + } + else if (lun->status == LUN_CHANGED) { + + TRACE_INFO_WP("Chg "); + senseKey = SBC_SENSE_KEY_UNIT_ATTENTION; + addSenseCode = SBC_ASC_NOT_READY_TO_READY_CHANGE; + lun->status = LUN_READY; + } + else { + + switch(media->state) { + //------------------- + case MED_STATE_READY: + //------------------- + // Nothing to do + TRACE_INFO_WP("Rdy "); + result = MSDD_STATUS_SUCCESS; + break; + + //------------------ + case MED_STATE_BUSY: + //------------------ + TRACE_INFO_WP("Bsy "); + senseKey = SBC_SENSE_KEY_NOT_READY; + break; + + //------ + default: + //------ + TRACE_INFO_WP("? "); + senseKey = SBC_SENSE_KEY_NOT_READY; + addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; + break; + } + } + SBC_UpdateSenseData(&(lun->requestSenseData), + senseKey, + addSenseCode, + addSenseCodeQual); + + return result; +} + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +//! \brief Updates the sense data of a LUN with the given key and codes +//! \param requestSenseData Pointer to the sense data to update +//! \param senseKey Sense key +//! \param additionalSenseCode Additional sense code +//! \param additionalSenseCodeQualifier Additional sense code qualifier +//------------------------------------------------------------------------------ +void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, + unsigned char senseKey, + unsigned char additionalSenseCode, + unsigned char additionalSenseCodeQualifier) +{ + requestSenseData->bSenseKey = senseKey; + requestSenseData->bAdditionalSenseCode = additionalSenseCode; + requestSenseData->bAdditionalSenseCodeQualifier + = additionalSenseCodeQualifier; +} + +//------------------------------------------------------------------------------ +//! \brief Return information about the transfer length and direction expected +//! by the device for a particular command. +//! \param command Pointer to a buffer holding the command to evaluate +//! \param length Expected length of the data transfer +//! \param type Expected direction of data transfer +//! \param lun Pointer to the LUN affected by the command +//------------------------------------------------------------------------------ +unsigned char SBC_GetCommandInformation(void *command, + unsigned int *length, + unsigned char *type, + MSDLun *lun) +{ + SBCCommand *sbcCommand = (SBCCommand *) command; + unsigned char isCommandSupported = 1; + Media *media = lun->media; + + // Identify command + switch (sbcCommand->bOperationCode) { + //--------------- + case SBC_INQUIRY: + //--------------- + (*type) = MSDD_DEVICE_TO_HOST; + + // Allocation length is stored in big-endian format + (*length) = WORDB(sbcCommand->inquiry.pAllocationLength); + break; + + //-------------------- + case SBC_MODE_SENSE_6: + //-------------------- + (*type) = MSDD_DEVICE_TO_HOST; + if (sbcCommand->modeSense6.bAllocationLength > + sizeof(SBCModeParameterHeader6)) { + + *length = sizeof(SBCModeParameterHeader6); + } + else { + + *length = sbcCommand->modeSense6.bAllocationLength; + } + break; + + //------------------------------------ + case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: + case SBC_START_STOP: + //------------------------------------ + (*type) = MSDD_NO_TRANSFER; + break; + + //--------------------- + case SBC_REQUEST_SENSE: + //--------------------- + (*type) = MSDD_DEVICE_TO_HOST; + (*length) = sbcCommand->requestSense.bAllocationLength; + break; + + //----------------------- + case SBC_TEST_UNIT_READY: + //----------------------- + (*type) = MSDD_NO_TRANSFER; + break; + + //--------------------- + case SBC_READ_CAPACITY_10: + //--------------------- + (*type) = MSDD_DEVICE_TO_HOST; + (*length) = sizeof(SBCReadCapacity10Data); + break; + + //--------------- + case SBC_READ_10: + //--------------- + (*type) = MSDD_DEVICE_TO_HOST; + (*length) = WORDB(sbcCommand->read10.pTransferLength) + * lun->blockSize * media->blockSize; + break; + + //---------------- + case SBC_WRITE_10: + //---------------- + (*type) = MSDD_HOST_TO_DEVICE; + (*length) = WORDB(sbcCommand->write10.pTransferLength) + * lun->blockSize * media->blockSize; + break; + + //----------------- + case SBC_VERIFY_10: + //----------------- + (*type) = MSDD_NO_TRANSFER; + break; + #if 0 + //--------------------- + case SBC_READ_FORMAT_CAPACITIES: + //--------------------- + (*type) = MSDD_DEVICE_TO_HOST; + (*length) = 1; + break; + #endif + //------ + default: + //------ + isCommandSupported = 0; + } + + // If length is 0, no transfer is expected + if ((*length) == 0) { + + (*type) = MSDD_NO_TRANSFER; + } + + return isCommandSupported; +} + +//------------------------------------------------------------------------------ +//! \brief Processes a SBC command by dispatching it to a subfunction. +//! \param lun Pointer to the affected LUN +//! \param commandState Pointer to the current command state +//! \return Operation result code +//------------------------------------------------------------------------------ +unsigned char SBC_ProcessCommand(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char result = MSDD_STATUS_INCOMPLETE; + SBCCommand *command = (SBCCommand *) commandState->cbw.pCommand; + Media *media = lun->media; + + // Identify command + switch (command->bOperationCode) { + //--------------- + case SBC_READ_10: + //--------------- + TRACE_DEBUG_WP("Read(10) "); + + // Perform the Read10 command + result = SBC_Read10(lun, commandState); + break; + + //---------------- + case SBC_WRITE_10: + //---------------- + TRACE_DEBUG_WP("Write(10) "); + + // Perform the Write10 command + result = SBC_Write10(lun, commandState); + break; + + //--------------------- + case SBC_READ_CAPACITY_10: + //--------------------- + TRACE_INFO_WP("RdCapacity(10) "); + + // Perform the ReadCapacity command + result = SBC_ReadCapacity10(lun, commandState); + break; + + //--------------------- + case SBC_VERIFY_10: + //--------------------- + TRACE_INFO_WP("Verify(10) "); + + // Flush media + MED_Flush(media); + result = MSDD_STATUS_SUCCESS; + break; + + //--------------- + case SBC_INQUIRY: + //--------------- + TRACE_INFO_WP("Inquiry "); + + // Process Inquiry command + result = SBC_Inquiry(lun, commandState); + break; + + //-------------------- + case SBC_MODE_SENSE_6: + //-------------------- + TRACE_INFO_WP("ModeSense(6) "); + + // Process ModeSense6 command + result = SBC_ModeSense6(lun, commandState); + break; + + //----------------------- + case SBC_TEST_UNIT_READY: + //----------------------- + TRACE_INFO_WP("TstUnitRdy "); + + // Process TestUnitReady command + //MED_Flush(media); + result = SBC_TestUnitReady(lun); + break; + + //--------------------- + case SBC_REQUEST_SENSE: + //--------------------- + TRACE_INFO_WP("ReqSense "); + + // Perform the RequestSense command + result = SBC_RequestSense(lun, commandState); + break; + + //------------------------------------ + case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: + //------------------------------------ + TRACE_INFO_WP("PrevAllowRem "); + + // Check parameter + result = command->mediumRemoval.bPrevent ? + MSDD_STATUS_PARAMETER : MSDD_STATUS_SUCCESS; + result = MSDD_STATUS_SUCCESS; + break; + + case SBC_START_STOP: + TRACE_INFO_WP("StartStop "); + + result = command->startStopCmd.startStop ; + if (result == 0) { + lun->status = LUN_EJECTED ; + } + else { + lun->status = LUN_CHANGED ; + } + result = MSDD_STATUS_SUCCESS; + break; + + #if 0 + //------------------------------------ + case SBC_READ_FORMAT_CAPACITIES: + //------------------------------------ + TRACE_INFO_WP("RdFmtCap "); + result = MSDD_STATUS_RW; + break; + /* TODO BSS Added if (!SBCLunIsReady(lun)) { + + result = MSDD_STATUS_RW; + break; + } */ + #endif + //------ + default: + //------ + result = MSDD_STATUS_PARAMETER; + } + + return result; +} diff --git a/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.h b/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.h index 697ec46df..09d049ec6 100644 --- a/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.h +++ b/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.h @@ -1,110 +1,110 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// SCSI commands implementation. -/// -/// !Usage -/// -/// -# After a CBW is received from host, use SBC_GetCommandInformation to check -/// if the command is supported, and get the command length and type -/// information before processing it. -/// -# Then SBC_ProcessCommand can be used to handle a valid command, to -/// perform the command operations. -/// -# SBC_UpdateSenseData is used to update the sense data that will be sent -/// to host. -//------------------------------------------------------------------------------ - -#ifndef SBCMETHODS_H -#define SBCMETHODS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/device/massstorage/MSDDStateMachine.h" -#include "../../../usb/device/massstorage/SBC.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Command States" -/// This page lists the possible states of a SBC command. -/// -/// !States -/// - SBC_STATE_READ -/// - SBC_STATE_WAIT_READ -/// - SBC_STATE_WRITE -/// - SBC_STATE_WAIT_WRITE -/// - SBC_STATE_NEXT_BLOCK - -/// Start of reading bulk data -#define SBC_STATE_READ 0x01 -/// Waiting for the bulk data reading complete -#define SBC_STATE_WAIT_READ 0x02 -/// Read error state -#define SBC_STATE_READ_ERROR 0x03 -/// Start next read block -#define SBC_STATE_NEXT_READ 0x04 -/// Start writing bulk data to host -#define SBC_STATE_WRITE 0x05 -/// Waiting for the bulk data sending complete -#define SBC_STATE_WAIT_WRITE 0x06 -/// Write error state -#define SBC_STATE_WRITE_ERROR 0x07 -/// Start next write block -#define SBC_STATE_NEXT_WRITE 0x08 -/// Start next command block -#define SBC_STATE_NEXT_BLOCK 0x09 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, - unsigned char senseKey, - unsigned char additionalSenseCode, - unsigned char additionalSenseCodeQualifier); - -unsigned char SBC_GetCommandInformation(void *command, - unsigned int *length, - unsigned char *type, - MSDLun *lun); - -unsigned char SBC_ProcessCommand(MSDLun *lun, - MSDCommandState *commandState); - -#endif //#ifndef SBCMETHODS_H - +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// SCSI commands implementation. +/// +/// !Usage +/// +/// -# After a CBW is received from host, use SBC_GetCommandInformation to check +/// if the command is supported, and get the command length and type +/// information before processing it. +/// -# Then SBC_ProcessCommand can be used to handle a valid command, to +/// perform the command operations. +/// -# SBC_UpdateSenseData is used to update the sense data that will be sent +/// to host. +//------------------------------------------------------------------------------ + +#ifndef SBCMETHODS_H +#define SBCMETHODS_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "../../../usb/device/massstorage/MSDDStateMachine.h" +#include "../../../usb/device/massstorage/SBC.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Command States" +/// This page lists the possible states of a SBC command. +/// +/// !States +/// - SBC_STATE_READ +/// - SBC_STATE_WAIT_READ +/// - SBC_STATE_WRITE +/// - SBC_STATE_WAIT_WRITE +/// - SBC_STATE_NEXT_BLOCK + +/// Start of reading bulk data +#define SBC_STATE_READ 0x01 +/// Waiting for the bulk data reading complete +#define SBC_STATE_WAIT_READ 0x02 +/// Read error state +#define SBC_STATE_READ_ERROR 0x03 +/// Start next read block +#define SBC_STATE_NEXT_READ 0x04 +/// Start writing bulk data to host +#define SBC_STATE_WRITE 0x05 +/// Waiting for the bulk data sending complete +#define SBC_STATE_WAIT_WRITE 0x06 +/// Write error state +#define SBC_STATE_WRITE_ERROR 0x07 +/// Start next write block +#define SBC_STATE_NEXT_WRITE 0x08 +/// Start next command block +#define SBC_STATE_NEXT_BLOCK 0x09 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, + unsigned char senseKey, + unsigned char additionalSenseCode, + unsigned char additionalSenseCodeQualifier); + +unsigned char SBC_GetCommandInformation(void *command, + unsigned int *length, + unsigned char *type, + MSDLun *lun); + +unsigned char SBC_ProcessCommand(MSDLun *lun, + MSDCommandState *commandState); + +#endif //#ifndef SBCMETHODS_H + diff --git a/radio/src/targets/sky9x/vectors_sam3s.c b/radio/src/targets/sky9x/vectors_sam3s.c index 5644a24f6..b03d8cdca 100644 --- a/radio/src/targets/sky9x/vectors_sam3s.c +++ b/radio/src/targets/sky9x/vectors_sam3s.c @@ -18,156 +18,156 @@ * GNU General Public License for more details. */ -#define __VECTORS_SAM3S_C__ - -#include "debug.h" - -/*=========================================================================*/ -/* DEFINE: All extern Data */ -/*=========================================================================*/ -extern unsigned long _estack; - -/*=========================================================================*/ -/* DEFINE: Prototypes */ -/*=========================================================================*/ -void ResetHandler(void); - -void NMI_Handler (void) __attribute__((weak)); -void HardFault_Handler (void) __attribute__((weak)); -void MemManage_Handler (void) __attribute__((weak)); -void BusFault_Handler (void) __attribute__((weak)); -void UsageFault_Handler (void) __attribute__((weak)); -void SVC_Handler (void) __attribute__((weak)); -void DebugMon_Handler (void) __attribute__((weak)); -void PendSV_Handler(void) __attribute__((weak)); -void SysTick_Handler (void) __attribute__((weak)); -void SUPC_IRQHandler (void) __attribute__((weak)); -void RSTC_IRQHandler (void) __attribute__((weak)); -void RTC_IRQHandler (void) __attribute__((weak)); -void RTT_IRQHandler (void) __attribute__((weak)); -void WDT_IRQHandler (void) __attribute__((weak)); -void PMC_IRQHandler (void) __attribute__((weak)); -void EEFC_IRQHandler (void) __attribute__((weak)); -void UART0_IRQHandler (void) __attribute__((weak)); -void UART1_IRQHandler (void) __attribute__((weak)); -void SMC_IRQHandler (void) __attribute__((weak)); -void PIOA_IRQHandler (void) __attribute__((weak)); -void PIOB_IRQHandler (void) __attribute__((weak)); -void PIOC_IRQHandler (void) __attribute__((weak)); -void USART0_IRQHandler (void) __attribute__((weak)); -void USART1_IRQHandler (void) __attribute__((weak)); -void MCI_IRQHandler (void) __attribute__((weak)); -void TWI0_IRQHandler (void) __attribute__((weak)); -void TWI1_IRQHandler (void) __attribute__((weak)); -void SPI_IRQHandler (void) __attribute__((weak)); -void SSC_IRQHandler (void) __attribute__((weak)); -void TC0_IRQHandler (void) __attribute__((weak)); -void TC1_IRQHandler (void) __attribute__((weak)); -void TC2_IRQHandler (void) __attribute__((weak)); -void TC3_IRQHandler (void) __attribute__((weak)); -void TC4_IRQHandler (void) __attribute__((weak)); -void TC5_IRQHandler (void) __attribute__((weak)); -void ADC_IRQHandler (void) __attribute__((weak)); -void DAC_IRQHandler (void) __attribute__((weak)); -void PWM_IRQHandler (void) __attribute__((weak)); -void CRCCU_IRQHandler (void) __attribute__((weak)); -void ACC_IRQHandler (void) __attribute__((weak)); -void USBD_IrqHandler (void) __attribute__((weak)); - -/*=========================================================================*/ -/* DEFINE: All code exported */ -/*=========================================================================*/ -/* - * This is our vector table. - */ -__attribute__ ((section(".vectors"), used)) -void (* const gVectors[])(void) = -{ - (void (*)(void))((unsigned long)&_estack), - ResetHandler, - NMI_Handler, - HardFault_Handler, - MemManage_Handler, - BusFault_Handler, - UsageFault_Handler, - 0, 0, 0, 0, - SVC_Handler, - DebugMon_Handler, - 0, - PendSV_Handler, - SysTick_Handler, - - SUPC_IRQHandler, /* 0 SUPPLY CONTROLLER */ - RSTC_IRQHandler, /* 1 RESET CONTROLLER */ - RTC_IRQHandler, /* 2 REAL TIME CLOCK */ - RTT_IRQHandler, /* 3 REAL TIME TIMER */ - WDT_IRQHandler, /* 4 WATCHDOG TIMER */ - PMC_IRQHandler, /* 5 PMC */ - EEFC_IRQHandler, /* 6 EEFC */ - 0, /* 7 Reserved */ - UART0_IRQHandler, /* 8 UART0 */ - UART1_IRQHandler, /* 9 UART1 */ - SMC_IRQHandler, /* 10 SMC */ - PIOA_IRQHandler, /* 11 Parallel IO Controller A */ - PIOB_IRQHandler, /* 12 Parallel IO Controller B */ - PIOC_IRQHandler, /* 13 Parallel IO Controller C */ - USART0_IRQHandler, /* 14 USART 0 */ - USART1_IRQHandler, /* 15 USART 1 */ - 0, /* 16 Reserved */ - 0, /* 17 Reserved */ - MCI_IRQHandler, /* 18 MCI */ - TWI0_IRQHandler, /* 19 TWI 0 */ - TWI1_IRQHandler, /* 20 TWI 1 */ - SPI_IRQHandler, /* 21 SPI */ - SSC_IRQHandler, /* 22 SSC */ - TC0_IRQHandler, /* 23 Timer Counter 0 */ - TC1_IRQHandler, /* 24 Timer Counter 1 */ - TC2_IRQHandler, /* 25 Timer Counter 2 */ - TC3_IRQHandler, /* 26 Timer Counter 3 */ - TC4_IRQHandler, /* 27 Timer Counter 4 */ - TC5_IRQHandler, /* 28 Timer Counter 5 */ - ADC_IRQHandler, /* 29 ADC controller */ - DAC_IRQHandler, /* 30 DAC controller */ - PWM_IRQHandler, /* 31 PWM */ - CRCCU_IRQHandler, /* 32 CRC Calculation Unit */ - ACC_IRQHandler, /* 33 Analog Comparator */ - USBD_IrqHandler, /* 34 USB Device Port */ - 0 /* 35 not used */ -}; /* gVectors */ - -/* - * And here are the weak interrupt handlers. - */ -void NMI_Handler (void) { while(1); } -void HardFault_Handler (void) { while(1); } -void MemManage_Handler (void) { while(1); } -void BusFault_Handler (void) { while(1); } -void UsageFault_Handler (void) { while(1); } -void SVC_Handler (void) { while(1); } -void DebugMon_Handler (void) { while(1); } -void SUPC_IRQHandler (void) { while(1); } -void RSTC_IRQHandler (void) { while(1); } -void RTC_IRQHandler (void) { while(1); } -void RTT_IRQHandler (void) { while(1); } -void WDT_IRQHandler (void) { while(1); } -void PMC_IRQHandler (void) { while(1); } -void EEFC_IRQHandler (void) { while(1); } -void UART1_IRQHandler (void) { while(1); } -void SMC_IRQHandler (void) { while(1); } -void PIOA_IRQHandler (void) { while(1); } -void PIOB_IRQHandler (void) { while(1); } -void PIOC_IRQHandler (void) { while(1); } -void USART0_IRQHandler (void) { while(1); } -void USART1_IRQHandler (void) { while(1); } -void MCI_IRQHandler (void) { while(1); } -void TWI1_IRQHandler (void) { while(1); } -void SSC_IRQHandler (void) { while(1); } -void TC0_IRQHandler (void) { while(1); } -void TC1_IRQHandler (void) { while(1); } -void TC4_IRQHandler (void) { while(1); } -void TC5_IRQHandler (void) { while(1); } -void ADC_IRQHandler (void) { while(1); } -void CRCCU_IRQHandler (void) { while(1); } -void ACC_IRQHandler (void) { while(1); } - -/*** EOF ***/ +#define __VECTORS_SAM3S_C__ + +#include "debug.h" + +/*=========================================================================*/ +/* DEFINE: All extern Data */ +/*=========================================================================*/ +extern unsigned long _estack; + +/*=========================================================================*/ +/* DEFINE: Prototypes */ +/*=========================================================================*/ +void ResetHandler(void); + +void NMI_Handler (void) __attribute__((weak)); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak)); +void BusFault_Handler (void) __attribute__((weak)); +void UsageFault_Handler (void) __attribute__((weak)); +void SVC_Handler (void) __attribute__((weak)); +void DebugMon_Handler (void) __attribute__((weak)); +void PendSV_Handler(void) __attribute__((weak)); +void SysTick_Handler (void) __attribute__((weak)); +void SUPC_IRQHandler (void) __attribute__((weak)); +void RSTC_IRQHandler (void) __attribute__((weak)); +void RTC_IRQHandler (void) __attribute__((weak)); +void RTT_IRQHandler (void) __attribute__((weak)); +void WDT_IRQHandler (void) __attribute__((weak)); +void PMC_IRQHandler (void) __attribute__((weak)); +void EEFC_IRQHandler (void) __attribute__((weak)); +void UART0_IRQHandler (void) __attribute__((weak)); +void UART1_IRQHandler (void) __attribute__((weak)); +void SMC_IRQHandler (void) __attribute__((weak)); +void PIOA_IRQHandler (void) __attribute__((weak)); +void PIOB_IRQHandler (void) __attribute__((weak)); +void PIOC_IRQHandler (void) __attribute__((weak)); +void USART0_IRQHandler (void) __attribute__((weak)); +void USART1_IRQHandler (void) __attribute__((weak)); +void MCI_IRQHandler (void) __attribute__((weak)); +void TWI0_IRQHandler (void) __attribute__((weak)); +void TWI1_IRQHandler (void) __attribute__((weak)); +void SPI_IRQHandler (void) __attribute__((weak)); +void SSC_IRQHandler (void) __attribute__((weak)); +void TC0_IRQHandler (void) __attribute__((weak)); +void TC1_IRQHandler (void) __attribute__((weak)); +void TC2_IRQHandler (void) __attribute__((weak)); +void TC3_IRQHandler (void) __attribute__((weak)); +void TC4_IRQHandler (void) __attribute__((weak)); +void TC5_IRQHandler (void) __attribute__((weak)); +void ADC_IRQHandler (void) __attribute__((weak)); +void DAC_IRQHandler (void) __attribute__((weak)); +void PWM_IRQHandler (void) __attribute__((weak)); +void CRCCU_IRQHandler (void) __attribute__((weak)); +void ACC_IRQHandler (void) __attribute__((weak)); +void USBD_IrqHandler (void) __attribute__((weak)); + +/*=========================================================================*/ +/* DEFINE: All code exported */ +/*=========================================================================*/ +/* + * This is our vector table. + */ +__attribute__ ((section(".vectors"), used)) +void (* const gVectors[])(void) = +{ + (void (*)(void))((unsigned long)&_estack), + ResetHandler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, 0, 0, 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + + SUPC_IRQHandler, /* 0 SUPPLY CONTROLLER */ + RSTC_IRQHandler, /* 1 RESET CONTROLLER */ + RTC_IRQHandler, /* 2 REAL TIME CLOCK */ + RTT_IRQHandler, /* 3 REAL TIME TIMER */ + WDT_IRQHandler, /* 4 WATCHDOG TIMER */ + PMC_IRQHandler, /* 5 PMC */ + EEFC_IRQHandler, /* 6 EEFC */ + 0, /* 7 Reserved */ + UART0_IRQHandler, /* 8 UART0 */ + UART1_IRQHandler, /* 9 UART1 */ + SMC_IRQHandler, /* 10 SMC */ + PIOA_IRQHandler, /* 11 Parallel IO Controller A */ + PIOB_IRQHandler, /* 12 Parallel IO Controller B */ + PIOC_IRQHandler, /* 13 Parallel IO Controller C */ + USART0_IRQHandler, /* 14 USART 0 */ + USART1_IRQHandler, /* 15 USART 1 */ + 0, /* 16 Reserved */ + 0, /* 17 Reserved */ + MCI_IRQHandler, /* 18 MCI */ + TWI0_IRQHandler, /* 19 TWI 0 */ + TWI1_IRQHandler, /* 20 TWI 1 */ + SPI_IRQHandler, /* 21 SPI */ + SSC_IRQHandler, /* 22 SSC */ + TC0_IRQHandler, /* 23 Timer Counter 0 */ + TC1_IRQHandler, /* 24 Timer Counter 1 */ + TC2_IRQHandler, /* 25 Timer Counter 2 */ + TC3_IRQHandler, /* 26 Timer Counter 3 */ + TC4_IRQHandler, /* 27 Timer Counter 4 */ + TC5_IRQHandler, /* 28 Timer Counter 5 */ + ADC_IRQHandler, /* 29 ADC controller */ + DAC_IRQHandler, /* 30 DAC controller */ + PWM_IRQHandler, /* 31 PWM */ + CRCCU_IRQHandler, /* 32 CRC Calculation Unit */ + ACC_IRQHandler, /* 33 Analog Comparator */ + USBD_IrqHandler, /* 34 USB Device Port */ + 0 /* 35 not used */ +}; /* gVectors */ + +/* + * And here are the weak interrupt handlers. + */ +void NMI_Handler (void) { while(1); } +void HardFault_Handler (void) { while(1); } +void MemManage_Handler (void) { while(1); } +void BusFault_Handler (void) { while(1); } +void UsageFault_Handler (void) { while(1); } +void SVC_Handler (void) { while(1); } +void DebugMon_Handler (void) { while(1); } +void SUPC_IRQHandler (void) { while(1); } +void RSTC_IRQHandler (void) { while(1); } +void RTC_IRQHandler (void) { while(1); } +void RTT_IRQHandler (void) { while(1); } +void WDT_IRQHandler (void) { while(1); } +void PMC_IRQHandler (void) { while(1); } +void EEFC_IRQHandler (void) { while(1); } +void UART1_IRQHandler (void) { while(1); } +void SMC_IRQHandler (void) { while(1); } +void PIOA_IRQHandler (void) { while(1); } +void PIOB_IRQHandler (void) { while(1); } +void PIOC_IRQHandler (void) { while(1); } +void USART0_IRQHandler (void) { while(1); } +void USART1_IRQHandler (void) { while(1); } +void MCI_IRQHandler (void) { while(1); } +void TWI1_IRQHandler (void) { while(1); } +void SSC_IRQHandler (void) { while(1); } +void TC0_IRQHandler (void) { while(1); } +void TC1_IRQHandler (void) { while(1); } +void TC4_IRQHandler (void) { while(1); } +void TC5_IRQHandler (void) { while(1); } +void ADC_IRQHandler (void) { while(1); } +void CRCCU_IRQHandler (void) { while(1); } +void ACC_IRQHandler (void) { while(1); } + +/*** EOF ***/ diff --git a/radio/src/targets/taranis/backlight_driver.cpp b/radio/src/targets/taranis/backlight_driver.cpp index feddb269c..322a674d6 100644 --- a/radio/src/targets/taranis/backlight_driver.cpp +++ b/radio/src/targets/taranis/backlight_driver.cpp @@ -1,168 +1,168 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#if defined(PCBX9E) -void backlightInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN_1|BACKLIGHT_GPIO_PIN_2; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_1, BACKLIGHT_GPIO_AF_1); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_2, BACKLIGHT_GPIO_AF_1); - BACKLIGHT_TIMER->ARR = 100; - BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz - BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; // PWM - BACKLIGHT_TIMER->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E; - BACKLIGHT_TIMER->CCR2 = 0; - BACKLIGHT_TIMER->CCR1 = 100; - BACKLIGHT_TIMER->EGR = 0; - BACKLIGHT_TIMER->CR1 = TIM_CR1_CEN; // Counter enable -} - -void backlightEnable(uint8_t level, uint8_t color) -{ - BACKLIGHT_TIMER->CCR1 = ((100-level)*(20-color))/20; - BACKLIGHT_TIMER->CCR2 = ((100-level)*color)/20; -} - -void backlightDisable() -{ - BACKLIGHT_TIMER->CCR1 = 0; - BACKLIGHT_TIMER->CCR2 = 0; -} - -uint8_t isBacklightEnabled() -{ - return (BACKLIGHT_TIMER->CCR1 != 0 || BACKLIGHT_TIMER->CCR2 != 0); -} -#elif defined(PCBX9DP) -void backlightInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN_1|BACKLIGHT_GPIO_PIN_2; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_1, BACKLIGHT_GPIO_AF_1); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_2, BACKLIGHT_GPIO_AF_1); - BACKLIGHT_TIMER->ARR = 100; - BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz - BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; // PWM - BACKLIGHT_TIMER->CCMR2 = TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2; // PWM - BACKLIGHT_TIMER->CCER = TIM_CCER_CC4E | TIM_CCER_CC2E; - BACKLIGHT_TIMER->CCR2 = 0; - BACKLIGHT_TIMER->CCR4 = 100; - BACKLIGHT_TIMER->EGR = 0; - BACKLIGHT_TIMER->CR1 = TIM_CR1_CEN; // Counter enable -} - -void backlightEnable(uint8_t level, uint8_t color) -{ - BACKLIGHT_TIMER->CCR4 = ((100-level)*(20-color))/20; - BACKLIGHT_TIMER->CCR2 = ((100-level)*color)/20; -} - -void backlightDisable() -{ - BACKLIGHT_TIMER->CCR4 = 0; - BACKLIGHT_TIMER->CCR2 = 0; -} - -uint8_t isBacklightEnabled() -{ - return (BACKLIGHT_TIMER->CCR4 != 0 || BACKLIGHT_TIMER->CCR2 != 0); -} -#elif defined(PCBX7) -void backlightInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource, BACKLIGHT_GPIO_AF); - BACKLIGHT_TIMER->ARR = 100; - BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz - BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; // PWM - BACKLIGHT_TIMER->CCER = TIM_CCER_CC2E; - BACKLIGHT_TIMER->CCR2 = 100; - BACKLIGHT_TIMER->EGR = 0; - BACKLIGHT_TIMER->CR1 = TIM_CR1_CEN; // Counter enable -} - -void backlightEnable(uint8_t level) -{ - BACKLIGHT_TIMER->CCR2 = 100 - level; -} - -void backlightDisable() -{ - BACKLIGHT_TIMER->CCR2 = 0; -} - -uint8_t isBacklightEnabled() -{ - return BACKLIGHT_TIMER->CCR2 != 0; -} -#else -void backlightInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource, BACKLIGHT_GPIO_AF); - BACKLIGHT_TIMER->ARR = 100; - BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz - BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; // PWM - BACKLIGHT_TIMER->CCER = TIM_CCER_CC1E; - BACKLIGHT_TIMER->CCR1 = 80; - BACKLIGHT_TIMER->EGR = 0; - BACKLIGHT_TIMER->CR1 = 1; -} - -void backlightEnable(uint8_t level) -{ - BACKLIGHT_TIMER->CCR1 = 100 - level; -} - -void backlightDisable() -{ - BACKLIGHT_TIMER->CCR1 = 0; -} - -uint8_t isBacklightEnabled() -{ - return BACKLIGHT_TIMER->CCR1 != 0; -} -#endif +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#if defined(PCBX9E) +void backlightInit() +{ + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN_1|BACKLIGHT_GPIO_PIN_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); + GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_1, BACKLIGHT_GPIO_AF_1); + GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_2, BACKLIGHT_GPIO_AF_1); + BACKLIGHT_TIMER->ARR = 100; + BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz + BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; // PWM + BACKLIGHT_TIMER->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E; + BACKLIGHT_TIMER->CCR2 = 0; + BACKLIGHT_TIMER->CCR1 = 100; + BACKLIGHT_TIMER->EGR = 0; + BACKLIGHT_TIMER->CR1 = TIM_CR1_CEN; // Counter enable +} + +void backlightEnable(uint8_t level, uint8_t color) +{ + BACKLIGHT_TIMER->CCR1 = ((100-level)*(20-color))/20; + BACKLIGHT_TIMER->CCR2 = ((100-level)*color)/20; +} + +void backlightDisable() +{ + BACKLIGHT_TIMER->CCR1 = 0; + BACKLIGHT_TIMER->CCR2 = 0; +} + +uint8_t isBacklightEnabled() +{ + return (BACKLIGHT_TIMER->CCR1 != 0 || BACKLIGHT_TIMER->CCR2 != 0); +} +#elif defined(PCBX9DP) +void backlightInit() +{ + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN_1|BACKLIGHT_GPIO_PIN_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); + GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_1, BACKLIGHT_GPIO_AF_1); + GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_2, BACKLIGHT_GPIO_AF_1); + BACKLIGHT_TIMER->ARR = 100; + BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz + BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; // PWM + BACKLIGHT_TIMER->CCMR2 = TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2; // PWM + BACKLIGHT_TIMER->CCER = TIM_CCER_CC4E | TIM_CCER_CC2E; + BACKLIGHT_TIMER->CCR2 = 0; + BACKLIGHT_TIMER->CCR4 = 100; + BACKLIGHT_TIMER->EGR = 0; + BACKLIGHT_TIMER->CR1 = TIM_CR1_CEN; // Counter enable +} + +void backlightEnable(uint8_t level, uint8_t color) +{ + BACKLIGHT_TIMER->CCR4 = ((100-level)*(20-color))/20; + BACKLIGHT_TIMER->CCR2 = ((100-level)*color)/20; +} + +void backlightDisable() +{ + BACKLIGHT_TIMER->CCR4 = 0; + BACKLIGHT_TIMER->CCR2 = 0; +} + +uint8_t isBacklightEnabled() +{ + return (BACKLIGHT_TIMER->CCR4 != 0 || BACKLIGHT_TIMER->CCR2 != 0); +} +#elif defined(PCBX7) +void backlightInit() +{ + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); + GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource, BACKLIGHT_GPIO_AF); + BACKLIGHT_TIMER->ARR = 100; + BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz + BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; // PWM + BACKLIGHT_TIMER->CCER = TIM_CCER_CC2E; + BACKLIGHT_TIMER->CCR2 = 100; + BACKLIGHT_TIMER->EGR = 0; + BACKLIGHT_TIMER->CR1 = TIM_CR1_CEN; // Counter enable +} + +void backlightEnable(uint8_t level) +{ + BACKLIGHT_TIMER->CCR2 = 100 - level; +} + +void backlightDisable() +{ + BACKLIGHT_TIMER->CCR2 = 0; +} + +uint8_t isBacklightEnabled() +{ + return BACKLIGHT_TIMER->CCR2 != 0; +} +#else +void backlightInit() +{ + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); + GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource, BACKLIGHT_GPIO_AF); + BACKLIGHT_TIMER->ARR = 100; + BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz + BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; // PWM + BACKLIGHT_TIMER->CCER = TIM_CCER_CC1E; + BACKLIGHT_TIMER->CCR1 = 80; + BACKLIGHT_TIMER->EGR = 0; + BACKLIGHT_TIMER->CR1 = 1; +} + +void backlightEnable(uint8_t level) +{ + BACKLIGHT_TIMER->CCR1 = 100 - level; +} + +void backlightDisable() +{ + BACKLIGHT_TIMER->CCR1 = 0; +} + +uint8_t isBacklightEnabled() +{ + return BACKLIGHT_TIMER->CCR1 != 0; +} +#endif diff --git a/radio/src/targets/taranis/bluetooth_driver.cpp b/radio/src/targets/taranis/bluetooth_driver.cpp index 736be4657..3cbb66ce4 100644 --- a/radio/src/targets/taranis/bluetooth_driver.cpp +++ b/radio/src/targets/taranis/bluetooth_driver.cpp @@ -1,249 +1,249 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -Fifo btTxFifo; -Fifo btRxFifo; - -enum BluetoothState -{ - BLUETOOTH_INIT, - BLUETOOTH_WAIT_TTM, - BLUETOOTH_WAIT_BAUDRATE_CHANGE, - BLUETOOTH_OK, -}; - -enum BluetoothWriteState -{ - BLUETOOTH_WRITE_IDLE, - BLUETOOTH_WRITE_INIT, - BLUETOOTH_WRITING, - BLUETOOTH_WRITE_DONE -}; - -volatile uint8_t bluetoothState = BLUETOOTH_INIT; -volatile uint8_t bluetoothWriteState = BLUETOOTH_WRITE_IDLE; - -void bluetoothInit(uint32_t baudrate) -{ - GPIO_InitTypeDef GPIO_InitStructure; - USART_InitTypeDef USART_InitStructure; - - USART_DeInit(BT_USART); - - RCC_AHB1PeriphClockCmd(BT_RCC_AHB1Periph, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); - - GPIO_InitStructure.GPIO_Pin = BT_EN_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BT_EN_GPIO, &GPIO_InitStructure); - -#if defined(BT_BRTS_GPIO_PIN) - GPIO_InitStructure.GPIO_Pin = BT_BRTS_GPIO_PIN; - GPIO_Init(BT_BRTS_GPIO, &GPIO_InitStructure); - GPIO_SetBits(BT_BRTS_GPIO, BT_BRTS_GPIO_PIN); -#endif - -#if defined(BT_BCTS_GPIO_PIN) - GPIO_InitStructure.GPIO_Pin = BT_BCTS_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_Init(BT_BCTS_GPIO, &GPIO_InitStructure); -#endif - - GPIO_InitStructure.GPIO_Pin = BT_TX_GPIO_PIN|BT_RX_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(BT_GPIO_TXRX, &GPIO_InitStructure); - - GPIO_PinAFConfig(BT_GPIO_TXRX, BT_TX_GPIO_PinSource, BT_GPIO_AF); - GPIO_PinAFConfig(BT_GPIO_TXRX, BT_RX_GPIO_PinSource, BT_GPIO_AF); - - USART_DeInit(BT_USART); - USART_InitStructure.USART_BaudRate = baudrate; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(BT_USART, &USART_InitStructure); - - USART_Cmd(BT_USART, ENABLE); - USART_ITConfig(BT_USART, USART_IT_RXNE, ENABLE); - - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = BT_USART_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 8; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - GPIO_ResetBits(BT_EN_GPIO, BT_EN_GPIO_PIN); // open bluetooth -} - -void bluetoothDone() -{ - GPIO_SetBits(BT_EN_GPIO, BT_EN_GPIO_PIN); // close bluetooth -} - -extern "C" void USART6_IRQHandler(void) -{ - DEBUG_INTERRUPT(INT_BLUETOOTH); - if (USART_GetITStatus(BT_USART, USART_IT_RXNE) != RESET) { - USART_ClearITPendingBit(BT_USART, USART_IT_RXNE); - uint8_t byte = USART_ReceiveData(BT_USART); - btRxFifo.push(byte); - } - - if (USART_GetITStatus(BT_USART, USART_IT_TXE) != RESET) { - uint8_t byte; - bool result = btTxFifo.pop(byte); - if (result) { - USART_SendData(BT_USART, byte); - } - else { - USART_ITConfig(BT_USART, USART_IT_TXE, DISABLE); - bluetoothWriteState = BLUETOOTH_WRITE_DONE; - } - } -} - -void bluetoothWrite(const void * buffer, int len) -{ - uint8_t * data = (uint8_t *)buffer; - for (int i=0; i waitEnd) { - char ttm[] = "TTM:REN"; - int index = 0; - uint8_t c; - bool found = false; - while (btRxFifo.pop(c)) { - if (c == ttm[index]) { - index++; - if (index == sizeof(ttm)-1) { - found = true; - break; - } - } - else { - index = 0; - } - } - if (found) { - bluetoothState = BLUETOOTH_OK; - } - else { - bluetoothInit(BLUETOOTH_FACTORY_BAUDRATE); - const char btMessage[] = "TTM:BPS-115200"; - bluetoothWriteString(btMessage); - bluetoothState = BLUETOOTH_WAIT_BAUDRATE_CHANGE; - waitEnd = get_tmr10ms() + 250; // 2.5s - } - } - } - else if (bluetoothState == BLUETOOTH_WAIT_BAUDRATE_CHANGE) { - if (get_tmr10ms() > waitEnd) { - bluetoothState = BLUETOOTH_INIT; - } - } - } - - bluetoothWriteWakeup(); - } -} - -uint8_t bluetoothReady() -{ - return (bluetoothState == BLUETOOTH_OK); -} - -int bluetoothRead(void * buffer, int len) -{ - int result = 0; - uint8_t * data = (uint8_t *)buffer; - while (result < len) { - uint8_t byte; - if (!btRxFifo.pop(byte)) { - break; - } - data[result++] = byte; - } - return result; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +Fifo btTxFifo; +Fifo btRxFifo; + +enum BluetoothState +{ + BLUETOOTH_INIT, + BLUETOOTH_WAIT_TTM, + BLUETOOTH_WAIT_BAUDRATE_CHANGE, + BLUETOOTH_OK, +}; + +enum BluetoothWriteState +{ + BLUETOOTH_WRITE_IDLE, + BLUETOOTH_WRITE_INIT, + BLUETOOTH_WRITING, + BLUETOOTH_WRITE_DONE +}; + +volatile uint8_t bluetoothState = BLUETOOTH_INIT; +volatile uint8_t bluetoothWriteState = BLUETOOTH_WRITE_IDLE; + +void bluetoothInit(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + + USART_DeInit(BT_USART); + + RCC_AHB1PeriphClockCmd(BT_RCC_AHB1Periph, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); + + GPIO_InitStructure.GPIO_Pin = BT_EN_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(BT_EN_GPIO, &GPIO_InitStructure); + +#if defined(BT_BRTS_GPIO_PIN) + GPIO_InitStructure.GPIO_Pin = BT_BRTS_GPIO_PIN; + GPIO_Init(BT_BRTS_GPIO, &GPIO_InitStructure); + GPIO_SetBits(BT_BRTS_GPIO, BT_BRTS_GPIO_PIN); +#endif + +#if defined(BT_BCTS_GPIO_PIN) + GPIO_InitStructure.GPIO_Pin = BT_BCTS_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_Init(BT_BCTS_GPIO, &GPIO_InitStructure); +#endif + + GPIO_InitStructure.GPIO_Pin = BT_TX_GPIO_PIN|BT_RX_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(BT_GPIO_TXRX, &GPIO_InitStructure); + + GPIO_PinAFConfig(BT_GPIO_TXRX, BT_TX_GPIO_PinSource, BT_GPIO_AF); + GPIO_PinAFConfig(BT_GPIO_TXRX, BT_RX_GPIO_PinSource, BT_GPIO_AF); + + USART_DeInit(BT_USART); + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(BT_USART, &USART_InitStructure); + + USART_Cmd(BT_USART, ENABLE); + USART_ITConfig(BT_USART, USART_IT_RXNE, ENABLE); + + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = BT_USART_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 8; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + GPIO_ResetBits(BT_EN_GPIO, BT_EN_GPIO_PIN); // open bluetooth +} + +void bluetoothDone() +{ + GPIO_SetBits(BT_EN_GPIO, BT_EN_GPIO_PIN); // close bluetooth +} + +extern "C" void USART6_IRQHandler(void) +{ + DEBUG_INTERRUPT(INT_BLUETOOTH); + if (USART_GetITStatus(BT_USART, USART_IT_RXNE) != RESET) { + USART_ClearITPendingBit(BT_USART, USART_IT_RXNE); + uint8_t byte = USART_ReceiveData(BT_USART); + btRxFifo.push(byte); + } + + if (USART_GetITStatus(BT_USART, USART_IT_TXE) != RESET) { + uint8_t byte; + bool result = btTxFifo.pop(byte); + if (result) { + USART_SendData(BT_USART, byte); + } + else { + USART_ITConfig(BT_USART, USART_IT_TXE, DISABLE); + bluetoothWriteState = BLUETOOTH_WRITE_DONE; + } + } +} + +void bluetoothWrite(const void * buffer, int len) +{ + uint8_t * data = (uint8_t *)buffer; + for (int i=0; i waitEnd) { + char ttm[] = "TTM:REN"; + int index = 0; + uint8_t c; + bool found = false; + while (btRxFifo.pop(c)) { + if (c == ttm[index]) { + index++; + if (index == sizeof(ttm)-1) { + found = true; + break; + } + } + else { + index = 0; + } + } + if (found) { + bluetoothState = BLUETOOTH_OK; + } + else { + bluetoothInit(BLUETOOTH_FACTORY_BAUDRATE); + const char btMessage[] = "TTM:BPS-115200"; + bluetoothWriteString(btMessage); + bluetoothState = BLUETOOTH_WAIT_BAUDRATE_CHANGE; + waitEnd = get_tmr10ms() + 250; // 2.5s + } + } + } + else if (bluetoothState == BLUETOOTH_WAIT_BAUDRATE_CHANGE) { + if (get_tmr10ms() > waitEnd) { + bluetoothState = BLUETOOTH_INIT; + } + } + } + + bluetoothWriteWakeup(); + } +} + +uint8_t bluetoothReady() +{ + return (bluetoothState == BLUETOOTH_OK); +} + +int bluetoothRead(void * buffer, int len) +{ + int result = 0; + uint8_t * data = (uint8_t *)buffer; + while (result < len) { + uint8_t byte; + if (!btRxFifo.pop(byte)) { + break; + } + data[result++] = byte; + } + return result; +} diff --git a/radio/src/targets/taranis/board.cpp b/radio/src/targets/taranis/board.cpp index bb1be46ae..b0bdb53b6 100644 --- a/radio/src/targets/taranis/board.cpp +++ b/radio/src/targets/taranis/board.cpp @@ -1,325 +1,325 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#if defined(__cplusplus) && !defined(SIMU) -extern "C" { -#endif -#include "usb_dcd_int.h" -#include "usb_bsp.h" -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -void watchdogInit(unsigned int duration) -{ - IWDG->KR = 0x5555; // Unlock registers - IWDG->PR = 3; // Divide by 32 => 1kHz clock - IWDG->KR = 0x5555; // Unlock registers - IWDG->RLR = duration; // 1.5 seconds nominal - IWDG->KR = 0xAAAA; // reload - IWDG->KR = 0xCCCC; // start -} - -// Starts TIMER at 2MHz -void init2MhzTimer() -{ - TIMER_2MHz_TIMER->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 2000000 - 1 ; // 0.5 uS, 2 MHz - TIMER_2MHz_TIMER->ARR = 65535; - TIMER_2MHz_TIMER->CR2 = 0; - TIMER_2MHz_TIMER->CR1 = TIM_CR1_CEN; -} - -// Starts TIMER at 200Hz (5ms) -void init5msTimer() -{ - INTERRUPT_5MS_TIMER->ARR = 4999 ; // 5mS - INTERRUPT_5MS_TIMER->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 1000000 - 1 ; // 1uS from 30MHz - INTERRUPT_5MS_TIMER->CCER = 0 ; - INTERRUPT_5MS_TIMER->CCMR1 = 0 ; - INTERRUPT_5MS_TIMER->EGR = 0 ; - INTERRUPT_5MS_TIMER->CR1 = 5 ; - INTERRUPT_5MS_TIMER->DIER |= 1 ; - NVIC_EnableIRQ(INTERRUPT_5MS_IRQn) ; - NVIC_SetPriority(INTERRUPT_5MS_IRQn, 7); -} - -void stop5msTimer( void ) -{ - INTERRUPT_5MS_TIMER->CR1 = 0 ; // stop timer - NVIC_DisableIRQ(INTERRUPT_5MS_IRQn) ; -} - -// TODO use the same than board_sky9x.cpp -void interrupt5ms() -{ - static uint32_t pre_scale ; // Used to get 10 Hz counter - - AUDIO_HEARTBEAT(); - -#if defined(HAPTIC) - HAPTIC_HEARTBEAT(); -#endif - - if (++pre_scale >= 2) { - pre_scale = 0 ; - DEBUG_TIMER_START(debugTimerPer10ms); - per10ms(); - DEBUG_TIMER_STOP(debugTimerPer10ms); - } - -#if defined(ROTARY_ENCODER_NAVIGATION) - checkRotaryEncoder(); -#endif -} - -#if !defined(SIMU) -extern "C" void INTERRUPT_5MS_IRQHandler() -{ - INTERRUPT_5MS_TIMER->SR &= ~TIM_SR_UIF ; - interrupt5ms() ; - DEBUG_INTERRUPT(INT_5MS); -} -#endif - -#if defined(PCBX9E) && !defined(SIMU) -#define PWR_PRESS_DURATION_MIN 200 // 2s -#define PWR_PRESS_DURATION_MAX 500 // 5s - -const pm_uchar bmp_startup[] PROGMEM = { - #include "startup.lbm" -}; - -const pm_uchar bmp_lock[] PROGMEM = { - #include "lock.lbm" -}; -#endif // defined(PCBX9E) && !defined(SIMU) - -#if defined(PCBX7) -void sportUpdateInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = SPORT_UPDATE_PWR_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(SPORT_UPDATE_PWR_GPIO, &GPIO_InitStructure); -} - -void sportUpdatePowerOn() -{ - if (IS_PCBREV_40()) - GPIO_SetBits(SPORT_UPDATE_PWR_GPIO, SPORT_UPDATE_PWR_GPIO_PIN); - else - EXTERNAL_MODULE_ON(); -} - -void sportUpdatePowerOff() -{ - if (IS_PCBREV_40()) - GPIO_ResetBits(SPORT_UPDATE_PWR_GPIO, SPORT_UPDATE_PWR_GPIO_PIN); - else - EXTERNAL_MODULE_OFF(); -} -#endif - -void boardInit() -{ -#if !defined(SIMU) - RCC_AHB1PeriphClockCmd(PWR_RCC_AHB1Periph | PCBREV_RCC_AHB1Periph | KEYS_RCC_AHB1Periph | LCD_RCC_AHB1Periph | AUDIO_RCC_AHB1Periph | BACKLIGHT_RCC_AHB1Periph | ADC_RCC_AHB1Periph | I2C_RCC_AHB1Periph | SD_RCC_AHB1Periph | HAPTIC_RCC_AHB1Periph | INTMODULE_RCC_AHB1Periph | EXTMODULE_RCC_AHB1Periph | TELEMETRY_RCC_AHB1Periph | SPORT_UPDATE_RCC_AHB1Periph | SERIAL_RCC_AHB1Periph | TRAINER_RCC_AHB1Periph | HEARTBEAT_RCC_AHB1Periph, ENABLE); - RCC_APB1PeriphClockCmd(LCD_RCC_APB1Periph | AUDIO_RCC_APB1Periph | BACKLIGHT_RCC_APB1Periph | INTERRUPT_5MS_APB1Periph | TIMER_2MHz_APB1Periph | I2C_RCC_APB1Periph | SD_RCC_APB1Periph | TRAINER_RCC_APB1Periph | TELEMETRY_RCC_APB1Periph | SERIAL_RCC_APB1Periph, ENABLE); - RCC_APB2PeriphClockCmd(BACKLIGHT_RCC_APB2Periph | ADC_RCC_APB2Periph | HAPTIC_RCC_APB2Periph | INTMODULE_RCC_APB2Periph | EXTMODULE_RCC_APB2Periph | HEARTBEAT_RCC_APB2Periph, ENABLE); - -#if !defined(PCBX9E) - // some X9E boards need that the pwrInit() is moved a little bit later - pwrInit(); -#endif - -#if defined(PCBX7) - ledInit(); - ledGreen(); -#endif - - keysInit(); - adcInit(); - delaysInit(); - lcdInit(); // delaysInit() must be called before - audioInit(); - init2MhzTimer(); - init5msTimer(); - __enable_irq(); - i2cInit(); - usbInit(); - -#if defined(DEBUG) && !defined(PCBX7) - serial2Init(0, 0); // default serial mode (None if DEBUG not defined) - TRACE("\nTaranis board started :)"); -#endif - -#if defined(HAPTIC) - hapticInit(); -#endif - -#if defined(PCBX9E) || defined(PCBX7) - bluetoothInit(BLUETOOTH_DEFAULT_BAUDRATE); -#endif - -#if defined(DEBUG) - DBGMCU_APB1PeriphConfig(DBGMCU_IWDG_STOP|DBGMCU_TIM1_STOP|DBGMCU_TIM2_STOP|DBGMCU_TIM3_STOP|DBGMCU_TIM6_STOP|DBGMCU_TIM8_STOP|DBGMCU_TIM10_STOP|DBGMCU_TIM13_STOP|DBGMCU_TIM14_STOP, ENABLE); -#endif - -#if defined(PCBX9E) - if (!WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { - lcdClear(); - lcdDrawBitmap(76, 2, bmp_lock, 0, 60); - lcdRefresh(); - lcdRefreshWait(); - - tmr10ms_t start = get_tmr10ms(); - tmr10ms_t duration = 0; - uint8_t pwr_on = 0; - while (pwrPressed()) { - duration = get_tmr10ms() - start; - if (duration < PWR_PRESS_DURATION_MIN) { - unsigned index = duration / (PWR_PRESS_DURATION_MIN / 4); - lcdClear(); - lcdDrawBitmap(76, 2, bmp_startup, index*60, 60); - } - else if (duration >= PWR_PRESS_DURATION_MAX) { - drawSleepBitmap(); - backlightDisable(); - } - else { - if (pwr_on != 1) { - pwr_on = 1; - pwrInit(); - backlightInit(); - haptic.play(15, 3, PLAY_NOW); - } - } - lcdRefresh(); - lcdRefreshWait(); - } - if (duration < PWR_PRESS_DURATION_MIN || duration >= PWR_PRESS_DURATION_MAX) { - boardOff(); - } - } - else { - pwrInit(); - backlightInit(); - } - toplcdInit(); -#else - backlightInit(); -#endif - -#if defined(PCBX7) - if (IS_PCBREV_40()) { - sportUpdateInit(); - } -#endif - -#endif // !defined(SIMU) -} - -void boardOff() -{ -#if defined(PCBX7) - ledOff(); -#endif - - BACKLIGHT_DISABLE(); - -#if defined(PCBX9E) - toplcdOff(); -#endif - -#if defined(PCBX9E) || defined(PCBX7) - while (pwrPressed()) { - wdt_reset(); - } -#endif - - lcdOff(); - SysTick->CTRL = 0; // turn off systick - pwrOff(); -} - -uint8_t currentTrainerMode = 0xff; - -void checkTrainerSettings() -{ - uint8_t requiredTrainerMode = g_model.trainerMode; - if (requiredTrainerMode != currentTrainerMode) { - switch (currentTrainerMode) { - case TRAINER_MODE_MASTER_TRAINER_JACK: - stop_trainer_capture(); - break; - case TRAINER_MODE_SLAVE: - stop_trainer_ppm(); - break; - case TRAINER_MODE_MASTER_CPPM_EXTERNAL_MODULE: - stop_cppm_on_heartbeat_capture() ; - break; - case TRAINER_MODE_MASTER_SBUS_EXTERNAL_MODULE: - stop_sbus_on_heartbeat_capture() ; - break; -#if defined(SERIAL2) - case TRAINER_MODE_MASTER_BATTERY_COMPARTMENT: - serial2Stop(); -#endif - } - - currentTrainerMode = requiredTrainerMode; - switch (requiredTrainerMode) { - case TRAINER_MODE_SLAVE: - init_trainer_ppm(); - break; - case TRAINER_MODE_MASTER_CPPM_EXTERNAL_MODULE: - init_cppm_on_heartbeat_capture() ; - break; - case TRAINER_MODE_MASTER_SBUS_EXTERNAL_MODULE: - init_sbus_on_heartbeat_capture() ; - break; -#if defined(SERIAL2) - case TRAINER_MODE_MASTER_BATTERY_COMPARTMENT: - if (g_eeGeneral.serial2Mode == UART_MODE_SBUS_TRAINER) { - serial2SbusInit(); - break; - } - // no break -#endif - default: - // master is default - init_trainer_capture(); - break; - } - } -} - -uint16_t getBatteryVoltage() -{ - int32_t instant_vbat = anaIn(TX_VOLTAGE); // using filtered ADC value on purpose - instant_vbat = (instant_vbat * BATT_SCALE * (128 + g_eeGeneral.txVoltageCalibration) ) / 26214; - instant_vbat += 20; // add 0.2V because of the diode TODO check if this is needed, but removal will beak existing calibrations!!! - return (uint16_t)instant_vbat; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#if defined(__cplusplus) && !defined(SIMU) +extern "C" { +#endif +#include "usb_dcd_int.h" +#include "usb_bsp.h" +#if defined(__cplusplus) && !defined(SIMU) +} +#endif + +void watchdogInit(unsigned int duration) +{ + IWDG->KR = 0x5555; // Unlock registers + IWDG->PR = 3; // Divide by 32 => 1kHz clock + IWDG->KR = 0x5555; // Unlock registers + IWDG->RLR = duration; // 1.5 seconds nominal + IWDG->KR = 0xAAAA; // reload + IWDG->KR = 0xCCCC; // start +} + +// Starts TIMER at 2MHz +void init2MhzTimer() +{ + TIMER_2MHz_TIMER->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 2000000 - 1 ; // 0.5 uS, 2 MHz + TIMER_2MHz_TIMER->ARR = 65535; + TIMER_2MHz_TIMER->CR2 = 0; + TIMER_2MHz_TIMER->CR1 = TIM_CR1_CEN; +} + +// Starts TIMER at 200Hz (5ms) +void init5msTimer() +{ + INTERRUPT_5MS_TIMER->ARR = 4999 ; // 5mS + INTERRUPT_5MS_TIMER->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 1000000 - 1 ; // 1uS from 30MHz + INTERRUPT_5MS_TIMER->CCER = 0 ; + INTERRUPT_5MS_TIMER->CCMR1 = 0 ; + INTERRUPT_5MS_TIMER->EGR = 0 ; + INTERRUPT_5MS_TIMER->CR1 = 5 ; + INTERRUPT_5MS_TIMER->DIER |= 1 ; + NVIC_EnableIRQ(INTERRUPT_5MS_IRQn) ; + NVIC_SetPriority(INTERRUPT_5MS_IRQn, 7); +} + +void stop5msTimer( void ) +{ + INTERRUPT_5MS_TIMER->CR1 = 0 ; // stop timer + NVIC_DisableIRQ(INTERRUPT_5MS_IRQn) ; +} + +// TODO use the same than board_sky9x.cpp +void interrupt5ms() +{ + static uint32_t pre_scale ; // Used to get 10 Hz counter + + AUDIO_HEARTBEAT(); + +#if defined(HAPTIC) + HAPTIC_HEARTBEAT(); +#endif + + if (++pre_scale >= 2) { + pre_scale = 0 ; + DEBUG_TIMER_START(debugTimerPer10ms); + per10ms(); + DEBUG_TIMER_STOP(debugTimerPer10ms); + } + +#if defined(ROTARY_ENCODER_NAVIGATION) + checkRotaryEncoder(); +#endif +} + +#if !defined(SIMU) +extern "C" void INTERRUPT_5MS_IRQHandler() +{ + INTERRUPT_5MS_TIMER->SR &= ~TIM_SR_UIF ; + interrupt5ms() ; + DEBUG_INTERRUPT(INT_5MS); +} +#endif + +#if defined(PCBX9E) && !defined(SIMU) +#define PWR_PRESS_DURATION_MIN 200 // 2s +#define PWR_PRESS_DURATION_MAX 500 // 5s + +const pm_uchar bmp_startup[] PROGMEM = { + #include "startup.lbm" +}; + +const pm_uchar bmp_lock[] PROGMEM = { + #include "lock.lbm" +}; +#endif // defined(PCBX9E) && !defined(SIMU) + +#if defined(PCBX7) +void sportUpdateInit() +{ + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = SPORT_UPDATE_PWR_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(SPORT_UPDATE_PWR_GPIO, &GPIO_InitStructure); +} + +void sportUpdatePowerOn() +{ + if (IS_PCBREV_40()) + GPIO_SetBits(SPORT_UPDATE_PWR_GPIO, SPORT_UPDATE_PWR_GPIO_PIN); + else + EXTERNAL_MODULE_ON(); +} + +void sportUpdatePowerOff() +{ + if (IS_PCBREV_40()) + GPIO_ResetBits(SPORT_UPDATE_PWR_GPIO, SPORT_UPDATE_PWR_GPIO_PIN); + else + EXTERNAL_MODULE_OFF(); +} +#endif + +void boardInit() +{ +#if !defined(SIMU) + RCC_AHB1PeriphClockCmd(PWR_RCC_AHB1Periph | PCBREV_RCC_AHB1Periph | KEYS_RCC_AHB1Periph | LCD_RCC_AHB1Periph | AUDIO_RCC_AHB1Periph | BACKLIGHT_RCC_AHB1Periph | ADC_RCC_AHB1Periph | I2C_RCC_AHB1Periph | SD_RCC_AHB1Periph | HAPTIC_RCC_AHB1Periph | INTMODULE_RCC_AHB1Periph | EXTMODULE_RCC_AHB1Periph | TELEMETRY_RCC_AHB1Periph | SPORT_UPDATE_RCC_AHB1Periph | SERIAL_RCC_AHB1Periph | TRAINER_RCC_AHB1Periph | HEARTBEAT_RCC_AHB1Periph, ENABLE); + RCC_APB1PeriphClockCmd(LCD_RCC_APB1Periph | AUDIO_RCC_APB1Periph | BACKLIGHT_RCC_APB1Periph | INTERRUPT_5MS_APB1Periph | TIMER_2MHz_APB1Periph | I2C_RCC_APB1Periph | SD_RCC_APB1Periph | TRAINER_RCC_APB1Periph | TELEMETRY_RCC_APB1Periph | SERIAL_RCC_APB1Periph, ENABLE); + RCC_APB2PeriphClockCmd(BACKLIGHT_RCC_APB2Periph | ADC_RCC_APB2Periph | HAPTIC_RCC_APB2Periph | INTMODULE_RCC_APB2Periph | EXTMODULE_RCC_APB2Periph | HEARTBEAT_RCC_APB2Periph, ENABLE); + +#if !defined(PCBX9E) + // some X9E boards need that the pwrInit() is moved a little bit later + pwrInit(); +#endif + +#if defined(PCBX7) + ledInit(); + ledGreen(); +#endif + + keysInit(); + adcInit(); + delaysInit(); + lcdInit(); // delaysInit() must be called before + audioInit(); + init2MhzTimer(); + init5msTimer(); + __enable_irq(); + i2cInit(); + usbInit(); + +#if defined(DEBUG) && !defined(PCBX7) + serial2Init(0, 0); // default serial mode (None if DEBUG not defined) + TRACE("\nTaranis board started :)"); +#endif + +#if defined(HAPTIC) + hapticInit(); +#endif + +#if defined(PCBX9E) || defined(PCBX7) + bluetoothInit(BLUETOOTH_DEFAULT_BAUDRATE); +#endif + +#if defined(DEBUG) + DBGMCU_APB1PeriphConfig(DBGMCU_IWDG_STOP|DBGMCU_TIM1_STOP|DBGMCU_TIM2_STOP|DBGMCU_TIM3_STOP|DBGMCU_TIM6_STOP|DBGMCU_TIM8_STOP|DBGMCU_TIM10_STOP|DBGMCU_TIM13_STOP|DBGMCU_TIM14_STOP, ENABLE); +#endif + +#if defined(PCBX9E) + if (!WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { + lcdClear(); + lcdDrawBitmap(76, 2, bmp_lock, 0, 60); + lcdRefresh(); + lcdRefreshWait(); + + tmr10ms_t start = get_tmr10ms(); + tmr10ms_t duration = 0; + uint8_t pwr_on = 0; + while (pwrPressed()) { + duration = get_tmr10ms() - start; + if (duration < PWR_PRESS_DURATION_MIN) { + unsigned index = duration / (PWR_PRESS_DURATION_MIN / 4); + lcdClear(); + lcdDrawBitmap(76, 2, bmp_startup, index*60, 60); + } + else if (duration >= PWR_PRESS_DURATION_MAX) { + drawSleepBitmap(); + backlightDisable(); + } + else { + if (pwr_on != 1) { + pwr_on = 1; + pwrInit(); + backlightInit(); + haptic.play(15, 3, PLAY_NOW); + } + } + lcdRefresh(); + lcdRefreshWait(); + } + if (duration < PWR_PRESS_DURATION_MIN || duration >= PWR_PRESS_DURATION_MAX) { + boardOff(); + } + } + else { + pwrInit(); + backlightInit(); + } + toplcdInit(); +#else + backlightInit(); +#endif + +#if defined(PCBX7) + if (IS_PCBREV_40()) { + sportUpdateInit(); + } +#endif + +#endif // !defined(SIMU) +} + +void boardOff() +{ +#if defined(PCBX7) + ledOff(); +#endif + + BACKLIGHT_DISABLE(); + +#if defined(PCBX9E) + toplcdOff(); +#endif + +#if defined(PCBX9E) || defined(PCBX7) + while (pwrPressed()) { + wdt_reset(); + } +#endif + + lcdOff(); + SysTick->CTRL = 0; // turn off systick + pwrOff(); +} + +uint8_t currentTrainerMode = 0xff; + +void checkTrainerSettings() +{ + uint8_t requiredTrainerMode = g_model.trainerMode; + if (requiredTrainerMode != currentTrainerMode) { + switch (currentTrainerMode) { + case TRAINER_MODE_MASTER_TRAINER_JACK: + stop_trainer_capture(); + break; + case TRAINER_MODE_SLAVE: + stop_trainer_ppm(); + break; + case TRAINER_MODE_MASTER_CPPM_EXTERNAL_MODULE: + stop_cppm_on_heartbeat_capture() ; + break; + case TRAINER_MODE_MASTER_SBUS_EXTERNAL_MODULE: + stop_sbus_on_heartbeat_capture() ; + break; +#if defined(SERIAL2) + case TRAINER_MODE_MASTER_BATTERY_COMPARTMENT: + serial2Stop(); +#endif + } + + currentTrainerMode = requiredTrainerMode; + switch (requiredTrainerMode) { + case TRAINER_MODE_SLAVE: + init_trainer_ppm(); + break; + case TRAINER_MODE_MASTER_CPPM_EXTERNAL_MODULE: + init_cppm_on_heartbeat_capture() ; + break; + case TRAINER_MODE_MASTER_SBUS_EXTERNAL_MODULE: + init_sbus_on_heartbeat_capture() ; + break; +#if defined(SERIAL2) + case TRAINER_MODE_MASTER_BATTERY_COMPARTMENT: + if (g_eeGeneral.serial2Mode == UART_MODE_SBUS_TRAINER) { + serial2SbusInit(); + break; + } + // no break +#endif + default: + // master is default + init_trainer_capture(); + break; + } + } +} + +uint16_t getBatteryVoltage() +{ + int32_t instant_vbat = anaIn(TX_VOLTAGE); // using filtered ADC value on purpose + instant_vbat = (instant_vbat * BATT_SCALE * (128 + g_eeGeneral.txVoltageCalibration) ) / 26214; + instant_vbat += 20; // add 0.2V because of the diode TODO check if this is needed, but removal will beak existing calibrations!!! + return (uint16_t)instant_vbat; +} diff --git a/radio/src/targets/taranis/diskio.cpp b/radio/src/targets/taranis/diskio.cpp index a67c47eaa..ad51be819 100644 --- a/radio/src/targets/taranis/diskio.cpp +++ b/radio/src/targets/taranis/diskio.cpp @@ -1,1041 +1,1041 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" -#include "FatFs/diskio.h" -#include "FatFs/ff.h" - -/* Definitions for MMC/SDC command */ -#define CMD0 (0x40+0) /* GO_IDLE_STATE */ -#define CMD1 (0x40+1) /* SEND_OP_COND (MMC) */ -#define ACMD41 (0xC0+41) /* SEND_OP_COND (SDC) */ -#define CMD8 (0x40+8) /* SEND_IF_COND */ -#define CMD9 (0x40+9) /* SEND_CSD */ -#define CMD10 (0x40+10) /* SEND_CID */ -#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ -#define ACMD13 (0xC0+13) /* SD_STATUS (SDC) */ -#define CMD16 (0x40+16) /* SET_BLOCKLEN */ -#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ -#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ -#define CMD23 (0x40+23) /* SET_BLOCK_COUNT (MMC) */ -#define ACMD23 (0xC0+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */ -#define CMD24 (0x40+24) /* WRITE_BLOCK */ -#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ -#define CMD55 (0x40+55) /* APP_CMD */ -#define CMD58 (0x40+58) /* READ_OCR */ - -/* Card-Select Controls (Platform dependent) */ -#define SD_SELECT() GPIO_ResetBits(SD_GPIO, SD_GPIO_PIN_CS) /* MMC CS = L */ -#define SD_DESELECT() GPIO_SetBits(SD_GPIO, SD_GPIO_PIN_CS) /* MMC CS = H */ - -#define BOOL bool -#define FALSE false -#define TRUE true - -/* Card type flags (CardType) */ -#define CT_MMC 0x01 -#define CT_SD1 0x02 -#define CT_SD2 0x04 -#define CT_SDC (CT_SD1|CT_SD2) -#define CT_BLOCK 0x08 - -/*-----------------------------------------------------------------------*/ -/* Lock / unlock functions */ -/*-----------------------------------------------------------------------*/ -#if !defined(BOOT) -static OS_MutexID ioMutex; - -int ff_cre_syncobj (BYTE vol, _SYNC_t *mutex) -{ - *mutex = ioMutex; - return 1; -} - -int ff_req_grant (_SYNC_t mutex) -{ - return CoEnterMutexSection(mutex) == E_OK; -} - -void ff_rel_grant (_SYNC_t mutex) -{ - CoLeaveMutexSection(mutex); -} - -int ff_del_syncobj (_SYNC_t mutex) -{ - return 1; -} -#endif - -static const DWORD socket_state_mask_cp = (1 << 0); -static const DWORD socket_state_mask_wp = (1 << 1); - -static volatile -DSTATUS Stat = STA_NOINIT; /* Disk status */ - -static volatile -DWORD Timer1, Timer2; /* 100Hz decrement timers */ - -BYTE CardType; /* Card type flags */ - -enum speed_setting { INTERFACE_SLOW, INTERFACE_FAST }; - -static void interface_speed( enum speed_setting speed ) -{ - DWORD tmp; - - tmp = SD_SPI->CR1; - if ( speed == INTERFACE_SLOW ) { - /* Set slow clock (100k-400k) */ - tmp = ( tmp | SPI_BaudRatePrescaler_128 ); - } else { - /* Set fast clock (depends on the CSD) */ - tmp = ( tmp & ~SPI_BaudRatePrescaler_128 ) | SD_SPI_BaudRatePrescaler; - } - SD_SPI->CR1 = tmp; -} - -static inline DWORD socket_is_write_protected(void) -{ - return 0; /* fake not protected */ -} - -static inline DWORD socket_is_empty(void) -{ - return !SD_CARD_PRESENT(); /* fake inserted */ -} - -static void card_power(BYTE on) -{ - on=on; -} - -static int chk_power(void) -{ - return 1; /* fake powered */ -} - -/*-----------------------------------------------------------------------*/ -/* Transmit/Receive a byte to MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ -static BYTE stm32_spi_rw( BYTE out ) -{ - /* Loop while DR register in not empty */ - /// not needed: while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET) { ; } - - /* Send byte through the SPI peripheral */ - SPI_I2S_SendData(SD_SPI, out); - - /* Wait to receive a byte */ - while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET) { ; } - - /* Return the byte read from the SPI bus */ - return SPI_I2S_ReceiveData(SD_SPI); -} - - - -/*-----------------------------------------------------------------------*/ -/* Transmit a byte to MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -#define xmit_spi(dat) stm32_spi_rw(dat) - -/*-----------------------------------------------------------------------*/ -/* Receive a byte from MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -static -BYTE rcvr_spi (void) -{ - return stm32_spi_rw(0xff); -} - -/* Alternative macro to receive data fast */ -#define rcvr_spi_m(dst) *(dst)=stm32_spi_rw(0xff) - - - -/*-----------------------------------------------------------------------*/ -/* Wait for card ready */ -/*-----------------------------------------------------------------------*/ -static BYTE wait_ready (void) -{ - BYTE res; - - Timer2 = 50; /* Wait for ready in timeout of 500ms */ - rcvr_spi(); - do { - res = rcvr_spi(); - } while ((res != 0xFF) && Timer2); - - return res; -} - -static void spi_reset() -{ - for (int n=0; n<520; ++n) { - stm32_spi_rw(0xFF); - } - TRACE_SD_CARD_EVENT(1, sd_spi_reset, 0); -} - -/*-----------------------------------------------------------------------*/ -/* Deselect the card and release SPI bus */ -/*-----------------------------------------------------------------------*/ - -static -void release_spi (void) -{ - SD_DESELECT(); - rcvr_spi(); -} - -#ifdef SD_USE_DMA - -#if defined(STM32F4) && !defined(BOOT) -WORD rw_workbyte[1] __DMA; -#endif - -/*-----------------------------------------------------------------------*/ -/* Transmit/Receive Block using DMA (Platform dependent. STM32 here) */ -/*-----------------------------------------------------------------------*/ -static -void stm32_dma_transfer( - BOOL receive, /* FALSE for buff->SPI, TRUE for SPI->buff */ - const BYTE *buff, /* receive TRUE : 512 byte data block to be transmitted - receive FALSE : Data buffer to store received data */ - UINT btr /* receive TRUE : Byte count (must be multiple of 2) - receive FALSE : Byte count (must be 512) */ -) -{ - DMA_InitTypeDef DMA_InitStructure; -#if defined(STM32F4) && !defined(BOOT) - rw_workbyte[0] = 0xffff; -#else - WORD rw_workbyte[] = { 0xffff }; -#endif - - DMA_DeInit(SD_DMA_Stream_SPI_RX); - DMA_DeInit(SD_DMA_Stream_SPI_TX); - - /* shared DMA configuration values between SPI2 RX & TX*/ - DMA_InitStructure.DMA_Channel = SD_DMA_Channel_SPI;//the same channel - DMA_InitStructure.DMA_PeripheralBaseAddr = (DWORD)(&(SD_SPI->DR)); - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_BufferSize = btr; - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - - // separate RX & TX - if (receive) { - DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)buff; - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_Init(SD_DMA_Stream_SPI_RX, &DMA_InitStructure); - DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)rw_workbyte; - DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_Init(SD_DMA_Stream_SPI_TX, &DMA_InitStructure); - } - else { -#if _FS_READONLY == 0 - DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)rw_workbyte; - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_Init(SD_DMA_Stream_SPI_RX, &DMA_InitStructure); - DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)buff; - DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_Init(SD_DMA_Stream_SPI_TX, &DMA_InitStructure); -#endif - } - - /* Enable DMA Channels */ - DMA_Cmd(SD_DMA_Stream_SPI_RX, ENABLE); - DMA_Cmd(SD_DMA_Stream_SPI_TX, ENABLE); - - /* Enable SPI TX/RX request */ - SPI_I2S_DMACmd(SD_SPI, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, ENABLE); - - while (DMA_GetFlagStatus(SD_DMA_Stream_SPI_TX, SD_DMA_FLAG_SPI_TC_TX) == RESET) { ; } - while (DMA_GetFlagStatus(SD_DMA_Stream_SPI_RX, SD_DMA_FLAG_SPI_TC_RX) == RESET) { ; } - - /* Disable DMA Channels */ - DMA_Cmd(SD_DMA_Stream_SPI_RX, DISABLE); - DMA_Cmd(SD_DMA_Stream_SPI_TX, DISABLE); - - /* Disable SPI RX/TX request */ - SPI_I2S_DMACmd(SD_SPI, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, DISABLE); -} -#endif /* SD_USE_DMA */ - - -/*-----------------------------------------------------------------------*/ -/* Power Control and interface-initialization (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -static -void power_on (void) -{ - SPI_InitTypeDef SPI_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - volatile BYTE dummyread; - - card_power(1); - - GPIO_InitStructure.GPIO_Pin = SD_GPIO_PIN_PRESENT; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(SD_GPIO_PRESENT, &GPIO_InitStructure); - - for (uint32_t Timer = 25000; Timer>0;Timer--); /* Wait for 250ms */ - - /* Configure I/O for Flash Chip select */ - GPIO_InitStructure.GPIO_Pin = SD_GPIO_PIN_CS; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(SD_GPIO, &GPIO_InitStructure); - - /* De-select the Card: Chip Select high */ - SD_DESELECT(); - - /* Configure SPI pins: SCK MISO and MOSI with alternate function push-down */ - GPIO_InitStructure.GPIO_Pin = SD_GPIO_PIN_SCK | SD_GPIO_PIN_MOSI|SD_GPIO_PIN_MISO; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(SD_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(SD_GPIO,SD_GPIO_PinSource_SCK ,SD_GPIO_AF); - GPIO_PinAFConfig(SD_GPIO,SD_GPIO_PinSource_MISO,SD_GPIO_AF); - GPIO_PinAFConfig(SD_GPIO,SD_GPIO_PinSource_MOSI,SD_GPIO_AF); - - /* SPI configuration */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SD_SPI_BaudRatePrescaler; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_Init(SD_SPI, &SPI_InitStructure); - SPI_CalculateCRC(SD_SPI, DISABLE); - SPI_Cmd(SD_SPI, ENABLE); - - /* drain SPI */ - while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET) { ; } - dummyread = SPI_I2S_ReceiveData(SD_SPI); - - (void) dummyread; // Discard value - prevents compiler warning -} - -static -void power_off (void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - if (!(Stat & STA_NOINIT)) { - SD_SELECT(); - wait_ready(); - release_spi(); - } - - SPI_I2S_DeInit(SD_SPI); - SPI_Cmd(SD_SPI, DISABLE); - - //All SPI-Pins to input with weak internal pull-downs - GPIO_InitStructure.GPIO_Pin = SD_GPIO_PIN_SCK | SD_GPIO_PIN_MISO | SD_GPIO_PIN_MOSI; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; - GPIO_Init(SD_GPIO, &GPIO_InitStructure); - - card_power(0); - - Stat |= STA_NOINIT; /* Set STA_NOINIT */ -} - -/*-----------------------------------------------------------------------*/ -/* Receive a data packet from MMC */ -/*-----------------------------------------------------------------------*/ - -#if defined(SD_USE_DMA) && defined(STM32F4) && !defined(BOOT) - uint8_t sd_buff[512] __DMA; -#endif - -static -BOOL rcvr_datablock ( - BYTE *buff, /* Data buffer to store received data */ - UINT btr /* Byte count (must be multiple of 4) */ -) -{ - BYTE token; - - - Timer1 = 10; - do { /* Wait for data packet in timeout of 100ms */ - token = rcvr_spi(); - } while ((token == 0xFF) && Timer1); - if(token != 0xFE) { - TRACE_SD_CARD_EVENT(1, sd_rcvr_datablock, ((uint32_t)(Timer1) << 24) + ((uint32_t)(btr) << 8) + token); - spi_reset(); - return FALSE; /* If not valid data token, return with error */ - } - -#if defined(SD_USE_DMA) && defined(STM32F4) && !defined(BOOT) - stm32_dma_transfer(TRUE, sd_buff, btr); - memcpy(buff, sd_buff, btr); -#elif defined(SD_USE_DMA) - stm32_dma_transfer(TRUE, buff, btr); -#else - do { /* Receive the data block into buffer */ - rcvr_spi_m(buff++); - rcvr_spi_m(buff++); - rcvr_spi_m(buff++); - rcvr_spi_m(buff++); - } while (btr -= 4); -#endif /* SD_USE_DMA */ - - rcvr_spi(); /* Discard CRC */ - rcvr_spi(); - - return TRUE; /* Return with success */ -} - - - -/*-----------------------------------------------------------------------*/ -/* Send a data packet to MMC */ -/*-----------------------------------------------------------------------*/ - -#define DATA_RESPONSE_TIMEOUT 10 - -static -BOOL xmit_datablock ( - const BYTE *buff, /* 512 byte data block to be transmitted */ - BYTE token /* Data/Stop token */ -) -{ - BYTE resp; -#ifndef SD_USE_DMA - BYTE wc; -#endif - - if (wait_ready() != 0xFF) { - TRACE_SD_CARD_EVENT(1, sd_xmit_datablock_wait_ready, token); - spi_reset(); - return FALSE; - } - - xmit_spi(token); /* transmit data token */ - if (token != 0xFD) { /* Is data token */ - -#if defined(SD_USE_DMA) && defined(STM32F4) && !defined(BOOT) - memcpy(sd_buff, buff, 512); - stm32_dma_transfer(FALSE, sd_buff, 512); -#elif defined(SD_USE_DMA) - stm32_dma_transfer(FALSE, buff, 512); -#else - wc = 0; - do { /* transmit the 512 byte data block to MMC */ - xmit_spi(*buff++); - xmit_spi(*buff++); - } while (--wc); -#endif /* SD_USE_DMA */ - - xmit_spi(0xFF); /* CRC (Dummy) */ - xmit_spi(0xFF); - - /* - Despite what the SD card standard says, the reality is that (at least for some SD cards) - the Data Response byte does not come immediately after the last byte of data. - - This delay only happens very rarely, but it does happen. Typical response delay is some 10ms - */ - Timer2 = DATA_RESPONSE_TIMEOUT; - do { - resp = rcvr_spi(); /* Receive data response */ - if ((resp & 0x1F) == 0x05) { - TRACE_SD_CARD_EVENT((Timer2 != DATA_RESPONSE_TIMEOUT), sd_xmit_datablock_rcvr_spi, ((uint32_t)(Timer2) << 16) + ((uint32_t)(resp) << 8) + token); - return TRUE; - } - if (resp != 0xFF) { - TRACE_SD_CARD_EVENT(1, sd_xmit_datablock_rcvr_spi, ((uint32_t)(Timer2) << 16) + ((uint32_t)(resp) << 8) + token); - spi_reset(); - return FALSE; - } - } while (Timer2); - TRACE_SD_CARD_EVENT(1, sd_xmit_datablock_rcvr_spi, ((uint32_t)(Timer2) << 16) + ((uint32_t)(resp) << 8) + token); - return FALSE; - } - return TRUE; -} - - -/*-----------------------------------------------------------------------*/ -/* Send a command packet to MMC */ -/*-----------------------------------------------------------------------*/ - -static -BYTE send_cmd ( - BYTE cmd, /* Command byte */ - DWORD arg /* Argument */ -) -{ - BYTE n, res; - - - if (cmd & 0x80) { /* ACMD is the command sequence of CMD55-CMD */ - cmd &= 0x7F; - res = send_cmd(CMD55, 0); - if (res > 1) return res; - } - - /* Select the card and wait for ready */ - SD_SELECT(); - if (wait_ready() != 0xFF) { - TRACE_SD_CARD_EVENT(1, sd_send_cmd_wait_ready, cmd); - spi_reset(); - return 0xFF; - } - - /* Send command packet */ - xmit_spi(cmd); /* Start + Command index */ - xmit_spi((BYTE)(arg >> 24)); /* Argument[31..24] */ - xmit_spi((BYTE)(arg >> 16)); /* Argument[23..16] */ - xmit_spi((BYTE)(arg >> 8)); /* Argument[15..8] */ - xmit_spi((BYTE)arg); /* Argument[7..0] */ - n = 0x01; /* Dummy CRC + Stop */ - if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) */ - if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) */ - xmit_spi(n); - - /* Receive command response */ - if (cmd == CMD12) rcvr_spi(); /* Skip a stuff byte when stop reading */ - - n = 10; /* Wait for a valid response in timeout of 10 attempts */ - do { - res = rcvr_spi(); - } while ((res & 0x80) && --n); - - TRACE_SD_CARD_EVENT((res > 1), sd_send_cmd_rcvr_spi, ((uint32_t)(n) << 16) + ((uint32_t)(res) << 8) + cmd); - - return res; /* Return with the response value */ -} - - - -/*-------------------------------------------------------------------------- - - Public Functions - ----------------------------------------------------------------------------*/ - - -/*-----------------------------------------------------------------------*/ -/* Initialize Disk Drive */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_initialize ( - BYTE drv /* Physical drive number (0) */ -) -{ - BYTE n, cmd, ty, ocr[4]; - - if (drv) return STA_NOINIT; /* Supports only single drive */ - if (Stat & STA_NODISK) return Stat; /* No card in the socket */ - - power_on(); /* Force socket power on and initialize interface */ - interface_speed(INTERFACE_SLOW); - for (n = 10; n; n--) rcvr_spi(); /* 80 dummy clocks */ - - ty = 0; - if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ - Timer1 = 100; /* Initialization timeout of 1000 milliseconds */ - if (send_cmd(CMD8, 0x1AA) == 1) { /* SDHC */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); /* Get trailing return value of R7 response */ - if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at VDD range of 2.7-3.6V */ - while (Timer1 && send_cmd(ACMD41, 1UL << 30)); /* Wait for leaving idle state (ACMD41 with HCS bit) */ - if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); - ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; - } - } - } else { /* SDSC or MMC */ - if (send_cmd(ACMD41, 0) <= 1) { - ty = CT_SD1; cmd = ACMD41; /* SDSC */ - } else { - ty = CT_MMC; cmd = CMD1; /* MMC */ - } - while (Timer1 && send_cmd(cmd, 0)); /* Wait for leaving idle state */ - if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Set R/W block length to 512 */ - ty = 0; - } - } - CardType = ty; - release_spi(); - - if (ty) { /* Initialization succeeded */ - Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ - interface_speed(INTERFACE_FAST); - } - else { /* Initialization failed */ - power_off(); - } - - return Stat; -} - - - -/*-----------------------------------------------------------------------*/ -/* Get Disk Status */ -/*-----------------------------------------------------------------------*/ -DSTATUS disk_status ( - BYTE drv /* Physical drive number (0) */ -) -{ - if (drv) return STA_NOINIT; /* Supports only single drive */ - return Stat; -} - - -#if defined(STM32F4) && !defined(BOOT) -DWORD scratch[BLOCK_SIZE / 4] __DMA; -#endif - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ -/*-----------------------------------------------------------------------*/ - -int8_t SD_ReadSectors(uint8_t * buff, uint32_t sector, uint32_t count) -{ -#if defined(STM32F4) && !defined(BOOT) - if ((DWORD)buff < 0x20000000 || ((DWORD)buff & 3)) { - TRACE("disk_read bad alignment (%p)", buff); - while (count--) { - int8_t res = SD_ReadSectors((BYTE *)scratch, sector++, 1); - - if (res != 0) { - return res; - } - - memcpy(buff, scratch, BLOCK_SIZE); - - buff += BLOCK_SIZE; - } - - return 0; - } -#endif - - if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ - - if (count == 1) { /* Single block read */ - if (send_cmd(CMD17, sector) == 0) { /* READ_SINGLE_BLOCK */ - if (rcvr_datablock(buff, 512)) { - count = 0; - } - } - else { - spi_reset(); - } - } - else { /* Multiple block read */ - if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ - do { - if (!rcvr_datablock(buff, 512)) { - break; - } - buff += 512; - } while (--count); - send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ - } - else { - spi_reset(); - } - } - release_spi(); - TRACE_SD_CARD_EVENT((count != 0), sd_SD_ReadSectors, (count << 24) + ((sector/((CardType & CT_BLOCK) ? 1 : 512)) & 0x00FFFFFF)); - - return count ? -1 : 0; -} - -DRESULT disk_read ( - BYTE drv, /* Physical drive number (0) */ - BYTE *buff, /* Pointer to the data buffer to store read data */ - DWORD sector, /* Start sector number (LBA) */ - UINT count /* Sector count (1..255) */ -) -{ - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - int8_t res = SD_ReadSectors(buff, sector, count); - TRACE_SD_CARD_EVENT((res != 0), sd_disk_read, (count << 24) + (sector & 0x00FFFFFF)); - return (res != 0) ? RES_ERROR : RES_OK; -} - - - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ -/*-----------------------------------------------------------------------*/ - -int8_t SD_WriteSectors(const uint8_t * buff, uint32_t sector, uint32_t count) -{ -#if defined(STM32F4) && !defined(BOOT) - if ((DWORD)buff < 0x20000000 || ((DWORD)buff & 3)) { - TRACE("disk_write bad alignment (%p)", buff); - while (count--) { - memcpy(scratch, buff, BLOCK_SIZE); - - int8_t res = SD_WriteSectors((const uint8_t *)scratch, sector++, 1); - - if (res != 0) { - return res; - } - - buff += BLOCK_SIZE; - } - - return 0; - } -#endif - - if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ - - if (count == 1) { /* Single block write */ - if (send_cmd(CMD24, sector) == 0) { /* WRITE_BLOCK */ - if (xmit_datablock(buff, 0xFE)) { - count = 0; - } - } - else { - spi_reset(); - } - } - else { /* Multiple block write */ - if (CardType & CT_SDC) send_cmd(ACMD23, count); - if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ - do { - if (!xmit_datablock(buff, 0xFC)) break; - buff += 512; - } while (--count); - if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ - count = 1; - } - else { - spi_reset(); - } - } - release_spi(); - TRACE_SD_CARD_EVENT((count != 0), sd_SD_WriteSectors, (count << 24) + ((sector/((CardType & CT_BLOCK) ? 1 : 512)) & 0x00FFFFFF)); - - return count ? -1 : 0; -} - -DRESULT disk_write ( - BYTE drv, /* Physical drive number (0) */ - const BYTE *buff, /* Pointer to the data to be written */ - DWORD sector, /* Start sector number (LBA) */ - UINT count /* Sector count (1..255) */ -) -{ - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - if (Stat & STA_PROTECT) return RES_WRPRT; - int8_t res = SD_WriteSectors(buff, sector, count); - TRACE_SD_CARD_EVENT((res != 0), sd_disk_write, (count << 24) + (sector & 0x00FFFFFF)); - return (res != 0) ? RES_ERROR : RES_OK; -} - - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ -/*-----------------------------------------------------------------------*/ - -DRESULT disk_ioctl ( - BYTE drv, /* Physical drive number (0) */ - BYTE ctrl, /* Control code */ - void *buff /* Buffer to send/receive control data */ -) -{ - DRESULT res; - BYTE n, csd[16], *ptr = (BYTE *)buff; - WORD csize; - - if (drv) return RES_PARERR; - - res = RES_ERROR; - - if (ctrl == CTRL_POWER) { - switch (*ptr) { - case 0: /* Sub control code == 0 (POWER_OFF) */ - if (chk_power()) - power_off(); /* Power off */ - res = RES_OK; - break; - case 1: /* Sub control code == 1 (POWER_ON) */ - power_on(); /* Power on */ - res = RES_OK; - break; - case 2: /* Sub control code == 2 (POWER_GET) */ - *(ptr+1) = (BYTE)chk_power(); - res = RES_OK; - break; - default : - res = RES_PARERR; - } - } - else { - if (Stat & STA_NOINIT) { - return RES_NOTRDY; - } - - switch (ctrl) { - case CTRL_SYNC : /* Make sure that no pending write process */ - SD_SELECT(); - if (wait_ready() == 0xFF) { - res = RES_OK; - } - else { - TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_CTRL_SYNC, 0); - } - break; - - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ - if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { - if ((csd[0] >> 6) == 1) { /* SDC version 2.00 */ - csize = csd[9] + ((WORD)csd[8] << 8) + 1; - *(DWORD*)buff = (DWORD)csize << 10; - } - else { /* SDC version 1.XX or MMC*/ - n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; - csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; - *(DWORD*)buff = (DWORD)csize << (n - 9); - } - res = RES_OK; - } - else { - TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_GET_SECTOR_COUNT, 0); - } - break; - - case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ - *(WORD*)buff = 512; - res = RES_OK; - break; - - case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ - if (CardType & CT_SD2) { /* SDC version 2.00 */ - if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ - rcvr_spi(); - if (rcvr_datablock(csd, 16)) { /* Read partial block */ - for (n = 64 - 16; n; n--) rcvr_spi(); /* Purge trailing data */ - *(DWORD*)buff = 16UL << (csd[10] >> 4); - res = RES_OK; - } - } - } else { /* SDC version 1.XX or MMC */ - if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ - if (CardType & CT_SD1) { /* SDC version 1.XX */ - *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); - } else { /* MMC */ - *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); - } - res = RES_OK; - } - } - break; - - case MMC_GET_TYPE : /* Get card type flags (1 byte) */ - *ptr = CardType; - res = RES_OK; - break; - - case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ - if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ - && rcvr_datablock(ptr, 16)) { - res = RES_OK; - } - else { - TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_MMC_GET_CSD, 0); - } - break; - - case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ - if (send_cmd(CMD10, 0) == 0 /* READ_CID */ - && rcvr_datablock(ptr, 16)) { - res = RES_OK; - } - else { - TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_MMC_GET_CID, 0); - } - break; - - case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ - if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ - for (n = 4; n; n--) *ptr++ = rcvr_spi(); - res = RES_OK; - } - else { - TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_MMC_GET_OCR, 0); - } - break; - - case MMC_GET_SDSTAT : /* Receive SD status as a data block (64 bytes) */ - if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ - rcvr_spi(); - if (rcvr_datablock(ptr, 64)) { - res = RES_OK; - } - else { - TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_MMC_GET_SDSTAT_1, 0); - } - } - else { - TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_MMC_GET_SDSTAT_2, 0); - } - break; - - default: - res = RES_PARERR; - } - - release_spi(); - } - - return res; -} - - -/*-----------------------------------------------------------------------*/ -/* Device Timer Interrupt Procedure (Platform dependent) */ -/*-----------------------------------------------------------------------*/ -/* This function must be called in period of 10ms */ - -void sdPoll10ms() -{ - static DWORD pv; - DWORD ns; - BYTE n, s; - - - n = Timer1; /* 100Hz decrement timers */ - if (n) Timer1 = --n; - n = Timer2; - if (n) Timer2 = --n; - - ns = pv; - pv = socket_is_empty() | socket_is_write_protected(); /* Sample socket switch */ - - if (ns == pv) { /* Have contacts stabled? */ - s = Stat; - - if (pv & socket_state_mask_wp) /* WP is H (write protected) */ - s |= STA_PROTECT; - else /* WP is L (write enabled) */ - s &= ~STA_PROTECT; - - if (pv & socket_state_mask_cp) /* INS = H (Socket empty) */ - s |= (STA_NODISK | STA_NOINIT); - else /* INS = L (Card inserted) */ - s &= ~STA_NODISK; - - Stat = s; - } -} - -// TODO everything here should not be in the driver layer ... - -FATFS g_FATFS_Obj; -#if defined(LOG_TELEMETRY) -FIL g_telemetryFile = {}; -#endif - -#if defined(BOOT) -void sdInit(void) -{ - if (f_mount(&g_FATFS_Obj, "", 1) == FR_OK) { - f_chdir("/"); - } -} -#else -// TODO shouldn't be there! -void sdInit(void) -{ - TRACE("sdInit"); - - ioMutex = CoCreateMutex(); - if (ioMutex >= CFG_MAX_MUTEX ) { - //sd error - return; - } - - if (f_mount(&g_FATFS_Obj, "", 1) == FR_OK) { - // call sdGetFreeSectors() now because f_getfree() takes a long time first time it's called - sdGetFreeSectors(); - -#if defined(LOG_TELEMETRY) - f_open(&g_telemetryFile, LOGS_PATH "/telemetry.log", FA_OPEN_ALWAYS | FA_WRITE); - if (f_size(&g_telemetryFile) > 0) { - f_lseek(&g_telemetryFile, f_size(&g_telemetryFile)); // append - } -#endif - } -} - -void sdDone() -{ - if (sdMounted()) { - audioQueue.stopSD(); -#if defined(LOG_TELEMETRY) - f_close(&g_telemetryFile); -#endif - f_mount(NULL, "", 0); // unmount SD - } -} -#endif - -uint32_t sdMounted() -{ - return g_FATFS_Obj.fs_type != 0; -} - -uint32_t sdIsHC() -{ - return (CardType & CT_BLOCK); -} - -uint32_t sdGetSpeed() -{ - return 330000; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" +#include "FatFs/diskio.h" +#include "FatFs/ff.h" + +/* Definitions for MMC/SDC command */ +#define CMD0 (0x40+0) /* GO_IDLE_STATE */ +#define CMD1 (0x40+1) /* SEND_OP_COND (MMC) */ +#define ACMD41 (0xC0+41) /* SEND_OP_COND (SDC) */ +#define CMD8 (0x40+8) /* SEND_IF_COND */ +#define CMD9 (0x40+9) /* SEND_CSD */ +#define CMD10 (0x40+10) /* SEND_CID */ +#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ +#define ACMD13 (0xC0+13) /* SD_STATUS (SDC) */ +#define CMD16 (0x40+16) /* SET_BLOCKLEN */ +#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ +#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (0x40+23) /* SET_BLOCK_COUNT (MMC) */ +#define ACMD23 (0xC0+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */ +#define CMD24 (0x40+24) /* WRITE_BLOCK */ +#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD55 (0x40+55) /* APP_CMD */ +#define CMD58 (0x40+58) /* READ_OCR */ + +/* Card-Select Controls (Platform dependent) */ +#define SD_SELECT() GPIO_ResetBits(SD_GPIO, SD_GPIO_PIN_CS) /* MMC CS = L */ +#define SD_DESELECT() GPIO_SetBits(SD_GPIO, SD_GPIO_PIN_CS) /* MMC CS = H */ + +#define BOOL bool +#define FALSE false +#define TRUE true + +/* Card type flags (CardType) */ +#define CT_MMC 0x01 +#define CT_SD1 0x02 +#define CT_SD2 0x04 +#define CT_SDC (CT_SD1|CT_SD2) +#define CT_BLOCK 0x08 + +/*-----------------------------------------------------------------------*/ +/* Lock / unlock functions */ +/*-----------------------------------------------------------------------*/ +#if !defined(BOOT) +static OS_MutexID ioMutex; + +int ff_cre_syncobj (BYTE vol, _SYNC_t *mutex) +{ + *mutex = ioMutex; + return 1; +} + +int ff_req_grant (_SYNC_t mutex) +{ + return CoEnterMutexSection(mutex) == E_OK; +} + +void ff_rel_grant (_SYNC_t mutex) +{ + CoLeaveMutexSection(mutex); +} + +int ff_del_syncobj (_SYNC_t mutex) +{ + return 1; +} +#endif + +static const DWORD socket_state_mask_cp = (1 << 0); +static const DWORD socket_state_mask_wp = (1 << 1); + +static volatile +DSTATUS Stat = STA_NOINIT; /* Disk status */ + +static volatile +DWORD Timer1, Timer2; /* 100Hz decrement timers */ + +BYTE CardType; /* Card type flags */ + +enum speed_setting { INTERFACE_SLOW, INTERFACE_FAST }; + +static void interface_speed( enum speed_setting speed ) +{ + DWORD tmp; + + tmp = SD_SPI->CR1; + if ( speed == INTERFACE_SLOW ) { + /* Set slow clock (100k-400k) */ + tmp = ( tmp | SPI_BaudRatePrescaler_128 ); + } else { + /* Set fast clock (depends on the CSD) */ + tmp = ( tmp & ~SPI_BaudRatePrescaler_128 ) | SD_SPI_BaudRatePrescaler; + } + SD_SPI->CR1 = tmp; +} + +static inline DWORD socket_is_write_protected(void) +{ + return 0; /* fake not protected */ +} + +static inline DWORD socket_is_empty(void) +{ + return !SD_CARD_PRESENT(); /* fake inserted */ +} + +static void card_power(BYTE on) +{ + on=on; +} + +static int chk_power(void) +{ + return 1; /* fake powered */ +} + +/*-----------------------------------------------------------------------*/ +/* Transmit/Receive a byte to MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ +static BYTE stm32_spi_rw( BYTE out ) +{ + /* Loop while DR register in not empty */ + /// not needed: while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET) { ; } + + /* Send byte through the SPI peripheral */ + SPI_I2S_SendData(SD_SPI, out); + + /* Wait to receive a byte */ + while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET) { ; } + + /* Return the byte read from the SPI bus */ + return SPI_I2S_ReceiveData(SD_SPI); +} + + + +/*-----------------------------------------------------------------------*/ +/* Transmit a byte to MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +#define xmit_spi(dat) stm32_spi_rw(dat) + +/*-----------------------------------------------------------------------*/ +/* Receive a byte from MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +static +BYTE rcvr_spi (void) +{ + return stm32_spi_rw(0xff); +} + +/* Alternative macro to receive data fast */ +#define rcvr_spi_m(dst) *(dst)=stm32_spi_rw(0xff) + + + +/*-----------------------------------------------------------------------*/ +/* Wait for card ready */ +/*-----------------------------------------------------------------------*/ +static BYTE wait_ready (void) +{ + BYTE res; + + Timer2 = 50; /* Wait for ready in timeout of 500ms */ + rcvr_spi(); + do { + res = rcvr_spi(); + } while ((res != 0xFF) && Timer2); + + return res; +} + +static void spi_reset() +{ + for (int n=0; n<520; ++n) { + stm32_spi_rw(0xFF); + } + TRACE_SD_CARD_EVENT(1, sd_spi_reset, 0); +} + +/*-----------------------------------------------------------------------*/ +/* Deselect the card and release SPI bus */ +/*-----------------------------------------------------------------------*/ + +static +void release_spi (void) +{ + SD_DESELECT(); + rcvr_spi(); +} + +#ifdef SD_USE_DMA + +#if defined(STM32F4) && !defined(BOOT) +WORD rw_workbyte[1] __DMA; +#endif + +/*-----------------------------------------------------------------------*/ +/* Transmit/Receive Block using DMA (Platform dependent. STM32 here) */ +/*-----------------------------------------------------------------------*/ +static +void stm32_dma_transfer( + BOOL receive, /* FALSE for buff->SPI, TRUE for SPI->buff */ + const BYTE *buff, /* receive TRUE : 512 byte data block to be transmitted + receive FALSE : Data buffer to store received data */ + UINT btr /* receive TRUE : Byte count (must be multiple of 2) + receive FALSE : Byte count (must be 512) */ +) +{ + DMA_InitTypeDef DMA_InitStructure; +#if defined(STM32F4) && !defined(BOOT) + rw_workbyte[0] = 0xffff; +#else + WORD rw_workbyte[] = { 0xffff }; +#endif + + DMA_DeInit(SD_DMA_Stream_SPI_RX); + DMA_DeInit(SD_DMA_Stream_SPI_TX); + + /* shared DMA configuration values between SPI2 RX & TX*/ + DMA_InitStructure.DMA_Channel = SD_DMA_Channel_SPI;//the same channel + DMA_InitStructure.DMA_PeripheralBaseAddr = (DWORD)(&(SD_SPI->DR)); + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_BufferSize = btr; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + + // separate RX & TX + if (receive) { + DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)buff; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_Init(SD_DMA_Stream_SPI_RX, &DMA_InitStructure); + DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)rw_workbyte; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_Init(SD_DMA_Stream_SPI_TX, &DMA_InitStructure); + } + else { +#if _FS_READONLY == 0 + DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)rw_workbyte; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_Init(SD_DMA_Stream_SPI_RX, &DMA_InitStructure); + DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)buff; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_Init(SD_DMA_Stream_SPI_TX, &DMA_InitStructure); +#endif + } + + /* Enable DMA Channels */ + DMA_Cmd(SD_DMA_Stream_SPI_RX, ENABLE); + DMA_Cmd(SD_DMA_Stream_SPI_TX, ENABLE); + + /* Enable SPI TX/RX request */ + SPI_I2S_DMACmd(SD_SPI, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, ENABLE); + + while (DMA_GetFlagStatus(SD_DMA_Stream_SPI_TX, SD_DMA_FLAG_SPI_TC_TX) == RESET) { ; } + while (DMA_GetFlagStatus(SD_DMA_Stream_SPI_RX, SD_DMA_FLAG_SPI_TC_RX) == RESET) { ; } + + /* Disable DMA Channels */ + DMA_Cmd(SD_DMA_Stream_SPI_RX, DISABLE); + DMA_Cmd(SD_DMA_Stream_SPI_TX, DISABLE); + + /* Disable SPI RX/TX request */ + SPI_I2S_DMACmd(SD_SPI, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, DISABLE); +} +#endif /* SD_USE_DMA */ + + +/*-----------------------------------------------------------------------*/ +/* Power Control and interface-initialization (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +static +void power_on (void) +{ + SPI_InitTypeDef SPI_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + volatile BYTE dummyread; + + card_power(1); + + GPIO_InitStructure.GPIO_Pin = SD_GPIO_PIN_PRESENT; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(SD_GPIO_PRESENT, &GPIO_InitStructure); + + for (uint32_t Timer = 25000; Timer>0;Timer--); /* Wait for 250ms */ + + /* Configure I/O for Flash Chip select */ + GPIO_InitStructure.GPIO_Pin = SD_GPIO_PIN_CS; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(SD_GPIO, &GPIO_InitStructure); + + /* De-select the Card: Chip Select high */ + SD_DESELECT(); + + /* Configure SPI pins: SCK MISO and MOSI with alternate function push-down */ + GPIO_InitStructure.GPIO_Pin = SD_GPIO_PIN_SCK | SD_GPIO_PIN_MOSI|SD_GPIO_PIN_MISO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(SD_GPIO, &GPIO_InitStructure); + GPIO_PinAFConfig(SD_GPIO,SD_GPIO_PinSource_SCK ,SD_GPIO_AF); + GPIO_PinAFConfig(SD_GPIO,SD_GPIO_PinSource_MISO,SD_GPIO_AF); + GPIO_PinAFConfig(SD_GPIO,SD_GPIO_PinSource_MOSI,SD_GPIO_AF); + + /* SPI configuration */ + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SD_SPI_BaudRatePrescaler; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + SPI_Init(SD_SPI, &SPI_InitStructure); + SPI_CalculateCRC(SD_SPI, DISABLE); + SPI_Cmd(SD_SPI, ENABLE); + + /* drain SPI */ + while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET) { ; } + dummyread = SPI_I2S_ReceiveData(SD_SPI); + + (void) dummyread; // Discard value - prevents compiler warning +} + +static +void power_off (void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + if (!(Stat & STA_NOINIT)) { + SD_SELECT(); + wait_ready(); + release_spi(); + } + + SPI_I2S_DeInit(SD_SPI); + SPI_Cmd(SD_SPI, DISABLE); + + //All SPI-Pins to input with weak internal pull-downs + GPIO_InitStructure.GPIO_Pin = SD_GPIO_PIN_SCK | SD_GPIO_PIN_MISO | SD_GPIO_PIN_MOSI; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; + GPIO_Init(SD_GPIO, &GPIO_InitStructure); + + card_power(0); + + Stat |= STA_NOINIT; /* Set STA_NOINIT */ +} + +/*-----------------------------------------------------------------------*/ +/* Receive a data packet from MMC */ +/*-----------------------------------------------------------------------*/ + +#if defined(SD_USE_DMA) && defined(STM32F4) && !defined(BOOT) + uint8_t sd_buff[512] __DMA; +#endif + +static +BOOL rcvr_datablock ( + BYTE *buff, /* Data buffer to store received data */ + UINT btr /* Byte count (must be multiple of 4) */ +) +{ + BYTE token; + + + Timer1 = 10; + do { /* Wait for data packet in timeout of 100ms */ + token = rcvr_spi(); + } while ((token == 0xFF) && Timer1); + if(token != 0xFE) { + TRACE_SD_CARD_EVENT(1, sd_rcvr_datablock, ((uint32_t)(Timer1) << 24) + ((uint32_t)(btr) << 8) + token); + spi_reset(); + return FALSE; /* If not valid data token, return with error */ + } + +#if defined(SD_USE_DMA) && defined(STM32F4) && !defined(BOOT) + stm32_dma_transfer(TRUE, sd_buff, btr); + memcpy(buff, sd_buff, btr); +#elif defined(SD_USE_DMA) + stm32_dma_transfer(TRUE, buff, btr); +#else + do { /* Receive the data block into buffer */ + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + } while (btr -= 4); +#endif /* SD_USE_DMA */ + + rcvr_spi(); /* Discard CRC */ + rcvr_spi(); + + return TRUE; /* Return with success */ +} + + + +/*-----------------------------------------------------------------------*/ +/* Send a data packet to MMC */ +/*-----------------------------------------------------------------------*/ + +#define DATA_RESPONSE_TIMEOUT 10 + +static +BOOL xmit_datablock ( + const BYTE *buff, /* 512 byte data block to be transmitted */ + BYTE token /* Data/Stop token */ +) +{ + BYTE resp; +#ifndef SD_USE_DMA + BYTE wc; +#endif + + if (wait_ready() != 0xFF) { + TRACE_SD_CARD_EVENT(1, sd_xmit_datablock_wait_ready, token); + spi_reset(); + return FALSE; + } + + xmit_spi(token); /* transmit data token */ + if (token != 0xFD) { /* Is data token */ + +#if defined(SD_USE_DMA) && defined(STM32F4) && !defined(BOOT) + memcpy(sd_buff, buff, 512); + stm32_dma_transfer(FALSE, sd_buff, 512); +#elif defined(SD_USE_DMA) + stm32_dma_transfer(FALSE, buff, 512); +#else + wc = 0; + do { /* transmit the 512 byte data block to MMC */ + xmit_spi(*buff++); + xmit_spi(*buff++); + } while (--wc); +#endif /* SD_USE_DMA */ + + xmit_spi(0xFF); /* CRC (Dummy) */ + xmit_spi(0xFF); + + /* + Despite what the SD card standard says, the reality is that (at least for some SD cards) + the Data Response byte does not come immediately after the last byte of data. + + This delay only happens very rarely, but it does happen. Typical response delay is some 10ms + */ + Timer2 = DATA_RESPONSE_TIMEOUT; + do { + resp = rcvr_spi(); /* Receive data response */ + if ((resp & 0x1F) == 0x05) { + TRACE_SD_CARD_EVENT((Timer2 != DATA_RESPONSE_TIMEOUT), sd_xmit_datablock_rcvr_spi, ((uint32_t)(Timer2) << 16) + ((uint32_t)(resp) << 8) + token); + return TRUE; + } + if (resp != 0xFF) { + TRACE_SD_CARD_EVENT(1, sd_xmit_datablock_rcvr_spi, ((uint32_t)(Timer2) << 16) + ((uint32_t)(resp) << 8) + token); + spi_reset(); + return FALSE; + } + } while (Timer2); + TRACE_SD_CARD_EVENT(1, sd_xmit_datablock_rcvr_spi, ((uint32_t)(Timer2) << 16) + ((uint32_t)(resp) << 8) + token); + return FALSE; + } + return TRUE; +} + + +/*-----------------------------------------------------------------------*/ +/* Send a command packet to MMC */ +/*-----------------------------------------------------------------------*/ + +static +BYTE send_cmd ( + BYTE cmd, /* Command byte */ + DWORD arg /* Argument */ +) +{ + BYTE n, res; + + + if (cmd & 0x80) { /* ACMD is the command sequence of CMD55-CMD */ + cmd &= 0x7F; + res = send_cmd(CMD55, 0); + if (res > 1) return res; + } + + /* Select the card and wait for ready */ + SD_SELECT(); + if (wait_ready() != 0xFF) { + TRACE_SD_CARD_EVENT(1, sd_send_cmd_wait_ready, cmd); + spi_reset(); + return 0xFF; + } + + /* Send command packet */ + xmit_spi(cmd); /* Start + Command index */ + xmit_spi((BYTE)(arg >> 24)); /* Argument[31..24] */ + xmit_spi((BYTE)(arg >> 16)); /* Argument[23..16] */ + xmit_spi((BYTE)(arg >> 8)); /* Argument[15..8] */ + xmit_spi((BYTE)arg); /* Argument[7..0] */ + n = 0x01; /* Dummy CRC + Stop */ + if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) */ + if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) */ + xmit_spi(n); + + /* Receive command response */ + if (cmd == CMD12) rcvr_spi(); /* Skip a stuff byte when stop reading */ + + n = 10; /* Wait for a valid response in timeout of 10 attempts */ + do { + res = rcvr_spi(); + } while ((res & 0x80) && --n); + + TRACE_SD_CARD_EVENT((res > 1), sd_send_cmd_rcvr_spi, ((uint32_t)(n) << 16) + ((uint32_t)(res) << 8) + cmd); + + return res; /* Return with the response value */ +} + + + +/*-------------------------------------------------------------------------- + + Public Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* Initialize Disk Drive */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_initialize ( + BYTE drv /* Physical drive number (0) */ +) +{ + BYTE n, cmd, ty, ocr[4]; + + if (drv) return STA_NOINIT; /* Supports only single drive */ + if (Stat & STA_NODISK) return Stat; /* No card in the socket */ + + power_on(); /* Force socket power on and initialize interface */ + interface_speed(INTERFACE_SLOW); + for (n = 10; n; n--) rcvr_spi(); /* 80 dummy clocks */ + + ty = 0; + if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ + Timer1 = 100; /* Initialization timeout of 1000 milliseconds */ + if (send_cmd(CMD8, 0x1AA) == 1) { /* SDHC */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); /* Get trailing return value of R7 response */ + if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at VDD range of 2.7-3.6V */ + while (Timer1 && send_cmd(ACMD41, 1UL << 30)); /* Wait for leaving idle state (ACMD41 with HCS bit) */ + if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); + ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; + } + } + } else { /* SDSC or MMC */ + if (send_cmd(ACMD41, 0) <= 1) { + ty = CT_SD1; cmd = ACMD41; /* SDSC */ + } else { + ty = CT_MMC; cmd = CMD1; /* MMC */ + } + while (Timer1 && send_cmd(cmd, 0)); /* Wait for leaving idle state */ + if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Set R/W block length to 512 */ + ty = 0; + } + } + CardType = ty; + release_spi(); + + if (ty) { /* Initialization succeeded */ + Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ + interface_speed(INTERFACE_FAST); + } + else { /* Initialization failed */ + power_off(); + } + + return Stat; +} + + + +/*-----------------------------------------------------------------------*/ +/* Get Disk Status */ +/*-----------------------------------------------------------------------*/ +DSTATUS disk_status ( + BYTE drv /* Physical drive number (0) */ +) +{ + if (drv) return STA_NOINIT; /* Supports only single drive */ + return Stat; +} + + +#if defined(STM32F4) && !defined(BOOT) +DWORD scratch[BLOCK_SIZE / 4] __DMA; +#endif + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ +/*-----------------------------------------------------------------------*/ + +int8_t SD_ReadSectors(uint8_t * buff, uint32_t sector, uint32_t count) +{ +#if defined(STM32F4) && !defined(BOOT) + if ((DWORD)buff < 0x20000000 || ((DWORD)buff & 3)) { + TRACE("disk_read bad alignment (%p)", buff); + while (count--) { + int8_t res = SD_ReadSectors((BYTE *)scratch, sector++, 1); + + if (res != 0) { + return res; + } + + memcpy(buff, scratch, BLOCK_SIZE); + + buff += BLOCK_SIZE; + } + + return 0; + } +#endif + + if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ + + if (count == 1) { /* Single block read */ + if (send_cmd(CMD17, sector) == 0) { /* READ_SINGLE_BLOCK */ + if (rcvr_datablock(buff, 512)) { + count = 0; + } + } + else { + spi_reset(); + } + } + else { /* Multiple block read */ + if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ + do { + if (!rcvr_datablock(buff, 512)) { + break; + } + buff += 512; + } while (--count); + send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ + } + else { + spi_reset(); + } + } + release_spi(); + TRACE_SD_CARD_EVENT((count != 0), sd_SD_ReadSectors, (count << 24) + ((sector/((CardType & CT_BLOCK) ? 1 : 512)) & 0x00FFFFFF)); + + return count ? -1 : 0; +} + +DRESULT disk_read ( + BYTE drv, /* Physical drive number (0) */ + BYTE *buff, /* Pointer to the data buffer to store read data */ + DWORD sector, /* Start sector number (LBA) */ + UINT count /* Sector count (1..255) */ +) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + int8_t res = SD_ReadSectors(buff, sector, count); + TRACE_SD_CARD_EVENT((res != 0), sd_disk_read, (count << 24) + (sector & 0x00FFFFFF)); + return (res != 0) ? RES_ERROR : RES_OK; +} + + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ +/*-----------------------------------------------------------------------*/ + +int8_t SD_WriteSectors(const uint8_t * buff, uint32_t sector, uint32_t count) +{ +#if defined(STM32F4) && !defined(BOOT) + if ((DWORD)buff < 0x20000000 || ((DWORD)buff & 3)) { + TRACE("disk_write bad alignment (%p)", buff); + while (count--) { + memcpy(scratch, buff, BLOCK_SIZE); + + int8_t res = SD_WriteSectors((const uint8_t *)scratch, sector++, 1); + + if (res != 0) { + return res; + } + + buff += BLOCK_SIZE; + } + + return 0; + } +#endif + + if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ + + if (count == 1) { /* Single block write */ + if (send_cmd(CMD24, sector) == 0) { /* WRITE_BLOCK */ + if (xmit_datablock(buff, 0xFE)) { + count = 0; + } + } + else { + spi_reset(); + } + } + else { /* Multiple block write */ + if (CardType & CT_SDC) send_cmd(ACMD23, count); + if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ + do { + if (!xmit_datablock(buff, 0xFC)) break; + buff += 512; + } while (--count); + if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ + count = 1; + } + else { + spi_reset(); + } + } + release_spi(); + TRACE_SD_CARD_EVENT((count != 0), sd_SD_WriteSectors, (count << 24) + ((sector/((CardType & CT_BLOCK) ? 1 : 512)) & 0x00FFFFFF)); + + return count ? -1 : 0; +} + +DRESULT disk_write ( + BYTE drv, /* Physical drive number (0) */ + const BYTE *buff, /* Pointer to the data to be written */ + DWORD sector, /* Start sector number (LBA) */ + UINT count /* Sector count (1..255) */ +) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + if (Stat & STA_PROTECT) return RES_WRPRT; + int8_t res = SD_WriteSectors(buff, sector, count); + TRACE_SD_CARD_EVENT((res != 0), sd_disk_write, (count << 24) + (sector & 0x00FFFFFF)); + return (res != 0) ? RES_ERROR : RES_OK; +} + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_ioctl ( + BYTE drv, /* Physical drive number (0) */ + BYTE ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ +) +{ + DRESULT res; + BYTE n, csd[16], *ptr = (BYTE *)buff; + WORD csize; + + if (drv) return RES_PARERR; + + res = RES_ERROR; + + if (ctrl == CTRL_POWER) { + switch (*ptr) { + case 0: /* Sub control code == 0 (POWER_OFF) */ + if (chk_power()) + power_off(); /* Power off */ + res = RES_OK; + break; + case 1: /* Sub control code == 1 (POWER_ON) */ + power_on(); /* Power on */ + res = RES_OK; + break; + case 2: /* Sub control code == 2 (POWER_GET) */ + *(ptr+1) = (BYTE)chk_power(); + res = RES_OK; + break; + default : + res = RES_PARERR; + } + } + else { + if (Stat & STA_NOINIT) { + return RES_NOTRDY; + } + + switch (ctrl) { + case CTRL_SYNC : /* Make sure that no pending write process */ + SD_SELECT(); + if (wait_ready() == 0xFF) { + res = RES_OK; + } + else { + TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_CTRL_SYNC, 0); + } + break; + + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ + if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { + if ((csd[0] >> 6) == 1) { /* SDC version 2.00 */ + csize = csd[9] + ((WORD)csd[8] << 8) + 1; + *(DWORD*)buff = (DWORD)csize << 10; + } + else { /* SDC version 1.XX or MMC*/ + n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; + csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; + *(DWORD*)buff = (DWORD)csize << (n - 9); + } + res = RES_OK; + } + else { + TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_GET_SECTOR_COUNT, 0); + } + break; + + case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ + *(WORD*)buff = 512; + res = RES_OK; + break; + + case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ + if (CardType & CT_SD2) { /* SDC version 2.00 */ + if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ + rcvr_spi(); + if (rcvr_datablock(csd, 16)) { /* Read partial block */ + for (n = 64 - 16; n; n--) rcvr_spi(); /* Purge trailing data */ + *(DWORD*)buff = 16UL << (csd[10] >> 4); + res = RES_OK; + } + } + } else { /* SDC version 1.XX or MMC */ + if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ + if (CardType & CT_SD1) { /* SDC version 1.XX */ + *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); + } else { /* MMC */ + *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); + } + res = RES_OK; + } + } + break; + + case MMC_GET_TYPE : /* Get card type flags (1 byte) */ + *ptr = CardType; + res = RES_OK; + break; + + case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ + if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ + && rcvr_datablock(ptr, 16)) { + res = RES_OK; + } + else { + TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_MMC_GET_CSD, 0); + } + break; + + case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ + if (send_cmd(CMD10, 0) == 0 /* READ_CID */ + && rcvr_datablock(ptr, 16)) { + res = RES_OK; + } + else { + TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_MMC_GET_CID, 0); + } + break; + + case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ + if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ + for (n = 4; n; n--) *ptr++ = rcvr_spi(); + res = RES_OK; + } + else { + TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_MMC_GET_OCR, 0); + } + break; + + case MMC_GET_SDSTAT : /* Receive SD status as a data block (64 bytes) */ + if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ + rcvr_spi(); + if (rcvr_datablock(ptr, 64)) { + res = RES_OK; + } + else { + TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_MMC_GET_SDSTAT_1, 0); + } + } + else { + TRACE_SD_CARD_EVENT(1, sd_disk_ioctl_MMC_GET_SDSTAT_2, 0); + } + break; + + default: + res = RES_PARERR; + } + + release_spi(); + } + + return res; +} + + +/*-----------------------------------------------------------------------*/ +/* Device Timer Interrupt Procedure (Platform dependent) */ +/*-----------------------------------------------------------------------*/ +/* This function must be called in period of 10ms */ + +void sdPoll10ms() +{ + static DWORD pv; + DWORD ns; + BYTE n, s; + + + n = Timer1; /* 100Hz decrement timers */ + if (n) Timer1 = --n; + n = Timer2; + if (n) Timer2 = --n; + + ns = pv; + pv = socket_is_empty() | socket_is_write_protected(); /* Sample socket switch */ + + if (ns == pv) { /* Have contacts stabled? */ + s = Stat; + + if (pv & socket_state_mask_wp) /* WP is H (write protected) */ + s |= STA_PROTECT; + else /* WP is L (write enabled) */ + s &= ~STA_PROTECT; + + if (pv & socket_state_mask_cp) /* INS = H (Socket empty) */ + s |= (STA_NODISK | STA_NOINIT); + else /* INS = L (Card inserted) */ + s &= ~STA_NODISK; + + Stat = s; + } +} + +// TODO everything here should not be in the driver layer ... + +FATFS g_FATFS_Obj; +#if defined(LOG_TELEMETRY) +FIL g_telemetryFile = {}; +#endif + +#if defined(BOOT) +void sdInit(void) +{ + if (f_mount(&g_FATFS_Obj, "", 1) == FR_OK) { + f_chdir("/"); + } +} +#else +// TODO shouldn't be there! +void sdInit(void) +{ + TRACE("sdInit"); + + ioMutex = CoCreateMutex(); + if (ioMutex >= CFG_MAX_MUTEX ) { + //sd error + return; + } + + if (f_mount(&g_FATFS_Obj, "", 1) == FR_OK) { + // call sdGetFreeSectors() now because f_getfree() takes a long time first time it's called + sdGetFreeSectors(); + +#if defined(LOG_TELEMETRY) + f_open(&g_telemetryFile, LOGS_PATH "/telemetry.log", FA_OPEN_ALWAYS | FA_WRITE); + if (f_size(&g_telemetryFile) > 0) { + f_lseek(&g_telemetryFile, f_size(&g_telemetryFile)); // append + } +#endif + } +} + +void sdDone() +{ + if (sdMounted()) { + audioQueue.stopSD(); +#if defined(LOG_TELEMETRY) + f_close(&g_telemetryFile); +#endif + f_mount(NULL, "", 0); // unmount SD + } +} +#endif + +uint32_t sdMounted() +{ + return g_FATFS_Obj.fs_type != 0; +} + +uint32_t sdIsHC() +{ + return (CardType & CT_BLOCK); +} + +uint32_t sdGetSpeed() +{ + return 330000; +} diff --git a/radio/src/targets/taranis/dwt.h b/radio/src/targets/taranis/dwt.h index 7cdf0437a..a267a797a 100644 --- a/radio/src/targets/taranis/dwt.h +++ b/radio/src/targets/taranis/dwt.h @@ -1,162 +1,162 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + diff --git a/radio/src/targets/taranis/extmodule_driver.cpp b/radio/src/targets/taranis/extmodule_driver.cpp index 652c0f81b..2667e4297 100644 --- a/radio/src/targets/taranis/extmodule_driver.cpp +++ b/radio/src/targets/taranis/extmodule_driver.cpp @@ -1,254 +1,254 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void extmoduleSendNextFrame(); - -void extmoduleStop() -{ - NVIC_DisableIRQ(EXTMODULE_DMA_IRQn); - NVIC_DisableIRQ(EXTMODULE_TIMER_CC_IRQn); - - EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - EXTMODULE_TIMER->DIER &= ~(TIM_DIER_CC2IE | TIM_DIER_UDE); - EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - - if (!IS_TRAINER_EXTERNAL_MODULE()) { - EXTERNAL_MODULE_OFF(); - } -} - -void extmoduleNoneStart() -{ - if (!IS_TRAINER_EXTERNAL_MODULE()) { - EXTERNAL_MODULE_OFF(); - } - - GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, 0); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); - GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high - - EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz - EXTMODULE_TIMER->ARR = 36000; // 18mS - EXTMODULE_TIMER->CCR2 = 32000; // Update time - EXTMODULE_TIMER->EGR = 1; // Restart - EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; - EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - - NVIC_EnableIRQ(EXTMODULE_TIMER_CC_IRQn); - NVIC_SetPriority(EXTMODULE_TIMER_CC_IRQn, 7); -} - -void extmodulePpmStart() -{ - EXTERNAL_MODULE_ON(); - - GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); - - EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz - EXTMODULE_TIMER->ARR = 45000; - EXTMODULE_TIMER->CCR1 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; - EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1NP : 0); // // we are using complementary output so logic has to be reversed here - EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high - EXTMODULE_TIMER->EGR = 1; - EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE; // PWM mode 1 - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - - extmoduleSendNextFrame(); - - NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); - NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); - NVIC_EnableIRQ(EXTMODULE_TIMER_CC_IRQn); - NVIC_SetPriority(EXTMODULE_TIMER_CC_IRQn, 7); -} - -void extmodulePxxStart() -{ - EXTERNAL_MODULE_ON(); - - GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); - - EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) - EXTMODULE_TIMER->ARR = 18000; - EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | TIM_CCER_CC1NE; - EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs - EXTMODULE_TIMER->CCR1 = 18; - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high - EXTMODULE_TIMER->EGR = 1; // Restart - EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - - extmoduleSendNextFrame(); - - NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); - NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); - NVIC_EnableIRQ(EXTMODULE_TIMER_CC_IRQn); - NVIC_SetPriority(EXTMODULE_TIMER_CC_IRQn, 7); -} - -#if defined(DSM2) || defined(MULTIMODULE) -void extmoduleDsm2Start() -{ - EXTERNAL_MODULE_ON(); - - GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); - - EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz - EXTMODULE_TIMER->ARR = 44000; // 22mS - EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP; - EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs - EXTMODULE_TIMER->CCR1 = 0; - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high - EXTMODULE_TIMER->EGR = 1; // Restart - EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0; - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - - extmoduleSendNextFrame(); - - NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); - NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); - NVIC_EnableIRQ(EXTMODULE_TIMER_CC_IRQn); - NVIC_SetPriority(EXTMODULE_TIMER_CC_IRQn, 7); -} -#endif - -void extmoduleCrossfireStart() -{ - EXTERNAL_MODULE_ON(); - - GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, 0); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); - GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high - - EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz - EXTMODULE_TIMER->ARR = (2000 * CROSSFIRE_FRAME_PERIOD); - EXTMODULE_TIMER->CCR2 = (2000 * CROSSFIRE_FRAME_PERIOD) - 1000; - EXTMODULE_TIMER->EGR = 1; // Restart - EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; - EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt - EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - - NVIC_EnableIRQ(EXTMODULE_TIMER_CC_IRQn); - NVIC_SetPriority(EXTMODULE_TIMER_CC_IRQn, 7); -} - -void extmoduleSendNextFrame() -{ - if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) { - EXTMODULE_TIMER->CCR1 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; - EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1NP : 0); // // we are using complementary output so logic has to be reversed here - EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance - EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; - EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); - EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].ppm.pulses); - EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].ppm.ptr - modulePulsesData[EXTERNAL_MODULE].ppm.pulses; - EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA - } - else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) { - EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].pxx.ptr - 1) - 4000; // 2mS in advance - EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; - EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); - EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].pxx.pulses); - EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].pxx.ptr - modulePulsesData[EXTERNAL_MODULE].pxx.pulses; - EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA - } - else if (IS_DSM2_PROTOCOL(s_current_protocol[EXTERNAL_MODULE]) || IS_MULTIMODULE_PROTOCOL(s_current_protocol[EXTERNAL_MODULE])) { - EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - 1) - 4000; // 2mS in advance - EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; - EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); - EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses); - EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - modulePulsesData[EXTERNAL_MODULE].dsm2.pulses; - EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA - } - else { - EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; - } -} - -extern "C" void EXTMODULE_DMA_IRQHandler() -{ - if (!DMA_GetITStatus(EXTMODULE_DMA_STREAM, EXTMODULE_DMA_FLAG_TC)) - return; - - DMA_ClearITPendingBit(EXTMODULE_DMA_STREAM, EXTMODULE_DMA_FLAG_TC); - - EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag - EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt -} - -extern "C" void EXTMODULE_TIMER_CC_IRQHandler() -{ - EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // Stop this interrupt - EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; - setupPulses(EXTERNAL_MODULE); - extmoduleSendNextFrame(); -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +void extmoduleSendNextFrame(); + +void extmoduleStop() +{ + NVIC_DisableIRQ(EXTMODULE_DMA_IRQn); + NVIC_DisableIRQ(EXTMODULE_TIMER_CC_IRQn); + + EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + EXTMODULE_TIMER->DIER &= ~(TIM_DIER_CC2IE | TIM_DIER_UDE); + EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + + if (!IS_TRAINER_EXTERNAL_MODULE()) { + EXTERNAL_MODULE_OFF(); + } +} + +void extmoduleNoneStart() +{ + if (!IS_TRAINER_EXTERNAL_MODULE()) { + EXTERNAL_MODULE_OFF(); + } + + GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, 0); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); + GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high + + EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz + EXTMODULE_TIMER->ARR = 36000; // 18mS + EXTMODULE_TIMER->CCR2 = 32000; // Update time + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; + EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; + + NVIC_EnableIRQ(EXTMODULE_TIMER_CC_IRQn); + NVIC_SetPriority(EXTMODULE_TIMER_CC_IRQn, 7); +} + +void extmodulePpmStart() +{ + EXTERNAL_MODULE_ON(); + + GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); + + EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz + EXTMODULE_TIMER->ARR = 45000; + EXTMODULE_TIMER->CCR1 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; + EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1NP : 0); // // we are using complementary output so logic has to be reversed here + EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high + EXTMODULE_TIMER->EGR = 1; + EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE; // PWM mode 1 + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; + + extmoduleSendNextFrame(); + + NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); + NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); + NVIC_EnableIRQ(EXTMODULE_TIMER_CC_IRQn); + NVIC_SetPriority(EXTMODULE_TIMER_CC_IRQn, 7); +} + +void extmodulePxxStart() +{ + EXTERNAL_MODULE_ON(); + + GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); + + EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) + EXTMODULE_TIMER->ARR = 18000; + EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | TIM_CCER_CC1NE; + EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs + EXTMODULE_TIMER->CCR1 = 18; + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; + + extmoduleSendNextFrame(); + + NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); + NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); + NVIC_EnableIRQ(EXTMODULE_TIMER_CC_IRQn); + NVIC_SetPriority(EXTMODULE_TIMER_CC_IRQn, 7); +} + +#if defined(DSM2) || defined(MULTIMODULE) +void extmoduleDsm2Start() +{ + EXTERNAL_MODULE_ON(); + + GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); + + EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz + EXTMODULE_TIMER->ARR = 44000; // 22mS + EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP; + EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs + EXTMODULE_TIMER->CCR1 = 0; + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0; + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; + + extmoduleSendNextFrame(); + + NVIC_EnableIRQ(EXTMODULE_DMA_IRQn); + NVIC_SetPriority(EXTMODULE_DMA_IRQn, 7); + NVIC_EnableIRQ(EXTMODULE_TIMER_CC_IRQn); + NVIC_SetPriority(EXTMODULE_TIMER_CC_IRQn, 7); +} +#endif + +void extmoduleCrossfireStart() +{ + EXTERNAL_MODULE_ON(); + + GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, 0); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure); + GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high + + EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz + EXTMODULE_TIMER->ARR = (2000 * CROSSFIRE_FRAME_PERIOD); + EXTMODULE_TIMER->CCR2 = (2000 * CROSSFIRE_FRAME_PERIOD) - 1000; + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; + EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; + + NVIC_EnableIRQ(EXTMODULE_TIMER_CC_IRQn); + NVIC_SetPriority(EXTMODULE_TIMER_CC_IRQn, 7); +} + +void extmoduleSendNextFrame() +{ + if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) { + EXTMODULE_TIMER->CCR1 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; + EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1NP : 0); // // we are using complementary output so logic has to be reversed here + EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance + EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; + EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); + EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].ppm.pulses); + EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].ppm.ptr - modulePulsesData[EXTERNAL_MODULE].ppm.pulses; + EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA + } + else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) { + EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].pxx.ptr - 1) - 4000; // 2mS in advance + EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; + EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); + EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].pxx.pulses); + EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].pxx.ptr - modulePulsesData[EXTERNAL_MODULE].pxx.pulses; + EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA + } + else if (IS_DSM2_PROTOCOL(s_current_protocol[EXTERNAL_MODULE]) || IS_MULTIMODULE_PROTOCOL(s_current_protocol[EXTERNAL_MODULE])) { + EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - 1) - 4000; // 2mS in advance + EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; + EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); + EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses); + EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - modulePulsesData[EXTERNAL_MODULE].dsm2.pulses; + EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA + } + else { + EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; + } +} + +extern "C" void EXTMODULE_DMA_IRQHandler() +{ + if (!DMA_GetITStatus(EXTMODULE_DMA_STREAM, EXTMODULE_DMA_FLAG_TC)) + return; + + DMA_ClearITPendingBit(EXTMODULE_DMA_STREAM, EXTMODULE_DMA_FLAG_TC); + + EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag + EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt +} + +extern "C" void EXTMODULE_TIMER_CC_IRQHandler() +{ + EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // Stop this interrupt + EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; + setupPulses(EXTERNAL_MODULE); + extmoduleSendNextFrame(); +} diff --git a/radio/src/targets/taranis/hal.h b/radio/src/targets/taranis/hal.h index 65cf327b3..49db43681 100644 --- a/radio/src/targets/taranis/hal.h +++ b/radio/src/targets/taranis/hal.h @@ -1,833 +1,833 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _HAL_H_ -#define _HAL_H_ - -// Keys -#if defined(PCBX7) - #define KEYS_GPIO_REG_PAGE GPIOD->IDR - #define KEYS_GPIO_PIN_PAGE GPIO_Pin_3 // PD.03 - #define KEYS_GPIO_REG_MENU GPIOD->IDR - #define KEYS_GPIO_PIN_MENU GPIO_Pin_7 // PD.07 - #define KEYS_GPIO_REG_EXIT GPIOD->IDR - #define KEYS_GPIO_PIN_EXIT GPIO_Pin_2 // PD.02 -#else - #define KEYS_GPIO_REG_MENU GPIOD->IDR - #define KEYS_GPIO_PIN_MENU GPIO_Pin_7 // PD.07 - #define KEYS_GPIO_REG_EXIT GPIOD->IDR - #define KEYS_GPIO_PIN_EXIT GPIO_Pin_2 // PD.02 - #define KEYS_GPIO_REG_PAGE GPIOD->IDR - #define KEYS_GPIO_PIN_PAGE GPIO_Pin_3 // PD.03 -#endif - -#if defined(PCBX9E) - #define KEYS_GPIO_REG_ENTER GPIOF->IDR - #define KEYS_GPIO_PIN_ENTER GPIO_Pin_0 // PF.00 -#elif defined(PCBX7) - #define KEYS_GPIO_REG_ENTER GPIOE->IDR - #define KEYS_GPIO_PIN_ENTER GPIO_Pin_10 // PE.10 -#else - #define KEYS_GPIO_REG_PLUS GPIOE->IDR - #define KEYS_GPIO_PIN_PLUS GPIO_Pin_10 // PE.10 - #define KEYS_GPIO_REG_MINUS GPIOE->IDR - #define KEYS_GPIO_PIN_MINUS GPIO_Pin_11 // PE.11 - #define KEYS_GPIO_REG_ENTER GPIOE->IDR - #define KEYS_GPIO_PIN_ENTER GPIO_Pin_12 // PE.12 -#endif - -// Rotary Encoder -#if defined(PCBX9E) - #define ENC_GPIO GPIOD - #define ENC_GPIO_PIN_A GPIO_Pin_12 // PD.12 - #define ENC_GPIO_PIN_B GPIO_Pin_13 // PD.13 - #define ROTARY_ENCODER_POSITION() (ENC_GPIO->IDR >> 12) & 0x03 -#elif defined(PCBX7) - #define ENC_GPIO GPIOE - #define ENC_GPIO_PIN_A GPIO_Pin_9 // PE.09 - #define ENC_GPIO_PIN_B GPIO_Pin_11 // PE.11 - #define ROTARY_ENCODER_POSITION() (((ENC_GPIO->IDR >> 10) & 0x02) + ((ENC_GPIO->IDR >> 9) & 0x01)) -#endif - -// This is for SIMU: reuse rotary encoder pins to map UP and DOWN keyboard keys -#if defined(SIMU) && (defined(PCBX9E) || defined(PCBX7)) - #define KEYS_GPIO_REG_PLUS ENC_GPIO->IDR - #define KEYS_GPIO_PIN_PLUS ENC_GPIO_PIN_A - #define KEYS_GPIO_REG_MINUS ENC_GPIO->IDR - #define KEYS_GPIO_PIN_MINUS ENC_GPIO_PIN_B -#endif - -// Trims -#if defined(PCBX9E) - #define TRIMS_GPIO_REG_LHL GPIOG->IDR - #define TRIMS_GPIO_PIN_LHL GPIO_Pin_1 // PG.01 - #define TRIMS_GPIO_REG_LHR GPIOG->IDR - #define TRIMS_GPIO_PIN_LHR GPIO_Pin_0 // PG.00 - #define TRIMS_GPIO_REG_LVD GPIOE->IDR - #define TRIMS_GPIO_PIN_LVD GPIO_Pin_4 // PE.04 - #define TRIMS_GPIO_REG_LVU GPIOE->IDR - #define TRIMS_GPIO_PIN_LVU GPIO_Pin_3 // PE.03 - #define TRIMS_GPIO_REG_RVD GPIOC->IDR - #define TRIMS_GPIO_PIN_RVD GPIO_Pin_3 // PC.03 - #define TRIMS_GPIO_REG_RHL GPIOC->IDR - #define TRIMS_GPIO_PIN_RHL GPIO_Pin_1 // PC.01 - #define TRIMS_GPIO_REG_RVU GPIOC->IDR - #define TRIMS_GPIO_PIN_RVU GPIO_Pin_2 // PC.02 - #define TRIMS_GPIO_REG_RHR GPIOC->IDR - #define TRIMS_GPIO_PIN_RHR GPIO_Pin_13 // PC.13 -#elif defined(PCBX7) - #define TRIMS_GPIO_REG_LHL GPIOD->IDR - #define TRIMS_GPIO_PIN_LHL GPIO_Pin_15 // PD.15 - #define TRIMS_GPIO_REG_LHR GPIOC->IDR - #define TRIMS_GPIO_PIN_LHR GPIO_Pin_1 // PC.01 - #define TRIMS_GPIO_REG_LVD GPIOE->IDR - #define TRIMS_GPIO_PIN_LVD GPIO_Pin_6 // PE.06 - #define TRIMS_GPIO_REG_LVU GPIOE->IDR - #define TRIMS_GPIO_PIN_LVU GPIO_Pin_5 // PE.05 - #define TRIMS_GPIO_REG_RVD GPIOC->IDR - #define TRIMS_GPIO_PIN_RVD GPIO_Pin_3 // PC.03 - #define TRIMS_GPIO_REG_RHL GPIOE->IDR - #define TRIMS_GPIO_PIN_RHL GPIO_Pin_3 // PE.03 - #define TRIMS_GPIO_REG_RVU GPIOC->IDR - #define TRIMS_GPIO_PIN_RVU GPIO_Pin_2 // PC.02 - #define TRIMS_GPIO_REG_RHR GPIOE->IDR - #define TRIMS_GPIO_PIN_RHR GPIO_Pin_4 // PE.04 -#else - #define TRIMS_GPIO_REG_LHL GPIOE->IDR - #define TRIMS_GPIO_PIN_LHL GPIO_Pin_4 // PE.04 - #define TRIMS_GPIO_REG_LHR GPIOE->IDR - #define TRIMS_GPIO_PIN_LHR GPIO_Pin_3 // PE.03 - #define TRIMS_GPIO_REG_LVD GPIOE->IDR - #define TRIMS_GPIO_PIN_LVD GPIO_Pin_6 // PE.06 - #define TRIMS_GPIO_REG_LVU GPIOE->IDR - #define TRIMS_GPIO_PIN_LVU GPIO_Pin_5 // PE.05 - #define TRIMS_GPIO_REG_RVD GPIOC->IDR - #define TRIMS_GPIO_PIN_RVD GPIO_Pin_3 // PC.03 - #define TRIMS_GPIO_REG_RHL GPIOC->IDR - #define TRIMS_GPIO_PIN_RHL GPIO_Pin_1 // PC.01 - #define TRIMS_GPIO_REG_RVU GPIOC->IDR - #define TRIMS_GPIO_PIN_RVU GPIO_Pin_2 // PC.02 - #define TRIMS_GPIO_REG_RHR GPIOC->IDR - #define TRIMS_GPIO_PIN_RHR GPIO_Pin_13 // PC.13 -#endif - -// Switches -#if defined(PCBX9E) - #define SWITCHES_GPIO_REG_A_H GPIOD->IDR - #define SWITCHES_GPIO_PIN_A_H GPIO_Pin_10 // PD.10 - #define SWITCHES_GPIO_REG_A_L GPIOD->IDR - #define SWITCHES_GPIO_PIN_A_L GPIO_Pin_14 // PD.14 -#elif defined(PCBX7) - #define SWITCHES_GPIO_REG_A_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_A_L GPIO_Pin_7 // PE.07 - #define SWITCHES_GPIO_REG_A_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_A_H GPIO_Pin_13 // PE.13 -#else - #define SWITCHES_GPIO_REG_A_H GPIOB->IDR - #define SWITCHES_GPIO_PIN_A_H GPIO_Pin_5 // PB.05 - #define SWITCHES_GPIO_REG_A_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_A_L GPIO_Pin_0 // PE.00 -#endif - -#if defined(PCBX9E) - #define SWITCHES_GPIO_REG_B_H GPIOG->IDR - #define SWITCHES_GPIO_PIN_B_H GPIO_Pin_11 // PG.11 - #define SWITCHES_GPIO_REG_B_L GPIOG->IDR - #define SWITCHES_GPIO_PIN_B_L GPIO_Pin_10 // PG.10 -#elif defined(PCBX7) - #define SWITCHES_GPIO_REG_B_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_B_L GPIO_Pin_15 // PE.15 - #define SWITCHES_GPIO_REG_B_H GPIOA->IDR - #define SWITCHES_GPIO_PIN_B_H GPIO_Pin_5 // PA.05 -#else - #define SWITCHES_GPIO_REG_B_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_B_H GPIO_Pin_1 // PE.01 - #define SWITCHES_GPIO_REG_B_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_B_L GPIO_Pin_2 // PE.02 -#endif - -#if defined(PCBX9E) - #define SWITCHES_GPIO_REG_C_H GPIOF->IDR - #define SWITCHES_GPIO_PIN_C_H GPIO_Pin_13 // PF.13 - #define SWITCHES_GPIO_REG_C_L GPIOF->IDR - #define SWITCHES_GPIO_PIN_C_L GPIO_Pin_14 // PF.14 -#elif defined(PCBX7) - #define SWITCHES_GPIO_REG_C_L GPIOD->IDR - #define SWITCHES_GPIO_PIN_C_L GPIO_Pin_11 // PD.11 - #define SWITCHES_GPIO_REG_C_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_C_H GPIO_Pin_0 // PE.00 -#else - #define SWITCHES_GPIO_REG_C_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_C_H GPIO_Pin_15 // PE.15 - #define SWITCHES_GPIO_REG_C_L GPIOA->IDR - #define SWITCHES_GPIO_PIN_C_L GPIO_Pin_5 // PA.05 -#endif - -#if defined(PCBX9E) - #define SWITCHES_GPIO_REG_D_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_D_H GPIO_Pin_1 // PE.01 - #define SWITCHES_GPIO_REG_D_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_D_L GPIO_Pin_2 // PE.02 -#elif defined(PCBX9DP) - #define SWITCHES_GPIO_REG_D_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_D_H GPIO_Pin_7 // PE.07 - #define SWITCHES_GPIO_REG_D_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_D_L GPIO_Pin_13 // PE.13 -#elif defined(PCBX7) - #define SWITCHES_GPIO_REG_D_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_D_L GPIO_Pin_1 // PE.01 - #define SWITCHES_GPIO_REG_D_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_D_H GPIO_Pin_2 // PE.02 -#else - #define SWITCHES_GPIO_REG_D_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_D_H GPIO_Pin_7 // PE.07 - #define SWITCHES_GPIO_REG_D_L GPIOB->IDR - #define SWITCHES_GPIO_PIN_D_L GPIO_Pin_1 // PB.01 -#endif - -#if defined(PCBX9E) - #define SWITCHES_GPIO_REG_E_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_E_H GPIO_Pin_7 // PE.07 - #define SWITCHES_GPIO_REG_E_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_E_L GPIO_Pin_13 // PE.13 -#elif !defined(PCBX7) - #define SWITCHES_GPIO_REG_E_H GPIOB->IDR - #define SWITCHES_GPIO_PIN_E_H GPIO_Pin_3 // PB.03 - #define SWITCHES_GPIO_REG_E_L GPIOB->IDR - #define SWITCHES_GPIO_PIN_E_L GPIO_Pin_4 // PB.04 -#endif - -#if defined(PCBX9E) - #define SWITCHES_GPIO_REG_F GPIOE->IDR - #define SWITCHES_GPIO_PIN_F GPIO_Pin_11 // PE.11 -#elif defined(PCBX7) - #define SWITCHES_GPIO_REG_F GPIOE->IDR - #define SWITCHES_GPIO_PIN_F GPIO_Pin_14 // PE.14 -#else - #define SWITCHES_GPIO_REG_F GPIOE->IDR - #define SWITCHES_GPIO_PIN_F GPIO_Pin_14 // PE.14 -#endif - -#if defined(PCBX9E) - #define SWITCHES_GPIO_REG_G_H GPIOF->IDR - #define SWITCHES_GPIO_PIN_G_H GPIO_Pin_3 // PF.03 - #define SWITCHES_GPIO_REG_G_L GPIOF->IDR - #define SWITCHES_GPIO_PIN_G_L GPIO_Pin_4 // PF.04 -#elif !defined(PCBX7) - #define SWITCHES_GPIO_REG_G_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_G_H GPIO_Pin_9 // PE.09 - #define SWITCHES_GPIO_REG_G_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_G_L GPIO_Pin_8 // PE.08 -#endif - -#if defined(PCBX9E) - #define SWITCHES_GPIO_REG_H GPIOF->IDR - #define SWITCHES_GPIO_PIN_H GPIO_Pin_1 // PF.01 -#elif defined(PCBX9DP) - #define SWITCHES_GPIO_REG_H GPIOD->IDR - #define SWITCHES_GPIO_PIN_H GPIO_Pin_14 // PD.14 -#elif defined(PCBX7) - #define SWITCHES_GPIO_REG_H GPIOD->IDR - #define SWITCHES_GPIO_PIN_H GPIO_Pin_14 // PD.14 -#else - #define SWITCHES_GPIO_REG_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_H GPIO_Pin_13 // PE.13 -#endif - -#if defined(PCBX9E) - #define SWITCHES_GPIO_REG_I_H GPIOF->IDR - #define SWITCHES_GPIO_PIN_I_H GPIO_Pin_15 // PF.15 - #define SWITCHES_GPIO_REG_I_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_I_L GPIO_Pin_14 // PE.14 - #define SWITCHES_GPIO_REG_J_H GPIOG->IDR - #define SWITCHES_GPIO_PIN_J_H GPIO_Pin_7 // PG.07 - #define SWITCHES_GPIO_REG_J_L GPIOG->IDR - #define SWITCHES_GPIO_PIN_J_L GPIO_Pin_8 // PG.08 - #define SWITCHES_GPIO_REG_K_H GPIOG->IDR - #define SWITCHES_GPIO_PIN_K_H GPIO_Pin_13 // PG.13 - #define SWITCHES_GPIO_REG_K_L GPIOG->IDR - #define SWITCHES_GPIO_PIN_K_L GPIO_Pin_12 // PG.12 - #define SWITCHES_GPIO_REG_L_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_L_H GPIO_Pin_9 // PE.09 - #define SWITCHES_GPIO_REG_L_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_L_L GPIO_Pin_8 // PE.08 - #define SWITCHES_GPIO_REG_M_H GPIOE->IDR - #define SWITCHES_GPIO_PIN_M_H GPIO_Pin_15 // PE.15 - #define SWITCHES_GPIO_REG_M_L GPIOA->IDR - #define SWITCHES_GPIO_PIN_M_L GPIO_Pin_5 // PA.05 - #define SWITCHES_GPIO_REG_N_H GPIOB->IDR - #define SWITCHES_GPIO_PIN_N_H GPIO_Pin_3 // PB.03 - #define SWITCHES_GPIO_REG_N_L GPIOB->IDR - #define SWITCHES_GPIO_PIN_N_L GPIO_Pin_4 // PB.04 - #define SWITCHES_GPIO_REG_O_H GPIOF->IDR - #define SWITCHES_GPIO_PIN_O_H GPIO_Pin_7 // PF.07 - #define SWITCHES_GPIO_REG_O_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_O_L GPIO_Pin_10 // PE.10 - #define SWITCHES_GPIO_REG_P_H GPIOF->IDR - #define SWITCHES_GPIO_PIN_P_H GPIO_Pin_11 // PF.11 - #define SWITCHES_GPIO_REG_P_L GPIOF->IDR - #define SWITCHES_GPIO_PIN_P_L GPIO_Pin_12 // PF.12 - #define SWITCHES_GPIO_REG_Q_H GPIOF->IDR - #define SWITCHES_GPIO_PIN_Q_H GPIO_Pin_5 // PF.05 - #define SWITCHES_GPIO_REG_Q_L GPIOF->IDR - #define SWITCHES_GPIO_PIN_Q_L GPIO_Pin_6 // PF.06 - #define SWITCHES_GPIO_REG_R_H GPIOB->IDR - #define SWITCHES_GPIO_PIN_R_H GPIO_Pin_5 // PB.05 - #define SWITCHES_GPIO_REG_R_L GPIOE->IDR - #define SWITCHES_GPIO_PIN_R_L GPIO_Pin_0 // PE.00 -#endif - -#if defined(PCBX9E) - #define KEYS_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA|RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOC|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG) - #define KEYS_GPIOA_PINS (SWITCHES_GPIO_PIN_M_L) - #define KEYS_GPIOB_PINS (SWITCHES_GPIO_PIN_N_H | SWITCHES_GPIO_PIN_N_L | SWITCHES_GPIO_PIN_R_H) - #define KEYS_GPIOC_PINS (TRIMS_GPIO_PIN_RVD | TRIMS_GPIO_PIN_RVU | TRIMS_GPIO_PIN_RHL | TRIMS_GPIO_PIN_RHR) - #define KEYS_GPIOD_PINS (KEYS_GPIO_PIN_MENU | KEYS_GPIO_PIN_EXIT | KEYS_GPIO_PIN_PAGE | SWITCHES_GPIO_PIN_A_H | SWITCHES_GPIO_PIN_A_L | ENC_GPIO_PIN_A | ENC_GPIO_PIN_B) - #define KEYS_GPIOE_PINS (TRIMS_GPIO_PIN_LVU | TRIMS_GPIO_PIN_LVD | SWITCHES_GPIO_PIN_D_H | SWITCHES_GPIO_PIN_D_L| SWITCHES_GPIO_PIN_E_H | SWITCHES_GPIO_PIN_E_L | SWITCHES_GPIO_PIN_F | SWITCHES_GPIO_PIN_I_L | SWITCHES_GPIO_PIN_L_H | SWITCHES_GPIO_PIN_L_L | SWITCHES_GPIO_PIN_M_H | SWITCHES_GPIO_PIN_O_L | SWITCHES_GPIO_PIN_R_L) - #define KEYS_GPIOF_PINS (KEYS_GPIO_PIN_ENTER | SWITCHES_GPIO_PIN_C_H | SWITCHES_GPIO_PIN_C_L | SWITCHES_GPIO_PIN_G_H | SWITCHES_GPIO_PIN_G_L | SWITCHES_GPIO_PIN_H | SWITCHES_GPIO_PIN_I_H | SWITCHES_GPIO_PIN_O_H | SWITCHES_GPIO_PIN_P_H | SWITCHES_GPIO_PIN_P_L | SWITCHES_GPIO_PIN_Q_H | SWITCHES_GPIO_PIN_Q_L) - #define KEYS_GPIOG_PINS (TRIMS_GPIO_PIN_LHL | TRIMS_GPIO_PIN_LHR| SWITCHES_GPIO_PIN_B_H | SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_J_H | SWITCHES_GPIO_PIN_J_L | SWITCHES_GPIO_PIN_K_H | SWITCHES_GPIO_PIN_K_L) -#elif defined(PCBX9DP) - #define KEYS_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA|RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOC|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE) - #define KEYS_GPIOA_PINS (SWITCHES_GPIO_PIN_C_L) - #define KEYS_GPIOB_PINS (SWITCHES_GPIO_PIN_E_L | SWITCHES_GPIO_PIN_E_H | SWITCHES_GPIO_PIN_A_H) - #define KEYS_GPIOC_PINS (TRIMS_GPIO_PIN_RVD | TRIMS_GPIO_PIN_RVU | TRIMS_GPIO_PIN_RHL | TRIMS_GPIO_PIN_RHR) - #define KEYS_GPIOD_PINS (KEYS_GPIO_PIN_MENU | KEYS_GPIO_PIN_EXIT | KEYS_GPIO_PIN_PAGE | SWITCHES_GPIO_PIN_H) - #define KEYS_GPIOE_PINS (KEYS_GPIO_PIN_PLUS | KEYS_GPIO_PIN_ENTER | KEYS_GPIO_PIN_MINUS | TRIMS_GPIO_PIN_LHR | TRIMS_GPIO_PIN_LHL | TRIMS_GPIO_PIN_LVD | TRIMS_GPIO_PIN_LVU | SWITCHES_GPIO_PIN_F | SWITCHES_GPIO_PIN_A_L | SWITCHES_GPIO_PIN_B_H | SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_C_H | SWITCHES_GPIO_PIN_D_H | SWITCHES_GPIO_PIN_D_L | SWITCHES_GPIO_PIN_G_H | SWITCHES_GPIO_PIN_G_L) -#elif defined(PCBX7) - #define KEYS_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOC|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE) - #define KEYS_GPIOA_PINS SWITCHES_GPIO_PIN_B_H - #define KEYS_GPIOC_PINS (TRIMS_GPIO_PIN_LHR | TRIMS_GPIO_PIN_RVD | TRIMS_GPIO_PIN_RVU) - #define KEYS_GPIOD_PINS (TRIMS_GPIO_PIN_LHL | KEYS_GPIO_PIN_MENU | KEYS_GPIO_PIN_EXIT | KEYS_GPIO_PIN_PAGE | SWITCHES_GPIO_PIN_C_L | SWITCHES_GPIO_PIN_H) - #define KEYS_GPIOE_PINS (ENC_GPIO_PIN_A | ENC_GPIO_PIN_B | KEYS_GPIO_PIN_ENTER | TRIMS_GPIO_PIN_RHR | TRIMS_GPIO_PIN_RHL | TRIMS_GPIO_PIN_LVD | TRIMS_GPIO_PIN_LVU | SWITCHES_GPIO_PIN_C_H | SWITCHES_GPIO_PIN_D_L | SWITCHES_GPIO_PIN_D_H | SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_A_L | SWITCHES_GPIO_PIN_A_H | SWITCHES_GPIO_PIN_F) -#else - #define KEYS_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA|RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOC|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE) - #define KEYS_GPIOA_PINS (SWITCHES_GPIO_PIN_C_L) - #define KEYS_GPIOB_PINS (SWITCHES_GPIO_PIN_E_L | SWITCHES_GPIO_PIN_E_H | SWITCHES_GPIO_PIN_A_H | SWITCHES_GPIO_PIN_D_L) - #define KEYS_GPIOC_PINS (TRIMS_GPIO_PIN_RVD | TRIMS_GPIO_PIN_RVU | TRIMS_GPIO_PIN_RHL | TRIMS_GPIO_PIN_RHR) - #define KEYS_GPIOD_PINS (KEYS_GPIO_PIN_MENU | KEYS_GPIO_PIN_EXIT | KEYS_GPIO_PIN_PAGE) - #define KEYS_GPIOE_PINS (KEYS_GPIO_PIN_PLUS | KEYS_GPIO_PIN_ENTER | KEYS_GPIO_PIN_MINUS | TRIMS_GPIO_PIN_LHR | TRIMS_GPIO_PIN_LHL | TRIMS_GPIO_PIN_LVD | TRIMS_GPIO_PIN_LVU | SWITCHES_GPIO_PIN_F | SWITCHES_GPIO_PIN_A_L | SWITCHES_GPIO_PIN_B_H | SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_C_H | SWITCHES_GPIO_PIN_D_H | SWITCHES_GPIO_PIN_G_H | SWITCHES_GPIO_PIN_G_L | SWITCHES_GPIO_PIN_H) -#endif - -// ADC -#if defined(PCBX9E) - #define ADC_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_DMA2) - #define ADC_RCC_APB2Periph (RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC3) -#else - #define ADC_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_DMA2) - #define ADC_RCC_APB2Periph RCC_APB2Periph_ADC1 -#endif -#define ADC_GPIO_PIN_STICK_RV GPIO_Pin_0 // PA.00 -#define ADC_GPIO_PIN_STICK_RH GPIO_Pin_1 // PA.01 -#if defined(PCBX7) - #define ADC_GPIO_PIN_STICK_LV GPIO_Pin_2 // PA.02 - #define ADC_GPIO_PIN_STICK_LH GPIO_Pin_3 // PA.03 - #define ADC_CHANNEL_STICK_LV ADC_Channel_2 // ADC1_IN2 - #define ADC_CHANNEL_STICK_LH ADC_Channel_3 // ADC1_IN3 -#else - #define ADC_GPIO_PIN_STICK_LH GPIO_Pin_2 // PA.02 - #define ADC_GPIO_PIN_STICK_LV GPIO_Pin_3 // PA.03 - #define ADC_CHANNEL_STICK_LH ADC_Channel_2 // ADC1_IN2 - #define ADC_CHANNEL_STICK_LV ADC_Channel_3 // ADC1_IN3 -#endif -#define ADC_CHANNEL_STICK_RV ADC_Channel_0 // ADC1_IN0 -#define ADC_CHANNEL_STICK_RH ADC_Channel_1 // ADC1_IN1 -#define ADC_MAIN ADC1 -#define ADC_DMA DMA2 -#define ADC_DMA_SxCR_CHSEL 0 -#define ADC_DMA_Stream DMA2_Stream4 -#define ADC_SET_DMA_FLAGS() ADC_DMA->HIFCR = (DMA_HIFCR_CTCIF4 | DMA_HIFCR_CHTIF4 | DMA_HIFCR_CTEIF4 | DMA_HIFCR_CDMEIF4 | DMA_HIFCR_CFEIF4) -#define ADC_TRANSFER_COMPLETE() (ADC_DMA->HISR & DMA_HISR_TCIF4) -#define ADC_SAMPTIME 2 // sample time = 28 cycles - -#if defined(PCBX9E) - #define ADC_GPIO_PIN_POT1 GPIO_Pin_8 // PF.08 - #define ADC_GPIO_PIN_POT2 GPIO_Pin_0 // PB.00 - #define ADC_GPIO_PIN_POT3 GPIO_Pin_5 // PC.05 - #define ADC_GPIO_PIN_POT4 GPIO_Pin_4 // PC.04 - #define ADC_GPIO_PIN_SLIDER1 GPIO_Pin_10 // PF.10 - #define ADC_GPIO_PIN_SLIDER2 GPIO_Pin_9 // PF.09 - #define ADC_GPIO_PIN_SLIDER3 GPIO_Pin_6 // PA.06 - #define ADC_GPIO_PIN_SLIDER4 GPIO_Pin_1 // PB.01 - #define ADC_GPIO_PIN_BATT GPIO_Pin_0 // PC.00 - #define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_STICK_RH | ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_SLIDER3) - #define ADC_GPIOB_PINS (ADC_GPIO_PIN_POT2 | ADC_GPIO_PIN_SLIDER4) - #define ADC_GPIOC_PINS (ADC_GPIO_PIN_POT3 | ADC_GPIO_PIN_POT4 | ADC_GPIO_PIN_SLIDER1 | ADC_GPIO_PIN_SLIDER2 | ADC_GPIO_PIN_BATT) - #define ADC_GPIOF_PINS (ADC_GPIO_PIN_POT1 | ADC_GPIO_PIN_SLIDER1 | ADC_GPIO_PIN_SLIDER2) - #define ADC_CHANNEL_POT1 ADC_Channel_6 // ADC3_IN6 - #define ADC_CHANNEL_POT2 ADC_Channel_8 // ADC1_IN8 - #define ADC_CHANNEL_POT3 ADC_Channel_15 // ADC1_IN15 - #define ADC_CHANNEL_POT4 ADC_Channel_14 // ADC1_IN14 - #define ADC_CHANNEL_SLIDER1 ADC_Channel_8 // ADC3_IN8 - #define ADC_CHANNEL_SLIDER2 ADC_Channel_7 // ADC3_IN7 - #define ADC_CHANNEL_SLIDER3 ADC_Channel_6 // ADC1_IN6 - #define ADC_CHANNEL_SLIDER4 ADC_Channel_9 // ADC1_IN9 - #define ADC_CHANNEL_BATT ADC_Channel_10 // ADC1_IN10 - #define ADC_EXT ADC3 - #define ADC_EXT_DMA DMA2 - #define ADC_EXT_DMA_Stream DMA2_Stream0 - #define ADC_EXT_SET_DMA_FLAGS() ADC_DMA->LIFCR = (DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 | DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0) - #define ADC_EXT_TRANSFER_COMPLETE() (ADC_DMA->LISR & DMA_LISR_TCIF0) - #define ADC_EXT_SAMPTIME 3 // sample time = 56 cycles -#elif defined(PCBX9DP) - #define ADC_GPIO_PIN_POT1 GPIO_Pin_6 // PA.06 - #define ADC_GPIO_PIN_POT2 GPIO_Pin_0 // PB.00 - #define ADC_GPIO_PIN_POT3 GPIO_Pin_1 // PB.01 - #define ADC_GPIO_PIN_SLIDER1 GPIO_Pin_4 // PC.04 - #define ADC_GPIO_PIN_SLIDER2 GPIO_Pin_5 // PC.05 - #define ADC_GPIO_PIN_BATT GPIO_Pin_0 // PC.00 - #define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_STICK_RH | ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT1) - #define ADC_GPIOB_PINS (ADC_GPIO_PIN_POT2 | ADC_GPIO_PIN_POT3) - #define ADC_GPIOC_PINS (ADC_GPIO_PIN_SLIDER1 | ADC_GPIO_PIN_SLIDER2 | ADC_GPIO_PIN_BATT) - #define ADC_CHANNEL_POT1 ADC_Channel_6 - #define ADC_CHANNEL_POT2 ADC_Channel_8 - #define ADC_CHANNEL_POT3 ADC_Channel_9 - #define ADC_CHANNEL_SLIDER1 ADC_Channel_14 - #define ADC_CHANNEL_SLIDER2 ADC_Channel_15 - #define ADC_CHANNEL_BATT ADC_Channel_10 -#elif defined(PCBX7) - #define ADC_GPIO_PIN_POT1 GPIO_Pin_6 // PA.06 - #define ADC_GPIO_PIN_POT2 GPIO_Pin_0 // PB.00 - #define ADC_GPIO_PIN_BATT GPIO_Pin_0 // PC.00 - #define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_STICK_RH | ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT1) - #define ADC_GPIOB_PINS ADC_GPIO_PIN_POT2 - #define ADC_GPIOC_PINS ADC_GPIO_PIN_BATT - #define ADC_CHANNEL_POT1 ADC_Channel_6 - #define ADC_CHANNEL_POT2 ADC_Channel_8 - #define ADC_CHANNEL_BATT ADC_Channel_10 -#else - #define ADC_GPIO_PIN_POT1 GPIO_Pin_6 // PA.06 - #define ADC_GPIO_PIN_POT2 GPIO_Pin_0 // PB.00 - #define ADC_GPIO_PIN_SLIDER1 GPIO_Pin_4 // PC.04 - #define ADC_GPIO_PIN_SLIDER2 GPIO_Pin_5 // PC.05 - #define ADC_GPIO_PIN_BATT GPIO_Pin_0 // PC.00 - #define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_STICK_RH | ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT1) - #define ADC_GPIOB_PINS (ADC_GPIO_PIN_POT2) - #define ADC_GPIOC_PINS (ADC_GPIO_PIN_SLIDER1 | ADC_GPIO_PIN_SLIDER2 | ADC_GPIO_PIN_BATT) - #define ADC_CHANNEL_POT1 ADC_Channel_6 - #define ADC_CHANNEL_POT2 ADC_Channel_8 - #define ADC_CHANNEL_POT3 ADC_Channel_9 - #define ADC_CHANNEL_SLIDER1 ADC_Channel_14 - #define ADC_CHANNEL_SLIDER2 ADC_Channel_15 - #define ADC_CHANNEL_BATT ADC_Channel_10 -#endif - -// PWR and LED driver -#define PWR_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD) -#if defined(PCBX9E) || defined(PCBX7) -#define PWR_PRESS_BUTTON -#endif -#define PWR_GPIO GPIOD -#define PWR_SWITCH_GPIO_PIN GPIO_Pin_1 // PD.01 -#define PWR_ON_GPIO_PIN GPIO_Pin_0 // PD.00 -#if defined(PCBX7) -#define LED_GREEN_GPIO GPIOC -#define LED_GREEN_GPIO_PIN GPIO_Pin_4 // PC.04 -#define LED_RED_GPIO GPIOC -#define LED_RED_GPIO_PIN GPIO_Pin_5 // PC.05 -#define LED_BLUE_GPIO GPIOB -#define LED_BLUE_GPIO_PIN GPIO_Pin_1 // PB.01 -#endif - -// Internal Module -#define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) -#define INTMODULE_RCC_APB2Periph RCC_APB2Periph_TIM1 -#if defined(PCBX9E) || defined(PCBX9DP) || defined(PCBX7) - #define INTMODULE_PWR_GPIO GPIOC - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_6 // PC.06 -#else - #define INTMODULE_PWR_GPIO GPIOD - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_15 // PD.15 -#endif -#define INTMODULE_PPM_GPIO GPIOA -#define INTMODULE_PPM_GPIO_PIN GPIO_Pin_10 // PA.10 -#define INTMODULE_PPM_GPIO_PinSource GPIO_PinSource10 -#define INTMODULE_TIMER TIM1 -#define INTMODULE_TIMER_CC_IRQn TIM1_CC_IRQn -#define INTMODULE_TIMER_CC_IRQHandler TIM1_CC_IRQHandler -#define INTMODULE_PPM_GPIO_AF GPIO_AF_TIM1 -#define INTMODULE_DMA_CHANNEL DMA_Channel_6 -#define INTMODULE_DMA_STREAM DMA2_Stream5 -#define INTMODULE_DMA_IRQn DMA2_Stream5_IRQn -#define INTMODULE_DMA_IRQHandler DMA2_Stream5_IRQHandler -#define INTMODULE_DMA_FLAG_TC DMA_IT_TCIF5 -#define INTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) - -// External Module -#define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) -#define EXTMODULE_RCC_APB2Periph RCC_APB2Periph_TIM8 -#define EXTMODULE_PWR_GPIO GPIOD -#define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_8 // PD.08 -#define EXTMODULE_PPM_GPIO GPIOA -#define EXTMODULE_PPM_GPIO_PIN GPIO_Pin_7 // PA.07 -#define EXTMODULE_PPM_GPIO_PinSource GPIO_PinSource7 -#define EXTMODULE_TIMER TIM8 -#define EXTMODULE_PPM_GPIO_AF GPIO_AF_TIM8 -#define EXTMODULE_TIMER_CC_IRQn TIM8_CC_IRQn -#define EXTMODULE_TIMER_CC_IRQHandler TIM8_CC_IRQHandler -#define EXTMODULE_DMA_CHANNEL DMA_Channel_7 -#define EXTMODULE_DMA_STREAM DMA2_Stream1 -#define EXTMODULE_DMA_IRQn DMA2_Stream1_IRQn -#define EXTMODULE_DMA_IRQHandler DMA2_Stream1_IRQHandler -#define EXTMODULE_DMA_FLAG_TC DMA_IT_TCIF1 -#define EXTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) - -// Trainer Port -#define TRAINER_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC) -#define TRAINER_RCC_APB1Periph RCC_APB1Periph_TIM3 -#define TRAINER_GPIO GPIOC -#define TRAINER_IN_GPIO_PIN GPIO_Pin_8 // PC.08 -#define TRAINER_IN_GPIO_PinSource GPIO_PinSource8 -#define TRAINER_OUT_GPIO_PIN GPIO_Pin_9 // PC.09 -#define TRAINER_OUT_GPIO_PinSource GPIO_PinSource9 -#define TRAINER_DETECT_GPIO GPIOA -#define TRAINER_DETECT_GPIO_PIN GPIO_Pin_8 // PA.08 -#define TRAINER_TIMER TIM3 -#define TRAINER_TIMER_IRQn TIM3_IRQn -#define TRAINER_GPIO_AF GPIO_AF_TIM3 -#define TRAINER_DMA DMA1 -#define TRAINER_DMA_CHANNEL DMA_Channel_5 -#define TRAINER_DMA_STREAM DMA1_Stream2 -#define TRAINER_DMA_IRQn DMA1_Stream2_IRQn -#define TRAINER_DMA_IRQHandler DMA1_Stream2_IRQHandler -#define TRAINER_DMA_FLAG_TC DMA_IT_TCIF2 -#define TRAINER_TIMER_IRQn TIM3_IRQn -#define TRAINER_TIMER_IRQHandler TIM3_IRQHandler -#define TRAINER_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) - -// Serial Port -#if defined(PCBX7) -#define SERIAL_RCC_AHB1Periph 0 -#define SERIAL_RCC_APB1Periph 0 -#else -#define SERIAL_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) -#define SERIAL_RCC_APB1Periph RCC_APB1Periph_USART3 -#define SERIAL_GPIO GPIOB -#define SERIAL_GPIO_PIN_TX GPIO_Pin_10 // PB.10 -#define SERIAL_GPIO_PIN_RX GPIO_Pin_11 // PB.11 -#define SERIAL_GPIO_PinSource_TX GPIO_PinSource10 -#define SERIAL_GPIO_PinSource_RX GPIO_PinSource11 -#define SERIAL_GPIO_AF GPIO_AF_USART3 -#define SERIAL_USART USART3 -#define SERIAL_USART_IRQHandler USART3_IRQHandler -#define SERIAL_USART_IRQn USART3_IRQn -#define SERIAL_DMA_Stream_RX DMA1_Stream1 -#define SERIAL_DMA_Channel_RX DMA_Channel_4 -#endif - -// Telemetry -#define TELEMETRY_RCC_AHB1Periph (RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) -#define TELEMETRY_RCC_APB1Periph RCC_APB1Periph_USART2 -#define TELEMETRY_DIR_GPIO GPIOD -#define TELEMETRY_DIR_GPIO_PIN GPIO_Pin_4 // PD.04 -#define TELEMETRY_GPIO GPIOD -#define TELEMETRY_TX_GPIO_PIN GPIO_Pin_5 // PD.05 -#define TELEMETRY_RX_GPIO_PIN GPIO_Pin_6 // PD.06 -#define TELEMETRY_GPIO_PinSource_TX GPIO_PinSource5 -#define TELEMETRY_GPIO_PinSource_RX GPIO_PinSource6 -#define TELEMETRY_GPIO_AF GPIO_AF_USART2 -#define TELEMETRY_USART USART2 -#define TELEMETRY_DMA_Stream_TX DMA1_Stream6 -#define TELEMETRY_DMA_Channel_TX DMA_Channel_4 -#define TELEMETRY_DMA_TX_Stream_IRQ DMA1_Stream6_IRQn -#define TELEMETRY_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler -#define TELEMETRY_DMA_TX_FLAG_TC DMA_IT_TCIF6 -#define TELEMETRY_USART_IRQHandler USART2_IRQHandler -#define TELEMETRY_USART_IRQn USART2_IRQn - -// PCBREV -#if defined(PCBX7) -#define PCBREV_RCC_AHB1Periph RCC_AHB1Periph_GPIOA -#define PCBREV_GPIO GPIOA -#define PCBREV_GPIO_PIN GPIO_Pin_14 // PA.14 -#else -#define PCBREV_RCC_AHB1Periph 0 -#endif - -// SPORT update connector -#if defined(PCBX7) -#define SPORT_UPDATE_RCC_AHB1Periph RCC_AHB1Periph_GPIOB -#define SPORT_UPDATE_PWR_GPIO GPIOB -#define SPORT_UPDATE_PWR_GPIO_PIN GPIO_Pin_2 // PB.02 -#else -#define SPORT_UPDATE_RCC_AHB1Periph 0 -#endif - -// Heartbeat -#define HEARTBEAT_RCC_AHB1Periph RCC_AHB1Periph_GPIOC -#define HEARTBEAT_RCC_APB2Periph RCC_APB2Periph_USART6 -#define HEARTBEAT_GPIO GPIOC -#define HEARTBEAT_GPIO_PIN GPIO_Pin_7 // PC.07 -#define HEARTBEAT_GPIO_PinSource GPIO_PinSource7 -#define HEARTBEAT_GPIO_AF_SBUS GPIO_AF_USART6 -#define HEARTBEAT_GPIO_AF_CAPTURE GPIO_AF_TIM3 -#define HEARTBEAT_USART USART6 -#define HEARTBEAT_USART_IRQHandler USART6_IRQHandler -#define HEARTBEAT_USART_IRQn USART6_IRQn -#define HEARTBEAT_DMA_Stream DMA2_Stream1 -#define HEARTBEAT_DMA_Channel DMA_Channel_5 - -// USB -#define USB_RCC_AHB1Periph_GPIO RCC_AHB1Periph_GPIOA -#define USB_GPIO GPIOA -#define USB_GPIO_PIN_VBUS GPIO_Pin_9 // PA.09 -#define USB_GPIO_PIN_DM GPIO_Pin_11 // PA.11 -#define USB_GPIO_PIN_DP GPIO_Pin_12 // PA.12 -#define USB_GPIO_PinSource_DM GPIO_PinSource11 -#define USB_GPIO_PinSource_DP GPIO_PinSource12 -#define USB_GPIO_AF GPIO_AF_OTG1_FS - -// BackLight -#if defined(PCBX9E) - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOE - #define BACKLIGHT_RCC_APB1Periph 0 - #define BACKLIGHT_RCC_APB2Periph RCC_APB2Periph_TIM9 - #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) - #define BACKLIGHT_TIMER TIM9 - #define BACKLIGHT_GPIO GPIOE - #define BACKLIGHT_GPIO_PIN_1 GPIO_Pin_6 // PE.06 - #define BACKLIGHT_GPIO_PIN_2 GPIO_Pin_5 // PE.05 - #define BACKLIGHT_GPIO_PinSource_1 GPIO_PinSource6 - #define BACKLIGHT_GPIO_PinSource_2 GPIO_PinSource5 - #define BACKLIGHT_GPIO_AF_1 GPIO_AF_TIM9 - #define BACKLIGHT_GPIO_AF_2 GPIO_AF_TIM9 -#elif defined (PCBX9DP) - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOD - #define BACKLIGHT_RCC_APB1Periph RCC_APB1Periph_TIM4 - #define BACKLIGHT_RCC_APB2Periph 0 - #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) - #define BACKLIGHT_TIMER TIM4 - #define BACKLIGHT_GPIO GPIOD - #define BACKLIGHT_GPIO_PIN_1 GPIO_Pin_15 // PD.15 - #define BACKLIGHT_GPIO_PIN_2 GPIO_Pin_13 // PD.13 - #define BACKLIGHT_GPIO_PinSource_1 GPIO_PinSource15 - #define BACKLIGHT_GPIO_PinSource_2 GPIO_PinSource13 - #define BACKLIGHT_GPIO_AF_1 GPIO_AF_TIM4 - #define BACKLIGHT_GPIO_AF_2 GPIO_AF_TIM4 -#elif defined(PCBX7) - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOD - #define BACKLIGHT_RCC_APB1Periph RCC_APB1Periph_TIM4 - #define BACKLIGHT_RCC_APB2Periph 0 - #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) - #define BACKLIGHT_TIMER TIM4 - #define BACKLIGHT_GPIO GPIOD - #define BACKLIGHT_GPIO_PIN GPIO_Pin_13 // PD.13 - #define BACKLIGHT_GPIO_PinSource GPIO_PinSource13 - #define BACKLIGHT_GPIO_AF GPIO_AF_TIM4 -#else - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define BACKLIGHT_RCC_APB1Periph 0 - #define BACKLIGHT_RCC_APB2Periph RCC_APB2Periph_TIM10 - #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) - #define BACKLIGHT_TIMER TIM10 - #define BACKLIGHT_GPIO GPIOB - #define BACKLIGHT_GPIO_PIN GPIO_Pin_8 // PB.08 - #define BACKLIGHT_GPIO_PinSource GPIO_PinSource8 - #define BACKLIGHT_GPIO_AF GPIO_AF_TIM10 -#endif - -// LCD driver -#if defined(PCBX9E) - #define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) - #define LCD_RCC_APB1Periph RCC_APB1Periph_SPI3 - #define LCD_SPI_GPIO GPIOC - #define LCD_MOSI_GPIO_PIN GPIO_Pin_12 // PC.12 - #define LCD_MOSI_GPIO_PinSource GPIO_PinSource12 - #define LCD_CLK_GPIO_PIN GPIO_Pin_10 // PC.10 - #define LCD_CLK_GPIO_PinSource GPIO_PinSource10 - #define LCD_A0_GPIO_PIN GPIO_Pin_11 // PC.11 - #define LCD_NCS_GPIO GPIOA - #define LCD_NCS_GPIO_PIN GPIO_Pin_15 // PA.15 - #define LCD_RST_GPIO GPIOD - #define LCD_RST_GPIO_PIN GPIO_Pin_15 // PD.15 - #define LCD_DMA DMA1 - #define LDC_DMA_Stream DMA1_Stream7 - #define LCD_DMA_Stream_IRQn DMA1_Stream7_IRQn - #define LCD_DMA_Stream_IRQHandler DMA1_Stream7_IRQHandler - #define LCD_DMA_FLAGS (DMA_HIFCR_CTCIF7 | DMA_HIFCR_CHTIF7 | DMA_HIFCR_CTEIF7 | DMA_HIFCR_CDMEIF7 | DMA_HIFCR_CFEIF7) - #define LCD_DMA_FLAG_INT DMA_HIFCR_CTCIF7 - #define LCD_SPI SPI3 - #define LCD_GPIO_AF GPIO_AF_SPI3 -#elif defined(PCBX9DP) || defined(PCBX7) - #define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) - #define LCD_RCC_APB1Periph RCC_APB1Periph_SPI3 - #define LCD_SPI_GPIO GPIOC - #define LCD_MOSI_GPIO_PIN GPIO_Pin_12 // PC.12 - #define LCD_MOSI_GPIO_PinSource GPIO_PinSource12 - #define LCD_CLK_GPIO_PIN GPIO_Pin_10 // PC.10 - #define LCD_CLK_GPIO_PinSource GPIO_PinSource10 - #define LCD_A0_GPIO_PIN GPIO_Pin_11 // PC.11 - #define LCD_NCS_GPIO GPIOA - #define LCD_NCS_GPIO_PIN GPIO_Pin_15 // PA.15 - #define LCD_RST_GPIO GPIOD - #define LCD_RST_GPIO_PIN GPIO_Pin_12 // PD.12 - #define LCD_DMA DMA1 - #define LDC_DMA_Stream DMA1_Stream7 - #define LCD_DMA_Stream_IRQn DMA1_Stream7_IRQn - #define LCD_DMA_Stream_IRQHandler DMA1_Stream7_IRQHandler - #define LCD_DMA_FLAGS (DMA_HIFCR_CTCIF7 | DMA_HIFCR_CHTIF7 | DMA_HIFCR_CTEIF7 | DMA_HIFCR_CDMEIF7 | DMA_HIFCR_CFEIF7) - #define LCD_DMA_FLAG_INT DMA_HIFCR_CTCIF7 - #define LCD_SPI SPI3 - #define LCD_GPIO_AF GPIO_AF_SPI3 -#else - #define LCD_RCC_AHB1Periph RCC_AHB1Periph_GPIOD - #define LCD_RCC_APB1Periph 0 - #define LCD_SPI_GPIO GPIOD - #define LCD_MOSI_GPIO_PIN GPIO_Pin_10 // PD.10 - #define LCD_CLK_GPIO_PIN GPIO_Pin_11 // PD.11 - #define LCD_A0_GPIO_PIN GPIO_Pin_13 // PD.13 - #define LCD_NCS_GPIO GPIOD - #define LCD_NCS_GPIO_PIN GPIO_Pin_14 // PD.14 - #define LCD_RST_GPIO GPIOD - #define LCD_RST_GPIO_PIN GPIO_Pin_12 // PD.12 -#endif - -// I2C Bus: EEPROM and CAT5137 digital pot for volume control -#define I2C_RCC_AHB1Periph RCC_AHB1Periph_GPIOB -#define I2C_RCC_APB1Periph RCC_APB1Periph_I2C1 -#define I2C I2C1 -#define I2C_GPIO GPIOB -#define I2C_SCL_GPIO_PIN GPIO_Pin_6 // PB.06 -#define I2C_SDA_GPIO_PIN GPIO_Pin_7 // PB.07 -#define I2C_GPIO_PIN_WP GPIO_Pin_9 // PB.09 -#define I2C_GPIO_AF GPIO_AF_I2C1 -#define I2C_SCL_GPIO_PinSource GPIO_PinSource6 -#define I2C_SDA_GPIO_PinSource GPIO_PinSource7 -#if defined(REV4a) - #define I2C_SPEED 100000 -#else - #define I2C_SPEED 400000 -#endif -#define I2C_ADDRESS_EEPROM 0xA2 -#define I2C_ADDRESS_VOLUME 0x5C -#define I2C_FLASH_PAGESIZE 64 - -// SD - SPI2 -#define SD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) -#define SD_RCC_APB1Periph RCC_APB1Periph_SPI2 -#define SD_GPIO_PRESENT GPIOD -#define SD_GPIO_PIN_PRESENT GPIO_Pin_9 // PD.09 -#define SD_GPIO GPIOB -#define SD_GPIO_PIN_CS GPIO_Pin_12 // PB.12 -#define SD_GPIO_PIN_SCK GPIO_Pin_13 // PB.13 -#define SD_GPIO_PIN_MISO GPIO_Pin_14 // PB.14 -#define SD_GPIO_PIN_MOSI GPIO_Pin_15 // PB.15 -#define SD_GPIO_AF GPIO_AF_SPI2 -#define SD_GPIO_PinSource_CS GPIO_PinSource12 -#define SD_GPIO_PinSource_SCK GPIO_PinSource13 -#define SD_GPIO_PinSource_MISO GPIO_PinSource14 -#define SD_GPIO_PinSource_MOSI GPIO_PinSource15 -#define SD_SPI SPI2 -#define SD_SPI_BaudRatePrescaler SPI_BaudRatePrescaler_4 // 10.5<20MHZ, make sure < 20MHZ - -#if !defined(BOOT) - #define SD_USE_DMA // Enable the DMA for SD - #define SD_DMA_Stream_SPI_RX DMA1_Stream3 - #define SD_DMA_Stream_SPI_TX DMA1_Stream4 - #define SD_DMA_FLAG_SPI_TC_RX DMA_FLAG_TCIF3 - #define SD_DMA_FLAG_SPI_TC_TX DMA_FLAG_TCIF4 - #define SD_DMA_Channel_SPI DMA_Channel_0 -#endif - -// Audio -#define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1) -#define AUDIO_RCC_APB1Periph (RCC_APB1Periph_TIM6 | RCC_APB1Periph_DAC) -#define AUDIO_OUTPUT_GPIO GPIOA -#define AUDIO_OUTPUT_GPIO_PIN GPIO_Pin_4 // PA.04 -#define AUDIO_DMA_Stream DMA1_Stream5 -#define AUDIO_DMA_Stream_IRQn DMA1_Stream5_IRQn -#define AUDIO_TIM_IRQn TIM6_DAC_IRQn -#define AUDIO_TIM_IRQHandler TIM6_DAC_IRQHandler -#define AUDIO_DMA_Stream_IRQHandler DMA1_Stream5_IRQHandler -#define AUDIO_TIMER TIM6 -#define AUDIO_DMA DMA1 - -// Haptic -#if defined(PCBX9E) || defined(PCBX9DP) || defined(PCBX7) - #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define HAPTIC_RCC_APB2Periph RCC_APB2Periph_TIM10 - #define HAPTIC_GPIO_PinSource GPIO_PinSource8 - #define HAPTIC_GPIO GPIOB - #define HAPTIC_GPIO_PIN GPIO_Pin_8 // PB.08 - #define HAPTIC_GPIO_AF GPIO_AF_TIM10 - #define HAPTIC_TIMER TIM10 -#else - #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOC - #define HAPTIC_RCC_APB2Periph 0 - #define HAPTIC_GPIO GPIOC - #define HAPTIC_GPIO_PIN GPIO_Pin_12 -#endif - -// Top LCD on X9E -#if defined(PCBX9E) - #define TOPLCD_RCC_AHB1Periph RCC_AHB1Periph_GPIOG - #define TOPLCD_GPIO GPIOG - #define TOPLCD_GPIO_PIN_DATA GPIO_Pin_5 - #define TOPLCD_GPIO_PIN_WR GPIO_Pin_4 - #define TOPLCD_GPIO_PIN_CS1 GPIO_Pin_3 - #define TOPLCD_GPIO_PIN_CS2 GPIO_Pin_15 - #define TOPLCD_GPIO_PIN_BL GPIO_Pin_2 -#endif - -// Bluetooth -#if defined(PCBX9E) - #define BT_USART USART6 - #define BT_GPIO_AF GPIO_AF_USART6 - #define BT_USART_IRQn USART6_IRQn - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOB) - #define BT_GPIO_TXRX GPIOG - #define BT_TX_GPIO_PIN GPIO_Pin_14 // PG.14 - #define BT_RX_GPIO_PIN GPIO_Pin_9 // PG.09 - #define BT_EN_GPIO GPIOD - #define BT_EN_GPIO_PIN GPIO_Pin_11 // PD.11 - #define BT_BRTS_GPIO GPIOE - #define BT_BRTS_GPIO_PIN GPIO_Pin_12 // PE.12 - #define BT_BCTS_GPIO GPIOG - #define BT_BCTS_GPIO_PIN GPIO_Pin_6 // PG.06 - #define BT_TX_GPIO_PinSource GPIO_PinSource14 - #define BT_RX_GPIO_PinSource GPIO_PinSource9 -#elif defined(PCBX7) - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_DMA1) - #define BT_RCC_APB1Periph RCC_APB1Periph_USART3 - #define BT_EN_GPIO GPIOE - #define BT_EN_GPIO_PIN GPIO_Pin_12 // PE.12 - #define BT_GPIO_TXRX GPIOB - #define BT_TX_GPIO_PIN GPIO_Pin_10 // PB.10 - #define BT_RX_GPIO_PIN GPIO_Pin_11 // PB.11 - #define BT_TX_GPIO_PinSource GPIO_PinSource10 - #define BT_RX_GPIO_PinSource GPIO_PinSource11 - #define BT_GPIO_AF GPIO_AF_USART3 - #define BT_USART USART3 - #define BT_USART_IRQHandler USART3_IRQHandler - #define BT_USART_IRQn USART3_IRQn - #define BT_DMA_Stream_RX DMA1_Stream1 - #define BT_DMA_Channel_RX DMA_Channel_4 -#endif - -// 5ms Interrupt -#define INTERRUPT_5MS_APB1Periph RCC_APB1Periph_TIM14 -#define INTERRUPT_5MS_TIMER TIM14 -#define INTERRUPT_5MS_IRQn TIM8_TRG_COM_TIM14_IRQn -#define INTERRUPT_5MS_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler - -// 2MHz Timer -#define TIMER_2MHz_APB1Periph RCC_APB1Periph_TIM7 -#define TIMER_2MHz_TIMER TIM7 - -#endif // _HAL_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _HAL_H_ +#define _HAL_H_ + +// Keys +#if defined(PCBX7) + #define KEYS_GPIO_REG_PAGE GPIOD->IDR + #define KEYS_GPIO_PIN_PAGE GPIO_Pin_3 // PD.03 + #define KEYS_GPIO_REG_MENU GPIOD->IDR + #define KEYS_GPIO_PIN_MENU GPIO_Pin_7 // PD.07 + #define KEYS_GPIO_REG_EXIT GPIOD->IDR + #define KEYS_GPIO_PIN_EXIT GPIO_Pin_2 // PD.02 +#else + #define KEYS_GPIO_REG_MENU GPIOD->IDR + #define KEYS_GPIO_PIN_MENU GPIO_Pin_7 // PD.07 + #define KEYS_GPIO_REG_EXIT GPIOD->IDR + #define KEYS_GPIO_PIN_EXIT GPIO_Pin_2 // PD.02 + #define KEYS_GPIO_REG_PAGE GPIOD->IDR + #define KEYS_GPIO_PIN_PAGE GPIO_Pin_3 // PD.03 +#endif + +#if defined(PCBX9E) + #define KEYS_GPIO_REG_ENTER GPIOF->IDR + #define KEYS_GPIO_PIN_ENTER GPIO_Pin_0 // PF.00 +#elif defined(PCBX7) + #define KEYS_GPIO_REG_ENTER GPIOE->IDR + #define KEYS_GPIO_PIN_ENTER GPIO_Pin_10 // PE.10 +#else + #define KEYS_GPIO_REG_PLUS GPIOE->IDR + #define KEYS_GPIO_PIN_PLUS GPIO_Pin_10 // PE.10 + #define KEYS_GPIO_REG_MINUS GPIOE->IDR + #define KEYS_GPIO_PIN_MINUS GPIO_Pin_11 // PE.11 + #define KEYS_GPIO_REG_ENTER GPIOE->IDR + #define KEYS_GPIO_PIN_ENTER GPIO_Pin_12 // PE.12 +#endif + +// Rotary Encoder +#if defined(PCBX9E) + #define ENC_GPIO GPIOD + #define ENC_GPIO_PIN_A GPIO_Pin_12 // PD.12 + #define ENC_GPIO_PIN_B GPIO_Pin_13 // PD.13 + #define ROTARY_ENCODER_POSITION() (ENC_GPIO->IDR >> 12) & 0x03 +#elif defined(PCBX7) + #define ENC_GPIO GPIOE + #define ENC_GPIO_PIN_A GPIO_Pin_9 // PE.09 + #define ENC_GPIO_PIN_B GPIO_Pin_11 // PE.11 + #define ROTARY_ENCODER_POSITION() (((ENC_GPIO->IDR >> 10) & 0x02) + ((ENC_GPIO->IDR >> 9) & 0x01)) +#endif + +// This is for SIMU: reuse rotary encoder pins to map UP and DOWN keyboard keys +#if defined(SIMU) && (defined(PCBX9E) || defined(PCBX7)) + #define KEYS_GPIO_REG_PLUS ENC_GPIO->IDR + #define KEYS_GPIO_PIN_PLUS ENC_GPIO_PIN_A + #define KEYS_GPIO_REG_MINUS ENC_GPIO->IDR + #define KEYS_GPIO_PIN_MINUS ENC_GPIO_PIN_B +#endif + +// Trims +#if defined(PCBX9E) + #define TRIMS_GPIO_REG_LHL GPIOG->IDR + #define TRIMS_GPIO_PIN_LHL GPIO_Pin_1 // PG.01 + #define TRIMS_GPIO_REG_LHR GPIOG->IDR + #define TRIMS_GPIO_PIN_LHR GPIO_Pin_0 // PG.00 + #define TRIMS_GPIO_REG_LVD GPIOE->IDR + #define TRIMS_GPIO_PIN_LVD GPIO_Pin_4 // PE.04 + #define TRIMS_GPIO_REG_LVU GPIOE->IDR + #define TRIMS_GPIO_PIN_LVU GPIO_Pin_3 // PE.03 + #define TRIMS_GPIO_REG_RVD GPIOC->IDR + #define TRIMS_GPIO_PIN_RVD GPIO_Pin_3 // PC.03 + #define TRIMS_GPIO_REG_RHL GPIOC->IDR + #define TRIMS_GPIO_PIN_RHL GPIO_Pin_1 // PC.01 + #define TRIMS_GPIO_REG_RVU GPIOC->IDR + #define TRIMS_GPIO_PIN_RVU GPIO_Pin_2 // PC.02 + #define TRIMS_GPIO_REG_RHR GPIOC->IDR + #define TRIMS_GPIO_PIN_RHR GPIO_Pin_13 // PC.13 +#elif defined(PCBX7) + #define TRIMS_GPIO_REG_LHL GPIOD->IDR + #define TRIMS_GPIO_PIN_LHL GPIO_Pin_15 // PD.15 + #define TRIMS_GPIO_REG_LHR GPIOC->IDR + #define TRIMS_GPIO_PIN_LHR GPIO_Pin_1 // PC.01 + #define TRIMS_GPIO_REG_LVD GPIOE->IDR + #define TRIMS_GPIO_PIN_LVD GPIO_Pin_6 // PE.06 + #define TRIMS_GPIO_REG_LVU GPIOE->IDR + #define TRIMS_GPIO_PIN_LVU GPIO_Pin_5 // PE.05 + #define TRIMS_GPIO_REG_RVD GPIOC->IDR + #define TRIMS_GPIO_PIN_RVD GPIO_Pin_3 // PC.03 + #define TRIMS_GPIO_REG_RHL GPIOE->IDR + #define TRIMS_GPIO_PIN_RHL GPIO_Pin_3 // PE.03 + #define TRIMS_GPIO_REG_RVU GPIOC->IDR + #define TRIMS_GPIO_PIN_RVU GPIO_Pin_2 // PC.02 + #define TRIMS_GPIO_REG_RHR GPIOE->IDR + #define TRIMS_GPIO_PIN_RHR GPIO_Pin_4 // PE.04 +#else + #define TRIMS_GPIO_REG_LHL GPIOE->IDR + #define TRIMS_GPIO_PIN_LHL GPIO_Pin_4 // PE.04 + #define TRIMS_GPIO_REG_LHR GPIOE->IDR + #define TRIMS_GPIO_PIN_LHR GPIO_Pin_3 // PE.03 + #define TRIMS_GPIO_REG_LVD GPIOE->IDR + #define TRIMS_GPIO_PIN_LVD GPIO_Pin_6 // PE.06 + #define TRIMS_GPIO_REG_LVU GPIOE->IDR + #define TRIMS_GPIO_PIN_LVU GPIO_Pin_5 // PE.05 + #define TRIMS_GPIO_REG_RVD GPIOC->IDR + #define TRIMS_GPIO_PIN_RVD GPIO_Pin_3 // PC.03 + #define TRIMS_GPIO_REG_RHL GPIOC->IDR + #define TRIMS_GPIO_PIN_RHL GPIO_Pin_1 // PC.01 + #define TRIMS_GPIO_REG_RVU GPIOC->IDR + #define TRIMS_GPIO_PIN_RVU GPIO_Pin_2 // PC.02 + #define TRIMS_GPIO_REG_RHR GPIOC->IDR + #define TRIMS_GPIO_PIN_RHR GPIO_Pin_13 // PC.13 +#endif + +// Switches +#if defined(PCBX9E) + #define SWITCHES_GPIO_REG_A_H GPIOD->IDR + #define SWITCHES_GPIO_PIN_A_H GPIO_Pin_10 // PD.10 + #define SWITCHES_GPIO_REG_A_L GPIOD->IDR + #define SWITCHES_GPIO_PIN_A_L GPIO_Pin_14 // PD.14 +#elif defined(PCBX7) + #define SWITCHES_GPIO_REG_A_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_A_L GPIO_Pin_7 // PE.07 + #define SWITCHES_GPIO_REG_A_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_A_H GPIO_Pin_13 // PE.13 +#else + #define SWITCHES_GPIO_REG_A_H GPIOB->IDR + #define SWITCHES_GPIO_PIN_A_H GPIO_Pin_5 // PB.05 + #define SWITCHES_GPIO_REG_A_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_A_L GPIO_Pin_0 // PE.00 +#endif + +#if defined(PCBX9E) + #define SWITCHES_GPIO_REG_B_H GPIOG->IDR + #define SWITCHES_GPIO_PIN_B_H GPIO_Pin_11 // PG.11 + #define SWITCHES_GPIO_REG_B_L GPIOG->IDR + #define SWITCHES_GPIO_PIN_B_L GPIO_Pin_10 // PG.10 +#elif defined(PCBX7) + #define SWITCHES_GPIO_REG_B_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_B_L GPIO_Pin_15 // PE.15 + #define SWITCHES_GPIO_REG_B_H GPIOA->IDR + #define SWITCHES_GPIO_PIN_B_H GPIO_Pin_5 // PA.05 +#else + #define SWITCHES_GPIO_REG_B_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_B_H GPIO_Pin_1 // PE.01 + #define SWITCHES_GPIO_REG_B_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_B_L GPIO_Pin_2 // PE.02 +#endif + +#if defined(PCBX9E) + #define SWITCHES_GPIO_REG_C_H GPIOF->IDR + #define SWITCHES_GPIO_PIN_C_H GPIO_Pin_13 // PF.13 + #define SWITCHES_GPIO_REG_C_L GPIOF->IDR + #define SWITCHES_GPIO_PIN_C_L GPIO_Pin_14 // PF.14 +#elif defined(PCBX7) + #define SWITCHES_GPIO_REG_C_L GPIOD->IDR + #define SWITCHES_GPIO_PIN_C_L GPIO_Pin_11 // PD.11 + #define SWITCHES_GPIO_REG_C_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_C_H GPIO_Pin_0 // PE.00 +#else + #define SWITCHES_GPIO_REG_C_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_C_H GPIO_Pin_15 // PE.15 + #define SWITCHES_GPIO_REG_C_L GPIOA->IDR + #define SWITCHES_GPIO_PIN_C_L GPIO_Pin_5 // PA.05 +#endif + +#if defined(PCBX9E) + #define SWITCHES_GPIO_REG_D_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_D_H GPIO_Pin_1 // PE.01 + #define SWITCHES_GPIO_REG_D_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_D_L GPIO_Pin_2 // PE.02 +#elif defined(PCBX9DP) + #define SWITCHES_GPIO_REG_D_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_D_H GPIO_Pin_7 // PE.07 + #define SWITCHES_GPIO_REG_D_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_D_L GPIO_Pin_13 // PE.13 +#elif defined(PCBX7) + #define SWITCHES_GPIO_REG_D_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_D_L GPIO_Pin_1 // PE.01 + #define SWITCHES_GPIO_REG_D_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_D_H GPIO_Pin_2 // PE.02 +#else + #define SWITCHES_GPIO_REG_D_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_D_H GPIO_Pin_7 // PE.07 + #define SWITCHES_GPIO_REG_D_L GPIOB->IDR + #define SWITCHES_GPIO_PIN_D_L GPIO_Pin_1 // PB.01 +#endif + +#if defined(PCBX9E) + #define SWITCHES_GPIO_REG_E_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_E_H GPIO_Pin_7 // PE.07 + #define SWITCHES_GPIO_REG_E_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_E_L GPIO_Pin_13 // PE.13 +#elif !defined(PCBX7) + #define SWITCHES_GPIO_REG_E_H GPIOB->IDR + #define SWITCHES_GPIO_PIN_E_H GPIO_Pin_3 // PB.03 + #define SWITCHES_GPIO_REG_E_L GPIOB->IDR + #define SWITCHES_GPIO_PIN_E_L GPIO_Pin_4 // PB.04 +#endif + +#if defined(PCBX9E) + #define SWITCHES_GPIO_REG_F GPIOE->IDR + #define SWITCHES_GPIO_PIN_F GPIO_Pin_11 // PE.11 +#elif defined(PCBX7) + #define SWITCHES_GPIO_REG_F GPIOE->IDR + #define SWITCHES_GPIO_PIN_F GPIO_Pin_14 // PE.14 +#else + #define SWITCHES_GPIO_REG_F GPIOE->IDR + #define SWITCHES_GPIO_PIN_F GPIO_Pin_14 // PE.14 +#endif + +#if defined(PCBX9E) + #define SWITCHES_GPIO_REG_G_H GPIOF->IDR + #define SWITCHES_GPIO_PIN_G_H GPIO_Pin_3 // PF.03 + #define SWITCHES_GPIO_REG_G_L GPIOF->IDR + #define SWITCHES_GPIO_PIN_G_L GPIO_Pin_4 // PF.04 +#elif !defined(PCBX7) + #define SWITCHES_GPIO_REG_G_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_G_H GPIO_Pin_9 // PE.09 + #define SWITCHES_GPIO_REG_G_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_G_L GPIO_Pin_8 // PE.08 +#endif + +#if defined(PCBX9E) + #define SWITCHES_GPIO_REG_H GPIOF->IDR + #define SWITCHES_GPIO_PIN_H GPIO_Pin_1 // PF.01 +#elif defined(PCBX9DP) + #define SWITCHES_GPIO_REG_H GPIOD->IDR + #define SWITCHES_GPIO_PIN_H GPIO_Pin_14 // PD.14 +#elif defined(PCBX7) + #define SWITCHES_GPIO_REG_H GPIOD->IDR + #define SWITCHES_GPIO_PIN_H GPIO_Pin_14 // PD.14 +#else + #define SWITCHES_GPIO_REG_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_H GPIO_Pin_13 // PE.13 +#endif + +#if defined(PCBX9E) + #define SWITCHES_GPIO_REG_I_H GPIOF->IDR + #define SWITCHES_GPIO_PIN_I_H GPIO_Pin_15 // PF.15 + #define SWITCHES_GPIO_REG_I_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_I_L GPIO_Pin_14 // PE.14 + #define SWITCHES_GPIO_REG_J_H GPIOG->IDR + #define SWITCHES_GPIO_PIN_J_H GPIO_Pin_7 // PG.07 + #define SWITCHES_GPIO_REG_J_L GPIOG->IDR + #define SWITCHES_GPIO_PIN_J_L GPIO_Pin_8 // PG.08 + #define SWITCHES_GPIO_REG_K_H GPIOG->IDR + #define SWITCHES_GPIO_PIN_K_H GPIO_Pin_13 // PG.13 + #define SWITCHES_GPIO_REG_K_L GPIOG->IDR + #define SWITCHES_GPIO_PIN_K_L GPIO_Pin_12 // PG.12 + #define SWITCHES_GPIO_REG_L_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_L_H GPIO_Pin_9 // PE.09 + #define SWITCHES_GPIO_REG_L_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_L_L GPIO_Pin_8 // PE.08 + #define SWITCHES_GPIO_REG_M_H GPIOE->IDR + #define SWITCHES_GPIO_PIN_M_H GPIO_Pin_15 // PE.15 + #define SWITCHES_GPIO_REG_M_L GPIOA->IDR + #define SWITCHES_GPIO_PIN_M_L GPIO_Pin_5 // PA.05 + #define SWITCHES_GPIO_REG_N_H GPIOB->IDR + #define SWITCHES_GPIO_PIN_N_H GPIO_Pin_3 // PB.03 + #define SWITCHES_GPIO_REG_N_L GPIOB->IDR + #define SWITCHES_GPIO_PIN_N_L GPIO_Pin_4 // PB.04 + #define SWITCHES_GPIO_REG_O_H GPIOF->IDR + #define SWITCHES_GPIO_PIN_O_H GPIO_Pin_7 // PF.07 + #define SWITCHES_GPIO_REG_O_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_O_L GPIO_Pin_10 // PE.10 + #define SWITCHES_GPIO_REG_P_H GPIOF->IDR + #define SWITCHES_GPIO_PIN_P_H GPIO_Pin_11 // PF.11 + #define SWITCHES_GPIO_REG_P_L GPIOF->IDR + #define SWITCHES_GPIO_PIN_P_L GPIO_Pin_12 // PF.12 + #define SWITCHES_GPIO_REG_Q_H GPIOF->IDR + #define SWITCHES_GPIO_PIN_Q_H GPIO_Pin_5 // PF.05 + #define SWITCHES_GPIO_REG_Q_L GPIOF->IDR + #define SWITCHES_GPIO_PIN_Q_L GPIO_Pin_6 // PF.06 + #define SWITCHES_GPIO_REG_R_H GPIOB->IDR + #define SWITCHES_GPIO_PIN_R_H GPIO_Pin_5 // PB.05 + #define SWITCHES_GPIO_REG_R_L GPIOE->IDR + #define SWITCHES_GPIO_PIN_R_L GPIO_Pin_0 // PE.00 +#endif + +#if defined(PCBX9E) + #define KEYS_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA|RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOC|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG) + #define KEYS_GPIOA_PINS (SWITCHES_GPIO_PIN_M_L) + #define KEYS_GPIOB_PINS (SWITCHES_GPIO_PIN_N_H | SWITCHES_GPIO_PIN_N_L | SWITCHES_GPIO_PIN_R_H) + #define KEYS_GPIOC_PINS (TRIMS_GPIO_PIN_RVD | TRIMS_GPIO_PIN_RVU | TRIMS_GPIO_PIN_RHL | TRIMS_GPIO_PIN_RHR) + #define KEYS_GPIOD_PINS (KEYS_GPIO_PIN_MENU | KEYS_GPIO_PIN_EXIT | KEYS_GPIO_PIN_PAGE | SWITCHES_GPIO_PIN_A_H | SWITCHES_GPIO_PIN_A_L | ENC_GPIO_PIN_A | ENC_GPIO_PIN_B) + #define KEYS_GPIOE_PINS (TRIMS_GPIO_PIN_LVU | TRIMS_GPIO_PIN_LVD | SWITCHES_GPIO_PIN_D_H | SWITCHES_GPIO_PIN_D_L| SWITCHES_GPIO_PIN_E_H | SWITCHES_GPIO_PIN_E_L | SWITCHES_GPIO_PIN_F | SWITCHES_GPIO_PIN_I_L | SWITCHES_GPIO_PIN_L_H | SWITCHES_GPIO_PIN_L_L | SWITCHES_GPIO_PIN_M_H | SWITCHES_GPIO_PIN_O_L | SWITCHES_GPIO_PIN_R_L) + #define KEYS_GPIOF_PINS (KEYS_GPIO_PIN_ENTER | SWITCHES_GPIO_PIN_C_H | SWITCHES_GPIO_PIN_C_L | SWITCHES_GPIO_PIN_G_H | SWITCHES_GPIO_PIN_G_L | SWITCHES_GPIO_PIN_H | SWITCHES_GPIO_PIN_I_H | SWITCHES_GPIO_PIN_O_H | SWITCHES_GPIO_PIN_P_H | SWITCHES_GPIO_PIN_P_L | SWITCHES_GPIO_PIN_Q_H | SWITCHES_GPIO_PIN_Q_L) + #define KEYS_GPIOG_PINS (TRIMS_GPIO_PIN_LHL | TRIMS_GPIO_PIN_LHR| SWITCHES_GPIO_PIN_B_H | SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_J_H | SWITCHES_GPIO_PIN_J_L | SWITCHES_GPIO_PIN_K_H | SWITCHES_GPIO_PIN_K_L) +#elif defined(PCBX9DP) + #define KEYS_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA|RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOC|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE) + #define KEYS_GPIOA_PINS (SWITCHES_GPIO_PIN_C_L) + #define KEYS_GPIOB_PINS (SWITCHES_GPIO_PIN_E_L | SWITCHES_GPIO_PIN_E_H | SWITCHES_GPIO_PIN_A_H) + #define KEYS_GPIOC_PINS (TRIMS_GPIO_PIN_RVD | TRIMS_GPIO_PIN_RVU | TRIMS_GPIO_PIN_RHL | TRIMS_GPIO_PIN_RHR) + #define KEYS_GPIOD_PINS (KEYS_GPIO_PIN_MENU | KEYS_GPIO_PIN_EXIT | KEYS_GPIO_PIN_PAGE | SWITCHES_GPIO_PIN_H) + #define KEYS_GPIOE_PINS (KEYS_GPIO_PIN_PLUS | KEYS_GPIO_PIN_ENTER | KEYS_GPIO_PIN_MINUS | TRIMS_GPIO_PIN_LHR | TRIMS_GPIO_PIN_LHL | TRIMS_GPIO_PIN_LVD | TRIMS_GPIO_PIN_LVU | SWITCHES_GPIO_PIN_F | SWITCHES_GPIO_PIN_A_L | SWITCHES_GPIO_PIN_B_H | SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_C_H | SWITCHES_GPIO_PIN_D_H | SWITCHES_GPIO_PIN_D_L | SWITCHES_GPIO_PIN_G_H | SWITCHES_GPIO_PIN_G_L) +#elif defined(PCBX7) + #define KEYS_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOC|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE) + #define KEYS_GPIOA_PINS SWITCHES_GPIO_PIN_B_H + #define KEYS_GPIOC_PINS (TRIMS_GPIO_PIN_LHR | TRIMS_GPIO_PIN_RVD | TRIMS_GPIO_PIN_RVU) + #define KEYS_GPIOD_PINS (TRIMS_GPIO_PIN_LHL | KEYS_GPIO_PIN_MENU | KEYS_GPIO_PIN_EXIT | KEYS_GPIO_PIN_PAGE | SWITCHES_GPIO_PIN_C_L | SWITCHES_GPIO_PIN_H) + #define KEYS_GPIOE_PINS (ENC_GPIO_PIN_A | ENC_GPIO_PIN_B | KEYS_GPIO_PIN_ENTER | TRIMS_GPIO_PIN_RHR | TRIMS_GPIO_PIN_RHL | TRIMS_GPIO_PIN_LVD | TRIMS_GPIO_PIN_LVU | SWITCHES_GPIO_PIN_C_H | SWITCHES_GPIO_PIN_D_L | SWITCHES_GPIO_PIN_D_H | SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_A_L | SWITCHES_GPIO_PIN_A_H | SWITCHES_GPIO_PIN_F) +#else + #define KEYS_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA|RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOC|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE) + #define KEYS_GPIOA_PINS (SWITCHES_GPIO_PIN_C_L) + #define KEYS_GPIOB_PINS (SWITCHES_GPIO_PIN_E_L | SWITCHES_GPIO_PIN_E_H | SWITCHES_GPIO_PIN_A_H | SWITCHES_GPIO_PIN_D_L) + #define KEYS_GPIOC_PINS (TRIMS_GPIO_PIN_RVD | TRIMS_GPIO_PIN_RVU | TRIMS_GPIO_PIN_RHL | TRIMS_GPIO_PIN_RHR) + #define KEYS_GPIOD_PINS (KEYS_GPIO_PIN_MENU | KEYS_GPIO_PIN_EXIT | KEYS_GPIO_PIN_PAGE) + #define KEYS_GPIOE_PINS (KEYS_GPIO_PIN_PLUS | KEYS_GPIO_PIN_ENTER | KEYS_GPIO_PIN_MINUS | TRIMS_GPIO_PIN_LHR | TRIMS_GPIO_PIN_LHL | TRIMS_GPIO_PIN_LVD | TRIMS_GPIO_PIN_LVU | SWITCHES_GPIO_PIN_F | SWITCHES_GPIO_PIN_A_L | SWITCHES_GPIO_PIN_B_H | SWITCHES_GPIO_PIN_B_L | SWITCHES_GPIO_PIN_C_H | SWITCHES_GPIO_PIN_D_H | SWITCHES_GPIO_PIN_G_H | SWITCHES_GPIO_PIN_G_L | SWITCHES_GPIO_PIN_H) +#endif + +// ADC +#if defined(PCBX9E) + #define ADC_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_DMA2) + #define ADC_RCC_APB2Periph (RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC3) +#else + #define ADC_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_DMA2) + #define ADC_RCC_APB2Periph RCC_APB2Periph_ADC1 +#endif +#define ADC_GPIO_PIN_STICK_RV GPIO_Pin_0 // PA.00 +#define ADC_GPIO_PIN_STICK_RH GPIO_Pin_1 // PA.01 +#if defined(PCBX7) + #define ADC_GPIO_PIN_STICK_LV GPIO_Pin_2 // PA.02 + #define ADC_GPIO_PIN_STICK_LH GPIO_Pin_3 // PA.03 + #define ADC_CHANNEL_STICK_LV ADC_Channel_2 // ADC1_IN2 + #define ADC_CHANNEL_STICK_LH ADC_Channel_3 // ADC1_IN3 +#else + #define ADC_GPIO_PIN_STICK_LH GPIO_Pin_2 // PA.02 + #define ADC_GPIO_PIN_STICK_LV GPIO_Pin_3 // PA.03 + #define ADC_CHANNEL_STICK_LH ADC_Channel_2 // ADC1_IN2 + #define ADC_CHANNEL_STICK_LV ADC_Channel_3 // ADC1_IN3 +#endif +#define ADC_CHANNEL_STICK_RV ADC_Channel_0 // ADC1_IN0 +#define ADC_CHANNEL_STICK_RH ADC_Channel_1 // ADC1_IN1 +#define ADC_MAIN ADC1 +#define ADC_DMA DMA2 +#define ADC_DMA_SxCR_CHSEL 0 +#define ADC_DMA_Stream DMA2_Stream4 +#define ADC_SET_DMA_FLAGS() ADC_DMA->HIFCR = (DMA_HIFCR_CTCIF4 | DMA_HIFCR_CHTIF4 | DMA_HIFCR_CTEIF4 | DMA_HIFCR_CDMEIF4 | DMA_HIFCR_CFEIF4) +#define ADC_TRANSFER_COMPLETE() (ADC_DMA->HISR & DMA_HISR_TCIF4) +#define ADC_SAMPTIME 2 // sample time = 28 cycles + +#if defined(PCBX9E) + #define ADC_GPIO_PIN_POT1 GPIO_Pin_8 // PF.08 + #define ADC_GPIO_PIN_POT2 GPIO_Pin_0 // PB.00 + #define ADC_GPIO_PIN_POT3 GPIO_Pin_5 // PC.05 + #define ADC_GPIO_PIN_POT4 GPIO_Pin_4 // PC.04 + #define ADC_GPIO_PIN_SLIDER1 GPIO_Pin_10 // PF.10 + #define ADC_GPIO_PIN_SLIDER2 GPIO_Pin_9 // PF.09 + #define ADC_GPIO_PIN_SLIDER3 GPIO_Pin_6 // PA.06 + #define ADC_GPIO_PIN_SLIDER4 GPIO_Pin_1 // PB.01 + #define ADC_GPIO_PIN_BATT GPIO_Pin_0 // PC.00 + #define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_STICK_RH | ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_SLIDER3) + #define ADC_GPIOB_PINS (ADC_GPIO_PIN_POT2 | ADC_GPIO_PIN_SLIDER4) + #define ADC_GPIOC_PINS (ADC_GPIO_PIN_POT3 | ADC_GPIO_PIN_POT4 | ADC_GPIO_PIN_SLIDER1 | ADC_GPIO_PIN_SLIDER2 | ADC_GPIO_PIN_BATT) + #define ADC_GPIOF_PINS (ADC_GPIO_PIN_POT1 | ADC_GPIO_PIN_SLIDER1 | ADC_GPIO_PIN_SLIDER2) + #define ADC_CHANNEL_POT1 ADC_Channel_6 // ADC3_IN6 + #define ADC_CHANNEL_POT2 ADC_Channel_8 // ADC1_IN8 + #define ADC_CHANNEL_POT3 ADC_Channel_15 // ADC1_IN15 + #define ADC_CHANNEL_POT4 ADC_Channel_14 // ADC1_IN14 + #define ADC_CHANNEL_SLIDER1 ADC_Channel_8 // ADC3_IN8 + #define ADC_CHANNEL_SLIDER2 ADC_Channel_7 // ADC3_IN7 + #define ADC_CHANNEL_SLIDER3 ADC_Channel_6 // ADC1_IN6 + #define ADC_CHANNEL_SLIDER4 ADC_Channel_9 // ADC1_IN9 + #define ADC_CHANNEL_BATT ADC_Channel_10 // ADC1_IN10 + #define ADC_EXT ADC3 + #define ADC_EXT_DMA DMA2 + #define ADC_EXT_DMA_Stream DMA2_Stream0 + #define ADC_EXT_SET_DMA_FLAGS() ADC_DMA->LIFCR = (DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 | DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0) + #define ADC_EXT_TRANSFER_COMPLETE() (ADC_DMA->LISR & DMA_LISR_TCIF0) + #define ADC_EXT_SAMPTIME 3 // sample time = 56 cycles +#elif defined(PCBX9DP) + #define ADC_GPIO_PIN_POT1 GPIO_Pin_6 // PA.06 + #define ADC_GPIO_PIN_POT2 GPIO_Pin_0 // PB.00 + #define ADC_GPIO_PIN_POT3 GPIO_Pin_1 // PB.01 + #define ADC_GPIO_PIN_SLIDER1 GPIO_Pin_4 // PC.04 + #define ADC_GPIO_PIN_SLIDER2 GPIO_Pin_5 // PC.05 + #define ADC_GPIO_PIN_BATT GPIO_Pin_0 // PC.00 + #define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_STICK_RH | ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT1) + #define ADC_GPIOB_PINS (ADC_GPIO_PIN_POT2 | ADC_GPIO_PIN_POT3) + #define ADC_GPIOC_PINS (ADC_GPIO_PIN_SLIDER1 | ADC_GPIO_PIN_SLIDER2 | ADC_GPIO_PIN_BATT) + #define ADC_CHANNEL_POT1 ADC_Channel_6 + #define ADC_CHANNEL_POT2 ADC_Channel_8 + #define ADC_CHANNEL_POT3 ADC_Channel_9 + #define ADC_CHANNEL_SLIDER1 ADC_Channel_14 + #define ADC_CHANNEL_SLIDER2 ADC_Channel_15 + #define ADC_CHANNEL_BATT ADC_Channel_10 +#elif defined(PCBX7) + #define ADC_GPIO_PIN_POT1 GPIO_Pin_6 // PA.06 + #define ADC_GPIO_PIN_POT2 GPIO_Pin_0 // PB.00 + #define ADC_GPIO_PIN_BATT GPIO_Pin_0 // PC.00 + #define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_STICK_RH | ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT1) + #define ADC_GPIOB_PINS ADC_GPIO_PIN_POT2 + #define ADC_GPIOC_PINS ADC_GPIO_PIN_BATT + #define ADC_CHANNEL_POT1 ADC_Channel_6 + #define ADC_CHANNEL_POT2 ADC_Channel_8 + #define ADC_CHANNEL_BATT ADC_Channel_10 +#else + #define ADC_GPIO_PIN_POT1 GPIO_Pin_6 // PA.06 + #define ADC_GPIO_PIN_POT2 GPIO_Pin_0 // PB.00 + #define ADC_GPIO_PIN_SLIDER1 GPIO_Pin_4 // PC.04 + #define ADC_GPIO_PIN_SLIDER2 GPIO_Pin_5 // PC.05 + #define ADC_GPIO_PIN_BATT GPIO_Pin_0 // PC.00 + #define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_STICK_RH | ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT1) + #define ADC_GPIOB_PINS (ADC_GPIO_PIN_POT2) + #define ADC_GPIOC_PINS (ADC_GPIO_PIN_SLIDER1 | ADC_GPIO_PIN_SLIDER2 | ADC_GPIO_PIN_BATT) + #define ADC_CHANNEL_POT1 ADC_Channel_6 + #define ADC_CHANNEL_POT2 ADC_Channel_8 + #define ADC_CHANNEL_POT3 ADC_Channel_9 + #define ADC_CHANNEL_SLIDER1 ADC_Channel_14 + #define ADC_CHANNEL_SLIDER2 ADC_Channel_15 + #define ADC_CHANNEL_BATT ADC_Channel_10 +#endif + +// PWR and LED driver +#define PWR_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD) +#if defined(PCBX9E) || defined(PCBX7) +#define PWR_PRESS_BUTTON +#endif +#define PWR_GPIO GPIOD +#define PWR_SWITCH_GPIO_PIN GPIO_Pin_1 // PD.01 +#define PWR_ON_GPIO_PIN GPIO_Pin_0 // PD.00 +#if defined(PCBX7) +#define LED_GREEN_GPIO GPIOC +#define LED_GREEN_GPIO_PIN GPIO_Pin_4 // PC.04 +#define LED_RED_GPIO GPIOC +#define LED_RED_GPIO_PIN GPIO_Pin_5 // PC.05 +#define LED_BLUE_GPIO GPIOB +#define LED_BLUE_GPIO_PIN GPIO_Pin_1 // PB.01 +#endif + +// Internal Module +#define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) +#define INTMODULE_RCC_APB2Periph RCC_APB2Periph_TIM1 +#if defined(PCBX9E) || defined(PCBX9DP) || defined(PCBX7) + #define INTMODULE_PWR_GPIO GPIOC + #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_6 // PC.06 +#else + #define INTMODULE_PWR_GPIO GPIOD + #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_15 // PD.15 +#endif +#define INTMODULE_PPM_GPIO GPIOA +#define INTMODULE_PPM_GPIO_PIN GPIO_Pin_10 // PA.10 +#define INTMODULE_PPM_GPIO_PinSource GPIO_PinSource10 +#define INTMODULE_TIMER TIM1 +#define INTMODULE_TIMER_CC_IRQn TIM1_CC_IRQn +#define INTMODULE_TIMER_CC_IRQHandler TIM1_CC_IRQHandler +#define INTMODULE_PPM_GPIO_AF GPIO_AF_TIM1 +#define INTMODULE_DMA_CHANNEL DMA_Channel_6 +#define INTMODULE_DMA_STREAM DMA2_Stream5 +#define INTMODULE_DMA_IRQn DMA2_Stream5_IRQn +#define INTMODULE_DMA_IRQHandler DMA2_Stream5_IRQHandler +#define INTMODULE_DMA_FLAG_TC DMA_IT_TCIF5 +#define INTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) + +// External Module +#define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) +#define EXTMODULE_RCC_APB2Periph RCC_APB2Periph_TIM8 +#define EXTMODULE_PWR_GPIO GPIOD +#define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_8 // PD.08 +#define EXTMODULE_PPM_GPIO GPIOA +#define EXTMODULE_PPM_GPIO_PIN GPIO_Pin_7 // PA.07 +#define EXTMODULE_PPM_GPIO_PinSource GPIO_PinSource7 +#define EXTMODULE_TIMER TIM8 +#define EXTMODULE_PPM_GPIO_AF GPIO_AF_TIM8 +#define EXTMODULE_TIMER_CC_IRQn TIM8_CC_IRQn +#define EXTMODULE_TIMER_CC_IRQHandler TIM8_CC_IRQHandler +#define EXTMODULE_DMA_CHANNEL DMA_Channel_7 +#define EXTMODULE_DMA_STREAM DMA2_Stream1 +#define EXTMODULE_DMA_IRQn DMA2_Stream1_IRQn +#define EXTMODULE_DMA_IRQHandler DMA2_Stream1_IRQHandler +#define EXTMODULE_DMA_FLAG_TC DMA_IT_TCIF1 +#define EXTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) + +// Trainer Port +#define TRAINER_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC) +#define TRAINER_RCC_APB1Periph RCC_APB1Periph_TIM3 +#define TRAINER_GPIO GPIOC +#define TRAINER_IN_GPIO_PIN GPIO_Pin_8 // PC.08 +#define TRAINER_IN_GPIO_PinSource GPIO_PinSource8 +#define TRAINER_OUT_GPIO_PIN GPIO_Pin_9 // PC.09 +#define TRAINER_OUT_GPIO_PinSource GPIO_PinSource9 +#define TRAINER_DETECT_GPIO GPIOA +#define TRAINER_DETECT_GPIO_PIN GPIO_Pin_8 // PA.08 +#define TRAINER_TIMER TIM3 +#define TRAINER_TIMER_IRQn TIM3_IRQn +#define TRAINER_GPIO_AF GPIO_AF_TIM3 +#define TRAINER_DMA DMA1 +#define TRAINER_DMA_CHANNEL DMA_Channel_5 +#define TRAINER_DMA_STREAM DMA1_Stream2 +#define TRAINER_DMA_IRQn DMA1_Stream2_IRQn +#define TRAINER_DMA_IRQHandler DMA1_Stream2_IRQHandler +#define TRAINER_DMA_FLAG_TC DMA_IT_TCIF2 +#define TRAINER_TIMER_IRQn TIM3_IRQn +#define TRAINER_TIMER_IRQHandler TIM3_IRQHandler +#define TRAINER_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) + +// Serial Port +#if defined(PCBX7) +#define SERIAL_RCC_AHB1Periph 0 +#define SERIAL_RCC_APB1Periph 0 +#else +#define SERIAL_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) +#define SERIAL_RCC_APB1Periph RCC_APB1Periph_USART3 +#define SERIAL_GPIO GPIOB +#define SERIAL_GPIO_PIN_TX GPIO_Pin_10 // PB.10 +#define SERIAL_GPIO_PIN_RX GPIO_Pin_11 // PB.11 +#define SERIAL_GPIO_PinSource_TX GPIO_PinSource10 +#define SERIAL_GPIO_PinSource_RX GPIO_PinSource11 +#define SERIAL_GPIO_AF GPIO_AF_USART3 +#define SERIAL_USART USART3 +#define SERIAL_USART_IRQHandler USART3_IRQHandler +#define SERIAL_USART_IRQn USART3_IRQn +#define SERIAL_DMA_Stream_RX DMA1_Stream1 +#define SERIAL_DMA_Channel_RX DMA_Channel_4 +#endif + +// Telemetry +#define TELEMETRY_RCC_AHB1Periph (RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) +#define TELEMETRY_RCC_APB1Periph RCC_APB1Periph_USART2 +#define TELEMETRY_DIR_GPIO GPIOD +#define TELEMETRY_DIR_GPIO_PIN GPIO_Pin_4 // PD.04 +#define TELEMETRY_GPIO GPIOD +#define TELEMETRY_TX_GPIO_PIN GPIO_Pin_5 // PD.05 +#define TELEMETRY_RX_GPIO_PIN GPIO_Pin_6 // PD.06 +#define TELEMETRY_GPIO_PinSource_TX GPIO_PinSource5 +#define TELEMETRY_GPIO_PinSource_RX GPIO_PinSource6 +#define TELEMETRY_GPIO_AF GPIO_AF_USART2 +#define TELEMETRY_USART USART2 +#define TELEMETRY_DMA_Stream_TX DMA1_Stream6 +#define TELEMETRY_DMA_Channel_TX DMA_Channel_4 +#define TELEMETRY_DMA_TX_Stream_IRQ DMA1_Stream6_IRQn +#define TELEMETRY_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler +#define TELEMETRY_DMA_TX_FLAG_TC DMA_IT_TCIF6 +#define TELEMETRY_USART_IRQHandler USART2_IRQHandler +#define TELEMETRY_USART_IRQn USART2_IRQn + +// PCBREV +#if defined(PCBX7) +#define PCBREV_RCC_AHB1Periph RCC_AHB1Periph_GPIOA +#define PCBREV_GPIO GPIOA +#define PCBREV_GPIO_PIN GPIO_Pin_14 // PA.14 +#else +#define PCBREV_RCC_AHB1Periph 0 +#endif + +// SPORT update connector +#if defined(PCBX7) +#define SPORT_UPDATE_RCC_AHB1Periph RCC_AHB1Periph_GPIOB +#define SPORT_UPDATE_PWR_GPIO GPIOB +#define SPORT_UPDATE_PWR_GPIO_PIN GPIO_Pin_2 // PB.02 +#else +#define SPORT_UPDATE_RCC_AHB1Periph 0 +#endif + +// Heartbeat +#define HEARTBEAT_RCC_AHB1Periph RCC_AHB1Periph_GPIOC +#define HEARTBEAT_RCC_APB2Periph RCC_APB2Periph_USART6 +#define HEARTBEAT_GPIO GPIOC +#define HEARTBEAT_GPIO_PIN GPIO_Pin_7 // PC.07 +#define HEARTBEAT_GPIO_PinSource GPIO_PinSource7 +#define HEARTBEAT_GPIO_AF_SBUS GPIO_AF_USART6 +#define HEARTBEAT_GPIO_AF_CAPTURE GPIO_AF_TIM3 +#define HEARTBEAT_USART USART6 +#define HEARTBEAT_USART_IRQHandler USART6_IRQHandler +#define HEARTBEAT_USART_IRQn USART6_IRQn +#define HEARTBEAT_DMA_Stream DMA2_Stream1 +#define HEARTBEAT_DMA_Channel DMA_Channel_5 + +// USB +#define USB_RCC_AHB1Periph_GPIO RCC_AHB1Periph_GPIOA +#define USB_GPIO GPIOA +#define USB_GPIO_PIN_VBUS GPIO_Pin_9 // PA.09 +#define USB_GPIO_PIN_DM GPIO_Pin_11 // PA.11 +#define USB_GPIO_PIN_DP GPIO_Pin_12 // PA.12 +#define USB_GPIO_PinSource_DM GPIO_PinSource11 +#define USB_GPIO_PinSource_DP GPIO_PinSource12 +#define USB_GPIO_AF GPIO_AF_OTG1_FS + +// BackLight +#if defined(PCBX9E) + #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOE + #define BACKLIGHT_RCC_APB1Periph 0 + #define BACKLIGHT_RCC_APB2Periph RCC_APB2Periph_TIM9 + #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) + #define BACKLIGHT_TIMER TIM9 + #define BACKLIGHT_GPIO GPIOE + #define BACKLIGHT_GPIO_PIN_1 GPIO_Pin_6 // PE.06 + #define BACKLIGHT_GPIO_PIN_2 GPIO_Pin_5 // PE.05 + #define BACKLIGHT_GPIO_PinSource_1 GPIO_PinSource6 + #define BACKLIGHT_GPIO_PinSource_2 GPIO_PinSource5 + #define BACKLIGHT_GPIO_AF_1 GPIO_AF_TIM9 + #define BACKLIGHT_GPIO_AF_2 GPIO_AF_TIM9 +#elif defined (PCBX9DP) + #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOD + #define BACKLIGHT_RCC_APB1Periph RCC_APB1Periph_TIM4 + #define BACKLIGHT_RCC_APB2Periph 0 + #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) + #define BACKLIGHT_TIMER TIM4 + #define BACKLIGHT_GPIO GPIOD + #define BACKLIGHT_GPIO_PIN_1 GPIO_Pin_15 // PD.15 + #define BACKLIGHT_GPIO_PIN_2 GPIO_Pin_13 // PD.13 + #define BACKLIGHT_GPIO_PinSource_1 GPIO_PinSource15 + #define BACKLIGHT_GPIO_PinSource_2 GPIO_PinSource13 + #define BACKLIGHT_GPIO_AF_1 GPIO_AF_TIM4 + #define BACKLIGHT_GPIO_AF_2 GPIO_AF_TIM4 +#elif defined(PCBX7) + #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOD + #define BACKLIGHT_RCC_APB1Periph RCC_APB1Periph_TIM4 + #define BACKLIGHT_RCC_APB2Periph 0 + #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) + #define BACKLIGHT_TIMER TIM4 + #define BACKLIGHT_GPIO GPIOD + #define BACKLIGHT_GPIO_PIN GPIO_Pin_13 // PD.13 + #define BACKLIGHT_GPIO_PinSource GPIO_PinSource13 + #define BACKLIGHT_GPIO_AF GPIO_AF_TIM4 +#else + #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOB + #define BACKLIGHT_RCC_APB1Periph 0 + #define BACKLIGHT_RCC_APB2Periph RCC_APB2Periph_TIM10 + #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) + #define BACKLIGHT_TIMER TIM10 + #define BACKLIGHT_GPIO GPIOB + #define BACKLIGHT_GPIO_PIN GPIO_Pin_8 // PB.08 + #define BACKLIGHT_GPIO_PinSource GPIO_PinSource8 + #define BACKLIGHT_GPIO_AF GPIO_AF_TIM10 +#endif + +// LCD driver +#if defined(PCBX9E) + #define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) + #define LCD_RCC_APB1Periph RCC_APB1Periph_SPI3 + #define LCD_SPI_GPIO GPIOC + #define LCD_MOSI_GPIO_PIN GPIO_Pin_12 // PC.12 + #define LCD_MOSI_GPIO_PinSource GPIO_PinSource12 + #define LCD_CLK_GPIO_PIN GPIO_Pin_10 // PC.10 + #define LCD_CLK_GPIO_PinSource GPIO_PinSource10 + #define LCD_A0_GPIO_PIN GPIO_Pin_11 // PC.11 + #define LCD_NCS_GPIO GPIOA + #define LCD_NCS_GPIO_PIN GPIO_Pin_15 // PA.15 + #define LCD_RST_GPIO GPIOD + #define LCD_RST_GPIO_PIN GPIO_Pin_15 // PD.15 + #define LCD_DMA DMA1 + #define LDC_DMA_Stream DMA1_Stream7 + #define LCD_DMA_Stream_IRQn DMA1_Stream7_IRQn + #define LCD_DMA_Stream_IRQHandler DMA1_Stream7_IRQHandler + #define LCD_DMA_FLAGS (DMA_HIFCR_CTCIF7 | DMA_HIFCR_CHTIF7 | DMA_HIFCR_CTEIF7 | DMA_HIFCR_CDMEIF7 | DMA_HIFCR_CFEIF7) + #define LCD_DMA_FLAG_INT DMA_HIFCR_CTCIF7 + #define LCD_SPI SPI3 + #define LCD_GPIO_AF GPIO_AF_SPI3 +#elif defined(PCBX9DP) || defined(PCBX7) + #define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) + #define LCD_RCC_APB1Periph RCC_APB1Periph_SPI3 + #define LCD_SPI_GPIO GPIOC + #define LCD_MOSI_GPIO_PIN GPIO_Pin_12 // PC.12 + #define LCD_MOSI_GPIO_PinSource GPIO_PinSource12 + #define LCD_CLK_GPIO_PIN GPIO_Pin_10 // PC.10 + #define LCD_CLK_GPIO_PinSource GPIO_PinSource10 + #define LCD_A0_GPIO_PIN GPIO_Pin_11 // PC.11 + #define LCD_NCS_GPIO GPIOA + #define LCD_NCS_GPIO_PIN GPIO_Pin_15 // PA.15 + #define LCD_RST_GPIO GPIOD + #define LCD_RST_GPIO_PIN GPIO_Pin_12 // PD.12 + #define LCD_DMA DMA1 + #define LDC_DMA_Stream DMA1_Stream7 + #define LCD_DMA_Stream_IRQn DMA1_Stream7_IRQn + #define LCD_DMA_Stream_IRQHandler DMA1_Stream7_IRQHandler + #define LCD_DMA_FLAGS (DMA_HIFCR_CTCIF7 | DMA_HIFCR_CHTIF7 | DMA_HIFCR_CTEIF7 | DMA_HIFCR_CDMEIF7 | DMA_HIFCR_CFEIF7) + #define LCD_DMA_FLAG_INT DMA_HIFCR_CTCIF7 + #define LCD_SPI SPI3 + #define LCD_GPIO_AF GPIO_AF_SPI3 +#else + #define LCD_RCC_AHB1Periph RCC_AHB1Periph_GPIOD + #define LCD_RCC_APB1Periph 0 + #define LCD_SPI_GPIO GPIOD + #define LCD_MOSI_GPIO_PIN GPIO_Pin_10 // PD.10 + #define LCD_CLK_GPIO_PIN GPIO_Pin_11 // PD.11 + #define LCD_A0_GPIO_PIN GPIO_Pin_13 // PD.13 + #define LCD_NCS_GPIO GPIOD + #define LCD_NCS_GPIO_PIN GPIO_Pin_14 // PD.14 + #define LCD_RST_GPIO GPIOD + #define LCD_RST_GPIO_PIN GPIO_Pin_12 // PD.12 +#endif + +// I2C Bus: EEPROM and CAT5137 digital pot for volume control +#define I2C_RCC_AHB1Periph RCC_AHB1Periph_GPIOB +#define I2C_RCC_APB1Periph RCC_APB1Periph_I2C1 +#define I2C I2C1 +#define I2C_GPIO GPIOB +#define I2C_SCL_GPIO_PIN GPIO_Pin_6 // PB.06 +#define I2C_SDA_GPIO_PIN GPIO_Pin_7 // PB.07 +#define I2C_GPIO_PIN_WP GPIO_Pin_9 // PB.09 +#define I2C_GPIO_AF GPIO_AF_I2C1 +#define I2C_SCL_GPIO_PinSource GPIO_PinSource6 +#define I2C_SDA_GPIO_PinSource GPIO_PinSource7 +#if defined(REV4a) + #define I2C_SPEED 100000 +#else + #define I2C_SPEED 400000 +#endif +#define I2C_ADDRESS_EEPROM 0xA2 +#define I2C_ADDRESS_VOLUME 0x5C +#define I2C_FLASH_PAGESIZE 64 + +// SD - SPI2 +#define SD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) +#define SD_RCC_APB1Periph RCC_APB1Periph_SPI2 +#define SD_GPIO_PRESENT GPIOD +#define SD_GPIO_PIN_PRESENT GPIO_Pin_9 // PD.09 +#define SD_GPIO GPIOB +#define SD_GPIO_PIN_CS GPIO_Pin_12 // PB.12 +#define SD_GPIO_PIN_SCK GPIO_Pin_13 // PB.13 +#define SD_GPIO_PIN_MISO GPIO_Pin_14 // PB.14 +#define SD_GPIO_PIN_MOSI GPIO_Pin_15 // PB.15 +#define SD_GPIO_AF GPIO_AF_SPI2 +#define SD_GPIO_PinSource_CS GPIO_PinSource12 +#define SD_GPIO_PinSource_SCK GPIO_PinSource13 +#define SD_GPIO_PinSource_MISO GPIO_PinSource14 +#define SD_GPIO_PinSource_MOSI GPIO_PinSource15 +#define SD_SPI SPI2 +#define SD_SPI_BaudRatePrescaler SPI_BaudRatePrescaler_4 // 10.5<20MHZ, make sure < 20MHZ + +#if !defined(BOOT) + #define SD_USE_DMA // Enable the DMA for SD + #define SD_DMA_Stream_SPI_RX DMA1_Stream3 + #define SD_DMA_Stream_SPI_TX DMA1_Stream4 + #define SD_DMA_FLAG_SPI_TC_RX DMA_FLAG_TCIF3 + #define SD_DMA_FLAG_SPI_TC_TX DMA_FLAG_TCIF4 + #define SD_DMA_Channel_SPI DMA_Channel_0 +#endif + +// Audio +#define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1) +#define AUDIO_RCC_APB1Periph (RCC_APB1Periph_TIM6 | RCC_APB1Periph_DAC) +#define AUDIO_OUTPUT_GPIO GPIOA +#define AUDIO_OUTPUT_GPIO_PIN GPIO_Pin_4 // PA.04 +#define AUDIO_DMA_Stream DMA1_Stream5 +#define AUDIO_DMA_Stream_IRQn DMA1_Stream5_IRQn +#define AUDIO_TIM_IRQn TIM6_DAC_IRQn +#define AUDIO_TIM_IRQHandler TIM6_DAC_IRQHandler +#define AUDIO_DMA_Stream_IRQHandler DMA1_Stream5_IRQHandler +#define AUDIO_TIMER TIM6 +#define AUDIO_DMA DMA1 + +// Haptic +#if defined(PCBX9E) || defined(PCBX9DP) || defined(PCBX7) + #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOB + #define HAPTIC_RCC_APB2Periph RCC_APB2Periph_TIM10 + #define HAPTIC_GPIO_PinSource GPIO_PinSource8 + #define HAPTIC_GPIO GPIOB + #define HAPTIC_GPIO_PIN GPIO_Pin_8 // PB.08 + #define HAPTIC_GPIO_AF GPIO_AF_TIM10 + #define HAPTIC_TIMER TIM10 +#else + #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOC + #define HAPTIC_RCC_APB2Periph 0 + #define HAPTIC_GPIO GPIOC + #define HAPTIC_GPIO_PIN GPIO_Pin_12 +#endif + +// Top LCD on X9E +#if defined(PCBX9E) + #define TOPLCD_RCC_AHB1Periph RCC_AHB1Periph_GPIOG + #define TOPLCD_GPIO GPIOG + #define TOPLCD_GPIO_PIN_DATA GPIO_Pin_5 + #define TOPLCD_GPIO_PIN_WR GPIO_Pin_4 + #define TOPLCD_GPIO_PIN_CS1 GPIO_Pin_3 + #define TOPLCD_GPIO_PIN_CS2 GPIO_Pin_15 + #define TOPLCD_GPIO_PIN_BL GPIO_Pin_2 +#endif + +// Bluetooth +#if defined(PCBX9E) + #define BT_USART USART6 + #define BT_GPIO_AF GPIO_AF_USART6 + #define BT_USART_IRQn USART6_IRQn + #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOB) + #define BT_GPIO_TXRX GPIOG + #define BT_TX_GPIO_PIN GPIO_Pin_14 // PG.14 + #define BT_RX_GPIO_PIN GPIO_Pin_9 // PG.09 + #define BT_EN_GPIO GPIOD + #define BT_EN_GPIO_PIN GPIO_Pin_11 // PD.11 + #define BT_BRTS_GPIO GPIOE + #define BT_BRTS_GPIO_PIN GPIO_Pin_12 // PE.12 + #define BT_BCTS_GPIO GPIOG + #define BT_BCTS_GPIO_PIN GPIO_Pin_6 // PG.06 + #define BT_TX_GPIO_PinSource GPIO_PinSource14 + #define BT_RX_GPIO_PinSource GPIO_PinSource9 +#elif defined(PCBX7) + #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_DMA1) + #define BT_RCC_APB1Periph RCC_APB1Periph_USART3 + #define BT_EN_GPIO GPIOE + #define BT_EN_GPIO_PIN GPIO_Pin_12 // PE.12 + #define BT_GPIO_TXRX GPIOB + #define BT_TX_GPIO_PIN GPIO_Pin_10 // PB.10 + #define BT_RX_GPIO_PIN GPIO_Pin_11 // PB.11 + #define BT_TX_GPIO_PinSource GPIO_PinSource10 + #define BT_RX_GPIO_PinSource GPIO_PinSource11 + #define BT_GPIO_AF GPIO_AF_USART3 + #define BT_USART USART3 + #define BT_USART_IRQHandler USART3_IRQHandler + #define BT_USART_IRQn USART3_IRQn + #define BT_DMA_Stream_RX DMA1_Stream1 + #define BT_DMA_Channel_RX DMA_Channel_4 +#endif + +// 5ms Interrupt +#define INTERRUPT_5MS_APB1Periph RCC_APB1Periph_TIM14 +#define INTERRUPT_5MS_TIMER TIM14 +#define INTERRUPT_5MS_IRQn TIM8_TRG_COM_TIM14_IRQn +#define INTERRUPT_5MS_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler + +// 2MHz Timer +#define TIMER_2MHz_APB1Periph RCC_APB1Periph_TIM7 +#define TIMER_2MHz_TIMER TIM7 + +#endif // _HAL_H_ diff --git a/radio/src/targets/taranis/i2c_driver.cpp b/radio/src/targets/taranis/i2c_driver.cpp index baf26b9f8..d8e9ef480 100644 --- a/radio/src/targets/taranis/i2c_driver.cpp +++ b/radio/src/targets/taranis/i2c_driver.cpp @@ -1,292 +1,292 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "board.h" - -void eepromPageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite); -void eepromWaitEepromStandbyState(void); - -void i2cInit() -{ - I2C_DeInit(I2C); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = I2C_GPIO_PIN_WP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(I2C_GPIO, &GPIO_InitStructure); - GPIO_ResetBits(I2C_GPIO, I2C_GPIO_PIN_WP); - - I2C_InitTypeDef I2C_InitStructure; - I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = 0x00; - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_Init(I2C, &I2C_InitStructure); - I2C_Cmd(I2C, ENABLE); - - GPIO_PinAFConfig(I2C_GPIO, I2C_SCL_GPIO_PinSource, I2C_GPIO_AF); - GPIO_PinAFConfig(I2C_GPIO, I2C_SDA_GPIO_PinSource, I2C_GPIO_AF); - - GPIO_InitStructure.GPIO_Pin = I2C_SCL_GPIO_PIN | I2C_SDA_GPIO_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(I2C_GPIO, &GPIO_InitStructure); -} - -#define I2C_TIMEOUT_MAX 1000 -bool I2C_WaitEvent(uint32_t event) -{ - uint32_t timeout = I2C_TIMEOUT_MAX; - while (!I2C_CheckEvent(I2C, event)) { - if ((timeout--) == 0) return false; - } - return true; -} - -bool I2C_WaitEventCleared(uint32_t event) -{ - uint32_t timeout = I2C_TIMEOUT_MAX; - while (I2C_CheckEvent(I2C, event)) { - if ((timeout--) == 0) return false; - } - return true; -} - -/** - * @brief Reads a block of data from the EEPROM. - * @param pBuffer : pointer to the buffer that receives the data read - * from the EEPROM. - * @param ReadAddr : EEPROM's internal address to read from. - * @param NumByteToRead : number of bytes to read from the EEPROM. - * @retval None - */ -bool I2C_EE_ReadBlock(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead) -{ - if (!I2C_WaitEventCleared(I2C_FLAG_BUSY)) - return false; - - I2C_GenerateSTART(I2C, ENABLE); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_MODE_SELECT)) - return false; - - I2C_Send7bitAddress(I2C, I2C_ADDRESS_EEPROM, I2C_Direction_Transmitter); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - return false; - - I2C_SendData(I2C, (uint8_t)((ReadAddr & 0xFF00) >> 8)); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTING)) - return false; - I2C_SendData(I2C, (uint8_t)(ReadAddr & 0x00FF)); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTED)) - return false; - - I2C_GenerateSTART(I2C, ENABLE); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_MODE_SELECT)) - return false; - - I2C_Send7bitAddress(I2C, I2C_ADDRESS_EEPROM, I2C_Direction_Receiver); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - return false; - - if (NumByteToRead > 1) { - I2C_AcknowledgeConfig(I2C, ENABLE); - } - - while (NumByteToRead) { - if (NumByteToRead == 1) { - I2C_AcknowledgeConfig(I2C, DISABLE); - } - if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_RECEIVED)) - return false; - *pBuffer++ = I2C_ReceiveData(I2C); - NumByteToRead--; - } - - I2C_GenerateSTOP(I2C, ENABLE); - return true; -} - -void eepromReadBlock(uint8_t * buffer, size_t address, size_t size) -{ - while (!I2C_EE_ReadBlock(buffer, address, size)) { - i2cInit(); - } -} - -/** - * @brief Writes buffer of data to the I2C EEPROM. - * @param buffer : pointer to the buffer containing the data to be - * written to the EEPROM. - * @param address : EEPROM's internal address to write to. - * @param size : number of bytes to write to the EEPROM. - * @retval None - */ -void eepromWriteBlock(uint8_t * buffer, size_t address, size_t size) -{ - uint8_t offset = address % I2C_FLASH_PAGESIZE; - uint8_t count = I2C_FLASH_PAGESIZE - offset; - if (size < count) { - count = size; - } - while (count > 0) { - eepromPageWrite(buffer, address, count); - eepromWaitEepromStandbyState(); - address += count; - buffer += count; - size -= count; - count = I2C_FLASH_PAGESIZE; - if (size < I2C_FLASH_PAGESIZE) { - count = size; - } - } -} - -uint8_t eepromIsTransferComplete() -{ - return 1; -} - -/** - * @brief Writes more than one byte to the EEPROM with a single WRITE cycle. - * @note The number of byte can't exceed the EEPROM page size. - * @param pBuffer : pointer to the buffer containing the data to be - * written to the EEPROM. - * @param WriteAddr : EEPROM's internal address to write to. - * @param NumByteToWrite : number of bytes to write to the EEPROM. - * @retval None - */ -bool I2C_EE_PageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite) -{ - if (!I2C_WaitEventCleared(I2C_FLAG_BUSY)) - return false; - - I2C_GenerateSTART(I2C, ENABLE); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_MODE_SELECT)) - return false; - - I2C_Send7bitAddress(I2C, I2C_ADDRESS_EEPROM, I2C_Direction_Transmitter); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - return false; - - I2C_SendData(I2C, (uint8_t)((WriteAddr & 0xFF00) >> 8)); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTING)) - return false; - I2C_SendData(I2C, (uint8_t)(WriteAddr & 0x00FF)); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTING)) - return false; - - /* While there is data to be written */ - while (NumByteToWrite--) { - I2C_SendData(I2C, *pBuffer); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTING)) - return false; - pBuffer++; - } - - if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTED)) - return false; - - I2C_GenerateSTOP(I2C, ENABLE); - return true; -} - -void eepromPageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite) -{ - while (!I2C_EE_PageWrite(pBuffer, WriteAddr, NumByteToWrite)) { - i2cInit(); - } -} - -/** - * @brief Wait for EEPROM Standby state - * @param None - * @retval None - */ -bool I2C_EE_WaitEepromStandbyState(void) -{ - do { - I2C_GenerateSTART(I2C, ENABLE); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_MODE_SELECT)) - return false; - - I2C_Send7bitAddress(I2C, I2C_ADDRESS_EEPROM, I2C_Direction_Transmitter); - } while (!I2C_WaitEvent(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)); - - I2C_GenerateSTOP(I2C, ENABLE); - return true; -} - -void eepromWaitEepromStandbyState(void) -{ - while (!I2C_EE_WaitEepromStandbyState()) { - i2cInit(); - } -} - -#if !defined(BOOT) && !defined(SOFTWARE_VOLUME) -const uint8_t volumeScale[VOLUME_LEVEL_MAX+1] = { - 0, 1, 2, 3, 5, 9, 13, 17, 22, 27, 33, 40, - 64, 82, 96, 105, 112, 117, 120, 122, 124, 125, 126, 127 -}; - -void setScaledVolume(uint8_t volume) -{ - if (volume > VOLUME_LEVEL_MAX) { - volume = VOLUME_LEVEL_MAX; - } - - setVolume(volumeScale[volume]); -} - -void setVolume(uint8_t volume) -{ - if (!I2C_WaitEventCleared(I2C_FLAG_BUSY)) - return; - - I2C_GenerateSTART(I2C, ENABLE); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_MODE_SELECT)) - return; - - I2C_Send7bitAddress(I2C, I2C_ADDRESS_VOLUME, I2C_Direction_Transmitter); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - return; - - I2C_SendData(I2C, 0); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTING)) - return; - I2C_SendData(I2C, volume); - if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTED)) - return; - - I2C_GenerateSTOP(I2C, ENABLE); -} - -int32_t getVolume() -{ - return -1; // TODO -} -#endif +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "board.h" + +void eepromPageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite); +void eepromWaitEepromStandbyState(void); + +void i2cInit() +{ + I2C_DeInit(I2C); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = I2C_GPIO_PIN_WP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(I2C_GPIO, &GPIO_InitStructure); + GPIO_ResetBits(I2C_GPIO, I2C_GPIO_PIN_WP); + + I2C_InitTypeDef I2C_InitStructure; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStructure.I2C_OwnAddress1 = 0x00; + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + I2C_Init(I2C, &I2C_InitStructure); + I2C_Cmd(I2C, ENABLE); + + GPIO_PinAFConfig(I2C_GPIO, I2C_SCL_GPIO_PinSource, I2C_GPIO_AF); + GPIO_PinAFConfig(I2C_GPIO, I2C_SDA_GPIO_PinSource, I2C_GPIO_AF); + + GPIO_InitStructure.GPIO_Pin = I2C_SCL_GPIO_PIN | I2C_SDA_GPIO_PIN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(I2C_GPIO, &GPIO_InitStructure); +} + +#define I2C_TIMEOUT_MAX 1000 +bool I2C_WaitEvent(uint32_t event) +{ + uint32_t timeout = I2C_TIMEOUT_MAX; + while (!I2C_CheckEvent(I2C, event)) { + if ((timeout--) == 0) return false; + } + return true; +} + +bool I2C_WaitEventCleared(uint32_t event) +{ + uint32_t timeout = I2C_TIMEOUT_MAX; + while (I2C_CheckEvent(I2C, event)) { + if ((timeout--) == 0) return false; + } + return true; +} + +/** + * @brief Reads a block of data from the EEPROM. + * @param pBuffer : pointer to the buffer that receives the data read + * from the EEPROM. + * @param ReadAddr : EEPROM's internal address to read from. + * @param NumByteToRead : number of bytes to read from the EEPROM. + * @retval None + */ +bool I2C_EE_ReadBlock(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead) +{ + if (!I2C_WaitEventCleared(I2C_FLAG_BUSY)) + return false; + + I2C_GenerateSTART(I2C, ENABLE); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_MODE_SELECT)) + return false; + + I2C_Send7bitAddress(I2C, I2C_ADDRESS_EEPROM, I2C_Direction_Transmitter); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + return false; + + I2C_SendData(I2C, (uint8_t)((ReadAddr & 0xFF00) >> 8)); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTING)) + return false; + I2C_SendData(I2C, (uint8_t)(ReadAddr & 0x00FF)); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTED)) + return false; + + I2C_GenerateSTART(I2C, ENABLE); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_MODE_SELECT)) + return false; + + I2C_Send7bitAddress(I2C, I2C_ADDRESS_EEPROM, I2C_Direction_Receiver); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) + return false; + + if (NumByteToRead > 1) { + I2C_AcknowledgeConfig(I2C, ENABLE); + } + + while (NumByteToRead) { + if (NumByteToRead == 1) { + I2C_AcknowledgeConfig(I2C, DISABLE); + } + if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_RECEIVED)) + return false; + *pBuffer++ = I2C_ReceiveData(I2C); + NumByteToRead--; + } + + I2C_GenerateSTOP(I2C, ENABLE); + return true; +} + +void eepromReadBlock(uint8_t * buffer, size_t address, size_t size) +{ + while (!I2C_EE_ReadBlock(buffer, address, size)) { + i2cInit(); + } +} + +/** + * @brief Writes buffer of data to the I2C EEPROM. + * @param buffer : pointer to the buffer containing the data to be + * written to the EEPROM. + * @param address : EEPROM's internal address to write to. + * @param size : number of bytes to write to the EEPROM. + * @retval None + */ +void eepromWriteBlock(uint8_t * buffer, size_t address, size_t size) +{ + uint8_t offset = address % I2C_FLASH_PAGESIZE; + uint8_t count = I2C_FLASH_PAGESIZE - offset; + if (size < count) { + count = size; + } + while (count > 0) { + eepromPageWrite(buffer, address, count); + eepromWaitEepromStandbyState(); + address += count; + buffer += count; + size -= count; + count = I2C_FLASH_PAGESIZE; + if (size < I2C_FLASH_PAGESIZE) { + count = size; + } + } +} + +uint8_t eepromIsTransferComplete() +{ + return 1; +} + +/** + * @brief Writes more than one byte to the EEPROM with a single WRITE cycle. + * @note The number of byte can't exceed the EEPROM page size. + * @param pBuffer : pointer to the buffer containing the data to be + * written to the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @param NumByteToWrite : number of bytes to write to the EEPROM. + * @retval None + */ +bool I2C_EE_PageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite) +{ + if (!I2C_WaitEventCleared(I2C_FLAG_BUSY)) + return false; + + I2C_GenerateSTART(I2C, ENABLE); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_MODE_SELECT)) + return false; + + I2C_Send7bitAddress(I2C, I2C_ADDRESS_EEPROM, I2C_Direction_Transmitter); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + return false; + + I2C_SendData(I2C, (uint8_t)((WriteAddr & 0xFF00) >> 8)); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTING)) + return false; + I2C_SendData(I2C, (uint8_t)(WriteAddr & 0x00FF)); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTING)) + return false; + + /* While there is data to be written */ + while (NumByteToWrite--) { + I2C_SendData(I2C, *pBuffer); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTING)) + return false; + pBuffer++; + } + + if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTED)) + return false; + + I2C_GenerateSTOP(I2C, ENABLE); + return true; +} + +void eepromPageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite) +{ + while (!I2C_EE_PageWrite(pBuffer, WriteAddr, NumByteToWrite)) { + i2cInit(); + } +} + +/** + * @brief Wait for EEPROM Standby state + * @param None + * @retval None + */ +bool I2C_EE_WaitEepromStandbyState(void) +{ + do { + I2C_GenerateSTART(I2C, ENABLE); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_MODE_SELECT)) + return false; + + I2C_Send7bitAddress(I2C, I2C_ADDRESS_EEPROM, I2C_Direction_Transmitter); + } while (!I2C_WaitEvent(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)); + + I2C_GenerateSTOP(I2C, ENABLE); + return true; +} + +void eepromWaitEepromStandbyState(void) +{ + while (!I2C_EE_WaitEepromStandbyState()) { + i2cInit(); + } +} + +#if !defined(BOOT) && !defined(SOFTWARE_VOLUME) +const uint8_t volumeScale[VOLUME_LEVEL_MAX+1] = { + 0, 1, 2, 3, 5, 9, 13, 17, 22, 27, 33, 40, + 64, 82, 96, 105, 112, 117, 120, 122, 124, 125, 126, 127 +}; + +void setScaledVolume(uint8_t volume) +{ + if (volume > VOLUME_LEVEL_MAX) { + volume = VOLUME_LEVEL_MAX; + } + + setVolume(volumeScale[volume]); +} + +void setVolume(uint8_t volume) +{ + if (!I2C_WaitEventCleared(I2C_FLAG_BUSY)) + return; + + I2C_GenerateSTART(I2C, ENABLE); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_MODE_SELECT)) + return; + + I2C_Send7bitAddress(I2C, I2C_ADDRESS_VOLUME, I2C_Direction_Transmitter); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + return; + + I2C_SendData(I2C, 0); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTING)) + return; + I2C_SendData(I2C, volume); + if (!I2C_WaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTED)) + return; + + I2C_GenerateSTOP(I2C, ENABLE); +} + +int32_t getVolume() +{ + return -1; // TODO +} +#endif diff --git a/radio/src/targets/taranis/keys_driver.cpp b/radio/src/targets/taranis/keys_driver.cpp index 3a43bbdb2..7ed417709 100644 --- a/radio/src/targets/taranis/keys_driver.cpp +++ b/radio/src/targets/taranis/keys_driver.cpp @@ -1,245 +1,245 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#if defined(ROTARY_ENCODER_NAVIGATION) -uint32_t rotencPosition; -#endif - -uint32_t readKeys() -{ - uint32_t result = 0; - - if (~KEYS_GPIO_REG_ENTER & KEYS_GPIO_PIN_ENTER) - result |= 1 << KEY_ENTER; - if (~KEYS_GPIO_REG_MENU & KEYS_GPIO_PIN_MENU) - result |= 1 << KEY_MENU; - if (~KEYS_GPIO_REG_PAGE & KEYS_GPIO_PIN_PAGE) - result |= 1 << KEY_PAGE; - if (~KEYS_GPIO_REG_EXIT & KEYS_GPIO_PIN_EXIT) - result |= 1 << KEY_EXIT; - -#if !defined(PCBX9E) && !defined(PCBX7) - if (~KEYS_GPIO_REG_PLUS & KEYS_GPIO_PIN_PLUS) - result |= 1 << KEY_PLUS; - if (~KEYS_GPIO_REG_MINUS & KEYS_GPIO_PIN_MINUS) - result |= 1 << KEY_MINUS; -#endif - - // if (result != 0) TRACE("readKeys(): result=0x%02x", result); - - return result; -} - -uint32_t readTrims() -{ - uint32_t result = 0; - - if (~TRIMS_GPIO_REG_LHL & TRIMS_GPIO_PIN_LHL) - result |= 0x01; - if (~TRIMS_GPIO_REG_LHR & TRIMS_GPIO_PIN_LHR) - result |= 0x02; - if (~TRIMS_GPIO_REG_LVD & TRIMS_GPIO_PIN_LVD) - result |= 0x04; - if (~TRIMS_GPIO_REG_LVU & TRIMS_GPIO_PIN_LVU) - result |= 0x08; - if (~TRIMS_GPIO_REG_RVD & TRIMS_GPIO_PIN_RVD) - result |= 0x10; - if (~TRIMS_GPIO_REG_RVU & TRIMS_GPIO_PIN_RVU) - result |= 0x20; - if (~TRIMS_GPIO_REG_RHL & TRIMS_GPIO_PIN_RHL) - result |= 0x40; - if (~TRIMS_GPIO_REG_RHR & TRIMS_GPIO_PIN_RHR) - result |= 0x80; - - // TRACE("readTrims(): result=0x%02x", result); - - return result; -} - -uint8_t trimDown(uint8_t idx) -{ - return readTrims() & (1 << idx); -} - -uint8_t keyDown() -{ - return readKeys(); -} - -#if defined(ROTARY_ENCODER_NAVIGATION) -void checkRotaryEncoder() -{ - uint32_t newpos = ROTARY_ENCODER_POSITION(); - if (newpos != rotencPosition && !keyState(KEY_ENTER)) { - if ((rotencPosition & 0x01) ^ ((newpos & 0x02) >> 1)) { - --rotencValue[0]; - } - else { - ++rotencValue[0]; - } - rotencPosition = newpos; - } -} -#endif - -/* TODO common to ARM */ -void readKeysAndTrims() -{ - uint8_t index = 0; - uint32_t in = readKeys(); - for (uint8_t i = 1; i != uint8_t(1 << TRM_BASE); i <<= 1) { - keys[index++].input(in & i); - } - - in = readTrims(); - for (uint8_t i = 1; i != uint8_t(1 << 8); i <<= 1) { - keys[index++].input(in & i); - } -} - -#if defined(PCBX9E) - #define ADD_2POS_CASE(x) \ - case SW_S ## x ## 2: \ - xxx = SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ - break; \ - case SW_S ## x ## 0: \ - xxx = ~SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ - break; -#else - #define ADD_2POS_CASE(x) \ - case SW_S ## x ## 0: \ - xxx = SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ - break; \ - case SW_S ## x ## 2: \ - xxx = ~SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ - break; -#endif - #define ADD_3POS_CASE(x, i) \ - case SW_S ## x ## 0: \ - xxx = (SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H); \ - if (IS_CONFIG_3POS(i)) { \ - xxx = xxx && (~SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ - } \ - break; \ - case SW_S ## x ## 1: \ - xxx = (SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H) && (SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ - break; \ - case SW_S ## x ## 2: \ - xxx = (~SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H); \ - if (IS_CONFIG_3POS(i)) { \ - xxx = xxx && (SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ - } \ - break - -uint8_t keyState(uint8_t index) -{ - return keys[index].state(); -} - -#if !defined(BOOT) -uint32_t switchState(uint8_t index) -{ - uint32_t xxx = 0; - - switch (index) { - ADD_3POS_CASE(A, 0); - ADD_3POS_CASE(B, 1); - ADD_3POS_CASE(C, 2); - ADD_3POS_CASE(D, 3); -#if defined(PCBX7) - ADD_2POS_CASE(F); - ADD_2POS_CASE(H); -#else - ADD_3POS_CASE(E, 4); - ADD_2POS_CASE(F); - ADD_3POS_CASE(G, 6); - ADD_2POS_CASE(H); -#endif -#if defined(PCBX9E) - ADD_3POS_CASE(I, 8); - ADD_3POS_CASE(J, 9); - ADD_3POS_CASE(K, 10); - ADD_3POS_CASE(L, 11); - ADD_3POS_CASE(M, 12); - ADD_3POS_CASE(N, 13); - ADD_3POS_CASE(O, 14); - ADD_3POS_CASE(P, 15); - ADD_3POS_CASE(Q, 16); - ADD_3POS_CASE(R, 17); -#endif - - default: - break; - } - - // TRACE("switch %d => %d", index, xxx); - return xxx; -} -#endif - -void keysInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; - -#if defined(KEYS_GPIOA_PINS) - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOA_PINS; - GPIO_Init(GPIOA, &GPIO_InitStructure); -#endif - -#if defined(KEYS_GPIOB_PINS) - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOB_PINS; - GPIO_Init(GPIOB, &GPIO_InitStructure); -#endif - -#if defined(KEYS_GPIOC_PINS) - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOC_PINS; - GPIO_Init(GPIOC, &GPIO_InitStructure); -#endif - -#if defined(KEYS_GPIOD_PINS) - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOD_PINS; - GPIO_Init(GPIOD, &GPIO_InitStructure); -#endif - -#if defined(KEYS_GPIOE_PINS) - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOE_PINS; - GPIO_Init(GPIOE, &GPIO_InitStructure); -#endif - -#if defined(KEYS_GPIOF_PINS) - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOF_PINS; - GPIO_Init(GPIOF, &GPIO_InitStructure); -#endif - -#if defined(KEYS_GPIOG_PINS) - GPIO_InitStructure.GPIO_Pin = KEYS_GPIOG_PINS; - GPIO_Init(GPIOG, &GPIO_InitStructure); -#endif - -#if defined(ROTARY_ENCODER_NAVIGATION) - rotencPosition = ROTARY_ENCODER_POSITION(); -#endif -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#if defined(ROTARY_ENCODER_NAVIGATION) +uint32_t rotencPosition; +#endif + +uint32_t readKeys() +{ + uint32_t result = 0; + + if (~KEYS_GPIO_REG_ENTER & KEYS_GPIO_PIN_ENTER) + result |= 1 << KEY_ENTER; + if (~KEYS_GPIO_REG_MENU & KEYS_GPIO_PIN_MENU) + result |= 1 << KEY_MENU; + if (~KEYS_GPIO_REG_PAGE & KEYS_GPIO_PIN_PAGE) + result |= 1 << KEY_PAGE; + if (~KEYS_GPIO_REG_EXIT & KEYS_GPIO_PIN_EXIT) + result |= 1 << KEY_EXIT; + +#if !defined(PCBX9E) && !defined(PCBX7) + if (~KEYS_GPIO_REG_PLUS & KEYS_GPIO_PIN_PLUS) + result |= 1 << KEY_PLUS; + if (~KEYS_GPIO_REG_MINUS & KEYS_GPIO_PIN_MINUS) + result |= 1 << KEY_MINUS; +#endif + + // if (result != 0) TRACE("readKeys(): result=0x%02x", result); + + return result; +} + +uint32_t readTrims() +{ + uint32_t result = 0; + + if (~TRIMS_GPIO_REG_LHL & TRIMS_GPIO_PIN_LHL) + result |= 0x01; + if (~TRIMS_GPIO_REG_LHR & TRIMS_GPIO_PIN_LHR) + result |= 0x02; + if (~TRIMS_GPIO_REG_LVD & TRIMS_GPIO_PIN_LVD) + result |= 0x04; + if (~TRIMS_GPIO_REG_LVU & TRIMS_GPIO_PIN_LVU) + result |= 0x08; + if (~TRIMS_GPIO_REG_RVD & TRIMS_GPIO_PIN_RVD) + result |= 0x10; + if (~TRIMS_GPIO_REG_RVU & TRIMS_GPIO_PIN_RVU) + result |= 0x20; + if (~TRIMS_GPIO_REG_RHL & TRIMS_GPIO_PIN_RHL) + result |= 0x40; + if (~TRIMS_GPIO_REG_RHR & TRIMS_GPIO_PIN_RHR) + result |= 0x80; + + // TRACE("readTrims(): result=0x%02x", result); + + return result; +} + +uint8_t trimDown(uint8_t idx) +{ + return readTrims() & (1 << idx); +} + +uint8_t keyDown() +{ + return readKeys(); +} + +#if defined(ROTARY_ENCODER_NAVIGATION) +void checkRotaryEncoder() +{ + uint32_t newpos = ROTARY_ENCODER_POSITION(); + if (newpos != rotencPosition && !keyState(KEY_ENTER)) { + if ((rotencPosition & 0x01) ^ ((newpos & 0x02) >> 1)) { + --rotencValue[0]; + } + else { + ++rotencValue[0]; + } + rotencPosition = newpos; + } +} +#endif + +/* TODO common to ARM */ +void readKeysAndTrims() +{ + uint8_t index = 0; + uint32_t in = readKeys(); + for (uint8_t i = 1; i != uint8_t(1 << TRM_BASE); i <<= 1) { + keys[index++].input(in & i); + } + + in = readTrims(); + for (uint8_t i = 1; i != uint8_t(1 << 8); i <<= 1) { + keys[index++].input(in & i); + } +} + +#if defined(PCBX9E) + #define ADD_2POS_CASE(x) \ + case SW_S ## x ## 2: \ + xxx = SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ + break; \ + case SW_S ## x ## 0: \ + xxx = ~SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ + break; +#else + #define ADD_2POS_CASE(x) \ + case SW_S ## x ## 0: \ + xxx = SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ + break; \ + case SW_S ## x ## 2: \ + xxx = ~SWITCHES_GPIO_REG_ ## x & SWITCHES_GPIO_PIN_ ## x ; \ + break; +#endif + #define ADD_3POS_CASE(x, i) \ + case SW_S ## x ## 0: \ + xxx = (SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H); \ + if (IS_CONFIG_3POS(i)) { \ + xxx = xxx && (~SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ + } \ + break; \ + case SW_S ## x ## 1: \ + xxx = (SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H) && (SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ + break; \ + case SW_S ## x ## 2: \ + xxx = (~SWITCHES_GPIO_REG_ ## x ## _H & SWITCHES_GPIO_PIN_ ## x ## _H); \ + if (IS_CONFIG_3POS(i)) { \ + xxx = xxx && (SWITCHES_GPIO_REG_ ## x ## _L & SWITCHES_GPIO_PIN_ ## x ## _L); \ + } \ + break + +uint8_t keyState(uint8_t index) +{ + return keys[index].state(); +} + +#if !defined(BOOT) +uint32_t switchState(uint8_t index) +{ + uint32_t xxx = 0; + + switch (index) { + ADD_3POS_CASE(A, 0); + ADD_3POS_CASE(B, 1); + ADD_3POS_CASE(C, 2); + ADD_3POS_CASE(D, 3); +#if defined(PCBX7) + ADD_2POS_CASE(F); + ADD_2POS_CASE(H); +#else + ADD_3POS_CASE(E, 4); + ADD_2POS_CASE(F); + ADD_3POS_CASE(G, 6); + ADD_2POS_CASE(H); +#endif +#if defined(PCBX9E) + ADD_3POS_CASE(I, 8); + ADD_3POS_CASE(J, 9); + ADD_3POS_CASE(K, 10); + ADD_3POS_CASE(L, 11); + ADD_3POS_CASE(M, 12); + ADD_3POS_CASE(N, 13); + ADD_3POS_CASE(O, 14); + ADD_3POS_CASE(P, 15); + ADD_3POS_CASE(Q, 16); + ADD_3POS_CASE(R, 17); +#endif + + default: + break; + } + + // TRACE("switch %d => %d", index, xxx); + return xxx; +} +#endif + +void keysInit() +{ + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + +#if defined(KEYS_GPIOA_PINS) + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOA_PINS; + GPIO_Init(GPIOA, &GPIO_InitStructure); +#endif + +#if defined(KEYS_GPIOB_PINS) + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOB_PINS; + GPIO_Init(GPIOB, &GPIO_InitStructure); +#endif + +#if defined(KEYS_GPIOC_PINS) + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOC_PINS; + GPIO_Init(GPIOC, &GPIO_InitStructure); +#endif + +#if defined(KEYS_GPIOD_PINS) + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOD_PINS; + GPIO_Init(GPIOD, &GPIO_InitStructure); +#endif + +#if defined(KEYS_GPIOE_PINS) + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOE_PINS; + GPIO_Init(GPIOE, &GPIO_InitStructure); +#endif + +#if defined(KEYS_GPIOF_PINS) + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOF_PINS; + GPIO_Init(GPIOF, &GPIO_InitStructure); +#endif + +#if defined(KEYS_GPIOG_PINS) + GPIO_InitStructure.GPIO_Pin = KEYS_GPIOG_PINS; + GPIO_Init(GPIOG, &GPIO_InitStructure); +#endif + +#if defined(ROTARY_ENCODER_NAVIGATION) + rotencPosition = ROTARY_ENCODER_POSITION(); +#endif +} diff --git a/radio/src/targets/taranis/lcd_driver_aspi.cpp b/radio/src/targets/taranis/lcd_driver_aspi.cpp index 5ec3a5a70..47e1b643a 100644 --- a/radio/src/targets/taranis/lcd_driver_aspi.cpp +++ b/radio/src/targets/taranis/lcd_driver_aspi.cpp @@ -1,301 +1,301 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#define CONTRAST_OFS 5 -#define RESET_WAIT_DELAY_MS 1300 // Wait time after LCD reset before first command - -bool lcdInitFinished = false; -void lcdInitFinish(); - -#define LCD_NCS_HIGH() LCD_NCS_GPIO->BSRRL = LCD_NCS_GPIO_PIN -#define LCD_NCS_LOW() LCD_NCS_GPIO->BSRRH = LCD_NCS_GPIO_PIN - -#define LCD_A0_HIGH() LCD_SPI_GPIO->BSRRL = LCD_A0_GPIO_PIN -#define LCD_A0_LOW() LCD_SPI_GPIO->BSRRH = LCD_A0_GPIO_PIN - -#define LCD_RST_HIGH() LCD_RST_GPIO->BSRRL = LCD_RST_GPIO_PIN -#define LCD_RST_LOW() LCD_RST_GPIO->BSRRH = LCD_RST_GPIO_PIN - -#define LCD_CLK_HIGH() LCD_SPI_GPIO->BSRRL = LCD_CLK_GPIO_PIN -#define LCD_CLK_LOW() LCD_SPI_GPIO->BSRRH = LCD_CLK_GPIO_PIN - -#define LCD_MOSI_HIGH() LCD_SPI_GPIO->BSRRL = LCD_MOSI_GPIO_PIN -#define LCD_MOSI_LOW() LCD_SPI_GPIO->BSRRH = LCD_MOSI_GPIO_PIN - -void lcdWriteCommand(uint8_t command) -{ - int i = 8; - LCD_A0_LOW(); - - LCD_CLK_HIGH(); - LCD_CLK_HIGH(); - LCD_NCS_LOW(); - - while (i--) { - LCD_CLK_LOW(); - - if (command & 0x80) - LCD_MOSI_HIGH(); - else - LCD_MOSI_LOW(); - - command <<= 1; - - LCD_CLK_LOW(); - LCD_CLK_LOW(); - - LCD_CLK_HIGH(); - LCD_CLK_HIGH(); - } - - LCD_NCS_HIGH(); - LCD_A0_HIGH(); -} - -void lcdWriteData(uint8_t data) -{ - int i = 8; - - LCD_CLK_HIGH(); - LCD_CLK_HIGH(); - LCD_A0_HIGH(); - LCD_NCS_LOW(); - - while (i--) { - LCD_CLK_LOW(); - if (data & 0x80) - LCD_MOSI_HIGH(); - else - LCD_MOSI_LOW(); - - data <<= 1; - - LCD_CLK_LOW(); - LCD_CLK_LOW(); - - LCD_CLK_HIGH(); - LCD_CLK_HIGH(); - } - - LCD_NCS_HIGH(); - LCD_A0_HIGH(); -} - -void lcdStart() -{ - lcdWriteCommand(0x2B); // Panel loading set, Internal VLCD. - delay_ms(20); - lcdWriteCommand(0x25); // Temperature compensation curve definition: 0x25 = -0.05%/oC - lcdWriteCommand(0xEA); // Set bias=1/10: Command table NO.27 - lcdWriteCommand(0x81); // Set Vop -#if defined(BOOT) - lcdWriteCommand(CONTRAST_OFS+25); -#else - lcdWriteCommand(CONTRAST_OFS+g_eeGeneral.contrast); -#endif - lcdWriteCommand(0xA6); // Inverse display off - lcdWriteCommand(0xD1); // Set RGB: Command table NO.21, D1=RGB - lcdWriteCommand(0xD5); // Set color mode 4K and 12bits: Command table NO.22 - lcdWriteCommand(0xA0); // Line rates, 25.2 Klps - lcdWriteCommand(0xC8); // Set N-LINE inversion - lcdWriteCommand(0x1D); // Disable NIV - lcdWriteCommand(0xF1); // Set CEN - lcdWriteCommand(0x3F); // 1/64 DUTY - lcdWriteCommand(0x84); // Disable Partial Display - lcdWriteCommand(0xC4); // MY=1, MX=0 - lcdWriteCommand(0x89); // WA=1, column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+1) - - lcdWriteCommand(0xF8); // Set Window Program Enable, inside modle - lcdWriteCommand(0xF4); // Start column address of RAM program window. - lcdWriteCommand(0x00); - lcdWriteCommand(0xF5); // Start row address of RAM program window. - lcdWriteCommand(0x60); - lcdWriteCommand(0xF6); // End column address of RAM program window. - lcdWriteCommand(0x47); - lcdWriteCommand(0xF7); // End row address of RAM program window. - lcdWriteCommand(0x9F); -} - -void lcdWriteAddress(uint8_t x, uint8_t y) -{ - lcdWriteCommand(x&0x0F); // Set Column Address LSB CA[3:0] - lcdWriteCommand((x>>4) | 0x10); // Set Column Address MSB CA[7:4] - - lcdWriteCommand((y&0x0F) | 0x60); // Set Row Address LSB RA [3:0] - lcdWriteCommand(((y>>4) & 0x0F) | 0x70); // Set Row Address MSB RA [7:4] -} - -#define LCD_WRITE_BIT(bit) \ - if (bit) \ - LCD_MOSI_HIGH(); \ - else \ - LCD_MOSI_LOW(); \ - LCD_CLK_LOW(); \ - LCD_CLK_LOW(); \ - LCD_CLK_LOW(); \ - LCD_CLK_HIGH(); \ - LCD_CLK_HIGH(); - -void lcdRefresh() -{ - if (!lcdInitFinished) { - lcdInitFinish(); - } - - for (uint8_t y=0; y>= 4; - LCD_WRITE_BIT(b & 0x08); - LCD_WRITE_BIT(b & 0x04); - LCD_WRITE_BIT(b & 0x02); - LCD_WRITE_BIT(b & 0x01); - } - - LCD_NCS_HIGH(); - LCD_A0_HIGH(); - - lcdWriteData(0); - } -} - -void lcdHardwareInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - - // Configure CLK, MOSI and A0 pins in output push-pull mode - GPIO_InitStructure.GPIO_Pin = LCD_MOSI_GPIO_PIN | LCD_CLK_GPIO_PIN | LCD_A0_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); - - LCD_NCS_HIGH(); - - // Configure NCS pin in output push-pull mode with PULLUP - GPIO_InitStructure.GPIO_Pin = LCD_NCS_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(LCD_NCS_GPIO, &GPIO_InitStructure); - - // Configure RST pin in output push-pull mode with PULLUP - GPIO_InitStructure.GPIO_Pin = LCD_RST_GPIO_PIN; - GPIO_Init(LCD_RST_GPIO, &GPIO_InitStructure); -} - -/* - Proper method for turning of LCD module. It must be used, - otherwise we might damage LCD crystals in the long run! -*/ -void lcdOff() -{ - /* - LCD Sleep mode is also good for draining capacitors and enables us - to re-init LCD without any delay - */ - lcdWriteCommand(0xAE); //LCD sleep - delay_ms(3); //wait for caps to drain -} - -void lcdReset() -{ - LCD_RST_LOW(); - delay_ms(1); // only 3 us needed according to data-sheet, we use 1 ms - LCD_RST_HIGH(); -} - -/* - Starts LCD initialization routine. It should be called as - soon as possible after the reset because LCD takes a lot of - time to properly power-on. - - Make sure that delay_ms() is functional before calling this function! -*/ -void lcdInit() -{ - lcdHardwareInit(); - - if (!WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { - lcdReset(); - } -} - -/* - Finishes LCD initialization. It is called auto-magically when first LCD command is - issued by the other parts of the code. -*/ -void lcdInitFinish() -{ - lcdInitFinished = true; - - /* - LCD needs longer time to initialize in low temperatures. The data-sheet - mentions a time of at least 150 ms. The delay of 1300 ms was obtained - experimentally. It was tested down to -10 deg Celsius. - - The longer initialization time seems to only be needed for regular Taranis, - the Taranis Plus (9XE) has been tested to work without any problems at -18 deg Celsius. - Therefore the delay for T+ is lower. - - If radio is reset by watchdog or boot-loader the wait is skipped, but the LCD - is initialized in any case. - - This initialization is needed in case the user moved power switch to OFF and - then immediately to ON position, because lcdOff() was called. In any case the LCD - initialization (without reset) is also recommended by the data sheet. - */ - - if (!WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { -#if !defined(BOOT) - while (g_tmr10ms < (RESET_WAIT_DELAY_MS/10)); // Wait measured from the power-on -#else - delay_ms(RESET_WAIT_DELAY_MS); -#endif - } - - lcdStart(); - lcdWriteCommand(0xAF); // dc2=1, IC into exit SLEEP MODE, dc3=1 gray=ON, dc4=1 Green Enhanc mode disabled - delay_ms(20); // Needed for internal DC-DC converter startup -} - -void lcdSetRefVolt(uint8_t val) -{ - if (!lcdInitFinished) { - lcdInitFinish(); - } - - lcdWriteCommand(0x81); // Set Vop - lcdWriteCommand(val+CONTRAST_OFS); // 0-255 -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#define CONTRAST_OFS 5 +#define RESET_WAIT_DELAY_MS 1300 // Wait time after LCD reset before first command + +bool lcdInitFinished = false; +void lcdInitFinish(); + +#define LCD_NCS_HIGH() LCD_NCS_GPIO->BSRRL = LCD_NCS_GPIO_PIN +#define LCD_NCS_LOW() LCD_NCS_GPIO->BSRRH = LCD_NCS_GPIO_PIN + +#define LCD_A0_HIGH() LCD_SPI_GPIO->BSRRL = LCD_A0_GPIO_PIN +#define LCD_A0_LOW() LCD_SPI_GPIO->BSRRH = LCD_A0_GPIO_PIN + +#define LCD_RST_HIGH() LCD_RST_GPIO->BSRRL = LCD_RST_GPIO_PIN +#define LCD_RST_LOW() LCD_RST_GPIO->BSRRH = LCD_RST_GPIO_PIN + +#define LCD_CLK_HIGH() LCD_SPI_GPIO->BSRRL = LCD_CLK_GPIO_PIN +#define LCD_CLK_LOW() LCD_SPI_GPIO->BSRRH = LCD_CLK_GPIO_PIN + +#define LCD_MOSI_HIGH() LCD_SPI_GPIO->BSRRL = LCD_MOSI_GPIO_PIN +#define LCD_MOSI_LOW() LCD_SPI_GPIO->BSRRH = LCD_MOSI_GPIO_PIN + +void lcdWriteCommand(uint8_t command) +{ + int i = 8; + LCD_A0_LOW(); + + LCD_CLK_HIGH(); + LCD_CLK_HIGH(); + LCD_NCS_LOW(); + + while (i--) { + LCD_CLK_LOW(); + + if (command & 0x80) + LCD_MOSI_HIGH(); + else + LCD_MOSI_LOW(); + + command <<= 1; + + LCD_CLK_LOW(); + LCD_CLK_LOW(); + + LCD_CLK_HIGH(); + LCD_CLK_HIGH(); + } + + LCD_NCS_HIGH(); + LCD_A0_HIGH(); +} + +void lcdWriteData(uint8_t data) +{ + int i = 8; + + LCD_CLK_HIGH(); + LCD_CLK_HIGH(); + LCD_A0_HIGH(); + LCD_NCS_LOW(); + + while (i--) { + LCD_CLK_LOW(); + if (data & 0x80) + LCD_MOSI_HIGH(); + else + LCD_MOSI_LOW(); + + data <<= 1; + + LCD_CLK_LOW(); + LCD_CLK_LOW(); + + LCD_CLK_HIGH(); + LCD_CLK_HIGH(); + } + + LCD_NCS_HIGH(); + LCD_A0_HIGH(); +} + +void lcdStart() +{ + lcdWriteCommand(0x2B); // Panel loading set, Internal VLCD. + delay_ms(20); + lcdWriteCommand(0x25); // Temperature compensation curve definition: 0x25 = -0.05%/oC + lcdWriteCommand(0xEA); // Set bias=1/10: Command table NO.27 + lcdWriteCommand(0x81); // Set Vop +#if defined(BOOT) + lcdWriteCommand(CONTRAST_OFS+25); +#else + lcdWriteCommand(CONTRAST_OFS+g_eeGeneral.contrast); +#endif + lcdWriteCommand(0xA6); // Inverse display off + lcdWriteCommand(0xD1); // Set RGB: Command table NO.21, D1=RGB + lcdWriteCommand(0xD5); // Set color mode 4K and 12bits: Command table NO.22 + lcdWriteCommand(0xA0); // Line rates, 25.2 Klps + lcdWriteCommand(0xC8); // Set N-LINE inversion + lcdWriteCommand(0x1D); // Disable NIV + lcdWriteCommand(0xF1); // Set CEN + lcdWriteCommand(0x3F); // 1/64 DUTY + lcdWriteCommand(0x84); // Disable Partial Display + lcdWriteCommand(0xC4); // MY=1, MX=0 + lcdWriteCommand(0x89); // WA=1, column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+1) + + lcdWriteCommand(0xF8); // Set Window Program Enable, inside modle + lcdWriteCommand(0xF4); // Start column address of RAM program window. + lcdWriteCommand(0x00); + lcdWriteCommand(0xF5); // Start row address of RAM program window. + lcdWriteCommand(0x60); + lcdWriteCommand(0xF6); // End column address of RAM program window. + lcdWriteCommand(0x47); + lcdWriteCommand(0xF7); // End row address of RAM program window. + lcdWriteCommand(0x9F); +} + +void lcdWriteAddress(uint8_t x, uint8_t y) +{ + lcdWriteCommand(x&0x0F); // Set Column Address LSB CA[3:0] + lcdWriteCommand((x>>4) | 0x10); // Set Column Address MSB CA[7:4] + + lcdWriteCommand((y&0x0F) | 0x60); // Set Row Address LSB RA [3:0] + lcdWriteCommand(((y>>4) & 0x0F) | 0x70); // Set Row Address MSB RA [7:4] +} + +#define LCD_WRITE_BIT(bit) \ + if (bit) \ + LCD_MOSI_HIGH(); \ + else \ + LCD_MOSI_LOW(); \ + LCD_CLK_LOW(); \ + LCD_CLK_LOW(); \ + LCD_CLK_LOW(); \ + LCD_CLK_HIGH(); \ + LCD_CLK_HIGH(); + +void lcdRefresh() +{ + if (!lcdInitFinished) { + lcdInitFinish(); + } + + for (uint8_t y=0; y>= 4; + LCD_WRITE_BIT(b & 0x08); + LCD_WRITE_BIT(b & 0x04); + LCD_WRITE_BIT(b & 0x02); + LCD_WRITE_BIT(b & 0x01); + } + + LCD_NCS_HIGH(); + LCD_A0_HIGH(); + + lcdWriteData(0); + } +} + +void lcdHardwareInit() +{ + GPIO_InitTypeDef GPIO_InitStructure; + + // Configure CLK, MOSI and A0 pins in output push-pull mode + GPIO_InitStructure.GPIO_Pin = LCD_MOSI_GPIO_PIN | LCD_CLK_GPIO_PIN | LCD_A0_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); + + LCD_NCS_HIGH(); + + // Configure NCS pin in output push-pull mode with PULLUP + GPIO_InitStructure.GPIO_Pin = LCD_NCS_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(LCD_NCS_GPIO, &GPIO_InitStructure); + + // Configure RST pin in output push-pull mode with PULLUP + GPIO_InitStructure.GPIO_Pin = LCD_RST_GPIO_PIN; + GPIO_Init(LCD_RST_GPIO, &GPIO_InitStructure); +} + +/* + Proper method for turning of LCD module. It must be used, + otherwise we might damage LCD crystals in the long run! +*/ +void lcdOff() +{ + /* + LCD Sleep mode is also good for draining capacitors and enables us + to re-init LCD without any delay + */ + lcdWriteCommand(0xAE); //LCD sleep + delay_ms(3); //wait for caps to drain +} + +void lcdReset() +{ + LCD_RST_LOW(); + delay_ms(1); // only 3 us needed according to data-sheet, we use 1 ms + LCD_RST_HIGH(); +} + +/* + Starts LCD initialization routine. It should be called as + soon as possible after the reset because LCD takes a lot of + time to properly power-on. + + Make sure that delay_ms() is functional before calling this function! +*/ +void lcdInit() +{ + lcdHardwareInit(); + + if (!WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { + lcdReset(); + } +} + +/* + Finishes LCD initialization. It is called auto-magically when first LCD command is + issued by the other parts of the code. +*/ +void lcdInitFinish() +{ + lcdInitFinished = true; + + /* + LCD needs longer time to initialize in low temperatures. The data-sheet + mentions a time of at least 150 ms. The delay of 1300 ms was obtained + experimentally. It was tested down to -10 deg Celsius. + + The longer initialization time seems to only be needed for regular Taranis, + the Taranis Plus (9XE) has been tested to work without any problems at -18 deg Celsius. + Therefore the delay for T+ is lower. + + If radio is reset by watchdog or boot-loader the wait is skipped, but the LCD + is initialized in any case. + + This initialization is needed in case the user moved power switch to OFF and + then immediately to ON position, because lcdOff() was called. In any case the LCD + initialization (without reset) is also recommended by the data sheet. + */ + + if (!WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { +#if !defined(BOOT) + while (g_tmr10ms < (RESET_WAIT_DELAY_MS/10)); // Wait measured from the power-on +#else + delay_ms(RESET_WAIT_DELAY_MS); +#endif + } + + lcdStart(); + lcdWriteCommand(0xAF); // dc2=1, IC into exit SLEEP MODE, dc3=1 gray=ON, dc4=1 Green Enhanc mode disabled + delay_ms(20); // Needed for internal DC-DC converter startup +} + +void lcdSetRefVolt(uint8_t val) +{ + if (!lcdInitFinished) { + lcdInitFinish(); + } + + lcdWriteCommand(0x81); // Set Vop + lcdWriteCommand(val+CONTRAST_OFS); // 0-255 +} diff --git a/radio/src/targets/taranis/lcd_driver_spi.cpp b/radio/src/targets/taranis/lcd_driver_spi.cpp index 7a8f27a7d..8f9e118f3 100644 --- a/radio/src/targets/taranis/lcd_driver_spi.cpp +++ b/radio/src/targets/taranis/lcd_driver_spi.cpp @@ -1,337 +1,337 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#define LCD_CONTRAST_OFFSET 160 -#define RESET_WAIT_DELAY_MS 300 // Wait time after LCD reset before first command -#define WAIT_FOR_DMA_END() do { } while (lcd_busy) - -#define LCD_NCS_HIGH() LCD_NCS_GPIO->BSRRL = LCD_NCS_GPIO_PIN -#define LCD_NCS_LOW() LCD_NCS_GPIO->BSRRH = LCD_NCS_GPIO_PIN - -#define LCD_A0_HIGH() LCD_SPI_GPIO->BSRRL = LCD_A0_GPIO_PIN -#define LCD_A0_LOW() LCD_SPI_GPIO->BSRRH = LCD_A0_GPIO_PIN - -#define LCD_RST_HIGH() LCD_RST_GPIO->BSRRL = LCD_RST_GPIO_PIN -#define LCD_RST_LOW() LCD_RST_GPIO->BSRRH = LCD_RST_GPIO_PIN - -bool lcdInitFinished = false; -void lcdInitFinish(); - -void lcdWriteCommand(uint8_t byte) -{ - LCD_A0_LOW(); - LCD_NCS_LOW(); - while ((SPI3->SR & SPI_SR_TXE) == 0) { - // Wait - } - (void)SPI3->DR; // Clear receive - LCD_SPI->DR = byte; - while ((SPI3->SR & SPI_SR_RXNE) == 0) { - // Wait - } - LCD_NCS_HIGH(); -} - -void lcdHardwareInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - - // APB1 clock / 2 = 133nS per clock - LCD_SPI->CR1 = 0; // Clear any mode error - LCD_SPI->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_CPOL | SPI_CR1_CPHA; - LCD_SPI->CR2 = 0; - LCD_SPI->CR1 |= SPI_CR1_MSTR; // Make sure in case SSM/SSI needed to be set first - LCD_SPI->CR1 |= SPI_CR1_SPE; - - LCD_NCS_HIGH(); - - GPIO_InitStructure.GPIO_Pin = LCD_NCS_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(LCD_NCS_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_RST_GPIO_PIN; - GPIO_Init(LCD_RST_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_A0_GPIO_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_CLK_GPIO_PIN | LCD_MOSI_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); - - GPIO_PinAFConfig(LCD_SPI_GPIO, LCD_MOSI_GPIO_PinSource, LCD_GPIO_AF); - GPIO_PinAFConfig(LCD_SPI_GPIO, LCD_CLK_GPIO_PinSource, LCD_GPIO_AF); - - LDC_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA - LCD_DMA->HIFCR = LCD_DMA_FLAGS; // Write ones to clear bits - LDC_DMA_Stream->CR = DMA_SxCR_PL_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0; - LDC_DMA_Stream->PAR = (uint32_t)&LCD_SPI->DR; -#if defined(PCBX7) - LDC_DMA_Stream->NDTR = LCD_W; -#else - LDC_DMA_Stream->M0AR = (uint32_t)displayBuf; - LDC_DMA_Stream->NDTR = LCD_W*LCD_H/8*4; -#endif - LDC_DMA_Stream->FCR = 0x05; // DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0; - - NVIC_EnableIRQ(LCD_DMA_Stream_IRQn); -} - -#if defined(PCBX7) -void lcdStart() -{ - lcdWriteCommand(0xe2); // (14) Soft reset - lcdWriteCommand(0xa1); // Set seg - lcdWriteCommand(0xc0); // Set com - lcdWriteCommand(0xf8); // Set booster - lcdWriteCommand(0x00); // 5x - lcdWriteCommand(0xa3); // Set bias=1/6 - lcdWriteCommand(0x22); // Set internal rb/ra=5.0 - lcdWriteCommand(0x2f); // All built-in power circuits on - lcdWriteCommand(0x81); // Set contrast - lcdWriteCommand(0x36); // Set Vop - lcdWriteCommand(0xa6); // Set display mode -} -#else -void lcdStart() -{ - lcdWriteCommand(0x2F); // Internal pump control - delay_ms(20); - lcdWriteCommand(0x24); // Temperature compensation - lcdWriteCommand(0xE9); // Set bias=1/10 - lcdWriteCommand(0x81); // Set Vop -#if defined(BOOT) - lcdWriteCommand(LCD_CONTRAST_OFFSET+LCD_CONTRAST_DEFAULT); -#else - lcdWriteCommand(LCD_CONTRAST_OFFSET+g_eeGeneral.contrast); -#endif - lcdWriteCommand(0xA2); // Set line rate: 28KLPS - lcdWriteCommand(0x28); // Set panel loading - lcdWriteCommand(0x40); // Scroll line LSB - lcdWriteCommand(0x50); // Scroll line MSB - lcdWriteCommand(0x89); // RAM address control - lcdWriteCommand(0xC0); // LCD mapping control - lcdWriteCommand(0x04); // MX=0, MY=1 - lcdWriteCommand(0xD0); // Display pattern = 16-SCALE GRAY - lcdWriteCommand(0xF1); // Set COM end - lcdWriteCommand(0x3F); // 64 - - lcdWriteCommand(0xF8); // Set Window Program Disable. - - lcdWriteCommand(0xF5); // Start row address of RAM program window. PAGE1 - lcdWriteCommand(0x00); - lcdWriteCommand(0xF7); // End row address of RAM program window. PAGE32 - lcdWriteCommand(0x1F); - lcdWriteCommand(0xF4); // Start column address of RAM program window. - lcdWriteCommand(0x00); - lcdWriteCommand(0xF6); // End column address of RAM program window. SEG212 - lcdWriteCommand(0xD3); -} - -void lcdWriteAddress(uint8_t x, uint8_t y) -{ - lcdWriteCommand(x & 0x0F); // Set Column Address LSB CA[3:0] - lcdWriteCommand((x>>4) | 0x10); // Set Column Address MSB CA[7:4] - - lcdWriteCommand((y&0x0F) | 0x60); // Set Row Address LSB RA [3:0] - lcdWriteCommand(((y>>4) & 0x0F) | 0x70); // Set Row Address MSB RA [7:4] -} -#endif - -volatile bool lcd_busy; - -#if !defined(LCD_DUAL_BUFFER) -void lcdRefreshWait() -{ - WAIT_FOR_DMA_END(); -} -#endif - -void lcdRefresh(bool wait) -{ - if (!lcdInitFinished) { - lcdInitFinish(); - } - -#if defined(PCBX7) - uint8_t * p = displayBuf; - for (uint8_t y=0; y < 8; y++, p+=LCD_W) { - lcdWriteCommand(0x10); // Column addr 0 - lcdWriteCommand(0xB0 | y); // Page addr y - lcdWriteCommand(0x04); - - LCD_NCS_LOW(); - LCD_A0_HIGH(); - - lcd_busy = true; - LDC_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA - LCD_DMA->HIFCR = LCD_DMA_FLAGS; // Write ones to clear bits - LDC_DMA_Stream->M0AR = (uint32_t)p; - LDC_DMA_Stream->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA & TC interrupts - LCD_SPI->CR2 |= SPI_CR2_TXDMAEN; - - WAIT_FOR_DMA_END(); - - LCD_NCS_HIGH(); - LCD_A0_HIGH(); - } -#else - // Wait if previous DMA transfer still active - WAIT_FOR_DMA_END(); - lcd_busy = true; - - lcdWriteAddress(0, 0); - - LCD_NCS_LOW(); - LCD_A0_HIGH(); - - LDC_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA - LCD_DMA->HIFCR = LCD_DMA_FLAGS; // Write ones to clear bits - -#if defined(LCD_DUAL_BUFFER) - // Switch LCD buffer - LDC_DMA_Stream->M0AR = (uint32_t)displayBuf; - displayBuf = (displayBuf == displayBuf1) ? displayBuf2 : displayBuf1; -#endif - - LDC_DMA_Stream->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA & TC interrupts - LCD_SPI->CR2 |= SPI_CR2_TXDMAEN; -#endif -} - -extern "C" void LCD_DMA_Stream_IRQHandler() -{ - DEBUG_INTERRUPT(INT_LCD); - - LDC_DMA_Stream->CR &= ~DMA_SxCR_TCIE; // Stop interrupt - LCD_DMA->HIFCR |= LCD_DMA_FLAG_INT; // Clear interrupt flag - LCD_SPI->CR2 &= ~SPI_CR2_TXDMAEN; - LDC_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA - - while (LCD_SPI->SR & SPI_SR_BSY) { - /* Wait for SPI to finish sending data - The DMA TX End interrupt comes two bytes before the end of SPI transmission, - therefore we have to wait here. - */ - } - LCD_NCS_HIGH(); - lcd_busy = false; -} - -/* - Proper method for turning of LCD module. It must be used, - otherwise we might damage LCD crystals in the long run! -*/ -void lcdOff() -{ - WAIT_FOR_DMA_END(); - - /* - LCD Sleep mode is also good for draining capacitors and enables us - to re-init LCD without any delay - */ - lcdWriteCommand(0xAE); // LCD sleep - delay_ms(3); // Wait for caps to drain -} - -void lcdReset() -{ - LCD_RST_LOW(); -#if defined(PCBX7) - delay_ms(150); -#else - delay_ms(1); // Only 3 us needed according to data-sheet, we use 1 ms -#endif - LCD_RST_HIGH(); -} - -/* - Starts LCD initialization routine. It should be called as - soon as possible after the reset because LCD takes a lot of - time to properly power-on. - - Make sure that delay_ms() is functional before calling this function! -*/ -void lcdInit() -{ - lcdHardwareInit(); - - if (IS_LCD_RESET_NEEDED()) { - lcdReset(); - } -} - -/* - Finishes LCD initialization. It is called auto-magically when first LCD command is - issued by the other parts of the code. -*/ -void lcdInitFinish() -{ - lcdInitFinished = true; - - /* - LCD needs longer time to initialize in low temperatures. The data-sheet - mentions a time of at least 150 ms. The delay of 1300 ms was obtained - experimentally. It was tested down to -10 deg Celsius. - - The longer initialization time seems to only be needed for regular Taranis, - the Taranis Plus (9XE) has been tested to work without any problems at -18 deg Celsius. - Therefore the delay for T+ is lower. - - If radio is reset by watchdog or boot-loader the wait is skipped, but the LCD - is initialized in any case. - - This initialization is needed in case the user moved power switch to OFF and - then immediately to ON position, because lcdOff() was called. In any case the LCD - initialization (without reset) is also recommended by the data sheet. - */ - - if (!WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { -#if !defined(BOOT) - while (g_tmr10ms < (RESET_WAIT_DELAY_MS/10)); // wait measured from the power-on -#else - delay_ms(RESET_WAIT_DELAY_MS); -#endif - } - - lcdStart(); - lcdWriteCommand(0xAF); // dc2=1, IC into exit SLEEP MODE, dc3=1 gray=ON, dc4=1 Green Enhanc mode disabled - delay_ms(20); // needed for internal DC-DC converter startup -} - -void lcdSetRefVolt(uint8_t val) -{ - if (!lcdInitFinished) { - lcdInitFinish(); - } - -#if !defined(PCBX7) - WAIT_FOR_DMA_END(); -#endif - - lcdWriteCommand(0x81); // Set Vop - lcdWriteCommand(val+LCD_CONTRAST_OFFSET); // 0-255 -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#define LCD_CONTRAST_OFFSET 160 +#define RESET_WAIT_DELAY_MS 300 // Wait time after LCD reset before first command +#define WAIT_FOR_DMA_END() do { } while (lcd_busy) + +#define LCD_NCS_HIGH() LCD_NCS_GPIO->BSRRL = LCD_NCS_GPIO_PIN +#define LCD_NCS_LOW() LCD_NCS_GPIO->BSRRH = LCD_NCS_GPIO_PIN + +#define LCD_A0_HIGH() LCD_SPI_GPIO->BSRRL = LCD_A0_GPIO_PIN +#define LCD_A0_LOW() LCD_SPI_GPIO->BSRRH = LCD_A0_GPIO_PIN + +#define LCD_RST_HIGH() LCD_RST_GPIO->BSRRL = LCD_RST_GPIO_PIN +#define LCD_RST_LOW() LCD_RST_GPIO->BSRRH = LCD_RST_GPIO_PIN + +bool lcdInitFinished = false; +void lcdInitFinish(); + +void lcdWriteCommand(uint8_t byte) +{ + LCD_A0_LOW(); + LCD_NCS_LOW(); + while ((SPI3->SR & SPI_SR_TXE) == 0) { + // Wait + } + (void)SPI3->DR; // Clear receive + LCD_SPI->DR = byte; + while ((SPI3->SR & SPI_SR_RXNE) == 0) { + // Wait + } + LCD_NCS_HIGH(); +} + +void lcdHardwareInit() +{ + GPIO_InitTypeDef GPIO_InitStructure; + + // APB1 clock / 2 = 133nS per clock + LCD_SPI->CR1 = 0; // Clear any mode error + LCD_SPI->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_CPOL | SPI_CR1_CPHA; + LCD_SPI->CR2 = 0; + LCD_SPI->CR1 |= SPI_CR1_MSTR; // Make sure in case SSM/SSI needed to be set first + LCD_SPI->CR1 |= SPI_CR1_SPE; + + LCD_NCS_HIGH(); + + GPIO_InitStructure.GPIO_Pin = LCD_NCS_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(LCD_NCS_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = LCD_RST_GPIO_PIN; + GPIO_Init(LCD_RST_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = LCD_A0_GPIO_PIN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = LCD_CLK_GPIO_PIN | LCD_MOSI_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); + + GPIO_PinAFConfig(LCD_SPI_GPIO, LCD_MOSI_GPIO_PinSource, LCD_GPIO_AF); + GPIO_PinAFConfig(LCD_SPI_GPIO, LCD_CLK_GPIO_PinSource, LCD_GPIO_AF); + + LDC_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA + LCD_DMA->HIFCR = LCD_DMA_FLAGS; // Write ones to clear bits + LDC_DMA_Stream->CR = DMA_SxCR_PL_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0; + LDC_DMA_Stream->PAR = (uint32_t)&LCD_SPI->DR; +#if defined(PCBX7) + LDC_DMA_Stream->NDTR = LCD_W; +#else + LDC_DMA_Stream->M0AR = (uint32_t)displayBuf; + LDC_DMA_Stream->NDTR = LCD_W*LCD_H/8*4; +#endif + LDC_DMA_Stream->FCR = 0x05; // DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0; + + NVIC_EnableIRQ(LCD_DMA_Stream_IRQn); +} + +#if defined(PCBX7) +void lcdStart() +{ + lcdWriteCommand(0xe2); // (14) Soft reset + lcdWriteCommand(0xa1); // Set seg + lcdWriteCommand(0xc0); // Set com + lcdWriteCommand(0xf8); // Set booster + lcdWriteCommand(0x00); // 5x + lcdWriteCommand(0xa3); // Set bias=1/6 + lcdWriteCommand(0x22); // Set internal rb/ra=5.0 + lcdWriteCommand(0x2f); // All built-in power circuits on + lcdWriteCommand(0x81); // Set contrast + lcdWriteCommand(0x36); // Set Vop + lcdWriteCommand(0xa6); // Set display mode +} +#else +void lcdStart() +{ + lcdWriteCommand(0x2F); // Internal pump control + delay_ms(20); + lcdWriteCommand(0x24); // Temperature compensation + lcdWriteCommand(0xE9); // Set bias=1/10 + lcdWriteCommand(0x81); // Set Vop +#if defined(BOOT) + lcdWriteCommand(LCD_CONTRAST_OFFSET+LCD_CONTRAST_DEFAULT); +#else + lcdWriteCommand(LCD_CONTRAST_OFFSET+g_eeGeneral.contrast); +#endif + lcdWriteCommand(0xA2); // Set line rate: 28KLPS + lcdWriteCommand(0x28); // Set panel loading + lcdWriteCommand(0x40); // Scroll line LSB + lcdWriteCommand(0x50); // Scroll line MSB + lcdWriteCommand(0x89); // RAM address control + lcdWriteCommand(0xC0); // LCD mapping control + lcdWriteCommand(0x04); // MX=0, MY=1 + lcdWriteCommand(0xD0); // Display pattern = 16-SCALE GRAY + lcdWriteCommand(0xF1); // Set COM end + lcdWriteCommand(0x3F); // 64 + + lcdWriteCommand(0xF8); // Set Window Program Disable. + + lcdWriteCommand(0xF5); // Start row address of RAM program window. PAGE1 + lcdWriteCommand(0x00); + lcdWriteCommand(0xF7); // End row address of RAM program window. PAGE32 + lcdWriteCommand(0x1F); + lcdWriteCommand(0xF4); // Start column address of RAM program window. + lcdWriteCommand(0x00); + lcdWriteCommand(0xF6); // End column address of RAM program window. SEG212 + lcdWriteCommand(0xD3); +} + +void lcdWriteAddress(uint8_t x, uint8_t y) +{ + lcdWriteCommand(x & 0x0F); // Set Column Address LSB CA[3:0] + lcdWriteCommand((x>>4) | 0x10); // Set Column Address MSB CA[7:4] + + lcdWriteCommand((y&0x0F) | 0x60); // Set Row Address LSB RA [3:0] + lcdWriteCommand(((y>>4) & 0x0F) | 0x70); // Set Row Address MSB RA [7:4] +} +#endif + +volatile bool lcd_busy; + +#if !defined(LCD_DUAL_BUFFER) +void lcdRefreshWait() +{ + WAIT_FOR_DMA_END(); +} +#endif + +void lcdRefresh(bool wait) +{ + if (!lcdInitFinished) { + lcdInitFinish(); + } + +#if defined(PCBX7) + uint8_t * p = displayBuf; + for (uint8_t y=0; y < 8; y++, p+=LCD_W) { + lcdWriteCommand(0x10); // Column addr 0 + lcdWriteCommand(0xB0 | y); // Page addr y + lcdWriteCommand(0x04); + + LCD_NCS_LOW(); + LCD_A0_HIGH(); + + lcd_busy = true; + LDC_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA + LCD_DMA->HIFCR = LCD_DMA_FLAGS; // Write ones to clear bits + LDC_DMA_Stream->M0AR = (uint32_t)p; + LDC_DMA_Stream->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA & TC interrupts + LCD_SPI->CR2 |= SPI_CR2_TXDMAEN; + + WAIT_FOR_DMA_END(); + + LCD_NCS_HIGH(); + LCD_A0_HIGH(); + } +#else + // Wait if previous DMA transfer still active + WAIT_FOR_DMA_END(); + lcd_busy = true; + + lcdWriteAddress(0, 0); + + LCD_NCS_LOW(); + LCD_A0_HIGH(); + + LDC_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA + LCD_DMA->HIFCR = LCD_DMA_FLAGS; // Write ones to clear bits + +#if defined(LCD_DUAL_BUFFER) + // Switch LCD buffer + LDC_DMA_Stream->M0AR = (uint32_t)displayBuf; + displayBuf = (displayBuf == displayBuf1) ? displayBuf2 : displayBuf1; +#endif + + LDC_DMA_Stream->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA & TC interrupts + LCD_SPI->CR2 |= SPI_CR2_TXDMAEN; +#endif +} + +extern "C" void LCD_DMA_Stream_IRQHandler() +{ + DEBUG_INTERRUPT(INT_LCD); + + LDC_DMA_Stream->CR &= ~DMA_SxCR_TCIE; // Stop interrupt + LCD_DMA->HIFCR |= LCD_DMA_FLAG_INT; // Clear interrupt flag + LCD_SPI->CR2 &= ~SPI_CR2_TXDMAEN; + LDC_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA + + while (LCD_SPI->SR & SPI_SR_BSY) { + /* Wait for SPI to finish sending data + The DMA TX End interrupt comes two bytes before the end of SPI transmission, + therefore we have to wait here. + */ + } + LCD_NCS_HIGH(); + lcd_busy = false; +} + +/* + Proper method for turning of LCD module. It must be used, + otherwise we might damage LCD crystals in the long run! +*/ +void lcdOff() +{ + WAIT_FOR_DMA_END(); + + /* + LCD Sleep mode is also good for draining capacitors and enables us + to re-init LCD without any delay + */ + lcdWriteCommand(0xAE); // LCD sleep + delay_ms(3); // Wait for caps to drain +} + +void lcdReset() +{ + LCD_RST_LOW(); +#if defined(PCBX7) + delay_ms(150); +#else + delay_ms(1); // Only 3 us needed according to data-sheet, we use 1 ms +#endif + LCD_RST_HIGH(); +} + +/* + Starts LCD initialization routine. It should be called as + soon as possible after the reset because LCD takes a lot of + time to properly power-on. + + Make sure that delay_ms() is functional before calling this function! +*/ +void lcdInit() +{ + lcdHardwareInit(); + + if (IS_LCD_RESET_NEEDED()) { + lcdReset(); + } +} + +/* + Finishes LCD initialization. It is called auto-magically when first LCD command is + issued by the other parts of the code. +*/ +void lcdInitFinish() +{ + lcdInitFinished = true; + + /* + LCD needs longer time to initialize in low temperatures. The data-sheet + mentions a time of at least 150 ms. The delay of 1300 ms was obtained + experimentally. It was tested down to -10 deg Celsius. + + The longer initialization time seems to only be needed for regular Taranis, + the Taranis Plus (9XE) has been tested to work without any problems at -18 deg Celsius. + Therefore the delay for T+ is lower. + + If radio is reset by watchdog or boot-loader the wait is skipped, but the LCD + is initialized in any case. + + This initialization is needed in case the user moved power switch to OFF and + then immediately to ON position, because lcdOff() was called. In any case the LCD + initialization (without reset) is also recommended by the data sheet. + */ + + if (!WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { +#if !defined(BOOT) + while (g_tmr10ms < (RESET_WAIT_DELAY_MS/10)); // wait measured from the power-on +#else + delay_ms(RESET_WAIT_DELAY_MS); +#endif + } + + lcdStart(); + lcdWriteCommand(0xAF); // dc2=1, IC into exit SLEEP MODE, dc3=1 gray=ON, dc4=1 Green Enhanc mode disabled + delay_ms(20); // needed for internal DC-DC converter startup +} + +void lcdSetRefVolt(uint8_t val) +{ + if (!lcdInitFinished) { + lcdInitFinish(); + } + +#if !defined(PCBX7) + WAIT_FOR_DMA_END(); +#endif + + lcdWriteCommand(0x81); // Set Vop + lcdWriteCommand(val+LCD_CONTRAST_OFFSET); // 0-255 +} diff --git a/radio/src/targets/taranis/pulses_driver.cpp b/radio/src/targets/taranis/pulses_driver.cpp index 615aae09b..fcbc04909 100644 --- a/radio/src/targets/taranis/pulses_driver.cpp +++ b/radio/src/targets/taranis/pulses_driver.cpp @@ -1,292 +1,292 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void intmoduleStop(void); -void extmoduleStop(void); - -void intmoduleNoneStart(void); -void intmodulePxxStart(void); -#if defined(TARANIS_INTERNAL_PPM) -void intmodulePpmStart(void); -#endif - -void extmoduleNoneStart(void); -void extmodulePpmStart(void); -void extmodulePxxStart(void); -#if defined(DSM2) || defined(MULTIMODULE) -void extmoduleDsm2Start(void); -#endif -void extmoduleCrossfireStart(void); - -void intmoduleSendNextFrame(); - -void init_pxx(uint32_t port) -{ - if (port == INTERNAL_MODULE) - intmodulePxxStart(); - else - extmodulePxxStart(); -} - -void disable_pxx(uint32_t port) -{ - if (port == INTERNAL_MODULE) - intmoduleStop(); - else - extmoduleStop(); -} - -#if defined(DSM2) -void init_dsm2(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmoduleDsm2Start(); - } -} - -void disable_dsm2(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmoduleStop(); - } -} -#endif - -#if defined(MULTIMODULE) -void init_multimodule(uint32_t port) -{ - init_dsm2(port); -} - -void disable_multimodule(uint32_t port) -{ - disable_dsm2(port); -} -#endif - - -void init_ppm(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmodulePpmStart(); - } -#if defined(TARANIS_INTERNAL_PPM) - else if (port == INTERNAL_MODULE) { - intmodulePpmStart(); - } -#endif -} - -void disable_ppm(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmoduleStop(); - } -#if defined(TARANIS_INTERNAL_PPM) - else if (port == INTERNAL_MODULE) { - intmoduleStop(); - } -#endif -} - -void init_no_pulses(uint32_t port) -{ - if (port == INTERNAL_MODULE) - intmoduleNoneStart(); - else - extmoduleNoneStart(); -} - -void disable_no_pulses(uint32_t port) -{ - if (port == INTERNAL_MODULE) - intmoduleStop(); - else - extmoduleStop(); -} - -void init_crossfire(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmoduleCrossfireStart(); - } -} - -void disable_crossfire(uint32_t port) -{ - if (port == EXTERNAL_MODULE) { - extmoduleStop(); - } -} - -void intmoduleStop() -{ - INTERNAL_MODULE_OFF(); - - NVIC_DisableIRQ(INTMODULE_DMA_IRQn); - NVIC_DisableIRQ(INTMODULE_TIMER_CC_IRQn); - - INTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - INTMODULE_TIMER->DIER &= ~(TIM_DIER_CC2IE | TIM_DIER_UDE); - INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; -} - -void intmoduleNoneStart() -{ - INTERNAL_MODULE_OFF(); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = INTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(INTMODULE_PPM_GPIO, &GPIO_InitStructure); - GPIO_SetBits(INTMODULE_PPM_GPIO, INTMODULE_PPM_GPIO_PIN); // Set high - - INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz - INTMODULE_TIMER->ARR = 36000; // 18mS - INTMODULE_TIMER->CCR2 = 32000; // Update time - INTMODULE_TIMER->EGR = 1; // Restart - INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag - INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt - INTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - - NVIC_EnableIRQ(INTMODULE_TIMER_CC_IRQn); - NVIC_SetPriority(INTMODULE_TIMER_CC_IRQn, 7); -} - -void intmodulePxxStart() -{ - INTERNAL_MODULE_ON(); - - GPIO_PinAFConfig(INTMODULE_PPM_GPIO, INTMODULE_PPM_GPIO_PinSource, INTMODULE_PPM_GPIO_AF); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = INTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(INTMODULE_PPM_GPIO, &GPIO_InitStructure); - - INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) - INTMODULE_TIMER->ARR = 18000; - INTMODULE_TIMER->CCER = TIM_CCER_CC3E | TIM_CCER_CC3NE; - INTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs - INTMODULE_TIMER->CCR3 = 16; - INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0; // Force O/P high - INTMODULE_TIMER->EGR = 1; // Restart - INTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update - INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2; - INTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - - intmoduleSendNextFrame(); - - NVIC_EnableIRQ(INTMODULE_DMA_IRQn); - NVIC_SetPriority(INTMODULE_DMA_IRQn, 7); - NVIC_EnableIRQ(INTMODULE_TIMER_CC_IRQn); - NVIC_SetPriority(INTMODULE_TIMER_CC_IRQn, 7); -} - -#if defined(TARANIS_INTERNAL_PPM) -void intmodulePpmStart() -{ - INTERNAL_MODULE_ON(); - - GPIO_PinAFConfig(INTMODULE_PPM_GPIO, INTMODULE_PPM_GPIO_PinSource, INTMODULE_PPM_GPIO_AF); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = INTMODULE_PPM_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(INTMODULE_PPM_GPIO, &GPIO_InitStructure); - - INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz - INTMODULE_TIMER->ARR = 45000; - INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2; // PWM mode 1 - INTMODULE_TIMER->BDTR = TIM_BDTR_MOE; - INTMODULE_TIMER->EGR = 1; - INTMODULE_TIMER->DIER = TIM_DIER_UDE; - INTMODULE_TIMER->CR1 = TIM_CR1_CEN; - - intmoduleSendNextFrame(); - - NVIC_EnableIRQ(INTMODULE_DMA_IRQn); - NVIC_SetPriority(INTMODULE_DMA_IRQn, 7); - NVIC_EnableIRQ(INTMODULE_TIMER_CC_IRQn); - NVIC_SetPriority(INTMODULE_TIMER_CC_IRQn, 7); -} -#endif // defined(TARANIS_INTERNAL_PPM) - -void intmoduleSendNextFrame() -{ - if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) { - INTMODULE_TIMER->CCR2 = *(modulePulsesData[INTERNAL_MODULE].pxx.ptr - 1) - 4000; // 2mS in advance - INTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - INTMODULE_DMA_STREAM->CR |= INTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; - INTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&INTMODULE_TIMER->ARR); - INTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[INTERNAL_MODULE].pxx.pulses); - INTMODULE_DMA_STREAM->NDTR = modulePulsesData[INTERNAL_MODULE].pxx.ptr - modulePulsesData[INTERNAL_MODULE].pxx.pulses; - INTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA - } -#if defined(TARANIS_INTERNAL_PPM) - else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) { - INTMODULE_TIMER->CCR3 = GET_PPM_DELAY(INTERNAL_MODULE)*2; - INTMODULE_TIMER->CCER = TIM_CCER_CC3E | (GET_PPM_POLARITY(INTERNAL_MODULE) ? 0 : TIM_CCER_CC3P); - INTMODULE_TIMER->CCR2 = *(modulePulsesData[INTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance - INTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - INTMODULE_DMA_STREAM->CR |= INTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; - INTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&INTMODULE_TIMER->ARR); - INTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[INTERNAL_MODULE].ppm.pulses); - INTMODULE_DMA_STREAM->NDTR = modulePulsesData[INTERNAL_MODULE].ppm.ptr - modulePulsesData[INTERNAL_MODULE].ppm.pulses; - INTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA - } -#endif - else { - INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; - } -} - -extern "C" void INTMODULE_DMA_IRQHandler() -{ - if (!DMA_GetITStatus(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC)) - return; - - DMA_ClearITPendingBit(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC); - - INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag - INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt -} - -extern "C" void INTMODULE_TIMER_CC_IRQHandler() -{ - INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // Stop this interrupt - INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; - setupPulses(INTERNAL_MODULE); - intmoduleSendNextFrame(); -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +void intmoduleStop(void); +void extmoduleStop(void); + +void intmoduleNoneStart(void); +void intmodulePxxStart(void); +#if defined(TARANIS_INTERNAL_PPM) +void intmodulePpmStart(void); +#endif + +void extmoduleNoneStart(void); +void extmodulePpmStart(void); +void extmodulePxxStart(void); +#if defined(DSM2) || defined(MULTIMODULE) +void extmoduleDsm2Start(void); +#endif +void extmoduleCrossfireStart(void); + +void intmoduleSendNextFrame(); + +void init_pxx(uint32_t port) +{ + if (port == INTERNAL_MODULE) + intmodulePxxStart(); + else + extmodulePxxStart(); +} + +void disable_pxx(uint32_t port) +{ + if (port == INTERNAL_MODULE) + intmoduleStop(); + else + extmoduleStop(); +} + +#if defined(DSM2) +void init_dsm2(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmoduleDsm2Start(); + } +} + +void disable_dsm2(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmoduleStop(); + } +} +#endif + +#if defined(MULTIMODULE) +void init_multimodule(uint32_t port) +{ + init_dsm2(port); +} + +void disable_multimodule(uint32_t port) +{ + disable_dsm2(port); +} +#endif + + +void init_ppm(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmodulePpmStart(); + } +#if defined(TARANIS_INTERNAL_PPM) + else if (port == INTERNAL_MODULE) { + intmodulePpmStart(); + } +#endif +} + +void disable_ppm(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmoduleStop(); + } +#if defined(TARANIS_INTERNAL_PPM) + else if (port == INTERNAL_MODULE) { + intmoduleStop(); + } +#endif +} + +void init_no_pulses(uint32_t port) +{ + if (port == INTERNAL_MODULE) + intmoduleNoneStart(); + else + extmoduleNoneStart(); +} + +void disable_no_pulses(uint32_t port) +{ + if (port == INTERNAL_MODULE) + intmoduleStop(); + else + extmoduleStop(); +} + +void init_crossfire(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmoduleCrossfireStart(); + } +} + +void disable_crossfire(uint32_t port) +{ + if (port == EXTERNAL_MODULE) { + extmoduleStop(); + } +} + +void intmoduleStop() +{ + INTERNAL_MODULE_OFF(); + + NVIC_DisableIRQ(INTMODULE_DMA_IRQn); + NVIC_DisableIRQ(INTMODULE_TIMER_CC_IRQn); + + INTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + INTMODULE_TIMER->DIER &= ~(TIM_DIER_CC2IE | TIM_DIER_UDE); + INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; +} + +void intmoduleNoneStart() +{ + INTERNAL_MODULE_OFF(); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = INTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(INTMODULE_PPM_GPIO, &GPIO_InitStructure); + GPIO_SetBits(INTMODULE_PPM_GPIO, INTMODULE_PPM_GPIO_PIN); // Set high + + INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz + INTMODULE_TIMER->ARR = 36000; // 18mS + INTMODULE_TIMER->CCR2 = 32000; // Update time + INTMODULE_TIMER->EGR = 1; // Restart + INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag + INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt + INTMODULE_TIMER->CR1 |= TIM_CR1_CEN; + + NVIC_EnableIRQ(INTMODULE_TIMER_CC_IRQn); + NVIC_SetPriority(INTMODULE_TIMER_CC_IRQn, 7); +} + +void intmodulePxxStart() +{ + INTERNAL_MODULE_ON(); + + GPIO_PinAFConfig(INTMODULE_PPM_GPIO, INTMODULE_PPM_GPIO_PinSource, INTMODULE_PPM_GPIO_AF); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = INTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(INTMODULE_PPM_GPIO, &GPIO_InitStructure); + + INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) + INTMODULE_TIMER->ARR = 18000; + INTMODULE_TIMER->CCER = TIM_CCER_CC3E | TIM_CCER_CC3NE; + INTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs + INTMODULE_TIMER->CCR3 = 16; + INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0; // Force O/P high + INTMODULE_TIMER->EGR = 1; // Restart + INTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update + INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2; + INTMODULE_TIMER->CR1 |= TIM_CR1_CEN; + + intmoduleSendNextFrame(); + + NVIC_EnableIRQ(INTMODULE_DMA_IRQn); + NVIC_SetPriority(INTMODULE_DMA_IRQn, 7); + NVIC_EnableIRQ(INTMODULE_TIMER_CC_IRQn); + NVIC_SetPriority(INTMODULE_TIMER_CC_IRQn, 7); +} + +#if defined(TARANIS_INTERNAL_PPM) +void intmodulePpmStart() +{ + INTERNAL_MODULE_ON(); + + GPIO_PinAFConfig(INTMODULE_PPM_GPIO, INTMODULE_PPM_GPIO_PinSource, INTMODULE_PPM_GPIO_AF); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = INTMODULE_PPM_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(INTMODULE_PPM_GPIO, &GPIO_InitStructure); + + INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; + INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS from 30MHz + INTMODULE_TIMER->ARR = 45000; + INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2; // PWM mode 1 + INTMODULE_TIMER->BDTR = TIM_BDTR_MOE; + INTMODULE_TIMER->EGR = 1; + INTMODULE_TIMER->DIER = TIM_DIER_UDE; + INTMODULE_TIMER->CR1 = TIM_CR1_CEN; + + intmoduleSendNextFrame(); + + NVIC_EnableIRQ(INTMODULE_DMA_IRQn); + NVIC_SetPriority(INTMODULE_DMA_IRQn, 7); + NVIC_EnableIRQ(INTMODULE_TIMER_CC_IRQn); + NVIC_SetPriority(INTMODULE_TIMER_CC_IRQn, 7); +} +#endif // defined(TARANIS_INTERNAL_PPM) + +void intmoduleSendNextFrame() +{ + if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) { + INTMODULE_TIMER->CCR2 = *(modulePulsesData[INTERNAL_MODULE].pxx.ptr - 1) - 4000; // 2mS in advance + INTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + INTMODULE_DMA_STREAM->CR |= INTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; + INTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&INTMODULE_TIMER->ARR); + INTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[INTERNAL_MODULE].pxx.pulses); + INTMODULE_DMA_STREAM->NDTR = modulePulsesData[INTERNAL_MODULE].pxx.ptr - modulePulsesData[INTERNAL_MODULE].pxx.pulses; + INTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA + } +#if defined(TARANIS_INTERNAL_PPM) + else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) { + INTMODULE_TIMER->CCR3 = GET_PPM_DELAY(INTERNAL_MODULE)*2; + INTMODULE_TIMER->CCER = TIM_CCER_CC3E | (GET_PPM_POLARITY(INTERNAL_MODULE) ? 0 : TIM_CCER_CC3P); + INTMODULE_TIMER->CCR2 = *(modulePulsesData[INTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance + INTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + INTMODULE_DMA_STREAM->CR |= INTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; + INTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&INTMODULE_TIMER->ARR); + INTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[INTERNAL_MODULE].ppm.pulses); + INTMODULE_DMA_STREAM->NDTR = modulePulsesData[INTERNAL_MODULE].ppm.ptr - modulePulsesData[INTERNAL_MODULE].ppm.pulses; + INTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA + } +#endif + else { + INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; + } +} + +extern "C" void INTMODULE_DMA_IRQHandler() +{ + if (!DMA_GetITStatus(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC)) + return; + + DMA_ClearITPendingBit(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC); + + INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag + INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt +} + +extern "C" void INTMODULE_TIMER_CC_IRQHandler() +{ + INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // Stop this interrupt + INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; + setupPulses(INTERNAL_MODULE); + intmoduleSendNextFrame(); +} diff --git a/radio/src/targets/taranis/pwr_driver.cpp b/radio/src/targets/taranis/pwr_driver.cpp index 10ad32558..8da5a4ff5 100644 --- a/radio/src/targets/taranis/pwr_driver.cpp +++ b/radio/src/targets/taranis/pwr_driver.cpp @@ -1,99 +1,99 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void pwrInit() -{ - // if any changes are done to the PWR PIN or pwrOn() function - // then the same changes must be done in _bootStart() - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = PWR_ON_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(PWR_GPIO, &GPIO_InitStructure); - - GPIO_ResetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN); - GPIO_InitStructure.GPIO_Pin = INTMODULE_PWR_GPIO_PIN; - GPIO_Init(INTMODULE_PWR_GPIO, &GPIO_InitStructure); - - GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN); - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PWR_GPIO_PIN; - GPIO_Init(EXTMODULE_PWR_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = PWR_SWITCH_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_Init(PWR_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = TRAINER_DETECT_GPIO_PIN; - GPIO_Init(TRAINER_DETECT_GPIO, &GPIO_InitStructure); - -#if defined(PCBX7) - // Init PCBREV PIN - GPIO_ResetBits(PCBREV_GPIO, PCBREV_GPIO_PIN); - GPIO_InitStructure.GPIO_Pin = PCBREV_GPIO_PIN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; - GPIO_Init(PCBREV_GPIO, &GPIO_InitStructure); -#endif - - pwrOn(); -} - -void pwrOn() -{ - GPIO_SetBits(PWR_GPIO, PWR_ON_GPIO_PIN); -} - -void pwrOff() -{ - GPIO_ResetBits(PWR_GPIO, PWR_ON_GPIO_PIN); - - // disable interrupts - __disable_irq(); - - while (1) { - wdt_reset(); -#if defined(PWR_PRESS_BUTTON) - // X9E/X7 needs watchdog reset because CPU is still running while - // the power key is held pressed by the user. - // The power key should be released by now, but we must make sure - if (!pwrPressed()) { - // Put the CPU into sleep to reduce the consumption, - // it might help with the RTC reset issue - PWR->CR |= PWR_CR_CWUF; - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - /* Request Wait For Event */ - __WFE(); - } -#endif - } - // this function must not return! -} - -uint32_t pwrPressed() -{ - return GPIO_ReadInputDataBit(PWR_GPIO, PWR_SWITCH_GPIO_PIN) == Bit_RESET; -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +void pwrInit() +{ + // if any changes are done to the PWR PIN or pwrOn() function + // then the same changes must be done in _bootStart() + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = PWR_ON_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(PWR_GPIO, &GPIO_InitStructure); + + GPIO_ResetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN); + GPIO_InitStructure.GPIO_Pin = INTMODULE_PWR_GPIO_PIN; + GPIO_Init(INTMODULE_PWR_GPIO, &GPIO_InitStructure); + + GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN); + GPIO_InitStructure.GPIO_Pin = EXTMODULE_PWR_GPIO_PIN; + GPIO_Init(EXTMODULE_PWR_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = PWR_SWITCH_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_Init(PWR_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = TRAINER_DETECT_GPIO_PIN; + GPIO_Init(TRAINER_DETECT_GPIO, &GPIO_InitStructure); + +#if defined(PCBX7) + // Init PCBREV PIN + GPIO_ResetBits(PCBREV_GPIO, PCBREV_GPIO_PIN); + GPIO_InitStructure.GPIO_Pin = PCBREV_GPIO_PIN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; + GPIO_Init(PCBREV_GPIO, &GPIO_InitStructure); +#endif + + pwrOn(); +} + +void pwrOn() +{ + GPIO_SetBits(PWR_GPIO, PWR_ON_GPIO_PIN); +} + +void pwrOff() +{ + GPIO_ResetBits(PWR_GPIO, PWR_ON_GPIO_PIN); + + // disable interrupts + __disable_irq(); + + while (1) { + wdt_reset(); +#if defined(PWR_PRESS_BUTTON) + // X9E/X7 needs watchdog reset because CPU is still running while + // the power key is held pressed by the user. + // The power key should be released by now, but we must make sure + if (!pwrPressed()) { + // Put the CPU into sleep to reduce the consumption, + // it might help with the RTC reset issue + PWR->CR |= PWR_CR_CWUF; + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + /* Request Wait For Event */ + __WFE(); + } +#endif + } + // this function must not return! +} + +uint32_t pwrPressed() +{ + return GPIO_ReadInputDataBit(PWR_GPIO, PWR_SWITCH_GPIO_PIN) == Bit_RESET; +} diff --git a/radio/src/targets/taranis/startup_stm32f40_41xxx.s b/radio/src/targets/taranis/startup_stm32f40_41xxx.s index 4fb8604f7..25fd9cf8c 100644 --- a/radio/src/targets/taranis/startup_stm32f40_41xxx.s +++ b/radio/src/targets/taranis/startup_stm32f40_41xxx.s @@ -1,527 +1,527 @@ -/** - ****************************************************************************** - * @file startup_stm32f40_41xxx.s - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief STM32F40xxx/41xxx Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM324xG-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/*Paint Main Stack */ - ldr r2, = _main_stack_start -PaintMainStack: - movs r3, #0x55555555 - str r3, [r2], #4 -LoopPaintMainStack: - ldr r3, = _estack - cmp r2, r3 - bcc PaintMainStack - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call C++ constructors for static objects */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word CRYP_IRQHandler /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CRYP_IRQHandler - .thumb_set CRYP_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file startup_stm32f40_41xxx.s + * @author MCD Application Team + * @version V1.3.0 + * @date 08-November-2013 + * @brief STM32F40xxx/41xxx Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM324xG-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2013 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/*Paint Main Stack */ + ldr r2, = _main_stack_start +PaintMainStack: + movs r3, #0x55555555 + str r3, [r2], #4 +LoopPaintMainStack: + ldr r3, = _estack + cmp r2, r3 + bcc PaintMainStack + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call C++ constructors for static objects */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/targets/taranis/telemetry_driver.cpp b/radio/src/targets/taranis/telemetry_driver.cpp index b40465a98..d91cad3b9 100644 --- a/radio/src/targets/taranis/telemetry_driver.cpp +++ b/radio/src/targets/taranis/telemetry_driver.cpp @@ -1,188 +1,188 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -Fifo telemetryFifo; -uint32_t telemetryErrors = 0; - -void telemetryPortInit(uint32_t baudrate, uint8_t mode) -{ - if (baudrate == 0) { - USART_DeInit(TELEMETRY_USART); - return; - } - - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = TELEMETRY_DMA_TX_Stream_IRQ; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pre-emption priority. */; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - USART_InitTypeDef USART_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - GPIO_PinAFConfig(TELEMETRY_GPIO, TELEMETRY_GPIO_PinSource_RX, TELEMETRY_GPIO_AF); - GPIO_PinAFConfig(TELEMETRY_GPIO, TELEMETRY_GPIO_PinSource_TX, TELEMETRY_GPIO_AF); - - GPIO_InitStructure.GPIO_Pin = TELEMETRY_TX_GPIO_PIN | TELEMETRY_RX_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_Init(TELEMETRY_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = TELEMETRY_DIR_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(TELEMETRY_DIR_GPIO, &GPIO_InitStructure); - GPIO_ResetBits(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN); - - USART_InitStructure.USART_BaudRate = baudrate; - if (mode & TELEMETRY_SERIAL_8E2) { - USART_InitStructure.USART_WordLength = USART_WordLength_9b; - USART_InitStructure.USART_StopBits = USART_StopBits_2; - USART_InitStructure.USART_Parity = USART_Parity_Even; - } - else { - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No; - } - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; - USART_Init(TELEMETRY_USART, &USART_InitStructure); - - USART_Cmd(TELEMETRY_USART, ENABLE); - USART_ITConfig(TELEMETRY_USART, USART_IT_RXNE, ENABLE); - NVIC_SetPriority(TELEMETRY_USART_IRQn, 6); - NVIC_EnableIRQ(TELEMETRY_USART_IRQn); -} - -void telemetryPortSetDirectionOutput() -{ - TELEMETRY_DIR_GPIO->BSRRL = TELEMETRY_DIR_GPIO_PIN; // output enable - TELEMETRY_USART->CR1 &= ~USART_CR1_RE; // turn off receiver -} - -void telemetryPortSetDirectionInput() -{ - TELEMETRY_DIR_GPIO->BSRRH = TELEMETRY_DIR_GPIO_PIN; // output disable - TELEMETRY_USART->CR1 |= USART_CR1_RE; // turn on receiver -} - -void sportSendBuffer(uint8_t * buffer, uint32_t count) -{ - telemetryPortSetDirectionOutput(); - - DMA_InitTypeDef DMA_InitStructure; - DMA_DeInit(TELEMETRY_DMA_Stream_TX); - DMA_InitStructure.DMA_Channel = TELEMETRY_DMA_Channel_TX; - DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&TELEMETRY_USART->DR); - DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; - DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(buffer); - DMA_InitStructure.DMA_BufferSize = count; - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - DMA_Init(TELEMETRY_DMA_Stream_TX, &DMA_InitStructure); - DMA_Cmd(TELEMETRY_DMA_Stream_TX, ENABLE); - USART_DMACmd(TELEMETRY_USART, USART_DMAReq_Tx, ENABLE); - DMA_ITConfig(TELEMETRY_DMA_Stream_TX, DMA_IT_TC, ENABLE); - - // enable interrupt and set it's priority - NVIC_EnableIRQ(TELEMETRY_DMA_TX_Stream_IRQ) ; - NVIC_SetPriority(TELEMETRY_DMA_TX_Stream_IRQ, 7); -} - -extern "C" void TELEMETRY_DMA_TX_IRQHandler(void) -{ - DEBUG_INTERRUPT(INT_TELEM_DMA); - if (DMA_GetITStatus(TELEMETRY_DMA_Stream_TX, TELEMETRY_DMA_TX_FLAG_TC)) { - DMA_ClearITPendingBit(TELEMETRY_DMA_Stream_TX, TELEMETRY_DMA_TX_FLAG_TC); - TELEMETRY_USART->CR1 |= USART_CR1_TCIE; - if (telemetryProtocol == PROTOCOL_FRSKY_SPORT) { - outputTelemetryBufferSize = 0; - outputTelemetryBufferTrigger = 0x7E; - } - } -} - -#define USART_FLAG_ERRORS (USART_FLAG_ORE | USART_FLAG_NE | USART_FLAG_FE | USART_FLAG_PE) -extern "C" void TELEMETRY_USART_IRQHandler(void) -{ - DEBUG_INTERRUPT(INT_TELEM_USART); - uint32_t status = TELEMETRY_USART->SR; - - if ((status & USART_SR_TC) && (TELEMETRY_USART->CR1 & USART_CR1_TCIE)) { - TELEMETRY_USART->CR1 &= ~USART_CR1_TCIE; - telemetryPortSetDirectionInput(); - while (status & (USART_FLAG_RXNE)) { - status = TELEMETRY_USART->DR; - status = TELEMETRY_USART->SR; - } - } - - while (status & (USART_FLAG_RXNE | USART_FLAG_ERRORS)) { - uint8_t data = TELEMETRY_USART->DR; - if (status & USART_FLAG_ERRORS) { - telemetryErrors++; - } - else { - telemetryFifo.push(data); -#if defined(LUA) - if (telemetryProtocol == PROTOCOL_FRSKY_SPORT) { - static uint8_t prevdata; - if (prevdata == 0x7E && outputTelemetryBufferSize > 0 && data == outputTelemetryBufferTrigger) { - sportSendBuffer(outputTelemetryBuffer, outputTelemetryBufferSize); - } - prevdata = data; - } -#endif - } - status = TELEMETRY_USART->SR; - } -} - -// TODO we should have telemetry in an higher layer, functions above should move to a sport_driver.cpp -uint8_t telemetryGetByte(uint8_t * byte) -{ -#if defined(SERIAL2) - if (telemetryProtocol == PROTOCOL_FRSKY_D_SECONDARY) { - if (serial2Mode == UART_MODE_TELEMETRY) - return serial2RxFifo.pop(*byte); - else - return false; - } - else { - return telemetryFifo.pop(*byte); - } -#else - return telemetryFifo.pop(*byte); -#endif -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +Fifo telemetryFifo; +uint32_t telemetryErrors = 0; + +void telemetryPortInit(uint32_t baudrate, uint8_t mode) +{ + if (baudrate == 0) { + USART_DeInit(TELEMETRY_USART); + return; + } + + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = TELEMETRY_DMA_TX_Stream_IRQ; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pre-emption priority. */; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + USART_InitTypeDef USART_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_PinAFConfig(TELEMETRY_GPIO, TELEMETRY_GPIO_PinSource_RX, TELEMETRY_GPIO_AF); + GPIO_PinAFConfig(TELEMETRY_GPIO, TELEMETRY_GPIO_PinSource_TX, TELEMETRY_GPIO_AF); + + GPIO_InitStructure.GPIO_Pin = TELEMETRY_TX_GPIO_PIN | TELEMETRY_RX_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_Init(TELEMETRY_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = TELEMETRY_DIR_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(TELEMETRY_DIR_GPIO, &GPIO_InitStructure); + GPIO_ResetBits(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN); + + USART_InitStructure.USART_BaudRate = baudrate; + if (mode & TELEMETRY_SERIAL_8E2) { + USART_InitStructure.USART_WordLength = USART_WordLength_9b; + USART_InitStructure.USART_StopBits = USART_StopBits_2; + USART_InitStructure.USART_Parity = USART_Parity_Even; + } + else { + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + } + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; + USART_Init(TELEMETRY_USART, &USART_InitStructure); + + USART_Cmd(TELEMETRY_USART, ENABLE); + USART_ITConfig(TELEMETRY_USART, USART_IT_RXNE, ENABLE); + NVIC_SetPriority(TELEMETRY_USART_IRQn, 6); + NVIC_EnableIRQ(TELEMETRY_USART_IRQn); +} + +void telemetryPortSetDirectionOutput() +{ + TELEMETRY_DIR_GPIO->BSRRL = TELEMETRY_DIR_GPIO_PIN; // output enable + TELEMETRY_USART->CR1 &= ~USART_CR1_RE; // turn off receiver +} + +void telemetryPortSetDirectionInput() +{ + TELEMETRY_DIR_GPIO->BSRRH = TELEMETRY_DIR_GPIO_PIN; // output disable + TELEMETRY_USART->CR1 |= USART_CR1_RE; // turn on receiver +} + +void sportSendBuffer(uint8_t * buffer, uint32_t count) +{ + telemetryPortSetDirectionOutput(); + + DMA_InitTypeDef DMA_InitStructure; + DMA_DeInit(TELEMETRY_DMA_Stream_TX); + DMA_InitStructure.DMA_Channel = TELEMETRY_DMA_Channel_TX; + DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&TELEMETRY_USART->DR); + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(buffer); + DMA_InitStructure.DMA_BufferSize = count; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(TELEMETRY_DMA_Stream_TX, &DMA_InitStructure); + DMA_Cmd(TELEMETRY_DMA_Stream_TX, ENABLE); + USART_DMACmd(TELEMETRY_USART, USART_DMAReq_Tx, ENABLE); + DMA_ITConfig(TELEMETRY_DMA_Stream_TX, DMA_IT_TC, ENABLE); + + // enable interrupt and set it's priority + NVIC_EnableIRQ(TELEMETRY_DMA_TX_Stream_IRQ) ; + NVIC_SetPriority(TELEMETRY_DMA_TX_Stream_IRQ, 7); +} + +extern "C" void TELEMETRY_DMA_TX_IRQHandler(void) +{ + DEBUG_INTERRUPT(INT_TELEM_DMA); + if (DMA_GetITStatus(TELEMETRY_DMA_Stream_TX, TELEMETRY_DMA_TX_FLAG_TC)) { + DMA_ClearITPendingBit(TELEMETRY_DMA_Stream_TX, TELEMETRY_DMA_TX_FLAG_TC); + TELEMETRY_USART->CR1 |= USART_CR1_TCIE; + if (telemetryProtocol == PROTOCOL_FRSKY_SPORT) { + outputTelemetryBufferSize = 0; + outputTelemetryBufferTrigger = 0x7E; + } + } +} + +#define USART_FLAG_ERRORS (USART_FLAG_ORE | USART_FLAG_NE | USART_FLAG_FE | USART_FLAG_PE) +extern "C" void TELEMETRY_USART_IRQHandler(void) +{ + DEBUG_INTERRUPT(INT_TELEM_USART); + uint32_t status = TELEMETRY_USART->SR; + + if ((status & USART_SR_TC) && (TELEMETRY_USART->CR1 & USART_CR1_TCIE)) { + TELEMETRY_USART->CR1 &= ~USART_CR1_TCIE; + telemetryPortSetDirectionInput(); + while (status & (USART_FLAG_RXNE)) { + status = TELEMETRY_USART->DR; + status = TELEMETRY_USART->SR; + } + } + + while (status & (USART_FLAG_RXNE | USART_FLAG_ERRORS)) { + uint8_t data = TELEMETRY_USART->DR; + if (status & USART_FLAG_ERRORS) { + telemetryErrors++; + } + else { + telemetryFifo.push(data); +#if defined(LUA) + if (telemetryProtocol == PROTOCOL_FRSKY_SPORT) { + static uint8_t prevdata; + if (prevdata == 0x7E && outputTelemetryBufferSize > 0 && data == outputTelemetryBufferTrigger) { + sportSendBuffer(outputTelemetryBuffer, outputTelemetryBufferSize); + } + prevdata = data; + } +#endif + } + status = TELEMETRY_USART->SR; + } +} + +// TODO we should have telemetry in an higher layer, functions above should move to a sport_driver.cpp +uint8_t telemetryGetByte(uint8_t * byte) +{ +#if defined(SERIAL2) + if (telemetryProtocol == PROTOCOL_FRSKY_D_SECONDARY) { + if (serial2Mode == UART_MODE_TELEMETRY) + return serial2RxFifo.pop(*byte); + else + return false; + } + else { + return telemetryFifo.pop(*byte); + } +#else + return telemetryFifo.pop(*byte); +#endif +} diff --git a/radio/src/targets/taranis/trainer_driver.cpp b/radio/src/targets/taranis/trainer_driver.cpp index 94ab52664..be0f7743a 100644 --- a/radio/src/targets/taranis/trainer_driver.cpp +++ b/radio/src/targets/taranis/trainer_driver.cpp @@ -1,275 +1,275 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -DMAFifo<32> heartbeatFifo __DMA (HEARTBEAT_DMA_Stream); - -void trainerSendNextFrame(); - -void init_trainer_ppm() -{ - GPIO_PinAFConfig(TRAINER_GPIO, TRAINER_OUT_GPIO_PinSource, TRAINER_GPIO_AF); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = TRAINER_OUT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(TRAINER_GPIO, &GPIO_InitStructure); - - TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; - TRAINER_TIMER->PSC = TRAINER_TIMER_FREQ / 2000000 - 1; // 0.5uS - TRAINER_TIMER->ARR = 45000; - TRAINER_TIMER->CCMR2 = TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4PE; // PWM mode 1 - TRAINER_TIMER->BDTR = TIM_BDTR_MOE; - TRAINER_TIMER->EGR = 1; - TRAINER_TIMER->DIER |= TIM_DIER_UDE; - TRAINER_TIMER->CR1 |= TIM_CR1_CEN; - - setupPulsesPPMTrainer(); - trainerSendNextFrame(); - - NVIC_EnableIRQ(TRAINER_DMA_IRQn); - NVIC_SetPriority(TRAINER_DMA_IRQn, 7); - NVIC_EnableIRQ(TRAINER_TIMER_IRQn); - NVIC_SetPriority(TRAINER_TIMER_IRQn, 7); -} - -void stop_trainer_ppm() -{ - NVIC_DisableIRQ(TRAINER_DMA_IRQn); - NVIC_DisableIRQ(TRAINER_TIMER_IRQn); - - TRAINER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - TRAINER_TIMER->DIER = 0; - TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; // Stop counter -} - -void init_trainer_capture() -{ - GPIO_PinAFConfig(TRAINER_GPIO, TRAINER_IN_GPIO_PinSource, TRAINER_GPIO_AF); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = TRAINER_IN_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(TRAINER_GPIO, &GPIO_InitStructure); - - TRAINER_TIMER->ARR = 0xFFFF; - TRAINER_TIMER->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 2000000 - 1; // 0.5uS - TRAINER_TIMER->CR2 = 0; - TRAINER_TIMER->CCMR2 = TIM_CCMR2_IC3F_0 | TIM_CCMR2_IC3F_1 | TIM_CCMR2_CC3S_0; - TRAINER_TIMER->CCER = TIM_CCER_CC3E; - TRAINER_TIMER->SR &= ~TIM_SR_CC3IF & ~TIM_SR_CC2IF & ~TIM_SR_UIF; // Clear flags - TRAINER_TIMER->DIER |= TIM_DIER_CC3IE; - TRAINER_TIMER->CR1 = TIM_CR1_CEN; - - NVIC_EnableIRQ(TRAINER_TIMER_IRQn); - NVIC_SetPriority(TRAINER_TIMER_IRQn, 7); -} - -void stop_trainer_capture() -{ - NVIC_DisableIRQ(TRAINER_TIMER_IRQn); // Stop Interrupt - - TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; // Stop counter - TRAINER_TIMER->DIER = 0; // Stop Interrupt -} - -void trainerSendNextFrame() -{ - TRAINER_TIMER->CCR4 = GET_PPM_DELAY(TRAINER_MODULE)*2; - TRAINER_TIMER->CCER = TIM_CCER_CC4E | (GET_PPM_POLARITY(TRAINER_MODULE) ? 0 : TIM_CCER_CC4P); - TRAINER_TIMER->CCR1 = *(trainerPulsesData.ppm.ptr - 1) - 4000; // 2mS in advance - - TRAINER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA - TRAINER_DMA_STREAM->CR |= TRAINER_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; - TRAINER_DMA_STREAM->PAR = CONVERT_PTR_UINT(&TRAINER_TIMER->ARR); - TRAINER_DMA_STREAM->M0AR = CONVERT_PTR_UINT(trainerPulsesData.ppm.pulses); - TRAINER_DMA_STREAM->NDTR = trainerPulsesData.ppm.ptr - trainerPulsesData.ppm.pulses; - TRAINER_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA -} - -extern "C" void TRAINER_DMA_IRQHandler() -{ - if (!DMA_GetITStatus(TRAINER_DMA_STREAM, TRAINER_DMA_FLAG_TC)) - return; - - DMA_ClearITPendingBit(TRAINER_DMA_STREAM, TRAINER_DMA_FLAG_TC); - - TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag - TRAINER_TIMER->DIER |= TIM_DIER_CC1IE; // Enable this interrupt -} - -extern "C" void TRAINER_TIMER_IRQHandler() -{ - DEBUG_INTERRUPT(INT_TRAINER); - - uint16_t capture = 0; - bool doCapture = false; - - // What mode? in or out? - if ((TRAINER_TIMER->DIER & TIM_DIER_CC3IE) && (TRAINER_TIMER->SR & TIM_SR_CC3IF)) { - // capture mode on trainer jack - capture = TRAINER_TIMER->CCR3; - if (TRAINER_CONNECTED() && currentTrainerMode == TRAINER_MODE_MASTER_TRAINER_JACK) { - doCapture = true; - } - } - - if ((TRAINER_TIMER->DIER & TIM_DIER_CC2IE) && (TRAINER_TIMER->SR & TIM_SR_CC2IF)) { - // capture mode on heartbeat pin (external module) - capture = TRAINER_TIMER->CCR2; - if (currentTrainerMode == TRAINER_MODE_MASTER_CPPM_EXTERNAL_MODULE) { - doCapture = true; - } - } - - if (doCapture) { - captureTrainerPulses(capture); - } - - // PPM out compare interrupt - if ((TRAINER_TIMER->DIER & TIM_DIER_CC1IE) && (TRAINER_TIMER->SR & TIM_SR_CC1IF)) { - // compare interrupt - TRAINER_TIMER->DIER &= ~TIM_DIER_CC1IE; // stop this interrupt - TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag - setupPulsesPPMTrainer(); - trainerSendNextFrame(); - } -} - -void init_cppm_on_heartbeat_capture(void) -{ - EXTERNAL_MODULE_ON(); - - GPIO_PinAFConfig(HEARTBEAT_GPIO, HEARTBEAT_GPIO_PinSource, HEARTBEAT_GPIO_AF_CAPTURE); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = HEARTBEAT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(HEARTBEAT_GPIO, &GPIO_InitStructure); - - TRAINER_TIMER->ARR = 0xFFFF; - TRAINER_TIMER->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 2000000 - 1; // 0.5uS - TRAINER_TIMER->CR2 = 0; - TRAINER_TIMER->CCMR1 = TIM_CCMR1_IC2F_0 | TIM_CCMR1_IC2F_1 | TIM_CCMR1_CC2S_0; - TRAINER_TIMER->CCER = TIM_CCER_CC2E; - TRAINER_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag - TRAINER_TIMER->DIER |= TIM_DIER_CC2IE; - TRAINER_TIMER->CR1 = TIM_CR1_CEN; - - NVIC_SetPriority(TRAINER_TIMER_IRQn, 7); - NVIC_EnableIRQ(TRAINER_TIMER_IRQn); -} - -void stop_cppm_on_heartbeat_capture() -{ - TRAINER_TIMER->DIER = 0; - TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; // Stop counter - NVIC_DisableIRQ(TRAINER_TIMER_IRQn); // Stop Interrupt - - if (!IS_EXTERNAL_MODULE_PRESENT()) { - EXTERNAL_MODULE_OFF(); - } -} - -void init_sbus_on_heartbeat_capture() -{ - EXTERNAL_MODULE_ON(); - - USART_InitTypeDef USART_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - GPIO_PinAFConfig(GPIOC, HEARTBEAT_GPIO_PinSource, HEARTBEAT_GPIO_AF_SBUS); - - GPIO_InitStructure.GPIO_Pin = HEARTBEAT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - USART_InitStructure.USART_BaudRate = 100000; - USART_InitStructure.USART_WordLength = USART_WordLength_9b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_Even; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Rx; - USART_Init(HEARTBEAT_USART, &USART_InitStructure); - - DMA_InitTypeDef DMA_InitStructure; - heartbeatFifo.clear(); - USART_ITConfig(HEARTBEAT_USART, USART_IT_RXNE, DISABLE); - USART_ITConfig(HEARTBEAT_USART, USART_IT_TXE, DISABLE); - DMA_InitStructure.DMA_Channel = HEARTBEAT_DMA_Channel; - DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&HEARTBEAT_USART->DR); - DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(heartbeatFifo.buffer()); - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; - DMA_InitStructure.DMA_BufferSize = heartbeatFifo.size(); - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; - DMA_InitStructure.DMA_Priority = DMA_Priority_Low; - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - DMA_Init(HEARTBEAT_DMA_Stream, &DMA_InitStructure); - USART_DMACmd(HEARTBEAT_USART, USART_DMAReq_Rx, ENABLE); - USART_Cmd(HEARTBEAT_USART, ENABLE); - DMA_Cmd(HEARTBEAT_DMA_Stream, ENABLE); -} - -void stop_sbus_on_heartbeat_capture() -{ - DMA_Cmd(HEARTBEAT_DMA_Stream, DISABLE); - USART_Cmd(HEARTBEAT_USART, DISABLE); - USART_DMACmd(HEARTBEAT_USART, USART_DMAReq_Rx, DISABLE); - DMA_DeInit(HEARTBEAT_DMA_Stream); - NVIC_DisableIRQ(HEARTBEAT_USART_IRQn); - - if (!IS_EXTERNAL_MODULE_PRESENT()) { - EXTERNAL_MODULE_OFF(); - } -} - -int sbusGetByte(uint8_t * byte) -{ - switch (currentTrainerMode) { - case TRAINER_MODE_MASTER_SBUS_EXTERNAL_MODULE: - return heartbeatFifo.pop(*byte); -#if defined(SERIAL2) - case TRAINER_MODE_MASTER_BATTERY_COMPARTMENT: - return serial2RxFifo.pop(*byte); -#endif - default: - return false; - } -} +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +DMAFifo<32> heartbeatFifo __DMA (HEARTBEAT_DMA_Stream); + +void trainerSendNextFrame(); + +void init_trainer_ppm() +{ + GPIO_PinAFConfig(TRAINER_GPIO, TRAINER_OUT_GPIO_PinSource, TRAINER_GPIO_AF); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = TRAINER_OUT_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(TRAINER_GPIO, &GPIO_InitStructure); + + TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; + TRAINER_TIMER->PSC = TRAINER_TIMER_FREQ / 2000000 - 1; // 0.5uS + TRAINER_TIMER->ARR = 45000; + TRAINER_TIMER->CCMR2 = TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4PE; // PWM mode 1 + TRAINER_TIMER->BDTR = TIM_BDTR_MOE; + TRAINER_TIMER->EGR = 1; + TRAINER_TIMER->DIER |= TIM_DIER_UDE; + TRAINER_TIMER->CR1 |= TIM_CR1_CEN; + + setupPulsesPPMTrainer(); + trainerSendNextFrame(); + + NVIC_EnableIRQ(TRAINER_DMA_IRQn); + NVIC_SetPriority(TRAINER_DMA_IRQn, 7); + NVIC_EnableIRQ(TRAINER_TIMER_IRQn); + NVIC_SetPriority(TRAINER_TIMER_IRQn, 7); +} + +void stop_trainer_ppm() +{ + NVIC_DisableIRQ(TRAINER_DMA_IRQn); + NVIC_DisableIRQ(TRAINER_TIMER_IRQn); + + TRAINER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + TRAINER_TIMER->DIER = 0; + TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; // Stop counter +} + +void init_trainer_capture() +{ + GPIO_PinAFConfig(TRAINER_GPIO, TRAINER_IN_GPIO_PinSource, TRAINER_GPIO_AF); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = TRAINER_IN_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(TRAINER_GPIO, &GPIO_InitStructure); + + TRAINER_TIMER->ARR = 0xFFFF; + TRAINER_TIMER->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 2000000 - 1; // 0.5uS + TRAINER_TIMER->CR2 = 0; + TRAINER_TIMER->CCMR2 = TIM_CCMR2_IC3F_0 | TIM_CCMR2_IC3F_1 | TIM_CCMR2_CC3S_0; + TRAINER_TIMER->CCER = TIM_CCER_CC3E; + TRAINER_TIMER->SR &= ~TIM_SR_CC3IF & ~TIM_SR_CC2IF & ~TIM_SR_UIF; // Clear flags + TRAINER_TIMER->DIER |= TIM_DIER_CC3IE; + TRAINER_TIMER->CR1 = TIM_CR1_CEN; + + NVIC_EnableIRQ(TRAINER_TIMER_IRQn); + NVIC_SetPriority(TRAINER_TIMER_IRQn, 7); +} + +void stop_trainer_capture() +{ + NVIC_DisableIRQ(TRAINER_TIMER_IRQn); // Stop Interrupt + + TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; // Stop counter + TRAINER_TIMER->DIER = 0; // Stop Interrupt +} + +void trainerSendNextFrame() +{ + TRAINER_TIMER->CCR4 = GET_PPM_DELAY(TRAINER_MODULE)*2; + TRAINER_TIMER->CCER = TIM_CCER_CC4E | (GET_PPM_POLARITY(TRAINER_MODULE) ? 0 : TIM_CCER_CC4P); + TRAINER_TIMER->CCR1 = *(trainerPulsesData.ppm.ptr - 1) - 4000; // 2mS in advance + + TRAINER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + TRAINER_DMA_STREAM->CR |= TRAINER_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; + TRAINER_DMA_STREAM->PAR = CONVERT_PTR_UINT(&TRAINER_TIMER->ARR); + TRAINER_DMA_STREAM->M0AR = CONVERT_PTR_UINT(trainerPulsesData.ppm.pulses); + TRAINER_DMA_STREAM->NDTR = trainerPulsesData.ppm.ptr - trainerPulsesData.ppm.pulses; + TRAINER_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA +} + +extern "C" void TRAINER_DMA_IRQHandler() +{ + if (!DMA_GetITStatus(TRAINER_DMA_STREAM, TRAINER_DMA_FLAG_TC)) + return; + + DMA_ClearITPendingBit(TRAINER_DMA_STREAM, TRAINER_DMA_FLAG_TC); + + TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag + TRAINER_TIMER->DIER |= TIM_DIER_CC1IE; // Enable this interrupt +} + +extern "C" void TRAINER_TIMER_IRQHandler() +{ + DEBUG_INTERRUPT(INT_TRAINER); + + uint16_t capture = 0; + bool doCapture = false; + + // What mode? in or out? + if ((TRAINER_TIMER->DIER & TIM_DIER_CC3IE) && (TRAINER_TIMER->SR & TIM_SR_CC3IF)) { + // capture mode on trainer jack + capture = TRAINER_TIMER->CCR3; + if (TRAINER_CONNECTED() && currentTrainerMode == TRAINER_MODE_MASTER_TRAINER_JACK) { + doCapture = true; + } + } + + if ((TRAINER_TIMER->DIER & TIM_DIER_CC2IE) && (TRAINER_TIMER->SR & TIM_SR_CC2IF)) { + // capture mode on heartbeat pin (external module) + capture = TRAINER_TIMER->CCR2; + if (currentTrainerMode == TRAINER_MODE_MASTER_CPPM_EXTERNAL_MODULE) { + doCapture = true; + } + } + + if (doCapture) { + captureTrainerPulses(capture); + } + + // PPM out compare interrupt + if ((TRAINER_TIMER->DIER & TIM_DIER_CC1IE) && (TRAINER_TIMER->SR & TIM_SR_CC1IF)) { + // compare interrupt + TRAINER_TIMER->DIER &= ~TIM_DIER_CC1IE; // stop this interrupt + TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag + setupPulsesPPMTrainer(); + trainerSendNextFrame(); + } +} + +void init_cppm_on_heartbeat_capture(void) +{ + EXTERNAL_MODULE_ON(); + + GPIO_PinAFConfig(HEARTBEAT_GPIO, HEARTBEAT_GPIO_PinSource, HEARTBEAT_GPIO_AF_CAPTURE); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = HEARTBEAT_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(HEARTBEAT_GPIO, &GPIO_InitStructure); + + TRAINER_TIMER->ARR = 0xFFFF; + TRAINER_TIMER->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 2000000 - 1; // 0.5uS + TRAINER_TIMER->CR2 = 0; + TRAINER_TIMER->CCMR1 = TIM_CCMR1_IC2F_0 | TIM_CCMR1_IC2F_1 | TIM_CCMR1_CC2S_0; + TRAINER_TIMER->CCER = TIM_CCER_CC2E; + TRAINER_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag + TRAINER_TIMER->DIER |= TIM_DIER_CC2IE; + TRAINER_TIMER->CR1 = TIM_CR1_CEN; + + NVIC_SetPriority(TRAINER_TIMER_IRQn, 7); + NVIC_EnableIRQ(TRAINER_TIMER_IRQn); +} + +void stop_cppm_on_heartbeat_capture() +{ + TRAINER_TIMER->DIER = 0; + TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN; // Stop counter + NVIC_DisableIRQ(TRAINER_TIMER_IRQn); // Stop Interrupt + + if (!IS_EXTERNAL_MODULE_PRESENT()) { + EXTERNAL_MODULE_OFF(); + } +} + +void init_sbus_on_heartbeat_capture() +{ + EXTERNAL_MODULE_ON(); + + USART_InitTypeDef USART_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_PinAFConfig(GPIOC, HEARTBEAT_GPIO_PinSource, HEARTBEAT_GPIO_AF_SBUS); + + GPIO_InitStructure.GPIO_Pin = HEARTBEAT_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + USART_InitStructure.USART_BaudRate = 100000; + USART_InitStructure.USART_WordLength = USART_WordLength_9b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_Even; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx; + USART_Init(HEARTBEAT_USART, &USART_InitStructure); + + DMA_InitTypeDef DMA_InitStructure; + heartbeatFifo.clear(); + USART_ITConfig(HEARTBEAT_USART, USART_IT_RXNE, DISABLE); + USART_ITConfig(HEARTBEAT_USART, USART_IT_TXE, DISABLE); + DMA_InitStructure.DMA_Channel = HEARTBEAT_DMA_Channel; + DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&HEARTBEAT_USART->DR); + DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(heartbeatFifo.buffer()); + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = heartbeatFifo.size(); + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_Low; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(HEARTBEAT_DMA_Stream, &DMA_InitStructure); + USART_DMACmd(HEARTBEAT_USART, USART_DMAReq_Rx, ENABLE); + USART_Cmd(HEARTBEAT_USART, ENABLE); + DMA_Cmd(HEARTBEAT_DMA_Stream, ENABLE); +} + +void stop_sbus_on_heartbeat_capture() +{ + DMA_Cmd(HEARTBEAT_DMA_Stream, DISABLE); + USART_Cmd(HEARTBEAT_USART, DISABLE); + USART_DMACmd(HEARTBEAT_USART, USART_DMAReq_Rx, DISABLE); + DMA_DeInit(HEARTBEAT_DMA_Stream); + NVIC_DisableIRQ(HEARTBEAT_USART_IRQn); + + if (!IS_EXTERNAL_MODULE_PRESENT()) { + EXTERNAL_MODULE_OFF(); + } +} + +int sbusGetByte(uint8_t * byte) +{ + switch (currentTrainerMode) { + case TRAINER_MODE_MASTER_SBUS_EXTERNAL_MODULE: + return heartbeatFifo.pop(*byte); +#if defined(SERIAL2) + case TRAINER_MODE_MASTER_BATTERY_COMPARTMENT: + return serial2RxFifo.pop(*byte); +#endif + default: + return false; + } +} diff --git a/radio/src/tasks_arm.h b/radio/src/tasks_arm.h index b26bd1795..8c82a2dd4 100644 --- a/radio/src/tasks_arm.h +++ b/radio/src/tasks_arm.h @@ -1,81 +1,81 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _TASKS_ARM_H_ -#define _TASKS_ARM_H_ - -#if !defined(SIMU) -extern "C" { -#include -} -#endif - -#define MENUS_STACK_SIZE 2000 -#define MIXER_STACK_SIZE 500 -#define AUDIO_STACK_SIZE 500 -#define BLUETOOTH_STACK_SIZE 500 - -#if defined(_MSC_VER) -#define _ALIGNED(x) __declspec(align(x)) -#elif defined(__GNUC__) -#define _ALIGNED(x) __attribute__ ((aligned(x))) -#endif - -uint16_t getStackAvailable(void * address, uint16_t size); - -template -class TaskStack -{ - public: - TaskStack() { } - void paint(); - uint16_t size() - { - return SIZE * 4; - } - uint16_t available() - { - return getStackAvailable(stack, SIZE); - } - OS_STK stack[SIZE]; -}; - -void stackPaint(); -uint16_t stackSize(); -uint16_t stackAvailable(); - -extern OS_TID menusTaskId; -// menus stack must be aligned to 8 bytes otherwise printf for %f does not work! -extern TaskStack _ALIGNED(8) menusStack; - -extern OS_TID mixerTaskId; -extern TaskStack mixerStack; - -extern OS_TID audioTaskId; -extern TaskStack audioStack; - -#if defined(BLUETOOTH) -extern OS_TID btTaskId; -extern TaskStack bluetoothStack; -#endif - -void tasksStart(); - -#endif // _TASKS_ARM_H_ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _TASKS_ARM_H_ +#define _TASKS_ARM_H_ + +#if !defined(SIMU) +extern "C" { +#include +} +#endif + +#define MENUS_STACK_SIZE 2000 +#define MIXER_STACK_SIZE 500 +#define AUDIO_STACK_SIZE 500 +#define BLUETOOTH_STACK_SIZE 500 + +#if defined(_MSC_VER) +#define _ALIGNED(x) __declspec(align(x)) +#elif defined(__GNUC__) +#define _ALIGNED(x) __attribute__ ((aligned(x))) +#endif + +uint16_t getStackAvailable(void * address, uint16_t size); + +template +class TaskStack +{ + public: + TaskStack() { } + void paint(); + uint16_t size() + { + return SIZE * 4; + } + uint16_t available() + { + return getStackAvailable(stack, SIZE); + } + OS_STK stack[SIZE]; +}; + +void stackPaint(); +uint16_t stackSize(); +uint16_t stackAvailable(); + +extern OS_TID menusTaskId; +// menus stack must be aligned to 8 bytes otherwise printf for %f does not work! +extern TaskStack _ALIGNED(8) menusStack; + +extern OS_TID mixerTaskId; +extern TaskStack mixerStack; + +extern OS_TID audioTaskId; +extern TaskStack audioStack; + +#if defined(BLUETOOTH) +extern OS_TID btTaskId; +extern TaskStack bluetoothStack; +#endif + +void tasksStart(); + +#endif // _TASKS_ARM_H_ diff --git a/radio/src/telemetry/ardupilot.cpp b/radio/src/telemetry/ardupilot.cpp index 6294ad06c..ea96a853c 100644 --- a/radio/src/telemetry/ardupilot.cpp +++ b/radio/src/telemetry/ardupilot.cpp @@ -1,716 +1,716 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#define NB_BUF 2 -#define LG_BUF 11 -#define VALSTR(val) (rbuf[val][0] ? rbuf[val] : val_unknown) -#define APSIZE (BSS | DBLSIZE) - -/* Received data - -Data are received as packets, each packet is identified by a prefix of three -characters and is ended by three stars. Some packets can contain more than -one value, the values are ended by a comma. - - -Position packet: -!!!LAT:0123456789,LON:9876543210,SPD:123,CRT:1,ALT:123456,ALH:654321,CRS:123,BER:123,WPN:12,DST:12345,BTV:12.4567 9012,RSP:123,TOW:123456,*** -...----1--------------2--------------3-------4-----5----------6----------7-------8-------9------10--------11-----------12----------13-----END - 1st value 2nd value - -Attitude packet: -+++ASP:123,THH:123,RLL:123,PCH:123,*** -...----1-------2-------3-------4---END - -Mode change packet: -###STABILIZE*** -...1--------END - -Waypoint packet: -%%%12 45*** -...1----END - -Alert packet: -XXXAlert Text alert*** -...1---------------END - -Performance packet: -PPPThis is performant*** -...1--------------END -*/ - -// Position packet prefix -#define PACK_POS 0x21 -// value occurence number in this packet -#define LAT 1 -#define LON 2 -#define SPD 3 -#define CRT 4 -#define ALT 5 -#define ALH 6 -#define CRS 7 -#define BER 8 -#define WPN 9 -#define DST 10 -#define BTV 11 -#define RSP 12 -#define TOW 13 - -#define PACK_ATT 0x2b -// value occurence number in this packet -#define ASP 1 -#define THH 2 -#define RLL 3 -#define PCH 4 - -#define PACK_MOD 0x23 -// value occurence number in this packet -#define MOD 1 - -#define PACK_WPC 0x25 -// value occurence number in this packet -#define WPC 1 - -#define PACK_ALR 0x58 -// value occurence number in this packet -#define ALR 1 - -#define PACK_PRF 0x50 -// value occurence number in this packet -#define PRF 1 - -// end of packet -#define PACK_END 0x2a -// end of value -#define VAL_END 0x2c -// end of title -#define TITLE_END 0x3a - -// stateful machine - -// Since the packets are sent continuously, we need to synchronize on the -// reception of the three chars prefixing a packet, whatever they are. - -// states values -#define WAIT_PACKET 1 -#define WAIT_PACK_POS1 2 -#define WAIT_PACK_POS2 3 -#define WAIT_PACK_POS3 4 -#define WAIT_PACK_ATT1 5 -#define WAIT_PACK_ATT2 6 -#define WAIT_PACK_ATT3 7 -#define WAIT_PACK_MOD1 8 -#define WAIT_PACK_MOD2 9 -#define WAIT_PACK_MOD3 10 -#define WAIT_PACK_WPC1 11 -#define WAIT_PACK_WPC2 12 -#define WAIT_PACK_WPC3 13 -#define WAIT_PACK_ALR1 14 -#define WAIT_PACK_ALR2 15 -#define WAIT_PACK_ALR3 16 -#define WAIT_PACK_PRF1 17 -#define WAIT_PACK_PRF2 18 -#define WAIT_PACK_PRF3 19 -#define FLUSH_TITLE1 20 -#define FLUSH_TITLE2 21 -#define FLUSH_TITLE3 22 -#define FLUSH_TITLE4 23 -#define READ_VALUE 24 - -uint8_t i; // working variable -uint8_t state; // currrent state -uint8_t rval, rpack; // received items -uint8_t xval[NB_BUF]; // expected value -uint8_t xpack[NB_BUF]; // expected packet -uint8_t ibuf[NB_BUF]; // subscripts on buffers values -char rbuf[NB_BUF][LG_BUF]; // receive buffers -const char val_unknown[] = "?"; - -void menuViewTelemetryArduPilot1(event_t event); -void menuViewTelemetryArduPilot2(event_t event); -void menuViewTelemetryArduPilot3(event_t event); -void menuViewTelemetryArduPilot4(event_t event); -void menuViewTelemetryArduPilot5(event_t event); -void menuViewTelemetryArduPilot6(event_t event); -void menuViewTelemetryArduPilot7(event_t event); -void menuViewTelemetryArduPilot8(event_t event); -void title(char x); -void initval(uint8_t num, uint8_t pack, uint8_t val); - -#ifndef SIMU -ISR (USART0_RX_vect) -{ - uint8_t rl; -// uint8_t rh; //USART control and Status Register 0 B - uint8_t iostat; //USART control and Status Register 0 A - - rl = UDR0; - iostat = UCSR0A; //USART control and Status Register 0 A - /* - bit 7 6 5 4 3 2 1 0 - RxC0 TxC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 - - RxC0: Receive complete - TXC0: Transmit Complete - UDRE0: USART Data Register Empty - FE0: Frame Error - DOR0: Data OverRun - UPE0: USART Parity Error - U2X0: Double Tx Speed - MPCM0: MultiProcessor Comms Mode -*/ - if (iostat & ((1 << FE0) | (1 << DOR0) | (1 << UPE0))) - { - rl = xpack[0] = xpack[1] = xval[0] = xval[1] = 0; - state = WAIT_PACKET; // restart on error - } - // rh = UCSR0B; //USART control and Status Register 0 B -/* bit 7 6 5 4 3 2 1 0 - RxCIE0 TxCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 - - RxCIE0: Receive complete int enable - TXCIE0: Transmit Complete int enable - UDRIE0: USART Data Register Empty int enable - RXEN0: Rx enable - TXEN0: Tx Enable - UCSZ02: Character Size bit 2 - RXB80: Rx data bit 8 - TXB80: Tx data bit 8 -*/ - switch (state) - { - case WAIT_PACKET: - switch (rl) - { - case PACK_POS: // found a new POS packet - state = WAIT_PACK_POS2; // wait for the 2nd char - break; - case PACK_ATT: // found a new ATT packet - state = WAIT_PACK_ATT2; // wait for the 2nd char - break; - case PACK_MOD: // found a new MOD packet - state = WAIT_PACK_MOD2; // wait for the 2nd char - break; - case PACK_WPC: // found a new WPC packet - state = WAIT_PACK_WPC2; // wait for the 2nd char - break; - case PACK_ALR: // found a new ALR packet - state = WAIT_PACK_ALR2; // wait for the 2nd char - break; - case PACK_PRF: // found a new PRF packet - state = WAIT_PACK_PRF2; // wait for the 2nd char - break; - } - break; - case WAIT_PACK_POS2: // wait for 2nd char - if (rl == PACK_POS) - state = WAIT_PACK_POS3; - else - state = WAIT_PACKET; // restart if not found - break; - case WAIT_PACK_POS3: // wait for 3rd char - if (rl == PACK_POS) // found - { - state = FLUSH_TITLE1; // flush title "LAT:" - rpack = PACK_POS; - rval = 1; - for (i = 0; i < NB_BUF; i++) - ibuf[i] = 0; - } - else - state = WAIT_PACKET; // restart if not found - break; - case WAIT_PACK_ATT2: // wait for 2nd char - if (rl == PACK_ATT) - state = WAIT_PACK_ATT3; - else - state = WAIT_PACKET; // restart if not found - break; - case WAIT_PACK_ATT3: // wait for 3rd char - if (rl == PACK_ATT) - { - state = FLUSH_TITLE1; // flush title "ASP:" - rpack = PACK_ATT; - rval = 1; - for (i = 0; i < NB_BUF; i++) - ibuf[i] = 0; - } - else - state = WAIT_PACKET; // restart if not found - break; - case WAIT_PACK_MOD2: // wait for 2nd char - if (rl == PACK_MOD) - state = WAIT_PACK_MOD3; - else - state = WAIT_PACKET; // restart if not found - break; - case WAIT_PACK_MOD3: // wait for 3rd char - if (rl == PACK_MOD) - { - state = READ_VALUE; // ready to read values from PACK_MOD packet - rpack = PACK_MOD; - rval = 1; - for (i = 0; i < NB_BUF; i++) - ibuf[i] = 0; - } - else - state = WAIT_PACKET; // restart if not found - break; - case WAIT_PACK_WPC2: // wait for 2nd char - if (rl == PACK_WPC) - state = WAIT_PACK_WPC3; - else - state = WAIT_PACKET; // restart if not found - break; - case WAIT_PACK_WPC3: // wait for 3rd char - if (rl == PACK_WPC) - { - state = READ_VALUE; // ready to read values from PACK_WPC packet - rpack = PACK_WPC; - rval = 1; - for (i = 0; i < NB_BUF; i++) - ibuf[i] = 0; - } - else - state = WAIT_PACKET; // restart if not found - break; - case WAIT_PACK_ALR2: // wait for 2nd char - if (rl == PACK_ALR) - state = WAIT_PACK_ALR3; - else - state = WAIT_PACKET; // restart if not found - break; - case WAIT_PACK_ALR3: // wait for 3rd char - if (rl == PACK_ALR) - { - state = READ_VALUE; // ready to read values from PACK_ALR packet - rpack = PACK_ALR; - rval = 1; - for (i = 0; i < NB_BUF; i++) - ibuf[i] = 0; - } - else - state = WAIT_PACKET; // restart if not found - break; - case WAIT_PACK_PRF2: // wait for 2nd char - if (rl == PACK_PRF) - state = WAIT_PACK_PRF3; - else - state = WAIT_PACKET; // restart if not found - break; - case WAIT_PACK_PRF3: // wait for 3rd char - if (rl == PACK_PRF) - { - state = READ_VALUE; // ready to read values from PACK_PRF packet - rpack = PACK_PRF; - rval = 1; - for (i = 0; i < NB_BUF; i++) - ibuf[i] = 0; - } - else - state = WAIT_PACKET; // restart if not found - break; - case FLUSH_TITLE1: // wait for 1st char of title - state = FLUSH_TITLE2; - break; - case FLUSH_TITLE2: // wait for 2nd char - state = FLUSH_TITLE3; - break; - case FLUSH_TITLE3: // wait for 3rd char - state = FLUSH_TITLE4; - break; - case FLUSH_TITLE4: // wait for 4th char - if (rl == TITLE_END) - state = READ_VALUE; - else - state = WAIT_PACKET; // was not a title, wait for the next packet - break; - case READ_VALUE: - switch (rl) - { - case PACK_END: - state = WAIT_PACKET; // packet completed, wait for the next packet - break; - case VAL_END: // comma found, value completed - state = FLUSH_TITLE1; // flush next title - rval++; // and get next value - break; - default: // store the char in the corresponding buffer - for (i = 0; i < NB_BUF; i++) - { // is it the expected value in the expected packet ? - if (rpack == xpack[i] && rval == xval[i] && ibuf[i] < LG_BUF - 1) - { // yes, store the char - rbuf[i] [ibuf[i]] = rl; - ibuf[i]++; - rbuf[i] [ibuf[i]] = 0; - } - } - break; - } - break; - } -} -#endif - -void ARDUPILOT_Init (void) -{ - DDRE &= ~(1 << DDE0); // set RXD0 pin as input - PORTE &= ~(1 << PORTE0); // disable pullup on RXD0 pin - -#ifndef SIMU - // switch (Telem_baud) - // { - // case 1: -#undef BAUD -#define BAUD 38400 -#include - UBRR0H = UBRRH_VALUE; - UBRR0L = UBRRL_VALUE; - // break; - // } - - UCSR0A &= ~(1 << U2X0); // disable double speed operation - // set 8N1 - UCSR0B = 0|(0<< RXCIE0)|(0<, , ); - ------------------------------------- - - That means that "" of "" is stored in the buffer. - The first is 0. - - Here are the packet names and the associated value names: - - Position packet (beginning with "!!!"): "PACK_POS" - value names: "LAT", "LON", "SPD", "CRT", "ALT", "ALH", "CRS", "BER", - "WPN", "DST", "BTV", "RSP", "TOW" - - Attitude packet (beginning with "+++"): "PACK_ATT" - value names: "ASP", "THH", "RLL", "PCH" - - Mode change packet (beginning with "###"): "PACK_MOD" - value name: "MOD" - - Waypoint packet (beginning with "%%%"): "PACK_WPC" - value name: "WPC" - - Alert packet (beginning with "XXX"): "PACK_ALR" - value name: "ALR" - - Performance packet (beginning with "PPP"): "PACK_PRF" - value name: "PRF" - - The buffers are accessed using the macro "VALSTR()", where "" is "0" - for the first buffer, and "1" for the second buffer. - - When a value is missing, it is replaced by the contents of val_unknown ("?"). -*/ -// expecting LAT value in POS packet to be stored in the first buffer - initval (0, PACK_POS, LAT); -// and LON value in POS packet stored in the second buffer - initval (1, PACK_POS, LON); -// title of the screen - title ('1'); - lcdDrawText(5*FW, 1*FH, PSTR(" Latitude")); // line 1 column 5 -// first buffer into line 2 column 2 - lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); - lcdDrawText(5*FW, 4*FH, PSTR(" Longitude")); // line 4 column 5 -// second buffer into line 5 column 2 - lcdDrawText (1*FW, 5*FH, VALSTR(1), APSIZE); -} - -void menuViewTelemetryArduPilot2(event_t event) -{ - switch(event) - { - case EVT_KEY_FIRST(KEY_UP): - chainMenu(menuViewTelemetryArduPilot1); - break; - case EVT_KEY_FIRST(KEY_DOWN): - chainMenu(menuViewTelemetryArduPilot3); - break; - case EVT_KEY_FIRST(KEY_EXIT): - ARDUPILOT_DisableRXD(); - chainMenu(menuMainView); - break; - } - initval (0, PACK_POS, SPD); - initval (1, PACK_POS, CRT); - title ('2'); - lcdDrawText(1*FW, 1*FH, PSTR(" Ground speed")); - lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); - lcdDrawText(1*FW, 4*FH, PSTR(" Climb rate") ); - lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); -} - -void menuViewTelemetryArduPilot3(event_t event) -{ - switch(event) - { - case EVT_KEY_FIRST(KEY_UP): - chainMenu(menuViewTelemetryArduPilot2); - break; - case EVT_KEY_FIRST(KEY_DOWN): - chainMenu(menuViewTelemetryArduPilot4); - break; - case EVT_KEY_FIRST(KEY_EXIT): - ARDUPILOT_DisableRXD(); - chainMenu(menuMainView); - break; - } - initval (0, PACK_POS, ALT); - initval (1, PACK_POS, ALH); - title ('3'); - lcdDrawText(1*FW, 1*FH, PSTR(" Altitude")); - lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); - lcdDrawText(1*FW, 4*FH, PSTR(" Altitude Hold") ); - lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); -} - -void menuViewTelemetryArduPilot4(event_t event) -{ - switch(event) - { - case EVT_KEY_FIRST(KEY_UP): - chainMenu(menuViewTelemetryArduPilot3); - break; - case EVT_KEY_FIRST(KEY_DOWN): - chainMenu(menuViewTelemetryArduPilot5); - break; - case EVT_KEY_FIRST(KEY_EXIT): - ARDUPILOT_DisableRXD(); - chainMenu(menuMainView); - break; - } - initval (0, PACK_POS, CRS); - initval (1, PACK_POS, BER); - title ('4'); - lcdDrawText(1*FW, 1*FH, PSTR(" Course")); - lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); - lcdDrawText(1*FW, 4*FH, PSTR(" Bearing")); - lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); -} - -void menuViewTelemetryArduPilot5(event_t event) -{ - switch(event) - { - case EVT_KEY_FIRST(KEY_UP): - chainMenu(menuViewTelemetryArduPilot4); - break; - case EVT_KEY_FIRST(KEY_DOWN): - chainMenu(menuViewTelemetryArduPilot6); - break; - case EVT_KEY_FIRST(KEY_MENU): - break; - case EVT_KEY_FIRST(KEY_EXIT): - ARDUPILOT_DisableRXD(); - chainMenu(menuMainView); - break; - } - initval (0, PACK_POS, WPN); - initval (1, PACK_POS, DST); - title ('5'); - lcdDrawText(1*FW, 1*FH, PSTR(" Way Point # ")); - lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); - lcdDrawText(1*FW, 4*FH, PSTR(" Distance ")); - lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); -} - -void menuViewTelemetryArduPilot6(event_t event) -{ - switch(event) - { - case EVT_KEY_FIRST(KEY_UP): - chainMenu(menuViewTelemetryArduPilot5); - break; - case EVT_KEY_FIRST(KEY_DOWN): - chainMenu(menuViewTelemetryArduPilot7); - break; - case EVT_KEY_FIRST(KEY_MENU): - break; - case EVT_KEY_FIRST(KEY_EXIT): - ARDUPILOT_DisableRXD(); - chainMenu(menuMainView); - break; - } - initval (0, PACK_ATT, ASP); - initval (1, PACK_ATT, THH); - title ('6'); - lcdDrawText(1*FW, 1*FH, PSTR(" Air Speed ")); - lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); - lcdDrawText(1*FW, 4*FH, PSTR(" Climb Rate ")); - lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); -} - -void menuViewTelemetryArduPilot7(event_t event) -{ - switch(event) - { - case EVT_KEY_FIRST(KEY_UP): - chainMenu(menuViewTelemetryArduPilot6); - break; - case EVT_KEY_FIRST(KEY_DOWN): - chainMenu(menuViewTelemetryArduPilot8); - break; - case EVT_KEY_FIRST(KEY_MENU): - break; - case EVT_KEY_FIRST(KEY_EXIT): - ARDUPILOT_DisableRXD(); - chainMenu(menuMainView); - break; - } - initval (0, PACK_ATT, RLL); - initval (1, PACK_ATT, PCH); - title ('7'); - lcdDrawText(1*FW, 1*FH, PSTR(" Roll Angle")); - lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); - lcdDrawText(1*FW, 4*FH, PSTR(" Pitch Angle")); - lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); -} - -void menuViewTelemetryArduPilot8(event_t event) -{ - switch(event) - { - case EVT_KEY_FIRST(KEY_UP): - chainMenu(menuViewTelemetryArduPilot7); - break; - case EVT_KEY_FIRST(KEY_DOWN): - chainMenu(menuViewTelemetryArduPilot1); - break; - case EVT_KEY_FIRST(KEY_MENU): - break; - case EVT_KEY_FIRST(KEY_EXIT): - ARDUPILOT_DisableRXD(); - chainMenu(menuMainView); - break; - } - initval (0, PACK_MOD, MOD); - initval (1, PACK_WPC, WPC); - title ('8'); - lcdDrawText(1*FW, 1*FH, PSTR(" ArduPilot Mode")); - lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); - lcdDrawText(1*FW, 4*FH, PSTR(" RTL Distance")); - lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); -} - -void title(char x) -{ - lcdDrawText (0, 0, PSTR(" ARDU PILOT Mega ?/8 "), INVERS); - lcdDrawChar(17*FW, 0*FH, x, INVERS); -} - -void initval(uint8_t num, uint8_t pack, uint8_t val) -{ - if (xpack[num] != pack || xval[num] != val) - { - ibuf[num] = rbuf[num][0] = 0; - xpack[num] = pack; - xval[num] = val; - state = WAIT_PACKET; // synchronize to the next packet - } -} - -/* -Without ArduPilot: -Size after: -er9x.elf : -section size addr -.data 164 8388864 -.text 50634 0 -.bss 3485 8389028 ----------------------------------- -With ArduPilot: -Size after: -er9x.elf : -section size addr -.data 166 8388864 -.text 53026 0 -.bss 3517 8389030 -*/ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "opentx.h" + +#define NB_BUF 2 +#define LG_BUF 11 +#define VALSTR(val) (rbuf[val][0] ? rbuf[val] : val_unknown) +#define APSIZE (BSS | DBLSIZE) + +/* Received data + +Data are received as packets, each packet is identified by a prefix of three +characters and is ended by three stars. Some packets can contain more than +one value, the values are ended by a comma. + + +Position packet: +!!!LAT:0123456789,LON:9876543210,SPD:123,CRT:1,ALT:123456,ALH:654321,CRS:123,BER:123,WPN:12,DST:12345,BTV:12.4567 9012,RSP:123,TOW:123456,*** +...----1--------------2--------------3-------4-----5----------6----------7-------8-------9------10--------11-----------12----------13-----END + 1st value 2nd value + +Attitude packet: ++++ASP:123,THH:123,RLL:123,PCH:123,*** +...----1-------2-------3-------4---END + +Mode change packet: +###STABILIZE*** +...1--------END + +Waypoint packet: +%%%12 45*** +...1----END + +Alert packet: +XXXAlert Text alert*** +...1---------------END + +Performance packet: +PPPThis is performant*** +...1--------------END +*/ + +// Position packet prefix +#define PACK_POS 0x21 +// value occurence number in this packet +#define LAT 1 +#define LON 2 +#define SPD 3 +#define CRT 4 +#define ALT 5 +#define ALH 6 +#define CRS 7 +#define BER 8 +#define WPN 9 +#define DST 10 +#define BTV 11 +#define RSP 12 +#define TOW 13 + +#define PACK_ATT 0x2b +// value occurence number in this packet +#define ASP 1 +#define THH 2 +#define RLL 3 +#define PCH 4 + +#define PACK_MOD 0x23 +// value occurence number in this packet +#define MOD 1 + +#define PACK_WPC 0x25 +// value occurence number in this packet +#define WPC 1 + +#define PACK_ALR 0x58 +// value occurence number in this packet +#define ALR 1 + +#define PACK_PRF 0x50 +// value occurence number in this packet +#define PRF 1 + +// end of packet +#define PACK_END 0x2a +// end of value +#define VAL_END 0x2c +// end of title +#define TITLE_END 0x3a + +// stateful machine + +// Since the packets are sent continuously, we need to synchronize on the +// reception of the three chars prefixing a packet, whatever they are. + +// states values +#define WAIT_PACKET 1 +#define WAIT_PACK_POS1 2 +#define WAIT_PACK_POS2 3 +#define WAIT_PACK_POS3 4 +#define WAIT_PACK_ATT1 5 +#define WAIT_PACK_ATT2 6 +#define WAIT_PACK_ATT3 7 +#define WAIT_PACK_MOD1 8 +#define WAIT_PACK_MOD2 9 +#define WAIT_PACK_MOD3 10 +#define WAIT_PACK_WPC1 11 +#define WAIT_PACK_WPC2 12 +#define WAIT_PACK_WPC3 13 +#define WAIT_PACK_ALR1 14 +#define WAIT_PACK_ALR2 15 +#define WAIT_PACK_ALR3 16 +#define WAIT_PACK_PRF1 17 +#define WAIT_PACK_PRF2 18 +#define WAIT_PACK_PRF3 19 +#define FLUSH_TITLE1 20 +#define FLUSH_TITLE2 21 +#define FLUSH_TITLE3 22 +#define FLUSH_TITLE4 23 +#define READ_VALUE 24 + +uint8_t i; // working variable +uint8_t state; // currrent state +uint8_t rval, rpack; // received items +uint8_t xval[NB_BUF]; // expected value +uint8_t xpack[NB_BUF]; // expected packet +uint8_t ibuf[NB_BUF]; // subscripts on buffers values +char rbuf[NB_BUF][LG_BUF]; // receive buffers +const char val_unknown[] = "?"; + +void menuViewTelemetryArduPilot1(event_t event); +void menuViewTelemetryArduPilot2(event_t event); +void menuViewTelemetryArduPilot3(event_t event); +void menuViewTelemetryArduPilot4(event_t event); +void menuViewTelemetryArduPilot5(event_t event); +void menuViewTelemetryArduPilot6(event_t event); +void menuViewTelemetryArduPilot7(event_t event); +void menuViewTelemetryArduPilot8(event_t event); +void title(char x); +void initval(uint8_t num, uint8_t pack, uint8_t val); + +#ifndef SIMU +ISR (USART0_RX_vect) +{ + uint8_t rl; +// uint8_t rh; //USART control and Status Register 0 B + uint8_t iostat; //USART control and Status Register 0 A + + rl = UDR0; + iostat = UCSR0A; //USART control and Status Register 0 A + /* + bit 7 6 5 4 3 2 1 0 + RxC0 TxC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 + + RxC0: Receive complete + TXC0: Transmit Complete + UDRE0: USART Data Register Empty + FE0: Frame Error + DOR0: Data OverRun + UPE0: USART Parity Error + U2X0: Double Tx Speed + MPCM0: MultiProcessor Comms Mode +*/ + if (iostat & ((1 << FE0) | (1 << DOR0) | (1 << UPE0))) + { + rl = xpack[0] = xpack[1] = xval[0] = xval[1] = 0; + state = WAIT_PACKET; // restart on error + } + // rh = UCSR0B; //USART control and Status Register 0 B +/* bit 7 6 5 4 3 2 1 0 + RxCIE0 TxCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 + + RxCIE0: Receive complete int enable + TXCIE0: Transmit Complete int enable + UDRIE0: USART Data Register Empty int enable + RXEN0: Rx enable + TXEN0: Tx Enable + UCSZ02: Character Size bit 2 + RXB80: Rx data bit 8 + TXB80: Tx data bit 8 +*/ + switch (state) + { + case WAIT_PACKET: + switch (rl) + { + case PACK_POS: // found a new POS packet + state = WAIT_PACK_POS2; // wait for the 2nd char + break; + case PACK_ATT: // found a new ATT packet + state = WAIT_PACK_ATT2; // wait for the 2nd char + break; + case PACK_MOD: // found a new MOD packet + state = WAIT_PACK_MOD2; // wait for the 2nd char + break; + case PACK_WPC: // found a new WPC packet + state = WAIT_PACK_WPC2; // wait for the 2nd char + break; + case PACK_ALR: // found a new ALR packet + state = WAIT_PACK_ALR2; // wait for the 2nd char + break; + case PACK_PRF: // found a new PRF packet + state = WAIT_PACK_PRF2; // wait for the 2nd char + break; + } + break; + case WAIT_PACK_POS2: // wait for 2nd char + if (rl == PACK_POS) + state = WAIT_PACK_POS3; + else + state = WAIT_PACKET; // restart if not found + break; + case WAIT_PACK_POS3: // wait for 3rd char + if (rl == PACK_POS) // found + { + state = FLUSH_TITLE1; // flush title "LAT:" + rpack = PACK_POS; + rval = 1; + for (i = 0; i < NB_BUF; i++) + ibuf[i] = 0; + } + else + state = WAIT_PACKET; // restart if not found + break; + case WAIT_PACK_ATT2: // wait for 2nd char + if (rl == PACK_ATT) + state = WAIT_PACK_ATT3; + else + state = WAIT_PACKET; // restart if not found + break; + case WAIT_PACK_ATT3: // wait for 3rd char + if (rl == PACK_ATT) + { + state = FLUSH_TITLE1; // flush title "ASP:" + rpack = PACK_ATT; + rval = 1; + for (i = 0; i < NB_BUF; i++) + ibuf[i] = 0; + } + else + state = WAIT_PACKET; // restart if not found + break; + case WAIT_PACK_MOD2: // wait for 2nd char + if (rl == PACK_MOD) + state = WAIT_PACK_MOD3; + else + state = WAIT_PACKET; // restart if not found + break; + case WAIT_PACK_MOD3: // wait for 3rd char + if (rl == PACK_MOD) + { + state = READ_VALUE; // ready to read values from PACK_MOD packet + rpack = PACK_MOD; + rval = 1; + for (i = 0; i < NB_BUF; i++) + ibuf[i] = 0; + } + else + state = WAIT_PACKET; // restart if not found + break; + case WAIT_PACK_WPC2: // wait for 2nd char + if (rl == PACK_WPC) + state = WAIT_PACK_WPC3; + else + state = WAIT_PACKET; // restart if not found + break; + case WAIT_PACK_WPC3: // wait for 3rd char + if (rl == PACK_WPC) + { + state = READ_VALUE; // ready to read values from PACK_WPC packet + rpack = PACK_WPC; + rval = 1; + for (i = 0; i < NB_BUF; i++) + ibuf[i] = 0; + } + else + state = WAIT_PACKET; // restart if not found + break; + case WAIT_PACK_ALR2: // wait for 2nd char + if (rl == PACK_ALR) + state = WAIT_PACK_ALR3; + else + state = WAIT_PACKET; // restart if not found + break; + case WAIT_PACK_ALR3: // wait for 3rd char + if (rl == PACK_ALR) + { + state = READ_VALUE; // ready to read values from PACK_ALR packet + rpack = PACK_ALR; + rval = 1; + for (i = 0; i < NB_BUF; i++) + ibuf[i] = 0; + } + else + state = WAIT_PACKET; // restart if not found + break; + case WAIT_PACK_PRF2: // wait for 2nd char + if (rl == PACK_PRF) + state = WAIT_PACK_PRF3; + else + state = WAIT_PACKET; // restart if not found + break; + case WAIT_PACK_PRF3: // wait for 3rd char + if (rl == PACK_PRF) + { + state = READ_VALUE; // ready to read values from PACK_PRF packet + rpack = PACK_PRF; + rval = 1; + for (i = 0; i < NB_BUF; i++) + ibuf[i] = 0; + } + else + state = WAIT_PACKET; // restart if not found + break; + case FLUSH_TITLE1: // wait for 1st char of title + state = FLUSH_TITLE2; + break; + case FLUSH_TITLE2: // wait for 2nd char + state = FLUSH_TITLE3; + break; + case FLUSH_TITLE3: // wait for 3rd char + state = FLUSH_TITLE4; + break; + case FLUSH_TITLE4: // wait for 4th char + if (rl == TITLE_END) + state = READ_VALUE; + else + state = WAIT_PACKET; // was not a title, wait for the next packet + break; + case READ_VALUE: + switch (rl) + { + case PACK_END: + state = WAIT_PACKET; // packet completed, wait for the next packet + break; + case VAL_END: // comma found, value completed + state = FLUSH_TITLE1; // flush next title + rval++; // and get next value + break; + default: // store the char in the corresponding buffer + for (i = 0; i < NB_BUF; i++) + { // is it the expected value in the expected packet ? + if (rpack == xpack[i] && rval == xval[i] && ibuf[i] < LG_BUF - 1) + { // yes, store the char + rbuf[i] [ibuf[i]] = rl; + ibuf[i]++; + rbuf[i] [ibuf[i]] = 0; + } + } + break; + } + break; + } +} +#endif + +void ARDUPILOT_Init (void) +{ + DDRE &= ~(1 << DDE0); // set RXD0 pin as input + PORTE &= ~(1 << PORTE0); // disable pullup on RXD0 pin + +#ifndef SIMU + // switch (Telem_baud) + // { + // case 1: +#undef BAUD +#define BAUD 38400 +#include + UBRR0H = UBRRH_VALUE; + UBRR0L = UBRRL_VALUE; + // break; + // } + + UCSR0A &= ~(1 << U2X0); // disable double speed operation + // set 8N1 + UCSR0B = 0|(0<< RXCIE0)|(0<, , ); + ------------------------------------- + + That means that "" of "" is stored in the buffer. + The first is 0. + + Here are the packet names and the associated value names: + + Position packet (beginning with "!!!"): "PACK_POS" + value names: "LAT", "LON", "SPD", "CRT", "ALT", "ALH", "CRS", "BER", + "WPN", "DST", "BTV", "RSP", "TOW" + + Attitude packet (beginning with "+++"): "PACK_ATT" + value names: "ASP", "THH", "RLL", "PCH" + + Mode change packet (beginning with "###"): "PACK_MOD" + value name: "MOD" + + Waypoint packet (beginning with "%%%"): "PACK_WPC" + value name: "WPC" + + Alert packet (beginning with "XXX"): "PACK_ALR" + value name: "ALR" + + Performance packet (beginning with "PPP"): "PACK_PRF" + value name: "PRF" + + The buffers are accessed using the macro "VALSTR()", where "" is "0" + for the first buffer, and "1" for the second buffer. + + When a value is missing, it is replaced by the contents of val_unknown ("?"). +*/ +// expecting LAT value in POS packet to be stored in the first buffer + initval (0, PACK_POS, LAT); +// and LON value in POS packet stored in the second buffer + initval (1, PACK_POS, LON); +// title of the screen + title ('1'); + lcdDrawText(5*FW, 1*FH, PSTR(" Latitude")); // line 1 column 5 +// first buffer into line 2 column 2 + lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); + lcdDrawText(5*FW, 4*FH, PSTR(" Longitude")); // line 4 column 5 +// second buffer into line 5 column 2 + lcdDrawText (1*FW, 5*FH, VALSTR(1), APSIZE); +} + +void menuViewTelemetryArduPilot2(event_t event) +{ + switch(event) + { + case EVT_KEY_FIRST(KEY_UP): + chainMenu(menuViewTelemetryArduPilot1); + break; + case EVT_KEY_FIRST(KEY_DOWN): + chainMenu(menuViewTelemetryArduPilot3); + break; + case EVT_KEY_FIRST(KEY_EXIT): + ARDUPILOT_DisableRXD(); + chainMenu(menuMainView); + break; + } + initval (0, PACK_POS, SPD); + initval (1, PACK_POS, CRT); + title ('2'); + lcdDrawText(1*FW, 1*FH, PSTR(" Ground speed")); + lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); + lcdDrawText(1*FW, 4*FH, PSTR(" Climb rate") ); + lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); +} + +void menuViewTelemetryArduPilot3(event_t event) +{ + switch(event) + { + case EVT_KEY_FIRST(KEY_UP): + chainMenu(menuViewTelemetryArduPilot2); + break; + case EVT_KEY_FIRST(KEY_DOWN): + chainMenu(menuViewTelemetryArduPilot4); + break; + case EVT_KEY_FIRST(KEY_EXIT): + ARDUPILOT_DisableRXD(); + chainMenu(menuMainView); + break; + } + initval (0, PACK_POS, ALT); + initval (1, PACK_POS, ALH); + title ('3'); + lcdDrawText(1*FW, 1*FH, PSTR(" Altitude")); + lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); + lcdDrawText(1*FW, 4*FH, PSTR(" Altitude Hold") ); + lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); +} + +void menuViewTelemetryArduPilot4(event_t event) +{ + switch(event) + { + case EVT_KEY_FIRST(KEY_UP): + chainMenu(menuViewTelemetryArduPilot3); + break; + case EVT_KEY_FIRST(KEY_DOWN): + chainMenu(menuViewTelemetryArduPilot5); + break; + case EVT_KEY_FIRST(KEY_EXIT): + ARDUPILOT_DisableRXD(); + chainMenu(menuMainView); + break; + } + initval (0, PACK_POS, CRS); + initval (1, PACK_POS, BER); + title ('4'); + lcdDrawText(1*FW, 1*FH, PSTR(" Course")); + lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); + lcdDrawText(1*FW, 4*FH, PSTR(" Bearing")); + lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); +} + +void menuViewTelemetryArduPilot5(event_t event) +{ + switch(event) + { + case EVT_KEY_FIRST(KEY_UP): + chainMenu(menuViewTelemetryArduPilot4); + break; + case EVT_KEY_FIRST(KEY_DOWN): + chainMenu(menuViewTelemetryArduPilot6); + break; + case EVT_KEY_FIRST(KEY_MENU): + break; + case EVT_KEY_FIRST(KEY_EXIT): + ARDUPILOT_DisableRXD(); + chainMenu(menuMainView); + break; + } + initval (0, PACK_POS, WPN); + initval (1, PACK_POS, DST); + title ('5'); + lcdDrawText(1*FW, 1*FH, PSTR(" Way Point # ")); + lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); + lcdDrawText(1*FW, 4*FH, PSTR(" Distance ")); + lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); +} + +void menuViewTelemetryArduPilot6(event_t event) +{ + switch(event) + { + case EVT_KEY_FIRST(KEY_UP): + chainMenu(menuViewTelemetryArduPilot5); + break; + case EVT_KEY_FIRST(KEY_DOWN): + chainMenu(menuViewTelemetryArduPilot7); + break; + case EVT_KEY_FIRST(KEY_MENU): + break; + case EVT_KEY_FIRST(KEY_EXIT): + ARDUPILOT_DisableRXD(); + chainMenu(menuMainView); + break; + } + initval (0, PACK_ATT, ASP); + initval (1, PACK_ATT, THH); + title ('6'); + lcdDrawText(1*FW, 1*FH, PSTR(" Air Speed ")); + lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); + lcdDrawText(1*FW, 4*FH, PSTR(" Climb Rate ")); + lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); +} + +void menuViewTelemetryArduPilot7(event_t event) +{ + switch(event) + { + case EVT_KEY_FIRST(KEY_UP): + chainMenu(menuViewTelemetryArduPilot6); + break; + case EVT_KEY_FIRST(KEY_DOWN): + chainMenu(menuViewTelemetryArduPilot8); + break; + case EVT_KEY_FIRST(KEY_MENU): + break; + case EVT_KEY_FIRST(KEY_EXIT): + ARDUPILOT_DisableRXD(); + chainMenu(menuMainView); + break; + } + initval (0, PACK_ATT, RLL); + initval (1, PACK_ATT, PCH); + title ('7'); + lcdDrawText(1*FW, 1*FH, PSTR(" Roll Angle")); + lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); + lcdDrawText(1*FW, 4*FH, PSTR(" Pitch Angle")); + lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); +} + +void menuViewTelemetryArduPilot8(event_t event) +{ + switch(event) + { + case EVT_KEY_FIRST(KEY_UP): + chainMenu(menuViewTelemetryArduPilot7); + break; + case EVT_KEY_FIRST(KEY_DOWN): + chainMenu(menuViewTelemetryArduPilot1); + break; + case EVT_KEY_FIRST(KEY_MENU): + break; + case EVT_KEY_FIRST(KEY_EXIT): + ARDUPILOT_DisableRXD(); + chainMenu(menuMainView); + break; + } + initval (0, PACK_MOD, MOD); + initval (1, PACK_WPC, WPC); + title ('8'); + lcdDrawText(1*FW, 1*FH, PSTR(" ArduPilot Mode")); + lcdDrawText (2*FW, 2*FH, VALSTR(0), APSIZE); + lcdDrawText(1*FW, 4*FH, PSTR(" RTL Distance")); + lcdDrawText (2*FW, 5*FH, VALSTR(1), APSIZE); +} + +void title(char x) +{ + lcdDrawText (0, 0, PSTR(" ARDU PILOT Mega ?/8 "), INVERS); + lcdDrawChar(17*FW, 0*FH, x, INVERS); +} + +void initval(uint8_t num, uint8_t pack, uint8_t val) +{ + if (xpack[num] != pack || xval[num] != val) + { + ibuf[num] = rbuf[num][0] = 0; + xpack[num] = pack; + xval[num] = val; + state = WAIT_PACKET; // synchronize to the next packet + } +} + +/* +Without ArduPilot: +Size after: +er9x.elf : +section size addr +.data 164 8388864 +.text 50634 0 +.bss 3485 8389028 +---------------------------------- +With ArduPilot: +Size after: +er9x.elf : +section size addr +.data 166 8388864 +.text 53026 0 +.bss 3517 8389030 +*/ diff --git a/radio/src/telemetry/mavlink.h b/radio/src/telemetry/mavlink.h index e07b239eb..7eb80b070 100644 --- a/radio/src/telemetry/mavlink.h +++ b/radio/src/telemetry/mavlink.h @@ -1,326 +1,326 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/*! \file mavlink.h - * Mavlink include file - */ - -#ifndef _MAVLINK_H_ -#define _MAVLINK_H_ - -#define MAVLINK_USE_CONVENIENCE_FUNCTIONS -#define MAVLINK_COMM_NUM_BUFFERS 1 - -#include "GCS_MAVLink/include_v1.0/mavlink_types.h" -#include "opentx.h" - -extern int8_t mav_heartbeat; -extern mavlink_system_t mavlink_system; -#define LEN_STATUSTEXT 20 -extern char mav_statustext[LEN_STATUSTEXT]; - -extern void SERIAL_start_uart_send(); -extern void SERIAL_end_uart_send(); -extern void SERIAL_send_uart_bytes(const uint8_t * buf, uint16_t len); - -# define MAV_SYSTEM_ID 1 -//mavlink_system.type = 2; //MAV_QUADROTOR; - - -#define MAVLINK_START_UART_SEND(chan,len) SERIAL_start_uart_send() -#define MAVLINK_END_UART_SEND(chan,len) SERIAL_end_uart_send() -#define MAVLINK_SEND_UART_BYTES(chan,buf,len) SERIAL_send_uart_bytes(buf,len) - -#include "GCS_MAVLink/include_v1.0/ardupilotmega/mavlink.h" - -//#define MAVLINK_PARAMS -//#define DUMP_RX_TX -#define ERROR_NUM_MODES 99 -#define ERROR_MAV_ACTION_NB 99 - - -// Auto Pilot modes -// ---------------- -#define AC_STABILIZE 0 // hold level position -#define AC_ACRO 1 // rate control -#define AC_ALT_HOLD 2 // AUTO control -#define AC_AUTO 3 // AUTO control -#define AC_GUIDED 4 // AUTO control -#define AC_LOITER 5 // Hold a single location -#define AC_RTL 6 // AUTO control -#define AC_CIRCLE 7 // AUTO control -#define AC_POSITION 8 // AUTO control -#define AC_LAND 9 // AUTO control -#define AC_OF_LOITER 10 // Hold a single location using optical flow - // sensor -#define AC_TOY_A 11 // THOR Enum for Toy mode -#define AC_TOY_M 12 // THOR Enum for Toy mode -#define AC_NUM_MODES 13 - -// Mavlink airframe types -#define MAVLINK_ARDUCOPTER 0 -#define MAVLINK_ARDUPLANE 1 -#define MAVLINK_INVALID_TYPE 2 - - -#define AP_MANUAL 0 -#define AP_CIRCLE 1 -#define AP_STABILIZE 2 -#define AP_TRAINING 3 -#define AP_FLY_BY_WIRE_A 5 -#define AP_FLY_BY_WIRE_B 6 -#define AP_AUTO 10 -#define AP_RTL 11 -#define AP_LOITER 12 -#define AP_GUIDED 15 -#define AP_INITIALISING 16 -#define AP_NUM_MODES 17 - -static const uint8_t ap_modes_lut[18] PROGMEM = {0,1,2,3,12,4,5,12,12,12,6,7,8,9,12,12,10,11}; - -/* - * Type definitions - */ - -#ifdef MAVLINK_PARAMS - -enum ACM_PARAMS { - RATE_YAW_P, // Rate Yaw - RATE_YAW_I, // Rate Yaw - STB_YAW_P, // Stabilize Yaw - STB_YAW_I, // Stabilize Yaw - RATE_PIT_P, // Rate Pitch - RATE_PIT_I, // Rate Pitch - STB_PIT_P, // Stabilize Pitch - STB_PIT_I, // Stabilize Pitch - RATE_RLL_P, // Rate Roll - RATE_RLL_I, // Rate Roll - STB_RLL_P, // Stabilize Roll - STB_RLL_I, // Stabilize Roll - THR_ALT_P, // THR_BAR, // Altitude Hold - THR_ALT_I, // THR_BAR, // Altitude Hold - HLD_LON_P, // Loiter - HLD_LON_I, // Loiter - HLD_LAT_P, // Loiter - HLD_LAT_I, // Loiter - NAV_LON_P, // Nav WP - NAV_LON_I, // Nav WP - NAV_LAT_P, // Nav WPs - NAV_LAT_I, // Nav WP - NB_PID_PARAMS, // Number of PI Parameters - LOW_VOLT = NB_PID_PARAMS, - IN_VOLT, // - BATT_MONITOR, // - BATT_CAPACITY, // - NB_PARAMS -}; -//#define NB_PID_PARAMS 24 -#define NB_COL_PARAMS 2 -#define NB_ROW_PARAMS ((NB_PARAMS+1)/NB_COL_PARAMS) - -typedef struct MavlinkParam_ { - uint8_t repeat :4; - uint8_t valid :4; - float value; -} MavlinkParam_t; - -#endif - -typedef struct Location_ { - float lat; ///< Latitude in degrees - float lon; ///< Longitude in degrees - float gps_alt; ///< Altitude in meters - float rel_alt; -} Location_t; - -typedef struct Telemetry_Data_ { - // INFOS - uint8_t status; ///< System status flag, see MAV_STATUS ENUM - uint8_t type; - uint8_t autopilot; - uint8_t type_autopilot; - uint16_t packet_drop; - uint16_t packet_fixed; - uint8_t radio_sysid; - uint8_t radio_compid; - uint8_t mav_sysid; - uint8_t mav_compid; - uint8_t mode; - uint32_t custom_mode; - bool active; - uint8_t nav_mode; - uint8_t rcv_control_mode; ///< System mode, see MAV_MODE ENUM in mavlink/include/mavlink_types.h - uint16_t load; ///< Maximum usage in percent of the mainloop time, (0%: 0, 100%: 1000) should be always below 1000 - uint8_t vbat; ///< Battery voltage, in millivolts (1 = 1 millivolt) - uint8_t ibat; ///< Battery voltage, in millivolts (1 = 1 millivolt) - uint8_t rem_bat; ///< Battery voltage, in millivolts (1 = 1 millivolt) - bool vbat_low; - - uint8_t rc_rssi; - uint8_t pc_rssi; - - uint8_t debug; - - // MSG ACTION / ACK - uint8_t req_mode; - int8_t ack_result; - - // GPS - uint8_t fix_type; ///< 0-1: no fix, 2: 2D fix, 3: 3D fix. Some applications will not use the value of this field unless it is at least two, so always correctly fill in the fix. - uint8_t satellites_visible; ///< Number of satellites visible - Location_t loc_current; - float eph; - uint16_t course; - float v; // Ground speed - // Navigation - uint16_t heading; - uint16_t bearing; - -#ifdef MAVLINK_PARAMS - // Params - MavlinkParam_t params[NB_PARAMS]; -#endif - -} Telemetry_Data_t; - -// Telemetry data hold -extern Telemetry_Data_t telemetry_data; - -/* - * Funtion definitions - */ - - - - -#if 0 -extern inline uint8_t MAVLINK_CtrlMode2Action(uint8_t mode) { - uint8_t action; - - return action; -} - -extern inline uint8_t MAVLINK_Action2CtrlMode(uint8_t action) { - uint8_t mode = ERROR_NUM_MODES; - switch (action) { - - return action; - } -} -#endif -void telemetryWakeup(); -void MAVLINK_Init(void); -void menuViewTelemetryMavlink(event_t event); -void MAVLINK10mspoll(uint16_t time); - -#ifdef MAVLINK_PARAMS - -void putsMavlinParams(uint8_t x, uint8_t y, uint8_t idx, uint8_t att); -void setMavlinParamsValue(uint8_t idx, float val); - -inline uint8_t getIdxParam(uint8_t rowIdx, uint8_t colIdx) { - return (rowIdx * NB_COL_PARAMS) + colIdx; -} - -inline MavlinkParam_t * getParam(uint8_t idx) { - return &telemetry_data.params[idx]; -} - -inline float getMavlinParamsValue(uint8_t idx) { - return telemetry_data.params[idx].value; -} - -inline uint8_t isDirtyParamsValue(uint8_t idx) { - return telemetry_data.params[idx].repeat; -} - -inline uint8_t isValidParamsValue(uint8_t idx) { - return telemetry_data.params[idx].valid; -} - -inline float getCoefPrecis(uint8_t precis) { - switch (precis) { - case 1: - return 10.0; - case 2: - return 100.0; - case 3: - return 1000.0; - } - return 1.0; - -} - -inline int16_t getMaxMavlinParamsValue(uint8_t idx) { - int16_t max = 0; - switch (idx) { - case LOW_VOLT: - max = 2500; // 25.0 Volt max - break; - case IN_VOLT: - max = 900; // 7.00 Volt max - break; - case BATT_MONITOR: - max = 3; - break; - case BATT_CAPACITY: - max = 7000; // 7000 mAh max - break; - default: - if (idx < NB_PID_PARAMS) { - max = (idx & 0x01) ? 1000 : 750; - } - break; - } - return max; -} - -inline uint8_t getPrecisMavlinParamsValue(uint8_t idx) { - uint8_t precis = 2; - switch (idx) { - case LOW_VOLT: - precis = 2; - break; - case IN_VOLT: - precis = 2; - break; - case BATT_MONITOR: - precis = 0; - break; - case BATT_CAPACITY: - precis = 0; - break; - default: - if (idx < NB_PID_PARAMS) { - if (idx & 0x01) - precis = 3; - } - break; - } - return precis; -} - -void lcd_outdezFloat(uint8_t x, uint8_t y, float val, uint8_t precis, uint8_t mode); -#endif - -void telemetryPortInit(uint8_t baudrate); - -#endif // _MAVLINK_H_ - +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*! \file mavlink.h + * Mavlink include file + */ + +#ifndef _MAVLINK_H_ +#define _MAVLINK_H_ + +#define MAVLINK_USE_CONVENIENCE_FUNCTIONS +#define MAVLINK_COMM_NUM_BUFFERS 1 + +#include "GCS_MAVLink/include_v1.0/mavlink_types.h" +#include "opentx.h" + +extern int8_t mav_heartbeat; +extern mavlink_system_t mavlink_system; +#define LEN_STATUSTEXT 20 +extern char mav_statustext[LEN_STATUSTEXT]; + +extern void SERIAL_start_uart_send(); +extern void SERIAL_end_uart_send(); +extern void SERIAL_send_uart_bytes(const uint8_t * buf, uint16_t len); + +# define MAV_SYSTEM_ID 1 +//mavlink_system.type = 2; //MAV_QUADROTOR; + + +#define MAVLINK_START_UART_SEND(chan,len) SERIAL_start_uart_send() +#define MAVLINK_END_UART_SEND(chan,len) SERIAL_end_uart_send() +#define MAVLINK_SEND_UART_BYTES(chan,buf,len) SERIAL_send_uart_bytes(buf,len) + +#include "GCS_MAVLink/include_v1.0/ardupilotmega/mavlink.h" + +//#define MAVLINK_PARAMS +//#define DUMP_RX_TX +#define ERROR_NUM_MODES 99 +#define ERROR_MAV_ACTION_NB 99 + + +// Auto Pilot modes +// ---------------- +#define AC_STABILIZE 0 // hold level position +#define AC_ACRO 1 // rate control +#define AC_ALT_HOLD 2 // AUTO control +#define AC_AUTO 3 // AUTO control +#define AC_GUIDED 4 // AUTO control +#define AC_LOITER 5 // Hold a single location +#define AC_RTL 6 // AUTO control +#define AC_CIRCLE 7 // AUTO control +#define AC_POSITION 8 // AUTO control +#define AC_LAND 9 // AUTO control +#define AC_OF_LOITER 10 // Hold a single location using optical flow + // sensor +#define AC_TOY_A 11 // THOR Enum for Toy mode +#define AC_TOY_M 12 // THOR Enum for Toy mode +#define AC_NUM_MODES 13 + +// Mavlink airframe types +#define MAVLINK_ARDUCOPTER 0 +#define MAVLINK_ARDUPLANE 1 +#define MAVLINK_INVALID_TYPE 2 + + +#define AP_MANUAL 0 +#define AP_CIRCLE 1 +#define AP_STABILIZE 2 +#define AP_TRAINING 3 +#define AP_FLY_BY_WIRE_A 5 +#define AP_FLY_BY_WIRE_B 6 +#define AP_AUTO 10 +#define AP_RTL 11 +#define AP_LOITER 12 +#define AP_GUIDED 15 +#define AP_INITIALISING 16 +#define AP_NUM_MODES 17 + +static const uint8_t ap_modes_lut[18] PROGMEM = {0,1,2,3,12,4,5,12,12,12,6,7,8,9,12,12,10,11}; + +/* + * Type definitions + */ + +#ifdef MAVLINK_PARAMS + +enum ACM_PARAMS { + RATE_YAW_P, // Rate Yaw + RATE_YAW_I, // Rate Yaw + STB_YAW_P, // Stabilize Yaw + STB_YAW_I, // Stabilize Yaw + RATE_PIT_P, // Rate Pitch + RATE_PIT_I, // Rate Pitch + STB_PIT_P, // Stabilize Pitch + STB_PIT_I, // Stabilize Pitch + RATE_RLL_P, // Rate Roll + RATE_RLL_I, // Rate Roll + STB_RLL_P, // Stabilize Roll + STB_RLL_I, // Stabilize Roll + THR_ALT_P, // THR_BAR, // Altitude Hold + THR_ALT_I, // THR_BAR, // Altitude Hold + HLD_LON_P, // Loiter + HLD_LON_I, // Loiter + HLD_LAT_P, // Loiter + HLD_LAT_I, // Loiter + NAV_LON_P, // Nav WP + NAV_LON_I, // Nav WP + NAV_LAT_P, // Nav WPs + NAV_LAT_I, // Nav WP + NB_PID_PARAMS, // Number of PI Parameters + LOW_VOLT = NB_PID_PARAMS, + IN_VOLT, // + BATT_MONITOR, // + BATT_CAPACITY, // + NB_PARAMS +}; +//#define NB_PID_PARAMS 24 +#define NB_COL_PARAMS 2 +#define NB_ROW_PARAMS ((NB_PARAMS+1)/NB_COL_PARAMS) + +typedef struct MavlinkParam_ { + uint8_t repeat :4; + uint8_t valid :4; + float value; +} MavlinkParam_t; + +#endif + +typedef struct Location_ { + float lat; ///< Latitude in degrees + float lon; ///< Longitude in degrees + float gps_alt; ///< Altitude in meters + float rel_alt; +} Location_t; + +typedef struct Telemetry_Data_ { + // INFOS + uint8_t status; ///< System status flag, see MAV_STATUS ENUM + uint8_t type; + uint8_t autopilot; + uint8_t type_autopilot; + uint16_t packet_drop; + uint16_t packet_fixed; + uint8_t radio_sysid; + uint8_t radio_compid; + uint8_t mav_sysid; + uint8_t mav_compid; + uint8_t mode; + uint32_t custom_mode; + bool active; + uint8_t nav_mode; + uint8_t rcv_control_mode; ///< System mode, see MAV_MODE ENUM in mavlink/include/mavlink_types.h + uint16_t load; ///< Maximum usage in percent of the mainloop time, (0%: 0, 100%: 1000) should be always below 1000 + uint8_t vbat; ///< Battery voltage, in millivolts (1 = 1 millivolt) + uint8_t ibat; ///< Battery voltage, in millivolts (1 = 1 millivolt) + uint8_t rem_bat; ///< Battery voltage, in millivolts (1 = 1 millivolt) + bool vbat_low; + + uint8_t rc_rssi; + uint8_t pc_rssi; + + uint8_t debug; + + // MSG ACTION / ACK + uint8_t req_mode; + int8_t ack_result; + + // GPS + uint8_t fix_type; ///< 0-1: no fix, 2: 2D fix, 3: 3D fix. Some applications will not use the value of this field unless it is at least two, so always correctly fill in the fix. + uint8_t satellites_visible; ///< Number of satellites visible + Location_t loc_current; + float eph; + uint16_t course; + float v; // Ground speed + // Navigation + uint16_t heading; + uint16_t bearing; + +#ifdef MAVLINK_PARAMS + // Params + MavlinkParam_t params[NB_PARAMS]; +#endif + +} Telemetry_Data_t; + +// Telemetry data hold +extern Telemetry_Data_t telemetry_data; + +/* + * Funtion definitions + */ + + + + +#if 0 +extern inline uint8_t MAVLINK_CtrlMode2Action(uint8_t mode) { + uint8_t action; + + return action; +} + +extern inline uint8_t MAVLINK_Action2CtrlMode(uint8_t action) { + uint8_t mode = ERROR_NUM_MODES; + switch (action) { + + return action; + } +} +#endif +void telemetryWakeup(); +void MAVLINK_Init(void); +void menuViewTelemetryMavlink(event_t event); +void MAVLINK10mspoll(uint16_t time); + +#ifdef MAVLINK_PARAMS + +void putsMavlinParams(uint8_t x, uint8_t y, uint8_t idx, uint8_t att); +void setMavlinParamsValue(uint8_t idx, float val); + +inline uint8_t getIdxParam(uint8_t rowIdx, uint8_t colIdx) { + return (rowIdx * NB_COL_PARAMS) + colIdx; +} + +inline MavlinkParam_t * getParam(uint8_t idx) { + return &telemetry_data.params[idx]; +} + +inline float getMavlinParamsValue(uint8_t idx) { + return telemetry_data.params[idx].value; +} + +inline uint8_t isDirtyParamsValue(uint8_t idx) { + return telemetry_data.params[idx].repeat; +} + +inline uint8_t isValidParamsValue(uint8_t idx) { + return telemetry_data.params[idx].valid; +} + +inline float getCoefPrecis(uint8_t precis) { + switch (precis) { + case 1: + return 10.0; + case 2: + return 100.0; + case 3: + return 1000.0; + } + return 1.0; + +} + +inline int16_t getMaxMavlinParamsValue(uint8_t idx) { + int16_t max = 0; + switch (idx) { + case LOW_VOLT: + max = 2500; // 25.0 Volt max + break; + case IN_VOLT: + max = 900; // 7.00 Volt max + break; + case BATT_MONITOR: + max = 3; + break; + case BATT_CAPACITY: + max = 7000; // 7000 mAh max + break; + default: + if (idx < NB_PID_PARAMS) { + max = (idx & 0x01) ? 1000 : 750; + } + break; + } + return max; +} + +inline uint8_t getPrecisMavlinParamsValue(uint8_t idx) { + uint8_t precis = 2; + switch (idx) { + case LOW_VOLT: + precis = 2; + break; + case IN_VOLT: + precis = 2; + break; + case BATT_MONITOR: + precis = 0; + break; + case BATT_CAPACITY: + precis = 0; + break; + default: + if (idx < NB_PID_PARAMS) { + if (idx & 0x01) + precis = 3; + } + break; + } + return precis; +} + +void lcd_outdezFloat(uint8_t x, uint8_t y, float val, uint8_t precis, uint8_t mode); +#endif + +void telemetryPortInit(uint8_t baudrate); + +#endif // _MAVLINK_H_ + diff --git a/radio/src/templates.h b/radio/src/templates.h index 1e5a33475..aeec86261 100644 --- a/radio/src/templates.h +++ b/radio/src/templates.h @@ -1,80 +1,80 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * ============================================================ - * Templates file - * - * eccpm - * crow - * throttle cut - * flaperon - * elevon - * v-tail - * throttle hold - * Aileron Differential - * Spoilers - * Snap Roll - * ELE->Flap - * Flap->ELE - * - */ - -#ifndef _TEMPLATES_H_ -#define _TEMPLATES_H_ - -#include - -#define STK_RUD 1 -#define STK_ELE 2 -#define STK_THR 3 -#define STK_AIL 4 -#define STK_P1 5 -#define STK_P2 6 -#define STK_P3 7 - -#define CV(x) (CURVE_BASE+(x)-1) -#define CC(x) (MIXSRC_Rud - 1 + channel_order(x)) // need to invert this to work with dest - -#if defined(PCBTARANIS) - #define mixSetCurve(mix, idx) mix->curve.type=CURVE_REF_CUSTOM; mix->curve.value=idx -#else - #define mixSetCurve(mix, idx) mix->curveMode=MODE_CURVE; mix->curveParam=CURVE_BASE+idx -#endif - -enum Templates { - TMPL_CLEAR_MIXES, - TMPL_SIMPLE_4CH, - TMPL_STI_THR_CUT, - TMPL_V_TAIL, - TMPL_ELEVON_DELTA, - TMPL_ECCPM, - TMPL_HELI_SETUP, - TMPL_SERVO_TEST, - TMPL_COUNT -}; - -void clearMixes(); -void clearCurves(); -void applyTemplate(uint8_t idx); - -#endif // _TEMPLATES_H_ - - +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * ============================================================ + * Templates file + * + * eccpm + * crow + * throttle cut + * flaperon + * elevon + * v-tail + * throttle hold + * Aileron Differential + * Spoilers + * Snap Roll + * ELE->Flap + * Flap->ELE + * + */ + +#ifndef _TEMPLATES_H_ +#define _TEMPLATES_H_ + +#include + +#define STK_RUD 1 +#define STK_ELE 2 +#define STK_THR 3 +#define STK_AIL 4 +#define STK_P1 5 +#define STK_P2 6 +#define STK_P3 7 + +#define CV(x) (CURVE_BASE+(x)-1) +#define CC(x) (MIXSRC_Rud - 1 + channel_order(x)) // need to invert this to work with dest + +#if defined(PCBTARANIS) + #define mixSetCurve(mix, idx) mix->curve.type=CURVE_REF_CUSTOM; mix->curve.value=idx +#else + #define mixSetCurve(mix, idx) mix->curveMode=MODE_CURVE; mix->curveParam=CURVE_BASE+idx +#endif + +enum Templates { + TMPL_CLEAR_MIXES, + TMPL_SIMPLE_4CH, + TMPL_STI_THR_CUT, + TMPL_V_TAIL, + TMPL_ELEVON_DELTA, + TMPL_ECCPM, + TMPL_HELI_SETUP, + TMPL_SERVO_TEST, + TMPL_COUNT +}; + +void clearMixes(); +void clearCurves(); +void applyTemplate(uint8_t idx); + +#endif // _TEMPLATES_H_ + + diff --git a/radio/src/thirdparty/CoOS/OsConfig.h b/radio/src/thirdparty/CoOS/OsConfig.h index d07972914..c56e47529 100644 --- a/radio/src/thirdparty/CoOS/OsConfig.h +++ b/radio/src/thirdparty/CoOS/OsConfig.h @@ -1,314 +1,314 @@ -/** - ******************************************************************************* - * @file OsConfig.h - * @version V1.1.6 - * @date 2014.05.23 - * @brief This file use by user to configuration CooCox CoOS. - * @note Ensure you have knew every item before modify this file. - ******************************************************************************* - * @copy - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - * - *

© COPYRIGHT 2014 CooCox

- ******************************************************************************* - */ - - -#ifndef _CONFIG_H -#define _CONFIG_H - - -/*!< -Defines chip type,cortex-m3(1),cortex-m0(2), cortex-m4 without FPU(1), cortex-m4 with FPU(3) -*/ - -#if defined(STM32F4) - #define CFG_CHIP_TYPE (3) // this add support for hardware floating point unit (saves registers on stack) -#else - #define CFG_CHIP_TYPE (1) -#endif - -/*!< -Defines the lowest priority that be assigned. -*/ -#define CFG_LOWEST_PRIO (64) - -/*!< -Max number of tasks that can be running. -*/ -#define CFG_MAX_USER_TASKS (5) - -/*!< -Idle task stack size(word). -*/ -#if CFG_CHIP_TYPE == 3 -#define CFG_IDLE_STACK_SIZE (58) -#else -#define CFG_IDLE_STACK_SIZE (25) -#endif - -/*!< -System frequency (Hz). -*/ -#if defined(STM32F4) -#define CFG_CPU_FREQ (168000000) -#elif defined(STM32) -#define CFG_CPU_FREQ (120000000) -#else -#define CFG_CPU_FREQ (36000000) // TODO check if really correct for sky9x? -#endif - -/*!< -systick frequency (Hz). -*/ -#define CFG_SYSTICK_FREQ (500) - -/*!< -max systerm api call num in ISR. -*/ -#define CFG_MAX_SERVICE_REQUEST (5) - -/*!< -Enable(1) or disable(0) order list schedule. -If disable(0),CoOS use Binary-Scheduling Algorithm. -*/ -#if (CFG_MAX_USER_TASKS) <15 -#define CFG_ORDER_LIST_SCHEDULE_EN (1) -#else -#define CFG_ORDER_LIST_SCHEDULE_EN (0) -#endif - - -/*!< -Enable(1) or disable(0) Round-Robin Task switching. -*/ -#define CFG_ROBIN_EN (1) - -/*!< -Default slice of task. -*/ -#if CFG_ROBIN_EN > 0 -#define CFG_TIME_SLICE (10) -#endif - - -/*----------------------- Schedule model Config -----------------------------*/ -/*!< -Enable(1) or disable(0) all waiting function. -Include sem,mailbox,queue,flag,mutex,delay modules. -If CFG_TASK_WAITTING_EN=0,all these modules are disable. -*/ -#define CFG_TASK_WAITTING_EN (1) - -/*!< -Dynamic task scheduling(1) or Static Task Scheduling(0) model. -If in Static Task Scheduling model(0),cannot creat task and change task priority -after coocox os start running. In Dynamic Task Scheduling model(1), all these can. -When task terminated, if in Static Task Scheduling model(0), -CoOS do not recovered task resources, and you can activate it again. -But in Dynamic Task Scheduling model(1),task resources will be recovered. -If in Static Task Scheduling model(0),mutex module can not be used, as this model don't -support to change task priority while CoOS running. -*/ -#define CFG_TASK_SCHEDULE_EN (1) - - -/*---------------------- Task Management Config -----------------------------*/ -/*!< -Enable(1) or disable(0) CoSetPriority() API. -*/ -#if CFG_TASK_SCHEDULE_EN >0 -#define CFG_PRIORITY_SET_EN (1) -#endif - -/*!< -Enable(1) or disable(0) CoAwakeTask() and CoSuspendTask() API. -*/ -#define CFG_TASK_SUSPEND_EN (0) - - -/*---------------------- Debug Management Config ----------------------------*/ -/*!< -Enable(1) or disable(0) parameter checkout . -*/ -#define CFG_PAR_CHECKOUT_EN (0) - -/*!< -Enable(1) or disable(0) stack overflow checkout . -*/ -#define CFG_STK_CHECKOUT_EN (0) - - - -/*---------------------- Memory Management Config ----------------------------*/ -/*!< -Enable(1) or disable(0) memory management. -*/ -#define CFG_MM_EN (0) - -/*!< -Max number of memory.(must be less than 32). -*/ -#if CFG_MM_EN >0 -#define CFG_MAX_MM (2) -#endif - - - -/*-------------------- Kernel heap Management Config -------------------------*/ -/*!< -Enable(1) or disable(0) kernel heap management. -*/ -#define CFG_KHEAP_EN (0) - -/*!< -Kernel heap size(word). -*/ -#if CFG_KHEAP_EN >0 -#define KHEAP_SIZE (50) -#endif - - - -/*---------------------- Time Management Config -----------------------------*/ -/*!< -Enable(1) or disable(0) TimeDelay() API. -*/ -#if CFG_TASK_WAITTING_EN >0 -#define CFG_TIME_DELAY_EN (0) -#endif - - -/*---------------------- Timer Management Config ----------------------------*/ -/*!< -Enable(1) or disable(0) timer management. -*/ -#define CFG_TMR_EN (1) - -/*!< -Specify max number timer.(must be less than 32) -*/ -#if CFG_TMR_EN >0 -#define CFG_MAX_TMR (2) -#endif - - -/*---------------------- Event Management Config ----------------------------*/ -/*!< -Enable(1) or disable(0) events management, -events including semaphore,mailbox,queue. -*/ -#if CFG_TASK_WAITTING_EN > 0 -#define CFG_EVENT_EN (1) -#endif - -#if CFG_EVENT_EN > 0 -/*!< -Event sort type.(1)FIFO (2)PRI (3)FIFO+PRI -*/ -#define CFG_EVENT_SORT (3) - -/*!< -Max number of event.(must be less than 255) -Event = semaphore + mailbox + queue; -*/ -#define CFG_MAX_EVENT (10) - -/*!< -Enable(1) or disable(0) semaphore management. -*/ -#define CFG_SEM_EN (0) - -/*!< -Enable(1) or disable(0) mailbox management. -*/ -#define CFG_MAILBOX_EN (0) - -/*!< -Enable(1) or disable(0) queue management. -*/ -#define CFG_QUEUE_EN (0) - -/*!< -Max number of queue.(less than CFG_MAX_EVENT). -*/ -#if CFG_QUEUE_EN >0 -#define CFG_MAX_QUEUE (2) -#endif // CFG_QUEUE_EN - -#endif // CFG_EVENT_EN - - - -/*----------------------- Flag Management Config ----------------------------*/ -/*!< -Enable(1) or disable(0) flag management. -Max number of flag is 32. -*/ -#if CFG_TASK_WAITTING_EN > 0 -#define CFG_FLAG_EN (1) -#endif - - -/*---------------------- Mutex Management Config ----------------------------*/ -/*!< -Enable(1) or disable(0) mutex management. -*/ -#if CFG_TASK_WAITTING_EN > 0 -#if CFG_TASK_SCHEDULE_EN > 0 -#define CFG_MUTEX_EN (1) -#endif -#endif - - -/*!< -Max number of mutex.(must be less than 255). -*/ -#if CFG_MUTEX_EN >0 -#define CFG_MAX_MUTEX (10) -#endif - -/*---------------------- Utility Management Config --------------------------*/ -/*!< -Enable(1) or disable(0) utility management. -*/ -#define CFG_UTILITY_EN (0) - -#if CFG_UTILITY_EN >0 - -/*!< -Enable(1) or disable(0) TickToTime() utility -*/ -#define CFG_TICK_TO_TIME_EN (1) -/*!< -Enable(1) or disable(0) TimeToTick() utility -*/ -#define CFG_TIME_TO_TICK_EN (1) -#endif - - -#endif // _CONFIG_H +/** + ******************************************************************************* + * @file OsConfig.h + * @version V1.1.6 + * @date 2014.05.23 + * @brief This file use by user to configuration CooCox CoOS. + * @note Ensure you have knew every item before modify this file. + ******************************************************************************* + * @copy + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + *

© COPYRIGHT 2014 CooCox

+ ******************************************************************************* + */ + + +#ifndef _CONFIG_H +#define _CONFIG_H + + +/*!< +Defines chip type,cortex-m3(1),cortex-m0(2), cortex-m4 without FPU(1), cortex-m4 with FPU(3) +*/ + +#if defined(STM32F4) + #define CFG_CHIP_TYPE (3) // this add support for hardware floating point unit (saves registers on stack) +#else + #define CFG_CHIP_TYPE (1) +#endif + +/*!< +Defines the lowest priority that be assigned. +*/ +#define CFG_LOWEST_PRIO (64) + +/*!< +Max number of tasks that can be running. +*/ +#define CFG_MAX_USER_TASKS (5) + +/*!< +Idle task stack size(word). +*/ +#if CFG_CHIP_TYPE == 3 +#define CFG_IDLE_STACK_SIZE (58) +#else +#define CFG_IDLE_STACK_SIZE (25) +#endif + +/*!< +System frequency (Hz). +*/ +#if defined(STM32F4) +#define CFG_CPU_FREQ (168000000) +#elif defined(STM32) +#define CFG_CPU_FREQ (120000000) +#else +#define CFG_CPU_FREQ (36000000) // TODO check if really correct for sky9x? +#endif + +/*!< +systick frequency (Hz). +*/ +#define CFG_SYSTICK_FREQ (500) + +/*!< +max systerm api call num in ISR. +*/ +#define CFG_MAX_SERVICE_REQUEST (5) + +/*!< +Enable(1) or disable(0) order list schedule. +If disable(0),CoOS use Binary-Scheduling Algorithm. +*/ +#if (CFG_MAX_USER_TASKS) <15 +#define CFG_ORDER_LIST_SCHEDULE_EN (1) +#else +#define CFG_ORDER_LIST_SCHEDULE_EN (0) +#endif + + +/*!< +Enable(1) or disable(0) Round-Robin Task switching. +*/ +#define CFG_ROBIN_EN (1) + +/*!< +Default slice of task. +*/ +#if CFG_ROBIN_EN > 0 +#define CFG_TIME_SLICE (10) +#endif + + +/*----------------------- Schedule model Config -----------------------------*/ +/*!< +Enable(1) or disable(0) all waiting function. +Include sem,mailbox,queue,flag,mutex,delay modules. +If CFG_TASK_WAITTING_EN=0,all these modules are disable. +*/ +#define CFG_TASK_WAITTING_EN (1) + +/*!< +Dynamic task scheduling(1) or Static Task Scheduling(0) model. +If in Static Task Scheduling model(0),cannot creat task and change task priority +after coocox os start running. In Dynamic Task Scheduling model(1), all these can. +When task terminated, if in Static Task Scheduling model(0), +CoOS do not recovered task resources, and you can activate it again. +But in Dynamic Task Scheduling model(1),task resources will be recovered. +If in Static Task Scheduling model(0),mutex module can not be used, as this model don't +support to change task priority while CoOS running. +*/ +#define CFG_TASK_SCHEDULE_EN (1) + + +/*---------------------- Task Management Config -----------------------------*/ +/*!< +Enable(1) or disable(0) CoSetPriority() API. +*/ +#if CFG_TASK_SCHEDULE_EN >0 +#define CFG_PRIORITY_SET_EN (1) +#endif + +/*!< +Enable(1) or disable(0) CoAwakeTask() and CoSuspendTask() API. +*/ +#define CFG_TASK_SUSPEND_EN (0) + + +/*---------------------- Debug Management Config ----------------------------*/ +/*!< +Enable(1) or disable(0) parameter checkout . +*/ +#define CFG_PAR_CHECKOUT_EN (0) + +/*!< +Enable(1) or disable(0) stack overflow checkout . +*/ +#define CFG_STK_CHECKOUT_EN (0) + + + +/*---------------------- Memory Management Config ----------------------------*/ +/*!< +Enable(1) or disable(0) memory management. +*/ +#define CFG_MM_EN (0) + +/*!< +Max number of memory.(must be less than 32). +*/ +#if CFG_MM_EN >0 +#define CFG_MAX_MM (2) +#endif + + + +/*-------------------- Kernel heap Management Config -------------------------*/ +/*!< +Enable(1) or disable(0) kernel heap management. +*/ +#define CFG_KHEAP_EN (0) + +/*!< +Kernel heap size(word). +*/ +#if CFG_KHEAP_EN >0 +#define KHEAP_SIZE (50) +#endif + + + +/*---------------------- Time Management Config -----------------------------*/ +/*!< +Enable(1) or disable(0) TimeDelay() API. +*/ +#if CFG_TASK_WAITTING_EN >0 +#define CFG_TIME_DELAY_EN (0) +#endif + + +/*---------------------- Timer Management Config ----------------------------*/ +/*!< +Enable(1) or disable(0) timer management. +*/ +#define CFG_TMR_EN (1) + +/*!< +Specify max number timer.(must be less than 32) +*/ +#if CFG_TMR_EN >0 +#define CFG_MAX_TMR (2) +#endif + + +/*---------------------- Event Management Config ----------------------------*/ +/*!< +Enable(1) or disable(0) events management, +events including semaphore,mailbox,queue. +*/ +#if CFG_TASK_WAITTING_EN > 0 +#define CFG_EVENT_EN (1) +#endif + +#if CFG_EVENT_EN > 0 +/*!< +Event sort type.(1)FIFO (2)PRI (3)FIFO+PRI +*/ +#define CFG_EVENT_SORT (3) + +/*!< +Max number of event.(must be less than 255) +Event = semaphore + mailbox + queue; +*/ +#define CFG_MAX_EVENT (10) + +/*!< +Enable(1) or disable(0) semaphore management. +*/ +#define CFG_SEM_EN (0) + +/*!< +Enable(1) or disable(0) mailbox management. +*/ +#define CFG_MAILBOX_EN (0) + +/*!< +Enable(1) or disable(0) queue management. +*/ +#define CFG_QUEUE_EN (0) + +/*!< +Max number of queue.(less than CFG_MAX_EVENT). +*/ +#if CFG_QUEUE_EN >0 +#define CFG_MAX_QUEUE (2) +#endif // CFG_QUEUE_EN + +#endif // CFG_EVENT_EN + + + +/*----------------------- Flag Management Config ----------------------------*/ +/*!< +Enable(1) or disable(0) flag management. +Max number of flag is 32. +*/ +#if CFG_TASK_WAITTING_EN > 0 +#define CFG_FLAG_EN (1) +#endif + + +/*---------------------- Mutex Management Config ----------------------------*/ +/*!< +Enable(1) or disable(0) mutex management. +*/ +#if CFG_TASK_WAITTING_EN > 0 +#if CFG_TASK_SCHEDULE_EN > 0 +#define CFG_MUTEX_EN (1) +#endif +#endif + + +/*!< +Max number of mutex.(must be less than 255). +*/ +#if CFG_MUTEX_EN >0 +#define CFG_MAX_MUTEX (10) +#endif + +/*---------------------- Utility Management Config --------------------------*/ +/*!< +Enable(1) or disable(0) utility management. +*/ +#define CFG_UTILITY_EN (0) + +#if CFG_UTILITY_EN >0 + +/*!< +Enable(1) or disable(0) TickToTime() utility +*/ +#define CFG_TICK_TO_TIME_EN (1) +/*!< +Enable(1) or disable(0) TimeToTick() utility +*/ +#define CFG_TIME_TO_TICK_EN (1) +#endif + + +#endif // _CONFIG_H diff --git a/radio/src/thirdparty/FatFs/00history.txt b/radio/src/thirdparty/FatFs/00history.txt index 49aac282b..ab22088e4 100644 --- a/radio/src/thirdparty/FatFs/00history.txt +++ b/radio/src/thirdparty/FatFs/00history.txt @@ -1,279 +1,279 @@ ----------------------------------------------------------------------------- - Revision history of FatFs module ----------------------------------------------------------------------------- - -R0.00 (February 26, 2006) - - Prototype. - - - -R0.01 (April 29, 2006) - - The first release. - - - -R0.02 (June 01, 2006) - - Added FAT12 support. - Removed unbuffered mode. - Fixed a problem on small (<32M) partition. - - - -R0.02a (June 10, 2006) - - Added a configuration option (_FS_MINIMUM). - - - -R0.03 (September 22, 2006) - - Added f_rename(). - Changed option _FS_MINIMUM to _FS_MINIMIZE. - - - -R0.03a (December 11, 2006) - - Improved cluster scan algorithm to write files fast. - Fixed f_mkdir() creates incorrect directory on FAT32. - - - -R0.04 (February 04, 2007) - - Added f_mkfs(). - Supported multiple drive system. - Changed some interfaces for multiple drive system. - Changed f_mountdrv() to f_mount(). - - - -R0.04a (April 01, 2007) - - Supported multiple partitions on a physical drive. - Added a capability of extending file size to f_lseek(). - Added minimization level 3. - Fixed an endian sensitive code in f_mkfs(). - - - -R0.04b (May 05, 2007) - - Added a configuration option _USE_NTFLAG. - Added FSINFO support. - Fixed DBCS name can result FR_INVALID_NAME. - Fixed short seek (<= csize) collapses the file object. - - - -R0.05 (August 25, 2007) - - Changed arguments of f_read(), f_write() and f_mkfs(). - Fixed f_mkfs() on FAT32 creates incorrect FSINFO. - Fixed f_mkdir() on FAT32 creates incorrect directory. - - - -R0.05a (February 03, 2008) - - Added f_truncate() and f_utime(). - Fixed off by one error at FAT sub-type determination. - Fixed btr in f_read() can be mistruncated. - Fixed cached sector is not flushed when create and close without write. - - - -R0.06 (April 01, 2008) - - Added fputc(), fputs(), fprintf() and fgets(). - Improved performance of f_lseek() on moving to the same or following cluster. - - - -R0.07 (April 01, 2009) - - Merged Tiny-FatFs as a configuration option. (_FS_TINY) - Added long file name feature. (_USE_LFN) - Added multiple code page feature. (_CODE_PAGE) - Added re-entrancy for multitask operation. (_FS_REENTRANT) - Added auto cluster size selection to f_mkfs(). - Added rewind option to f_readdir(). - Changed result code of critical errors. - Renamed string functions to avoid name collision. - - - -R0.07a (April 14, 2009) - - Septemberarated out OS dependent code on reentrant cfg. - Added multiple sector size feature. - - - -R0.07c (June 21, 2009) - - Fixed f_unlink() can return FR_OK on error. - Fixed wrong cache control in f_lseek(). - Added relative path feature. - Added f_chdir() and f_chdrive(). - Added proper case conversion to extended character. - - - -R0.07e (November 03, 2009) - - Septemberarated out configuration options from ff.h to ffconf.h. - Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH. - Fixed name matching error on the 13 character boundary. - Added a configuration option, _LFN_UNICODE. - Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. - - - -R0.08 (May 15, 2010) - - Added a memory configuration option. (_USE_LFN = 3) - Added file lock feature. (_FS_SHARE) - Added fast seek feature. (_USE_FASTSEEK) - Changed some types on the API, XCHAR->TCHAR. - Changed .fname in the FILINFO structure on Unicode cfg. - String functions support UTF-8 encoding files on Unicode cfg. - - - -R0.08a (August 16, 2010) - - Added f_getcwd(). (_FS_RPATH = 2) - Added sector erase feature. (_USE_ERASE) - Moved file lock semaphore table from fs object to the bss. - Fixed f_mkfs() creates wrong FAT32 volume. - - - -R0.08b (January 15, 2011) - - Fast seek feature is also applied to f_read() and f_write(). - f_lseek() reports required table size on creating CLMP. - Extended format syntax of f_printf(). - Ignores duplicated directory separators in given path name. - - - -R0.09 (September 06, 2011) - - f_mkfs() supports multiple partition to complete the multiple partition feature. - Added f_fdisk(). - - - -R0.09a (August 27, 2012) - - Changed f_open() and f_opendir() reject null object pointer to avoid crash. - Changed option name _FS_SHARE to _FS_LOCK. - Fixed assertion failure due to OS/2 EA on FAT12/16 volume. - - - -R0.09b (January 24, 2013) - - Added f_setlabel() and f_getlabel(). - - - -R0.10 (October 02, 2013) - - Added selection of character encoding on the file. (_STRF_ENCODE) - Added f_closedir(). - Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) - Added forced mount feature with changes of f_mount(). - Improved behavior of volume auto detection. - Improved write throughput of f_puts() and f_printf(). - Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). - Fixed f_write() can be truncated when the file size is close to 4GB. - Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error. - - - -R0.10a (January 15, 2014) - - Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID) - Added a configuration option of minimum sector size. (_MIN_SS) - 2nd argument of f_rename() can have a drive number and it will be ignored. - Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10) - Fixed f_close() invalidates the file object without volume lock. - Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10) - Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07) - - - -R0.10b (May 19, 2014) - - Fixed a hard error in the disk I/O layer can collapse the directory entry. - Fixed LFN entry is not deleted on delete/rename an object with lossy converted SFN. (appeared at R0.07) - - - -R0.10c (November 09, 2014) - - Added a configuration option for the platforms without RTC. (_FS_NORTC) - Changed option name _USE_ERASE to _USE_TRIM. - Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b) - Fixed a potential problem of FAT access that can appear on disk error. - Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08) - - - -R0.11 (February 09, 2015) - - Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND) - Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c) - Fixed _FS_NORTC option does not work properly. (appeared at R0.10c) - - - -R0.11a (September 05, 2015) - - Fixed wrong media change can lead a deadlock at thread-safe configuration. - Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE) - Removed some code pages actually not exist on the standard systems. (_CODE_PAGE) - Fixed errors in the case conversion teble of code page 437 and 850 (ff.c). - Fixed errors in the case conversion teble of Unicode (cc*.c). - - - -R0.12 (April 12, 2016) - - Added support for exFAT file system. (_FS_EXFAT) - Added f_expand(). (_USE_EXPAND) - Changed some members in FINFO structure and behavior of f_readdir(). - Added an option _USE_CHMOD. - Removed an option _WORD_ACCESS. - Fixed errors in the case conversion table of Unicode (cc*.c). - - - -R0.12a (July 10, 2016) - - Added support for creating exFAT volume with some changes of f_mkfs(). - Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed. - f_forward() is available regardless of _FS_TINY. - Fixed f_mkfs() creates wrong volume. (appeared at R0.12) - Fixed wrong memory read in create_name(). (appeared at R0.12) - Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD. - - - -R0.12b (September 04, 2016) - - Improved f_rename() to be able to rename objects with the same name but case. - Fixed an error in the case conversion teble of code page 866. (ff.c) - Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12) - Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12) - Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12) - Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12) - Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12) - Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12) - +---------------------------------------------------------------------------- + Revision history of FatFs module +---------------------------------------------------------------------------- + +R0.00 (February 26, 2006) + + Prototype. + + + +R0.01 (April 29, 2006) + + The first release. + + + +R0.02 (June 01, 2006) + + Added FAT12 support. + Removed unbuffered mode. + Fixed a problem on small (<32M) partition. + + + +R0.02a (June 10, 2006) + + Added a configuration option (_FS_MINIMUM). + + + +R0.03 (September 22, 2006) + + Added f_rename(). + Changed option _FS_MINIMUM to _FS_MINIMIZE. + + + +R0.03a (December 11, 2006) + + Improved cluster scan algorithm to write files fast. + Fixed f_mkdir() creates incorrect directory on FAT32. + + + +R0.04 (February 04, 2007) + + Added f_mkfs(). + Supported multiple drive system. + Changed some interfaces for multiple drive system. + Changed f_mountdrv() to f_mount(). + + + +R0.04a (April 01, 2007) + + Supported multiple partitions on a physical drive. + Added a capability of extending file size to f_lseek(). + Added minimization level 3. + Fixed an endian sensitive code in f_mkfs(). + + + +R0.04b (May 05, 2007) + + Added a configuration option _USE_NTFLAG. + Added FSINFO support. + Fixed DBCS name can result FR_INVALID_NAME. + Fixed short seek (<= csize) collapses the file object. + + + +R0.05 (August 25, 2007) + + Changed arguments of f_read(), f_write() and f_mkfs(). + Fixed f_mkfs() on FAT32 creates incorrect FSINFO. + Fixed f_mkdir() on FAT32 creates incorrect directory. + + + +R0.05a (February 03, 2008) + + Added f_truncate() and f_utime(). + Fixed off by one error at FAT sub-type determination. + Fixed btr in f_read() can be mistruncated. + Fixed cached sector is not flushed when create and close without write. + + + +R0.06 (April 01, 2008) + + Added fputc(), fputs(), fprintf() and fgets(). + Improved performance of f_lseek() on moving to the same or following cluster. + + + +R0.07 (April 01, 2009) + + Merged Tiny-FatFs as a configuration option. (_FS_TINY) + Added long file name feature. (_USE_LFN) + Added multiple code page feature. (_CODE_PAGE) + Added re-entrancy for multitask operation. (_FS_REENTRANT) + Added auto cluster size selection to f_mkfs(). + Added rewind option to f_readdir(). + Changed result code of critical errors. + Renamed string functions to avoid name collision. + + + +R0.07a (April 14, 2009) + + Septemberarated out OS dependent code on reentrant cfg. + Added multiple sector size feature. + + + +R0.07c (June 21, 2009) + + Fixed f_unlink() can return FR_OK on error. + Fixed wrong cache control in f_lseek(). + Added relative path feature. + Added f_chdir() and f_chdrive(). + Added proper case conversion to extended character. + + + +R0.07e (November 03, 2009) + + Septemberarated out configuration options from ff.h to ffconf.h. + Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH. + Fixed name matching error on the 13 character boundary. + Added a configuration option, _LFN_UNICODE. + Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. + + + +R0.08 (May 15, 2010) + + Added a memory configuration option. (_USE_LFN = 3) + Added file lock feature. (_FS_SHARE) + Added fast seek feature. (_USE_FASTSEEK) + Changed some types on the API, XCHAR->TCHAR. + Changed .fname in the FILINFO structure on Unicode cfg. + String functions support UTF-8 encoding files on Unicode cfg. + + + +R0.08a (August 16, 2010) + + Added f_getcwd(). (_FS_RPATH = 2) + Added sector erase feature. (_USE_ERASE) + Moved file lock semaphore table from fs object to the bss. + Fixed f_mkfs() creates wrong FAT32 volume. + + + +R0.08b (January 15, 2011) + + Fast seek feature is also applied to f_read() and f_write(). + f_lseek() reports required table size on creating CLMP. + Extended format syntax of f_printf(). + Ignores duplicated directory separators in given path name. + + + +R0.09 (September 06, 2011) + + f_mkfs() supports multiple partition to complete the multiple partition feature. + Added f_fdisk(). + + + +R0.09a (August 27, 2012) + + Changed f_open() and f_opendir() reject null object pointer to avoid crash. + Changed option name _FS_SHARE to _FS_LOCK. + Fixed assertion failure due to OS/2 EA on FAT12/16 volume. + + + +R0.09b (January 24, 2013) + + Added f_setlabel() and f_getlabel(). + + + +R0.10 (October 02, 2013) + + Added selection of character encoding on the file. (_STRF_ENCODE) + Added f_closedir(). + Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) + Added forced mount feature with changes of f_mount(). + Improved behavior of volume auto detection. + Improved write throughput of f_puts() and f_printf(). + Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). + Fixed f_write() can be truncated when the file size is close to 4GB. + Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error. + + + +R0.10a (January 15, 2014) + + Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID) + Added a configuration option of minimum sector size. (_MIN_SS) + 2nd argument of f_rename() can have a drive number and it will be ignored. + Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10) + Fixed f_close() invalidates the file object without volume lock. + Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10) + Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07) + + + +R0.10b (May 19, 2014) + + Fixed a hard error in the disk I/O layer can collapse the directory entry. + Fixed LFN entry is not deleted on delete/rename an object with lossy converted SFN. (appeared at R0.07) + + + +R0.10c (November 09, 2014) + + Added a configuration option for the platforms without RTC. (_FS_NORTC) + Changed option name _USE_ERASE to _USE_TRIM. + Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b) + Fixed a potential problem of FAT access that can appear on disk error. + Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08) + + + +R0.11 (February 09, 2015) + + Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND) + Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c) + Fixed _FS_NORTC option does not work properly. (appeared at R0.10c) + + + +R0.11a (September 05, 2015) + + Fixed wrong media change can lead a deadlock at thread-safe configuration. + Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE) + Removed some code pages actually not exist on the standard systems. (_CODE_PAGE) + Fixed errors in the case conversion teble of code page 437 and 850 (ff.c). + Fixed errors in the case conversion teble of Unicode (cc*.c). + + + +R0.12 (April 12, 2016) + + Added support for exFAT file system. (_FS_EXFAT) + Added f_expand(). (_USE_EXPAND) + Changed some members in FINFO structure and behavior of f_readdir(). + Added an option _USE_CHMOD. + Removed an option _WORD_ACCESS. + Fixed errors in the case conversion table of Unicode (cc*.c). + + + +R0.12a (July 10, 2016) + + Added support for creating exFAT volume with some changes of f_mkfs(). + Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed. + f_forward() is available regardless of _FS_TINY. + Fixed f_mkfs() creates wrong volume. (appeared at R0.12) + Fixed wrong memory read in create_name(). (appeared at R0.12) + Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD. + + + +R0.12b (September 04, 2016) + + Improved f_rename() to be able to rename objects with the same name but case. + Fixed an error in the case conversion teble of code page 866. (ff.c) + Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12) + Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12) + Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12) + Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12) + Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12) + Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12) + diff --git a/radio/src/thirdparty/FatFs/00readme.txt b/radio/src/thirdparty/FatFs/00readme.txt index 42426a401..3d583cbb1 100644 --- a/radio/src/thirdparty/FatFs/00readme.txt +++ b/radio/src/thirdparty/FatFs/00readme.txt @@ -1,21 +1,21 @@ -FatFs Module Source Files R0.12a - - -FILES - - 00readme.txt This file. - history.txt Revision history. - ffconf.h Configuration file for FatFs module. - ff.h Common include file for FatFs and application module. - ff.c FatFs module. - diskio.h Common include file for FatFs and disk I/O module. - diskio.c An example of glue function to attach existing disk I/O module to FatFs. - integer.h Integer type definitions for FatFs. - option Optional external functions. - - - Low level disk I/O module is not included in this archive because the FatFs - module is only a generic file system layer and not depend on any specific - storage device. You have to provide a low level disk I/O module that written - to control the target storage device. - +FatFs Module Source Files R0.12a + + +FILES + + 00readme.txt This file. + history.txt Revision history. + ffconf.h Configuration file for FatFs module. + ff.h Common include file for FatFs and application module. + ff.c FatFs module. + diskio.h Common include file for FatFs and disk I/O module. + diskio.c An example of glue function to attach existing disk I/O module to FatFs. + integer.h Integer type definitions for FatFs. + option Optional external functions. + + + Low level disk I/O module is not included in this archive because the FatFs + module is only a generic file system layer and not depend on any specific + storage device. You have to provide a low level disk I/O module that written + to control the target storage device. + diff --git a/radio/src/thirdparty/FatFs/diskio.h b/radio/src/thirdparty/FatFs/diskio.h index 03e8b7c56..20ebde941 100644 --- a/radio/src/thirdparty/FatFs/diskio.h +++ b/radio/src/thirdparty/FatFs/diskio.h @@ -1,80 +1,80 @@ -/*-----------------------------------------------------------------------/ -/ Low level disk interface modlue include file (C)ChaN, 2014 / -/-----------------------------------------------------------------------*/ - -#ifndef _DISKIO_DEFINED -#define _DISKIO_DEFINED - -#ifdef __cplusplus -extern "C" { -#endif - -#include "integer.h" - - -/* Status of Disk Functions */ -typedef BYTE DSTATUS; - -/* Results of Disk Functions */ -typedef enum { - RES_OK = 0, /* 0: Successful */ - RES_ERROR, /* 1: R/W Error */ - RES_WRPRT, /* 2: Write Protected */ - RES_NOTRDY, /* 3: Not Ready */ - RES_PARERR /* 4: Invalid Parameter */ -} DRESULT; - - -/*---------------------------------------*/ -/* Prototypes for disk control functions */ - - -DSTATUS disk_initialize (BYTE pdrv); -DSTATUS disk_status (BYTE pdrv); -DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count); -DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count); -DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff); - - -/* Disk Status Bits (DSTATUS) */ - -#define STA_NOINIT 0x01 /* Drive not initialized */ -#define STA_NODISK 0x02 /* No medium in the drive */ -#define STA_PROTECT 0x04 /* Write protected */ - - -/* Command code for disk_ioctrl fucntion */ - -/* Generic command (Used by FatFs) */ -#define CTRL_SYNC 0 /* Complete pending write process (needed at _FS_READONLY == 0) */ -#define GET_SECTOR_COUNT 1 /* Get media size (needed at _USE_MKFS == 1) */ -#define GET_SECTOR_SIZE 2 /* Get sector size (needed at _MAX_SS != _MIN_SS) */ -#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at _USE_MKFS == 1) */ -#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */ - -/* Generic command (Not used by FatFs) */ -#define CTRL_POWER 5 /* Get/Set power status */ -#define CTRL_LOCK 6 /* Lock/Unlock media removal */ -#define CTRL_EJECT 7 /* Eject media */ -#define CTRL_FORMAT 8 /* Create physical format on the media */ - -/* MMC/SDC specific ioctl command */ -#define MMC_GET_TYPE 10 /* Get card type */ -#define MMC_GET_CSD 11 /* Get CSD */ -#define MMC_GET_CID 12 /* Get CID */ -#define MMC_GET_OCR 13 /* Get OCR */ -#define MMC_GET_SDSTAT 14 /* Get SD status */ -#define ISDIO_READ 55 /* Read data form SD iSDIO register */ -#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */ -#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */ - -/* ATA/CF specific ioctl command */ -#define ATA_GET_REV 20 /* Get F/W revision */ -#define ATA_GET_MODEL 21 /* Get model name */ -#define ATA_GET_SN 22 /* Get serial number */ - -#ifdef __cplusplus -} -#endif - -#endif +/*-----------------------------------------------------------------------/ +/ Low level disk interface modlue include file (C)ChaN, 2014 / +/-----------------------------------------------------------------------*/ + +#ifndef _DISKIO_DEFINED +#define _DISKIO_DEFINED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "integer.h" + + +/* Status of Disk Functions */ +typedef BYTE DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + + +DSTATUS disk_initialize (BYTE pdrv); +DSTATUS disk_status (BYTE pdrv); +DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count); +DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count); +DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff); + + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl fucntion */ + +/* Generic command (Used by FatFs) */ +#define CTRL_SYNC 0 /* Complete pending write process (needed at _FS_READONLY == 0) */ +#define GET_SECTOR_COUNT 1 /* Get media size (needed at _USE_MKFS == 1) */ +#define GET_SECTOR_SIZE 2 /* Get sector size (needed at _MAX_SS != _MIN_SS) */ +#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at _USE_MKFS == 1) */ +#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */ + +/* Generic command (Not used by FatFs) */ +#define CTRL_POWER 5 /* Get/Set power status */ +#define CTRL_LOCK 6 /* Lock/Unlock media removal */ +#define CTRL_EJECT 7 /* Eject media */ +#define CTRL_FORMAT 8 /* Create physical format on the media */ + +/* MMC/SDC specific ioctl command */ +#define MMC_GET_TYPE 10 /* Get card type */ +#define MMC_GET_CSD 11 /* Get CSD */ +#define MMC_GET_CID 12 /* Get CID */ +#define MMC_GET_OCR 13 /* Get OCR */ +#define MMC_GET_SDSTAT 14 /* Get SD status */ +#define ISDIO_READ 55 /* Read data form SD iSDIO register */ +#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */ +#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */ + +/* ATA/CF specific ioctl command */ +#define ATA_GET_REV 20 /* Get F/W revision */ +#define ATA_GET_MODEL 21 /* Get model name */ +#define ATA_GET_SN 22 /* Get serial number */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/radio/src/thirdparty/FatFs/ff.c b/radio/src/thirdparty/FatFs/ff.c index 66a94e898..4e1135f9f 100644 --- a/radio/src/thirdparty/FatFs/ff.c +++ b/radio/src/thirdparty/FatFs/ff.c @@ -1,6041 +1,6041 @@ -/*----------------------------------------------------------------------------/ -/ FatFs - Generic FAT file system module R0.12b / -/-----------------------------------------------------------------------------/ -/ -/ Copyright (C) 2016, ChaN, all right reserved. -/ -/ FatFs module is an open source software. Redistribution and use of FatFs in -/ source and binary forms, with or without modification, are permitted provided -/ that the following condition is met: - -/ 1. Redistributions of source code must retain the above copyright notice, -/ this condition and the following disclaimer. -/ -/ This software is provided by the copyright holder and contributors "AS IS" -/ and any warranties related to this software are DISCLAIMED. -/ The copyright owner or contributors be NOT LIABLE for any damages caused -/ by use of this software. -/----------------------------------------------------------------------------*/ - - -#include "ff.h" /* Declarations of FatFs API */ -#include "diskio.h" /* Declarations of device I/O functions */ - - -/*-------------------------------------------------------------------------- - - Module Private Definitions - ----------------------------------------------------------------------------*/ - -#if _FATFS != 68020 /* Revision ID */ -#error Wrong include file (ff.h). -#endif - - -#define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); } - - -/* Reentrancy related */ -#if _FS_REENTRANT -#if _USE_LFN == 1 -#error Static LFN work area cannot be used at thread-safe configuration -#endif -#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } -#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } -#else -#define ENTER_FF(fs) -#define LEAVE_FF(fs, res) return res -#endif - - - -/* Definitions of sector size */ -#if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096) || (_MIN_SS != 512 && _MIN_SS != 1024 && _MIN_SS != 2048 && _MIN_SS != 4096) -#error Wrong sector size configuration -#endif -#if _MAX_SS == _MIN_SS -#define SS(fs) ((UINT)_MAX_SS) /* Fixed sector size */ -#else -#define SS(fs) ((fs)->ssize) /* Variable sector size */ -#endif - - -/* Timestamp */ -#if _FS_NORTC == 1 -#if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < 1 || _NORTC_MDAY > 31 -#error Invalid _FS_NORTC settings -#endif -#define GET_FATTIME() ((DWORD)(_NORTC_YEAR - 1980) << 25 | (DWORD)_NORTC_MON << 21 | (DWORD)_NORTC_MDAY << 16) -#else -#define GET_FATTIME() get_fattime() -#endif - - -/* File lock controls */ -#if _FS_LOCK != 0 -#if _FS_READONLY -#error _FS_LOCK must be 0 at read-only configuration -#endif -typedef struct { - FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */ - DWORD clu; /* Object ID 2, directory (0:root) */ - DWORD ofs; /* Object ID 3, directory offset */ - WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ -} FILESEM; -#endif - - - -/* DBCS code ranges and SBCS upper conversion tables */ - -#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ -#define _DF1S 0x81 /* DBC 1st byte range 1 start */ -#define _DF1E 0x9F /* DBC 1st byte range 1 end */ -#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ -#define _DF2E 0xFC /* DBC 1st byte range 2 end */ -#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ -#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ -#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ -#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ - -#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x40 -#define _DS1E 0x7E -#define _DS2S 0x80 -#define _DS2E 0xFE - -#elif _CODE_PAGE == 949 /* Korean */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x41 -#define _DS1E 0x5A -#define _DS2S 0x61 -#define _DS2E 0x7A -#define _DS3S 0x81 -#define _DS3E 0xFE - -#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x40 -#define _DS1E 0x7E -#define _DS2S 0xA1 -#define _DS2E 0xFE - -#elif _CODE_PAGE == 437 /* U.S. */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ - 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 720 /* Arabic */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 737 /* Greek */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ - 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 771 /* KBL */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF} - -#elif _CODE_PAGE == 775 /* Baltic */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \ - 0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 850 /* Latin 1 */ -#define _DF1S 0 -#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \ - 0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \ - 0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 852 /* Latin 2 */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \ - 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} - -#elif _CODE_PAGE == 855 /* Cyrillic */ -#define _DF1S 0 -#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \ - 0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ - 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ - 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \ - 0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 857 /* Turkish */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \ - 0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 860 /* Portuguese */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \ - 0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 861 /* Icelandic */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \ - 0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 862 /* Hebrew */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 863 /* Canadian-French */ -#define _DF1S 0 -#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \ - 0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \ - 0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 864 /* Arabic */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ - 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 865 /* Nordic */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ - 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 866 /* Russian */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 869 /* Greek 2 */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \ - 0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \ - 0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \ - 0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF} - -#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ -#if _USE_LFN != 0 -#error Cannot enable LFN without valid code page. -#endif -#define _DF1S 0 - -#else -#error Unknown code page - -#endif - - -/* Character code support macros */ -#define IsUpper(c) (((c)>='A')&&((c)<='Z')) -#define IsLower(c) (((c)>='a')&&((c)<='z')) -#define IsDigit(c) (((c)>='0')&&((c)<='9')) - -#if _DF1S != 0 /* Code page is DBCS */ - -#ifdef _DF2S /* Two 1st byte areas */ -#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) -#else /* One 1st byte area */ -#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) -#endif - -#ifdef _DS3S /* Three 2nd byte areas */ -#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) -#else /* Two 2nd byte areas */ -#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) -#endif - -#else /* Code page is SBCS */ - -#define IsDBCS1(c) 0 -#define IsDBCS2(c) 0 - -#endif /* _DF1S */ - - -/* File attribute bits (internal use) */ -#define AM_VOL 0x08 /* Volume label */ -#define AM_LFN 0x0F /* LFN entry */ -#define AM_MASK 0x3F /* Mask of defined bits */ - - -/* File access control and file status flags (internal use) */ -#define FA_SEEKEND 0x20 /* Seek to end of the file on file open */ -#define FA_MODIFIED 0x40 /* File has been modified */ -#define FA_DIRTY 0x80 /* FIL.buf[] needs to be written-back */ - - -/* Name status flags */ -#define NSFLAG 11 /* Index of name status byte in fn[] */ -#define NS_LOSS 0x01 /* Out of 8.3 format */ -#define NS_LFN 0x02 /* Force to create LFN entry */ -#define NS_LAST 0x04 /* Last segment */ -#define NS_BODY 0x08 /* Lower case flag (body) */ -#define NS_EXT 0x10 /* Lower case flag (ext) */ -#define NS_DOT 0x20 /* Dot entry */ -#define NS_NOLFN 0x40 /* Do not find LFN */ -#define NS_NONAME 0x80 /* Not followed */ - - -/* Limits and boundaries (differ from specs but correct for real DOS/Windows) */ -#define MAX_FAT12 0xFF5 /* Maximum number of FAT12 clusters */ -#define MAX_FAT16 0xFFF5 /* Maximum number of FAT16 clusters */ -#define MAX_FAT32 0xFFFFFF5 /* Maximum number of FAT32 clusters */ -#define MAX_EXFAT 0x7FFFFFFD /* Maximum number of exFAT clusters (limited by implementation) */ -#define MAX_DIR 0x200000 /* Maximum size of FAT directory */ -#define MAX_DIR_EX 0x10000000 /* Maximum size of exFAT directory */ - - -/* FatFs refers the members in the FAT structures as byte array instead of -/ structure members because the structure is not binary compatible between -/ different platforms */ - -#define BS_JmpBoot 0 /* x86 jump instruction (3-byte) */ -#define BS_OEMName 3 /* OEM name (8-byte) */ -#define BPB_BytsPerSec 11 /* Sector size [byte] (WORD) */ -#define BPB_SecPerClus 13 /* Cluster size [sector] (BYTE) */ -#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (WORD) */ -#define BPB_NumFATs 16 /* Number of FATs (BYTE) */ -#define BPB_RootEntCnt 17 /* Size of root directory area for FAT12/16 [entry] (WORD) */ -#define BPB_TotSec16 19 /* Volume size (16-bit) [sector] (WORD) */ -#define BPB_Media 21 /* Media descriptor byte (BYTE) */ -#define BPB_FATSz16 22 /* FAT size (16-bit) [sector] (WORD) */ -#define BPB_SecPerTrk 24 /* Track size for int13h [sector] (WORD) */ -#define BPB_NumHeads 26 /* Number of heads for int13h (WORD) */ -#define BPB_HiddSec 28 /* Volume offset from top of the drive (DWORD) */ -#define BPB_TotSec32 32 /* Volume size (32-bit) [sector] (DWORD) */ -#define BS_DrvNum 36 /* Physical drive number for int13h (BYTE) */ -#define BS_NTres 37 /* Error flag (BYTE) */ -#define BS_BootSig 38 /* Extended boot signature (BYTE) */ -#define BS_VolID 39 /* Volume serial number (DWORD) */ -#define BS_VolLab 43 /* Volume label string (8-byte) */ -#define BS_FilSysType 54 /* File system type string (8-byte) */ -#define BS_BootCode 62 /* Boot code (448-byte) */ -#define BS_55AA 510 /* Signature word (WORD) */ - -#define BPB_FATSz32 36 /* FAT32: FAT size [sector] (DWORD) */ -#define BPB_ExtFlags32 40 /* FAT32: Extended flags (WORD) */ -#define BPB_FSVer32 42 /* FAT32: File system version (WORD) */ -#define BPB_RootClus32 44 /* FAT32: Root directory cluster (DWORD) */ -#define BPB_FSInfo32 48 /* FAT32: Offset of FSINFO sector (WORD) */ -#define BPB_BkBootSec32 50 /* FAT32: Offset of backup boot sector (WORD) */ -#define BS_DrvNum32 64 /* FAT32: Physical drive number for int13h (BYTE) */ -#define BS_NTres32 65 /* FAT32: Error flag (BYTE) */ -#define BS_BootSig32 66 /* FAT32: Extended boot signature (BYTE) */ -#define BS_VolID32 67 /* FAT32: Volume serial number (DWORD) */ -#define BS_VolLab32 71 /* FAT32: Volume label string (8-byte) */ -#define BS_FilSysType32 82 /* FAT32: File system type string (8-byte) */ -#define BS_BootCode32 90 /* FAT32: Boot code (420-byte) */ - -#define BPB_ZeroedEx 11 /* exFAT: MBZ field (53-byte) */ -#define BPB_VolOfsEx 64 /* exFAT: Volume offset from top of the drive [sector] (QWORD) */ -#define BPB_TotSecEx 72 /* exFAT: Volume size [sector] (QWORD) */ -#define BPB_FatOfsEx 80 /* exFAT: FAT offset from top of the volume [sector] (DWORD) */ -#define BPB_FatSzEx 84 /* exFAT: FAT size [sector] (DWORD) */ -#define BPB_DataOfsEx 88 /* exFAT: Data offset from top of the volume [sector] (DWORD) */ -#define BPB_NumClusEx 92 /* exFAT: Number of clusters (DWORD) */ -#define BPB_RootClusEx 96 /* exFAT: Root directory cluster (DWORD) */ -#define BPB_VolIDEx 100 /* exFAT: Volume serial number (DWORD) */ -#define BPB_FSVerEx 104 /* exFAT: File system version (WORD) */ -#define BPB_VolFlagEx 106 /* exFAT: Volume flags (BYTE) */ -#define BPB_ActFatEx 107 /* exFAT: Active FAT flags (BYTE) */ -#define BPB_BytsPerSecEx 108 /* exFAT: Log2 of sector size in byte (BYTE) */ -#define BPB_SecPerClusEx 109 /* exFAT: Log2 of cluster size in sector (BYTE) */ -#define BPB_NumFATsEx 110 /* exFAT: Number of FATs (BYTE) */ -#define BPB_DrvNumEx 111 /* exFAT: Physical drive number for int13h (BYTE) */ -#define BPB_PercInUseEx 112 /* exFAT: Percent in use (BYTE) */ -#define BPB_RsvdEx 113 /* exFAT: Reserved (7-byte) */ -#define BS_BootCodeEx 120 /* exFAT: Boot code (390-byte) */ - -#define FSI_LeadSig 0 /* FAT32 FSI: Leading signature (DWORD) */ -#define FSI_StrucSig 484 /* FAT32 FSI: Structure signature (DWORD) */ -#define FSI_Free_Count 488 /* FAT32 FSI: Number of free clusters (DWORD) */ -#define FSI_Nxt_Free 492 /* FAT32 FSI: Last allocated cluster (DWORD) */ - -#define MBR_Table 446 /* MBR: Offset of partition table in the MBR */ -#define SZ_PTE 16 /* MBR: Size of a partition table entry */ -#define PTE_Boot 0 /* MBR PTE: Boot indicator */ -#define PTE_StHead 1 /* MBR PTE: Start head */ -#define PTE_StSec 2 /* MBR PTE: Start sector */ -#define PTE_StCyl 3 /* MBR PTE: Start cylinder */ -#define PTE_System 4 /* MBR PTE: System ID */ -#define PTE_EdHead 5 /* MBR PTE: End head */ -#define PTE_EdSec 6 /* MBR PTE: End sector */ -#define PTE_EdCyl 7 /* MBR PTE: End cylinder */ -#define PTE_StLba 8 /* MBR PTE: Start in LBA */ -#define PTE_SizLba 12 /* MBR PTE: Size in LBA */ - -#define DIR_Name 0 /* Short file name (11-byte) */ -#define DIR_Attr 11 /* Attribute (BYTE) */ -#define DIR_NTres 12 /* Lower case flag (BYTE) */ -#define DIR_CrtTime10 13 /* Created time sub-second (BYTE) */ -#define DIR_CrtTime 14 /* Created time (DWORD) */ -#define DIR_LstAccDate 18 /* Last accessed date (WORD) */ -#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (WORD) */ -#define DIR_ModTime 22 /* Modified time (DWORD) */ -#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (WORD) */ -#define DIR_FileSize 28 /* File size (DWORD) */ -#define LDIR_Ord 0 /* LFN entry order and LLE flag (BYTE) */ -#define LDIR_Attr 11 /* LFN attribute (BYTE) */ -#define LDIR_Type 12 /* LFN type (BYTE) */ -#define LDIR_Chksum 13 /* Checksum of the SFN entry (BYTE) */ -#define LDIR_FstClusLO 26 /* Must be zero (WORD) */ -#define XDIR_Type 0 /* Type of exFAT directory entry (BYTE) */ -#define XDIR_NumLabel 1 /* Number of volume label characters (BYTE) */ -#define XDIR_Label 2 /* Volume label (11-WORD) */ -#define XDIR_CaseSum 4 /* Sum of case conversion table (DWORD) */ -#define XDIR_NumSec 1 /* Number of secondary entries (BYTE) */ -#define XDIR_SetSum 2 /* Sum of the set of directory entries (WORD) */ -#define XDIR_Attr 4 /* File attribute (WORD) */ -#define XDIR_CrtTime 8 /* Created time (DWORD) */ -#define XDIR_ModTime 12 /* Modified time (DWORD) */ -#define XDIR_AccTime 16 /* Last accessed time (DWORD) */ -#define XDIR_CrtTime10 20 /* Created time subsecond (BYTE) */ -#define XDIR_ModTime10 21 /* Modified time subsecond (BYTE) */ -#define XDIR_CrtTZ 22 /* Created timezone (BYTE) */ -#define XDIR_ModTZ 23 /* Modified timezone (BYTE) */ -#define XDIR_AccTZ 24 /* Last accessed timezone (BYTE) */ -#define XDIR_GenFlags 33 /* Gneral secondary flags (WORD) */ -#define XDIR_NumName 35 /* Number of file name characters (BYTE) */ -#define XDIR_NameHash 36 /* Hash of file name (WORD) */ -#define XDIR_ValidFileSize 40 /* Valid file size (QWORD) */ -#define XDIR_FstClus 52 /* First cluster of the file data (DWORD) */ -#define XDIR_FileSize 56 /* File/Directory size (QWORD) */ - -#define SZDIRE 32 /* Size of a directory entry */ -#define LLEF 0x40 /* Last long entry flag in LDIR_Ord */ -#define DDEM 0xE5 /* Deleted directory entry mark set to DIR_Name[0] */ -#define RDDEM 0x05 /* Replacement of the character collides with DDEM */ - - - - - -/*-------------------------------------------------------------------------- - - Module Private Work Area - ----------------------------------------------------------------------------*/ - -/* Remark: Variables here without initial value shall be guaranteed zero/null -/ at start-up. If not, either the linker or start-up routine being used is -/ not compliance with C standard. */ - -#if _VOLUMES < 1 || _VOLUMES > 9 -#error Wrong _VOLUMES setting -#endif -static FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ -static WORD Fsid; /* File system mount ID */ - -#if _FS_RPATH != 0 && _VOLUMES >= 2 -static BYTE CurrVol; /* Current drive */ -#endif - -#if _FS_LOCK != 0 -static FILESEM Files[_FS_LOCK]; /* Open object lock semaphores */ -#endif - -#if _USE_LFN == 0 /* Non-LFN configuration */ -#define DEF_NAMBUF -#define INIT_NAMBUF(fs) -#define FREE_NAMBUF() -#else -#if _MAX_LFN < 12 || _MAX_LFN > 255 -#error Wrong _MAX_LFN setting -#endif - -#if _USE_LFN == 1 /* LFN enabled with static working buffer */ -#if _FS_EXFAT -static BYTE DirBuf[SZDIRE*19]; /* Directory entry block scratchpad buffer (19 entries in size) */ -#endif -static WCHAR LfnBuf[_MAX_LFN+1]; /* LFN enabled with static working buffer */ -#define DEF_NAMBUF -#define INIT_NAMBUF(fs) -#define FREE_NAMBUF() - -#elif _USE_LFN == 2 /* LFN enabled with dynamic working buffer on the stack */ -#if _FS_EXFAT -#define DEF_NAMBUF WCHAR lbuf[_MAX_LFN+1]; BYTE dbuf[SZDIRE*19]; -#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; } -#define FREE_NAMBUF() -#else -#define DEF_NAMBUF WCHAR lbuf[_MAX_LFN+1]; -#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; } -#define FREE_NAMBUF() -#endif - -#elif _USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */ -#if _FS_EXFAT -#define DEF_NAMBUF WCHAR *lfn; -#define INIT_NAMBUF(fs) { lfn = ff_memalloc((_MAX_LFN+1)*2 + SZDIRE*19); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+_MAX_LFN+1); } -#define FREE_NAMBUF() ff_memfree(lfn) -#else -#define DEF_NAMBUF WCHAR *lfn; -#define INIT_NAMBUF(fs) { lfn = ff_memalloc((_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; } -#define FREE_NAMBUF() ff_memfree(lfn) -#endif - -#else -#error Wrong _USE_LFN setting -#endif -#endif - -#ifdef _EXCVT -static const BYTE ExCvt[] = _EXCVT; /* Upper conversion table for SBCS extended characters */ -#endif - - - - - - -/*-------------------------------------------------------------------------- - - Module Private Functions - ----------------------------------------------------------------------------*/ - - -/*-----------------------------------------------------------------------*/ -/* Load/Store multi-byte word in the FAT structure */ -/*-----------------------------------------------------------------------*/ - -static -WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */ -{ - WORD rv; - - rv = ptr[1]; - rv = rv << 8 | ptr[0]; - return rv; -} - -static -DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */ -{ - DWORD rv; - - rv = ptr[3]; - rv = rv << 8 | ptr[2]; - rv = rv << 8 | ptr[1]; - rv = rv << 8 | ptr[0]; - return rv; -} - -#if _FS_EXFAT -static -QWORD ld_qword (const BYTE* ptr) /* Load an 8-byte little-endian word */ -{ - QWORD rv; - - rv = ptr[7]; - rv = rv << 8 | ptr[6]; - rv = rv << 8 | ptr[5]; - rv = rv << 8 | ptr[4]; - rv = rv << 8 | ptr[3]; - rv = rv << 8 | ptr[2]; - rv = rv << 8 | ptr[1]; - rv = rv << 8 | ptr[0]; - return rv; -} -#endif - -#if !_FS_READONLY -static -void st_word (BYTE* ptr, WORD val) /* Store a 2-byte word in little-endian */ -{ - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; -} - -static -void st_dword (BYTE* ptr, DWORD val) /* Store a 4-byte word in little-endian */ -{ - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; -} - -#if _FS_EXFAT -static -void st_qword (BYTE* ptr, QWORD val) /* Store an 8-byte word in little-endian */ -{ - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; -} -#endif -#endif /* !_FS_READONLY */ - - - -/*-----------------------------------------------------------------------*/ -/* String functions */ -/*-----------------------------------------------------------------------*/ - -/* Copy memory to memory */ -static -void mem_cpy (void* dst, const void* src, UINT cnt) { - BYTE *d = (BYTE*)dst; - const BYTE *s = (const BYTE*)src; - - if (cnt) { - do *d++ = *s++; while (--cnt); - } -} - -/* Fill memory block */ -static -void mem_set (void* dst, int val, UINT cnt) { - BYTE *d = (BYTE*)dst; - - do *d++ = (BYTE)val; while (--cnt); -} - -/* Compare memory block */ -static -int mem_cmp (const void* dst, const void* src, UINT cnt) { /* ZR:same, NZ:different */ - const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; - int r = 0; - - do { - r = *d++ - *s++; - } while (--cnt && r == 0); - - return r; -} - -/* Check if chr is contained in the string */ -static -int chk_chr (const char* str, int chr) { /* NZ:contained, ZR:not contained */ - while (*str && *str != chr) str++; - return *str; -} - - - - -#if _FS_REENTRANT -/*-----------------------------------------------------------------------*/ -/* Request/Release grant to access the volume */ -/*-----------------------------------------------------------------------*/ -static -int lock_fs ( - FATFS* fs /* File system object */ -) -{ - return ff_req_grant(fs->sobj); -} - - -static -void unlock_fs ( - FATFS* fs, /* File system object */ - FRESULT res /* Result code to be returned */ -) -{ - if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) { - ff_rel_grant(fs->sobj); - } -} - -#endif - - - -#if _FS_LOCK != 0 -/*-----------------------------------------------------------------------*/ -/* File lock control functions */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT chk_lock ( /* Check if the file can be accessed */ - DIR* dp, /* Directory object pointing the file to be checked */ - int acc /* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */ -) -{ - UINT i, be; - - /* Search file semaphore table */ - for (i = be = 0; i < _FS_LOCK; i++) { - if (Files[i].fs) { /* Existing entry */ - if (Files[i].fs == dp->obj.fs && /* Check if the object matched with an open object */ - Files[i].clu == dp->obj.sclust && - Files[i].ofs == dp->dptr) break; - } else { /* Blank entry */ - be = 1; - } - } - if (i == _FS_LOCK) { /* The object is not opened */ - return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new object? */ - } - - /* The object has been opened. Reject any open against writing file and all write mode open */ - return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; -} - - -static -int enq_lock (void) /* Check if an entry is available for a new object */ -{ - UINT i; - - for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; - return (i == _FS_LOCK) ? 0 : 1; -} - - -static -UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */ - DIR* dp, /* Directory object pointing the file to register or increment */ - int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ -) -{ - UINT i; - - - for (i = 0; i < _FS_LOCK; i++) { /* Find the object */ - if (Files[i].fs == dp->obj.fs && - Files[i].clu == dp->obj.sclust && - Files[i].ofs == dp->dptr) break; - } - - if (i == _FS_LOCK) { /* Not opened. Register it as new. */ - for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; - if (i == _FS_LOCK) return 0; /* No free entry to register (int err) */ - Files[i].fs = dp->obj.fs; - Files[i].clu = dp->obj.sclust; - Files[i].ofs = dp->dptr; - Files[i].ctr = 0; - } - - if (acc && Files[i].ctr) return 0; /* Access violation (int err) */ - - Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ - - return i + 1; -} - - -static -FRESULT dec_lock ( /* Decrement object open counter */ - UINT i /* Semaphore index (1..) */ -) -{ - WORD n; - FRESULT res; - - - if (--i < _FS_LOCK) { /* Shift index number origin from 0 */ - n = Files[i].ctr; - if (n == 0x100) n = 0; /* If write mode open, delete the entry */ - if (n > 0) n--; /* Decrement read mode open count */ - Files[i].ctr = n; - if (n == 0) Files[i].fs = 0; /* Delete the entry if open count gets zero */ - res = FR_OK; - } else { - res = FR_INT_ERR; /* Invalid index nunber */ - } - return res; -} - - -static -void clear_lock ( /* Clear lock entries of the volume */ - FATFS *fs -) -{ - UINT i; - - for (i = 0; i < _FS_LOCK; i++) { - if (Files[i].fs == fs) Files[i].fs = 0; - } -} - -#endif /* _FS_LOCK != 0 */ - - - -/*-----------------------------------------------------------------------*/ -/* Move/Flush disk access window in the file system object */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERROR */ - FATFS* fs /* File system object */ -) -{ - DWORD wsect; - UINT nf; - FRESULT res = FR_OK; - - - if (fs->wflag) { /* Write back the sector if it is dirty */ - wsect = fs->winsect; /* Current sector number */ - if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) { - res = FR_DISK_ERR; - } else { - fs->wflag = 0; - if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */ - for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ - wsect += fs->fsize; - disk_write(fs->drv, fs->win, wsect, 1); - } - } - } - } - return res; -} -#endif - - -static -FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERROR */ - FATFS* fs, /* File system object */ - DWORD sector /* Sector number to make appearance in the fs->win[] */ -) -{ - FRESULT res = FR_OK; - - - if (sector != fs->winsect) { /* Window offset changed? */ -#if !_FS_READONLY - res = sync_window(fs); /* Write-back changes */ -#endif - if (res == FR_OK) { /* Fill sector window with new data */ - if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) { - sector = 0xFFFFFFFF; /* Invalidate window if data is not reliable */ - res = FR_DISK_ERR; - } - fs->winsect = sector; - } - } - return res; -} - - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Synchronize file system and strage device */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT sync_fs ( /* FR_OK:succeeded, !=0:error */ - FATFS* fs /* File system object */ -) -{ - FRESULT res; - - - res = sync_window(fs); - if (res == FR_OK) { - /* Update FSInfo sector if needed */ - if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { - /* Create FSInfo structure */ - mem_set(fs->win, 0, SS(fs)); - st_word(fs->win + BS_55AA, 0xAA55); - st_dword(fs->win + FSI_LeadSig, 0x41615252); - st_dword(fs->win + FSI_StrucSig, 0x61417272); - st_dword(fs->win + FSI_Free_Count, fs->free_clst); - st_dword(fs->win + FSI_Nxt_Free, fs->last_clst); - /* Write it into the FSInfo sector */ - fs->winsect = fs->volbase + 1; - disk_write(fs->drv, fs->win, fs->winsect, 1); - fs->fsi_flag = 0; - } - /* Make sure that no pending write process in the physical drive */ - if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR; - } - - return res; -} - -#endif - - - -/*-----------------------------------------------------------------------*/ -/* Get sector# from cluster# */ -/*-----------------------------------------------------------------------*/ - -static -DWORD clust2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */ - FATFS* fs, /* File system object */ - DWORD clst /* Cluster# to be converted */ -) -{ - clst -= 2; - if (clst >= fs->n_fatent - 2) return 0; /* Invalid cluster# */ - return clst * fs->csize + fs->database; -} - - - - -/*-----------------------------------------------------------------------*/ -/* FAT access - Read value of a FAT entry */ -/*-----------------------------------------------------------------------*/ - -static -DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */ - _FDID* obj, /* Corresponding object */ - DWORD clst /* Cluster number to get the value */ -) -{ - UINT wc, bc; - DWORD val; - FATFS *fs = obj->fs; - - - if (clst < 2 || clst >= fs->n_fatent) { /* Check if in valid range */ - val = 1; /* Internal error */ - - } else { - val = 0xFFFFFFFF; /* Default value falls on disk error */ - - switch (fs->fs_type) { - case FS_FAT12 : - bc = (UINT)clst; bc += bc / 2; - if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; - wc = fs->win[bc++ % SS(fs)]; - if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; - wc |= fs->win[bc % SS(fs)] << 8; - val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); - break; - - case FS_FAT16 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break; - val = ld_word(fs->win + clst * 2 % SS(fs)); - break; - - case FS_FAT32 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; - val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; - break; -#if _FS_EXFAT - case FS_EXFAT : - if (obj->objsize) { - DWORD cofs = clst - obj->sclust; /* Offset from start cluster */ - DWORD clen = (DWORD)((obj->objsize - 1) / SS(fs)) / fs->csize; /* Number of clusters - 1 */ - - if (obj->stat == 2) { /* Is there no valid chain on the FAT? */ - if (cofs <= clen) { - val = (cofs == clen) ? 0x7FFFFFFF : clst + 1; /* Generate the value */ - break; - } - } - if (obj->stat == 3 && cofs < obj->n_cont) { /* Is it in the contiguous part? */ - val = clst + 1; /* Generate the value */ - break; - } - if (obj->stat != 2) { /* Get value from FAT if FAT chain is valid */ - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; - val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF; - break; - } - } - /* go next */ -#endif - default: - val = 1; /* Internal error */ - } - } - - return val; -} - - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* FAT access - Change value of a FAT entry */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */ - FATFS* fs, /* Corresponding file system object */ - DWORD clst, /* FAT index number (cluster number) to be changed */ - DWORD val /* New value to be set to the entry */ -) -{ - UINT bc; - BYTE *p; - FRESULT res = FR_INT_ERR; - - - if (clst >= 2 && clst < fs->n_fatent) { /* Check if in valid range */ - switch (fs->fs_type) { - case FS_FAT12 : /* Bitfield items */ - bc = (UINT)clst; bc += bc / 2; - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = fs->win + bc++ % SS(fs); - *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; - fs->wflag = 1; - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = fs->win + bc % SS(fs); - *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); - fs->wflag = 1; - break; - - case FS_FAT16 : /* WORD aligned items */ - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); - if (res != FR_OK) break; - st_word(fs->win + clst * 2 % SS(fs), (WORD)val); - fs->wflag = 1; - break; - - case FS_FAT32 : /* DWORD aligned items */ -#if _FS_EXFAT - case FS_EXFAT : -#endif - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); - if (res != FR_OK) break; - if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { - val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000); - } - st_dword(fs->win + clst * 4 % SS(fs), val); - fs->wflag = 1; - break; - } - } - return res; -} - -#endif /* !_FS_READONLY */ - - - - -#if _FS_EXFAT && !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* exFAT: Accessing FAT and Allocation Bitmap */ -/*-----------------------------------------------------------------------*/ - -/*---------------------------------------------*/ -/* exFAT: Find a contiguous free cluster block */ -/*---------------------------------------------*/ - -static -DWORD find_bitmap ( /* 0:No free cluster, 2..:Free cluster found, 0xFFFFFFFF:Disk error */ - FATFS* fs, /* File system object */ - DWORD clst, /* Cluster number to scan from */ - DWORD ncl /* Number of contiguous clusters to find (1..) */ -) -{ - BYTE bm, bv; - UINT i; - DWORD val, scl, ctr; - - - clst -= 2; /* The first bit in the bitmap corresponds to cluster #2 */ - if (clst >= fs->n_fatent - 2) clst = 0; - scl = val = clst; ctr = 0; - for (;;) { - if (move_window(fs, fs->database + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF; /* (assuming bitmap is located top of the cluster heap) */ - i = val / 8 % SS(fs); bm = 1 << (val % 8); - do { - do { - bv = fs->win[i] & bm; bm <<= 1; /* Get bit value */ - if (++val >= fs->n_fatent - 2) { /* Next cluster (with wrap-around) */ - val = 0; bm = 0; i = 4096; - } - if (!bv) { /* Is it a free cluster? */ - if (++ctr == ncl) return scl + 2; /* Check run length */ - } else { - scl = val; ctr = 0; /* Encountered a live cluster, restart to scan */ - } - if (val == clst) return 0; /* All cluster scanned? */ - } while (bm); - bm = 1; - } while (++i < SS(fs)); - } -} - - -/*------------------------------------*/ -/* exFAT: Set/Clear a block of bitmap */ -/*------------------------------------*/ - -static -FRESULT change_bitmap ( - FATFS* fs, /* File system object */ - DWORD clst, /* Cluster number to change from */ - DWORD ncl, /* Number of clusters to be changed */ - int bv /* bit value to be set (0 or 1) */ -) -{ - BYTE bm; - UINT i; - DWORD sect; - - - clst -= 2; /* The first bit corresponds to cluster #2 */ - sect = fs->database + clst / 8 / SS(fs); /* Sector address (assuming bitmap is located top of the cluster heap) */ - i = clst / 8 % SS(fs); /* Byte offset in the sector */ - bm = 1 << (clst % 8); /* Bit mask in the byte */ - for (;;) { - if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR; - do { - do { - if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR; /* Is the bit expected value? */ - fs->win[i] ^= bm; /* Flip the bit */ - fs->wflag = 1; - if (--ncl == 0) return FR_OK; /* All bits processed? */ - } while (bm <<= 1); /* Next bit */ - bm = 1; - } while (++i < SS(fs)); /* Next byte */ - i = 0; - } -} - - -/*---------------------------------------------*/ -/* Complement contiguous part of the FAT chain */ -/*---------------------------------------------*/ - -static -FRESULT fill_fat_chain ( - _FDID* obj /* Pointer to the corresponding object */ -) -{ - FRESULT res; - DWORD cl, n; - - if (obj->stat == 3) { /* Has the object been changed 'fragmented'? */ - for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) { /* Create cluster chain on the FAT */ - res = put_fat(obj->fs, cl, cl + 1); - if (res != FR_OK) return res; - } - obj->stat = 0; /* Change status 'FAT chain is valid' */ - } - return FR_OK; -} - -#endif /* _FS_EXFAT && !_FS_READONLY */ - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* FAT handling - Remove a cluster chain */ -/*-----------------------------------------------------------------------*/ -static -FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ - _FDID* obj, /* Corresponding object */ - DWORD clst, /* Cluster to remove a chain from */ - DWORD pclst /* Previous cluster of clst (0:an entire chain) */ -) -{ - FRESULT res = FR_OK; - DWORD nxt; - FATFS *fs = obj->fs; -#if _FS_EXFAT || _USE_TRIM - DWORD scl = clst, ecl = clst; -#endif -#if _USE_TRIM - DWORD rt[2]; -#endif - - if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Check if in valid range */ - - /* Mark the previous cluster 'EOC' on the FAT if it exists */ - if (pclst && (!_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) { - res = put_fat(fs, pclst, 0xFFFFFFFF); - if (res != FR_OK) return res; - } - - /* Remove the chain */ - do { - nxt = get_fat(obj, clst); /* Get cluster status */ - if (nxt == 0) break; /* Empty cluster? */ - if (nxt == 1) return FR_INT_ERR; /* Internal error? */ - if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ - if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { - res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */ - if (res != FR_OK) return res; - } - if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */ - fs->free_clst++; - fs->fsi_flag |= 1; - } -#if _FS_EXFAT || _USE_TRIM - if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ - ecl = nxt; - } else { /* End of contiguous cluster block */ -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - res = change_bitmap(fs, scl, ecl - scl + 1, 0); /* Mark the cluster block 'free' on the bitmap */ - if (res != FR_OK) return res; - } -#endif -#if _USE_TRIM - rt[0] = clust2sect(fs, scl); /* Start sector */ - rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ - disk_ioctl(fs->drv, CTRL_TRIM, rt); /* Inform device the block can be erased */ -#endif - scl = ecl = nxt; - } -#endif - clst = nxt; /* Next cluster */ - } while (clst < fs->n_fatent); /* Repeat while not the last link */ - -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - if (pclst == 0) { /* Does object have no chain? */ - obj->stat = 0; /* Change the object status 'initial' */ - } else { - if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) { /* Did the chain got contiguous? */ - obj->stat = 2; /* Change the object status 'contiguous' */ - } - } - } -#endif - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Stretch a chain or Create a new chain */ -/*-----------------------------------------------------------------------*/ -static -DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ - _FDID* obj, /* Corresponding object */ - DWORD clst /* Cluster# to stretch, 0:Create a new chain */ -) -{ - DWORD cs, ncl, scl; - FRESULT res; - FATFS *fs = obj->fs; - - - if (clst == 0) { /* Create a new chain */ - scl = fs->last_clst; /* Get suggested cluster to start from */ - if (scl == 0 || scl >= fs->n_fatent) scl = 1; - } - else { /* Stretch current chain */ - cs = get_fat(obj, clst); /* Check the cluster status */ - if (cs < 2) return 1; /* Invalid value */ - if (cs == 0xFFFFFFFF) return cs; /* A disk error occurred */ - if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ - scl = clst; - } - -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ - ncl = find_bitmap(fs, scl, 1); /* Find a free cluster */ - if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl; /* No free cluster or hard error? */ - res = change_bitmap(fs, ncl, 1, 1); /* Mark the cluster 'in use' */ - if (res == FR_INT_ERR) return 1; - if (res == FR_DISK_ERR) return 0xFFFFFFFF; - if (clst == 0) { /* Is it a new chain? */ - obj->stat = 2; /* Set status 'contiguous chain' */ - } else { /* This is a stretched chain */ - if (obj->stat == 2 && ncl != scl + 1) { /* Is the chain got fragmented? */ - obj->n_cont = scl - obj->sclust; /* Set size of the contiguous part */ - obj->stat = 3; /* Change status 'just fragmented' */ - } - } - } else -#endif - { /* On the FAT12/16/32 volume */ - ncl = scl; /* Start cluster */ - for (;;) { - ncl++; /* Next cluster */ - if (ncl >= fs->n_fatent) { /* Check wrap-around */ - ncl = 2; - if (ncl > scl) return 0; /* No free cluster */ - } - cs = get_fat(obj, ncl); /* Get the cluster status */ - if (cs == 0) break; /* Found a free cluster */ - if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* An error occurred */ - if (ncl == scl) return 0; /* No free cluster */ - } - } - - if (_FS_EXFAT && fs->fs_type == FS_EXFAT && obj->stat == 2) { /* Is it a contiguous chain? */ - res = FR_OK; /* FAT does not need to be written */ - } else { - res = put_fat(fs, ncl, 0xFFFFFFFF); /* Mark the new cluster 'EOC' */ - if (res == FR_OK && clst) { - res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ - } - } - - if (res == FR_OK) { /* Update FSINFO if function succeeded. */ - fs->last_clst = ncl; - if (fs->free_clst < fs->n_fatent - 2) fs->free_clst--; - fs->fsi_flag |= 1; - } else { - ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; /* Failed. Create error status */ - } - - return ncl; /* Return new cluster number or error status */ -} - -#endif /* !_FS_READONLY */ - - - - -#if _USE_FASTSEEK -/*-----------------------------------------------------------------------*/ -/* FAT handling - Convert offset into cluster with link map table */ -/*-----------------------------------------------------------------------*/ - -static -DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ - FIL* fp, /* Pointer to the file object */ - FSIZE_t ofs /* File offset to be converted to cluster# */ -) -{ - DWORD cl, ncl, *tbl; - FATFS *fs = fp->obj.fs; - - - tbl = fp->cltbl + 1; /* Top of CLMT */ - cl = (DWORD)(ofs / SS(fs) / fs->csize); /* Cluster order from top of the file */ - for (;;) { - ncl = *tbl++; /* Number of cluters in the fragment */ - if (ncl == 0) return 0; /* End of table? (error) */ - if (cl < ncl) break; /* In this fragment? */ - cl -= ncl; tbl++; /* Next fragment */ - } - return cl + *tbl; /* Return the cluster number */ -} - -#endif /* _USE_FASTSEEK */ - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Set directory index */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */ - DIR* dp, /* Pointer to directory object */ - DWORD ofs /* Offset of directory table */ -) -{ - DWORD csz, clst; - FATFS *fs = dp->obj.fs; - - - if (ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) { /* Check range of offset and alignment */ - return FR_INT_ERR; - } - dp->dptr = ofs; /* Set current offset */ - clst = dp->obj.sclust; /* Table start cluster (0:root) */ - if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */ - clst = fs->dirbase; - if (_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */ - } - - if (clst == 0) { /* Static table (root-directory in FAT12/16) */ - if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */ - dp->sect = fs->dirbase; - - } else { /* Dynamic table (sub-directory or root-directory in FAT32+) */ - csz = (DWORD)fs->csize * SS(fs); /* Bytes per cluster */ - while (ofs >= csz) { /* Follow cluster chain */ - clst = get_fat(&dp->obj, clst); /* Get next cluster */ - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ - if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal error */ - ofs -= csz; - } - dp->sect = clust2sect(fs, clst); - } - dp->clust = clst; /* Current cluster# */ - if (!dp->sect) return FR_INT_ERR; - dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ - dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Move directory table index next */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ - DIR* dp, /* Pointer to the directory object */ - int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ -) -{ - DWORD ofs, clst; - FATFS *fs = dp->obj.fs; -#if !_FS_READONLY - UINT n; -#endif - - ofs = dp->dptr + SZDIRE; /* Next entry */ - if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) return FR_NO_FILE; /* Report EOT when offset has reached max value */ - - if (ofs % SS(fs) == 0) { /* Sector changed? */ - dp->sect++; /* Next sector */ - - if (!dp->clust) { /* Static table */ - if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */ - dp->sect = 0; return FR_NO_FILE; - } - } - else { /* Dynamic table */ - if ((ofs / SS(fs) & (fs->csize - 1)) == 0) { /* Cluster changed? */ - clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ - if (clst <= 1) return FR_INT_ERR; /* Internal error */ - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ - if (clst >= fs->n_fatent) { /* Reached end of dynamic table */ -#if !_FS_READONLY - if (!stretch) { /* If no stretch, report EOT */ - dp->sect = 0; return FR_NO_FILE; - } - clst = create_chain(&dp->obj, dp->clust); /* Allocate a cluster */ - if (clst == 0) return FR_DENIED; /* No free cluster */ - if (clst == 1) return FR_INT_ERR; /* Internal error */ - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ - /* Clean-up the stretched table */ - if (_FS_EXFAT) dp->obj.stat |= 4; /* The directory needs to be updated */ - if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */ - mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */ - for (n = 0, fs->winsect = clust2sect(fs, clst); n < fs->csize; n++, fs->winsect++) { /* Fill the new cluster with 0 */ - fs->wflag = 1; - if (sync_window(fs) != FR_OK) return FR_DISK_ERR; - } - fs->winsect -= n; /* Restore window offset */ -#else - if (!stretch) dp->sect = 0; /* If no stretch, report EOT (this is to suppress warning) */ - dp->sect = 0; return FR_NO_FILE; /* Report EOT */ -#endif - } - dp->clust = clst; /* Initialize data for new cluster */ - dp->sect = clust2sect(fs, clst); - } - } - } - dp->dptr = ofs; /* Current entry */ - dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */ - - return FR_OK; -} - - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Directory handling - Reserve a block of directory entries */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */ - DIR* dp, /* Pointer to the directory object */ - UINT nent /* Number of contiguous entries to allocate */ -) -{ - FRESULT res; - UINT n; - FATFS *fs = dp->obj.fs; - - - res = dir_sdi(dp, 0); - if (res == FR_OK) { - n = 0; - do { - res = move_window(fs, dp->sect); - if (res != FR_OK) break; -#if _FS_EXFAT - if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) { -#else - if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) { -#endif - if (++n == nent) break; /* A block of contiguous free entries is found */ - } else { - n = 0; /* Not a blank entry. Restart to search */ - } - res = dir_next(dp, 1); - } while (res == FR_OK); /* Next entry with table stretch enabled */ - } - - if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ - return res; -} - -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* FAT: Directory handling - Load/Store start cluster number */ -/*-----------------------------------------------------------------------*/ - -static -DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */ - FATFS* fs, /* Pointer to the fs object */ - const BYTE* dir /* Pointer to the key entry */ -) -{ - DWORD cl; - - cl = ld_word(dir + DIR_FstClusLO); - if (fs->fs_type == FS_FAT32) { - cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16; - } - - return cl; -} - - -#if !_FS_READONLY -static -void st_clust ( - FATFS* fs, /* Pointer to the fs object */ - BYTE* dir, /* Pointer to the key entry */ - DWORD cl /* Value to be set */ -) -{ - st_word(dir + DIR_FstClusLO, (WORD)cl); - if (fs->fs_type == FS_FAT32) { - st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16)); - } -} -#endif - - - -#if _USE_LFN != 0 -/*------------------------------------------------------------------------*/ -/* FAT-LFN: LFN handling */ -/*------------------------------------------------------------------------*/ -static -const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN characters in the directory entry */ - - -/*--------------------------------------------------------*/ -/* FAT-LFN: Compare a part of file name with an LFN entry */ -/*--------------------------------------------------------*/ -static -int cmp_lfn ( /* 1:matched, 0:not matched */ - const WCHAR* lfnbuf, /* Pointer to the LFN working buffer to be compared */ - BYTE* dir /* Pointer to the directory entry containing the part of LFN */ -) -{ - UINT i, s; - WCHAR wc, uc; - - - if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */ - - i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ - - for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ - uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ - if (wc) { - if (i >= _MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) { /* Compare it */ - return 0; /* Not matched */ - } - wc = uc; - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ - } - } - - if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0; /* Last segment matched but different length */ - - return 1; /* The part of LFN matched */ -} - - -#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT -/*-----------------------------------------------------*/ -/* FAT-LFN: Pick a part of file name from an LFN entry */ -/*-----------------------------------------------------*/ -static -int pick_lfn ( /* 1:succeeded, 0:buffer overflow or invalid LFN entry */ - WCHAR* lfnbuf, /* Pointer to the LFN working buffer */ - BYTE* dir /* Pointer to the LFN entry */ -) -{ - UINT i, s; - WCHAR wc, uc; - - - if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */ - - i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ - - for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ - uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ - if (wc) { - if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - lfnbuf[i++] = wc = uc; /* Store it */ - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ - } - } - - if (dir[LDIR_Ord] & LLEF) { /* Put terminator if it is the last LFN part */ - if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - lfnbuf[i] = 0; - } - - return 1; /* The part of LFN is valid */ -} -#endif - - -#if !_FS_READONLY -/*-----------------------------------------*/ -/* FAT-LFN: Create an entry of LFN entries */ -/*-----------------------------------------*/ -static -void put_lfn ( - const WCHAR* lfn, /* Pointer to the LFN */ - BYTE* dir, /* Pointer to the LFN entry to be created */ - BYTE ord, /* LFN order (1-20) */ - BYTE sum /* Checksum of the corresponding SFN */ -) -{ - UINT i, s; - WCHAR wc; - - - dir[LDIR_Chksum] = sum; /* Set checksum */ - dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ - dir[LDIR_Type] = 0; - st_word(dir + LDIR_FstClusLO, 0); - - i = (ord - 1) * 13; /* Get offset in the LFN working buffer */ - s = wc = 0; - do { - if (wc != 0xFFFF) wc = lfn[i++]; /* Get an effective character */ - st_word(dir + LfnOfs[s], wc); /* Put it */ - if (wc == 0) wc = 0xFFFF; /* Padding characters for left locations */ - } while (++s < 13); - if (wc == 0xFFFF || !lfn[i]) ord |= LLEF; /* Last LFN part is the start of LFN sequence */ - dir[LDIR_Ord] = ord; /* Set the LFN order */ -} - -#endif /* !_FS_READONLY */ -#endif /* _USE_LFN != 0 */ - - - -#if _USE_LFN != 0 && !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* FAT-LFN: Create a Numbered SFN */ -/*-----------------------------------------------------------------------*/ - -static -void gen_numname ( - BYTE* dst, /* Pointer to the buffer to store numbered SFN */ - const BYTE* src, /* Pointer to SFN */ - const WCHAR* lfn, /* Pointer to LFN */ - UINT seq /* Sequence number */ -) -{ - BYTE ns[8], c; - UINT i, j; - WCHAR wc; - DWORD sr; - - - mem_cpy(dst, src, 11); - - if (seq > 5) { /* In case of many collisions, generate a hash number instead of sequential number */ - sr = seq; - while (*lfn) { /* Create a CRC */ - wc = *lfn++; - for (i = 0; i < 16; i++) { - sr = (sr << 1) + (wc & 1); - wc >>= 1; - if (sr & 0x10000) sr ^= 0x11021; - } - } - seq = (UINT)sr; - } - - /* itoa (hexdecimal) */ - i = 7; - do { - c = (BYTE)((seq % 16) + '0'); - if (c > '9') c += 7; - ns[i--] = c; - seq /= 16; - } while (seq); - ns[i] = '~'; - - /* Append the number */ - for (j = 0; j < i && dst[j] != ' '; j++) { - if (IsDBCS1(dst[j])) { - if (j == i - 1) break; - j++; - } - } - do { - dst[j++] = (i < 8) ? ns[i++] : ' '; - } while (j < 8); -} -#endif /* _USE_LFN != 0 && !_FS_READONLY */ - - - -#if _USE_LFN != 0 -/*-----------------------------------------------------------------------*/ -/* FAT-LFN: Calculate checksum of an SFN entry */ -/*-----------------------------------------------------------------------*/ - -static -BYTE sum_sfn ( - const BYTE* dir /* Pointer to the SFN entry */ -) -{ - BYTE sum = 0; - UINT n = 11; - - do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); - return sum; -} - -#endif /* _USE_LFN != 0 */ - - - -#if _FS_EXFAT -/*-----------------------------------------------------------------------*/ -/* exFAT: Checksum */ -/*-----------------------------------------------------------------------*/ - -static -WORD xdir_sum ( /* Get checksum of the directoly block */ - const BYTE* dir /* Directory entry block to be calculated */ -) -{ - UINT i, szblk; - WORD sum; - - - szblk = (dir[XDIR_NumSec] + 1) * SZDIRE; - for (i = sum = 0; i < szblk; i++) { - if (i == XDIR_SetSum) { /* Skip sum field */ - i++; - } else { - sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i]; - } - } - return sum; -} - - - -static -WORD xname_sum ( /* Get check sum (to be used as hash) of the name */ - const WCHAR* name /* File name to be calculated */ -) -{ - WCHAR chr; - WORD sum = 0; - - - while ((chr = *name++) != 0) { - chr = ff_wtoupper(chr); /* File name needs to be ignored case */ - sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF); - sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8); - } - return sum; -} - - -#if !_FS_READONLY && _USE_MKFS -static -DWORD xsum32 ( - BYTE dat, /* Data to be sumed */ - DWORD sum /* Previous value */ -) -{ - sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat; - return sum; -} -#endif - - -#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 -/*------------------------------------------------------*/ -/* exFAT: Get object information from a directory block */ -/*------------------------------------------------------*/ - -static -void get_xdir_info ( - BYTE* dirb, /* Pointer to the direcotry entry block 85+C0+C1s */ - FILINFO* fno /* Buffer to store the extracted file information */ -) -{ - UINT di, si; - WCHAR w; -#if !_LFN_UNICODE - UINT nc; -#endif - - /* Get file name */ -#if _LFN_UNICODE - if (dirb[XDIR_NumName] <= _MAX_LFN) { - for (si = SZDIRE * 2, di = 0; di < dirb[XDIR_NumName]; si += 2, di++) { - if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */ - w = ld_word(dirb + si); /* Get a character */ - fno->fname[di] = w; /* Store it */ - } - } else { - di = 0; /* Buffer overflow and inaccessible object */ - } -#else - for (si = SZDIRE * 2, di = nc = 0; nc < dirb[XDIR_NumName]; si += 2, nc++) { - if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */ - w = ld_word(dirb + si); /* Get a character */ - w = ff_convert(w, 0); /* Unicode -> OEM */ - if (w == 0) { di = 0; break; } /* Could not be converted and inaccessible object */ - if (_DF1S && w >= 0x100) { /* Put 1st byte if it is a DBC (always false at SBCS cfg) */ - fno->fname[di++] = (char)(w >> 8); - } - if (di >= _MAX_LFN) { di = 0; break; } /* Buffer overflow and inaccessible object */ - fno->fname[di++] = (char)w; - } -#endif - if (di == 0) fno->fname[di++] = '?'; /* Inaccessible object? */ - fno->fname[di] = 0; /* Terminate file name */ - - fno->altname[0] = 0; /* No SFN */ - fno->fattrib = dirb[XDIR_Attr]; /* Attribute */ - fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(dirb + XDIR_FileSize); /* Size */ - fno->ftime = ld_word(dirb + XDIR_ModTime + 0); /* Time */ - fno->fdate = ld_word(dirb + XDIR_ModTime + 2); /* Date */ -} - -#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */ - - -/*-----------------------------------*/ -/* exFAT: Get a directry entry block */ -/*-----------------------------------*/ - -static -FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */ - DIR* dp /* Pointer to the reading direcotry object pointing the 85 entry */ -) -{ - FRESULT res; - UINT i, nent; - BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the on-memory direcotry entry block 85+C0+C1s */ - - - /* Load 85 entry */ - res = move_window(dp->obj.fs, dp->sect); - if (res != FR_OK) return res; - if (dp->dir[XDIR_Type] != 0x85) return FR_INT_ERR; - mem_cpy(dirb, dp->dir, SZDIRE); - nent = dirb[XDIR_NumSec] + 1; - - /* Load C0 entry */ - res = dir_next(dp, 0); - if (res != FR_OK) return res; - res = move_window(dp->obj.fs, dp->sect); - if (res != FR_OK) return res; - if (dp->dir[XDIR_Type] != 0xC0) return FR_INT_ERR; - mem_cpy(dirb + SZDIRE, dp->dir, SZDIRE); - - /* Load C1 entries */ - if (nent < 3 || nent > 19) return FR_NO_FILE; - i = SZDIRE * 2; nent *= SZDIRE; - do { - res = dir_next(dp, 0); - if (res != FR_OK) return res; - res = move_window(dp->obj.fs, dp->sect); - if (res != FR_OK) return res; - if (dp->dir[XDIR_Type] != 0xC1) return FR_INT_ERR; - mem_cpy(dirb + i, dp->dir, SZDIRE); - i += SZDIRE; - } while (i < nent); - - /* Sanity check */ - if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR; - - return FR_OK; -} - - -#if !_FS_READONLY || _FS_RPATH != 0 -/*------------------------------------------------*/ -/* exFAT: Load the object's directory entry block */ -/*------------------------------------------------*/ -static -FRESULT load_obj_dir ( - DIR* dp, /* Blank directory object to be used to access containing direcotry */ - const _FDID* obj /* Object with containing directory information */ -) -{ - FRESULT res; - - - /* Open object containing directory */ - dp->obj.fs = obj->fs; - dp->obj.sclust = obj->c_scl; - dp->obj.stat = (BYTE)obj->c_size; - dp->obj.objsize = obj->c_size & 0xFFFFFF00; - dp->blk_ofs = obj->c_ofs; - - res = dir_sdi(dp, dp->blk_ofs); /* Goto the block location */ - if (res == FR_OK) { - res = load_xdir(dp); /* Load the object's entry block */ - } - return res; -} -#endif - - -#if !_FS_READONLY -/*-----------------------------------------------*/ -/* exFAT: Store the directory block to the media */ -/*-----------------------------------------------*/ -static -FRESULT store_xdir ( - DIR* dp /* Pointer to the direcotry object */ -) -{ - FRESULT res; - UINT nent; - BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the direcotry entry block 85+C0+C1s */ - - /* Create set sum */ - st_word(dirb + XDIR_SetSum, xdir_sum(dirb)); - nent = dirb[XDIR_NumSec] + 1; - - /* Store the set of directory to the volume */ - res = dir_sdi(dp, dp->blk_ofs); - while (res == FR_OK) { - res = move_window(dp->obj.fs, dp->sect); - if (res != FR_OK) break; - mem_cpy(dp->dir, dirb, SZDIRE); - dp->obj.fs->wflag = 1; - if (--nent == 0) break; - dirb += SZDIRE; - res = dir_next(dp, 0); - } - return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR; -} - - - -/*-------------------------------------------*/ -/* exFAT: Create a new directory enrty block */ -/*-------------------------------------------*/ - -static -void create_xdir ( - BYTE* dirb, /* Pointer to the direcotry entry block buffer */ - const WCHAR* lfn /* Pointer to the nul terminated file name */ -) -{ - UINT i; - BYTE nb, nc; - WCHAR chr; - - - mem_set(dirb, 0, 2 * SZDIRE); /* Initialize 85+C0 entry */ - dirb[XDIR_Type] = 0x85; - dirb[XDIR_Type + SZDIRE] = 0xC0; - st_word(dirb + XDIR_NameHash, xname_sum(lfn)); /* Set name hash */ - - i = SZDIRE * 2; /* C1 offset */ - nc = 0; nb = 1; chr = 1; - do { - dirb[i++] = 0xC1; dirb[i++] = 0; /* Entry type C1 */ - do { /* Fill name field */ - if (chr && (chr = lfn[nc]) != 0) nc++; /* Get a character if exist */ - st_word(dirb + i, chr); i += 2; /* Store it */ - } while (i % SZDIRE); - nb++; - } while (lfn[nc]); /* Fill next entry if any char follows */ - - dirb[XDIR_NumName] = nc; /* Set name length */ - dirb[XDIR_NumSec] = nb; /* Set number of C0+C1s */ -} - -#endif /* !_FS_READONLY */ -#endif /* _FS_EXFAT */ - - - -#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT -/*-----------------------------------------------------------------------*/ -/* Read an object from the directory */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_read ( - DIR* dp, /* Pointer to the directory object */ - int vol /* Filtered by 0:file/directory or 1:volume label */ -) -{ - FRESULT res = FR_NO_FILE; - FATFS *fs = dp->obj.fs; - BYTE a, c; -#if _USE_LFN != 0 - BYTE ord = 0xFF, sum = 0xFF; -#endif - - while (dp->sect) { - res = move_window(fs, dp->sect); - if (res != FR_OK) break; - c = dp->dir[DIR_Name]; /* Test for the entry type */ - if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of the directory */ -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ - if (_USE_LABEL && vol) { - if (c == 0x83) break; /* Volume label entry? */ - } else { - if (c == 0x85) { /* Start of the file entry block? */ - dp->blk_ofs = dp->dptr; /* Get location of the block */ - res = load_xdir(dp); /* Load the entry block */ - if (res == FR_OK) { - dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK; /* Get attribute */ - } - break; - } - } - } else -#endif - { /* On the FAT12/16/32 volume */ - dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; /* Get attribute */ -#if _USE_LFN != 0 /* LFN configuration */ - if (c == DDEM || c == '.' || (int)((a & ~AM_ARC) == AM_VOL) != vol) { /* An entry without valid data */ - ord = 0xFF; - } else { - if (a == AM_LFN) { /* An LFN entry is found */ - if (c & LLEF) { /* Is it start of an LFN sequence? */ - sum = dp->dir[LDIR_Chksum]; - c &= (BYTE)~LLEF; ord = c; - dp->blk_ofs = dp->dptr; - } - /* Check LFN validity and capture it */ - ord = (c == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; - } else { /* An SFN entry is found */ - if (ord || sum != sum_sfn(dp->dir)) { /* Is there a valid LFN? */ - dp->blk_ofs = 0xFFFFFFFF; /* It has no LFN. */ - } - break; - } - } -#else /* Non LFN configuration */ - if (c != DDEM && c != '.' && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol) { /* Is it a valid entry? */ - break; - } -#endif - } - res = dir_next(dp, 0); /* Next entry */ - if (res != FR_OK) break; - } - - if (res != FR_OK) dp->sect = 0; /* Terminate the read operation on error or EOT */ - return res; -} - -#endif /* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */ - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Find an object in the directory */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */ - DIR* dp /* Pointer to the directory object with the file name */ -) -{ - FRESULT res; - FATFS *fs = dp->obj.fs; - BYTE c; -#if _USE_LFN != 0 - BYTE a, ord, sum; -#endif - - res = dir_sdi(dp, 0); /* Rewind directory object */ - if (res != FR_OK) return res; -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ - BYTE nc; - UINT di, ni; - WORD hash = xname_sum(fs->lfnbuf); /* Hash value of the name to find */ - - while ((res = dir_read(dp, 0)) == FR_OK) { /* Read an item */ - if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue; /* Skip the comparison if hash value mismatched */ - for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) { /* Compare the name */ - if ((di % SZDIRE) == 0) di += 2; - if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break; - } - if (nc == 0 && !fs->lfnbuf[ni]) break; /* Name matched? */ - } - return res; - } -#endif - /* On the FAT12/16/32 volume */ -#if _USE_LFN != 0 - ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ -#endif - do { - res = move_window(fs, dp->sect); - if (res != FR_OK) break; - c = dp->dir[DIR_Name]; - if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ -#if _USE_LFN != 0 /* LFN configuration */ - dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; - if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ - ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ - } else { - if (a == AM_LFN) { /* An LFN entry is found */ - if (!(dp->fn[NSFLAG] & NS_NOLFN)) { - if (c & LLEF) { /* Is it start of LFN sequence? */ - sum = dp->dir[LDIR_Chksum]; - c &= (BYTE)~LLEF; ord = c; /* LFN start order */ - dp->blk_ofs = dp->dptr; /* Start offset of LFN */ - } - /* Check validity of the LFN entry and compare it with given name */ - ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; - } - } else { /* An SFN entry is found */ - if (!ord && sum == sum_sfn(dp->dir)) break; /* LFN matched? */ - if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */ - ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ - } - } -#else /* Non LFN configuration */ - dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK; - if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry? */ -#endif - res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK); - - return res; -} - - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Register an object to the directory */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */ - DIR* dp /* Target directory with object name to be created */ -) -{ - FRESULT res; - FATFS *fs = dp->obj.fs; -#if _USE_LFN != 0 /* LFN configuration */ - UINT n, nlen, nent; - BYTE sn[12], sum; - - - if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME; /* Check name validity */ - for (nlen = 0; fs->lfnbuf[nlen]; nlen++) ; /* Get lfn length */ - -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ - DIR dj; - - nent = (nlen + 14) / 15 + 2; /* Number of entries to allocate (85+C0+C1s) */ - res = dir_alloc(dp, nent); /* Allocate entries */ - if (res != FR_OK) return res; - dp->blk_ofs = dp->dptr - SZDIRE * (nent - 1); /* Set block position */ - - if (dp->obj.sclust != 0 && (dp->obj.stat & 4)) { /* Has the sub-directory been stretched? */ - dp->obj.stat &= 3; - dp->obj.objsize += (DWORD)fs->csize * SS(fs); /* Increase object size by cluster size */ - res = fill_fat_chain(&dp->obj); /* Complement FAT chain if needed */ - if (res != FR_OK) return res; - res = load_obj_dir(&dj, &dp->obj); - if (res != FR_OK) return res; /* Load the object status */ - st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize); /* Update the allocation status */ - st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize); - fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1; - res = store_xdir(&dj); /* Store the object status */ - if (res != FR_OK) return res; - } - - create_xdir(fs->dirbuf, fs->lfnbuf); /* Create on-memory directory block to be written later */ - return FR_OK; - } -#endif - /* On the FAT12/16/32 volume */ - mem_cpy(sn, dp->fn, 12); - if (sn[NSFLAG] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ - dp->fn[NSFLAG] = NS_NOLFN; /* Find only SFN */ - for (n = 1; n < 100; n++) { - gen_numname(dp->fn, sn, fs->lfnbuf, n); /* Generate a numbered name */ - res = dir_find(dp); /* Check if the name collides with existing SFN */ - if (res != FR_OK) break; - } - if (n == 100) return FR_DENIED; /* Abort if too many collisions */ - if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ - dp->fn[NSFLAG] = sn[NSFLAG]; - } - - /* Create an SFN with/without LFNs. */ - nent = (sn[NSFLAG] & NS_LFN) ? (nlen + 12) / 13 + 1 : 1; /* Number of entries to allocate */ - res = dir_alloc(dp, nent); /* Allocate entries */ - if (res == FR_OK && --nent) { /* Set LFN entry if needed */ - res = dir_sdi(dp, dp->dptr - nent * SZDIRE); - if (res == FR_OK) { - sum = sum_sfn(dp->fn); /* Checksum value of the SFN tied to the LFN */ - do { /* Store LFN entries in bottom first */ - res = move_window(fs, dp->sect); - if (res != FR_OK) break; - put_lfn(fs->lfnbuf, dp->dir, (BYTE)nent, sum); - fs->wflag = 1; - res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK && --nent); - } - } - -#else /* Non LFN configuration */ - res = dir_alloc(dp, 1); /* Allocate an entry for SFN */ - -#endif - - /* Set SFN entry */ - if (res == FR_OK) { - res = move_window(fs, dp->sect); - if (res == FR_OK) { - mem_set(dp->dir, 0, SZDIRE); /* Clean the entry */ - mem_cpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */ -#if _USE_LFN != 0 - dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT); /* Put NT flag */ -#endif - fs->wflag = 1; - } - } - - return res; -} - -#endif /* !_FS_READONLY */ - - - -#if !_FS_READONLY && _FS_MINIMIZE == 0 -/*-----------------------------------------------------------------------*/ -/* Remove an object from the directory */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */ - DIR* dp /* Directory object pointing the entry to be removed */ -) -{ - FRESULT res; - FATFS *fs = dp->obj.fs; -#if _USE_LFN != 0 /* LFN configuration */ - DWORD last = dp->dptr; - - res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs); /* Goto top of the entry block if LFN is exist */ - if (res == FR_OK) { - do { - res = move_window(fs, dp->sect); - if (res != FR_OK) break; - /* Mark an entry 'deleted' */ - if (_FS_EXFAT && fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ - dp->dir[XDIR_Type] &= 0x7F; - } else { /* On the FAT12/16/32 volume */ - dp->dir[DIR_Name] = DDEM; - } - fs->wflag = 1; - if (dp->dptr >= last) break; /* If reached last entry then all entries of the object has been deleted. */ - res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR; - } -#else /* Non LFN configuration */ - - res = move_window(fs, dp->sect); - if (res == FR_OK) { - dp->dir[DIR_Name] = DDEM; - fs->wflag = 1; - } -#endif - - return res; -} - -#endif /* !_FS_READONLY && _FS_MINIMIZE == 0 */ - - - -#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 -/*-----------------------------------------------------------------------*/ -/* Get file information from directory entry */ -/*-----------------------------------------------------------------------*/ - -static -void get_fileinfo ( /* No return code */ - DIR* dp, /* Pointer to the directory object */ - FILINFO* fno /* Pointer to the file information to be filled */ -) -{ - UINT i, j; - TCHAR c; - DWORD tm; -#if _USE_LFN != 0 - WCHAR w, lfv; - FATFS *fs = dp->obj.fs; -#endif - - - fno->fname[0] = 0; /* Invaidate file info */ - if (!dp->sect) return; /* Exit if read pointer has reached end of directory */ - -#if _USE_LFN != 0 /* LFN configuration */ -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ - get_xdir_info(fs->dirbuf, fno); - return; - } else -#endif - { /* On the FAT12/16/32 volume */ - if (dp->blk_ofs != 0xFFFFFFFF) { /* Get LFN if available */ - i = j = 0; - while ((w = fs->lfnbuf[j++]) != 0) { /* Get an LFN character */ -#if !_LFN_UNICODE - w = ff_convert(w, 0); /* Unicode -> OEM */ - if (w == 0) { i = 0; break; } /* No LFN if it could not be converted */ - if (_DF1S && w >= 0x100) { /* Put 1st byte if it is a DBC (always false at SBCS cfg) */ - fno->fname[i++] = (char)(w >> 8); - } -#endif - if (i >= _MAX_LFN) { i = 0; break; } /* No LFN if buffer overflow */ - fno->fname[i++] = (TCHAR)w; - } - fno->fname[i] = 0; /* Terminate the LFN */ - } - } - - i = j = 0; - lfv = fno->fname[i]; /* LFN is exist if non-zero */ - while (i < 11) { /* Copy name body and extension */ - c = (TCHAR)dp->dir[i++]; - if (c == ' ') continue; /* Skip padding spaces */ - if (c == RDDEM) c = (TCHAR)DDEM; /* Restore replaced DDEM character */ - if (i == 9) { /* Insert a . if extension is exist */ - if (!lfv) fno->fname[j] = '.'; - fno->altname[j++] = '.'; - } -#if _LFN_UNICODE - if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dp->dir[i])) { - c = c << 8 | dp->dir[i++]; - } - c = ff_convert(c, 1); /* OEM -> Unicode */ - if (!c) c = '?'; -#endif - fno->altname[j] = c; - if (!lfv) { - if (IsUpper(c) && (dp->dir[DIR_NTres] & (i >= 9 ? NS_EXT : NS_BODY))) { - c += 0x20; /* To lower */ - } - fno->fname[j] = c; - } - j++; - } - if (!lfv) { - fno->fname[j] = 0; - if (!dp->dir[DIR_NTres]) j = 0; /* Altname is no longer needed if neither LFN nor case info is exist. */ - } - fno->altname[j] = 0; /* Terminate the SFN */ - -#else /* Non-LFN configuration */ - i = j = 0; - while (i < 11) { /* Copy name body and extension */ - c = (TCHAR)dp->dir[i++]; - if (c == ' ') continue; /* Skip padding spaces */ - if (c == RDDEM) c = (TCHAR)DDEM; /* Restore replaced DDEM character */ - if (i == 9) fno->fname[j++] = '.'; /* Insert a . if extension is exist */ - fno->fname[j++] = c; - } - fno->fname[j] = 0; -#endif - - fno->fattrib = dp->dir[DIR_Attr]; /* Attribute */ - fno->fsize = ld_dword(dp->dir + DIR_FileSize); /* Size */ - tm = ld_dword(dp->dir + DIR_ModTime); /* Timestamp */ - fno->ftime = (WORD)tm; fno->fdate = (WORD)(tm >> 16); -} - -#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */ - - - -#if _USE_FIND && _FS_MINIMIZE <= 1 -/*-----------------------------------------------------------------------*/ -/* Pattern matching */ -/*-----------------------------------------------------------------------*/ - -static -WCHAR get_achar ( /* Get a character and advances ptr 1 or 2 */ - const TCHAR** ptr /* Pointer to pointer to the SBCS/DBCS/Unicode string */ -) -{ -#if !_LFN_UNICODE - WCHAR chr; - - chr = (BYTE)*(*ptr)++; /* Get a byte */ - if (IsLower(chr)) chr -= 0x20; /* To upper ASCII char */ -#ifdef _EXCVT - if (chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ -#else - if (IsDBCS1(chr) && IsDBCS2(**ptr)) { /* Get DBC 2nd byte if needed */ - chr = chr << 8 | (BYTE)*(*ptr)++; - } -#endif - return chr; -#else - return ff_wtoupper(*(*ptr)++); /* Get a word and to upper */ -#endif -} - - -static -int pattern_matching ( /* 0:not matched, 1:matched */ - const TCHAR* pat, /* Matching pattern */ - const TCHAR* nam, /* String to be tested */ - int skip, /* Number of pre-skip chars (number of ?s) */ - int inf /* Infinite search (* specified) */ -) -{ - const TCHAR *pp, *np; - WCHAR pc, nc; - int nm, nx; - - - while (skip--) { /* Pre-skip name chars */ - if (!get_achar(&nam)) return 0; /* Branch mismatched if less name chars */ - } - if (!*pat && inf) return 1; /* (short circuit) */ - - do { - pp = pat; np = nam; /* Top of pattern and name to match */ - for (;;) { - if (*pp == '?' || *pp == '*') { /* Wildcard? */ - nm = nx = 0; - do { /* Analyze the wildcard chars */ - if (*pp++ == '?') nm++; else nx = 1; - } while (*pp == '?' || *pp == '*'); - if (pattern_matching(pp, np, nm, nx)) return 1; /* Test new branch (recurs upto number of wildcard blocks in the pattern) */ - nc = *np; break; /* Branch mismatched */ - } - pc = get_achar(&pp); /* Get a pattern char */ - nc = get_achar(&np); /* Get a name char */ - if (pc != nc) break; /* Branch mismatched? */ - if (pc == 0) return 1; /* Branch matched? (matched at end of both strings) */ - } - get_achar(&nam); /* nam++ */ - } while (inf && nc); /* Retry until end of name if infinite search is specified */ - - return 0; -} - -#endif /* _USE_FIND && _FS_MINIMIZE <= 1 */ - - - -/*-----------------------------------------------------------------------*/ -/* Pick a top segment and create the object name in directory form */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not create */ - DIR* dp, /* Pointer to the directory object */ - const TCHAR** path /* Pointer to pointer to the segment in the path string */ -) -{ -#if _USE_LFN != 0 /* LFN configuration */ - BYTE b, cf; - WCHAR w, *lfn; - UINT i, ni, si, di; - const TCHAR *p; - - /* Create LFN in Unicode */ - p = *path; lfn = dp->obj.fs->lfnbuf; si = di = 0; - for (;;) { - w = p[si++]; /* Get a character */ - if (w < ' ') break; /* Break if end of the path name */ - if (w == '/' || w == '\\') { /* Break if a separator is found */ - while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */ - break; - } - if (di >= _MAX_LFN) return FR_INVALID_NAME; /* Reject too long name */ -#if !_LFN_UNICODE - w &= 0xFF; - if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ - b = (BYTE)p[si++]; /* Get 2nd byte */ - w = (w << 8) + b; /* Create a DBC */ - if (!IsDBCS2(b)) return FR_INVALID_NAME; /* Reject invalid sequence */ - } - w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ - if (!w) return FR_INVALID_NAME; /* Reject invalid code */ -#endif - if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) return FR_INVALID_NAME; /* Reject illegal characters for LFN */ - lfn[di++] = w; /* Store the Unicode character */ - } - *path = &p[si]; /* Return pointer to the next segment */ - cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ -#if _FS_RPATH != 0 - if ((di == 1 && lfn[di - 1] == '.') || - (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { /* Is this segment a dot name? */ - lfn[di] = 0; - for (i = 0; i < 11; i++) /* Create dot name for SFN entry */ - dp->fn[i] = (i < di) ? '.' : ' '; - dp->fn[i] = cf | NS_DOT; /* This is a dot entry */ - return FR_OK; - } -#endif - while (di) { /* Snip off trailing spaces and dots if exist */ - w = lfn[di - 1]; - if (w != ' ' && w != '.') break; - di--; - } - lfn[di] = 0; /* LFN is created */ - if (di == 0) return FR_INVALID_NAME; /* Reject nul name */ - - /* Create SFN in directory form */ - mem_set(dp->fn, ' ', 11); - for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ - if (si) cf |= NS_LOSS | NS_LFN; - while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ - - i = b = 0; ni = 8; - for (;;) { - w = lfn[si++]; /* Get an LFN character */ - if (!w) break; /* Break on end of the LFN */ - if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ - cf |= NS_LOSS | NS_LFN; continue; - } - - if (i >= ni || si == di) { /* Extension or end of SFN */ - if (ni == 11) { /* Long extension */ - cf |= NS_LOSS | NS_LFN; break; - } - if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ - if (si > di) break; /* No extension */ - si = di; i = 8; ni = 11; /* Enter extension section */ - b <<= 2; continue; - } - - if (w >= 0x80) { /* Non ASCII character */ -#ifdef _EXCVT - w = ff_convert(w, 0); /* Unicode -> OEM code */ - if (w) w = ExCvt[w - 0x80]; /* Convert extended character to upper (SBCS) */ -#else - w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ -#endif - cf |= NS_LFN; /* Force create LFN entry */ - } - - if (_DF1S && w >= 0x100) { /* Is this DBC? (always false at SBCS cfg) */ - if (i >= ni - 1) { - cf |= NS_LOSS | NS_LFN; i = ni; continue; - } - dp->fn[i++] = (BYTE)(w >> 8); - } else { /* SBC */ - if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal characters for SFN */ - w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ - } else { - if (IsUpper(w)) { /* ASCII large capital */ - b |= 2; - } else { - if (IsLower(w)) { /* ASCII small capital */ - b |= 1; w -= 0x20; - } - } - } - } - dp->fn[i++] = (BYTE)w; - } - - if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ - - if (ni == 8) b <<= 2; - if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN; /* Create LFN entry when there are composite capitals */ - if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */ - if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ - if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ - } - - dp->fn[NSFLAG] = cf; /* SFN is created */ - - return FR_OK; - - -#else /* _USE_LFN != 0 : Non-LFN configuration */ - BYTE c, d, *sfn; - UINT ni, si, i; - const char *p; - - /* Create file name in directory form */ - p = *path; sfn = dp->fn; - mem_set(sfn, ' ', 11); - si = i = 0; ni = 8; -#if _FS_RPATH != 0 - if (p[si] == '.') { /* Is this a dot entry? */ - for (;;) { - c = (BYTE)p[si++]; - if (c != '.' || si >= 3) break; - sfn[i++] = c; - } - if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; - *path = p + si; /* Return pointer to the next segment */ - sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of the path */ - return FR_OK; - } -#endif - for (;;) { - c = (BYTE)p[si++]; - if (c <= ' ') break; /* Break if end of the path name */ - if (c == '/' || c == '\\') { /* Break if a separator is found */ - while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */ - break; - } - if (c == '.' || i >= ni) { /* End of body or over size? */ - if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Over size or invalid dot */ - i = 8; ni = 11; /* Goto extension */ - continue; - } - if (c >= 0x80) { /* Extended character? */ -#ifdef _EXCVT - c = ExCvt[c - 0x80]; /* To upper extended characters (SBCS cfg) */ -#else -#if !_DF1S - return FR_INVALID_NAME; /* Reject extended characters (ASCII only cfg) */ -#endif -#endif - } - if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false at SBCS cfg.) */ - d = (BYTE)p[si++]; /* Get 2nd byte */ - if (!IsDBCS2(d) || i >= ni - 1) return FR_INVALID_NAME; /* Reject invalid DBC */ - sfn[i++] = c; - sfn[i++] = d; - } else { /* SBC */ - if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) return FR_INVALID_NAME; /* Reject illegal chrs for SFN */ - if (IsLower(c)) c -= 0x20; /* To upper */ - sfn[i++] = c; - } - } - *path = p + si; /* Return pointer to the next segment */ - if (i == 0) return FR_INVALID_NAME; /* Reject nul string */ - - if (sfn[0] == DDEM) sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ - sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ - - return FR_OK; -#endif /* _USE_LFN != 0 */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* Follow a file path */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ - DIR* dp, /* Directory object to return last directory and found object */ - const TCHAR* path /* Full-path string to find a file or directory */ -) -{ - FRESULT res; - BYTE ns; - _FDID *obj = &dp->obj; - FATFS *fs = obj->fs; - - -#if _FS_RPATH != 0 - if (*path != '/' && *path != '\\') { /* Without heading separator */ - obj->sclust = fs->cdir; /* Start from the current directory */ - } else -#endif - { /* With heading separator */ - while (*path == '/' || *path == '\\') path++; /* Strip heading separator */ - obj->sclust = 0; /* Start from the root directory */ - } -#if _FS_EXFAT && _FS_RPATH != 0 - if (fs->fs_type == FS_EXFAT && obj->sclust) { /* Retrieve the sub-directory status if needed */ - DIR dj; - - obj->c_scl = fs->cdc_scl; - obj->c_size = fs->cdc_size; - obj->c_ofs = fs->cdc_ofs; - res = load_obj_dir(&dj, obj); - if (res != FR_OK) return res; - obj->objsize = ld_dword(fs->dirbuf + XDIR_FileSize); - obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; - } -#endif - - if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */ - dp->fn[NSFLAG] = NS_NONAME; - res = dir_sdi(dp, 0); - - } else { /* Follow path */ - for (;;) { - res = create_name(dp, &path); /* Get a segment name of the path */ - if (res != FR_OK) break; - res = dir_find(dp); /* Find an object with the segment name */ - ns = dp->fn[NSFLAG]; - if (res != FR_OK) { /* Failed to find the object */ - if (res == FR_NO_FILE) { /* Object is not found */ - if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */ - if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ - dp->fn[NSFLAG] = NS_NONAME; - res = FR_OK; - } else { /* Could not find the object */ - if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ - } - } - break; - } - if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ - /* Get into the sub-directory */ - if (!(obj->attr & AM_DIR)) { /* It is not a sub-directory and cannot follow */ - res = FR_NO_PATH; break; - } -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - obj->c_scl = obj->sclust; /* Save containing directory information for next dir */ - obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat; - obj->c_ofs = dp->blk_ofs; - obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Open next directory */ - obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; - obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); - } else -#endif - { - obj->sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs)); /* Open next directory */ - } - } - } - - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Get logical drive number from path name */ -/*-----------------------------------------------------------------------*/ - -static -int get_ldnumber ( /* Returns logical drive number (-1:invalid drive) */ - const TCHAR** path /* Pointer to pointer to the path name */ -) -{ - const TCHAR *tp, *tt; - UINT i; - int vol = -1; -#if _STR_VOLUME_ID /* Find string drive id */ - static const char* const str[] = {_VOLUME_STRS}; - const char *sp; - char c; - TCHAR tc; -#endif - - - if (*path) { /* If the pointer is not a null */ - for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ; /* Find ':' in the path */ - if (*tt == ':') { /* If a ':' is exist in the path name */ - tp = *path; - i = *tp++ - '0'; - if (i < 10 && tp == tt) { /* Is there a numeric drive id? */ - if (i < _VOLUMES) { /* If a drive id is found, get the value and strip it */ - vol = (int)i; - *path = ++tt; - } - } -#if _STR_VOLUME_ID - else { /* No numeric drive number, find string drive id */ - i = 0; tt++; - do { - sp = str[i]; tp = *path; - do { /* Compare a string drive id with path name */ - c = *sp++; tc = *tp++; - if (IsLower(tc)) tc -= 0x20; - } while (c && (TCHAR)c == tc); - } while ((c || tp != tt) && ++i < _VOLUMES); /* Repeat for each id until pattern match */ - if (i < _VOLUMES) { /* If a drive id is found, get the value and strip it */ - vol = (int)i; - *path = tt; - } - } -#endif - return vol; - } -#if _FS_RPATH != 0 && _VOLUMES >= 2 - vol = CurrVol; /* Current drive */ -#else - vol = 0; /* Drive 0 */ -#endif - } - return vol; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Load a sector and check if it is an FAT boot sector */ -/*-----------------------------------------------------------------------*/ - -static -BYTE check_fs ( /* 0:FAT, 1:exFAT, 2:Valid BS but not FAT, 3:Not a BS, 4:Disk error */ - FATFS* fs, /* File system object */ - DWORD sect /* Sector# (lba) to check if it is an FAT-VBR or not */ -) -{ - fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */ - if (move_window(fs, sect) != FR_OK) return 4; /* Load boot record */ - - if (ld_word(fs->win + BS_55AA) != 0xAA55) return 3; /* Check boot record signature (always placed at offset 510 even if the sector size is >512) */ - - if (fs->win[BS_JmpBoot] == 0xE9 || (fs->win[BS_JmpBoot] == 0xEB && fs->win[BS_JmpBoot + 2] == 0x90)) { - if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0; /* Check "FAT" string */ - if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0; /* Check "FAT3" string */ - } -#if _FS_EXFAT - if (!mem_cmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) return 1; -#endif - return 2; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Find logical drive and check if the volume is mounted */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */ - const TCHAR** path, /* Pointer to pointer to the path name (drive number) */ - FATFS** rfs, /* Pointer to pointer to the found file system object */ - BYTE mode /* !=0: Check write protection for write access */ -) -{ - BYTE fmt, *pt; - int vol; - DSTATUS stat; - DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4]; - WORD nrsv; - FATFS *fs; - UINT i; - - - /* Get logical drive number */ - *rfs = 0; - vol = get_ldnumber(path); - if (vol < 0) return FR_INVALID_DRIVE; - - /* Check if the file system object is valid or not */ - fs = FatFs[vol]; /* Get pointer to the file system object */ - if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ - - ENTER_FF(fs); /* Lock the volume */ - *rfs = fs; /* Return pointer to the file system object */ - - mode &= (BYTE)~FA_READ; /* Desired access mode, write access or not */ - if (fs->fs_type) { /* If the volume has been mounted */ - stat = disk_status(fs->drv); - if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ - if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ - return FR_WRITE_PROTECTED; - } - return FR_OK; /* The file system object is valid */ - } - } - - /* The file system object is not valid. */ - /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */ - - fs->fs_type = 0; /* Clear the file system object */ - fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ - stat = disk_initialize(fs->drv); /* Initialize the physical drive */ - if (stat & STA_NOINIT) { /* Check if the initialization succeeded */ - return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ - } - if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */ - return FR_WRITE_PROTECTED; - } -#if _MAX_SS != _MIN_SS /* Get sector size (multiple sector size cfg only) */ - if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR; - if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; -#endif - /* Find an FAT partition on the drive. Supports only generic partitioning, FDISK and SFD. */ - bsect = 0; - fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT-VBR as SFD */ - if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) { /* Not an FAT-VBR or forced partition number */ - for (i = 0; i < 4; i++) { /* Get partition offset */ - pt = fs->win + (MBR_Table + i * SZ_PTE); - br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0; - } - i = LD2PT(vol); /* Partition number: 0:auto, 1-4:forced */ - if (i) i--; - do { /* Find an FAT volume */ - bsect = br[i]; - fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */ - } while (!LD2PT(vol) && fmt >= 2 && ++i < 4); - } - if (fmt == 4) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ - if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ - - /* An FAT volume is found. Following code initializes the file system object */ - -#if _FS_EXFAT - if (fmt == 1) { - QWORD maxlba; - - for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ; /* Check zero filler */ - if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM; - - if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM; /* Check exFAT revision (Must be 1.0) */ - - if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) /* (BPB_BytsPerSecEx must be equal to the physical sector size) */ - return FR_NO_FILESYSTEM; - - maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect; /* Last LBA + 1 of the volume */ - if (maxlba >= 0x100000000) return FR_NO_FILESYSTEM; /* (It cannot be handled in 32-bit LBA) */ - - fs->fsize = ld_dword(fs->win + BPB_FatSzEx); /* Number of sectors per FAT */ - - fs->n_fats = fs->win[BPB_NumFATsEx]; /* Number of FATs */ - if (fs->n_fats != 1) return FR_NO_FILESYSTEM; /* (Supports only 1 FAT) */ - - fs->csize = 1 << fs->win[BPB_SecPerClusEx]; /* Cluster size */ - if (fs->csize == 0) return FR_NO_FILESYSTEM; /* (Must be 1..32768) */ - - nclst = ld_dword(fs->win + BPB_NumClusEx); /* Number of clusters */ - if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM; /* (Too many clusters) */ - fs->n_fatent = nclst + 2; - - /* Boundaries and Limits */ - fs->volbase = bsect; - fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx); - fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx); - if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM; /* (Volume size must not be smaller than the size requiered) */ - fs->dirbase = ld_dword(fs->win + BPB_RootClusEx); - - /* Check if bitmap location is in assumption (at the first cluster) */ - if (move_window(fs, clust2sect(fs, fs->dirbase)) != FR_OK) return FR_DISK_ERR; - for (i = 0; i < SS(fs); i += SZDIRE) { - if (fs->win[i] == 0x81 && ld_dword(fs->win + i + 20) == 2) break; /* 81 entry with cluster #2? */ - } - if (i == SS(fs)) return FR_NO_FILESYSTEM; -#if !_FS_READONLY - fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ -#endif - fmt = FS_EXFAT; /* FAT sub-type */ - } else -#endif /* _FS_EXFAT */ - { - if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must be equal to the physical sector size) */ - - fasize = ld_word(fs->win + BPB_FATSz16); /* Number of sectors per FAT */ - if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32); - fs->fsize = fasize; - - fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FATs */ - if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ - fasize *= fs->n_fats; /* Number of sectors for FAT area */ - - fs->csize = fs->win[BPB_SecPerClus]; /* Cluster size */ - if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ - - fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt); /* Number of root directory entries */ - if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ - - tsect = ld_word(fs->win + BPB_TotSec16); /* Number of sectors on the volume */ - if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32); - - nrsv = ld_word(fs->win + BPB_RsvdSecCnt); /* Number of reserved sectors */ - if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */ - - /* Determine the FAT sub type */ - sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE); /* RSV + FAT + DIR */ - if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ - if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - fmt = FS_FAT32; - if (nclst <= MAX_FAT16) fmt = FS_FAT16; - if (nclst <= MAX_FAT12) fmt = FS_FAT12; - - /* Boundaries and Limits */ - fs->n_fatent = nclst + 2; /* Number of FAT entries */ - fs->volbase = bsect; /* Volume start sector */ - fs->fatbase = bsect + nrsv; /* FAT start sector */ - fs->database = bsect + sysect; /* Data start sector */ - if (fmt == FS_FAT32) { - if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0) */ - if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ - fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */ - szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ - } else { - if (fs->n_rootdir == 0) return FR_NO_FILESYSTEM;/* (BPB_RootEntCnt must not be 0) */ - fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ - szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ - fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); - } - if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_FATSz must not be less than the size needed) */ - -#if !_FS_READONLY - /* Get FSINFO if available */ - fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ - fs->fsi_flag = 0x80; -#if (_FS_NOFSINFO & 3) != 3 - if (fmt == FS_FAT32 /* Enable FSINFO only if FAT32 and BPB_FSInfo32 == 1 */ - && ld_word(fs->win + BPB_FSInfo32) == 1 - && move_window(fs, bsect + 1) == FR_OK) - { - fs->fsi_flag = 0; - if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSINFO data if available */ - && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 - && ld_dword(fs->win + FSI_StrucSig) == 0x61417272) - { -#if (_FS_NOFSINFO & 1) == 0 - fs->free_clst = ld_dword(fs->win + FSI_Free_Count); -#endif -#if (_FS_NOFSINFO & 2) == 0 - fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free); -#endif - } - } -#endif /* (_FS_NOFSINFO & 3) != 3 */ -#endif /* !_FS_READONLY */ - } - - fs->fs_type = fmt; /* FAT sub-type */ - fs->id = ++Fsid; /* File system mount ID */ -#if _USE_LFN == 1 - fs->lfnbuf = LfnBuf; /* Static LFN working buffer */ -#if _FS_EXFAT - fs->dirbuf = DirBuf; /* Static directory block working buuffer */ -#endif -#endif -#if _FS_RPATH != 0 - fs->cdir = 0; /* Initialize current directory */ -#endif -#if _FS_LOCK != 0 /* Clear file lock semaphores */ - clear_lock(fs); -#endif - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Check if the file/directory object is valid or not */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */ - _FDID* obj, /* Pointer to the _OBJ, the 1st member in the FIL/DIR object, to check validity */ - FATFS** fs /* Pointer to pointer to the owner file system object to return */ -) -{ - FRESULT res; - - - if (!obj || !obj->fs || !obj->fs->fs_type || obj->fs->id != obj->id || (disk_status(obj->fs->drv) & STA_NOINIT)) { - *fs = 0; /* The object is invalid */ - res = FR_INVALID_OBJECT; - } else { - *fs = obj->fs; /* Owner file sytem object */ - ENTER_FF(obj->fs); /* Lock file system */ - res = FR_OK; - } - return res; -} - - - - -/*--------------------------------------------------------------------------- - - Public Functions (FatFs API) - -----------------------------------------------------------------------------*/ - - - -/*-----------------------------------------------------------------------*/ -/* Mount/Unmount a Logical Drive */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_mount ( - FATFS* fs, /* Pointer to the file system object (NULL:unmount)*/ - const TCHAR* path, /* Logical drive number to be mounted/unmounted */ - BYTE opt /* Mode option 0:Do not mount (delayed mount), 1:Mount immediately */ -) -{ - FATFS *cfs; - int vol; - FRESULT res; - const TCHAR *rp = path; - - - /* Get logical drive number */ - vol = get_ldnumber(&rp); - if (vol < 0) return FR_INVALID_DRIVE; - cfs = FatFs[vol]; /* Pointer to fs object */ - - if (cfs) { -#if _FS_LOCK != 0 - clear_lock(cfs); -#endif -#if _FS_REENTRANT /* Discard sync object of the current volume */ - if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR; -#endif - cfs->fs_type = 0; /* Clear old fs object */ - } - - if (fs) { - fs->fs_type = 0; /* Clear new fs object */ -#if _FS_REENTRANT /* Create sync object for the new volume */ - if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR; -#endif - } - FatFs[vol] = fs; /* Register new fs object */ - - if (!fs || opt != 1) return FR_OK; /* Do not mount now, it will be mounted later */ - - res = find_volume(&path, &fs, 0); /* Force mounted the volume */ - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Open or Create a File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_open ( - FIL* fp, /* Pointer to the blank file object */ - const TCHAR* path, /* Pointer to the file name */ - BYTE mode /* Access mode and file open mode flags */ -) -{ - FRESULT res; - DIR dj; - FATFS *fs; -#if !_FS_READONLY - DWORD dw, cl, bcs, clst, sc; - FSIZE_t ofs; -#endif - DEF_NAMBUF - - - if (!fp) return FR_INVALID_OBJECT; - - /* Get logical drive */ - mode &= _FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND | FA_SEEKEND; - res = find_volume(&path, &fs, mode); - if (res == FR_OK) { - dj.obj.fs = fs; - INIT_NAMBUF(fs); - res = follow_path(&dj, path); /* Follow the file path */ -#if !_FS_READONLY /* R/W configuration */ - if (res == FR_OK) { - if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ - res = FR_INVALID_NAME; - } -#if _FS_LOCK != 0 - else { - res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); - } -#endif - } - /* Create or Open a file */ - if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { - if (res != FR_OK) { /* No file, create new */ - if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ -#if _FS_LOCK != 0 - res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; -#else - res = dir_register(&dj); -#endif - mode |= FA_CREATE_ALWAYS; /* File is created */ - } - else { /* Any object is already existing */ - if (dj.obj.attr & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ - res = FR_DENIED; - } else { - if (mode & FA_CREATE_NEW) res = FR_EXIST; /* Cannot create as new file */ - } - } - if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ - dw = GET_FATTIME(); -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - /* Get current allocation info */ - fp->obj.fs = fs; - fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus); - fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize); - fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; - /* Initialize directory entry block */ - st_dword(fs->dirbuf + XDIR_CrtTime, dw); /* Set created time */ - fs->dirbuf[XDIR_CrtTime10] = 0; - st_dword(fs->dirbuf + XDIR_ModTime, dw); /* Set modified time */ - fs->dirbuf[XDIR_ModTime10] = 0; - fs->dirbuf[XDIR_Attr] = AM_ARC; /* Reset attribute */ - st_dword(fs->dirbuf + XDIR_FstClus, 0); /* Reset file allocation info */ - st_qword(fs->dirbuf + XDIR_FileSize, 0); - st_qword(fs->dirbuf + XDIR_ValidFileSize, 0); - fs->dirbuf[XDIR_GenFlags] = 1; - res = store_xdir(&dj); - if (res == FR_OK && fp->obj.sclust) { /* Remove the cluster chain if exist */ - res = remove_chain(&fp->obj, fp->obj.sclust, 0); - fs->last_clst = fp->obj.sclust - 1; /* Reuse the cluster hole */ - } - } else -#endif - { - /* Clean directory info */ - st_dword(dj.dir + DIR_CrtTime, dw); /* Set created time */ - st_dword(dj.dir + DIR_ModTime, dw); /* Set modified time */ - dj.dir[DIR_Attr] = AM_ARC; /* Reset attribute */ - cl = ld_clust(fs, dj.dir); /* Get cluster chain */ - st_clust(fs, dj.dir, 0); /* Reset file allocation info */ - st_dword(dj.dir + DIR_FileSize, 0); - fs->wflag = 1; - - if (cl) { /* Remove the cluster chain if exist */ - dw = fs->winsect; - res = remove_chain(&dj.obj, cl, 0); - if (res == FR_OK) { - res = move_window(fs, dw); - fs->last_clst = cl - 1; /* Reuse the cluster hole */ - } - } - } - } - } - else { /* Open an existing file */ - if (res == FR_OK) { /* Following succeeded */ - if (dj.obj.attr & AM_DIR) { /* It is a directory */ - res = FR_NO_FILE; - } else { - if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* R/O violation */ - res = FR_DENIED; - } - } - } - } - if (res == FR_OK) { - if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ - mode |= FA_MODIFIED; - fp->dir_sect = fs->winsect; /* Pointer to the directory entry */ - fp->dir_ptr = dj.dir; -#if _FS_LOCK != 0 - fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); - if (!fp->obj.lockid) res = FR_INT_ERR; -#endif - } -#else /* R/O configuration */ - if (res == FR_OK) { - if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ - res = FR_INVALID_NAME; - } else { - if (dj.obj.attr & AM_DIR) { /* It is a directory */ - res = FR_NO_FILE; - } - } - } -#endif - - if (res == FR_OK) { -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Get allocation info */ - fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize); - fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; - fp->obj.c_scl = dj.obj.sclust; - fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; - fp->obj.c_ofs = dj.blk_ofs; - } else -#endif - { - fp->obj.sclust = ld_clust(fs, dj.dir); /* Get allocation info */ - fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); - } -#if _USE_FASTSEEK - fp->cltbl = 0; /* Disable fast seek mode */ -#endif - fp->obj.fs = fs; /* Validate the file object */ - fp->obj.id = fs->id; - fp->flag = mode; /* Set file access mode */ - fp->err = 0; /* Clear error flag */ - fp->sect = 0; /* Invalidate current data sector */ - fp->fptr = 0; /* Set file pointer top of the file */ -#if !_FS_READONLY -#if !_FS_TINY - mem_set(fp->buf, 0, _MAX_SS); /* Clear sector buffer */ -#endif - if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) { /* Seek to end of file if FA_OPEN_APPEND is specified */ - fp->fptr = fp->obj.objsize; /* Offset to seek */ - bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */ - clst = fp->obj.sclust; /* Follow the cluster chain */ - for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) { - clst = get_fat(&fp->obj, clst); - if (clst <= 1) res = FR_INT_ERR; - if (clst == 0xFFFFFFFF) res = FR_DISK_ERR; - } - fp->clust = clst; - if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */ - if ((sc = clust2sect(fs, clst)) == 0) { - res = FR_INT_ERR; - } else { - fp->sect = sc + (DWORD)(ofs / SS(fs)); -#if !_FS_TINY - if (disk_read(fs->drv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR; -#endif - } - } - } -#endif - } - - FREE_NAMBUF(); - } - - if (res != FR_OK) fp->obj.fs = 0; /* Invalidate file object on error */ - - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_read ( - FIL* fp, /* Pointer to the file object */ - void* buff, /* Pointer to data buffer */ - UINT btr, /* Number of bytes to read */ - UINT* br /* Pointer to number of bytes read */ -) -{ - FRESULT res; - FATFS *fs; - DWORD clst, sect; - FSIZE_t remain; - UINT rcnt, cc, csect; - BYTE *rbuff = (BYTE*)buff; - - - *br = 0; /* Clear read byte counter */ - res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ - if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ - remain = fp->obj.objsize - fp->fptr; - if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ - - for ( ; btr; /* Repeat until all data read */ - rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { - if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ - csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ - if (csect == 0) { /* On the cluster boundary? */ - if (fp->fptr == 0) { /* On the top of the file? */ - clst = fp->obj.sclust; /* Follow cluster chain from the origin */ - } else { /* Middle or end of the file */ -#if _USE_FASTSEEK - if (fp->cltbl) { - clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ - } else -#endif - { - clst = get_fat(&fp->obj, fp->clust); /* Follow cluster chain on the FAT */ - } - } - if (clst < 2) ABORT(fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - } - sect = clust2sect(fs, fp->clust); /* Get current sector */ - if (!sect) ABORT(fs, FR_INT_ERR); - sect += csect; - cc = btr / SS(fs); /* When remaining bytes >= sector size, */ - if (cc) { /* Read maximum contiguous sectors directly */ - if (csect + cc > fs->csize) { /* Clip at cluster boundary */ - cc = fs->csize - csect; - } - if (disk_read(fs->drv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); -#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ -#if _FS_TINY - if (fs->wflag && fs->winsect - sect < cc) { - mem_cpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs)); - } -#else - if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) { - mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); - } -#endif -#endif - rcnt = SS(fs) * cc; /* Number of bytes transferred */ - continue; - } -#if !_FS_TINY - if (fp->sect != sect) { /* Load data sector if not in cache */ -#if !_FS_READONLY - if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); - fp->flag &= (BYTE)~FA_DIRTY; - } -#endif - if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ - } -#endif - fp->sect = sect; - } - rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ - if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ -#if _FS_TINY - if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ - mem_cpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ -#else - mem_cpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ -#endif - } - - LEAVE_FF(fs, FR_OK); -} - - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Write File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_write ( - FIL* fp, /* Pointer to the file object */ - const void* buff, /* Pointer to the data to be written */ - UINT btw, /* Number of bytes to write */ - UINT* bw /* Pointer to number of bytes written */ -) -{ - FRESULT res; - FATFS *fs; - DWORD clst, sect; - UINT wcnt, cc, csect; - const BYTE *wbuff = (const BYTE*)buff; - - - *bw = 0; /* Clear write byte counter */ - res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ - if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ - - /* Check fptr wrap-around (file size cannot reach 4GiB on FATxx) */ - if ((!_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) { - btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr); - } - - for ( ; btw; /* Repeat until all data written */ - wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize, *bw += wcnt, btw -= wcnt) { - if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ - csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ - if (csect == 0) { /* On the cluster boundary? */ - if (fp->fptr == 0) { /* On the top of the file? */ - clst = fp->obj.sclust; /* Follow from the origin */ - if (clst == 0) { /* If no cluster is allocated, */ - clst = create_chain(&fp->obj, 0); /* create a new cluster chain */ - } - } else { /* On the middle or end of the file */ -#if _USE_FASTSEEK - if (fp->cltbl) { - clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ - } else -#endif - { - clst = create_chain(&fp->obj, fp->clust); /* Follow or stretch cluster chain on the FAT */ - } - } - if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ - if (clst == 1) ABORT(fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */ - } -#if _FS_TINY - if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Write-back sector cache */ -#else - if (fp->flag & FA_DIRTY) { /* Write-back sector cache */ - if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); - fp->flag &= (BYTE)~FA_DIRTY; - } -#endif - sect = clust2sect(fs, fp->clust); /* Get current sector */ - if (!sect) ABORT(fs, FR_INT_ERR); - sect += csect; - cc = btw / SS(fs); /* When remaining bytes >= sector size, */ - if (cc) { /* Write maximum contiguous sectors directly */ - if (csect + cc > fs->csize) { /* Clip at cluster boundary */ - cc = fs->csize - csect; - } - if (disk_write(fs->drv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); -#if _FS_MINIMIZE <= 2 -#if _FS_TINY - if (fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ - mem_cpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs)); - fs->wflag = 0; - } -#else - if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ - mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs)); - fp->flag &= (BYTE)~FA_DIRTY; - } -#endif -#endif - wcnt = SS(fs) * cc; /* Number of bytes transferred */ - continue; - } -#if _FS_TINY - if (fp->fptr >= fp->obj.objsize) { /* Avoid silly cache filling on the growing edge */ - if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); - fs->winsect = sect; - } -#else - if (fp->sect != sect && /* Fill sector cache with file data */ - fp->fptr < fp->obj.objsize && - disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) { - ABORT(fs, FR_DISK_ERR); - } -#endif - fp->sect = sect; - } - wcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ - if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ -#if _FS_TINY - if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ - mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ - fs->wflag = 1; -#else - mem_cpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ - fp->flag |= FA_DIRTY; -#endif - } - - fp->flag |= FA_MODIFIED; /* Set file change flag */ - - LEAVE_FF(fs, FR_OK); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Synchronize the File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_sync ( - FIL* fp /* Pointer to the file object */ -) -{ - FRESULT res; - FATFS *fs; - DWORD tm; - BYTE *dir; - // DEF_NAMBUF - - - res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res == FR_OK) { - if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */ -#if !_FS_TINY - if (fp->flag & FA_DIRTY) { /* Write-back cached data if needed */ - if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR); - fp->flag &= (BYTE)~FA_DIRTY; - } -#endif - /* Update the directory entry */ - tm = GET_FATTIME(); /* Modified time */ -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - res = fill_fat_chain(&fp->obj); /* Create FAT chain if needed */ - if (res == FR_OK) { - DIR dj; - - INIT_NAMBUF(fs); - res = load_obj_dir(&dj, &fp->obj); /* Load directory entry block */ - if (res == FR_OK) { - fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive bit */ - fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1; /* Update file allocation info */ - st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust); - st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize); - st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize); - st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Update modified time */ - fs->dirbuf[XDIR_ModTime10] = 0; - st_dword(fs->dirbuf + XDIR_AccTime, 0); - res = store_xdir(&dj); /* Restore it to the directory */ - if (res == FR_OK) { - res = sync_fs(fs); - fp->flag &= (BYTE)~FA_MODIFIED; - } - } - FREE_NAMBUF(); - } - } else -#endif - { - res = move_window(fs, fp->dir_sect); - if (res == FR_OK) { - dir = fp->dir_ptr; - dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ - st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation info */ - st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */ - st_dword(dir + DIR_ModTime, tm); /* Update modified time */ - st_word(dir + DIR_LstAccDate, 0); - fs->wflag = 1; - res = sync_fs(fs); /* Restore it to the directory */ - fp->flag &= (BYTE)~FA_MODIFIED; - } - } - } - } - - LEAVE_FF(fs, res); -} - -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Close File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_close ( - FIL* fp /* Pointer to the file object to be closed */ -) -{ - FRESULT res; - FATFS *fs; - -#if !_FS_READONLY - res = f_sync(fp); /* Flush cached data */ - if (res == FR_OK) -#endif - { - res = validate(&fp->obj, &fs); /* Lock volume */ - if (res == FR_OK) { -#if _FS_LOCK != 0 - res = dec_lock(fp->obj.lockid); /* Decrement file open counter */ - if (res == FR_OK) -#endif - { - fp->obj.fs = 0; /* Invalidate file object */ - } -#if _FS_REENTRANT - unlock_fs(fs, FR_OK); /* Unlock volume */ -#endif - } - } - return res; -} - - - - -#if _FS_RPATH >= 1 -/*-----------------------------------------------------------------------*/ -/* Change Current Directory or Current Drive, Get Current Directory */ -/*-----------------------------------------------------------------------*/ - -#if _VOLUMES >= 2 -FRESULT f_chdrive ( - const TCHAR* path /* Drive number */ -) -{ - int vol; - - - /* Get logical drive number */ - vol = get_ldnumber(&path); - if (vol < 0) return FR_INVALID_DRIVE; - - CurrVol = (BYTE)vol; /* Set it as current volume */ - - return FR_OK; -} -#endif - - -FRESULT f_chdir ( - const TCHAR* path /* Pointer to the directory path */ -) -{ - FRESULT res; - DIR dj; - FATFS *fs; - DEF_NAMBUF - - /* Get logical drive */ - res = find_volume(&path, &fs, 0); - if (res == FR_OK) { - dj.obj.fs = fs; - INIT_NAMBUF(fs); - res = follow_path(&dj, path); /* Follow the path */ - if (res == FR_OK) { /* Follow completed */ - if (dj.fn[NSFLAG] & NS_NONAME) { - fs->cdir = dj.obj.sclust; /* It is the start directory itself */ -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - fs->cdc_scl = dj.obj.c_scl; - fs->cdc_size = dj.obj.c_size; - fs->cdc_ofs = dj.obj.c_ofs; - } -#endif - } else { - if (dj.obj.attr & AM_DIR) { /* It is a sub-directory */ -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus); /* Sub-directory cluster */ - fs->cdc_scl = dj.obj.sclust; /* Save containing directory information */ - fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; - fs->cdc_ofs = dj.blk_ofs; - } else -#endif - { - fs->cdir = ld_clust(fs, dj.dir); /* Sub-directory cluster */ - } - } else { - res = FR_NO_PATH; /* Reached but a file */ - } - } - } - FREE_NAMBUF(); - if (res == FR_NO_FILE) res = FR_NO_PATH; - } - - LEAVE_FF(fs, res); -} - - -#if _FS_RPATH >= 2 -FRESULT f_getcwd ( - TCHAR* buff, /* Pointer to the directory path */ - UINT len /* Size of path */ -) -{ - FRESULT res; - DIR dj; - FATFS *fs; - UINT i, n; - DWORD ccl; - TCHAR *tp; - FILINFO fno; - DEF_NAMBUF - - - *buff = 0; - /* Get logical drive */ - res = find_volume((const TCHAR**)&buff, &fs, 0); /* Get current volume */ - if (res == FR_OK) { - dj.obj.fs = fs; - INIT_NAMBUF(fs); - i = len; /* Bottom of buffer (directory stack base) */ - if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* (Cannot do getcwd on exFAT and returns root path) */ - dj.obj.sclust = fs->cdir; /* Start to follow upper directory from current directory */ - while ((ccl = dj.obj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ - res = dir_sdi(&dj, 1 * SZDIRE); /* Get parent directory */ - if (res != FR_OK) break; - res = move_window(fs, dj.sect); - if (res != FR_OK) break; - dj.obj.sclust = ld_clust(fs, dj.dir); /* Goto parent directory */ - res = dir_sdi(&dj, 0); - if (res != FR_OK) break; - do { /* Find the entry links to the child directory */ - res = dir_read(&dj, 0); - if (res != FR_OK) break; - if (ccl == ld_clust(fs, dj.dir)) break; /* Found the entry */ - res = dir_next(&dj, 0); - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ - if (res != FR_OK) break; - get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ - for (n = 0; fno.fname[n]; n++) ; - if (i < n + 3) { - res = FR_NOT_ENOUGH_CORE; break; - } - while (n) buff[--i] = fno.fname[--n]; - buff[--i] = '/'; - } - } - tp = buff; - if (res == FR_OK) { -#if _VOLUMES >= 2 - *tp++ = '0' + CurrVol; /* Put drive number */ - *tp++ = ':'; -#endif - if (i == len) { /* Root-directory */ - *tp++ = '/'; - } else { /* Sub-directroy */ - do /* Add stacked path str */ - *tp++ = buff[i++]; - while (i < len); - } - } - *tp = 0; - FREE_NAMBUF(); - } - - LEAVE_FF(fs, res); -} - -#endif /* _FS_RPATH >= 2 */ -#endif /* _FS_RPATH >= 1 */ - - - -#if _FS_MINIMIZE <= 2 -/*-----------------------------------------------------------------------*/ -/* Seek File R/W Pointer */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_lseek ( - FIL* fp, /* Pointer to the file object */ - FSIZE_t ofs /* File pointer from top of file */ -) -{ - FRESULT res; - FATFS *fs; - DWORD clst, bcs, nsect; - FSIZE_t ifptr; -#if _USE_FASTSEEK - DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl; -#endif - - res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ -#if _USE_FASTSEEK - if (fp->cltbl) { /* Fast seek */ - if (ofs == CREATE_LINKMAP) { /* Create CLMT */ - tbl = fp->cltbl; - tlen = *tbl++; ulen = 2; /* Given table size and required table size */ - cl = fp->obj.sclust; /* Origin of the chain */ - if (cl) { - do { - /* Get a fragment */ - tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ - do { - pcl = cl; ncl++; - cl = get_fat(&fp->obj, cl); - if (cl <= 1) ABORT(fs, FR_INT_ERR); - if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); - } while (cl == pcl + 1); - if (ulen <= tlen) { /* Store the length and top of the fragment */ - *tbl++ = ncl; *tbl++ = tcl; - } - } while (cl < fs->n_fatent); /* Repeat until end of chain */ - } - *fp->cltbl = ulen; /* Number of items used */ - if (ulen <= tlen) { - *tbl = 0; /* Terminate table */ - } else { - res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ - } - } else { /* Fast seek */ - if (ofs > fp->obj.objsize) ofs = fp->obj.objsize; /* Clip offset at the file size */ - fp->fptr = ofs; /* Set file pointer */ - if (ofs) { - fp->clust = clmt_clust(fp, ofs - 1); - dsc = clust2sect(fs, fp->clust); - if (!dsc) ABORT(fs, FR_INT_ERR); - dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); - if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ -#if !_FS_TINY -#if !_FS_READONLY - if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); - fp->flag &= (BYTE)~FA_DIRTY; - } -#endif - if (disk_read(fs->drv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Load current sector */ -#endif - fp->sect = dsc; - } - } - } - } else -#endif - - /* Normal Seek */ - { -#if _FS_EXFAT - if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF; /* Clip at 4GiB-1 if at FATxx */ -#endif - if (ofs > fp->obj.objsize && (_FS_READONLY || !(fp->flag & FA_WRITE))) { /* In read-only mode, clip offset with the file size */ - ofs = fp->obj.objsize; - } - ifptr = fp->fptr; - fp->fptr = nsect = 0; - if (ofs) { - bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */ - if (ifptr > 0 && - (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ - fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ - ofs -= fp->fptr; - clst = fp->clust; - } else { /* When seek to back cluster, */ - clst = fp->obj.sclust; /* start from the first cluster */ -#if !_FS_READONLY - if (clst == 0) { /* If no cluster chain, create a new chain */ - clst = create_chain(&fp->obj, 0); - if (clst == 1) ABORT(fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); - fp->obj.sclust = clst; - } -#endif - fp->clust = clst; - } - if (clst != 0) { - while (ofs > bcs) { /* Cluster following loop */ - ofs -= bcs; fp->fptr += bcs; -#if !_FS_READONLY - if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ - if (_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize to generate FAT value */ - fp->obj.objsize = fp->fptr; - fp->flag |= FA_MODIFIED; - } - clst = create_chain(&fp->obj, clst); /* Follow chain with forceed stretch */ - if (clst == 0) { /* Clip file size in case of disk full */ - ofs = 0; break; - } - } else -#endif - { - clst = get_fat(&fp->obj, clst); /* Follow cluster chain if not in write mode */ - } - if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); - if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); - fp->clust = clst; - } - fp->fptr += ofs; - if (ofs % SS(fs)) { - nsect = clust2sect(fs, clst); /* Current sector */ - if (!nsect) ABORT(fs, FR_INT_ERR); - nsect += (DWORD)(ofs / SS(fs)); - } - } - } - if (!_FS_READONLY && fp->fptr > fp->obj.objsize) { /* Set file change flag if the file size is extended */ - fp->obj.objsize = fp->fptr; - fp->flag |= FA_MODIFIED; - } - if (fp->fptr % SS(fs) && nsect != fp->sect) { /* Fill sector cache if needed */ -#if !_FS_TINY -#if !_FS_READONLY - if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); - fp->flag &= (BYTE)~FA_DIRTY; - } -#endif - if (disk_read(fs->drv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ -#endif - fp->sect = nsect; - } - } - - LEAVE_FF(fs, res); -} - - - -#if _FS_MINIMIZE <= 1 -/*-----------------------------------------------------------------------*/ -/* Create a Directory Object */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_opendir ( - DIR* dp, /* Pointer to directory object to create */ - const TCHAR* path /* Pointer to the directory path */ -) -{ - FRESULT res; - FATFS *fs; - _FDID *obj; - DEF_NAMBUF - - - if (!dp) return FR_INVALID_OBJECT; - - /* Get logical drive */ - obj = &dp->obj; - res = find_volume(&path, &fs, 0); - if (res == FR_OK) { - obj->fs = fs; - INIT_NAMBUF(fs); - res = follow_path(dp, path); /* Follow the path to the directory */ - if (res == FR_OK) { /* Follow completed */ - if (!(dp->fn[NSFLAG] & NS_NONAME)) { /* It is not the origin directory itself */ - if (obj->attr & AM_DIR) { /* This object is a sub-directory */ -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - obj->c_scl = obj->sclust; /* Save containing directory inforamation */ - obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat; - obj->c_ofs = dp->blk_ofs; - obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Get object location and status */ - obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); - obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; - } else -#endif - { - obj->sclust = ld_clust(fs, dp->dir); /* Get object location */ - } - } else { /* This object is a file */ - res = FR_NO_PATH; - } - } - if (res == FR_OK) { - obj->id = fs->id; - res = dir_sdi(dp, 0); /* Rewind directory */ -#if _FS_LOCK != 0 - if (res == FR_OK) { - if (obj->sclust) { - obj->lockid = inc_lock(dp, 0); /* Lock the sub directory */ - if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES; - } else { - obj->lockid = 0; /* Root directory need not to be locked */ - } - } -#endif - } - } - FREE_NAMBUF(); - if (res == FR_NO_FILE) res = FR_NO_PATH; - } - if (res != FR_OK) obj->fs = 0; /* Invalidate the directory object if function faild */ - - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Close Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_closedir ( - DIR *dp /* Pointer to the directory object to be closed */ -) -{ - FRESULT res; - FATFS *fs; - - - res = validate(&dp->obj, &fs); /* Check validity of the file object */ - if (res == FR_OK) { -#if _FS_LOCK != 0 - if (dp->obj.lockid) { /* Decrement sub-directory open counter */ - res = dec_lock(dp->obj.lockid); - } - if (res == FR_OK) -#endif - { - dp->obj.fs = 0; /* Invalidate directory object */ - } -#if _FS_REENTRANT - unlock_fs(fs, FR_OK); /* Unlock volume */ -#endif - } - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read Directory Entries in Sequence */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_readdir ( - DIR* dp, /* Pointer to the open directory object */ - FILINFO* fno /* Pointer to file information to return */ -) -{ - FRESULT res; - FATFS *fs; - DEF_NAMBUF - - - res = validate(&dp->obj, &fs); /* Check validity of the directory object */ - if (res == FR_OK) { - if (!fno) { - res = dir_sdi(dp, 0); /* Rewind the directory object */ - } else { - INIT_NAMBUF(fs); - res = dir_read(dp, 0); /* Read an item */ - if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */ - if (res == FR_OK) { /* A valid entry is found */ - get_fileinfo(dp, fno); /* Get the object information */ - res = dir_next(dp, 0); /* Increment index for next */ - if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */ - } - FREE_NAMBUF(); - } - } - LEAVE_FF(fs, res); -} - - - -#if _USE_FIND -/*-----------------------------------------------------------------------*/ -/* Find Next File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_findnext ( - DIR* dp, /* Pointer to the open directory object */ - FILINFO* fno /* Pointer to the file information structure */ -) -{ - FRESULT res; - - - for (;;) { - res = f_readdir(dp, fno); /* Get a directory item */ - if (res != FR_OK || !fno || !fno->fname[0]) break; /* Terminate if any error or end of directory */ - if (pattern_matching(dp->pat, fno->fname, 0, 0)) break; /* Test for the file name */ -#if _USE_LFN != 0 && _USE_FIND == 2 - if (pattern_matching(dp->pat, fno->altname, 0, 0)) break; /* Test for alternative name if exist */ -#endif - } - return res; -} - - - -/*-----------------------------------------------------------------------*/ -/* Find First File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_findfirst ( - DIR* dp, /* Pointer to the blank directory object */ - FILINFO* fno, /* Pointer to the file information structure */ - const TCHAR* path, /* Pointer to the directory to open */ - const TCHAR* pattern /* Pointer to the matching pattern */ -) -{ - FRESULT res; - - - dp->pat = pattern; /* Save pointer to pattern string */ - res = f_opendir(dp, path); /* Open the target directory */ - if (res == FR_OK) { - res = f_findnext(dp, fno); /* Find the first item */ - } - return res; -} - -#endif /* _USE_FIND */ - - - -#if _FS_MINIMIZE == 0 -/*-----------------------------------------------------------------------*/ -/* Get File Status */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_stat ( - const TCHAR* path, /* Pointer to the file path */ - FILINFO* fno /* Pointer to file information to return */ -) -{ - FRESULT res; - DIR dj; - DEF_NAMBUF - - - /* Get logical drive */ - res = find_volume(&path, &dj.obj.fs, 0); - if (res == FR_OK) { - INIT_NAMBUF(dj.obj.fs); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK) { /* Follow completed */ - if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */ - res = FR_INVALID_NAME; - } else { /* Found an object */ - if (fno) get_fileinfo(&dj, fno); - } - } - FREE_NAMBUF(); - } - - LEAVE_FF(dj.obj.fs, res); -} - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Get Number of Free Clusters */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_getfree ( - const TCHAR* path, /* Path name of the logical drive number */ - DWORD* nclst, /* Pointer to a variable to return number of free clusters */ - FATFS** fatfs /* Pointer to return pointer to corresponding file system object */ -) -{ - FRESULT res; - FATFS *fs; - DWORD nfree, clst, sect, stat; - UINT i; - BYTE *p; - _FDID obj; - - - /* Get logical drive */ - res = find_volume(&path, &fs, 0); - if (res == FR_OK) { - *fatfs = fs; /* Return ptr to the fs object */ - /* If free_clst is valid, return it without full cluster scan */ - if (fs->free_clst <= fs->n_fatent - 2) { - *nclst = fs->free_clst; - } else { - /* Get number of free clusters */ - nfree = 0; - if (fs->fs_type == FS_FAT12) { /* FAT12: Sector unalighed FAT entries */ - clst = 2; obj.fs = fs; - do { - stat = get_fat(&obj, clst); - if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } - if (stat == 1) { res = FR_INT_ERR; break; } - if (stat == 0) nfree++; - } while (++clst < fs->n_fatent); - } else { -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { /* exFAT: Scan bitmap table */ - BYTE bm; - UINT b; - - clst = fs->n_fatent - 2; - sect = fs->database; - i = 0; - do { - if (i == 0 && (res = move_window(fs, sect++)) != FR_OK) break; - for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) { - if (!(bm & 1)) nfree++; - bm >>= 1; - } - i = (i + 1) % SS(fs); - } while (clst); - } else -#endif - { /* FAT16/32: Sector alighed FAT entries */ - clst = fs->n_fatent; sect = fs->fatbase; - i = 0; p = 0; - do { - if (i == 0) { - res = move_window(fs, sect++); - if (res != FR_OK) break; - p = fs->win; - i = SS(fs); - } - if (fs->fs_type == FS_FAT16) { - if (ld_word(p) == 0) nfree++; - p += 2; i -= 2; - } else { - if ((ld_dword(p) & 0x0FFFFFFF) == 0) nfree++; - p += 4; i -= 4; - } - } while (--clst); - } - } - *nclst = nfree; /* Return the free clusters */ - fs->free_clst = nfree; /* Now free_clst is valid */ - fs->fsi_flag |= 1; /* FSInfo is to be updated */ - } - } - - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Truncate File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_truncate ( - FIL* fp /* Pointer to the file object */ -) -{ - FRESULT res; - FATFS *fs; - DWORD ncl; - - - res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); - if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ - - if (fp->obj.objsize > fp->fptr) { - if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ - res = remove_chain(&fp->obj, fp->obj.sclust, 0); - fp->obj.sclust = 0; - } else { /* When truncate a part of the file, remove remaining clusters */ - ncl = get_fat(&fp->obj, fp->clust); - res = FR_OK; - if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (ncl == 1) res = FR_INT_ERR; - if (res == FR_OK && ncl < fs->n_fatent) { - res = remove_chain(&fp->obj, ncl, fp->clust); - } - } - fp->obj.objsize = fp->fptr; /* Set file size to current R/W point */ - fp->flag |= FA_MODIFIED; -#if !_FS_TINY - if (res == FR_OK && (fp->flag & FA_DIRTY)) { - if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) { - res = FR_DISK_ERR; - } else { - fp->flag &= (BYTE)~FA_DIRTY; - } - } -#endif - if (res != FR_OK) ABORT(fs, res); - } - - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Delete a File/Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_unlink ( - const TCHAR* path /* Pointer to the file or directory path */ -) -{ - FRESULT res; - DIR dj, sdj; - DWORD dclst = 0; - FATFS *fs; -#if _FS_EXFAT - _FDID obj; -#endif - DEF_NAMBUF - - - /* Get logical drive */ - res = find_volume(&path, &fs, FA_WRITE); - dj.obj.fs = fs; - if (res == FR_OK) { - INIT_NAMBUF(fs); - res = follow_path(&dj, path); /* Follow the file path */ - if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) { - res = FR_INVALID_NAME; /* Cannot remove dot entry */ - } -#if _FS_LOCK != 0 - if (res == FR_OK) res = chk_lock(&dj, 2); /* Check if it is an open object */ -#endif - if (res == FR_OK) { /* The object is accessible */ - if (dj.fn[NSFLAG] & NS_NONAME) { - res = FR_INVALID_NAME; /* Cannot remove the origin directory */ - } else { - if (dj.obj.attr & AM_RDO) { - res = FR_DENIED; /* Cannot remove R/O object */ - } - } - if (res == FR_OK) { -#if _FS_EXFAT - obj.fs = fs; - if (fs->fs_type == FS_EXFAT) { - obj.sclust = dclst = ld_dword(fs->dirbuf + XDIR_FstClus); - obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize); - obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; - } else -#endif - { - dclst = ld_clust(fs, dj.dir); - } - if (dj.obj.attr & AM_DIR) { /* Is it a sub-directory ? */ -#if _FS_RPATH != 0 - if (dclst == fs->cdir) { /* Is it the current directory? */ - res = FR_DENIED; - } else -#endif - { - sdj.obj.fs = fs; /* Open the sub-directory */ - sdj.obj.sclust = dclst; -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - sdj.obj.objsize = obj.objsize; - sdj.obj.stat = obj.stat; - } -#endif - res = dir_sdi(&sdj, 0); - if (res == FR_OK) { - res = dir_read(&sdj, 0); /* Read an item */ - if (res == FR_OK) res = FR_DENIED; /* Not empty? */ - if (res == FR_NO_FILE) res = FR_OK; /* Empty? */ - } - } - } - } - if (res == FR_OK) { - res = dir_remove(&dj); /* Remove the directory entry */ - if (res == FR_OK && dclst) { /* Remove the cluster chain if exist */ -#if _FS_EXFAT - res = remove_chain(&obj, dclst, 0); -#else - res = remove_chain(&dj.obj, dclst, 0); -#endif - } - if (res == FR_OK) res = sync_fs(fs); - } - } - FREE_NAMBUF(); - } - - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Create a Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_mkdir ( - const TCHAR* path /* Pointer to the directory path */ -) -{ - FRESULT res; - DIR dj; - FATFS *fs; - BYTE *dir; - UINT n; - DWORD dsc, dcl, pcl, tm; - DEF_NAMBUF - - - /* Get logical drive */ - res = find_volume(&path, &fs, FA_WRITE); - dj.obj.fs = fs; - if (res == FR_OK) { - INIT_NAMBUF(fs); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ - if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) { - res = FR_INVALID_NAME; - } - if (res == FR_NO_FILE) { /* Can create a new directory */ - dcl = create_chain(&dj.obj, 0); /* Allocate a cluster for the new directory table */ - dj.obj.objsize = (DWORD)fs->csize * SS(fs); - res = FR_OK; - if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ - if (dcl == 1) res = FR_INT_ERR; - if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (res == FR_OK) res = sync_window(fs); /* Flush FAT */ - tm = GET_FATTIME(); - if (res == FR_OK) { /* Initialize the new directory table */ - dsc = clust2sect(fs, dcl); - dir = fs->win; - mem_set(dir, 0, SS(fs)); - if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { - mem_set(dir + DIR_Name, ' ', 11); /* Create "." entry */ - dir[DIR_Name] = '.'; - dir[DIR_Attr] = AM_DIR; - st_dword(dir + DIR_ModTime, tm); - st_clust(fs, dir, dcl); - mem_cpy(dir + SZDIRE, dir, SZDIRE); /* Create ".." entry */ - dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust; - if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0; - st_clust(fs, dir + SZDIRE, pcl); - } - for (n = fs->csize; n; n--) { /* Write dot entries and clear following sectors */ - fs->winsect = dsc++; - fs->wflag = 1; - res = sync_window(fs); - if (res != FR_OK) break; - mem_set(dir, 0, SS(fs)); - } - } - if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ - if (res == FR_OK) { -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { /* Initialize directory entry block */ - st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Created time */ - st_dword(fs->dirbuf + XDIR_FstClus, dcl); /* Table start cluster */ - st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)dj.obj.objsize); /* File size needs to be valid */ - st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)dj.obj.objsize); - fs->dirbuf[XDIR_GenFlags] = 3; /* Initialize the object flag (contiguous) */ - fs->dirbuf[XDIR_Attr] = AM_DIR; /* Attribute */ - res = store_xdir(&dj); - } else -#endif - { - dir = dj.dir; - st_dword(dir + DIR_ModTime, tm); /* Created time */ - st_clust(fs, dir, dcl); /* Table start cluster */ - dir[DIR_Attr] = AM_DIR; /* Attribute */ - fs->wflag = 1; - } - if (res == FR_OK) res = sync_fs(fs); - } else { - remove_chain(&dj.obj, dcl, 0); /* Could not register, remove cluster chain */ - } - } - FREE_NAMBUF(); - } - - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Rename a File/Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_rename ( - const TCHAR* path_old, /* Pointer to the object name to be renamed */ - const TCHAR* path_new /* Pointer to the new name */ -) -{ - FRESULT res; - DIR djo, djn; - FATFS *fs; - BYTE buf[_FS_EXFAT ? SZDIRE * 2 : 24], *dir; - DWORD dw; - DEF_NAMBUF - - - get_ldnumber(&path_new); /* Ignore drive number of new name */ - res = find_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */ - if (res == FR_OK) { - djo.obj.fs = fs; - INIT_NAMBUF(fs); - res = follow_path(&djo, path_old); /* Check old object */ - if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check validity of name */ -#if _FS_LOCK != 0 - if (res == FR_OK) res = chk_lock(&djo, 2); -#endif - if (res == FR_OK) { /* Object to be renamed is found */ -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { /* At exFAT */ - BYTE nf, nn; - WORD nh; - - mem_cpy(buf, fs->dirbuf, SZDIRE * 2); /* Save 85+C0 entry of old object */ - mem_cpy(&djn, &djo, sizeof djo); - res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ - if (res == FR_OK) { /* Is new name already in use by any other object? */ - res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; - } - if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ - res = dir_register(&djn); /* Register the new entry */ - if (res == FR_OK) { - nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName]; - nh = ld_word(fs->dirbuf + XDIR_NameHash); - mem_cpy(fs->dirbuf, buf, SZDIRE * 2); - fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn; - st_word(fs->dirbuf + XDIR_NameHash, nh); -/* Start of critical section where any interruption can cause a cross-link */ - res = store_xdir(&djn); - } - } - } else -#endif - { /* At FAT12/FAT16/FAT32 */ - mem_cpy(buf, djo.dir + DIR_Attr, 21); /* Save information about the object except name */ - mem_cpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */ - res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ - if (res == FR_OK) { /* Is new name already in use by any other object? */ - res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; - } - if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ - res = dir_register(&djn); /* Register the new entry */ - if (res == FR_OK) { - dir = djn.dir; /* Copy information about object except name */ - mem_cpy(dir + 13, buf + 2, 19); - dir[DIR_Attr] = buf[0] | AM_ARC; - fs->wflag = 1; - if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the sub-directory if needed */ - dw = clust2sect(fs, ld_clust(fs, dir)); - if (!dw) { - res = FR_INT_ERR; - } else { -/* Start of critical section where any interruption can cause a cross-link */ - res = move_window(fs, dw); - dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */ - if (res == FR_OK && dir[1] == '.') { - st_clust(fs, dir, djn.obj.sclust); - fs->wflag = 1; - } - } - } - } - } - } - if (res == FR_OK) { - res = dir_remove(&djo); /* Remove old entry */ - if (res == FR_OK) { - res = sync_fs(fs); - } - } -/* End of critical section */ - } - FREE_NAMBUF(); - } - - LEAVE_FF(fs, res); -} - -#endif /* !_FS_READONLY */ -#endif /* _FS_MINIMIZE == 0 */ -#endif /* _FS_MINIMIZE <= 1 */ -#endif /* _FS_MINIMIZE <= 2 */ - - - -#if _USE_CHMOD && !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Change Attribute */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_chmod ( - const TCHAR* path, /* Pointer to the file path */ - BYTE attr, /* Attribute bits */ - BYTE mask /* Attribute mask to change */ -) -{ - FRESULT res; - DIR dj; - FATFS *fs; - DEF_NAMBUF - - - res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */ - dj.obj.fs = fs; - if (res == FR_OK) { - INIT_NAMBUF(fs); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ - if (res == FR_OK) { - mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask); /* Apply attribute change */ - res = store_xdir(&dj); - } else -#endif - { - dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ - fs->wflag = 1; - } - if (res == FR_OK) res = sync_fs(fs); - } - FREE_NAMBUF(); - } - - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Change Timestamp */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_utime ( - const TCHAR* path, /* Pointer to the file/directory name */ - const FILINFO* fno /* Pointer to the time stamp to be set */ -) -{ - FRESULT res; - DIR dj; - FATFS *fs; - DEF_NAMBUF - - - res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */ - dj.obj.fs = fs; - if (res == FR_OK) { - INIT_NAMBUF(fs); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ - if (res == FR_OK) { -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); - res = store_xdir(&dj); - } else -#endif - { - st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); - fs->wflag = 1; - } - if (res == FR_OK) res = sync_fs(fs); - } - FREE_NAMBUF(); - } - - LEAVE_FF(fs, res); -} - -#endif /* _USE_CHMOD && !_FS_READONLY */ - - - -#if _USE_LABEL -/*-----------------------------------------------------------------------*/ -/* Get Volume Label */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_getlabel ( - const TCHAR* path, /* Path name of the logical drive number */ - TCHAR* label, /* Pointer to a buffer to return the volume label */ - DWORD* vsn /* Pointer to a variable to return the volume serial number */ -) -{ - FRESULT res; - DIR dj; - FATFS *fs; - UINT si, di; -#if _LFN_UNICODE || _FS_EXFAT - WCHAR w; -#endif - - /* Get logical drive */ - res = find_volume(&path, &fs, 0); - - /* Get volume label */ - if (res == FR_OK && label) { - dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ - res = dir_sdi(&dj, 0); - if (res == FR_OK) { - res = dir_read(&dj, 1); /* Find a volume label entry */ - if (res == FR_OK) { -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - for (si = di = 0; si < dj.dir[XDIR_NumLabel]; si++) { /* Extract volume label from 83 entry */ - w = ld_word(dj.dir + XDIR_Label + si * 2); -#if _LFN_UNICODE - label[di++] = w; -#else - w = ff_convert(w, 0); /* Unicode -> OEM */ - if (w == 0) w = '?'; /* Replace wrong character */ - if (_DF1S && w >= 0x100) label[di++] = (char)(w >> 8); - label[di++] = (char)w; -#endif - } - label[di] = 0; - } else -#endif - { - si = di = 0; /* Extract volume label from AM_VOL entry with code comversion */ - do { -#if _LFN_UNICODE - w = (si < 11) ? dj.dir[si++] : ' '; - if (IsDBCS1(w) && si < 11 && IsDBCS2(dj.dir[si])) { - w = w << 8 | dj.dir[si++]; - } - label[di++] = ff_convert(w, 1); /* OEM -> Unicode */ -#else - label[di++] = dj.dir[si++]; -#endif - } while (di < 11); - do { /* Truncate trailing spaces */ - label[di] = 0; - if (di == 0) break; - } while (label[--di] == ' '); - } - } - } - if (res == FR_NO_FILE) { /* No label entry and return nul string */ - label[0] = 0; - res = FR_OK; - } - } - - /* Get volume serial number */ - if (res == FR_OK && vsn) { - res = move_window(fs, fs->volbase); - if (res == FR_OK) { - switch (fs->fs_type) { - case FS_EXFAT: di = BPB_VolIDEx; break; - case FS_FAT32: di = BS_VolID32; break; - default: di = BS_VolID; - } - *vsn = ld_dword(fs->win + di); - } - } - - LEAVE_FF(fs, res); -} - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Set Volume Label */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_setlabel ( - const TCHAR* label /* Pointer to the volume label to set */ -) -{ - FRESULT res; - DIR dj; - FATFS *fs; - BYTE dirvn[22]; - UINT i, j, slen; - WCHAR w; - static const char badchr[] = "\"*+,.:;<=>\?[]|\x7F"; - - - /* Get logical drive */ - res = find_volume(&label, &fs, FA_WRITE); - if (res != FR_OK) LEAVE_FF(fs, res); - dj.obj.fs = fs; - - /* Get length of given volume label */ - for (slen = 0; (UINT)label[slen] >= ' '; slen++) ; /* Get name length */ - -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ - for (i = j = 0; i < slen; ) { /* Create volume label in directory form */ - w = label[i++]; -#if !_LFN_UNICODE - if (IsDBCS1(w)) { - w = (i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0; - } - w = ff_convert(w, 1); -#endif - if (w == 0 || chk_chr(badchr, w) || j == 22) { /* Check validity check validity of the volume label */ - LEAVE_FF(fs, FR_INVALID_NAME); - } - st_word(dirvn + j, w); j += 2; - } - slen = j; - } else -#endif - { /* On the FAT12/16/32 volume */ - for ( ; slen && label[slen - 1] == ' '; slen--) ; /* Remove trailing spaces */ - if (slen) { /* Is there a volume label to be set? */ - dirvn[0] = 0; i = j = 0; /* Create volume label in directory form */ - do { -#if _LFN_UNICODE - w = ff_convert(ff_wtoupper(label[i++]), 0); -#else - w = (BYTE)label[i++]; - if (IsDBCS1(w)) { - w = (j < 10 && i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0; - } -#if _USE_LFN != 0 - w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0); -#else - if (IsLower(w)) w -= 0x20; /* To upper ASCII characters */ -#ifdef _EXCVT - if (w >= 0x80) w = ExCvt[w - 0x80]; /* To upper extended characters (SBCS cfg) */ -#else - if (!_DF1S && w >= 0x80) w = 0; /* Reject extended characters (ASCII cfg) */ -#endif -#endif -#endif - if (w == 0 || chk_chr(badchr, w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) { /* Reject invalid characters for volume label */ - LEAVE_FF(fs, FR_INVALID_NAME); - } - if (w >= 0x100) dirvn[j++] = (BYTE)(w >> 8); - dirvn[j++] = (BYTE)w; - } while (i < slen); - while (j < 11) dirvn[j++] = ' '; /* Fill remaining name field */ - if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME); /* Reject illegal name (heading DDEM) */ - } - } - - /* Set volume label */ - dj.obj.sclust = 0; /* Open root directory */ - res = dir_sdi(&dj, 0); - if (res == FR_OK) { - res = dir_read(&dj, 1); /* Get volume label entry */ - if (res == FR_OK) { - if (_FS_EXFAT && fs->fs_type == FS_EXFAT) { - dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2); /* Change the volume label */ - mem_cpy(dj.dir + XDIR_Label, dirvn, slen); - } else { - if (slen) { - mem_cpy(dj.dir, dirvn, 11); /* Change the volume label */ - } else { - dj.dir[DIR_Name] = DDEM; /* Remove the volume label */ - } - } - fs->wflag = 1; - res = sync_fs(fs); - } else { /* No volume label entry is found or error */ - if (res == FR_NO_FILE) { - res = FR_OK; - if (slen) { /* Create a volume label entry */ - res = dir_alloc(&dj, 1); /* Allocate an entry */ - if (res == FR_OK) { - mem_set(dj.dir, 0, SZDIRE); /* Clear the entry */ - if (_FS_EXFAT && fs->fs_type == FS_EXFAT) { - dj.dir[XDIR_Type] = 0x83; /* Create 83 entry */ - dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2); - mem_cpy(dj.dir + XDIR_Label, dirvn, slen); - } else { - dj.dir[DIR_Attr] = AM_VOL; /* Create volume label entry */ - mem_cpy(dj.dir, dirvn, 11); - } - fs->wflag = 1; - res = sync_fs(fs); - } - } - } - } - } - - LEAVE_FF(fs, res); -} - -#endif /* !_FS_READONLY */ -#endif /* _USE_LABEL */ - - - -#if _USE_EXPAND && !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Allocate a Contiguous Blocks to the File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_expand ( - FIL* fp, /* Pointer to the file object */ - FSIZE_t fsz, /* File size to be expanded to */ - BYTE opt /* Operation mode 0:Find and prepare or 1:Find and allocate */ -) -{ - FRESULT res; - FATFS *fs; - DWORD n, clst, stcl, scl, ncl, tcl, lclst; - - - res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); - if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); -#if _FS_EXFAT - if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED); /* Check if in size limit */ -#endif - n = (DWORD)fs->csize * SS(fs); /* Cluster size */ - tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0); /* Number of clusters required */ - stcl = fs->last_clst; lclst = 0; - if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2; - -#if _FS_EXFAT - if (fs->fs_type == FS_EXFAT) { - scl = find_bitmap(fs, stcl, tcl); /* Find a contiguous cluster block */ - if (scl == 0) res = FR_DENIED; /* No contiguous cluster block was found */ - if (scl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (res == FR_OK) { - if (opt) { - res = change_bitmap(fs, scl, tcl, 1); /* Mark the cluster block 'in use' */ - lclst = scl + tcl - 1; - } else { - lclst = scl - 1; - } - } - } else -#endif - { - scl = clst = stcl; ncl = 0; - for (;;) { /* Find a contiguous cluster block */ - n = get_fat(&fp->obj, clst); - if (++clst >= fs->n_fatent) clst = 2; - if (n == 1) { res = FR_INT_ERR; break; } - if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } - if (n == 0) { /* Is it a free cluster? */ - if (++ncl == tcl) break; /* Break if a contiguous cluster block is found */ - } else { - scl = clst; ncl = 0; /* Not a free cluster */ - } - if (clst == stcl) { res = FR_DENIED; break; } /* No contiguous cluster? */ - } - if (res == FR_OK) { - if (opt) { - for (clst = scl, n = tcl; n; clst++, n--) { /* Create a cluster chain on the FAT */ - res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1); - if (res != FR_OK) break; - lclst = clst; - } - } else { - lclst = scl - 1; - } - } - } - - if (res == FR_OK) { - fs->last_clst = lclst; /* Set suggested start cluster to start next */ - if (opt) { - fp->obj.sclust = scl; /* Update object allocation information */ - fp->obj.objsize = fsz; - if (_FS_EXFAT) fp->obj.stat = 2; /* Set status 'contiguous chain' */ - fp->flag |= FA_MODIFIED; - if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */ - fs->free_clst -= tcl; - fs->fsi_flag |= 1; - } - } - } - - LEAVE_FF(fs, res); -} - -#endif /* _USE_EXPAND && !_FS_READONLY */ - - - -#if _USE_FORWARD -/*-----------------------------------------------------------------------*/ -/* Forward data to the stream directly */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_forward ( - FIL* fp, /* Pointer to the file object */ - UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ - UINT btf, /* Number of bytes to forward */ - UINT* bf /* Pointer to number of bytes forwarded */ -) -{ - FRESULT res; - FATFS *fs; - DWORD clst, sect; - FSIZE_t remain; - UINT rcnt, csect; - BYTE *dbuf; - - - *bf = 0; /* Clear transfer byte counter */ - res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); - if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ - - remain = fp->obj.objsize - fp->fptr; - if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ - - for ( ; btf && (*func)(0, 0); /* Repeat until all data transferred or stream goes busy */ - fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { - csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ - if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ - if (csect == 0) { /* On the cluster boundary? */ - clst = (fp->fptr == 0) ? /* On the top of the file? */ - fp->obj.sclust : get_fat(&fp->obj, fp->clust); - if (clst <= 1) ABORT(fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - } - } - sect = clust2sect(fs, fp->clust); /* Get current data sector */ - if (!sect) ABORT(fs, FR_INT_ERR); - sect += csect; -#if _FS_TINY - if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window to the file data */ - dbuf = fs->win; -#else - if (fp->sect != sect) { /* Fill sector cache with file data */ -#if !_FS_READONLY - if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); - fp->flag &= (BYTE)~FA_DIRTY; - } -#endif - if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); - } - dbuf = fp->buf; -#endif - fp->sect = sect; - rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ - if (rcnt > btf) rcnt = btf; /* Clip it by btr if needed */ - rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt); /* Forward the file data */ - if (!rcnt) ABORT(fs, FR_INT_ERR); - } - - LEAVE_FF(fs, FR_OK); -} -#endif /* _USE_FORWARD */ - - - -#if _USE_MKFS && !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Create FAT file system on the logical drive */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_mkfs ( - const TCHAR* path, /* Logical drive number */ - BYTE opt, /* Format option */ - DWORD au, /* Size of allocation unit [byte] */ - void* work, /* Pointer to working buffer */ - UINT len /* Size of working buffer */ -) -{ - const UINT n_fats = 1; /* Number of FATs for FAT12/16/32 volume (1 or 2) */ - const UINT n_rootdir = 512; /* Number of root directory entries for FAT12/16 volume */ - static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0}; /* Cluster size boundary for FAT12/16 volume (4Ks unit) */ - static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0}; /* Cluster size boundary for FAT32 volume (128Ks unit) */ - BYTE fmt, sys, *buf, *pte, pdrv, part; - WORD ss; - DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n; - DWORD b_vol, b_fat, b_data; /* Base LBA for volume, fat, data */ - DWORD sz_vol, sz_rsv, sz_fat, sz_dir; /* Size for volume, fat, dir, data */ - UINT i; - int vol; - DSTATUS stat; -#if _USE_TRIM || _FS_EXFAT - DWORD tbl[3]; -#endif - - - /* Check mounted drive and clear work area */ - vol = get_ldnumber(&path); /* Get target logical drive */ - if (vol < 0) return FR_INVALID_DRIVE; - if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear mounted volume */ - pdrv = LD2PD(vol); /* Physical drive */ - part = LD2PT(vol); /* Partition (0:create as new, 1-4:get from partition table) */ - - /* Check physical drive status */ - stat = disk_initialize(pdrv); - if (stat & STA_NOINIT) return FR_NOT_READY; - if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; - if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & (sz_blk - 1))) sz_blk = 1; /* Erase block to align data area */ -#if _MAX_SS != _MIN_SS /* Get sector size of the medium */ - if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; - if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; -#else - ss = _MAX_SS; -#endif - if ((au != 0 && au < ss) || au > 0x1000000 || (au & (au - 1))) return FR_INVALID_PARAMETER; /* Check if au is valid */ - au /= ss; /* Cluster size in unit of sector */ - - /* Get working buffer */ - buf = (BYTE*)work; /* Working buffer */ - sz_buf = len / ss; /* Size of working buffer (sector) */ - szb_buf = sz_buf * ss; /* Size of working buffer (byte) */ - if (!szb_buf) return FR_MKFS_ABORTED; - - /* Determine where the volume to be located (b_vol, sz_vol) */ - if (_MULTI_PARTITION && part != 0) { - /* Get partition information from partition table in the MBR */ - if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Load MBR */ - if (ld_word(buf + BS_55AA) != 0xAA55) return FR_MKFS_ABORTED; /* Check if MBR is valid */ - pte = buf + (MBR_Table + (part - 1) * SZ_PTE); - if (!pte[PTE_System]) return FR_MKFS_ABORTED; /* No partition? */ - b_vol = ld_dword(pte + PTE_StLba); /* Get volume start sector */ - sz_vol = ld_dword(pte + PTE_SizLba); /* Get volume size */ - } else { - /* Create a single-partition in this function */ - if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) return FR_DISK_ERR; - b_vol = (opt & FM_SFD) ? 0 : 63; /* Volume start sector */ - if (sz_vol < b_vol) return FR_MKFS_ABORTED; - sz_vol -= b_vol; /* Volume size */ - } - if (sz_vol < 128) return FR_MKFS_ABORTED; /* Check if volume size is >=128s */ - - /* Pre-determine the FAT type */ - do { - if (_FS_EXFAT && (opt & FM_EXFAT)) { /* exFAT possible? */ - if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) { /* exFAT only, vol >= 64Ms or au > 128s ? */ - fmt = FS_EXFAT; break; - } - } - if (au > 128) return FR_INVALID_PARAMETER; /* Too large au for FAT/FAT32 */ - if (opt & FM_FAT32) { /* FAT32 possible? */ - if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) { /* FAT32 only or no-FAT? */ - fmt = FS_FAT32; break; - } - } - if (!(opt & FM_FAT)) return FR_INVALID_PARAMETER; /* no-FAT? */ - fmt = FS_FAT16; - } while (0); - -#if _FS_EXFAT - if (fmt == FS_EXFAT) { /* Create an exFAT volume */ - DWORD szb_bit, szb_case, sum, nb, cl; - WCHAR ch, si; - UINT j, st; - BYTE b; - - if (sz_vol < 0x1000) return FR_MKFS_ABORTED; /* Too small volume? */ -#if _USE_TRIM - tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area can be erased */ - disk_ioctl(pdrv, CTRL_TRIM, tbl); -#endif - /* Determine FAT location, data location and number of clusters */ - if (!au) { /* au auto-selection */ - au = 8; - if (sz_vol >= 0x80000) au = 64; /* >= 512Ks */ - if (sz_vol >= 0x4000000) au = 256; /* >= 64Ms */ - } - b_fat = b_vol + 32; /* FAT start at offset 32 */ - sz_fat = ((sz_vol / au + 2) * 4 + ss - 1) / ss; /* Number of FAT sectors */ - b_data = (b_fat + sz_fat + sz_blk - 1) & ~(sz_blk - 1); /* Align data area to the erase block boundary */ - if (b_data >= sz_vol / 2) return FR_MKFS_ABORTED; /* Too small volume? */ - n_clst = (sz_vol - (b_data - b_vol)) / au; /* Number of clusters */ - if (n_clst <16) return FR_MKFS_ABORTED; /* Too few clusters? */ - if (n_clst > MAX_EXFAT) return FR_MKFS_ABORTED; /* Too many clusters? */ - - szb_bit = (n_clst + 7) / 8; /* Size of allocation bitmap */ - tbl[0] = (szb_bit + au * ss - 1) / (au * ss); /* Number of allocation bitmap clusters */ - - /* Create a compressed up-case table */ - sect = b_data + au * tbl[0]; /* Table start sector */ - sum = 0; /* Table checksum to be stored in the 82 entry */ - st = si = i = j = szb_case = 0; - do { - switch (st) { - case 0: - ch = ff_wtoupper(si); /* Get an up-case char */ - if (ch != si) { - si++; break; /* Store the up-case char if exist */ - } - for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ; /* Get run length of no-case block */ - if (j >= 128) { - ch = 0xFFFF; st = 2; break; /* Compress the no-case block if run is >= 128 */ - } - st = 1; /* Do not compress short run */ - /* continue */ - case 1: - ch = si++; /* Fill the short run */ - if (--j == 0) st = 0; - break; - default: - ch = (WCHAR)j; si += j; /* Number of chars to skip */ - st = 0; - } - sum = xsum32(buf[i + 0] = (BYTE)ch, sum); /* Put it into the write buffer */ - sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum); - i += 2; szb_case += 2; - if (!si || i == szb_buf) { /* Write buffered data when buffer full or end of process */ - n = (i + ss - 1) / ss; - if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; - sect += n; i = 0; - } - } while (si); - tbl[1] = (szb_case + au * ss - 1) / (au * ss); /* Number of up-case table clusters */ - tbl[2] = 1; /* Number of root dir clusters */ - - /* Initialize the allocation bitmap */ - sect = b_data; nsect = (szb_bit + ss - 1) / ss; /* Start of bitmap and number of sectors */ - nb = tbl[0] + tbl[1] + tbl[2]; /* Number of clusters in-use by system */ - do { - mem_set(buf, 0, szb_buf); - for (i = 0; nb >= 8 && i < szb_buf; buf[i++] = 0xFF, nb -= 8) ; - for (b = 1; nb && i < szb_buf; buf[i] |= b, b <<= 1, nb--) ; - n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ - if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; - sect += n; nsect -= n; - } while (nsect); - - /* Initialize the FAT */ - sect = b_fat; nsect = sz_fat; /* Start of FAT and number of FAT sectors */ - j = nb = cl = 0; - do { - mem_set(buf, 0, szb_buf); i = 0; /* Clear work area and reset write index */ - if (cl == 0) { /* Set entry 0 and 1 */ - st_dword(buf + i, 0xFFFFFFF8); i += 4; cl++; - st_dword(buf + i, 0xFFFFFFFF); i += 4; cl++; - } - do { /* Create chains of bitmap, up-case and root dir */ - while (nb && i < szb_buf) { /* Create a chain */ - st_dword(buf + i, (nb > 1) ? cl + 1 : 0xFFFFFFFF); - i += 4; cl++; nb--; - } - if (!nb && j < 3) nb = tbl[j++]; /* Next chain */ - } while (nb && i < szb_buf); - n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ - if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; - sect += n; nsect -= n; - } while (nsect); - - /* Initialize the root directory */ - mem_set(buf, 0, szb_buf); - buf[SZDIRE * 0 + 0] = 0x83; /* 83 entry (volume label) */ - buf[SZDIRE * 1 + 0] = 0x81; /* 81 entry (allocation bitmap) */ - st_dword(buf + SZDIRE * 1 + 20, 2); - st_dword(buf + SZDIRE * 1 + 24, szb_bit); - buf[SZDIRE * 2 + 0] = 0x82; /* 82 entry (up-case table) */ - st_dword(buf + SZDIRE * 2 + 4, sum); - st_dword(buf + SZDIRE * 2 + 20, 2 + tbl[0]); - st_dword(buf + SZDIRE * 2 + 24, szb_case); - sect = b_data + au * (tbl[0] + tbl[1]); nsect = au; /* Start of the root directory and number of sectors */ - do { /* Fill root directory sectors */ - n = (nsect > sz_buf) ? sz_buf : nsect; - if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; - mem_set(buf, 0, ss); - sect += n; nsect -= n; - } while (nsect); - - /* Create two set of the exFAT VBR blocks */ - sect = b_vol; - for (n = 0; n < 2; n++) { - /* Main record (+0) */ - mem_set(buf, 0, ss); - mem_cpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11); /* Boot jump code (x86), OEM name */ - st_dword(buf + BPB_VolOfsEx, b_vol); /* Volume offset in the physical drive [sector] */ - st_dword(buf + BPB_TotSecEx, sz_vol); /* Volume size [sector] */ - st_dword(buf + BPB_FatOfsEx, b_fat - b_vol); /* FAT offset [sector] */ - st_dword(buf + BPB_FatSzEx, sz_fat); /* FAT size [sector] */ - st_dword(buf + BPB_DataOfsEx, b_data - b_vol); /* Data offset [sector] */ - st_dword(buf + BPB_NumClusEx, n_clst); /* Number of clusters */ - st_dword(buf + BPB_RootClusEx, 2 + tbl[0] + tbl[1]); /* Root dir cluster # */ - st_dword(buf + BPB_VolIDEx, GET_FATTIME()); /* VSN */ - st_word(buf + BPB_FSVerEx, 0x100); /* File system version (1.00) */ - for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ; /* Log2 of sector size [byte] */ - for (buf[BPB_SecPerClusEx] = 0, i = au; i >>= 1; buf[BPB_SecPerClusEx]++) ; /* Log2 of cluster size [sector] */ - buf[BPB_NumFATsEx] = 1; /* Number of FATs */ - buf[BPB_DrvNumEx] = 0x80; /* Drive number (for int13) */ - st_word(buf + BS_BootCodeEx, 0xFEEB); /* Boot code (x86) */ - st_word(buf + BS_55AA, 0xAA55); /* Signature (placed here regardless of sector size) */ - for (i = sum = 0; i < ss; i++) { /* VBR checksum */ - if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum); - } - if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; - /* Extended bootstrap record (+1..+8) */ - mem_set(buf, 0, ss); - st_word(buf + ss - 2, 0xAA55); /* Signature (placed at end of sector) */ - for (j = 1; j < 9; j++) { - for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ - if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; - } - /* OEM/Reserved record (+9..+10) */ - mem_set(buf, 0, ss); - for ( ; j < 11; j++) { - for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ - if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; - } - /* Sum record (+11) */ - for (i = 0; i < ss; i += 4) st_dword(buf + i, sum); /* Fill with checksum value */ - if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; - } - - } else -#endif /* _FS_EXFAT */ - { /* Create an FAT12/16/32 volume */ - do { - pau = au; - /* Pre-determine number of clusters and FAT sub-type */ - if (fmt == FS_FAT32) { /* FAT32 volume */ - if (!pau) { /* au auto-selection */ - n = sz_vol / 0x20000; /* Volume size in unit of 128KS */ - for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ; /* Get from table */ - } - n_clst = sz_vol / pau; /* Number of clusters */ - sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */ - sz_rsv = 32; /* Number of reserved sectors */ - sz_dir = 0; /* No static directory */ - if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) return FR_MKFS_ABORTED; - } else { /* FAT12/16 volume */ - if (!pau) { /* au auto-selection */ - n = sz_vol / 0x1000; /* Volume size in unit of 4KS */ - for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */ - } - n_clst = sz_vol / pau; - if (n_clst > MAX_FAT12) { - n = n_clst * 2 + 4; /* FAT size [byte] */ - } else { - fmt = FS_FAT12; - n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */ - } - sz_fat = (n + ss - 1) / ss; /* FAT size [sector] */ - sz_rsv = 1; /* Number of reserved sectors */ - sz_dir = (DWORD)n_rootdir * SZDIRE / ss; /* Rootdir size [sector] */ - } - b_fat = b_vol + sz_rsv; /* FAT base */ - b_data = b_fat + sz_fat * n_fats + sz_dir; /* Data base */ - - /* Align data base to erase block boundary (for flash memory media) */ - n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data; /* Next nearest erase block from current data base */ - if (fmt == FS_FAT32) { /* FAT32: Move FAT base */ - sz_rsv += n; b_fat += n; - } else { /* FAT12/16: Expand FAT size */ - sz_fat += n / n_fats; - } - - /* Determine number of clusters and final check of validity of the FAT sub-type */ - if (sz_vol < b_data + pau * 16 - b_vol) return FR_MKFS_ABORTED; /* Too small volume */ - n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau; - if (fmt == FS_FAT32) { - if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32 */ - if (!au && (au = pau / 2) != 0) continue; /* Adjust cluster size and retry */ - return FR_MKFS_ABORTED; - } - } - if (fmt == FS_FAT16) { - if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */ - if (!au && (pau * 2) <= 64) { - au = pau * 2; continue; /* Adjust cluster size and retry */ - } - if ((opt & FM_FAT32)) { - fmt = FS_FAT32; continue; /* Switch type to FAT32 and retry */ - } - if (!au && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ - return FR_MKFS_ABORTED; - } - if (n_clst <= MAX_FAT12) { /* Too few clusters for FAT16 */ - if (!au && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ - return FR_MKFS_ABORTED; - } - } - if (fmt == FS_FAT12 && n_clst > MAX_FAT12) return FR_MKFS_ABORTED; /* Too many clusters for FAT12 */ - - /* Ok, it is the valid cluster configuration */ - break; - } while (1); - -#if _USE_TRIM - tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area can be erased */ - disk_ioctl(pdrv, CTRL_TRIM, tbl); -#endif - /* Create FAT VBR */ - mem_set(buf, 0, ss); - mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */ - st_word(buf + BPB_BytsPerSec, ss); /* Sector size [byte] */ - buf[BPB_SecPerClus] = (BYTE)pau; /* Cluster size [sector] */ - st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv); /* Size of reserved area */ - buf[BPB_NumFATs] = (BYTE)n_fats; /* Number of FATs */ - st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir)); /* Number of root directory entries */ - if (sz_vol < 0x10000) { - st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */ - } else { - st_dword(buf + BPB_TotSec32, sz_vol); /* Volume size in 32-bit LBA */ - } - buf[BPB_Media] = 0xF8; /* Media descriptor byte */ - st_word(buf + BPB_SecPerTrk, 63); /* Number of sectors per track (for int13) */ - st_word(buf + BPB_NumHeads, 255); /* Number of heads (for int13) */ - st_dword(buf + BPB_HiddSec, b_vol); /* Volume offset in the physical drive [sector] */ - if (fmt == FS_FAT32) { - st_dword(buf + BS_VolID32, GET_FATTIME()); /* VSN */ - st_dword(buf + BPB_FATSz32, sz_fat); /* FAT size [sector] */ - st_dword(buf + BPB_RootClus32, 2); /* Root directory cluster # (2) */ - st_word(buf + BPB_FSInfo32, 1); /* Offset of FSINFO sector (VBR + 1) */ - st_word(buf + BPB_BkBootSec32, 6); /* Offset of backup VBR (VBR + 6) */ - buf[BS_DrvNum32] = 0x80; /* Drive number (for int13) */ - buf[BS_BootSig32] = 0x29; /* Extended boot signature */ - mem_cpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ - } else { - st_dword(buf + BS_VolID, GET_FATTIME()); /* VSN */ - st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */ - buf[BS_DrvNum] = 0x80; /* Drive number (for int13) */ - buf[BS_BootSig] = 0x29; /* Extended boot signature */ - mem_cpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ - } - st_word(buf + BS_55AA, 0xAA55); /* Signature (offset is fixed here regardless of sector size) */ - if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the VBR sector */ - - /* Create FSINFO record if needed */ - if (fmt == FS_FAT32) { - disk_write(pdrv, buf, b_vol + 6, 1); /* Write backup VBR (VBR + 6) */ - mem_set(buf, 0, ss); - st_dword(buf + FSI_LeadSig, 0x41615252); - st_dword(buf + FSI_StrucSig, 0x61417272); - st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */ - st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */ - st_word(buf + BS_55AA, 0xAA55); - disk_write(pdrv, buf, b_vol + 7, 1); /* Write backup FSINFO (VBR + 7) */ - disk_write(pdrv, buf, b_vol + 1, 1); /* Write original FSINFO (VBR + 1) */ - } - - /* Initialize FAT area */ - mem_set(buf, 0, (UINT)szb_buf); - sect = b_fat; /* FAT start sector */ - for (i = 0; i < n_fats; i++) { /* Initialize FATs each */ - if (fmt == FS_FAT32) { - st_dword(buf + 0, 0xFFFFFFF8); /* Entry 0 */ - st_dword(buf + 4, 0xFFFFFFFF); /* Entry 1 */ - st_dword(buf + 8, 0x0FFFFFFF); /* Entry 2 (root directory) */ - } else { - st_dword(buf + 0, (fmt == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8); /* Entry 0 and 1 */ - } - nsect = sz_fat; /* Number of FAT sectors */ - do { /* Fill FAT sectors */ - n = (nsect > sz_buf) ? sz_buf : nsect; - if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR; - mem_set(buf, 0, ss); - sect += n; nsect -= n; - } while (nsect); - } - - /* Initialize root directory (fill with zero) */ - nsect = (fmt == FS_FAT32) ? pau : sz_dir; /* Number of root directory sectors */ - do { - n = (nsect > sz_buf) ? sz_buf : nsect; - if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR; - sect += n; nsect -= n; - } while (nsect); - } - - /* Determine system ID in the partition table */ - if (_FS_EXFAT && fmt == FS_EXFAT) { - sys = 0x07; /* HPFS/NTFS/exFAT */ - } else { - if (fmt == FS_FAT32) { - sys = 0x0C; /* FAT32X */ - } else { - if (sz_vol >= 0x10000) { - sys = 0x06; /* FAT12/16 (>=64KS) */ - } else { - sys = (fmt == FS_FAT16) ? 0x04 : 0x01; /* FAT16 (<64KS) : FAT12 (<64KS) */ - } - } - } - - if (_MULTI_PARTITION && part != 0) { - /* Update system ID in the partition table */ - if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Read the MBR */ - buf[MBR_Table + (part - 1) * SZ_PTE + PTE_System] = sys; /* Set system type */ - if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Write it back to the MBR */ - } else { - if (!(opt & FM_SFD)) { - /* Create partition table in FDISK format */ - mem_set(buf, 0, ss); - st_word(buf + BS_55AA, 0xAA55); /* MBR signature */ - pte = buf + MBR_Table; /* Create partition table for single partition in the drive */ - pte[PTE_Boot] = 0; /* Boot indicator */ - pte[PTE_StHead] = 1; /* Start head */ - pte[PTE_StSec] = 1; /* Start sector */ - pte[PTE_StCyl] = 0; /* Start cylinder */ - pte[PTE_System] = sys; /* System type */ - n = (b_vol + sz_vol) / (63 * 255); /* (End CHS is incorrect) */ - pte[PTE_EdHead] = 254; /* End head */ - pte[PTE_EdSec] = (BYTE)(n >> 2 | 63); /* End sector */ - pte[PTE_EdCyl] = (BYTE)n; /* End cylinder */ - st_dword(pte + PTE_StLba, b_vol); /* Start offset in LBA */ - st_dword(pte + PTE_SizLba, sz_vol); /* Size in sectors */ - if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the MBR */ - } - } - - if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) return FR_DISK_ERR; - - return FR_OK; -} - - - -#if _MULTI_PARTITION -/*-----------------------------------------------------------------------*/ -/* Create partition table on the physical drive */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_fdisk ( - BYTE pdrv, /* Physical drive number */ - const DWORD* szt, /* Pointer to the size table for each partitions */ - void* work /* Pointer to the working buffer */ -) -{ - UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl; - BYTE s_hd, e_hd, *p, *buf = (BYTE*)work; - DSTATUS stat; - DWORD sz_disk, sz_part, s_part; - - - stat = disk_initialize(pdrv); - if (stat & STA_NOINIT) return FR_NOT_READY; - if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; - if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR; - - /* Determine the CHS without any care of the drive geometry */ - for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ; - if (n == 256) n--; - e_hd = n - 1; - sz_cyl = 63 * n; - tot_cyl = sz_disk / sz_cyl; - - /* Create partition table */ - mem_set(buf, 0, _MAX_SS); - p = buf + MBR_Table; b_cyl = 0; - for (i = 0; i < 4; i++, p += SZ_PTE) { - p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; - if (!p_cyl) continue; - s_part = (DWORD)sz_cyl * b_cyl; - sz_part = (DWORD)sz_cyl * p_cyl; - if (i == 0) { /* Exclude first track of cylinder 0 */ - s_hd = 1; - s_part += 63; sz_part -= 63; - } else { - s_hd = 0; - } - e_cyl = b_cyl + p_cyl - 1; - if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER; - - /* Set partition table */ - p[1] = s_hd; /* Start head */ - p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */ - p[3] = (BYTE)b_cyl; /* Start cylinder */ - p[4] = 0x06; /* System type (temporary setting) */ - p[5] = e_hd; /* End head */ - p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */ - p[7] = (BYTE)e_cyl; /* End cylinder */ - st_dword(p + 8, s_part); /* Start sector in LBA */ - st_dword(p + 12, sz_part); /* Partition size */ - - /* Next partition */ - b_cyl += p_cyl; - } - st_word(p, 0xAA55); - - /* Write it to the MBR */ - return (disk_write(pdrv, buf, 0, 1) != RES_OK || disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) ? FR_DISK_ERR : FR_OK; -} - -#endif /* _MULTI_PARTITION */ -#endif /* _USE_MKFS && !_FS_READONLY */ - - - - -#if _USE_STRFUNC -/*-----------------------------------------------------------------------*/ -/* Get a string from the file */ -/*-----------------------------------------------------------------------*/ - -TCHAR* f_gets ( - TCHAR* buff, /* Pointer to the string buffer to read */ - int len, /* Size of string buffer (characters) */ - FIL* fp /* Pointer to the file object */ -) -{ - int n = 0; - TCHAR c, *p = buff; - BYTE s[2]; - UINT rc; - - - while (n < len - 1) { /* Read characters until buffer gets filled */ -#if _LFN_UNICODE -#if _STRF_ENCODE == 3 /* Read a character in UTF-8 */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = s[0]; - if (c >= 0x80) { - if (c < 0xC0) continue; /* Skip stray trailer */ - if (c < 0xE0) { /* Two-byte sequence */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = (c & 0x1F) << 6 | (s[0] & 0x3F); - if (c < 0x80) c = '?'; - } else { - if (c < 0xF0) { /* Three-byte sequence */ - f_read(fp, s, 2, &rc); - if (rc != 2) break; - c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F); - if (c < 0x800) c = '?'; - } else { /* Reject four-byte sequence */ - c = '?'; - } - } - } -#elif _STRF_ENCODE == 2 /* Read a character in UTF-16BE */ - f_read(fp, s, 2, &rc); - if (rc != 2) break; - c = s[1] + (s[0] << 8); -#elif _STRF_ENCODE == 1 /* Read a character in UTF-16LE */ - f_read(fp, s, 2, &rc); - if (rc != 2) break; - c = s[0] + (s[1] << 8); -#else /* Read a character in ANSI/OEM */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = s[0]; - if (IsDBCS1(c)) { - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = (c << 8) + s[0]; - } - c = ff_convert(c, 1); /* OEM -> Unicode */ - if (!c) c = '?'; -#endif -#else /* Read a character without conversion */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = s[0]; -#endif - if (_USE_STRFUNC == 2 && c == '\r') continue; /* Strip '\r' */ - *p++ = c; - n++; - if (c == '\n') break; /* Break on EOL */ - } - *p = 0; - return n ? buff : 0; /* When no data read (eof or error), return with error. */ -} - - - - -#if !_FS_READONLY -#include -/*-----------------------------------------------------------------------*/ -/* Put a character to the file */ -/*-----------------------------------------------------------------------*/ - -typedef struct { - FIL *fp; /* Ptr to the writing file */ - int idx, nchr; /* Write index of buf[] (-1:error), number of chars written */ - BYTE buf[64]; /* Write buffer */ -} putbuff; - - -static -void putc_bfd ( /* Buffered write with code conversion */ - putbuff* pb, - TCHAR c -) -{ - UINT bw; - int i; - - - if (_USE_STRFUNC == 2 && c == '\n') { /* LF -> CRLF conversion */ - putc_bfd(pb, '\r'); - } - - i = pb->idx; /* Write index of pb->buf[] */ - if (i < 0) return; - -#if _LFN_UNICODE -#if _STRF_ENCODE == 3 /* Write a character in UTF-8 */ - if (c < 0x80) { /* 7-bit */ - pb->buf[i++] = (BYTE)c; - } else { - if (c < 0x800) { /* 11-bit */ - pb->buf[i++] = (BYTE)(0xC0 | c >> 6); - } else { /* 16-bit */ - pb->buf[i++] = (BYTE)(0xE0 | c >> 12); - pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F)); - } - pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F)); - } -#elif _STRF_ENCODE == 2 /* Write a character in UTF-16BE */ - pb->buf[i++] = (BYTE)(c >> 8); - pb->buf[i++] = (BYTE)c; -#elif _STRF_ENCODE == 1 /* Write a character in UTF-16LE */ - pb->buf[i++] = (BYTE)c; - pb->buf[i++] = (BYTE)(c >> 8); -#else /* Write a character in ANSI/OEM */ - c = ff_convert(c, 0); /* Unicode -> OEM */ - if (!c) c = '?'; - if (c >= 0x100) - pb->buf[i++] = (BYTE)(c >> 8); - pb->buf[i++] = (BYTE)c; -#endif -#else /* Write a character without conversion */ - pb->buf[i++] = (BYTE)c; -#endif - - if (i >= (int)(sizeof pb->buf) - 3) { /* Write buffered characters to the file */ - f_write(pb->fp, pb->buf, (UINT)i, &bw); - i = (bw == (UINT)i) ? 0 : -1; - } - pb->idx = i; - pb->nchr++; -} - - -static -int putc_flush ( /* Flush left characters in the buffer */ - putbuff* pb -) -{ - UINT nw; - - if ( pb->idx >= 0 /* Flush buffered characters to the file */ - && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK - && (UINT)pb->idx == nw) return pb->nchr; - return EOF; -} - - -static -void putc_init ( /* Initialize write buffer */ - putbuff* pb, - FIL* fp -) -{ - pb->fp = fp; - pb->nchr = pb->idx = 0; -} - - - -int f_putc ( - TCHAR c, /* A character to be output */ - FIL* fp /* Pointer to the file object */ -) -{ - putbuff pb; - - - putc_init(&pb, fp); - putc_bfd(&pb, c); /* Put the character */ - return putc_flush(&pb); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Put a string to the file */ -/*-----------------------------------------------------------------------*/ - -int f_puts ( - const TCHAR* str, /* Pointer to the string to be output */ - FIL* fp /* Pointer to the file object */ -) -{ - putbuff pb; - - - putc_init(&pb, fp); - while (*str) putc_bfd(&pb, *str++); /* Put the string */ - return putc_flush(&pb); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Put a formatted string to the file */ -/*-----------------------------------------------------------------------*/ - -int f_printf ( - FIL* fp, /* Pointer to the file object */ - const TCHAR* fmt, /* Pointer to the format string */ - ... /* Optional arguments... */ -) -{ - va_list arp; - putbuff pb; - BYTE f, r; - UINT i, j, w; - DWORD v; - TCHAR c, d, str[32], *p; - - - putc_init(&pb, fp); - - va_start(arp, fmt); - - for (;;) { - c = *fmt++; - if (c == 0) break; /* End of string */ - if (c != '%') { /* Non escape character */ - putc_bfd(&pb, c); - continue; - } - w = f = 0; - c = *fmt++; - if (c == '0') { /* Flag: '0' padding */ - f = 1; c = *fmt++; - } else { - if (c == '-') { /* Flag: left justified */ - f = 2; c = *fmt++; - } - } - while (IsDigit(c)) { /* Precision */ - w = w * 10 + c - '0'; - c = *fmt++; - } - if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ - f |= 4; c = *fmt++; - } - if (!c) break; - d = c; - if (IsLower(d)) d -= 0x20; - switch (d) { /* Type is... */ - case 'S' : /* String */ - p = va_arg(arp, TCHAR*); - for (j = 0; p[j]; j++) ; - if (!(f & 2)) { - while (j++ < w) putc_bfd(&pb, ' '); - } - while (*p) putc_bfd(&pb, *p++); - while (j++ < w) putc_bfd(&pb, ' '); - continue; - case 'C' : /* Character */ - putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue; - case 'B' : /* Binary */ - r = 2; break; - case 'O' : /* Octal */ - r = 8; break; - case 'D' : /* Signed decimal */ - case 'U' : /* Unsigned decimal */ - r = 10; break; - case 'X' : /* Hexdecimal */ - r = 16; break; - default: /* Unknown type (pass-through) */ - putc_bfd(&pb, c); continue; - } - - /* Get an argument and put it in numeral */ - v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int)); - if (d == 'D' && (v & 0x80000000)) { - v = 0 - v; - f |= 8; - } - i = 0; - do { - d = (TCHAR)(v % r); v /= r; - if (d > 9) d += (c == 'x') ? 0x27 : 0x07; - str[i++] = d + '0'; - } while (v && i < sizeof str / sizeof str[0]); - if (f & 8) str[i++] = '-'; - j = i; d = (f & 1) ? '0' : ' '; - while (!(f & 2) && j++ < w) putc_bfd(&pb, d); - do putc_bfd(&pb, str[--i]); while (i); - while (j++ < w) putc_bfd(&pb, d); - } - - va_end(arp); - - return putc_flush(&pb); -} - -#endif /* !_FS_READONLY */ -#endif /* _USE_STRFUNC */ +/*----------------------------------------------------------------------------/ +/ FatFs - Generic FAT file system module R0.12b / +/-----------------------------------------------------------------------------/ +/ +/ Copyright (C) 2016, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: + +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +/----------------------------------------------------------------------------*/ + + +#include "ff.h" /* Declarations of FatFs API */ +#include "diskio.h" /* Declarations of device I/O functions */ + + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ + +#if _FATFS != 68020 /* Revision ID */ +#error Wrong include file (ff.h). +#endif + + +#define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); } + + +/* Reentrancy related */ +#if _FS_REENTRANT +#if _USE_LFN == 1 +#error Static LFN work area cannot be used at thread-safe configuration +#endif +#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } +#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } +#else +#define ENTER_FF(fs) +#define LEAVE_FF(fs, res) return res +#endif + + + +/* Definitions of sector size */ +#if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096) || (_MIN_SS != 512 && _MIN_SS != 1024 && _MIN_SS != 2048 && _MIN_SS != 4096) +#error Wrong sector size configuration +#endif +#if _MAX_SS == _MIN_SS +#define SS(fs) ((UINT)_MAX_SS) /* Fixed sector size */ +#else +#define SS(fs) ((fs)->ssize) /* Variable sector size */ +#endif + + +/* Timestamp */ +#if _FS_NORTC == 1 +#if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < 1 || _NORTC_MDAY > 31 +#error Invalid _FS_NORTC settings +#endif +#define GET_FATTIME() ((DWORD)(_NORTC_YEAR - 1980) << 25 | (DWORD)_NORTC_MON << 21 | (DWORD)_NORTC_MDAY << 16) +#else +#define GET_FATTIME() get_fattime() +#endif + + +/* File lock controls */ +#if _FS_LOCK != 0 +#if _FS_READONLY +#error _FS_LOCK must be 0 at read-only configuration +#endif +typedef struct { + FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */ + DWORD clu; /* Object ID 2, directory (0:root) */ + DWORD ofs; /* Object ID 3, directory offset */ + WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ +} FILESEM; +#endif + + + +/* DBCS code ranges and SBCS upper conversion tables */ + +#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ +#define _DF1S 0x81 /* DBC 1st byte range 1 start */ +#define _DF1E 0x9F /* DBC 1st byte range 1 end */ +#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ +#define _DF2E 0xFC /* DBC 1st byte range 2 end */ +#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ +#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ +#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ +#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ + +#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0x80 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 949 /* Korean */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x41 +#define _DS1E 0x5A +#define _DS2S 0x61 +#define _DS2E 0x7A +#define _DS3S 0x81 +#define _DS3E 0xFE + +#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0xA1 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 437 /* U.S. */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 720 /* Arabic */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 737 /* Greek */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 771 /* KBL */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF} + +#elif _CODE_PAGE == 775 /* Baltic */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 850 /* Latin 1 */ +#define _DF1S 0 +#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \ + 0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \ + 0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 852 /* Latin 2 */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} + +#elif _CODE_PAGE == 855 /* Cyrillic */ +#define _DF1S 0 +#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \ + 0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \ + 0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 857 /* Turkish */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 860 /* Portuguese */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \ + 0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 861 /* Icelandic */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 862 /* Hebrew */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 863 /* Canadian-French */ +#define _DF1S 0 +#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \ + 0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \ + 0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 864 /* Arabic */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 865 /* Nordic */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 866 /* Russian */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 869 /* Greek 2 */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \ + 0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \ + 0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \ + 0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF} + +#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ +#if _USE_LFN != 0 +#error Cannot enable LFN without valid code page. +#endif +#define _DF1S 0 + +#else +#error Unknown code page + +#endif + + +/* Character code support macros */ +#define IsUpper(c) (((c)>='A')&&((c)<='Z')) +#define IsLower(c) (((c)>='a')&&((c)<='z')) +#define IsDigit(c) (((c)>='0')&&((c)<='9')) + +#if _DF1S != 0 /* Code page is DBCS */ + +#ifdef _DF2S /* Two 1st byte areas */ +#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) +#else /* One 1st byte area */ +#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) +#endif + +#ifdef _DS3S /* Three 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) +#else /* Two 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) +#endif + +#else /* Code page is SBCS */ + +#define IsDBCS1(c) 0 +#define IsDBCS2(c) 0 + +#endif /* _DF1S */ + + +/* File attribute bits (internal use) */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_MASK 0x3F /* Mask of defined bits */ + + +/* File access control and file status flags (internal use) */ +#define FA_SEEKEND 0x20 /* Seek to end of the file on file open */ +#define FA_MODIFIED 0x40 /* File has been modified */ +#define FA_DIRTY 0x80 /* FIL.buf[] needs to be written-back */ + + +/* Name status flags */ +#define NSFLAG 11 /* Index of name status byte in fn[] */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ +#define NS_NOLFN 0x40 /* Do not find LFN */ +#define NS_NONAME 0x80 /* Not followed */ + + +/* Limits and boundaries (differ from specs but correct for real DOS/Windows) */ +#define MAX_FAT12 0xFF5 /* Maximum number of FAT12 clusters */ +#define MAX_FAT16 0xFFF5 /* Maximum number of FAT16 clusters */ +#define MAX_FAT32 0xFFFFFF5 /* Maximum number of FAT32 clusters */ +#define MAX_EXFAT 0x7FFFFFFD /* Maximum number of exFAT clusters (limited by implementation) */ +#define MAX_DIR 0x200000 /* Maximum size of FAT directory */ +#define MAX_DIR_EX 0x10000000 /* Maximum size of exFAT directory */ + + +/* FatFs refers the members in the FAT structures as byte array instead of +/ structure members because the structure is not binary compatible between +/ different platforms */ + +#define BS_JmpBoot 0 /* x86 jump instruction (3-byte) */ +#define BS_OEMName 3 /* OEM name (8-byte) */ +#define BPB_BytsPerSec 11 /* Sector size [byte] (WORD) */ +#define BPB_SecPerClus 13 /* Cluster size [sector] (BYTE) */ +#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (WORD) */ +#define BPB_NumFATs 16 /* Number of FATs (BYTE) */ +#define BPB_RootEntCnt 17 /* Size of root directory area for FAT12/16 [entry] (WORD) */ +#define BPB_TotSec16 19 /* Volume size (16-bit) [sector] (WORD) */ +#define BPB_Media 21 /* Media descriptor byte (BYTE) */ +#define BPB_FATSz16 22 /* FAT size (16-bit) [sector] (WORD) */ +#define BPB_SecPerTrk 24 /* Track size for int13h [sector] (WORD) */ +#define BPB_NumHeads 26 /* Number of heads for int13h (WORD) */ +#define BPB_HiddSec 28 /* Volume offset from top of the drive (DWORD) */ +#define BPB_TotSec32 32 /* Volume size (32-bit) [sector] (DWORD) */ +#define BS_DrvNum 36 /* Physical drive number for int13h (BYTE) */ +#define BS_NTres 37 /* Error flag (BYTE) */ +#define BS_BootSig 38 /* Extended boot signature (BYTE) */ +#define BS_VolID 39 /* Volume serial number (DWORD) */ +#define BS_VolLab 43 /* Volume label string (8-byte) */ +#define BS_FilSysType 54 /* File system type string (8-byte) */ +#define BS_BootCode 62 /* Boot code (448-byte) */ +#define BS_55AA 510 /* Signature word (WORD) */ + +#define BPB_FATSz32 36 /* FAT32: FAT size [sector] (DWORD) */ +#define BPB_ExtFlags32 40 /* FAT32: Extended flags (WORD) */ +#define BPB_FSVer32 42 /* FAT32: File system version (WORD) */ +#define BPB_RootClus32 44 /* FAT32: Root directory cluster (DWORD) */ +#define BPB_FSInfo32 48 /* FAT32: Offset of FSINFO sector (WORD) */ +#define BPB_BkBootSec32 50 /* FAT32: Offset of backup boot sector (WORD) */ +#define BS_DrvNum32 64 /* FAT32: Physical drive number for int13h (BYTE) */ +#define BS_NTres32 65 /* FAT32: Error flag (BYTE) */ +#define BS_BootSig32 66 /* FAT32: Extended boot signature (BYTE) */ +#define BS_VolID32 67 /* FAT32: Volume serial number (DWORD) */ +#define BS_VolLab32 71 /* FAT32: Volume label string (8-byte) */ +#define BS_FilSysType32 82 /* FAT32: File system type string (8-byte) */ +#define BS_BootCode32 90 /* FAT32: Boot code (420-byte) */ + +#define BPB_ZeroedEx 11 /* exFAT: MBZ field (53-byte) */ +#define BPB_VolOfsEx 64 /* exFAT: Volume offset from top of the drive [sector] (QWORD) */ +#define BPB_TotSecEx 72 /* exFAT: Volume size [sector] (QWORD) */ +#define BPB_FatOfsEx 80 /* exFAT: FAT offset from top of the volume [sector] (DWORD) */ +#define BPB_FatSzEx 84 /* exFAT: FAT size [sector] (DWORD) */ +#define BPB_DataOfsEx 88 /* exFAT: Data offset from top of the volume [sector] (DWORD) */ +#define BPB_NumClusEx 92 /* exFAT: Number of clusters (DWORD) */ +#define BPB_RootClusEx 96 /* exFAT: Root directory cluster (DWORD) */ +#define BPB_VolIDEx 100 /* exFAT: Volume serial number (DWORD) */ +#define BPB_FSVerEx 104 /* exFAT: File system version (WORD) */ +#define BPB_VolFlagEx 106 /* exFAT: Volume flags (BYTE) */ +#define BPB_ActFatEx 107 /* exFAT: Active FAT flags (BYTE) */ +#define BPB_BytsPerSecEx 108 /* exFAT: Log2 of sector size in byte (BYTE) */ +#define BPB_SecPerClusEx 109 /* exFAT: Log2 of cluster size in sector (BYTE) */ +#define BPB_NumFATsEx 110 /* exFAT: Number of FATs (BYTE) */ +#define BPB_DrvNumEx 111 /* exFAT: Physical drive number for int13h (BYTE) */ +#define BPB_PercInUseEx 112 /* exFAT: Percent in use (BYTE) */ +#define BPB_RsvdEx 113 /* exFAT: Reserved (7-byte) */ +#define BS_BootCodeEx 120 /* exFAT: Boot code (390-byte) */ + +#define FSI_LeadSig 0 /* FAT32 FSI: Leading signature (DWORD) */ +#define FSI_StrucSig 484 /* FAT32 FSI: Structure signature (DWORD) */ +#define FSI_Free_Count 488 /* FAT32 FSI: Number of free clusters (DWORD) */ +#define FSI_Nxt_Free 492 /* FAT32 FSI: Last allocated cluster (DWORD) */ + +#define MBR_Table 446 /* MBR: Offset of partition table in the MBR */ +#define SZ_PTE 16 /* MBR: Size of a partition table entry */ +#define PTE_Boot 0 /* MBR PTE: Boot indicator */ +#define PTE_StHead 1 /* MBR PTE: Start head */ +#define PTE_StSec 2 /* MBR PTE: Start sector */ +#define PTE_StCyl 3 /* MBR PTE: Start cylinder */ +#define PTE_System 4 /* MBR PTE: System ID */ +#define PTE_EdHead 5 /* MBR PTE: End head */ +#define PTE_EdSec 6 /* MBR PTE: End sector */ +#define PTE_EdCyl 7 /* MBR PTE: End cylinder */ +#define PTE_StLba 8 /* MBR PTE: Start in LBA */ +#define PTE_SizLba 12 /* MBR PTE: Size in LBA */ + +#define DIR_Name 0 /* Short file name (11-byte) */ +#define DIR_Attr 11 /* Attribute (BYTE) */ +#define DIR_NTres 12 /* Lower case flag (BYTE) */ +#define DIR_CrtTime10 13 /* Created time sub-second (BYTE) */ +#define DIR_CrtTime 14 /* Created time (DWORD) */ +#define DIR_LstAccDate 18 /* Last accessed date (WORD) */ +#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (WORD) */ +#define DIR_ModTime 22 /* Modified time (DWORD) */ +#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (WORD) */ +#define DIR_FileSize 28 /* File size (DWORD) */ +#define LDIR_Ord 0 /* LFN entry order and LLE flag (BYTE) */ +#define LDIR_Attr 11 /* LFN attribute (BYTE) */ +#define LDIR_Type 12 /* LFN type (BYTE) */ +#define LDIR_Chksum 13 /* Checksum of the SFN entry (BYTE) */ +#define LDIR_FstClusLO 26 /* Must be zero (WORD) */ +#define XDIR_Type 0 /* Type of exFAT directory entry (BYTE) */ +#define XDIR_NumLabel 1 /* Number of volume label characters (BYTE) */ +#define XDIR_Label 2 /* Volume label (11-WORD) */ +#define XDIR_CaseSum 4 /* Sum of case conversion table (DWORD) */ +#define XDIR_NumSec 1 /* Number of secondary entries (BYTE) */ +#define XDIR_SetSum 2 /* Sum of the set of directory entries (WORD) */ +#define XDIR_Attr 4 /* File attribute (WORD) */ +#define XDIR_CrtTime 8 /* Created time (DWORD) */ +#define XDIR_ModTime 12 /* Modified time (DWORD) */ +#define XDIR_AccTime 16 /* Last accessed time (DWORD) */ +#define XDIR_CrtTime10 20 /* Created time subsecond (BYTE) */ +#define XDIR_ModTime10 21 /* Modified time subsecond (BYTE) */ +#define XDIR_CrtTZ 22 /* Created timezone (BYTE) */ +#define XDIR_ModTZ 23 /* Modified timezone (BYTE) */ +#define XDIR_AccTZ 24 /* Last accessed timezone (BYTE) */ +#define XDIR_GenFlags 33 /* Gneral secondary flags (WORD) */ +#define XDIR_NumName 35 /* Number of file name characters (BYTE) */ +#define XDIR_NameHash 36 /* Hash of file name (WORD) */ +#define XDIR_ValidFileSize 40 /* Valid file size (QWORD) */ +#define XDIR_FstClus 52 /* First cluster of the file data (DWORD) */ +#define XDIR_FileSize 56 /* File/Directory size (QWORD) */ + +#define SZDIRE 32 /* Size of a directory entry */ +#define LLEF 0x40 /* Last long entry flag in LDIR_Ord */ +#define DDEM 0xE5 /* Deleted directory entry mark set to DIR_Name[0] */ +#define RDDEM 0x05 /* Replacement of the character collides with DDEM */ + + + + + +/*-------------------------------------------------------------------------- + + Module Private Work Area + +---------------------------------------------------------------------------*/ + +/* Remark: Variables here without initial value shall be guaranteed zero/null +/ at start-up. If not, either the linker or start-up routine being used is +/ not compliance with C standard. */ + +#if _VOLUMES < 1 || _VOLUMES > 9 +#error Wrong _VOLUMES setting +#endif +static FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ +static WORD Fsid; /* File system mount ID */ + +#if _FS_RPATH != 0 && _VOLUMES >= 2 +static BYTE CurrVol; /* Current drive */ +#endif + +#if _FS_LOCK != 0 +static FILESEM Files[_FS_LOCK]; /* Open object lock semaphores */ +#endif + +#if _USE_LFN == 0 /* Non-LFN configuration */ +#define DEF_NAMBUF +#define INIT_NAMBUF(fs) +#define FREE_NAMBUF() +#else +#if _MAX_LFN < 12 || _MAX_LFN > 255 +#error Wrong _MAX_LFN setting +#endif + +#if _USE_LFN == 1 /* LFN enabled with static working buffer */ +#if _FS_EXFAT +static BYTE DirBuf[SZDIRE*19]; /* Directory entry block scratchpad buffer (19 entries in size) */ +#endif +static WCHAR LfnBuf[_MAX_LFN+1]; /* LFN enabled with static working buffer */ +#define DEF_NAMBUF +#define INIT_NAMBUF(fs) +#define FREE_NAMBUF() + +#elif _USE_LFN == 2 /* LFN enabled with dynamic working buffer on the stack */ +#if _FS_EXFAT +#define DEF_NAMBUF WCHAR lbuf[_MAX_LFN+1]; BYTE dbuf[SZDIRE*19]; +#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; } +#define FREE_NAMBUF() +#else +#define DEF_NAMBUF WCHAR lbuf[_MAX_LFN+1]; +#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; } +#define FREE_NAMBUF() +#endif + +#elif _USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */ +#if _FS_EXFAT +#define DEF_NAMBUF WCHAR *lfn; +#define INIT_NAMBUF(fs) { lfn = ff_memalloc((_MAX_LFN+1)*2 + SZDIRE*19); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+_MAX_LFN+1); } +#define FREE_NAMBUF() ff_memfree(lfn) +#else +#define DEF_NAMBUF WCHAR *lfn; +#define INIT_NAMBUF(fs) { lfn = ff_memalloc((_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; } +#define FREE_NAMBUF() ff_memfree(lfn) +#endif + +#else +#error Wrong _USE_LFN setting +#endif +#endif + +#ifdef _EXCVT +static const BYTE ExCvt[] = _EXCVT; /* Upper conversion table for SBCS extended characters */ +#endif + + + + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* Load/Store multi-byte word in the FAT structure */ +/*-----------------------------------------------------------------------*/ + +static +WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */ +{ + WORD rv; + + rv = ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} + +static +DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */ +{ + DWORD rv; + + rv = ptr[3]; + rv = rv << 8 | ptr[2]; + rv = rv << 8 | ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} + +#if _FS_EXFAT +static +QWORD ld_qword (const BYTE* ptr) /* Load an 8-byte little-endian word */ +{ + QWORD rv; + + rv = ptr[7]; + rv = rv << 8 | ptr[6]; + rv = rv << 8 | ptr[5]; + rv = rv << 8 | ptr[4]; + rv = rv << 8 | ptr[3]; + rv = rv << 8 | ptr[2]; + rv = rv << 8 | ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} +#endif + +#if !_FS_READONLY +static +void st_word (BYTE* ptr, WORD val) /* Store a 2-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} + +static +void st_dword (BYTE* ptr, DWORD val) /* Store a 4-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} + +#if _FS_EXFAT +static +void st_qword (BYTE* ptr, QWORD val) /* Store an 8-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} +#endif +#endif /* !_FS_READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* String functions */ +/*-----------------------------------------------------------------------*/ + +/* Copy memory to memory */ +static +void mem_cpy (void* dst, const void* src, UINT cnt) { + BYTE *d = (BYTE*)dst; + const BYTE *s = (const BYTE*)src; + + if (cnt) { + do *d++ = *s++; while (--cnt); + } +} + +/* Fill memory block */ +static +void mem_set (void* dst, int val, UINT cnt) { + BYTE *d = (BYTE*)dst; + + do *d++ = (BYTE)val; while (--cnt); +} + +/* Compare memory block */ +static +int mem_cmp (const void* dst, const void* src, UINT cnt) { /* ZR:same, NZ:different */ + const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; + int r = 0; + + do { + r = *d++ - *s++; + } while (--cnt && r == 0); + + return r; +} + +/* Check if chr is contained in the string */ +static +int chk_chr (const char* str, int chr) { /* NZ:contained, ZR:not contained */ + while (*str && *str != chr) str++; + return *str; +} + + + + +#if _FS_REENTRANT +/*-----------------------------------------------------------------------*/ +/* Request/Release grant to access the volume */ +/*-----------------------------------------------------------------------*/ +static +int lock_fs ( + FATFS* fs /* File system object */ +) +{ + return ff_req_grant(fs->sobj); +} + + +static +void unlock_fs ( + FATFS* fs, /* File system object */ + FRESULT res /* Result code to be returned */ +) +{ + if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) { + ff_rel_grant(fs->sobj); + } +} + +#endif + + + +#if _FS_LOCK != 0 +/*-----------------------------------------------------------------------*/ +/* File lock control functions */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT chk_lock ( /* Check if the file can be accessed */ + DIR* dp, /* Directory object pointing the file to be checked */ + int acc /* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i, be; + + /* Search file semaphore table */ + for (i = be = 0; i < _FS_LOCK; i++) { + if (Files[i].fs) { /* Existing entry */ + if (Files[i].fs == dp->obj.fs && /* Check if the object matched with an open object */ + Files[i].clu == dp->obj.sclust && + Files[i].ofs == dp->dptr) break; + } else { /* Blank entry */ + be = 1; + } + } + if (i == _FS_LOCK) { /* The object is not opened */ + return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new object? */ + } + + /* The object has been opened. Reject any open against writing file and all write mode open */ + return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; +} + + +static +int enq_lock (void) /* Check if an entry is available for a new object */ +{ + UINT i; + + for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + return (i == _FS_LOCK) ? 0 : 1; +} + + +static +UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */ + DIR* dp, /* Directory object pointing the file to register or increment */ + int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i; + + + for (i = 0; i < _FS_LOCK; i++) { /* Find the object */ + if (Files[i].fs == dp->obj.fs && + Files[i].clu == dp->obj.sclust && + Files[i].ofs == dp->dptr) break; + } + + if (i == _FS_LOCK) { /* Not opened. Register it as new. */ + for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + if (i == _FS_LOCK) return 0; /* No free entry to register (int err) */ + Files[i].fs = dp->obj.fs; + Files[i].clu = dp->obj.sclust; + Files[i].ofs = dp->dptr; + Files[i].ctr = 0; + } + + if (acc && Files[i].ctr) return 0; /* Access violation (int err) */ + + Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ + + return i + 1; +} + + +static +FRESULT dec_lock ( /* Decrement object open counter */ + UINT i /* Semaphore index (1..) */ +) +{ + WORD n; + FRESULT res; + + + if (--i < _FS_LOCK) { /* Shift index number origin from 0 */ + n = Files[i].ctr; + if (n == 0x100) n = 0; /* If write mode open, delete the entry */ + if (n > 0) n--; /* Decrement read mode open count */ + Files[i].ctr = n; + if (n == 0) Files[i].fs = 0; /* Delete the entry if open count gets zero */ + res = FR_OK; + } else { + res = FR_INT_ERR; /* Invalid index nunber */ + } + return res; +} + + +static +void clear_lock ( /* Clear lock entries of the volume */ + FATFS *fs +) +{ + UINT i; + + for (i = 0; i < _FS_LOCK; i++) { + if (Files[i].fs == fs) Files[i].fs = 0; + } +} + +#endif /* _FS_LOCK != 0 */ + + + +/*-----------------------------------------------------------------------*/ +/* Move/Flush disk access window in the file system object */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERROR */ + FATFS* fs /* File system object */ +) +{ + DWORD wsect; + UINT nf; + FRESULT res = FR_OK; + + + if (fs->wflag) { /* Write back the sector if it is dirty */ + wsect = fs->winsect; /* Current sector number */ + if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) { + res = FR_DISK_ERR; + } else { + fs->wflag = 0; + if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */ + for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ + wsect += fs->fsize; + disk_write(fs->drv, fs->win, wsect, 1); + } + } + } + } + return res; +} +#endif + + +static +FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERROR */ + FATFS* fs, /* File system object */ + DWORD sector /* Sector number to make appearance in the fs->win[] */ +) +{ + FRESULT res = FR_OK; + + + if (sector != fs->winsect) { /* Window offset changed? */ +#if !_FS_READONLY + res = sync_window(fs); /* Write-back changes */ +#endif + if (res == FR_OK) { /* Fill sector window with new data */ + if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) { + sector = 0xFFFFFFFF; /* Invalidate window if data is not reliable */ + res = FR_DISK_ERR; + } + fs->winsect = sector; + } + } + return res; +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Synchronize file system and strage device */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT sync_fs ( /* FR_OK:succeeded, !=0:error */ + FATFS* fs /* File system object */ +) +{ + FRESULT res; + + + res = sync_window(fs); + if (res == FR_OK) { + /* Update FSInfo sector if needed */ + if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { + /* Create FSInfo structure */ + mem_set(fs->win, 0, SS(fs)); + st_word(fs->win + BS_55AA, 0xAA55); + st_dword(fs->win + FSI_LeadSig, 0x41615252); + st_dword(fs->win + FSI_StrucSig, 0x61417272); + st_dword(fs->win + FSI_Free_Count, fs->free_clst); + st_dword(fs->win + FSI_Nxt_Free, fs->last_clst); + /* Write it into the FSInfo sector */ + fs->winsect = fs->volbase + 1; + disk_write(fs->drv, fs->win, fs->winsect, 1); + fs->fsi_flag = 0; + } + /* Make sure that no pending write process in the physical drive */ + if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR; + } + + return res; +} + +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Get sector# from cluster# */ +/*-----------------------------------------------------------------------*/ + +static +DWORD clust2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */ + FATFS* fs, /* File system object */ + DWORD clst /* Cluster# to be converted */ +) +{ + clst -= 2; + if (clst >= fs->n_fatent - 2) return 0; /* Invalid cluster# */ + return clst * fs->csize + fs->database; +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Read value of a FAT entry */ +/*-----------------------------------------------------------------------*/ + +static +DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */ + _FDID* obj, /* Corresponding object */ + DWORD clst /* Cluster number to get the value */ +) +{ + UINT wc, bc; + DWORD val; + FATFS *fs = obj->fs; + + + if (clst < 2 || clst >= fs->n_fatent) { /* Check if in valid range */ + val = 1; /* Internal error */ + + } else { + val = 0xFFFFFFFF; /* Default value falls on disk error */ + + switch (fs->fs_type) { + case FS_FAT12 : + bc = (UINT)clst; bc += bc / 2; + if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + wc = fs->win[bc++ % SS(fs)]; + if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + wc |= fs->win[bc % SS(fs)] << 8; + val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); + break; + + case FS_FAT16 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break; + val = ld_word(fs->win + clst * 2 % SS(fs)); + break; + + case FS_FAT32 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; + val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; + break; +#if _FS_EXFAT + case FS_EXFAT : + if (obj->objsize) { + DWORD cofs = clst - obj->sclust; /* Offset from start cluster */ + DWORD clen = (DWORD)((obj->objsize - 1) / SS(fs)) / fs->csize; /* Number of clusters - 1 */ + + if (obj->stat == 2) { /* Is there no valid chain on the FAT? */ + if (cofs <= clen) { + val = (cofs == clen) ? 0x7FFFFFFF : clst + 1; /* Generate the value */ + break; + } + } + if (obj->stat == 3 && cofs < obj->n_cont) { /* Is it in the contiguous part? */ + val = clst + 1; /* Generate the value */ + break; + } + if (obj->stat != 2) { /* Get value from FAT if FAT chain is valid */ + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; + val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF; + break; + } + } + /* go next */ +#endif + default: + val = 1; /* Internal error */ + } + } + + return val; +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT access - Change value of a FAT entry */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */ + FATFS* fs, /* Corresponding file system object */ + DWORD clst, /* FAT index number (cluster number) to be changed */ + DWORD val /* New value to be set to the entry */ +) +{ + UINT bc; + BYTE *p; + FRESULT res = FR_INT_ERR; + + + if (clst >= 2 && clst < fs->n_fatent) { /* Check if in valid range */ + switch (fs->fs_type) { + case FS_FAT12 : /* Bitfield items */ + bc = (UINT)clst; bc += bc / 2; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = fs->win + bc++ % SS(fs); + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + fs->wflag = 1; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = fs->win + bc % SS(fs); + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + fs->wflag = 1; + break; + + case FS_FAT16 : /* WORD aligned items */ + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); + if (res != FR_OK) break; + st_word(fs->win + clst * 2 % SS(fs), (WORD)val); + fs->wflag = 1; + break; + + case FS_FAT32 : /* DWORD aligned items */ +#if _FS_EXFAT + case FS_EXFAT : +#endif + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); + if (res != FR_OK) break; + if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { + val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000); + } + st_dword(fs->win + clst * 4 % SS(fs), val); + fs->wflag = 1; + break; + } + } + return res; +} + +#endif /* !_FS_READONLY */ + + + + +#if _FS_EXFAT && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* exFAT: Accessing FAT and Allocation Bitmap */ +/*-----------------------------------------------------------------------*/ + +/*---------------------------------------------*/ +/* exFAT: Find a contiguous free cluster block */ +/*---------------------------------------------*/ + +static +DWORD find_bitmap ( /* 0:No free cluster, 2..:Free cluster found, 0xFFFFFFFF:Disk error */ + FATFS* fs, /* File system object */ + DWORD clst, /* Cluster number to scan from */ + DWORD ncl /* Number of contiguous clusters to find (1..) */ +) +{ + BYTE bm, bv; + UINT i; + DWORD val, scl, ctr; + + + clst -= 2; /* The first bit in the bitmap corresponds to cluster #2 */ + if (clst >= fs->n_fatent - 2) clst = 0; + scl = val = clst; ctr = 0; + for (;;) { + if (move_window(fs, fs->database + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF; /* (assuming bitmap is located top of the cluster heap) */ + i = val / 8 % SS(fs); bm = 1 << (val % 8); + do { + do { + bv = fs->win[i] & bm; bm <<= 1; /* Get bit value */ + if (++val >= fs->n_fatent - 2) { /* Next cluster (with wrap-around) */ + val = 0; bm = 0; i = 4096; + } + if (!bv) { /* Is it a free cluster? */ + if (++ctr == ncl) return scl + 2; /* Check run length */ + } else { + scl = val; ctr = 0; /* Encountered a live cluster, restart to scan */ + } + if (val == clst) return 0; /* All cluster scanned? */ + } while (bm); + bm = 1; + } while (++i < SS(fs)); + } +} + + +/*------------------------------------*/ +/* exFAT: Set/Clear a block of bitmap */ +/*------------------------------------*/ + +static +FRESULT change_bitmap ( + FATFS* fs, /* File system object */ + DWORD clst, /* Cluster number to change from */ + DWORD ncl, /* Number of clusters to be changed */ + int bv /* bit value to be set (0 or 1) */ +) +{ + BYTE bm; + UINT i; + DWORD sect; + + + clst -= 2; /* The first bit corresponds to cluster #2 */ + sect = fs->database + clst / 8 / SS(fs); /* Sector address (assuming bitmap is located top of the cluster heap) */ + i = clst / 8 % SS(fs); /* Byte offset in the sector */ + bm = 1 << (clst % 8); /* Bit mask in the byte */ + for (;;) { + if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR; + do { + do { + if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR; /* Is the bit expected value? */ + fs->win[i] ^= bm; /* Flip the bit */ + fs->wflag = 1; + if (--ncl == 0) return FR_OK; /* All bits processed? */ + } while (bm <<= 1); /* Next bit */ + bm = 1; + } while (++i < SS(fs)); /* Next byte */ + i = 0; + } +} + + +/*---------------------------------------------*/ +/* Complement contiguous part of the FAT chain */ +/*---------------------------------------------*/ + +static +FRESULT fill_fat_chain ( + _FDID* obj /* Pointer to the corresponding object */ +) +{ + FRESULT res; + DWORD cl, n; + + if (obj->stat == 3) { /* Has the object been changed 'fragmented'? */ + for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) { /* Create cluster chain on the FAT */ + res = put_fat(obj->fs, cl, cl + 1); + if (res != FR_OK) return res; + } + obj->stat = 0; /* Change status 'FAT chain is valid' */ + } + return FR_OK; +} + +#endif /* _FS_EXFAT && !_FS_READONLY */ + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT handling - Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ +static +FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ + _FDID* obj, /* Corresponding object */ + DWORD clst, /* Cluster to remove a chain from */ + DWORD pclst /* Previous cluster of clst (0:an entire chain) */ +) +{ + FRESULT res = FR_OK; + DWORD nxt; + FATFS *fs = obj->fs; +#if _FS_EXFAT || _USE_TRIM + DWORD scl = clst, ecl = clst; +#endif +#if _USE_TRIM + DWORD rt[2]; +#endif + + if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Check if in valid range */ + + /* Mark the previous cluster 'EOC' on the FAT if it exists */ + if (pclst && (!_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) { + res = put_fat(fs, pclst, 0xFFFFFFFF); + if (res != FR_OK) return res; + } + + /* Remove the chain */ + do { + nxt = get_fat(obj, clst); /* Get cluster status */ + if (nxt == 0) break; /* Empty cluster? */ + if (nxt == 1) return FR_INT_ERR; /* Internal error? */ + if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ + if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { + res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */ + if (res != FR_OK) return res; + } + if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */ + fs->free_clst++; + fs->fsi_flag |= 1; + } +#if _FS_EXFAT || _USE_TRIM + if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ + ecl = nxt; + } else { /* End of contiguous cluster block */ +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + res = change_bitmap(fs, scl, ecl - scl + 1, 0); /* Mark the cluster block 'free' on the bitmap */ + if (res != FR_OK) return res; + } +#endif +#if _USE_TRIM + rt[0] = clust2sect(fs, scl); /* Start sector */ + rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ + disk_ioctl(fs->drv, CTRL_TRIM, rt); /* Inform device the block can be erased */ +#endif + scl = ecl = nxt; + } +#endif + clst = nxt; /* Next cluster */ + } while (clst < fs->n_fatent); /* Repeat while not the last link */ + +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + if (pclst == 0) { /* Does object have no chain? */ + obj->stat = 0; /* Change the object status 'initial' */ + } else { + if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) { /* Did the chain got contiguous? */ + obj->stat = 2; /* Change the object status 'contiguous' */ + } + } + } +#endif + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Stretch a chain or Create a new chain */ +/*-----------------------------------------------------------------------*/ +static +DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + _FDID* obj, /* Corresponding object */ + DWORD clst /* Cluster# to stretch, 0:Create a new chain */ +) +{ + DWORD cs, ncl, scl; + FRESULT res; + FATFS *fs = obj->fs; + + + if (clst == 0) { /* Create a new chain */ + scl = fs->last_clst; /* Get suggested cluster to start from */ + if (scl == 0 || scl >= fs->n_fatent) scl = 1; + } + else { /* Stretch current chain */ + cs = get_fat(obj, clst); /* Check the cluster status */ + if (cs < 2) return 1; /* Invalid value */ + if (cs == 0xFFFFFFFF) return cs; /* A disk error occurred */ + if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + scl = clst; + } + +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + ncl = find_bitmap(fs, scl, 1); /* Find a free cluster */ + if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl; /* No free cluster or hard error? */ + res = change_bitmap(fs, ncl, 1, 1); /* Mark the cluster 'in use' */ + if (res == FR_INT_ERR) return 1; + if (res == FR_DISK_ERR) return 0xFFFFFFFF; + if (clst == 0) { /* Is it a new chain? */ + obj->stat = 2; /* Set status 'contiguous chain' */ + } else { /* This is a stretched chain */ + if (obj->stat == 2 && ncl != scl + 1) { /* Is the chain got fragmented? */ + obj->n_cont = scl - obj->sclust; /* Set size of the contiguous part */ + obj->stat = 3; /* Change status 'just fragmented' */ + } + } + } else +#endif + { /* On the FAT12/16/32 volume */ + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= fs->n_fatent) { /* Check wrap-around */ + ncl = 2; + if (ncl > scl) return 0; /* No free cluster */ + } + cs = get_fat(obj, ncl); /* Get the cluster status */ + if (cs == 0) break; /* Found a free cluster */ + if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* An error occurred */ + if (ncl == scl) return 0; /* No free cluster */ + } + } + + if (_FS_EXFAT && fs->fs_type == FS_EXFAT && obj->stat == 2) { /* Is it a contiguous chain? */ + res = FR_OK; /* FAT does not need to be written */ + } else { + res = put_fat(fs, ncl, 0xFFFFFFFF); /* Mark the new cluster 'EOC' */ + if (res == FR_OK && clst) { + res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ + } + } + + if (res == FR_OK) { /* Update FSINFO if function succeeded. */ + fs->last_clst = ncl; + if (fs->free_clst < fs->n_fatent - 2) fs->free_clst--; + fs->fsi_flag |= 1; + } else { + ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; /* Failed. Create error status */ + } + + return ncl; /* Return new cluster number or error status */ +} + +#endif /* !_FS_READONLY */ + + + + +#if _USE_FASTSEEK +/*-----------------------------------------------------------------------*/ +/* FAT handling - Convert offset into cluster with link map table */ +/*-----------------------------------------------------------------------*/ + +static +DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ + FIL* fp, /* Pointer to the file object */ + FSIZE_t ofs /* File offset to be converted to cluster# */ +) +{ + DWORD cl, ncl, *tbl; + FATFS *fs = fp->obj.fs; + + + tbl = fp->cltbl + 1; /* Top of CLMT */ + cl = (DWORD)(ofs / SS(fs) / fs->csize); /* Cluster order from top of the file */ + for (;;) { + ncl = *tbl++; /* Number of cluters in the fragment */ + if (ncl == 0) return 0; /* End of table? (error) */ + if (cl < ncl) break; /* In this fragment? */ + cl -= ncl; tbl++; /* Next fragment */ + } + return cl + *tbl; /* Return the cluster number */ +} + +#endif /* _USE_FASTSEEK */ + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Set directory index */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp, /* Pointer to directory object */ + DWORD ofs /* Offset of directory table */ +) +{ + DWORD csz, clst; + FATFS *fs = dp->obj.fs; + + + if (ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) { /* Check range of offset and alignment */ + return FR_INT_ERR; + } + dp->dptr = ofs; /* Set current offset */ + clst = dp->obj.sclust; /* Table start cluster (0:root) */ + if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */ + clst = fs->dirbase; + if (_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */ + } + + if (clst == 0) { /* Static table (root-directory in FAT12/16) */ + if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */ + dp->sect = fs->dirbase; + + } else { /* Dynamic table (sub-directory or root-directory in FAT32+) */ + csz = (DWORD)fs->csize * SS(fs); /* Bytes per cluster */ + while (ofs >= csz) { /* Follow cluster chain */ + clst = get_fat(&dp->obj, clst); /* Get next cluster */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal error */ + ofs -= csz; + } + dp->sect = clust2sect(fs, clst); + } + dp->clust = clst; /* Current cluster# */ + if (!dp->sect) return FR_INT_ERR; + dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ + dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Move directory table index next */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ + DIR* dp, /* Pointer to the directory object */ + int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ +) +{ + DWORD ofs, clst; + FATFS *fs = dp->obj.fs; +#if !_FS_READONLY + UINT n; +#endif + + ofs = dp->dptr + SZDIRE; /* Next entry */ + if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) return FR_NO_FILE; /* Report EOT when offset has reached max value */ + + if (ofs % SS(fs) == 0) { /* Sector changed? */ + dp->sect++; /* Next sector */ + + if (!dp->clust) { /* Static table */ + if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */ + dp->sect = 0; return FR_NO_FILE; + } + } + else { /* Dynamic table */ + if ((ofs / SS(fs) & (fs->csize - 1)) == 0) { /* Cluster changed? */ + clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ + if (clst <= 1) return FR_INT_ERR; /* Internal error */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst >= fs->n_fatent) { /* Reached end of dynamic table */ +#if !_FS_READONLY + if (!stretch) { /* If no stretch, report EOT */ + dp->sect = 0; return FR_NO_FILE; + } + clst = create_chain(&dp->obj, dp->clust); /* Allocate a cluster */ + if (clst == 0) return FR_DENIED; /* No free cluster */ + if (clst == 1) return FR_INT_ERR; /* Internal error */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + /* Clean-up the stretched table */ + if (_FS_EXFAT) dp->obj.stat |= 4; /* The directory needs to be updated */ + if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */ + mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */ + for (n = 0, fs->winsect = clust2sect(fs, clst); n < fs->csize; n++, fs->winsect++) { /* Fill the new cluster with 0 */ + fs->wflag = 1; + if (sync_window(fs) != FR_OK) return FR_DISK_ERR; + } + fs->winsect -= n; /* Restore window offset */ +#else + if (!stretch) dp->sect = 0; /* If no stretch, report EOT (this is to suppress warning) */ + dp->sect = 0; return FR_NO_FILE; /* Report EOT */ +#endif + } + dp->clust = clst; /* Initialize data for new cluster */ + dp->sect = clust2sect(fs, clst); + } + } + } + dp->dptr = ofs; /* Current entry */ + dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */ + + return FR_OK; +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Directory handling - Reserve a block of directory entries */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp, /* Pointer to the directory object */ + UINT nent /* Number of contiguous entries to allocate */ +) +{ + FRESULT res; + UINT n; + FATFS *fs = dp->obj.fs; + + + res = dir_sdi(dp, 0); + if (res == FR_OK) { + n = 0; + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; +#if _FS_EXFAT + if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) { +#else + if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) { +#endif + if (++n == nent) break; /* A block of contiguous free entries is found */ + } else { + n = 0; /* Not a blank entry. Restart to search */ + } + res = dir_next(dp, 1); + } while (res == FR_OK); /* Next entry with table stretch enabled */ + } + + if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ + return res; +} + +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT: Directory handling - Load/Store start cluster number */ +/*-----------------------------------------------------------------------*/ + +static +DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */ + FATFS* fs, /* Pointer to the fs object */ + const BYTE* dir /* Pointer to the key entry */ +) +{ + DWORD cl; + + cl = ld_word(dir + DIR_FstClusLO); + if (fs->fs_type == FS_FAT32) { + cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16; + } + + return cl; +} + + +#if !_FS_READONLY +static +void st_clust ( + FATFS* fs, /* Pointer to the fs object */ + BYTE* dir, /* Pointer to the key entry */ + DWORD cl /* Value to be set */ +) +{ + st_word(dir + DIR_FstClusLO, (WORD)cl); + if (fs->fs_type == FS_FAT32) { + st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16)); + } +} +#endif + + + +#if _USE_LFN != 0 +/*------------------------------------------------------------------------*/ +/* FAT-LFN: LFN handling */ +/*------------------------------------------------------------------------*/ +static +const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN characters in the directory entry */ + + +/*--------------------------------------------------------*/ +/* FAT-LFN: Compare a part of file name with an LFN entry */ +/*--------------------------------------------------------*/ +static +int cmp_lfn ( /* 1:matched, 0:not matched */ + const WCHAR* lfnbuf, /* Pointer to the LFN working buffer to be compared */ + BYTE* dir /* Pointer to the directory entry containing the part of LFN */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */ + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ + uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ + if (wc) { + if (i >= _MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) { /* Compare it */ + return 0; /* Not matched */ + } + wc = uc; + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } + + if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0; /* Last segment matched but different length */ + + return 1; /* The part of LFN matched */ +} + + +#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT +/*-----------------------------------------------------*/ +/* FAT-LFN: Pick a part of file name from an LFN entry */ +/*-----------------------------------------------------*/ +static +int pick_lfn ( /* 1:succeeded, 0:buffer overflow or invalid LFN entry */ + WCHAR* lfnbuf, /* Pointer to the LFN working buffer */ + BYTE* dir /* Pointer to the LFN entry */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */ + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ + uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ + if (wc) { + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i++] = wc = uc; /* Store it */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } + + if (dir[LDIR_Ord] & LLEF) { /* Put terminator if it is the last LFN part */ + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i] = 0; + } + + return 1; /* The part of LFN is valid */ +} +#endif + + +#if !_FS_READONLY +/*-----------------------------------------*/ +/* FAT-LFN: Create an entry of LFN entries */ +/*-----------------------------------------*/ +static +void put_lfn ( + const WCHAR* lfn, /* Pointer to the LFN */ + BYTE* dir, /* Pointer to the LFN entry to be created */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* Checksum of the corresponding SFN */ +) +{ + UINT i, s; + WCHAR wc; + + + dir[LDIR_Chksum] = sum; /* Set checksum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + st_word(dir + LDIR_FstClusLO, 0); + + i = (ord - 1) * 13; /* Get offset in the LFN working buffer */ + s = wc = 0; + do { + if (wc != 0xFFFF) wc = lfn[i++]; /* Get an effective character */ + st_word(dir + LfnOfs[s], wc); /* Put it */ + if (wc == 0) wc = 0xFFFF; /* Padding characters for left locations */ + } while (++s < 13); + if (wc == 0xFFFF || !lfn[i]) ord |= LLEF; /* Last LFN part is the start of LFN sequence */ + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_LFN != 0 */ + + + +#if _USE_LFN != 0 && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT-LFN: Create a Numbered SFN */ +/*-----------------------------------------------------------------------*/ + +static +void gen_numname ( + BYTE* dst, /* Pointer to the buffer to store numbered SFN */ + const BYTE* src, /* Pointer to SFN */ + const WCHAR* lfn, /* Pointer to LFN */ + UINT seq /* Sequence number */ +) +{ + BYTE ns[8], c; + UINT i, j; + WCHAR wc; + DWORD sr; + + + mem_cpy(dst, src, 11); + + if (seq > 5) { /* In case of many collisions, generate a hash number instead of sequential number */ + sr = seq; + while (*lfn) { /* Create a CRC */ + wc = *lfn++; + for (i = 0; i < 16; i++) { + sr = (sr << 1) + (wc & 1); + wc >>= 1; + if (sr & 0x10000) sr ^= 0x11021; + } + } + seq = (UINT)sr; + } + + /* itoa (hexdecimal) */ + i = 7; + do { + c = (BYTE)((seq % 16) + '0'); + if (c > '9') c += 7; + ns[i--] = c; + seq /= 16; + } while (seq); + ns[i] = '~'; + + /* Append the number */ + for (j = 0; j < i && dst[j] != ' '; j++) { + if (IsDBCS1(dst[j])) { + if (j == i - 1) break; + j++; + } + } + do { + dst[j++] = (i < 8) ? ns[i++] : ' '; + } while (j < 8); +} +#endif /* _USE_LFN != 0 && !_FS_READONLY */ + + + +#if _USE_LFN != 0 +/*-----------------------------------------------------------------------*/ +/* FAT-LFN: Calculate checksum of an SFN entry */ +/*-----------------------------------------------------------------------*/ + +static +BYTE sum_sfn ( + const BYTE* dir /* Pointer to the SFN entry */ +) +{ + BYTE sum = 0; + UINT n = 11; + + do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); + return sum; +} + +#endif /* _USE_LFN != 0 */ + + + +#if _FS_EXFAT +/*-----------------------------------------------------------------------*/ +/* exFAT: Checksum */ +/*-----------------------------------------------------------------------*/ + +static +WORD xdir_sum ( /* Get checksum of the directoly block */ + const BYTE* dir /* Directory entry block to be calculated */ +) +{ + UINT i, szblk; + WORD sum; + + + szblk = (dir[XDIR_NumSec] + 1) * SZDIRE; + for (i = sum = 0; i < szblk; i++) { + if (i == XDIR_SetSum) { /* Skip sum field */ + i++; + } else { + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i]; + } + } + return sum; +} + + + +static +WORD xname_sum ( /* Get check sum (to be used as hash) of the name */ + const WCHAR* name /* File name to be calculated */ +) +{ + WCHAR chr; + WORD sum = 0; + + + while ((chr = *name++) != 0) { + chr = ff_wtoupper(chr); /* File name needs to be ignored case */ + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF); + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8); + } + return sum; +} + + +#if !_FS_READONLY && _USE_MKFS +static +DWORD xsum32 ( + BYTE dat, /* Data to be sumed */ + DWORD sum /* Previous value */ +) +{ + sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat; + return sum; +} +#endif + + +#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 +/*------------------------------------------------------*/ +/* exFAT: Get object information from a directory block */ +/*------------------------------------------------------*/ + +static +void get_xdir_info ( + BYTE* dirb, /* Pointer to the direcotry entry block 85+C0+C1s */ + FILINFO* fno /* Buffer to store the extracted file information */ +) +{ + UINT di, si; + WCHAR w; +#if !_LFN_UNICODE + UINT nc; +#endif + + /* Get file name */ +#if _LFN_UNICODE + if (dirb[XDIR_NumName] <= _MAX_LFN) { + for (si = SZDIRE * 2, di = 0; di < dirb[XDIR_NumName]; si += 2, di++) { + if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */ + w = ld_word(dirb + si); /* Get a character */ + fno->fname[di] = w; /* Store it */ + } + } else { + di = 0; /* Buffer overflow and inaccessible object */ + } +#else + for (si = SZDIRE * 2, di = nc = 0; nc < dirb[XDIR_NumName]; si += 2, nc++) { + if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */ + w = ld_word(dirb + si); /* Get a character */ + w = ff_convert(w, 0); /* Unicode -> OEM */ + if (w == 0) { di = 0; break; } /* Could not be converted and inaccessible object */ + if (_DF1S && w >= 0x100) { /* Put 1st byte if it is a DBC (always false at SBCS cfg) */ + fno->fname[di++] = (char)(w >> 8); + } + if (di >= _MAX_LFN) { di = 0; break; } /* Buffer overflow and inaccessible object */ + fno->fname[di++] = (char)w; + } +#endif + if (di == 0) fno->fname[di++] = '?'; /* Inaccessible object? */ + fno->fname[di] = 0; /* Terminate file name */ + + fno->altname[0] = 0; /* No SFN */ + fno->fattrib = dirb[XDIR_Attr]; /* Attribute */ + fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(dirb + XDIR_FileSize); /* Size */ + fno->ftime = ld_word(dirb + XDIR_ModTime + 0); /* Time */ + fno->fdate = ld_word(dirb + XDIR_ModTime + 2); /* Date */ +} + +#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */ + + +/*-----------------------------------*/ +/* exFAT: Get a directry entry block */ +/*-----------------------------------*/ + +static +FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */ + DIR* dp /* Pointer to the reading direcotry object pointing the 85 entry */ +) +{ + FRESULT res; + UINT i, nent; + BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the on-memory direcotry entry block 85+C0+C1s */ + + + /* Load 85 entry */ + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != 0x85) return FR_INT_ERR; + mem_cpy(dirb, dp->dir, SZDIRE); + nent = dirb[XDIR_NumSec] + 1; + + /* Load C0 entry */ + res = dir_next(dp, 0); + if (res != FR_OK) return res; + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != 0xC0) return FR_INT_ERR; + mem_cpy(dirb + SZDIRE, dp->dir, SZDIRE); + + /* Load C1 entries */ + if (nent < 3 || nent > 19) return FR_NO_FILE; + i = SZDIRE * 2; nent *= SZDIRE; + do { + res = dir_next(dp, 0); + if (res != FR_OK) return res; + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != 0xC1) return FR_INT_ERR; + mem_cpy(dirb + i, dp->dir, SZDIRE); + i += SZDIRE; + } while (i < nent); + + /* Sanity check */ + if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR; + + return FR_OK; +} + + +#if !_FS_READONLY || _FS_RPATH != 0 +/*------------------------------------------------*/ +/* exFAT: Load the object's directory entry block */ +/*------------------------------------------------*/ +static +FRESULT load_obj_dir ( + DIR* dp, /* Blank directory object to be used to access containing direcotry */ + const _FDID* obj /* Object with containing directory information */ +) +{ + FRESULT res; + + + /* Open object containing directory */ + dp->obj.fs = obj->fs; + dp->obj.sclust = obj->c_scl; + dp->obj.stat = (BYTE)obj->c_size; + dp->obj.objsize = obj->c_size & 0xFFFFFF00; + dp->blk_ofs = obj->c_ofs; + + res = dir_sdi(dp, dp->blk_ofs); /* Goto the block location */ + if (res == FR_OK) { + res = load_xdir(dp); /* Load the object's entry block */ + } + return res; +} +#endif + + +#if !_FS_READONLY +/*-----------------------------------------------*/ +/* exFAT: Store the directory block to the media */ +/*-----------------------------------------------*/ +static +FRESULT store_xdir ( + DIR* dp /* Pointer to the direcotry object */ +) +{ + FRESULT res; + UINT nent; + BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the direcotry entry block 85+C0+C1s */ + + /* Create set sum */ + st_word(dirb + XDIR_SetSum, xdir_sum(dirb)); + nent = dirb[XDIR_NumSec] + 1; + + /* Store the set of directory to the volume */ + res = dir_sdi(dp, dp->blk_ofs); + while (res == FR_OK) { + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) break; + mem_cpy(dp->dir, dirb, SZDIRE); + dp->obj.fs->wflag = 1; + if (--nent == 0) break; + dirb += SZDIRE; + res = dir_next(dp, 0); + } + return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR; +} + + + +/*-------------------------------------------*/ +/* exFAT: Create a new directory enrty block */ +/*-------------------------------------------*/ + +static +void create_xdir ( + BYTE* dirb, /* Pointer to the direcotry entry block buffer */ + const WCHAR* lfn /* Pointer to the nul terminated file name */ +) +{ + UINT i; + BYTE nb, nc; + WCHAR chr; + + + mem_set(dirb, 0, 2 * SZDIRE); /* Initialize 85+C0 entry */ + dirb[XDIR_Type] = 0x85; + dirb[XDIR_Type + SZDIRE] = 0xC0; + st_word(dirb + XDIR_NameHash, xname_sum(lfn)); /* Set name hash */ + + i = SZDIRE * 2; /* C1 offset */ + nc = 0; nb = 1; chr = 1; + do { + dirb[i++] = 0xC1; dirb[i++] = 0; /* Entry type C1 */ + do { /* Fill name field */ + if (chr && (chr = lfn[nc]) != 0) nc++; /* Get a character if exist */ + st_word(dirb + i, chr); i += 2; /* Store it */ + } while (i % SZDIRE); + nb++; + } while (lfn[nc]); /* Fill next entry if any char follows */ + + dirb[XDIR_NumName] = nc; /* Set name length */ + dirb[XDIR_NumSec] = nb; /* Set number of C0+C1s */ +} + +#endif /* !_FS_READONLY */ +#endif /* _FS_EXFAT */ + + + +#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT +/*-----------------------------------------------------------------------*/ +/* Read an object from the directory */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_read ( + DIR* dp, /* Pointer to the directory object */ + int vol /* Filtered by 0:file/directory or 1:volume label */ +) +{ + FRESULT res = FR_NO_FILE; + FATFS *fs = dp->obj.fs; + BYTE a, c; +#if _USE_LFN != 0 + BYTE ord = 0xFF, sum = 0xFF; +#endif + + while (dp->sect) { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + c = dp->dir[DIR_Name]; /* Test for the entry type */ + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of the directory */ +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + if (_USE_LABEL && vol) { + if (c == 0x83) break; /* Volume label entry? */ + } else { + if (c == 0x85) { /* Start of the file entry block? */ + dp->blk_ofs = dp->dptr; /* Get location of the block */ + res = load_xdir(dp); /* Load the entry block */ + if (res == FR_OK) { + dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK; /* Get attribute */ + } + break; + } + } + } else +#endif + { /* On the FAT12/16/32 volume */ + dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; /* Get attribute */ +#if _USE_LFN != 0 /* LFN configuration */ + if (c == DDEM || c == '.' || (int)((a & ~AM_ARC) == AM_VOL) != vol) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (c & LLEF) { /* Is it start of an LFN sequence? */ + sum = dp->dir[LDIR_Chksum]; + c &= (BYTE)~LLEF; ord = c; + dp->blk_ofs = dp->dptr; + } + /* Check LFN validity and capture it */ + ord = (c == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; + } else { /* An SFN entry is found */ + if (ord || sum != sum_sfn(dp->dir)) { /* Is there a valid LFN? */ + dp->blk_ofs = 0xFFFFFFFF; /* It has no LFN. */ + } + break; + } + } +#else /* Non LFN configuration */ + if (c != DDEM && c != '.' && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol) { /* Is it a valid entry? */ + break; + } +#endif + } + res = dir_next(dp, 0); /* Next entry */ + if (res != FR_OK) break; + } + + if (res != FR_OK) dp->sect = 0; /* Terminate the read operation on error or EOT */ + return res; +} + +#endif /* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */ + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Find an object in the directory */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp /* Pointer to the directory object with the file name */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; + BYTE c; +#if _USE_LFN != 0 + BYTE a, ord, sum; +#endif + + res = dir_sdi(dp, 0); /* Rewind directory object */ + if (res != FR_OK) return res; +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + BYTE nc; + UINT di, ni; + WORD hash = xname_sum(fs->lfnbuf); /* Hash value of the name to find */ + + while ((res = dir_read(dp, 0)) == FR_OK) { /* Read an item */ + if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue; /* Skip the comparison if hash value mismatched */ + for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) { /* Compare the name */ + if ((di % SZDIRE) == 0) di += 2; + if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break; + } + if (nc == 0 && !fs->lfnbuf[ni]) break; /* Name matched? */ + } + return res; + } +#endif + /* On the FAT12/16/32 volume */ +#if _USE_LFN != 0 + ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ +#endif + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + c = dp->dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN != 0 /* LFN configuration */ + dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; + if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (!(dp->fn[NSFLAG] & NS_NOLFN)) { + if (c & LLEF) { /* Is it start of LFN sequence? */ + sum = dp->dir[LDIR_Chksum]; + c &= (BYTE)~LLEF; ord = c; /* LFN start order */ + dp->blk_ofs = dp->dptr; /* Start offset of LFN */ + } + /* Check validity of the LFN entry and compare it with given name */ + ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; + } + } else { /* An SFN entry is found */ + if (!ord && sum == sum_sfn(dp->dir)) break; /* LFN matched? */ + if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */ + ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ + } + } +#else /* Non LFN configuration */ + dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK; + if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry? */ +#endif + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + + return res; +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Register an object to the directory */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */ + DIR* dp /* Target directory with object name to be created */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; +#if _USE_LFN != 0 /* LFN configuration */ + UINT n, nlen, nent; + BYTE sn[12], sum; + + + if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME; /* Check name validity */ + for (nlen = 0; fs->lfnbuf[nlen]; nlen++) ; /* Get lfn length */ + +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + DIR dj; + + nent = (nlen + 14) / 15 + 2; /* Number of entries to allocate (85+C0+C1s) */ + res = dir_alloc(dp, nent); /* Allocate entries */ + if (res != FR_OK) return res; + dp->blk_ofs = dp->dptr - SZDIRE * (nent - 1); /* Set block position */ + + if (dp->obj.sclust != 0 && (dp->obj.stat & 4)) { /* Has the sub-directory been stretched? */ + dp->obj.stat &= 3; + dp->obj.objsize += (DWORD)fs->csize * SS(fs); /* Increase object size by cluster size */ + res = fill_fat_chain(&dp->obj); /* Complement FAT chain if needed */ + if (res != FR_OK) return res; + res = load_obj_dir(&dj, &dp->obj); + if (res != FR_OK) return res; /* Load the object status */ + st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize); /* Update the allocation status */ + st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize); + fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1; + res = store_xdir(&dj); /* Store the object status */ + if (res != FR_OK) return res; + } + + create_xdir(fs->dirbuf, fs->lfnbuf); /* Create on-memory directory block to be written later */ + return FR_OK; + } +#endif + /* On the FAT12/16/32 volume */ + mem_cpy(sn, dp->fn, 12); + if (sn[NSFLAG] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ + dp->fn[NSFLAG] = NS_NOLFN; /* Find only SFN */ + for (n = 1; n < 100; n++) { + gen_numname(dp->fn, sn, fs->lfnbuf, n); /* Generate a numbered name */ + res = dir_find(dp); /* Check if the name collides with existing SFN */ + if (res != FR_OK) break; + } + if (n == 100) return FR_DENIED; /* Abort if too many collisions */ + if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ + dp->fn[NSFLAG] = sn[NSFLAG]; + } + + /* Create an SFN with/without LFNs. */ + nent = (sn[NSFLAG] & NS_LFN) ? (nlen + 12) / 13 + 1 : 1; /* Number of entries to allocate */ + res = dir_alloc(dp, nent); /* Allocate entries */ + if (res == FR_OK && --nent) { /* Set LFN entry if needed */ + res = dir_sdi(dp, dp->dptr - nent * SZDIRE); + if (res == FR_OK) { + sum = sum_sfn(dp->fn); /* Checksum value of the SFN tied to the LFN */ + do { /* Store LFN entries in bottom first */ + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + put_lfn(fs->lfnbuf, dp->dir, (BYTE)nent, sum); + fs->wflag = 1; + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK && --nent); + } + } + +#else /* Non LFN configuration */ + res = dir_alloc(dp, 1); /* Allocate an entry for SFN */ + +#endif + + /* Set SFN entry */ + if (res == FR_OK) { + res = move_window(fs, dp->sect); + if (res == FR_OK) { + mem_set(dp->dir, 0, SZDIRE); /* Clean the entry */ + mem_cpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */ +#if _USE_LFN != 0 + dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT); /* Put NT flag */ +#endif + fs->wflag = 1; + } + } + + return res; +} + +#endif /* !_FS_READONLY */ + + + +#if !_FS_READONLY && _FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Remove an object from the directory */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */ + DIR* dp /* Directory object pointing the entry to be removed */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; +#if _USE_LFN != 0 /* LFN configuration */ + DWORD last = dp->dptr; + + res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs); /* Goto top of the entry block if LFN is exist */ + if (res == FR_OK) { + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + /* Mark an entry 'deleted' */ + if (_FS_EXFAT && fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + dp->dir[XDIR_Type] &= 0x7F; + } else { /* On the FAT12/16/32 volume */ + dp->dir[DIR_Name] = DDEM; + } + fs->wflag = 1; + if (dp->dptr >= last) break; /* If reached last entry then all entries of the object has been deleted. */ + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR; + } +#else /* Non LFN configuration */ + + res = move_window(fs, dp->sect); + if (res == FR_OK) { + dp->dir[DIR_Name] = DDEM; + fs->wflag = 1; + } +#endif + + return res; +} + +#endif /* !_FS_READONLY && _FS_MINIMIZE == 0 */ + + + +#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 +/*-----------------------------------------------------------------------*/ +/* Get file information from directory entry */ +/*-----------------------------------------------------------------------*/ + +static +void get_fileinfo ( /* No return code */ + DIR* dp, /* Pointer to the directory object */ + FILINFO* fno /* Pointer to the file information to be filled */ +) +{ + UINT i, j; + TCHAR c; + DWORD tm; +#if _USE_LFN != 0 + WCHAR w, lfv; + FATFS *fs = dp->obj.fs; +#endif + + + fno->fname[0] = 0; /* Invaidate file info */ + if (!dp->sect) return; /* Exit if read pointer has reached end of directory */ + +#if _USE_LFN != 0 /* LFN configuration */ +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + get_xdir_info(fs->dirbuf, fno); + return; + } else +#endif + { /* On the FAT12/16/32 volume */ + if (dp->blk_ofs != 0xFFFFFFFF) { /* Get LFN if available */ + i = j = 0; + while ((w = fs->lfnbuf[j++]) != 0) { /* Get an LFN character */ +#if !_LFN_UNICODE + w = ff_convert(w, 0); /* Unicode -> OEM */ + if (w == 0) { i = 0; break; } /* No LFN if it could not be converted */ + if (_DF1S && w >= 0x100) { /* Put 1st byte if it is a DBC (always false at SBCS cfg) */ + fno->fname[i++] = (char)(w >> 8); + } +#endif + if (i >= _MAX_LFN) { i = 0; break; } /* No LFN if buffer overflow */ + fno->fname[i++] = (TCHAR)w; + } + fno->fname[i] = 0; /* Terminate the LFN */ + } + } + + i = j = 0; + lfv = fno->fname[i]; /* LFN is exist if non-zero */ + while (i < 11) { /* Copy name body and extension */ + c = (TCHAR)dp->dir[i++]; + if (c == ' ') continue; /* Skip padding spaces */ + if (c == RDDEM) c = (TCHAR)DDEM; /* Restore replaced DDEM character */ + if (i == 9) { /* Insert a . if extension is exist */ + if (!lfv) fno->fname[j] = '.'; + fno->altname[j++] = '.'; + } +#if _LFN_UNICODE + if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dp->dir[i])) { + c = c << 8 | dp->dir[i++]; + } + c = ff_convert(c, 1); /* OEM -> Unicode */ + if (!c) c = '?'; +#endif + fno->altname[j] = c; + if (!lfv) { + if (IsUpper(c) && (dp->dir[DIR_NTres] & (i >= 9 ? NS_EXT : NS_BODY))) { + c += 0x20; /* To lower */ + } + fno->fname[j] = c; + } + j++; + } + if (!lfv) { + fno->fname[j] = 0; + if (!dp->dir[DIR_NTres]) j = 0; /* Altname is no longer needed if neither LFN nor case info is exist. */ + } + fno->altname[j] = 0; /* Terminate the SFN */ + +#else /* Non-LFN configuration */ + i = j = 0; + while (i < 11) { /* Copy name body and extension */ + c = (TCHAR)dp->dir[i++]; + if (c == ' ') continue; /* Skip padding spaces */ + if (c == RDDEM) c = (TCHAR)DDEM; /* Restore replaced DDEM character */ + if (i == 9) fno->fname[j++] = '.'; /* Insert a . if extension is exist */ + fno->fname[j++] = c; + } + fno->fname[j] = 0; +#endif + + fno->fattrib = dp->dir[DIR_Attr]; /* Attribute */ + fno->fsize = ld_dword(dp->dir + DIR_FileSize); /* Size */ + tm = ld_dword(dp->dir + DIR_ModTime); /* Timestamp */ + fno->ftime = (WORD)tm; fno->fdate = (WORD)(tm >> 16); +} + +#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */ + + + +#if _USE_FIND && _FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Pattern matching */ +/*-----------------------------------------------------------------------*/ + +static +WCHAR get_achar ( /* Get a character and advances ptr 1 or 2 */ + const TCHAR** ptr /* Pointer to pointer to the SBCS/DBCS/Unicode string */ +) +{ +#if !_LFN_UNICODE + WCHAR chr; + + chr = (BYTE)*(*ptr)++; /* Get a byte */ + if (IsLower(chr)) chr -= 0x20; /* To upper ASCII char */ +#ifdef _EXCVT + if (chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ +#else + if (IsDBCS1(chr) && IsDBCS2(**ptr)) { /* Get DBC 2nd byte if needed */ + chr = chr << 8 | (BYTE)*(*ptr)++; + } +#endif + return chr; +#else + return ff_wtoupper(*(*ptr)++); /* Get a word and to upper */ +#endif +} + + +static +int pattern_matching ( /* 0:not matched, 1:matched */ + const TCHAR* pat, /* Matching pattern */ + const TCHAR* nam, /* String to be tested */ + int skip, /* Number of pre-skip chars (number of ?s) */ + int inf /* Infinite search (* specified) */ +) +{ + const TCHAR *pp, *np; + WCHAR pc, nc; + int nm, nx; + + + while (skip--) { /* Pre-skip name chars */ + if (!get_achar(&nam)) return 0; /* Branch mismatched if less name chars */ + } + if (!*pat && inf) return 1; /* (short circuit) */ + + do { + pp = pat; np = nam; /* Top of pattern and name to match */ + for (;;) { + if (*pp == '?' || *pp == '*') { /* Wildcard? */ + nm = nx = 0; + do { /* Analyze the wildcard chars */ + if (*pp++ == '?') nm++; else nx = 1; + } while (*pp == '?' || *pp == '*'); + if (pattern_matching(pp, np, nm, nx)) return 1; /* Test new branch (recurs upto number of wildcard blocks in the pattern) */ + nc = *np; break; /* Branch mismatched */ + } + pc = get_achar(&pp); /* Get a pattern char */ + nc = get_achar(&np); /* Get a name char */ + if (pc != nc) break; /* Branch mismatched? */ + if (pc == 0) return 1; /* Branch matched? (matched at end of both strings) */ + } + get_achar(&nam); /* nam++ */ + } while (inf && nc); /* Retry until end of name if infinite search is specified */ + + return 0; +} + +#endif /* _USE_FIND && _FS_MINIMIZE <= 1 */ + + + +/*-----------------------------------------------------------------------*/ +/* Pick a top segment and create the object name in directory form */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not create */ + DIR* dp, /* Pointer to the directory object */ + const TCHAR** path /* Pointer to pointer to the segment in the path string */ +) +{ +#if _USE_LFN != 0 /* LFN configuration */ + BYTE b, cf; + WCHAR w, *lfn; + UINT i, ni, si, di; + const TCHAR *p; + + /* Create LFN in Unicode */ + p = *path; lfn = dp->obj.fs->lfnbuf; si = di = 0; + for (;;) { + w = p[si++]; /* Get a character */ + if (w < ' ') break; /* Break if end of the path name */ + if (w == '/' || w == '\\') { /* Break if a separator is found */ + while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */ + break; + } + if (di >= _MAX_LFN) return FR_INVALID_NAME; /* Reject too long name */ +#if !_LFN_UNICODE + w &= 0xFF; + if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ + b = (BYTE)p[si++]; /* Get 2nd byte */ + w = (w << 8) + b; /* Create a DBC */ + if (!IsDBCS2(b)) return FR_INVALID_NAME; /* Reject invalid sequence */ + } + w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ + if (!w) return FR_INVALID_NAME; /* Reject invalid code */ +#endif + if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) return FR_INVALID_NAME; /* Reject illegal characters for LFN */ + lfn[di++] = w; /* Store the Unicode character */ + } + *path = &p[si]; /* Return pointer to the next segment */ + cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ +#if _FS_RPATH != 0 + if ((di == 1 && lfn[di - 1] == '.') || + (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { /* Is this segment a dot name? */ + lfn[di] = 0; + for (i = 0; i < 11; i++) /* Create dot name for SFN entry */ + dp->fn[i] = (i < di) ? '.' : ' '; + dp->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } +#endif + while (di) { /* Snip off trailing spaces and dots if exist */ + w = lfn[di - 1]; + if (w != ' ' && w != '.') break; + di--; + } + lfn[di] = 0; /* LFN is created */ + if (di == 0) return FR_INVALID_NAME; /* Reject nul name */ + + /* Create SFN in directory form */ + mem_set(dp->fn, ' ', 11); + for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ + if (si) cf |= NS_LOSS | NS_LFN; + while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ + + i = b = 0; ni = 8; + for (;;) { + w = lfn[si++]; /* Get an LFN character */ + if (!w) break; /* Break on end of the LFN */ + if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ + cf |= NS_LOSS | NS_LFN; continue; + } + + if (i >= ni || si == di) { /* Extension or end of SFN */ + if (ni == 11) { /* Long extension */ + cf |= NS_LOSS | NS_LFN; break; + } + if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ + if (si > di) break; /* No extension */ + si = di; i = 8; ni = 11; /* Enter extension section */ + b <<= 2; continue; + } + + if (w >= 0x80) { /* Non ASCII character */ +#ifdef _EXCVT + w = ff_convert(w, 0); /* Unicode -> OEM code */ + if (w) w = ExCvt[w - 0x80]; /* Convert extended character to upper (SBCS) */ +#else + w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ +#endif + cf |= NS_LFN; /* Force create LFN entry */ + } + + if (_DF1S && w >= 0x100) { /* Is this DBC? (always false at SBCS cfg) */ + if (i >= ni - 1) { + cf |= NS_LOSS | NS_LFN; i = ni; continue; + } + dp->fn[i++] = (BYTE)(w >> 8); + } else { /* SBC */ + if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal characters for SFN */ + w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ + } else { + if (IsUpper(w)) { /* ASCII large capital */ + b |= 2; + } else { + if (IsLower(w)) { /* ASCII small capital */ + b |= 1; w -= 0x20; + } + } + } + } + dp->fn[i++] = (BYTE)w; + } + + if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + + if (ni == 8) b <<= 2; + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN; /* Create LFN entry when there are composite capitals */ + if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */ + if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ + if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ + } + + dp->fn[NSFLAG] = cf; /* SFN is created */ + + return FR_OK; + + +#else /* _USE_LFN != 0 : Non-LFN configuration */ + BYTE c, d, *sfn; + UINT ni, si, i; + const char *p; + + /* Create file name in directory form */ + p = *path; sfn = dp->fn; + mem_set(sfn, ' ', 11); + si = i = 0; ni = 8; +#if _FS_RPATH != 0 + if (p[si] == '.') { /* Is this a dot entry? */ + for (;;) { + c = (BYTE)p[si++]; + if (c != '.' || si >= 3) break; + sfn[i++] = c; + } + if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; + *path = p + si; /* Return pointer to the next segment */ + sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of the path */ + return FR_OK; + } +#endif + for (;;) { + c = (BYTE)p[si++]; + if (c <= ' ') break; /* Break if end of the path name */ + if (c == '/' || c == '\\') { /* Break if a separator is found */ + while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */ + break; + } + if (c == '.' || i >= ni) { /* End of body or over size? */ + if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Over size or invalid dot */ + i = 8; ni = 11; /* Goto extension */ + continue; + } + if (c >= 0x80) { /* Extended character? */ +#ifdef _EXCVT + c = ExCvt[c - 0x80]; /* To upper extended characters (SBCS cfg) */ +#else +#if !_DF1S + return FR_INVALID_NAME; /* Reject extended characters (ASCII only cfg) */ +#endif +#endif + } + if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false at SBCS cfg.) */ + d = (BYTE)p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(d) || i >= ni - 1) return FR_INVALID_NAME; /* Reject invalid DBC */ + sfn[i++] = c; + sfn[i++] = d; + } else { /* SBC */ + if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) return FR_INVALID_NAME; /* Reject illegal chrs for SFN */ + if (IsLower(c)) c -= 0x20; /* To upper */ + sfn[i++] = c; + } + } + *path = p + si; /* Return pointer to the next segment */ + if (i == 0) return FR_INVALID_NAME; /* Reject nul string */ + + if (sfn[0] == DDEM) sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ + + return FR_OK; +#endif /* _USE_LFN != 0 */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Follow a file path */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ + DIR* dp, /* Directory object to return last directory and found object */ + const TCHAR* path /* Full-path string to find a file or directory */ +) +{ + FRESULT res; + BYTE ns; + _FDID *obj = &dp->obj; + FATFS *fs = obj->fs; + + +#if _FS_RPATH != 0 + if (*path != '/' && *path != '\\') { /* Without heading separator */ + obj->sclust = fs->cdir; /* Start from the current directory */ + } else +#endif + { /* With heading separator */ + while (*path == '/' || *path == '\\') path++; /* Strip heading separator */ + obj->sclust = 0; /* Start from the root directory */ + } +#if _FS_EXFAT && _FS_RPATH != 0 + if (fs->fs_type == FS_EXFAT && obj->sclust) { /* Retrieve the sub-directory status if needed */ + DIR dj; + + obj->c_scl = fs->cdc_scl; + obj->c_size = fs->cdc_size; + obj->c_ofs = fs->cdc_ofs; + res = load_obj_dir(&dj, obj); + if (res != FR_OK) return res; + obj->objsize = ld_dword(fs->dirbuf + XDIR_FileSize); + obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; + } +#endif + + if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */ + dp->fn[NSFLAG] = NS_NONAME; + res = dir_sdi(dp, 0); + + } else { /* Follow path */ + for (;;) { + res = create_name(dp, &path); /* Get a segment name of the path */ + if (res != FR_OK) break; + res = dir_find(dp); /* Find an object with the segment name */ + ns = dp->fn[NSFLAG]; + if (res != FR_OK) { /* Failed to find the object */ + if (res == FR_NO_FILE) { /* Object is not found */ + if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */ + if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ + dp->fn[NSFLAG] = NS_NONAME; + res = FR_OK; + } else { /* Could not find the object */ + if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ + } + } + break; + } + if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ + /* Get into the sub-directory */ + if (!(obj->attr & AM_DIR)) { /* It is not a sub-directory and cannot follow */ + res = FR_NO_PATH; break; + } +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + obj->c_scl = obj->sclust; /* Save containing directory information for next dir */ + obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat; + obj->c_ofs = dp->blk_ofs; + obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Open next directory */ + obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; + obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); + } else +#endif + { + obj->sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs)); /* Open next directory */ + } + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get logical drive number from path name */ +/*-----------------------------------------------------------------------*/ + +static +int get_ldnumber ( /* Returns logical drive number (-1:invalid drive) */ + const TCHAR** path /* Pointer to pointer to the path name */ +) +{ + const TCHAR *tp, *tt; + UINT i; + int vol = -1; +#if _STR_VOLUME_ID /* Find string drive id */ + static const char* const str[] = {_VOLUME_STRS}; + const char *sp; + char c; + TCHAR tc; +#endif + + + if (*path) { /* If the pointer is not a null */ + for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ; /* Find ':' in the path */ + if (*tt == ':') { /* If a ':' is exist in the path name */ + tp = *path; + i = *tp++ - '0'; + if (i < 10 && tp == tt) { /* Is there a numeric drive id? */ + if (i < _VOLUMES) { /* If a drive id is found, get the value and strip it */ + vol = (int)i; + *path = ++tt; + } + } +#if _STR_VOLUME_ID + else { /* No numeric drive number, find string drive id */ + i = 0; tt++; + do { + sp = str[i]; tp = *path; + do { /* Compare a string drive id with path name */ + c = *sp++; tc = *tp++; + if (IsLower(tc)) tc -= 0x20; + } while (c && (TCHAR)c == tc); + } while ((c || tp != tt) && ++i < _VOLUMES); /* Repeat for each id until pattern match */ + if (i < _VOLUMES) { /* If a drive id is found, get the value and strip it */ + vol = (int)i; + *path = tt; + } + } +#endif + return vol; + } +#if _FS_RPATH != 0 && _VOLUMES >= 2 + vol = CurrVol; /* Current drive */ +#else + vol = 0; /* Drive 0 */ +#endif + } + return vol; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Load a sector and check if it is an FAT boot sector */ +/*-----------------------------------------------------------------------*/ + +static +BYTE check_fs ( /* 0:FAT, 1:exFAT, 2:Valid BS but not FAT, 3:Not a BS, 4:Disk error */ + FATFS* fs, /* File system object */ + DWORD sect /* Sector# (lba) to check if it is an FAT-VBR or not */ +) +{ + fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */ + if (move_window(fs, sect) != FR_OK) return 4; /* Load boot record */ + + if (ld_word(fs->win + BS_55AA) != 0xAA55) return 3; /* Check boot record signature (always placed at offset 510 even if the sector size is >512) */ + + if (fs->win[BS_JmpBoot] == 0xE9 || (fs->win[BS_JmpBoot] == 0xEB && fs->win[BS_JmpBoot + 2] == 0x90)) { + if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0; /* Check "FAT" string */ + if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0; /* Check "FAT3" string */ + } +#if _FS_EXFAT + if (!mem_cmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) return 1; +#endif + return 2; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Find logical drive and check if the volume is mounted */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */ + const TCHAR** path, /* Pointer to pointer to the path name (drive number) */ + FATFS** rfs, /* Pointer to pointer to the found file system object */ + BYTE mode /* !=0: Check write protection for write access */ +) +{ + BYTE fmt, *pt; + int vol; + DSTATUS stat; + DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4]; + WORD nrsv; + FATFS *fs; + UINT i; + + + /* Get logical drive number */ + *rfs = 0; + vol = get_ldnumber(path); + if (vol < 0) return FR_INVALID_DRIVE; + + /* Check if the file system object is valid or not */ + fs = FatFs[vol]; /* Get pointer to the file system object */ + if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ + + ENTER_FF(fs); /* Lock the volume */ + *rfs = fs; /* Return pointer to the file system object */ + + mode &= (BYTE)~FA_READ; /* Desired access mode, write access or not */ + if (fs->fs_type) { /* If the volume has been mounted */ + stat = disk_status(fs->drv); + if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ + if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ + return FR_WRITE_PROTECTED; + } + return FR_OK; /* The file system object is valid */ + } + } + + /* The file system object is not valid. */ + /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */ + + fs->fs_type = 0; /* Clear the file system object */ + fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ + stat = disk_initialize(fs->drv); /* Initialize the physical drive */ + if (stat & STA_NOINIT) { /* Check if the initialization succeeded */ + return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ + } + if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; + } +#if _MAX_SS != _MIN_SS /* Get sector size (multiple sector size cfg only) */ + if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR; + if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; +#endif + /* Find an FAT partition on the drive. Supports only generic partitioning, FDISK and SFD. */ + bsect = 0; + fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT-VBR as SFD */ + if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) { /* Not an FAT-VBR or forced partition number */ + for (i = 0; i < 4; i++) { /* Get partition offset */ + pt = fs->win + (MBR_Table + i * SZ_PTE); + br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0; + } + i = LD2PT(vol); /* Partition number: 0:auto, 1-4:forced */ + if (i) i--; + do { /* Find an FAT volume */ + bsect = br[i]; + fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */ + } while (!LD2PT(vol) && fmt >= 2 && ++i < 4); + } + if (fmt == 4) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ + if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + + /* An FAT volume is found. Following code initializes the file system object */ + +#if _FS_EXFAT + if (fmt == 1) { + QWORD maxlba; + + for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ; /* Check zero filler */ + if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM; + + if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM; /* Check exFAT revision (Must be 1.0) */ + + if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) /* (BPB_BytsPerSecEx must be equal to the physical sector size) */ + return FR_NO_FILESYSTEM; + + maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect; /* Last LBA + 1 of the volume */ + if (maxlba >= 0x100000000) return FR_NO_FILESYSTEM; /* (It cannot be handled in 32-bit LBA) */ + + fs->fsize = ld_dword(fs->win + BPB_FatSzEx); /* Number of sectors per FAT */ + + fs->n_fats = fs->win[BPB_NumFATsEx]; /* Number of FATs */ + if (fs->n_fats != 1) return FR_NO_FILESYSTEM; /* (Supports only 1 FAT) */ + + fs->csize = 1 << fs->win[BPB_SecPerClusEx]; /* Cluster size */ + if (fs->csize == 0) return FR_NO_FILESYSTEM; /* (Must be 1..32768) */ + + nclst = ld_dword(fs->win + BPB_NumClusEx); /* Number of clusters */ + if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM; /* (Too many clusters) */ + fs->n_fatent = nclst + 2; + + /* Boundaries and Limits */ + fs->volbase = bsect; + fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx); + fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx); + if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM; /* (Volume size must not be smaller than the size requiered) */ + fs->dirbase = ld_dword(fs->win + BPB_RootClusEx); + + /* Check if bitmap location is in assumption (at the first cluster) */ + if (move_window(fs, clust2sect(fs, fs->dirbase)) != FR_OK) return FR_DISK_ERR; + for (i = 0; i < SS(fs); i += SZDIRE) { + if (fs->win[i] == 0x81 && ld_dword(fs->win + i + 20) == 2) break; /* 81 entry with cluster #2? */ + } + if (i == SS(fs)) return FR_NO_FILESYSTEM; +#if !_FS_READONLY + fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ +#endif + fmt = FS_EXFAT; /* FAT sub-type */ + } else +#endif /* _FS_EXFAT */ + { + if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must be equal to the physical sector size) */ + + fasize = ld_word(fs->win + BPB_FATSz16); /* Number of sectors per FAT */ + if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32); + fs->fsize = fasize; + + fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FATs */ + if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + fasize *= fs->n_fats; /* Number of sectors for FAT area */ + + fs->csize = fs->win[BPB_SecPerClus]; /* Cluster size */ + if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ + + fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt); /* Number of root directory entries */ + if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ + + tsect = ld_word(fs->win + BPB_TotSec16); /* Number of sectors on the volume */ + if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32); + + nrsv = ld_word(fs->win + BPB_RsvdSecCnt); /* Number of reserved sectors */ + if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */ + + /* Determine the FAT sub type */ + sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE); /* RSV + FAT + DIR */ + if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + fmt = FS_FAT32; + if (nclst <= MAX_FAT16) fmt = FS_FAT16; + if (nclst <= MAX_FAT12) fmt = FS_FAT12; + + /* Boundaries and Limits */ + fs->n_fatent = nclst + 2; /* Number of FAT entries */ + fs->volbase = bsect; /* Volume start sector */ + fs->fatbase = bsect + nrsv; /* FAT start sector */ + fs->database = bsect + sysect; /* Data start sector */ + if (fmt == FS_FAT32) { + if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0) */ + if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */ + szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ + } else { + if (fs->n_rootdir == 0) return FR_NO_FILESYSTEM;/* (BPB_RootEntCnt must not be 0) */ + fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ + fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + } + if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_FATSz must not be less than the size needed) */ + +#if !_FS_READONLY + /* Get FSINFO if available */ + fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ + fs->fsi_flag = 0x80; +#if (_FS_NOFSINFO & 3) != 3 + if (fmt == FS_FAT32 /* Enable FSINFO only if FAT32 and BPB_FSInfo32 == 1 */ + && ld_word(fs->win + BPB_FSInfo32) == 1 + && move_window(fs, bsect + 1) == FR_OK) + { + fs->fsi_flag = 0; + if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSINFO data if available */ + && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 + && ld_dword(fs->win + FSI_StrucSig) == 0x61417272) + { +#if (_FS_NOFSINFO & 1) == 0 + fs->free_clst = ld_dword(fs->win + FSI_Free_Count); +#endif +#if (_FS_NOFSINFO & 2) == 0 + fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free); +#endif + } + } +#endif /* (_FS_NOFSINFO & 3) != 3 */ +#endif /* !_FS_READONLY */ + } + + fs->fs_type = fmt; /* FAT sub-type */ + fs->id = ++Fsid; /* File system mount ID */ +#if _USE_LFN == 1 + fs->lfnbuf = LfnBuf; /* Static LFN working buffer */ +#if _FS_EXFAT + fs->dirbuf = DirBuf; /* Static directory block working buuffer */ +#endif +#endif +#if _FS_RPATH != 0 + fs->cdir = 0; /* Initialize current directory */ +#endif +#if _FS_LOCK != 0 /* Clear file lock semaphores */ + clear_lock(fs); +#endif + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/directory object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */ + _FDID* obj, /* Pointer to the _OBJ, the 1st member in the FIL/DIR object, to check validity */ + FATFS** fs /* Pointer to pointer to the owner file system object to return */ +) +{ + FRESULT res; + + + if (!obj || !obj->fs || !obj->fs->fs_type || obj->fs->id != obj->id || (disk_status(obj->fs->drv) & STA_NOINIT)) { + *fs = 0; /* The object is invalid */ + res = FR_INVALID_OBJECT; + } else { + *fs = obj->fs; /* Owner file sytem object */ + ENTER_FF(obj->fs); /* Lock file system */ + res = FR_OK; + } + return res; +} + + + + +/*--------------------------------------------------------------------------- + + Public Functions (FatFs API) + +----------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Logical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + FATFS* fs, /* Pointer to the file system object (NULL:unmount)*/ + const TCHAR* path, /* Logical drive number to be mounted/unmounted */ + BYTE opt /* Mode option 0:Do not mount (delayed mount), 1:Mount immediately */ +) +{ + FATFS *cfs; + int vol; + FRESULT res; + const TCHAR *rp = path; + + + /* Get logical drive number */ + vol = get_ldnumber(&rp); + if (vol < 0) return FR_INVALID_DRIVE; + cfs = FatFs[vol]; /* Pointer to fs object */ + + if (cfs) { +#if _FS_LOCK != 0 + clear_lock(cfs); +#endif +#if _FS_REENTRANT /* Discard sync object of the current volume */ + if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR; +#endif + cfs->fs_type = 0; /* Clear old fs object */ + } + + if (fs) { + fs->fs_type = 0; /* Clear new fs object */ +#if _FS_REENTRANT /* Create sync object for the new volume */ + if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR; +#endif + } + FatFs[vol] = fs; /* Register new fs object */ + + if (!fs || opt != 1) return FR_OK; /* Do not mount now, it will be mounted later */ + + res = find_volume(&path, &fs, 0); /* Force mounted the volume */ + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL* fp, /* Pointer to the blank file object */ + const TCHAR* path, /* Pointer to the file name */ + BYTE mode /* Access mode and file open mode flags */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; +#if !_FS_READONLY + DWORD dw, cl, bcs, clst, sc; + FSIZE_t ofs; +#endif + DEF_NAMBUF + + + if (!fp) return FR_INVALID_OBJECT; + + /* Get logical drive */ + mode &= _FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND | FA_SEEKEND; + res = find_volume(&path, &fs, mode); + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ +#if !_FS_READONLY /* R/W configuration */ + if (res == FR_OK) { + if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ + res = FR_INVALID_NAME; + } +#if _FS_LOCK != 0 + else { + res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); + } +#endif + } + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { + if (res != FR_OK) { /* No file, create new */ + if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ +#if _FS_LOCK != 0 + res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; +#else + res = dir_register(&dj); +#endif + mode |= FA_CREATE_ALWAYS; /* File is created */ + } + else { /* Any object is already existing */ + if (dj.obj.attr & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ + res = FR_DENIED; + } else { + if (mode & FA_CREATE_NEW) res = FR_EXIST; /* Cannot create as new file */ + } + } + if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ + dw = GET_FATTIME(); +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + /* Get current allocation info */ + fp->obj.fs = fs; + fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus); + fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize); + fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; + /* Initialize directory entry block */ + st_dword(fs->dirbuf + XDIR_CrtTime, dw); /* Set created time */ + fs->dirbuf[XDIR_CrtTime10] = 0; + st_dword(fs->dirbuf + XDIR_ModTime, dw); /* Set modified time */ + fs->dirbuf[XDIR_ModTime10] = 0; + fs->dirbuf[XDIR_Attr] = AM_ARC; /* Reset attribute */ + st_dword(fs->dirbuf + XDIR_FstClus, 0); /* Reset file allocation info */ + st_qword(fs->dirbuf + XDIR_FileSize, 0); + st_qword(fs->dirbuf + XDIR_ValidFileSize, 0); + fs->dirbuf[XDIR_GenFlags] = 1; + res = store_xdir(&dj); + if (res == FR_OK && fp->obj.sclust) { /* Remove the cluster chain if exist */ + res = remove_chain(&fp->obj, fp->obj.sclust, 0); + fs->last_clst = fp->obj.sclust - 1; /* Reuse the cluster hole */ + } + } else +#endif + { + /* Clean directory info */ + st_dword(dj.dir + DIR_CrtTime, dw); /* Set created time */ + st_dword(dj.dir + DIR_ModTime, dw); /* Set modified time */ + dj.dir[DIR_Attr] = AM_ARC; /* Reset attribute */ + cl = ld_clust(fs, dj.dir); /* Get cluster chain */ + st_clust(fs, dj.dir, 0); /* Reset file allocation info */ + st_dword(dj.dir + DIR_FileSize, 0); + fs->wflag = 1; + + if (cl) { /* Remove the cluster chain if exist */ + dw = fs->winsect; + res = remove_chain(&dj.obj, cl, 0); + if (res == FR_OK) { + res = move_window(fs, dw); + fs->last_clst = cl - 1; /* Reuse the cluster hole */ + } + } + } + } + } + else { /* Open an existing file */ + if (res == FR_OK) { /* Following succeeded */ + if (dj.obj.attr & AM_DIR) { /* It is a directory */ + res = FR_NO_FILE; + } else { + if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* R/O violation */ + res = FR_DENIED; + } + } + } + } + if (res == FR_OK) { + if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ + mode |= FA_MODIFIED; + fp->dir_sect = fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dj.dir; +#if _FS_LOCK != 0 + fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); + if (!fp->obj.lockid) res = FR_INT_ERR; +#endif + } +#else /* R/O configuration */ + if (res == FR_OK) { + if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ + res = FR_INVALID_NAME; + } else { + if (dj.obj.attr & AM_DIR) { /* It is a directory */ + res = FR_NO_FILE; + } + } + } +#endif + + if (res == FR_OK) { +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Get allocation info */ + fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize); + fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; + fp->obj.c_scl = dj.obj.sclust; + fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; + fp->obj.c_ofs = dj.blk_ofs; + } else +#endif + { + fp->obj.sclust = ld_clust(fs, dj.dir); /* Get allocation info */ + fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); + } +#if _USE_FASTSEEK + fp->cltbl = 0; /* Disable fast seek mode */ +#endif + fp->obj.fs = fs; /* Validate the file object */ + fp->obj.id = fs->id; + fp->flag = mode; /* Set file access mode */ + fp->err = 0; /* Clear error flag */ + fp->sect = 0; /* Invalidate current data sector */ + fp->fptr = 0; /* Set file pointer top of the file */ +#if !_FS_READONLY +#if !_FS_TINY + mem_set(fp->buf, 0, _MAX_SS); /* Clear sector buffer */ +#endif + if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) { /* Seek to end of file if FA_OPEN_APPEND is specified */ + fp->fptr = fp->obj.objsize; /* Offset to seek */ + bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */ + clst = fp->obj.sclust; /* Follow the cluster chain */ + for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) { + clst = get_fat(&fp->obj, clst); + if (clst <= 1) res = FR_INT_ERR; + if (clst == 0xFFFFFFFF) res = FR_DISK_ERR; + } + fp->clust = clst; + if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */ + if ((sc = clust2sect(fs, clst)) == 0) { + res = FR_INT_ERR; + } else { + fp->sect = sc + (DWORD)(ofs / SS(fs)); +#if !_FS_TINY + if (disk_read(fs->drv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR; +#endif + } + } + } +#endif + } + + FREE_NAMBUF(); + } + + if (res != FR_OK) fp->obj.fs = 0; /* Invalidate file object on error */ + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL* fp, /* Pointer to the file object */ + void* buff, /* Pointer to data buffer */ + UINT btr, /* Number of bytes to read */ + UINT* br /* Pointer to number of bytes read */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst, sect; + FSIZE_t remain; + UINT rcnt, cc, csect; + BYTE *rbuff = (BYTE*)buff; + + + *br = 0; /* Clear read byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + remain = fp->obj.objsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr; /* Repeat until all data read */ + rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + if (csect == 0) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->obj.sclust; /* Follow cluster chain from the origin */ + } else { /* Middle or end of the file */ +#if _USE_FASTSEEK + if (fp->cltbl) { + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + } else +#endif + { + clst = get_fat(&fp->obj, fp->clust); /* Follow cluster chain on the FAT */ + } + } + if (clst < 2) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + sect = clust2sect(fs, fp->clust); /* Get current sector */ + if (!sect) ABORT(fs, FR_INT_ERR); + sect += csect; + cc = btr / SS(fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Read maximum contiguous sectors directly */ + if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + cc = fs->csize - csect; + } + if (disk_read(fs->drv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); +#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ +#if _FS_TINY + if (fs->wflag && fs->winsect - sect < cc) { + mem_cpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs)); + } +#else + if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) { + mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); + } +#endif +#endif + rcnt = SS(fs) * cc; /* Number of bytes transferred */ + continue; + } +#if !_FS_TINY + if (fp->sect != sect) { /* Load data sector if not in cache */ +#if !_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ + } +#endif + fp->sect = sect; + } + rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ + if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ +#if _FS_TINY + if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ + mem_cpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ +#else + mem_cpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ +#endif + } + + LEAVE_FF(fs, FR_OK); +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL* fp, /* Pointer to the file object */ + const void* buff, /* Pointer to the data to be written */ + UINT btw, /* Number of bytes to write */ + UINT* bw /* Pointer to number of bytes written */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst, sect; + UINT wcnt, cc, csect; + const BYTE *wbuff = (const BYTE*)buff; + + + *bw = 0; /* Clear write byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + /* Check fptr wrap-around (file size cannot reach 4GiB on FATxx) */ + if ((!_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) { + btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr); + } + + for ( ; btw; /* Repeat until all data written */ + wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize, *bw += wcnt, btw -= wcnt) { + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ + if (csect == 0) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->obj.sclust; /* Follow from the origin */ + if (clst == 0) { /* If no cluster is allocated, */ + clst = create_chain(&fp->obj, 0); /* create a new cluster chain */ + } + } else { /* On the middle or end of the file */ +#if _USE_FASTSEEK + if (fp->cltbl) { + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + } else +#endif + { + clst = create_chain(&fp->obj, fp->clust); /* Follow or stretch cluster chain on the FAT */ + } + } + if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clst == 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */ + } +#if _FS_TINY + if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Write-back sector cache */ +#else + if (fp->flag & FA_DIRTY) { /* Write-back sector cache */ + if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + sect = clust2sect(fs, fp->clust); /* Get current sector */ + if (!sect) ABORT(fs, FR_INT_ERR); + sect += csect; + cc = btw / SS(fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Write maximum contiguous sectors directly */ + if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + cc = fs->csize - csect; + } + if (disk_write(fs->drv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); +#if _FS_MINIMIZE <= 2 +#if _FS_TINY + if (fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + mem_cpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs)); + fs->wflag = 0; + } +#else + if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs)); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif +#endif + wcnt = SS(fs) * cc; /* Number of bytes transferred */ + continue; + } +#if _FS_TINY + if (fp->fptr >= fp->obj.objsize) { /* Avoid silly cache filling on the growing edge */ + if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); + fs->winsect = sect; + } +#else + if (fp->sect != sect && /* Fill sector cache with file data */ + fp->fptr < fp->obj.objsize && + disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } +#endif + fp->sect = sect; + } + wcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ + if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ +#if _FS_TINY + if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ + mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ + fs->wflag = 1; +#else + mem_cpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ + fp->flag |= FA_DIRTY; +#endif + } + + fp->flag |= FA_MODIFIED; /* Set file change flag */ + + LEAVE_FF(fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL* fp /* Pointer to the file object */ +) +{ + FRESULT res; + FATFS *fs; + DWORD tm; + BYTE *dir; + // DEF_NAMBUF + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res == FR_OK) { + if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */ +#if !_FS_TINY + if (fp->flag & FA_DIRTY) { /* Write-back cached data if needed */ + if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + /* Update the directory entry */ + tm = GET_FATTIME(); /* Modified time */ +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + res = fill_fat_chain(&fp->obj); /* Create FAT chain if needed */ + if (res == FR_OK) { + DIR dj; + + INIT_NAMBUF(fs); + res = load_obj_dir(&dj, &fp->obj); /* Load directory entry block */ + if (res == FR_OK) { + fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive bit */ + fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1; /* Update file allocation info */ + st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust); + st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize); + st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize); + st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Update modified time */ + fs->dirbuf[XDIR_ModTime10] = 0; + st_dword(fs->dirbuf + XDIR_AccTime, 0); + res = store_xdir(&dj); /* Restore it to the directory */ + if (res == FR_OK) { + res = sync_fs(fs); + fp->flag &= (BYTE)~FA_MODIFIED; + } + } + FREE_NAMBUF(); + } + } else +#endif + { + res = move_window(fs, fp->dir_sect); + if (res == FR_OK) { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation info */ + st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */ + st_dword(dir + DIR_ModTime, tm); /* Update modified time */ + st_word(dir + DIR_LstAccDate, 0); + fs->wflag = 1; + res = sync_fs(fs); /* Restore it to the directory */ + fp->flag &= (BYTE)~FA_MODIFIED; + } + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL* fp /* Pointer to the file object to be closed */ +) +{ + FRESULT res; + FATFS *fs; + +#if !_FS_READONLY + res = f_sync(fp); /* Flush cached data */ + if (res == FR_OK) +#endif + { + res = validate(&fp->obj, &fs); /* Lock volume */ + if (res == FR_OK) { +#if _FS_LOCK != 0 + res = dec_lock(fp->obj.lockid); /* Decrement file open counter */ + if (res == FR_OK) +#endif + { + fp->obj.fs = 0; /* Invalidate file object */ + } +#if _FS_REENTRANT + unlock_fs(fs, FR_OK); /* Unlock volume */ +#endif + } + } + return res; +} + + + + +#if _FS_RPATH >= 1 +/*-----------------------------------------------------------------------*/ +/* Change Current Directory or Current Drive, Get Current Directory */ +/*-----------------------------------------------------------------------*/ + +#if _VOLUMES >= 2 +FRESULT f_chdrive ( + const TCHAR* path /* Drive number */ +) +{ + int vol; + + + /* Get logical drive number */ + vol = get_ldnumber(&path); + if (vol < 0) return FR_INVALID_DRIVE; + + CurrVol = (BYTE)vol; /* Set it as current volume */ + + return FR_OK; +} +#endif + + +FRESULT f_chdir ( + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + DEF_NAMBUF + + /* Get logical drive */ + res = find_volume(&path, &fs, 0); + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.fn[NSFLAG] & NS_NONAME) { + fs->cdir = dj.obj.sclust; /* It is the start directory itself */ +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->cdc_scl = dj.obj.c_scl; + fs->cdc_size = dj.obj.c_size; + fs->cdc_ofs = dj.obj.c_ofs; + } +#endif + } else { + if (dj.obj.attr & AM_DIR) { /* It is a sub-directory */ +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus); /* Sub-directory cluster */ + fs->cdc_scl = dj.obj.sclust; /* Save containing directory information */ + fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; + fs->cdc_ofs = dj.blk_ofs; + } else +#endif + { + fs->cdir = ld_clust(fs, dj.dir); /* Sub-directory cluster */ + } + } else { + res = FR_NO_PATH; /* Reached but a file */ + } + } + } + FREE_NAMBUF(); + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(fs, res); +} + + +#if _FS_RPATH >= 2 +FRESULT f_getcwd ( + TCHAR* buff, /* Pointer to the directory path */ + UINT len /* Size of path */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + UINT i, n; + DWORD ccl; + TCHAR *tp; + FILINFO fno; + DEF_NAMBUF + + + *buff = 0; + /* Get logical drive */ + res = find_volume((const TCHAR**)&buff, &fs, 0); /* Get current volume */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + i = len; /* Bottom of buffer (directory stack base) */ + if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* (Cannot do getcwd on exFAT and returns root path) */ + dj.obj.sclust = fs->cdir; /* Start to follow upper directory from current directory */ + while ((ccl = dj.obj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ + res = dir_sdi(&dj, 1 * SZDIRE); /* Get parent directory */ + if (res != FR_OK) break; + res = move_window(fs, dj.sect); + if (res != FR_OK) break; + dj.obj.sclust = ld_clust(fs, dj.dir); /* Goto parent directory */ + res = dir_sdi(&dj, 0); + if (res != FR_OK) break; + do { /* Find the entry links to the child directory */ + res = dir_read(&dj, 0); + if (res != FR_OK) break; + if (ccl == ld_clust(fs, dj.dir)) break; /* Found the entry */ + res = dir_next(&dj, 0); + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ + if (res != FR_OK) break; + get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ + for (n = 0; fno.fname[n]; n++) ; + if (i < n + 3) { + res = FR_NOT_ENOUGH_CORE; break; + } + while (n) buff[--i] = fno.fname[--n]; + buff[--i] = '/'; + } + } + tp = buff; + if (res == FR_OK) { +#if _VOLUMES >= 2 + *tp++ = '0' + CurrVol; /* Put drive number */ + *tp++ = ':'; +#endif + if (i == len) { /* Root-directory */ + *tp++ = '/'; + } else { /* Sub-directroy */ + do /* Add stacked path str */ + *tp++ = buff[i++]; + while (i < len); + } + } + *tp = 0; + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + +#endif /* _FS_RPATH >= 2 */ +#endif /* _FS_RPATH >= 1 */ + + + +#if _FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File R/W Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL* fp, /* Pointer to the file object */ + FSIZE_t ofs /* File pointer from top of file */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst, bcs, nsect; + FSIZE_t ifptr; +#if _USE_FASTSEEK + DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl; +#endif + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ +#if _USE_FASTSEEK + if (fp->cltbl) { /* Fast seek */ + if (ofs == CREATE_LINKMAP) { /* Create CLMT */ + tbl = fp->cltbl; + tlen = *tbl++; ulen = 2; /* Given table size and required table size */ + cl = fp->obj.sclust; /* Origin of the chain */ + if (cl) { + do { + /* Get a fragment */ + tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ + do { + pcl = cl; ncl++; + cl = get_fat(&fp->obj, cl); + if (cl <= 1) ABORT(fs, FR_INT_ERR); + if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + } while (cl == pcl + 1); + if (ulen <= tlen) { /* Store the length and top of the fragment */ + *tbl++ = ncl; *tbl++ = tcl; + } + } while (cl < fs->n_fatent); /* Repeat until end of chain */ + } + *fp->cltbl = ulen; /* Number of items used */ + if (ulen <= tlen) { + *tbl = 0; /* Terminate table */ + } else { + res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ + } + } else { /* Fast seek */ + if (ofs > fp->obj.objsize) ofs = fp->obj.objsize; /* Clip offset at the file size */ + fp->fptr = ofs; /* Set file pointer */ + if (ofs) { + fp->clust = clmt_clust(fp, ofs - 1); + dsc = clust2sect(fs, fp->clust); + if (!dsc) ABORT(fs, FR_INT_ERR); + dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); + if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->drv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Load current sector */ +#endif + fp->sect = dsc; + } + } + } + } else +#endif + + /* Normal Seek */ + { +#if _FS_EXFAT + if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF; /* Clip at 4GiB-1 if at FATxx */ +#endif + if (ofs > fp->obj.objsize && (_FS_READONLY || !(fp->flag & FA_WRITE))) { /* In read-only mode, clip offset with the file size */ + ofs = fp->obj.objsize; + } + ifptr = fp->fptr; + fp->fptr = nsect = 0; + if (ofs) { + bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->clust; + } else { /* When seek to back cluster, */ + clst = fp->obj.sclust; /* start from the first cluster */ +#if !_FS_READONLY + if (clst == 0) { /* If no cluster chain, create a new chain */ + clst = create_chain(&fp->obj, 0); + if (clst == 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->obj.sclust = clst; + } +#endif + fp->clust = clst; + } + if (clst != 0) { + while (ofs > bcs) { /* Cluster following loop */ + ofs -= bcs; fp->fptr += bcs; +#if !_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + if (_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize to generate FAT value */ + fp->obj.objsize = fp->fptr; + fp->flag |= FA_MODIFIED; + } + clst = create_chain(&fp->obj, clst); /* Follow chain with forceed stretch */ + if (clst == 0) { /* Clip file size in case of disk full */ + ofs = 0; break; + } + } else +#endif + { + clst = get_fat(&fp->obj, clst); /* Follow cluster chain if not in write mode */ + } + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + fp->clust = clst; + } + fp->fptr += ofs; + if (ofs % SS(fs)) { + nsect = clust2sect(fs, clst); /* Current sector */ + if (!nsect) ABORT(fs, FR_INT_ERR); + nsect += (DWORD)(ofs / SS(fs)); + } + } + } + if (!_FS_READONLY && fp->fptr > fp->obj.objsize) { /* Set file change flag if the file size is extended */ + fp->obj.objsize = fp->fptr; + fp->flag |= FA_MODIFIED; + } + if (fp->fptr % SS(fs) && nsect != fp->sect) { /* Fill sector cache if needed */ +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->drv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ +#endif + fp->sect = nsect; + } + } + + LEAVE_FF(fs, res); +} + + + +#if _FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a Directory Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR* dp, /* Pointer to directory object to create */ + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + FATFS *fs; + _FDID *obj; + DEF_NAMBUF + + + if (!dp) return FR_INVALID_OBJECT; + + /* Get logical drive */ + obj = &dp->obj; + res = find_volume(&path, &fs, 0); + if (res == FR_OK) { + obj->fs = fs; + INIT_NAMBUF(fs); + res = follow_path(dp, path); /* Follow the path to the directory */ + if (res == FR_OK) { /* Follow completed */ + if (!(dp->fn[NSFLAG] & NS_NONAME)) { /* It is not the origin directory itself */ + if (obj->attr & AM_DIR) { /* This object is a sub-directory */ +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + obj->c_scl = obj->sclust; /* Save containing directory inforamation */ + obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat; + obj->c_ofs = dp->blk_ofs; + obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Get object location and status */ + obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); + obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; + } else +#endif + { + obj->sclust = ld_clust(fs, dp->dir); /* Get object location */ + } + } else { /* This object is a file */ + res = FR_NO_PATH; + } + } + if (res == FR_OK) { + obj->id = fs->id; + res = dir_sdi(dp, 0); /* Rewind directory */ +#if _FS_LOCK != 0 + if (res == FR_OK) { + if (obj->sclust) { + obj->lockid = inc_lock(dp, 0); /* Lock the sub directory */ + if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES; + } else { + obj->lockid = 0; /* Root directory need not to be locked */ + } + } +#endif + } + } + FREE_NAMBUF(); + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + if (res != FR_OK) obj->fs = 0; /* Invalidate the directory object if function faild */ + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Close Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_closedir ( + DIR *dp /* Pointer to the directory object to be closed */ +) +{ + FRESULT res; + FATFS *fs; + + + res = validate(&dp->obj, &fs); /* Check validity of the file object */ + if (res == FR_OK) { +#if _FS_LOCK != 0 + if (dp->obj.lockid) { /* Decrement sub-directory open counter */ + res = dec_lock(dp->obj.lockid); + } + if (res == FR_OK) +#endif + { + dp->obj.fs = 0; /* Invalidate directory object */ + } +#if _FS_REENTRANT + unlock_fs(fs, FR_OK); /* Unlock volume */ +#endif + } + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entries in Sequence */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR* dp, /* Pointer to the open directory object */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + FATFS *fs; + DEF_NAMBUF + + + res = validate(&dp->obj, &fs); /* Check validity of the directory object */ + if (res == FR_OK) { + if (!fno) { + res = dir_sdi(dp, 0); /* Rewind the directory object */ + } else { + INIT_NAMBUF(fs); + res = dir_read(dp, 0); /* Read an item */ + if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */ + if (res == FR_OK) { /* A valid entry is found */ + get_fileinfo(dp, fno); /* Get the object information */ + res = dir_next(dp, 0); /* Increment index for next */ + if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */ + } + FREE_NAMBUF(); + } + } + LEAVE_FF(fs, res); +} + + + +#if _USE_FIND +/*-----------------------------------------------------------------------*/ +/* Find Next File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_findnext ( + DIR* dp, /* Pointer to the open directory object */ + FILINFO* fno /* Pointer to the file information structure */ +) +{ + FRESULT res; + + + for (;;) { + res = f_readdir(dp, fno); /* Get a directory item */ + if (res != FR_OK || !fno || !fno->fname[0]) break; /* Terminate if any error or end of directory */ + if (pattern_matching(dp->pat, fno->fname, 0, 0)) break; /* Test for the file name */ +#if _USE_LFN != 0 && _USE_FIND == 2 + if (pattern_matching(dp->pat, fno->altname, 0, 0)) break; /* Test for alternative name if exist */ +#endif + } + return res; +} + + + +/*-----------------------------------------------------------------------*/ +/* Find First File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_findfirst ( + DIR* dp, /* Pointer to the blank directory object */ + FILINFO* fno, /* Pointer to the file information structure */ + const TCHAR* path, /* Pointer to the directory to open */ + const TCHAR* pattern /* Pointer to the matching pattern */ +) +{ + FRESULT res; + + + dp->pat = pattern; /* Save pointer to pattern string */ + res = f_opendir(dp, path); /* Open the target directory */ + if (res == FR_OK) { + res = f_findnext(dp, fno); /* Find the first item */ + } + return res; +} + +#endif /* _USE_FIND */ + + + +#if _FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const TCHAR* path, /* Pointer to the file path */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMBUF + + + /* Get logical drive */ + res = find_volume(&path, &dj.obj.fs, 0); + if (res == FR_OK) { + INIT_NAMBUF(dj.obj.fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */ + res = FR_INVALID_NAME; + } else { /* Found an object */ + if (fno) get_fileinfo(&dj, fno); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(dj.obj.fs, res); +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const TCHAR* path, /* Path name of the logical drive number */ + DWORD* nclst, /* Pointer to a variable to return number of free clusters */ + FATFS** fatfs /* Pointer to return pointer to corresponding file system object */ +) +{ + FRESULT res; + FATFS *fs; + DWORD nfree, clst, sect, stat; + UINT i; + BYTE *p; + _FDID obj; + + + /* Get logical drive */ + res = find_volume(&path, &fs, 0); + if (res == FR_OK) { + *fatfs = fs; /* Return ptr to the fs object */ + /* If free_clst is valid, return it without full cluster scan */ + if (fs->free_clst <= fs->n_fatent - 2) { + *nclst = fs->free_clst; + } else { + /* Get number of free clusters */ + nfree = 0; + if (fs->fs_type == FS_FAT12) { /* FAT12: Sector unalighed FAT entries */ + clst = 2; obj.fs = fs; + do { + stat = get_fat(&obj, clst); + if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + if (stat == 1) { res = FR_INT_ERR; break; } + if (stat == 0) nfree++; + } while (++clst < fs->n_fatent); + } else { +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* exFAT: Scan bitmap table */ + BYTE bm; + UINT b; + + clst = fs->n_fatent - 2; + sect = fs->database; + i = 0; + do { + if (i == 0 && (res = move_window(fs, sect++)) != FR_OK) break; + for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) { + if (!(bm & 1)) nfree++; + bm >>= 1; + } + i = (i + 1) % SS(fs); + } while (clst); + } else +#endif + { /* FAT16/32: Sector alighed FAT entries */ + clst = fs->n_fatent; sect = fs->fatbase; + i = 0; p = 0; + do { + if (i == 0) { + res = move_window(fs, sect++); + if (res != FR_OK) break; + p = fs->win; + i = SS(fs); + } + if (fs->fs_type == FS_FAT16) { + if (ld_word(p) == 0) nfree++; + p += 2; i -= 2; + } else { + if ((ld_dword(p) & 0x0FFFFFFF) == 0) nfree++; + p += 4; i -= 4; + } + } while (--clst); + } + } + *nclst = nfree; /* Return the free clusters */ + fs->free_clst = nfree; /* Now free_clst is valid */ + fs->fsi_flag |= 1; /* FSInfo is to be updated */ + } + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL* fp /* Pointer to the file object */ +) +{ + FRESULT res; + FATFS *fs; + DWORD ncl; + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + if (fp->obj.objsize > fp->fptr) { + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain(&fp->obj, fp->obj.sclust, 0); + fp->obj.sclust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat(&fp->obj, fp->clust); + res = FR_OK; + if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (ncl == 1) res = FR_INT_ERR; + if (res == FR_OK && ncl < fs->n_fatent) { + res = remove_chain(&fp->obj, ncl, fp->clust); + } + } + fp->obj.objsize = fp->fptr; /* Set file size to current R/W point */ + fp->flag |= FA_MODIFIED; +#if !_FS_TINY + if (res == FR_OK && (fp->flag & FA_DIRTY)) { + if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) { + res = FR_DISK_ERR; + } else { + fp->flag &= (BYTE)~FA_DIRTY; + } + } +#endif + if (res != FR_OK) ABORT(fs, res); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const TCHAR* path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR dj, sdj; + DWORD dclst = 0; + FATFS *fs; +#if _FS_EXFAT + _FDID obj; +#endif + DEF_NAMBUF + + + /* Get logical drive */ + res = find_volume(&path, &fs, FA_WRITE); + dj.obj.fs = fs; + if (res == FR_OK) { + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) { + res = FR_INVALID_NAME; /* Cannot remove dot entry */ + } +#if _FS_LOCK != 0 + if (res == FR_OK) res = chk_lock(&dj, 2); /* Check if it is an open object */ +#endif + if (res == FR_OK) { /* The object is accessible */ + if (dj.fn[NSFLAG] & NS_NONAME) { + res = FR_INVALID_NAME; /* Cannot remove the origin directory */ + } else { + if (dj.obj.attr & AM_RDO) { + res = FR_DENIED; /* Cannot remove R/O object */ + } + } + if (res == FR_OK) { +#if _FS_EXFAT + obj.fs = fs; + if (fs->fs_type == FS_EXFAT) { + obj.sclust = dclst = ld_dword(fs->dirbuf + XDIR_FstClus); + obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize); + obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; + } else +#endif + { + dclst = ld_clust(fs, dj.dir); + } + if (dj.obj.attr & AM_DIR) { /* Is it a sub-directory ? */ +#if _FS_RPATH != 0 + if (dclst == fs->cdir) { /* Is it the current directory? */ + res = FR_DENIED; + } else +#endif + { + sdj.obj.fs = fs; /* Open the sub-directory */ + sdj.obj.sclust = dclst; +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + sdj.obj.objsize = obj.objsize; + sdj.obj.stat = obj.stat; + } +#endif + res = dir_sdi(&sdj, 0); + if (res == FR_OK) { + res = dir_read(&sdj, 0); /* Read an item */ + if (res == FR_OK) res = FR_DENIED; /* Not empty? */ + if (res == FR_NO_FILE) res = FR_OK; /* Empty? */ + } + } + } + } + if (res == FR_OK) { + res = dir_remove(&dj); /* Remove the directory entry */ + if (res == FR_OK && dclst) { /* Remove the cluster chain if exist */ +#if _FS_EXFAT + res = remove_chain(&obj, dclst, 0); +#else + res = remove_chain(&dj.obj, dclst, 0); +#endif + } + if (res == FR_OK) res = sync_fs(fs); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + BYTE *dir; + UINT n; + DWORD dsc, dcl, pcl, tm; + DEF_NAMBUF + + + /* Get logical drive */ + res = find_volume(&path, &fs, FA_WRITE); + dj.obj.fs = fs; + if (res == FR_OK) { + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ + if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) { + res = FR_INVALID_NAME; + } + if (res == FR_NO_FILE) { /* Can create a new directory */ + dcl = create_chain(&dj.obj, 0); /* Allocate a cluster for the new directory table */ + dj.obj.objsize = (DWORD)fs->csize * SS(fs); + res = FR_OK; + if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ + if (dcl == 1) res = FR_INT_ERR; + if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) res = sync_window(fs); /* Flush FAT */ + tm = GET_FATTIME(); + if (res == FR_OK) { /* Initialize the new directory table */ + dsc = clust2sect(fs, dcl); + dir = fs->win; + mem_set(dir, 0, SS(fs)); + if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { + mem_set(dir + DIR_Name, ' ', 11); /* Create "." entry */ + dir[DIR_Name] = '.'; + dir[DIR_Attr] = AM_DIR; + st_dword(dir + DIR_ModTime, tm); + st_clust(fs, dir, dcl); + mem_cpy(dir + SZDIRE, dir, SZDIRE); /* Create ".." entry */ + dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust; + if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0; + st_clust(fs, dir + SZDIRE, pcl); + } + for (n = fs->csize; n; n--) { /* Write dot entries and clear following sectors */ + fs->winsect = dsc++; + fs->wflag = 1; + res = sync_window(fs); + if (res != FR_OK) break; + mem_set(dir, 0, SS(fs)); + } + } + if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ + if (res == FR_OK) { +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* Initialize directory entry block */ + st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Created time */ + st_dword(fs->dirbuf + XDIR_FstClus, dcl); /* Table start cluster */ + st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)dj.obj.objsize); /* File size needs to be valid */ + st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)dj.obj.objsize); + fs->dirbuf[XDIR_GenFlags] = 3; /* Initialize the object flag (contiguous) */ + fs->dirbuf[XDIR_Attr] = AM_DIR; /* Attribute */ + res = store_xdir(&dj); + } else +#endif + { + dir = dj.dir; + st_dword(dir + DIR_ModTime, tm); /* Created time */ + st_clust(fs, dir, dcl); /* Table start cluster */ + dir[DIR_Attr] = AM_DIR; /* Attribute */ + fs->wflag = 1; + } + if (res == FR_OK) res = sync_fs(fs); + } else { + remove_chain(&dj.obj, dcl, 0); /* Could not register, remove cluster chain */ + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename a File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const TCHAR* path_old, /* Pointer to the object name to be renamed */ + const TCHAR* path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR djo, djn; + FATFS *fs; + BYTE buf[_FS_EXFAT ? SZDIRE * 2 : 24], *dir; + DWORD dw; + DEF_NAMBUF + + + get_ldnumber(&path_new); /* Ignore drive number of new name */ + res = find_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */ + if (res == FR_OK) { + djo.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&djo, path_old); /* Check old object */ + if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check validity of name */ +#if _FS_LOCK != 0 + if (res == FR_OK) res = chk_lock(&djo, 2); +#endif + if (res == FR_OK) { /* Object to be renamed is found */ +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* At exFAT */ + BYTE nf, nn; + WORD nh; + + mem_cpy(buf, fs->dirbuf, SZDIRE * 2); /* Save 85+C0 entry of old object */ + mem_cpy(&djn, &djo, sizeof djo); + res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ + if (res == FR_OK) { /* Is new name already in use by any other object? */ + res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; + } + if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName]; + nh = ld_word(fs->dirbuf + XDIR_NameHash); + mem_cpy(fs->dirbuf, buf, SZDIRE * 2); + fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn; + st_word(fs->dirbuf + XDIR_NameHash, nh); +/* Start of critical section where any interruption can cause a cross-link */ + res = store_xdir(&djn); + } + } + } else +#endif + { /* At FAT12/FAT16/FAT32 */ + mem_cpy(buf, djo.dir + DIR_Attr, 21); /* Save information about the object except name */ + mem_cpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */ + res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ + if (res == FR_OK) { /* Is new name already in use by any other object? */ + res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; + } + if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + dir = djn.dir; /* Copy information about object except name */ + mem_cpy(dir + 13, buf + 2, 19); + dir[DIR_Attr] = buf[0] | AM_ARC; + fs->wflag = 1; + if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the sub-directory if needed */ + dw = clust2sect(fs, ld_clust(fs, dir)); + if (!dw) { + res = FR_INT_ERR; + } else { +/* Start of critical section where any interruption can cause a cross-link */ + res = move_window(fs, dw); + dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */ + if (res == FR_OK && dir[1] == '.') { + st_clust(fs, dir, djn.obj.sclust); + fs->wflag = 1; + } + } + } + } + } + } + if (res == FR_OK) { + res = dir_remove(&djo); /* Remove old entry */ + if (res == FR_OK) { + res = sync_fs(fs); + } + } +/* End of critical section */ + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + +#endif /* !_FS_READONLY */ +#endif /* _FS_MINIMIZE == 0 */ +#endif /* _FS_MINIMIZE <= 1 */ +#endif /* _FS_MINIMIZE <= 2 */ + + + +#if _USE_CHMOD && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Change Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const TCHAR* path, /* Pointer to the file path */ + BYTE attr, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + DEF_NAMBUF + + + res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */ + dj.obj.fs = fs; + if (res == FR_OK) { + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ + if (res == FR_OK) { + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + res = store_xdir(&dj); + } else +#endif + { + dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + fs->wflag = 1; + } + if (res == FR_OK) res = sync_fs(fs); + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const TCHAR* path, /* Pointer to the file/directory name */ + const FILINFO* fno /* Pointer to the time stamp to be set */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + DEF_NAMBUF + + + res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */ + dj.obj.fs = fs; + if (res == FR_OK) { + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ + if (res == FR_OK) { +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); + res = store_xdir(&dj); + } else +#endif + { + st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); + fs->wflag = 1; + } + if (res == FR_OK) res = sync_fs(fs); + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + +#endif /* _USE_CHMOD && !_FS_READONLY */ + + + +#if _USE_LABEL +/*-----------------------------------------------------------------------*/ +/* Get Volume Label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getlabel ( + const TCHAR* path, /* Path name of the logical drive number */ + TCHAR* label, /* Pointer to a buffer to return the volume label */ + DWORD* vsn /* Pointer to a variable to return the volume serial number */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + UINT si, di; +#if _LFN_UNICODE || _FS_EXFAT + WCHAR w; +#endif + + /* Get logical drive */ + res = find_volume(&path, &fs, 0); + + /* Get volume label */ + if (res == FR_OK && label) { + dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = dir_read(&dj, 1); /* Find a volume label entry */ + if (res == FR_OK) { +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + for (si = di = 0; si < dj.dir[XDIR_NumLabel]; si++) { /* Extract volume label from 83 entry */ + w = ld_word(dj.dir + XDIR_Label + si * 2); +#if _LFN_UNICODE + label[di++] = w; +#else + w = ff_convert(w, 0); /* Unicode -> OEM */ + if (w == 0) w = '?'; /* Replace wrong character */ + if (_DF1S && w >= 0x100) label[di++] = (char)(w >> 8); + label[di++] = (char)w; +#endif + } + label[di] = 0; + } else +#endif + { + si = di = 0; /* Extract volume label from AM_VOL entry with code comversion */ + do { +#if _LFN_UNICODE + w = (si < 11) ? dj.dir[si++] : ' '; + if (IsDBCS1(w) && si < 11 && IsDBCS2(dj.dir[si])) { + w = w << 8 | dj.dir[si++]; + } + label[di++] = ff_convert(w, 1); /* OEM -> Unicode */ +#else + label[di++] = dj.dir[si++]; +#endif + } while (di < 11); + do { /* Truncate trailing spaces */ + label[di] = 0; + if (di == 0) break; + } while (label[--di] == ' '); + } + } + } + if (res == FR_NO_FILE) { /* No label entry and return nul string */ + label[0] = 0; + res = FR_OK; + } + } + + /* Get volume serial number */ + if (res == FR_OK && vsn) { + res = move_window(fs, fs->volbase); + if (res == FR_OK) { + switch (fs->fs_type) { + case FS_EXFAT: di = BPB_VolIDEx; break; + case FS_FAT32: di = BS_VolID32; break; + default: di = BS_VolID; + } + *vsn = ld_dword(fs->win + di); + } + } + + LEAVE_FF(fs, res); +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Set Volume Label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_setlabel ( + const TCHAR* label /* Pointer to the volume label to set */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + BYTE dirvn[22]; + UINT i, j, slen; + WCHAR w; + static const char badchr[] = "\"*+,.:;<=>\?[]|\x7F"; + + + /* Get logical drive */ + res = find_volume(&label, &fs, FA_WRITE); + if (res != FR_OK) LEAVE_FF(fs, res); + dj.obj.fs = fs; + + /* Get length of given volume label */ + for (slen = 0; (UINT)label[slen] >= ' '; slen++) ; /* Get name length */ + +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + for (i = j = 0; i < slen; ) { /* Create volume label in directory form */ + w = label[i++]; +#if !_LFN_UNICODE + if (IsDBCS1(w)) { + w = (i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0; + } + w = ff_convert(w, 1); +#endif + if (w == 0 || chk_chr(badchr, w) || j == 22) { /* Check validity check validity of the volume label */ + LEAVE_FF(fs, FR_INVALID_NAME); + } + st_word(dirvn + j, w); j += 2; + } + slen = j; + } else +#endif + { /* On the FAT12/16/32 volume */ + for ( ; slen && label[slen - 1] == ' '; slen--) ; /* Remove trailing spaces */ + if (slen) { /* Is there a volume label to be set? */ + dirvn[0] = 0; i = j = 0; /* Create volume label in directory form */ + do { +#if _LFN_UNICODE + w = ff_convert(ff_wtoupper(label[i++]), 0); +#else + w = (BYTE)label[i++]; + if (IsDBCS1(w)) { + w = (j < 10 && i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0; + } +#if _USE_LFN != 0 + w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0); +#else + if (IsLower(w)) w -= 0x20; /* To upper ASCII characters */ +#ifdef _EXCVT + if (w >= 0x80) w = ExCvt[w - 0x80]; /* To upper extended characters (SBCS cfg) */ +#else + if (!_DF1S && w >= 0x80) w = 0; /* Reject extended characters (ASCII cfg) */ +#endif +#endif +#endif + if (w == 0 || chk_chr(badchr, w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) { /* Reject invalid characters for volume label */ + LEAVE_FF(fs, FR_INVALID_NAME); + } + if (w >= 0x100) dirvn[j++] = (BYTE)(w >> 8); + dirvn[j++] = (BYTE)w; + } while (i < slen); + while (j < 11) dirvn[j++] = ' '; /* Fill remaining name field */ + if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME); /* Reject illegal name (heading DDEM) */ + } + } + + /* Set volume label */ + dj.obj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = dir_read(&dj, 1); /* Get volume label entry */ + if (res == FR_OK) { + if (_FS_EXFAT && fs->fs_type == FS_EXFAT) { + dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2); /* Change the volume label */ + mem_cpy(dj.dir + XDIR_Label, dirvn, slen); + } else { + if (slen) { + mem_cpy(dj.dir, dirvn, 11); /* Change the volume label */ + } else { + dj.dir[DIR_Name] = DDEM; /* Remove the volume label */ + } + } + fs->wflag = 1; + res = sync_fs(fs); + } else { /* No volume label entry is found or error */ + if (res == FR_NO_FILE) { + res = FR_OK; + if (slen) { /* Create a volume label entry */ + res = dir_alloc(&dj, 1); /* Allocate an entry */ + if (res == FR_OK) { + mem_set(dj.dir, 0, SZDIRE); /* Clear the entry */ + if (_FS_EXFAT && fs->fs_type == FS_EXFAT) { + dj.dir[XDIR_Type] = 0x83; /* Create 83 entry */ + dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2); + mem_cpy(dj.dir + XDIR_Label, dirvn, slen); + } else { + dj.dir[DIR_Attr] = AM_VOL; /* Create volume label entry */ + mem_cpy(dj.dir, dirvn, 11); + } + fs->wflag = 1; + res = sync_fs(fs); + } + } + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_LABEL */ + + + +#if _USE_EXPAND && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Allocate a Contiguous Blocks to the File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_expand ( + FIL* fp, /* Pointer to the file object */ + FSIZE_t fsz, /* File size to be expanded to */ + BYTE opt /* Operation mode 0:Find and prepare or 1:Find and allocate */ +) +{ + FRESULT res; + FATFS *fs; + DWORD n, clst, stcl, scl, ncl, tcl, lclst; + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); +#if _FS_EXFAT + if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED); /* Check if in size limit */ +#endif + n = (DWORD)fs->csize * SS(fs); /* Cluster size */ + tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0); /* Number of clusters required */ + stcl = fs->last_clst; lclst = 0; + if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2; + +#if _FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + scl = find_bitmap(fs, stcl, tcl); /* Find a contiguous cluster block */ + if (scl == 0) res = FR_DENIED; /* No contiguous cluster block was found */ + if (scl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) { + if (opt) { + res = change_bitmap(fs, scl, tcl, 1); /* Mark the cluster block 'in use' */ + lclst = scl + tcl - 1; + } else { + lclst = scl - 1; + } + } + } else +#endif + { + scl = clst = stcl; ncl = 0; + for (;;) { /* Find a contiguous cluster block */ + n = get_fat(&fp->obj, clst); + if (++clst >= fs->n_fatent) clst = 2; + if (n == 1) { res = FR_INT_ERR; break; } + if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + if (n == 0) { /* Is it a free cluster? */ + if (++ncl == tcl) break; /* Break if a contiguous cluster block is found */ + } else { + scl = clst; ncl = 0; /* Not a free cluster */ + } + if (clst == stcl) { res = FR_DENIED; break; } /* No contiguous cluster? */ + } + if (res == FR_OK) { + if (opt) { + for (clst = scl, n = tcl; n; clst++, n--) { /* Create a cluster chain on the FAT */ + res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1); + if (res != FR_OK) break; + lclst = clst; + } + } else { + lclst = scl - 1; + } + } + } + + if (res == FR_OK) { + fs->last_clst = lclst; /* Set suggested start cluster to start next */ + if (opt) { + fp->obj.sclust = scl; /* Update object allocation information */ + fp->obj.objsize = fsz; + if (_FS_EXFAT) fp->obj.stat = 2; /* Set status 'contiguous chain' */ + fp->flag |= FA_MODIFIED; + if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */ + fs->free_clst -= tcl; + fs->fsi_flag |= 1; + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* _USE_EXPAND && !_FS_READONLY */ + + + +#if _USE_FORWARD +/*-----------------------------------------------------------------------*/ +/* Forward data to the stream directly */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_forward ( + FIL* fp, /* Pointer to the file object */ + UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + UINT btf, /* Number of bytes to forward */ + UINT* bf /* Pointer to number of bytes forwarded */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst, sect; + FSIZE_t remain; + UINT rcnt, csect; + BYTE *dbuf; + + + *bf = 0; /* Clear transfer byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + remain = fp->obj.objsize - fp->fptr; + if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ + + for ( ; btf && (*func)(0, 0); /* Repeat until all data transferred or stream goes busy */ + fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { + csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + if (csect == 0) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->obj.sclust : get_fat(&fp->obj, fp->clust); + if (clst <= 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + } + sect = clust2sect(fs, fp->clust); /* Get current data sector */ + if (!sect) ABORT(fs, FR_INT_ERR); + sect += csect; +#if _FS_TINY + if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window to the file data */ + dbuf = fs->win; +#else + if (fp->sect != sect) { /* Fill sector cache with file data */ +#if !_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + } + dbuf = fp->buf; +#endif + fp->sect = sect; + rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ + if (rcnt > btf) rcnt = btf; /* Clip it by btr if needed */ + rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt); /* Forward the file data */ + if (!rcnt) ABORT(fs, FR_INT_ERR); + } + + LEAVE_FF(fs, FR_OK); +} +#endif /* _USE_FORWARD */ + + + +#if _USE_MKFS && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Create FAT file system on the logical drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkfs ( + const TCHAR* path, /* Logical drive number */ + BYTE opt, /* Format option */ + DWORD au, /* Size of allocation unit [byte] */ + void* work, /* Pointer to working buffer */ + UINT len /* Size of working buffer */ +) +{ + const UINT n_fats = 1; /* Number of FATs for FAT12/16/32 volume (1 or 2) */ + const UINT n_rootdir = 512; /* Number of root directory entries for FAT12/16 volume */ + static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0}; /* Cluster size boundary for FAT12/16 volume (4Ks unit) */ + static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0}; /* Cluster size boundary for FAT32 volume (128Ks unit) */ + BYTE fmt, sys, *buf, *pte, pdrv, part; + WORD ss; + DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n; + DWORD b_vol, b_fat, b_data; /* Base LBA for volume, fat, data */ + DWORD sz_vol, sz_rsv, sz_fat, sz_dir; /* Size for volume, fat, dir, data */ + UINT i; + int vol; + DSTATUS stat; +#if _USE_TRIM || _FS_EXFAT + DWORD tbl[3]; +#endif + + + /* Check mounted drive and clear work area */ + vol = get_ldnumber(&path); /* Get target logical drive */ + if (vol < 0) return FR_INVALID_DRIVE; + if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear mounted volume */ + pdrv = LD2PD(vol); /* Physical drive */ + part = LD2PT(vol); /* Partition (0:create as new, 1-4:get from partition table) */ + + /* Check physical drive status */ + stat = disk_initialize(pdrv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & (sz_blk - 1))) sz_blk = 1; /* Erase block to align data area */ +#if _MAX_SS != _MIN_SS /* Get sector size of the medium */ + if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; + if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; +#else + ss = _MAX_SS; +#endif + if ((au != 0 && au < ss) || au > 0x1000000 || (au & (au - 1))) return FR_INVALID_PARAMETER; /* Check if au is valid */ + au /= ss; /* Cluster size in unit of sector */ + + /* Get working buffer */ + buf = (BYTE*)work; /* Working buffer */ + sz_buf = len / ss; /* Size of working buffer (sector) */ + szb_buf = sz_buf * ss; /* Size of working buffer (byte) */ + if (!szb_buf) return FR_MKFS_ABORTED; + + /* Determine where the volume to be located (b_vol, sz_vol) */ + if (_MULTI_PARTITION && part != 0) { + /* Get partition information from partition table in the MBR */ + if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Load MBR */ + if (ld_word(buf + BS_55AA) != 0xAA55) return FR_MKFS_ABORTED; /* Check if MBR is valid */ + pte = buf + (MBR_Table + (part - 1) * SZ_PTE); + if (!pte[PTE_System]) return FR_MKFS_ABORTED; /* No partition? */ + b_vol = ld_dword(pte + PTE_StLba); /* Get volume start sector */ + sz_vol = ld_dword(pte + PTE_SizLba); /* Get volume size */ + } else { + /* Create a single-partition in this function */ + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) return FR_DISK_ERR; + b_vol = (opt & FM_SFD) ? 0 : 63; /* Volume start sector */ + if (sz_vol < b_vol) return FR_MKFS_ABORTED; + sz_vol -= b_vol; /* Volume size */ + } + if (sz_vol < 128) return FR_MKFS_ABORTED; /* Check if volume size is >=128s */ + + /* Pre-determine the FAT type */ + do { + if (_FS_EXFAT && (opt & FM_EXFAT)) { /* exFAT possible? */ + if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) { /* exFAT only, vol >= 64Ms or au > 128s ? */ + fmt = FS_EXFAT; break; + } + } + if (au > 128) return FR_INVALID_PARAMETER; /* Too large au for FAT/FAT32 */ + if (opt & FM_FAT32) { /* FAT32 possible? */ + if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) { /* FAT32 only or no-FAT? */ + fmt = FS_FAT32; break; + } + } + if (!(opt & FM_FAT)) return FR_INVALID_PARAMETER; /* no-FAT? */ + fmt = FS_FAT16; + } while (0); + +#if _FS_EXFAT + if (fmt == FS_EXFAT) { /* Create an exFAT volume */ + DWORD szb_bit, szb_case, sum, nb, cl; + WCHAR ch, si; + UINT j, st; + BYTE b; + + if (sz_vol < 0x1000) return FR_MKFS_ABORTED; /* Too small volume? */ +#if _USE_TRIM + tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area can be erased */ + disk_ioctl(pdrv, CTRL_TRIM, tbl); +#endif + /* Determine FAT location, data location and number of clusters */ + if (!au) { /* au auto-selection */ + au = 8; + if (sz_vol >= 0x80000) au = 64; /* >= 512Ks */ + if (sz_vol >= 0x4000000) au = 256; /* >= 64Ms */ + } + b_fat = b_vol + 32; /* FAT start at offset 32 */ + sz_fat = ((sz_vol / au + 2) * 4 + ss - 1) / ss; /* Number of FAT sectors */ + b_data = (b_fat + sz_fat + sz_blk - 1) & ~(sz_blk - 1); /* Align data area to the erase block boundary */ + if (b_data >= sz_vol / 2) return FR_MKFS_ABORTED; /* Too small volume? */ + n_clst = (sz_vol - (b_data - b_vol)) / au; /* Number of clusters */ + if (n_clst <16) return FR_MKFS_ABORTED; /* Too few clusters? */ + if (n_clst > MAX_EXFAT) return FR_MKFS_ABORTED; /* Too many clusters? */ + + szb_bit = (n_clst + 7) / 8; /* Size of allocation bitmap */ + tbl[0] = (szb_bit + au * ss - 1) / (au * ss); /* Number of allocation bitmap clusters */ + + /* Create a compressed up-case table */ + sect = b_data + au * tbl[0]; /* Table start sector */ + sum = 0; /* Table checksum to be stored in the 82 entry */ + st = si = i = j = szb_case = 0; + do { + switch (st) { + case 0: + ch = ff_wtoupper(si); /* Get an up-case char */ + if (ch != si) { + si++; break; /* Store the up-case char if exist */ + } + for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ; /* Get run length of no-case block */ + if (j >= 128) { + ch = 0xFFFF; st = 2; break; /* Compress the no-case block if run is >= 128 */ + } + st = 1; /* Do not compress short run */ + /* continue */ + case 1: + ch = si++; /* Fill the short run */ + if (--j == 0) st = 0; + break; + default: + ch = (WCHAR)j; si += j; /* Number of chars to skip */ + st = 0; + } + sum = xsum32(buf[i + 0] = (BYTE)ch, sum); /* Put it into the write buffer */ + sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum); + i += 2; szb_case += 2; + if (!si || i == szb_buf) { /* Write buffered data when buffer full or end of process */ + n = (i + ss - 1) / ss; + if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; + sect += n; i = 0; + } + } while (si); + tbl[1] = (szb_case + au * ss - 1) / (au * ss); /* Number of up-case table clusters */ + tbl[2] = 1; /* Number of root dir clusters */ + + /* Initialize the allocation bitmap */ + sect = b_data; nsect = (szb_bit + ss - 1) / ss; /* Start of bitmap and number of sectors */ + nb = tbl[0] + tbl[1] + tbl[2]; /* Number of clusters in-use by system */ + do { + mem_set(buf, 0, szb_buf); + for (i = 0; nb >= 8 && i < szb_buf; buf[i++] = 0xFF, nb -= 8) ; + for (b = 1; nb && i < szb_buf; buf[i] |= b, b <<= 1, nb--) ; + n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ + if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; + sect += n; nsect -= n; + } while (nsect); + + /* Initialize the FAT */ + sect = b_fat; nsect = sz_fat; /* Start of FAT and number of FAT sectors */ + j = nb = cl = 0; + do { + mem_set(buf, 0, szb_buf); i = 0; /* Clear work area and reset write index */ + if (cl == 0) { /* Set entry 0 and 1 */ + st_dword(buf + i, 0xFFFFFFF8); i += 4; cl++; + st_dword(buf + i, 0xFFFFFFFF); i += 4; cl++; + } + do { /* Create chains of bitmap, up-case and root dir */ + while (nb && i < szb_buf) { /* Create a chain */ + st_dword(buf + i, (nb > 1) ? cl + 1 : 0xFFFFFFFF); + i += 4; cl++; nb--; + } + if (!nb && j < 3) nb = tbl[j++]; /* Next chain */ + } while (nb && i < szb_buf); + n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ + if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; + sect += n; nsect -= n; + } while (nsect); + + /* Initialize the root directory */ + mem_set(buf, 0, szb_buf); + buf[SZDIRE * 0 + 0] = 0x83; /* 83 entry (volume label) */ + buf[SZDIRE * 1 + 0] = 0x81; /* 81 entry (allocation bitmap) */ + st_dword(buf + SZDIRE * 1 + 20, 2); + st_dword(buf + SZDIRE * 1 + 24, szb_bit); + buf[SZDIRE * 2 + 0] = 0x82; /* 82 entry (up-case table) */ + st_dword(buf + SZDIRE * 2 + 4, sum); + st_dword(buf + SZDIRE * 2 + 20, 2 + tbl[0]); + st_dword(buf + SZDIRE * 2 + 24, szb_case); + sect = b_data + au * (tbl[0] + tbl[1]); nsect = au; /* Start of the root directory and number of sectors */ + do { /* Fill root directory sectors */ + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; + mem_set(buf, 0, ss); + sect += n; nsect -= n; + } while (nsect); + + /* Create two set of the exFAT VBR blocks */ + sect = b_vol; + for (n = 0; n < 2; n++) { + /* Main record (+0) */ + mem_set(buf, 0, ss); + mem_cpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11); /* Boot jump code (x86), OEM name */ + st_dword(buf + BPB_VolOfsEx, b_vol); /* Volume offset in the physical drive [sector] */ + st_dword(buf + BPB_TotSecEx, sz_vol); /* Volume size [sector] */ + st_dword(buf + BPB_FatOfsEx, b_fat - b_vol); /* FAT offset [sector] */ + st_dword(buf + BPB_FatSzEx, sz_fat); /* FAT size [sector] */ + st_dword(buf + BPB_DataOfsEx, b_data - b_vol); /* Data offset [sector] */ + st_dword(buf + BPB_NumClusEx, n_clst); /* Number of clusters */ + st_dword(buf + BPB_RootClusEx, 2 + tbl[0] + tbl[1]); /* Root dir cluster # */ + st_dword(buf + BPB_VolIDEx, GET_FATTIME()); /* VSN */ + st_word(buf + BPB_FSVerEx, 0x100); /* File system version (1.00) */ + for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ; /* Log2 of sector size [byte] */ + for (buf[BPB_SecPerClusEx] = 0, i = au; i >>= 1; buf[BPB_SecPerClusEx]++) ; /* Log2 of cluster size [sector] */ + buf[BPB_NumFATsEx] = 1; /* Number of FATs */ + buf[BPB_DrvNumEx] = 0x80; /* Drive number (for int13) */ + st_word(buf + BS_BootCodeEx, 0xFEEB); /* Boot code (x86) */ + st_word(buf + BS_55AA, 0xAA55); /* Signature (placed here regardless of sector size) */ + for (i = sum = 0; i < ss; i++) { /* VBR checksum */ + if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum); + } + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; + /* Extended bootstrap record (+1..+8) */ + mem_set(buf, 0, ss); + st_word(buf + ss - 2, 0xAA55); /* Signature (placed at end of sector) */ + for (j = 1; j < 9; j++) { + for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; + } + /* OEM/Reserved record (+9..+10) */ + mem_set(buf, 0, ss); + for ( ; j < 11; j++) { + for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; + } + /* Sum record (+11) */ + for (i = 0; i < ss; i += 4) st_dword(buf + i, sum); /* Fill with checksum value */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; + } + + } else +#endif /* _FS_EXFAT */ + { /* Create an FAT12/16/32 volume */ + do { + pau = au; + /* Pre-determine number of clusters and FAT sub-type */ + if (fmt == FS_FAT32) { /* FAT32 volume */ + if (!pau) { /* au auto-selection */ + n = sz_vol / 0x20000; /* Volume size in unit of 128KS */ + for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ; /* Get from table */ + } + n_clst = sz_vol / pau; /* Number of clusters */ + sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */ + sz_rsv = 32; /* Number of reserved sectors */ + sz_dir = 0; /* No static directory */ + if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) return FR_MKFS_ABORTED; + } else { /* FAT12/16 volume */ + if (!pau) { /* au auto-selection */ + n = sz_vol / 0x1000; /* Volume size in unit of 4KS */ + for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */ + } + n_clst = sz_vol / pau; + if (n_clst > MAX_FAT12) { + n = n_clst * 2 + 4; /* FAT size [byte] */ + } else { + fmt = FS_FAT12; + n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */ + } + sz_fat = (n + ss - 1) / ss; /* FAT size [sector] */ + sz_rsv = 1; /* Number of reserved sectors */ + sz_dir = (DWORD)n_rootdir * SZDIRE / ss; /* Rootdir size [sector] */ + } + b_fat = b_vol + sz_rsv; /* FAT base */ + b_data = b_fat + sz_fat * n_fats + sz_dir; /* Data base */ + + /* Align data base to erase block boundary (for flash memory media) */ + n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data; /* Next nearest erase block from current data base */ + if (fmt == FS_FAT32) { /* FAT32: Move FAT base */ + sz_rsv += n; b_fat += n; + } else { /* FAT12/16: Expand FAT size */ + sz_fat += n / n_fats; + } + + /* Determine number of clusters and final check of validity of the FAT sub-type */ + if (sz_vol < b_data + pau * 16 - b_vol) return FR_MKFS_ABORTED; /* Too small volume */ + n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau; + if (fmt == FS_FAT32) { + if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32 */ + if (!au && (au = pau / 2) != 0) continue; /* Adjust cluster size and retry */ + return FR_MKFS_ABORTED; + } + } + if (fmt == FS_FAT16) { + if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */ + if (!au && (pau * 2) <= 64) { + au = pau * 2; continue; /* Adjust cluster size and retry */ + } + if ((opt & FM_FAT32)) { + fmt = FS_FAT32; continue; /* Switch type to FAT32 and retry */ + } + if (!au && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ + return FR_MKFS_ABORTED; + } + if (n_clst <= MAX_FAT12) { /* Too few clusters for FAT16 */ + if (!au && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ + return FR_MKFS_ABORTED; + } + } + if (fmt == FS_FAT12 && n_clst > MAX_FAT12) return FR_MKFS_ABORTED; /* Too many clusters for FAT12 */ + + /* Ok, it is the valid cluster configuration */ + break; + } while (1); + +#if _USE_TRIM + tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area can be erased */ + disk_ioctl(pdrv, CTRL_TRIM, tbl); +#endif + /* Create FAT VBR */ + mem_set(buf, 0, ss); + mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */ + st_word(buf + BPB_BytsPerSec, ss); /* Sector size [byte] */ + buf[BPB_SecPerClus] = (BYTE)pau; /* Cluster size [sector] */ + st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv); /* Size of reserved area */ + buf[BPB_NumFATs] = (BYTE)n_fats; /* Number of FATs */ + st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir)); /* Number of root directory entries */ + if (sz_vol < 0x10000) { + st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */ + } else { + st_dword(buf + BPB_TotSec32, sz_vol); /* Volume size in 32-bit LBA */ + } + buf[BPB_Media] = 0xF8; /* Media descriptor byte */ + st_word(buf + BPB_SecPerTrk, 63); /* Number of sectors per track (for int13) */ + st_word(buf + BPB_NumHeads, 255); /* Number of heads (for int13) */ + st_dword(buf + BPB_HiddSec, b_vol); /* Volume offset in the physical drive [sector] */ + if (fmt == FS_FAT32) { + st_dword(buf + BS_VolID32, GET_FATTIME()); /* VSN */ + st_dword(buf + BPB_FATSz32, sz_fat); /* FAT size [sector] */ + st_dword(buf + BPB_RootClus32, 2); /* Root directory cluster # (2) */ + st_word(buf + BPB_FSInfo32, 1); /* Offset of FSINFO sector (VBR + 1) */ + st_word(buf + BPB_BkBootSec32, 6); /* Offset of backup VBR (VBR + 6) */ + buf[BS_DrvNum32] = 0x80; /* Drive number (for int13) */ + buf[BS_BootSig32] = 0x29; /* Extended boot signature */ + mem_cpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ + } else { + st_dword(buf + BS_VolID, GET_FATTIME()); /* VSN */ + st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */ + buf[BS_DrvNum] = 0x80; /* Drive number (for int13) */ + buf[BS_BootSig] = 0x29; /* Extended boot signature */ + mem_cpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ + } + st_word(buf + BS_55AA, 0xAA55); /* Signature (offset is fixed here regardless of sector size) */ + if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the VBR sector */ + + /* Create FSINFO record if needed */ + if (fmt == FS_FAT32) { + disk_write(pdrv, buf, b_vol + 6, 1); /* Write backup VBR (VBR + 6) */ + mem_set(buf, 0, ss); + st_dword(buf + FSI_LeadSig, 0x41615252); + st_dword(buf + FSI_StrucSig, 0x61417272); + st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */ + st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */ + st_word(buf + BS_55AA, 0xAA55); + disk_write(pdrv, buf, b_vol + 7, 1); /* Write backup FSINFO (VBR + 7) */ + disk_write(pdrv, buf, b_vol + 1, 1); /* Write original FSINFO (VBR + 1) */ + } + + /* Initialize FAT area */ + mem_set(buf, 0, (UINT)szb_buf); + sect = b_fat; /* FAT start sector */ + for (i = 0; i < n_fats; i++) { /* Initialize FATs each */ + if (fmt == FS_FAT32) { + st_dword(buf + 0, 0xFFFFFFF8); /* Entry 0 */ + st_dword(buf + 4, 0xFFFFFFFF); /* Entry 1 */ + st_dword(buf + 8, 0x0FFFFFFF); /* Entry 2 (root directory) */ + } else { + st_dword(buf + 0, (fmt == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8); /* Entry 0 and 1 */ + } + nsect = sz_fat; /* Number of FAT sectors */ + do { /* Fill FAT sectors */ + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR; + mem_set(buf, 0, ss); + sect += n; nsect -= n; + } while (nsect); + } + + /* Initialize root directory (fill with zero) */ + nsect = (fmt == FS_FAT32) ? pau : sz_dir; /* Number of root directory sectors */ + do { + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR; + sect += n; nsect -= n; + } while (nsect); + } + + /* Determine system ID in the partition table */ + if (_FS_EXFAT && fmt == FS_EXFAT) { + sys = 0x07; /* HPFS/NTFS/exFAT */ + } else { + if (fmt == FS_FAT32) { + sys = 0x0C; /* FAT32X */ + } else { + if (sz_vol >= 0x10000) { + sys = 0x06; /* FAT12/16 (>=64KS) */ + } else { + sys = (fmt == FS_FAT16) ? 0x04 : 0x01; /* FAT16 (<64KS) : FAT12 (<64KS) */ + } + } + } + + if (_MULTI_PARTITION && part != 0) { + /* Update system ID in the partition table */ + if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Read the MBR */ + buf[MBR_Table + (part - 1) * SZ_PTE + PTE_System] = sys; /* Set system type */ + if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Write it back to the MBR */ + } else { + if (!(opt & FM_SFD)) { + /* Create partition table in FDISK format */ + mem_set(buf, 0, ss); + st_word(buf + BS_55AA, 0xAA55); /* MBR signature */ + pte = buf + MBR_Table; /* Create partition table for single partition in the drive */ + pte[PTE_Boot] = 0; /* Boot indicator */ + pte[PTE_StHead] = 1; /* Start head */ + pte[PTE_StSec] = 1; /* Start sector */ + pte[PTE_StCyl] = 0; /* Start cylinder */ + pte[PTE_System] = sys; /* System type */ + n = (b_vol + sz_vol) / (63 * 255); /* (End CHS is incorrect) */ + pte[PTE_EdHead] = 254; /* End head */ + pte[PTE_EdSec] = (BYTE)(n >> 2 | 63); /* End sector */ + pte[PTE_EdCyl] = (BYTE)n; /* End cylinder */ + st_dword(pte + PTE_StLba, b_vol); /* Start offset in LBA */ + st_dword(pte + PTE_SizLba, sz_vol); /* Size in sectors */ + if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the MBR */ + } + } + + if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) return FR_DISK_ERR; + + return FR_OK; +} + + + +#if _MULTI_PARTITION +/*-----------------------------------------------------------------------*/ +/* Create partition table on the physical drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_fdisk ( + BYTE pdrv, /* Physical drive number */ + const DWORD* szt, /* Pointer to the size table for each partitions */ + void* work /* Pointer to the working buffer */ +) +{ + UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl; + BYTE s_hd, e_hd, *p, *buf = (BYTE*)work; + DSTATUS stat; + DWORD sz_disk, sz_part, s_part; + + + stat = disk_initialize(pdrv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR; + + /* Determine the CHS without any care of the drive geometry */ + for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ; + if (n == 256) n--; + e_hd = n - 1; + sz_cyl = 63 * n; + tot_cyl = sz_disk / sz_cyl; + + /* Create partition table */ + mem_set(buf, 0, _MAX_SS); + p = buf + MBR_Table; b_cyl = 0; + for (i = 0; i < 4; i++, p += SZ_PTE) { + p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; + if (!p_cyl) continue; + s_part = (DWORD)sz_cyl * b_cyl; + sz_part = (DWORD)sz_cyl * p_cyl; + if (i == 0) { /* Exclude first track of cylinder 0 */ + s_hd = 1; + s_part += 63; sz_part -= 63; + } else { + s_hd = 0; + } + e_cyl = b_cyl + p_cyl - 1; + if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER; + + /* Set partition table */ + p[1] = s_hd; /* Start head */ + p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */ + p[3] = (BYTE)b_cyl; /* Start cylinder */ + p[4] = 0x06; /* System type (temporary setting) */ + p[5] = e_hd; /* End head */ + p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */ + p[7] = (BYTE)e_cyl; /* End cylinder */ + st_dword(p + 8, s_part); /* Start sector in LBA */ + st_dword(p + 12, sz_part); /* Partition size */ + + /* Next partition */ + b_cyl += p_cyl; + } + st_word(p, 0xAA55); + + /* Write it to the MBR */ + return (disk_write(pdrv, buf, 0, 1) != RES_OK || disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) ? FR_DISK_ERR : FR_OK; +} + +#endif /* _MULTI_PARTITION */ +#endif /* _USE_MKFS && !_FS_READONLY */ + + + + +#if _USE_STRFUNC +/*-----------------------------------------------------------------------*/ +/* Get a string from the file */ +/*-----------------------------------------------------------------------*/ + +TCHAR* f_gets ( + TCHAR* buff, /* Pointer to the string buffer to read */ + int len, /* Size of string buffer (characters) */ + FIL* fp /* Pointer to the file object */ +) +{ + int n = 0; + TCHAR c, *p = buff; + BYTE s[2]; + UINT rc; + + + while (n < len - 1) { /* Read characters until buffer gets filled */ +#if _LFN_UNICODE +#if _STRF_ENCODE == 3 /* Read a character in UTF-8 */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = s[0]; + if (c >= 0x80) { + if (c < 0xC0) continue; /* Skip stray trailer */ + if (c < 0xE0) { /* Two-byte sequence */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = (c & 0x1F) << 6 | (s[0] & 0x3F); + if (c < 0x80) c = '?'; + } else { + if (c < 0xF0) { /* Three-byte sequence */ + f_read(fp, s, 2, &rc); + if (rc != 2) break; + c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F); + if (c < 0x800) c = '?'; + } else { /* Reject four-byte sequence */ + c = '?'; + } + } + } +#elif _STRF_ENCODE == 2 /* Read a character in UTF-16BE */ + f_read(fp, s, 2, &rc); + if (rc != 2) break; + c = s[1] + (s[0] << 8); +#elif _STRF_ENCODE == 1 /* Read a character in UTF-16LE */ + f_read(fp, s, 2, &rc); + if (rc != 2) break; + c = s[0] + (s[1] << 8); +#else /* Read a character in ANSI/OEM */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = s[0]; + if (IsDBCS1(c)) { + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = (c << 8) + s[0]; + } + c = ff_convert(c, 1); /* OEM -> Unicode */ + if (!c) c = '?'; +#endif +#else /* Read a character without conversion */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = s[0]; +#endif + if (_USE_STRFUNC == 2 && c == '\r') continue; /* Strip '\r' */ + *p++ = c; + n++; + if (c == '\n') break; /* Break on EOL */ + } + *p = 0; + return n ? buff : 0; /* When no data read (eof or error), return with error. */ +} + + + + +#if !_FS_READONLY +#include +/*-----------------------------------------------------------------------*/ +/* Put a character to the file */ +/*-----------------------------------------------------------------------*/ + +typedef struct { + FIL *fp; /* Ptr to the writing file */ + int idx, nchr; /* Write index of buf[] (-1:error), number of chars written */ + BYTE buf[64]; /* Write buffer */ +} putbuff; + + +static +void putc_bfd ( /* Buffered write with code conversion */ + putbuff* pb, + TCHAR c +) +{ + UINT bw; + int i; + + + if (_USE_STRFUNC == 2 && c == '\n') { /* LF -> CRLF conversion */ + putc_bfd(pb, '\r'); + } + + i = pb->idx; /* Write index of pb->buf[] */ + if (i < 0) return; + +#if _LFN_UNICODE +#if _STRF_ENCODE == 3 /* Write a character in UTF-8 */ + if (c < 0x80) { /* 7-bit */ + pb->buf[i++] = (BYTE)c; + } else { + if (c < 0x800) { /* 11-bit */ + pb->buf[i++] = (BYTE)(0xC0 | c >> 6); + } else { /* 16-bit */ + pb->buf[i++] = (BYTE)(0xE0 | c >> 12); + pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F)); + } + pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F)); + } +#elif _STRF_ENCODE == 2 /* Write a character in UTF-16BE */ + pb->buf[i++] = (BYTE)(c >> 8); + pb->buf[i++] = (BYTE)c; +#elif _STRF_ENCODE == 1 /* Write a character in UTF-16LE */ + pb->buf[i++] = (BYTE)c; + pb->buf[i++] = (BYTE)(c >> 8); +#else /* Write a character in ANSI/OEM */ + c = ff_convert(c, 0); /* Unicode -> OEM */ + if (!c) c = '?'; + if (c >= 0x100) + pb->buf[i++] = (BYTE)(c >> 8); + pb->buf[i++] = (BYTE)c; +#endif +#else /* Write a character without conversion */ + pb->buf[i++] = (BYTE)c; +#endif + + if (i >= (int)(sizeof pb->buf) - 3) { /* Write buffered characters to the file */ + f_write(pb->fp, pb->buf, (UINT)i, &bw); + i = (bw == (UINT)i) ? 0 : -1; + } + pb->idx = i; + pb->nchr++; +} + + +static +int putc_flush ( /* Flush left characters in the buffer */ + putbuff* pb +) +{ + UINT nw; + + if ( pb->idx >= 0 /* Flush buffered characters to the file */ + && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK + && (UINT)pb->idx == nw) return pb->nchr; + return EOF; +} + + +static +void putc_init ( /* Initialize write buffer */ + putbuff* pb, + FIL* fp +) +{ + pb->fp = fp; + pb->nchr = pb->idx = 0; +} + + + +int f_putc ( + TCHAR c, /* A character to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + + + putc_init(&pb, fp); + putc_bfd(&pb, c); /* Put the character */ + return putc_flush(&pb); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a string to the file */ +/*-----------------------------------------------------------------------*/ + +int f_puts ( + const TCHAR* str, /* Pointer to the string to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + + + putc_init(&pb, fp); + while (*str) putc_bfd(&pb, *str++); /* Put the string */ + return putc_flush(&pb); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a formatted string to the file */ +/*-----------------------------------------------------------------------*/ + +int f_printf ( + FIL* fp, /* Pointer to the file object */ + const TCHAR* fmt, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + putbuff pb; + BYTE f, r; + UINT i, j, w; + DWORD v; + TCHAR c, d, str[32], *p; + + + putc_init(&pb, fp); + + va_start(arp, fmt); + + for (;;) { + c = *fmt++; + if (c == 0) break; /* End of string */ + if (c != '%') { /* Non escape character */ + putc_bfd(&pb, c); + continue; + } + w = f = 0; + c = *fmt++; + if (c == '0') { /* Flag: '0' padding */ + f = 1; c = *fmt++; + } else { + if (c == '-') { /* Flag: left justified */ + f = 2; c = *fmt++; + } + } + while (IsDigit(c)) { /* Precision */ + w = w * 10 + c - '0'; + c = *fmt++; + } + if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ + f |= 4; c = *fmt++; + } + if (!c) break; + d = c; + if (IsLower(d)) d -= 0x20; + switch (d) { /* Type is... */ + case 'S' : /* String */ + p = va_arg(arp, TCHAR*); + for (j = 0; p[j]; j++) ; + if (!(f & 2)) { + while (j++ < w) putc_bfd(&pb, ' '); + } + while (*p) putc_bfd(&pb, *p++); + while (j++ < w) putc_bfd(&pb, ' '); + continue; + case 'C' : /* Character */ + putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue; + case 'B' : /* Binary */ + r = 2; break; + case 'O' : /* Octal */ + r = 8; break; + case 'D' : /* Signed decimal */ + case 'U' : /* Unsigned decimal */ + r = 10; break; + case 'X' : /* Hexdecimal */ + r = 16; break; + default: /* Unknown type (pass-through) */ + putc_bfd(&pb, c); continue; + } + + /* Get an argument and put it in numeral */ + v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int)); + if (d == 'D' && (v & 0x80000000)) { + v = 0 - v; + f |= 8; + } + i = 0; + do { + d = (TCHAR)(v % r); v /= r; + if (d > 9) d += (c == 'x') ? 0x27 : 0x07; + str[i++] = d + '0'; + } while (v && i < sizeof str / sizeof str[0]); + if (f & 8) str[i++] = '-'; + j = i; d = (f & 1) ? '0' : ' '; + while (!(f & 2) && j++ < w) putc_bfd(&pb, d); + do putc_bfd(&pb, str[--i]); while (i); + while (j++ < w) putc_bfd(&pb, d); + } + + va_end(arp); + + return putc_flush(&pb); +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_STRFUNC */ diff --git a/radio/src/thirdparty/FatFs/ff.h b/radio/src/thirdparty/FatFs/ff.h index f2be482f7..84ab016ed 100644 --- a/radio/src/thirdparty/FatFs/ff.h +++ b/radio/src/thirdparty/FatFs/ff.h @@ -1,370 +1,370 @@ -/*----------------------------------------------------------------------------/ -/ FatFs - Generic FAT file system module R0.12b / -/-----------------------------------------------------------------------------/ -/ -/ Copyright (C) 2016, ChaN, all right reserved. -/ -/ FatFs module is an open source software. Redistribution and use of FatFs in -/ source and binary forms, with or without modification, are permitted provided -/ that the following condition is met: - -/ 1. Redistributions of source code must retain the above copyright notice, -/ this condition and the following disclaimer. -/ -/ This software is provided by the copyright holder and contributors "AS IS" -/ and any warranties related to this software are DISCLAIMED. -/ The copyright owner or contributors be NOT LIABLE for any damages caused -/ by use of this software. -/----------------------------------------------------------------------------*/ - - -#ifndef _FATFS -#define _FATFS 68020 /* Revision ID */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "integer.h" /* Basic integer types */ -#include "ffconf.h" /* FatFs configuration options */ - -#if _FATFS != _FFCONF -#error Wrong configuration file (ffconf.h). -#endif - - - -/* Definitions of volume management */ - -#if _MULTI_PARTITION /* Multiple partition configuration */ -typedef struct { - BYTE pd; /* Physical drive number */ - BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */ -} PARTITION; -extern PARTITION VolToPart[]; /* Volume - Partition resolution table */ -#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */ -#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */ - -#else /* Single partition configuration */ -#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */ -#define LD2PT(vol) 0 /* Find first valid partition or in SFD */ - -#endif - - - -/* Type of path name strings on FatFs API */ - -#if _LFN_UNICODE /* Unicode (UTF-16) string */ -#if _USE_LFN == 0 -#error _LFN_UNICODE must be 0 at non-LFN cfg. -#endif -#ifndef _INC_TCHAR -typedef WCHAR TCHAR; -#define _T(x) L ## x -#define _TEXT(x) L ## x -#endif -#else /* ANSI/OEM string */ -#ifndef _INC_TCHAR -typedef char TCHAR; -#define _T(x) x -#define _TEXT(x) x -#endif -#endif - - - -/* Type of file size variables */ - -#if _FS_EXFAT -#if _USE_LFN == 0 -#error LFN must be enabled when enable exFAT -#endif -typedef QWORD FSIZE_t; -#else -typedef DWORD FSIZE_t; -#endif - - - -/* File system object structure (FATFS) */ - -typedef struct { - BYTE fs_type; /* File system type (0:N/A) */ - BYTE drv; /* Physical drive number */ - BYTE n_fats; /* Number of FATs (1 or 2) */ - BYTE wflag; /* win[] flag (b0:dirty) */ - BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */ - WORD id; /* File system mount ID */ - WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ - WORD csize; /* Cluster size [sectors] */ -#if _MAX_SS != _MIN_SS - WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */ -#endif -#if _USE_LFN != 0 - WCHAR* lfnbuf; /* LFN working buffer */ -#endif -#if _FS_EXFAT - BYTE* dirbuf; /* Directory entry block scratchpad buffer */ -#endif -#if _FS_REENTRANT - _SYNC_t sobj; /* Identifier of sync object */ -#endif -#if !_FS_READONLY - DWORD last_clst; /* Last allocated cluster */ - DWORD free_clst; /* Number of free clusters */ -#endif -#if _FS_RPATH != 0 - DWORD cdir; /* Current directory start cluster (0:root) */ -#if _FS_EXFAT - DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */ - DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */ - DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */ -#endif -#endif - DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */ - DWORD fsize; /* Size of an FAT [sectors] */ - DWORD volbase; /* Volume base sector */ - DWORD fatbase; /* FAT base sector */ - DWORD dirbase; /* Root directory base sector/cluster */ - DWORD database; /* Data base sector */ - DWORD winsect; /* Current sector appearing in the win[] */ - BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */ -} FATFS; - - - -/* Object ID and allocation information (_FDID) */ - -typedef struct { - FATFS* fs; /* Pointer to the owner file system object */ - WORD id; /* Owner file system mount ID */ - BYTE attr; /* Object attribute */ - BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous (no data on FAT), =3:got flagmented, b2:sub-directory stretched) */ - DWORD sclust; /* Object start cluster (0:no cluster or root directory) */ - FSIZE_t objsize; /* Object size (valid when sclust != 0) */ -#if _FS_EXFAT - DWORD n_cont; /* Size of coutiguous part, clusters - 1 (valid when stat == 3) */ - DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */ - DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */ - DWORD c_ofs; /* Offset in the containing directory (valid when sclust != 0) */ -#endif -#if _FS_LOCK != 0 - UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */ -#endif -} _FDID; - - - -/* File object structure (FIL) */ - -typedef struct { - _FDID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */ - BYTE flag; /* File status flags */ - BYTE err; /* Abort flag (error code) */ - FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */ - DWORD clust; /* Current cluster of fpter (invalid when fprt is 0) */ - DWORD sect; /* Sector number appearing in buf[] (0:invalid) */ -#if !_FS_READONLY - DWORD dir_sect; /* Sector number containing the directory entry */ - BYTE* dir_ptr; /* Pointer to the directory entry in the win[] */ -#endif -#if _USE_FASTSEEK - DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */ -#endif -#if !_FS_TINY - BYTE buf[_MAX_SS]; /* File private data read/write window */ -#endif -} FIL; - - - -/* Directory object structure (DIR) */ - -typedef struct { - _FDID obj; /* Object identifier */ - DWORD dptr; /* Current read/write offset */ - DWORD clust; /* Current cluster */ - DWORD sect; /* Current sector */ - BYTE* dir; /* Pointer to the directory item in the win[] */ - BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */ -#if _USE_LFN != 0 - DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */ -#endif -#if _USE_FIND - const TCHAR* pat; /* Pointer to the name matching pattern */ -#endif -} DIR; - - - -/* File information structure (FILINFO) */ - -typedef struct { - FSIZE_t fsize; /* File size */ - WORD fdate; /* Modified date */ - WORD ftime; /* Modified time */ - BYTE fattrib; /* File attribute */ -#if _USE_LFN != 0 - TCHAR altname[13]; /* Altenative file name */ - TCHAR fname[_MAX_LFN + 1]; /* Primary file name */ -#else - TCHAR fname[13]; /* File name */ -#endif -} FILINFO; - - - -/* File function return code (FRESULT) */ - -typedef enum { - FR_OK = 0, /* (0) Succeeded */ - FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */ - FR_INT_ERR, /* (2) Assertion failed */ - FR_NOT_READY, /* (3) The physical drive cannot work */ - FR_NO_FILE, /* (4) Could not find the file */ - FR_NO_PATH, /* (5) Could not find the path */ - FR_INVALID_NAME, /* (6) The path name format is invalid */ - FR_DENIED, /* (7) Access denied due to prohibited access or directory full */ - FR_EXIST, /* (8) Access denied due to prohibited access */ - FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ - FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ - FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ - FR_NOT_ENABLED, /* (12) The volume has no work area */ - FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */ - FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */ - FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ - FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */ - FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ - FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_LOCK */ - FR_INVALID_PARAMETER /* (19) Given parameter is invalid */ -} FRESULT; - - - -/*--------------------------------------------------------------*/ -/* FatFs module application interface */ - -FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */ -FRESULT f_close (FIL* fp); /* Close an open file object */ -FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */ -FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */ -FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */ -FRESULT f_truncate (FIL* fp); /* Truncate the file */ -FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */ -FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */ -FRESULT f_closedir (DIR* dp); /* Close an open directory */ -FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */ -FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */ -FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */ -FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */ -FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */ -FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */ -FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */ -FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */ -FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */ -FRESULT f_chdir (const TCHAR* path); /* Change current directory */ -FRESULT f_chdrive (const TCHAR* path); /* Change current drive */ -FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */ -FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */ -FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */ -FRESULT f_setlabel (const TCHAR* label); /* Set volume label */ -FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */ -FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */ -FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */ -FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */ -FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */ -int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */ -int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ -int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ -TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ - -#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize)) -#define f_error(fp) ((fp)->err) -#define f_tell(fp) ((fp)->fptr) -#if !defined(SIMU) || defined(SIMU_DISKIO) - #define f_size(fp) ((fp)->obj.objsize) -#else - UINT f_size(FIL* fil); -#endif -#define f_rewind(fp) f_lseek((fp), 0) -#define f_rewinddir(dp) f_readdir((dp), 0) - -#ifndef EOF -#define EOF (-1) -#endif - - - - -/*--------------------------------------------------------------*/ -/* Additional user defined functions */ - -/* RTC function */ -#if !_FS_READONLY && !_FS_NORTC -DWORD get_fattime (void); -#endif - -/* Unicode support functions */ -#if _USE_LFN != 0 /* Unicode - OEM code conversion */ -WCHAR ff_convert (WCHAR chr, UINT dir); /* OEM-Unicode bidirectional conversion */ -WCHAR ff_wtoupper (WCHAR chr); /* Unicode upper-case conversion */ -#if _USE_LFN == 3 /* Memory functions */ -void* ff_memalloc (UINT msize); /* Allocate memory block */ -void ff_memfree (void* mblock); /* Free memory block */ -#endif -#endif - -/* Sync functions */ -#if _FS_REENTRANT -int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj); /* Create a sync object */ -int ff_req_grant (_SYNC_t sobj); /* Lock sync object */ -void ff_rel_grant (_SYNC_t sobj); /* Unlock sync object */ -int ff_del_syncobj (_SYNC_t sobj); /* Delete a sync object */ -#endif - - - - -/*--------------------------------------------------------------*/ -/* Flags and offset address */ - - -/* File access mode and open method flags (3rd argument of f_open) */ -#define FA_READ 0x01 -#define FA_WRITE 0x02 -#define FA_OPEN_EXISTING 0x00 -#define FA_CREATE_NEW 0x04 -#define FA_CREATE_ALWAYS 0x08 -#define FA_OPEN_ALWAYS 0x10 -#define FA_OPEN_APPEND 0x30 - -/* Fast seek controls (2nd argument of f_lseek) */ -#define CREATE_LINKMAP ((FSIZE_t)0 - 1) - -/* Format options (2nd argument of f_mkfs) */ -#define FM_FAT 0x01 -#define FM_FAT32 0x02 -#define FM_EXFAT 0x04 -#define FM_ANY 0x07 -#define FM_SFD 0x08 - -/* Filesystem type (FATFS.fs_type) */ -#define FS_FAT12 1 -#define FS_FAT16 2 -#define FS_FAT32 3 -#define FS_EXFAT 4 - -/* File attribute bits for directory entry (FILINFO.fattrib) */ -#define AM_RDO 0x01 /* Read only */ -#define AM_HID 0x02 /* Hidden */ -#define AM_SYS 0x04 /* System */ -#define AM_DIR 0x10 /* Directory */ -#define AM_ARC 0x20 /* Archive */ - - -#ifdef __cplusplus -} -#endif - -#endif /* _FATFS */ +/*----------------------------------------------------------------------------/ +/ FatFs - Generic FAT file system module R0.12b / +/-----------------------------------------------------------------------------/ +/ +/ Copyright (C) 2016, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: + +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +/----------------------------------------------------------------------------*/ + + +#ifndef _FATFS +#define _FATFS 68020 /* Revision ID */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "integer.h" /* Basic integer types */ +#include "ffconf.h" /* FatFs configuration options */ + +#if _FATFS != _FFCONF +#error Wrong configuration file (ffconf.h). +#endif + + + +/* Definitions of volume management */ + +#if _MULTI_PARTITION /* Multiple partition configuration */ +typedef struct { + BYTE pd; /* Physical drive number */ + BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */ +} PARTITION; +extern PARTITION VolToPart[]; /* Volume - Partition resolution table */ +#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */ +#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */ + +#else /* Single partition configuration */ +#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */ +#define LD2PT(vol) 0 /* Find first valid partition or in SFD */ + +#endif + + + +/* Type of path name strings on FatFs API */ + +#if _LFN_UNICODE /* Unicode (UTF-16) string */ +#if _USE_LFN == 0 +#error _LFN_UNICODE must be 0 at non-LFN cfg. +#endif +#ifndef _INC_TCHAR +typedef WCHAR TCHAR; +#define _T(x) L ## x +#define _TEXT(x) L ## x +#endif +#else /* ANSI/OEM string */ +#ifndef _INC_TCHAR +typedef char TCHAR; +#define _T(x) x +#define _TEXT(x) x +#endif +#endif + + + +/* Type of file size variables */ + +#if _FS_EXFAT +#if _USE_LFN == 0 +#error LFN must be enabled when enable exFAT +#endif +typedef QWORD FSIZE_t; +#else +typedef DWORD FSIZE_t; +#endif + + + +/* File system object structure (FATFS) */ + +typedef struct { + BYTE fs_type; /* File system type (0:N/A) */ + BYTE drv; /* Physical drive number */ + BYTE n_fats; /* Number of FATs (1 or 2) */ + BYTE wflag; /* win[] flag (b0:dirty) */ + BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */ + WORD id; /* File system mount ID */ + WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ + WORD csize; /* Cluster size [sectors] */ +#if _MAX_SS != _MIN_SS + WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */ +#endif +#if _USE_LFN != 0 + WCHAR* lfnbuf; /* LFN working buffer */ +#endif +#if _FS_EXFAT + BYTE* dirbuf; /* Directory entry block scratchpad buffer */ +#endif +#if _FS_REENTRANT + _SYNC_t sobj; /* Identifier of sync object */ +#endif +#if !_FS_READONLY + DWORD last_clst; /* Last allocated cluster */ + DWORD free_clst; /* Number of free clusters */ +#endif +#if _FS_RPATH != 0 + DWORD cdir; /* Current directory start cluster (0:root) */ +#if _FS_EXFAT + DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */ + DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */ + DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */ +#endif +#endif + DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */ + DWORD fsize; /* Size of an FAT [sectors] */ + DWORD volbase; /* Volume base sector */ + DWORD fatbase; /* FAT base sector */ + DWORD dirbase; /* Root directory base sector/cluster */ + DWORD database; /* Data base sector */ + DWORD winsect; /* Current sector appearing in the win[] */ + BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */ +} FATFS; + + + +/* Object ID and allocation information (_FDID) */ + +typedef struct { + FATFS* fs; /* Pointer to the owner file system object */ + WORD id; /* Owner file system mount ID */ + BYTE attr; /* Object attribute */ + BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous (no data on FAT), =3:got flagmented, b2:sub-directory stretched) */ + DWORD sclust; /* Object start cluster (0:no cluster or root directory) */ + FSIZE_t objsize; /* Object size (valid when sclust != 0) */ +#if _FS_EXFAT + DWORD n_cont; /* Size of coutiguous part, clusters - 1 (valid when stat == 3) */ + DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */ + DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */ + DWORD c_ofs; /* Offset in the containing directory (valid when sclust != 0) */ +#endif +#if _FS_LOCK != 0 + UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */ +#endif +} _FDID; + + + +/* File object structure (FIL) */ + +typedef struct { + _FDID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */ + BYTE flag; /* File status flags */ + BYTE err; /* Abort flag (error code) */ + FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */ + DWORD clust; /* Current cluster of fpter (invalid when fprt is 0) */ + DWORD sect; /* Sector number appearing in buf[] (0:invalid) */ +#if !_FS_READONLY + DWORD dir_sect; /* Sector number containing the directory entry */ + BYTE* dir_ptr; /* Pointer to the directory entry in the win[] */ +#endif +#if _USE_FASTSEEK + DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */ +#endif +#if !_FS_TINY + BYTE buf[_MAX_SS]; /* File private data read/write window */ +#endif +} FIL; + + + +/* Directory object structure (DIR) */ + +typedef struct { + _FDID obj; /* Object identifier */ + DWORD dptr; /* Current read/write offset */ + DWORD clust; /* Current cluster */ + DWORD sect; /* Current sector */ + BYTE* dir; /* Pointer to the directory item in the win[] */ + BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */ +#if _USE_LFN != 0 + DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */ +#endif +#if _USE_FIND + const TCHAR* pat; /* Pointer to the name matching pattern */ +#endif +} DIR; + + + +/* File information structure (FILINFO) */ + +typedef struct { + FSIZE_t fsize; /* File size */ + WORD fdate; /* Modified date */ + WORD ftime; /* Modified time */ + BYTE fattrib; /* File attribute */ +#if _USE_LFN != 0 + TCHAR altname[13]; /* Altenative file name */ + TCHAR fname[_MAX_LFN + 1]; /* Primary file name */ +#else + TCHAR fname[13]; /* File name */ +#endif +} FILINFO; + + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* (0) Succeeded */ + FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */ + FR_INT_ERR, /* (2) Assertion failed */ + FR_NOT_READY, /* (3) The physical drive cannot work */ + FR_NO_FILE, /* (4) Could not find the file */ + FR_NO_PATH, /* (5) Could not find the path */ + FR_INVALID_NAME, /* (6) The path name format is invalid */ + FR_DENIED, /* (7) Access denied due to prohibited access or directory full */ + FR_EXIST, /* (8) Access denied due to prohibited access */ + FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ + FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ + FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ + FR_NOT_ENABLED, /* (12) The volume has no work area */ + FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */ + FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */ + FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ + FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */ + FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ + FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_LOCK */ + FR_INVALID_PARAMETER /* (19) Given parameter is invalid */ +} FRESULT; + + + +/*--------------------------------------------------------------*/ +/* FatFs module application interface */ + +FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */ +FRESULT f_close (FIL* fp); /* Close an open file object */ +FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */ +FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */ +FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */ +FRESULT f_truncate (FIL* fp); /* Truncate the file */ +FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */ +FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */ +FRESULT f_closedir (DIR* dp); /* Close an open directory */ +FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */ +FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */ +FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */ +FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */ +FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */ +FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */ +FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */ +FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */ +FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */ +FRESULT f_chdir (const TCHAR* path); /* Change current directory */ +FRESULT f_chdrive (const TCHAR* path); /* Change current drive */ +FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */ +FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */ +FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */ +FRESULT f_setlabel (const TCHAR* label); /* Set volume label */ +FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */ +FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */ +FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */ +FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */ +FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */ +int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */ +int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ +int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ +TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ + +#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize)) +#define f_error(fp) ((fp)->err) +#define f_tell(fp) ((fp)->fptr) +#if !defined(SIMU) || defined(SIMU_DISKIO) + #define f_size(fp) ((fp)->obj.objsize) +#else + UINT f_size(FIL* fil); +#endif +#define f_rewind(fp) f_lseek((fp), 0) +#define f_rewinddir(dp) f_readdir((dp), 0) + +#ifndef EOF +#define EOF (-1) +#endif + + + + +/*--------------------------------------------------------------*/ +/* Additional user defined functions */ + +/* RTC function */ +#if !_FS_READONLY && !_FS_NORTC +DWORD get_fattime (void); +#endif + +/* Unicode support functions */ +#if _USE_LFN != 0 /* Unicode - OEM code conversion */ +WCHAR ff_convert (WCHAR chr, UINT dir); /* OEM-Unicode bidirectional conversion */ +WCHAR ff_wtoupper (WCHAR chr); /* Unicode upper-case conversion */ +#if _USE_LFN == 3 /* Memory functions */ +void* ff_memalloc (UINT msize); /* Allocate memory block */ +void ff_memfree (void* mblock); /* Free memory block */ +#endif +#endif + +/* Sync functions */ +#if _FS_REENTRANT +int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj); /* Create a sync object */ +int ff_req_grant (_SYNC_t sobj); /* Lock sync object */ +void ff_rel_grant (_SYNC_t sobj); /* Unlock sync object */ +int ff_del_syncobj (_SYNC_t sobj); /* Delete a sync object */ +#endif + + + + +/*--------------------------------------------------------------*/ +/* Flags and offset address */ + + +/* File access mode and open method flags (3rd argument of f_open) */ +#define FA_READ 0x01 +#define FA_WRITE 0x02 +#define FA_OPEN_EXISTING 0x00 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA_OPEN_APPEND 0x30 + +/* Fast seek controls (2nd argument of f_lseek) */ +#define CREATE_LINKMAP ((FSIZE_t)0 - 1) + +/* Format options (2nd argument of f_mkfs) */ +#define FM_FAT 0x01 +#define FM_FAT32 0x02 +#define FM_EXFAT 0x04 +#define FM_ANY 0x07 +#define FM_SFD 0x08 + +/* Filesystem type (FATFS.fs_type) */ +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 +#define FS_EXFAT 4 + +/* File attribute bits for directory entry (FILINFO.fattrib) */ +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ + + +#ifdef __cplusplus +} +#endif + +#endif /* _FATFS */ diff --git a/radio/src/thirdparty/FatFs/ffconf.h b/radio/src/thirdparty/FatFs/ffconf.h index e91fe2c2a..fe214d1f1 100644 --- a/radio/src/thirdparty/FatFs/ffconf.h +++ b/radio/src/thirdparty/FatFs/ffconf.h @@ -1,297 +1,297 @@ -/*---------------------------------------------------------------------------/ -/ FatFs - FAT file system module configuration file -/---------------------------------------------------------------------------*/ - -#define _FFCONF 68020 /* Revision ID */ - -#if defined(CPUARM) && !defined(SIMU) -#ifdef __cplusplus -extern "C" { -#endif -#include "../CoOS/kernel/CoOS.h" -#ifdef __cplusplus -} -#endif -#endif - -/*---------------------------------------------------------------------------/ -/ Function Configurations -/---------------------------------------------------------------------------*/ - -#if defined(BOOT) - #define _FS_READONLY 1 -#else - #define _FS_READONLY 0 -#endif -/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) -/ Read-only configuration removes writing API functions, f_write(), f_sync(), -/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() -/ and optional writing functions as well. */ - - -#if defined(BOOT) - #define _FS_MINIMIZE 1 -#else - #define _FS_MINIMIZE 0 -#endif -/* This option defines minimization level to remove some basic API functions. -/ -/ 0: All basic functions are enabled. -/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() -/ are removed. -/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. -/ 3: f_lseek() function is removed in addition to 2. */ - - -#if defined(BOOT) - #define _USE_STRFUNC 0 -#else - #define _USE_STRFUNC 1 -#endif -/* This option switches string functions, f_gets(), f_putc(), f_puts() and -/ f_printf(). -/ -/ 0: Disable string functions. -/ 1: Enable without LF-CRLF conversion. -/ 2: Enable with LF-CRLF conversion. */ - - -#define _USE_FIND 0 -/* This option switches filtered directory read functions, f_findfirst() and -/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ - -#define _USE_MKFS 1 -/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ - - -#define _USE_FASTSEEK 0 -/* This option switches fast seek function. (0:Disable or 1:Enable) */ - - -#define _USE_EXPAND 0 -/* This option switches f_expand function. (0:Disable or 1:Enable) */ - - -#define _USE_CHMOD 1 -/* This option switches attribute manipulation functions, f_chmod() and f_utime(). -/ (0:Disable or 1:Enable) Also _FS_READONLY needs to be 0 to enable this option. */ - - -#define _USE_LABEL 0 -/* This option switches volume label functions, f_getlabel() and f_setlabel(). -/ (0:Disable or 1:Enable) */ - - -#define _USE_FORWARD 0 -/* This option switches f_forward() function. (0:Disable or 1:Enable) */ - - -/*---------------------------------------------------------------------------/ -/ Locale and Namespace Configurations -/---------------------------------------------------------------------------*/ - -#define _CODE_PAGE 437 -/* This option specifies the OEM code page to be used on the target system. -/ Incorrect setting of the code page can cause a file open failure. -/ -/ 1 - ASCII (No extended character. Non-LFN cfg. only) -/ 437 - U.S. -/ 720 - Arabic -/ 737 - Greek -/ 771 - KBL -/ 775 - Baltic -/ 850 - Latin 1 -/ 852 - Latin 2 -/ 855 - Cyrillic -/ 857 - Turkish -/ 860 - Portuguese -/ 861 - Icelandic -/ 862 - Hebrew -/ 863 - Canadian French -/ 864 - Arabic -/ 865 - Nordic -/ 866 - Russian -/ 869 - Greek 2 -/ 932 - Japanese (DBCS) -/ 936 - Simplified Chinese (DBCS) -/ 949 - Korean (DBCS) -/ 950 - Traditional Chinese (DBCS) -*/ - - -#if defined(CPUARM) - #define _USE_LFN 2 - #define _MAX_LFN 255 -#else - #define _USE_LFN 1 - #define _MAX_LFN 32 -#endif -/* The _USE_LFN switches the support of long file name (LFN). -/ -/ 0: Disable support of LFN. _MAX_LFN has no effect. -/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. -/ 2: Enable LFN with dynamic working buffer on the STACK. -/ 3: Enable LFN with dynamic working buffer on the HEAP. -/ -/ To enable the LFN, Unicode handling functions (option/unicode.c) must be added -/ to the project. The working buffer occupies (_MAX_LFN + 1) * 2 bytes and -/ additional 608 bytes at exFAT enabled. _MAX_LFN can be in range from 12 to 255. -/ It should be set 255 to support full featured LFN operations. -/ When use stack for the working buffer, take care on stack overflow. When use heap -/ memory for the working buffer, memory management functions, ff_memalloc() and -/ ff_memfree(), must be added to the project. */ - - -#define _LFN_UNICODE 0 -/* This option switches character encoding on the API. (0:ANSI/OEM or 1:UTF-16) -/ To use Unicode string for the path name, enable LFN and set _LFN_UNICODE = 1. -/ This option also affects behavior of string I/O functions. */ - - -#define _STRF_ENCODE 3 -/* When _LFN_UNICODE == 1, this option selects the character encoding ON THE FILE to -/ be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf(). -/ -/ 0: ANSI/OEM -/ 1: UTF-16LE -/ 2: UTF-16BE -/ 3: UTF-8 -/ -/ This option has no effect when _LFN_UNICODE == 0. */ - - -#define _FS_RPATH 2 -/* This option configures support of relative path. -/ -/ 0: Disable relative path and remove related functions. -/ 1: Enable relative path. f_chdir() and f_chdrive() are available. -/ 2: f_getcwd() function is available in addition to 1. -*/ - - -/*---------------------------------------------------------------------------/ -/ Drive/Volume Configurations -/---------------------------------------------------------------------------*/ - -#define _VOLUMES 1 -/* Number of volumes (logical drives) to be used. */ - - -#define _STR_VOLUME_ID 0 -#define _VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3" -/* _STR_VOLUME_ID switches string support of volume ID. -/ When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive -/ number in the path name. _VOLUME_STRS defines the drive ID strings for each -/ logical drives. Number of items must be equal to _VOLUMES. Valid characters for -/ the drive ID strings are: A-Z and 0-9. */ - - -#define _MULTI_PARTITION 0 -/* This option switches support of multi-partition on a physical drive. -/ By default (0), each logical drive number is bound to the same physical drive -/ number and only an FAT volume found on the physical drive will be mounted. -/ When multi-partition is enabled (1), each logical drive number can be bound to -/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() -/ funciton will be available. */ - - -#define _MIN_SS 512 -#define _MAX_SS 512 -/* These options configure the range of sector size to be supported. (512, 1024, -/ 2048 or 4096) Always set both 512 for most systems, all type of memory cards and -/ harddisk. But a larger value may be required for on-board flash memory and some -/ type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured -/ to variable sector size and GET_SECTOR_SIZE command must be implemented to the -/ disk_ioctl() function. */ - - -#define _USE_TRIM 0 -/* This option switches support of ATA-TRIM. (0:Disable or 1:Enable) -/ To enable Trim function, also CTRL_TRIM command should be implemented to the -/ disk_ioctl() function. */ - - -#define _FS_NOFSINFO 0 -/* If you need to know correct free space on the FAT32 volume, set bit 0 of this -/ option, and f_getfree() function at first time after volume mount will force -/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. -/ -/ bit0=0: Use free cluster count in the FSINFO if available. -/ bit0=1: Do not trust free cluster count in the FSINFO. -/ bit1=0: Use last allocated cluster number in the FSINFO if available. -/ bit1=1: Do not trust last allocated cluster number in the FSINFO. -*/ - - - -/*---------------------------------------------------------------------------/ -/ System Configurations -/---------------------------------------------------------------------------*/ - -#define _FS_TINY 0 -/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) -/ At the tiny configuration, size of file object (FIL) is reduced _MAX_SS bytes. -/ Instead of private sector buffer eliminated from the file object, common sector -/ buffer in the file system object (FATFS) is used for the file data transfer. */ - - -#define _FS_EXFAT 0 -/* This option switches support of exFAT file system. (0:Disable or 1:Enable) -/ When enable exFAT, also LFN needs to be enabled. (_USE_LFN >= 1) -/ Note that enabling exFAT discards C89 compatibility. */ - - -#define _FS_NORTC 0 -#define _NORTC_MON 1 -#define _NORTC_MDAY 1 -#define _NORTC_YEAR 2016 -/* The option _FS_NORTC switches timestamp functiton. If the system does not have -/ any RTC function or valid timestamp is not needed, set _FS_NORTC = 1 to disable -/ the timestamp function. All objects modified by FatFs will have a fixed timestamp -/ defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time. -/ To enable timestamp function (_FS_NORTC = 0), get_fattime() function need to be -/ added to the project to get current time form real-time clock. _NORTC_MON, -/ _NORTC_MDAY and _NORTC_YEAR have no effect. -/ These options have no effect at read-only configuration (_FS_READONLY = 1). */ - - -#define _FS_LOCK 0 -/* The option _FS_LOCK switches file lock function to control duplicated file open -/ and illegal operation to open objects. This option must be 0 when _FS_READONLY -/ is 1. -/ -/ 0: Disable file lock function. To avoid volume corruption, application program -/ should avoid illegal open, remove and rename to the open objects. -/ >0: Enable file lock function. The value defines how many files/sub-directories -/ can be opened simultaneously under file lock control. Note that the file -/ lock control is independent of re-entrancy. */ - -#if defined(CPUARM) && !defined(BOOT) - #define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ - #define _SYNC_t unsigned char /*OS_MutexID*/ /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ -#else - #define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ -#endif - -#define _FS_TIMEOUT 1000 - -/* The option _FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs -/ module itself. Note that regardless of this option, file access to different -/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() -/ and f_fdisk() function, are always not re-entrant. Only file/directory access -/ to the same volume is under control of this function. -/ -/ 0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect. -/ 1: Enable re-entrancy. Also user provided synchronization handlers, -/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() -/ function, must be added to the project. Samples are available in -/ option/syscall.c. -/ -/ The _FS_TIMEOUT defines timeout period in unit of time tick. -/ The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, -/ SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be -/ included somewhere in the scope of ff.h. */ - - - -/*--- End of configuration options ---*/ +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file +/---------------------------------------------------------------------------*/ + +#define _FFCONF 68020 /* Revision ID */ + +#if defined(CPUARM) && !defined(SIMU) +#ifdef __cplusplus +extern "C" { +#endif +#include "../CoOS/kernel/CoOS.h" +#ifdef __cplusplus +} +#endif +#endif + +/*---------------------------------------------------------------------------/ +/ Function Configurations +/---------------------------------------------------------------------------*/ + +#if defined(BOOT) + #define _FS_READONLY 1 +#else + #define _FS_READONLY 0 +#endif +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + + +#if defined(BOOT) + #define _FS_MINIMIZE 1 +#else + #define _FS_MINIMIZE 0 +#endif +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: All basic functions are enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#if defined(BOOT) + #define _USE_STRFUNC 0 +#else + #define _USE_STRFUNC 1 +#endif +/* This option switches string functions, f_gets(), f_putc(), f_puts() and +/ f_printf(). +/ +/ 0: Disable string functions. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. */ + + +#define _USE_FIND 0 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + +#define _USE_MKFS 1 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + + +#define _USE_FASTSEEK 0 +/* This option switches fast seek function. (0:Disable or 1:Enable) */ + + +#define _USE_EXPAND 0 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + + +#define _USE_CHMOD 1 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also _FS_READONLY needs to be 0 to enable this option. */ + + +#define _USE_LABEL 0 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + + +#define _USE_FORWARD 0 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define _CODE_PAGE 437 +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 1 - ASCII (No extended character. Non-LFN cfg. only) +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +*/ + + +#if defined(CPUARM) + #define _USE_LFN 2 + #define _MAX_LFN 255 +#else + #define _USE_LFN 1 + #define _MAX_LFN 32 +#endif +/* The _USE_LFN switches the support of long file name (LFN). +/ +/ 0: Disable support of LFN. _MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, Unicode handling functions (option/unicode.c) must be added +/ to the project. The working buffer occupies (_MAX_LFN + 1) * 2 bytes and +/ additional 608 bytes at exFAT enabled. _MAX_LFN can be in range from 12 to 255. +/ It should be set 255 to support full featured LFN operations. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree(), must be added to the project. */ + + +#define _LFN_UNICODE 0 +/* This option switches character encoding on the API. (0:ANSI/OEM or 1:UTF-16) +/ To use Unicode string for the path name, enable LFN and set _LFN_UNICODE = 1. +/ This option also affects behavior of string I/O functions. */ + + +#define _STRF_ENCODE 3 +/* When _LFN_UNICODE == 1, this option selects the character encoding ON THE FILE to +/ be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf(). +/ +/ 0: ANSI/OEM +/ 1: UTF-16LE +/ 2: UTF-16BE +/ 3: UTF-8 +/ +/ This option has no effect when _LFN_UNICODE == 0. */ + + +#define _FS_RPATH 2 +/* This option configures support of relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _STR_VOLUME_ID 0 +#define _VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3" +/* _STR_VOLUME_ID switches string support of volume ID. +/ When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive +/ number in the path name. _VOLUME_STRS defines the drive ID strings for each +/ logical drives. Number of items must be equal to _VOLUMES. Valid characters for +/ the drive ID strings are: A-Z and 0-9. */ + + +#define _MULTI_PARTITION 0 +/* This option switches support of multi-partition on a physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When multi-partition is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ funciton will be available. */ + + +#define _MIN_SS 512 +#define _MAX_SS 512 +/* These options configure the range of sector size to be supported. (512, 1024, +/ 2048 or 4096) Always set both 512 for most systems, all type of memory cards and +/ harddisk. But a larger value may be required for on-board flash memory and some +/ type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured +/ to variable sector size and GET_SECTOR_SIZE command must be implemented to the +/ disk_ioctl() function. */ + + +#define _USE_TRIM 0 +/* This option switches support of ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + + +#define _FS_NOFSINFO 0 +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define _FS_TINY 0 +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is reduced _MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the file system object (FATFS) is used for the file data transfer. */ + + +#define _FS_EXFAT 0 +/* This option switches support of exFAT file system. (0:Disable or 1:Enable) +/ When enable exFAT, also LFN needs to be enabled. (_USE_LFN >= 1) +/ Note that enabling exFAT discards C89 compatibility. */ + + +#define _FS_NORTC 0 +#define _NORTC_MON 1 +#define _NORTC_MDAY 1 +#define _NORTC_YEAR 2016 +/* The option _FS_NORTC switches timestamp functiton. If the system does not have +/ any RTC function or valid timestamp is not needed, set _FS_NORTC = 1 to disable +/ the timestamp function. All objects modified by FatFs will have a fixed timestamp +/ defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time. +/ To enable timestamp function (_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to get current time form real-time clock. _NORTC_MON, +/ _NORTC_MDAY and _NORTC_YEAR have no effect. +/ These options have no effect at read-only configuration (_FS_READONLY = 1). */ + + +#define _FS_LOCK 0 +/* The option _FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when _FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + +#if defined(CPUARM) && !defined(BOOT) + #define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ + #define _SYNC_t unsigned char /*OS_MutexID*/ /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ +#else + #define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#endif + +#define _FS_TIMEOUT 1000 + +/* The option _FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this function. +/ +/ 0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function, must be added to the project. Samples are available in +/ option/syscall.c. +/ +/ The _FS_TIMEOUT defines timeout period in unit of time tick. +/ The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, +/ SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be +/ included somewhere in the scope of ff.h. */ + + + +/*--- End of configuration options ---*/ diff --git a/radio/src/thirdparty/FatFs/integer.h b/radio/src/thirdparty/FatFs/integer.h index 4660ed624..5dd8ec316 100644 --- a/radio/src/thirdparty/FatFs/integer.h +++ b/radio/src/thirdparty/FatFs/integer.h @@ -1,38 +1,38 @@ -/*-------------------------------------------*/ -/* Integer type definitions for FatFs module */ -/*-------------------------------------------*/ - -#ifndef _FF_INTEGER -#define _FF_INTEGER - -#ifdef _WIN32 /* FatFs development platform */ - -#include -#include -typedef unsigned __int64 QWORD; - - -#else /* Embedded platform */ - -/* These types MUST be 16-bit or 32-bit */ -typedef int INT; -typedef unsigned int UINT; - -/* This type MUST be 8-bit */ -typedef unsigned char BYTE; - -/* These types MUST be 16-bit */ -typedef short SHORT; -typedef unsigned short WORD; -typedef unsigned short WCHAR; - -/* These types MUST be 32-bit */ -typedef long LONG; -typedef unsigned long DWORD; - -/* This type MUST be 64-bit (Remove this for C89 compatibility) */ -typedef unsigned long long QWORD; - -#endif - -#endif +/*-------------------------------------------*/ +/* Integer type definitions for FatFs module */ +/*-------------------------------------------*/ + +#ifndef _FF_INTEGER +#define _FF_INTEGER + +#ifdef _WIN32 /* FatFs development platform */ + +#include +#include +typedef unsigned __int64 QWORD; + + +#else /* Embedded platform */ + +/* These types MUST be 16-bit or 32-bit */ +typedef int INT; +typedef unsigned int UINT; + +/* This type MUST be 8-bit */ +typedef unsigned char BYTE; + +/* These types MUST be 16-bit */ +typedef short SHORT; +typedef unsigned short WORD; +typedef unsigned short WCHAR; + +/* These types MUST be 32-bit */ +typedef long LONG; +typedef unsigned long DWORD; + +/* This type MUST be 64-bit (Remove this for C89 compatibility) */ +typedef unsigned long long QWORD; + +#endif + +#endif diff --git a/radio/src/thirdparty/FatFs/option/cc932.c b/radio/src/thirdparty/FatFs/option/cc932.c index 1e244c374..9515c1289 100644 --- a/radio/src/thirdparty/FatFs/option/cc932.c +++ b/radio/src/thirdparty/FatFs/option/cc932.c @@ -1,3870 +1,3870 @@ -/*------------------------------------------------------------------------*/ -/* Unicode - OEM code bidirectional converter (C)ChaN, 2015 */ -/* CP932 (Japanese Shift-JIS) */ -/*------------------------------------------------------------------------*/ - -#include "../ff.h" - -#define _TINY_TABLE 0 - -#if !_USE_LFN || _CODE_PAGE != 932 -#error This file is not needed in current configuration. Remove from the project. -#endif - - -static -const WCHAR uni2sjis[] = { -/* Unicode - Sjis, Unicode - Sjis, Unicode - Sjis, Unicode - Sjis, */ - 0x00A7, 0x8198, 0x00A8, 0x814E, 0x00B0, 0x818B, 0x00B1, 0x817D, - 0x00B4, 0x814C, 0x00B6, 0x81F7, 0x00D7, 0x817E, 0x00F7, 0x8180, - 0x0391, 0x839F, 0x0392, 0x83A0, 0x0393, 0x83A1, 0x0394, 0x83A2, - 0x0395, 0x83A3, 0x0396, 0x83A4, 0x0397, 0x83A5, 0x0398, 0x83A6, - 0x0399, 0x83A7, 0x039A, 0x83A8, 0x039B, 0x83A9, 0x039C, 0x83AA, - 0x039D, 0x83AB, 0x039E, 0x83AC, 0x039F, 0x83AD, 0x03A0, 0x83AE, - 0x03A1, 0x83AF, 0x03A3, 0x83B0, 0x03A4, 0x83B1, 0x03A5, 0x83B2, - 0x03A6, 0x83B3, 0x03A7, 0x83B4, 0x03A8, 0x83B5, 0x03A9, 0x83B6, - 0x03B1, 0x83BF, 0x03B2, 0x83C0, 0x03B3, 0x83C1, 0x03B4, 0x83C2, - 0x03B5, 0x83C3, 0x03B6, 0x83C4, 0x03B7, 0x83C5, 0x03B8, 0x83C6, - 0x03B9, 0x83C7, 0x03BA, 0x83C8, 0x03BB, 0x83C9, 0x03BC, 0x83CA, - 0x03BD, 0x83CB, 0x03BE, 0x83CC, 0x03BF, 0x83CD, 0x03C0, 0x83CE, - 0x03C1, 0x83CF, 0x03C3, 0x83D0, 0x03C4, 0x83D1, 0x03C5, 0x83D2, - 0x03C6, 0x83D3, 0x03C7, 0x83D4, 0x03C8, 0x83D5, 0x03C9, 0x83D6, - 0x0401, 0x8446, 0x0410, 0x8440, 0x0411, 0x8441, 0x0412, 0x8442, - 0x0413, 0x8443, 0x0414, 0x8444, 0x0415, 0x8445, 0x0416, 0x8447, - 0x0417, 0x8448, 0x0418, 0x8449, 0x0419, 0x844A, 0x041A, 0x844B, - 0x041B, 0x844C, 0x041C, 0x844D, 0x041D, 0x844E, 0x041E, 0x844F, - 0x041F, 0x8450, 0x0420, 0x8451, 0x0421, 0x8452, 0x0422, 0x8453, - 0x0423, 0x8454, 0x0424, 0x8455, 0x0425, 0x8456, 0x0426, 0x8457, - 0x0427, 0x8458, 0x0428, 0x8459, 0x0429, 0x845A, 0x042A, 0x845B, - 0x042B, 0x845C, 0x042C, 0x845D, 0x042D, 0x845E, 0x042E, 0x845F, - 0x042F, 0x8460, 0x0430, 0x8470, 0x0431, 0x8471, 0x0432, 0x8472, - 0x0433, 0x8473, 0x0434, 0x8474, 0x0435, 0x8475, 0x0436, 0x8477, - 0x0437, 0x8478, 0x0438, 0x8479, 0x0439, 0x847A, 0x043A, 0x847B, - 0x043B, 0x847C, 0x043C, 0x847D, 0x043D, 0x847E, 0x043E, 0x8480, - 0x043F, 0x8481, 0x0440, 0x8482, 0x0441, 0x8483, 0x0442, 0x8484, - 0x0443, 0x8485, 0x0444, 0x8486, 0x0445, 0x8487, 0x0446, 0x8488, - 0x0447, 0x8489, 0x0448, 0x848A, 0x0449, 0x848B, 0x044A, 0x848C, - 0x044B, 0x848D, 0x044C, 0x848E, 0x044D, 0x848F, 0x044E, 0x8490, - 0x044F, 0x8491, 0x0451, 0x8476, 0x2010, 0x815D, 0x2015, 0x815C, - 0x2018, 0x8165, 0x2019, 0x8166, 0x201C, 0x8167, 0x201D, 0x8168, - 0x2020, 0x81F5, 0x2021, 0x81F6, 0x2025, 0x8164, 0x2026, 0x8163, - 0x2030, 0x81F1, 0x2032, 0x818C, 0x2033, 0x818D, 0x203B, 0x81A6, - 0x2103, 0x818E, 0x2116, 0x8782, 0x2121, 0x8784, 0x212B, 0x81F0, - 0x2160, 0x8754, 0x2161, 0x8755, 0x2162, 0x8756, 0x2163, 0x8757, - 0x2164, 0x8758, 0x2165, 0x8759, 0x2166, 0x875A, 0x2167, 0x875B, - 0x2168, 0x875C, 0x2169, 0x875D, 0x2170, 0xFA40, 0x2171, 0xFA41, - 0x2172, 0xFA42, 0x2173, 0xFA43, 0x2174, 0xFA44, 0x2175, 0xFA45, - 0x2176, 0xFA46, 0x2177, 0xFA47, 0x2178, 0xFA48, 0x2179, 0xFA49, - 0x2190, 0x81A9, 0x2191, 0x81AA, 0x2192, 0x81A8, 0x2193, 0x81AB, - 0x21D2, 0x81CB, 0x21D4, 0x81CC, 0x2200, 0x81CD, 0x2202, 0x81DD, - 0x2203, 0x81CE, 0x2207, 0x81DE, 0x2208, 0x81B8, 0x220B, 0x81B9, - 0x2211, 0x8794, 0x221A, 0x81E3, 0x221D, 0x81E5, 0x221E, 0x8187, - 0x221F, 0x8798, 0x2220, 0x81DA, 0x2225, 0x8161, 0x2227, 0x81C8, - 0x2228, 0x81C9, 0x2229, 0x81BF, 0x222A, 0x81BE, 0x222B, 0x81E7, - 0x222C, 0x81E8, 0x222E, 0x8793, 0x2234, 0x8188, 0x2235, 0x81E6, - 0x223D, 0x81E4, 0x2252, 0x81E0, 0x2260, 0x8182, 0x2261, 0x81DF, - 0x2266, 0x8185, 0x2267, 0x8186, 0x226A, 0x81E1, 0x226B, 0x81E2, - 0x2282, 0x81BC, 0x2283, 0x81BD, 0x2286, 0x81BA, 0x2287, 0x81BB, - 0x22A5, 0x81DB, 0x22BF, 0x8799, 0x2312, 0x81DC, 0x2460, 0x8740, - 0x2461, 0x8741, 0x2462, 0x8742, 0x2463, 0x8743, 0x2464, 0x8744, - 0x2465, 0x8745, 0x2466, 0x8746, 0x2467, 0x8747, 0x2468, 0x8748, - 0x2469, 0x8749, 0x246A, 0x874A, 0x246B, 0x874B, 0x246C, 0x874C, - 0x246D, 0x874D, 0x246E, 0x874E, 0x246F, 0x874F, 0x2470, 0x8750, - 0x2471, 0x8751, 0x2472, 0x8752, 0x2473, 0x8753, 0x2500, 0x849F, - 0x2501, 0x84AA, 0x2502, 0x84A0, 0x2503, 0x84AB, 0x250C, 0x84A1, - 0x250F, 0x84AC, 0x2510, 0x84A2, 0x2513, 0x84AD, 0x2514, 0x84A4, - 0x2517, 0x84AF, 0x2518, 0x84A3, 0x251B, 0x84AE, 0x251C, 0x84A5, - 0x251D, 0x84BA, 0x2520, 0x84B5, 0x2523, 0x84B0, 0x2524, 0x84A7, - 0x2525, 0x84BC, 0x2528, 0x84B7, 0x252B, 0x84B2, 0x252C, 0x84A6, - 0x252F, 0x84B6, 0x2530, 0x84BB, 0x2533, 0x84B1, 0x2534, 0x84A8, - 0x2537, 0x84B8, 0x2538, 0x84BD, 0x253B, 0x84B3, 0x253C, 0x84A9, - 0x253F, 0x84B9, 0x2542, 0x84BE, 0x254B, 0x84B4, 0x25A0, 0x81A1, - 0x25A1, 0x81A0, 0x25B2, 0x81A3, 0x25B3, 0x81A2, 0x25BC, 0x81A5, - 0x25BD, 0x81A4, 0x25C6, 0x819F, 0x25C7, 0x819E, 0x25CB, 0x819B, - 0x25CE, 0x819D, 0x25CF, 0x819C, 0x25EF, 0x81FC, 0x2605, 0x819A, - 0x2606, 0x8199, 0x2640, 0x818A, 0x2642, 0x8189, 0x266A, 0x81F4, - 0x266D, 0x81F3, 0x266F, 0x81F2, 0x3000, 0x8140, 0x3001, 0x8141, - 0x3002, 0x8142, 0x3003, 0x8156, 0x3005, 0x8158, 0x3006, 0x8159, - 0x3007, 0x815A, 0x3008, 0x8171, 0x3009, 0x8172, 0x300A, 0x8173, - 0x300B, 0x8174, 0x300C, 0x8175, 0x300D, 0x8176, 0x300E, 0x8177, - 0x300F, 0x8178, 0x3010, 0x8179, 0x3011, 0x817A, 0x3012, 0x81A7, - 0x3013, 0x81AC, 0x3014, 0x816B, 0x3015, 0x816C, 0x301D, 0x8780, - 0x301F, 0x8781, 0x3041, 0x829F, 0x3042, 0x82A0, 0x3043, 0x82A1, - 0x3044, 0x82A2, 0x3045, 0x82A3, 0x3046, 0x82A4, 0x3047, 0x82A5, - 0x3048, 0x82A6, 0x3049, 0x82A7, 0x304A, 0x82A8, 0x304B, 0x82A9, - 0x304C, 0x82AA, 0x304D, 0x82AB, 0x304E, 0x82AC, 0x304F, 0x82AD, - 0x3050, 0x82AE, 0x3051, 0x82AF, 0x3052, 0x82B0, 0x3053, 0x82B1, - 0x3054, 0x82B2, 0x3055, 0x82B3, 0x3056, 0x82B4, 0x3057, 0x82B5, - 0x3058, 0x82B6, 0x3059, 0x82B7, 0x305A, 0x82B8, 0x305B, 0x82B9, - 0x305C, 0x82BA, 0x305D, 0x82BB, 0x305E, 0x82BC, 0x305F, 0x82BD, - 0x3060, 0x82BE, 0x3061, 0x82BF, 0x3062, 0x82C0, 0x3063, 0x82C1, - 0x3064, 0x82C2, 0x3065, 0x82C3, 0x3066, 0x82C4, 0x3067, 0x82C5, - 0x3068, 0x82C6, 0x3069, 0x82C7, 0x306A, 0x82C8, 0x306B, 0x82C9, - 0x306C, 0x82CA, 0x306D, 0x82CB, 0x306E, 0x82CC, 0x306F, 0x82CD, - 0x3070, 0x82CE, 0x3071, 0x82CF, 0x3072, 0x82D0, 0x3073, 0x82D1, - 0x3074, 0x82D2, 0x3075, 0x82D3, 0x3076, 0x82D4, 0x3077, 0x82D5, - 0x3078, 0x82D6, 0x3079, 0x82D7, 0x307A, 0x82D8, 0x307B, 0x82D9, - 0x307C, 0x82DA, 0x307D, 0x82DB, 0x307E, 0x82DC, 0x307F, 0x82DD, - 0x3080, 0x82DE, 0x3081, 0x82DF, 0x3082, 0x82E0, 0x3083, 0x82E1, - 0x3084, 0x82E2, 0x3085, 0x82E3, 0x3086, 0x82E4, 0x3087, 0x82E5, - 0x3088, 0x82E6, 0x3089, 0x82E7, 0x308A, 0x82E8, 0x308B, 0x82E9, - 0x308C, 0x82EA, 0x308D, 0x82EB, 0x308E, 0x82EC, 0x308F, 0x82ED, - 0x3090, 0x82EE, 0x3091, 0x82EF, 0x3092, 0x82F0, 0x3093, 0x82F1, - 0x309B, 0x814A, 0x309C, 0x814B, 0x309D, 0x8154, 0x309E, 0x8155, - 0x30A1, 0x8340, 0x30A2, 0x8341, 0x30A3, 0x8342, 0x30A4, 0x8343, - 0x30A5, 0x8344, 0x30A6, 0x8345, 0x30A7, 0x8346, 0x30A8, 0x8347, - 0x30A9, 0x8348, 0x30AA, 0x8349, 0x30AB, 0x834A, 0x30AC, 0x834B, - 0x30AD, 0x834C, 0x30AE, 0x834D, 0x30AF, 0x834E, 0x30B0, 0x834F, - 0x30B1, 0x8350, 0x30B2, 0x8351, 0x30B3, 0x8352, 0x30B4, 0x8353, - 0x30B5, 0x8354, 0x30B6, 0x8355, 0x30B7, 0x8356, 0x30B8, 0x8357, - 0x30B9, 0x8358, 0x30BA, 0x8359, 0x30BB, 0x835A, 0x30BC, 0x835B, - 0x30BD, 0x835C, 0x30BE, 0x835D, 0x30BF, 0x835E, 0x30C0, 0x835F, - 0x30C1, 0x8360, 0x30C2, 0x8361, 0x30C3, 0x8362, 0x30C4, 0x8363, - 0x30C5, 0x8364, 0x30C6, 0x8365, 0x30C7, 0x8366, 0x30C8, 0x8367, - 0x30C9, 0x8368, 0x30CA, 0x8369, 0x30CB, 0x836A, 0x30CC, 0x836B, - 0x30CD, 0x836C, 0x30CE, 0x836D, 0x30CF, 0x836E, 0x30D0, 0x836F, - 0x30D1, 0x8370, 0x30D2, 0x8371, 0x30D3, 0x8372, 0x30D4, 0x8373, - 0x30D5, 0x8374, 0x30D6, 0x8375, 0x30D7, 0x8376, 0x30D8, 0x8377, - 0x30D9, 0x8378, 0x30DA, 0x8379, 0x30DB, 0x837A, 0x30DC, 0x837B, - 0x30DD, 0x837C, 0x30DE, 0x837D, 0x30DF, 0x837E, 0x30E0, 0x8380, - 0x30E1, 0x8381, 0x30E2, 0x8382, 0x30E3, 0x8383, 0x30E4, 0x8384, - 0x30E5, 0x8385, 0x30E6, 0x8386, 0x30E7, 0x8387, 0x30E8, 0x8388, - 0x30E9, 0x8389, 0x30EA, 0x838A, 0x30EB, 0x838B, 0x30EC, 0x838C, - 0x30ED, 0x838D, 0x30EE, 0x838E, 0x30EF, 0x838F, 0x30F0, 0x8390, - 0x30F1, 0x8391, 0x30F2, 0x8392, 0x30F3, 0x8393, 0x30F4, 0x8394, - 0x30F5, 0x8395, 0x30F6, 0x8396, 0x30FB, 0x8145, 0x30FC, 0x815B, - 0x30FD, 0x8152, 0x30FE, 0x8153, 0x3231, 0x878A, 0x3232, 0x878B, - 0x3239, 0x878C, 0x32A4, 0x8785, 0x32A5, 0x8786, 0x32A6, 0x8787, - 0x32A7, 0x8788, 0x32A8, 0x8789, 0x3303, 0x8765, 0x330D, 0x8769, - 0x3314, 0x8760, 0x3318, 0x8763, 0x3322, 0x8761, 0x3323, 0x876B, - 0x3326, 0x876A, 0x3327, 0x8764, 0x332B, 0x876C, 0x3336, 0x8766, - 0x333B, 0x876E, 0x3349, 0x875F, 0x334A, 0x876D, 0x334D, 0x8762, - 0x3351, 0x8767, 0x3357, 0x8768, 0x337B, 0x877E, 0x337C, 0x878F, - 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0xFF7D, 0x00BD, 0xFF7E, 0x00BE, 0xFF7F, 0x00BF, 0xFF80, 0x00C0, - 0xFF81, 0x00C1, 0xFF82, 0x00C2, 0xFF83, 0x00C3, 0xFF84, 0x00C4, - 0xFF85, 0x00C5, 0xFF86, 0x00C6, 0xFF87, 0x00C7, 0xFF88, 0x00C8, - 0xFF89, 0x00C9, 0xFF8A, 0x00CA, 0xFF8B, 0x00CB, 0xFF8C, 0x00CC, - 0xFF8D, 0x00CD, 0xFF8E, 0x00CE, 0xFF8F, 0x00CF, 0xFF90, 0x00D0, - 0xFF91, 0x00D1, 0xFF92, 0x00D2, 0xFF93, 0x00D3, 0xFF94, 0x00D4, - 0xFF95, 0x00D5, 0xFF96, 0x00D6, 0xFF97, 0x00D7, 0xFF98, 0x00D8, - 0xFF99, 0x00D9, 0xFF9A, 0x00DA, 0xFF9B, 0x00DB, 0xFF9C, 0x00DC, - 0xFF9D, 0x00DD, 0xFF9E, 0x00DE, 0xFF9F, 0x00DF, 0xFFE0, 0x8191, - 0xFFE1, 0x8192, 0xFFE2, 0x81CA, 0xFFE3, 0x8150, 0xFFE4, 0xFA55, - 0xFFE5, 0x818F, 0, 0 -}; - -#if !_TINY_TABLE -static -const WCHAR sjis2uni[] = { -/* SJIS - Unicode, SJIS - Unicode, SJIS - Unicode, SJIS - Unicode, */ - 0x00A1, 0xFF61, 0x00A2, 0xFF62, 0x00A3, 0xFF63, 0x00A4, 0xFF64, - 0x00A5, 0xFF65, 0x00A6, 0xFF66, 0x00A7, 0xFF67, 0x00A8, 0xFF68, - 0x00A9, 0xFF69, 0x00AA, 0xFF6A, 0x00AB, 0xFF6B, 0x00AC, 0xFF6C, - 0x00AD, 0xFF6D, 0x00AE, 0xFF6E, 0x00AF, 0xFF6F, 0x00B0, 0xFF70, - 0x00B1, 0xFF71, 0x00B2, 0xFF72, 0x00B3, 0xFF73, 0x00B4, 0xFF74, - 0x00B5, 0xFF75, 0x00B6, 0xFF76, 0x00B7, 0xFF77, 0x00B8, 0xFF78, - 0x00B9, 0xFF79, 0x00BA, 0xFF7A, 0x00BB, 0xFF7B, 0x00BC, 0xFF7C, - 0x00BD, 0xFF7D, 0x00BE, 0xFF7E, 0x00BF, 0xFF7F, 0x00C0, 0xFF80, - 0x00C1, 0xFF81, 0x00C2, 0xFF82, 0x00C3, 0xFF83, 0x00C4, 0xFF84, - 0x00C5, 0xFF85, 0x00C6, 0xFF86, 0x00C7, 0xFF87, 0x00C8, 0xFF88, - 0x00C9, 0xFF89, 0x00CA, 0xFF8A, 0x00CB, 0xFF8B, 0x00CC, 0xFF8C, - 0x00CD, 0xFF8D, 0x00CE, 0xFF8E, 0x00CF, 0xFF8F, 0x00D0, 0xFF90, - 0x00D1, 0xFF91, 0x00D2, 0xFF92, 0x00D3, 0xFF93, 0x00D4, 0xFF94, - 0x00D5, 0xFF95, 0x00D6, 0xFF96, 0x00D7, 0xFF97, 0x00D8, 0xFF98, - 0x00D9, 0xFF99, 0x00DA, 0xFF9A, 0x00DB, 0xFF9B, 0x00DC, 0xFF9C, - 0x00DD, 0xFF9D, 0x00DE, 0xFF9E, 0x00DF, 0xFF9F, 0x8140, 0x3000, - 0x8141, 0x3001, 0x8142, 0x3002, 0x8143, 0xFF0C, 0x8144, 0xFF0E, - 0x8145, 0x30FB, 0x8146, 0xFF1A, 0x8147, 0xFF1B, 0x8148, 0xFF1F, - 0x8149, 0xFF01, 0x814A, 0x309B, 0x814B, 0x309C, 0x814C, 0x00B4, - 0x814D, 0xFF40, 0x814E, 0x00A8, 0x814F, 0xFF3E, 0x8150, 0xFFE3, - 0x8151, 0xFF3F, 0x8152, 0x30FD, 0x8153, 0x30FE, 0x8154, 0x309D, - 0x8155, 0x309E, 0x8156, 0x3003, 0x8157, 0x4EDD, 0x8158, 0x3005, - 0x8159, 0x3006, 0x815A, 0x3007, 0x815B, 0x30FC, 0x815C, 0x2015, - 0x815D, 0x2010, 0x815E, 0xFF0F, 0x815F, 0xFF3C, 0x8160, 0xFF5E, - 0x8161, 0x2225, 0x8162, 0xFF5C, 0x8163, 0x2026, 0x8164, 0x2025, - 0x8165, 0x2018, 0x8166, 0x2019, 0x8167, 0x201C, 0x8168, 0x201D, - 0x8169, 0xFF08, 0x816A, 0xFF09, 0x816B, 0x3014, 0x816C, 0x3015, - 0x816D, 0xFF3B, 0x816E, 0xFF3D, 0x816F, 0xFF5B, 0x8170, 0xFF5D, - 0x8171, 0x3008, 0x8172, 0x3009, 0x8173, 0x300A, 0x8174, 0x300B, - 0x8175, 0x300C, 0x8176, 0x300D, 0x8177, 0x300E, 0x8178, 0x300F, - 0x8179, 0x3010, 0x817A, 0x3011, 0x817B, 0xFF0B, 0x817C, 0xFF0D, - 0x817D, 0x00B1, 0x817E, 0x00D7, 0x8180, 0x00F7, 0x8181, 0xFF1D, - 0x8182, 0x2260, 0x8183, 0xFF1C, 0x8184, 0xFF1E, 0x8185, 0x2266, - 0x8186, 0x2267, 0x8187, 0x221E, 0x8188, 0x2234, 0x8189, 0x2642, - 0x818A, 0x2640, 0x818B, 0x00B0, 0x818C, 0x2032, 0x818D, 0x2033, - 0x818E, 0x2103, 0x818F, 0xFFE5, 0x8190, 0xFF04, 0x8191, 0xFFE0, - 0x8192, 0xFFE1, 0x8193, 0xFF05, 0x8194, 0xFF03, 0x8195, 0xFF06, - 0x8196, 0xFF0A, 0x8197, 0xFF20, 0x8198, 0x00A7, 0x8199, 0x2606, - 0x819A, 0x2605, 0x819B, 0x25CB, 0x819C, 0x25CF, 0x819D, 0x25CE, - 0x819E, 0x25C7, 0x819F, 0x25C6, 0x81A0, 0x25A1, 0x81A1, 0x25A0, - 0x81A2, 0x25B3, 0x81A3, 0x25B2, 0x81A4, 0x25BD, 0x81A5, 0x25BC, - 0x81A6, 0x203B, 0x81A7, 0x3012, 0x81A8, 0x2192, 0x81A9, 0x2190, - 0x81AA, 0x2191, 0x81AB, 0x2193, 0x81AC, 0x3013, 0x81B8, 0x2208, - 0x81B9, 0x220B, 0x81BA, 0x2286, 0x81BB, 0x2287, 0x81BC, 0x2282, - 0x81BD, 0x2283, 0x81BE, 0x222A, 0x81BF, 0x2229, 0x81C8, 0x2227, - 0x81C9, 0x2228, 0x81CA, 0xFFE2, 0x81CB, 0x21D2, 0x81CC, 0x21D4, - 0x81CD, 0x2200, 0x81CE, 0x2203, 0x81DA, 0x2220, 0x81DB, 0x22A5, - 0x81DC, 0x2312, 0x81DD, 0x2202, 0x81DE, 0x2207, 0x81DF, 0x2261, - 0x81E0, 0x2252, 0x81E1, 0x226A, 0x81E2, 0x226B, 0x81E3, 0x221A, - 0x81E4, 0x223D, 0x81E5, 0x221D, 0x81E6, 0x2235, 0x81E7, 0x222B, - 0x81E8, 0x222C, 0x81F0, 0x212B, 0x81F1, 0x2030, 0x81F2, 0x266F, - 0x81F3, 0x266D, 0x81F4, 0x266A, 0x81F5, 0x2020, 0x81F6, 0x2021, - 0x81F7, 0x00B6, 0x81FC, 0x25EF, 0x824F, 0xFF10, 0x8250, 0xFF11, - 0x8251, 0xFF12, 0x8252, 0xFF13, 0x8253, 0xFF14, 0x8254, 0xFF15, - 0x8255, 0xFF16, 0x8256, 0xFF17, 0x8257, 0xFF18, 0x8258, 0xFF19, - 0x8260, 0xFF21, 0x8261, 0xFF22, 0x8262, 0xFF23, 0x8263, 0xFF24, - 0x8264, 0xFF25, 0x8265, 0xFF26, 0x8266, 0xFF27, 0x8267, 0xFF28, - 0x8268, 0xFF29, 0x8269, 0xFF2A, 0x826A, 0xFF2B, 0x826B, 0xFF2C, - 0x826C, 0xFF2D, 0x826D, 0xFF2E, 0x826E, 0xFF2F, 0x826F, 0xFF30, - 0x8270, 0xFF31, 0x8271, 0xFF32, 0x8272, 0xFF33, 0x8273, 0xFF34, - 0x8274, 0xFF35, 0x8275, 0xFF36, 0x8276, 0xFF37, 0x8277, 0xFF38, - 0x8278, 0xFF39, 0x8279, 0xFF3A, 0x8281, 0xFF41, 0x8282, 0xFF42, - 0x8283, 0xFF43, 0x8284, 0xFF44, 0x8285, 0xFF45, 0x8286, 0xFF46, - 0x8287, 0xFF47, 0x8288, 0xFF48, 0x8289, 0xFF49, 0x828A, 0xFF4A, - 0x828B, 0xFF4B, 0x828C, 0xFF4C, 0x828D, 0xFF4D, 0x828E, 0xFF4E, - 0x828F, 0xFF4F, 0x8290, 0xFF50, 0x8291, 0xFF51, 0x8292, 0xFF52, - 0x8293, 0xFF53, 0x8294, 0xFF54, 0x8295, 0xFF55, 0x8296, 0xFF56, - 0x8297, 0xFF57, 0x8298, 0xFF58, 0x8299, 0xFF59, 0x829A, 0xFF5A, - 0x829F, 0x3041, 0x82A0, 0x3042, 0x82A1, 0x3043, 0x82A2, 0x3044, - 0x82A3, 0x3045, 0x82A4, 0x3046, 0x82A5, 0x3047, 0x82A6, 0x3048, - 0x82A7, 0x3049, 0x82A8, 0x304A, 0x82A9, 0x304B, 0x82AA, 0x304C, - 0x82AB, 0x304D, 0x82AC, 0x304E, 0x82AD, 0x304F, 0x82AE, 0x3050, - 0x82AF, 0x3051, 0x82B0, 0x3052, 0x82B1, 0x3053, 0x82B2, 0x3054, - 0x82B3, 0x3055, 0x82B4, 0x3056, 0x82B5, 0x3057, 0x82B6, 0x3058, - 0x82B7, 0x3059, 0x82B8, 0x305A, 0x82B9, 0x305B, 0x82BA, 0x305C, - 0x82BB, 0x305D, 0x82BC, 0x305E, 0x82BD, 0x305F, 0x82BE, 0x3060, - 0x82BF, 0x3061, 0x82C0, 0x3062, 0x82C1, 0x3063, 0x82C2, 0x3064, - 0x82C3, 0x3065, 0x82C4, 0x3066, 0x82C5, 0x3067, 0x82C6, 0x3068, - 0x82C7, 0x3069, 0x82C8, 0x306A, 0x82C9, 0x306B, 0x82CA, 0x306C, - 0x82CB, 0x306D, 0x82CC, 0x306E, 0x82CD, 0x306F, 0x82CE, 0x3070, - 0x82CF, 0x3071, 0x82D0, 0x3072, 0x82D1, 0x3073, 0x82D2, 0x3074, - 0x82D3, 0x3075, 0x82D4, 0x3076, 0x82D5, 0x3077, 0x82D6, 0x3078, - 0x82D7, 0x3079, 0x82D8, 0x307A, 0x82D9, 0x307B, 0x82DA, 0x307C, - 0x82DB, 0x307D, 0x82DC, 0x307E, 0x82DD, 0x307F, 0x82DE, 0x3080, - 0x82DF, 0x3081, 0x82E0, 0x3082, 0x82E1, 0x3083, 0x82E2, 0x3084, - 0x82E3, 0x3085, 0x82E4, 0x3086, 0x82E5, 0x3087, 0x82E6, 0x3088, - 0x82E7, 0x3089, 0x82E8, 0x308A, 0x82E9, 0x308B, 0x82EA, 0x308C, - 0x82EB, 0x308D, 0x82EC, 0x308E, 0x82ED, 0x308F, 0x82EE, 0x3090, - 0x82EF, 0x3091, 0x82F0, 0x3092, 0x82F1, 0x3093, 0x8340, 0x30A1, - 0x8341, 0x30A2, 0x8342, 0x30A3, 0x8343, 0x30A4, 0x8344, 0x30A5, - 0x8345, 0x30A6, 0x8346, 0x30A7, 0x8347, 0x30A8, 0x8348, 0x30A9, - 0x8349, 0x30AA, 0x834A, 0x30AB, 0x834B, 0x30AC, 0x834C, 0x30AD, - 0x834D, 0x30AE, 0x834E, 0x30AF, 0x834F, 0x30B0, 0x8350, 0x30B1, - 0x8351, 0x30B2, 0x8352, 0x30B3, 0x8353, 0x30B4, 0x8354, 0x30B5, - 0x8355, 0x30B6, 0x8356, 0x30B7, 0x8357, 0x30B8, 0x8358, 0x30B9, - 0x8359, 0x30BA, 0x835A, 0x30BB, 0x835B, 0x30BC, 0x835C, 0x30BD, - 0x835D, 0x30BE, 0x835E, 0x30BF, 0x835F, 0x30C0, 0x8360, 0x30C1, - 0x8361, 0x30C2, 0x8362, 0x30C3, 0x8363, 0x30C4, 0x8364, 0x30C5, - 0x8365, 0x30C6, 0x8366, 0x30C7, 0x8367, 0x30C8, 0x8368, 0x30C9, - 0x8369, 0x30CA, 0x836A, 0x30CB, 0x836B, 0x30CC, 0x836C, 0x30CD, - 0x836D, 0x30CE, 0x836E, 0x30CF, 0x836F, 0x30D0, 0x8370, 0x30D1, - 0x8371, 0x30D2, 0x8372, 0x30D3, 0x8373, 0x30D4, 0x8374, 0x30D5, - 0x8375, 0x30D6, 0x8376, 0x30D7, 0x8377, 0x30D8, 0x8378, 0x30D9, - 0x8379, 0x30DA, 0x837A, 0x30DB, 0x837B, 0x30DC, 0x837C, 0x30DD, - 0x837D, 0x30DE, 0x837E, 0x30DF, 0x8380, 0x30E0, 0x8381, 0x30E1, - 0x8382, 0x30E2, 0x8383, 0x30E3, 0x8384, 0x30E4, 0x8385, 0x30E5, - 0x8386, 0x30E6, 0x8387, 0x30E7, 0x8388, 0x30E8, 0x8389, 0x30E9, - 0x838A, 0x30EA, 0x838B, 0x30EB, 0x838C, 0x30EC, 0x838D, 0x30ED, - 0x838E, 0x30EE, 0x838F, 0x30EF, 0x8390, 0x30F0, 0x8391, 0x30F1, - 0x8392, 0x30F2, 0x8393, 0x30F3, 0x8394, 0x30F4, 0x8395, 0x30F5, - 0x8396, 0x30F6, 0x839F, 0x0391, 0x83A0, 0x0392, 0x83A1, 0x0393, - 0x83A2, 0x0394, 0x83A3, 0x0395, 0x83A4, 0x0396, 0x83A5, 0x0397, - 0x83A6, 0x0398, 0x83A7, 0x0399, 0x83A8, 0x039A, 0x83A9, 0x039B, - 0x83AA, 0x039C, 0x83AB, 0x039D, 0x83AC, 0x039E, 0x83AD, 0x039F, - 0x83AE, 0x03A0, 0x83AF, 0x03A1, 0x83B0, 0x03A3, 0x83B1, 0x03A4, - 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0xFB77, 0x52AF, 0xFB78, 0x7821, 0xFB79, 0x784E, 0xFB7A, 0x7864, - 0xFB7B, 0x787A, 0xFB7C, 0x7930, 0xFB7D, 0xFA18, 0xFB7E, 0xFA19, - 0xFB80, 0xFA1A, 0xFB81, 0x7994, 0xFB82, 0xFA1B, 0xFB83, 0x799B, - 0xFB84, 0x7AD1, 0xFB85, 0x7AE7, 0xFB86, 0xFA1C, 0xFB87, 0x7AEB, - 0xFB88, 0x7B9E, 0xFB89, 0xFA1D, 0xFB8A, 0x7D48, 0xFB8B, 0x7D5C, - 0xFB8C, 0x7DB7, 0xFB8D, 0x7DA0, 0xFB8E, 0x7DD6, 0xFB8F, 0x7E52, - 0xFB90, 0x7F47, 0xFB91, 0x7FA1, 0xFB92, 0xFA1E, 0xFB93, 0x8301, - 0xFB94, 0x8362, 0xFB95, 0x837F, 0xFB96, 0x83C7, 0xFB97, 0x83F6, - 0xFB98, 0x8448, 0xFB99, 0x84B4, 0xFB9A, 0x8553, 0xFB9B, 0x8559, - 0xFB9C, 0x856B, 0xFB9D, 0xFA1F, 0xFB9E, 0x85B0, 0xFB9F, 0xFA20, - 0xFBA0, 0xFA21, 0xFBA1, 0x8807, 0xFBA2, 0x88F5, 0xFBA3, 0x8A12, - 0xFBA4, 0x8A37, 0xFBA5, 0x8A79, 0xFBA6, 0x8AA7, 0xFBA7, 0x8ABE, - 0xFBA8, 0x8ADF, 0xFBA9, 0xFA22, 0xFBAA, 0x8AF6, 0xFBAB, 0x8B53, - 0xFBAC, 0x8B7F, 0xFBAD, 0x8CF0, 0xFBAE, 0x8CF4, 0xFBAF, 0x8D12, - 0xFBB0, 0x8D76, 0xFBB1, 0xFA23, 0xFBB2, 0x8ECF, 0xFBB3, 0xFA24, - 0xFBB4, 0xFA25, 0xFBB5, 0x9067, 0xFBB6, 0x90DE, 0xFBB7, 0xFA26, - 0xFBB8, 0x9115, 0xFBB9, 0x9127, 0xFBBA, 0x91DA, 0xFBBB, 0x91D7, - 0xFBBC, 0x91DE, 0xFBBD, 0x91ED, 0xFBBE, 0x91EE, 0xFBBF, 0x91E4, - 0xFBC0, 0x91E5, 0xFBC1, 0x9206, 0xFBC2, 0x9210, 0xFBC3, 0x920A, - 0xFBC4, 0x923A, 0xFBC5, 0x9240, 0xFBC6, 0x923C, 0xFBC7, 0x924E, - 0xFBC8, 0x9259, 0xFBC9, 0x9251, 0xFBCA, 0x9239, 0xFBCB, 0x9267, - 0xFBCC, 0x92A7, 0xFBCD, 0x9277, 0xFBCE, 0x9278, 0xFBCF, 0x92E7, - 0xFBD0, 0x92D7, 0xFBD1, 0x92D9, 0xFBD2, 0x92D0, 0xFBD3, 0xFA27, - 0xFBD4, 0x92D5, 0xFBD5, 0x92E0, 0xFBD6, 0x92D3, 0xFBD7, 0x9325, - 0xFBD8, 0x9321, 0xFBD9, 0x92FB, 0xFBDA, 0xFA28, 0xFBDB, 0x931E, - 0xFBDC, 0x92FF, 0xFBDD, 0x931D, 0xFBDE, 0x9302, 0xFBDF, 0x9370, - 0xFBE0, 0x9357, 0xFBE1, 0x93A4, 0xFBE2, 0x93C6, 0xFBE3, 0x93DE, - 0xFBE4, 0x93F8, 0xFBE5, 0x9431, 0xFBE6, 0x9445, 0xFBE7, 0x9448, - 0xFBE8, 0x9592, 0xFBE9, 0xF9DC, 0xFBEA, 0xFA29, 0xFBEB, 0x969D, - 0xFBEC, 0x96AF, 0xFBED, 0x9733, 0xFBEE, 0x973B, 0xFBEF, 0x9743, - 0xFBF0, 0x974D, 0xFBF1, 0x974F, 0xFBF2, 0x9751, 0xFBF3, 0x9755, - 0xFBF4, 0x9857, 0xFBF5, 0x9865, 0xFBF6, 0xFA2A, 0xFBF7, 0xFA2B, - 0xFBF8, 0x9927, 0xFBF9, 0xFA2C, 0xFBFA, 0x999E, 0xFBFB, 0x9A4E, - 0xFBFC, 0x9AD9, 0xFC40, 0x9ADC, 0xFC41, 0x9B75, 0xFC42, 0x9B72, - 0xFC43, 0x9B8F, 0xFC44, 0x9BB1, 0xFC45, 0x9BBB, 0xFC46, 0x9C00, - 0xFC47, 0x9D70, 0xFC48, 0x9D6B, 0xFC49, 0xFA2D, 0xFC4A, 0x9E19, - 0xFC4B, 0x9ED1, 0, 0 -}; -#endif - - - -WCHAR ff_convert ( /* Converted code, 0 means conversion error */ - WCHAR chr, /* Character code to be converted */ - UINT dir /* 0: Unicode to OEM code, 1: OEM code to Unicode */ -) -{ - const WCHAR *p; - WCHAR c; - int i, n, li, hi; - - - if (chr <= 0x80) { /* ASCII */ - c = chr; - } else { -#if !_TINY_TABLE - if (dir) { /* OEM code to unicode */ - p = sjis2uni; - hi = sizeof sjis2uni / 4 - 1; - } else { /* Unicode to OEM code */ - p = uni2sjis; - hi = sizeof uni2sjis / 4 - 1; - } - li = 0; - for (n = 16; n; n--) { - i = li + (hi - li) / 2; - if (chr == p[i * 2]) break; - if (chr > p[i * 2]) - li = i; - else - hi = i; - } - c = n ? p[i * 2 + 1] : 0; -#else - if (dir) { /* OEM code to unicode (Incremental search)*/ - p = &uni2sjis[1]; - do { - c = *p; - p += 2; - } while (c && c != chr); - p -= 3; - c = *p; - } else { /* Unicode to OEM code */ - li = 0; hi = sizeof uni2sjis / 4 - 1; - for (n = 16; n; n--) { - i = li + (hi - li) / 2; - if (chr == uni2sjis[i * 2]) break; - if (chr > uni2sjis[i * 2]) - li = i; - else - hi = i; - } - c = n ? uni2sjis[i * 2 + 1] : 0; - } -#endif - } - - return c; -} - - - -WCHAR ff_wtoupper ( /* Returns upper converted character */ - WCHAR chr /* Unicode character to be upper converted (BMP only) */ -) -{ - /* Compressed upper conversion table */ - static const WCHAR cvt1[] = { /* U+0000 - U+0FFF */ - /* Basic Latin */ - 0x0061,0x031A, - /* Latin-1 Supplement */ - 0x00E0,0x0317, 0x00F8,0x0307, 0x00FF,0x0001,0x0178, - /* Latin Extended-A */ - 0x0100,0x0130, 0x0132,0x0106, 0x0139,0x0110, 0x014A,0x012E, 0x0179,0x0106, - /* Latin Extended-B */ - 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, - 0x01CD,0x0110, 0x01DD,0x0001,0x018E, 0x01DE,0x0112, 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, 0x01F8,0x0128, - 0x0222,0x0112, 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, 0x0246,0x010A, - /* IPA Extensions */ - 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, - /* Greek, Coptic */ - 0x037B,0x0003,0x03FD,0x03FE,0x03FF, 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, 0x03B1,0x0311, - 0x03C2,0x0002,0x03A3,0x03A3, 0x03C4,0x0308, 0x03CC,0x0003,0x038C,0x038E,0x038F, 0x03D8,0x0118, - 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, - /* Cyrillic */ - 0x0430,0x0320, 0x0450,0x0710, 0x0460,0x0122, 0x048A,0x0136, 0x04C1,0x010E, 0x04CF,0x0001,0x04C0, 0x04D0,0x0144, - /* Armenian */ - 0x0561,0x0426, - - 0x0000 - }; - static const WCHAR cvt2[] = { /* U+1000 - U+FFFF */ - /* Phonetic Extensions */ - 0x1D7D,0x0001,0x2C63, - /* Latin Extended Additional */ - 0x1E00,0x0196, 0x1EA0,0x015A, - /* Greek Extended */ - 0x1F00,0x0608, 0x1F10,0x0606, 0x1F20,0x0608, 0x1F30,0x0608, 0x1F40,0x0606, - 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, 0x1F60,0x0608, - 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, - 0x1F80,0x0608, 0x1F90,0x0608, 0x1FA0,0x0608, 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, - 0x1FCC,0x0001,0x1FC3, 0x1FD0,0x0602, 0x1FE0,0x0602, 0x1FE5,0x0001,0x1FEC, 0x1FF2,0x0001,0x1FFC, - /* Letterlike Symbols */ - 0x214E,0x0001,0x2132, - /* Number forms */ - 0x2170,0x0210, 0x2184,0x0001,0x2183, - /* Enclosed Alphanumerics */ - 0x24D0,0x051A, 0x2C30,0x042F, - /* Latin Extended-C */ - 0x2C60,0x0102, 0x2C67,0x0106, 0x2C75,0x0102, - /* Coptic */ - 0x2C80,0x0164, - /* Georgian Supplement */ - 0x2D00,0x0826, - /* Full-width */ - 0xFF41,0x031A, - - 0x0000 - }; - const WCHAR *p; - WCHAR bc, nc, cmd; - - - p = chr < 0x1000 ? cvt1 : cvt2; - for (;;) { - bc = *p++; /* Get block base */ - if (!bc || chr < bc) break; - nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ - if (chr < bc + nc) { /* In the block? */ - switch (cmd) { - case 0: chr = p[chr - bc]; break; /* Table conversion */ - case 1: chr -= (chr - bc) & 1; break; /* Case pairs */ - case 2: chr -= 16; break; /* Shift -16 */ - case 3: chr -= 32; break; /* Shift -32 */ - case 4: chr -= 48; break; /* Shift -48 */ - case 5: chr -= 26; break; /* Shift -26 */ - case 6: chr += 8; break; /* Shift +8 */ - case 7: chr -= 80; break; /* Shift -80 */ - case 8: chr -= 0x1C60; break; /* Shift -0x1C60 */ - } - break; - } - if (!cmd) p += nc; - } - - return chr; -} - +/*------------------------------------------------------------------------*/ +/* Unicode - OEM code bidirectional converter (C)ChaN, 2015 */ +/* CP932 (Japanese Shift-JIS) */ +/*------------------------------------------------------------------------*/ + +#include "../ff.h" + +#define _TINY_TABLE 0 + +#if !_USE_LFN || _CODE_PAGE != 932 +#error This file is not needed in current configuration. Remove from the project. +#endif + + +static +const WCHAR uni2sjis[] = { +/* Unicode - Sjis, Unicode - Sjis, Unicode - Sjis, Unicode - Sjis, */ + 0x00A7, 0x8198, 0x00A8, 0x814E, 0x00B0, 0x818B, 0x00B1, 0x817D, + 0x00B4, 0x814C, 0x00B6, 0x81F7, 0x00D7, 0x817E, 0x00F7, 0x8180, + 0x0391, 0x839F, 0x0392, 0x83A0, 0x0393, 0x83A1, 0x0394, 0x83A2, + 0x0395, 0x83A3, 0x0396, 0x83A4, 0x0397, 0x83A5, 0x0398, 0x83A6, + 0x0399, 0x83A7, 0x039A, 0x83A8, 0x039B, 0x83A9, 0x039C, 0x83AA, + 0x039D, 0x83AB, 0x039E, 0x83AC, 0x039F, 0x83AD, 0x03A0, 0x83AE, + 0x03A1, 0x83AF, 0x03A3, 0x83B0, 0x03A4, 0x83B1, 0x03A5, 0x83B2, + 0x03A6, 0x83B3, 0x03A7, 0x83B4, 0x03A8, 0x83B5, 0x03A9, 0x83B6, + 0x03B1, 0x83BF, 0x03B2, 0x83C0, 0x03B3, 0x83C1, 0x03B4, 0x83C2, + 0x03B5, 0x83C3, 0x03B6, 0x83C4, 0x03B7, 0x83C5, 0x03B8, 0x83C6, + 0x03B9, 0x83C7, 0x03BA, 0x83C8, 0x03BB, 0x83C9, 0x03BC, 0x83CA, + 0x03BD, 0x83CB, 0x03BE, 0x83CC, 0x03BF, 0x83CD, 0x03C0, 0x83CE, + 0x03C1, 0x83CF, 0x03C3, 0x83D0, 0x03C4, 0x83D1, 0x03C5, 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0x9844, 0x9B72, 0xFC42, 0x9B74, 0xE9B5, 0x9B75, 0xFC41, + 0x9B83, 0xE9B7, 0x9B8E, 0x88BC, 0x9B8F, 0xFC43, 0x9B91, 0xE9B8, + 0x9B92, 0x95A9, 0x9B93, 0xE9B6, 0x9B96, 0xE9B9, 0x9B97, 0xE9BA, + 0x9B9F, 0xE9BB, 0x9BA0, 0xE9BC, 0x9BA8, 0xE9BD, 0x9BAA, 0x968E, + 0x9BAB, 0x8E4C, 0x9BAD, 0x8DF8, 0x9BAE, 0x914E, 0x9BB1, 0xFC44, + 0x9BB4, 0xE9BE, 0x9BB9, 0xE9C1, 0x9BBB, 0xFC45, 0x9BC0, 0xE9BF, + 0x9BC6, 0xE9C2, 0x9BC9, 0x8CEF, 0x9BCA, 0xE9C0, 0x9BCF, 0xE9C3, + 0x9BD1, 0xE9C4, 0x9BD2, 0xE9C5, 0x9BD4, 0xE9C9, 0x9BD6, 0x8E49, + 0x9BDB, 0x91E2, 0x9BE1, 0xE9CA, 0x9BE2, 0xE9C7, 0x9BE3, 0xE9C6, + 0x9BE4, 0xE9C8, 0x9BE8, 0x8C7E, 0x9BF0, 0xE9CE, 0x9BF1, 0xE9CD, + 0x9BF2, 0xE9CC, 0x9BF5, 0x88B1, 0x9C00, 0xFC46, 0x9C04, 0xE9D8, + 0x9C06, 0xE9D4, 0x9C08, 0xE9D5, 0x9C09, 0xE9D1, 0x9C0A, 0xE9D7, + 0x9C0C, 0xE9D3, 0x9C0D, 0x8A82, 0x9C10, 0x986B, 0x9C12, 0xE9D6, + 0x9C13, 0xE9D2, 0x9C14, 0xE9D0, 0x9C15, 0xE9CF, 0x9C1B, 0xE9DA, + 0x9C21, 0xE9DD, 0x9C24, 0xE9DC, 0x9C25, 0xE9DB, 0x9C2D, 0x9568, + 0x9C2E, 0xE9D9, 0x9C2F, 0x88F1, 0x9C30, 0xE9DE, 0x9C32, 0xE9E0, + 0x9C39, 0x8A8F, 0x9C3A, 0xE9CB, 0x9C3B, 0x8956, 0x9C3E, 0xE9E2, + 0x9C46, 0xE9E1, 0x9C47, 0xE9DF, 0x9C48, 0x924C, 0x9C52, 0x9690, + 0x9C57, 0x97D8, 0x9C5A, 0xE9E3, 0x9C60, 0xE9E4, 0x9C67, 0xE9E5, + 0x9C76, 0xE9E6, 0x9C78, 0xE9E7, 0x9CE5, 0x92B9, 0x9CE7, 0xE9E8, + 0x9CE9, 0x94B5, 0x9CEB, 0xE9ED, 0x9CEC, 0xE9E9, 0x9CF0, 0xE9EA, + 0x9CF3, 0x9650, 0x9CF4, 0x96C2, 0x9CF6, 0x93CE, 0x9D03, 0xE9EE, + 0x9D06, 0xE9EF, 0x9D07, 0x93BC, 0x9D08, 0xE9EC, 0x9D09, 0xE9EB, + 0x9D0E, 0x89A8, 0x9D12, 0xE9F7, 0x9D15, 0xE9F6, 0x9D1B, 0x8995, + 0x9D1F, 0xE9F4, 0x9D23, 0xE9F3, 0x9D26, 0xE9F1, 0x9D28, 0x8A9B, + 0x9D2A, 0xE9F0, 0x9D2B, 0x8EB0, 0x9D2C, 0x89A7, 0x9D3B, 0x8D83, + 0x9D3E, 0xE9FA, 0x9D3F, 0xE9F9, 0x9D41, 0xE9F8, 0x9D44, 0xE9F5, + 0x9D46, 0xE9FB, 0x9D48, 0xE9FC, 0x9D50, 0xEA44, 0x9D51, 0xEA43, + 0x9D59, 0xEA45, 0x9D5C, 0x894C, 0x9D5D, 0xEA40, 0x9D5E, 0xEA41, + 0x9D60, 0x8D94, 0x9D61, 0x96B7, 0x9D64, 0xEA42, 0x9D6B, 0xFC48, + 0x9D6C, 0x9651, 0x9D6F, 0xEA4A, 0x9D70, 0xFC47, 0x9D72, 0xEA46, + 0x9D7A, 0xEA4B, 0x9D87, 0xEA48, 0x9D89, 0xEA47, 0x9D8F, 0x8C7B, + 0x9D9A, 0xEA4C, 0x9DA4, 0xEA4D, 0x9DA9, 0xEA4E, 0x9DAB, 0xEA49, + 0x9DAF, 0xE9F2, 0x9DB2, 0xEA4F, 0x9DB4, 0x92DF, 0x9DB8, 0xEA53, + 0x9DBA, 0xEA54, 0x9DBB, 0xEA52, 0x9DC1, 0xEA51, 0x9DC2, 0xEA57, + 0x9DC4, 0xEA50, 0x9DC6, 0xEA55, 0x9DCF, 0xEA56, 0x9DD3, 0xEA59, + 0x9DD9, 0xEA58, 0x9DE6, 0xEA5B, 0x9DED, 0xEA5C, 0x9DEF, 0xEA5D, + 0x9DF2, 0x9868, 0x9DF8, 0xEA5A, 0x9DF9, 0x91E9, 0x9DFA, 0x8DEB, + 0x9DFD, 0xEA5E, 0x9E19, 0xFC4A, 0x9E1A, 0xEA5F, 0x9E1B, 0xEA60, + 0x9E1E, 0xEA61, 0x9E75, 0xEA62, 0x9E78, 0x8CB2, 0x9E79, 0xEA63, + 0x9E7D, 0xEA64, 0x9E7F, 0x8EAD, 0x9E81, 0xEA65, 0x9E88, 0xEA66, + 0x9E8B, 0xEA67, 0x9E8C, 0xEA68, 0x9E91, 0xEA6B, 0x9E92, 0xEA69, + 0x9E93, 0x985B, 0x9E95, 0xEA6A, 0x9E97, 0x97ED, 0x9E9D, 0xEA6C, + 0x9E9F, 0x97D9, 0x9EA5, 0xEA6D, 0x9EA6, 0x949E, 0x9EA9, 0xEA6E, + 0x9EAA, 0xEA70, 0x9EAD, 0xEA71, 0x9EB8, 0xEA6F, 0x9EB9, 0x8D8D, + 0x9EBA, 0x96CB, 0x9EBB, 0x9683, 0x9EBC, 0x9BF5, 0x9EBE, 0x9F80, + 0x9EBF, 0x969B, 0x9EC4, 0x89A9, 0x9ECC, 0xEA73, 0x9ECD, 0x8B6F, + 0x9ECE, 0xEA74, 0x9ECF, 0xEA75, 0x9ED0, 0xEA76, 0x9ED1, 0xFC4B, + 0x9ED2, 0x8D95, 0x9ED4, 0xEA77, 0x9ED8, 0xE0D2, 0x9ED9, 0x96D9, + 0x9EDB, 0x91E1, 0x9EDC, 0xEA78, 0x9EDD, 0xEA7A, 0x9EDE, 0xEA79, + 0x9EE0, 0xEA7B, 0x9EE5, 0xEA7C, 0x9EE8, 0xEA7D, 0x9EEF, 0xEA7E, + 0x9EF4, 0xEA80, 0x9EF6, 0xEA81, 0x9EF7, 0xEA82, 0x9EF9, 0xEA83, + 0x9EFB, 0xEA84, 0x9EFC, 0xEA85, 0x9EFD, 0xEA86, 0x9F07, 0xEA87, + 0x9F08, 0xEA88, 0x9F0E, 0x9343, 0x9F13, 0x8CDB, 0x9F15, 0xEA8A, + 0x9F20, 0x916C, 0x9F21, 0xEA8B, 0x9F2C, 0xEA8C, 0x9F3B, 0x9540, + 0x9F3E, 0xEA8D, 0x9F4A, 0xEA8E, 0x9F4B, 0xE256, 0x9F4E, 0xE6D8, + 0x9F4F, 0xE8EB, 0x9F52, 0xEA8F, 0x9F54, 0xEA90, 0x9F5F, 0xEA92, + 0x9F60, 0xEA93, 0x9F61, 0xEA94, 0x9F62, 0x97EE, 0x9F63, 0xEA91, + 0x9F66, 0xEA95, 0x9F67, 0xEA96, 0x9F6A, 0xEA98, 0x9F6C, 0xEA97, + 0x9F72, 0xEA9A, 0x9F76, 0xEA9B, 0x9F77, 0xEA99, 0x9F8D, 0x97B4, + 0x9F95, 0xEA9C, 0x9F9C, 0xEA9D, 0x9F9D, 0xE273, 0x9FA0, 0xEA9E, + 0xF929, 0xFAE0, 0xF9DC, 0xFBE9, 0xFA0E, 0xFA90, 0xFA0F, 0xFA9B, + 0xFA10, 0xFA9C, 0xFA11, 0xFAB1, 0xFA12, 0xFAD8, 0xFA13, 0xFAE8, + 0xFA14, 0xFAEA, 0xFA15, 0xFB58, 0xFA16, 0xFB5E, 0xFA17, 0xFB75, + 0xFA18, 0xFB7D, 0xFA19, 0xFB7E, 0xFA1A, 0xFB80, 0xFA1B, 0xFB82, + 0xFA1C, 0xFB86, 0xFA1D, 0xFB89, 0xFA1E, 0xFB92, 0xFA1F, 0xFB9D, + 0xFA20, 0xFB9F, 0xFA21, 0xFBA0, 0xFA22, 0xFBA9, 0xFA23, 0xFBB1, + 0xFA24, 0xFBB3, 0xFA25, 0xFBB4, 0xFA26, 0xFBB7, 0xFA27, 0xFBD3, + 0xFA28, 0xFBDA, 0xFA29, 0xFBEA, 0xFA2A, 0xFBF6, 0xFA2B, 0xFBF7, + 0xFA2C, 0xFBF9, 0xFA2D, 0xFC49, 0xFF01, 0x8149, 0xFF02, 0xFA57, + 0xFF03, 0x8194, 0xFF04, 0x8190, 0xFF05, 0x8193, 0xFF06, 0x8195, + 0xFF07, 0xFA56, 0xFF08, 0x8169, 0xFF09, 0x816A, 0xFF0A, 0x8196, + 0xFF0B, 0x817B, 0xFF0C, 0x8143, 0xFF0D, 0x817C, 0xFF0E, 0x8144, + 0xFF0F, 0x815E, 0xFF10, 0x824F, 0xFF11, 0x8250, 0xFF12, 0x8251, + 0xFF13, 0x8252, 0xFF14, 0x8253, 0xFF15, 0x8254, 0xFF16, 0x8255, + 0xFF17, 0x8256, 0xFF18, 0x8257, 0xFF19, 0x8258, 0xFF1A, 0x8146, + 0xFF1B, 0x8147, 0xFF1C, 0x8183, 0xFF1D, 0x8181, 0xFF1E, 0x8184, + 0xFF1F, 0x8148, 0xFF20, 0x8197, 0xFF21, 0x8260, 0xFF22, 0x8261, + 0xFF23, 0x8262, 0xFF24, 0x8263, 0xFF25, 0x8264, 0xFF26, 0x8265, + 0xFF27, 0x8266, 0xFF28, 0x8267, 0xFF29, 0x8268, 0xFF2A, 0x8269, + 0xFF2B, 0x826A, 0xFF2C, 0x826B, 0xFF2D, 0x826C, 0xFF2E, 0x826D, + 0xFF2F, 0x826E, 0xFF30, 0x826F, 0xFF31, 0x8270, 0xFF32, 0x8271, + 0xFF33, 0x8272, 0xFF34, 0x8273, 0xFF35, 0x8274, 0xFF36, 0x8275, + 0xFF37, 0x8276, 0xFF38, 0x8277, 0xFF39, 0x8278, 0xFF3A, 0x8279, + 0xFF3B, 0x816D, 0xFF3C, 0x815F, 0xFF3D, 0x816E, 0xFF3E, 0x814F, + 0xFF3F, 0x8151, 0xFF40, 0x814D, 0xFF41, 0x8281, 0xFF42, 0x8282, + 0xFF43, 0x8283, 0xFF44, 0x8284, 0xFF45, 0x8285, 0xFF46, 0x8286, + 0xFF47, 0x8287, 0xFF48, 0x8288, 0xFF49, 0x8289, 0xFF4A, 0x828A, + 0xFF4B, 0x828B, 0xFF4C, 0x828C, 0xFF4D, 0x828D, 0xFF4E, 0x828E, + 0xFF4F, 0x828F, 0xFF50, 0x8290, 0xFF51, 0x8291, 0xFF52, 0x8292, + 0xFF53, 0x8293, 0xFF54, 0x8294, 0xFF55, 0x8295, 0xFF56, 0x8296, + 0xFF57, 0x8297, 0xFF58, 0x8298, 0xFF59, 0x8299, 0xFF5A, 0x829A, + 0xFF5B, 0x816F, 0xFF5C, 0x8162, 0xFF5D, 0x8170, 0xFF5E, 0x8160, + 0xFF61, 0x00A1, 0xFF62, 0x00A2, 0xFF63, 0x00A3, 0xFF64, 0x00A4, + 0xFF65, 0x00A5, 0xFF66, 0x00A6, 0xFF67, 0x00A7, 0xFF68, 0x00A8, + 0xFF69, 0x00A9, 0xFF6A, 0x00AA, 0xFF6B, 0x00AB, 0xFF6C, 0x00AC, + 0xFF6D, 0x00AD, 0xFF6E, 0x00AE, 0xFF6F, 0x00AF, 0xFF70, 0x00B0, + 0xFF71, 0x00B1, 0xFF72, 0x00B2, 0xFF73, 0x00B3, 0xFF74, 0x00B4, + 0xFF75, 0x00B5, 0xFF76, 0x00B6, 0xFF77, 0x00B7, 0xFF78, 0x00B8, + 0xFF79, 0x00B9, 0xFF7A, 0x00BA, 0xFF7B, 0x00BB, 0xFF7C, 0x00BC, + 0xFF7D, 0x00BD, 0xFF7E, 0x00BE, 0xFF7F, 0x00BF, 0xFF80, 0x00C0, + 0xFF81, 0x00C1, 0xFF82, 0x00C2, 0xFF83, 0x00C3, 0xFF84, 0x00C4, + 0xFF85, 0x00C5, 0xFF86, 0x00C6, 0xFF87, 0x00C7, 0xFF88, 0x00C8, + 0xFF89, 0x00C9, 0xFF8A, 0x00CA, 0xFF8B, 0x00CB, 0xFF8C, 0x00CC, + 0xFF8D, 0x00CD, 0xFF8E, 0x00CE, 0xFF8F, 0x00CF, 0xFF90, 0x00D0, + 0xFF91, 0x00D1, 0xFF92, 0x00D2, 0xFF93, 0x00D3, 0xFF94, 0x00D4, + 0xFF95, 0x00D5, 0xFF96, 0x00D6, 0xFF97, 0x00D7, 0xFF98, 0x00D8, + 0xFF99, 0x00D9, 0xFF9A, 0x00DA, 0xFF9B, 0x00DB, 0xFF9C, 0x00DC, + 0xFF9D, 0x00DD, 0xFF9E, 0x00DE, 0xFF9F, 0x00DF, 0xFFE0, 0x8191, + 0xFFE1, 0x8192, 0xFFE2, 0x81CA, 0xFFE3, 0x8150, 0xFFE4, 0xFA55, + 0xFFE5, 0x818F, 0, 0 +}; + +#if !_TINY_TABLE +static +const WCHAR sjis2uni[] = { +/* SJIS - Unicode, SJIS - Unicode, SJIS - Unicode, SJIS - Unicode, */ + 0x00A1, 0xFF61, 0x00A2, 0xFF62, 0x00A3, 0xFF63, 0x00A4, 0xFF64, + 0x00A5, 0xFF65, 0x00A6, 0xFF66, 0x00A7, 0xFF67, 0x00A8, 0xFF68, + 0x00A9, 0xFF69, 0x00AA, 0xFF6A, 0x00AB, 0xFF6B, 0x00AC, 0xFF6C, + 0x00AD, 0xFF6D, 0x00AE, 0xFF6E, 0x00AF, 0xFF6F, 0x00B0, 0xFF70, + 0x00B1, 0xFF71, 0x00B2, 0xFF72, 0x00B3, 0xFF73, 0x00B4, 0xFF74, + 0x00B5, 0xFF75, 0x00B6, 0xFF76, 0x00B7, 0xFF77, 0x00B8, 0xFF78, + 0x00B9, 0xFF79, 0x00BA, 0xFF7A, 0x00BB, 0xFF7B, 0x00BC, 0xFF7C, + 0x00BD, 0xFF7D, 0x00BE, 0xFF7E, 0x00BF, 0xFF7F, 0x00C0, 0xFF80, + 0x00C1, 0xFF81, 0x00C2, 0xFF82, 0x00C3, 0xFF83, 0x00C4, 0xFF84, + 0x00C5, 0xFF85, 0x00C6, 0xFF86, 0x00C7, 0xFF87, 0x00C8, 0xFF88, + 0x00C9, 0xFF89, 0x00CA, 0xFF8A, 0x00CB, 0xFF8B, 0x00CC, 0xFF8C, + 0x00CD, 0xFF8D, 0x00CE, 0xFF8E, 0x00CF, 0xFF8F, 0x00D0, 0xFF90, + 0x00D1, 0xFF91, 0x00D2, 0xFF92, 0x00D3, 0xFF93, 0x00D4, 0xFF94, + 0x00D5, 0xFF95, 0x00D6, 0xFF96, 0x00D7, 0xFF97, 0x00D8, 0xFF98, + 0x00D9, 0xFF99, 0x00DA, 0xFF9A, 0x00DB, 0xFF9B, 0x00DC, 0xFF9C, + 0x00DD, 0xFF9D, 0x00DE, 0xFF9E, 0x00DF, 0xFF9F, 0x8140, 0x3000, + 0x8141, 0x3001, 0x8142, 0x3002, 0x8143, 0xFF0C, 0x8144, 0xFF0E, + 0x8145, 0x30FB, 0x8146, 0xFF1A, 0x8147, 0xFF1B, 0x8148, 0xFF1F, + 0x8149, 0xFF01, 0x814A, 0x309B, 0x814B, 0x309C, 0x814C, 0x00B4, + 0x814D, 0xFF40, 0x814E, 0x00A8, 0x814F, 0xFF3E, 0x8150, 0xFFE3, + 0x8151, 0xFF3F, 0x8152, 0x30FD, 0x8153, 0x30FE, 0x8154, 0x309D, + 0x8155, 0x309E, 0x8156, 0x3003, 0x8157, 0x4EDD, 0x8158, 0x3005, + 0x8159, 0x3006, 0x815A, 0x3007, 0x815B, 0x30FC, 0x815C, 0x2015, + 0x815D, 0x2010, 0x815E, 0xFF0F, 0x815F, 0xFF3C, 0x8160, 0xFF5E, + 0x8161, 0x2225, 0x8162, 0xFF5C, 0x8163, 0x2026, 0x8164, 0x2025, + 0x8165, 0x2018, 0x8166, 0x2019, 0x8167, 0x201C, 0x8168, 0x201D, + 0x8169, 0xFF08, 0x816A, 0xFF09, 0x816B, 0x3014, 0x816C, 0x3015, + 0x816D, 0xFF3B, 0x816E, 0xFF3D, 0x816F, 0xFF5B, 0x8170, 0xFF5D, + 0x8171, 0x3008, 0x8172, 0x3009, 0x8173, 0x300A, 0x8174, 0x300B, + 0x8175, 0x300C, 0x8176, 0x300D, 0x8177, 0x300E, 0x8178, 0x300F, + 0x8179, 0x3010, 0x817A, 0x3011, 0x817B, 0xFF0B, 0x817C, 0xFF0D, + 0x817D, 0x00B1, 0x817E, 0x00D7, 0x8180, 0x00F7, 0x8181, 0xFF1D, + 0x8182, 0x2260, 0x8183, 0xFF1C, 0x8184, 0xFF1E, 0x8185, 0x2266, + 0x8186, 0x2267, 0x8187, 0x221E, 0x8188, 0x2234, 0x8189, 0x2642, + 0x818A, 0x2640, 0x818B, 0x00B0, 0x818C, 0x2032, 0x818D, 0x2033, + 0x818E, 0x2103, 0x818F, 0xFFE5, 0x8190, 0xFF04, 0x8191, 0xFFE0, + 0x8192, 0xFFE1, 0x8193, 0xFF05, 0x8194, 0xFF03, 0x8195, 0xFF06, + 0x8196, 0xFF0A, 0x8197, 0xFF20, 0x8198, 0x00A7, 0x8199, 0x2606, + 0x819A, 0x2605, 0x819B, 0x25CB, 0x819C, 0x25CF, 0x819D, 0x25CE, + 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0xEA50, 0x9DC4, 0xEA51, 0x9DC1, 0xEA52, 0x9DBB, 0xEA53, 0x9DB8, + 0xEA54, 0x9DBA, 0xEA55, 0x9DC6, 0xEA56, 0x9DCF, 0xEA57, 0x9DC2, + 0xEA58, 0x9DD9, 0xEA59, 0x9DD3, 0xEA5A, 0x9DF8, 0xEA5B, 0x9DE6, + 0xEA5C, 0x9DED, 0xEA5D, 0x9DEF, 0xEA5E, 0x9DFD, 0xEA5F, 0x9E1A, + 0xEA60, 0x9E1B, 0xEA61, 0x9E1E, 0xEA62, 0x9E75, 0xEA63, 0x9E79, + 0xEA64, 0x9E7D, 0xEA65, 0x9E81, 0xEA66, 0x9E88, 0xEA67, 0x9E8B, + 0xEA68, 0x9E8C, 0xEA69, 0x9E92, 0xEA6A, 0x9E95, 0xEA6B, 0x9E91, + 0xEA6C, 0x9E9D, 0xEA6D, 0x9EA5, 0xEA6E, 0x9EA9, 0xEA6F, 0x9EB8, + 0xEA70, 0x9EAA, 0xEA71, 0x9EAD, 0xEA72, 0x9761, 0xEA73, 0x9ECC, + 0xEA74, 0x9ECE, 0xEA75, 0x9ECF, 0xEA76, 0x9ED0, 0xEA77, 0x9ED4, + 0xEA78, 0x9EDC, 0xEA79, 0x9EDE, 0xEA7A, 0x9EDD, 0xEA7B, 0x9EE0, + 0xEA7C, 0x9EE5, 0xEA7D, 0x9EE8, 0xEA7E, 0x9EEF, 0xEA80, 0x9EF4, + 0xEA81, 0x9EF6, 0xEA82, 0x9EF7, 0xEA83, 0x9EF9, 0xEA84, 0x9EFB, + 0xEA85, 0x9EFC, 0xEA86, 0x9EFD, 0xEA87, 0x9F07, 0xEA88, 0x9F08, + 0xEA89, 0x76B7, 0xEA8A, 0x9F15, 0xEA8B, 0x9F21, 0xEA8C, 0x9F2C, + 0xEA8D, 0x9F3E, 0xEA8E, 0x9F4A, 0xEA8F, 0x9F52, 0xEA90, 0x9F54, + 0xEA91, 0x9F63, 0xEA92, 0x9F5F, 0xEA93, 0x9F60, 0xEA94, 0x9F61, + 0xEA95, 0x9F66, 0xEA96, 0x9F67, 0xEA97, 0x9F6C, 0xEA98, 0x9F6A, + 0xEA99, 0x9F77, 0xEA9A, 0x9F72, 0xEA9B, 0x9F76, 0xEA9C, 0x9F95, + 0xEA9D, 0x9F9C, 0xEA9E, 0x9FA0, 0xEA9F, 0x582F, 0xEAA0, 0x69C7, + 0xEAA1, 0x9059, 0xEAA2, 0x7464, 0xEAA3, 0x51DC, 0xEAA4, 0x7199, + 0xFA40, 0x2170, 0xFA41, 0x2171, 0xFA42, 0x2172, 0xFA43, 0x2173, + 0xFA44, 0x2174, 0xFA45, 0x2175, 0xFA46, 0x2176, 0xFA47, 0x2177, + 0xFA48, 0x2178, 0xFA49, 0x2179, 0xFA55, 0xFFE4, 0xFA56, 0xFF07, + 0xFA57, 0xFF02, 0xFA5C, 0x7E8A, 0xFA5D, 0x891C, 0xFA5E, 0x9348, + 0xFA5F, 0x9288, 0xFA60, 0x84DC, 0xFA61, 0x4FC9, 0xFA62, 0x70BB, + 0xFA63, 0x6631, 0xFA64, 0x68C8, 0xFA65, 0x92F9, 0xFA66, 0x66FB, + 0xFA67, 0x5F45, 0xFA68, 0x4E28, 0xFA69, 0x4EE1, 0xFA6A, 0x4EFC, + 0xFA6B, 0x4F00, 0xFA6C, 0x4F03, 0xFA6D, 0x4F39, 0xFA6E, 0x4F56, + 0xFA6F, 0x4F92, 0xFA70, 0x4F8A, 0xFA71, 0x4F9A, 0xFA72, 0x4F94, + 0xFA73, 0x4FCD, 0xFA74, 0x5040, 0xFA75, 0x5022, 0xFA76, 0x4FFF, + 0xFA77, 0x501E, 0xFA78, 0x5046, 0xFA79, 0x5070, 0xFA7A, 0x5042, + 0xFA7B, 0x5094, 0xFA7C, 0x50F4, 0xFA7D, 0x50D8, 0xFA7E, 0x514A, + 0xFA80, 0x5164, 0xFA81, 0x519D, 0xFA82, 0x51BE, 0xFA83, 0x51EC, + 0xFA84, 0x5215, 0xFA85, 0x529C, 0xFA86, 0x52A6, 0xFA87, 0x52C0, + 0xFA88, 0x52DB, 0xFA89, 0x5300, 0xFA8A, 0x5307, 0xFA8B, 0x5324, + 0xFA8C, 0x5372, 0xFA8D, 0x5393, 0xFA8E, 0x53B2, 0xFA8F, 0x53DD, + 0xFA90, 0xFA0E, 0xFA91, 0x549C, 0xFA92, 0x548A, 0xFA93, 0x54A9, + 0xFA94, 0x54FF, 0xFA95, 0x5586, 0xFA96, 0x5759, 0xFA97, 0x5765, + 0xFA98, 0x57AC, 0xFA99, 0x57C8, 0xFA9A, 0x57C7, 0xFA9B, 0xFA0F, + 0xFA9C, 0xFA10, 0xFA9D, 0x589E, 0xFA9E, 0x58B2, 0xFA9F, 0x590B, + 0xFAA0, 0x5953, 0xFAA1, 0x595B, 0xFAA2, 0x595D, 0xFAA3, 0x5963, + 0xFAA4, 0x59A4, 0xFAA5, 0x59BA, 0xFAA6, 0x5B56, 0xFAA7, 0x5BC0, + 0xFAA8, 0x752F, 0xFAA9, 0x5BD8, 0xFAAA, 0x5BEC, 0xFAAB, 0x5C1E, + 0xFAAC, 0x5CA6, 0xFAAD, 0x5CBA, 0xFAAE, 0x5CF5, 0xFAAF, 0x5D27, + 0xFAB0, 0x5D53, 0xFAB1, 0xFA11, 0xFAB2, 0x5D42, 0xFAB3, 0x5D6D, + 0xFAB4, 0x5DB8, 0xFAB5, 0x5DB9, 0xFAB6, 0x5DD0, 0xFAB7, 0x5F21, + 0xFAB8, 0x5F34, 0xFAB9, 0x5F67, 0xFABA, 0x5FB7, 0xFABB, 0x5FDE, + 0xFABC, 0x605D, 0xFABD, 0x6085, 0xFABE, 0x608A, 0xFABF, 0x60DE, + 0xFAC0, 0x60D5, 0xFAC1, 0x6120, 0xFAC2, 0x60F2, 0xFAC3, 0x6111, + 0xFAC4, 0x6137, 0xFAC5, 0x6130, 0xFAC6, 0x6198, 0xFAC7, 0x6213, + 0xFAC8, 0x62A6, 0xFAC9, 0x63F5, 0xFACA, 0x6460, 0xFACB, 0x649D, + 0xFACC, 0x64CE, 0xFACD, 0x654E, 0xFACE, 0x6600, 0xFACF, 0x6615, + 0xFAD0, 0x663B, 0xFAD1, 0x6609, 0xFAD2, 0x662E, 0xFAD3, 0x661E, + 0xFAD4, 0x6624, 0xFAD5, 0x6665, 0xFAD6, 0x6657, 0xFAD7, 0x6659, + 0xFAD8, 0xFA12, 0xFAD9, 0x6673, 0xFADA, 0x6699, 0xFADB, 0x66A0, + 0xFADC, 0x66B2, 0xFADD, 0x66BF, 0xFADE, 0x66FA, 0xFADF, 0x670E, + 0xFAE0, 0xF929, 0xFAE1, 0x6766, 0xFAE2, 0x67BB, 0xFAE3, 0x6852, + 0xFAE4, 0x67C0, 0xFAE5, 0x6801, 0xFAE6, 0x6844, 0xFAE7, 0x68CF, + 0xFAE8, 0xFA13, 0xFAE9, 0x6968, 0xFAEA, 0xFA14, 0xFAEB, 0x6998, + 0xFAEC, 0x69E2, 0xFAED, 0x6A30, 0xFAEE, 0x6A6B, 0xFAEF, 0x6A46, + 0xFAF0, 0x6A73, 0xFAF1, 0x6A7E, 0xFAF2, 0x6AE2, 0xFAF3, 0x6AE4, + 0xFAF4, 0x6BD6, 0xFAF5, 0x6C3F, 0xFAF6, 0x6C5C, 0xFAF7, 0x6C86, + 0xFAF8, 0x6C6F, 0xFAF9, 0x6CDA, 0xFAFA, 0x6D04, 0xFAFB, 0x6D87, + 0xFAFC, 0x6D6F, 0xFB40, 0x6D96, 0xFB41, 0x6DAC, 0xFB42, 0x6DCF, + 0xFB43, 0x6DF8, 0xFB44, 0x6DF2, 0xFB45, 0x6DFC, 0xFB46, 0x6E39, + 0xFB47, 0x6E5C, 0xFB48, 0x6E27, 0xFB49, 0x6E3C, 0xFB4A, 0x6EBF, + 0xFB4B, 0x6F88, 0xFB4C, 0x6FB5, 0xFB4D, 0x6FF5, 0xFB4E, 0x7005, + 0xFB4F, 0x7007, 0xFB50, 0x7028, 0xFB51, 0x7085, 0xFB52, 0x70AB, + 0xFB53, 0x710F, 0xFB54, 0x7104, 0xFB55, 0x715C, 0xFB56, 0x7146, + 0xFB57, 0x7147, 0xFB58, 0xFA15, 0xFB59, 0x71C1, 0xFB5A, 0x71FE, + 0xFB5B, 0x72B1, 0xFB5C, 0x72BE, 0xFB5D, 0x7324, 0xFB5E, 0xFA16, + 0xFB5F, 0x7377, 0xFB60, 0x73BD, 0xFB61, 0x73C9, 0xFB62, 0x73D6, + 0xFB63, 0x73E3, 0xFB64, 0x73D2, 0xFB65, 0x7407, 0xFB66, 0x73F5, + 0xFB67, 0x7426, 0xFB68, 0x742A, 0xFB69, 0x7429, 0xFB6A, 0x742E, + 0xFB6B, 0x7462, 0xFB6C, 0x7489, 0xFB6D, 0x749F, 0xFB6E, 0x7501, + 0xFB6F, 0x756F, 0xFB70, 0x7682, 0xFB71, 0x769C, 0xFB72, 0x769E, + 0xFB73, 0x769B, 0xFB74, 0x76A6, 0xFB75, 0xFA17, 0xFB76, 0x7746, + 0xFB77, 0x52AF, 0xFB78, 0x7821, 0xFB79, 0x784E, 0xFB7A, 0x7864, + 0xFB7B, 0x787A, 0xFB7C, 0x7930, 0xFB7D, 0xFA18, 0xFB7E, 0xFA19, + 0xFB80, 0xFA1A, 0xFB81, 0x7994, 0xFB82, 0xFA1B, 0xFB83, 0x799B, + 0xFB84, 0x7AD1, 0xFB85, 0x7AE7, 0xFB86, 0xFA1C, 0xFB87, 0x7AEB, + 0xFB88, 0x7B9E, 0xFB89, 0xFA1D, 0xFB8A, 0x7D48, 0xFB8B, 0x7D5C, + 0xFB8C, 0x7DB7, 0xFB8D, 0x7DA0, 0xFB8E, 0x7DD6, 0xFB8F, 0x7E52, + 0xFB90, 0x7F47, 0xFB91, 0x7FA1, 0xFB92, 0xFA1E, 0xFB93, 0x8301, + 0xFB94, 0x8362, 0xFB95, 0x837F, 0xFB96, 0x83C7, 0xFB97, 0x83F6, + 0xFB98, 0x8448, 0xFB99, 0x84B4, 0xFB9A, 0x8553, 0xFB9B, 0x8559, + 0xFB9C, 0x856B, 0xFB9D, 0xFA1F, 0xFB9E, 0x85B0, 0xFB9F, 0xFA20, + 0xFBA0, 0xFA21, 0xFBA1, 0x8807, 0xFBA2, 0x88F5, 0xFBA3, 0x8A12, + 0xFBA4, 0x8A37, 0xFBA5, 0x8A79, 0xFBA6, 0x8AA7, 0xFBA7, 0x8ABE, + 0xFBA8, 0x8ADF, 0xFBA9, 0xFA22, 0xFBAA, 0x8AF6, 0xFBAB, 0x8B53, + 0xFBAC, 0x8B7F, 0xFBAD, 0x8CF0, 0xFBAE, 0x8CF4, 0xFBAF, 0x8D12, + 0xFBB0, 0x8D76, 0xFBB1, 0xFA23, 0xFBB2, 0x8ECF, 0xFBB3, 0xFA24, + 0xFBB4, 0xFA25, 0xFBB5, 0x9067, 0xFBB6, 0x90DE, 0xFBB7, 0xFA26, + 0xFBB8, 0x9115, 0xFBB9, 0x9127, 0xFBBA, 0x91DA, 0xFBBB, 0x91D7, + 0xFBBC, 0x91DE, 0xFBBD, 0x91ED, 0xFBBE, 0x91EE, 0xFBBF, 0x91E4, + 0xFBC0, 0x91E5, 0xFBC1, 0x9206, 0xFBC2, 0x9210, 0xFBC3, 0x920A, + 0xFBC4, 0x923A, 0xFBC5, 0x9240, 0xFBC6, 0x923C, 0xFBC7, 0x924E, + 0xFBC8, 0x9259, 0xFBC9, 0x9251, 0xFBCA, 0x9239, 0xFBCB, 0x9267, + 0xFBCC, 0x92A7, 0xFBCD, 0x9277, 0xFBCE, 0x9278, 0xFBCF, 0x92E7, + 0xFBD0, 0x92D7, 0xFBD1, 0x92D9, 0xFBD2, 0x92D0, 0xFBD3, 0xFA27, + 0xFBD4, 0x92D5, 0xFBD5, 0x92E0, 0xFBD6, 0x92D3, 0xFBD7, 0x9325, + 0xFBD8, 0x9321, 0xFBD9, 0x92FB, 0xFBDA, 0xFA28, 0xFBDB, 0x931E, + 0xFBDC, 0x92FF, 0xFBDD, 0x931D, 0xFBDE, 0x9302, 0xFBDF, 0x9370, + 0xFBE0, 0x9357, 0xFBE1, 0x93A4, 0xFBE2, 0x93C6, 0xFBE3, 0x93DE, + 0xFBE4, 0x93F8, 0xFBE5, 0x9431, 0xFBE6, 0x9445, 0xFBE7, 0x9448, + 0xFBE8, 0x9592, 0xFBE9, 0xF9DC, 0xFBEA, 0xFA29, 0xFBEB, 0x969D, + 0xFBEC, 0x96AF, 0xFBED, 0x9733, 0xFBEE, 0x973B, 0xFBEF, 0x9743, + 0xFBF0, 0x974D, 0xFBF1, 0x974F, 0xFBF2, 0x9751, 0xFBF3, 0x9755, + 0xFBF4, 0x9857, 0xFBF5, 0x9865, 0xFBF6, 0xFA2A, 0xFBF7, 0xFA2B, + 0xFBF8, 0x9927, 0xFBF9, 0xFA2C, 0xFBFA, 0x999E, 0xFBFB, 0x9A4E, + 0xFBFC, 0x9AD9, 0xFC40, 0x9ADC, 0xFC41, 0x9B75, 0xFC42, 0x9B72, + 0xFC43, 0x9B8F, 0xFC44, 0x9BB1, 0xFC45, 0x9BBB, 0xFC46, 0x9C00, + 0xFC47, 0x9D70, 0xFC48, 0x9D6B, 0xFC49, 0xFA2D, 0xFC4A, 0x9E19, + 0xFC4B, 0x9ED1, 0, 0 +}; +#endif + + + +WCHAR ff_convert ( /* Converted code, 0 means conversion error */ + WCHAR chr, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEM code, 1: OEM code to Unicode */ +) +{ + const WCHAR *p; + WCHAR c; + int i, n, li, hi; + + + if (chr <= 0x80) { /* ASCII */ + c = chr; + } else { +#if !_TINY_TABLE + if (dir) { /* OEM code to unicode */ + p = sjis2uni; + hi = sizeof sjis2uni / 4 - 1; + } else { /* Unicode to OEM code */ + p = uni2sjis; + hi = sizeof uni2sjis / 4 - 1; + } + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (chr == p[i * 2]) break; + if (chr > p[i * 2]) + li = i; + else + hi = i; + } + c = n ? p[i * 2 + 1] : 0; +#else + if (dir) { /* OEM code to unicode (Incremental search)*/ + p = &uni2sjis[1]; + do { + c = *p; + p += 2; + } while (c && c != chr); + p -= 3; + c = *p; + } else { /* Unicode to OEM code */ + li = 0; hi = sizeof uni2sjis / 4 - 1; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (chr == uni2sjis[i * 2]) break; + if (chr > uni2sjis[i * 2]) + li = i; + else + hi = i; + } + c = n ? uni2sjis[i * 2 + 1] : 0; + } +#endif + } + + return c; +} + + + +WCHAR ff_wtoupper ( /* Returns upper converted character */ + WCHAR chr /* Unicode character to be upper converted (BMP only) */ +) +{ + /* Compressed upper conversion table */ + static const WCHAR cvt1[] = { /* U+0000 - U+0FFF */ + /* Basic Latin */ + 0x0061,0x031A, + /* Latin-1 Supplement */ + 0x00E0,0x0317, 0x00F8,0x0307, 0x00FF,0x0001,0x0178, + /* Latin Extended-A */ + 0x0100,0x0130, 0x0132,0x0106, 0x0139,0x0110, 0x014A,0x012E, 0x0179,0x0106, + /* Latin Extended-B */ + 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, + 0x01CD,0x0110, 0x01DD,0x0001,0x018E, 0x01DE,0x0112, 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, 0x01F8,0x0128, + 0x0222,0x0112, 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, 0x0246,0x010A, + /* IPA Extensions */ + 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, + /* Greek, Coptic */ + 0x037B,0x0003,0x03FD,0x03FE,0x03FF, 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, 0x03B1,0x0311, + 0x03C2,0x0002,0x03A3,0x03A3, 0x03C4,0x0308, 0x03CC,0x0003,0x038C,0x038E,0x038F, 0x03D8,0x0118, + 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, + /* Cyrillic */ + 0x0430,0x0320, 0x0450,0x0710, 0x0460,0x0122, 0x048A,0x0136, 0x04C1,0x010E, 0x04CF,0x0001,0x04C0, 0x04D0,0x0144, + /* Armenian */ + 0x0561,0x0426, + + 0x0000 + }; + static const WCHAR cvt2[] = { /* U+1000 - U+FFFF */ + /* Phonetic Extensions */ + 0x1D7D,0x0001,0x2C63, + /* Latin Extended Additional */ + 0x1E00,0x0196, 0x1EA0,0x015A, + /* Greek Extended */ + 0x1F00,0x0608, 0x1F10,0x0606, 0x1F20,0x0608, 0x1F30,0x0608, 0x1F40,0x0606, + 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, 0x1F60,0x0608, + 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, + 0x1F80,0x0608, 0x1F90,0x0608, 0x1FA0,0x0608, 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, + 0x1FCC,0x0001,0x1FC3, 0x1FD0,0x0602, 0x1FE0,0x0602, 0x1FE5,0x0001,0x1FEC, 0x1FF2,0x0001,0x1FFC, + /* Letterlike Symbols */ + 0x214E,0x0001,0x2132, + /* Number forms */ + 0x2170,0x0210, 0x2184,0x0001,0x2183, + /* Enclosed Alphanumerics */ + 0x24D0,0x051A, 0x2C30,0x042F, + /* Latin Extended-C */ + 0x2C60,0x0102, 0x2C67,0x0106, 0x2C75,0x0102, + /* Coptic */ + 0x2C80,0x0164, + /* Georgian Supplement */ + 0x2D00,0x0826, + /* Full-width */ + 0xFF41,0x031A, + + 0x0000 + }; + const WCHAR *p; + WCHAR bc, nc, cmd; + + + p = chr < 0x1000 ? cvt1 : cvt2; + for (;;) { + bc = *p++; /* Get block base */ + if (!bc || chr < bc) break; + nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ + if (chr < bc + nc) { /* In the block? */ + switch (cmd) { + case 0: chr = p[chr - bc]; break; /* Table conversion */ + case 1: chr -= (chr - bc) & 1; break; /* Case pairs */ + case 2: chr -= 16; break; /* Shift -16 */ + case 3: chr -= 32; break; /* Shift -32 */ + case 4: chr -= 48; break; /* Shift -48 */ + case 5: chr -= 26; break; /* Shift -26 */ + case 6: chr += 8; break; /* Shift +8 */ + case 7: chr -= 80; break; /* Shift -80 */ + case 8: chr -= 0x1C60; break; /* Shift -0x1C60 */ + } + break; + } + if (!cmd) p += nc; + } + + return chr; +} + diff --git a/radio/src/thirdparty/FatFs/option/cc936.c b/radio/src/thirdparty/FatFs/option/cc936.c index 3a5960f47..ec9e88668 100644 --- a/radio/src/thirdparty/FatFs/option/cc936.c +++ b/radio/src/thirdparty/FatFs/option/cc936.c @@ -1,11045 +1,11045 @@ -/*------------------------------------------------------------------------*/ -/* Unicode - OEM code bidirectional converter (C)ChaN, 2015 */ -/* CP936 (Simplified Chinese GBK) */ -/*------------------------------------------------------------------------*/ - -#include "../ff.h" - - -#if !_USE_LFN || _CODE_PAGE != 936 -#error This file is not needed in current configuration. Remove from the project. -#endif - -static -const WCHAR uni2oem[] = { -/* Unicode - OEM, Unicode - OEM, Unicode - OEM, Unicode - OEM */ - 0x00A4, 0xA1E8, 0x00A7, 0xA1EC, 0x00A8, 0xA1A7, 0x00B0, 0xA1E3, - 0x00B1, 0xA1C0, 0x00B7, 0xA1A4, 0x00D7, 0xA1C1, 0x00E0, 0xA8A4, - 0x00E1, 0xA8A2, 0x00E8, 0xA8A8, 0x00E9, 0xA8A6, 0x00EA, 0xA8BA, - 0x00EC, 0xA8AC, 0x00ED, 0xA8AA, 0x00F2, 0xA8B0, 0x00F3, 0xA8AE, - 0x00F7, 0xA1C2, 0x00F9, 0xA8B4, 0x00FA, 0xA8B2, 0x00FC, 0xA8B9, - 0x0101, 0xA8A1, 0x0113, 0xA8A5, 0x011B, 0xA8A7, 0x012B, 0xA8A9, - 0x0144, 0xA8BD, 0x0148, 0xA8BE, 0x014D, 0xA8AD, 0x016B, 0xA8B1, - 0x01CE, 0xA8A3, 0x01D0, 0xA8AB, 0x01D2, 0xA8AF, 0x01D4, 0xA8B3, - 0x01D6, 0xA8B5, 0x01D8, 0xA8B6, 0x01DA, 0xA8B7, 0x01DC, 0xA8B8, - 0x0251, 0xA8BB, 0x0261, 0xA8C0, 0x02C7, 0xA1A6, 0x02C9, 0xA1A5, - 0x02CA, 0xA840, 0x02CB, 0xA841, 0x02D9, 0xA842, 0x0391, 0xA6A1, - 0x0392, 0xA6A2, 0x0393, 0xA6A3, 0x0394, 0xA6A4, 0x0395, 0xA6A5, - 0x0396, 0xA6A6, 0x0397, 0xA6A7, 0x0398, 0xA6A8, 0x0399, 0xA6A9, - 0x039A, 0xA6AA, 0x039B, 0xA6AB, 0x039C, 0xA6AC, 0x039D, 0xA6AD, - 0x039E, 0xA6AE, 0x039F, 0xA6AF, 0x03A0, 0xA6B0, 0x03A1, 0xA6B1, - 0x03A3, 0xA6B2, 0x03A4, 0xA6B3, 0x03A5, 0xA6B4, 0x03A6, 0xA6B5, - 0x03A7, 0xA6B6, 0x03A8, 0xA6B7, 0x03A9, 0xA6B8, 0x03B1, 0xA6C1, - 0x03B2, 0xA6C2, 0x03B3, 0xA6C3, 0x03B4, 0xA6C4, 0x03B5, 0xA6C5, - 0x03B6, 0xA6C6, 0x03B7, 0xA6C7, 0x03B8, 0xA6C8, 0x03B9, 0xA6C9, - 0x03BA, 0xA6CA, 0x03BB, 0xA6CB, 0x03BC, 0xA6CC, 0x03BD, 0xA6CD, - 0x03BE, 0xA6CE, 0x03BF, 0xA6CF, 0x03C0, 0xA6D0, 0x03C1, 0xA6D1, - 0x03C3, 0xA6D2, 0x03C4, 0xA6D3, 0x03C5, 0xA6D4, 0x03C6, 0xA6D5, - 0x03C7, 0xA6D6, 0x03C8, 0xA6D7, 0x03C9, 0xA6D8, 0x0401, 0xA7A7, - 0x0410, 0xA7A1, 0x0411, 0xA7A2, 0x0412, 0xA7A3, 0x0413, 0xA7A4, - 0x0414, 0xA7A5, 0x0415, 0xA7A6, 0x0416, 0xA7A8, 0x0417, 0xA7A9, - 0x0418, 0xA7AA, 0x0419, 0xA7AB, 0x041A, 0xA7AC, 0x041B, 0xA7AD, - 0x041C, 0xA7AE, 0x041D, 0xA7AF, 0x041E, 0xA7B0, 0x041F, 0xA7B1, - 0x0420, 0xA7B2, 0x0421, 0xA7B3, 0x0422, 0xA7B4, 0x0423, 0xA7B5, - 0x0424, 0xA7B6, 0x0425, 0xA7B7, 0x0426, 0xA7B8, 0x0427, 0xA7B9, - 0x0428, 0xA7BA, 0x0429, 0xA7BB, 0x042A, 0xA7BC, 0x042B, 0xA7BD, - 0x042C, 0xA7BE, 0x042D, 0xA7BF, 0x042E, 0xA7C0, 0x042F, 0xA7C1, - 0x0430, 0xA7D1, 0x0431, 0xA7D2, 0x0432, 0xA7D3, 0x0433, 0xA7D4, - 0x0434, 0xA7D5, 0x0435, 0xA7D6, 0x0436, 0xA7D8, 0x0437, 0xA7D9, - 0x0438, 0xA7DA, 0x0439, 0xA7DB, 0x043A, 0xA7DC, 0x043B, 0xA7DD, - 0x043C, 0xA7DE, 0x043D, 0xA7DF, 0x043E, 0xA7E0, 0x043F, 0xA7E1, - 0x0440, 0xA7E2, 0x0441, 0xA7E3, 0x0442, 0xA7E4, 0x0443, 0xA7E5, - 0x0444, 0xA7E6, 0x0445, 0xA7E7, 0x0446, 0xA7E8, 0x0447, 0xA7E9, - 0x0448, 0xA7EA, 0x0449, 0xA7EB, 0x044A, 0xA7EC, 0x044B, 0xA7ED, - 0x044C, 0xA7EE, 0x044D, 0xA7EF, 0x044E, 0xA7F0, 0x044F, 0xA7F1, - 0x0451, 0xA7D7, 0x2010, 0xA95C, 0x2013, 0xA843, 0x2014, 0xA1AA, - 0x2015, 0xA844, 0x2016, 0xA1AC, 0x2018, 0xA1AE, 0x2019, 0xA1AF, - 0x201C, 0xA1B0, 0x201D, 0xA1B1, 0x2025, 0xA845, 0x2026, 0xA1AD, - 0x2030, 0xA1EB, 0x2032, 0xA1E4, 0x2033, 0xA1E5, 0x2035, 0xA846, - 0x203B, 0xA1F9, 0x20AC, 0x0080, 0x2103, 0xA1E6, 0x2105, 0xA847, - 0x2109, 0xA848, 0x2116, 0xA1ED, 0x2121, 0xA959, 0x2160, 0xA2F1, - 0x2161, 0xA2F2, 0x2162, 0xA2F3, 0x2163, 0xA2F4, 0x2164, 0xA2F5, - 0x2165, 0xA2F6, 0x2166, 0xA2F7, 0x2167, 0xA2F8, 0x2168, 0xA2F9, - 0x2169, 0xA2FA, 0x216A, 0xA2FB, 0x216B, 0xA2FC, 0x2170, 0xA2A1, - 0x2171, 0xA2A2, 0x2172, 0xA2A3, 0x2173, 0xA2A4, 0x2174, 0xA2A5, - 0x2175, 0xA2A6, 0x2176, 0xA2A7, 0x2177, 0xA2A8, 0x2178, 0xA2A9, - 0x2179, 0xA2AA, 0x2190, 0xA1FB, 0x2191, 0xA1FC, 0x2192, 0xA1FA, - 0x2193, 0xA1FD, 0x2196, 0xA849, 0x2197, 0xA84A, 0x2198, 0xA84B, - 0x2199, 0xA84C, 0x2208, 0xA1CA, 0x220F, 0xA1C7, 0x2211, 0xA1C6, - 0x2215, 0xA84D, 0x221A, 0xA1CC, 0x221D, 0xA1D8, 0x221E, 0xA1DE, - 0x221F, 0xA84E, 0x2220, 0xA1CF, 0x2223, 0xA84F, 0x2225, 0xA1CE, - 0x2227, 0xA1C4, 0x2228, 0xA1C5, 0x2229, 0xA1C9, 0x222A, 0xA1C8, - 0x222B, 0xA1D2, 0x222E, 0xA1D3, 0x2234, 0xA1E0, 0x2235, 0xA1DF, - 0x2236, 0xA1C3, 0x2237, 0xA1CB, 0x223D, 0xA1D7, 0x2248, 0xA1D6, - 0x224C, 0xA1D5, 0x2252, 0xA850, 0x2260, 0xA1D9, 0x2261, 0xA1D4, - 0x2264, 0xA1DC, 0x2265, 0xA1DD, 0x2266, 0xA851, 0x2267, 0xA852, - 0x226E, 0xA1DA, 0x226F, 0xA1DB, 0x2295, 0xA892, 0x2299, 0xA1D1, - 0x22A5, 0xA1CD, 0x22BF, 0xA853, 0x2312, 0xA1D0, 0x2460, 0xA2D9, - 0x2461, 0xA2DA, 0x2462, 0xA2DB, 0x2463, 0xA2DC, 0x2464, 0xA2DD, - 0x2465, 0xA2DE, 0x2466, 0xA2DF, 0x2467, 0xA2E0, 0x2468, 0xA2E1, - 0x2469, 0xA2E2, 0x2474, 0xA2C5, 0x2475, 0xA2C6, 0x2476, 0xA2C7, - 0x2477, 0xA2C8, 0x2478, 0xA2C9, 0x2479, 0xA2CA, 0x247A, 0xA2CB, - 0x247B, 0xA2CC, 0x247C, 0xA2CD, 0x247D, 0xA2CE, 0x247E, 0xA2CF, - 0x247F, 0xA2D0, 0x2480, 0xA2D1, 0x2481, 0xA2D2, 0x2482, 0xA2D3, - 0x2483, 0xA2D4, 0x2484, 0xA2D5, 0x2485, 0xA2D6, 0x2486, 0xA2D7, - 0x2487, 0xA2D8, 0x2488, 0xA2B1, 0x2489, 0xA2B2, 0x248A, 0xA2B3, - 0x248B, 0xA2B4, 0x248C, 0xA2B5, 0x248D, 0xA2B6, 0x248E, 0xA2B7, - 0x248F, 0xA2B8, 0x2490, 0xA2B9, 0x2491, 0xA2BA, 0x2492, 0xA2BB, - 0x2493, 0xA2BC, 0x2494, 0xA2BD, 0x2495, 0xA2BE, 0x2496, 0xA2BF, - 0x2497, 0xA2C0, 0x2498, 0xA2C1, 0x2499, 0xA2C2, 0x249A, 0xA2C3, - 0x249B, 0xA2C4, 0x2500, 0xA9A4, 0x2501, 0xA9A5, 0x2502, 0xA9A6, - 0x2503, 0xA9A7, 0x2504, 0xA9A8, 0x2505, 0xA9A9, 0x2506, 0xA9AA, - 0x2507, 0xA9AB, 0x2508, 0xA9AC, 0x2509, 0xA9AD, 0x250A, 0xA9AE, - 0x250B, 0xA9AF, 0x250C, 0xA9B0, 0x250D, 0xA9B1, 0x250E, 0xA9B2, - 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0x9F2B, 0xFC9C, 0x9F2C, 0xF7F8, 0x9F2D, 0xFC9D, 0x9F2E, 0xFC9E, - 0x9F2F, 0xF7F9, 0x9F30, 0xFC9F, 0x9F31, 0xFCA0, 0x9F32, 0xFD40, - 0x9F33, 0xFD41, 0x9F34, 0xFD42, 0x9F35, 0xFD43, 0x9F36, 0xFD44, - 0x9F37, 0xF7FB, 0x9F38, 0xFD45, 0x9F39, 0xF7FA, 0x9F3A, 0xFD46, - 0x9F3B, 0xB1C7, 0x9F3C, 0xFD47, 0x9F3D, 0xF7FC, 0x9F3E, 0xF7FD, - 0x9F3F, 0xFD48, 0x9F40, 0xFD49, 0x9F41, 0xFD4A, 0x9F42, 0xFD4B, - 0x9F43, 0xFD4C, 0x9F44, 0xF7FE, 0x9F45, 0xFD4D, 0x9F46, 0xFD4E, - 0x9F47, 0xFD4F, 0x9F48, 0xFD50, 0x9F49, 0xFD51, 0x9F4A, 0xFD52, - 0x9F4B, 0xFD53, 0x9F4C, 0xFD54, 0x9F4D, 0xFD55, 0x9F4E, 0xFD56, - 0x9F4F, 0xFD57, 0x9F50, 0xC6EB, 0x9F51, 0xECB4, 0x9F52, 0xFD58, - 0x9F53, 0xFD59, 0x9F54, 0xFD5A, 0x9F55, 0xFD5B, 0x9F56, 0xFD5C, - 0x9F57, 0xFD5D, 0x9F58, 0xFD5E, 0x9F59, 0xFD5F, 0x9F5A, 0xFD60, - 0x9F5B, 0xFD61, 0x9F5C, 0xFD62, 0x9F5D, 0xFD63, 0x9F5E, 0xFD64, - 0x9F5F, 0xFD65, 0x9F60, 0xFD66, 0x9F61, 0xFD67, 0x9F62, 0xFD68, - 0x9F63, 0xFD69, 0x9F64, 0xFD6A, 0x9F65, 0xFD6B, 0x9F66, 0xFD6C, - 0x9F67, 0xFD6D, 0x9F68, 0xFD6E, 0x9F69, 0xFD6F, 0x9F6A, 0xFD70, - 0x9F6B, 0xFD71, 0x9F6C, 0xFD72, 0x9F6D, 0xFD73, 0x9F6E, 0xFD74, - 0x9F6F, 0xFD75, 0x9F70, 0xFD76, 0x9F71, 0xFD77, 0x9F72, 0xFD78, - 0x9F73, 0xFD79, 0x9F74, 0xFD7A, 0x9F75, 0xFD7B, 0x9F76, 0xFD7C, - 0x9F77, 0xFD7D, 0x9F78, 0xFD7E, 0x9F79, 0xFD80, 0x9F7A, 0xFD81, - 0x9F7B, 0xFD82, 0x9F7C, 0xFD83, 0x9F7D, 0xFD84, 0x9F7E, 0xFD85, - 0x9F7F, 0xB3DD, 0x9F80, 0xF6B3, 0x9F81, 0xFD86, 0x9F82, 0xFD87, - 0x9F83, 0xF6B4, 0x9F84, 0xC1E4, 0x9F85, 0xF6B5, 0x9F86, 0xF6B6, - 0x9F87, 0xF6B7, 0x9F88, 0xF6B8, 0x9F89, 0xF6B9, 0x9F8A, 0xF6BA, - 0x9F8B, 0xC8A3, 0x9F8C, 0xF6BB, 0x9F8D, 0xFD88, 0x9F8E, 0xFD89, - 0x9F8F, 0xFD8A, 0x9F90, 0xFD8B, 0x9F91, 0xFD8C, 0x9F92, 0xFD8D, - 0x9F93, 0xFD8E, 0x9F94, 0xFD8F, 0x9F95, 0xFD90, 0x9F96, 0xFD91, - 0x9F97, 0xFD92, 0x9F98, 0xFD93, 0x9F99, 0xC1FA, 0x9F9A, 0xB9A8, - 0x9F9B, 0xEDE8, 0x9F9C, 0xFD94, 0x9F9D, 0xFD95, 0x9F9E, 0xFD96, - 0x9F9F, 0xB9EA, 0x9FA0, 0xD9DF, 0x9FA1, 0xFD97, 0x9FA2, 0xFD98, - 0x9FA3, 0xFD99, 0x9FA4, 0xFD9A, 0x9FA5, 0xFD9B, 0xF92C, 0xFD9C, - 0xF979, 0xFD9D, 0xF995, 0xFD9E, 0xF9E7, 0xFD9F, 0xF9F1, 0xFDA0, - 0xFA0C, 0xFE40, 0xFA0D, 0xFE41, 0xFA0E, 0xFE42, 0xFA0F, 0xFE43, - 0xFA11, 0xFE44, 0xFA13, 0xFE45, 0xFA14, 0xFE46, 0xFA18, 0xFE47, - 0xFA1F, 0xFE48, 0xFA20, 0xFE49, 0xFA21, 0xFE4A, 0xFA23, 0xFE4B, - 0xFA24, 0xFE4C, 0xFA27, 0xFE4D, 0xFA28, 0xFE4E, 0xFA29, 0xFE4F, - 0xFE30, 0xA955, 0xFE31, 0xA6F2, 0xFE33, 0xA6F4, 0xFE34, 0xA6F5, - 0xFE35, 0xA6E0, 0xFE36, 0xA6E1, 0xFE37, 0xA6F0, 0xFE38, 0xA6F1, - 0xFE39, 0xA6E2, 0xFE3A, 0xA6E3, 0xFE3B, 0xA6EE, 0xFE3C, 0xA6EF, - 0xFE3D, 0xA6E6, 0xFE3E, 0xA6E7, 0xFE3F, 0xA6E4, 0xFE40, 0xA6E5, - 0xFE41, 0xA6E8, 0xFE42, 0xA6E9, 0xFE43, 0xA6EA, 0xFE44, 0xA6EB, - 0xFE49, 0xA968, 0xFE4A, 0xA969, 0xFE4B, 0xA96A, 0xFE4C, 0xA96B, - 0xFE4D, 0xA96C, 0xFE4E, 0xA96D, 0xFE4F, 0xA96E, 0xFE50, 0xA96F, - 0xFE51, 0xA970, 0xFE52, 0xA971, 0xFE54, 0xA972, 0xFE55, 0xA973, - 0xFE56, 0xA974, 0xFE57, 0xA975, 0xFE59, 0xA976, 0xFE5A, 0xA977, - 0xFE5B, 0xA978, 0xFE5C, 0xA979, 0xFE5D, 0xA97A, 0xFE5E, 0xA97B, - 0xFE5F, 0xA97C, 0xFE60, 0xA97D, 0xFE61, 0xA97E, 0xFE62, 0xA980, - 0xFE63, 0xA981, 0xFE64, 0xA982, 0xFE65, 0xA983, 0xFE66, 0xA984, - 0xFE68, 0xA985, 0xFE69, 0xA986, 0xFE6A, 0xA987, 0xFE6B, 0xA988, - 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA1E7, - 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, - 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, - 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, - 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, - 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, - 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, - 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, - 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, - 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, - 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, - 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, - 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, - 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, - 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA3DC, - 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, - 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, - 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, - 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, - 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, - 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, - 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, - 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, - 0xFF5D, 0xA3FD, 0xFF5E, 0xA1AB, 0xFFE0, 0xA1E9, 0xFFE1, 0xA1EA, - 0xFFE2, 0xA956, 0xFFE3, 0xA3FE, 0xFFE4, 0xA957, 0xFFE5, 0xA3A4, - 0, 0 -}; - -static -const WCHAR oem2uni[] = { -/* OEM - Unicode, OEM - Unicode, OEM - Unicode, OEM - Unicode */ - 0x0080, 0x20AC, 0x8140, 0x4E02, 0x8141, 0x4E04, 0x8142, 0x4E05, - 0x8143, 0x4E06, 0x8144, 0x4E0F, 0x8145, 0x4E12, 0x8146, 0x4E17, - 0x8147, 0x4E1F, 0x8148, 0x4E20, 0x8149, 0x4E21, 0x814A, 0x4E23, - 0x814B, 0x4E26, 0x814C, 0x4E29, 0x814D, 0x4E2E, 0x814E, 0x4E2F, - 0x814F, 0x4E31, 0x8150, 0x4E33, 0x8151, 0x4E35, 0x8152, 0x4E37, - 0x8153, 0x4E3C, 0x8154, 0x4E40, 0x8155, 0x4E41, 0x8156, 0x4E42, - 0x8157, 0x4E44, 0x8158, 0x4E46, 0x8159, 0x4E4A, 0x815A, 0x4E51, - 0x815B, 0x4E55, 0x815C, 0x4E57, 0x815D, 0x4E5A, 0x815E, 0x4E5B, - 0x815F, 0x4E62, 0x8160, 0x4E63, 0x8161, 0x4E64, 0x8162, 0x4E65, - 0x8163, 0x4E67, 0x8164, 0x4E68, 0x8165, 0x4E6A, 0x8166, 0x4E6B, - 0x8167, 0x4E6C, 0x8168, 0x4E6D, 0x8169, 0x4E6E, 0x816A, 0x4E6F, - 0x816B, 0x4E72, 0x816C, 0x4E74, 0x816D, 0x4E75, 0x816E, 0x4E76, - 0x816F, 0x4E77, 0x8170, 0x4E78, 0x8171, 0x4E79, 0x8172, 0x4E7A, - 0x8173, 0x4E7B, 0x8174, 0x4E7C, 0x8175, 0x4E7D, 0x8176, 0x4E7F, - 0x8177, 0x4E80, 0x8178, 0x4E81, 0x8179, 0x4E82, 0x817A, 0x4E83, - 0x817B, 0x4E84, 0x817C, 0x4E85, 0x817D, 0x4E87, 0x817E, 0x4E8A, - 0x8180, 0x4E90, 0x8181, 0x4E96, 0x8182, 0x4E97, 0x8183, 0x4E99, - 0x8184, 0x4E9C, 0x8185, 0x4E9D, 0x8186, 0x4E9E, 0x8187, 0x4EA3, - 0x8188, 0x4EAA, 0x8189, 0x4EAF, 0x818A, 0x4EB0, 0x818B, 0x4EB1, - 0x818C, 0x4EB4, 0x818D, 0x4EB6, 0x818E, 0x4EB7, 0x818F, 0x4EB8, - 0x8190, 0x4EB9, 0x8191, 0x4EBC, 0x8192, 0x4EBD, 0x8193, 0x4EBE, - 0x8194, 0x4EC8, 0x8195, 0x4ECC, 0x8196, 0x4ECF, 0x8197, 0x4ED0, - 0x8198, 0x4ED2, 0x8199, 0x4EDA, 0x819A, 0x4EDB, 0x819B, 0x4EDC, - 0x819C, 0x4EE0, 0x819D, 0x4EE2, 0x819E, 0x4EE6, 0x819F, 0x4EE7, - 0x81A0, 0x4EE9, 0x81A1, 0x4EED, 0x81A2, 0x4EEE, 0x81A3, 0x4EEF, - 0x81A4, 0x4EF1, 0x81A5, 0x4EF4, 0x81A6, 0x4EF8, 0x81A7, 0x4EF9, - 0x81A8, 0x4EFA, 0x81A9, 0x4EFC, 0x81AA, 0x4EFE, 0x81AB, 0x4F00, - 0x81AC, 0x4F02, 0x81AD, 0x4F03, 0x81AE, 0x4F04, 0x81AF, 0x4F05, - 0x81B0, 0x4F06, 0x81B1, 0x4F07, 0x81B2, 0x4F08, 0x81B3, 0x4F0B, - 0x81B4, 0x4F0C, 0x81B5, 0x4F12, 0x81B6, 0x4F13, 0x81B7, 0x4F14, - 0x81B8, 0x4F15, 0x81B9, 0x4F16, 0x81BA, 0x4F1C, 0x81BB, 0x4F1D, - 0x81BC, 0x4F21, 0x81BD, 0x4F23, 0x81BE, 0x4F28, 0x81BF, 0x4F29, - 0x81C0, 0x4F2C, 0x81C1, 0x4F2D, 0x81C2, 0x4F2E, 0x81C3, 0x4F31, - 0x81C4, 0x4F33, 0x81C5, 0x4F35, 0x81C6, 0x4F37, 0x81C7, 0x4F39, - 0x81C8, 0x4F3B, 0x81C9, 0x4F3E, 0x81CA, 0x4F3F, 0x81CB, 0x4F40, - 0x81CC, 0x4F41, 0x81CD, 0x4F42, 0x81CE, 0x4F44, 0x81CF, 0x4F45, - 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0xFD60, 0x9F5A, 0xFD61, 0x9F5B, 0xFD62, 0x9F5C, 0xFD63, 0x9F5D, - 0xFD64, 0x9F5E, 0xFD65, 0x9F5F, 0xFD66, 0x9F60, 0xFD67, 0x9F61, - 0xFD68, 0x9F62, 0xFD69, 0x9F63, 0xFD6A, 0x9F64, 0xFD6B, 0x9F65, - 0xFD6C, 0x9F66, 0xFD6D, 0x9F67, 0xFD6E, 0x9F68, 0xFD6F, 0x9F69, - 0xFD70, 0x9F6A, 0xFD71, 0x9F6B, 0xFD72, 0x9F6C, 0xFD73, 0x9F6D, - 0xFD74, 0x9F6E, 0xFD75, 0x9F6F, 0xFD76, 0x9F70, 0xFD77, 0x9F71, - 0xFD78, 0x9F72, 0xFD79, 0x9F73, 0xFD7A, 0x9F74, 0xFD7B, 0x9F75, - 0xFD7C, 0x9F76, 0xFD7D, 0x9F77, 0xFD7E, 0x9F78, 0xFD80, 0x9F79, - 0xFD81, 0x9F7A, 0xFD82, 0x9F7B, 0xFD83, 0x9F7C, 0xFD84, 0x9F7D, - 0xFD85, 0x9F7E, 0xFD86, 0x9F81, 0xFD87, 0x9F82, 0xFD88, 0x9F8D, - 0xFD89, 0x9F8E, 0xFD8A, 0x9F8F, 0xFD8B, 0x9F90, 0xFD8C, 0x9F91, - 0xFD8D, 0x9F92, 0xFD8E, 0x9F93, 0xFD8F, 0x9F94, 0xFD90, 0x9F95, - 0xFD91, 0x9F96, 0xFD92, 0x9F97, 0xFD93, 0x9F98, 0xFD94, 0x9F9C, - 0xFD95, 0x9F9D, 0xFD96, 0x9F9E, 0xFD97, 0x9FA1, 0xFD98, 0x9FA2, - 0xFD99, 0x9FA3, 0xFD9A, 0x9FA4, 0xFD9B, 0x9FA5, 0xFD9C, 0xF92C, - 0xFD9D, 0xF979, 0xFD9E, 0xF995, 0xFD9F, 0xF9E7, 0xFDA0, 0xF9F1, - 0xFE40, 0xFA0C, 0xFE41, 0xFA0D, 0xFE42, 0xFA0E, 0xFE43, 0xFA0F, - 0xFE44, 0xFA11, 0xFE45, 0xFA13, 0xFE46, 0xFA14, 0xFE47, 0xFA18, - 0xFE48, 0xFA1F, 0xFE49, 0xFA20, 0xFE4A, 0xFA21, 0xFE4B, 0xFA23, - 0xFE4C, 0xFA24, 0xFE4D, 0xFA27, 0xFE4E, 0xFA28, 0xFE4F, 0xFA29, - 0, 0 -}; - - - -WCHAR ff_convert ( /* Converted code, 0 means conversion error */ - WCHAR chr, /* Character code to be converted */ - UINT dir /* 0: Unicode to OEM code, 1: OEM code to Unicode */ -) -{ - const WCHAR *p; - WCHAR c; - int i, n, li, hi; - - - if (chr < 0x80) { /* ASCII */ - c = chr; - } else { - if (dir) { /* OEM code to unicode */ - p = oem2uni; - hi = sizeof oem2uni / 4 - 1; - } else { /* Unicode to OEM code */ - p = uni2oem; - hi = sizeof uni2oem / 4 - 1; - } - li = 0; - for (n = 16; n; n--) { - i = li + (hi - li) / 2; - if (chr == p[i * 2]) break; - if (chr > p[i * 2]) - li = i; - else - hi = i; - } - c = n ? p[i * 2 + 1] : 0; - } - - return c; -} - - - -WCHAR ff_wtoupper ( /* Returns upper converted character */ - WCHAR chr /* Unicode character to be upper converted (BMP only) */ -) -{ - /* Compressed upper conversion table */ - static const WCHAR cvt1[] = { /* U+0000 - U+0FFF */ - /* Basic Latin */ - 0x0061,0x031A, - /* Latin-1 Supplement */ - 0x00E0,0x0317, 0x00F8,0x0307, 0x00FF,0x0001,0x0178, - /* Latin Extended-A */ - 0x0100,0x0130, 0x0132,0x0106, 0x0139,0x0110, 0x014A,0x012E, 0x0179,0x0106, - /* Latin Extended-B */ - 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, - 0x01CD,0x0110, 0x01DD,0x0001,0x018E, 0x01DE,0x0112, 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, 0x01F8,0x0128, - 0x0222,0x0112, 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, 0x0246,0x010A, - /* IPA Extensions */ - 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, - /* Greek, Coptic */ - 0x037B,0x0003,0x03FD,0x03FE,0x03FF, 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, 0x03B1,0x0311, - 0x03C2,0x0002,0x03A3,0x03A3, 0x03C4,0x0308, 0x03CC,0x0003,0x038C,0x038E,0x038F, 0x03D8,0x0118, - 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, - /* Cyrillic */ - 0x0430,0x0320, 0x0450,0x0710, 0x0460,0x0122, 0x048A,0x0136, 0x04C1,0x010E, 0x04CF,0x0001,0x04C0, 0x04D0,0x0144, - /* Armenian */ - 0x0561,0x0426, - - 0x0000 - }; - static const WCHAR cvt2[] = { /* U+1000 - U+FFFF */ - /* Phonetic Extensions */ - 0x1D7D,0x0001,0x2C63, - /* Latin Extended Additional */ - 0x1E00,0x0196, 0x1EA0,0x015A, - /* Greek Extended */ - 0x1F00,0x0608, 0x1F10,0x0606, 0x1F20,0x0608, 0x1F30,0x0608, 0x1F40,0x0606, - 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, 0x1F60,0x0608, - 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, - 0x1F80,0x0608, 0x1F90,0x0608, 0x1FA0,0x0608, 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, - 0x1FCC,0x0001,0x1FC3, 0x1FD0,0x0602, 0x1FE0,0x0602, 0x1FE5,0x0001,0x1FEC, 0x1FF2,0x0001,0x1FFC, - /* Letterlike Symbols */ - 0x214E,0x0001,0x2132, - /* Number forms */ - 0x2170,0x0210, 0x2184,0x0001,0x2183, - /* Enclosed Alphanumerics */ - 0x24D0,0x051A, 0x2C30,0x042F, - /* Latin Extended-C */ - 0x2C60,0x0102, 0x2C67,0x0106, 0x2C75,0x0102, - /* Coptic */ - 0x2C80,0x0164, - /* Georgian Supplement */ - 0x2D00,0x0826, - /* Full-width */ - 0xFF41,0x031A, - - 0x0000 - }; - const WCHAR *p; - WCHAR bc, nc, cmd; - - - p = chr < 0x1000 ? cvt1 : cvt2; - for (;;) { - bc = *p++; /* Get block base */ - if (!bc || chr < bc) break; - nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ - if (chr < bc + nc) { /* In the block? */ - switch (cmd) { - case 0: chr = p[chr - bc]; break; /* Table conversion */ - case 1: chr -= (chr - bc) & 1; break; /* Case pairs */ - case 2: chr -= 16; break; /* Shift -16 */ - case 3: chr -= 32; break; /* Shift -32 */ - case 4: chr -= 48; break; /* Shift -48 */ - case 5: chr -= 26; break; /* Shift -26 */ - case 6: chr += 8; break; /* Shift +8 */ - case 7: chr -= 80; break; /* Shift -80 */ - case 8: chr -= 0x1C60; break; /* Shift -0x1C60 */ - } - break; - } - if (!cmd) p += nc; - } - - return chr; -} - +/*------------------------------------------------------------------------*/ +/* Unicode - OEM code bidirectional converter (C)ChaN, 2015 */ +/* CP936 (Simplified Chinese GBK) */ +/*------------------------------------------------------------------------*/ + +#include "../ff.h" + + +#if !_USE_LFN || _CODE_PAGE != 936 +#error This file is not needed in current configuration. Remove from the project. +#endif + +static +const WCHAR uni2oem[] = { +/* Unicode - OEM, Unicode - OEM, Unicode - OEM, Unicode - OEM */ + 0x00A4, 0xA1E8, 0x00A7, 0xA1EC, 0x00A8, 0xA1A7, 0x00B0, 0xA1E3, + 0x00B1, 0xA1C0, 0x00B7, 0xA1A4, 0x00D7, 0xA1C1, 0x00E0, 0xA8A4, + 0x00E1, 0xA8A2, 0x00E8, 0xA8A8, 0x00E9, 0xA8A6, 0x00EA, 0xA8BA, + 0x00EC, 0xA8AC, 0x00ED, 0xA8AA, 0x00F2, 0xA8B0, 0x00F3, 0xA8AE, + 0x00F7, 0xA1C2, 0x00F9, 0xA8B4, 0x00FA, 0xA8B2, 0x00FC, 0xA8B9, + 0x0101, 0xA8A1, 0x0113, 0xA8A5, 0x011B, 0xA8A7, 0x012B, 0xA8A9, + 0x0144, 0xA8BD, 0x0148, 0xA8BE, 0x014D, 0xA8AD, 0x016B, 0xA8B1, + 0x01CE, 0xA8A3, 0x01D0, 0xA8AB, 0x01D2, 0xA8AF, 0x01D4, 0xA8B3, + 0x01D6, 0xA8B5, 0x01D8, 0xA8B6, 0x01DA, 0xA8B7, 0x01DC, 0xA8B8, + 0x0251, 0xA8BB, 0x0261, 0xA8C0, 0x02C7, 0xA1A6, 0x02C9, 0xA1A5, + 0x02CA, 0xA840, 0x02CB, 0xA841, 0x02D9, 0xA842, 0x0391, 0xA6A1, + 0x0392, 0xA6A2, 0x0393, 0xA6A3, 0x0394, 0xA6A4, 0x0395, 0xA6A5, + 0x0396, 0xA6A6, 0x0397, 0xA6A7, 0x0398, 0xA6A8, 0x0399, 0xA6A9, + 0x039A, 0xA6AA, 0x039B, 0xA6AB, 0x039C, 0xA6AC, 0x039D, 0xA6AD, + 0x039E, 0xA6AE, 0x039F, 0xA6AF, 0x03A0, 0xA6B0, 0x03A1, 0xA6B1, + 0x03A3, 0xA6B2, 0x03A4, 0xA6B3, 0x03A5, 0xA6B4, 0x03A6, 0xA6B5, + 0x03A7, 0xA6B6, 0x03A8, 0xA6B7, 0x03A9, 0xA6B8, 0x03B1, 0xA6C1, + 0x03B2, 0xA6C2, 0x03B3, 0xA6C3, 0x03B4, 0xA6C4, 0x03B5, 0xA6C5, + 0x03B6, 0xA6C6, 0x03B7, 0xA6C7, 0x03B8, 0xA6C8, 0x03B9, 0xA6C9, + 0x03BA, 0xA6CA, 0x03BB, 0xA6CB, 0x03BC, 0xA6CC, 0x03BD, 0xA6CD, + 0x03BE, 0xA6CE, 0x03BF, 0xA6CF, 0x03C0, 0xA6D0, 0x03C1, 0xA6D1, + 0x03C3, 0xA6D2, 0x03C4, 0xA6D3, 0x03C5, 0xA6D4, 0x03C6, 0xA6D5, + 0x03C7, 0xA6D6, 0x03C8, 0xA6D7, 0x03C9, 0xA6D8, 0x0401, 0xA7A7, + 0x0410, 0xA7A1, 0x0411, 0xA7A2, 0x0412, 0xA7A3, 0x0413, 0xA7A4, + 0x0414, 0xA7A5, 0x0415, 0xA7A6, 0x0416, 0xA7A8, 0x0417, 0xA7A9, + 0x0418, 0xA7AA, 0x0419, 0xA7AB, 0x041A, 0xA7AC, 0x041B, 0xA7AD, + 0x041C, 0xA7AE, 0x041D, 0xA7AF, 0x041E, 0xA7B0, 0x041F, 0xA7B1, + 0x0420, 0xA7B2, 0x0421, 0xA7B3, 0x0422, 0xA7B4, 0x0423, 0xA7B5, + 0x0424, 0xA7B6, 0x0425, 0xA7B7, 0x0426, 0xA7B8, 0x0427, 0xA7B9, + 0x0428, 0xA7BA, 0x0429, 0xA7BB, 0x042A, 0xA7BC, 0x042B, 0xA7BD, + 0x042C, 0xA7BE, 0x042D, 0xA7BF, 0x042E, 0xA7C0, 0x042F, 0xA7C1, + 0x0430, 0xA7D1, 0x0431, 0xA7D2, 0x0432, 0xA7D3, 0x0433, 0xA7D4, + 0x0434, 0xA7D5, 0x0435, 0xA7D6, 0x0436, 0xA7D8, 0x0437, 0xA7D9, + 0x0438, 0xA7DA, 0x0439, 0xA7DB, 0x043A, 0xA7DC, 0x043B, 0xA7DD, + 0x043C, 0xA7DE, 0x043D, 0xA7DF, 0x043E, 0xA7E0, 0x043F, 0xA7E1, + 0x0440, 0xA7E2, 0x0441, 0xA7E3, 0x0442, 0xA7E4, 0x0443, 0xA7E5, + 0x0444, 0xA7E6, 0x0445, 0xA7E7, 0x0446, 0xA7E8, 0x0447, 0xA7E9, + 0x0448, 0xA7EA, 0x0449, 0xA7EB, 0x044A, 0xA7EC, 0x044B, 0xA7ED, + 0x044C, 0xA7EE, 0x044D, 0xA7EF, 0x044E, 0xA7F0, 0x044F, 0xA7F1, + 0x0451, 0xA7D7, 0x2010, 0xA95C, 0x2013, 0xA843, 0x2014, 0xA1AA, + 0x2015, 0xA844, 0x2016, 0xA1AC, 0x2018, 0xA1AE, 0x2019, 0xA1AF, + 0x201C, 0xA1B0, 0x201D, 0xA1B1, 0x2025, 0xA845, 0x2026, 0xA1AD, + 0x2030, 0xA1EB, 0x2032, 0xA1E4, 0x2033, 0xA1E5, 0x2035, 0xA846, + 0x203B, 0xA1F9, 0x20AC, 0x0080, 0x2103, 0xA1E6, 0x2105, 0xA847, + 0x2109, 0xA848, 0x2116, 0xA1ED, 0x2121, 0xA959, 0x2160, 0xA2F1, + 0x2161, 0xA2F2, 0x2162, 0xA2F3, 0x2163, 0xA2F4, 0x2164, 0xA2F5, + 0x2165, 0xA2F6, 0x2166, 0xA2F7, 0x2167, 0xA2F8, 0x2168, 0xA2F9, + 0x2169, 0xA2FA, 0x216A, 0xA2FB, 0x216B, 0xA2FC, 0x2170, 0xA2A1, + 0x2171, 0xA2A2, 0x2172, 0xA2A3, 0x2173, 0xA2A4, 0x2174, 0xA2A5, + 0x2175, 0xA2A6, 0x2176, 0xA2A7, 0x2177, 0xA2A8, 0x2178, 0xA2A9, + 0x2179, 0xA2AA, 0x2190, 0xA1FB, 0x2191, 0xA1FC, 0x2192, 0xA1FA, + 0x2193, 0xA1FD, 0x2196, 0xA849, 0x2197, 0xA84A, 0x2198, 0xA84B, + 0x2199, 0xA84C, 0x2208, 0xA1CA, 0x220F, 0xA1C7, 0x2211, 0xA1C6, + 0x2215, 0xA84D, 0x221A, 0xA1CC, 0x221D, 0xA1D8, 0x221E, 0xA1DE, + 0x221F, 0xA84E, 0x2220, 0xA1CF, 0x2223, 0xA84F, 0x2225, 0xA1CE, + 0x2227, 0xA1C4, 0x2228, 0xA1C5, 0x2229, 0xA1C9, 0x222A, 0xA1C8, + 0x222B, 0xA1D2, 0x222E, 0xA1D3, 0x2234, 0xA1E0, 0x2235, 0xA1DF, + 0x2236, 0xA1C3, 0x2237, 0xA1CB, 0x223D, 0xA1D7, 0x2248, 0xA1D6, + 0x224C, 0xA1D5, 0x2252, 0xA850, 0x2260, 0xA1D9, 0x2261, 0xA1D4, + 0x2264, 0xA1DC, 0x2265, 0xA1DD, 0x2266, 0xA851, 0x2267, 0xA852, + 0x226E, 0xA1DA, 0x226F, 0xA1DB, 0x2295, 0xA892, 0x2299, 0xA1D1, + 0x22A5, 0xA1CD, 0x22BF, 0xA853, 0x2312, 0xA1D0, 0x2460, 0xA2D9, + 0x2461, 0xA2DA, 0x2462, 0xA2DB, 0x2463, 0xA2DC, 0x2464, 0xA2DD, + 0x2465, 0xA2DE, 0x2466, 0xA2DF, 0x2467, 0xA2E0, 0x2468, 0xA2E1, + 0x2469, 0xA2E2, 0x2474, 0xA2C5, 0x2475, 0xA2C6, 0x2476, 0xA2C7, + 0x2477, 0xA2C8, 0x2478, 0xA2C9, 0x2479, 0xA2CA, 0x247A, 0xA2CB, + 0x247B, 0xA2CC, 0x247C, 0xA2CD, 0x247D, 0xA2CE, 0x247E, 0xA2CF, + 0x247F, 0xA2D0, 0x2480, 0xA2D1, 0x2481, 0xA2D2, 0x2482, 0xA2D3, + 0x2483, 0xA2D4, 0x2484, 0xA2D5, 0x2485, 0xA2D6, 0x2486, 0xA2D7, + 0x2487, 0xA2D8, 0x2488, 0xA2B1, 0x2489, 0xA2B2, 0x248A, 0xA2B3, + 0x248B, 0xA2B4, 0x248C, 0xA2B5, 0x248D, 0xA2B6, 0x248E, 0xA2B7, + 0x248F, 0xA2B8, 0x2490, 0xA2B9, 0x2491, 0xA2BA, 0x2492, 0xA2BB, + 0x2493, 0xA2BC, 0x2494, 0xA2BD, 0x2495, 0xA2BE, 0x2496, 0xA2BF, + 0x2497, 0xA2C0, 0x2498, 0xA2C1, 0x2499, 0xA2C2, 0x249A, 0xA2C3, + 0x249B, 0xA2C4, 0x2500, 0xA9A4, 0x2501, 0xA9A5, 0x2502, 0xA9A6, + 0x2503, 0xA9A7, 0x2504, 0xA9A8, 0x2505, 0xA9A9, 0x2506, 0xA9AA, + 0x2507, 0xA9AB, 0x2508, 0xA9AC, 0x2509, 0xA9AD, 0x250A, 0xA9AE, + 0x250B, 0xA9AF, 0x250C, 0xA9B0, 0x250D, 0xA9B1, 0x250E, 0xA9B2, + 0x250F, 0xA9B3, 0x2510, 0xA9B4, 0x2511, 0xA9B5, 0x2512, 0xA9B6, + 0x2513, 0xA9B7, 0x2514, 0xA9B8, 0x2515, 0xA9B9, 0x2516, 0xA9BA, + 0x2517, 0xA9BB, 0x2518, 0xA9BC, 0x2519, 0xA9BD, 0x251A, 0xA9BE, + 0x251B, 0xA9BF, 0x251C, 0xA9C0, 0x251D, 0xA9C1, 0x251E, 0xA9C2, + 0x251F, 0xA9C3, 0x2520, 0xA9C4, 0x2521, 0xA9C5, 0x2522, 0xA9C6, + 0x2523, 0xA9C7, 0x2524, 0xA9C8, 0x2525, 0xA9C9, 0x2526, 0xA9CA, + 0x2527, 0xA9CB, 0x2528, 0xA9CC, 0x2529, 0xA9CD, 0x252A, 0xA9CE, + 0x252B, 0xA9CF, 0x252C, 0xA9D0, 0x252D, 0xA9D1, 0x252E, 0xA9D2, + 0x252F, 0xA9D3, 0x2530, 0xA9D4, 0x2531, 0xA9D5, 0x2532, 0xA9D6, + 0x2533, 0xA9D7, 0x2534, 0xA9D8, 0x2535, 0xA9D9, 0x2536, 0xA9DA, + 0x2537, 0xA9DB, 0x2538, 0xA9DC, 0x2539, 0xA9DD, 0x253A, 0xA9DE, + 0x253B, 0xA9DF, 0x253C, 0xA9E0, 0x253D, 0xA9E1, 0x253E, 0xA9E2, + 0x253F, 0xA9E3, 0x2540, 0xA9E4, 0x2541, 0xA9E5, 0x2542, 0xA9E6, + 0x2543, 0xA9E7, 0x2544, 0xA9E8, 0x2545, 0xA9E9, 0x2546, 0xA9EA, + 0x2547, 0xA9EB, 0x2548, 0xA9EC, 0x2549, 0xA9ED, 0x254A, 0xA9EE, + 0x254B, 0xA9EF, 0x2550, 0xA854, 0x2551, 0xA855, 0x2552, 0xA856, + 0x2553, 0xA857, 0x2554, 0xA858, 0x2555, 0xA859, 0x2556, 0xA85A, + 0x2557, 0xA85B, 0x2558, 0xA85C, 0x2559, 0xA85D, 0x255A, 0xA85E, + 0x255B, 0xA85F, 0x255C, 0xA860, 0x255D, 0xA861, 0x255E, 0xA862, + 0x255F, 0xA863, 0x2560, 0xA864, 0x2561, 0xA865, 0x2562, 0xA866, + 0x2563, 0xA867, 0x2564, 0xA868, 0x2565, 0xA869, 0x2566, 0xA86A, + 0x2567, 0xA86B, 0x2568, 0xA86C, 0x2569, 0xA86D, 0x256A, 0xA86E, + 0x256B, 0xA86F, 0x256C, 0xA870, 0x256D, 0xA871, 0x256E, 0xA872, + 0x256F, 0xA873, 0x2570, 0xA874, 0x2571, 0xA875, 0x2572, 0xA876, + 0x2573, 0xA877, 0x2581, 0xA878, 0x2582, 0xA879, 0x2583, 0xA87A, + 0x2584, 0xA87B, 0x2585, 0xA87C, 0x2586, 0xA87D, 0x2587, 0xA87E, + 0x2588, 0xA880, 0x2589, 0xA881, 0x258A, 0xA882, 0x258B, 0xA883, + 0x258C, 0xA884, 0x258D, 0xA885, 0x258E, 0xA886, 0x258F, 0xA887, + 0x2593, 0xA888, 0x2594, 0xA889, 0x2595, 0xA88A, 0x25A0, 0xA1F6, + 0x25A1, 0xA1F5, 0x25B2, 0xA1F8, 0x25B3, 0xA1F7, 0x25BC, 0xA88B, + 0x25BD, 0xA88C, 0x25C6, 0xA1F4, 0x25C7, 0xA1F3, 0x25CB, 0xA1F0, + 0x25CE, 0xA1F2, 0x25CF, 0xA1F1, 0x25E2, 0xA88D, 0x25E3, 0xA88E, + 0x25E4, 0xA88F, 0x25E5, 0xA890, 0x2605, 0xA1EF, 0x2606, 0xA1EE, + 0x2609, 0xA891, 0x2640, 0xA1E2, 0x2642, 0xA1E1, 0x3000, 0xA1A1, + 0x3001, 0xA1A2, 0x3002, 0xA1A3, 0x3003, 0xA1A8, 0x3005, 0xA1A9, + 0x3006, 0xA965, 0x3007, 0xA996, 0x3008, 0xA1B4, 0x3009, 0xA1B5, + 0x300A, 0xA1B6, 0x300B, 0xA1B7, 0x300C, 0xA1B8, 0x300D, 0xA1B9, + 0x300E, 0xA1BA, 0x300F, 0xA1BB, 0x3010, 0xA1BE, 0x3011, 0xA1BF, + 0x3012, 0xA893, 0x3013, 0xA1FE, 0x3014, 0xA1B2, 0x3015, 0xA1B3, + 0x3016, 0xA1BC, 0x3017, 0xA1BD, 0x301D, 0xA894, 0x301E, 0xA895, + 0x3021, 0xA940, 0x3022, 0xA941, 0x3023, 0xA942, 0x3024, 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0xA6EE, 0xFE3C, 0xA6EF, + 0xFE3D, 0xA6E6, 0xFE3E, 0xA6E7, 0xFE3F, 0xA6E4, 0xFE40, 0xA6E5, + 0xFE41, 0xA6E8, 0xFE42, 0xA6E9, 0xFE43, 0xA6EA, 0xFE44, 0xA6EB, + 0xFE49, 0xA968, 0xFE4A, 0xA969, 0xFE4B, 0xA96A, 0xFE4C, 0xA96B, + 0xFE4D, 0xA96C, 0xFE4E, 0xA96D, 0xFE4F, 0xA96E, 0xFE50, 0xA96F, + 0xFE51, 0xA970, 0xFE52, 0xA971, 0xFE54, 0xA972, 0xFE55, 0xA973, + 0xFE56, 0xA974, 0xFE57, 0xA975, 0xFE59, 0xA976, 0xFE5A, 0xA977, + 0xFE5B, 0xA978, 0xFE5C, 0xA979, 0xFE5D, 0xA97A, 0xFE5E, 0xA97B, + 0xFE5F, 0xA97C, 0xFE60, 0xA97D, 0xFE61, 0xA97E, 0xFE62, 0xA980, + 0xFE63, 0xA981, 0xFE64, 0xA982, 0xFE65, 0xA983, 0xFE66, 0xA984, + 0xFE68, 0xA985, 0xFE69, 0xA986, 0xFE6A, 0xA987, 0xFE6B, 0xA988, + 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA1E7, + 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, + 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, + 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, + 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, + 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, + 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, + 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, + 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, + 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, + 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, + 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, + 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, + 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, + 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA3DC, + 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, + 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, + 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, + 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, + 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, + 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, + 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, + 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, + 0xFF5D, 0xA3FD, 0xFF5E, 0xA1AB, 0xFFE0, 0xA1E9, 0xFFE1, 0xA1EA, + 0xFFE2, 0xA956, 0xFFE3, 0xA3FE, 0xFFE4, 0xA957, 0xFFE5, 0xA3A4, + 0, 0 +}; + +static +const WCHAR oem2uni[] = { +/* OEM - Unicode, OEM - Unicode, OEM - Unicode, OEM - Unicode */ + 0x0080, 0x20AC, 0x8140, 0x4E02, 0x8141, 0x4E04, 0x8142, 0x4E05, + 0x8143, 0x4E06, 0x8144, 0x4E0F, 0x8145, 0x4E12, 0x8146, 0x4E17, + 0x8147, 0x4E1F, 0x8148, 0x4E20, 0x8149, 0x4E21, 0x814A, 0x4E23, + 0x814B, 0x4E26, 0x814C, 0x4E29, 0x814D, 0x4E2E, 0x814E, 0x4E2F, + 0x814F, 0x4E31, 0x8150, 0x4E33, 0x8151, 0x4E35, 0x8152, 0x4E37, + 0x8153, 0x4E3C, 0x8154, 0x4E40, 0x8155, 0x4E41, 0x8156, 0x4E42, + 0x8157, 0x4E44, 0x8158, 0x4E46, 0x8159, 0x4E4A, 0x815A, 0x4E51, + 0x815B, 0x4E55, 0x815C, 0x4E57, 0x815D, 0x4E5A, 0x815E, 0x4E5B, + 0x815F, 0x4E62, 0x8160, 0x4E63, 0x8161, 0x4E64, 0x8162, 0x4E65, + 0x8163, 0x4E67, 0x8164, 0x4E68, 0x8165, 0x4E6A, 0x8166, 0x4E6B, + 0x8167, 0x4E6C, 0x8168, 0x4E6D, 0x8169, 0x4E6E, 0x816A, 0x4E6F, + 0x816B, 0x4E72, 0x816C, 0x4E74, 0x816D, 0x4E75, 0x816E, 0x4E76, + 0x816F, 0x4E77, 0x8170, 0x4E78, 0x8171, 0x4E79, 0x8172, 0x4E7A, + 0x8173, 0x4E7B, 0x8174, 0x4E7C, 0x8175, 0x4E7D, 0x8176, 0x4E7F, + 0x8177, 0x4E80, 0x8178, 0x4E81, 0x8179, 0x4E82, 0x817A, 0x4E83, + 0x817B, 0x4E84, 0x817C, 0x4E85, 0x817D, 0x4E87, 0x817E, 0x4E8A, + 0x8180, 0x4E90, 0x8181, 0x4E96, 0x8182, 0x4E97, 0x8183, 0x4E99, + 0x8184, 0x4E9C, 0x8185, 0x4E9D, 0x8186, 0x4E9E, 0x8187, 0x4EA3, + 0x8188, 0x4EAA, 0x8189, 0x4EAF, 0x818A, 0x4EB0, 0x818B, 0x4EB1, + 0x818C, 0x4EB4, 0x818D, 0x4EB6, 0x818E, 0x4EB7, 0x818F, 0x4EB8, + 0x8190, 0x4EB9, 0x8191, 0x4EBC, 0x8192, 0x4EBD, 0x8193, 0x4EBE, + 0x8194, 0x4EC8, 0x8195, 0x4ECC, 0x8196, 0x4ECF, 0x8197, 0x4ED0, + 0x8198, 0x4ED2, 0x8199, 0x4EDA, 0x819A, 0x4EDB, 0x819B, 0x4EDC, + 0x819C, 0x4EE0, 0x819D, 0x4EE2, 0x819E, 0x4EE6, 0x819F, 0x4EE7, + 0x81A0, 0x4EE9, 0x81A1, 0x4EED, 0x81A2, 0x4EEE, 0x81A3, 0x4EEF, + 0x81A4, 0x4EF1, 0x81A5, 0x4EF4, 0x81A6, 0x4EF8, 0x81A7, 0x4EF9, + 0x81A8, 0x4EFA, 0x81A9, 0x4EFC, 0x81AA, 0x4EFE, 0x81AB, 0x4F00, + 0x81AC, 0x4F02, 0x81AD, 0x4F03, 0x81AE, 0x4F04, 0x81AF, 0x4F05, + 0x81B0, 0x4F06, 0x81B1, 0x4F07, 0x81B2, 0x4F08, 0x81B3, 0x4F0B, + 0x81B4, 0x4F0C, 0x81B5, 0x4F12, 0x81B6, 0x4F13, 0x81B7, 0x4F14, + 0x81B8, 0x4F15, 0x81B9, 0x4F16, 0x81BA, 0x4F1C, 0x81BB, 0x4F1D, + 0x81BC, 0x4F21, 0x81BD, 0x4F23, 0x81BE, 0x4F28, 0x81BF, 0x4F29, + 0x81C0, 0x4F2C, 0x81C1, 0x4F2D, 0x81C2, 0x4F2E, 0x81C3, 0x4F31, + 0x81C4, 0x4F33, 0x81C5, 0x4F35, 0x81C6, 0x4F37, 0x81C7, 0x4F39, + 0x81C8, 0x4F3B, 0x81C9, 0x4F3E, 0x81CA, 0x4F3F, 0x81CB, 0x4F40, + 0x81CC, 0x4F41, 0x81CD, 0x4F42, 0x81CE, 0x4F44, 0x81CF, 0x4F45, + 0x81D0, 0x4F47, 0x81D1, 0x4F48, 0x81D2, 0x4F49, 0x81D3, 0x4F4A, + 0x81D4, 0x4F4B, 0x81D5, 0x4F4C, 0x81D6, 0x4F52, 0x81D7, 0x4F54, + 0x81D8, 0x4F56, 0x81D9, 0x4F61, 0x81DA, 0x4F62, 0x81DB, 0x4F66, + 0x81DC, 0x4F68, 0x81DD, 0x4F6A, 0x81DE, 0x4F6B, 0x81DF, 0x4F6D, + 0x81E0, 0x4F6E, 0x81E1, 0x4F71, 0x81E2, 0x4F72, 0x81E3, 0x4F75, + 0x81E4, 0x4F77, 0x81E5, 0x4F78, 0x81E6, 0x4F79, 0x81E7, 0x4F7A, + 0x81E8, 0x4F7D, 0x81E9, 0x4F80, 0x81EA, 0x4F81, 0x81EB, 0x4F82, + 0x81EC, 0x4F85, 0x81ED, 0x4F86, 0x81EE, 0x4F87, 0x81EF, 0x4F8A, + 0x81F0, 0x4F8C, 0x81F1, 0x4F8E, 0x81F2, 0x4F90, 0x81F3, 0x4F92, + 0x81F4, 0x4F93, 0x81F5, 0x4F95, 0x81F6, 0x4F96, 0x81F7, 0x4F98, + 0x81F8, 0x4F99, 0x81F9, 0x4F9A, 0x81FA, 0x4F9C, 0x81FB, 0x4F9E, + 0x81FC, 0x4F9F, 0x81FD, 0x4FA1, 0x81FE, 0x4FA2, 0x8240, 0x4FA4, + 0x8241, 0x4FAB, 0x8242, 0x4FAD, 0x8243, 0x4FB0, 0x8244, 0x4FB1, + 0x8245, 0x4FB2, 0x8246, 0x4FB3, 0x8247, 0x4FB4, 0x8248, 0x4FB6, + 0x8249, 0x4FB7, 0x824A, 0x4FB8, 0x824B, 0x4FB9, 0x824C, 0x4FBA, + 0x824D, 0x4FBB, 0x824E, 0x4FBC, 0x824F, 0x4FBD, 0x8250, 0x4FBE, + 0x8251, 0x4FC0, 0x8252, 0x4FC1, 0x8253, 0x4FC2, 0x8254, 0x4FC6, + 0x8255, 0x4FC7, 0x8256, 0x4FC8, 0x8257, 0x4FC9, 0x8258, 0x4FCB, + 0x8259, 0x4FCC, 0x825A, 0x4FCD, 0x825B, 0x4FD2, 0x825C, 0x4FD3, + 0x825D, 0x4FD4, 0x825E, 0x4FD5, 0x825F, 0x4FD6, 0x8260, 0x4FD9, + 0x8261, 0x4FDB, 0x8262, 0x4FE0, 0x8263, 0x4FE2, 0x8264, 0x4FE4, + 0x8265, 0x4FE5, 0x8266, 0x4FE7, 0x8267, 0x4FEB, 0x8268, 0x4FEC, + 0x8269, 0x4FF0, 0x826A, 0x4FF2, 0x826B, 0x4FF4, 0x826C, 0x4FF5, + 0x826D, 0x4FF6, 0x826E, 0x4FF7, 0x826F, 0x4FF9, 0x8270, 0x4FFB, + 0x8271, 0x4FFC, 0x8272, 0x4FFD, 0x8273, 0x4FFF, 0x8274, 0x5000, + 0x8275, 0x5001, 0x8276, 0x5002, 0x8277, 0x5003, 0x8278, 0x5004, + 0x8279, 0x5005, 0x827A, 0x5006, 0x827B, 0x5007, 0x827C, 0x5008, + 0x827D, 0x5009, 0x827E, 0x500A, 0x8280, 0x500B, 0x8281, 0x500E, + 0x8282, 0x5010, 0x8283, 0x5011, 0x8284, 0x5013, 0x8285, 0x5015, + 0x8286, 0x5016, 0x8287, 0x5017, 0x8288, 0x501B, 0x8289, 0x501D, + 0x828A, 0x501E, 0x828B, 0x5020, 0x828C, 0x5022, 0x828D, 0x5023, + 0x828E, 0x5024, 0x828F, 0x5027, 0x8290, 0x502B, 0x8291, 0x502F, + 0x8292, 0x5030, 0x8293, 0x5031, 0x8294, 0x5032, 0x8295, 0x5033, + 0x8296, 0x5034, 0x8297, 0x5035, 0x8298, 0x5036, 0x8299, 0x5037, + 0x829A, 0x5038, 0x829B, 0x5039, 0x829C, 0x503B, 0x829D, 0x503D, + 0x829E, 0x503F, 0x829F, 0x5040, 0x82A0, 0x5041, 0x82A1, 0x5042, + 0x82A2, 0x5044, 0x82A3, 0x5045, 0x82A4, 0x5046, 0x82A5, 0x5049, + 0x82A6, 0x504A, 0x82A7, 0x504B, 0x82A8, 0x504D, 0x82A9, 0x5050, + 0x82AA, 0x5051, 0x82AB, 0x5052, 0x82AC, 0x5053, 0x82AD, 0x5054, + 0x82AE, 0x5056, 0x82AF, 0x5057, 0x82B0, 0x5058, 0x82B1, 0x5059, + 0x82B2, 0x505B, 0x82B3, 0x505D, 0x82B4, 0x505E, 0x82B5, 0x505F, + 0x82B6, 0x5060, 0x82B7, 0x5061, 0x82B8, 0x5062, 0x82B9, 0x5063, + 0x82BA, 0x5064, 0x82BB, 0x5066, 0x82BC, 0x5067, 0x82BD, 0x5068, + 0x82BE, 0x5069, 0x82BF, 0x506A, 0x82C0, 0x506B, 0x82C1, 0x506D, + 0x82C2, 0x506E, 0x82C3, 0x506F, 0x82C4, 0x5070, 0x82C5, 0x5071, + 0x82C6, 0x5072, 0x82C7, 0x5073, 0x82C8, 0x5074, 0x82C9, 0x5075, + 0x82CA, 0x5078, 0x82CB, 0x5079, 0x82CC, 0x507A, 0x82CD, 0x507C, + 0x82CE, 0x507D, 0x82CF, 0x5081, 0x82D0, 0x5082, 0x82D1, 0x5083, + 0x82D2, 0x5084, 0x82D3, 0x5086, 0x82D4, 0x5087, 0x82D5, 0x5089, + 0x82D6, 0x508A, 0x82D7, 0x508B, 0x82D8, 0x508C, 0x82D9, 0x508E, + 0x82DA, 0x508F, 0x82DB, 0x5090, 0x82DC, 0x5091, 0x82DD, 0x5092, + 0x82DE, 0x5093, 0x82DF, 0x5094, 0x82E0, 0x5095, 0x82E1, 0x5096, + 0x82E2, 0x5097, 0x82E3, 0x5098, 0x82E4, 0x5099, 0x82E5, 0x509A, + 0x82E6, 0x509B, 0x82E7, 0x509C, 0x82E8, 0x509D, 0x82E9, 0x509E, + 0x82EA, 0x509F, 0x82EB, 0x50A0, 0x82EC, 0x50A1, 0x82ED, 0x50A2, + 0x82EE, 0x50A4, 0x82EF, 0x50A6, 0x82F0, 0x50AA, 0x82F1, 0x50AB, + 0x82F2, 0x50AD, 0x82F3, 0x50AE, 0x82F4, 0x50AF, 0x82F5, 0x50B0, + 0x82F6, 0x50B1, 0x82F7, 0x50B3, 0x82F8, 0x50B4, 0x82F9, 0x50B5, + 0x82FA, 0x50B6, 0x82FB, 0x50B7, 0x82FC, 0x50B8, 0x82FD, 0x50B9, + 0x82FE, 0x50BC, 0x8340, 0x50BD, 0x8341, 0x50BE, 0x8342, 0x50BF, + 0x8343, 0x50C0, 0x8344, 0x50C1, 0x8345, 0x50C2, 0x8346, 0x50C3, + 0x8347, 0x50C4, 0x8348, 0x50C5, 0x8349, 0x50C6, 0x834A, 0x50C7, + 0x834B, 0x50C8, 0x834C, 0x50C9, 0x834D, 0x50CA, 0x834E, 0x50CB, + 0x834F, 0x50CC, 0x8350, 0x50CD, 0x8351, 0x50CE, 0x8352, 0x50D0, + 0x8353, 0x50D1, 0x8354, 0x50D2, 0x8355, 0x50D3, 0x8356, 0x50D4, + 0x8357, 0x50D5, 0x8358, 0x50D7, 0x8359, 0x50D8, 0x835A, 0x50D9, + 0x835B, 0x50DB, 0x835C, 0x50DC, 0x835D, 0x50DD, 0x835E, 0x50DE, + 0x835F, 0x50DF, 0x8360, 0x50E0, 0x8361, 0x50E1, 0x8362, 0x50E2, + 0x8363, 0x50E3, 0x8364, 0x50E4, 0x8365, 0x50E5, 0x8366, 0x50E8, + 0x8367, 0x50E9, 0x8368, 0x50EA, 0x8369, 0x50EB, 0x836A, 0x50EF, + 0x836B, 0x50F0, 0x836C, 0x50F1, 0x836D, 0x50F2, 0x836E, 0x50F4, + 0x836F, 0x50F6, 0x8370, 0x50F7, 0x8371, 0x50F8, 0x8372, 0x50F9, + 0x8373, 0x50FA, 0x8374, 0x50FC, 0x8375, 0x50FD, 0x8376, 0x50FE, + 0x8377, 0x50FF, 0x8378, 0x5100, 0x8379, 0x5101, 0x837A, 0x5102, + 0x837B, 0x5103, 0x837C, 0x5104, 0x837D, 0x5105, 0x837E, 0x5108, + 0x8380, 0x5109, 0x8381, 0x510A, 0x8382, 0x510C, 0x8383, 0x510D, + 0x8384, 0x510E, 0x8385, 0x510F, 0x8386, 0x5110, 0x8387, 0x5111, + 0x8388, 0x5113, 0x8389, 0x5114, 0x838A, 0x5115, 0x838B, 0x5116, + 0x838C, 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0xA1A3, 0x3002, + 0xA1A4, 0x00B7, 0xA1A5, 0x02C9, 0xA1A6, 0x02C7, 0xA1A7, 0x00A8, + 0xA1A8, 0x3003, 0xA1A9, 0x3005, 0xA1AA, 0x2014, 0xA1AB, 0xFF5E, + 0xA1AC, 0x2016, 0xA1AD, 0x2026, 0xA1AE, 0x2018, 0xA1AF, 0x2019, + 0xA1B0, 0x201C, 0xA1B1, 0x201D, 0xA1B2, 0x3014, 0xA1B3, 0x3015, + 0xA1B4, 0x3008, 0xA1B5, 0x3009, 0xA1B6, 0x300A, 0xA1B7, 0x300B, + 0xA1B8, 0x300C, 0xA1B9, 0x300D, 0xA1BA, 0x300E, 0xA1BB, 0x300F, + 0xA1BC, 0x3016, 0xA1BD, 0x3017, 0xA1BE, 0x3010, 0xA1BF, 0x3011, + 0xA1C0, 0x00B1, 0xA1C1, 0x00D7, 0xA1C2, 0x00F7, 0xA1C3, 0x2236, + 0xA1C4, 0x2227, 0xA1C5, 0x2228, 0xA1C6, 0x2211, 0xA1C7, 0x220F, + 0xA1C8, 0x222A, 0xA1C9, 0x2229, 0xA1CA, 0x2208, 0xA1CB, 0x2237, + 0xA1CC, 0x221A, 0xA1CD, 0x22A5, 0xA1CE, 0x2225, 0xA1CF, 0x2220, + 0xA1D0, 0x2312, 0xA1D1, 0x2299, 0xA1D2, 0x222B, 0xA1D3, 0x222E, + 0xA1D4, 0x2261, 0xA1D5, 0x224C, 0xA1D6, 0x2248, 0xA1D7, 0x223D, + 0xA1D8, 0x221D, 0xA1D9, 0x2260, 0xA1DA, 0x226E, 0xA1DB, 0x226F, + 0xA1DC, 0x2264, 0xA1DD, 0x2265, 0xA1DE, 0x221E, 0xA1DF, 0x2235, + 0xA1E0, 0x2234, 0xA1E1, 0x2642, 0xA1E2, 0x2640, 0xA1E3, 0x00B0, + 0xA1E4, 0x2032, 0xA1E5, 0x2033, 0xA1E6, 0x2103, 0xA1E7, 0xFF04, + 0xA1E8, 0x00A4, 0xA1E9, 0xFFE0, 0xA1EA, 0xFFE1, 0xA1EB, 0x2030, + 0xA1EC, 0x00A7, 0xA1ED, 0x2116, 0xA1EE, 0x2606, 0xA1EF, 0x2605, + 0xA1F0, 0x25CB, 0xA1F1, 0x25CF, 0xA1F2, 0x25CE, 0xA1F3, 0x25C7, + 0xA1F4, 0x25C6, 0xA1F5, 0x25A1, 0xA1F6, 0x25A0, 0xA1F7, 0x25B3, + 0xA1F8, 0x25B2, 0xA1F9, 0x203B, 0xA1FA, 0x2192, 0xA1FB, 0x2190, + 0xA1FC, 0x2191, 0xA1FD, 0x2193, 0xA1FE, 0x3013, 0xA2A1, 0x2170, + 0xA2A2, 0x2171, 0xA2A3, 0x2172, 0xA2A4, 0x2173, 0xA2A5, 0x2174, + 0xA2A6, 0x2175, 0xA2A7, 0x2176, 0xA2A8, 0x2177, 0xA2A9, 0x2178, + 0xA2AA, 0x2179, 0xA2B1, 0x2488, 0xA2B2, 0x2489, 0xA2B3, 0x248A, + 0xA2B4, 0x248B, 0xA2B5, 0x248C, 0xA2B6, 0x248D, 0xA2B7, 0x248E, + 0xA2B8, 0x248F, 0xA2B9, 0x2490, 0xA2BA, 0x2491, 0xA2BB, 0x2492, + 0xA2BC, 0x2493, 0xA2BD, 0x2494, 0xA2BE, 0x2495, 0xA2BF, 0x2496, + 0xA2C0, 0x2497, 0xA2C1, 0x2498, 0xA2C2, 0x2499, 0xA2C3, 0x249A, + 0xA2C4, 0x249B, 0xA2C5, 0x2474, 0xA2C6, 0x2475, 0xA2C7, 0x2476, + 0xA2C8, 0x2477, 0xA2C9, 0x2478, 0xA2CA, 0x2479, 0xA2CB, 0x247A, + 0xA2CC, 0x247B, 0xA2CD, 0x247C, 0xA2CE, 0x247D, 0xA2CF, 0x247E, + 0xA2D0, 0x247F, 0xA2D1, 0x2480, 0xA2D2, 0x2481, 0xA2D3, 0x2482, + 0xA2D4, 0x2483, 0xA2D5, 0x2484, 0xA2D6, 0x2485, 0xA2D7, 0x2486, + 0xA2D8, 0x2487, 0xA2D9, 0x2460, 0xA2DA, 0x2461, 0xA2DB, 0x2462, + 0xA2DC, 0x2463, 0xA2DD, 0x2464, 0xA2DE, 0x2465, 0xA2DF, 0x2466, + 0xA2E0, 0x2467, 0xA2E1, 0x2468, 0xA2E2, 0x2469, 0xA2E5, 0x3220, + 0xA2E6, 0x3221, 0xA2E7, 0x3222, 0xA2E8, 0x3223, 0xA2E9, 0x3224, + 0xA2EA, 0x3225, 0xA2EB, 0x3226, 0xA2EC, 0x3227, 0xA2ED, 0x3228, + 0xA2EE, 0x3229, 0xA2F1, 0x2160, 0xA2F2, 0x2161, 0xA2F3, 0x2162, + 0xA2F4, 0x2163, 0xA2F5, 0x2164, 0xA2F6, 0x2165, 0xA2F7, 0x2166, + 0xA2F8, 0x2167, 0xA2F9, 0x2168, 0xA2FA, 0x2169, 0xA2FB, 0x216A, + 0xA2FC, 0x216B, 0xA3A1, 0xFF01, 0xA3A2, 0xFF02, 0xA3A3, 0xFF03, + 0xA3A4, 0xFFE5, 0xA3A5, 0xFF05, 0xA3A6, 0xFF06, 0xA3A7, 0xFF07, + 0xA3A8, 0xFF08, 0xA3A9, 0xFF09, 0xA3AA, 0xFF0A, 0xA3AB, 0xFF0B, + 0xA3AC, 0xFF0C, 0xA3AD, 0xFF0D, 0xA3AE, 0xFF0E, 0xA3AF, 0xFF0F, + 0xA3B0, 0xFF10, 0xA3B1, 0xFF11, 0xA3B2, 0xFF12, 0xA3B3, 0xFF13, + 0xA3B4, 0xFF14, 0xA3B5, 0xFF15, 0xA3B6, 0xFF16, 0xA3B7, 0xFF17, + 0xA3B8, 0xFF18, 0xA3B9, 0xFF19, 0xA3BA, 0xFF1A, 0xA3BB, 0xFF1B, + 0xA3BC, 0xFF1C, 0xA3BD, 0xFF1D, 0xA3BE, 0xFF1E, 0xA3BF, 0xFF1F, + 0xA3C0, 0xFF20, 0xA3C1, 0xFF21, 0xA3C2, 0xFF22, 0xA3C3, 0xFF23, + 0xA3C4, 0xFF24, 0xA3C5, 0xFF25, 0xA3C6, 0xFF26, 0xA3C7, 0xFF27, + 0xA3C8, 0xFF28, 0xA3C9, 0xFF29, 0xA3CA, 0xFF2A, 0xA3CB, 0xFF2B, + 0xA3CC, 0xFF2C, 0xA3CD, 0xFF2D, 0xA3CE, 0xFF2E, 0xA3CF, 0xFF2F, + 0xA3D0, 0xFF30, 0xA3D1, 0xFF31, 0xA3D2, 0xFF32, 0xA3D3, 0xFF33, + 0xA3D4, 0xFF34, 0xA3D5, 0xFF35, 0xA3D6, 0xFF36, 0xA3D7, 0xFF37, + 0xA3D8, 0xFF38, 0xA3D9, 0xFF39, 0xA3DA, 0xFF3A, 0xA3DB, 0xFF3B, + 0xA3DC, 0xFF3C, 0xA3DD, 0xFF3D, 0xA3DE, 0xFF3E, 0xA3DF, 0xFF3F, + 0xA3E0, 0xFF40, 0xA3E1, 0xFF41, 0xA3E2, 0xFF42, 0xA3E3, 0xFF43, + 0xA3E4, 0xFF44, 0xA3E5, 0xFF45, 0xA3E6, 0xFF46, 0xA3E7, 0xFF47, + 0xA3E8, 0xFF48, 0xA3E9, 0xFF49, 0xA3EA, 0xFF4A, 0xA3EB, 0xFF4B, + 0xA3EC, 0xFF4C, 0xA3ED, 0xFF4D, 0xA3EE, 0xFF4E, 0xA3EF, 0xFF4F, + 0xA3F0, 0xFF50, 0xA3F1, 0xFF51, 0xA3F2, 0xFF52, 0xA3F3, 0xFF53, + 0xA3F4, 0xFF54, 0xA3F5, 0xFF55, 0xA3F6, 0xFF56, 0xA3F7, 0xFF57, + 0xA3F8, 0xFF58, 0xA3F9, 0xFF59, 0xA3FA, 0xFF5A, 0xA3FB, 0xFF5B, + 0xA3FC, 0xFF5C, 0xA3FD, 0xFF5D, 0xA3FE, 0xFFE3, 0xA4A1, 0x3041, + 0xA4A2, 0x3042, 0xA4A3, 0x3043, 0xA4A4, 0x3044, 0xA4A5, 0x3045, + 0xA4A6, 0x3046, 0xA4A7, 0x3047, 0xA4A8, 0x3048, 0xA4A9, 0x3049, + 0xA4AA, 0x304A, 0xA4AB, 0x304B, 0xA4AC, 0x304C, 0xA4AD, 0x304D, + 0xA4AE, 0x304E, 0xA4AF, 0x304F, 0xA4B0, 0x3050, 0xA4B1, 0x3051, + 0xA4B2, 0x3052, 0xA4B3, 0x3053, 0xA4B4, 0x3054, 0xA4B5, 0x3055, + 0xA4B6, 0x3056, 0xA4B7, 0x3057, 0xA4B8, 0x3058, 0xA4B9, 0x3059, + 0xA4BA, 0x305A, 0xA4BB, 0x305B, 0xA4BC, 0x305C, 0xA4BD, 0x305D, + 0xA4BE, 0x305E, 0xA4BF, 0x305F, 0xA4C0, 0x3060, 0xA4C1, 0x3061, + 0xA4C2, 0x3062, 0xA4C3, 0x3063, 0xA4C4, 0x3064, 0xA4C5, 0x3065, + 0xA4C6, 0x3066, 0xA4C7, 0x3067, 0xA4C8, 0x3068, 0xA4C9, 0x3069, + 0xA4CA, 0x306A, 0xA4CB, 0x306B, 0xA4CC, 0x306C, 0xA4CD, 0x306D, + 0xA4CE, 0x306E, 0xA4CF, 0x306F, 0xA4D0, 0x3070, 0xA4D1, 0x3071, + 0xA4D2, 0x3072, 0xA4D3, 0x3073, 0xA4D4, 0x3074, 0xA4D5, 0x3075, + 0xA4D6, 0x3076, 0xA4D7, 0x3077, 0xA4D8, 0x3078, 0xA4D9, 0x3079, + 0xA4DA, 0x307A, 0xA4DB, 0x307B, 0xA4DC, 0x307C, 0xA4DD, 0x307D, + 0xA4DE, 0x307E, 0xA4DF, 0x307F, 0xA4E0, 0x3080, 0xA4E1, 0x3081, + 0xA4E2, 0x3082, 0xA4E3, 0x3083, 0xA4E4, 0x3084, 0xA4E5, 0x3085, + 0xA4E6, 0x3086, 0xA4E7, 0x3087, 0xA4E8, 0x3088, 0xA4E9, 0x3089, + 0xA4EA, 0x308A, 0xA4EB, 0x308B, 0xA4EC, 0x308C, 0xA4ED, 0x308D, + 0xA4EE, 0x308E, 0xA4EF, 0x308F, 0xA4F0, 0x3090, 0xA4F1, 0x3091, + 0xA4F2, 0x3092, 0xA4F3, 0x3093, 0xA5A1, 0x30A1, 0xA5A2, 0x30A2, + 0xA5A3, 0x30A3, 0xA5A4, 0x30A4, 0xA5A5, 0x30A5, 0xA5A6, 0x30A6, + 0xA5A7, 0x30A7, 0xA5A8, 0x30A8, 0xA5A9, 0x30A9, 0xA5AA, 0x30AA, + 0xA5AB, 0x30AB, 0xA5AC, 0x30AC, 0xA5AD, 0x30AD, 0xA5AE, 0x30AE, + 0xA5AF, 0x30AF, 0xA5B0, 0x30B0, 0xA5B1, 0x30B1, 0xA5B2, 0x30B2, + 0xA5B3, 0x30B3, 0xA5B4, 0x30B4, 0xA5B5, 0x30B5, 0xA5B6, 0x30B6, + 0xA5B7, 0x30B7, 0xA5B8, 0x30B8, 0xA5B9, 0x30B9, 0xA5BA, 0x30BA, + 0xA5BB, 0x30BB, 0xA5BC, 0x30BC, 0xA5BD, 0x30BD, 0xA5BE, 0x30BE, + 0xA5BF, 0x30BF, 0xA5C0, 0x30C0, 0xA5C1, 0x30C1, 0xA5C2, 0x30C2, + 0xA5C3, 0x30C3, 0xA5C4, 0x30C4, 0xA5C5, 0x30C5, 0xA5C6, 0x30C6, + 0xA5C7, 0x30C7, 0xA5C8, 0x30C8, 0xA5C9, 0x30C9, 0xA5CA, 0x30CA, + 0xA5CB, 0x30CB, 0xA5CC, 0x30CC, 0xA5CD, 0x30CD, 0xA5CE, 0x30CE, + 0xA5CF, 0x30CF, 0xA5D0, 0x30D0, 0xA5D1, 0x30D1, 0xA5D2, 0x30D2, + 0xA5D3, 0x30D3, 0xA5D4, 0x30D4, 0xA5D5, 0x30D5, 0xA5D6, 0x30D6, + 0xA5D7, 0x30D7, 0xA5D8, 0x30D8, 0xA5D9, 0x30D9, 0xA5DA, 0x30DA, + 0xA5DB, 0x30DB, 0xA5DC, 0x30DC, 0xA5DD, 0x30DD, 0xA5DE, 0x30DE, + 0xA5DF, 0x30DF, 0xA5E0, 0x30E0, 0xA5E1, 0x30E1, 0xA5E2, 0x30E2, + 0xA5E3, 0x30E3, 0xA5E4, 0x30E4, 0xA5E5, 0x30E5, 0xA5E6, 0x30E6, + 0xA5E7, 0x30E7, 0xA5E8, 0x30E8, 0xA5E9, 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0xF2F5, 0x8753, 0xF2F6, 0x8763, 0xF2F7, 0x877C, 0xF2F8, 0x8764, + 0xF2F9, 0x8759, 0xF2FA, 0x8765, 0xF2FB, 0x8793, 0xF2FC, 0x87AF, + 0xF2FD, 0x87A8, 0xF2FE, 0x87D2, 0xF340, 0x9A5A, 0xF341, 0x9A5B, + 0xF342, 0x9A5C, 0xF343, 0x9A5D, 0xF344, 0x9A5E, 0xF345, 0x9A5F, + 0xF346, 0x9A60, 0xF347, 0x9A61, 0xF348, 0x9A62, 0xF349, 0x9A63, + 0xF34A, 0x9A64, 0xF34B, 0x9A65, 0xF34C, 0x9A66, 0xF34D, 0x9A67, + 0xF34E, 0x9A68, 0xF34F, 0x9A69, 0xF350, 0x9A6A, 0xF351, 0x9A6B, + 0xF352, 0x9A72, 0xF353, 0x9A83, 0xF354, 0x9A89, 0xF355, 0x9A8D, + 0xF356, 0x9A8E, 0xF357, 0x9A94, 0xF358, 0x9A95, 0xF359, 0x9A99, + 0xF35A, 0x9AA6, 0xF35B, 0x9AA9, 0xF35C, 0x9AAA, 0xF35D, 0x9AAB, + 0xF35E, 0x9AAC, 0xF35F, 0x9AAD, 0xF360, 0x9AAE, 0xF361, 0x9AAF, + 0xF362, 0x9AB2, 0xF363, 0x9AB3, 0xF364, 0x9AB4, 0xF365, 0x9AB5, + 0xF366, 0x9AB9, 0xF367, 0x9ABB, 0xF368, 0x9ABD, 0xF369, 0x9ABE, + 0xF36A, 0x9ABF, 0xF36B, 0x9AC3, 0xF36C, 0x9AC4, 0xF36D, 0x9AC6, + 0xF36E, 0x9AC7, 0xF36F, 0x9AC8, 0xF370, 0x9AC9, 0xF371, 0x9ACA, + 0xF372, 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0xF848, 0x9CEB, 0xF849, 0x9CEC, 0xF84A, 0x9CED, 0xF84B, 0x9CEE, + 0xF84C, 0x9CEF, 0xF84D, 0x9CF0, 0xF84E, 0x9CF1, 0xF84F, 0x9CF2, + 0xF850, 0x9CF3, 0xF851, 0x9CF4, 0xF852, 0x9CF5, 0xF853, 0x9CF6, + 0xF854, 0x9CF7, 0xF855, 0x9CF8, 0xF856, 0x9CF9, 0xF857, 0x9CFA, + 0xF858, 0x9CFB, 0xF859, 0x9CFC, 0xF85A, 0x9CFD, 0xF85B, 0x9CFE, + 0xF85C, 0x9CFF, 0xF85D, 0x9D00, 0xF85E, 0x9D01, 0xF85F, 0x9D02, + 0xF860, 0x9D03, 0xF861, 0x9D04, 0xF862, 0x9D05, 0xF863, 0x9D06, + 0xF864, 0x9D07, 0xF865, 0x9D08, 0xF866, 0x9D09, 0xF867, 0x9D0A, + 0xF868, 0x9D0B, 0xF869, 0x9D0C, 0xF86A, 0x9D0D, 0xF86B, 0x9D0E, + 0xF86C, 0x9D0F, 0xF86D, 0x9D10, 0xF86E, 0x9D11, 0xF86F, 0x9D12, + 0xF870, 0x9D13, 0xF871, 0x9D14, 0xF872, 0x9D15, 0xF873, 0x9D16, + 0xF874, 0x9D17, 0xF875, 0x9D18, 0xF876, 0x9D19, 0xF877, 0x9D1A, + 0xF878, 0x9D1B, 0xF879, 0x9D1C, 0xF87A, 0x9D1D, 0xF87B, 0x9D1E, + 0xF87C, 0x9D1F, 0xF87D, 0x9D20, 0xF87E, 0x9D21, 0xF880, 0x9D22, + 0xF881, 0x9D23, 0xF882, 0x9D24, 0xF883, 0x9D25, 0xF884, 0x9D26, + 0xF885, 0x9D27, 0xF886, 0x9D28, 0xF887, 0x9D29, 0xF888, 0x9D2A, + 0xF889, 0x9D2B, 0xF88A, 0x9D2C, 0xF88B, 0x9D2D, 0xF88C, 0x9D2E, + 0xF88D, 0x9D2F, 0xF88E, 0x9D30, 0xF88F, 0x9D31, 0xF890, 0x9D32, + 0xF891, 0x9D33, 0xF892, 0x9D34, 0xF893, 0x9D35, 0xF894, 0x9D36, + 0xF895, 0x9D37, 0xF896, 0x9D38, 0xF897, 0x9D39, 0xF898, 0x9D3A, + 0xF899, 0x9D3B, 0xF89A, 0x9D3C, 0xF89B, 0x9D3D, 0xF89C, 0x9D3E, + 0xF89D, 0x9D3F, 0xF89E, 0x9D40, 0xF89F, 0x9D41, 0xF8A0, 0x9D42, + 0xF940, 0x9D43, 0xF941, 0x9D44, 0xF942, 0x9D45, 0xF943, 0x9D46, + 0xF944, 0x9D47, 0xF945, 0x9D48, 0xF946, 0x9D49, 0xF947, 0x9D4A, + 0xF948, 0x9D4B, 0xF949, 0x9D4C, 0xF94A, 0x9D4D, 0xF94B, 0x9D4E, + 0xF94C, 0x9D4F, 0xF94D, 0x9D50, 0xF94E, 0x9D51, 0xF94F, 0x9D52, + 0xF950, 0x9D53, 0xF951, 0x9D54, 0xF952, 0x9D55, 0xF953, 0x9D56, + 0xF954, 0x9D57, 0xF955, 0x9D58, 0xF956, 0x9D59, 0xF957, 0x9D5A, + 0xF958, 0x9D5B, 0xF959, 0x9D5C, 0xF95A, 0x9D5D, 0xF95B, 0x9D5E, + 0xF95C, 0x9D5F, 0xF95D, 0x9D60, 0xF95E, 0x9D61, 0xF95F, 0x9D62, + 0xF960, 0x9D63, 0xF961, 0x9D64, 0xF962, 0x9D65, 0xF963, 0x9D66, + 0xF964, 0x9D67, 0xF965, 0x9D68, 0xF966, 0x9D69, 0xF967, 0x9D6A, + 0xF968, 0x9D6B, 0xF969, 0x9D6C, 0xF96A, 0x9D6D, 0xF96B, 0x9D6E, + 0xF96C, 0x9D6F, 0xF96D, 0x9D70, 0xF96E, 0x9D71, 0xF96F, 0x9D72, + 0xF970, 0x9D73, 0xF971, 0x9D74, 0xF972, 0x9D75, 0xF973, 0x9D76, + 0xF974, 0x9D77, 0xF975, 0x9D78, 0xF976, 0x9D79, 0xF977, 0x9D7A, + 0xF978, 0x9D7B, 0xF979, 0x9D7C, 0xF97A, 0x9D7D, 0xF97B, 0x9D7E, + 0xF97C, 0x9D7F, 0xF97D, 0x9D80, 0xF97E, 0x9D81, 0xF980, 0x9D82, + 0xF981, 0x9D83, 0xF982, 0x9D84, 0xF983, 0x9D85, 0xF984, 0x9D86, + 0xF985, 0x9D87, 0xF986, 0x9D88, 0xF987, 0x9D89, 0xF988, 0x9D8A, + 0xF989, 0x9D8B, 0xF98A, 0x9D8C, 0xF98B, 0x9D8D, 0xF98C, 0x9D8E, + 0xF98D, 0x9D8F, 0xF98E, 0x9D90, 0xF98F, 0x9D91, 0xF990, 0x9D92, + 0xF991, 0x9D93, 0xF992, 0x9D94, 0xF993, 0x9D95, 0xF994, 0x9D96, + 0xF995, 0x9D97, 0xF996, 0x9D98, 0xF997, 0x9D99, 0xF998, 0x9D9A, + 0xF999, 0x9D9B, 0xF99A, 0x9D9C, 0xF99B, 0x9D9D, 0xF99C, 0x9D9E, + 0xF99D, 0x9D9F, 0xF99E, 0x9DA0, 0xF99F, 0x9DA1, 0xF9A0, 0x9DA2, + 0xFA40, 0x9DA3, 0xFA41, 0x9DA4, 0xFA42, 0x9DA5, 0xFA43, 0x9DA6, + 0xFA44, 0x9DA7, 0xFA45, 0x9DA8, 0xFA46, 0x9DA9, 0xFA47, 0x9DAA, + 0xFA48, 0x9DAB, 0xFA49, 0x9DAC, 0xFA4A, 0x9DAD, 0xFA4B, 0x9DAE, + 0xFA4C, 0x9DAF, 0xFA4D, 0x9DB0, 0xFA4E, 0x9DB1, 0xFA4F, 0x9DB2, + 0xFA50, 0x9DB3, 0xFA51, 0x9DB4, 0xFA52, 0x9DB5, 0xFA53, 0x9DB6, + 0xFA54, 0x9DB7, 0xFA55, 0x9DB8, 0xFA56, 0x9DB9, 0xFA57, 0x9DBA, + 0xFA58, 0x9DBB, 0xFA59, 0x9DBC, 0xFA5A, 0x9DBD, 0xFA5B, 0x9DBE, + 0xFA5C, 0x9DBF, 0xFA5D, 0x9DC0, 0xFA5E, 0x9DC1, 0xFA5F, 0x9DC2, + 0xFA60, 0x9DC3, 0xFA61, 0x9DC4, 0xFA62, 0x9DC5, 0xFA63, 0x9DC6, + 0xFA64, 0x9DC7, 0xFA65, 0x9DC8, 0xFA66, 0x9DC9, 0xFA67, 0x9DCA, + 0xFA68, 0x9DCB, 0xFA69, 0x9DCC, 0xFA6A, 0x9DCD, 0xFA6B, 0x9DCE, + 0xFA6C, 0x9DCF, 0xFA6D, 0x9DD0, 0xFA6E, 0x9DD1, 0xFA6F, 0x9DD2, + 0xFA70, 0x9DD3, 0xFA71, 0x9DD4, 0xFA72, 0x9DD5, 0xFA73, 0x9DD6, + 0xFA74, 0x9DD7, 0xFA75, 0x9DD8, 0xFA76, 0x9DD9, 0xFA77, 0x9DDA, + 0xFA78, 0x9DDB, 0xFA79, 0x9DDC, 0xFA7A, 0x9DDD, 0xFA7B, 0x9DDE, + 0xFA7C, 0x9DDF, 0xFA7D, 0x9DE0, 0xFA7E, 0x9DE1, 0xFA80, 0x9DE2, + 0xFA81, 0x9DE3, 0xFA82, 0x9DE4, 0xFA83, 0x9DE5, 0xFA84, 0x9DE6, + 0xFA85, 0x9DE7, 0xFA86, 0x9DE8, 0xFA87, 0x9DE9, 0xFA88, 0x9DEA, + 0xFA89, 0x9DEB, 0xFA8A, 0x9DEC, 0xFA8B, 0x9DED, 0xFA8C, 0x9DEE, + 0xFA8D, 0x9DEF, 0xFA8E, 0x9DF0, 0xFA8F, 0x9DF1, 0xFA90, 0x9DF2, + 0xFA91, 0x9DF3, 0xFA92, 0x9DF4, 0xFA93, 0x9DF5, 0xFA94, 0x9DF6, + 0xFA95, 0x9DF7, 0xFA96, 0x9DF8, 0xFA97, 0x9DF9, 0xFA98, 0x9DFA, + 0xFA99, 0x9DFB, 0xFA9A, 0x9DFC, 0xFA9B, 0x9DFD, 0xFA9C, 0x9DFE, + 0xFA9D, 0x9DFF, 0xFA9E, 0x9E00, 0xFA9F, 0x9E01, 0xFAA0, 0x9E02, + 0xFB40, 0x9E03, 0xFB41, 0x9E04, 0xFB42, 0x9E05, 0xFB43, 0x9E06, + 0xFB44, 0x9E07, 0xFB45, 0x9E08, 0xFB46, 0x9E09, 0xFB47, 0x9E0A, + 0xFB48, 0x9E0B, 0xFB49, 0x9E0C, 0xFB4A, 0x9E0D, 0xFB4B, 0x9E0E, + 0xFB4C, 0x9E0F, 0xFB4D, 0x9E10, 0xFB4E, 0x9E11, 0xFB4F, 0x9E12, + 0xFB50, 0x9E13, 0xFB51, 0x9E14, 0xFB52, 0x9E15, 0xFB53, 0x9E16, + 0xFB54, 0x9E17, 0xFB55, 0x9E18, 0xFB56, 0x9E19, 0xFB57, 0x9E1A, + 0xFB58, 0x9E1B, 0xFB59, 0x9E1C, 0xFB5A, 0x9E1D, 0xFB5B, 0x9E1E, + 0xFB5C, 0x9E24, 0xFB5D, 0x9E27, 0xFB5E, 0x9E2E, 0xFB5F, 0x9E30, + 0xFB60, 0x9E34, 0xFB61, 0x9E3B, 0xFB62, 0x9E3C, 0xFB63, 0x9E40, + 0xFB64, 0x9E4D, 0xFB65, 0x9E50, 0xFB66, 0x9E52, 0xFB67, 0x9E53, + 0xFB68, 0x9E54, 0xFB69, 0x9E56, 0xFB6A, 0x9E59, 0xFB6B, 0x9E5D, + 0xFB6C, 0x9E5F, 0xFB6D, 0x9E60, 0xFB6E, 0x9E61, 0xFB6F, 0x9E62, + 0xFB70, 0x9E65, 0xFB71, 0x9E6E, 0xFB72, 0x9E6F, 0xFB73, 0x9E72, + 0xFB74, 0x9E74, 0xFB75, 0x9E75, 0xFB76, 0x9E76, 0xFB77, 0x9E77, + 0xFB78, 0x9E78, 0xFB79, 0x9E79, 0xFB7A, 0x9E7A, 0xFB7B, 0x9E7B, + 0xFB7C, 0x9E7C, 0xFB7D, 0x9E7D, 0xFB7E, 0x9E80, 0xFB80, 0x9E81, + 0xFB81, 0x9E83, 0xFB82, 0x9E84, 0xFB83, 0x9E85, 0xFB84, 0x9E86, + 0xFB85, 0x9E89, 0xFB86, 0x9E8A, 0xFB87, 0x9E8C, 0xFB88, 0x9E8D, + 0xFB89, 0x9E8E, 0xFB8A, 0x9E8F, 0xFB8B, 0x9E90, 0xFB8C, 0x9E91, + 0xFB8D, 0x9E94, 0xFB8E, 0x9E95, 0xFB8F, 0x9E96, 0xFB90, 0x9E97, + 0xFB91, 0x9E98, 0xFB92, 0x9E99, 0xFB93, 0x9E9A, 0xFB94, 0x9E9B, + 0xFB95, 0x9E9C, 0xFB96, 0x9E9E, 0xFB97, 0x9EA0, 0xFB98, 0x9EA1, + 0xFB99, 0x9EA2, 0xFB9A, 0x9EA3, 0xFB9B, 0x9EA4, 0xFB9C, 0x9EA5, + 0xFB9D, 0x9EA7, 0xFB9E, 0x9EA8, 0xFB9F, 0x9EA9, 0xFBA0, 0x9EAA, + 0xFC40, 0x9EAB, 0xFC41, 0x9EAC, 0xFC42, 0x9EAD, 0xFC43, 0x9EAE, + 0xFC44, 0x9EAF, 0xFC45, 0x9EB0, 0xFC46, 0x9EB1, 0xFC47, 0x9EB2, + 0xFC48, 0x9EB3, 0xFC49, 0x9EB5, 0xFC4A, 0x9EB6, 0xFC4B, 0x9EB7, + 0xFC4C, 0x9EB9, 0xFC4D, 0x9EBA, 0xFC4E, 0x9EBC, 0xFC4F, 0x9EBF, + 0xFC50, 0x9EC0, 0xFC51, 0x9EC1, 0xFC52, 0x9EC2, 0xFC53, 0x9EC3, + 0xFC54, 0x9EC5, 0xFC55, 0x9EC6, 0xFC56, 0x9EC7, 0xFC57, 0x9EC8, + 0xFC58, 0x9ECA, 0xFC59, 0x9ECB, 0xFC5A, 0x9ECC, 0xFC5B, 0x9ED0, + 0xFC5C, 0x9ED2, 0xFC5D, 0x9ED3, 0xFC5E, 0x9ED5, 0xFC5F, 0x9ED6, + 0xFC60, 0x9ED7, 0xFC61, 0x9ED9, 0xFC62, 0x9EDA, 0xFC63, 0x9EDE, + 0xFC64, 0x9EE1, 0xFC65, 0x9EE3, 0xFC66, 0x9EE4, 0xFC67, 0x9EE6, + 0xFC68, 0x9EE8, 0xFC69, 0x9EEB, 0xFC6A, 0x9EEC, 0xFC6B, 0x9EED, + 0xFC6C, 0x9EEE, 0xFC6D, 0x9EF0, 0xFC6E, 0x9EF1, 0xFC6F, 0x9EF2, + 0xFC70, 0x9EF3, 0xFC71, 0x9EF4, 0xFC72, 0x9EF5, 0xFC73, 0x9EF6, + 0xFC74, 0x9EF7, 0xFC75, 0x9EF8, 0xFC76, 0x9EFA, 0xFC77, 0x9EFD, + 0xFC78, 0x9EFF, 0xFC79, 0x9F00, 0xFC7A, 0x9F01, 0xFC7B, 0x9F02, + 0xFC7C, 0x9F03, 0xFC7D, 0x9F04, 0xFC7E, 0x9F05, 0xFC80, 0x9F06, + 0xFC81, 0x9F07, 0xFC82, 0x9F08, 0xFC83, 0x9F09, 0xFC84, 0x9F0A, + 0xFC85, 0x9F0C, 0xFC86, 0x9F0F, 0xFC87, 0x9F11, 0xFC88, 0x9F12, + 0xFC89, 0x9F14, 0xFC8A, 0x9F15, 0xFC8B, 0x9F16, 0xFC8C, 0x9F18, + 0xFC8D, 0x9F1A, 0xFC8E, 0x9F1B, 0xFC8F, 0x9F1C, 0xFC90, 0x9F1D, + 0xFC91, 0x9F1E, 0xFC92, 0x9F1F, 0xFC93, 0x9F21, 0xFC94, 0x9F23, + 0xFC95, 0x9F24, 0xFC96, 0x9F25, 0xFC97, 0x9F26, 0xFC98, 0x9F27, + 0xFC99, 0x9F28, 0xFC9A, 0x9F29, 0xFC9B, 0x9F2A, 0xFC9C, 0x9F2B, + 0xFC9D, 0x9F2D, 0xFC9E, 0x9F2E, 0xFC9F, 0x9F30, 0xFCA0, 0x9F31, + 0xFD40, 0x9F32, 0xFD41, 0x9F33, 0xFD42, 0x9F34, 0xFD43, 0x9F35, + 0xFD44, 0x9F36, 0xFD45, 0x9F38, 0xFD46, 0x9F3A, 0xFD47, 0x9F3C, + 0xFD48, 0x9F3F, 0xFD49, 0x9F40, 0xFD4A, 0x9F41, 0xFD4B, 0x9F42, + 0xFD4C, 0x9F43, 0xFD4D, 0x9F45, 0xFD4E, 0x9F46, 0xFD4F, 0x9F47, + 0xFD50, 0x9F48, 0xFD51, 0x9F49, 0xFD52, 0x9F4A, 0xFD53, 0x9F4B, + 0xFD54, 0x9F4C, 0xFD55, 0x9F4D, 0xFD56, 0x9F4E, 0xFD57, 0x9F4F, + 0xFD58, 0x9F52, 0xFD59, 0x9F53, 0xFD5A, 0x9F54, 0xFD5B, 0x9F55, + 0xFD5C, 0x9F56, 0xFD5D, 0x9F57, 0xFD5E, 0x9F58, 0xFD5F, 0x9F59, + 0xFD60, 0x9F5A, 0xFD61, 0x9F5B, 0xFD62, 0x9F5C, 0xFD63, 0x9F5D, + 0xFD64, 0x9F5E, 0xFD65, 0x9F5F, 0xFD66, 0x9F60, 0xFD67, 0x9F61, + 0xFD68, 0x9F62, 0xFD69, 0x9F63, 0xFD6A, 0x9F64, 0xFD6B, 0x9F65, + 0xFD6C, 0x9F66, 0xFD6D, 0x9F67, 0xFD6E, 0x9F68, 0xFD6F, 0x9F69, + 0xFD70, 0x9F6A, 0xFD71, 0x9F6B, 0xFD72, 0x9F6C, 0xFD73, 0x9F6D, + 0xFD74, 0x9F6E, 0xFD75, 0x9F6F, 0xFD76, 0x9F70, 0xFD77, 0x9F71, + 0xFD78, 0x9F72, 0xFD79, 0x9F73, 0xFD7A, 0x9F74, 0xFD7B, 0x9F75, + 0xFD7C, 0x9F76, 0xFD7D, 0x9F77, 0xFD7E, 0x9F78, 0xFD80, 0x9F79, + 0xFD81, 0x9F7A, 0xFD82, 0x9F7B, 0xFD83, 0x9F7C, 0xFD84, 0x9F7D, + 0xFD85, 0x9F7E, 0xFD86, 0x9F81, 0xFD87, 0x9F82, 0xFD88, 0x9F8D, + 0xFD89, 0x9F8E, 0xFD8A, 0x9F8F, 0xFD8B, 0x9F90, 0xFD8C, 0x9F91, + 0xFD8D, 0x9F92, 0xFD8E, 0x9F93, 0xFD8F, 0x9F94, 0xFD90, 0x9F95, + 0xFD91, 0x9F96, 0xFD92, 0x9F97, 0xFD93, 0x9F98, 0xFD94, 0x9F9C, + 0xFD95, 0x9F9D, 0xFD96, 0x9F9E, 0xFD97, 0x9FA1, 0xFD98, 0x9FA2, + 0xFD99, 0x9FA3, 0xFD9A, 0x9FA4, 0xFD9B, 0x9FA5, 0xFD9C, 0xF92C, + 0xFD9D, 0xF979, 0xFD9E, 0xF995, 0xFD9F, 0xF9E7, 0xFDA0, 0xF9F1, + 0xFE40, 0xFA0C, 0xFE41, 0xFA0D, 0xFE42, 0xFA0E, 0xFE43, 0xFA0F, + 0xFE44, 0xFA11, 0xFE45, 0xFA13, 0xFE46, 0xFA14, 0xFE47, 0xFA18, + 0xFE48, 0xFA1F, 0xFE49, 0xFA20, 0xFE4A, 0xFA21, 0xFE4B, 0xFA23, + 0xFE4C, 0xFA24, 0xFE4D, 0xFA27, 0xFE4E, 0xFA28, 0xFE4F, 0xFA29, + 0, 0 +}; + + + +WCHAR ff_convert ( /* Converted code, 0 means conversion error */ + WCHAR chr, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEM code, 1: OEM code to Unicode */ +) +{ + const WCHAR *p; + WCHAR c; + int i, n, li, hi; + + + if (chr < 0x80) { /* ASCII */ + c = chr; + } else { + if (dir) { /* OEM code to unicode */ + p = oem2uni; + hi = sizeof oem2uni / 4 - 1; + } else { /* Unicode to OEM code */ + p = uni2oem; + hi = sizeof uni2oem / 4 - 1; + } + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (chr == p[i * 2]) break; + if (chr > p[i * 2]) + li = i; + else + hi = i; + } + c = n ? p[i * 2 + 1] : 0; + } + + return c; +} + + + +WCHAR ff_wtoupper ( /* Returns upper converted character */ + WCHAR chr /* Unicode character to be upper converted (BMP only) */ +) +{ + /* Compressed upper conversion table */ + static const WCHAR cvt1[] = { /* U+0000 - U+0FFF */ + /* Basic Latin */ + 0x0061,0x031A, + /* Latin-1 Supplement */ + 0x00E0,0x0317, 0x00F8,0x0307, 0x00FF,0x0001,0x0178, + /* Latin Extended-A */ + 0x0100,0x0130, 0x0132,0x0106, 0x0139,0x0110, 0x014A,0x012E, 0x0179,0x0106, + /* Latin Extended-B */ + 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, + 0x01CD,0x0110, 0x01DD,0x0001,0x018E, 0x01DE,0x0112, 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, 0x01F8,0x0128, + 0x0222,0x0112, 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, 0x0246,0x010A, + /* IPA Extensions */ + 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, + /* Greek, Coptic */ + 0x037B,0x0003,0x03FD,0x03FE,0x03FF, 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, 0x03B1,0x0311, + 0x03C2,0x0002,0x03A3,0x03A3, 0x03C4,0x0308, 0x03CC,0x0003,0x038C,0x038E,0x038F, 0x03D8,0x0118, + 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, + /* Cyrillic */ + 0x0430,0x0320, 0x0450,0x0710, 0x0460,0x0122, 0x048A,0x0136, 0x04C1,0x010E, 0x04CF,0x0001,0x04C0, 0x04D0,0x0144, + /* Armenian */ + 0x0561,0x0426, + + 0x0000 + }; + static const WCHAR cvt2[] = { /* U+1000 - U+FFFF */ + /* Phonetic Extensions */ + 0x1D7D,0x0001,0x2C63, + /* Latin Extended Additional */ + 0x1E00,0x0196, 0x1EA0,0x015A, + /* Greek Extended */ + 0x1F00,0x0608, 0x1F10,0x0606, 0x1F20,0x0608, 0x1F30,0x0608, 0x1F40,0x0606, + 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, 0x1F60,0x0608, + 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, + 0x1F80,0x0608, 0x1F90,0x0608, 0x1FA0,0x0608, 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, + 0x1FCC,0x0001,0x1FC3, 0x1FD0,0x0602, 0x1FE0,0x0602, 0x1FE5,0x0001,0x1FEC, 0x1FF2,0x0001,0x1FFC, + /* Letterlike Symbols */ + 0x214E,0x0001,0x2132, + /* Number forms */ + 0x2170,0x0210, 0x2184,0x0001,0x2183, + /* Enclosed Alphanumerics */ + 0x24D0,0x051A, 0x2C30,0x042F, + /* Latin Extended-C */ + 0x2C60,0x0102, 0x2C67,0x0106, 0x2C75,0x0102, + /* Coptic */ + 0x2C80,0x0164, + /* Georgian Supplement */ + 0x2D00,0x0826, + /* Full-width */ + 0xFF41,0x031A, + + 0x0000 + }; + const WCHAR *p; + WCHAR bc, nc, cmd; + + + p = chr < 0x1000 ? cvt1 : cvt2; + for (;;) { + bc = *p++; /* Get block base */ + if (!bc || chr < bc) break; + nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ + if (chr < bc + nc) { /* In the block? */ + switch (cmd) { + case 0: chr = p[chr - bc]; break; /* Table conversion */ + case 1: chr -= (chr - bc) & 1; break; /* Case pairs */ + case 2: chr -= 16; break; /* Shift -16 */ + case 3: chr -= 32; break; /* Shift -32 */ + case 4: chr -= 48; break; /* Shift -48 */ + case 5: chr -= 26; break; /* Shift -26 */ + case 6: chr += 8; break; /* Shift +8 */ + case 7: chr -= 80; break; /* Shift -80 */ + case 8: chr -= 0x1C60; break; /* Shift -0x1C60 */ + } + break; + } + if (!cmd) p += nc; + } + + return chr; +} + diff --git a/radio/src/thirdparty/FatFs/option/cc949.c b/radio/src/thirdparty/FatFs/option/cc949.c index 3bc617cc1..c3aa7c7b8 100644 --- a/radio/src/thirdparty/FatFs/option/cc949.c +++ b/radio/src/thirdparty/FatFs/option/cc949.c @@ -1,8674 +1,8674 @@ -/*------------------------------------------------------------------------*/ -/* Unicode - OEM code bidirectional converter (C)ChaN, 2015 */ -/* CP949 (Korean EUC-KR) */ -/*------------------------------------------------------------------------*/ - -#include "../ff.h" - - -#if !_USE_LFN || _CODE_PAGE != 949 -#error This file is not needed in current configuration. Remove from the project. -#endif - - -static -const WCHAR uni2oem[] = { -/* Unicode - OEM, Unicode - OEM, Unicode - OEM, Unicode - OEM */ - 0x00A1, 0xA2AE, 0x00A4, 0xA2B4, 0x00A7, 0xA1D7, 0x00A8, 0xA1A7, - 0x00AA, 0xA8A3, 0x00AD, 0xA1A9, 0x00AE, 0xA2E7, 0x00B0, 0xA1C6, - 0x00B1, 0xA1BE, 0x00B2, 0xA9F7, 0x00B3, 0xA9F8, 0x00B4, 0xA2A5, - 0x00B6, 0xA2D2, 0x00B7, 0xA1A4, 0x00B8, 0xA2AC, 0x00B9, 0xA9F6, - 0x00BA, 0xA8AC, 0x00BC, 0xA8F9, 0x00BD, 0xA8F6, 0x00BE, 0xA8FA, - 0x00BF, 0xA2AF, 0x00C6, 0xA8A1, 0x00D0, 0xA8A2, 0x00D7, 0xA1BF, - 0x00D8, 0xA8AA, 0x00DE, 0xA8AD, 0x00DF, 0xA9AC, 0x00E6, 0xA9A1, - 0x00F0, 0xA9A3, 0x00F7, 0xA1C0, 0x00F8, 0xA9AA, 0x00FE, 0xA9AD, - 0x0111, 0xA9A2, 0x0126, 0xA8A4, 0x0127, 0xA9A4, 0x0131, 0xA9A5, - 0x0132, 0xA8A6, 0x0133, 0xA9A6, 0x0138, 0xA9A7, 0x013F, 0xA8A8, - 0x0140, 0xA9A8, 0x0141, 0xA8A9, 0x0142, 0xA9A9, 0x0149, 0xA9B0, - 0x014A, 0xA8AF, 0x014B, 0xA9AF, 0x0152, 0xA8AB, 0x0153, 0xA9AB, - 0x0166, 0xA8AE, 0x0167, 0xA9AE, 0x02C7, 0xA2A7, 0x02D0, 0xA2B0, - 0x02D8, 0xA2A8, 0x02D9, 0xA2AB, 0x02DA, 0xA2AA, 0x02DB, 0xA2AD, - 0x02DD, 0xA2A9, 0x0391, 0xA5C1, 0x0392, 0xA5C2, 0x0393, 0xA5C3, - 0x0394, 0xA5C4, 0x0395, 0xA5C5, 0x0396, 0xA5C6, 0x0397, 0xA5C7, - 0x0398, 0xA5C8, 0x0399, 0xA5C9, 0x039A, 0xA5CA, 0x039B, 0xA5CB, - 0x039C, 0xA5CC, 0x039D, 0xA5CD, 0x039E, 0xA5CE, 0x039F, 0xA5CF, - 0x03A0, 0xA5D0, 0x03A1, 0xA5D1, 0x03A3, 0xA5D2, 0x03A4, 0xA5D3, - 0x03A5, 0xA5D4, 0x03A6, 0xA5D5, 0x03A7, 0xA5D6, 0x03A8, 0xA5D7, - 0x03A9, 0xA5D8, 0x03B1, 0xA5E1, 0x03B2, 0xA5E2, 0x03B3, 0xA5E3, - 0x03B4, 0xA5E4, 0x03B5, 0xA5E5, 0x03B6, 0xA5E6, 0x03B7, 0xA5E7, - 0x03B8, 0xA5E8, 0x03B9, 0xA5E9, 0x03BA, 0xA5EA, 0x03BB, 0xA5EB, - 0x03BC, 0xA5EC, 0x03BD, 0xA5ED, 0x03BE, 0xA5EE, 0x03BF, 0xA5EF, - 0x03C0, 0xA5F0, 0x03C1, 0xA5F1, 0x03C3, 0xA5F2, 0x03C4, 0xA5F3, - 0x03C5, 0xA5F4, 0x03C6, 0xA5F5, 0x03C7, 0xA5F6, 0x03C8, 0xA5F7, - 0x03C9, 0xA5F8, 0x0401, 0xACA7, 0x0410, 0xACA1, 0x0411, 0xACA2, - 0x0412, 0xACA3, 0x0413, 0xACA4, 0x0414, 0xACA5, 0x0415, 0xACA6, - 0x0416, 0xACA8, 0x0417, 0xACA9, 0x0418, 0xACAA, 0x0419, 0xACAB, - 0x041A, 0xACAC, 0x041B, 0xACAD, 0x041C, 0xACAE, 0x041D, 0xACAF, - 0x041E, 0xACB0, 0x041F, 0xACB1, 0x0420, 0xACB2, 0x0421, 0xACB3, - 0x0422, 0xACB4, 0x0423, 0xACB5, 0x0424, 0xACB6, 0x0425, 0xACB7, - 0x0426, 0xACB8, 0x0427, 0xACB9, 0x0428, 0xACBA, 0x0429, 0xACBB, - 0x042A, 0xACBC, 0x042B, 0xACBD, 0x042C, 0xACBE, 0x042D, 0xACBF, - 0x042E, 0xACC0, 0x042F, 0xACC1, 0x0430, 0xACD1, 0x0431, 0xACD2, - 0x0432, 0xACD3, 0x0433, 0xACD4, 0x0434, 0xACD5, 0x0435, 0xACD6, - 0x0436, 0xACD8, 0x0437, 0xACD9, 0x0438, 0xACDA, 0x0439, 0xACDB, - 0x043A, 0xACDC, 0x043B, 0xACDD, 0x043C, 0xACDE, 0x043D, 0xACDF, - 0x043E, 0xACE0, 0x043F, 0xACE1, 0x0440, 0xACE2, 0x0441, 0xACE3, - 0x0442, 0xACE4, 0x0443, 0xACE5, 0x0444, 0xACE6, 0x0445, 0xACE7, - 0x0446, 0xACE8, 0x0447, 0xACE9, 0x0448, 0xACEA, 0x0449, 0xACEB, - 0x044A, 0xACEC, 0x044B, 0xACED, 0x044C, 0xACEE, 0x044D, 0xACEF, - 0x044E, 0xACF0, 0x044F, 0xACF1, 0x0451, 0xACD7, 0x2015, 0xA1AA, - 0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1, - 0x2020, 0xA2D3, 0x2021, 0xA2D4, 0x2025, 0xA1A5, 0x2026, 0xA1A6, - 0x2030, 0xA2B6, 0x2032, 0xA1C7, 0x2033, 0xA1C8, 0x203B, 0xA1D8, - 0x2074, 0xA9F9, 0x207F, 0xA9FA, 0x2081, 0xA9FB, 0x2082, 0xA9FC, - 0x2083, 0xA9FD, 0x2084, 0xA9FE, 0x20AC, 0xA2E6, 0x2103, 0xA1C9, - 0x2109, 0xA2B5, 0x2113, 0xA7A4, 0x2116, 0xA2E0, 0x2121, 0xA2E5, - 0x2122, 0xA2E2, 0x2126, 0xA7D9, 0x212B, 0xA1CA, 0x2153, 0xA8F7, - 0x2154, 0xA8F8, 0x215B, 0xA8FB, 0x215C, 0xA8FC, 0x215D, 0xA8FD, - 0x215E, 0xA8FE, 0x2160, 0xA5B0, 0x2161, 0xA5B1, 0x2162, 0xA5B2, - 0x2163, 0xA5B3, 0x2164, 0xA5B4, 0x2165, 0xA5B5, 0x2166, 0xA5B6, - 0x2167, 0xA5B7, 0x2168, 0xA5B8, 0x2169, 0xA5B9, 0x2170, 0xA5A1, - 0x2171, 0xA5A2, 0x2172, 0xA5A3, 0x2173, 0xA5A4, 0x2174, 0xA5A5, - 0x2175, 0xA5A6, 0x2176, 0xA5A7, 0x2177, 0xA5A8, 0x2178, 0xA5A9, - 0x2179, 0xA5AA, 0x2190, 0xA1E7, 0x2191, 0xA1E8, 0x2192, 0xA1E6, - 0x2193, 0xA1E9, 0x2194, 0xA1EA, 0x2195, 0xA2D5, 0x2196, 0xA2D8, - 0x2197, 0xA2D6, 0x2198, 0xA2D9, 0x2199, 0xA2D7, 0x21D2, 0xA2A1, - 0x21D4, 0xA2A2, 0x2200, 0xA2A3, 0x2202, 0xA1D3, 0x2203, 0xA2A4, - 0x2207, 0xA1D4, 0x2208, 0xA1F4, 0x220B, 0xA1F5, 0x220F, 0xA2B3, - 0x2211, 0xA2B2, 0x221A, 0xA1EE, 0x221D, 0xA1F0, 0x221E, 0xA1C4, - 0x2220, 0xA1D0, 0x2225, 0xA1AB, 0x2227, 0xA1FC, 0x2228, 0xA1FD, - 0x2229, 0xA1FB, 0x222A, 0xA1FA, 0x222B, 0xA1F2, 0x222C, 0xA1F3, - 0x222E, 0xA2B1, 0x2234, 0xA1C5, 0x2235, 0xA1F1, 0x223C, 0xA1AD, - 0x223D, 0xA1EF, 0x2252, 0xA1D6, 0x2260, 0xA1C1, 0x2261, 0xA1D5, - 0x2264, 0xA1C2, 0x2265, 0xA1C3, 0x226A, 0xA1EC, 0x226B, 0xA1ED, - 0x2282, 0xA1F8, 0x2283, 0xA1F9, 0x2286, 0xA1F6, 0x2287, 0xA1F7, - 0x2299, 0xA2C1, 0x22A5, 0xA1D1, 0x2312, 0xA1D2, 0x2460, 0xA8E7, - 0x2461, 0xA8E8, 0x2462, 0xA8E9, 0x2463, 0xA8EA, 0x2464, 0xA8EB, - 0x2465, 0xA8EC, 0x2466, 0xA8ED, 0x2467, 0xA8EE, 0x2468, 0xA8EF, - 0x2469, 0xA8F0, 0x246A, 0xA8F1, 0x246B, 0xA8F2, 0x246C, 0xA8F3, - 0x246D, 0xA8F4, 0x246E, 0xA8F5, 0x2474, 0xA9E7, 0x2475, 0xA9E8, - 0x2476, 0xA9E9, 0x2477, 0xA9EA, 0x2478, 0xA9EB, 0x2479, 0xA9EC, - 0x247A, 0xA9ED, 0x247B, 0xA9EE, 0x247C, 0xA9EF, 0x247D, 0xA9F0, - 0x247E, 0xA9F1, 0x247F, 0xA9F2, 0x2480, 0xA9F3, 0x2481, 0xA9F4, - 0x2482, 0xA9F5, 0x249C, 0xA9CD, 0x249D, 0xA9CE, 0x249E, 0xA9CF, - 0x249F, 0xA9D0, 0x24A0, 0xA9D1, 0x24A1, 0xA9D2, 0x24A2, 0xA9D3, - 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0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, - 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, - 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, - 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, - 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, - 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, - 0xFF5D, 0xA3FD, 0xFF5E, 0xA2A6, 0xFFE0, 0xA1CB, 0xFFE1, 0xA1CC, - 0xFFE2, 0xA1FE, 0xFFE3, 0xA3FE, 0xFFE5, 0xA1CD, 0xFFE6, 0xA3DC, - 0, 0 -}; - -static -const WCHAR oem2uni[] = { -/* OEM - Unicode, OEM - Unicode, OEM - Unicode, OEM - Unicode */ - 0x8141, 0xAC02, 0x8142, 0xAC03, 0x8143, 0xAC05, 0x8144, 0xAC06, - 0x8145, 0xAC0B, 0x8146, 0xAC0C, 0x8147, 0xAC0D, 0x8148, 0xAC0E, - 0x8149, 0xAC0F, 0x814A, 0xAC18, 0x814B, 0xAC1E, 0x814C, 0xAC1F, - 0x814D, 0xAC21, 0x814E, 0xAC22, 0x814F, 0xAC23, 0x8150, 0xAC25, - 0x8151, 0xAC26, 0x8152, 0xAC27, 0x8153, 0xAC28, 0x8154, 0xAC29, - 0x8155, 0xAC2A, 0x8156, 0xAC2B, 0x8157, 0xAC2E, 0x8158, 0xAC32, - 0x8159, 0xAC33, 0x815A, 0xAC34, 0x8161, 0xAC35, 0x8162, 0xAC36, - 0x8163, 0xAC37, 0x8164, 0xAC3A, 0x8165, 0xAC3B, 0x8166, 0xAC3D, - 0x8167, 0xAC3E, 0x8168, 0xAC3F, 0x8169, 0xAC41, 0x816A, 0xAC42, - 0x816B, 0xAC43, 0x816C, 0xAC44, 0x816D, 0xAC45, 0x816E, 0xAC46, - 0x816F, 0xAC47, 0x8170, 0xAC48, 0x8171, 0xAC49, 0x8172, 0xAC4A, - 0x8173, 0xAC4C, 0x8174, 0xAC4E, 0x8175, 0xAC4F, 0x8176, 0xAC50, - 0x8177, 0xAC51, 0x8178, 0xAC52, 0x8179, 0xAC53, 0x817A, 0xAC55, - 0x8181, 0xAC56, 0x8182, 0xAC57, 0x8183, 0xAC59, 0x8184, 0xAC5A, - 0x8185, 0xAC5B, 0x8186, 0xAC5D, 0x8187, 0xAC5E, 0x8188, 0xAC5F, - 0x8189, 0xAC60, 0x818A, 0xAC61, 0x818B, 0xAC62, 0x818C, 0xAC63, - 0x818D, 0xAC64, 0x818E, 0xAC65, 0x818F, 0xAC66, 0x8190, 0xAC67, - 0x8191, 0xAC68, 0x8192, 0xAC69, 0x8193, 0xAC6A, 0x8194, 0xAC6B, - 0x8195, 0xAC6C, 0x8196, 0xAC6D, 0x8197, 0xAC6E, 0x8198, 0xAC6F, - 0x8199, 0xAC72, 0x819A, 0xAC73, 0x819B, 0xAC75, 0x819C, 0xAC76, - 0x819D, 0xAC79, 0x819E, 0xAC7B, 0x819F, 0xAC7C, 0x81A0, 0xAC7D, - 0x81A1, 0xAC7E, 0x81A2, 0xAC7F, 0x81A3, 0xAC82, 0x81A4, 0xAC87, - 0x81A5, 0xAC88, 0x81A6, 0xAC8D, 0x81A7, 0xAC8E, 0x81A8, 0xAC8F, - 0x81A9, 0xAC91, 0x81AA, 0xAC92, 0x81AB, 0xAC93, 0x81AC, 0xAC95, - 0x81AD, 0xAC96, 0x81AE, 0xAC97, 0x81AF, 0xAC98, 0x81B0, 0xAC99, - 0x81B1, 0xAC9A, 0x81B2, 0xAC9B, 0x81B3, 0xAC9E, 0x81B4, 0xACA2, - 0x81B5, 0xACA3, 0x81B6, 0xACA4, 0x81B7, 0xACA5, 0x81B8, 0xACA6, - 0x81B9, 0xACA7, 0x81BA, 0xACAB, 0x81BB, 0xACAD, 0x81BC, 0xACAE, - 0x81BD, 0xACB1, 0x81BE, 0xACB2, 0x81BF, 0xACB3, 0x81C0, 0xACB4, - 0x81C1, 0xACB5, 0x81C2, 0xACB6, 0x81C3, 0xACB7, 0x81C4, 0xACBA, - 0x81C5, 0xACBE, 0x81C6, 0xACBF, 0x81C7, 0xACC0, 0x81C8, 0xACC2, - 0x81C9, 0xACC3, 0x81CA, 0xACC5, 0x81CB, 0xACC6, 0x81CC, 0xACC7, - 0x81CD, 0xACC9, 0x81CE, 0xACCA, 0x81CF, 0xACCB, 0x81D0, 0xACCD, - 0x81D1, 0xACCE, 0x81D2, 0xACCF, 0x81D3, 0xACD0, 0x81D4, 0xACD1, - 0x81D5, 0xACD2, 0x81D6, 0xACD3, 0x81D7, 0xACD4, 0x81D8, 0xACD6, - 0x81D9, 0xACD8, 0x81DA, 0xACD9, 0x81DB, 0xACDA, 0x81DC, 0xACDB, - 0x81DD, 0xACDC, 0x81DE, 0xACDD, 0x81DF, 0xACDE, 0x81E0, 0xACDF, - 0x81E1, 0xACE2, 0x81E2, 0xACE3, 0x81E3, 0xACE5, 0x81E4, 0xACE6, - 0x81E5, 0xACE9, 0x81E6, 0xACEB, 0x81E7, 0xACED, 0x81E8, 0xACEE, - 0x81E9, 0xACF2, 0x81EA, 0xACF4, 0x81EB, 0xACF7, 0x81EC, 0xACF8, - 0x81ED, 0xACF9, 0x81EE, 0xACFA, 0x81EF, 0xACFB, 0x81F0, 0xACFE, - 0x81F1, 0xACFF, 0x81F2, 0xAD01, 0x81F3, 0xAD02, 0x81F4, 0xAD03, - 0x81F5, 0xAD05, 0x81F6, 0xAD07, 0x81F7, 0xAD08, 0x81F8, 0xAD09, - 0x81F9, 0xAD0A, 0x81FA, 0xAD0B, 0x81FB, 0xAD0E, 0x81FC, 0xAD10, - 0x81FD, 0xAD12, 0x81FE, 0xAD13, 0x8241, 0xAD14, 0x8242, 0xAD15, - 0x8243, 0xAD16, 0x8244, 0xAD17, 0x8245, 0xAD19, 0x8246, 0xAD1A, - 0x8247, 0xAD1B, 0x8248, 0xAD1D, 0x8249, 0xAD1E, 0x824A, 0xAD1F, - 0x824B, 0xAD21, 0x824C, 0xAD22, 0x824D, 0xAD23, 0x824E, 0xAD24, - 0x824F, 0xAD25, 0x8250, 0xAD26, 0x8251, 0xAD27, 0x8252, 0xAD28, - 0x8253, 0xAD2A, 0x8254, 0xAD2B, 0x8255, 0xAD2E, 0x8256, 0xAD2F, - 0x8257, 0xAD30, 0x8258, 0xAD31, 0x8259, 0xAD32, 0x825A, 0xAD33, - 0x8261, 0xAD36, 0x8262, 0xAD37, 0x8263, 0xAD39, 0x8264, 0xAD3A, - 0x8265, 0xAD3B, 0x8266, 0xAD3D, 0x8267, 0xAD3E, 0x8268, 0xAD3F, - 0x8269, 0xAD40, 0x826A, 0xAD41, 0x826B, 0xAD42, 0x826C, 0xAD43, - 0x826D, 0xAD46, 0x826E, 0xAD48, 0x826F, 0xAD4A, 0x8270, 0xAD4B, - 0x8271, 0xAD4C, 0x8272, 0xAD4D, 0x8273, 0xAD4E, 0x8274, 0xAD4F, - 0x8275, 0xAD51, 0x8276, 0xAD52, 0x8277, 0xAD53, 0x8278, 0xAD55, - 0x8279, 0xAD56, 0x827A, 0xAD57, 0x8281, 0xAD59, 0x8282, 0xAD5A, - 0x8283, 0xAD5B, 0x8284, 0xAD5C, 0x8285, 0xAD5D, 0x8286, 0xAD5E, - 0x8287, 0xAD5F, 0x8288, 0xAD60, 0x8289, 0xAD62, 0x828A, 0xAD64, - 0x828B, 0xAD65, 0x828C, 0xAD66, 0x828D, 0xAD67, 0x828E, 0xAD68, - 0x828F, 0xAD69, 0x8290, 0xAD6A, 0x8291, 0xAD6B, 0x8292, 0xAD6E, - 0x8293, 0xAD6F, 0x8294, 0xAD71, 0x8295, 0xAD72, 0x8296, 0xAD77, - 0x8297, 0xAD78, 0x8298, 0xAD79, 0x8299, 0xAD7A, 0x829A, 0xAD7E, - 0x829B, 0xAD80, 0x829C, 0xAD83, 0x829D, 0xAD84, 0x829E, 0xAD85, - 0x829F, 0xAD86, 0x82A0, 0xAD87, 0x82A1, 0xAD8A, 0x82A2, 0xAD8B, - 0x82A3, 0xAD8D, 0x82A4, 0xAD8E, 0x82A5, 0xAD8F, 0x82A6, 0xAD91, - 0x82A7, 0xAD92, 0x82A8, 0xAD93, 0x82A9, 0xAD94, 0x82AA, 0xAD95, - 0x82AB, 0xAD96, 0x82AC, 0xAD97, 0x82AD, 0xAD98, 0x82AE, 0xAD99, - 0x82AF, 0xAD9A, 0x82B0, 0xAD9B, 0x82B1, 0xAD9E, 0x82B2, 0xAD9F, - 0x82B3, 0xADA0, 0x82B4, 0xADA1, 0x82B5, 0xADA2, 0x82B6, 0xADA3, - 0x82B7, 0xADA5, 0x82B8, 0xADA6, 0x82B9, 0xADA7, 0x82BA, 0xADA8, - 0x82BB, 0xADA9, 0x82BC, 0xADAA, 0x82BD, 0xADAB, 0x82BE, 0xADAC, - 0x82BF, 0xADAD, 0x82C0, 0xADAE, 0x82C1, 0xADAF, 0x82C2, 0xADB0, - 0x82C3, 0xADB1, 0x82C4, 0xADB2, 0x82C5, 0xADB3, 0x82C6, 0xADB4, - 0x82C7, 0xADB5, 0x82C8, 0xADB6, 0x82C9, 0xADB8, 0x82CA, 0xADB9, - 0x82CB, 0xADBA, 0x82CC, 0xADBB, 0x82CD, 0xADBC, 0x82CE, 0xADBD, - 0x82CF, 0xADBE, 0x82D0, 0xADBF, 0x82D1, 0xADC2, 0x82D2, 0xADC3, - 0x82D3, 0xADC5, 0x82D4, 0xADC6, 0x82D5, 0xADC7, 0x82D6, 0xADC9, - 0x82D7, 0xADCA, 0x82D8, 0xADCB, 0x82D9, 0xADCC, 0x82DA, 0xADCD, - 0x82DB, 0xADCE, 0x82DC, 0xADCF, 0x82DD, 0xADD2, 0x82DE, 0xADD4, - 0x82DF, 0xADD5, 0x82E0, 0xADD6, 0x82E1, 0xADD7, 0x82E2, 0xADD8, - 0x82E3, 0xADD9, 0x82E4, 0xADDA, 0x82E5, 0xADDB, 0x82E6, 0xADDD, - 0x82E7, 0xADDE, 0x82E8, 0xADDF, 0x82E9, 0xADE1, 0x82EA, 0xADE2, - 0x82EB, 0xADE3, 0x82EC, 0xADE5, 0x82ED, 0xADE6, 0x82EE, 0xADE7, - 0x82EF, 0xADE8, 0x82F0, 0xADE9, 0x82F1, 0xADEA, 0x82F2, 0xADEB, - 0x82F3, 0xADEC, 0x82F4, 0xADED, 0x82F5, 0xADEE, 0x82F6, 0xADEF, - 0x82F7, 0xADF0, 0x82F8, 0xADF1, 0x82F9, 0xADF2, 0x82FA, 0xADF3, - 0x82FB, 0xADF4, 0x82FC, 0xADF5, 0x82FD, 0xADF6, 0x82FE, 0xADF7, - 0x8341, 0xADFA, 0x8342, 0xADFB, 0x8343, 0xADFD, 0x8344, 0xADFE, - 0x8345, 0xAE02, 0x8346, 0xAE03, 0x8347, 0xAE04, 0x8348, 0xAE05, - 0x8349, 0xAE06, 0x834A, 0xAE07, 0x834B, 0xAE0A, 0x834C, 0xAE0C, - 0x834D, 0xAE0E, 0x834E, 0xAE0F, 0x834F, 0xAE10, 0x8350, 0xAE11, - 0x8351, 0xAE12, 0x8352, 0xAE13, 0x8353, 0xAE15, 0x8354, 0xAE16, - 0x8355, 0xAE17, 0x8356, 0xAE18, 0x8357, 0xAE19, 0x8358, 0xAE1A, - 0x8359, 0xAE1B, 0x835A, 0xAE1C, 0x8361, 0xAE1D, 0x8362, 0xAE1E, - 0x8363, 0xAE1F, 0x8364, 0xAE20, 0x8365, 0xAE21, 0x8366, 0xAE22, - 0x8367, 0xAE23, 0x8368, 0xAE24, 0x8369, 0xAE25, 0x836A, 0xAE26, - 0x836B, 0xAE27, 0x836C, 0xAE28, 0x836D, 0xAE29, 0x836E, 0xAE2A, - 0x836F, 0xAE2B, 0x8370, 0xAE2C, 0x8371, 0xAE2D, 0x8372, 0xAE2E, - 0x8373, 0xAE2F, 0x8374, 0xAE32, 0x8375, 0xAE33, 0x8376, 0xAE35, - 0x8377, 0xAE36, 0x8378, 0xAE39, 0x8379, 0xAE3B, 0x837A, 0xAE3C, - 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0xF8D5, 0x5703, 0xF8D6, 0x5E03, 0xF8D7, 0x6016, 0xF8D8, 0x629B, - 0xF8D9, 0x62B1, 0xF8DA, 0x6355, 0xF8DB, 0xFA06, 0xF8DC, 0x6CE1, - 0xF8DD, 0x6D66, 0xF8DE, 0x75B1, 0xF8DF, 0x7832, 0xF8E0, 0x80DE, - 0xF8E1, 0x812F, 0xF8E2, 0x82DE, 0xF8E3, 0x8461, 0xF8E4, 0x84B2, - 0xF8E5, 0x888D, 0xF8E6, 0x8912, 0xF8E7, 0x900B, 0xF8E8, 0x92EA, - 0xF8E9, 0x98FD, 0xF8EA, 0x9B91, 0xF8EB, 0x5E45, 0xF8EC, 0x66B4, - 0xF8ED, 0x66DD, 0xF8EE, 0x7011, 0xF8EF, 0x7206, 0xF8F0, 0xFA07, - 0xF8F1, 0x4FF5, 0xF8F2, 0x527D, 0xF8F3, 0x5F6A, 0xF8F4, 0x6153, - 0xF8F5, 0x6753, 0xF8F6, 0x6A19, 0xF8F7, 0x6F02, 0xF8F8, 0x74E2, - 0xF8F9, 0x7968, 0xF8FA, 0x8868, 0xF8FB, 0x8C79, 0xF8FC, 0x98C7, - 0xF8FD, 0x98C4, 0xF8FE, 0x9A43, 0xF9A1, 0x54C1, 0xF9A2, 0x7A1F, - 0xF9A3, 0x6953, 0xF9A4, 0x8AF7, 0xF9A5, 0x8C4A, 0xF9A6, 0x98A8, - 0xF9A7, 0x99AE, 0xF9A8, 0x5F7C, 0xF9A9, 0x62AB, 0xF9AA, 0x75B2, - 0xF9AB, 0x76AE, 0xF9AC, 0x88AB, 0xF9AD, 0x907F, 0xF9AE, 0x9642, - 0xF9AF, 0x5339, 0xF9B0, 0x5F3C, 0xF9B1, 0x5FC5, 0xF9B2, 0x6CCC, - 0xF9B3, 0x73CC, 0xF9B4, 0x7562, 0xF9B5, 0x758B, 0xF9B6, 0x7B46, - 0xF9B7, 0x82FE, 0xF9B8, 0x999D, 0xF9B9, 0x4E4F, 0xF9BA, 0x903C, - 0xF9BB, 0x4E0B, 0xF9BC, 0x4F55, 0xF9BD, 0x53A6, 0xF9BE, 0x590F, - 0xF9BF, 0x5EC8, 0xF9C0, 0x6630, 0xF9C1, 0x6CB3, 0xF9C2, 0x7455, - 0xF9C3, 0x8377, 0xF9C4, 0x8766, 0xF9C5, 0x8CC0, 0xF9C6, 0x9050, - 0xF9C7, 0x971E, 0xF9C8, 0x9C15, 0xF9C9, 0x58D1, 0xF9CA, 0x5B78, - 0xF9CB, 0x8650, 0xF9CC, 0x8B14, 0xF9CD, 0x9DB4, 0xF9CE, 0x5BD2, - 0xF9CF, 0x6068, 0xF9D0, 0x608D, 0xF9D1, 0x65F1, 0xF9D2, 0x6C57, - 0xF9D3, 0x6F22, 0xF9D4, 0x6FA3, 0xF9D5, 0x701A, 0xF9D6, 0x7F55, - 0xF9D7, 0x7FF0, 0xF9D8, 0x9591, 0xF9D9, 0x9592, 0xF9DA, 0x9650, - 0xF9DB, 0x97D3, 0xF9DC, 0x5272, 0xF9DD, 0x8F44, 0xF9DE, 0x51FD, - 0xF9DF, 0x542B, 0xF9E0, 0x54B8, 0xF9E1, 0x5563, 0xF9E2, 0x558A, - 0xF9E3, 0x6ABB, 0xF9E4, 0x6DB5, 0xF9E5, 0x7DD8, 0xF9E6, 0x8266, - 0xF9E7, 0x929C, 0xF9E8, 0x9677, 0xF9E9, 0x9E79, 0xF9EA, 0x5408, - 0xF9EB, 0x54C8, 0xF9EC, 0x76D2, 0xF9ED, 0x86E4, 0xF9EE, 0x95A4, - 0xF9EF, 0x95D4, 0xF9F0, 0x965C, 0xF9F1, 0x4EA2, 0xF9F2, 0x4F09, - 0xF9F3, 0x59EE, 0xF9F4, 0x5AE6, 0xF9F5, 0x5DF7, 0xF9F6, 0x6052, - 0xF9F7, 0x6297, 0xF9F8, 0x676D, 0xF9F9, 0x6841, 0xF9FA, 0x6C86, - 0xF9FB, 0x6E2F, 0xF9FC, 0x7F38, 0xF9FD, 0x809B, 0xF9FE, 0x822A, - 0xFAA1, 0xFA08, 0xFAA2, 0xFA09, 0xFAA3, 0x9805, 0xFAA4, 0x4EA5, - 0xFAA5, 0x5055, 0xFAA6, 0x54B3, 0xFAA7, 0x5793, 0xFAA8, 0x595A, - 0xFAA9, 0x5B69, 0xFAAA, 0x5BB3, 0xFAAB, 0x61C8, 0xFAAC, 0x6977, - 0xFAAD, 0x6D77, 0xFAAE, 0x7023, 0xFAAF, 0x87F9, 0xFAB0, 0x89E3, - 0xFAB1, 0x8A72, 0xFAB2, 0x8AE7, 0xFAB3, 0x9082, 0xFAB4, 0x99ED, - 0xFAB5, 0x9AB8, 0xFAB6, 0x52BE, 0xFAB7, 0x6838, 0xFAB8, 0x5016, - 0xFAB9, 0x5E78, 0xFABA, 0x674F, 0xFABB, 0x8347, 0xFABC, 0x884C, - 0xFABD, 0x4EAB, 0xFABE, 0x5411, 0xFABF, 0x56AE, 0xFAC0, 0x73E6, - 0xFAC1, 0x9115, 0xFAC2, 0x97FF, 0xFAC3, 0x9909, 0xFAC4, 0x9957, - 0xFAC5, 0x9999, 0xFAC6, 0x5653, 0xFAC7, 0x589F, 0xFAC8, 0x865B, - 0xFAC9, 0x8A31, 0xFACA, 0x61B2, 0xFACB, 0x6AF6, 0xFACC, 0x737B, - 0xFACD, 0x8ED2, 0xFACE, 0x6B47, 0xFACF, 0x96AA, 0xFAD0, 0x9A57, - 0xFAD1, 0x5955, 0xFAD2, 0x7200, 0xFAD3, 0x8D6B, 0xFAD4, 0x9769, - 0xFAD5, 0x4FD4, 0xFAD6, 0x5CF4, 0xFAD7, 0x5F26, 0xFAD8, 0x61F8, - 0xFAD9, 0x665B, 0xFADA, 0x6CEB, 0xFADB, 0x70AB, 0xFADC, 0x7384, - 0xFADD, 0x73B9, 0xFADE, 0x73FE, 0xFADF, 0x7729, 0xFAE0, 0x774D, - 0xFAE1, 0x7D43, 0xFAE2, 0x7D62, 0xFAE3, 0x7E23, 0xFAE4, 0x8237, - 0xFAE5, 0x8852, 0xFAE6, 0xFA0A, 0xFAE7, 0x8CE2, 0xFAE8, 0x9249, - 0xFAE9, 0x986F, 0xFAEA, 0x5B51, 0xFAEB, 0x7A74, 0xFAEC, 0x8840, - 0xFAED, 0x9801, 0xFAEE, 0x5ACC, 0xFAEF, 0x4FE0, 0xFAF0, 0x5354, - 0xFAF1, 0x593E, 0xFAF2, 0x5CFD, 0xFAF3, 0x633E, 0xFAF4, 0x6D79, - 0xFAF5, 0x72F9, 0xFAF6, 0x8105, 0xFAF7, 0x8107, 0xFAF8, 0x83A2, - 0xFAF9, 0x92CF, 0xFAFA, 0x9830, 0xFAFB, 0x4EA8, 0xFAFC, 0x5144, - 0xFAFD, 0x5211, 0xFAFE, 0x578B, 0xFBA1, 0x5F62, 0xFBA2, 0x6CC2, - 0xFBA3, 0x6ECE, 0xFBA4, 0x7005, 0xFBA5, 0x7050, 0xFBA6, 0x70AF, - 0xFBA7, 0x7192, 0xFBA8, 0x73E9, 0xFBA9, 0x7469, 0xFBAA, 0x834A, - 0xFBAB, 0x87A2, 0xFBAC, 0x8861, 0xFBAD, 0x9008, 0xFBAE, 0x90A2, - 0xFBAF, 0x93A3, 0xFBB0, 0x99A8, 0xFBB1, 0x516E, 0xFBB2, 0x5F57, - 0xFBB3, 0x60E0, 0xFBB4, 0x6167, 0xFBB5, 0x66B3, 0xFBB6, 0x8559, - 0xFBB7, 0x8E4A, 0xFBB8, 0x91AF, 0xFBB9, 0x978B, 0xFBBA, 0x4E4E, - 0xFBBB, 0x4E92, 0xFBBC, 0x547C, 0xFBBD, 0x58D5, 0xFBBE, 0x58FA, - 0xFBBF, 0x597D, 0xFBC0, 0x5CB5, 0xFBC1, 0x5F27, 0xFBC2, 0x6236, - 0xFBC3, 0x6248, 0xFBC4, 0x660A, 0xFBC5, 0x6667, 0xFBC6, 0x6BEB, - 0xFBC7, 0x6D69, 0xFBC8, 0x6DCF, 0xFBC9, 0x6E56, 0xFBCA, 0x6EF8, - 0xFBCB, 0x6F94, 0xFBCC, 0x6FE0, 0xFBCD, 0x6FE9, 0xFBCE, 0x705D, - 0xFBCF, 0x72D0, 0xFBD0, 0x7425, 0xFBD1, 0x745A, 0xFBD2, 0x74E0, - 0xFBD3, 0x7693, 0xFBD4, 0x795C, 0xFBD5, 0x7CCA, 0xFBD6, 0x7E1E, - 0xFBD7, 0x80E1, 0xFBD8, 0x82A6, 0xFBD9, 0x846B, 0xFBDA, 0x84BF, - 0xFBDB, 0x864E, 0xFBDC, 0x865F, 0xFBDD, 0x8774, 0xFBDE, 0x8B77, - 0xFBDF, 0x8C6A, 0xFBE0, 0x93AC, 0xFBE1, 0x9800, 0xFBE2, 0x9865, - 0xFBE3, 0x60D1, 0xFBE4, 0x6216, 0xFBE5, 0x9177, 0xFBE6, 0x5A5A, - 0xFBE7, 0x660F, 0xFBE8, 0x6DF7, 0xFBE9, 0x6E3E, 0xFBEA, 0x743F, - 0xFBEB, 0x9B42, 0xFBEC, 0x5FFD, 0xFBED, 0x60DA, 0xFBEE, 0x7B0F, - 0xFBEF, 0x54C4, 0xFBF0, 0x5F18, 0xFBF1, 0x6C5E, 0xFBF2, 0x6CD3, - 0xFBF3, 0x6D2A, 0xFBF4, 0x70D8, 0xFBF5, 0x7D05, 0xFBF6, 0x8679, - 0xFBF7, 0x8A0C, 0xFBF8, 0x9D3B, 0xFBF9, 0x5316, 0xFBFA, 0x548C, - 0xFBFB, 0x5B05, 0xFBFC, 0x6A3A, 0xFBFD, 0x706B, 0xFBFE, 0x7575, - 0xFCA1, 0x798D, 0xFCA2, 0x79BE, 0xFCA3, 0x82B1, 0xFCA4, 0x83EF, - 0xFCA5, 0x8A71, 0xFCA6, 0x8B41, 0xFCA7, 0x8CA8, 0xFCA8, 0x9774, - 0xFCA9, 0xFA0B, 0xFCAA, 0x64F4, 0xFCAB, 0x652B, 0xFCAC, 0x78BA, - 0xFCAD, 0x78BB, 0xFCAE, 0x7A6B, 0xFCAF, 0x4E38, 0xFCB0, 0x559A, - 0xFCB1, 0x5950, 0xFCB2, 0x5BA6, 0xFCB3, 0x5E7B, 0xFCB4, 0x60A3, - 0xFCB5, 0x63DB, 0xFCB6, 0x6B61, 0xFCB7, 0x6665, 0xFCB8, 0x6853, - 0xFCB9, 0x6E19, 0xFCBA, 0x7165, 0xFCBB, 0x74B0, 0xFCBC, 0x7D08, - 0xFCBD, 0x9084, 0xFCBE, 0x9A69, 0xFCBF, 0x9C25, 0xFCC0, 0x6D3B, - 0xFCC1, 0x6ED1, 0xFCC2, 0x733E, 0xFCC3, 0x8C41, 0xFCC4, 0x95CA, - 0xFCC5, 0x51F0, 0xFCC6, 0x5E4C, 0xFCC7, 0x5FA8, 0xFCC8, 0x604D, - 0xFCC9, 0x60F6, 0xFCCA, 0x6130, 0xFCCB, 0x614C, 0xFCCC, 0x6643, - 0xFCCD, 0x6644, 0xFCCE, 0x69A5, 0xFCCF, 0x6CC1, 0xFCD0, 0x6E5F, - 0xFCD1, 0x6EC9, 0xFCD2, 0x6F62, 0xFCD3, 0x714C, 0xFCD4, 0x749C, - 0xFCD5, 0x7687, 0xFCD6, 0x7BC1, 0xFCD7, 0x7C27, 0xFCD8, 0x8352, - 0xFCD9, 0x8757, 0xFCDA, 0x9051, 0xFCDB, 0x968D, 0xFCDC, 0x9EC3, - 0xFCDD, 0x532F, 0xFCDE, 0x56DE, 0xFCDF, 0x5EFB, 0xFCE0, 0x5F8A, - 0xFCE1, 0x6062, 0xFCE2, 0x6094, 0xFCE3, 0x61F7, 0xFCE4, 0x6666, - 0xFCE5, 0x6703, 0xFCE6, 0x6A9C, 0xFCE7, 0x6DEE, 0xFCE8, 0x6FAE, - 0xFCE9, 0x7070, 0xFCEA, 0x736A, 0xFCEB, 0x7E6A, 0xFCEC, 0x81BE, - 0xFCED, 0x8334, 0xFCEE, 0x86D4, 0xFCEF, 0x8AA8, 0xFCF0, 0x8CC4, - 0xFCF1, 0x5283, 0xFCF2, 0x7372, 0xFCF3, 0x5B96, 0xFCF4, 0x6A6B, - 0xFCF5, 0x9404, 0xFCF6, 0x54EE, 0xFCF7, 0x5686, 0xFCF8, 0x5B5D, - 0xFCF9, 0x6548, 0xFCFA, 0x6585, 0xFCFB, 0x66C9, 0xFCFC, 0x689F, - 0xFCFD, 0x6D8D, 0xFCFE, 0x6DC6, 0xFDA1, 0x723B, 0xFDA2, 0x80B4, - 0xFDA3, 0x9175, 0xFDA4, 0x9A4D, 0xFDA5, 0x4FAF, 0xFDA6, 0x5019, - 0xFDA7, 0x539A, 0xFDA8, 0x540E, 0xFDA9, 0x543C, 0xFDAA, 0x5589, - 0xFDAB, 0x55C5, 0xFDAC, 0x5E3F, 0xFDAD, 0x5F8C, 0xFDAE, 0x673D, - 0xFDAF, 0x7166, 0xFDB0, 0x73DD, 0xFDB1, 0x9005, 0xFDB2, 0x52DB, - 0xFDB3, 0x52F3, 0xFDB4, 0x5864, 0xFDB5, 0x58CE, 0xFDB6, 0x7104, - 0xFDB7, 0x718F, 0xFDB8, 0x71FB, 0xFDB9, 0x85B0, 0xFDBA, 0x8A13, - 0xFDBB, 0x6688, 0xFDBC, 0x85A8, 0xFDBD, 0x55A7, 0xFDBE, 0x6684, - 0xFDBF, 0x714A, 0xFDC0, 0x8431, 0xFDC1, 0x5349, 0xFDC2, 0x5599, - 0xFDC3, 0x6BC1, 0xFDC4, 0x5F59, 0xFDC5, 0x5FBD, 0xFDC6, 0x63EE, - 0xFDC7, 0x6689, 0xFDC8, 0x7147, 0xFDC9, 0x8AF1, 0xFDCA, 0x8F1D, - 0xFDCB, 0x9EBE, 0xFDCC, 0x4F11, 0xFDCD, 0x643A, 0xFDCE, 0x70CB, - 0xFDCF, 0x7566, 0xFDD0, 0x8667, 0xFDD1, 0x6064, 0xFDD2, 0x8B4E, - 0xFDD3, 0x9DF8, 0xFDD4, 0x5147, 0xFDD5, 0x51F6, 0xFDD6, 0x5308, - 0xFDD7, 0x6D36, 0xFDD8, 0x80F8, 0xFDD9, 0x9ED1, 0xFDDA, 0x6615, - 0xFDDB, 0x6B23, 0xFDDC, 0x7098, 0xFDDD, 0x75D5, 0xFDDE, 0x5403, - 0xFDDF, 0x5C79, 0xFDE0, 0x7D07, 0xFDE1, 0x8A16, 0xFDE2, 0x6B20, - 0xFDE3, 0x6B3D, 0xFDE4, 0x6B46, 0xFDE5, 0x5438, 0xFDE6, 0x6070, - 0xFDE7, 0x6D3D, 0xFDE8, 0x7FD5, 0xFDE9, 0x8208, 0xFDEA, 0x50D6, - 0xFDEB, 0x51DE, 0xFDEC, 0x559C, 0xFDED, 0x566B, 0xFDEE, 0x56CD, - 0xFDEF, 0x59EC, 0xFDF0, 0x5B09, 0xFDF1, 0x5E0C, 0xFDF2, 0x6199, - 0xFDF3, 0x6198, 0xFDF4, 0x6231, 0xFDF5, 0x665E, 0xFDF6, 0x66E6, - 0xFDF7, 0x7199, 0xFDF8, 0x71B9, 0xFDF9, 0x71BA, 0xFDFA, 0x72A7, - 0xFDFB, 0x79A7, 0xFDFC, 0x7A00, 0xFDFD, 0x7FB2, 0xFDFE, 0x8A70, - 0, 0 -}; - - - -WCHAR ff_convert ( /* Converted code, 0 means conversion error */ - WCHAR chr, /* Character code to be converted */ - UINT dir /* 0: Unicode to OEM code, 1: OEM code to Unicode */ -) -{ - const WCHAR *p; - WCHAR c; - int i, n, li, hi; - - - if (chr < 0x80) { /* ASCII */ - c = chr; - } else { - if (dir) { /* OEM code to unicode */ - p = oem2uni; - hi = sizeof oem2uni / 4 - 1; - } else { /* Unicode to OEM code */ - p = uni2oem; - hi = sizeof uni2oem / 4 - 1; - } - li = 0; - for (n = 16; n; n--) { - i = li + (hi - li) / 2; - if (chr == p[i * 2]) break; - if (chr > p[i * 2]) - li = i; - else - hi = i; - } - c = n ? p[i * 2 + 1] : 0; - } - - return c; -} - - - -WCHAR ff_wtoupper ( /* Returns upper converted character */ - WCHAR chr /* Unicode character to be upper converted (BMP only) */ -) -{ - /* Compressed upper conversion table */ - static const WCHAR cvt1[] = { /* U+0000 - U+0FFF */ - /* Basic Latin */ - 0x0061,0x031A, - /* Latin-1 Supplement */ - 0x00E0,0x0317, 0x00F8,0x0307, 0x00FF,0x0001,0x0178, - /* Latin Extended-A */ - 0x0100,0x0130, 0x0132,0x0106, 0x0139,0x0110, 0x014A,0x012E, 0x0179,0x0106, - /* Latin Extended-B */ - 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, - 0x01CD,0x0110, 0x01DD,0x0001,0x018E, 0x01DE,0x0112, 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, 0x01F8,0x0128, - 0x0222,0x0112, 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, 0x0246,0x010A, - /* IPA Extensions */ - 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, - /* Greek, Coptic */ - 0x037B,0x0003,0x03FD,0x03FE,0x03FF, 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, 0x03B1,0x0311, - 0x03C2,0x0002,0x03A3,0x03A3, 0x03C4,0x0308, 0x03CC,0x0003,0x038C,0x038E,0x038F, 0x03D8,0x0118, - 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, - /* Cyrillic */ - 0x0430,0x0320, 0x0450,0x0710, 0x0460,0x0122, 0x048A,0x0136, 0x04C1,0x010E, 0x04CF,0x0001,0x04C0, 0x04D0,0x0144, - /* Armenian */ - 0x0561,0x0426, - - 0x0000 - }; - static const WCHAR cvt2[] = { /* U+1000 - U+FFFF */ - /* Phonetic Extensions */ - 0x1D7D,0x0001,0x2C63, - /* Latin Extended Additional */ - 0x1E00,0x0196, 0x1EA0,0x015A, - /* Greek Extended */ - 0x1F00,0x0608, 0x1F10,0x0606, 0x1F20,0x0608, 0x1F30,0x0608, 0x1F40,0x0606, - 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, 0x1F60,0x0608, - 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, - 0x1F80,0x0608, 0x1F90,0x0608, 0x1FA0,0x0608, 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, - 0x1FCC,0x0001,0x1FC3, 0x1FD0,0x0602, 0x1FE0,0x0602, 0x1FE5,0x0001,0x1FEC, 0x1FF2,0x0001,0x1FFC, - /* Letterlike Symbols */ - 0x214E,0x0001,0x2132, - /* Number forms */ - 0x2170,0x0210, 0x2184,0x0001,0x2183, - /* Enclosed Alphanumerics */ - 0x24D0,0x051A, 0x2C30,0x042F, - /* Latin Extended-C */ - 0x2C60,0x0102, 0x2C67,0x0106, 0x2C75,0x0102, - /* Coptic */ - 0x2C80,0x0164, - /* Georgian Supplement */ - 0x2D00,0x0826, - /* Full-width */ - 0xFF41,0x031A, - - 0x0000 - }; - const WCHAR *p; - WCHAR bc, nc, cmd; - - - p = chr < 0x1000 ? cvt1 : cvt2; - for (;;) { - bc = *p++; /* Get block base */ - if (!bc || chr < bc) break; - nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ - if (chr < bc + nc) { /* In the block? */ - switch (cmd) { - case 0: chr = p[chr - bc]; break; /* Table conversion */ - case 1: chr -= (chr - bc) & 1; break; /* Case pairs */ - case 2: chr -= 16; break; /* Shift -16 */ - case 3: chr -= 32; break; /* Shift -32 */ - case 4: chr -= 48; break; /* Shift -48 */ - case 5: chr -= 26; break; /* Shift -26 */ - case 6: chr += 8; break; /* Shift +8 */ - case 7: chr -= 80; break; /* Shift -80 */ - case 8: chr -= 0x1C60; break; /* Shift -0x1C60 */ - } - break; - } - if (!cmd) p += nc; - } - - return chr; -} - +/*------------------------------------------------------------------------*/ +/* Unicode - OEM code bidirectional converter (C)ChaN, 2015 */ +/* CP949 (Korean EUC-KR) */ +/*------------------------------------------------------------------------*/ + +#include "../ff.h" + + +#if !_USE_LFN || _CODE_PAGE != 949 +#error This file is not needed in current configuration. Remove from the project. +#endif + + +static +const WCHAR uni2oem[] = { +/* Unicode - OEM, Unicode - OEM, Unicode - OEM, Unicode - OEM */ + 0x00A1, 0xA2AE, 0x00A4, 0xA2B4, 0x00A7, 0xA1D7, 0x00A8, 0xA1A7, + 0x00AA, 0xA8A3, 0x00AD, 0xA1A9, 0x00AE, 0xA2E7, 0x00B0, 0xA1C6, + 0x00B1, 0xA1BE, 0x00B2, 0xA9F7, 0x00B3, 0xA9F8, 0x00B4, 0xA2A5, + 0x00B6, 0xA2D2, 0x00B7, 0xA1A4, 0x00B8, 0xA2AC, 0x00B9, 0xA9F6, + 0x00BA, 0xA8AC, 0x00BC, 0xA8F9, 0x00BD, 0xA8F6, 0x00BE, 0xA8FA, + 0x00BF, 0xA2AF, 0x00C6, 0xA8A1, 0x00D0, 0xA8A2, 0x00D7, 0xA1BF, + 0x00D8, 0xA8AA, 0x00DE, 0xA8AD, 0x00DF, 0xA9AC, 0x00E6, 0xA9A1, + 0x00F0, 0xA9A3, 0x00F7, 0xA1C0, 0x00F8, 0xA9AA, 0x00FE, 0xA9AD, + 0x0111, 0xA9A2, 0x0126, 0xA8A4, 0x0127, 0xA9A4, 0x0131, 0xA9A5, + 0x0132, 0xA8A6, 0x0133, 0xA9A6, 0x0138, 0xA9A7, 0x013F, 0xA8A8, + 0x0140, 0xA9A8, 0x0141, 0xA8A9, 0x0142, 0xA9A9, 0x0149, 0xA9B0, + 0x014A, 0xA8AF, 0x014B, 0xA9AF, 0x0152, 0xA8AB, 0x0153, 0xA9AB, + 0x0166, 0xA8AE, 0x0167, 0xA9AE, 0x02C7, 0xA2A7, 0x02D0, 0xA2B0, + 0x02D8, 0xA2A8, 0x02D9, 0xA2AB, 0x02DA, 0xA2AA, 0x02DB, 0xA2AD, + 0x02DD, 0xA2A9, 0x0391, 0xA5C1, 0x0392, 0xA5C2, 0x0393, 0xA5C3, + 0x0394, 0xA5C4, 0x0395, 0xA5C5, 0x0396, 0xA5C6, 0x0397, 0xA5C7, + 0x0398, 0xA5C8, 0x0399, 0xA5C9, 0x039A, 0xA5CA, 0x039B, 0xA5CB, + 0x039C, 0xA5CC, 0x039D, 0xA5CD, 0x039E, 0xA5CE, 0x039F, 0xA5CF, + 0x03A0, 0xA5D0, 0x03A1, 0xA5D1, 0x03A3, 0xA5D2, 0x03A4, 0xA5D3, + 0x03A5, 0xA5D4, 0x03A6, 0xA5D5, 0x03A7, 0xA5D6, 0x03A8, 0xA5D7, + 0x03A9, 0xA5D8, 0x03B1, 0xA5E1, 0x03B2, 0xA5E2, 0x03B3, 0xA5E3, + 0x03B4, 0xA5E4, 0x03B5, 0xA5E5, 0x03B6, 0xA5E6, 0x03B7, 0xA5E7, + 0x03B8, 0xA5E8, 0x03B9, 0xA5E9, 0x03BA, 0xA5EA, 0x03BB, 0xA5EB, + 0x03BC, 0xA5EC, 0x03BD, 0xA5ED, 0x03BE, 0xA5EE, 0x03BF, 0xA5EF, + 0x03C0, 0xA5F0, 0x03C1, 0xA5F1, 0x03C3, 0xA5F2, 0x03C4, 0xA5F3, + 0x03C5, 0xA5F4, 0x03C6, 0xA5F5, 0x03C7, 0xA5F6, 0x03C8, 0xA5F7, + 0x03C9, 0xA5F8, 0x0401, 0xACA7, 0x0410, 0xACA1, 0x0411, 0xACA2, + 0x0412, 0xACA3, 0x0413, 0xACA4, 0x0414, 0xACA5, 0x0415, 0xACA6, + 0x0416, 0xACA8, 0x0417, 0xACA9, 0x0418, 0xACAA, 0x0419, 0xACAB, + 0x041A, 0xACAC, 0x041B, 0xACAD, 0x041C, 0xACAE, 0x041D, 0xACAF, + 0x041E, 0xACB0, 0x041F, 0xACB1, 0x0420, 0xACB2, 0x0421, 0xACB3, + 0x0422, 0xACB4, 0x0423, 0xACB5, 0x0424, 0xACB6, 0x0425, 0xACB7, + 0x0426, 0xACB8, 0x0427, 0xACB9, 0x0428, 0xACBA, 0x0429, 0xACBB, + 0x042A, 0xACBC, 0x042B, 0xACBD, 0x042C, 0xACBE, 0x042D, 0xACBF, + 0x042E, 0xACC0, 0x042F, 0xACC1, 0x0430, 0xACD1, 0x0431, 0xACD2, + 0x0432, 0xACD3, 0x0433, 0xACD4, 0x0434, 0xACD5, 0x0435, 0xACD6, + 0x0436, 0xACD8, 0x0437, 0xACD9, 0x0438, 0xACDA, 0x0439, 0xACDB, + 0x043A, 0xACDC, 0x043B, 0xACDD, 0x043C, 0xACDE, 0x043D, 0xACDF, + 0x043E, 0xACE0, 0x043F, 0xACE1, 0x0440, 0xACE2, 0x0441, 0xACE3, + 0x0442, 0xACE4, 0x0443, 0xACE5, 0x0444, 0xACE6, 0x0445, 0xACE7, + 0x0446, 0xACE8, 0x0447, 0xACE9, 0x0448, 0xACEA, 0x0449, 0xACEB, + 0x044A, 0xACEC, 0x044B, 0xACED, 0x044C, 0xACEE, 0x044D, 0xACEF, + 0x044E, 0xACF0, 0x044F, 0xACF1, 0x0451, 0xACD7, 0x2015, 0xA1AA, + 0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1, + 0x2020, 0xA2D3, 0x2021, 0xA2D4, 0x2025, 0xA1A5, 0x2026, 0xA1A6, + 0x2030, 0xA2B6, 0x2032, 0xA1C7, 0x2033, 0xA1C8, 0x203B, 0xA1D8, + 0x2074, 0xA9F9, 0x207F, 0xA9FA, 0x2081, 0xA9FB, 0x2082, 0xA9FC, + 0x2083, 0xA9FD, 0x2084, 0xA9FE, 0x20AC, 0xA2E6, 0x2103, 0xA1C9, + 0x2109, 0xA2B5, 0x2113, 0xA7A4, 0x2116, 0xA2E0, 0x2121, 0xA2E5, + 0x2122, 0xA2E2, 0x2126, 0xA7D9, 0x212B, 0xA1CA, 0x2153, 0xA8F7, + 0x2154, 0xA8F8, 0x215B, 0xA8FB, 0x215C, 0xA8FC, 0x215D, 0xA8FD, + 0x215E, 0xA8FE, 0x2160, 0xA5B0, 0x2161, 0xA5B1, 0x2162, 0xA5B2, + 0x2163, 0xA5B3, 0x2164, 0xA5B4, 0x2165, 0xA5B5, 0x2166, 0xA5B6, + 0x2167, 0xA5B7, 0x2168, 0xA5B8, 0x2169, 0xA5B9, 0x2170, 0xA5A1, + 0x2171, 0xA5A2, 0x2172, 0xA5A3, 0x2173, 0xA5A4, 0x2174, 0xA5A5, + 0x2175, 0xA5A6, 0x2176, 0xA5A7, 0x2177, 0xA5A8, 0x2178, 0xA5A9, + 0x2179, 0xA5AA, 0x2190, 0xA1E7, 0x2191, 0xA1E8, 0x2192, 0xA1E6, + 0x2193, 0xA1E9, 0x2194, 0xA1EA, 0x2195, 0xA2D5, 0x2196, 0xA2D8, + 0x2197, 0xA2D6, 0x2198, 0xA2D9, 0x2199, 0xA2D7, 0x21D2, 0xA2A1, + 0x21D4, 0xA2A2, 0x2200, 0xA2A3, 0x2202, 0xA1D3, 0x2203, 0xA2A4, + 0x2207, 0xA1D4, 0x2208, 0xA1F4, 0x220B, 0xA1F5, 0x220F, 0xA2B3, + 0x2211, 0xA2B2, 0x221A, 0xA1EE, 0x221D, 0xA1F0, 0x221E, 0xA1C4, + 0x2220, 0xA1D0, 0x2225, 0xA1AB, 0x2227, 0xA1FC, 0x2228, 0xA1FD, + 0x2229, 0xA1FB, 0x222A, 0xA1FA, 0x222B, 0xA1F2, 0x222C, 0xA1F3, + 0x222E, 0xA2B1, 0x2234, 0xA1C5, 0x2235, 0xA1F1, 0x223C, 0xA1AD, + 0x223D, 0xA1EF, 0x2252, 0xA1D6, 0x2260, 0xA1C1, 0x2261, 0xA1D5, + 0x2264, 0xA1C2, 0x2265, 0xA1C3, 0x226A, 0xA1EC, 0x226B, 0xA1ED, + 0x2282, 0xA1F8, 0x2283, 0xA1F9, 0x2286, 0xA1F6, 0x2287, 0xA1F7, + 0x2299, 0xA2C1, 0x22A5, 0xA1D1, 0x2312, 0xA1D2, 0x2460, 0xA8E7, + 0x2461, 0xA8E8, 0x2462, 0xA8E9, 0x2463, 0xA8EA, 0x2464, 0xA8EB, + 0x2465, 0xA8EC, 0x2466, 0xA8ED, 0x2467, 0xA8EE, 0x2468, 0xA8EF, + 0x2469, 0xA8F0, 0x246A, 0xA8F1, 0x246B, 0xA8F2, 0x246C, 0xA8F3, + 0x246D, 0xA8F4, 0x246E, 0xA8F5, 0x2474, 0xA9E7, 0x2475, 0xA9E8, + 0x2476, 0xA9E9, 0x2477, 0xA9EA, 0x2478, 0xA9EB, 0x2479, 0xA9EC, + 0x247A, 0xA9ED, 0x247B, 0xA9EE, 0x247C, 0xA9EF, 0x247D, 0xA9F0, + 0x247E, 0xA9F1, 0x247F, 0xA9F2, 0x2480, 0xA9F3, 0x2481, 0xA9F4, + 0x2482, 0xA9F5, 0x249C, 0xA9CD, 0x249D, 0xA9CE, 0x249E, 0xA9CF, + 0x249F, 0xA9D0, 0x24A0, 0xA9D1, 0x24A1, 0xA9D2, 0x24A2, 0xA9D3, + 0x24A3, 0xA9D4, 0x24A4, 0xA9D5, 0x24A5, 0xA9D6, 0x24A6, 0xA9D7, + 0x24A7, 0xA9D8, 0x24A8, 0xA9D9, 0x24A9, 0xA9DA, 0x24AA, 0xA9DB, + 0x24AB, 0xA9DC, 0x24AC, 0xA9DD, 0x24AD, 0xA9DE, 0x24AE, 0xA9DF, + 0x24AF, 0xA9E0, 0x24B0, 0xA9E1, 0x24B1, 0xA9E2, 0x24B2, 0xA9E3, + 0x24B3, 0xA9E4, 0x24B4, 0xA9E5, 0x24B5, 0xA9E6, 0x24D0, 0xA8CD, + 0x24D1, 0xA8CE, 0x24D2, 0xA8CF, 0x24D3, 0xA8D0, 0x24D4, 0xA8D1, + 0x24D5, 0xA8D2, 0x24D6, 0xA8D3, 0x24D7, 0xA8D4, 0x24D8, 0xA8D5, + 0x24D9, 0xA8D6, 0x24DA, 0xA8D7, 0x24DB, 0xA8D8, 0x24DC, 0xA8D9, + 0x24DD, 0xA8DA, 0x24DE, 0xA8DB, 0x24DF, 0xA8DC, 0x24E0, 0xA8DD, + 0x24E1, 0xA8DE, 0x24E2, 0xA8DF, 0x24E3, 0xA8E0, 0x24E4, 0xA8E1, + 0x24E5, 0xA8E2, 0x24E6, 0xA8E3, 0x24E7, 0xA8E4, 0x24E8, 0xA8E5, + 0x24E9, 0xA8E6, 0x2500, 0xA6A1, 0x2501, 0xA6AC, 0x2502, 0xA6A2, + 0x2503, 0xA6AD, 0x250C, 0xA6A3, 0x250D, 0xA6C8, 0x250E, 0xA6C7, + 0x250F, 0xA6AE, 0x2510, 0xA6A4, 0x2511, 0xA6C2, 0x2512, 0xA6C1, + 0x2513, 0xA6AF, 0x2514, 0xA6A6, 0x2515, 0xA6C6, 0x2516, 0xA6C5, + 0x2517, 0xA6B1, 0x2518, 0xA6A5, 0x2519, 0xA6C4, 0x251A, 0xA6C3, + 0x251B, 0xA6B0, 0x251C, 0xA6A7, 0x251D, 0xA6BC, 0x251E, 0xA6C9, + 0x251F, 0xA6CA, 0x2520, 0xA6B7, 0x2521, 0xA6CB, 0x2522, 0xA6CC, + 0x2523, 0xA6B2, 0x2524, 0xA6A9, 0x2525, 0xA6BE, 0x2526, 0xA6CD, + 0x2527, 0xA6CE, 0x2528, 0xA6B9, 0x2529, 0xA6CF, 0x252A, 0xA6D0, + 0x252B, 0xA6B4, 0x252C, 0xA6A8, 0x252D, 0xA6D1, 0x252E, 0xA6D2, + 0x252F, 0xA6B8, 0x2530, 0xA6BD, 0x2531, 0xA6D3, 0x2532, 0xA6D4, + 0x2533, 0xA6B3, 0x2534, 0xA6AA, 0x2535, 0xA6D5, 0x2536, 0xA6D6, + 0x2537, 0xA6BA, 0x2538, 0xA6BF, 0x2539, 0xA6D7, 0x253A, 0xA6D8, + 0x253B, 0xA6B5, 0x253C, 0xA6AB, 0x253D, 0xA6D9, 0x253E, 0xA6DA, + 0x253F, 0xA6BB, 0x2540, 0xA6DB, 0x2541, 0xA6DC, 0x2542, 0xA6C0, + 0x2543, 0xA6DD, 0x2544, 0xA6DE, 0x2545, 0xA6DF, 0x2546, 0xA6E0, + 0x2547, 0xA6E1, 0x2548, 0xA6E2, 0x2549, 0xA6E3, 0x254A, 0xA6E4, + 0x254B, 0xA6B6, 0x2592, 0xA2C6, 0x25A0, 0xA1E1, 0x25A1, 0xA1E0, + 0x25A3, 0xA2C3, 0x25A4, 0xA2C7, 0x25A5, 0xA2C8, 0x25A6, 0xA2CB, + 0x25A7, 0xA2CA, 0x25A8, 0xA2C9, 0x25A9, 0xA2CC, 0x25B2, 0xA1E3, + 0x25B3, 0xA1E2, 0x25B6, 0xA2BA, 0x25B7, 0xA2B9, 0x25BC, 0xA1E5, + 0x25BD, 0xA1E4, 0x25C0, 0xA2B8, 0x25C1, 0xA2B7, 0x25C6, 0xA1DF, + 0x25C7, 0xA1DE, 0x25C8, 0xA2C2, 0x25CB, 0xA1DB, 0x25CE, 0xA1DD, + 0x25CF, 0xA1DC, 0x25D0, 0xA2C4, 0x25D1, 0xA2C5, 0x2605, 0xA1DA, + 0x2606, 0xA1D9, 0x260E, 0xA2CF, 0x260F, 0xA2CE, 0x261C, 0xA2D0, + 0x261E, 0xA2D1, 0x2640, 0xA1CF, 0x2642, 0xA1CE, 0x2660, 0xA2BC, + 0x2661, 0xA2BD, 0x2663, 0xA2C0, 0x2664, 0xA2BB, 0x2665, 0xA2BE, + 0x2667, 0xA2BF, 0x2668, 0xA2CD, 0x2669, 0xA2DB, 0x266A, 0xA2DC, + 0x266C, 0xA2DD, 0x266D, 0xA2DA, 0x3000, 0xA1A1, 0x3001, 0xA1A2, + 0x3002, 0xA1A3, 0x3003, 0xA1A8, 0x3008, 0xA1B4, 0x3009, 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0xC8DE, 0xD735, 0xC8DF, 0xD736, 0xC558, 0xD737, 0xC559, + 0xD738, 0xC8E0, 0xD739, 0xC55A, 0xD73A, 0xC561, 0xD73B, 0xC562, + 0xD73C, 0xC8E1, 0xD73D, 0xC563, 0xD73E, 0xC564, 0xD73F, 0xC565, + 0xD740, 0xC566, 0xD741, 0xC567, 0xD742, 0xC568, 0xD743, 0xC569, + 0xD744, 0xC8E2, 0xD745, 0xC56A, 0xD746, 0xC56B, 0xD747, 0xC8E3, + 0xD748, 0xC56C, 0xD749, 0xC8E4, 0xD74A, 0xC56D, 0xD74B, 0xC56E, + 0xD74C, 0xC56F, 0xD74D, 0xC570, 0xD74E, 0xC571, 0xD74F, 0xC572, + 0xD750, 0xC8E5, 0xD751, 0xC8E6, 0xD752, 0xC573, 0xD753, 0xC574, + 0xD754, 0xC8E7, 0xD755, 0xC575, 0xD756, 0xC8E8, 0xD757, 0xC8E9, + 0xD758, 0xC8EA, 0xD759, 0xC8EB, 0xD75A, 0xC576, 0xD75B, 0xC577, + 0xD75C, 0xC578, 0xD75D, 0xC579, 0xD75E, 0xC57A, 0xD75F, 0xC581, + 0xD760, 0xC8EC, 0xD761, 0xC8ED, 0xD762, 0xC582, 0xD763, 0xC8EE, + 0xD764, 0xC583, 0xD765, 0xC8EF, 0xD766, 0xC584, 0xD767, 0xC585, + 0xD768, 0xC586, 0xD769, 0xC8F0, 0xD76A, 0xC587, 0xD76B, 0xC588, + 0xD76C, 0xC8F1, 0xD76D, 0xC589, 0xD76E, 0xC58A, 0xD76F, 0xC58B, + 0xD770, 0xC8F2, 0xD771, 0xC58C, 0xD772, 0xC58D, 0xD773, 0xC58E, + 0xD774, 0xC8F3, 0xD775, 0xC58F, 0xD776, 0xC590, 0xD777, 0xC591, + 0xD778, 0xC592, 0xD779, 0xC593, 0xD77A, 0xC594, 0xD77B, 0xC595, + 0xD77C, 0xC8F4, 0xD77D, 0xC8F5, 0xD77E, 0xC596, 0xD77F, 0xC597, + 0xD780, 0xC598, 0xD781, 0xC8F6, 0xD782, 0xC599, 0xD783, 0xC59A, + 0xD784, 0xC59B, 0xD785, 0xC59C, 0xD786, 0xC59D, 0xD787, 0xC59E, + 0xD788, 0xC8F7, 0xD789, 0xC8F8, 0xD78A, 0xC59F, 0xD78B, 0xC5A0, + 0xD78C, 0xC8F9, 0xD78D, 0xC641, 0xD78E, 0xC642, 0xD78F, 0xC643, + 0xD790, 0xC8FA, 0xD791, 0xC644, 0xD792, 0xC645, 0xD793, 0xC646, + 0xD794, 0xC647, 0xD795, 0xC648, 0xD796, 0xC649, 0xD797, 0xC64A, + 0xD798, 0xC8FB, 0xD799, 0xC8FC, 0xD79A, 0xC64B, 0xD79B, 0xC8FD, + 0xD79C, 0xC64C, 0xD79D, 0xC8FE, 0xD79E, 0xC64D, 0xD79F, 0xC64E, + 0xD7A0, 0xC64F, 0xD7A1, 0xC650, 0xD7A2, 0xC651, 0xD7A3, 0xC652, + 0xF900, 0xCBD0, 0xF901, 0xCBD6, 0xF902, 0xCBE7, 0xF903, 0xCDCF, + 0xF904, 0xCDE8, 0xF905, 0xCEAD, 0xF906, 0xCFFB, 0xF907, 0xD0A2, + 0xF908, 0xD0B8, 0xF909, 0xD0D0, 0xF90A, 0xD0DD, 0xF90B, 0xD1D4, + 0xF90C, 0xD1D5, 0xF90D, 0xD1D8, 0xF90E, 0xD1DB, 0xF90F, 0xD1DC, + 0xF910, 0xD1DD, 0xF911, 0xD1DE, 0xF912, 0xD1DF, 0xF913, 0xD1E0, + 0xF914, 0xD1E2, 0xF915, 0xD1E3, 0xF916, 0xD1E4, 0xF917, 0xD1E5, + 0xF918, 0xD1E6, 0xF919, 0xD1E8, 0xF91A, 0xD1E9, 0xF91B, 0xD1EA, + 0xF91C, 0xD1EB, 0xF91D, 0xD1ED, 0xF91E, 0xD1EF, 0xF91F, 0xD1F0, + 0xF920, 0xD1F2, 0xF921, 0xD1F6, 0xF922, 0xD1FA, 0xF923, 0xD1FC, + 0xF924, 0xD1FD, 0xF925, 0xD1FE, 0xF926, 0xD2A2, 0xF927, 0xD2A3, + 0xF928, 0xD2A7, 0xF929, 0xD2A8, 0xF92A, 0xD2A9, 0xF92B, 0xD2AA, + 0xF92C, 0xD2AB, 0xF92D, 0xD2AD, 0xF92E, 0xD2B2, 0xF92F, 0xD2BE, + 0xF930, 0xD2C2, 0xF931, 0xD2C3, 0xF932, 0xD2C4, 0xF933, 0xD2C6, + 0xF934, 0xD2C7, 0xF935, 0xD2C8, 0xF936, 0xD2C9, 0xF937, 0xD2CA, + 0xF938, 0xD2CB, 0xF939, 0xD2CD, 0xF93A, 0xD2CE, 0xF93B, 0xD2CF, + 0xF93C, 0xD2D0, 0xF93D, 0xD2D1, 0xF93E, 0xD2D2, 0xF93F, 0xD2D3, + 0xF940, 0xD2D4, 0xF941, 0xD2D5, 0xF942, 0xD2D6, 0xF943, 0xD2D7, + 0xF944, 0xD2D9, 0xF945, 0xD2DA, 0xF946, 0xD2DE, 0xF947, 0xD2DF, + 0xF948, 0xD2E1, 0xF949, 0xD2E2, 0xF94A, 0xD2E4, 0xF94B, 0xD2E5, + 0xF94C, 0xD2E6, 0xF94D, 0xD2E7, 0xF94E, 0xD2E8, 0xF94F, 0xD2E9, + 0xF950, 0xD2EA, 0xF951, 0xD2EB, 0xF952, 0xD2F0, 0xF953, 0xD2F1, + 0xF954, 0xD2F2, 0xF955, 0xD2F3, 0xF956, 0xD2F4, 0xF957, 0xD2F5, + 0xF958, 0xD2F7, 0xF959, 0xD2F8, 0xF95A, 0xD4E6, 0xF95B, 0xD4FC, + 0xF95C, 0xD5A5, 0xF95D, 0xD5AB, 0xF95E, 0xD5AE, 0xF95F, 0xD6B8, + 0xF960, 0xD6CD, 0xF961, 0xD7CB, 0xF962, 0xD7E4, 0xF963, 0xDBC5, + 0xF964, 0xDBE4, 0xF965, 0xDCA5, 0xF966, 0xDDA5, 0xF967, 0xDDD5, + 0xF968, 0xDDF4, 0xF969, 0xDEFC, 0xF96A, 0xDEFE, 0xF96B, 0xDFB3, + 0xF96C, 0xDFE1, 0xF96D, 0xDFE8, 0xF96E, 0xE0F1, 0xF96F, 0xE1AD, + 0xF970, 0xE1ED, 0xF971, 0xE3F5, 0xF972, 0xE4A1, 0xF973, 0xE4A9, + 0xF974, 0xE5AE, 0xF975, 0xE5B1, 0xF976, 0xE5B2, 0xF977, 0xE5B9, + 0xF978, 0xE5BB, 0xF979, 0xE5BC, 0xF97A, 0xE5C4, 0xF97B, 0xE5CE, + 0xF97C, 0xE5D0, 0xF97D, 0xE5D2, 0xF97E, 0xE5D6, 0xF97F, 0xE5FA, + 0xF980, 0xE5FB, 0xF981, 0xE5FC, 0xF982, 0xE5FE, 0xF983, 0xE6A1, + 0xF984, 0xE6A4, 0xF985, 0xE6A7, 0xF986, 0xE6AD, 0xF987, 0xE6AF, + 0xF988, 0xE6B0, 0xF989, 0xE6B1, 0xF98A, 0xE6B3, 0xF98B, 0xE6B7, + 0xF98C, 0xE6B8, 0xF98D, 0xE6BC, 0xF98E, 0xE6C4, 0xF98F, 0xE6C6, + 0xF990, 0xE6C7, 0xF991, 0xE6CA, 0xF992, 0xE6D2, 0xF993, 0xE6D6, + 0xF994, 0xE6D9, 0xF995, 0xE6DC, 0xF996, 0xE6DF, 0xF997, 0xE6E1, + 0xF998, 0xE6E4, 0xF999, 0xE6E5, 0xF99A, 0xE6E6, 0xF99B, 0xE6E8, + 0xF99C, 0xE6EA, 0xF99D, 0xE6EB, 0xF99E, 0xE6EC, 0xF99F, 0xE6EF, + 0xF9A0, 0xE6F1, 0xF9A1, 0xE6F2, 0xF9A2, 0xE6F5, 0xF9A3, 0xE6F6, + 0xF9A4, 0xE6F7, 0xF9A5, 0xE6F9, 0xF9A6, 0xE7A1, 0xF9A7, 0xE7A6, + 0xF9A8, 0xE7A9, 0xF9A9, 0xE7AA, 0xF9AA, 0xE7AC, 0xF9AB, 0xE7AD, + 0xF9AC, 0xE7B0, 0xF9AD, 0xE7BF, 0xF9AE, 0xE7C1, 0xF9AF, 0xE7C6, + 0xF9B0, 0xE7C7, 0xF9B1, 0xE7CB, 0xF9B2, 0xE7CD, 0xF9B3, 0xE7CF, + 0xF9B4, 0xE7D0, 0xF9B5, 0xE7D3, 0xF9B6, 0xE7DF, 0xF9B7, 0xE7E4, + 0xF9B8, 0xE7E6, 0xF9B9, 0xE7F7, 0xF9BA, 0xE8E7, 0xF9BB, 0xE8E8, + 0xF9BC, 0xE8F0, 0xF9BD, 0xE8F1, 0xF9BE, 0xE8F7, 0xF9BF, 0xE8F9, + 0xF9C0, 0xE8FB, 0xF9C1, 0xE8FE, 0xF9C2, 0xE9A7, 0xF9C3, 0xE9AC, + 0xF9C4, 0xE9CC, 0xF9C5, 0xE9F7, 0xF9C6, 0xEAC1, 0xF9C7, 0xEAE5, + 0xF9C8, 0xEAF4, 0xF9C9, 0xEAF7, 0xF9CA, 0xEAFC, 0xF9CB, 0xEAFE, + 0xF9CC, 0xEBA4, 0xF9CD, 0xEBA7, 0xF9CE, 0xEBA9, 0xF9CF, 0xEBAA, + 0xF9D0, 0xEBBA, 0xF9D1, 0xEBBB, 0xF9D2, 0xEBBD, 0xF9D3, 0xEBC1, + 0xF9D4, 0xEBC2, 0xF9D5, 0xEBC6, 0xF9D6, 0xEBC7, 0xF9D7, 0xEBCC, + 0xF9D8, 0xEBCF, 0xF9D9, 0xEBD0, 0xF9DA, 0xEBD1, 0xF9DB, 0xEBD2, + 0xF9DC, 0xEBD8, 0xF9DD, 0xECA6, 0xF9DE, 0xECA7, 0xF9DF, 0xECAA, + 0xF9E0, 0xECAF, 0xF9E1, 0xECB0, 0xF9E2, 0xECB1, 0xF9E3, 0xECB2, + 0xF9E4, 0xECB5, 0xF9E5, 0xECB8, 0xF9E6, 0xECBA, 0xF9E7, 0xECC0, + 0xF9E8, 0xECC1, 0xF9E9, 0xECC5, 0xF9EA, 0xECC6, 0xF9EB, 0xECC9, + 0xF9EC, 0xECCA, 0xF9ED, 0xECD5, 0xF9EE, 0xECDD, 0xF9EF, 0xECDE, + 0xF9F0, 0xECE1, 0xF9F1, 0xECE4, 0xF9F2, 0xECE7, 0xF9F3, 0xECE8, + 0xF9F4, 0xECF7, 0xF9F5, 0xECF8, 0xF9F6, 0xECFA, 0xF9F7, 0xEDA1, + 0xF9F8, 0xEDA2, 0xF9F9, 0xEDA3, 0xF9FA, 0xEDEE, 0xF9FB, 0xEEDB, + 0xF9FC, 0xF2BD, 0xF9FD, 0xF2FA, 0xF9FE, 0xF3B1, 0xF9FF, 0xF4A7, + 0xFA00, 0xF4EE, 0xFA01, 0xF6F4, 0xFA02, 0xF6F6, 0xFA03, 0xF7B8, + 0xFA04, 0xF7C8, 0xFA05, 0xF7D3, 0xFA06, 0xF8DB, 0xFA07, 0xF8F0, + 0xFA08, 0xFAA1, 0xFA09, 0xFAA2, 0xFA0A, 0xFAE6, 0xFA0B, 0xFCA9, + 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA3A4, + 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, + 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, + 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, + 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, + 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, + 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, + 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, + 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, + 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, + 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, + 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, + 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, + 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, + 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA1AC, + 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, + 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, + 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, + 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, + 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, + 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, + 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, + 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, + 0xFF5D, 0xA3FD, 0xFF5E, 0xA2A6, 0xFFE0, 0xA1CB, 0xFFE1, 0xA1CC, + 0xFFE2, 0xA1FE, 0xFFE3, 0xA3FE, 0xFFE5, 0xA1CD, 0xFFE6, 0xA3DC, + 0, 0 +}; + +static +const WCHAR oem2uni[] = { +/* OEM - Unicode, OEM - Unicode, OEM - Unicode, OEM - Unicode */ + 0x8141, 0xAC02, 0x8142, 0xAC03, 0x8143, 0xAC05, 0x8144, 0xAC06, + 0x8145, 0xAC0B, 0x8146, 0xAC0C, 0x8147, 0xAC0D, 0x8148, 0xAC0E, + 0x8149, 0xAC0F, 0x814A, 0xAC18, 0x814B, 0xAC1E, 0x814C, 0xAC1F, + 0x814D, 0xAC21, 0x814E, 0xAC22, 0x814F, 0xAC23, 0x8150, 0xAC25, + 0x8151, 0xAC26, 0x8152, 0xAC27, 0x8153, 0xAC28, 0x8154, 0xAC29, + 0x8155, 0xAC2A, 0x8156, 0xAC2B, 0x8157, 0xAC2E, 0x8158, 0xAC32, + 0x8159, 0xAC33, 0x815A, 0xAC34, 0x8161, 0xAC35, 0x8162, 0xAC36, + 0x8163, 0xAC37, 0x8164, 0xAC3A, 0x8165, 0xAC3B, 0x8166, 0xAC3D, + 0x8167, 0xAC3E, 0x8168, 0xAC3F, 0x8169, 0xAC41, 0x816A, 0xAC42, + 0x816B, 0xAC43, 0x816C, 0xAC44, 0x816D, 0xAC45, 0x816E, 0xAC46, + 0x816F, 0xAC47, 0x8170, 0xAC48, 0x8171, 0xAC49, 0x8172, 0xAC4A, + 0x8173, 0xAC4C, 0x8174, 0xAC4E, 0x8175, 0xAC4F, 0x8176, 0xAC50, + 0x8177, 0xAC51, 0x8178, 0xAC52, 0x8179, 0xAC53, 0x817A, 0xAC55, + 0x8181, 0xAC56, 0x8182, 0xAC57, 0x8183, 0xAC59, 0x8184, 0xAC5A, + 0x8185, 0xAC5B, 0x8186, 0xAC5D, 0x8187, 0xAC5E, 0x8188, 0xAC5F, + 0x8189, 0xAC60, 0x818A, 0xAC61, 0x818B, 0xAC62, 0x818C, 0xAC63, + 0x818D, 0xAC64, 0x818E, 0xAC65, 0x818F, 0xAC66, 0x8190, 0xAC67, + 0x8191, 0xAC68, 0x8192, 0xAC69, 0x8193, 0xAC6A, 0x8194, 0xAC6B, + 0x8195, 0xAC6C, 0x8196, 0xAC6D, 0x8197, 0xAC6E, 0x8198, 0xAC6F, + 0x8199, 0xAC72, 0x819A, 0xAC73, 0x819B, 0xAC75, 0x819C, 0xAC76, + 0x819D, 0xAC79, 0x819E, 0xAC7B, 0x819F, 0xAC7C, 0x81A0, 0xAC7D, + 0x81A1, 0xAC7E, 0x81A2, 0xAC7F, 0x81A3, 0xAC82, 0x81A4, 0xAC87, + 0x81A5, 0xAC88, 0x81A6, 0xAC8D, 0x81A7, 0xAC8E, 0x81A8, 0xAC8F, + 0x81A9, 0xAC91, 0x81AA, 0xAC92, 0x81AB, 0xAC93, 0x81AC, 0xAC95, + 0x81AD, 0xAC96, 0x81AE, 0xAC97, 0x81AF, 0xAC98, 0x81B0, 0xAC99, + 0x81B1, 0xAC9A, 0x81B2, 0xAC9B, 0x81B3, 0xAC9E, 0x81B4, 0xACA2, + 0x81B5, 0xACA3, 0x81B6, 0xACA4, 0x81B7, 0xACA5, 0x81B8, 0xACA6, + 0x81B9, 0xACA7, 0x81BA, 0xACAB, 0x81BB, 0xACAD, 0x81BC, 0xACAE, + 0x81BD, 0xACB1, 0x81BE, 0xACB2, 0x81BF, 0xACB3, 0x81C0, 0xACB4, + 0x81C1, 0xACB5, 0x81C2, 0xACB6, 0x81C3, 0xACB7, 0x81C4, 0xACBA, + 0x81C5, 0xACBE, 0x81C6, 0xACBF, 0x81C7, 0xACC0, 0x81C8, 0xACC2, + 0x81C9, 0xACC3, 0x81CA, 0xACC5, 0x81CB, 0xACC6, 0x81CC, 0xACC7, + 0x81CD, 0xACC9, 0x81CE, 0xACCA, 0x81CF, 0xACCB, 0x81D0, 0xACCD, + 0x81D1, 0xACCE, 0x81D2, 0xACCF, 0x81D3, 0xACD0, 0x81D4, 0xACD1, + 0x81D5, 0xACD2, 0x81D6, 0xACD3, 0x81D7, 0xACD4, 0x81D8, 0xACD6, + 0x81D9, 0xACD8, 0x81DA, 0xACD9, 0x81DB, 0xACDA, 0x81DC, 0xACDB, + 0x81DD, 0xACDC, 0x81DE, 0xACDD, 0x81DF, 0xACDE, 0x81E0, 0xACDF, + 0x81E1, 0xACE2, 0x81E2, 0xACE3, 0x81E3, 0xACE5, 0x81E4, 0xACE6, + 0x81E5, 0xACE9, 0x81E6, 0xACEB, 0x81E7, 0xACED, 0x81E8, 0xACEE, + 0x81E9, 0xACF2, 0x81EA, 0xACF4, 0x81EB, 0xACF7, 0x81EC, 0xACF8, + 0x81ED, 0xACF9, 0x81EE, 0xACFA, 0x81EF, 0xACFB, 0x81F0, 0xACFE, + 0x81F1, 0xACFF, 0x81F2, 0xAD01, 0x81F3, 0xAD02, 0x81F4, 0xAD03, + 0x81F5, 0xAD05, 0x81F6, 0xAD07, 0x81F7, 0xAD08, 0x81F8, 0xAD09, + 0x81F9, 0xAD0A, 0x81FA, 0xAD0B, 0x81FB, 0xAD0E, 0x81FC, 0xAD10, + 0x81FD, 0xAD12, 0x81FE, 0xAD13, 0x8241, 0xAD14, 0x8242, 0xAD15, + 0x8243, 0xAD16, 0x8244, 0xAD17, 0x8245, 0xAD19, 0x8246, 0xAD1A, + 0x8247, 0xAD1B, 0x8248, 0xAD1D, 0x8249, 0xAD1E, 0x824A, 0xAD1F, + 0x824B, 0xAD21, 0x824C, 0xAD22, 0x824D, 0xAD23, 0x824E, 0xAD24, + 0x824F, 0xAD25, 0x8250, 0xAD26, 0x8251, 0xAD27, 0x8252, 0xAD28, + 0x8253, 0xAD2A, 0x8254, 0xAD2B, 0x8255, 0xAD2E, 0x8256, 0xAD2F, + 0x8257, 0xAD30, 0x8258, 0xAD31, 0x8259, 0xAD32, 0x825A, 0xAD33, + 0x8261, 0xAD36, 0x8262, 0xAD37, 0x8263, 0xAD39, 0x8264, 0xAD3A, + 0x8265, 0xAD3B, 0x8266, 0xAD3D, 0x8267, 0xAD3E, 0x8268, 0xAD3F, + 0x8269, 0xAD40, 0x826A, 0xAD41, 0x826B, 0xAD42, 0x826C, 0xAD43, + 0x826D, 0xAD46, 0x826E, 0xAD48, 0x826F, 0xAD4A, 0x8270, 0xAD4B, + 0x8271, 0xAD4C, 0x8272, 0xAD4D, 0x8273, 0xAD4E, 0x8274, 0xAD4F, + 0x8275, 0xAD51, 0x8276, 0xAD52, 0x8277, 0xAD53, 0x8278, 0xAD55, + 0x8279, 0xAD56, 0x827A, 0xAD57, 0x8281, 0xAD59, 0x8282, 0xAD5A, + 0x8283, 0xAD5B, 0x8284, 0xAD5C, 0x8285, 0xAD5D, 0x8286, 0xAD5E, + 0x8287, 0xAD5F, 0x8288, 0xAD60, 0x8289, 0xAD62, 0x828A, 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0xB38D, 0x8961, 0xB38E, 0x8962, 0xB38F, + 0x8963, 0xB391, 0x8964, 0xB392, 0x8965, 0xB393, 0x8966, 0xB395, + 0x8967, 0xB396, 0x8968, 0xB397, 0x8969, 0xB398, 0x896A, 0xB399, + 0x896B, 0xB39A, 0x896C, 0xB39B, 0x896D, 0xB39C, 0x896E, 0xB39D, + 0x896F, 0xB39E, 0x8970, 0xB39F, 0x8971, 0xB3A2, 0x8972, 0xB3A3, + 0x8973, 0xB3A4, 0x8974, 0xB3A5, 0x8975, 0xB3A6, 0x8976, 0xB3A7, + 0x8977, 0xB3A9, 0x8978, 0xB3AA, 0x8979, 0xB3AB, 0x897A, 0xB3AD, + 0x8981, 0xB3AE, 0x8982, 0xB3AF, 0x8983, 0xB3B0, 0x8984, 0xB3B1, + 0x8985, 0xB3B2, 0x8986, 0xB3B3, 0x8987, 0xB3B4, 0x8988, 0xB3B5, + 0x8989, 0xB3B6, 0x898A, 0xB3B7, 0x898B, 0xB3B8, 0x898C, 0xB3B9, + 0x898D, 0xB3BA, 0x898E, 0xB3BB, 0x898F, 0xB3BC, 0x8990, 0xB3BD, + 0x8991, 0xB3BE, 0x8992, 0xB3BF, 0x8993, 0xB3C0, 0x8994, 0xB3C1, + 0x8995, 0xB3C2, 0x8996, 0xB3C3, 0x8997, 0xB3C6, 0x8998, 0xB3C7, + 0x8999, 0xB3C9, 0x899A, 0xB3CA, 0x899B, 0xB3CD, 0x899C, 0xB3CF, + 0x899D, 0xB3D1, 0x899E, 0xB3D2, 0x899F, 0xB3D3, 0x89A0, 0xB3D6, + 0x89A1, 0xB3D8, 0x89A2, 0xB3DA, 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0xB421, 0x89E0, 0xB422, + 0x89E1, 0xB423, 0x89E2, 0xB424, 0x89E3, 0xB425, 0x89E4, 0xB426, + 0x89E5, 0xB427, 0x89E6, 0xB42A, 0x89E7, 0xB42C, 0x89E8, 0xB42D, + 0x89E9, 0xB42E, 0x89EA, 0xB42F, 0x89EB, 0xB430, 0x89EC, 0xB431, + 0x89ED, 0xB432, 0x89EE, 0xB433, 0x89EF, 0xB435, 0x89F0, 0xB436, + 0x89F1, 0xB437, 0x89F2, 0xB438, 0x89F3, 0xB439, 0x89F4, 0xB43A, + 0x89F5, 0xB43B, 0x89F6, 0xB43C, 0x89F7, 0xB43D, 0x89F8, 0xB43E, + 0x89F9, 0xB43F, 0x89FA, 0xB440, 0x89FB, 0xB441, 0x89FC, 0xB442, + 0x89FD, 0xB443, 0x89FE, 0xB444, 0x8A41, 0xB445, 0x8A42, 0xB446, + 0x8A43, 0xB447, 0x8A44, 0xB448, 0x8A45, 0xB449, 0x8A46, 0xB44A, + 0x8A47, 0xB44B, 0x8A48, 0xB44C, 0x8A49, 0xB44D, 0x8A4A, 0xB44E, + 0x8A4B, 0xB44F, 0x8A4C, 0xB452, 0x8A4D, 0xB453, 0x8A4E, 0xB455, + 0x8A4F, 0xB456, 0x8A50, 0xB457, 0x8A51, 0xB459, 0x8A52, 0xB45A, + 0x8A53, 0xB45B, 0x8A54, 0xB45C, 0x8A55, 0xB45D, 0x8A56, 0xB45E, + 0x8A57, 0xB45F, 0x8A58, 0xB462, 0x8A59, 0xB464, 0x8A5A, 0xB466, + 0x8A61, 0xB467, 0x8A62, 0xB468, 0x8A63, 0xB469, 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0xB4AD, + 0x8AA7, 0xB4AE, 0x8AA8, 0xB4AF, 0x8AA9, 0xB4B0, 0x8AAA, 0xB4B1, + 0x8AAB, 0xB4B2, 0x8AAC, 0xB4B3, 0x8AAD, 0xB4B4, 0x8AAE, 0xB4B6, + 0x8AAF, 0xB4B8, 0x8AB0, 0xB4BA, 0x8AB1, 0xB4BB, 0x8AB2, 0xB4BC, + 0x8AB3, 0xB4BD, 0x8AB4, 0xB4BE, 0x8AB5, 0xB4BF, 0x8AB6, 0xB4C1, + 0x8AB7, 0xB4C2, 0x8AB8, 0xB4C3, 0x8AB9, 0xB4C5, 0x8ABA, 0xB4C6, + 0x8ABB, 0xB4C7, 0x8ABC, 0xB4C9, 0x8ABD, 0xB4CA, 0x8ABE, 0xB4CB, + 0x8ABF, 0xB4CC, 0x8AC0, 0xB4CD, 0x8AC1, 0xB4CE, 0x8AC2, 0xB4CF, + 0x8AC3, 0xB4D1, 0x8AC4, 0xB4D2, 0x8AC5, 0xB4D3, 0x8AC6, 0xB4D4, + 0x8AC7, 0xB4D6, 0x8AC8, 0xB4D7, 0x8AC9, 0xB4D8, 0x8ACA, 0xB4D9, + 0x8ACB, 0xB4DA, 0x8ACC, 0xB4DB, 0x8ACD, 0xB4DE, 0x8ACE, 0xB4DF, + 0x8ACF, 0xB4E1, 0x8AD0, 0xB4E2, 0x8AD1, 0xB4E5, 0x8AD2, 0xB4E7, + 0x8AD3, 0xB4E8, 0x8AD4, 0xB4E9, 0x8AD5, 0xB4EA, 0x8AD6, 0xB4EB, + 0x8AD7, 0xB4EE, 0x8AD8, 0xB4F0, 0x8AD9, 0xB4F2, 0x8ADA, 0xB4F3, + 0x8ADB, 0xB4F4, 0x8ADC, 0xB4F5, 0x8ADD, 0xB4F6, 0x8ADE, 0xB4F7, + 0x8ADF, 0xB4F9, 0x8AE0, 0xB4FA, 0x8AE1, 0xB4FB, 0x8AE2, 0xB4FC, + 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0xB66A, 0x8CAE, 0xB66B, + 0x8CAF, 0xB66C, 0x8CB0, 0xB66D, 0x8CB1, 0xB66E, 0x8CB2, 0xB66F, + 0x8CB3, 0xB670, 0x8CB4, 0xB671, 0x8CB5, 0xB672, 0x8CB6, 0xB673, + 0x8CB7, 0xB674, 0x8CB8, 0xB675, 0x8CB9, 0xB676, 0x8CBA, 0xB677, + 0x8CBB, 0xB678, 0x8CBC, 0xB679, 0x8CBD, 0xB67A, 0x8CBE, 0xB67B, + 0x8CBF, 0xB67C, 0x8CC0, 0xB67D, 0x8CC1, 0xB67E, 0x8CC2, 0xB67F, + 0x8CC3, 0xB680, 0x8CC4, 0xB681, 0x8CC5, 0xB682, 0x8CC6, 0xB683, + 0x8CC7, 0xB684, 0x8CC8, 0xB685, 0x8CC9, 0xB686, 0x8CCA, 0xB687, + 0x8CCB, 0xB688, 0x8CCC, 0xB689, 0x8CCD, 0xB68A, 0x8CCE, 0xB68B, + 0x8CCF, 0xB68C, 0x8CD0, 0xB68D, 0x8CD1, 0xB68E, 0x8CD2, 0xB68F, + 0x8CD3, 0xB690, 0x8CD4, 0xB691, 0x8CD5, 0xB692, 0x8CD6, 0xB693, + 0x8CD7, 0xB694, 0x8CD8, 0xB695, 0x8CD9, 0xB696, 0x8CDA, 0xB697, + 0x8CDB, 0xB698, 0x8CDC, 0xB699, 0x8CDD, 0xB69A, 0x8CDE, 0xB69B, + 0x8CDF, 0xB69E, 0x8CE0, 0xB69F, 0x8CE1, 0xB6A1, 0x8CE2, 0xB6A2, + 0x8CE3, 0xB6A3, 0x8CE4, 0xB6A5, 0x8CE5, 0xB6A6, 0x8CE6, 0xB6A7, + 0x8CE7, 0xB6A8, 0x8CE8, 0xB6A9, 0x8CE9, 0xB6AA, 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0xB6EB, + 0x8D6F, 0xB6EC, 0x8D70, 0xB6ED, 0x8D71, 0xB6EE, 0x8D72, 0xB6EF, + 0x8D73, 0xB6F1, 0x8D74, 0xB6F2, 0x8D75, 0xB6F3, 0x8D76, 0xB6F5, + 0x8D77, 0xB6F6, 0x8D78, 0xB6F7, 0x8D79, 0xB6F9, 0x8D7A, 0xB6FA, + 0x8D81, 0xB6FB, 0x8D82, 0xB6FC, 0x8D83, 0xB6FD, 0x8D84, 0xB6FE, + 0x8D85, 0xB6FF, 0x8D86, 0xB702, 0x8D87, 0xB703, 0x8D88, 0xB704, + 0x8D89, 0xB706, 0x8D8A, 0xB707, 0x8D8B, 0xB708, 0x8D8C, 0xB709, + 0x8D8D, 0xB70A, 0x8D8E, 0xB70B, 0x8D8F, 0xB70C, 0x8D90, 0xB70D, + 0x8D91, 0xB70E, 0x8D92, 0xB70F, 0x8D93, 0xB710, 0x8D94, 0xB711, + 0x8D95, 0xB712, 0x8D96, 0xB713, 0x8D97, 0xB714, 0x8D98, 0xB715, + 0x8D99, 0xB716, 0x8D9A, 0xB717, 0x8D9B, 0xB718, 0x8D9C, 0xB719, + 0x8D9D, 0xB71A, 0x8D9E, 0xB71B, 0x8D9F, 0xB71C, 0x8DA0, 0xB71D, + 0x8DA1, 0xB71E, 0x8DA2, 0xB71F, 0x8DA3, 0xB720, 0x8DA4, 0xB721, + 0x8DA5, 0xB722, 0x8DA6, 0xB723, 0x8DA7, 0xB724, 0x8DA8, 0xB725, + 0x8DA9, 0xB726, 0x8DAA, 0xB727, 0x8DAB, 0xB72A, 0x8DAC, 0xB72B, + 0x8DAD, 0xB72D, 0x8DAE, 0xB72E, 0x8DAF, 0xB731, 0x8DB0, 0xB732, + 0x8DB1, 0xB733, 0x8DB2, 0xB734, 0x8DB3, 0xB735, 0x8DB4, 0xB736, + 0x8DB5, 0xB737, 0x8DB6, 0xB73A, 0x8DB7, 0xB73C, 0x8DB8, 0xB73D, + 0x8DB9, 0xB73E, 0x8DBA, 0xB73F, 0x8DBB, 0xB740, 0x8DBC, 0xB741, + 0x8DBD, 0xB742, 0x8DBE, 0xB743, 0x8DBF, 0xB745, 0x8DC0, 0xB746, + 0x8DC1, 0xB747, 0x8DC2, 0xB749, 0x8DC3, 0xB74A, 0x8DC4, 0xB74B, + 0x8DC5, 0xB74D, 0x8DC6, 0xB74E, 0x8DC7, 0xB74F, 0x8DC8, 0xB750, + 0x8DC9, 0xB751, 0x8DCA, 0xB752, 0x8DCB, 0xB753, 0x8DCC, 0xB756, + 0x8DCD, 0xB757, 0x8DCE, 0xB758, 0x8DCF, 0xB759, 0x8DD0, 0xB75A, + 0x8DD1, 0xB75B, 0x8DD2, 0xB75C, 0x8DD3, 0xB75D, 0x8DD4, 0xB75E, + 0x8DD5, 0xB75F, 0x8DD6, 0xB761, 0x8DD7, 0xB762, 0x8DD8, 0xB763, + 0x8DD9, 0xB765, 0x8DDA, 0xB766, 0x8DDB, 0xB767, 0x8DDC, 0xB769, + 0x8DDD, 0xB76A, 0x8DDE, 0xB76B, 0x8DDF, 0xB76C, 0x8DE0, 0xB76D, + 0x8DE1, 0xB76E, 0x8DE2, 0xB76F, 0x8DE3, 0xB772, 0x8DE4, 0xB774, + 0x8DE5, 0xB776, 0x8DE6, 0xB777, 0x8DE7, 0xB778, 0x8DE8, 0xB779, + 0x8DE9, 0xB77A, 0x8DEA, 0xB77B, 0x8DEB, 0xB77E, 0x8DEC, 0xB77F, + 0x8DED, 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0xB4BF, 0xB289, 0xB4C0, 0xB290, + 0xB4C1, 0xB291, 0xB4C2, 0xB294, 0xB4C3, 0xB298, 0xB4C4, 0xB299, + 0xB4C5, 0xB29A, 0xB4C6, 0xB2A0, 0xB4C7, 0xB2A1, 0xB4C8, 0xB2A3, + 0xB4C9, 0xB2A5, 0xB4CA, 0xB2A6, 0xB4CB, 0xB2AA, 0xB4CC, 0xB2AC, + 0xB4CD, 0xB2B0, 0xB4CE, 0xB2B4, 0xB4CF, 0xB2C8, 0xB4D0, 0xB2C9, + 0xB4D1, 0xB2CC, 0xB4D2, 0xB2D0, 0xB4D3, 0xB2D2, 0xB4D4, 0xB2D8, + 0xB4D5, 0xB2D9, 0xB4D6, 0xB2DB, 0xB4D7, 0xB2DD, 0xB4D8, 0xB2E2, + 0xB4D9, 0xB2E4, 0xB4DA, 0xB2E5, 0xB4DB, 0xB2E6, 0xB4DC, 0xB2E8, + 0xB4DD, 0xB2EB, 0xB4DE, 0xB2EC, 0xB4DF, 0xB2ED, 0xB4E0, 0xB2EE, + 0xB4E1, 0xB2EF, 0xB4E2, 0xB2F3, 0xB4E3, 0xB2F4, 0xB4E4, 0xB2F5, + 0xB4E5, 0xB2F7, 0xB4E6, 0xB2F8, 0xB4E7, 0xB2F9, 0xB4E8, 0xB2FA, + 0xB4E9, 0xB2FB, 0xB4EA, 0xB2FF, 0xB4EB, 0xB300, 0xB4EC, 0xB301, + 0xB4ED, 0xB304, 0xB4EE, 0xB308, 0xB4EF, 0xB310, 0xB4F0, 0xB311, + 0xB4F1, 0xB313, 0xB4F2, 0xB314, 0xB4F3, 0xB315, 0xB4F4, 0xB31C, + 0xB4F5, 0xB354, 0xB4F6, 0xB355, 0xB4F7, 0xB356, 0xB4F8, 0xB358, + 0xB4F9, 0xB35B, 0xB4FA, 0xB35C, 0xB4FB, 0xB35E, 0xB4FC, 0xB35F, + 0xB4FD, 0xB364, 0xB4FE, 0xB365, 0xB541, 0xD095, 0xB542, 0xD096, + 0xB543, 0xD097, 0xB544, 0xD098, 0xB545, 0xD099, 0xB546, 0xD09A, + 0xB547, 0xD09B, 0xB548, 0xD09C, 0xB549, 0xD09D, 0xB54A, 0xD09E, + 0xB54B, 0xD09F, 0xB54C, 0xD0A0, 0xB54D, 0xD0A1, 0xB54E, 0xD0A2, + 0xB54F, 0xD0A3, 0xB550, 0xD0A6, 0xB551, 0xD0A7, 0xB552, 0xD0A9, + 0xB553, 0xD0AA, 0xB554, 0xD0AB, 0xB555, 0xD0AD, 0xB556, 0xD0AE, + 0xB557, 0xD0AF, 0xB558, 0xD0B0, 0xB559, 0xD0B1, 0xB55A, 0xD0B2, + 0xB561, 0xD0B3, 0xB562, 0xD0B6, 0xB563, 0xD0B8, 0xB564, 0xD0BA, + 0xB565, 0xD0BB, 0xB566, 0xD0BC, 0xB567, 0xD0BD, 0xB568, 0xD0BE, + 0xB569, 0xD0BF, 0xB56A, 0xD0C2, 0xB56B, 0xD0C3, 0xB56C, 0xD0C5, + 0xB56D, 0xD0C6, 0xB56E, 0xD0C7, 0xB56F, 0xD0CA, 0xB570, 0xD0CB, + 0xB571, 0xD0CC, 0xB572, 0xD0CD, 0xB573, 0xD0CE, 0xB574, 0xD0CF, + 0xB575, 0xD0D2, 0xB576, 0xD0D6, 0xB577, 0xD0D7, 0xB578, 0xD0D8, + 0xB579, 0xD0D9, 0xB57A, 0xD0DA, 0xB581, 0xD0DB, 0xB582, 0xD0DE, + 0xB583, 0xD0DF, 0xB584, 0xD0E1, 0xB585, 0xD0E2, 0xB586, 0xD0E3, + 0xB587, 0xD0E5, 0xB588, 0xD0E6, 0xB589, 0xD0E7, 0xB58A, 0xD0E8, + 0xB58B, 0xD0E9, 0xB58C, 0xD0EA, 0xB58D, 0xD0EB, 0xB58E, 0xD0EE, + 0xB58F, 0xD0F2, 0xB590, 0xD0F3, 0xB591, 0xD0F4, 0xB592, 0xD0F5, + 0xB593, 0xD0F6, 0xB594, 0xD0F7, 0xB595, 0xD0F9, 0xB596, 0xD0FA, + 0xB597, 0xD0FB, 0xB598, 0xD0FC, 0xB599, 0xD0FD, 0xB59A, 0xD0FE, + 0xB59B, 0xD0FF, 0xB59C, 0xD100, 0xB59D, 0xD101, 0xB59E, 0xD102, + 0xB59F, 0xD103, 0xB5A0, 0xD104, 0xB5A1, 0xB367, 0xB5A2, 0xB369, + 0xB5A3, 0xB36B, 0xB5A4, 0xB36E, 0xB5A5, 0xB370, 0xB5A6, 0xB371, + 0xB5A7, 0xB374, 0xB5A8, 0xB378, 0xB5A9, 0xB380, 0xB5AA, 0xB381, + 0xB5AB, 0xB383, 0xB5AC, 0xB384, 0xB5AD, 0xB385, 0xB5AE, 0xB38C, + 0xB5AF, 0xB390, 0xB5B0, 0xB394, 0xB5B1, 0xB3A0, 0xB5B2, 0xB3A1, + 0xB5B3, 0xB3A8, 0xB5B4, 0xB3AC, 0xB5B5, 0xB3C4, 0xB5B6, 0xB3C5, + 0xB5B7, 0xB3C8, 0xB5B8, 0xB3CB, 0xB5B9, 0xB3CC, 0xB5BA, 0xB3CE, + 0xB5BB, 0xB3D0, 0xB5BC, 0xB3D4, 0xB5BD, 0xB3D5, 0xB5BE, 0xB3D7, + 0xB5BF, 0xB3D9, 0xB5C0, 0xB3DB, 0xB5C1, 0xB3DD, 0xB5C2, 0xB3E0, + 0xB5C3, 0xB3E4, 0xB5C4, 0xB3E8, 0xB5C5, 0xB3FC, 0xB5C6, 0xB410, + 0xB5C7, 0xB418, 0xB5C8, 0xB41C, 0xB5C9, 0xB420, 0xB5CA, 0xB428, + 0xB5CB, 0xB429, 0xB5CC, 0xB42B, 0xB5CD, 0xB434, 0xB5CE, 0xB450, + 0xB5CF, 0xB451, 0xB5D0, 0xB454, 0xB5D1, 0xB458, 0xB5D2, 0xB460, + 0xB5D3, 0xB461, 0xB5D4, 0xB463, 0xB5D5, 0xB465, 0xB5D6, 0xB46C, + 0xB5D7, 0xB480, 0xB5D8, 0xB488, 0xB5D9, 0xB49D, 0xB5DA, 0xB4A4, + 0xB5DB, 0xB4A8, 0xB5DC, 0xB4AC, 0xB5DD, 0xB4B5, 0xB5DE, 0xB4B7, + 0xB5DF, 0xB4B9, 0xB5E0, 0xB4C0, 0xB5E1, 0xB4C4, 0xB5E2, 0xB4C8, + 0xB5E3, 0xB4D0, 0xB5E4, 0xB4D5, 0xB5E5, 0xB4DC, 0xB5E6, 0xB4DD, + 0xB5E7, 0xB4E0, 0xB5E8, 0xB4E3, 0xB5E9, 0xB4E4, 0xB5EA, 0xB4E6, + 0xB5EB, 0xB4EC, 0xB5EC, 0xB4ED, 0xB5ED, 0xB4EF, 0xB5EE, 0xB4F1, + 0xB5EF, 0xB4F8, 0xB5F0, 0xB514, 0xB5F1, 0xB515, 0xB5F2, 0xB518, + 0xB5F3, 0xB51B, 0xB5F4, 0xB51C, 0xB5F5, 0xB524, 0xB5F6, 0xB525, + 0xB5F7, 0xB527, 0xB5F8, 0xB528, 0xB5F9, 0xB529, 0xB5FA, 0xB52A, + 0xB5FB, 0xB530, 0xB5FC, 0xB531, 0xB5FD, 0xB534, 0xB5FE, 0xB538, + 0xB641, 0xD105, 0xB642, 0xD106, 0xB643, 0xD107, 0xB644, 0xD108, + 0xB645, 0xD109, 0xB646, 0xD10A, 0xB647, 0xD10B, 0xB648, 0xD10C, + 0xB649, 0xD10E, 0xB64A, 0xD10F, 0xB64B, 0xD110, 0xB64C, 0xD111, + 0xB64D, 0xD112, 0xB64E, 0xD113, 0xB64F, 0xD114, 0xB650, 0xD115, + 0xB651, 0xD116, 0xB652, 0xD117, 0xB653, 0xD118, 0xB654, 0xD119, + 0xB655, 0xD11A, 0xB656, 0xD11B, 0xB657, 0xD11C, 0xB658, 0xD11D, + 0xB659, 0xD11E, 0xB65A, 0xD11F, 0xB661, 0xD120, 0xB662, 0xD121, + 0xB663, 0xD122, 0xB664, 0xD123, 0xB665, 0xD124, 0xB666, 0xD125, + 0xB667, 0xD126, 0xB668, 0xD127, 0xB669, 0xD128, 0xB66A, 0xD129, + 0xB66B, 0xD12A, 0xB66C, 0xD12B, 0xB66D, 0xD12C, 0xB66E, 0xD12D, + 0xB66F, 0xD12E, 0xB670, 0xD12F, 0xB671, 0xD132, 0xB672, 0xD133, + 0xB673, 0xD135, 0xB674, 0xD136, 0xB675, 0xD137, 0xB676, 0xD139, + 0xB677, 0xD13B, 0xB678, 0xD13C, 0xB679, 0xD13D, 0xB67A, 0xD13E, + 0xB681, 0xD13F, 0xB682, 0xD142, 0xB683, 0xD146, 0xB684, 0xD147, + 0xB685, 0xD148, 0xB686, 0xD149, 0xB687, 0xD14A, 0xB688, 0xD14B, + 0xB689, 0xD14E, 0xB68A, 0xD14F, 0xB68B, 0xD151, 0xB68C, 0xD152, + 0xB68D, 0xD153, 0xB68E, 0xD155, 0xB68F, 0xD156, 0xB690, 0xD157, + 0xB691, 0xD158, 0xB692, 0xD159, 0xB693, 0xD15A, 0xB694, 0xD15B, + 0xB695, 0xD15E, 0xB696, 0xD160, 0xB697, 0xD162, 0xB698, 0xD163, + 0xB699, 0xD164, 0xB69A, 0xD165, 0xB69B, 0xD166, 0xB69C, 0xD167, + 0xB69D, 0xD169, 0xB69E, 0xD16A, 0xB69F, 0xD16B, 0xB6A0, 0xD16D, + 0xB6A1, 0xB540, 0xB6A2, 0xB541, 0xB6A3, 0xB543, 0xB6A4, 0xB544, + 0xB6A5, 0xB545, 0xB6A6, 0xB54B, 0xB6A7, 0xB54C, 0xB6A8, 0xB54D, + 0xB6A9, 0xB550, 0xB6AA, 0xB554, 0xB6AB, 0xB55C, 0xB6AC, 0xB55D, + 0xB6AD, 0xB55F, 0xB6AE, 0xB560, 0xB6AF, 0xB561, 0xB6B0, 0xB5A0, + 0xB6B1, 0xB5A1, 0xB6B2, 0xB5A4, 0xB6B3, 0xB5A8, 0xB6B4, 0xB5AA, + 0xB6B5, 0xB5AB, 0xB6B6, 0xB5B0, 0xB6B7, 0xB5B1, 0xB6B8, 0xB5B3, + 0xB6B9, 0xB5B4, 0xB6BA, 0xB5B5, 0xB6BB, 0xB5BB, 0xB6BC, 0xB5BC, + 0xB6BD, 0xB5BD, 0xB6BE, 0xB5C0, 0xB6BF, 0xB5C4, 0xB6C0, 0xB5CC, + 0xB6C1, 0xB5CD, 0xB6C2, 0xB5CF, 0xB6C3, 0xB5D0, 0xB6C4, 0xB5D1, + 0xB6C5, 0xB5D8, 0xB6C6, 0xB5EC, 0xB6C7, 0xB610, 0xB6C8, 0xB611, + 0xB6C9, 0xB614, 0xB6CA, 0xB618, 0xB6CB, 0xB625, 0xB6CC, 0xB62C, + 0xB6CD, 0xB634, 0xB6CE, 0xB648, 0xB6CF, 0xB664, 0xB6D0, 0xB668, + 0xB6D1, 0xB69C, 0xB6D2, 0xB69D, 0xB6D3, 0xB6A0, 0xB6D4, 0xB6A4, + 0xB6D5, 0xB6AB, 0xB6D6, 0xB6AC, 0xB6D7, 0xB6B1, 0xB6D8, 0xB6D4, + 0xB6D9, 0xB6F0, 0xB6DA, 0xB6F4, 0xB6DB, 0xB6F8, 0xB6DC, 0xB700, + 0xB6DD, 0xB701, 0xB6DE, 0xB705, 0xB6DF, 0xB728, 0xB6E0, 0xB729, + 0xB6E1, 0xB72C, 0xB6E2, 0xB72F, 0xB6E3, 0xB730, 0xB6E4, 0xB738, + 0xB6E5, 0xB739, 0xB6E6, 0xB73B, 0xB6E7, 0xB744, 0xB6E8, 0xB748, + 0xB6E9, 0xB74C, 0xB6EA, 0xB754, 0xB6EB, 0xB755, 0xB6EC, 0xB760, + 0xB6ED, 0xB764, 0xB6EE, 0xB768, 0xB6EF, 0xB770, 0xB6F0, 0xB771, + 0xB6F1, 0xB773, 0xB6F2, 0xB775, 0xB6F3, 0xB77C, 0xB6F4, 0xB77D, + 0xB6F5, 0xB780, 0xB6F6, 0xB784, 0xB6F7, 0xB78C, 0xB6F8, 0xB78D, + 0xB6F9, 0xB78F, 0xB6FA, 0xB790, 0xB6FB, 0xB791, 0xB6FC, 0xB792, + 0xB6FD, 0xB796, 0xB6FE, 0xB797, 0xB741, 0xD16E, 0xB742, 0xD16F, + 0xB743, 0xD170, 0xB744, 0xD171, 0xB745, 0xD172, 0xB746, 0xD173, + 0xB747, 0xD174, 0xB748, 0xD175, 0xB749, 0xD176, 0xB74A, 0xD177, + 0xB74B, 0xD178, 0xB74C, 0xD179, 0xB74D, 0xD17A, 0xB74E, 0xD17B, + 0xB74F, 0xD17D, 0xB750, 0xD17E, 0xB751, 0xD17F, 0xB752, 0xD180, + 0xB753, 0xD181, 0xB754, 0xD182, 0xB755, 0xD183, 0xB756, 0xD185, + 0xB757, 0xD186, 0xB758, 0xD187, 0xB759, 0xD189, 0xB75A, 0xD18A, + 0xB761, 0xD18B, 0xB762, 0xD18C, 0xB763, 0xD18D, 0xB764, 0xD18E, + 0xB765, 0xD18F, 0xB766, 0xD190, 0xB767, 0xD191, 0xB768, 0xD192, + 0xB769, 0xD193, 0xB76A, 0xD194, 0xB76B, 0xD195, 0xB76C, 0xD196, + 0xB76D, 0xD197, 0xB76E, 0xD198, 0xB76F, 0xD199, 0xB770, 0xD19A, + 0xB771, 0xD19B, 0xB772, 0xD19C, 0xB773, 0xD19D, 0xB774, 0xD19E, + 0xB775, 0xD19F, 0xB776, 0xD1A2, 0xB777, 0xD1A3, 0xB778, 0xD1A5, + 0xB779, 0xD1A6, 0xB77A, 0xD1A7, 0xB781, 0xD1A9, 0xB782, 0xD1AA, + 0xB783, 0xD1AB, 0xB784, 0xD1AC, 0xB785, 0xD1AD, 0xB786, 0xD1AE, + 0xB787, 0xD1AF, 0xB788, 0xD1B2, 0xB789, 0xD1B4, 0xB78A, 0xD1B6, + 0xB78B, 0xD1B7, 0xB78C, 0xD1B8, 0xB78D, 0xD1B9, 0xB78E, 0xD1BB, + 0xB78F, 0xD1BD, 0xB790, 0xD1BE, 0xB791, 0xD1BF, 0xB792, 0xD1C1, + 0xB793, 0xD1C2, 0xB794, 0xD1C3, 0xB795, 0xD1C4, 0xB796, 0xD1C5, + 0xB797, 0xD1C6, 0xB798, 0xD1C7, 0xB799, 0xD1C8, 0xB79A, 0xD1C9, + 0xB79B, 0xD1CA, 0xB79C, 0xD1CB, 0xB79D, 0xD1CC, 0xB79E, 0xD1CD, + 0xB79F, 0xD1CE, 0xB7A0, 0xD1CF, 0xB7A1, 0xB798, 0xB7A2, 0xB799, + 0xB7A3, 0xB79C, 0xB7A4, 0xB7A0, 0xB7A5, 0xB7A8, 0xB7A6, 0xB7A9, + 0xB7A7, 0xB7AB, 0xB7A8, 0xB7AC, 0xB7A9, 0xB7AD, 0xB7AA, 0xB7B4, + 0xB7AB, 0xB7B5, 0xB7AC, 0xB7B8, 0xB7AD, 0xB7C7, 0xB7AE, 0xB7C9, + 0xB7AF, 0xB7EC, 0xB7B0, 0xB7ED, 0xB7B1, 0xB7F0, 0xB7B2, 0xB7F4, + 0xB7B3, 0xB7FC, 0xB7B4, 0xB7FD, 0xB7B5, 0xB7FF, 0xB7B6, 0xB800, + 0xB7B7, 0xB801, 0xB7B8, 0xB807, 0xB7B9, 0xB808, 0xB7BA, 0xB809, + 0xB7BB, 0xB80C, 0xB7BC, 0xB810, 0xB7BD, 0xB818, 0xB7BE, 0xB819, + 0xB7BF, 0xB81B, 0xB7C0, 0xB81D, 0xB7C1, 0xB824, 0xB7C2, 0xB825, + 0xB7C3, 0xB828, 0xB7C4, 0xB82C, 0xB7C5, 0xB834, 0xB7C6, 0xB835, + 0xB7C7, 0xB837, 0xB7C8, 0xB838, 0xB7C9, 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0x7DC7, 0xF6C6, 0x7DFB, 0xF6C7, 0x7F6E, 0xF6C8, 0x81F4, + 0xF6C9, 0x86A9, 0xF6CA, 0x8F1C, 0xF6CB, 0x96C9, 0xF6CC, 0x99B3, + 0xF6CD, 0x9F52, 0xF6CE, 0x5247, 0xF6CF, 0x52C5, 0xF6D0, 0x98ED, + 0xF6D1, 0x89AA, 0xF6D2, 0x4E03, 0xF6D3, 0x67D2, 0xF6D4, 0x6F06, + 0xF6D5, 0x4FB5, 0xF6D6, 0x5BE2, 0xF6D7, 0x6795, 0xF6D8, 0x6C88, + 0xF6D9, 0x6D78, 0xF6DA, 0x741B, 0xF6DB, 0x7827, 0xF6DC, 0x91DD, + 0xF6DD, 0x937C, 0xF6DE, 0x87C4, 0xF6DF, 0x79E4, 0xF6E0, 0x7A31, + 0xF6E1, 0x5FEB, 0xF6E2, 0x4ED6, 0xF6E3, 0x54A4, 0xF6E4, 0x553E, + 0xF6E5, 0x58AE, 0xF6E6, 0x59A5, 0xF6E7, 0x60F0, 0xF6E8, 0x6253, + 0xF6E9, 0x62D6, 0xF6EA, 0x6736, 0xF6EB, 0x6955, 0xF6EC, 0x8235, + 0xF6ED, 0x9640, 0xF6EE, 0x99B1, 0xF6EF, 0x99DD, 0xF6F0, 0x502C, + 0xF6F1, 0x5353, 0xF6F2, 0x5544, 0xF6F3, 0x577C, 0xF6F4, 0xFA01, + 0xF6F5, 0x6258, 0xF6F6, 0xFA02, 0xF6F7, 0x64E2, 0xF6F8, 0x666B, + 0xF6F9, 0x67DD, 0xF6FA, 0x6FC1, 0xF6FB, 0x6FEF, 0xF6FC, 0x7422, + 0xF6FD, 0x7438, 0xF6FE, 0x8A17, 0xF7A1, 0x9438, 0xF7A2, 0x5451, + 0xF7A3, 0x5606, 0xF7A4, 0x5766, 0xF7A5, 0x5F48, 0xF7A6, 0x619A, + 0xF7A7, 0x6B4E, 0xF7A8, 0x7058, 0xF7A9, 0x70AD, 0xF7AA, 0x7DBB, + 0xF7AB, 0x8A95, 0xF7AC, 0x596A, 0xF7AD, 0x812B, 0xF7AE, 0x63A2, + 0xF7AF, 0x7708, 0xF7B0, 0x803D, 0xF7B1, 0x8CAA, 0xF7B2, 0x5854, + 0xF7B3, 0x642D, 0xF7B4, 0x69BB, 0xF7B5, 0x5B95, 0xF7B6, 0x5E11, + 0xF7B7, 0x6E6F, 0xF7B8, 0xFA03, 0xF7B9, 0x8569, 0xF7BA, 0x514C, + 0xF7BB, 0x53F0, 0xF7BC, 0x592A, 0xF7BD, 0x6020, 0xF7BE, 0x614B, + 0xF7BF, 0x6B86, 0xF7C0, 0x6C70, 0xF7C1, 0x6CF0, 0xF7C2, 0x7B1E, + 0xF7C3, 0x80CE, 0xF7C4, 0x82D4, 0xF7C5, 0x8DC6, 0xF7C6, 0x90B0, + 0xF7C7, 0x98B1, 0xF7C8, 0xFA04, 0xF7C9, 0x64C7, 0xF7CA, 0x6FA4, + 0xF7CB, 0x6491, 0xF7CC, 0x6504, 0xF7CD, 0x514E, 0xF7CE, 0x5410, + 0xF7CF, 0x571F, 0xF7D0, 0x8A0E, 0xF7D1, 0x615F, 0xF7D2, 0x6876, + 0xF7D3, 0xFA05, 0xF7D4, 0x75DB, 0xF7D5, 0x7B52, 0xF7D6, 0x7D71, + 0xF7D7, 0x901A, 0xF7D8, 0x5806, 0xF7D9, 0x69CC, 0xF7DA, 0x817F, + 0xF7DB, 0x892A, 0xF7DC, 0x9000, 0xF7DD, 0x9839, 0xF7DE, 0x5078, + 0xF7DF, 0x5957, 0xF7E0, 0x59AC, 0xF7E1, 0x6295, 0xF7E2, 0x900F, + 0xF7E3, 0x9B2A, 0xF7E4, 0x615D, 0xF7E5, 0x7279, 0xF7E6, 0x95D6, + 0xF7E7, 0x5761, 0xF7E8, 0x5A46, 0xF7E9, 0x5DF4, 0xF7EA, 0x628A, + 0xF7EB, 0x64AD, 0xF7EC, 0x64FA, 0xF7ED, 0x6777, 0xF7EE, 0x6CE2, + 0xF7EF, 0x6D3E, 0xF7F0, 0x722C, 0xF7F1, 0x7436, 0xF7F2, 0x7834, + 0xF7F3, 0x7F77, 0xF7F4, 0x82AD, 0xF7F5, 0x8DDB, 0xF7F6, 0x9817, + 0xF7F7, 0x5224, 0xF7F8, 0x5742, 0xF7F9, 0x677F, 0xF7FA, 0x7248, + 0xF7FB, 0x74E3, 0xF7FC, 0x8CA9, 0xF7FD, 0x8FA6, 0xF7FE, 0x9211, + 0xF8A1, 0x962A, 0xF8A2, 0x516B, 0xF8A3, 0x53ED, 0xF8A4, 0x634C, + 0xF8A5, 0x4F69, 0xF8A6, 0x5504, 0xF8A7, 0x6096, 0xF8A8, 0x6557, + 0xF8A9, 0x6C9B, 0xF8AA, 0x6D7F, 0xF8AB, 0x724C, 0xF8AC, 0x72FD, + 0xF8AD, 0x7A17, 0xF8AE, 0x8987, 0xF8AF, 0x8C9D, 0xF8B0, 0x5F6D, + 0xF8B1, 0x6F8E, 0xF8B2, 0x70F9, 0xF8B3, 0x81A8, 0xF8B4, 0x610E, + 0xF8B5, 0x4FBF, 0xF8B6, 0x504F, 0xF8B7, 0x6241, 0xF8B8, 0x7247, + 0xF8B9, 0x7BC7, 0xF8BA, 0x7DE8, 0xF8BB, 0x7FE9, 0xF8BC, 0x904D, + 0xF8BD, 0x97AD, 0xF8BE, 0x9A19, 0xF8BF, 0x8CB6, 0xF8C0, 0x576A, + 0xF8C1, 0x5E73, 0xF8C2, 0x67B0, 0xF8C3, 0x840D, 0xF8C4, 0x8A55, + 0xF8C5, 0x5420, 0xF8C6, 0x5B16, 0xF8C7, 0x5E63, 0xF8C8, 0x5EE2, + 0xF8C9, 0x5F0A, 0xF8CA, 0x6583, 0xF8CB, 0x80BA, 0xF8CC, 0x853D, + 0xF8CD, 0x9589, 0xF8CE, 0x965B, 0xF8CF, 0x4F48, 0xF8D0, 0x5305, + 0xF8D1, 0x530D, 0xF8D2, 0x530F, 0xF8D3, 0x5486, 0xF8D4, 0x54FA, + 0xF8D5, 0x5703, 0xF8D6, 0x5E03, 0xF8D7, 0x6016, 0xF8D8, 0x629B, + 0xF8D9, 0x62B1, 0xF8DA, 0x6355, 0xF8DB, 0xFA06, 0xF8DC, 0x6CE1, + 0xF8DD, 0x6D66, 0xF8DE, 0x75B1, 0xF8DF, 0x7832, 0xF8E0, 0x80DE, + 0xF8E1, 0x812F, 0xF8E2, 0x82DE, 0xF8E3, 0x8461, 0xF8E4, 0x84B2, + 0xF8E5, 0x888D, 0xF8E6, 0x8912, 0xF8E7, 0x900B, 0xF8E8, 0x92EA, + 0xF8E9, 0x98FD, 0xF8EA, 0x9B91, 0xF8EB, 0x5E45, 0xF8EC, 0x66B4, + 0xF8ED, 0x66DD, 0xF8EE, 0x7011, 0xF8EF, 0x7206, 0xF8F0, 0xFA07, + 0xF8F1, 0x4FF5, 0xF8F2, 0x527D, 0xF8F3, 0x5F6A, 0xF8F4, 0x6153, + 0xF8F5, 0x6753, 0xF8F6, 0x6A19, 0xF8F7, 0x6F02, 0xF8F8, 0x74E2, + 0xF8F9, 0x7968, 0xF8FA, 0x8868, 0xF8FB, 0x8C79, 0xF8FC, 0x98C7, + 0xF8FD, 0x98C4, 0xF8FE, 0x9A43, 0xF9A1, 0x54C1, 0xF9A2, 0x7A1F, + 0xF9A3, 0x6953, 0xF9A4, 0x8AF7, 0xF9A5, 0x8C4A, 0xF9A6, 0x98A8, + 0xF9A7, 0x99AE, 0xF9A8, 0x5F7C, 0xF9A9, 0x62AB, 0xF9AA, 0x75B2, + 0xF9AB, 0x76AE, 0xF9AC, 0x88AB, 0xF9AD, 0x907F, 0xF9AE, 0x9642, + 0xF9AF, 0x5339, 0xF9B0, 0x5F3C, 0xF9B1, 0x5FC5, 0xF9B2, 0x6CCC, + 0xF9B3, 0x73CC, 0xF9B4, 0x7562, 0xF9B5, 0x758B, 0xF9B6, 0x7B46, + 0xF9B7, 0x82FE, 0xF9B8, 0x999D, 0xF9B9, 0x4E4F, 0xF9BA, 0x903C, + 0xF9BB, 0x4E0B, 0xF9BC, 0x4F55, 0xF9BD, 0x53A6, 0xF9BE, 0x590F, + 0xF9BF, 0x5EC8, 0xF9C0, 0x6630, 0xF9C1, 0x6CB3, 0xF9C2, 0x7455, + 0xF9C3, 0x8377, 0xF9C4, 0x8766, 0xF9C5, 0x8CC0, 0xF9C6, 0x9050, + 0xF9C7, 0x971E, 0xF9C8, 0x9C15, 0xF9C9, 0x58D1, 0xF9CA, 0x5B78, + 0xF9CB, 0x8650, 0xF9CC, 0x8B14, 0xF9CD, 0x9DB4, 0xF9CE, 0x5BD2, + 0xF9CF, 0x6068, 0xF9D0, 0x608D, 0xF9D1, 0x65F1, 0xF9D2, 0x6C57, + 0xF9D3, 0x6F22, 0xF9D4, 0x6FA3, 0xF9D5, 0x701A, 0xF9D6, 0x7F55, + 0xF9D7, 0x7FF0, 0xF9D8, 0x9591, 0xF9D9, 0x9592, 0xF9DA, 0x9650, + 0xF9DB, 0x97D3, 0xF9DC, 0x5272, 0xF9DD, 0x8F44, 0xF9DE, 0x51FD, + 0xF9DF, 0x542B, 0xF9E0, 0x54B8, 0xF9E1, 0x5563, 0xF9E2, 0x558A, + 0xF9E3, 0x6ABB, 0xF9E4, 0x6DB5, 0xF9E5, 0x7DD8, 0xF9E6, 0x8266, + 0xF9E7, 0x929C, 0xF9E8, 0x9677, 0xF9E9, 0x9E79, 0xF9EA, 0x5408, + 0xF9EB, 0x54C8, 0xF9EC, 0x76D2, 0xF9ED, 0x86E4, 0xF9EE, 0x95A4, + 0xF9EF, 0x95D4, 0xF9F0, 0x965C, 0xF9F1, 0x4EA2, 0xF9F2, 0x4F09, + 0xF9F3, 0x59EE, 0xF9F4, 0x5AE6, 0xF9F5, 0x5DF7, 0xF9F6, 0x6052, + 0xF9F7, 0x6297, 0xF9F8, 0x676D, 0xF9F9, 0x6841, 0xF9FA, 0x6C86, + 0xF9FB, 0x6E2F, 0xF9FC, 0x7F38, 0xF9FD, 0x809B, 0xF9FE, 0x822A, + 0xFAA1, 0xFA08, 0xFAA2, 0xFA09, 0xFAA3, 0x9805, 0xFAA4, 0x4EA5, + 0xFAA5, 0x5055, 0xFAA6, 0x54B3, 0xFAA7, 0x5793, 0xFAA8, 0x595A, + 0xFAA9, 0x5B69, 0xFAAA, 0x5BB3, 0xFAAB, 0x61C8, 0xFAAC, 0x6977, + 0xFAAD, 0x6D77, 0xFAAE, 0x7023, 0xFAAF, 0x87F9, 0xFAB0, 0x89E3, + 0xFAB1, 0x8A72, 0xFAB2, 0x8AE7, 0xFAB3, 0x9082, 0xFAB4, 0x99ED, + 0xFAB5, 0x9AB8, 0xFAB6, 0x52BE, 0xFAB7, 0x6838, 0xFAB8, 0x5016, + 0xFAB9, 0x5E78, 0xFABA, 0x674F, 0xFABB, 0x8347, 0xFABC, 0x884C, + 0xFABD, 0x4EAB, 0xFABE, 0x5411, 0xFABF, 0x56AE, 0xFAC0, 0x73E6, + 0xFAC1, 0x9115, 0xFAC2, 0x97FF, 0xFAC3, 0x9909, 0xFAC4, 0x9957, + 0xFAC5, 0x9999, 0xFAC6, 0x5653, 0xFAC7, 0x589F, 0xFAC8, 0x865B, + 0xFAC9, 0x8A31, 0xFACA, 0x61B2, 0xFACB, 0x6AF6, 0xFACC, 0x737B, + 0xFACD, 0x8ED2, 0xFACE, 0x6B47, 0xFACF, 0x96AA, 0xFAD0, 0x9A57, + 0xFAD1, 0x5955, 0xFAD2, 0x7200, 0xFAD3, 0x8D6B, 0xFAD4, 0x9769, + 0xFAD5, 0x4FD4, 0xFAD6, 0x5CF4, 0xFAD7, 0x5F26, 0xFAD8, 0x61F8, + 0xFAD9, 0x665B, 0xFADA, 0x6CEB, 0xFADB, 0x70AB, 0xFADC, 0x7384, + 0xFADD, 0x73B9, 0xFADE, 0x73FE, 0xFADF, 0x7729, 0xFAE0, 0x774D, + 0xFAE1, 0x7D43, 0xFAE2, 0x7D62, 0xFAE3, 0x7E23, 0xFAE4, 0x8237, + 0xFAE5, 0x8852, 0xFAE6, 0xFA0A, 0xFAE7, 0x8CE2, 0xFAE8, 0x9249, + 0xFAE9, 0x986F, 0xFAEA, 0x5B51, 0xFAEB, 0x7A74, 0xFAEC, 0x8840, + 0xFAED, 0x9801, 0xFAEE, 0x5ACC, 0xFAEF, 0x4FE0, 0xFAF0, 0x5354, + 0xFAF1, 0x593E, 0xFAF2, 0x5CFD, 0xFAF3, 0x633E, 0xFAF4, 0x6D79, + 0xFAF5, 0x72F9, 0xFAF6, 0x8105, 0xFAF7, 0x8107, 0xFAF8, 0x83A2, + 0xFAF9, 0x92CF, 0xFAFA, 0x9830, 0xFAFB, 0x4EA8, 0xFAFC, 0x5144, + 0xFAFD, 0x5211, 0xFAFE, 0x578B, 0xFBA1, 0x5F62, 0xFBA2, 0x6CC2, + 0xFBA3, 0x6ECE, 0xFBA4, 0x7005, 0xFBA5, 0x7050, 0xFBA6, 0x70AF, + 0xFBA7, 0x7192, 0xFBA8, 0x73E9, 0xFBA9, 0x7469, 0xFBAA, 0x834A, + 0xFBAB, 0x87A2, 0xFBAC, 0x8861, 0xFBAD, 0x9008, 0xFBAE, 0x90A2, + 0xFBAF, 0x93A3, 0xFBB0, 0x99A8, 0xFBB1, 0x516E, 0xFBB2, 0x5F57, + 0xFBB3, 0x60E0, 0xFBB4, 0x6167, 0xFBB5, 0x66B3, 0xFBB6, 0x8559, + 0xFBB7, 0x8E4A, 0xFBB8, 0x91AF, 0xFBB9, 0x978B, 0xFBBA, 0x4E4E, + 0xFBBB, 0x4E92, 0xFBBC, 0x547C, 0xFBBD, 0x58D5, 0xFBBE, 0x58FA, + 0xFBBF, 0x597D, 0xFBC0, 0x5CB5, 0xFBC1, 0x5F27, 0xFBC2, 0x6236, + 0xFBC3, 0x6248, 0xFBC4, 0x660A, 0xFBC5, 0x6667, 0xFBC6, 0x6BEB, + 0xFBC7, 0x6D69, 0xFBC8, 0x6DCF, 0xFBC9, 0x6E56, 0xFBCA, 0x6EF8, + 0xFBCB, 0x6F94, 0xFBCC, 0x6FE0, 0xFBCD, 0x6FE9, 0xFBCE, 0x705D, + 0xFBCF, 0x72D0, 0xFBD0, 0x7425, 0xFBD1, 0x745A, 0xFBD2, 0x74E0, + 0xFBD3, 0x7693, 0xFBD4, 0x795C, 0xFBD5, 0x7CCA, 0xFBD6, 0x7E1E, + 0xFBD7, 0x80E1, 0xFBD8, 0x82A6, 0xFBD9, 0x846B, 0xFBDA, 0x84BF, + 0xFBDB, 0x864E, 0xFBDC, 0x865F, 0xFBDD, 0x8774, 0xFBDE, 0x8B77, + 0xFBDF, 0x8C6A, 0xFBE0, 0x93AC, 0xFBE1, 0x9800, 0xFBE2, 0x9865, + 0xFBE3, 0x60D1, 0xFBE4, 0x6216, 0xFBE5, 0x9177, 0xFBE6, 0x5A5A, + 0xFBE7, 0x660F, 0xFBE8, 0x6DF7, 0xFBE9, 0x6E3E, 0xFBEA, 0x743F, + 0xFBEB, 0x9B42, 0xFBEC, 0x5FFD, 0xFBED, 0x60DA, 0xFBEE, 0x7B0F, + 0xFBEF, 0x54C4, 0xFBF0, 0x5F18, 0xFBF1, 0x6C5E, 0xFBF2, 0x6CD3, + 0xFBF3, 0x6D2A, 0xFBF4, 0x70D8, 0xFBF5, 0x7D05, 0xFBF6, 0x8679, + 0xFBF7, 0x8A0C, 0xFBF8, 0x9D3B, 0xFBF9, 0x5316, 0xFBFA, 0x548C, + 0xFBFB, 0x5B05, 0xFBFC, 0x6A3A, 0xFBFD, 0x706B, 0xFBFE, 0x7575, + 0xFCA1, 0x798D, 0xFCA2, 0x79BE, 0xFCA3, 0x82B1, 0xFCA4, 0x83EF, + 0xFCA5, 0x8A71, 0xFCA6, 0x8B41, 0xFCA7, 0x8CA8, 0xFCA8, 0x9774, + 0xFCA9, 0xFA0B, 0xFCAA, 0x64F4, 0xFCAB, 0x652B, 0xFCAC, 0x78BA, + 0xFCAD, 0x78BB, 0xFCAE, 0x7A6B, 0xFCAF, 0x4E38, 0xFCB0, 0x559A, + 0xFCB1, 0x5950, 0xFCB2, 0x5BA6, 0xFCB3, 0x5E7B, 0xFCB4, 0x60A3, + 0xFCB5, 0x63DB, 0xFCB6, 0x6B61, 0xFCB7, 0x6665, 0xFCB8, 0x6853, + 0xFCB9, 0x6E19, 0xFCBA, 0x7165, 0xFCBB, 0x74B0, 0xFCBC, 0x7D08, + 0xFCBD, 0x9084, 0xFCBE, 0x9A69, 0xFCBF, 0x9C25, 0xFCC0, 0x6D3B, + 0xFCC1, 0x6ED1, 0xFCC2, 0x733E, 0xFCC3, 0x8C41, 0xFCC4, 0x95CA, + 0xFCC5, 0x51F0, 0xFCC6, 0x5E4C, 0xFCC7, 0x5FA8, 0xFCC8, 0x604D, + 0xFCC9, 0x60F6, 0xFCCA, 0x6130, 0xFCCB, 0x614C, 0xFCCC, 0x6643, + 0xFCCD, 0x6644, 0xFCCE, 0x69A5, 0xFCCF, 0x6CC1, 0xFCD0, 0x6E5F, + 0xFCD1, 0x6EC9, 0xFCD2, 0x6F62, 0xFCD3, 0x714C, 0xFCD4, 0x749C, + 0xFCD5, 0x7687, 0xFCD6, 0x7BC1, 0xFCD7, 0x7C27, 0xFCD8, 0x8352, + 0xFCD9, 0x8757, 0xFCDA, 0x9051, 0xFCDB, 0x968D, 0xFCDC, 0x9EC3, + 0xFCDD, 0x532F, 0xFCDE, 0x56DE, 0xFCDF, 0x5EFB, 0xFCE0, 0x5F8A, + 0xFCE1, 0x6062, 0xFCE2, 0x6094, 0xFCE3, 0x61F7, 0xFCE4, 0x6666, + 0xFCE5, 0x6703, 0xFCE6, 0x6A9C, 0xFCE7, 0x6DEE, 0xFCE8, 0x6FAE, + 0xFCE9, 0x7070, 0xFCEA, 0x736A, 0xFCEB, 0x7E6A, 0xFCEC, 0x81BE, + 0xFCED, 0x8334, 0xFCEE, 0x86D4, 0xFCEF, 0x8AA8, 0xFCF0, 0x8CC4, + 0xFCF1, 0x5283, 0xFCF2, 0x7372, 0xFCF3, 0x5B96, 0xFCF4, 0x6A6B, + 0xFCF5, 0x9404, 0xFCF6, 0x54EE, 0xFCF7, 0x5686, 0xFCF8, 0x5B5D, + 0xFCF9, 0x6548, 0xFCFA, 0x6585, 0xFCFB, 0x66C9, 0xFCFC, 0x689F, + 0xFCFD, 0x6D8D, 0xFCFE, 0x6DC6, 0xFDA1, 0x723B, 0xFDA2, 0x80B4, + 0xFDA3, 0x9175, 0xFDA4, 0x9A4D, 0xFDA5, 0x4FAF, 0xFDA6, 0x5019, + 0xFDA7, 0x539A, 0xFDA8, 0x540E, 0xFDA9, 0x543C, 0xFDAA, 0x5589, + 0xFDAB, 0x55C5, 0xFDAC, 0x5E3F, 0xFDAD, 0x5F8C, 0xFDAE, 0x673D, + 0xFDAF, 0x7166, 0xFDB0, 0x73DD, 0xFDB1, 0x9005, 0xFDB2, 0x52DB, + 0xFDB3, 0x52F3, 0xFDB4, 0x5864, 0xFDB5, 0x58CE, 0xFDB6, 0x7104, + 0xFDB7, 0x718F, 0xFDB8, 0x71FB, 0xFDB9, 0x85B0, 0xFDBA, 0x8A13, + 0xFDBB, 0x6688, 0xFDBC, 0x85A8, 0xFDBD, 0x55A7, 0xFDBE, 0x6684, + 0xFDBF, 0x714A, 0xFDC0, 0x8431, 0xFDC1, 0x5349, 0xFDC2, 0x5599, + 0xFDC3, 0x6BC1, 0xFDC4, 0x5F59, 0xFDC5, 0x5FBD, 0xFDC6, 0x63EE, + 0xFDC7, 0x6689, 0xFDC8, 0x7147, 0xFDC9, 0x8AF1, 0xFDCA, 0x8F1D, + 0xFDCB, 0x9EBE, 0xFDCC, 0x4F11, 0xFDCD, 0x643A, 0xFDCE, 0x70CB, + 0xFDCF, 0x7566, 0xFDD0, 0x8667, 0xFDD1, 0x6064, 0xFDD2, 0x8B4E, + 0xFDD3, 0x9DF8, 0xFDD4, 0x5147, 0xFDD5, 0x51F6, 0xFDD6, 0x5308, + 0xFDD7, 0x6D36, 0xFDD8, 0x80F8, 0xFDD9, 0x9ED1, 0xFDDA, 0x6615, + 0xFDDB, 0x6B23, 0xFDDC, 0x7098, 0xFDDD, 0x75D5, 0xFDDE, 0x5403, + 0xFDDF, 0x5C79, 0xFDE0, 0x7D07, 0xFDE1, 0x8A16, 0xFDE2, 0x6B20, + 0xFDE3, 0x6B3D, 0xFDE4, 0x6B46, 0xFDE5, 0x5438, 0xFDE6, 0x6070, + 0xFDE7, 0x6D3D, 0xFDE8, 0x7FD5, 0xFDE9, 0x8208, 0xFDEA, 0x50D6, + 0xFDEB, 0x51DE, 0xFDEC, 0x559C, 0xFDED, 0x566B, 0xFDEE, 0x56CD, + 0xFDEF, 0x59EC, 0xFDF0, 0x5B09, 0xFDF1, 0x5E0C, 0xFDF2, 0x6199, + 0xFDF3, 0x6198, 0xFDF4, 0x6231, 0xFDF5, 0x665E, 0xFDF6, 0x66E6, + 0xFDF7, 0x7199, 0xFDF8, 0x71B9, 0xFDF9, 0x71BA, 0xFDFA, 0x72A7, + 0xFDFB, 0x79A7, 0xFDFC, 0x7A00, 0xFDFD, 0x7FB2, 0xFDFE, 0x8A70, + 0, 0 +}; + + + +WCHAR ff_convert ( /* Converted code, 0 means conversion error */ + WCHAR chr, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEM code, 1: OEM code to Unicode */ +) +{ + const WCHAR *p; + WCHAR c; + int i, n, li, hi; + + + if (chr < 0x80) { /* ASCII */ + c = chr; + } else { + if (dir) { /* OEM code to unicode */ + p = oem2uni; + hi = sizeof oem2uni / 4 - 1; + } else { /* Unicode to OEM code */ + p = uni2oem; + hi = sizeof uni2oem / 4 - 1; + } + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (chr == p[i * 2]) break; + if (chr > p[i * 2]) + li = i; + else + hi = i; + } + c = n ? p[i * 2 + 1] : 0; + } + + return c; +} + + + +WCHAR ff_wtoupper ( /* Returns upper converted character */ + WCHAR chr /* Unicode character to be upper converted (BMP only) */ +) +{ + /* Compressed upper conversion table */ + static const WCHAR cvt1[] = { /* U+0000 - U+0FFF */ + /* Basic Latin */ + 0x0061,0x031A, + /* Latin-1 Supplement */ + 0x00E0,0x0317, 0x00F8,0x0307, 0x00FF,0x0001,0x0178, + /* Latin Extended-A */ + 0x0100,0x0130, 0x0132,0x0106, 0x0139,0x0110, 0x014A,0x012E, 0x0179,0x0106, + /* Latin Extended-B */ + 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, + 0x01CD,0x0110, 0x01DD,0x0001,0x018E, 0x01DE,0x0112, 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, 0x01F8,0x0128, + 0x0222,0x0112, 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, 0x0246,0x010A, + /* IPA Extensions */ + 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, + /* Greek, Coptic */ + 0x037B,0x0003,0x03FD,0x03FE,0x03FF, 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, 0x03B1,0x0311, + 0x03C2,0x0002,0x03A3,0x03A3, 0x03C4,0x0308, 0x03CC,0x0003,0x038C,0x038E,0x038F, 0x03D8,0x0118, + 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, + /* Cyrillic */ + 0x0430,0x0320, 0x0450,0x0710, 0x0460,0x0122, 0x048A,0x0136, 0x04C1,0x010E, 0x04CF,0x0001,0x04C0, 0x04D0,0x0144, + /* Armenian */ + 0x0561,0x0426, + + 0x0000 + }; + static const WCHAR cvt2[] = { /* U+1000 - U+FFFF */ + /* Phonetic Extensions */ + 0x1D7D,0x0001,0x2C63, + /* Latin Extended Additional */ + 0x1E00,0x0196, 0x1EA0,0x015A, + /* Greek Extended */ + 0x1F00,0x0608, 0x1F10,0x0606, 0x1F20,0x0608, 0x1F30,0x0608, 0x1F40,0x0606, + 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, 0x1F60,0x0608, + 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, + 0x1F80,0x0608, 0x1F90,0x0608, 0x1FA0,0x0608, 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, + 0x1FCC,0x0001,0x1FC3, 0x1FD0,0x0602, 0x1FE0,0x0602, 0x1FE5,0x0001,0x1FEC, 0x1FF2,0x0001,0x1FFC, + /* Letterlike Symbols */ + 0x214E,0x0001,0x2132, + /* Number forms */ + 0x2170,0x0210, 0x2184,0x0001,0x2183, + /* Enclosed Alphanumerics */ + 0x24D0,0x051A, 0x2C30,0x042F, + /* Latin Extended-C */ + 0x2C60,0x0102, 0x2C67,0x0106, 0x2C75,0x0102, + /* Coptic */ + 0x2C80,0x0164, + /* Georgian Supplement */ + 0x2D00,0x0826, + /* Full-width */ + 0xFF41,0x031A, + + 0x0000 + }; + const WCHAR *p; + WCHAR bc, nc, cmd; + + + p = chr < 0x1000 ? cvt1 : cvt2; + for (;;) { + bc = *p++; /* Get block base */ + if (!bc || chr < bc) break; + nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ + if (chr < bc + nc) { /* In the block? */ + switch (cmd) { + case 0: chr = p[chr - bc]; break; /* Table conversion */ + case 1: chr -= (chr - bc) & 1; break; /* Case pairs */ + case 2: chr -= 16; break; /* Shift -16 */ + case 3: chr -= 32; break; /* Shift -32 */ + case 4: chr -= 48; break; /* Shift -48 */ + case 5: chr -= 26; break; /* Shift -26 */ + case 6: chr += 8; break; /* Shift +8 */ + case 7: chr -= 80; break; /* Shift -80 */ + case 8: chr -= 0x1C60; break; /* Shift -0x1C60 */ + } + break; + } + if (!cmd) p += nc; + } + + return chr; +} + diff --git a/radio/src/thirdparty/FatFs/option/cc950.c b/radio/src/thirdparty/FatFs/option/cc950.c index bbcaa2443..deac542c6 100644 --- a/radio/src/thirdparty/FatFs/option/cc950.c +++ b/radio/src/thirdparty/FatFs/option/cc950.c @@ -1,6900 +1,6900 @@ -/*------------------------------------------------------------------------*/ -/* Unicode - OEM code bidirectional converter (C)ChaN, 2015 */ -/* CP950 (Traditional Chinese Big5) */ -/*------------------------------------------------------------------------*/ - -#include "../ff.h" - - -#if !_USE_LFN || _CODE_PAGE != 950 -#error This file is not needed in current configuration. Remove from the project. -#endif - - -static -const WCHAR uni2oem[] = { -/* Unicode - OEM, Unicode - OEM, Unicode - OEM, Unicode - OEM */ - 0x00A7, 0xA1B1, 0x00AF, 0xA1C2, 0x00B0, 0xA258, 0x00B1, 0xA1D3, - 0x00B7, 0xA150, 0x00D7, 0xA1D1, 0x00F7, 0xA1D2, 0x02C7, 0xA3BE, - 0x02C9, 0xA3BC, 0x02CA, 0xA3BD, 0x02CB, 0xA3BF, 0x02CD, 0xA1C5, - 0x02D9, 0xA3BB, 0x0391, 0xA344, 0x0392, 0xA345, 0x0393, 0xA346, - 0x0394, 0xA347, 0x0395, 0xA348, 0x0396, 0xA349, 0x0397, 0xA34A, - 0x0398, 0xA34B, 0x0399, 0xA34C, 0x039A, 0xA34D, 0x039B, 0xA34E, - 0x039C, 0xA34F, 0x039D, 0xA350, 0x039E, 0xA351, 0x039F, 0xA352, - 0x03A0, 0xA353, 0x03A1, 0xA354, 0x03A3, 0xA355, 0x03A4, 0xA356, - 0x03A5, 0xA357, 0x03A6, 0xA358, 0x03A7, 0xA359, 0x03A8, 0xA35A, - 0x03A9, 0xA35B, 0x03B1, 0xA35C, 0x03B2, 0xA35D, 0x03B3, 0xA35E, - 0x03B4, 0xA35F, 0x03B5, 0xA360, 0x03B6, 0xA361, 0x03B7, 0xA362, - 0x03B8, 0xA363, 0x03B9, 0xA364, 0x03BA, 0xA365, 0x03BB, 0xA366, - 0x03BC, 0xA367, 0x03BD, 0xA368, 0x03BE, 0xA369, 0x03BF, 0xA36A, - 0x03C0, 0xA36B, 0x03C1, 0xA36C, 0x03C3, 0xA36D, 0x03C4, 0xA36E, - 0x03C5, 0xA36F, 0x03C6, 0xA370, 0x03C7, 0xA371, 0x03C8, 0xA372, - 0x03C9, 0xA373, 0x2013, 0xA156, 0x2014, 0xA158, 0x2018, 0xA1A5, - 0x2019, 0xA1A6, 0x201C, 0xA1A7, 0x201D, 0xA1A8, 0x2025, 0xA14C, - 0x2026, 0xA14B, 0x2027, 0xA145, 0x2032, 0xA1AC, 0x2035, 0xA1AB, - 0x203B, 0xA1B0, 0x20AC, 0xA3E1, 0x2103, 0xA24A, 0x2105, 0xA1C1, - 0x2109, 0xA24B, 0x2160, 0xA2B9, 0x2161, 0xA2BA, 0x2162, 0xA2BB, - 0x2163, 0xA2BC, 0x2164, 0xA2BD, 0x2165, 0xA2BE, 0x2166, 0xA2BF, - 0x2167, 0xA2C0, 0x2168, 0xA2C1, 0x2169, 0xA2C2, 0x2190, 0xA1F6, - 0x2191, 0xA1F4, 0x2192, 0xA1F7, 0x2193, 0xA1F5, 0x2196, 0xA1F8, - 0x2197, 0xA1F9, 0x2198, 0xA1FB, 0x2199, 0xA1FA, 0x2215, 0xA241, - 0x221A, 0xA1D4, 0x221E, 0xA1DB, 0x221F, 0xA1E8, 0x2220, 0xA1E7, - 0x2223, 0xA1FD, 0x2225, 0xA1FC, 0x2229, 0xA1E4, 0x222A, 0xA1E5, - 0x222B, 0xA1EC, 0x222E, 0xA1ED, 0x2234, 0xA1EF, 0x2235, 0xA1EE, - 0x2252, 0xA1DC, 0x2260, 0xA1DA, 0x2261, 0xA1DD, 0x2266, 0xA1D8, - 0x2267, 0xA1D9, 0x2295, 0xA1F2, 0x2299, 0xA1F3, 0x22A5, 0xA1E6, - 0x22BF, 0xA1E9, 0x2500, 0xA277, 0x2502, 0xA278, 0x250C, 0xA27A, - 0x2510, 0xA27B, 0x2514, 0xA27C, 0x2518, 0xA27D, 0x251C, 0xA275, - 0x2524, 0xA274, 0x252C, 0xA273, 0x2534, 0xA272, 0x253C, 0xA271, - 0x2550, 0xA2A4, 0x2550, 0xF9F9, 0x2551, 0xF9F8, 0x2552, 0xF9E6, - 0x2553, 0xF9EF, 0x2554, 0xF9DD, 0x2555, 0xF9E8, 0x2556, 0xF9F1, - 0x2557, 0xF9DF, 0x2558, 0xF9EC, 0x2559, 0xF9F5, 0x255A, 0xF9E3, - 0x255B, 0xF9EE, 0x255C, 0xF9F7, 0x255D, 0xF9E5, 0x255E, 0xA2A5, - 0x255E, 0xF9E9, 0x255F, 0xF9F2, 0x2560, 0xF9E0, 0x2561, 0xA2A7, - 0x2561, 0xF9EB, 0x2562, 0xF9F4, 0x2563, 0xF9E2, 0x2564, 0xF9E7, - 0x2565, 0xF9F0, 0x2566, 0xF9DE, 0x2567, 0xF9ED, 0x2568, 0xF9F6, - 0x2569, 0xF9E4, 0x256A, 0xA2A6, 0x256A, 0xF9EA, 0x256B, 0xF9F3, - 0x256C, 0xF9E1, 0x256D, 0xA27E, 0x256D, 0xF9FA, 0x256E, 0xA2A1, - 0x256E, 0xF9FB, 0x256F, 0xA2A3, 0x256F, 0xF9FD, 0x2570, 0xA2A2, - 0x2570, 0xF9FC, 0x2571, 0xA2AC, 0x2572, 0xA2AD, 0x2573, 0xA2AE, - 0x2574, 0xA15A, 0x2581, 0xA262, 0x2582, 0xA263, 0x2583, 0xA264, - 0x2584, 0xA265, 0x2585, 0xA266, 0x2586, 0xA267, 0x2587, 0xA268, - 0x2588, 0xA269, 0x2589, 0xA270, 0x258A, 0xA26F, 0x258B, 0xA26E, - 0x258C, 0xA26D, 0x258D, 0xA26C, 0x258E, 0xA26B, 0x258F, 0xA26A, - 0x2593, 0xF9FE, 0x2594, 0xA276, 0x2595, 0xA279, 0x25A0, 0xA1BD, - 0x25A1, 0xA1BC, 0x25B2, 0xA1B6, 0x25B3, 0xA1B5, 0x25BC, 0xA1BF, - 0x25BD, 0xA1BE, 0x25C6, 0xA1BB, 0x25C7, 0xA1BA, 0x25CB, 0xA1B3, - 0x25CE, 0xA1B7, 0x25CF, 0xA1B4, 0x25E2, 0xA2A8, 0x25E3, 0xA2A9, - 0x25E4, 0xA2AB, 0x25E5, 0xA2AA, 0x2605, 0xA1B9, 0x2606, 0xA1B8, - 0x2640, 0xA1F0, 0x2642, 0xA1F1, 0x3000, 0xA140, 0x3001, 0xA142, - 0x3002, 0xA143, 0x3003, 0xA1B2, 0x3008, 0xA171, 0x3009, 0xA172, - 0x300A, 0xA16D, 0x300B, 0xA16E, 0x300C, 0xA175, 0x300D, 0xA176, - 0x300E, 0xA179, 0x300F, 0xA17A, 0x3010, 0xA169, 0x3011, 0xA16A, - 0x3012, 0xA245, 0x3014, 0xA165, 0x3015, 0xA166, 0x301D, 0xA1A9, - 0x301E, 0xA1AA, 0x3021, 0xA2C3, 0x3022, 0xA2C4, 0x3023, 0xA2C5, - 0x3024, 0xA2C6, 0x3025, 0xA2C7, 0x3026, 0xA2C8, 0x3027, 0xA2C9, - 0x3028, 0xA2CA, 0x3029, 0xA2CB, 0x3105, 0xA374, 0x3106, 0xA375, - 0x3107, 0xA376, 0x3108, 0xA377, 0x3109, 0xA378, 0x310A, 0xA379, - 0x310B, 0xA37A, 0x310C, 0xA37B, 0x310D, 0xA37C, 0x310E, 0xA37D, - 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0x9D37, 0xEFA5, 0x9D38, 0xEF7D, 0x9D3B, 0xC245, 0x9D3D, 0xEFA7, - 0x9D3E, 0xEFA4, 0x9D3F, 0xC246, 0x9D40, 0xEFA6, 0x9D41, 0xEF77, - 0x9D42, 0xEFA2, 0x9D43, 0xEFA3, 0x9D45, 0xEFA1, 0x9D4A, 0xF1D2, - 0x9D4B, 0xF1D4, 0x9D4C, 0xF1D7, 0x9D4F, 0xF1D1, 0x9D51, 0xC359, - 0x9D52, 0xF1D9, 0x9D53, 0xF1D0, 0x9D54, 0xF1DA, 0x9D56, 0xF1D6, - 0x9D57, 0xF1D8, 0x9D58, 0xF1DC, 0x9D59, 0xF1D5, 0x9D5A, 0xF1DD, - 0x9D5B, 0xF1D3, 0x9D5C, 0xF1CF, 0x9D5D, 0xC35A, 0x9D5F, 0xF1DB, - 0x9D60, 0xC35B, 0x9D61, 0xC44D, 0x9D67, 0xEF78, 0x9D68, 0xF3F1, - 0x9D69, 0xF3E8, 0x9D6A, 0xC44F, 0x9D6B, 0xF3E4, 0x9D6C, 0xC450, - 0x9D6F, 0xF3ED, 0x9D70, 0xF3E7, 0x9D71, 0xF3DD, 0x9D72, 0xC44E, - 0x9D73, 0xF3EA, 0x9D74, 0xF3E5, 0x9D75, 0xF3E6, 0x9D77, 0xF3D8, - 0x9D78, 0xF3DF, 0x9D79, 0xF3EE, 0x9D7B, 0xF3EB, 0x9D7D, 0xF3E3, - 0x9D7F, 0xF3EF, 0x9D80, 0xF3DE, 0x9D81, 0xF3D9, 0x9D82, 0xF3EC, - 0x9D84, 0xF3DB, 0x9D85, 0xF3E9, 0x9D86, 0xF3E0, 0x9D87, 0xF3F0, - 0x9D88, 0xF3DC, 0x9D89, 0xC44C, 0x9D8A, 0xF3DA, 0x9D8B, 0xF3E1, - 0x9D8C, 0xF3E2, 0x9D90, 0xF57D, 0x9D92, 0xF57B, 0x9D94, 0xF5A2, - 0x9D96, 0xF5AE, 0x9D97, 0xF5A5, 0x9D98, 0xF57C, 0x9D99, 0xF578, - 0x9D9A, 0xF5A7, 0x9D9B, 0xF57E, 0x9D9C, 0xF5A3, 0x9D9D, 0xF57A, - 0x9D9E, 0xF5AA, 0x9D9F, 0xF577, 0x9DA0, 0xF5A1, 0x9DA1, 0xF5A6, - 0x9DA2, 0xF5A8, 0x9DA3, 0xF5AB, 0x9DA4, 0xF579, 0x9DA6, 0xF5AF, - 0x9DA7, 0xF5B0, 0x9DA8, 0xF5A9, 0x9DA9, 0xF5AD, 0x9DAA, 0xF5A4, - 0x9DAC, 0xF6C1, 0x9DAD, 0xF6C4, 0x9DAF, 0xC561, 0x9DB1, 0xF6C3, - 0x9DB2, 0xF6C8, 0x9DB3, 0xF6C6, 0x9DB4, 0xC562, 0x9DB5, 0xF6BD, - 0x9DB6, 0xF6B3, 0x9DB7, 0xF6B2, 0x9DB8, 0xC564, 0x9DB9, 0xF6BF, - 0x9DBA, 0xF6C0, 0x9DBB, 0xF6BC, 0x9DBC, 0xF6B4, 0x9DBE, 0xF6B9, - 0x9DBF, 0xF5AC, 0x9DC1, 0xF6B5, 0x9DC2, 0xC563, 0x9DC3, 0xF6BB, - 0x9DC5, 0xF6BA, 0x9DC7, 0xF6B6, 0x9DC8, 0xF6C2, 0x9DCA, 0xF6B7, - 0x9DCB, 0xF7BB, 0x9DCC, 0xF6C5, 0x9DCD, 0xF6C7, 0x9DCE, 0xF6BE, - 0x9DCF, 0xF6B8, 0x9DD0, 0xF7BC, 0x9DD1, 0xF7BE, 0x9DD2, 0xF7B8, - 0x9DD3, 0xC5C2, 0x9DD5, 0xF7C5, 0x9DD6, 0xF7C3, 0x9DD7, 0xC5C3, - 0x9DD8, 0xF7C2, 0x9DD9, 0xF7C1, 0x9DDA, 0xF7BA, 0x9DDB, 0xF7B7, - 0x9DDC, 0xF7BD, 0x9DDD, 0xF7C6, 0x9DDE, 0xF7B9, 0x9DDF, 0xF7BF, - 0x9DE1, 0xF869, 0x9DE2, 0xF86E, 0x9DE3, 0xF864, 0x9DE4, 0xF867, - 0x9DE5, 0xC5EE, 0x9DE6, 0xF86B, 0x9DE8, 0xF872, 0x9DE9, 0xF7C0, - 0x9DEB, 0xF865, 0x9DEC, 0xF86F, 0x9DED, 0xF873, 0x9DEE, 0xF86A, - 0x9DEF, 0xF863, 0x9DF0, 0xF86D, 0x9DF2, 0xF86C, 0x9DF3, 0xF871, - 0x9DF4, 0xF870, 0x9DF5, 0xF7C4, 0x9DF6, 0xF868, 0x9DF7, 0xF862, - 0x9DF8, 0xF866, 0x9DF9, 0xC64E, 0x9DFA, 0xC64F, 0x9DFB, 0xF861, - 0x9DFD, 0xF8E6, 0x9DFE, 0xF8DD, 0x9DFF, 0xF8E5, 0x9E00, 0xF8E2, - 0x9E01, 0xF8E3, 0x9E02, 0xF8DC, 0x9E03, 0xF8DF, 0x9E04, 0xF8E7, - 0x9E05, 0xF8E1, 0x9E06, 0xF8E0, 0x9E07, 0xF8DE, 0x9E09, 0xF8E4, - 0x9E0B, 0xF95D, 0x9E0D, 0xF95E, 0x9E0F, 0xF960, 0x9E10, 0xF95F, - 0x9E11, 0xF962, 0x9E12, 0xF961, 0x9E13, 0xF97C, 0x9E14, 0xF97B, - 0x9E15, 0xF9B7, 0x9E17, 0xF9B8, 0x9E19, 0xF9C5, 0x9E1A, 0xC678, - 0x9E1B, 0xC67C, 0x9E1D, 0xF9CF, 0x9E1E, 0xC67D, 0x9E75, 0xB3BF, - 0x9E79, 0xC4D0, 0x9E7A, 0xF6C9, 0x9E7C, 0xC650, 0x9E7D, 0xC651, - 0x9E7F, 0xB3C0, 0x9E80, 0xE0EE, 0x9E82, 0xB9A8, 0x9E83, 0xE8F0, - 0x9E86, 0xECB0, 0x9E87, 0xECB1, 0x9E88, 0xECAF, 0x9E89, 0xEFAB, - 0x9E8A, 0xEFAA, 0x9E8B, 0xC247, 0x9E8C, 0xF1DF, 0x9E8D, 0xEFAC, - 0x9E8E, 0xF1DE, 0x9E91, 0xF3F3, 0x9E92, 0xC451, 0x9E93, 0xC453, - 0x9E94, 0xF3F2, 0x9E97, 0xC452, 0x9E99, 0xF5B1, 0x9E9A, 0xF5B3, - 0x9E9B, 0xF5B2, 0x9E9C, 0xF6CA, 0x9E9D, 0xC565, 0x9E9F, 0xC5EF, - 0x9EA0, 0xF8E8, 0x9EA1, 0xF963, 0x9EA4, 0xF9D2, 0x9EA5, 0xB3C1, - 0x9EA7, 0xE4E5, 0x9EA9, 0xBEA2, 0x9EAD, 0xECB3, 0x9EAE, 0xECB2, - 0x9EB0, 0xEFAD, 0x9EB4, 0xC454, 0x9EB5, 0xC4D1, 0x9EB6, 0xF7C7, - 0x9EB7, 0xF9CB, 0x9EBB, 0xB3C2, 0x9EBC, 0xBBF2, 0x9EBE, 0xBEA3, - 0x9EC0, 0xF3F4, 0x9EC2, 0xF874, 0x9EC3, 0xB6C0, 0x9EC8, 0xEFAE, - 0x9ECC, 0xC664, 0x9ECD, 0xB6C1, 0x9ECE, 0xBEA4, 0x9ECF, 0xC248, - 0x9ED0, 0xF875, 0x9ED1, 0xB6C2, 0x9ED3, 0xE8F1, 0x9ED4, 0xC072, - 0x9ED5, 0xECB4, 0x9ED6, 0xECB5, 0x9ED8, 0xC071, 0x9EDA, 0xEFAF, - 0x9EDB, 0xC24C, 0x9EDC, 0xC24A, 0x9EDD, 0xC24B, 0x9EDE, 0xC249, - 0x9EDF, 0xF1E0, 0x9EE0, 0xC35C, 0x9EE4, 0xF5B5, 0x9EE5, 0xF5B4, - 0x9EE6, 0xF5B7, 0x9EE7, 0xF5B6, 0x9EE8, 0xC4D2, 0x9EEB, 0xF6CB, - 0x9EED, 0xF6CD, 0x9EEE, 0xF6CC, 0x9EEF, 0xC566, 0x9EF0, 0xF7C8, - 0x9EF2, 0xF876, 0x9EF3, 0xF877, 0x9EF4, 0xC5F0, 0x9EF5, 0xF964, - 0x9EF6, 0xF97D, 0x9EF7, 0xC675, 0x9EF9, 0xDCB0, 0x9EFA, 0xECB6, - 0x9EFB, 0xEFB0, 0x9EFC, 0xF3F5, 0x9EFD, 0xE0EF, 0x9EFF, 0xEFB1, - 0x9F00, 0xF1E2, 0x9F01, 0xF1E1, 0x9F06, 0xF878, 0x9F07, 0xC652, - 0x9F09, 0xF965, 0x9F0A, 0xF97E, 0x9F0E, 0xB9A9, 0x9F0F, 0xE8F2, - 0x9F10, 0xE8F3, 0x9F12, 0xECB7, 0x9F13, 0xB9AA, 0x9F15, 0xC35D, - 0x9F16, 0xF1E3, 0x9F18, 0xF6CF, 0x9F19, 0xC567, 0x9F1A, 0xF6D0, - 0x9F1B, 0xF6CE, 0x9F1C, 0xF879, 0x9F1E, 0xF8E9, 0x9F20, 0xB9AB, - 0x9F22, 0xEFB4, 0x9F23, 0xEFB3, 0x9F24, 0xEFB2, 0x9F25, 0xF1E4, - 0x9F28, 0xF1E8, 0x9F29, 0xF1E7, 0x9F2A, 0xF1E6, 0x9F2B, 0xF1E5, - 0x9F2C, 0xC35E, 0x9F2D, 0xF3F6, 0x9F2E, 0xF5B9, 0x9F2F, 0xC4D3, - 0x9F30, 0xF5B8, 0x9F31, 0xF6D1, 0x9F32, 0xF7CB, 0x9F33, 0xF7CA, - 0x9F34, 0xC5C4, 0x9F35, 0xF7C9, 0x9F36, 0xF87C, 0x9F37, 0xF87B, - 0x9F38, 0xF87A, 0x9F3B, 0xBBF3, 0x9F3D, 0xECB8, 0x9F3E, 0xC24D, - 0x9F40, 0xF3F7, 0x9F41, 0xF3F8, 0x9F42, 0xF7CC, 0x9F43, 0xF87D, - 0x9F46, 0xF8EA, 0x9F47, 0xF966, 0x9F48, 0xF9B9, 0x9F49, 0xF9D4, - 0x9F4A, 0xBBF4, 0x9F4B, 0xC24E, 0x9F4C, 0xF1E9, 0x9F4D, 0xF3F9, - 0x9F4E, 0xF6D2, 0x9F4F, 0xF87E, 0x9F52, 0xBEA6, 0x9F54, 0xEFB5, - 0x9F55, 0xF1EA, 0x9F56, 0xF3FA, 0x9F57, 0xF3FB, 0x9F58, 0xF3FC, - 0x9F59, 0xF5BE, 0x9F5B, 0xF5BA, 0x9F5C, 0xC568, 0x9F5D, 0xF5BD, - 0x9F5E, 0xF5BC, 0x9F5F, 0xC4D4, 0x9F60, 0xF5BB, 0x9F61, 0xC4D6, - 0x9F63, 0xC4D5, 0x9F64, 0xF6D4, 0x9F65, 0xF6D3, 0x9F66, 0xC569, - 0x9F67, 0xC56A, 0x9F6A, 0xC5C6, 0x9F6B, 0xF7CD, 0x9F6C, 0xC5C5, - 0x9F6E, 0xF8A3, 0x9F6F, 0xF8A4, 0x9F70, 0xF8A2, 0x9F71, 0xF8A1, - 0x9F72, 0xC654, 0x9F74, 0xF8EB, 0x9F75, 0xF8EC, 0x9F76, 0xF8ED, - 0x9F77, 0xC653, 0x9F78, 0xF967, 0x9F79, 0xF96A, 0x9F7A, 0xF969, - 0x9F7B, 0xF968, 0x9F7E, 0xF9D3, 0x9F8D, 0xC073, 0x9F90, 0xC365, - 0x9F91, 0xF5BF, 0x9F92, 0xF6D5, 0x9F94, 0xC5C7, 0x9F95, 0xF7CE, - 0x9F98, 0xF9D5, 0x9F9C, 0xC074, 0x9FA0, 0xEFB6, 0x9FA2, 0xF7CF, - 0x9FA4, 0xF9A1, 0xFA0C, 0xC94A, 0xFA0D, 0xDDFC, 0xFE30, 0xA14A, - 0xFE31, 0xA157, 0xFE33, 0xA159, 0xFE34, 0xA15B, 0xFE35, 0xA15F, - 0xFE36, 0xA160, 0xFE37, 0xA163, 0xFE38, 0xA164, 0xFE39, 0xA167, - 0xFE3A, 0xA168, 0xFE3B, 0xA16B, 0xFE3C, 0xA16C, 0xFE3D, 0xA16F, - 0xFE3E, 0xA170, 0xFE3F, 0xA173, 0xFE40, 0xA174, 0xFE41, 0xA177, - 0xFE42, 0xA178, 0xFE43, 0xA17B, 0xFE44, 0xA17C, 0xFE49, 0xA1C6, - 0xFE4A, 0xA1C7, 0xFE4B, 0xA1CA, 0xFE4C, 0xA1CB, 0xFE4D, 0xA1C8, - 0xFE4E, 0xA1C9, 0xFE4F, 0xA15C, 0xFE50, 0xA14D, 0xFE51, 0xA14E, - 0xFE52, 0xA14F, 0xFE54, 0xA151, 0xFE55, 0xA152, 0xFE56, 0xA153, - 0xFE57, 0xA154, 0xFE59, 0xA17D, 0xFE5A, 0xA17E, 0xFE5B, 0xA1A1, - 0xFE5C, 0xA1A2, 0xFE5D, 0xA1A3, 0xFE5E, 0xA1A4, 0xFE5F, 0xA1CC, - 0xFE60, 0xA1CD, 0xFE61, 0xA1CE, 0xFE62, 0xA1DE, 0xFE63, 0xA1DF, - 0xFE64, 0xA1E0, 0xFE65, 0xA1E1, 0xFE66, 0xA1E2, 0xFE68, 0xA242, - 0xFE69, 0xA24C, 0xFE6A, 0xA24D, 0xFE6B, 0xA24E, 0xFF01, 0xA149, - 0xFF03, 0xA1AD, 0xFF04, 0xA243, 0xFF05, 0xA248, 0xFF06, 0xA1AE, - 0xFF08, 0xA15D, 0xFF09, 0xA15E, 0xFF0A, 0xA1AF, 0xFF0B, 0xA1CF, - 0xFF0C, 0xA141, 0xFF0D, 0xA1D0, 0xFF0E, 0xA144, 0xFF0F, 0xA1FE, - 0xFF10, 0xA2AF, 0xFF11, 0xA2B0, 0xFF12, 0xA2B1, 0xFF13, 0xA2B2, - 0xFF14, 0xA2B3, 0xFF15, 0xA2B4, 0xFF16, 0xA2B5, 0xFF17, 0xA2B6, - 0xFF18, 0xA2B7, 0xFF19, 0xA2B8, 0xFF1A, 0xA147, 0xFF1B, 0xA146, - 0xFF1C, 0xA1D5, 0xFF1D, 0xA1D7, 0xFF1E, 0xA1D6, 0xFF1F, 0xA148, - 0xFF20, 0xA249, 0xFF21, 0xA2CF, 0xFF22, 0xA2D0, 0xFF23, 0xA2D1, - 0xFF24, 0xA2D2, 0xFF25, 0xA2D3, 0xFF26, 0xA2D4, 0xFF27, 0xA2D5, - 0xFF28, 0xA2D6, 0xFF29, 0xA2D7, 0xFF2A, 0xA2D8, 0xFF2B, 0xA2D9, - 0xFF2C, 0xA2DA, 0xFF2D, 0xA2DB, 0xFF2E, 0xA2DC, 0xFF2F, 0xA2DD, - 0xFF30, 0xA2DE, 0xFF31, 0xA2DF, 0xFF32, 0xA2E0, 0xFF33, 0xA2E1, - 0xFF34, 0xA2E2, 0xFF35, 0xA2E3, 0xFF36, 0xA2E4, 0xFF37, 0xA2E5, - 0xFF38, 0xA2E6, 0xFF39, 0xA2E7, 0xFF3A, 0xA2E8, 0xFF3C, 0xA240, - 0xFF3F, 0xA1C4, 0xFF41, 0xA2E9, 0xFF42, 0xA2EA, 0xFF43, 0xA2EB, - 0xFF44, 0xA2EC, 0xFF45, 0xA2ED, 0xFF46, 0xA2EE, 0xFF47, 0xA2EF, - 0xFF48, 0xA2F0, 0xFF49, 0xA2F1, 0xFF4A, 0xA2F2, 0xFF4B, 0xA2F3, - 0xFF4C, 0xA2F4, 0xFF4D, 0xA2F5, 0xFF4E, 0xA2F6, 0xFF4F, 0xA2F7, - 0xFF50, 0xA2F8, 0xFF51, 0xA2F9, 0xFF52, 0xA2FA, 0xFF53, 0xA2FB, - 0xFF54, 0xA2FC, 0xFF55, 0xA2FD, 0xFF56, 0xA2FE, 0xFF57, 0xA340, - 0xFF58, 0xA341, 0xFF59, 0xA342, 0xFF5A, 0xA343, 0xFF5B, 0xA161, - 0xFF5C, 0xA155, 0xFF5D, 0xA162, 0xFF5E, 0xA1E3, 0xFFE0, 0xA246, - 0xFFE1, 0xA247, 0xFFE3, 0xA1C3, 0xFFE5, 0xA244, 0, 0 -}; - -static -const WCHAR oem2uni[] = { -/* OEM - Unicode, OEM - Unicode, OEM - Unicode, OEM - Unicode */ - 0xA140, 0x3000, 0xA141, 0xFF0C, 0xA142, 0x3001, 0xA143, 0x3002, - 0xA144, 0xFF0E, 0xA145, 0x2027, 0xA146, 0xFF1B, 0xA147, 0xFF1A, - 0xA148, 0xFF1F, 0xA149, 0xFF01, 0xA14A, 0xFE30, 0xA14B, 0x2026, - 0xA14C, 0x2025, 0xA14D, 0xFE50, 0xA14E, 0xFE51, 0xA14F, 0xFE52, - 0xA150, 0x00B7, 0xA151, 0xFE54, 0xA152, 0xFE55, 0xA153, 0xFE56, - 0xA154, 0xFE57, 0xA155, 0xFF5C, 0xA156, 0x2013, 0xA157, 0xFE31, - 0xA158, 0x2014, 0xA159, 0xFE33, 0xA15A, 0x2574, 0xA15B, 0xFE34, - 0xA15C, 0xFE4F, 0xA15D, 0xFF08, 0xA15E, 0xFF09, 0xA15F, 0xFE35, - 0xA160, 0xFE36, 0xA161, 0xFF5B, 0xA162, 0xFF5D, 0xA163, 0xFE37, - 0xA164, 0xFE38, 0xA165, 0x3014, 0xA166, 0x3015, 0xA167, 0xFE39, - 0xA168, 0xFE3A, 0xA169, 0x3010, 0xA16A, 0x3011, 0xA16B, 0xFE3B, - 0xA16C, 0xFE3C, 0xA16D, 0x300A, 0xA16E, 0x300B, 0xA16F, 0xFE3D, - 0xA170, 0xFE3E, 0xA171, 0x3008, 0xA172, 0x3009, 0xA173, 0xFE3F, - 0xA174, 0xFE40, 0xA175, 0x300C, 0xA176, 0x300D, 0xA177, 0xFE41, - 0xA178, 0xFE42, 0xA179, 0x300E, 0xA17A, 0x300F, 0xA17B, 0xFE43, - 0xA17C, 0xFE44, 0xA17D, 0xFE59, 0xA17E, 0xFE5A, 0xA1A1, 0xFE5B, - 0xA1A2, 0xFE5C, 0xA1A3, 0xFE5D, 0xA1A4, 0xFE5E, 0xA1A5, 0x2018, - 0xA1A6, 0x2019, 0xA1A7, 0x201C, 0xA1A8, 0x201D, 0xA1A9, 0x301D, - 0xA1AA, 0x301E, 0xA1AB, 0x2035, 0xA1AC, 0x2032, 0xA1AD, 0xFF03, - 0xA1AE, 0xFF06, 0xA1AF, 0xFF0A, 0xA1B0, 0x203B, 0xA1B1, 0x00A7, - 0xA1B2, 0x3003, 0xA1B3, 0x25CB, 0xA1B4, 0x25CF, 0xA1B5, 0x25B3, - 0xA1B6, 0x25B2, 0xA1B7, 0x25CE, 0xA1B8, 0x2606, 0xA1B9, 0x2605, - 0xA1BA, 0x25C7, 0xA1BB, 0x25C6, 0xA1BC, 0x25A1, 0xA1BD, 0x25A0, - 0xA1BE, 0x25BD, 0xA1BF, 0x25BC, 0xA1C0, 0x32A3, 0xA1C1, 0x2105, - 0xA1C2, 0x00AF, 0xA1C3, 0xFFE3, 0xA1C4, 0xFF3F, 0xA1C5, 0x02CD, - 0xA1C6, 0xFE49, 0xA1C7, 0xFE4A, 0xA1C8, 0xFE4D, 0xA1C9, 0xFE4E, - 0xA1CA, 0xFE4B, 0xA1CB, 0xFE4C, 0xA1CC, 0xFE5F, 0xA1CD, 0xFE60, - 0xA1CE, 0xFE61, 0xA1CF, 0xFF0B, 0xA1D0, 0xFF0D, 0xA1D1, 0x00D7, - 0xA1D2, 0x00F7, 0xA1D3, 0x00B1, 0xA1D4, 0x221A, 0xA1D5, 0xFF1C, - 0xA1D6, 0xFF1E, 0xA1D7, 0xFF1D, 0xA1D8, 0x2266, 0xA1D9, 0x2267, - 0xA1DA, 0x2260, 0xA1DB, 0x221E, 0xA1DC, 0x2252, 0xA1DD, 0x2261, - 0xA1DE, 0xFE62, 0xA1DF, 0xFE63, 0xA1E0, 0xFE64, 0xA1E1, 0xFE65, - 0xA1E2, 0xFE66, 0xA1E3, 0xFF5E, 0xA1E4, 0x2229, 0xA1E5, 0x222A, - 0xA1E6, 0x22A5, 0xA1E7, 0x2220, 0xA1E8, 0x221F, 0xA1E9, 0x22BF, - 0xA1EA, 0x33D2, 0xA1EB, 0x33D1, 0xA1EC, 0x222B, 0xA1ED, 0x222E, - 0xA1EE, 0x2235, 0xA1EF, 0x2234, 0xA1F0, 0x2640, 0xA1F1, 0x2642, - 0xA1F2, 0x2295, 0xA1F3, 0x2299, 0xA1F4, 0x2191, 0xA1F5, 0x2193, - 0xA1F6, 0x2190, 0xA1F7, 0x2192, 0xA1F8, 0x2196, 0xA1F9, 0x2197, - 0xA1FA, 0x2199, 0xA1FB, 0x2198, 0xA1FC, 0x2225, 0xA1FD, 0x2223, - 0xA1FE, 0xFF0F, 0xA240, 0xFF3C, 0xA241, 0x2215, 0xA242, 0xFE68, - 0xA243, 0xFF04, 0xA244, 0xFFE5, 0xA245, 0x3012, 0xA246, 0xFFE0, - 0xA247, 0xFFE1, 0xA248, 0xFF05, 0xA249, 0xFF20, 0xA24A, 0x2103, - 0xA24B, 0x2109, 0xA24C, 0xFE69, 0xA24D, 0xFE6A, 0xA24E, 0xFE6B, - 0xA24F, 0x33D5, 0xA250, 0x339C, 0xA251, 0x339D, 0xA252, 0x339E, - 0xA253, 0x33CE, 0xA254, 0x33A1, 0xA255, 0x338E, 0xA256, 0x338F, - 0xA257, 0x33C4, 0xA258, 0x00B0, 0xA259, 0x5159, 0xA25A, 0x515B, - 0xA25B, 0x515E, 0xA25C, 0x515D, 0xA25D, 0x5161, 0xA25E, 0x5163, - 0xA25F, 0x55E7, 0xA260, 0x74E9, 0xA261, 0x7CCE, 0xA262, 0x2581, - 0xA263, 0x2582, 0xA264, 0x2583, 0xA265, 0x2584, 0xA266, 0x2585, - 0xA267, 0x2586, 0xA268, 0x2587, 0xA269, 0x2588, 0xA26A, 0x258F, - 0xA26B, 0x258E, 0xA26C, 0x258D, 0xA26D, 0x258C, 0xA26E, 0x258B, - 0xA26F, 0x258A, 0xA270, 0x2589, 0xA271, 0x253C, 0xA272, 0x2534, - 0xA273, 0x252C, 0xA274, 0x2524, 0xA275, 0x251C, 0xA276, 0x2594, - 0xA277, 0x2500, 0xA278, 0x2502, 0xA279, 0x2595, 0xA27A, 0x250C, - 0xA27B, 0x2510, 0xA27C, 0x2514, 0xA27D, 0x2518, 0xA27E, 0x256D, - 0xA2A1, 0x256E, 0xA2A2, 0x2570, 0xA2A3, 0x256F, 0xA2A4, 0x2550, - 0xA2A5, 0x255E, 0xA2A6, 0x256A, 0xA2A7, 0x2561, 0xA2A8, 0x25E2, - 0xA2A9, 0x25E3, 0xA2AA, 0x25E5, 0xA2AB, 0x25E4, 0xA2AC, 0x2571, - 0xA2AD, 0x2572, 0xA2AE, 0x2573, 0xA2AF, 0xFF10, 0xA2B0, 0xFF11, - 0xA2B1, 0xFF12, 0xA2B2, 0xFF13, 0xA2B3, 0xFF14, 0xA2B4, 0xFF15, - 0xA2B5, 0xFF16, 0xA2B6, 0xFF17, 0xA2B7, 0xFF18, 0xA2B8, 0xFF19, - 0xA2B9, 0x2160, 0xA2BA, 0x2161, 0xA2BB, 0x2162, 0xA2BC, 0x2163, - 0xA2BD, 0x2164, 0xA2BE, 0x2165, 0xA2BF, 0x2166, 0xA2C0, 0x2167, - 0xA2C1, 0x2168, 0xA2C2, 0x2169, 0xA2C3, 0x3021, 0xA2C4, 0x3022, - 0xA2C5, 0x3023, 0xA2C6, 0x3024, 0xA2C7, 0x3025, 0xA2C8, 0x3026, - 0xA2C9, 0x3027, 0xA2CA, 0x3028, 0xA2CB, 0x3029, 0xA2CC, 0x5341, - 0xA2CD, 0x5344, 0xA2CE, 0x5345, 0xA2CF, 0xFF21, 0xA2D0, 0xFF22, - 0xA2D1, 0xFF23, 0xA2D2, 0xFF24, 0xA2D3, 0xFF25, 0xA2D4, 0xFF26, - 0xA2D5, 0xFF27, 0xA2D6, 0xFF28, 0xA2D7, 0xFF29, 0xA2D8, 0xFF2A, - 0xA2D9, 0xFF2B, 0xA2DA, 0xFF2C, 0xA2DB, 0xFF2D, 0xA2DC, 0xFF2E, - 0xA2DD, 0xFF2F, 0xA2DE, 0xFF30, 0xA2DF, 0xFF31, 0xA2E0, 0xFF32, - 0xA2E1, 0xFF33, 0xA2E2, 0xFF34, 0xA2E3, 0xFF35, 0xA2E4, 0xFF36, - 0xA2E5, 0xFF37, 0xA2E6, 0xFF38, 0xA2E7, 0xFF39, 0xA2E8, 0xFF3A, - 0xA2E9, 0xFF41, 0xA2EA, 0xFF42, 0xA2EB, 0xFF43, 0xA2EC, 0xFF44, - 0xA2ED, 0xFF45, 0xA2EE, 0xFF46, 0xA2EF, 0xFF47, 0xA2F0, 0xFF48, - 0xA2F1, 0xFF49, 0xA2F2, 0xFF4A, 0xA2F3, 0xFF4B, 0xA2F4, 0xFF4C, - 0xA2F5, 0xFF4D, 0xA2F6, 0xFF4E, 0xA2F7, 0xFF4F, 0xA2F8, 0xFF50, - 0xA2F9, 0xFF51, 0xA2FA, 0xFF52, 0xA2FB, 0xFF53, 0xA2FC, 0xFF54, - 0xA2FD, 0xFF55, 0xA2FE, 0xFF56, 0xA340, 0xFF57, 0xA341, 0xFF58, - 0xA342, 0xFF59, 0xA343, 0xFF5A, 0xA344, 0x0391, 0xA345, 0x0392, - 0xA346, 0x0393, 0xA347, 0x0394, 0xA348, 0x0395, 0xA349, 0x0396, - 0xA34A, 0x0397, 0xA34B, 0x0398, 0xA34C, 0x0399, 0xA34D, 0x039A, - 0xA34E, 0x039B, 0xA34F, 0x039C, 0xA350, 0x039D, 0xA351, 0x039E, - 0xA352, 0x039F, 0xA353, 0x03A0, 0xA354, 0x03A1, 0xA355, 0x03A3, - 0xA356, 0x03A4, 0xA357, 0x03A5, 0xA358, 0x03A6, 0xA359, 0x03A7, - 0xA35A, 0x03A8, 0xA35B, 0x03A9, 0xA35C, 0x03B1, 0xA35D, 0x03B2, - 0xA35E, 0x03B3, 0xA35F, 0x03B4, 0xA360, 0x03B5, 0xA361, 0x03B6, - 0xA362, 0x03B7, 0xA363, 0x03B8, 0xA364, 0x03B9, 0xA365, 0x03BA, - 0xA366, 0x03BB, 0xA367, 0x03BC, 0xA368, 0x03BD, 0xA369, 0x03BE, - 0xA36A, 0x03BF, 0xA36B, 0x03C0, 0xA36C, 0x03C1, 0xA36D, 0x03C3, - 0xA36E, 0x03C4, 0xA36F, 0x03C5, 0xA370, 0x03C6, 0xA371, 0x03C7, - 0xA372, 0x03C8, 0xA373, 0x03C9, 0xA374, 0x3105, 0xA375, 0x3106, - 0xA376, 0x3107, 0xA377, 0x3108, 0xA378, 0x3109, 0xA379, 0x310A, - 0xA37A, 0x310B, 0xA37B, 0x310C, 0xA37C, 0x310D, 0xA37D, 0x310E, - 0xA37E, 0x310F, 0xA3A1, 0x3110, 0xA3A2, 0x3111, 0xA3A3, 0x3112, - 0xA3A4, 0x3113, 0xA3A5, 0x3114, 0xA3A6, 0x3115, 0xA3A7, 0x3116, - 0xA3A8, 0x3117, 0xA3A9, 0x3118, 0xA3AA, 0x3119, 0xA3AB, 0x311A, - 0xA3AC, 0x311B, 0xA3AD, 0x311C, 0xA3AE, 0x311D, 0xA3AF, 0x311E, - 0xA3B0, 0x311F, 0xA3B1, 0x3120, 0xA3B2, 0x3121, 0xA3B3, 0x3122, - 0xA3B4, 0x3123, 0xA3B5, 0x3124, 0xA3B6, 0x3125, 0xA3B7, 0x3126, - 0xA3B8, 0x3127, 0xA3B9, 0x3128, 0xA3BA, 0x3129, 0xA3BB, 0x02D9, - 0xA3BC, 0x02C9, 0xA3BD, 0x02CA, 0xA3BE, 0x02C7, 0xA3BF, 0x02CB, - 0xA3E1, 0x20AC, 0xA440, 0x4E00, 0xA441, 0x4E59, 0xA442, 0x4E01, - 0xA443, 0x4E03, 0xA444, 0x4E43, 0xA445, 0x4E5D, 0xA446, 0x4E86, - 0xA447, 0x4E8C, 0xA448, 0x4EBA, 0xA449, 0x513F, 0xA44A, 0x5165, - 0xA44B, 0x516B, 0xA44C, 0x51E0, 0xA44D, 0x5200, 0xA44E, 0x5201, - 0xA44F, 0x529B, 0xA450, 0x5315, 0xA451, 0x5341, 0xA452, 0x535C, - 0xA453, 0x53C8, 0xA454, 0x4E09, 0xA455, 0x4E0B, 0xA456, 0x4E08, - 0xA457, 0x4E0A, 0xA458, 0x4E2B, 0xA459, 0x4E38, 0xA45A, 0x51E1, - 0xA45B, 0x4E45, 0xA45C, 0x4E48, 0xA45D, 0x4E5F, 0xA45E, 0x4E5E, - 0xA45F, 0x4E8E, 0xA460, 0x4EA1, 0xA461, 0x5140, 0xA462, 0x5203, - 0xA463, 0x52FA, 0xA464, 0x5343, 0xA465, 0x53C9, 0xA466, 0x53E3, - 0xA467, 0x571F, 0xA468, 0x58EB, 0xA469, 0x5915, 0xA46A, 0x5927, - 0xA46B, 0x5973, 0xA46C, 0x5B50, 0xA46D, 0x5B51, 0xA46E, 0x5B53, - 0xA46F, 0x5BF8, 0xA470, 0x5C0F, 0xA471, 0x5C22, 0xA472, 0x5C38, - 0xA473, 0x5C71, 0xA474, 0x5DDD, 0xA475, 0x5DE5, 0xA476, 0x5DF1, - 0xA477, 0x5DF2, 0xA478, 0x5DF3, 0xA479, 0x5DFE, 0xA47A, 0x5E72, - 0xA47B, 0x5EFE, 0xA47C, 0x5F0B, 0xA47D, 0x5F13, 0xA47E, 0x624D, - 0xA4A1, 0x4E11, 0xA4A2, 0x4E10, 0xA4A3, 0x4E0D, 0xA4A4, 0x4E2D, - 0xA4A5, 0x4E30, 0xA4A6, 0x4E39, 0xA4A7, 0x4E4B, 0xA4A8, 0x5C39, - 0xA4A9, 0x4E88, 0xA4AA, 0x4E91, 0xA4AB, 0x4E95, 0xA4AC, 0x4E92, - 0xA4AD, 0x4E94, 0xA4AE, 0x4EA2, 0xA4AF, 0x4EC1, 0xA4B0, 0x4EC0, - 0xA4B1, 0x4EC3, 0xA4B2, 0x4EC6, 0xA4B3, 0x4EC7, 0xA4B4, 0x4ECD, - 0xA4B5, 0x4ECA, 0xA4B6, 0x4ECB, 0xA4B7, 0x4EC4, 0xA4B8, 0x5143, - 0xA4B9, 0x5141, 0xA4BA, 0x5167, 0xA4BB, 0x516D, 0xA4BC, 0x516E, - 0xA4BD, 0x516C, 0xA4BE, 0x5197, 0xA4BF, 0x51F6, 0xA4C0, 0x5206, - 0xA4C1, 0x5207, 0xA4C2, 0x5208, 0xA4C3, 0x52FB, 0xA4C4, 0x52FE, - 0xA4C5, 0x52FF, 0xA4C6, 0x5316, 0xA4C7, 0x5339, 0xA4C8, 0x5348, - 0xA4C9, 0x5347, 0xA4CA, 0x5345, 0xA4CB, 0x535E, 0xA4CC, 0x5384, - 0xA4CD, 0x53CB, 0xA4CE, 0x53CA, 0xA4CF, 0x53CD, 0xA4D0, 0x58EC, - 0xA4D1, 0x5929, 0xA4D2, 0x592B, 0xA4D3, 0x592A, 0xA4D4, 0x592D, - 0xA4D5, 0x5B54, 0xA4D6, 0x5C11, 0xA4D7, 0x5C24, 0xA4D8, 0x5C3A, - 0xA4D9, 0x5C6F, 0xA4DA, 0x5DF4, 0xA4DB, 0x5E7B, 0xA4DC, 0x5EFF, - 0xA4DD, 0x5F14, 0xA4DE, 0x5F15, 0xA4DF, 0x5FC3, 0xA4E0, 0x6208, - 0xA4E1, 0x6236, 0xA4E2, 0x624B, 0xA4E3, 0x624E, 0xA4E4, 0x652F, - 0xA4E5, 0x6587, 0xA4E6, 0x6597, 0xA4E7, 0x65A4, 0xA4E8, 0x65B9, - 0xA4E9, 0x65E5, 0xA4EA, 0x66F0, 0xA4EB, 0x6708, 0xA4EC, 0x6728, - 0xA4ED, 0x6B20, 0xA4EE, 0x6B62, 0xA4EF, 0x6B79, 0xA4F0, 0x6BCB, - 0xA4F1, 0x6BD4, 0xA4F2, 0x6BDB, 0xA4F3, 0x6C0F, 0xA4F4, 0x6C34, - 0xA4F5, 0x706B, 0xA4F6, 0x722A, 0xA4F7, 0x7236, 0xA4F8, 0x723B, - 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0xF86B, 0x9DE6, 0xF86C, 0x9DF2, 0xF86D, 0x9DF0, 0xF86E, 0x9DE2, - 0xF86F, 0x9DEC, 0xF870, 0x9DF4, 0xF871, 0x9DF3, 0xF872, 0x9DE8, - 0xF873, 0x9DED, 0xF874, 0x9EC2, 0xF875, 0x9ED0, 0xF876, 0x9EF2, - 0xF877, 0x9EF3, 0xF878, 0x9F06, 0xF879, 0x9F1C, 0xF87A, 0x9F38, - 0xF87B, 0x9F37, 0xF87C, 0x9F36, 0xF87D, 0x9F43, 0xF87E, 0x9F4F, - 0xF8A1, 0x9F71, 0xF8A2, 0x9F70, 0xF8A3, 0x9F6E, 0xF8A4, 0x9F6F, - 0xF8A5, 0x56D3, 0xF8A6, 0x56CD, 0xF8A7, 0x5B4E, 0xF8A8, 0x5C6D, - 0xF8A9, 0x652D, 0xF8AA, 0x66ED, 0xF8AB, 0x66EE, 0xF8AC, 0x6B13, - 0xF8AD, 0x705F, 0xF8AE, 0x7061, 0xF8AF, 0x705D, 0xF8B0, 0x7060, - 0xF8B1, 0x7223, 0xF8B2, 0x74DB, 0xF8B3, 0x74E5, 0xF8B4, 0x77D5, - 0xF8B5, 0x7938, 0xF8B6, 0x79B7, 0xF8B7, 0x79B6, 0xF8B8, 0x7C6A, - 0xF8B9, 0x7E97, 0xF8BA, 0x7F89, 0xF8BB, 0x826D, 0xF8BC, 0x8643, - 0xF8BD, 0x8838, 0xF8BE, 0x8837, 0xF8BF, 0x8835, 0xF8C0, 0x884B, - 0xF8C1, 0x8B94, 0xF8C2, 0x8B95, 0xF8C3, 0x8E9E, 0xF8C4, 0x8E9F, - 0xF8C5, 0x8EA0, 0xF8C6, 0x8E9D, 0xF8C7, 0x91BE, 0xF8C8, 0x91BD, - 0xF8C9, 0x91C2, 0xF8CA, 0x946B, 0xF8CB, 0x9468, 0xF8CC, 0x9469, - 0xF8CD, 0x96E5, 0xF8CE, 0x9746, 0xF8CF, 0x9743, 0xF8D0, 0x9747, - 0xF8D1, 0x97C7, 0xF8D2, 0x97E5, 0xF8D3, 0x9A5E, 0xF8D4, 0x9AD5, - 0xF8D5, 0x9B59, 0xF8D6, 0x9C63, 0xF8D7, 0x9C67, 0xF8D8, 0x9C66, - 0xF8D9, 0x9C62, 0xF8DA, 0x9C5E, 0xF8DB, 0x9C60, 0xF8DC, 0x9E02, - 0xF8DD, 0x9DFE, 0xF8DE, 0x9E07, 0xF8DF, 0x9E03, 0xF8E0, 0x9E06, - 0xF8E1, 0x9E05, 0xF8E2, 0x9E00, 0xF8E3, 0x9E01, 0xF8E4, 0x9E09, - 0xF8E5, 0x9DFF, 0xF8E6, 0x9DFD, 0xF8E7, 0x9E04, 0xF8E8, 0x9EA0, - 0xF8E9, 0x9F1E, 0xF8EA, 0x9F46, 0xF8EB, 0x9F74, 0xF8EC, 0x9F75, - 0xF8ED, 0x9F76, 0xF8EE, 0x56D4, 0xF8EF, 0x652E, 0xF8F0, 0x65B8, - 0xF8F1, 0x6B18, 0xF8F2, 0x6B19, 0xF8F3, 0x6B17, 0xF8F4, 0x6B1A, - 0xF8F5, 0x7062, 0xF8F6, 0x7226, 0xF8F7, 0x72AA, 0xF8F8, 0x77D8, - 0xF8F9, 0x77D9, 0xF8FA, 0x7939, 0xF8FB, 0x7C69, 0xF8FC, 0x7C6B, - 0xF8FD, 0x7CF6, 0xF8FE, 0x7E9A, 0xF940, 0x7E98, 0xF941, 0x7E9B, - 0xF942, 0x7E99, 0xF943, 0x81E0, 0xF944, 0x81E1, 0xF945, 0x8646, - 0xF946, 0x8647, 0xF947, 0x8648, 0xF948, 0x8979, 0xF949, 0x897A, - 0xF94A, 0x897C, 0xF94B, 0x897B, 0xF94C, 0x89FF, 0xF94D, 0x8B98, - 0xF94E, 0x8B99, 0xF94F, 0x8EA5, 0xF950, 0x8EA4, 0xF951, 0x8EA3, - 0xF952, 0x946E, 0xF953, 0x946D, 0xF954, 0x946F, 0xF955, 0x9471, - 0xF956, 0x9473, 0xF957, 0x9749, 0xF958, 0x9872, 0xF959, 0x995F, - 0xF95A, 0x9C68, 0xF95B, 0x9C6E, 0xF95C, 0x9C6D, 0xF95D, 0x9E0B, - 0xF95E, 0x9E0D, 0xF95F, 0x9E10, 0xF960, 0x9E0F, 0xF961, 0x9E12, - 0xF962, 0x9E11, 0xF963, 0x9EA1, 0xF964, 0x9EF5, 0xF965, 0x9F09, - 0xF966, 0x9F47, 0xF967, 0x9F78, 0xF968, 0x9F7B, 0xF969, 0x9F7A, - 0xF96A, 0x9F79, 0xF96B, 0x571E, 0xF96C, 0x7066, 0xF96D, 0x7C6F, - 0xF96E, 0x883C, 0xF96F, 0x8DB2, 0xF970, 0x8EA6, 0xF971, 0x91C3, - 0xF972, 0x9474, 0xF973, 0x9478, 0xF974, 0x9476, 0xF975, 0x9475, - 0xF976, 0x9A60, 0xF977, 0x9C74, 0xF978, 0x9C73, 0xF979, 0x9C71, - 0xF97A, 0x9C75, 0xF97B, 0x9E14, 0xF97C, 0x9E13, 0xF97D, 0x9EF6, - 0xF97E, 0x9F0A, 0xF9A1, 0x9FA4, 0xF9A2, 0x7068, 0xF9A3, 0x7065, - 0xF9A4, 0x7CF7, 0xF9A5, 0x866A, 0xF9A6, 0x883E, 0xF9A7, 0x883D, - 0xF9A8, 0x883F, 0xF9A9, 0x8B9E, 0xF9AA, 0x8C9C, 0xF9AB, 0x8EA9, - 0xF9AC, 0x8EC9, 0xF9AD, 0x974B, 0xF9AE, 0x9873, 0xF9AF, 0x9874, - 0xF9B0, 0x98CC, 0xF9B1, 0x9961, 0xF9B2, 0x99AB, 0xF9B3, 0x9A64, - 0xF9B4, 0x9A66, 0xF9B5, 0x9A67, 0xF9B6, 0x9B24, 0xF9B7, 0x9E15, - 0xF9B8, 0x9E17, 0xF9B9, 0x9F48, 0xF9BA, 0x6207, 0xF9BB, 0x6B1E, - 0xF9BC, 0x7227, 0xF9BD, 0x864C, 0xF9BE, 0x8EA8, 0xF9BF, 0x9482, - 0xF9C0, 0x9480, 0xF9C1, 0x9481, 0xF9C2, 0x9A69, 0xF9C3, 0x9A68, - 0xF9C4, 0x9B2E, 0xF9C5, 0x9E19, 0xF9C6, 0x7229, 0xF9C7, 0x864B, - 0xF9C8, 0x8B9F, 0xF9C9, 0x9483, 0xF9CA, 0x9C79, 0xF9CB, 0x9EB7, - 0xF9CC, 0x7675, 0xF9CD, 0x9A6B, 0xF9CE, 0x9C7A, 0xF9CF, 0x9E1D, - 0xF9D0, 0x7069, 0xF9D1, 0x706A, 0xF9D2, 0x9EA4, 0xF9D3, 0x9F7E, - 0xF9D4, 0x9F49, 0xF9D5, 0x9F98, 0xF9D6, 0x7881, 0xF9D7, 0x92B9, - 0xF9D8, 0x88CF, 0xF9D9, 0x58BB, 0xF9DA, 0x6052, 0xF9DB, 0x7CA7, - 0xF9DC, 0x5AFA, 0xF9DD, 0x2554, 0xF9DE, 0x2566, 0xF9DF, 0x2557, - 0xF9E0, 0x2560, 0xF9E1, 0x256C, 0xF9E2, 0x2563, 0xF9E3, 0x255A, - 0xF9E4, 0x2569, 0xF9E5, 0x255D, 0xF9E6, 0x2552, 0xF9E7, 0x2564, - 0xF9E8, 0x2555, 0xF9E9, 0x255E, 0xF9EA, 0x256A, 0xF9EB, 0x2561, - 0xF9EC, 0x2558, 0xF9ED, 0x2567, 0xF9EE, 0x255B, 0xF9EF, 0x2553, - 0xF9F0, 0x2565, 0xF9F1, 0x2556, 0xF9F2, 0x255F, 0xF9F3, 0x256B, - 0xF9F4, 0x2562, 0xF9F5, 0x2559, 0xF9F6, 0x2568, 0xF9F7, 0x255C, - 0xF9F8, 0x2551, 0xF9F9, 0x2550, 0xF9FA, 0x256D, 0xF9FB, 0x256E, - 0xF9FC, 0x2570, 0xF9FD, 0x256F, 0xF9FE, 0x2593, 0, 0 -}; - - - -WCHAR ff_convert ( /* Converted code, 0 means conversion error */ - WCHAR chr, /* Character code to be converted */ - UINT dir /* 0: Unicode to OEM code, 1: OEM code to Unicode */ -) -{ - const WCHAR *p; - WCHAR c; - int i, n, li, hi; - - - if (chr < 0x80) { /* ASCII */ - c = chr; - } else { - if (dir) { /* OEM code to unicode */ - p = oem2uni; - hi = sizeof oem2uni / 4 - 1; - } else { /* Unicode to OEM code */ - p = uni2oem; - hi = sizeof uni2oem / 4 - 1; - } - li = 0; - for (n = 16; n; n--) { - i = li + (hi - li) / 2; - if (chr == p[i * 2]) break; - if (chr > p[i * 2]) - li = i; - else - hi = i; - } - c = n ? p[i * 2 + 1] : 0; - } - - return c; -} - - - -WCHAR ff_wtoupper ( /* Returns upper converted character */ - WCHAR chr /* Unicode character to be upper converted (BMP only) */ -) -{ - /* Compressed upper conversion table */ - static const WCHAR cvt1[] = { /* U+0000 - U+0FFF */ - /* Basic Latin */ - 0x0061,0x031A, - /* Latin-1 Supplement */ - 0x00E0,0x0317, 0x00F8,0x0307, 0x00FF,0x0001,0x0178, - /* Latin Extended-A */ - 0x0100,0x0130, 0x0132,0x0106, 0x0139,0x0110, 0x014A,0x012E, 0x0179,0x0106, - /* Latin Extended-B */ - 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, - 0x01CD,0x0110, 0x01DD,0x0001,0x018E, 0x01DE,0x0112, 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, 0x01F8,0x0128, - 0x0222,0x0112, 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, 0x0246,0x010A, - /* IPA Extensions */ - 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, - /* Greek, Coptic */ - 0x037B,0x0003,0x03FD,0x03FE,0x03FF, 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, 0x03B1,0x0311, - 0x03C2,0x0002,0x03A3,0x03A3, 0x03C4,0x0308, 0x03CC,0x0003,0x038C,0x038E,0x038F, 0x03D8,0x0118, - 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, - /* Cyrillic */ - 0x0430,0x0320, 0x0450,0x0710, 0x0460,0x0122, 0x048A,0x0136, 0x04C1,0x010E, 0x04CF,0x0001,0x04C0, 0x04D0,0x0144, - /* Armenian */ - 0x0561,0x0426, - - 0x0000 - }; - static const WCHAR cvt2[] = { /* U+1000 - U+FFFF */ - /* Phonetic Extensions */ - 0x1D7D,0x0001,0x2C63, - /* Latin Extended Additional */ - 0x1E00,0x0196, 0x1EA0,0x015A, - /* Greek Extended */ - 0x1F00,0x0608, 0x1F10,0x0606, 0x1F20,0x0608, 0x1F30,0x0608, 0x1F40,0x0606, - 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, 0x1F60,0x0608, - 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, - 0x1F80,0x0608, 0x1F90,0x0608, 0x1FA0,0x0608, 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, - 0x1FCC,0x0001,0x1FC3, 0x1FD0,0x0602, 0x1FE0,0x0602, 0x1FE5,0x0001,0x1FEC, 0x1FF2,0x0001,0x1FFC, - /* Letterlike Symbols */ - 0x214E,0x0001,0x2132, - /* Number forms */ - 0x2170,0x0210, 0x2184,0x0001,0x2183, - /* Enclosed Alphanumerics */ - 0x24D0,0x051A, 0x2C30,0x042F, - /* Latin Extended-C */ - 0x2C60,0x0102, 0x2C67,0x0106, 0x2C75,0x0102, - /* Coptic */ - 0x2C80,0x0164, - /* Georgian Supplement */ - 0x2D00,0x0826, - /* Full-width */ - 0xFF41,0x031A, - - 0x0000 - }; - const WCHAR *p; - WCHAR bc, nc, cmd; - - - p = chr < 0x1000 ? cvt1 : cvt2; - for (;;) { - bc = *p++; /* Get block base */ - if (!bc || chr < bc) break; - nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ - if (chr < bc + nc) { /* In the block? */ - switch (cmd) { - case 0: chr = p[chr - bc]; break; /* Table conversion */ - case 1: chr -= (chr - bc) & 1; break; /* Case pairs */ - case 2: chr -= 16; break; /* Shift -16 */ - case 3: chr -= 32; break; /* Shift -32 */ - case 4: chr -= 48; break; /* Shift -48 */ - case 5: chr -= 26; break; /* Shift -26 */ - case 6: chr += 8; break; /* Shift +8 */ - case 7: chr -= 80; break; /* Shift -80 */ - case 8: chr -= 0x1C60; break; /* Shift -0x1C60 */ - } - break; - } - if (!cmd) p += nc; - } - - return chr; -} - +/*------------------------------------------------------------------------*/ +/* Unicode - OEM code bidirectional converter (C)ChaN, 2015 */ +/* CP950 (Traditional Chinese Big5) */ +/*------------------------------------------------------------------------*/ + +#include "../ff.h" + + +#if !_USE_LFN || _CODE_PAGE != 950 +#error This file is not needed in current configuration. Remove from the project. +#endif + + +static +const WCHAR uni2oem[] = { +/* Unicode - OEM, Unicode - OEM, Unicode - OEM, Unicode - OEM */ + 0x00A7, 0xA1B1, 0x00AF, 0xA1C2, 0x00B0, 0xA258, 0x00B1, 0xA1D3, + 0x00B7, 0xA150, 0x00D7, 0xA1D1, 0x00F7, 0xA1D2, 0x02C7, 0xA3BE, + 0x02C9, 0xA3BC, 0x02CA, 0xA3BD, 0x02CB, 0xA3BF, 0x02CD, 0xA1C5, + 0x02D9, 0xA3BB, 0x0391, 0xA344, 0x0392, 0xA345, 0x0393, 0xA346, + 0x0394, 0xA347, 0x0395, 0xA348, 0x0396, 0xA349, 0x0397, 0xA34A, + 0x0398, 0xA34B, 0x0399, 0xA34C, 0x039A, 0xA34D, 0x039B, 0xA34E, + 0x039C, 0xA34F, 0x039D, 0xA350, 0x039E, 0xA351, 0x039F, 0xA352, + 0x03A0, 0xA353, 0x03A1, 0xA354, 0x03A3, 0xA355, 0x03A4, 0xA356, + 0x03A5, 0xA357, 0x03A6, 0xA358, 0x03A7, 0xA359, 0x03A8, 0xA35A, + 0x03A9, 0xA35B, 0x03B1, 0xA35C, 0x03B2, 0xA35D, 0x03B3, 0xA35E, + 0x03B4, 0xA35F, 0x03B5, 0xA360, 0x03B6, 0xA361, 0x03B7, 0xA362, + 0x03B8, 0xA363, 0x03B9, 0xA364, 0x03BA, 0xA365, 0x03BB, 0xA366, + 0x03BC, 0xA367, 0x03BD, 0xA368, 0x03BE, 0xA369, 0x03BF, 0xA36A, + 0x03C0, 0xA36B, 0x03C1, 0xA36C, 0x03C3, 0xA36D, 0x03C4, 0xA36E, + 0x03C5, 0xA36F, 0x03C6, 0xA370, 0x03C7, 0xA371, 0x03C8, 0xA372, + 0x03C9, 0xA373, 0x2013, 0xA156, 0x2014, 0xA158, 0x2018, 0xA1A5, + 0x2019, 0xA1A6, 0x201C, 0xA1A7, 0x201D, 0xA1A8, 0x2025, 0xA14C, + 0x2026, 0xA14B, 0x2027, 0xA145, 0x2032, 0xA1AC, 0x2035, 0xA1AB, + 0x203B, 0xA1B0, 0x20AC, 0xA3E1, 0x2103, 0xA24A, 0x2105, 0xA1C1, + 0x2109, 0xA24B, 0x2160, 0xA2B9, 0x2161, 0xA2BA, 0x2162, 0xA2BB, + 0x2163, 0xA2BC, 0x2164, 0xA2BD, 0x2165, 0xA2BE, 0x2166, 0xA2BF, + 0x2167, 0xA2C0, 0x2168, 0xA2C1, 0x2169, 0xA2C2, 0x2190, 0xA1F6, + 0x2191, 0xA1F4, 0x2192, 0xA1F7, 0x2193, 0xA1F5, 0x2196, 0xA1F8, + 0x2197, 0xA1F9, 0x2198, 0xA1FB, 0x2199, 0xA1FA, 0x2215, 0xA241, + 0x221A, 0xA1D4, 0x221E, 0xA1DB, 0x221F, 0xA1E8, 0x2220, 0xA1E7, + 0x2223, 0xA1FD, 0x2225, 0xA1FC, 0x2229, 0xA1E4, 0x222A, 0xA1E5, + 0x222B, 0xA1EC, 0x222E, 0xA1ED, 0x2234, 0xA1EF, 0x2235, 0xA1EE, + 0x2252, 0xA1DC, 0x2260, 0xA1DA, 0x2261, 0xA1DD, 0x2266, 0xA1D8, + 0x2267, 0xA1D9, 0x2295, 0xA1F2, 0x2299, 0xA1F3, 0x22A5, 0xA1E6, + 0x22BF, 0xA1E9, 0x2500, 0xA277, 0x2502, 0xA278, 0x250C, 0xA27A, + 0x2510, 0xA27B, 0x2514, 0xA27C, 0x2518, 0xA27D, 0x251C, 0xA275, + 0x2524, 0xA274, 0x252C, 0xA273, 0x2534, 0xA272, 0x253C, 0xA271, + 0x2550, 0xA2A4, 0x2550, 0xF9F9, 0x2551, 0xF9F8, 0x2552, 0xF9E6, + 0x2553, 0xF9EF, 0x2554, 0xF9DD, 0x2555, 0xF9E8, 0x2556, 0xF9F1, + 0x2557, 0xF9DF, 0x2558, 0xF9EC, 0x2559, 0xF9F5, 0x255A, 0xF9E3, + 0x255B, 0xF9EE, 0x255C, 0xF9F7, 0x255D, 0xF9E5, 0x255E, 0xA2A5, + 0x255E, 0xF9E9, 0x255F, 0xF9F2, 0x2560, 0xF9E0, 0x2561, 0xA2A7, + 0x2561, 0xF9EB, 0x2562, 0xF9F4, 0x2563, 0xF9E2, 0x2564, 0xF9E7, + 0x2565, 0xF9F0, 0x2566, 0xF9DE, 0x2567, 0xF9ED, 0x2568, 0xF9F6, + 0x2569, 0xF9E4, 0x256A, 0xA2A6, 0x256A, 0xF9EA, 0x256B, 0xF9F3, + 0x256C, 0xF9E1, 0x256D, 0xA27E, 0x256D, 0xF9FA, 0x256E, 0xA2A1, + 0x256E, 0xF9FB, 0x256F, 0xA2A3, 0x256F, 0xF9FD, 0x2570, 0xA2A2, + 0x2570, 0xF9FC, 0x2571, 0xA2AC, 0x2572, 0xA2AD, 0x2573, 0xA2AE, + 0x2574, 0xA15A, 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0xE4E2, 0x9CF2, 0xE4E3, + 0x9CF3, 0xBBF1, 0x9CF4, 0xBBEF, 0x9CF5, 0xE4E4, 0x9CF6, 0xBBF0, + 0x9CF7, 0xE8E8, 0x9CF9, 0xE8EB, 0x9CFA, 0xE8E5, 0x9CFB, 0xE8EC, + 0x9CFC, 0xE8E4, 0x9CFD, 0xE8E6, 0x9CFF, 0xE8E7, 0x9D00, 0xE8EA, + 0x9D03, 0xBEA1, 0x9D04, 0xE8EF, 0x9D05, 0xE8EE, 0x9D06, 0xBE7D, + 0x9D07, 0xE8E9, 0x9D08, 0xE8ED, 0x9D09, 0xBE7E, 0x9D10, 0xECAC, + 0x9D12, 0xC06F, 0x9D14, 0xECA7, 0x9D15, 0xC06B, 0x9D17, 0xECA4, + 0x9D18, 0xECAA, 0x9D19, 0xECAD, 0x9D1B, 0xC070, 0x9D1D, 0xECA9, + 0x9D1E, 0xECA6, 0x9D1F, 0xECAE, 0x9D20, 0xECA5, 0x9D22, 0xECAB, + 0x9D23, 0xC06C, 0x9D25, 0xECA3, 0x9D26, 0xC06D, 0x9D28, 0xC06E, + 0x9D29, 0xECA8, 0x9D2D, 0xEFA9, 0x9D2E, 0xEF7A, 0x9D2F, 0xEF7B, + 0x9D30, 0xEF7E, 0x9D31, 0xEF7C, 0x9D33, 0xEF76, 0x9D36, 0xEF79, + 0x9D37, 0xEFA5, 0x9D38, 0xEF7D, 0x9D3B, 0xC245, 0x9D3D, 0xEFA7, + 0x9D3E, 0xEFA4, 0x9D3F, 0xC246, 0x9D40, 0xEFA6, 0x9D41, 0xEF77, + 0x9D42, 0xEFA2, 0x9D43, 0xEFA3, 0x9D45, 0xEFA1, 0x9D4A, 0xF1D2, + 0x9D4B, 0xF1D4, 0x9D4C, 0xF1D7, 0x9D4F, 0xF1D1, 0x9D51, 0xC359, + 0x9D52, 0xF1D9, 0x9D53, 0xF1D0, 0x9D54, 0xF1DA, 0x9D56, 0xF1D6, + 0x9D57, 0xF1D8, 0x9D58, 0xF1DC, 0x9D59, 0xF1D5, 0x9D5A, 0xF1DD, + 0x9D5B, 0xF1D3, 0x9D5C, 0xF1CF, 0x9D5D, 0xC35A, 0x9D5F, 0xF1DB, + 0x9D60, 0xC35B, 0x9D61, 0xC44D, 0x9D67, 0xEF78, 0x9D68, 0xF3F1, + 0x9D69, 0xF3E8, 0x9D6A, 0xC44F, 0x9D6B, 0xF3E4, 0x9D6C, 0xC450, + 0x9D6F, 0xF3ED, 0x9D70, 0xF3E7, 0x9D71, 0xF3DD, 0x9D72, 0xC44E, + 0x9D73, 0xF3EA, 0x9D74, 0xF3E5, 0x9D75, 0xF3E6, 0x9D77, 0xF3D8, + 0x9D78, 0xF3DF, 0x9D79, 0xF3EE, 0x9D7B, 0xF3EB, 0x9D7D, 0xF3E3, + 0x9D7F, 0xF3EF, 0x9D80, 0xF3DE, 0x9D81, 0xF3D9, 0x9D82, 0xF3EC, + 0x9D84, 0xF3DB, 0x9D85, 0xF3E9, 0x9D86, 0xF3E0, 0x9D87, 0xF3F0, + 0x9D88, 0xF3DC, 0x9D89, 0xC44C, 0x9D8A, 0xF3DA, 0x9D8B, 0xF3E1, + 0x9D8C, 0xF3E2, 0x9D90, 0xF57D, 0x9D92, 0xF57B, 0x9D94, 0xF5A2, + 0x9D96, 0xF5AE, 0x9D97, 0xF5A5, 0x9D98, 0xF57C, 0x9D99, 0xF578, + 0x9D9A, 0xF5A7, 0x9D9B, 0xF57E, 0x9D9C, 0xF5A3, 0x9D9D, 0xF57A, + 0x9D9E, 0xF5AA, 0x9D9F, 0xF577, 0x9DA0, 0xF5A1, 0x9DA1, 0xF5A6, + 0x9DA2, 0xF5A8, 0x9DA3, 0xF5AB, 0x9DA4, 0xF579, 0x9DA6, 0xF5AF, + 0x9DA7, 0xF5B0, 0x9DA8, 0xF5A9, 0x9DA9, 0xF5AD, 0x9DAA, 0xF5A4, + 0x9DAC, 0xF6C1, 0x9DAD, 0xF6C4, 0x9DAF, 0xC561, 0x9DB1, 0xF6C3, + 0x9DB2, 0xF6C8, 0x9DB3, 0xF6C6, 0x9DB4, 0xC562, 0x9DB5, 0xF6BD, + 0x9DB6, 0xF6B3, 0x9DB7, 0xF6B2, 0x9DB8, 0xC564, 0x9DB9, 0xF6BF, + 0x9DBA, 0xF6C0, 0x9DBB, 0xF6BC, 0x9DBC, 0xF6B4, 0x9DBE, 0xF6B9, + 0x9DBF, 0xF5AC, 0x9DC1, 0xF6B5, 0x9DC2, 0xC563, 0x9DC3, 0xF6BB, + 0x9DC5, 0xF6BA, 0x9DC7, 0xF6B6, 0x9DC8, 0xF6C2, 0x9DCA, 0xF6B7, + 0x9DCB, 0xF7BB, 0x9DCC, 0xF6C5, 0x9DCD, 0xF6C7, 0x9DCE, 0xF6BE, + 0x9DCF, 0xF6B8, 0x9DD0, 0xF7BC, 0x9DD1, 0xF7BE, 0x9DD2, 0xF7B8, + 0x9DD3, 0xC5C2, 0x9DD5, 0xF7C5, 0x9DD6, 0xF7C3, 0x9DD7, 0xC5C3, + 0x9DD8, 0xF7C2, 0x9DD9, 0xF7C1, 0x9DDA, 0xF7BA, 0x9DDB, 0xF7B7, + 0x9DDC, 0xF7BD, 0x9DDD, 0xF7C6, 0x9DDE, 0xF7B9, 0x9DDF, 0xF7BF, + 0x9DE1, 0xF869, 0x9DE2, 0xF86E, 0x9DE3, 0xF864, 0x9DE4, 0xF867, + 0x9DE5, 0xC5EE, 0x9DE6, 0xF86B, 0x9DE8, 0xF872, 0x9DE9, 0xF7C0, + 0x9DEB, 0xF865, 0x9DEC, 0xF86F, 0x9DED, 0xF873, 0x9DEE, 0xF86A, + 0x9DEF, 0xF863, 0x9DF0, 0xF86D, 0x9DF2, 0xF86C, 0x9DF3, 0xF871, + 0x9DF4, 0xF870, 0x9DF5, 0xF7C4, 0x9DF6, 0xF868, 0x9DF7, 0xF862, + 0x9DF8, 0xF866, 0x9DF9, 0xC64E, 0x9DFA, 0xC64F, 0x9DFB, 0xF861, + 0x9DFD, 0xF8E6, 0x9DFE, 0xF8DD, 0x9DFF, 0xF8E5, 0x9E00, 0xF8E2, + 0x9E01, 0xF8E3, 0x9E02, 0xF8DC, 0x9E03, 0xF8DF, 0x9E04, 0xF8E7, + 0x9E05, 0xF8E1, 0x9E06, 0xF8E0, 0x9E07, 0xF8DE, 0x9E09, 0xF8E4, + 0x9E0B, 0xF95D, 0x9E0D, 0xF95E, 0x9E0F, 0xF960, 0x9E10, 0xF95F, + 0x9E11, 0xF962, 0x9E12, 0xF961, 0x9E13, 0xF97C, 0x9E14, 0xF97B, + 0x9E15, 0xF9B7, 0x9E17, 0xF9B8, 0x9E19, 0xF9C5, 0x9E1A, 0xC678, + 0x9E1B, 0xC67C, 0x9E1D, 0xF9CF, 0x9E1E, 0xC67D, 0x9E75, 0xB3BF, + 0x9E79, 0xC4D0, 0x9E7A, 0xF6C9, 0x9E7C, 0xC650, 0x9E7D, 0xC651, + 0x9E7F, 0xB3C0, 0x9E80, 0xE0EE, 0x9E82, 0xB9A8, 0x9E83, 0xE8F0, + 0x9E86, 0xECB0, 0x9E87, 0xECB1, 0x9E88, 0xECAF, 0x9E89, 0xEFAB, + 0x9E8A, 0xEFAA, 0x9E8B, 0xC247, 0x9E8C, 0xF1DF, 0x9E8D, 0xEFAC, + 0x9E8E, 0xF1DE, 0x9E91, 0xF3F3, 0x9E92, 0xC451, 0x9E93, 0xC453, + 0x9E94, 0xF3F2, 0x9E97, 0xC452, 0x9E99, 0xF5B1, 0x9E9A, 0xF5B3, + 0x9E9B, 0xF5B2, 0x9E9C, 0xF6CA, 0x9E9D, 0xC565, 0x9E9F, 0xC5EF, + 0x9EA0, 0xF8E8, 0x9EA1, 0xF963, 0x9EA4, 0xF9D2, 0x9EA5, 0xB3C1, + 0x9EA7, 0xE4E5, 0x9EA9, 0xBEA2, 0x9EAD, 0xECB3, 0x9EAE, 0xECB2, + 0x9EB0, 0xEFAD, 0x9EB4, 0xC454, 0x9EB5, 0xC4D1, 0x9EB6, 0xF7C7, + 0x9EB7, 0xF9CB, 0x9EBB, 0xB3C2, 0x9EBC, 0xBBF2, 0x9EBE, 0xBEA3, + 0x9EC0, 0xF3F4, 0x9EC2, 0xF874, 0x9EC3, 0xB6C0, 0x9EC8, 0xEFAE, + 0x9ECC, 0xC664, 0x9ECD, 0xB6C1, 0x9ECE, 0xBEA4, 0x9ECF, 0xC248, + 0x9ED0, 0xF875, 0x9ED1, 0xB6C2, 0x9ED3, 0xE8F1, 0x9ED4, 0xC072, + 0x9ED5, 0xECB4, 0x9ED6, 0xECB5, 0x9ED8, 0xC071, 0x9EDA, 0xEFAF, + 0x9EDB, 0xC24C, 0x9EDC, 0xC24A, 0x9EDD, 0xC24B, 0x9EDE, 0xC249, + 0x9EDF, 0xF1E0, 0x9EE0, 0xC35C, 0x9EE4, 0xF5B5, 0x9EE5, 0xF5B4, + 0x9EE6, 0xF5B7, 0x9EE7, 0xF5B6, 0x9EE8, 0xC4D2, 0x9EEB, 0xF6CB, + 0x9EED, 0xF6CD, 0x9EEE, 0xF6CC, 0x9EEF, 0xC566, 0x9EF0, 0xF7C8, + 0x9EF2, 0xF876, 0x9EF3, 0xF877, 0x9EF4, 0xC5F0, 0x9EF5, 0xF964, + 0x9EF6, 0xF97D, 0x9EF7, 0xC675, 0x9EF9, 0xDCB0, 0x9EFA, 0xECB6, + 0x9EFB, 0xEFB0, 0x9EFC, 0xF3F5, 0x9EFD, 0xE0EF, 0x9EFF, 0xEFB1, + 0x9F00, 0xF1E2, 0x9F01, 0xF1E1, 0x9F06, 0xF878, 0x9F07, 0xC652, + 0x9F09, 0xF965, 0x9F0A, 0xF97E, 0x9F0E, 0xB9A9, 0x9F0F, 0xE8F2, + 0x9F10, 0xE8F3, 0x9F12, 0xECB7, 0x9F13, 0xB9AA, 0x9F15, 0xC35D, + 0x9F16, 0xF1E3, 0x9F18, 0xF6CF, 0x9F19, 0xC567, 0x9F1A, 0xF6D0, + 0x9F1B, 0xF6CE, 0x9F1C, 0xF879, 0x9F1E, 0xF8E9, 0x9F20, 0xB9AB, + 0x9F22, 0xEFB4, 0x9F23, 0xEFB3, 0x9F24, 0xEFB2, 0x9F25, 0xF1E4, + 0x9F28, 0xF1E8, 0x9F29, 0xF1E7, 0x9F2A, 0xF1E6, 0x9F2B, 0xF1E5, + 0x9F2C, 0xC35E, 0x9F2D, 0xF3F6, 0x9F2E, 0xF5B9, 0x9F2F, 0xC4D3, + 0x9F30, 0xF5B8, 0x9F31, 0xF6D1, 0x9F32, 0xF7CB, 0x9F33, 0xF7CA, + 0x9F34, 0xC5C4, 0x9F35, 0xF7C9, 0x9F36, 0xF87C, 0x9F37, 0xF87B, + 0x9F38, 0xF87A, 0x9F3B, 0xBBF3, 0x9F3D, 0xECB8, 0x9F3E, 0xC24D, + 0x9F40, 0xF3F7, 0x9F41, 0xF3F8, 0x9F42, 0xF7CC, 0x9F43, 0xF87D, + 0x9F46, 0xF8EA, 0x9F47, 0xF966, 0x9F48, 0xF9B9, 0x9F49, 0xF9D4, + 0x9F4A, 0xBBF4, 0x9F4B, 0xC24E, 0x9F4C, 0xF1E9, 0x9F4D, 0xF3F9, + 0x9F4E, 0xF6D2, 0x9F4F, 0xF87E, 0x9F52, 0xBEA6, 0x9F54, 0xEFB5, + 0x9F55, 0xF1EA, 0x9F56, 0xF3FA, 0x9F57, 0xF3FB, 0x9F58, 0xF3FC, + 0x9F59, 0xF5BE, 0x9F5B, 0xF5BA, 0x9F5C, 0xC568, 0x9F5D, 0xF5BD, + 0x9F5E, 0xF5BC, 0x9F5F, 0xC4D4, 0x9F60, 0xF5BB, 0x9F61, 0xC4D6, + 0x9F63, 0xC4D5, 0x9F64, 0xF6D4, 0x9F65, 0xF6D3, 0x9F66, 0xC569, + 0x9F67, 0xC56A, 0x9F6A, 0xC5C6, 0x9F6B, 0xF7CD, 0x9F6C, 0xC5C5, + 0x9F6E, 0xF8A3, 0x9F6F, 0xF8A4, 0x9F70, 0xF8A2, 0x9F71, 0xF8A1, + 0x9F72, 0xC654, 0x9F74, 0xF8EB, 0x9F75, 0xF8EC, 0x9F76, 0xF8ED, + 0x9F77, 0xC653, 0x9F78, 0xF967, 0x9F79, 0xF96A, 0x9F7A, 0xF969, + 0x9F7B, 0xF968, 0x9F7E, 0xF9D3, 0x9F8D, 0xC073, 0x9F90, 0xC365, + 0x9F91, 0xF5BF, 0x9F92, 0xF6D5, 0x9F94, 0xC5C7, 0x9F95, 0xF7CE, + 0x9F98, 0xF9D5, 0x9F9C, 0xC074, 0x9FA0, 0xEFB6, 0x9FA2, 0xF7CF, + 0x9FA4, 0xF9A1, 0xFA0C, 0xC94A, 0xFA0D, 0xDDFC, 0xFE30, 0xA14A, + 0xFE31, 0xA157, 0xFE33, 0xA159, 0xFE34, 0xA15B, 0xFE35, 0xA15F, + 0xFE36, 0xA160, 0xFE37, 0xA163, 0xFE38, 0xA164, 0xFE39, 0xA167, + 0xFE3A, 0xA168, 0xFE3B, 0xA16B, 0xFE3C, 0xA16C, 0xFE3D, 0xA16F, + 0xFE3E, 0xA170, 0xFE3F, 0xA173, 0xFE40, 0xA174, 0xFE41, 0xA177, + 0xFE42, 0xA178, 0xFE43, 0xA17B, 0xFE44, 0xA17C, 0xFE49, 0xA1C6, + 0xFE4A, 0xA1C7, 0xFE4B, 0xA1CA, 0xFE4C, 0xA1CB, 0xFE4D, 0xA1C8, + 0xFE4E, 0xA1C9, 0xFE4F, 0xA15C, 0xFE50, 0xA14D, 0xFE51, 0xA14E, + 0xFE52, 0xA14F, 0xFE54, 0xA151, 0xFE55, 0xA152, 0xFE56, 0xA153, + 0xFE57, 0xA154, 0xFE59, 0xA17D, 0xFE5A, 0xA17E, 0xFE5B, 0xA1A1, + 0xFE5C, 0xA1A2, 0xFE5D, 0xA1A3, 0xFE5E, 0xA1A4, 0xFE5F, 0xA1CC, + 0xFE60, 0xA1CD, 0xFE61, 0xA1CE, 0xFE62, 0xA1DE, 0xFE63, 0xA1DF, + 0xFE64, 0xA1E0, 0xFE65, 0xA1E1, 0xFE66, 0xA1E2, 0xFE68, 0xA242, + 0xFE69, 0xA24C, 0xFE6A, 0xA24D, 0xFE6B, 0xA24E, 0xFF01, 0xA149, + 0xFF03, 0xA1AD, 0xFF04, 0xA243, 0xFF05, 0xA248, 0xFF06, 0xA1AE, + 0xFF08, 0xA15D, 0xFF09, 0xA15E, 0xFF0A, 0xA1AF, 0xFF0B, 0xA1CF, + 0xFF0C, 0xA141, 0xFF0D, 0xA1D0, 0xFF0E, 0xA144, 0xFF0F, 0xA1FE, + 0xFF10, 0xA2AF, 0xFF11, 0xA2B0, 0xFF12, 0xA2B1, 0xFF13, 0xA2B2, + 0xFF14, 0xA2B3, 0xFF15, 0xA2B4, 0xFF16, 0xA2B5, 0xFF17, 0xA2B6, + 0xFF18, 0xA2B7, 0xFF19, 0xA2B8, 0xFF1A, 0xA147, 0xFF1B, 0xA146, + 0xFF1C, 0xA1D5, 0xFF1D, 0xA1D7, 0xFF1E, 0xA1D6, 0xFF1F, 0xA148, + 0xFF20, 0xA249, 0xFF21, 0xA2CF, 0xFF22, 0xA2D0, 0xFF23, 0xA2D1, + 0xFF24, 0xA2D2, 0xFF25, 0xA2D3, 0xFF26, 0xA2D4, 0xFF27, 0xA2D5, + 0xFF28, 0xA2D6, 0xFF29, 0xA2D7, 0xFF2A, 0xA2D8, 0xFF2B, 0xA2D9, + 0xFF2C, 0xA2DA, 0xFF2D, 0xA2DB, 0xFF2E, 0xA2DC, 0xFF2F, 0xA2DD, + 0xFF30, 0xA2DE, 0xFF31, 0xA2DF, 0xFF32, 0xA2E0, 0xFF33, 0xA2E1, + 0xFF34, 0xA2E2, 0xFF35, 0xA2E3, 0xFF36, 0xA2E4, 0xFF37, 0xA2E5, + 0xFF38, 0xA2E6, 0xFF39, 0xA2E7, 0xFF3A, 0xA2E8, 0xFF3C, 0xA240, + 0xFF3F, 0xA1C4, 0xFF41, 0xA2E9, 0xFF42, 0xA2EA, 0xFF43, 0xA2EB, + 0xFF44, 0xA2EC, 0xFF45, 0xA2ED, 0xFF46, 0xA2EE, 0xFF47, 0xA2EF, + 0xFF48, 0xA2F0, 0xFF49, 0xA2F1, 0xFF4A, 0xA2F2, 0xFF4B, 0xA2F3, + 0xFF4C, 0xA2F4, 0xFF4D, 0xA2F5, 0xFF4E, 0xA2F6, 0xFF4F, 0xA2F7, + 0xFF50, 0xA2F8, 0xFF51, 0xA2F9, 0xFF52, 0xA2FA, 0xFF53, 0xA2FB, + 0xFF54, 0xA2FC, 0xFF55, 0xA2FD, 0xFF56, 0xA2FE, 0xFF57, 0xA340, + 0xFF58, 0xA341, 0xFF59, 0xA342, 0xFF5A, 0xA343, 0xFF5B, 0xA161, + 0xFF5C, 0xA155, 0xFF5D, 0xA162, 0xFF5E, 0xA1E3, 0xFFE0, 0xA246, + 0xFFE1, 0xA247, 0xFFE3, 0xA1C3, 0xFFE5, 0xA244, 0, 0 +}; + +static +const WCHAR oem2uni[] = { +/* OEM - Unicode, OEM - Unicode, OEM - Unicode, OEM - Unicode */ + 0xA140, 0x3000, 0xA141, 0xFF0C, 0xA142, 0x3001, 0xA143, 0x3002, + 0xA144, 0xFF0E, 0xA145, 0x2027, 0xA146, 0xFF1B, 0xA147, 0xFF1A, + 0xA148, 0xFF1F, 0xA149, 0xFF01, 0xA14A, 0xFE30, 0xA14B, 0x2026, + 0xA14C, 0x2025, 0xA14D, 0xFE50, 0xA14E, 0xFE51, 0xA14F, 0xFE52, + 0xA150, 0x00B7, 0xA151, 0xFE54, 0xA152, 0xFE55, 0xA153, 0xFE56, + 0xA154, 0xFE57, 0xA155, 0xFF5C, 0xA156, 0x2013, 0xA157, 0xFE31, + 0xA158, 0x2014, 0xA159, 0xFE33, 0xA15A, 0x2574, 0xA15B, 0xFE34, + 0xA15C, 0xFE4F, 0xA15D, 0xFF08, 0xA15E, 0xFF09, 0xA15F, 0xFE35, + 0xA160, 0xFE36, 0xA161, 0xFF5B, 0xA162, 0xFF5D, 0xA163, 0xFE37, + 0xA164, 0xFE38, 0xA165, 0x3014, 0xA166, 0x3015, 0xA167, 0xFE39, + 0xA168, 0xFE3A, 0xA169, 0x3010, 0xA16A, 0x3011, 0xA16B, 0xFE3B, + 0xA16C, 0xFE3C, 0xA16D, 0x300A, 0xA16E, 0x300B, 0xA16F, 0xFE3D, + 0xA170, 0xFE3E, 0xA171, 0x3008, 0xA172, 0x3009, 0xA173, 0xFE3F, + 0xA174, 0xFE40, 0xA175, 0x300C, 0xA176, 0x300D, 0xA177, 0xFE41, + 0xA178, 0xFE42, 0xA179, 0x300E, 0xA17A, 0x300F, 0xA17B, 0xFE43, + 0xA17C, 0xFE44, 0xA17D, 0xFE59, 0xA17E, 0xFE5A, 0xA1A1, 0xFE5B, + 0xA1A2, 0xFE5C, 0xA1A3, 0xFE5D, 0xA1A4, 0xFE5E, 0xA1A5, 0x2018, + 0xA1A6, 0x2019, 0xA1A7, 0x201C, 0xA1A8, 0x201D, 0xA1A9, 0x301D, + 0xA1AA, 0x301E, 0xA1AB, 0x2035, 0xA1AC, 0x2032, 0xA1AD, 0xFF03, + 0xA1AE, 0xFF06, 0xA1AF, 0xFF0A, 0xA1B0, 0x203B, 0xA1B1, 0x00A7, + 0xA1B2, 0x3003, 0xA1B3, 0x25CB, 0xA1B4, 0x25CF, 0xA1B5, 0x25B3, + 0xA1B6, 0x25B2, 0xA1B7, 0x25CE, 0xA1B8, 0x2606, 0xA1B9, 0x2605, + 0xA1BA, 0x25C7, 0xA1BB, 0x25C6, 0xA1BC, 0x25A1, 0xA1BD, 0x25A0, + 0xA1BE, 0x25BD, 0xA1BF, 0x25BC, 0xA1C0, 0x32A3, 0xA1C1, 0x2105, + 0xA1C2, 0x00AF, 0xA1C3, 0xFFE3, 0xA1C4, 0xFF3F, 0xA1C5, 0x02CD, + 0xA1C6, 0xFE49, 0xA1C7, 0xFE4A, 0xA1C8, 0xFE4D, 0xA1C9, 0xFE4E, + 0xA1CA, 0xFE4B, 0xA1CB, 0xFE4C, 0xA1CC, 0xFE5F, 0xA1CD, 0xFE60, + 0xA1CE, 0xFE61, 0xA1CF, 0xFF0B, 0xA1D0, 0xFF0D, 0xA1D1, 0x00D7, + 0xA1D2, 0x00F7, 0xA1D3, 0x00B1, 0xA1D4, 0x221A, 0xA1D5, 0xFF1C, + 0xA1D6, 0xFF1E, 0xA1D7, 0xFF1D, 0xA1D8, 0x2266, 0xA1D9, 0x2267, + 0xA1DA, 0x2260, 0xA1DB, 0x221E, 0xA1DC, 0x2252, 0xA1DD, 0x2261, + 0xA1DE, 0xFE62, 0xA1DF, 0xFE63, 0xA1E0, 0xFE64, 0xA1E1, 0xFE65, + 0xA1E2, 0xFE66, 0xA1E3, 0xFF5E, 0xA1E4, 0x2229, 0xA1E5, 0x222A, + 0xA1E6, 0x22A5, 0xA1E7, 0x2220, 0xA1E8, 0x221F, 0xA1E9, 0x22BF, + 0xA1EA, 0x33D2, 0xA1EB, 0x33D1, 0xA1EC, 0x222B, 0xA1ED, 0x222E, + 0xA1EE, 0x2235, 0xA1EF, 0x2234, 0xA1F0, 0x2640, 0xA1F1, 0x2642, + 0xA1F2, 0x2295, 0xA1F3, 0x2299, 0xA1F4, 0x2191, 0xA1F5, 0x2193, + 0xA1F6, 0x2190, 0xA1F7, 0x2192, 0xA1F8, 0x2196, 0xA1F9, 0x2197, + 0xA1FA, 0x2199, 0xA1FB, 0x2198, 0xA1FC, 0x2225, 0xA1FD, 0x2223, + 0xA1FE, 0xFF0F, 0xA240, 0xFF3C, 0xA241, 0x2215, 0xA242, 0xFE68, + 0xA243, 0xFF04, 0xA244, 0xFFE5, 0xA245, 0x3012, 0xA246, 0xFFE0, + 0xA247, 0xFFE1, 0xA248, 0xFF05, 0xA249, 0xFF20, 0xA24A, 0x2103, + 0xA24B, 0x2109, 0xA24C, 0xFE69, 0xA24D, 0xFE6A, 0xA24E, 0xFE6B, + 0xA24F, 0x33D5, 0xA250, 0x339C, 0xA251, 0x339D, 0xA252, 0x339E, + 0xA253, 0x33CE, 0xA254, 0x33A1, 0xA255, 0x338E, 0xA256, 0x338F, + 0xA257, 0x33C4, 0xA258, 0x00B0, 0xA259, 0x5159, 0xA25A, 0x515B, + 0xA25B, 0x515E, 0xA25C, 0x515D, 0xA25D, 0x5161, 0xA25E, 0x5163, + 0xA25F, 0x55E7, 0xA260, 0x74E9, 0xA261, 0x7CCE, 0xA262, 0x2581, + 0xA263, 0x2582, 0xA264, 0x2583, 0xA265, 0x2584, 0xA266, 0x2585, + 0xA267, 0x2586, 0xA268, 0x2587, 0xA269, 0x2588, 0xA26A, 0x258F, + 0xA26B, 0x258E, 0xA26C, 0x258D, 0xA26D, 0x258C, 0xA26E, 0x258B, + 0xA26F, 0x258A, 0xA270, 0x2589, 0xA271, 0x253C, 0xA272, 0x2534, + 0xA273, 0x252C, 0xA274, 0x2524, 0xA275, 0x251C, 0xA276, 0x2594, + 0xA277, 0x2500, 0xA278, 0x2502, 0xA279, 0x2595, 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0xFF2A, + 0xA2D9, 0xFF2B, 0xA2DA, 0xFF2C, 0xA2DB, 0xFF2D, 0xA2DC, 0xFF2E, + 0xA2DD, 0xFF2F, 0xA2DE, 0xFF30, 0xA2DF, 0xFF31, 0xA2E0, 0xFF32, + 0xA2E1, 0xFF33, 0xA2E2, 0xFF34, 0xA2E3, 0xFF35, 0xA2E4, 0xFF36, + 0xA2E5, 0xFF37, 0xA2E6, 0xFF38, 0xA2E7, 0xFF39, 0xA2E8, 0xFF3A, + 0xA2E9, 0xFF41, 0xA2EA, 0xFF42, 0xA2EB, 0xFF43, 0xA2EC, 0xFF44, + 0xA2ED, 0xFF45, 0xA2EE, 0xFF46, 0xA2EF, 0xFF47, 0xA2F0, 0xFF48, + 0xA2F1, 0xFF49, 0xA2F2, 0xFF4A, 0xA2F3, 0xFF4B, 0xA2F4, 0xFF4C, + 0xA2F5, 0xFF4D, 0xA2F6, 0xFF4E, 0xA2F7, 0xFF4F, 0xA2F8, 0xFF50, + 0xA2F9, 0xFF51, 0xA2FA, 0xFF52, 0xA2FB, 0xFF53, 0xA2FC, 0xFF54, + 0xA2FD, 0xFF55, 0xA2FE, 0xFF56, 0xA340, 0xFF57, 0xA341, 0xFF58, + 0xA342, 0xFF59, 0xA343, 0xFF5A, 0xA344, 0x0391, 0xA345, 0x0392, + 0xA346, 0x0393, 0xA347, 0x0394, 0xA348, 0x0395, 0xA349, 0x0396, + 0xA34A, 0x0397, 0xA34B, 0x0398, 0xA34C, 0x0399, 0xA34D, 0x039A, + 0xA34E, 0x039B, 0xA34F, 0x039C, 0xA350, 0x039D, 0xA351, 0x039E, + 0xA352, 0x039F, 0xA353, 0x03A0, 0xA354, 0x03A1, 0xA355, 0x03A3, + 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0xF8C0, 0x884B, + 0xF8C1, 0x8B94, 0xF8C2, 0x8B95, 0xF8C3, 0x8E9E, 0xF8C4, 0x8E9F, + 0xF8C5, 0x8EA0, 0xF8C6, 0x8E9D, 0xF8C7, 0x91BE, 0xF8C8, 0x91BD, + 0xF8C9, 0x91C2, 0xF8CA, 0x946B, 0xF8CB, 0x9468, 0xF8CC, 0x9469, + 0xF8CD, 0x96E5, 0xF8CE, 0x9746, 0xF8CF, 0x9743, 0xF8D0, 0x9747, + 0xF8D1, 0x97C7, 0xF8D2, 0x97E5, 0xF8D3, 0x9A5E, 0xF8D4, 0x9AD5, + 0xF8D5, 0x9B59, 0xF8D6, 0x9C63, 0xF8D7, 0x9C67, 0xF8D8, 0x9C66, + 0xF8D9, 0x9C62, 0xF8DA, 0x9C5E, 0xF8DB, 0x9C60, 0xF8DC, 0x9E02, + 0xF8DD, 0x9DFE, 0xF8DE, 0x9E07, 0xF8DF, 0x9E03, 0xF8E0, 0x9E06, + 0xF8E1, 0x9E05, 0xF8E2, 0x9E00, 0xF8E3, 0x9E01, 0xF8E4, 0x9E09, + 0xF8E5, 0x9DFF, 0xF8E6, 0x9DFD, 0xF8E7, 0x9E04, 0xF8E8, 0x9EA0, + 0xF8E9, 0x9F1E, 0xF8EA, 0x9F46, 0xF8EB, 0x9F74, 0xF8EC, 0x9F75, + 0xF8ED, 0x9F76, 0xF8EE, 0x56D4, 0xF8EF, 0x652E, 0xF8F0, 0x65B8, + 0xF8F1, 0x6B18, 0xF8F2, 0x6B19, 0xF8F3, 0x6B17, 0xF8F4, 0x6B1A, + 0xF8F5, 0x7062, 0xF8F6, 0x7226, 0xF8F7, 0x72AA, 0xF8F8, 0x77D8, + 0xF8F9, 0x77D9, 0xF8FA, 0x7939, 0xF8FB, 0x7C69, 0xF8FC, 0x7C6B, + 0xF8FD, 0x7CF6, 0xF8FE, 0x7E9A, 0xF940, 0x7E98, 0xF941, 0x7E9B, + 0xF942, 0x7E99, 0xF943, 0x81E0, 0xF944, 0x81E1, 0xF945, 0x8646, + 0xF946, 0x8647, 0xF947, 0x8648, 0xF948, 0x8979, 0xF949, 0x897A, + 0xF94A, 0x897C, 0xF94B, 0x897B, 0xF94C, 0x89FF, 0xF94D, 0x8B98, + 0xF94E, 0x8B99, 0xF94F, 0x8EA5, 0xF950, 0x8EA4, 0xF951, 0x8EA3, + 0xF952, 0x946E, 0xF953, 0x946D, 0xF954, 0x946F, 0xF955, 0x9471, + 0xF956, 0x9473, 0xF957, 0x9749, 0xF958, 0x9872, 0xF959, 0x995F, + 0xF95A, 0x9C68, 0xF95B, 0x9C6E, 0xF95C, 0x9C6D, 0xF95D, 0x9E0B, + 0xF95E, 0x9E0D, 0xF95F, 0x9E10, 0xF960, 0x9E0F, 0xF961, 0x9E12, + 0xF962, 0x9E11, 0xF963, 0x9EA1, 0xF964, 0x9EF5, 0xF965, 0x9F09, + 0xF966, 0x9F47, 0xF967, 0x9F78, 0xF968, 0x9F7B, 0xF969, 0x9F7A, + 0xF96A, 0x9F79, 0xF96B, 0x571E, 0xF96C, 0x7066, 0xF96D, 0x7C6F, + 0xF96E, 0x883C, 0xF96F, 0x8DB2, 0xF970, 0x8EA6, 0xF971, 0x91C3, + 0xF972, 0x9474, 0xF973, 0x9478, 0xF974, 0x9476, 0xF975, 0x9475, + 0xF976, 0x9A60, 0xF977, 0x9C74, 0xF978, 0x9C73, 0xF979, 0x9C71, + 0xF97A, 0x9C75, 0xF97B, 0x9E14, 0xF97C, 0x9E13, 0xF97D, 0x9EF6, + 0xF97E, 0x9F0A, 0xF9A1, 0x9FA4, 0xF9A2, 0x7068, 0xF9A3, 0x7065, + 0xF9A4, 0x7CF7, 0xF9A5, 0x866A, 0xF9A6, 0x883E, 0xF9A7, 0x883D, + 0xF9A8, 0x883F, 0xF9A9, 0x8B9E, 0xF9AA, 0x8C9C, 0xF9AB, 0x8EA9, + 0xF9AC, 0x8EC9, 0xF9AD, 0x974B, 0xF9AE, 0x9873, 0xF9AF, 0x9874, + 0xF9B0, 0x98CC, 0xF9B1, 0x9961, 0xF9B2, 0x99AB, 0xF9B3, 0x9A64, + 0xF9B4, 0x9A66, 0xF9B5, 0x9A67, 0xF9B6, 0x9B24, 0xF9B7, 0x9E15, + 0xF9B8, 0x9E17, 0xF9B9, 0x9F48, 0xF9BA, 0x6207, 0xF9BB, 0x6B1E, + 0xF9BC, 0x7227, 0xF9BD, 0x864C, 0xF9BE, 0x8EA8, 0xF9BF, 0x9482, + 0xF9C0, 0x9480, 0xF9C1, 0x9481, 0xF9C2, 0x9A69, 0xF9C3, 0x9A68, + 0xF9C4, 0x9B2E, 0xF9C5, 0x9E19, 0xF9C6, 0x7229, 0xF9C7, 0x864B, + 0xF9C8, 0x8B9F, 0xF9C9, 0x9483, 0xF9CA, 0x9C79, 0xF9CB, 0x9EB7, + 0xF9CC, 0x7675, 0xF9CD, 0x9A6B, 0xF9CE, 0x9C7A, 0xF9CF, 0x9E1D, + 0xF9D0, 0x7069, 0xF9D1, 0x706A, 0xF9D2, 0x9EA4, 0xF9D3, 0x9F7E, + 0xF9D4, 0x9F49, 0xF9D5, 0x9F98, 0xF9D6, 0x7881, 0xF9D7, 0x92B9, + 0xF9D8, 0x88CF, 0xF9D9, 0x58BB, 0xF9DA, 0x6052, 0xF9DB, 0x7CA7, + 0xF9DC, 0x5AFA, 0xF9DD, 0x2554, 0xF9DE, 0x2566, 0xF9DF, 0x2557, + 0xF9E0, 0x2560, 0xF9E1, 0x256C, 0xF9E2, 0x2563, 0xF9E3, 0x255A, + 0xF9E4, 0x2569, 0xF9E5, 0x255D, 0xF9E6, 0x2552, 0xF9E7, 0x2564, + 0xF9E8, 0x2555, 0xF9E9, 0x255E, 0xF9EA, 0x256A, 0xF9EB, 0x2561, + 0xF9EC, 0x2558, 0xF9ED, 0x2567, 0xF9EE, 0x255B, 0xF9EF, 0x2553, + 0xF9F0, 0x2565, 0xF9F1, 0x2556, 0xF9F2, 0x255F, 0xF9F3, 0x256B, + 0xF9F4, 0x2562, 0xF9F5, 0x2559, 0xF9F6, 0x2568, 0xF9F7, 0x255C, + 0xF9F8, 0x2551, 0xF9F9, 0x2550, 0xF9FA, 0x256D, 0xF9FB, 0x256E, + 0xF9FC, 0x2570, 0xF9FD, 0x256F, 0xF9FE, 0x2593, 0, 0 +}; + + + +WCHAR ff_convert ( /* Converted code, 0 means conversion error */ + WCHAR chr, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEM code, 1: OEM code to Unicode */ +) +{ + const WCHAR *p; + WCHAR c; + int i, n, li, hi; + + + if (chr < 0x80) { /* ASCII */ + c = chr; + } else { + if (dir) { /* OEM code to unicode */ + p = oem2uni; + hi = sizeof oem2uni / 4 - 1; + } else { /* Unicode to OEM code */ + p = uni2oem; + hi = sizeof uni2oem / 4 - 1; + } + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (chr == p[i * 2]) break; + if (chr > p[i * 2]) + li = i; + else + hi = i; + } + c = n ? p[i * 2 + 1] : 0; + } + + return c; +} + + + +WCHAR ff_wtoupper ( /* Returns upper converted character */ + WCHAR chr /* Unicode character to be upper converted (BMP only) */ +) +{ + /* Compressed upper conversion table */ + static const WCHAR cvt1[] = { /* U+0000 - U+0FFF */ + /* Basic Latin */ + 0x0061,0x031A, + /* Latin-1 Supplement */ + 0x00E0,0x0317, 0x00F8,0x0307, 0x00FF,0x0001,0x0178, + /* Latin Extended-A */ + 0x0100,0x0130, 0x0132,0x0106, 0x0139,0x0110, 0x014A,0x012E, 0x0179,0x0106, + /* Latin Extended-B */ + 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, + 0x01CD,0x0110, 0x01DD,0x0001,0x018E, 0x01DE,0x0112, 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, 0x01F8,0x0128, + 0x0222,0x0112, 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, 0x0246,0x010A, + /* IPA Extensions */ + 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, + /* Greek, Coptic */ + 0x037B,0x0003,0x03FD,0x03FE,0x03FF, 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, 0x03B1,0x0311, + 0x03C2,0x0002,0x03A3,0x03A3, 0x03C4,0x0308, 0x03CC,0x0003,0x038C,0x038E,0x038F, 0x03D8,0x0118, + 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, + /* Cyrillic */ + 0x0430,0x0320, 0x0450,0x0710, 0x0460,0x0122, 0x048A,0x0136, 0x04C1,0x010E, 0x04CF,0x0001,0x04C0, 0x04D0,0x0144, + /* Armenian */ + 0x0561,0x0426, + + 0x0000 + }; + static const WCHAR cvt2[] = { /* U+1000 - U+FFFF */ + /* Phonetic Extensions */ + 0x1D7D,0x0001,0x2C63, + /* Latin Extended Additional */ + 0x1E00,0x0196, 0x1EA0,0x015A, + /* Greek Extended */ + 0x1F00,0x0608, 0x1F10,0x0606, 0x1F20,0x0608, 0x1F30,0x0608, 0x1F40,0x0606, + 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, 0x1F60,0x0608, + 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, + 0x1F80,0x0608, 0x1F90,0x0608, 0x1FA0,0x0608, 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, + 0x1FCC,0x0001,0x1FC3, 0x1FD0,0x0602, 0x1FE0,0x0602, 0x1FE5,0x0001,0x1FEC, 0x1FF2,0x0001,0x1FFC, + /* Letterlike Symbols */ + 0x214E,0x0001,0x2132, + /* Number forms */ + 0x2170,0x0210, 0x2184,0x0001,0x2183, + /* Enclosed Alphanumerics */ + 0x24D0,0x051A, 0x2C30,0x042F, + /* Latin Extended-C */ + 0x2C60,0x0102, 0x2C67,0x0106, 0x2C75,0x0102, + /* Coptic */ + 0x2C80,0x0164, + /* Georgian Supplement */ + 0x2D00,0x0826, + /* Full-width */ + 0xFF41,0x031A, + + 0x0000 + }; + const WCHAR *p; + WCHAR bc, nc, cmd; + + + p = chr < 0x1000 ? cvt1 : cvt2; + for (;;) { + bc = *p++; /* Get block base */ + if (!bc || chr < bc) break; + nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ + if (chr < bc + nc) { /* In the block? */ + switch (cmd) { + case 0: chr = p[chr - bc]; break; /* Table conversion */ + case 1: chr -= (chr - bc) & 1; break; /* Case pairs */ + case 2: chr -= 16; break; /* Shift -16 */ + case 3: chr -= 32; break; /* Shift -32 */ + case 4: chr -= 48; break; /* Shift -48 */ + case 5: chr -= 26; break; /* Shift -26 */ + case 6: chr += 8; break; /* Shift +8 */ + case 7: chr -= 80; break; /* Shift -80 */ + case 8: chr -= 0x1C60; break; /* Shift -0x1C60 */ + } + break; + } + if (!cmd) p += nc; + } + + return chr; +} + diff --git a/radio/src/thirdparty/FatFs/option/ccsbcs.c b/radio/src/thirdparty/FatFs/option/ccsbcs.c index 164caa066..e2762dc65 100644 --- a/radio/src/thirdparty/FatFs/option/ccsbcs.c +++ b/radio/src/thirdparty/FatFs/option/ccsbcs.c @@ -1,388 +1,388 @@ -/*------------------------------------------------------------------------*/ -/* Unicode - Local code bidirectional converter (C)ChaN, 2015 */ -/* (SBCS code pages) */ -/*------------------------------------------------------------------------*/ -/* 437 U.S. -/ 720 Arabic -/ 737 Greek -/ 771 KBL -/ 775 Baltic -/ 850 Latin 1 -/ 852 Latin 2 -/ 855 Cyrillic -/ 857 Turkish -/ 860 Portuguese -/ 861 Icelandic -/ 862 Hebrew -/ 863 Canadian French -/ 864 Arabic -/ 865 Nordic -/ 866 Russian -/ 869 Greek 2 -*/ - -#include "../ff.h" - - -#if _CODE_PAGE == 437 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 720 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ - 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, - 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, - 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 737 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ - 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, - 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, - 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, - 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 771 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP771(0x80-0xFF) to Unicode conversion table */ - 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, - 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, - 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x0104, 0x0105, 0x010C, 0x010D, - 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, - 0x0118, 0x0119, 0x0116, 0x0117, 0x012E, 0x012F, 0x0160, 0x0161, 0x0172, 0x0173, 0x016A, 0x016B, 0x017D, 0x017E, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 775 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ - 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, - 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, - 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, - 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 850 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 852 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, - 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, - 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 855 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ - 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, - 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, - 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, - 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, - 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 857 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 860 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP860(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E3, 0x00E0, 0x00C1, 0x00E7, 0x00EA, 0x00CA, 0x00E8, 0x00CD, 0x00D4, 0x00EC, 0x00C3, 0x00C2, - 0x00C9, 0x00C0, 0x00C8, 0x00F4, 0x00F5, 0x00F2, 0x00DA, 0x00F9, 0x00CC, 0x00D5, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x20A7, 0x00D3, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00D2, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 861 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP861(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00D0, 0x00F0, 0x00DE, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00FE, 0x00FB, 0x00DD, 0x00FD, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00C1, 0x00CD, 0x00D3, 0x00DA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 862 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ - 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, - 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 863 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP863(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00C2, 0x00E0, 0x00B6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x2017, 0x00C0, - 0x00C9, 0x00C8, 0x00CA, 0x00F4, 0x00CB, 0x00CF, 0x00FB, 0x00F9, 0x00A4, 0x00D4, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x00DB, 0x0192, - 0x00A6, 0x00B4, 0x00F3, 0x00FA, 0x00A8, 0x00BB, 0x00B3, 0x00AF, 0x00CE, 0x3210, 0x00AC, 0x00BD, 0x00BC, 0x00BE, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2219, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 864 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP864(0x80-0xFF) to Unicode conversion table */ - 0x00B0, 0x00B7, 0x2219, 0x221A, 0x2592, 0x2500, 0x2502, 0x253C, 0x2524, 0x252C, 0x251C, 0x2534, 0x2510, 0x250C, 0x2514, 0x2518, - 0x03B2, 0x221E, 0x03C6, 0x00B1, 0x00BD, 0x00BC, 0x2248, 0x00AB, 0x00BB, 0xFEF7, 0xFEF8, 0x0000, 0x0000, 0xFEFB, 0xFEFC, 0x0000, - 0x00A0, 0x00AD, 0xFE82, 0x00A3, 0x00A4, 0xFE84, 0x0000, 0x20AC, 0xFE8E, 0xFE8F, 0xFE95, 0xFE99, 0x060C, 0xFE9D, 0xFEA1, 0xFEA5, - 0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667, 0x0668, 0x0669, 0xFED1, 0x061B, 0xFEB1, 0xFEB5, 0xFEB9, 0x061F, - 0x00A2, 0xFE80, 0xFE81, 0xFE83, 0xFE85, 0xFECA, 0xFE8B, 0xFE8D, 0xFE91, 0xFE93, 0xFE97, 0xFE9B, 0xFE9F, 0xFEA3, 0xFEA7, 0xFEA9, - 0xFEAB, 0xFEAD, 0xFEAF, 0xFEB3, 0xFEB7, 0xFEBB, 0xFEBF, 0xFEC1, 0xFEC5, 0xFECB, 0xFECF, 0x00A6, 0x00AC, 0x00F7, 0x00D7, 0xFEC9, - 0x0640, 0xFED3, 0xFED7, 0xFEDB, 0xFEDF, 0xFEE3, 0xFEE7, 0xFEEB, 0xFEED, 0xFEEF, 0xFEF3, 0xFEBD, 0xFECC, 0xFECE, 0xFECD, 0xFEE1, - 0xFE7D, 0x0651, 0xFEE5, 0xFEE9, 0xFEEC, 0xFEF0, 0xFEF2, 0xFED0, 0xFED5, 0xFEF5, 0xFEF6, 0xFEDD, 0xFED9, 0xFEF1, 0x25A0, 0x0000 -}; - -#elif _CODE_PAGE == 865 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP865(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C5, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00A4, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 866 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ - 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, - 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, - 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, - 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 869 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP869(0x80-0xFF) to Unicode conversion table */ - 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x0386, 0x00B7, 0x00B7, 0x00AC, 0x00A6, 0x2018, 0x2019, 0x0388, 0x2015, 0x0389, - 0x038A, 0x03AA, 0x038C, 0x00B7, 0x00B7, 0x038E, 0x03AB, 0x00A9, 0x038F, 0x00B2, 0x00B3, 0x03AC, 0x00A3, 0x03AD, 0x03AE, 0x03AF, - 0x03CA, 0x0390, 0x03CC, 0x03CD, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x00BD, 0x0398, 0x0399, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x039A, 0x039B, 0x039C, 0x039D, 0x2563, 0x2551, 0x2557, 0x255D, 0x039E, 0x039F, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0A30, 0x03A1, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x03A3, - 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x2518, 0x250C, 0x2588, 0x2584, 0x03B4, 0x03B5, 0x2580, - 0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x0384, - 0x00AD, 0x00B1, 0x03C5, 0x03C6, 0x03C7, 0x00A7, 0x03C8, 0x0385, 0x00B0, 0x00A8, 0x03C9, 0x03CB, 0x03B0, 0x03CE, 0x25A0, 0x00A0 -}; - -#endif - - -#if !_TBLDEF || !_USE_LFN -#error This file is not needed at current configuration. Remove from the project. -#endif - - - - -WCHAR ff_convert ( /* Converted character, Returns zero on error */ - WCHAR chr, /* Character code to be converted */ - UINT dir /* 0: Unicode to OEM code, 1: OEM code to Unicode */ -) -{ - WCHAR c; - - - if (chr < 0x80) { /* ASCII */ - c = chr; - - } else { - if (dir) { /* OEM code to Unicode */ - c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80]; - - } else { /* Unicode to OEM code */ - for (c = 0; c < 0x80; c++) { - if (chr == Tbl[c]) break; - } - c = (c + 0x80) & 0xFF; - } - } - - return c; -} - - - -WCHAR ff_wtoupper ( /* Returns upper converted character */ - WCHAR chr /* Unicode character to be upper converted (BMP only) */ -) -{ - /* Compressed upper conversion table */ - static const WCHAR cvt1[] = { /* U+0000 - U+0FFF */ - /* Basic Latin */ - 0x0061,0x031A, - /* Latin-1 Supplement */ - 0x00E0,0x0317, 0x00F8,0x0307, 0x00FF,0x0001,0x0178, - /* Latin Extended-A */ - 0x0100,0x0130, 0x0132,0x0106, 0x0139,0x0110, 0x014A,0x012E, 0x0179,0x0106, - /* Latin Extended-B */ - 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, - 0x01CD,0x0110, 0x01DD,0x0001,0x018E, 0x01DE,0x0112, 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, 0x01F8,0x0128, - 0x0222,0x0112, 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, 0x0246,0x010A, - /* IPA Extensions */ - 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, - /* Greek, Coptic */ - 0x037B,0x0003,0x03FD,0x03FE,0x03FF, 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, 0x03B1,0x0311, - 0x03C2,0x0002,0x03A3,0x03A3, 0x03C4,0x0308, 0x03CC,0x0003,0x038C,0x038E,0x038F, 0x03D8,0x0118, - 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, - /* Cyrillic */ - 0x0430,0x0320, 0x0450,0x0710, 0x0460,0x0122, 0x048A,0x0136, 0x04C1,0x010E, 0x04CF,0x0001,0x04C0, 0x04D0,0x0144, - /* Armenian */ - 0x0561,0x0426, - - 0x0000 - }; - static const WCHAR cvt2[] = { /* U+1000 - U+FFFF */ - /* Phonetic Extensions */ - 0x1D7D,0x0001,0x2C63, - /* Latin Extended Additional */ - 0x1E00,0x0196, 0x1EA0,0x015A, - /* Greek Extended */ - 0x1F00,0x0608, 0x1F10,0x0606, 0x1F20,0x0608, 0x1F30,0x0608, 0x1F40,0x0606, - 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, 0x1F60,0x0608, - 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, - 0x1F80,0x0608, 0x1F90,0x0608, 0x1FA0,0x0608, 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, - 0x1FCC,0x0001,0x1FC3, 0x1FD0,0x0602, 0x1FE0,0x0602, 0x1FE5,0x0001,0x1FEC, 0x1FF2,0x0001,0x1FFC, - /* Letterlike Symbols */ - 0x214E,0x0001,0x2132, - /* Number forms */ - 0x2170,0x0210, 0x2184,0x0001,0x2183, - /* Enclosed Alphanumerics */ - 0x24D0,0x051A, 0x2C30,0x042F, - /* Latin Extended-C */ - 0x2C60,0x0102, 0x2C67,0x0106, 0x2C75,0x0102, - /* Coptic */ - 0x2C80,0x0164, - /* Georgian Supplement */ - 0x2D00,0x0826, - /* Full-width */ - 0xFF41,0x031A, - - 0x0000 - }; - const WCHAR *p; - WCHAR bc, nc, cmd; - - - p = chr < 0x1000 ? cvt1 : cvt2; - for (;;) { - bc = *p++; /* Get block base */ - if (!bc || chr < bc) break; - nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ - if (chr < bc + nc) { /* In the block? */ - switch (cmd) { - case 0: chr = p[chr - bc]; break; /* Table conversion */ - case 1: chr -= (chr - bc) & 1; break; /* Case pairs */ - case 2: chr -= 16; break; /* Shift -16 */ - case 3: chr -= 32; break; /* Shift -32 */ - case 4: chr -= 48; break; /* Shift -48 */ - case 5: chr -= 26; break; /* Shift -26 */ - case 6: chr += 8; break; /* Shift +8 */ - case 7: chr -= 80; break; /* Shift -80 */ - case 8: chr -= 0x1C60; break; /* Shift -0x1C60 */ - } - break; - } - if (!cmd) p += nc; - } - - return chr; -} - +/*------------------------------------------------------------------------*/ +/* Unicode - Local code bidirectional converter (C)ChaN, 2015 */ +/* (SBCS code pages) */ +/*------------------------------------------------------------------------*/ +/* 437 U.S. +/ 720 Arabic +/ 737 Greek +/ 771 KBL +/ 775 Baltic +/ 850 Latin 1 +/ 852 Latin 2 +/ 855 Cyrillic +/ 857 Turkish +/ 860 Portuguese +/ 861 Icelandic +/ 862 Hebrew +/ 863 Canadian French +/ 864 Arabic +/ 865 Nordic +/ 866 Russian +/ 869 Greek 2 +*/ + +#include "../ff.h" + + +#if _CODE_PAGE == 437 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 720 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ + 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, + 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 737 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ + 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, + 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, + 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, + 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 771 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP771(0x80-0xFF) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x0104, 0x0105, 0x010C, 0x010D, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0118, 0x0119, 0x0116, 0x0117, 0x012E, 0x012F, 0x0160, 0x0161, 0x0172, 0x0173, 0x016A, 0x016B, 0x017D, 0x017E, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 775 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ + 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, + 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, + 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, + 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 850 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 852 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, + 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, + 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 855 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ + 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, + 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, + 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, + 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, + 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 857 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 860 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP860(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E3, 0x00E0, 0x00C1, 0x00E7, 0x00EA, 0x00CA, 0x00E8, 0x00CD, 0x00D4, 0x00EC, 0x00C3, 0x00C2, + 0x00C9, 0x00C0, 0x00C8, 0x00F4, 0x00F5, 0x00F2, 0x00DA, 0x00F9, 0x00CC, 0x00D5, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x20A7, 0x00D3, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00D2, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 861 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP861(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00D0, 0x00F0, 0x00DE, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00FE, 0x00FB, 0x00DD, 0x00FD, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00C1, 0x00CD, 0x00D3, 0x00DA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 862 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 863 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP863(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00C2, 0x00E0, 0x00B6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x2017, 0x00C0, + 0x00C9, 0x00C8, 0x00CA, 0x00F4, 0x00CB, 0x00CF, 0x00FB, 0x00F9, 0x00A4, 0x00D4, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x00DB, 0x0192, + 0x00A6, 0x00B4, 0x00F3, 0x00FA, 0x00A8, 0x00BB, 0x00B3, 0x00AF, 0x00CE, 0x3210, 0x00AC, 0x00BD, 0x00BC, 0x00BE, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2219, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 864 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP864(0x80-0xFF) to Unicode conversion table */ + 0x00B0, 0x00B7, 0x2219, 0x221A, 0x2592, 0x2500, 0x2502, 0x253C, 0x2524, 0x252C, 0x251C, 0x2534, 0x2510, 0x250C, 0x2514, 0x2518, + 0x03B2, 0x221E, 0x03C6, 0x00B1, 0x00BD, 0x00BC, 0x2248, 0x00AB, 0x00BB, 0xFEF7, 0xFEF8, 0x0000, 0x0000, 0xFEFB, 0xFEFC, 0x0000, + 0x00A0, 0x00AD, 0xFE82, 0x00A3, 0x00A4, 0xFE84, 0x0000, 0x20AC, 0xFE8E, 0xFE8F, 0xFE95, 0xFE99, 0x060C, 0xFE9D, 0xFEA1, 0xFEA5, + 0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667, 0x0668, 0x0669, 0xFED1, 0x061B, 0xFEB1, 0xFEB5, 0xFEB9, 0x061F, + 0x00A2, 0xFE80, 0xFE81, 0xFE83, 0xFE85, 0xFECA, 0xFE8B, 0xFE8D, 0xFE91, 0xFE93, 0xFE97, 0xFE9B, 0xFE9F, 0xFEA3, 0xFEA7, 0xFEA9, + 0xFEAB, 0xFEAD, 0xFEAF, 0xFEB3, 0xFEB7, 0xFEBB, 0xFEBF, 0xFEC1, 0xFEC5, 0xFECB, 0xFECF, 0x00A6, 0x00AC, 0x00F7, 0x00D7, 0xFEC9, + 0x0640, 0xFED3, 0xFED7, 0xFEDB, 0xFEDF, 0xFEE3, 0xFEE7, 0xFEEB, 0xFEED, 0xFEEF, 0xFEF3, 0xFEBD, 0xFECC, 0xFECE, 0xFECD, 0xFEE1, + 0xFE7D, 0x0651, 0xFEE5, 0xFEE9, 0xFEEC, 0xFEF0, 0xFEF2, 0xFED0, 0xFED5, 0xFEF5, 0xFEF6, 0xFEDD, 0xFED9, 0xFEF1, 0x25A0, 0x0000 +}; + +#elif _CODE_PAGE == 865 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP865(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C5, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00A4, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 866 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 869 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP869(0x80-0xFF) to Unicode conversion table */ + 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x0386, 0x00B7, 0x00B7, 0x00AC, 0x00A6, 0x2018, 0x2019, 0x0388, 0x2015, 0x0389, + 0x038A, 0x03AA, 0x038C, 0x00B7, 0x00B7, 0x038E, 0x03AB, 0x00A9, 0x038F, 0x00B2, 0x00B3, 0x03AC, 0x00A3, 0x03AD, 0x03AE, 0x03AF, + 0x03CA, 0x0390, 0x03CC, 0x03CD, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x00BD, 0x0398, 0x0399, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x039A, 0x039B, 0x039C, 0x039D, 0x2563, 0x2551, 0x2557, 0x255D, 0x039E, 0x039F, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0A30, 0x03A1, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x03A3, + 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x2518, 0x250C, 0x2588, 0x2584, 0x03B4, 0x03B5, 0x2580, + 0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x0384, + 0x00AD, 0x00B1, 0x03C5, 0x03C6, 0x03C7, 0x00A7, 0x03C8, 0x0385, 0x00B0, 0x00A8, 0x03C9, 0x03CB, 0x03B0, 0x03CE, 0x25A0, 0x00A0 +}; + +#endif + + +#if !_TBLDEF || !_USE_LFN +#error This file is not needed at current configuration. Remove from the project. +#endif + + + + +WCHAR ff_convert ( /* Converted character, Returns zero on error */ + WCHAR chr, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEM code, 1: OEM code to Unicode */ +) +{ + WCHAR c; + + + if (chr < 0x80) { /* ASCII */ + c = chr; + + } else { + if (dir) { /* OEM code to Unicode */ + c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80]; + + } else { /* Unicode to OEM code */ + for (c = 0; c < 0x80; c++) { + if (chr == Tbl[c]) break; + } + c = (c + 0x80) & 0xFF; + } + } + + return c; +} + + + +WCHAR ff_wtoupper ( /* Returns upper converted character */ + WCHAR chr /* Unicode character to be upper converted (BMP only) */ +) +{ + /* Compressed upper conversion table */ + static const WCHAR cvt1[] = { /* U+0000 - U+0FFF */ + /* Basic Latin */ + 0x0061,0x031A, + /* Latin-1 Supplement */ + 0x00E0,0x0317, 0x00F8,0x0307, 0x00FF,0x0001,0x0178, + /* Latin Extended-A */ + 0x0100,0x0130, 0x0132,0x0106, 0x0139,0x0110, 0x014A,0x012E, 0x0179,0x0106, + /* Latin Extended-B */ + 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, + 0x01CD,0x0110, 0x01DD,0x0001,0x018E, 0x01DE,0x0112, 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, 0x01F8,0x0128, + 0x0222,0x0112, 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, 0x0246,0x010A, + /* IPA Extensions */ + 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, + /* Greek, Coptic */ + 0x037B,0x0003,0x03FD,0x03FE,0x03FF, 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, 0x03B1,0x0311, + 0x03C2,0x0002,0x03A3,0x03A3, 0x03C4,0x0308, 0x03CC,0x0003,0x038C,0x038E,0x038F, 0x03D8,0x0118, + 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, + /* Cyrillic */ + 0x0430,0x0320, 0x0450,0x0710, 0x0460,0x0122, 0x048A,0x0136, 0x04C1,0x010E, 0x04CF,0x0001,0x04C0, 0x04D0,0x0144, + /* Armenian */ + 0x0561,0x0426, + + 0x0000 + }; + static const WCHAR cvt2[] = { /* U+1000 - U+FFFF */ + /* Phonetic Extensions */ + 0x1D7D,0x0001,0x2C63, + /* Latin Extended Additional */ + 0x1E00,0x0196, 0x1EA0,0x015A, + /* Greek Extended */ + 0x1F00,0x0608, 0x1F10,0x0606, 0x1F20,0x0608, 0x1F30,0x0608, 0x1F40,0x0606, + 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, 0x1F60,0x0608, + 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, + 0x1F80,0x0608, 0x1F90,0x0608, 0x1FA0,0x0608, 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, + 0x1FCC,0x0001,0x1FC3, 0x1FD0,0x0602, 0x1FE0,0x0602, 0x1FE5,0x0001,0x1FEC, 0x1FF2,0x0001,0x1FFC, + /* Letterlike Symbols */ + 0x214E,0x0001,0x2132, + /* Number forms */ + 0x2170,0x0210, 0x2184,0x0001,0x2183, + /* Enclosed Alphanumerics */ + 0x24D0,0x051A, 0x2C30,0x042F, + /* Latin Extended-C */ + 0x2C60,0x0102, 0x2C67,0x0106, 0x2C75,0x0102, + /* Coptic */ + 0x2C80,0x0164, + /* Georgian Supplement */ + 0x2D00,0x0826, + /* Full-width */ + 0xFF41,0x031A, + + 0x0000 + }; + const WCHAR *p; + WCHAR bc, nc, cmd; + + + p = chr < 0x1000 ? cvt1 : cvt2; + for (;;) { + bc = *p++; /* Get block base */ + if (!bc || chr < bc) break; + nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ + if (chr < bc + nc) { /* In the block? */ + switch (cmd) { + case 0: chr = p[chr - bc]; break; /* Table conversion */ + case 1: chr -= (chr - bc) & 1; break; /* Case pairs */ + case 2: chr -= 16; break; /* Shift -16 */ + case 3: chr -= 32; break; /* Shift -32 */ + case 4: chr -= 48; break; /* Shift -48 */ + case 5: chr -= 26; break; /* Shift -26 */ + case 6: chr += 8; break; /* Shift +8 */ + case 7: chr -= 80; break; /* Shift -80 */ + case 8: chr -= 0x1C60; break; /* Shift -0x1C60 */ + } + break; + } + if (!cmd) p += nc; + } + + return chr; +} + diff --git a/radio/src/thirdparty/FatFs/option/syscall.c b/radio/src/thirdparty/FatFs/option/syscall.c index c9d219b79..4fed617ff 100644 --- a/radio/src/thirdparty/FatFs/option/syscall.c +++ b/radio/src/thirdparty/FatFs/option/syscall.c @@ -1,151 +1,151 @@ -/*------------------------------------------------------------------------*/ -/* Sample code of OS dependent controls for FatFs */ -/* (C)ChaN, 2014 */ -/*------------------------------------------------------------------------*/ - - -#include "../ff.h" - - -#if _FS_REENTRANT -/*------------------------------------------------------------------------*/ -/* Create a Synchronization Object -/*------------------------------------------------------------------------*/ -/* This function is called in f_mount() function to create a new -/ synchronization object, such as semaphore and mutex. When a 0 is returned, -/ the f_mount() function fails with FR_INT_ERR. -*/ - -int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object */ - BYTE vol, /* Corresponding volume (logical drive number) */ - _SYNC_t *sobj /* Pointer to return the created sync object */ -) -{ - int ret; - - - *sobj = CreateMutex(NULL, FALSE, NULL); /* Win32 */ - ret = (int)(*sobj != INVALID_HANDLE_VALUE); - -// *sobj = SyncObjects[vol]; /* uITRON (give a static sync object) */ -// ret = 1; /* The initial value of the semaphore must be 1. */ - -// *sobj = OSMutexCreate(0, &err); /* uC/OS-II */ -// ret = (int)(err == OS_NO_ERR); - -// *sobj = xSemaphoreCreateMutex(); /* FreeRTOS */ -// ret = (int)(*sobj != NULL); - - return ret; -} - - - -/*------------------------------------------------------------------------*/ -/* Delete a Synchronization Object */ -/*------------------------------------------------------------------------*/ -/* This function is called in f_mount() function to delete a synchronization -/ object that created with ff_cre_syncobj() function. When a 0 is returned, -/ the f_mount() function fails with FR_INT_ERR. -*/ - -int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to any error */ - _SYNC_t sobj /* Sync object tied to the logical drive to be deleted */ -) -{ - int ret; - - - ret = CloseHandle(sobj); /* Win32 */ - -// ret = 1; /* uITRON (nothing to do) */ - -// OSMutexDel(sobj, OS_DEL_ALWAYS, &err); /* uC/OS-II */ -// ret = (int)(err == OS_NO_ERR); - -// vSemaphoreDelete(sobj); /* FreeRTOS */ -// ret = 1; - - return ret; -} - - - -/*------------------------------------------------------------------------*/ -/* Request Grant to Access the Volume */ -/*------------------------------------------------------------------------*/ -/* This function is called on entering file functions to lock the volume. -/ When a 0 is returned, the file function fails with FR_TIMEOUT. -*/ - -int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */ - _SYNC_t sobj /* Sync object to wait */ -) -{ - int ret; - - ret = (int)(WaitForSingleObject(sobj, _FS_TIMEOUT) == WAIT_OBJECT_0); /* Win32 */ - -// ret = (int)(wai_sem(sobj) == E_OK); /* uITRON */ - -// OSMutexPend(sobj, _FS_TIMEOUT, &err)); /* uC/OS-II */ -// ret = (int)(err == OS_NO_ERR); - -// ret = (int)(xSemaphoreTake(sobj, _FS_TIMEOUT) == pdTRUE); /* FreeRTOS */ - - return ret; -} - - - -/*------------------------------------------------------------------------*/ -/* Release Grant to Access the Volume */ -/*------------------------------------------------------------------------*/ -/* This function is called on leaving file functions to unlock the volume. -*/ - -void ff_rel_grant ( - _SYNC_t sobj /* Sync object to be signaled */ -) -{ - ReleaseMutex(sobj); /* Win32 */ - -// sig_sem(sobj); /* uITRON */ - -// OSMutexPost(sobj); /* uC/OS-II */ - -// xSemaphoreGive(sobj); /* FreeRTOS */ -} - -#endif - - - - -#if _USE_LFN == 3 /* LFN with a working buffer on the heap */ -/*------------------------------------------------------------------------*/ -/* Allocate a memory block */ -/*------------------------------------------------------------------------*/ -/* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE. -*/ - -void* ff_memalloc ( /* Returns pointer to the allocated memory block */ - UINT msize /* Number of bytes to allocate */ -) -{ - return malloc(msize); /* Allocate a new memory block with POSIX API */ -} - - -/*------------------------------------------------------------------------*/ -/* Free a memory block */ -/*------------------------------------------------------------------------*/ - -void ff_memfree ( - void* mblock /* Pointer to the memory block to free */ -) -{ - free(mblock); /* Discard the memory block with POSIX API */ -} - -#endif +/*------------------------------------------------------------------------*/ +/* Sample code of OS dependent controls for FatFs */ +/* (C)ChaN, 2014 */ +/*------------------------------------------------------------------------*/ + + +#include "../ff.h" + + +#if _FS_REENTRANT +/*------------------------------------------------------------------------*/ +/* Create a Synchronization Object +/*------------------------------------------------------------------------*/ +/* This function is called in f_mount() function to create a new +/ synchronization object, such as semaphore and mutex. When a 0 is returned, +/ the f_mount() function fails with FR_INT_ERR. +*/ + +int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object */ + BYTE vol, /* Corresponding volume (logical drive number) */ + _SYNC_t *sobj /* Pointer to return the created sync object */ +) +{ + int ret; + + + *sobj = CreateMutex(NULL, FALSE, NULL); /* Win32 */ + ret = (int)(*sobj != INVALID_HANDLE_VALUE); + +// *sobj = SyncObjects[vol]; /* uITRON (give a static sync object) */ +// ret = 1; /* The initial value of the semaphore must be 1. */ + +// *sobj = OSMutexCreate(0, &err); /* uC/OS-II */ +// ret = (int)(err == OS_NO_ERR); + +// *sobj = xSemaphoreCreateMutex(); /* FreeRTOS */ +// ret = (int)(*sobj != NULL); + + return ret; +} + + + +/*------------------------------------------------------------------------*/ +/* Delete a Synchronization Object */ +/*------------------------------------------------------------------------*/ +/* This function is called in f_mount() function to delete a synchronization +/ object that created with ff_cre_syncobj() function. When a 0 is returned, +/ the f_mount() function fails with FR_INT_ERR. +*/ + +int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to any error */ + _SYNC_t sobj /* Sync object tied to the logical drive to be deleted */ +) +{ + int ret; + + + ret = CloseHandle(sobj); /* Win32 */ + +// ret = 1; /* uITRON (nothing to do) */ + +// OSMutexDel(sobj, OS_DEL_ALWAYS, &err); /* uC/OS-II */ +// ret = (int)(err == OS_NO_ERR); + +// vSemaphoreDelete(sobj); /* FreeRTOS */ +// ret = 1; + + return ret; +} + + + +/*------------------------------------------------------------------------*/ +/* Request Grant to Access the Volume */ +/*------------------------------------------------------------------------*/ +/* This function is called on entering file functions to lock the volume. +/ When a 0 is returned, the file function fails with FR_TIMEOUT. +*/ + +int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */ + _SYNC_t sobj /* Sync object to wait */ +) +{ + int ret; + + ret = (int)(WaitForSingleObject(sobj, _FS_TIMEOUT) == WAIT_OBJECT_0); /* Win32 */ + +// ret = (int)(wai_sem(sobj) == E_OK); /* uITRON */ + +// OSMutexPend(sobj, _FS_TIMEOUT, &err)); /* uC/OS-II */ +// ret = (int)(err == OS_NO_ERR); + +// ret = (int)(xSemaphoreTake(sobj, _FS_TIMEOUT) == pdTRUE); /* FreeRTOS */ + + return ret; +} + + + +/*------------------------------------------------------------------------*/ +/* Release Grant to Access the Volume */ +/*------------------------------------------------------------------------*/ +/* This function is called on leaving file functions to unlock the volume. +*/ + +void ff_rel_grant ( + _SYNC_t sobj /* Sync object to be signaled */ +) +{ + ReleaseMutex(sobj); /* Win32 */ + +// sig_sem(sobj); /* uITRON */ + +// OSMutexPost(sobj); /* uC/OS-II */ + +// xSemaphoreGive(sobj); /* FreeRTOS */ +} + +#endif + + + + +#if _USE_LFN == 3 /* LFN with a working buffer on the heap */ +/*------------------------------------------------------------------------*/ +/* Allocate a memory block */ +/*------------------------------------------------------------------------*/ +/* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE. +*/ + +void* ff_memalloc ( /* Returns pointer to the allocated memory block */ + UINT msize /* Number of bytes to allocate */ +) +{ + return malloc(msize); /* Allocate a new memory block with POSIX API */ +} + + +/*------------------------------------------------------------------------*/ +/* Free a memory block */ +/*------------------------------------------------------------------------*/ + +void ff_memfree ( + void* mblock /* Pointer to the memory block to free */ +) +{ + free(mblock); /* Discard the memory block with POSIX API */ +} + +#endif diff --git a/radio/src/thirdparty/FatFs/option/unicode.c b/radio/src/thirdparty/FatFs/option/unicode.c index 170e2e09e..0afe13e13 100644 --- a/radio/src/thirdparty/FatFs/option/unicode.c +++ b/radio/src/thirdparty/FatFs/option/unicode.c @@ -1,17 +1,17 @@ -#include "../ff.h" - -#if _USE_LFN != 0 - -#if _CODE_PAGE == 932 /* Japanese Shift_JIS */ -#include "cc932.c" -#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ -#include "cc936.c" -#elif _CODE_PAGE == 949 /* Korean */ -#include "cc949.c" -#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ -#include "cc950.c" -#else /* Single Byte Character-Set */ -#include "ccsbcs.c" -#endif - -#endif +#include "../ff.h" + +#if _USE_LFN != 0 + +#if _CODE_PAGE == 932 /* Japanese Shift_JIS */ +#include "cc932.c" +#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ +#include "cc936.c" +#elif _CODE_PAGE == 949 /* Korean */ +#include "cc949.c" +#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ +#include "cc950.c" +#else /* Single Byte Character-Set */ +#include "ccsbcs.c" +#endif + +#endif diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h index de2ac94bd..0381f4e00 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h @@ -1,6967 +1,6967 @@ -/** - ****************************************************************************** - * @file stm32f2xx.h - * @author MCD Application Team - * @version V1.1.3 - * @date 05-March-2012 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F2xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral�s drivers in application code(i.e. - * code will be based on direct access to peripheral�s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral�s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx - * @{ - */ - -#ifndef __STM32F2xx_H -#define __STM32F2xx_H - -#define assert_param(xx) - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F2XX) - #define STM32F2XX -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (STM32F2XX) - #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief STM32F2XX Standard Peripherals Library version number V1.1.3 - */ -#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ -#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ -#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F2XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32F2XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F2XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "../../../../Include/core_cm3.h" -#include "system_stm32f2xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; /* added for STM32F2xx */ - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; /* added for STM32F2xx */ - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ -} FLASH_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< Reserved, 0x28 */ - uint32_t RESERVED2; /*!< Reserved, 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - uint32_t RESERVED3; /*!< Reserved, 0x38 */ - uint32_t RESERVED4; /*!< Reserved, 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - uint32_t RESERVED5; /*!< Reserved, 0x44 */ - uint32_t RESERVED6; /*!< Reserved, 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED11; /*!< Reserved, 0x46 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - uint16_t RESERVED14; /*!< Reserved, 0x52 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Crypto Processor - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ - __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ - __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ - __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ - __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ - __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ - __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ - __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ - __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ - __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ - __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ - __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ - __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ - __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ - __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ - __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ - __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ - __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ -} CRYP_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ -} HASH_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) -#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#if !defined WIN32 && defined __GNUC__ -#define CRC ((CRC_TypeDef *) CRC_BASE) -#endif -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define CRYP ((CRYP_TypeDef *) CRYP_BASE) -#define HASH ((HASH_TypeDef *) HASH_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!*/ - -#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!*/ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx + * @{ + */ + +#ifndef __STM32F2xx_H +#define __STM32F2xx_H + +#define assert_param(xx) + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F2XX) + #define STM32F2XX +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F2XX) + #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief STM32F2XX Standard Peripherals Library version number V1.1.3 + */ +#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F2XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32F2XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F2XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "../../../../Include/core_cm3.h" +#include "system_stm32f2xx.h" +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; /* added for STM32F2xx */ + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; /* added for STM32F2xx */ + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved, 0x38 */ + uint32_t RESERVED4; /*!< Reserved, 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + uint32_t RESERVED5; /*!< Reserved, 0x44 */ + uint32_t RESERVED6; /*!< Reserved, 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + uint16_t RESERVED11; /*!< Reserved, 0x46 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED12; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED13; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED14; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ +} HASH_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#if !defined WIN32 && defined __GNUC__ +#define CRC ((CRC_TypeDef *) CRC_BASE) +#endif +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!*/ + +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F2XX_H -#define __SYSTEM_STM32F2XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F2xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F2xx_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F2XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file system_stm32f2xx.h + * @author MCD Application Team + * @version V1.1.3 + * @date 05-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F2XX_H +#define __SYSTEM_STM32F2XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F2xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F2xx_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F2XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s index 2fa2d4149..14e568956 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s @@ -1,527 +1,527 @@ -/** - ****************************************************************************** - * @file startup_stm32f2xx.s - * @author MCD Application Team - * @version V1.1.3 - * @date 05-March-2012 - * @brief STM32F2xx Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the system clock and the external SRAM mounted on - * STM322xG-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/*Paint Main Stack */ - ldr r2, = _main_stack_start -PaintMainStack: - movs r3, #0x55555555 - str r3, [r2], #4 -LoopPaintMainStack: - ldr r3, = _estack - cmp r2, r3 - bcc PaintMainStack - -/* Call the clock system intitialization function.*/ - bl SystemInit - -/* Call C++ constructors for static objects */ - bl __libc_init_array - -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word CRYP_IRQHandler /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CRYP_IRQHandler - .thumb_set CRYP_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file startup_stm32f2xx.s + * @author MCD Application Team + * @version V1.1.3 + * @date 05-March-2012 + * @brief STM32F2xx Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock and the external SRAM mounted on + * STM322xG-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/*Paint Main Stack */ + ldr r2, = _main_stack_start +PaintMainStack: + movs r3, #0x55555555 + str r3, [r2], #4 +LoopPaintMainStack: + ldr r3, = _estack + cmp r2, r3 + bcc PaintMainStack + +/* Call the clock system intitialization function.*/ + bl SystemInit + +/* Call C++ constructors for static objects */ + bl __libc_init_array + +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_common_tables.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_common_tables.h index 34f910f9b..7245c4f12 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_common_tables.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_common_tables.h @@ -1,35 +1,35 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 11. November 2010 -* $Revision: V1.0.2 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern uint16_t armBitRevTable[256]; -extern q15_t armRecipTableQ15[64]; -extern q31_t armRecipTableQ31[64]; -extern const q31_t realCoefAQ31[1024]; -extern const q31_t realCoefBQ31[1024]; - -#endif /* ARM_COMMON_TABLES_H */ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 11. November 2010 +* $Revision: V1.0.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern uint16_t armBitRevTable[256]; +extern q15_t armRecipTableQ15[64]; +extern q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_math.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_math.h index d8901db15..ffa03b6fd 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_math.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_math.h @@ -1,7051 +1,7051 @@ -/* ---------------------------------------------------------------------- - * Copyright (C) 2010 ARM Limited. All rights reserved. - * - * $Date: 15. July 2011 - * $Revision: V1.0.10 - * - * Project: CMSIS DSP Library - * Title: arm_math.h - * - * Description: Public header file for CMSIS DSP Library - * - * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 - * - * Version 1.0.10 2011/7/15 - * Big Endian support added and Merged M0 and M3/M4 Source code. - * - * Version 1.0.3 2010/11/29 - * Re-organized the CMSIS folders and updated documentation. - * - * Version 1.0.2 2010/11/11 - * Documentation updated. - * - * Version 1.0.1 2010/10/05 - * Production release and review comments incorporated. - * - * Version 1.0.0 2010/09/20 - * Production release and review comments incorporated. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of modules each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Processor Support - * - * The library is completely written in C and is fully CMSIS compliant. - * High performance is achieved through maximum use of Cortex-M4 intrinsics. - * - * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, - * with the DSP intrinsics being emulated through software. - * - * - * Toolchain Support - * - * The library has been developed and tested with MDK-ARM version 4.21. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Using the Library - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 depending on the target processor in the application. - * - * Examples - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Building the Library - * - * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder. - * - arm_cortexM0b_math.uvproj - * - arm_cortexM0l_math.uvproj - * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj - * - arm_cortexM4b_math.uvproj - * - arm_cortexM4l_math.uvproj - * - arm_cortexM4bf_math.uvproj - * - arm_cortexM4lf_math.uvproj - * - * Each library project have differant pre-processor macros. - * - * ARM_MATH_CMx: - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target. - * - * ARM_MATH_BIG_ENDIAN: - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * ARM_MATH_MATRIX_CHECK: - * Define macro for checking on the input and output sizes of matrices - * - * ARM_MATH_ROUNDING: - * Define macro for rounding on support functions - * - * __FPU_PRESENT: - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - * - * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. - * - * Copyright Notice - * - * Copyright (C) 2010 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the #define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" - #include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#define PI 3.14159265358979f - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#define __SIMD32(addr) (*(int32_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ(q31_t data); - - - static __INLINE uint32_t __CLZ(q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return(count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0 */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) - - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) + - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) y)) + - ((short) x * (short) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - - -#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t *pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t *pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t *pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - #ifdef ARM_MATH_CM0 - q15_t A1; - q15_t A2; - #else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ - #endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; - float32_t x1; - float32_t xSpacing; - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - - /** - * @brief Processing function for the Q15 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Initialization function for the Q15 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Initialization function for the Q31 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point CFFT/CIFFT. - * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Initialization function for the floating-point CFFT/CIFFT. - * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - - - /*---------------------------------------------------------------------- - * Internal functions prototypes FFT function - ----------------------------------------------------------------------*/ - - /** - * @brief Core function for the floating-point CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to the twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the floating-point CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @param[in] onebyfftLen value of 1/fftLen. - * @return none. - */ - - void arm_radix4_butterfly_inverse_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier, - float32_t onebyfftLen); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftSize length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. - * @param[in] *pBitRevTab points to the bit reversal table. - * @return none. - */ - - void arm_bitreversal_f32( - float32_t *pSrc, - uint16_t fftSize, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q31 CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q31( - q31_t *pSrc, - uint32_t fftLen, - q31_t *pCoef, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q31 CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q31( - q31_t * pSrc, - uint32_t fftLen, - q31_t * pCoef, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q31( - q31_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q15 CFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q15 CIFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q15( - q15_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - /** - * @brief Processing function for the Q15 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Initialization function for the Q15 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Initialization function for the Q31 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Initialization function for the floating-point RFFT/RIFFT. - * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point RFFT/RIFFT. - * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t *pkCoeffs, - float32_t *pvCoeffs, - float32_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t *pkCoeffs, - q31_t *pvCoeffs, - q31_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t *pkCoeffs, - q15_t *pvCoeffs, - q15_t *pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t *pCoeffs, - q31_t *pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t *pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t *pSinVal, - float32_t *pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t *pSinVal, - q31_t *pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - - /* Implementation of PID controller */ - - #ifdef ARM_MATH_CM0 - - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0 )* in ; - - #else - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - #endif - - #ifdef ARM_MATH_CM0 - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0] ; - acc += (q31_t) S->A2 * S->state[1] ; - - #else - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); - - #endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (x - S->x1) / xSpacing; - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if(i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues-1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i +1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, - q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, float32_t *pOut) - { - if(in > 0) - { - -// #if __FPU_USED - #if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); - #else - *pOut = sqrtf(in); - #endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, q31_t *pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, q15_t *pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) - { - return(0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex-1) * S->numCols ; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex-1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * $Date: 15. July 2011 + * $Revision: V1.0.10 + * + * Project: CMSIS DSP Library + * Title: arm_math.h + * + * Description: Public header file for CMSIS DSP Library + * + * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 + * + * Version 1.0.10 2011/7/15 + * Big Endian support added and Merged M0 and M3/M4 Source code. + * + * Version 1.0.3 2010/11/29 + * Re-organized the CMSIS folders and updated documentation. + * + * Version 1.0.2 2010/11/11 + * Documentation updated. + * + * Version 1.0.1 2010/10/05 + * Production release and review comments incorporated. + * + * Version 1.0.0 2010/09/20 + * Production release and review comments incorporated. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of modules each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Processor Support + * + * The library is completely written in C and is fully CMSIS compliant. + * High performance is achieved through maximum use of Cortex-M4 intrinsics. + * + * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, + * with the DSP intrinsics being emulated through software. + * + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.21. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * Each library project have differant pre-processor macros. + * + * ARM_MATH_CMx: + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target. + * + * ARM_MATH_BIG_ENDIAN: + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * ARM_MATH_MATRIX_CHECK: + * Define macro for checking on the input and output sizes of matrices + * + * ARM_MATH_ROUNDING: + * Define macro for rounding on support functions + * + * __FPU_PRESENT: + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. + * + * Copyright Notice + * + * Copyright (C) 2010 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the #define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" + #include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#define PI 3.14159265358979f + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#define __SIMD32(addr) (*(int32_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ(q31_t data); + + + static __INLINE uint32_t __CLZ(q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return(count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0 */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (char) x; + s = (char) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (char) x; + s = (char) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t)(((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t)(((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + + +#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t *pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t *pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t *pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + #ifdef ARM_MATH_CM0 + q15_t A1; + q15_t A2; + #else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ + #endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; + float32_t x1; + float32_t xSpacing; + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + /** + * @brief Processing function for the Q15 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Initialization function for the Q15 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Initialization function for the Q31 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point CFFT/CIFFT. + * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Initialization function for the floating-point CFFT/CIFFT. + * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + + /*---------------------------------------------------------------------- + * Internal functions prototypes FFT function + ----------------------------------------------------------------------*/ + + /** + * @brief Core function for the floating-point CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to the twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the floating-point CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @param[in] onebyfftLen value of 1/fftLen. + * @return none. + */ + + void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftSize length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. + * @param[in] *pBitRevTab points to the bit reversal table. + * @return none. + */ + + void arm_bitreversal_f32( + float32_t *pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Core function for the Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q31( + q31_t *pSrc, + uint32_t fftLen, + q31_t *pCoef, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the Q31 CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Core function for the Q15 CFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q15( + q15_t *pSrc16, + uint32_t fftLen, + q15_t *pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the Q15 CIFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q15( + q15_t *pSrc16, + uint32_t fftLen, + q15_t *pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + /** + * @brief Processing function for the Q15 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Initialization function for the Q15 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Initialization function for the Q31 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Initialization function for the floating-point RFFT/RIFFT. + * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point RFFT/RIFFT. + * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t *pkCoeffs, + float32_t *pvCoeffs, + float32_t *pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t *pkCoeffs, + q31_t *pvCoeffs, + q31_t *pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t *pkCoeffs, + q15_t *pvCoeffs, + q15_t *pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t *pSinVal, + float32_t *pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t *pSinVal, + q31_t *pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + + /* Implementation of PID controller */ + + #ifdef ARM_MATH_CM0 + + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0 )* in ; + + #else + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + #endif + + #ifdef ARM_MATH_CM0 + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0] ; + acc += (q31_t) S->A2 * S->state[1] ; + + #else + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); + + #endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (x - S->x1) / xSpacing; + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if(i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues-1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i +1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, + q31_t x, uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, float32_t *pOut) + { + if(in > 0) + { + +// #if __FPU_USED + #if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, q31_t *pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, q15_t *pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) + { + return(0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex-1) * S->numCols ; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex-1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm0.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm0.h index edd522173..9d7a19f9a 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm0.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm0.h @@ -1,665 +1,665 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - - -/** \mainpage CMSIS Cortex-M0 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP - and not via processor. Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + + +/** \mainpage CMSIS Cortex-M0 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks */ +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP + and not via processor. Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm3.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm3.h index c6f976fd1..5d39ef86c 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm3.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm3.h @@ -1,1240 +1,1240 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - - -/** \mainpage CMSIS Cortex-M3 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#else - #define __INLINE - #define __DSB() - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + + +/** \mainpage CMSIS Cortex-M3 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#else + #define __INLINE + #define __DSB() + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks */ +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB + Type definitions for the Cortex-M System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ +#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4.h index 76bf8292a..bf022ba67 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4.h @@ -1,1378 +1,1378 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - - -/** \mainpage CMSIS Cortex-M4 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - Cortex-M SIMD instructions - - The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks to define __FPU_USED */ - #define __FPU_USED 0 -#endif - -#include /*!< standard types definitions */ -#include /*!< Core Instruction Access */ -#include /*!< Core Function Access */ -#include /*!< Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU CMSIS FPU - Type definitions for the Cortex-M Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + + +/** \mainpage CMSIS Cortex-M4 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + - Cortex-M SIMD instructions + + The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks to define __FPU_USED */ + #define __FPU_USED 0 +#endif + +#include /*!< standard types definitions */ +#include /*!< Core Instruction Access */ +#include /*!< Core Function Access */ +#include /*!< Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB + Type definitions for the Cortex-M System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ +#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU CMSIS FPU + Type definitions for the Cortex-M Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4_simd.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4_simd.h index 479188696..e7b676522 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4_simd.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4_simd.h @@ -1,701 +1,701 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/ -/* intrinsic __SADD8 see intrinsics.h */ -/* intrinsic __QADD8 see intrinsics.h */ -/* intrinsic __SHADD8 see intrinsics.h */ -/* intrinsic __UADD8 see intrinsics.h */ -/* intrinsic __UQADD8 see intrinsics.h */ -/* intrinsic __UHADD8 see intrinsics.h */ -/* intrinsic __SSUB8 see intrinsics.h */ -/* intrinsic __QSUB8 see intrinsics.h */ -/* intrinsic __SHSUB8 see intrinsics.h */ -/* intrinsic __USUB8 see intrinsics.h */ -/* intrinsic __UQSUB8 see intrinsics.h */ -/* intrinsic __UHSUB8 see intrinsics.h */ -/* intrinsic __SADD16 see intrinsics.h */ -/* intrinsic __QADD16 see intrinsics.h */ -/* intrinsic __SHADD16 see intrinsics.h */ -/* intrinsic __UADD16 see intrinsics.h */ -/* intrinsic __UQADD16 see intrinsics.h */ -/* intrinsic __UHADD16 see intrinsics.h */ -/* intrinsic __SSUB16 see intrinsics.h */ -/* intrinsic __QSUB16 see intrinsics.h */ -/* intrinsic __SHSUB16 see intrinsics.h */ -/* intrinsic __USUB16 see intrinsics.h */ -/* intrinsic __UQSUB16 see intrinsics.h */ -/* intrinsic __UHSUB16 see intrinsics.h */ -/* intrinsic __SASX see intrinsics.h */ -/* intrinsic __QASX see intrinsics.h */ -/* intrinsic __SHASX see intrinsics.h */ -/* intrinsic __UASX see intrinsics.h */ -/* intrinsic __UQASX see intrinsics.h */ -/* intrinsic __UHASX see intrinsics.h */ -/* intrinsic __SSAX see intrinsics.h */ -/* intrinsic __QSAX see intrinsics.h */ -/* intrinsic __SHSAX see intrinsics.h */ -/* intrinsic __USAX see intrinsics.h */ -/* intrinsic __UQSAX see intrinsics.h */ -/* intrinsic __UHSAX see intrinsics.h */ -/* intrinsic __USAD8 see intrinsics.h */ -/* intrinsic __USADA8 see intrinsics.h */ -/* intrinsic __SSAT16 see intrinsics.h */ -/* intrinsic __USAT16 see intrinsics.h */ -/* intrinsic __UXTB16 see intrinsics.h */ -/* intrinsic __SXTB16 see intrinsics.h */ -/* intrinsic __UXTAB16 see intrinsics.h */ -/* intrinsic __SXTAB16 see intrinsics.h */ -/* intrinsic __SMUAD see intrinsics.h */ -/* intrinsic __SMUADX see intrinsics.h */ -/* intrinsic __SMLAD see intrinsics.h */ -/* intrinsic __SMLADX see intrinsics.h */ -/* intrinsic __SMLALD see intrinsics.h */ -/* intrinsic __SMLALDX see intrinsics.h */ -/* intrinsic __SMUSD see intrinsics.h */ -/* intrinsic __SMUSDX see intrinsics.h */ -/* intrinsic __SMLSD see intrinsics.h */ -/* intrinsic __SMLSDX see intrinsics.h */ -/* intrinsic __SMLSLD see intrinsics.h */ -/* intrinsic __SMLSLDX see intrinsics.h */ -/* intrinsic __SEL see intrinsics.h */ -/* intrinsic __QADD see intrinsics.h */ -/* intrinsic __QSUB see intrinsics.h */ -/* intrinsic __PKHBT see intrinsics.h */ -/* intrinsic __PKHTB see intrinsics.h */ - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/ +/* intrinsic __SADD8 see intrinsics.h */ +/* intrinsic __QADD8 see intrinsics.h */ +/* intrinsic __SHADD8 see intrinsics.h */ +/* intrinsic __UADD8 see intrinsics.h */ +/* intrinsic __UQADD8 see intrinsics.h */ +/* intrinsic __UHADD8 see intrinsics.h */ +/* intrinsic __SSUB8 see intrinsics.h */ +/* intrinsic __QSUB8 see intrinsics.h */ +/* intrinsic __SHSUB8 see intrinsics.h */ +/* intrinsic __USUB8 see intrinsics.h */ +/* intrinsic __UQSUB8 see intrinsics.h */ +/* intrinsic __UHSUB8 see intrinsics.h */ +/* intrinsic __SADD16 see intrinsics.h */ +/* intrinsic __QADD16 see intrinsics.h */ +/* intrinsic __SHADD16 see intrinsics.h */ +/* intrinsic __UADD16 see intrinsics.h */ +/* intrinsic __UQADD16 see intrinsics.h */ +/* intrinsic __UHADD16 see intrinsics.h */ +/* intrinsic __SSUB16 see intrinsics.h */ +/* intrinsic __QSUB16 see intrinsics.h */ +/* intrinsic __SHSUB16 see intrinsics.h */ +/* intrinsic __USUB16 see intrinsics.h */ +/* intrinsic __UQSUB16 see intrinsics.h */ +/* intrinsic __UHSUB16 see intrinsics.h */ +/* intrinsic __SASX see intrinsics.h */ +/* intrinsic __QASX see intrinsics.h */ +/* intrinsic __SHASX see intrinsics.h */ +/* intrinsic __UASX see intrinsics.h */ +/* intrinsic __UQASX see intrinsics.h */ +/* intrinsic __UHASX see intrinsics.h */ +/* intrinsic __SSAX see intrinsics.h */ +/* intrinsic __QSAX see intrinsics.h */ +/* intrinsic __SHSAX see intrinsics.h */ +/* intrinsic __USAX see intrinsics.h */ +/* intrinsic __UQSAX see intrinsics.h */ +/* intrinsic __UHSAX see intrinsics.h */ +/* intrinsic __USAD8 see intrinsics.h */ +/* intrinsic __USADA8 see intrinsics.h */ +/* intrinsic __SSAT16 see intrinsics.h */ +/* intrinsic __USAT16 see intrinsics.h */ +/* intrinsic __UXTB16 see intrinsics.h */ +/* intrinsic __SXTB16 see intrinsics.h */ +/* intrinsic __UXTAB16 see intrinsics.h */ +/* intrinsic __SXTAB16 see intrinsics.h */ +/* intrinsic __SMUAD see intrinsics.h */ +/* intrinsic __SMUADX see intrinsics.h */ +/* intrinsic __SMLAD see intrinsics.h */ +/* intrinsic __SMLADX see intrinsics.h */ +/* intrinsic __SMLALD see intrinsics.h */ +/* intrinsic __SMLALDX see intrinsics.h */ +/* intrinsic __SMUSD see intrinsics.h */ +/* intrinsic __SMUSDX see intrinsics.h */ +/* intrinsic __SMLSD see intrinsics.h */ +/* intrinsic __SMLSDX see intrinsics.h */ +/* intrinsic __SMLSLD see intrinsics.h */ +/* intrinsic __SMLSLDX see intrinsics.h */ +/* intrinsic __SEL see intrinsics.h */ +/* intrinsic __QADD see intrinsics.h */ +/* intrinsic __QSUB see intrinsics.h */ +/* intrinsic __PKHBT see intrinsics.h */ +/* intrinsic __PKHTB see intrinsics.h */ + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmFunc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmFunc.h index c999b1c83..88819f9dd 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmFunc.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmFunc.h @@ -1,609 +1,609 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V2.10 - * @date 26. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -static __INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -static __INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -static __INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V2.10 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmInstr.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmInstr.h index ceb4f8756..78d2ef80b 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmInstr.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmInstr.h @@ -1,585 +1,585 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h index 1f18fc8dd..bd5e4f52e 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h @@ -1,178 +1,178 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be an enumerator of @ref IRQn_Type - enumeration (For the complete STM32 Devices IRQ Channels - list, please refer to stm32f2xx.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup MISC_Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup MISC_System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup MISC_Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup MISC_SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be an enumerator of @ref IRQn_Type + enumeration (For the complete STM32 Devices IRQ Channels + list, please refer to stm32f2xx.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup MISC_Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup MISC_System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup MISC_Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup MISC_SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h index 2b80ad325..4dae8c173 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h @@ -1,649 +1,649 @@ -/** - ****************************************************************************** - * @file stm32f2xx_adc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_ADC_H -#define __STM32F2xx_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief ADC Init structure definition - */ -typedef struct -{ - uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. - This parameter can be a value of @ref ADC_resolution */ - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion - is performed in Scan (multichannels) - or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion - is performed in Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and - enable the trigger of a regular group. - This parameter can be a value of - @ref ADC_external_trigger_edge_for_regular_channels_conversion */ - uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger - the start of conversion of a regular group. - This parameter can be a value of - @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment - is left or right. This parameter can be - a value of @ref ADC_data_align */ - uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions - that will be done using the sequencer for - regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; - -/** - * @brief ADC Common Init structure definition - */ -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in - independent or multi mode. - This parameter can be a value of @ref ADC_Common_mode */ - uint32_t ADC_Prescaler; /*!< Select the frequency of the clock - to the ADC. The clock is common for all the ADCs. - This parameter can be a value of @ref ADC_Prescaler */ - uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access - mode for multi ADC mode. - This parameter can be a value of - @ref ADC_Direct_memory_access_mode_for_multi_mode */ - uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value of - @ref ADC_delay_between_2_sampling_phases */ - -}ADC_CommonInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants - * @{ - */ -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_Common_mode - * @{ - */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) -#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) -#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) -#define ADC_DualMode_RegSimult ((uint32_t)0x00000006) -#define ADC_DualMode_Interl ((uint32_t)0x00000007) -#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) -#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) -#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) -#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) -#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) -#define ADC_TripleMode_Interl ((uint32_t)0x00000017) -#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_DualMode_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult) || \ - ((MODE) == ADC_DualMode_Interl) || \ - ((MODE) == ADC_DualMode_AlterTrig) || \ - ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_TripleMode_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult) || \ - ((MODE) == ADC_TripleMode_Interl) || \ - ((MODE) == ADC_TripleMode_AlterTrig)) -/** - * @} - */ - - -/** @defgroup ADC_Prescaler - * @{ - */ -#define ADC_Prescaler_Div2 ((uint32_t)0x00000000) -#define ADC_Prescaler_Div4 ((uint32_t)0x00010000) -#define ADC_Prescaler_Div6 ((uint32_t)0x00020000) -#define ADC_Prescaler_Div8 ((uint32_t)0x00030000) -#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ - ((PRESCALER) == ADC_Prescaler_Div4) || \ - ((PRESCALER) == ADC_Prescaler_Div6) || \ - ((PRESCALER) == ADC_Prescaler_Div8)) -/** - * @} - */ - - -/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode - * @{ - */ -#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ -#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ -#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ -#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ -#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ - ((MODE) == ADC_DMAAccessMode_1) || \ - ((MODE) == ADC_DMAAccessMode_2) || \ - ((MODE) == ADC_DMAAccessMode_3)) - -/** - * @} - */ - - -/** @defgroup ADC_delay_between_2_sampling_phases - * @{ - */ -#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) -#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) -#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) -#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) -#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) -#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) -#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) -#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) -#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) -#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) -#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) -#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) -#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) -#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) -#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) -#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) -#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) - -/** - * @} - */ - - -/** @defgroup ADC_resolution - * @{ - */ -#define ADC_Resolution_12b ((uint32_t)0x00000000) -#define ADC_Resolution_10b ((uint32_t)0x01000000) -#define ADC_Resolution_8b ((uint32_t)0x02000000) -#define ADC_Resolution_6b ((uint32_t)0x03000000) -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ - ((RESOLUTION) == ADC_Resolution_10b) || \ - ((RESOLUTION) == ADC_Resolution_8b) || \ - ((RESOLUTION) == ADC_Resolution_6b)) - -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) -#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) -#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) -#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) -#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) -#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) -#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) -#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) -/** - * @} - */ - - -/** @defgroup ADC_data_align - * @{ - */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - - -/** @defgroup ADC_channels - * @{ - */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) -#define ADC_Channel_18 ((uint8_t)0x12) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) -#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ - ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || \ - ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || \ - ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || \ - ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || \ - ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || \ - ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || \ - ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || \ - ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || \ - ((CHANNEL) == ADC_Channel_17) || \ - ((CHANNEL) == ADC_Channel_18)) -/** - * @} - */ - - -/** @defgroup ADC_sampling_times - * @{ - */ -#define ADC_SampleTime_3Cycles ((uint8_t)0x00) -#define ADC_SampleTime_15Cycles ((uint8_t)0x01) -#define ADC_SampleTime_28Cycles ((uint8_t)0x02) -#define ADC_SampleTime_56Cycles ((uint8_t)0x03) -#define ADC_SampleTime_84Cycles ((uint8_t)0x04) -#define ADC_SampleTime_112Cycles ((uint8_t)0x05) -#define ADC_SampleTime_144Cycles ((uint8_t)0x06) -#define ADC_SampleTime_480Cycles ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ - ((TIME) == ADC_SampleTime_15Cycles) || \ - ((TIME) == ADC_SampleTime_28Cycles) || \ - ((TIME) == ADC_SampleTime_56Cycles) || \ - ((TIME) == ADC_SampleTime_84Cycles) || \ - ((TIME) == ADC_SampleTime_112Cycles) || \ - ((TIME) == ADC_SampleTime_144Cycles) || \ - ((TIME) == ADC_SampleTime_480Cycles)) -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) -#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) -#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) -#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) - -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) -#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) -#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) -#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) -#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) -#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) -/** - * @} - */ - - -/** @defgroup ADC_injected_channel_selection - * @{ - */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - - -/** @defgroup ADC_interrupts_definition - * @{ - */ -#define ADC_IT_EOC ((uint16_t)0x0205) -#define ADC_IT_AWD ((uint16_t)0x0106) -#define ADC_IT_JEOC ((uint16_t)0x0407) -#define ADC_IT_OVR ((uint16_t)0x201A) -#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_flags_definition - * @{ - */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define ADC_FLAG_OVR ((uint8_t)0x20) - -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ - ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || \ - ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT) || \ - ((FLAG)== ADC_FLAG_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_thresholds - * @{ - */ -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_offset - * @{ - */ -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_length - * @{ - */ -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_injected_rank - * @{ - */ -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_rank - * @{ - */ -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the ADC configuration to the default reset state *****/ -void ADC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Analog Watchdog configuration functions ************************************/ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); - -/* Temperature Sensor, Vrefint and VBAT management functions ******************/ -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -void ADC_VBATCmd(FunctionalState NewState); - -/* Regular Channels Configuration functions ***********************************/ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetMultiModeConversionValue(void); - -/* Regular Channels DMA Configuration functions *******************************/ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); - -/* Injected channels Configuration functions **********************************/ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); - -/* Interrupts and flags management functions **********************************/ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_adc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the ADC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_ADC_H +#define __STM32F2xx_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief ADC Init structure definition + */ +typedef struct +{ + uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. + This parameter can be a value of @ref ADC_resolution */ + FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion + is performed in Scan (multichannels) + or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion + is performed in Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and + enable the trigger of a regular group. + This parameter can be a value of + @ref ADC_external_trigger_edge_for_regular_channels_conversion */ + uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger + the start of conversion of a regular group. + This parameter can be a value of + @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment + is left or right. This parameter can be + a value of @ref ADC_data_align */ + uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions + that will be done using the sequencer for + regular channel group. + This parameter must range from 1 to 16. */ +}ADC_InitTypeDef; + +/** + * @brief ADC Common Init structure definition + */ +typedef struct +{ + uint32_t ADC_Mode; /*!< Configures the ADC to operate in + independent or multi mode. + This parameter can be a value of @ref ADC_Common_mode */ + uint32_t ADC_Prescaler; /*!< Select the frequency of the clock + to the ADC. The clock is common for all the ADCs. + This parameter can be a value of @ref ADC_Prescaler */ + uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access + mode for multi ADC mode. + This parameter can be a value of + @ref ADC_Direct_memory_access_mode_for_multi_mode */ + uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. + This parameter can be a value of + @ref ADC_delay_between_2_sampling_phases */ + +}ADC_CommonInitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants + * @{ + */ +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) + +/** @defgroup ADC_Common_mode + * @{ + */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) +#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) +#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) +#define ADC_DualMode_RegSimult ((uint32_t)0x00000006) +#define ADC_DualMode_Interl ((uint32_t)0x00000007) +#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) +#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) +#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) +#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) +#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) +#define ADC_TripleMode_Interl ((uint32_t)0x00000017) +#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ + ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_DualMode_InjecSimult) || \ + ((MODE) == ADC_DualMode_RegSimult) || \ + ((MODE) == ADC_DualMode_Interl) || \ + ((MODE) == ADC_DualMode_AlterTrig) || \ + ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ + ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_TripleMode_InjecSimult) || \ + ((MODE) == ADC_TripleMode_RegSimult) || \ + ((MODE) == ADC_TripleMode_Interl) || \ + ((MODE) == ADC_TripleMode_AlterTrig)) +/** + * @} + */ + + +/** @defgroup ADC_Prescaler + * @{ + */ +#define ADC_Prescaler_Div2 ((uint32_t)0x00000000) +#define ADC_Prescaler_Div4 ((uint32_t)0x00010000) +#define ADC_Prescaler_Div6 ((uint32_t)0x00020000) +#define ADC_Prescaler_Div8 ((uint32_t)0x00030000) +#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ + ((PRESCALER) == ADC_Prescaler_Div4) || \ + ((PRESCALER) == ADC_Prescaler_Div6) || \ + ((PRESCALER) == ADC_Prescaler_Div8)) +/** + * @} + */ + + +/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode + * @{ + */ +#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ +#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ +#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ +#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ +#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ + ((MODE) == ADC_DMAAccessMode_1) || \ + ((MODE) == ADC_DMAAccessMode_2) || \ + ((MODE) == ADC_DMAAccessMode_3)) + +/** + * @} + */ + + +/** @defgroup ADC_delay_between_2_sampling_phases + * @{ + */ +#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) +#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) +#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) +#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) +#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) +#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) +#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) +#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) +#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) +#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) +#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) +#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) +#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) +#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) +#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) +#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) +#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) + +/** + * @} + */ + + +/** @defgroup ADC_resolution + * @{ + */ +#define ADC_Resolution_12b ((uint32_t)0x00000000) +#define ADC_Resolution_10b ((uint32_t)0x01000000) +#define ADC_Resolution_8b ((uint32_t)0x02000000) +#define ADC_Resolution_6b ((uint32_t)0x03000000) +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ + ((RESOLUTION) == ADC_Resolution_10b) || \ + ((RESOLUTION) == ADC_Resolution_8b) || \ + ((RESOLUTION) == ADC_Resolution_6b)) + +/** + * @} + */ + + +/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion + * @{ + */ +#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) +#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) +#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) +#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) +#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) +/** + * @} + */ + + +/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion + * @{ + */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) +#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) +#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) +#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) +/** + * @} + */ + + +/** @defgroup ADC_data_align + * @{ + */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + + +/** @defgroup ADC_channels + * @{ + */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) +#define ADC_Channel_18 ((uint8_t)0x12) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) +#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ + ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || \ + ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || \ + ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || \ + ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || \ + ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || \ + ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || \ + ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || \ + ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || \ + ((CHANNEL) == ADC_Channel_17) || \ + ((CHANNEL) == ADC_Channel_18)) +/** + * @} + */ + + +/** @defgroup ADC_sampling_times + * @{ + */ +#define ADC_SampleTime_3Cycles ((uint8_t)0x00) +#define ADC_SampleTime_15Cycles ((uint8_t)0x01) +#define ADC_SampleTime_28Cycles ((uint8_t)0x02) +#define ADC_SampleTime_56Cycles ((uint8_t)0x03) +#define ADC_SampleTime_84Cycles ((uint8_t)0x04) +#define ADC_SampleTime_112Cycles ((uint8_t)0x05) +#define ADC_SampleTime_144Cycles ((uint8_t)0x06) +#define ADC_SampleTime_480Cycles ((uint8_t)0x07) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ + ((TIME) == ADC_SampleTime_15Cycles) || \ + ((TIME) == ADC_SampleTime_28Cycles) || \ + ((TIME) == ADC_SampleTime_56Cycles) || \ + ((TIME) == ADC_SampleTime_84Cycles) || \ + ((TIME) == ADC_SampleTime_112Cycles) || \ + ((TIME) == ADC_SampleTime_144Cycles) || \ + ((TIME) == ADC_SampleTime_480Cycles)) +/** + * @} + */ + + +/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion + * @{ + */ +#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) +#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) +#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) +#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) + +/** + * @} + */ + + +/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion + * @{ + */ +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) +#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) +#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) +#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) +/** + * @} + */ + + +/** @defgroup ADC_injected_channel_selection + * @{ + */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) +/** + * @} + */ + + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** + * @} + */ + + +/** @defgroup ADC_interrupts_definition + * @{ + */ +#define ADC_IT_EOC ((uint16_t)0x0205) +#define ADC_IT_AWD ((uint16_t)0x0106) +#define ADC_IT_JEOC ((uint16_t)0x0407) +#define ADC_IT_OVR ((uint16_t)0x201A) +#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) +/** + * @} + */ + + +/** @defgroup ADC_flags_definition + * @{ + */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) +#define ADC_FLAG_OVR ((uint8_t)0x20) + +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ + ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || \ + ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT) || \ + ((FLAG)== ADC_FLAG_OVR)) +/** + * @} + */ + + +/** @defgroup ADC_thresholds + * @{ + */ +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) +/** + * @} + */ + + +/** @defgroup ADC_injected_offset + * @{ + */ +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) +/** + * @} + */ + + +/** @defgroup ADC_injected_length + * @{ + */ +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) +/** + * @} + */ + + +/** @defgroup ADC_injected_rank + * @{ + */ +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) +/** + * @} + */ + + +/** @defgroup ADC_regular_length + * @{ + */ +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + + +/** @defgroup ADC_regular_rank + * @{ + */ +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) +/** + * @} + */ + + +/** @defgroup ADC_regular_discontinuous_mode_number + * @{ + */ +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the ADC configuration to the default reset state *****/ +void ADC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); +void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +/* Analog Watchdog configuration functions ************************************/ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); + +/* Temperature Sensor, Vrefint and VBAT management functions ******************/ +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +void ADC_VBATCmd(FunctionalState NewState); + +/* Regular Channels Configuration functions ***********************************/ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetMultiModeConversionValue(void); + +/* Regular Channels DMA Configuration functions *******************************/ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); + +/* Injected channels Configuration functions **********************************/ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); +void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); + +/* Interrupts and flags management functions **********************************/ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_can.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_can.h index 42cfdedf8..ba287d77a 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_can.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_can.h @@ -1,644 +1,644 @@ -/** - ****************************************************************************** - * @file stm32f2xx_can.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the CAN firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_CAN_H -#define __STM32F2xx_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ - ((PERIPH) == CAN2)) - -/** - * @brief CAN init structure definition - */ -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_InitStatus - * @{ - */ - -#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ - - -/* Legacy defines */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -/** - * @} - */ - -/** @defgroup CAN_operating_mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ - ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || \ - ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - - - /** - * @defgroup CAN_operating_mode - * @{ - */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ - - -#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ - ((MODE) == CAN_OperatingMode_Normal)|| \ - ((MODE) == CAN_OperatingMode_Sleep)) -/** - * @} - */ - -/** - * @defgroup CAN_operating_mode_status - * @{ - */ - -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) - -/* Legacy defines */ -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -/** - * @} - */ - -/** @defgroup CAN_Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ -#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ - ((IDTYPE) == CAN_Id_Extended)) - -/* Legacy defines */ -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ -#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) - -/* Legacy defines */ -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ -#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide - an empty mailbox */ -/* Legacy defines */ -#define CANTXFAILED CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ -#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/* Legacy defines */ -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ -#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/* Legacy defines */ -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok -/** - * @} - */ - -/** - * @defgroup CAN_Error_Code_constants - * @{ - */ -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ - -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ - -#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ - ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ - ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ - ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_SLAK )) - -#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ - ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) -/** - * @} - */ - - -/** @defgroup CAN_interrupts - * @{ - */ -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CAN configuration to the default reset state *****/ -void CAN_DeInit(CAN_TypeDef* CANx); - -/* Initialization and Configuration functions *********************************/ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); - -/* CAN Frames Transmission functions ******************************************/ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); - -/* CAN Frames Reception functions *********************************************/ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); - -/* Operation modes functions **************************************************/ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); - -/* CAN Bus Error management functions *****************************************/ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); - -/* Interrupts and flags management functions **********************************/ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_CAN_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_can.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the CAN firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CAN_H +#define __STM32F2xx_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ + ((PERIPH) == CAN2)) + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_InitTypeDef; + +/** + * @brief CAN filter init structure definition + */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Constants + * @{ + */ + +/** @defgroup CAN_InitStatus + * @{ + */ + +#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ + + +/* Legacy defines */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +/** + * @} + */ + +/** @defgroup CAN_operating_mode + * @{ + */ + +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ + ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || \ + ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + + + /** + * @defgroup CAN_operating_mode + * @{ + */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ + + +#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ + ((MODE) == CAN_OperatingMode_Normal)|| \ + ((MODE) == CAN_OperatingMode_Sleep)) +/** + * @} + */ + +/** + * @defgroup CAN_operating_mode_status + * @{ + */ + +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ +#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ +#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler + * @{ + */ +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) +/** + * @} + */ + +/** @defgroup CAN_filter_number + * @{ + */ +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +/** + * @} + */ + +/** @defgroup CAN_filter_mode + * @{ + */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale + * @{ + */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO + * @{ + */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) + +/* Legacy defines */ +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +/** + * @} + */ + +/** @defgroup CAN_Start_bank_filter_for_slave_CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) +/** + * @} + */ + +/** @defgroup CAN_Tx + * @{ + */ +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) +/** + * @} + */ + +/** @defgroup CAN_identifier_type + * @{ + */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ + ((IDTYPE) == CAN_Id_Extended)) + +/* Legacy defines */ +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request + * @{ + */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) + +/* Legacy defines */ +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +/** + * @} + */ + +/** @defgroup CAN_transmit_constants + * @{ + */ +#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide + an empty mailbox */ +/* Legacy defines */ +#define CANTXFAILED CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +/** + * @} + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/* Legacy defines */ +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +/** + * @} + */ + +/** @defgroup CAN_wake_up_constants + * @{ + */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/* Legacy defines */ +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok +/** + * @} + */ + +/** + * @defgroup CAN_Error_Code_constants + * @{ + */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ +/** + * @} + */ + +/** @defgroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ + ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ + ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ + ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_SLAK )) + +#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ + ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + + +/** @defgroup CAN_interrupts + * @{ + */ +#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + + +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the CAN configuration to the default reset state *****/ +void CAN_DeInit(CAN_TypeDef* CANx); + +/* Initialization and Configuration functions *********************************/ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); + +/* CAN Frames Transmission functions ******************************************/ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); + +/* CAN Frames Reception functions *********************************************/ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); + +/* CAN Bus Error management functions *****************************************/ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_CAN_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_crc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_crc.h index 725c581f5..3361bbccb 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_crc.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_crc.h @@ -1,83 +1,83 @@ -/** - ****************************************************************************** - * @file stm32f2xx_crc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_CRC_H -#define __STM32F2xx_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRC_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_CRC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_crc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CRC_H +#define __STM32F2xx_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_CRC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_cryp.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_cryp.h index 893e92586..e0b45016f 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_cryp.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_cryp.h @@ -1,344 +1,344 @@ -/** - ****************************************************************************** - * @file stm32f2xx_cryp.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the Cryptographic - * processor(CRYP) firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_CRYP_H -#define __STM32F2xx_CRYP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRYP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief CRYP Init structure definition - */ -typedef struct -{ - uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a - value of @ref CRYP_Algorithm_Direction */ - uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, - AES-CBC, AES-CTR, AES-Key. This parameter can be - a value of @ref CRYP_Algorithm_Mode */ - uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string. - This parameter can be a value of @ref CRYP_Data_Type */ - uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit - key length. This parameter can be a value of - @ref CRYP_Key_Size_for_AES_only */ -}CRYP_InitTypeDef; - -/** - * @brief CRYP Key(s) structure definition - */ -typedef struct -{ - uint32_t CRYP_Key0Left; /*!< Key 0 Left */ - uint32_t CRYP_Key0Right; /*!< Key 0 Right */ - uint32_t CRYP_Key1Left; /*!< Key 1 left */ - uint32_t CRYP_Key1Right; /*!< Key 1 Right */ - uint32_t CRYP_Key2Left; /*!< Key 2 left */ - uint32_t CRYP_Key2Right; /*!< Key 2 Right */ - uint32_t CRYP_Key3Left; /*!< Key 3 left */ - uint32_t CRYP_Key3Right; /*!< Key 3 Right */ -}CRYP_KeyInitTypeDef; -/** - * @brief CRYP Initialization Vectors (IV) structure definition - */ -typedef struct -{ - uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */ - uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */ - uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */ - uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */ -}CRYP_IVInitTypeDef; - -/** - * @brief CRYP context swapping structure definition - */ -typedef struct -{ - /*!< Configuration */ - uint32_t CR_bits9to2; - /*!< KEY */ - uint32_t CRYP_IV0LR; - uint32_t CRYP_IV0RR; - uint32_t CRYP_IV1LR; - uint32_t CRYP_IV1RR; - /*!< IV */ - uint32_t CRYP_K0LR; - uint32_t CRYP_K0RR; - uint32_t CRYP_K1LR; - uint32_t CRYP_K1RR; - uint32_t CRYP_K2LR; - uint32_t CRYP_K2RR; - uint32_t CRYP_K3LR; - uint32_t CRYP_K3RR; -}CRYP_Context; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRYP_Exported_Constants - * @{ - */ - -/** @defgroup CRYP_Algorithm_Direction - * @{ - */ -#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000) -#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004) -#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \ - ((ALGODIR) == CRYP_AlgoDir_Decrypt)) - -/** - * @} - */ - -/** @defgroup CRYP_Algorithm_Mode - * @{ - */ - -/*!< TDES Modes */ -#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000) -#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008) - -/*!< DES Modes */ -#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010) -#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018) - -/*!< AES Modes */ -#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020) -#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028) -#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030) -#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038) - -#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ - ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \ - ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_Key)) -/** - * @} - */ - -/** @defgroup CRYP_Data_Type - * @{ - */ -#define CRYP_DataType_32b ((uint16_t)0x0000) -#define CRYP_DataType_16b ((uint16_t)0x0040) -#define CRYP_DataType_8b ((uint16_t)0x0080) -#define CRYP_DataType_1b ((uint16_t)0x00C0) -#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \ - ((DATATYPE) == CRYP_DataType_16b)|| \ - ((DATATYPE) == CRYP_DataType_8b)|| \ - ((DATATYPE) == CRYP_DataType_1b)) -/** - * @} - */ - -/** @defgroup CRYP_Key_Size_for_AES_only - * @{ - */ -#define CRYP_KeySize_128b ((uint16_t)0x0000) -#define CRYP_KeySize_192b ((uint16_t)0x0100) -#define CRYP_KeySize_256b ((uint16_t)0x0200) -#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \ - ((KEYSIZE) == CRYP_KeySize_192b)|| \ - ((KEYSIZE) == CRYP_KeySize_256b)) -/** - * @} - */ - -/** @defgroup CRYP_flags_definition - * @{ - */ -#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently - processing a block of data - or a key preparation (for - AES decryption). */ -#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */ -#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */ -#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */ -#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw - interrupt status */ -#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */ -#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw - interrupt status */ - -#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \ - ((FLAG) == CRYP_FLAG_IFNF) || \ - ((FLAG) == CRYP_FLAG_OFNE) || \ - ((FLAG) == CRYP_FLAG_OFFU) || \ - ((FLAG) == CRYP_FLAG_BUSY) || \ - ((FLAG) == CRYP_FLAG_OUTRIS)|| \ - ((FLAG) == CRYP_FLAG_INRIS)) -/** - * @} - */ - -/** @defgroup CRYP_interrupts_definition - * @{ - */ -#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */ -#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */ -#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) -#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI)) - -/** - * @} - */ - -/** @defgroup CRYP_Encryption_Decryption_modes_definition - * @{ - */ -#define MODE_ENCRYPT ((uint8_t)0x01) -#define MODE_DECRYPT ((uint8_t)0x00) - -/** - * @} - */ - -/** @defgroup CRYP_DMA_transfer_requests - * @{ - */ -#define CRYP_DMAReq_DataIN ((uint8_t)0x01) -#define CRYP_DMAReq_DataOUT ((uint8_t)0x02) -#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CRYP configuration to the default reset state ****/ -void CRYP_DeInit(void); - -/* CRYP Initialization and Configuration functions ****************************/ -void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct); -void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct); -void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); -void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); -void CRYP_Cmd(FunctionalState NewState); - -/* CRYP Data processing functions *********************************************/ -void CRYP_DataIn(uint32_t Data); -uint32_t CRYP_DataOut(void); -void CRYP_FIFOFlush(void); - -/* CRYP Context swapping functions ********************************************/ -ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, - CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); - -/* CRYP's DMA interface function **********************************************/ -void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); -ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); -FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); - -/* High Level AES functions **************************************************/ -ErrorStatus CRYP_AES_ECB(uint8_t Mode, - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_CBC(uint8_t Mode, - uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_CTR(uint8_t Mode, - uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -/* High Level TDES functions **************************************************/ -ErrorStatus CRYP_TDES_ECB(uint8_t Mode, - uint8_t Key[24], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_TDES_CBC(uint8_t Mode, - uint8_t Key[24], - uint8_t InitVectors[8], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -/* High Level DES functions **************************************************/ -ErrorStatus CRYP_DES_ECB(uint8_t Mode, - uint8_t Key[8], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_DES_CBC(uint8_t Mode, - uint8_t Key[8], - uint8_t InitVectors[8], - uint8_t *Input,uint32_t Ilength, - uint8_t *Output); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_CRYP_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_cryp.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the Cryptographic + * processor(CRYP) firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CRYP_H +#define __STM32F2xx_CRYP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRYP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief CRYP Init structure definition + */ +typedef struct +{ + uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a + value of @ref CRYP_Algorithm_Direction */ + uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, + AES-CBC, AES-CTR, AES-Key. This parameter can be + a value of @ref CRYP_Algorithm_Mode */ + uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string. + This parameter can be a value of @ref CRYP_Data_Type */ + uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit + key length. This parameter can be a value of + @ref CRYP_Key_Size_for_AES_only */ +}CRYP_InitTypeDef; + +/** + * @brief CRYP Key(s) structure definition + */ +typedef struct +{ + uint32_t CRYP_Key0Left; /*!< Key 0 Left */ + uint32_t CRYP_Key0Right; /*!< Key 0 Right */ + uint32_t CRYP_Key1Left; /*!< Key 1 left */ + uint32_t CRYP_Key1Right; /*!< Key 1 Right */ + uint32_t CRYP_Key2Left; /*!< Key 2 left */ + uint32_t CRYP_Key2Right; /*!< Key 2 Right */ + uint32_t CRYP_Key3Left; /*!< Key 3 left */ + uint32_t CRYP_Key3Right; /*!< Key 3 Right */ +}CRYP_KeyInitTypeDef; +/** + * @brief CRYP Initialization Vectors (IV) structure definition + */ +typedef struct +{ + uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */ + uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */ + uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */ + uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */ +}CRYP_IVInitTypeDef; + +/** + * @brief CRYP context swapping structure definition + */ +typedef struct +{ + /*!< Configuration */ + uint32_t CR_bits9to2; + /*!< KEY */ + uint32_t CRYP_IV0LR; + uint32_t CRYP_IV0RR; + uint32_t CRYP_IV1LR; + uint32_t CRYP_IV1RR; + /*!< IV */ + uint32_t CRYP_K0LR; + uint32_t CRYP_K0RR; + uint32_t CRYP_K1LR; + uint32_t CRYP_K1RR; + uint32_t CRYP_K2LR; + uint32_t CRYP_K2RR; + uint32_t CRYP_K3LR; + uint32_t CRYP_K3RR; +}CRYP_Context; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRYP_Exported_Constants + * @{ + */ + +/** @defgroup CRYP_Algorithm_Direction + * @{ + */ +#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000) +#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004) +#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \ + ((ALGODIR) == CRYP_AlgoDir_Decrypt)) + +/** + * @} + */ + +/** @defgroup CRYP_Algorithm_Mode + * @{ + */ + +/*!< TDES Modes */ +#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000) +#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008) + +/*!< DES Modes */ +#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010) +#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018) + +/*!< AES Modes */ +#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020) +#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028) +#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030) +#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038) + +#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ + ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ + ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \ + ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_Key)) +/** + * @} + */ + +/** @defgroup CRYP_Data_Type + * @{ + */ +#define CRYP_DataType_32b ((uint16_t)0x0000) +#define CRYP_DataType_16b ((uint16_t)0x0040) +#define CRYP_DataType_8b ((uint16_t)0x0080) +#define CRYP_DataType_1b ((uint16_t)0x00C0) +#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \ + ((DATATYPE) == CRYP_DataType_16b)|| \ + ((DATATYPE) == CRYP_DataType_8b)|| \ + ((DATATYPE) == CRYP_DataType_1b)) +/** + * @} + */ + +/** @defgroup CRYP_Key_Size_for_AES_only + * @{ + */ +#define CRYP_KeySize_128b ((uint16_t)0x0000) +#define CRYP_KeySize_192b ((uint16_t)0x0100) +#define CRYP_KeySize_256b ((uint16_t)0x0200) +#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \ + ((KEYSIZE) == CRYP_KeySize_192b)|| \ + ((KEYSIZE) == CRYP_KeySize_256b)) +/** + * @} + */ + +/** @defgroup CRYP_flags_definition + * @{ + */ +#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently + processing a block of data + or a key preparation (for + AES decryption). */ +#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */ +#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */ +#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */ +#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw + interrupt status */ +#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */ +#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw + interrupt status */ + +#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \ + ((FLAG) == CRYP_FLAG_IFNF) || \ + ((FLAG) == CRYP_FLAG_OFNE) || \ + ((FLAG) == CRYP_FLAG_OFFU) || \ + ((FLAG) == CRYP_FLAG_BUSY) || \ + ((FLAG) == CRYP_FLAG_OUTRIS)|| \ + ((FLAG) == CRYP_FLAG_INRIS)) +/** + * @} + */ + +/** @defgroup CRYP_interrupts_definition + * @{ + */ +#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */ +#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */ +#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) +#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI)) + +/** + * @} + */ + +/** @defgroup CRYP_Encryption_Decryption_modes_definition + * @{ + */ +#define MODE_ENCRYPT ((uint8_t)0x01) +#define MODE_DECRYPT ((uint8_t)0x00) + +/** + * @} + */ + +/** @defgroup CRYP_DMA_transfer_requests + * @{ + */ +#define CRYP_DMAReq_DataIN ((uint8_t)0x01) +#define CRYP_DMAReq_DataOUT ((uint8_t)0x02) +#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the CRYP configuration to the default reset state ****/ +void CRYP_DeInit(void); + +/* CRYP Initialization and Configuration functions ****************************/ +void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct); +void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct); +void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); +void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); +void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); +void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); +void CRYP_Cmd(FunctionalState NewState); + +/* CRYP Data processing functions *********************************************/ +void CRYP_DataIn(uint32_t Data); +uint32_t CRYP_DataOut(void); +void CRYP_FIFOFlush(void); + +/* CRYP Context swapping functions ********************************************/ +ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, + CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); +void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); + +/* CRYP's DMA interface function **********************************************/ +void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); +ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); +FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); + +/* High Level AES functions **************************************************/ +ErrorStatus CRYP_AES_ECB(uint8_t Mode, + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_AES_CBC(uint8_t Mode, + uint8_t InitVectors[16], + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_AES_CTR(uint8_t Mode, + uint8_t InitVectors[16], + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +/* High Level TDES functions **************************************************/ +ErrorStatus CRYP_TDES_ECB(uint8_t Mode, + uint8_t Key[24], + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_TDES_CBC(uint8_t Mode, + uint8_t Key[24], + uint8_t InitVectors[8], + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +/* High Level DES functions **************************************************/ +ErrorStatus CRYP_DES_ECB(uint8_t Mode, + uint8_t Key[8], + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_DES_CBC(uint8_t Mode, + uint8_t Key[8], + uint8_t InitVectors[8], + uint8_t *Input,uint32_t Ilength, + uint8_t *Output); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_CRYP_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dac.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dac.h index f5e1c3355..2a0afc323 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dac.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dac.h @@ -1,304 +1,304 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dac.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_DAC_H -#define __STM32F2xx_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ - -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignement - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ - -/** @defgroup DAC_interrupts_definition - * @{ - */ -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DAC configuration to the default reset state *****/ -void DAC_DeInit(void); - -/* DAC channels configuration: trigger, output buffer, data format functions */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); - -/* DMA management functions ***************************************************/ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_DAC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_dac.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_DAC_H +#define __STM32F2xx_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ + +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** @defgroup DAC_interrupts_definition + * @{ + */ +#define DAC_IT_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the DAC configuration to the default reset state *****/ +void DAC_DeInit(void); + +/* DAC channels configuration: trigger, output buffer, data format functions */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +/* DMA management functions ***************************************************/ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_DAC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h index 80215d12d..415a5b91e 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h @@ -1,109 +1,109 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dbgmcu.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the DBGMCU firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_DBGMCU_H -#define __STM32F2xx_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) -#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040) -#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080) -#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100) -#define DBGMCU_RTC_STOP ((uint32_t)0x00000400) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) -#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000) -#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000) -#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000) -#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_DBGMCU_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_dbgmcu.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the DBGMCU firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_DBGMCU_H +#define __STM32F2xx_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) + +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) +#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040) +#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080) +#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100) +#define DBGMCU_RTC_STOP ((uint32_t)0x00000400) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) +#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000) +#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00)) + +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) +#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000) +#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_DBGMCU_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dcmi.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dcmi.h index eb3212674..d6baafd1c 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dcmi.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dcmi.h @@ -1,312 +1,312 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dcmi.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the DCMI firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_DCMI_H -#define __STM32F2xx_DCMI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DCMI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief DCMI Init structure definition - */ -typedef struct -{ - uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot. - This parameter can be a value of @ref DCMI_Capture_Mode */ - - uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. - This parameter can be a value of @ref DCMI_Synchronization_Mode */ - - uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. - This parameter can be a value of @ref DCMI_PIXCK_Polarity */ - - uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_VSYNC_Polarity */ - - uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_HSYNC_Polarity */ - - uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. - This parameter can be a value of @ref DCMI_Capture_Rate */ - - uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. - This parameter can be a value of @ref DCMI_Extended_Data_Mode */ -} DCMI_InitTypeDef; - -/** - * @brief DCMI CROP Init structure definition - */ -typedef struct -{ - uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture - will start. This parameter can be a value between 0x00 and 0x1FFF */ - - uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture. - This parameter can be a value between 0x00 and 0x3FFF */ - - uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point. - This parameter can be a value between 0x00 and 0x3FFF */ - - uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting - point on the same line. - This parameter can be a value between 0x00 and 0x3FFF */ -} DCMI_CROPInitTypeDef; - -/** - * @brief DCMI Embedded Synchronisation CODE Init structure definition - */ -typedef struct -{ - uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ - uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */ - uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */ - uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ -} DCMI_CodesInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DCMI_Exported_Constants - * @{ - */ - -/** @defgroup DCMI_Capture_Mode - * @{ - */ -#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously - into the destination memory through the DMA */ -#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of - frame and then transfers a single frame through the DMA */ -#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \ - ((MODE) == DCMI_CaptureMode_SnapShot)) -/** - * @} - */ - - -/** @defgroup DCMI_Synchronization_Mode - * @{ - */ -#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop) - is synchronized with the HSYNC/VSYNC signals */ -#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with - synchronization codes embedded in the data flow */ -#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \ - ((MODE) == DCMI_SynchroMode_Embedded)) -/** - * @} - */ - - -/** @defgroup DCMI_PIXCK_Polarity - * @{ - */ -#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */ -#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */ -#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \ - ((POLARITY) == DCMI_PCKPolarity_Rising)) -/** - * @} - */ - - -/** @defgroup DCMI_VSYNC_Polarity - * @{ - */ -#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */ -#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */ -#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \ - ((POLARITY) == DCMI_VSPolarity_High)) -/** - * @} - */ - - -/** @defgroup DCMI_HSYNC_Polarity - * @{ - */ -#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */ -#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */ -#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \ - ((POLARITY) == DCMI_HSPolarity_High)) -/** - * @} - */ - - -/** @defgroup DCMI_Capture_Rate - * @{ - */ -#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */ -#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */ -#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */ -#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \ - ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\ - ((RATE) == DCMI_CaptureRate_1of4_Frame)) -/** - * @} - */ - - -/** @defgroup DCMI_Extended_Data_Mode - * @{ - */ -#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */ -#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \ - ((DATA) == DCMI_ExtendedDataMode_10b) ||\ - ((DATA) == DCMI_ExtendedDataMode_12b) ||\ - ((DATA) == DCMI_ExtendedDataMode_14b)) -/** - * @} - */ - - -/** @defgroup DCMI_interrupt_sources - * @{ - */ -#define DCMI_IT_FRAME ((uint16_t)0x0001) -#define DCMI_IT_OVF ((uint16_t)0x0002) -#define DCMI_IT_ERR ((uint16_t)0x0004) -#define DCMI_IT_VSYNC ((uint16_t)0x0008) -#define DCMI_IT_LINE ((uint16_t)0x0010) -#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000)) -#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \ - ((IT) == DCMI_IT_OVF) || \ - ((IT) == DCMI_IT_ERR) || \ - ((IT) == DCMI_IT_VSYNC) || \ - ((IT) == DCMI_IT_LINE)) -/** - * @} - */ - - -/** @defgroup DCMI_Flags - * @{ - */ -/** - * @brief DCMI SR register - */ -#define DCMI_FLAG_HSYNC ((uint16_t)0x2001) -#define DCMI_FLAG_VSYNC ((uint16_t)0x2002) -#define DCMI_FLAG_FNE ((uint16_t)0x2004) -/** - * @brief DCMI RISR register - */ -#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001) -#define DCMI_FLAG_OVFRI ((uint16_t)0x0002) -#define DCMI_FLAG_ERRRI ((uint16_t)0x0004) -#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008) -#define DCMI_FLAG_LINERI ((uint16_t)0x0010) -/** - * @brief DCMI MISR register - */ -#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001) -#define DCMI_FLAG_OVFMI ((uint16_t)0x1002) -#define DCMI_FLAG_ERRMI ((uint16_t)0x1004) -#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008) -#define DCMI_FLAG_LINEMI ((uint16_t)0x1010) -#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \ - ((FLAG) == DCMI_FLAG_VSYNC) || \ - ((FLAG) == DCMI_FLAG_FNE) || \ - ((FLAG) == DCMI_FLAG_FRAMERI) || \ - ((FLAG) == DCMI_FLAG_OVFRI) || \ - ((FLAG) == DCMI_FLAG_ERRRI) || \ - ((FLAG) == DCMI_FLAG_VSYNCRI) || \ - ((FLAG) == DCMI_FLAG_LINERI) || \ - ((FLAG) == DCMI_FLAG_FRAMEMI) || \ - ((FLAG) == DCMI_FLAG_OVFMI) || \ - ((FLAG) == DCMI_FLAG_ERRMI) || \ - ((FLAG) == DCMI_FLAG_VSYNCMI) || \ - ((FLAG) == DCMI_FLAG_LINEMI)) - -#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DCMI configuration to the default reset state ****/ -void DCMI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct); -void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct); -void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct); -void DCMI_CROPCmd(FunctionalState NewState); -void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct); -void DCMI_JPEGCmd(FunctionalState NewState); - -/* Image capture functions ****************************************************/ -void DCMI_Cmd(FunctionalState NewState); -void DCMI_CaptureCmd(FunctionalState NewState); -uint32_t DCMI_ReadData(void); - -/* Interrupts and flags management functions **********************************/ -void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState); -FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG); -void DCMI_ClearFlag(uint16_t DCMI_FLAG); -ITStatus DCMI_GetITStatus(uint16_t DCMI_IT); -void DCMI_ClearITPendingBit(uint16_t DCMI_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_DCMI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_dcmi.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the DCMI firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_DCMI_H +#define __STM32F2xx_DCMI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DCMI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief DCMI Init structure definition + */ +typedef struct +{ + uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot. + This parameter can be a value of @ref DCMI_Capture_Mode */ + + uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. + This parameter can be a value of @ref DCMI_Synchronization_Mode */ + + uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. + This parameter can be a value of @ref DCMI_PIXCK_Polarity */ + + uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. + This parameter can be a value of @ref DCMI_VSYNC_Polarity */ + + uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. + This parameter can be a value of @ref DCMI_HSYNC_Polarity */ + + uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. + This parameter can be a value of @ref DCMI_Capture_Rate */ + + uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. + This parameter can be a value of @ref DCMI_Extended_Data_Mode */ +} DCMI_InitTypeDef; + +/** + * @brief DCMI CROP Init structure definition + */ +typedef struct +{ + uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture + will start. This parameter can be a value between 0x00 and 0x1FFF */ + + uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture. + This parameter can be a value between 0x00 and 0x3FFF */ + + uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point. + This parameter can be a value between 0x00 and 0x3FFF */ + + uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting + point on the same line. + This parameter can be a value between 0x00 and 0x3FFF */ +} DCMI_CROPInitTypeDef; + +/** + * @brief DCMI Embedded Synchronisation CODE Init structure definition + */ +typedef struct +{ + uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ + uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */ + uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */ + uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ +} DCMI_CodesInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DCMI_Exported_Constants + * @{ + */ + +/** @defgroup DCMI_Capture_Mode + * @{ + */ +#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously + into the destination memory through the DMA */ +#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of + frame and then transfers a single frame through the DMA */ +#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \ + ((MODE) == DCMI_CaptureMode_SnapShot)) +/** + * @} + */ + + +/** @defgroup DCMI_Synchronization_Mode + * @{ + */ +#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop) + is synchronized with the HSYNC/VSYNC signals */ +#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with + synchronization codes embedded in the data flow */ +#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \ + ((MODE) == DCMI_SynchroMode_Embedded)) +/** + * @} + */ + + +/** @defgroup DCMI_PIXCK_Polarity + * @{ + */ +#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */ +#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */ +#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \ + ((POLARITY) == DCMI_PCKPolarity_Rising)) +/** + * @} + */ + + +/** @defgroup DCMI_VSYNC_Polarity + * @{ + */ +#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */ +#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */ +#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \ + ((POLARITY) == DCMI_VSPolarity_High)) +/** + * @} + */ + + +/** @defgroup DCMI_HSYNC_Polarity + * @{ + */ +#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */ +#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */ +#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \ + ((POLARITY) == DCMI_HSPolarity_High)) +/** + * @} + */ + + +/** @defgroup DCMI_Capture_Rate + * @{ + */ +#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */ +#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */ +#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */ +#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \ + ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\ + ((RATE) == DCMI_CaptureRate_1of4_Frame)) +/** + * @} + */ + + +/** @defgroup DCMI_Extended_Data_Mode + * @{ + */ +#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */ +#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */ +#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */ +#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */ +#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \ + ((DATA) == DCMI_ExtendedDataMode_10b) ||\ + ((DATA) == DCMI_ExtendedDataMode_12b) ||\ + ((DATA) == DCMI_ExtendedDataMode_14b)) +/** + * @} + */ + + +/** @defgroup DCMI_interrupt_sources + * @{ + */ +#define DCMI_IT_FRAME ((uint16_t)0x0001) +#define DCMI_IT_OVF ((uint16_t)0x0002) +#define DCMI_IT_ERR ((uint16_t)0x0004) +#define DCMI_IT_VSYNC ((uint16_t)0x0008) +#define DCMI_IT_LINE ((uint16_t)0x0010) +#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000)) +#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \ + ((IT) == DCMI_IT_OVF) || \ + ((IT) == DCMI_IT_ERR) || \ + ((IT) == DCMI_IT_VSYNC) || \ + ((IT) == DCMI_IT_LINE)) +/** + * @} + */ + + +/** @defgroup DCMI_Flags + * @{ + */ +/** + * @brief DCMI SR register + */ +#define DCMI_FLAG_HSYNC ((uint16_t)0x2001) +#define DCMI_FLAG_VSYNC ((uint16_t)0x2002) +#define DCMI_FLAG_FNE ((uint16_t)0x2004) +/** + * @brief DCMI RISR register + */ +#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001) +#define DCMI_FLAG_OVFRI ((uint16_t)0x0002) +#define DCMI_FLAG_ERRRI ((uint16_t)0x0004) +#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008) +#define DCMI_FLAG_LINERI ((uint16_t)0x0010) +/** + * @brief DCMI MISR register + */ +#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001) +#define DCMI_FLAG_OVFMI ((uint16_t)0x1002) +#define DCMI_FLAG_ERRMI ((uint16_t)0x1004) +#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008) +#define DCMI_FLAG_LINEMI ((uint16_t)0x1010) +#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \ + ((FLAG) == DCMI_FLAG_VSYNC) || \ + ((FLAG) == DCMI_FLAG_FNE) || \ + ((FLAG) == DCMI_FLAG_FRAMERI) || \ + ((FLAG) == DCMI_FLAG_OVFRI) || \ + ((FLAG) == DCMI_FLAG_ERRRI) || \ + ((FLAG) == DCMI_FLAG_VSYNCRI) || \ + ((FLAG) == DCMI_FLAG_LINERI) || \ + ((FLAG) == DCMI_FLAG_FRAMEMI) || \ + ((FLAG) == DCMI_FLAG_OVFMI) || \ + ((FLAG) == DCMI_FLAG_ERRMI) || \ + ((FLAG) == DCMI_FLAG_VSYNCMI) || \ + ((FLAG) == DCMI_FLAG_LINEMI)) + +#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the DCMI configuration to the default reset state ****/ +void DCMI_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct); +void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct); +void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct); +void DCMI_CROPCmd(FunctionalState NewState); +void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct); +void DCMI_JPEGCmd(FunctionalState NewState); + +/* Image capture functions ****************************************************/ +void DCMI_Cmd(FunctionalState NewState); +void DCMI_CaptureCmd(FunctionalState NewState); +uint32_t DCMI_ReadData(void); + +/* Interrupts and flags management functions **********************************/ +void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState); +FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG); +void DCMI_ClearFlag(uint16_t DCMI_FLAG); +ITStatus DCMI_GetITStatus(uint16_t DCMI_IT); +void DCMI_ClearITPendingBit(uint16_t DCMI_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_DCMI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h index 44b70cb85..fb27ff06c 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h @@ -1,609 +1,609 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dma.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_DMA_H -#define __STM32F2xx_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA Init structure definition - */ - -typedef struct -{ - uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. - This parameter can be a value of @ref DMA_channel */ - - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ - - uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. - This memory is the default memory used when double buffer mode is - not enabled. */ - - uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. - This parameter can be a value of @ref DMA_circular_normal_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Stream */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. - This parameter can be a value of @ref DMA_fifo_direct_mode - @note The Direct mode (FIFO mode disabled) cannot be used if the - memory-to-memory data transfer is configured on the selected Stream */ - - uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref DMA_fifo_threshold_level */ - - uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_memory_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ - - uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_peripheral_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ - ((PERIPH) == DMA1_Stream1) || \ - ((PERIPH) == DMA1_Stream2) || \ - ((PERIPH) == DMA1_Stream3) || \ - ((PERIPH) == DMA1_Stream4) || \ - ((PERIPH) == DMA1_Stream5) || \ - ((PERIPH) == DMA1_Stream6) || \ - ((PERIPH) == DMA1_Stream7) || \ - ((PERIPH) == DMA2_Stream0) || \ - ((PERIPH) == DMA2_Stream1) || \ - ((PERIPH) == DMA2_Stream2) || \ - ((PERIPH) == DMA2_Stream3) || \ - ((PERIPH) == DMA2_Stream4) || \ - ((PERIPH) == DMA2_Stream5) || \ - ((PERIPH) == DMA2_Stream6) || \ - ((PERIPH) == DMA2_Stream7)) - -#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \ - ((CONTROLLER) == DMA2)) - -/** @defgroup DMA_channel - * @{ - */ -#define DMA_Channel_0 ((uint32_t)0x00000000) -#define DMA_Channel_1 ((uint32_t)0x02000000) -#define DMA_Channel_2 ((uint32_t)0x04000000) -#define DMA_Channel_3 ((uint32_t)0x06000000) -#define DMA_Channel_4 ((uint32_t)0x08000000) -#define DMA_Channel_5 ((uint32_t)0x0A000000) -#define DMA_Channel_6 ((uint32_t)0x0C000000) -#define DMA_Channel_7 ((uint32_t)0x0E000000) - -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ - ((CHANNEL) == DMA_Channel_1) || \ - ((CHANNEL) == DMA_Channel_2) || \ - ((CHANNEL) == DMA_Channel_3) || \ - ((CHANNEL) == DMA_Channel_4) || \ - ((CHANNEL) == DMA_Channel_5) || \ - ((CHANNEL) == DMA_Channel_6) || \ - ((CHANNEL) == DMA_Channel_7)) -/** - * @} - */ - - -/** @defgroup DMA_data_transfer_direction - * @{ - */ -#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) -#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) -#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ - ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ - ((DIRECTION) == DMA_DIR_MemoryToMemory)) -/** - * @} - */ - - -/** @defgroup DMA_data_buffer_size - * @{ - */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ - ((STATE) == DMA_PeripheralInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000400) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ - ((STATE) == DMA_MemoryInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_data_size - * @{ - */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - - -/** @defgroup DMA_memory_data_size - * @{ - */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word )) -/** - * @} - */ - - -/** @defgroup DMA_circular_normal_mode - * @{ - */ -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define DMA_Mode_Circular ((uint32_t)0x00000100) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \ - ((MODE) == DMA_Mode_Circular)) -/** - * @} - */ - - -/** @defgroup DMA_priority_level - * @{ - */ -#define DMA_Priority_Low ((uint32_t)0x00000000) -#define DMA_Priority_Medium ((uint32_t)0x00010000) -#define DMA_Priority_High ((uint32_t)0x00020000) -#define DMA_Priority_VeryHigh ((uint32_t)0x00030000) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_VeryHigh)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_direct_mode - * @{ - */ -#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) -#define DMA_FIFOMode_Enable ((uint32_t)0x00000004) - -#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ - ((STATE) == DMA_FIFOMode_Enable)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_threshold_level - * @{ - */ -#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) -#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) -#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) -#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) - -#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ - ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_Full)) -/** - * @} - */ - - -/** @defgroup DMA_memory_burst - * @{ - */ -#define DMA_MemoryBurst_Single ((uint32_t)0x00000000) -#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) -#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) -#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) - -#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ - ((BURST) == DMA_MemoryBurst_INC4) || \ - ((BURST) == DMA_MemoryBurst_INC8) || \ - ((BURST) == DMA_MemoryBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_burst - * @{ - */ -#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) -#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) -#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) -#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) - -#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ - ((BURST) == DMA_PeripheralBurst_INC4) || \ - ((BURST) == DMA_PeripheralBurst_INC8) || \ - ((BURST) == DMA_PeripheralBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_status_level - * @{ - */ -#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) -#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) -#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) -#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) -#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) -#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) - -#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ - ((STATUS) == DMA_FIFOStatus_HalfFull) || \ - ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ - ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ - ((STATUS) == DMA_FIFOStatus_Full) || \ - ((STATUS) == DMA_FIFOStatus_Empty)) -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) -#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) -#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) -#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) -#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) -#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) -#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) -#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) -#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) -#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) -#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) -#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) -#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) -#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) -#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) -#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) -#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) -#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) -#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) -#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) -#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) -#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) -#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) -#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) -#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) -#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) -#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) -#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) -#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) -#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) -#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) -#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) -#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) -#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) -#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) -#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) -#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) -#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) -#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) -#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) - -#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ - (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ - ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ - ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ - ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ - ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ - ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ - ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ - ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ - ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ - ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ - ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ - ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ - ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ - ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ - ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ - ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ - ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ - ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ - ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ - ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions - * @{ - */ -#define DMA_IT_TC ((uint32_t)0x00000010) -#define DMA_IT_HT ((uint32_t)0x00000008) -#define DMA_IT_TE ((uint32_t)0x00000004) -#define DMA_IT_DME ((uint32_t)0x00000002) -#define DMA_IT_FE ((uint32_t)0x00000080) - -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - - -/** @defgroup DMA_interrupts_definitions - * @{ - */ -#define DMA_IT_FEIF0 ((uint32_t)0x90000001) -#define DMA_IT_DMEIF0 ((uint32_t)0x10001004) -#define DMA_IT_TEIF0 ((uint32_t)0x10002008) -#define DMA_IT_HTIF0 ((uint32_t)0x10004010) -#define DMA_IT_TCIF0 ((uint32_t)0x10008020) -#define DMA_IT_FEIF1 ((uint32_t)0x90000040) -#define DMA_IT_DMEIF1 ((uint32_t)0x10001100) -#define DMA_IT_TEIF1 ((uint32_t)0x10002200) -#define DMA_IT_HTIF1 ((uint32_t)0x10004400) -#define DMA_IT_TCIF1 ((uint32_t)0x10008800) -#define DMA_IT_FEIF2 ((uint32_t)0x90010000) -#define DMA_IT_DMEIF2 ((uint32_t)0x10041000) -#define DMA_IT_TEIF2 ((uint32_t)0x10082000) -#define DMA_IT_HTIF2 ((uint32_t)0x10104000) -#define DMA_IT_TCIF2 ((uint32_t)0x10208000) -#define DMA_IT_FEIF3 ((uint32_t)0x90400000) -#define DMA_IT_DMEIF3 ((uint32_t)0x11001000) -#define DMA_IT_TEIF3 ((uint32_t)0x12002000) -#define DMA_IT_HTIF3 ((uint32_t)0x14004000) -#define DMA_IT_TCIF3 ((uint32_t)0x18008000) -#define DMA_IT_FEIF4 ((uint32_t)0xA0000001) -#define DMA_IT_DMEIF4 ((uint32_t)0x20001004) -#define DMA_IT_TEIF4 ((uint32_t)0x20002008) -#define DMA_IT_HTIF4 ((uint32_t)0x20004010) -#define DMA_IT_TCIF4 ((uint32_t)0x20008020) -#define DMA_IT_FEIF5 ((uint32_t)0xA0000040) -#define DMA_IT_DMEIF5 ((uint32_t)0x20001100) -#define DMA_IT_TEIF5 ((uint32_t)0x20002200) -#define DMA_IT_HTIF5 ((uint32_t)0x20004400) -#define DMA_IT_TCIF5 ((uint32_t)0x20008800) -#define DMA_IT_FEIF6 ((uint32_t)0xA0010000) -#define DMA_IT_DMEIF6 ((uint32_t)0x20041000) -#define DMA_IT_TEIF6 ((uint32_t)0x20082000) -#define DMA_IT_HTIF6 ((uint32_t)0x20104000) -#define DMA_IT_TCIF6 ((uint32_t)0x20208000) -#define DMA_IT_FEIF7 ((uint32_t)0xA0400000) -#define DMA_IT_DMEIF7 ((uint32_t)0x21001000) -#define DMA_IT_TEIF7 ((uint32_t)0x22002000) -#define DMA_IT_HTIF7 ((uint32_t)0x24004000) -#define DMA_IT_TCIF7 ((uint32_t)0x28008000) - -#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ - (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ - (((IT) & 0x40820082) == 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \ - ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ - ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ - ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ - ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ - ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ - ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ - ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ - ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ - ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ - ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ - ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ - ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ - ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ - ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ - ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ - ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ - ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ - ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ - ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_increment_offset - * @{ - */ -#define DMA_PINCOS_Psize ((uint32_t)0x00000000) -#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) - -#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ - ((SIZE) == DMA_PINCOS_WordAligned)) -/** - * @} - */ - - -/** @defgroup DMA_flow_controller_definitions - * @{ - */ -#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) -#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) - -#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ - ((CTRL) == DMA_FlowCtrl_Peripheral)) -/** - * @} - */ - - -/** @defgroup DMA_memory_targets_definitions - * @{ - */ -#define DMA_Memory_0 ((uint32_t)0x00000000) -#define DMA_Memory_1 ((uint32_t)0x00080000) - -#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DMA configuration to the default reset state *****/ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Initialization and Configuration functions *********************************/ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - -/* Optional Configuration functions *******************************************/ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos); -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl); - -/* Data Counter functions *****************************************************/ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Double Buffer mode functions ***********************************************/ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory); -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget); -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Interrupts and flags management functions **********************************/ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_DMA_H */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_dma.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_DMA_H +#define __STM32F2xx_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. + This parameter can be a value of @ref DMA_channel */ + + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ + + uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. + This memory is the default memory used when double buffer mode is + not enabled. */ + + uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_circular_normal_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. + This parameter can be a value of @ref DMA_fifo_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected Stream */ + + uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_fifo_threshold_level */ + + uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptable + transaction. This parameter can be a value of @ref DMA_memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptable + transaction. This parameter can be a value of @ref DMA_peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ + ((PERIPH) == DMA1_Stream1) || \ + ((PERIPH) == DMA1_Stream2) || \ + ((PERIPH) == DMA1_Stream3) || \ + ((PERIPH) == DMA1_Stream4) || \ + ((PERIPH) == DMA1_Stream5) || \ + ((PERIPH) == DMA1_Stream6) || \ + ((PERIPH) == DMA1_Stream7) || \ + ((PERIPH) == DMA2_Stream0) || \ + ((PERIPH) == DMA2_Stream1) || \ + ((PERIPH) == DMA2_Stream2) || \ + ((PERIPH) == DMA2_Stream3) || \ + ((PERIPH) == DMA2_Stream4) || \ + ((PERIPH) == DMA2_Stream5) || \ + ((PERIPH) == DMA2_Stream6) || \ + ((PERIPH) == DMA2_Stream7)) + +#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \ + ((CONTROLLER) == DMA2)) + +/** @defgroup DMA_channel + * @{ + */ +#define DMA_Channel_0 ((uint32_t)0x00000000) +#define DMA_Channel_1 ((uint32_t)0x02000000) +#define DMA_Channel_2 ((uint32_t)0x04000000) +#define DMA_Channel_3 ((uint32_t)0x06000000) +#define DMA_Channel_4 ((uint32_t)0x08000000) +#define DMA_Channel_5 ((uint32_t)0x0A000000) +#define DMA_Channel_6 ((uint32_t)0x0C000000) +#define DMA_Channel_7 ((uint32_t)0x0E000000) + +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ + ((CHANNEL) == DMA_Channel_1) || \ + ((CHANNEL) == DMA_Channel_2) || \ + ((CHANNEL) == DMA_Channel_3) || \ + ((CHANNEL) == DMA_Channel_4) || \ + ((CHANNEL) == DMA_Channel_5) || \ + ((CHANNEL) == DMA_Channel_6) || \ + ((CHANNEL) == DMA_Channel_7)) +/** + * @} + */ + + +/** @defgroup DMA_data_transfer_direction + * @{ + */ +#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) +#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) +#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ + ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ + ((DIRECTION) == DMA_DIR_MemoryToMemory)) +/** + * @} + */ + + +/** @defgroup DMA_data_buffer_size + * @{ + */ +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** + * @} + */ + + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000400) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_data_size + * @{ + */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + + +/** @defgroup DMA_memory_data_size + * @{ + */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word )) +/** + * @} + */ + + +/** @defgroup DMA_circular_normal_mode + * @{ + */ +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define DMA_Mode_Circular ((uint32_t)0x00000100) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \ + ((MODE) == DMA_Mode_Circular)) +/** + * @} + */ + + +/** @defgroup DMA_priority_level + * @{ + */ +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define DMA_Priority_Medium ((uint32_t)0x00010000) +#define DMA_Priority_High ((uint32_t)0x00020000) +#define DMA_Priority_VeryHigh ((uint32_t)0x00030000) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_VeryHigh)) +/** + * @} + */ + + +/** @defgroup DMA_fifo_direct_mode + * @{ + */ +#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) +#define DMA_FIFOMode_Enable ((uint32_t)0x00000004) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ + ((STATE) == DMA_FIFOMode_Enable)) +/** + * @} + */ + + +/** @defgroup DMA_fifo_threshold_level + * @{ + */ +#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) +#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) +#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) +#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ + ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ + ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ + ((THRESHOLD) == DMA_FIFOThreshold_Full)) +/** + * @} + */ + + +/** @defgroup DMA_memory_burst + * @{ + */ +#define DMA_MemoryBurst_Single ((uint32_t)0x00000000) +#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) +#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) +#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ + ((BURST) == DMA_MemoryBurst_INC4) || \ + ((BURST) == DMA_MemoryBurst_INC8) || \ + ((BURST) == DMA_MemoryBurst_INC16)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_burst + * @{ + */ +#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) +#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) +#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) +#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ + ((BURST) == DMA_PeripheralBurst_INC4) || \ + ((BURST) == DMA_PeripheralBurst_INC8) || \ + ((BURST) == DMA_PeripheralBurst_INC16)) +/** + * @} + */ + + +/** @defgroup DMA_fifo_status_level + * @{ + */ +#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) +#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) +#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) +#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) +#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) +#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) + +#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ + ((STATUS) == DMA_FIFOStatus_HalfFull) || \ + ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ + ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ + ((STATUS) == DMA_FIFOStatus_Full) || \ + ((STATUS) == DMA_FIFOStatus_Empty)) +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) +#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) +#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) +#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) +#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) +#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) +#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) +#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) +#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) +#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) +#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) +#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) +#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) +#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) +#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) +#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) +#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) +#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) +#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) +#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) +#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) +#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) +#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) +#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) +#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) +#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) +#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) +#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) +#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) +#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) +#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) +#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) +#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) +#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) +#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) +#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) +#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) +#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) +#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) +#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) + +#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ + (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ + ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ + ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ + ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ + ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ + ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ + ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ + ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ + ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ + ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ + ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ + ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ + ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ + ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ + ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ + ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ + ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ + ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ + ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ + ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions + * @{ + */ +#define DMA_IT_TC ((uint32_t)0x00000010) +#define DMA_IT_HT ((uint32_t)0x00000008) +#define DMA_IT_TE ((uint32_t)0x00000004) +#define DMA_IT_DME ((uint32_t)0x00000002) +#define DMA_IT_FE ((uint32_t)0x00000080) + +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + + +/** @defgroup DMA_interrupts_definitions + * @{ + */ +#define DMA_IT_FEIF0 ((uint32_t)0x90000001) +#define DMA_IT_DMEIF0 ((uint32_t)0x10001004) +#define DMA_IT_TEIF0 ((uint32_t)0x10002008) +#define DMA_IT_HTIF0 ((uint32_t)0x10004010) +#define DMA_IT_TCIF0 ((uint32_t)0x10008020) +#define DMA_IT_FEIF1 ((uint32_t)0x90000040) +#define DMA_IT_DMEIF1 ((uint32_t)0x10001100) +#define DMA_IT_TEIF1 ((uint32_t)0x10002200) +#define DMA_IT_HTIF1 ((uint32_t)0x10004400) +#define DMA_IT_TCIF1 ((uint32_t)0x10008800) +#define DMA_IT_FEIF2 ((uint32_t)0x90010000) +#define DMA_IT_DMEIF2 ((uint32_t)0x10041000) +#define DMA_IT_TEIF2 ((uint32_t)0x10082000) +#define DMA_IT_HTIF2 ((uint32_t)0x10104000) +#define DMA_IT_TCIF2 ((uint32_t)0x10208000) +#define DMA_IT_FEIF3 ((uint32_t)0x90400000) +#define DMA_IT_DMEIF3 ((uint32_t)0x11001000) +#define DMA_IT_TEIF3 ((uint32_t)0x12002000) +#define DMA_IT_HTIF3 ((uint32_t)0x14004000) +#define DMA_IT_TCIF3 ((uint32_t)0x18008000) +#define DMA_IT_FEIF4 ((uint32_t)0xA0000001) +#define DMA_IT_DMEIF4 ((uint32_t)0x20001004) +#define DMA_IT_TEIF4 ((uint32_t)0x20002008) +#define DMA_IT_HTIF4 ((uint32_t)0x20004010) +#define DMA_IT_TCIF4 ((uint32_t)0x20008020) +#define DMA_IT_FEIF5 ((uint32_t)0xA0000040) +#define DMA_IT_DMEIF5 ((uint32_t)0x20001100) +#define DMA_IT_TEIF5 ((uint32_t)0x20002200) +#define DMA_IT_HTIF5 ((uint32_t)0x20004400) +#define DMA_IT_TCIF5 ((uint32_t)0x20008800) +#define DMA_IT_FEIF6 ((uint32_t)0xA0010000) +#define DMA_IT_DMEIF6 ((uint32_t)0x20041000) +#define DMA_IT_TEIF6 ((uint32_t)0x20082000) +#define DMA_IT_HTIF6 ((uint32_t)0x20104000) +#define DMA_IT_TCIF6 ((uint32_t)0x20208000) +#define DMA_IT_FEIF7 ((uint32_t)0xA0400000) +#define DMA_IT_DMEIF7 ((uint32_t)0x21001000) +#define DMA_IT_TEIF7 ((uint32_t)0x22002000) +#define DMA_IT_HTIF7 ((uint32_t)0x24004000) +#define DMA_IT_TCIF7 ((uint32_t)0x28008000) + +#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ + (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ + (((IT) & 0x40820082) == 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \ + ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ + ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ + ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ + ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ + ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ + ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ + ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ + ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ + ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ + ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ + ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ + ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ + ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ + ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ + ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ + ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ + ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ + ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ + ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_increment_offset + * @{ + */ +#define DMA_PINCOS_Psize ((uint32_t)0x00000000) +#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) + +#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ + ((SIZE) == DMA_PINCOS_WordAligned)) +/** + * @} + */ + + +/** @defgroup DMA_flow_controller_definitions + * @{ + */ +#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) +#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) + +#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ + ((CTRL) == DMA_FlowCtrl_Peripheral)) +/** + * @} + */ + + +/** @defgroup DMA_memory_targets_definitions + * @{ + */ +#define DMA_Memory_0 ((uint32_t)0x00000000) +#define DMA_Memory_1 ((uint32_t)0x00080000) + +#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the DMA configuration to the default reset state *****/ +void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx); + +/* Initialization and Configuration functions *********************************/ +void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); + +/* Optional Configuration functions *******************************************/ +void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos); +void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl); + +/* Data Counter functions *****************************************************/ +void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); +uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); + +/* Double Buffer mode functions ***********************************************/ +void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, + uint32_t DMA_CurrentMemory); +void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); +void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, + uint32_t DMA_MemoryTarget); +uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); + +/* Interrupts and flags management functions **********************************/ +FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); +uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); +FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); +void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); +void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); +ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); +void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_DMA_H */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h index 186e87f08..f9f0a9179 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h @@ -1,183 +1,183 @@ -/** - ****************************************************************************** - * @file stm32f2xx_exti.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_EXTI_H -#define __STM32F2xx_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination value of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTITrigger_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ -#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ -#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) - -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ - ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ - ((LINE) == EXTI_Line22)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the EXTI configuration to the default reset state *****/ -void EXTI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); - -/* Interrupts and flags management functions **********************************/ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_EXTI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_exti.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the EXTI firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_EXTI_H +#define __STM32F2xx_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination value of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTITrigger_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ + +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) + +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ + ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ + ((LINE) == EXTI_Line22)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the EXTI configuration to the default reset state *****/ +void EXTI_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); + +/* Interrupts and flags management functions **********************************/ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_EXTI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h index 76d937655..32b165133 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h @@ -1,340 +1,340 @@ -/** - ****************************************************************************** - * @file stm32f2xx_flash.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_FLASH_H -#define __STM32F2xx_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PGS, - FLASH_ERROR_PGP, - FLASH_ERROR_PGA, - FLASH_ERROR_WRP, - FLASH_ERROR_PROGRAM, - FLASH_ERROR_OPERATION, - FLASH_COMPLETE -}FLASH_Status; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ -#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ -#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ -#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ -#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ -#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ -#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2) || \ - ((LATENCY) == FLASH_Latency_3) || \ - ((LATENCY) == FLASH_Latency_4) || \ - ((LATENCY) == FLASH_Latency_5) || \ - ((LATENCY) == FLASH_Latency_6) || \ - ((LATENCY) == FLASH_Latency_7)) -/** - * @} - */ - -/** @defgroup FLASH_Voltage_Range - * @{ - */ -#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ -#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ -#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ -#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ -#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ -#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ -#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ -#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ -#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ -#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ -#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ -#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ -#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ -#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ -#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_Read_Protection - * @{ - */ -#define OB_RDP_Level_0 ((uint8_t)0xAA) -#define OB_RDP_Level_1 ((uint8_t)0x55) -/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ -#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ - ((LEVEL) == OB_RDP_Level_1))/*||\ - ((LEVEL) == OB_RDP_Level_2))*/ -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_IWatchdog - * @{ - */ -#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_nRST_STOP - * @{ - */ -#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) -/** - * @} - */ - - -/** @defgroup FLASH_Option_Bytes_nRST_STDBY - * @{ - */ -#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) -/** - * @} - */ - -/** @defgroup FLASH_BOR_Reset_Level - * @{ - */ -#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ -#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ - ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ -#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ -#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ -#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ -#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ - ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ - ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ - ((FLAG) == FLASH_FLAG_BSY)) -/** - * @} - */ - -/** @defgroup FLASH_Program_Parallelism - * @{ - */ -#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) -#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) -#define FLASH_PSIZE_WORD ((uint32_t)0x00000200) -#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) -#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) -/** - * @} - */ - -/** @defgroup FLASH_Keys - * @{ - */ -#define RDP_KEY ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) -#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) -#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) -/** - * @} - */ - -/** - * @brief ACR register byte 0 (Bits[8:0]) base address - */ -#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) -/** - * @brief OPTCR register byte 3 (Bits[24:16]) base address - */ -#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) -#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) -#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_PrefetchBufferCmd(FunctionalState NewState); -void FLASH_InstructionCacheCmd(FunctionalState NewState); -void FLASH_DataCacheCmd(FunctionalState NewState); -void FLASH_InstructionCacheReset(void); -void FLASH_DataCacheReset(void); - -/* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); - -/* Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); -void FLASH_OB_RDPConfig(uint8_t OB_RDP); -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -void FLASH_OB_BORConfig(uint8_t OB_BOR); -FLASH_Status FLASH_OB_Launch(void); -uint8_t FLASH_OB_GetUser(void); -uint16_t FLASH_OB_GetWRP(void); -FlagStatus FLASH_OB_GetRDP(void); -uint8_t FLASH_OB_GetBOR(void); - -/* Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_flash.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_FLASH_H +#define __STM32F2xx_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief FLASH Status + */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PGS, + FLASH_ERROR_PGP, + FLASH_ERROR_PGA, + FLASH_ERROR_WRP, + FLASH_ERROR_PROGRAM, + FLASH_ERROR_OPERATION, + FLASH_COMPLETE +}FLASH_Status; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ +#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ +#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ +#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ +#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ +#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ +#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2) || \ + ((LATENCY) == FLASH_Latency_3) || \ + ((LATENCY) == FLASH_Latency_4) || \ + ((LATENCY) == FLASH_Latency_5) || \ + ((LATENCY) == FLASH_Latency_6) || \ + ((LATENCY) == FLASH_Latency_7)) +/** + * @} + */ + +/** @defgroup FLASH_Voltage_Range + * @{ + */ +#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ +#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ + (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ +#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ +#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ +#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ +#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ +#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ +#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ +#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ +#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ +#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ +#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ +#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ +#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ +#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ + +#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_Read_Protection + * @{ + */ +#define OB_RDP_Level_0 ((uint8_t)0xAA) +#define OB_RDP_Level_1 ((uint8_t)0x55) +/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 + it's no more possible to go back to level 1 or 0 */ +#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ + ((LEVEL) == OB_RDP_Level_1))/*||\ + ((LEVEL) == OB_RDP_Level_2))*/ +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_IWatchdog + * @{ + */ +#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_nRST_STOP + * @{ + */ +#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) +/** + * @} + */ + + +/** @defgroup FLASH_Option_Bytes_nRST_STDBY + * @{ + */ +#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) +/** + * @} + */ + +/** @defgroup FLASH_BOR_Reset_Level + * @{ + */ +#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ + ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) +/** + * @} + */ + +/** @defgroup FLASH_Interrupts + * @{ + */ +#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ +#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ + ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ + ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ + ((FLAG) == FLASH_FLAG_BSY)) +/** + * @} + */ + +/** @defgroup FLASH_Program_Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) +#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) +#define FLASH_PSIZE_WORD ((uint32_t)0x00000200) +#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) +#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) +/** + * @} + */ + +/** @defgroup FLASH_Keys + * @{ + */ +#define RDP_KEY ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) +#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) +#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) +/** + * @} + */ + +/** + * @brief ACR register byte 0 (Bits[8:0]) base address + */ +#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) +/** + * @brief OPTCR register byte 3 (Bits[24:16]) base address + */ +#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) +#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) +#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* FLASH Interface configuration functions ************************************/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_PrefetchBufferCmd(FunctionalState NewState); +void FLASH_InstructionCacheCmd(FunctionalState NewState); +void FLASH_DataCacheCmd(FunctionalState NewState); +void FLASH_InstructionCacheReset(void); +void FLASH_DataCacheReset(void); + +/* FLASH Memory Programming functions *****************************************/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); +FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); +FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); + +/* Option Bytes Programming functions *****************************************/ +void FLASH_OB_Unlock(void); +void FLASH_OB_Lock(void); +void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); +void FLASH_OB_RDPConfig(uint8_t OB_RDP); +void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); +void FLASH_OB_BORConfig(uint8_t OB_BOR); +FLASH_Status FLASH_OB_Launch(void); +uint8_t FLASH_OB_GetUser(void); +uint16_t FLASH_OB_GetWRP(void); +FlagStatus FLASH_OB_GetRDP(void); +uint8_t FLASH_OB_GetBOR(void); + +/* Interrupts and flags management functions **********************************/ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_FLASH_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_fsmc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_fsmc.h index 65ffc3269..102b1cfd0 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_fsmc.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_fsmc.h @@ -1,675 +1,675 @@ -/** - ****************************************************************************** - * @file stm32f2xx_fsmc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the FSMC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_FSMC_H -#define __STM32F2xx_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FSMC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FSMC NOR/SRAM Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ -}FSMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FSMC NAND and PCCARD Banks - */ -typedef struct -{ - uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command deassertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FSMC NAND Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - -/** - * @brief FSMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ -}FSMC_PCCARDInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FSMC_Exported_Constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank - * @{ - */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Bank - * @{ - */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) -#define FSMC_Bank3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Bank - * @{ - */ -#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ - ((BANK) == FSMC_Bank1_NORSRAM2) || \ - ((BANK) == FSMC_Bank1_NORSRAM3) || \ - ((BANK) == FSMC_Bank1_NORSRAM4)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND)) - -#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -/** @defgroup FSMC_NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) -#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ - ((MUX) == FSMC_DataAddressMux_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type - * @{ - */ - -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) -#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ - ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FSMC_MemoryType_NOR)) -/** - * @} - */ - -/** @defgroup FSMC_Data_Width - * @{ - */ - -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ - ((WIDTH) == FSMC_MemoryDataWidth_16b)) -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode - * @{ - */ - -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) -#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ - ((STATE) == FSMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_AsynchronousWait - * @{ - */ -#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) -#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ - ((STATE) == FSMC_AsynchronousWait_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity - * @{ - */ -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) -#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FSMC_WaitSignalPolarity_High)) -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode - * @{ - */ -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) -#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ - ((MODE) == FSMC_WrapMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing - * @{ - */ -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation - * @{ - */ -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) -#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ - ((OPERATION) == FSMC_WriteOperation_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal - * @{ - */ -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) -#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ - ((SIGNAL) == FSMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode - * @{ - */ -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ - ((MODE) == FSMC_ExtendedMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst - * @{ - */ - -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) -#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ - ((BURST) == FSMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time - * @{ - */ -#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time - * @{ - */ -#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time - * @{ - */ -#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration - * @{ - */ -#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division - * @{ - */ -#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency - * @{ - */ -#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode - * @{ - */ -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) -#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ - ((MODE) == FSMC_AccessMode_B) || \ - ((MODE) == FSMC_AccessMode_C) || \ - ((MODE) == FSMC_AccessMode_D)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FSMC_NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FSMC_Wait_feature - * @{ - */ -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ - ((FEATURE) == FSMC_Waitfeature_Enable)) -/** - * @} - */ - - -/** @defgroup FSMC_ECC - * @{ - */ -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ - ((STATE) == FSMC_ECC_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size - * @{ - */ -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_8192Bytes)) -/** - * @} - */ - -/** @defgroup FSMC_TCLR_Setup_Time - * @{ - */ -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time - * @{ - */ -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time - * @{ - */ -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time - * @{ - */ -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time - * @{ - */ -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time - * @{ - */ -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Interrupt_sources - * @{ - */ -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) -#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ - ((IT) == FSMC_IT_Level) || \ - ((IT) == FSMC_IT_FallingEdge)) -/** - * @} - */ - -/** @defgroup FSMC_Flags - * @{ - */ -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ - ((FLAG) == FSMC_FLAG_Level) || \ - ((FLAG) == FSMC_FLAG_FallingEdge) || \ - ((FLAG) == FSMC_FLAG_FEMPT)) - -#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* NOR/SRAM Controller functions **********************************************/ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); - -/* NAND Controller functions **************************************************/ -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); - -/* PCCARD Controller functions ************************************************/ -void FSMC_PCCARDDeInit(void); -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDCmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_FSMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_fsmc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the FSMC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_FSMC_H +#define __STM32F2xx_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note This parameter is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ +typedef struct +{ + uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank + * @{ + */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Bank + * @{ + */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FSMC_PCCARD_Bank + * @{ + */ +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +/** @defgroup FSMC_NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_AsynchronousWait + * @{ + */ +#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) +#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ + ((STATE) == FSMC_AsynchronousWait_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) +/** + * @} + */ + + +/** @defgroup FSMC_ECC + * @{ + */ +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* NOR/SRAM Controller functions **********************************************/ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); + +/* NAND Controller functions **************************************************/ +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); + +/* PCCARD Controller functions ************************************************/ +void FSMC_PCCARDDeInit(void); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_PCCARDCmd(FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h index 54cdfec47..a284e856a 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h @@ -1,411 +1,411 @@ -/** - ****************************************************************************** - * @file stm32f2xx_gpio.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the GPIO firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_GPIO_H -#define __STM32F2xx_GPIO_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG) || \ - ((PERIPH) == GPIOH) || \ - ((PERIPH) == GPIOI)) - -/** - * @brief GPIO Configuration Mode enumeration - */ -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ - GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ -}GPIOMode_TypeDef; -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ - ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) - -/** - * @brief GPIO Output type enumeration - */ -typedef enum -{ - GPIO_OType_PP = 0x00, - GPIO_OType_OD = 0x01 -}GPIOOType_TypeDef; -#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) - - -/** - * @brief GPIO Output Maximum frequency enumeration - */ -typedef enum -{ - GPIO_Speed_2MHz = 0x00, /*!< Low speed */ - GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ - GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ - GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ -}GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \ - ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) - -/** - * @brief GPIO Configuration PullUp PullDown enumeration - */ -typedef enum -{ - GPIO_PuPd_NOPULL = 0x00, - GPIO_PuPd_UP = 0x01, - GPIO_PuPd_DOWN = 0x02 -}GPIOPuPd_TypeDef; -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ - ((PUPD) == GPIO_PuPd_DOWN)) - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIOOType_TypeDef */ - - GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIOPuPd_TypeDef */ -}GPIO_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) -/** - * @} - */ - - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) -/** - * @} - */ - -/** @defgroup GPIO_Alternat_function_selection_define - * @{ - */ -/** - * @brief AF 0 selection - */ -#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ -#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ - ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \ - ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \ - ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT)) -/** - * @} - */ - -/** @defgroup GPIO_Legacy - * @{ - */ - -#define GPIO_Mode_AIN GPIO_Mode_AN - -#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS -#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS -#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the GPIO configuration to the default reset state ****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); - -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Read and Write functions **********************************************/ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Alternate functions configuration function ****************************/ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /*__STM32F2xx_GPIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_gpio.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the GPIO firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_GPIO_H +#define __STM32F2xx_GPIO_H + +#if defined(__cplusplus) && !defined(SIMU) + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG) || \ + ((PERIPH) == GPIOH) || \ + ((PERIPH) == GPIOI)) + +/** + * @brief GPIO Configuration Mode enumeration + */ +typedef enum +{ + GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ + GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ + GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ +}GPIOMode_TypeDef; +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ + ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) + +/** + * @brief GPIO Output type enumeration + */ +typedef enum +{ + GPIO_OType_PP = 0x00, + GPIO_OType_OD = 0x01 +}GPIOOType_TypeDef; +#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) + + +/** + * @brief GPIO Output Maximum frequency enumeration + */ +typedef enum +{ + GPIO_Speed_2MHz = 0x00, /*!< Low speed */ + GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ + GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ + GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) + +/** + * @brief GPIO Configuration PullUp PullDown enumeration + */ +typedef enum +{ + GPIO_PuPd_NOPULL = 0x00, + GPIO_PuPd_UP = 0x01, + GPIO_PuPd_DOWN = 0x02 +}GPIOPuPd_TypeDef; +#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ + ((PUPD) == GPIO_PuPd_DOWN)) + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIOOType_TypeDef */ + + GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIOPuPd_TypeDef */ +}GPIO_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) +/** + * @} + */ + + +/** @defgroup GPIO_Pin_sources + * @{ + */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) +/** + * @} + */ + +/** @defgroup GPIO_Alternat_function_selection_define + * @{ + */ +/** + * @brief AF 0 selection + */ +#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ +#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ + ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \ + ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \ + ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT)) +/** + * @} + */ + +/** @defgroup GPIO_Legacy + * @{ + */ + +#define GPIO_Mode_AIN GPIO_Mode_AN + +#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS +#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS +#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the GPIO configuration to the default reset state ****/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); + +/* Initialization and Configuration functions *********************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Read and Write functions **********************************************/ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Alternate functions configuration function ****************************/ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); + +#if defined(__cplusplus) && !defined(SIMU) +} +#endif + +#endif /*__STM32F2xx_GPIO_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_hash.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_hash.h index 62445fe33..2e5039e30 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_hash.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_hash.h @@ -1,250 +1,250 @@ -/** - ****************************************************************************** - * @file stm32f2xx_hash.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the HASH - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_HASH_H -#define __STM32F2xx_HASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup HASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HASH Init structure definition - */ -typedef struct -{ - uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value - of @ref HASH_Algo_Selection */ - uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value - of @ref HASH_processor_Algorithm_Mode */ - uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or - bit-string. This parameter can be a value of - @ref HASH_Data_Type */ - uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter - can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ -}HASH_InitTypeDef; - -/** - * @brief HASH message digest result structure definition - */ -typedef struct -{ - uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or - 4x 32bit words for MD5 */ -} HASH_MsgDigest; - -/** - * @brief HASH context swapping structure definition - */ -typedef struct -{ - uint32_t HASH_IMR; - uint32_t HASH_STR; - uint32_t HASH_CR; - uint32_t HASH_CSR[51]; -}HASH_Context; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HASH_Exported_Constants - * @{ - */ - -/** @defgroup HASH_Algo_Selection - * @{ - */ -#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */ -#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */ - -#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ - ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) -/** - * @} - */ - -/** @defgroup HASH_processor_Algorithm_Mode - * @{ - */ -#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */ -#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */ - -#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ - ((ALGOMODE) == HASH_AlgoMode_HMAC)) -/** - * @} - */ - -/** @defgroup HASH_Data_Type - * @{ - */ -#define HASH_DataType_32b ((uint16_t)0x0000) -#define HASH_DataType_16b ((uint16_t)0x0010) -#define HASH_DataType_8b ((uint16_t)0x0020) -#define HASH_DataType_1b ((uint16_t)0x0030) - -#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ - ((DATATYPE) == HASH_DataType_16b)|| \ - ((DATATYPE) == HASH_DataType_8b)|| \ - ((DATATYPE) == HASH_DataType_1b)) -/** - * @} - */ - -/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode - * @{ - */ -#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ -#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */ - -#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ - ((KEYTYPE) == HASH_HMACKeyType_LongKey)) -/** - * @} - */ - -/** @defgroup Number_of_valid_bits_in_last_word_of_the_message - * @{ - */ -#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F) - -/** - * @} - */ - -/** @defgroup HASH_interrupts_definition - * @{ - */ -#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/ -#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */ - -#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) -#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) - -/** - * @} - */ - -/** @defgroup HASH_flags_definition - * @{ - */ -#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/ -#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */ -#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ -#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */ -#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */ - -#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ - ((FLAG) == HASH_FLAG_DCIS) || \ - ((FLAG) == HASH_FLAG_DMAS) || \ - ((FLAG) == HASH_FLAG_BUSY) || \ - ((FLAG) == HASH_FLAG_DINNE)) - -#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \ - ((FLAG) == HASH_FLAG_DCIS)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the HASH configuration to the default reset state ****/ -void HASH_DeInit(void); - -/* HASH Configuration function ************************************************/ -void HASH_Init(HASH_InitTypeDef* HASH_InitStruct); -void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct); -void HASH_Reset(void); - -/* HASH Message Digest generation functions ***********************************/ -void HASH_DataIn(uint32_t Data); -uint8_t HASH_GetInFIFOWordsNbr(void); -void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); -void HASH_StartDigest(void); -void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); - -/* HASH Context swapping functions ********************************************/ -void HASH_SaveContext(HASH_Context* HASH_ContextSave); -void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); - -/* HASH's DMA interface function **********************************************/ -void HASH_DMACmd(FunctionalState NewState); - -/* HASH Interrupts and flags management functions *****************************/ -void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState); -FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG); -void HASH_ClearFlag(uint16_t HASH_FLAG); -ITStatus HASH_GetITStatus(uint8_t HASH_IT); -void HASH_ClearITPendingBit(uint8_t HASH_IT); - -/* High Level SHA1 functions **************************************************/ -ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); -ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, - uint8_t *Input, uint32_t Ilen, - uint8_t Output[20]); - -/* High Level MD5 functions ***************************************************/ -ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); -ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, - uint8_t *Input, uint32_t Ilen, - uint8_t Output[16]); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_HASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_hash.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the HASH + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_HASH_H +#define __STM32F2xx_HASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup HASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HASH Init structure definition + */ +typedef struct +{ + uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value + of @ref HASH_Algo_Selection */ + uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value + of @ref HASH_processor_Algorithm_Mode */ + uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or + bit-string. This parameter can be a value of + @ref HASH_Data_Type */ + uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter + can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ +}HASH_InitTypeDef; + +/** + * @brief HASH message digest result structure definition + */ +typedef struct +{ + uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or + 4x 32bit words for MD5 */ +} HASH_MsgDigest; + +/** + * @brief HASH context swapping structure definition + */ +typedef struct +{ + uint32_t HASH_IMR; + uint32_t HASH_STR; + uint32_t HASH_CR; + uint32_t HASH_CSR[51]; +}HASH_Context; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HASH_Exported_Constants + * @{ + */ + +/** @defgroup HASH_Algo_Selection + * @{ + */ +#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */ +#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */ + +#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ + ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) +/** + * @} + */ + +/** @defgroup HASH_processor_Algorithm_Mode + * @{ + */ +#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */ +#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */ + +#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ + ((ALGOMODE) == HASH_AlgoMode_HMAC)) +/** + * @} + */ + +/** @defgroup HASH_Data_Type + * @{ + */ +#define HASH_DataType_32b ((uint16_t)0x0000) +#define HASH_DataType_16b ((uint16_t)0x0010) +#define HASH_DataType_8b ((uint16_t)0x0020) +#define HASH_DataType_1b ((uint16_t)0x0030) + +#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ + ((DATATYPE) == HASH_DataType_16b)|| \ + ((DATATYPE) == HASH_DataType_8b)|| \ + ((DATATYPE) == HASH_DataType_1b)) +/** + * @} + */ + +/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode + * @{ + */ +#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ +#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */ + +#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ + ((KEYTYPE) == HASH_HMACKeyType_LongKey)) +/** + * @} + */ + +/** @defgroup Number_of_valid_bits_in_last_word_of_the_message + * @{ + */ +#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F) + +/** + * @} + */ + +/** @defgroup HASH_interrupts_definition + * @{ + */ +#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/ +#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */ + +#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) +#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) + +/** + * @} + */ + +/** @defgroup HASH_flags_definition + * @{ + */ +#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/ +#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */ +#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ +#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */ +#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */ + +#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ + ((FLAG) == HASH_FLAG_DCIS) || \ + ((FLAG) == HASH_FLAG_DMAS) || \ + ((FLAG) == HASH_FLAG_BUSY) || \ + ((FLAG) == HASH_FLAG_DINNE)) + +#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \ + ((FLAG) == HASH_FLAG_DCIS)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the HASH configuration to the default reset state ****/ +void HASH_DeInit(void); + +/* HASH Configuration function ************************************************/ +void HASH_Init(HASH_InitTypeDef* HASH_InitStruct); +void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct); +void HASH_Reset(void); + +/* HASH Message Digest generation functions ***********************************/ +void HASH_DataIn(uint32_t Data); +uint8_t HASH_GetInFIFOWordsNbr(void); +void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); +void HASH_StartDigest(void); +void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); + +/* HASH Context swapping functions ********************************************/ +void HASH_SaveContext(HASH_Context* HASH_ContextSave); +void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); + +/* HASH's DMA interface function **********************************************/ +void HASH_DMACmd(FunctionalState NewState); + +/* HASH Interrupts and flags management functions *****************************/ +void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState); +FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG); +void HASH_ClearFlag(uint16_t HASH_FLAG); +ITStatus HASH_GetITStatus(uint8_t HASH_IT); +void HASH_ClearITPendingBit(uint8_t HASH_IT); + +/* High Level SHA1 functions **************************************************/ +ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); +ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, + uint8_t *Input, uint32_t Ilen, + uint8_t Output[20]); + +/* High Level MD5 functions ***************************************************/ +ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); +ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, + uint8_t *Input, uint32_t Ilen, + uint8_t Output[16]); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_HASH_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h index 983d28d52..afff514c7 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h @@ -1,698 +1,698 @@ -/** - ****************************************************************************** - * @file stm32f2xx_i2c.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_I2C_H -#define __STM32F2xx_I2C_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2) || \ - ((PERIPH) == I2C3)) -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_NACK_position - * @{ - */ - -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ - ((POSITION) == I2C_NACKPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/** - =============================================================================== - I2C Master Events (Events grouped in order of communication) - =============================================================================== - */ - -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/** - =============================================================================== - I2C Slave Events (Events grouped in order of communication) - =============================================================================== - */ - - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of transfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/* - =============================================================================== - End of Events Description - =============================================================================== - */ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the I2C configuration to the default reset state *****/ -void I2C_DeInit(I2C_TypeDef* I2Cx); - -/* Initialization and Configuration functions *********************************/ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); - -/* PEC management functions ***************************************************/ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); - -/* DMA transfers management functions *****************************************/ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Interrupts, events and flags management functions **************************/ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); - -/* - =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - - When to use - - This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0033). - - It is also suitable for users who need to define their own events. - - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - Note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - - When to use - - This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - - The returned value could be compared to events already defined in - this file or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - - At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - - When to use - - This function could be used for specific applications or in debug - phase. - - It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor - one single event. - */ - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /*__STM32F2xx_I2C_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_i2c.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the I2C firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_I2C_H +#define __STM32F2xx_I2C_H + +#if defined(__cplusplus) && !defined(SIMU) + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2) || \ + ((PERIPH) == I2C3)) +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ + ((CYCLE) == I2C_DutyCycle_2)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ + ((STATE) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_DR ((uint8_t)0x10) +#define I2C_Register_SR1 ((uint8_t)0x14) +#define I2C_Register_SR2 ((uint8_t)0x18) +#define I2C_Register_CCR ((uint8_t)0x1C) +#define I2C_Register_TRISE ((uint8_t)0x20) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_DR) || \ + ((REGISTER) == I2C_Register_SR1) || \ + ((REGISTER) == I2C_Register_SR2) || \ + ((REGISTER) == I2C_Register_CCR) || \ + ((REGISTER) == I2C_Register_TRISE)) +/** + * @} + */ + +/** @defgroup I2C_NACK_position + * @{ + */ + +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ + ((POSITION) == I2C_NACKPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) +#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ + ((ALERT) == I2C_SMBusAlert_High)) +/** + * @} + */ + +/** @defgroup I2C_PEC_position + * @{ + */ + +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ + ((POSITION) == I2C_PECPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ + ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ + ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ + ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +/** + * @brief SR2 register flags + */ + +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/** + * @brief SR1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ + ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ + ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ + ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ + ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ + ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ + ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ + ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_SB)) +/** + * @} + */ + +/** @defgroup I2C_Events + * @{ + */ + +/** + =============================================================================== + I2C Master Events (Events grouped in order of communication) + =============================================================================== + */ + +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateSTART() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* --EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_Send7bitAddress() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_ReceiveData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/** + =============================================================================== + I2C Slave Events (Events grouped in order of communication) + =============================================================================== + */ + + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_AcknowledgeConfig()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of transfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +/* + =============================================================================== + End of Events Description + =============================================================================== + */ + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ + ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @defgroup I2C_clock_speed + * @{ + */ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the I2C configuration to the default reset state *****/ +void I2C_DeInit(I2C_TypeDef* I2Cx); + +/* Initialization and Configuration functions *********************************/ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); + +/* PEC management functions ***************************************************/ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); + +/* DMA transfers management functions *****************************************/ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); + +/* Interrupts, events and flags management functions **************************/ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); + +/* + =============================================================================== + I2C State Monitoring Functions + =============================================================================== + This I2C driver provides three different ways for I2C state monitoring + depending on the application requirements and constraints: + + + 1. Basic state monitoring (Using I2C_CheckEvent() function) + ----------------------------------------------------------- + It compares the status registers (SR1 and SR2) content to a given event + (can be the combination of one or more flags). + It returns SUCCESS if the current status includes the given flags + and returns ERROR if one or more flags are missing in the current status. + + - When to use + - This function is suitable for most applications as well as for startup + activity since the events are fully described in the product reference + manual (RM0033). + - It is also suitable for users who need to define their own events. + + - Limitations + - If an error occurs (ie. error flags are set besides to the monitored + flags), the I2C_CheckEvent() function may return SUCCESS despite + the communication hold or corrupted real state. + In this case, it is advised to use error interrupts to monitor + the error events and handle them in the interrupt IRQ handler. + + Note + For error management, it is advised to use the following functions: + - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + Where x is the peripheral instance (I2C1, I2C2 ...) + - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the + I2Cx_ER_IRQHandler() function in order to determine which error occurred. + - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + and/or I2C_GenerateStop() in order to clear the error flag and source + and return to correct communication status. + + + 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) + -------------------------------------------------------------------- + Using the function I2C_GetLastEvent() which returns the image of both status + registers in a single word (uint32_t) (Status Register 2 value is shifted left + by 16 bits and concatenated to Status Register 1). + + - When to use + - This function is suitable for the same applications above but it + allows to overcome the mentioned limitation of I2C_GetFlagStatus() + function. + - The returned value could be compared to events already defined in + this file or to custom values defined by user. + This function is suitable when multiple flags are monitored at the + same time. + - At the opposite of I2C_CheckEvent() function, this function allows + user to choose when an event is accepted (when all events flags are + set and no other flags are set or just when the needed flags are set + like I2C_CheckEvent() function. + + - Limitations + - User may need to define his own events. + - Same remark concerning the error management is applicable for this + function if user decides to check only regular communication flags + (and ignores error flags). + + + 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) + ----------------------------------------------------------------------- + + Using the function I2C_GetFlagStatus() which simply returns the status of + one single flag (ie. I2C_FLAG_RXNE ...). + + - When to use + - This function could be used for specific applications or in debug + phase. + - It is suitable when only one flag checking is needed (most I2C + events are monitored through multiple flags). + - Limitations: + - When calling this function, the Status register is accessed. + Some flags are cleared when the status register is accessed. + So checking the status of one Flag, may clear other ones. + - Function may need to be called twice or more in order to monitor + one single event. + */ + +/* + =============================================================================== + 1. Basic state monitoring + =============================================================================== + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/* + =============================================================================== + 2. Advanced state monitoring + =============================================================================== + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/* + =============================================================================== + 3. Flag-based state monitoring + =============================================================================== + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#if defined(__cplusplus) && !defined(SIMU) +} +#endif + +#endif /*__STM32F2xx_I2C_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_iwdg.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_iwdg.h index e689bd763..731ca2f64 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_iwdg.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_iwdg.h @@ -1,131 +1,131 @@ -/** - ****************************************************************************** - * @file stm32f2xx_iwdg.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_IWDG_H -#define __STM32F2xx_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Prescaler and Counter configuration functions ******************************/ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); - -/* IWDG activation function ***************************************************/ -void IWDG_Enable(void); - -/* Flag management function ***************************************************/ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_IWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_iwdg.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IWDG_H +#define __STM32F2xx_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Prescaler and Counter configuration functions ******************************/ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); + +/* IWDG activation function ***************************************************/ +void IWDG_Enable(void); + +/* Flag management function ***************************************************/ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h index 459b39dce..33b6d686b 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h @@ -1,166 +1,166 @@ -/** - ****************************************************************************** - * @file stm32f2xx_pwr.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_PWR_H -#define __STM32F2xx_PWR_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level - * @{ - */ - -#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ - ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ - ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ - ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) -/** - * @} - */ - - -/** @defgroup PWR_Regulator_state_in_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower PWR_CR_LPDS -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_BRR PWR_CSR_BRR - -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the PWR configuration to the default reset state ******/ -void PWR_DeInit(void); - -/* Backup Domain Access function **********************************************/ -void PWR_BackupAccessCmd(FunctionalState NewState); - -/* PVD configuration functions ************************************************/ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_PVDCmd(FunctionalState NewState); - -/* WakeUp pins configuration functions ****************************************/ -void PWR_WakeUpPinCmd(FunctionalState NewState); - -/* Backup Regulator configuration functions ***********************************/ -void PWR_BackupRegulatorCmd(FunctionalState NewState); - -/* FLASH Power Down configuration functions ***********************************/ -void PWR_FlashPowerDownCmd(FunctionalState NewState); - -/* Low Power modes configuration functions ************************************/ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); - -/* Flags management functions *************************************************/ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /* __STM32F2xx_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_pwr.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_PWR_H +#define __STM32F2xx_PWR_H + +#if defined(__cplusplus) && !defined(SIMU) + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level + * @{ + */ + +#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 + +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ + ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ + ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ + ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) +/** + * @} + */ + + +/** @defgroup PWR_Regulator_state_in_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower PWR_CR_LPDS +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_BRR PWR_CSR_BRR + +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the PWR configuration to the default reset state ******/ +void PWR_DeInit(void); + +/* Backup Domain Access function **********************************************/ +void PWR_BackupAccessCmd(FunctionalState NewState); + +/* PVD configuration functions ************************************************/ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_PVDCmd(FunctionalState NewState); + +/* WakeUp pins configuration functions ****************************************/ +void PWR_WakeUpPinCmd(FunctionalState NewState); + +/* Backup Regulator configuration functions ***********************************/ +void PWR_BackupRegulatorCmd(FunctionalState NewState); + +/* FLASH Power Down configuration functions ***********************************/ +void PWR_FlashPowerDownCmd(FunctionalState NewState); + +/* Low Power modes configuration functions ************************************/ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); + +/* Flags management functions *************************************************/ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#if defined(__cplusplus) && !defined(SIMU) +} +#endif + +#endif /* __STM32F2xx_PWR_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h index f28c8745c..ece02058c 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h @@ -1,515 +1,515 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rcc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the RCC firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_RCC_H -#define __STM32F2xx_RCC_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup RCC_HSE_configuration - * @{ - */ -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_Bypass ((uint8_t)0x05) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source - * @{ - */ -#define RCC_PLLSource_HSI ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE ((uint32_t)0x00400000) -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ - ((SOURCE) == RCC_PLLSource_HSE)) -#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) -#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) -#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) - -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source - * @{ - */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source - * @{ - */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source - * @{ - */ -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00001000) -#define RCC_HCLK_Div4 ((uint32_t)0x00001400) -#define RCC_HCLK_Div8 ((uint32_t)0x00001800) -#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_Source - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) -#define RCC_IT_CSS ((uint8_t)0x80) -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLLI2SRDY)) -#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration - * @{ - */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source - * @{ - */ -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) -#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) -#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) -#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) -#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) -#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) -#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) -#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) -#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) -#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) -#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) -#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) -#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) -#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) -#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) -#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) -#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) -#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) -#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) -#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) -#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) -#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) -#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) -#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) -#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) -#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) -#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) -#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) -#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) -#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) -/** - * @} - */ - -/** @defgroup RCC_I2S_Clock_Source - * @{ - */ -#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) -#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) - -#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripherals - * @{ - */ -#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) -#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) -#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) -#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) -#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) -#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) -#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) -#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) -#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) -#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) -#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) -#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) -#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) -#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) -#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) -#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) -#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) -#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) -#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) -#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) -#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) -#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) -#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripherals - * @{ - */ -#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) -#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) -#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) -#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) -#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) -#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_AHB3_Peripherals - * @{ - */ -#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) -#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripherals - * @{ - */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripherals - * @{ - */ -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) -#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) -#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) -#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) -#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) -#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) -#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) -#define RCC_MCO1Div_1 ((uint32_t)0x00000000) -#define RCC_MCO1Div_2 ((uint32_t)0x04000000) -#define RCC_MCO1Div_3 ((uint32_t)0x05000000) -#define RCC_MCO1Div_4 ((uint32_t)0x06000000) -#define RCC_MCO1Div_5 ((uint32_t)0x07000000) -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ - ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) - -#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ - ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ - ((DIV) == RCC_MCO1Div_5)) -/** - * @} - */ - -/** @defgroup RCC_MCO2_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) -#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) -#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) -#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) -#define RCC_MCO2Div_1 ((uint32_t)0x00000000) -#define RCC_MCO2Div_2 ((uint32_t)0x20000000) -#define RCC_MCO2Div_3 ((uint32_t)0x28000000) -#define RCC_MCO2Div_4 ((uint32_t)0x30000000) -#define RCC_MCO2Div_5 ((uint32_t)0x38000000) -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ - ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) - -#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ - ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ - ((DIV) == RCC_MCO2Div_5)) -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_BORRST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ - ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ - ((FLAG) == RCC_FLAG_PLLI2SRDY)) -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RCC clock configuration to the default reset state */ -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); - -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); -void RCC_PLLI2SCmd(FunctionalState NewState); - -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); - -/* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); - -/* Peripheral clocks configuration functions **********************************/ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); - -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /* __STM32F2xx_RCC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_rcc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the RCC firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_RCC_H +#define __STM32F2xx_RCC_H + +#if defined(__cplusplus) && !defined(SIMU) + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup RCC_HSE_configuration + * @{ + */ +#define RCC_HSE_OFF ((uint8_t)0x00) +#define RCC_HSE_ON ((uint8_t)0x01) +#define RCC_HSE_Bypass ((uint8_t)0x05) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source + * @{ + */ +#define RCC_PLLSource_HSI ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE ((uint32_t)0x00400000) +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ + ((SOURCE) == RCC_PLLSource_HSE)) +#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) +#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) + +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source + * @{ + */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source + * @{ + */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source + * @{ + */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00001000) +#define RCC_HCLK_Div4 ((uint32_t)0x00001400) +#define RCC_HCLK_Div8 ((uint32_t)0x00001800) +#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_Source + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) +#define RCC_IT_CSS ((uint8_t)0x80) +#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLLI2SRDY)) +#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration + * @{ + */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source + * @{ + */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) +#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) +#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) +#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) +#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) +#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) +#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) +#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) +#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) +#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) +#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) +#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) +#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) +#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) +#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) +#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) +#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) +#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) +#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) +#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) +#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) +#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) +#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) +#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) +#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) +#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) +#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) +#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) +#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) +#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) +/** + * @} + */ + +/** @defgroup RCC_I2S_Clock_Source + * @{ + */ +#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) +#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) + +#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripherals + * @{ + */ +#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) +#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) +#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) +#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) +#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) +#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) +#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) +#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) +#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) +#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) +#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) +#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) +#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) +#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) +#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) +#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) +#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) +#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) +#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) +#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) +#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) +#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) +#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripherals + * @{ + */ +#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) +#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) +#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) +#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) +#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) +#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_AHB3_Peripherals + * @{ + */ +#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) +#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripherals + * @{ + */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripherals + * @{ + */ +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) +#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) +#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) +#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source_Prescaler + * @{ + */ +#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) +#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) +#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) +#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) +#define RCC_MCO1Div_1 ((uint32_t)0x00000000) +#define RCC_MCO1Div_2 ((uint32_t)0x04000000) +#define RCC_MCO1Div_3 ((uint32_t)0x05000000) +#define RCC_MCO1Div_4 ((uint32_t)0x06000000) +#define RCC_MCO1Div_5 ((uint32_t)0x07000000) +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ + ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) + +#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ + ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ + ((DIV) == RCC_MCO1Div_5)) +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source_Prescaler + * @{ + */ +#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) +#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) +#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) +#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) +#define RCC_MCO2Div_1 ((uint32_t)0x00000000) +#define RCC_MCO2Div_2 ((uint32_t)0x20000000) +#define RCC_MCO2Div_3 ((uint32_t)0x28000000) +#define RCC_MCO2Div_4 ((uint32_t)0x30000000) +#define RCC_MCO2Div_5 ((uint32_t)0x38000000) +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) + +#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ + ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ + ((DIV) == RCC_MCO2Div_5)) +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_BORRST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ + ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ + ((FLAG) == RCC_FLAG_PLLI2SRDY)) +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RCC clock configuration to the default reset state */ +void RCC_DeInit(void); + +/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ +void RCC_HSEConfig(uint8_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); + +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); +void RCC_PLLI2SCmd(FunctionalState NewState); + +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); +void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); + +/* System, AHB and APB busses clocks configuration functions ******************/ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); + +/* Peripheral clocks configuration functions **********************************/ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); + +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#if defined(__cplusplus) && !defined(SIMU) +} +#endif + +#endif /* __STM32F2xx_RCC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rng.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rng.h index c2b52e686..72f33cb24 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rng.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rng.h @@ -1,120 +1,120 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rng.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the Random - * Number Generator(RNG) firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_RNG_H -#define __STM32F2xx_RNG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RNG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RNG_Exported_Constants - * @{ - */ - -/** @defgroup RNG_flags_definition - * @{ - */ -#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ -#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ -#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ - -#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ - ((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -/** - * @} - */ - -/** @defgroup RNG_interrupts_definition - * @{ - */ -#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ -#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ - -#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) -#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RNG configuration to the default reset state *****/ -void RNG_DeInit(void); - -/* Configuration function *****************************************************/ -void RNG_Cmd(FunctionalState NewState); - -/* Get 32 bit Random number function ******************************************/ -uint32_t RNG_GetRandomNumber(void); - -/* Interrupts and flags management functions **********************************/ -void RNG_ITConfig(FunctionalState NewState); -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); -void RNG_ClearFlag(uint8_t RNG_FLAG); -ITStatus RNG_GetITStatus(uint8_t RNG_IT); -void RNG_ClearITPendingBit(uint8_t RNG_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_RNG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_rng.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the Random + * Number Generator(RNG) firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_RNG_H +#define __STM32F2xx_RNG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RNG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RNG_Exported_Constants + * @{ + */ + +/** @defgroup RNG_flags_definition + * @{ + */ +#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ +#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ +#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ + +#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ + ((RNG_FLAG) == RNG_FLAG_CECS) || \ + ((RNG_FLAG) == RNG_FLAG_SECS)) +#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ + ((RNG_FLAG) == RNG_FLAG_SECS)) +/** + * @} + */ + +/** @defgroup RNG_interrupts_definition + * @{ + */ +#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ +#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ + +#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) +#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RNG configuration to the default reset state *****/ +void RNG_DeInit(void); + +/* Configuration function *****************************************************/ +void RNG_Cmd(FunctionalState NewState); + +/* Get 32 bit Random number function ******************************************/ +uint32_t RNG_GetRandomNumber(void); + +/* Interrupts and flags management functions **********************************/ +void RNG_ITConfig(FunctionalState NewState); +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); +void RNG_ClearFlag(uint8_t RNG_FLAG); +ITStatus RNG_GetITStatus(uint8_t RNG_IT); +void RNG_ClearITPendingBit(uint8_t RNG_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_RNG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h index 69ec3d29a..31d4cd811 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h @@ -1,650 +1,650 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rtc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_RTC_H -#define __STM32F2xx_RTC_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be set to a value lower than 0x7F */ - - uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be set to a value lower than 0x1FFF */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. - This parameter must be set to a value in the 0-12 range - if the RTC_HourFormat_12 is selected or 0-23 range if - the RTC_HourFormat_24 is selected. */ - - uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t RTC_Date; /*!< Specifies the RTC Date. - This parameter must be set to a value in the 1-31 range. */ - - uint8_t RTC_Year; /*!< Specifies the RTC Date Year. - This parameter must be set to a value in the 0-99 range. */ -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter - must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this - parameter can be a value of @ref RTC_WeekDay_Definitions */ -}RTC_AlarmTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - - -/** @defgroup RTC_Hour_Formats - * @{ - */ -#define RTC_HourFormat_24 ((uint32_t)0x00000000) -#define RTC_HourFormat_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ - ((FORMAT) == RTC_HourFormat_24)) -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) - -/** - * @} - */ - - -/** @defgroup RTC_Synchronous_Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFF) - -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) - -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions - * @{ - */ -#define RTC_H12_AM ((uint8_t)0x00) -#define RTC_H12_PM ((uint8_t)0x40) -#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) - -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_Month_January ((uint8_t)0x01) -#define RTC_Month_February ((uint8_t)0x02) -#define RTC_Month_March ((uint8_t)0x03) -#define RTC_Month_April ((uint8_t)0x04) -#define RTC_Month_May ((uint8_t)0x05) -#define RTC_Month_June ((uint8_t)0x06) -#define RTC_Month_July ((uint8_t)0x07) -#define RTC_Month_August ((uint8_t)0x08) -#define RTC_Month_September ((uint8_t)0x09) -#define RTC_Month_October ((uint8_t)0x10) -#define RTC_Month_November ((uint8_t)0x11) -#define RTC_Month_December ((uint8_t)0x12) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions - * @{ - */ - -#define RTC_Weekday_Monday ((uint8_t)0x01) -#define RTC_Weekday_Tuesday ((uint8_t)0x02) -#define RTC_Weekday_Wednesday ((uint8_t)0x03) -#define RTC_Weekday_Thursday ((uint8_t)0x04) -#define RTC_Weekday_Friday ((uint8_t)0x05) -#define RTC_Weekday_Saturday ((uint8_t)0x06) -#define RTC_Weekday_Sunday ((uint8_t)0x07) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) -/** - * @} - */ - - -/** @defgroup RTC_Alarm_Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions - * @{ - */ -#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) -#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ - ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions - * @{ - */ -#define RTC_AlarmMask_None ((uint32_t)0x00000000) -#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) -#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) -#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) -#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) -#define RTC_AlarmMask_All ((uint32_t)0x80808080) -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions - * @{ - */ -#define RTC_Alarm_A ((uint32_t)0x00000100) -#define RTC_Alarm_B ((uint32_t)0x00000200) -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) -#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Wakeup_Timer_Definitions - * @{ - */ -#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) -#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) -#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) -#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) -#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) -#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTC_Time_Stamp_Edges_definitions - * @{ - */ -#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) -#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) -#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ - ((EDGE) == RTC_TimeStampEdge_Falling)) -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions - * @{ - */ -#define RTC_Output_Disable ((uint32_t)0x00000000) -#define RTC_Output_AlarmA ((uint32_t)0x00200000) -#define RTC_Output_AlarmB ((uint32_t)0x00400000) -#define RTC_Output_WakeUp ((uint32_t)0x00600000) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ - ((OUTPUT) == RTC_Output_AlarmA) || \ - ((OUTPUT) == RTC_Output_AlarmB) || \ - ((OUTPUT) == RTC_Output_WakeUp)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions - * @{ - */ -#define RTC_OutputPolarity_High ((uint32_t)0x00000000) -#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ - ((POL) == RTC_OutputPolarity_Low)) -/** - * @} - */ - - -/** @defgroup RTC_Digital_Calibration_Definitions - * @{ - */ -#define RTC_CalibSign_Positive ((uint32_t)0x00000000) -#define RTC_CalibSign_Negative ((uint32_t)0x00000080) -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ - ((SIGN) == RTC_CalibSign_Negative)) -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) - -/** - * @} - */ - - -/** @defgroup RTC_DayLightSaving_Definitions - * @{ - */ -#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) -#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ - ((SAVE) == RTC_DayLightSaving_ADD1H)) - -#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) -#define RTC_StoreOperation_Set ((uint32_t)0x00040000) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ - ((OPERATION) == RTC_StoreOperation_Set)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Trigger_Definitions - * @{ - */ -#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) -#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_FallingEdge)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pins_Definitions - * @{ - */ -#define RTC_Tamper_1 RTC_TAFCR_TAMP1E -#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pin_Selection - * @{ - */ -#define RTC_TamperPin_PC13 ((uint32_t)0x00000000) -#define RTC_TamperPin_PI8 ((uint32_t)0x00010000) -#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ - ((PIN) == RTC_TamperPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_TimeStamp_Pin_Selection - * @{ - */ -#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) -#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) -#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ - ((PIN) == RTC_TimeStampPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT - * @{ - */ -#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) -#define RTC_OutputType_PushPull ((uint32_t)0x00040000) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ - ((TYPE) == RTC_OutputType_PushPull)) - -/** - * @} - */ - -/** @defgroup RTC_Backup_Registers_Definitions - * @{ - */ - -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4) || \ - ((BKP) == RTC_BKP_DR5) || \ - ((BKP) == RTC_BKP_DR6) || \ - ((BKP) == RTC_BKP_DR7) || \ - ((BKP) == RTC_BKP_DR8) || \ - ((BKP) == RTC_BKP_DR9) || \ - ((BKP) == RTC_BKP_DR10) || \ - ((BKP) == RTC_BKP_DR11) || \ - ((BKP) == RTC_BKP_DR12) || \ - ((BKP) == RTC_BKP_DR13) || \ - ((BKP) == RTC_BKP_DR14) || \ - ((BKP) == RTC_BKP_DR15) || \ - ((BKP) == RTC_BKP_DR16) || \ - ((BKP) == RTC_BKP_DR17) || \ - ((BKP) == RTC_BKP_DR18) || \ - ((BKP) == RTC_BKP_DR19)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions - * @{ - */ -#define RTC_Format_BIN ((uint32_t)0x000000000) -#define RTC_Format_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) - -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions - * @{ - */ -#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) -#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) -#define RTC_FLAG_TSF ((uint32_t)0x00000800) -#define RTC_FLAG_WUTF ((uint32_t)0x00000400) -#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) -#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) -#define RTC_FLAG_INITF ((uint32_t)0x00000040) -#define RTC_FLAG_RSF ((uint32_t)0x00000020) -#define RTC_FLAG_INITS ((uint32_t)0x00000010) -#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) -#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) -#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ - ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ - ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ - ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ - ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ - ((FLAG) == RTC_FLAG_TAMP1F)) -#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFC0DF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRB ((uint32_t)0x00002000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) - -#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ - ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ - ((IT) == RTC_IT_TAMP1)) -#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Legacy - * @{ - */ -#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig -#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RTC configuration to the default reset state *****/ -ErrorStatus RTC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); -void RTC_WriteProtectionCmd(FunctionalState NewState); -ErrorStatus RTC_EnterInitMode(void); -void RTC_ExitInitMode(void); -ErrorStatus RTC_WaitForSynchro(void); -ErrorStatus RTC_RefClockCmd(FunctionalState NewState); - -/* Time and Date configuration functions **************************************/ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); - -/* Alarms (Alarm A and Alarm B) configuration functions **********************/ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); - -/* WakeUp Timer configuration functions ***************************************/ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); -uint32_t RTC_GetWakeUpCounter(void); -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); - -/* Daylight Saving configuration functions ************************************/ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); -uint32_t RTC_GetStoreOperation(void); - -/* Output pin Configuration function ******************************************/ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); - -/* Coarse Calibration configuration functions *********************************/ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); -void RTC_CalibOutputCmd(FunctionalState NewState); - -/* TimeStamp configuration functions ******************************************/ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct); - -/* Tampers configuration functions ********************************************/ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); - -/* Backup Data Registers configuration functions ******************************/ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); - -/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - functions ******************************************************************/ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin); -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); -void RTC_OutputTypeConfig(uint32_t RTC_OutputType); - -/* Interrupts and flags management functions **********************************/ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); -void RTC_ClearFlag(uint32_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint32_t RTC_IT); -void RTC_ClearITPendingBit(uint32_t RTC_IT); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /*__STM32F2xx_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_rtc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_RTC_H +#define __STM32F2xx_RTC_H + +#if defined(__cplusplus) && !defined(SIMU) + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be set to a value lower than 0x7F */ + + uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be set to a value lower than 0x1FFF */ +}RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. + This parameter must be set to a value in the 0-12 range + if the RTC_HourFormat_12 is selected or 0-23 range if + the RTC_HourFormat_24 is selected. */ + + uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ +}RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t RTC_Date; /*!< Specifies the RTC Date. + This parameter must be set to a value in the 1-31 range. */ + + uint8_t RTC_Year; /*!< Specifies the RTC Date Year. + This parameter must be set to a value in the 0-99 range. */ +}RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter + must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this + parameter can be a value of @ref RTC_WeekDay_Definitions */ +}RTC_AlarmTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + + +/** @defgroup RTC_Hour_Formats + * @{ + */ +#define RTC_HourFormat_24 ((uint32_t)0x00000000) +#define RTC_HourFormat_12 ((uint32_t)0x00000040) +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ + ((FORMAT) == RTC_HourFormat_24)) +/** + * @} + */ + +/** @defgroup RTC_Asynchronous_Predivider + * @{ + */ +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) + +/** + * @} + */ + + +/** @defgroup RTC_Synchronous_Predivider + * @{ + */ +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFF) + +/** + * @} + */ + +/** @defgroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) + +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_H12_AM ((uint8_t)0x00) +#define RTC_H12_PM ((uint8_t)0x40) +#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) + +/** + * @} + */ + +/** @defgroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) + +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_Month_January ((uint8_t)0x01) +#define RTC_Month_February ((uint8_t)0x02) +#define RTC_Month_March ((uint8_t)0x03) +#define RTC_Month_April ((uint8_t)0x04) +#define RTC_Month_May ((uint8_t)0x05) +#define RTC_Month_June ((uint8_t)0x06) +#define RTC_Month_July ((uint8_t)0x07) +#define RTC_Month_August ((uint8_t)0x08) +#define RTC_Month_September ((uint8_t)0x09) +#define RTC_Month_October ((uint8_t)0x10) +#define RTC_Month_November ((uint8_t)0x11) +#define RTC_Month_December ((uint8_t)0x12) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions + * @{ + */ + +#define RTC_Weekday_Monday ((uint8_t)0x01) +#define RTC_Weekday_Tuesday ((uint8_t)0x02) +#define RTC_Weekday_Wednesday ((uint8_t)0x03) +#define RTC_Weekday_Thursday ((uint8_t)0x04) +#define RTC_Weekday_Friday ((uint8_t)0x05) +#define RTC_Weekday_Saturday ((uint8_t)0x06) +#define RTC_Weekday_Sunday ((uint8_t)0x07) +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) +/** + * @} + */ + + +/** @defgroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmDateWeekDay_Definitions + * @{ + */ +#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) +#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ + ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_AlarmMask_None ((uint32_t)0x00000000) +#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) +#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) +#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) +#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) +#define RTC_AlarmMask_All ((uint32_t)0x80808080) +#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions + * @{ + */ +#define RTC_Alarm_A ((uint32_t)0x00000100) +#define RTC_Alarm_B ((uint32_t)0x00000200) +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) +#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup RTC_Wakeup_Timer_Definitions + * @{ + */ +#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) +#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) +#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) +#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) +#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) +#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ + ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ + ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +/** + * @} + */ + +/** @defgroup RTC_Time_Stamp_Edges_definitions + * @{ + */ +#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) +#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) +#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ + ((EDGE) == RTC_TimeStampEdge_Falling)) +/** + * @} + */ + +/** @defgroup RTC_Output_selection_Definitions + * @{ + */ +#define RTC_Output_Disable ((uint32_t)0x00000000) +#define RTC_Output_AlarmA ((uint32_t)0x00200000) +#define RTC_Output_AlarmB ((uint32_t)0x00400000) +#define RTC_Output_WakeUp ((uint32_t)0x00600000) + +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ + ((OUTPUT) == RTC_Output_AlarmA) || \ + ((OUTPUT) == RTC_Output_AlarmB) || \ + ((OUTPUT) == RTC_Output_WakeUp)) + +/** + * @} + */ + +/** @defgroup RTC_Output_Polarity_Definitions + * @{ + */ +#define RTC_OutputPolarity_High ((uint32_t)0x00000000) +#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ + ((POL) == RTC_OutputPolarity_Low)) +/** + * @} + */ + + +/** @defgroup RTC_Digital_Calibration_Definitions + * @{ + */ +#define RTC_CalibSign_Positive ((uint32_t)0x00000000) +#define RTC_CalibSign_Negative ((uint32_t)0x00000080) +#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ + ((SIGN) == RTC_CalibSign_Negative)) +#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) + +/** + * @} + */ + + +/** @defgroup RTC_DayLightSaving_Definitions + * @{ + */ +#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) +#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ + ((SAVE) == RTC_DayLightSaving_ADD1H)) + +#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) +#define RTC_StoreOperation_Set ((uint32_t)0x00040000) +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ + ((OPERATION) == RTC_StoreOperation_Set)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Trigger_Definitions + * @{ + */ +#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) +#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pins_Definitions + * @{ + */ +#define RTC_Tamper_1 RTC_TAFCR_TAMP1E +#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pin_Selection + * @{ + */ +#define RTC_TamperPin_PC13 ((uint32_t)0x00000000) +#define RTC_TamperPin_PI8 ((uint32_t)0x00010000) +#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ + ((PIN) == RTC_TamperPin_PI8)) +/** + * @} + */ + +/** @defgroup RTC_TimeStamp_Pin_Selection + * @{ + */ +#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) +#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) +#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ + ((PIN) == RTC_TimeStampPin_PI8)) +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT + * @{ + */ +#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) +#define RTC_OutputType_PushPull ((uint32_t)0x00040000) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ + ((TYPE) == RTC_OutputType_PushPull)) + +/** + * @} + */ + +/** @defgroup RTC_Backup_Registers_Definitions + * @{ + */ + +#define RTC_BKP_DR0 ((uint32_t)0x00000000) +#define RTC_BKP_DR1 ((uint32_t)0x00000001) +#define RTC_BKP_DR2 ((uint32_t)0x00000002) +#define RTC_BKP_DR3 ((uint32_t)0x00000003) +#define RTC_BKP_DR4 ((uint32_t)0x00000004) +#define RTC_BKP_DR5 ((uint32_t)0x00000005) +#define RTC_BKP_DR6 ((uint32_t)0x00000006) +#define RTC_BKP_DR7 ((uint32_t)0x00000007) +#define RTC_BKP_DR8 ((uint32_t)0x00000008) +#define RTC_BKP_DR9 ((uint32_t)0x00000009) +#define RTC_BKP_DR10 ((uint32_t)0x0000000A) +#define RTC_BKP_DR11 ((uint32_t)0x0000000B) +#define RTC_BKP_DR12 ((uint32_t)0x0000000C) +#define RTC_BKP_DR13 ((uint32_t)0x0000000D) +#define RTC_BKP_DR14 ((uint32_t)0x0000000E) +#define RTC_BKP_DR15 ((uint32_t)0x0000000F) +#define RTC_BKP_DR16 ((uint32_t)0x00000010) +#define RTC_BKP_DR17 ((uint32_t)0x00000011) +#define RTC_BKP_DR18 ((uint32_t)0x00000012) +#define RTC_BKP_DR19 ((uint32_t)0x00000013) +#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ + ((BKP) == RTC_BKP_DR1) || \ + ((BKP) == RTC_BKP_DR2) || \ + ((BKP) == RTC_BKP_DR3) || \ + ((BKP) == RTC_BKP_DR4) || \ + ((BKP) == RTC_BKP_DR5) || \ + ((BKP) == RTC_BKP_DR6) || \ + ((BKP) == RTC_BKP_DR7) || \ + ((BKP) == RTC_BKP_DR8) || \ + ((BKP) == RTC_BKP_DR9) || \ + ((BKP) == RTC_BKP_DR10) || \ + ((BKP) == RTC_BKP_DR11) || \ + ((BKP) == RTC_BKP_DR12) || \ + ((BKP) == RTC_BKP_DR13) || \ + ((BKP) == RTC_BKP_DR14) || \ + ((BKP) == RTC_BKP_DR15) || \ + ((BKP) == RTC_BKP_DR16) || \ + ((BKP) == RTC_BKP_DR17) || \ + ((BKP) == RTC_BKP_DR18) || \ + ((BKP) == RTC_BKP_DR19)) +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions + * @{ + */ +#define RTC_Format_BIN ((uint32_t)0x000000000) +#define RTC_Format_BCD ((uint32_t)0x000000001) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) + +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) +#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) +#define RTC_FLAG_TSF ((uint32_t)0x00000800) +#define RTC_FLAG_WUTF ((uint32_t)0x00000400) +#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) +#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) +#define RTC_FLAG_INITF ((uint32_t)0x00000040) +#define RTC_FLAG_RSF ((uint32_t)0x00000020) +#define RTC_FLAG_INITS ((uint32_t)0x00000010) +#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) +#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) +#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ + ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ + ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ + ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ + ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ + ((FLAG) == RTC_FLAG_TAMP1F)) +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFC0DF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions + * @{ + */ +#define RTC_IT_TS ((uint32_t)0x00008000) +#define RTC_IT_WUT ((uint32_t)0x00004000) +#define RTC_IT_ALRB ((uint32_t)0x00002000) +#define RTC_IT_ALRA ((uint32_t)0x00001000) +#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TAMP1 ((uint32_t)0x00020000) + +#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ + ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ + ((IT) == RTC_IT_TAMP1)) +#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup RTC_Legacy + * @{ + */ +#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig +#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RTC configuration to the default reset state *****/ +ErrorStatus RTC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); +void RTC_WriteProtectionCmd(FunctionalState NewState); +ErrorStatus RTC_EnterInitMode(void); +void RTC_ExitInitMode(void); +ErrorStatus RTC_WaitForSynchro(void); +ErrorStatus RTC_RefClockCmd(FunctionalState NewState); + +/* Time and Date configuration functions **************************************/ +ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); +void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); + +/* Alarms (Alarm A and Alarm B) configuration functions **********************/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); + +/* WakeUp Timer configuration functions ***************************************/ +void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); +uint32_t RTC_GetWakeUpCounter(void); +ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); + +/* Daylight Saving configuration functions ************************************/ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void); + +/* Output pin Configuration function ******************************************/ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); + +/* Coarse Calibration configuration functions *********************************/ +ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); +ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); +void RTC_CalibOutputCmd(FunctionalState NewState); + +/* TimeStamp configuration functions ******************************************/ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, + RTC_DateTypeDef* RTC_StampDateStruct); + +/* Tampers configuration functions ********************************************/ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); + +/* Backup Data Registers configuration functions ******************************/ +void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); +uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); + +/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration + functions ******************************************************************/ +void RTC_TamperPinSelection(uint32_t RTC_TamperPin); +void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); +void RTC_OutputTypeConfig(uint32_t RTC_OutputType); + +/* Interrupts and flags management functions **********************************/ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +void RTC_ClearFlag(uint32_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint32_t RTC_IT); +void RTC_ClearITPendingBit(uint32_t RTC_IT); + +#if defined(__cplusplus) && !defined(SIMU) +} +#endif + +#endif /*__STM32F2xx_RTC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_sdio.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_sdio.h index 16efdeeb2..dbe2e3d3a 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_sdio.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_sdio.h @@ -1,536 +1,536 @@ -/** - ****************************************************************************** - * @file stm32f2xx_sdio.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the SDIO firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_SDIO_H -#define __STM32F2xx_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - -typedef struct -{ - uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ - -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ - ((EDGE) == SDIO_ClockEdge_Falling)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass - * @{ - */ - -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ - ((BYPASS) == SDIO_ClockBypass_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Power_Save - * @{ - */ - -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ - ((SAVE) == SDIO_ClockPowerSave_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Bus_Wide - * @{ - */ - -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ - ((WIDE) == SDIO_BusWide_8b)) - -/** - * @} - */ - -/** @defgroup SDIO_Hardware_Flow_Control - * @{ - */ - -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ - ((CONTROL) == SDIO_HardwareFlowControl_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ - -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) -#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) -/** - * @} - */ - - -/** @defgroup SDIO_Interrupt_sources - * @{ - */ - -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup SDIO_Command_Index - * @{ - */ - -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ - -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ - ((RESPONSE) == SDIO_Response_Short) || \ - ((RESPONSE) == SDIO_Response_Long)) -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ - -#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ -#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ -#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ - ((WAIT) == SDIO_Wait_Pend)) -/** - * @} - */ - -/** @defgroup SDIO_CPSM_State - * @{ - */ - -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ - -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDIO_Data_Length - * @{ - */ - -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ - -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ - ((SIZE) == SDIO_DataBlockSize_2b) || \ - ((SIZE) == SDIO_DataBlockSize_4b) || \ - ((SIZE) == SDIO_DataBlockSize_8b) || \ - ((SIZE) == SDIO_DataBlockSize_16b) || \ - ((SIZE) == SDIO_DataBlockSize_32b) || \ - ((SIZE) == SDIO_DataBlockSize_64b) || \ - ((SIZE) == SDIO_DataBlockSize_128b) || \ - ((SIZE) == SDIO_DataBlockSize_256b) || \ - ((SIZE) == SDIO_DataBlockSize_512b) || \ - ((SIZE) == SDIO_DataBlockSize_1024b) || \ - ((SIZE) == SDIO_DataBlockSize_2048b) || \ - ((SIZE) == SDIO_DataBlockSize_4096b) || \ - ((SIZE) == SDIO_DataBlockSize_8192b) || \ - ((SIZE) == SDIO_DataBlockSize_16384b)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ - -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ - ((DIR) == SDIO_TransferDir_ToSDIO)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Type - * @{ - */ - -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ - ((MODE) == SDIO_TransferMode_Block)) -/** - * @} - */ - -/** @defgroup SDIO_DPSM_State - * @{ - */ - -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Flags - * @{ - */ - -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_TXUNDERR) || \ - ((FLAG) == SDIO_FLAG_RXOVERR) || \ - ((FLAG) == SDIO_FLAG_CMDREND) || \ - ((FLAG) == SDIO_FLAG_CMDSENT) || \ - ((FLAG) == SDIO_FLAG_DATAEND) || \ - ((FLAG) == SDIO_FLAG_STBITERR) || \ - ((FLAG) == SDIO_FLAG_DBCKEND) || \ - ((FLAG) == SDIO_FLAG_CMDACT) || \ - ((FLAG) == SDIO_FLAG_TXACT) || \ - ((FLAG) == SDIO_FLAG_RXACT) || \ - ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOF) || \ - ((FLAG) == SDIO_FLAG_RXFIFOF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOE) || \ - ((FLAG) == SDIO_FLAG_TXDAVL) || \ - ((FLAG) == SDIO_FLAG_RXDAVL) || \ - ((FLAG) == SDIO_FLAG_SDIOIT) || \ - ((FLAG) == SDIO_FLAG_CEATAEND)) - -#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) - -#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ - ((IT) == SDIO_IT_DCRCFAIL) || \ - ((IT) == SDIO_IT_CTIMEOUT) || \ - ((IT) == SDIO_IT_DTIMEOUT) || \ - ((IT) == SDIO_IT_TXUNDERR) || \ - ((IT) == SDIO_IT_RXOVERR) || \ - ((IT) == SDIO_IT_CMDREND) || \ - ((IT) == SDIO_IT_CMDSENT) || \ - ((IT) == SDIO_IT_DATAEND) || \ - ((IT) == SDIO_IT_STBITERR) || \ - ((IT) == SDIO_IT_DBCKEND) || \ - ((IT) == SDIO_IT_CMDACT) || \ - ((IT) == SDIO_IT_TXACT) || \ - ((IT) == SDIO_IT_RXACT) || \ - ((IT) == SDIO_IT_TXFIFOHE) || \ - ((IT) == SDIO_IT_RXFIFOHF) || \ - ((IT) == SDIO_IT_TXFIFOF) || \ - ((IT) == SDIO_IT_RXFIFOF) || \ - ((IT) == SDIO_IT_TXFIFOE) || \ - ((IT) == SDIO_IT_RXFIFOE) || \ - ((IT) == SDIO_IT_TXDAVL) || \ - ((IT) == SDIO_IT_RXDAVL) || \ - ((IT) == SDIO_IT_SDIOIT) || \ - ((IT) == SDIO_IT_CEATAEND)) - -#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ - -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ - ((MODE) == SDIO_ReadWaitMode_DATA2)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/* Function used to set the SDIO configuration to the default reset state ****/ -void SDIO_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); - -/* Command path state machine (CPSM) management functions *********************/ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); - -/* Data path state machine (DPSM) management functions ************************/ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); - -/* SDIO IO Cards mode management functions ************************************/ -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); - -/* CE-ATA mode management functions *******************************************/ -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void SDIO_DMACmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_SDIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_sdio.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the SDIO firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_SDIO_H +#define __STM32F2xx_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_sources + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/* Function used to set the SDIO configuration to the default reset state ****/ +void SDIO_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); + +/* Command path state machine (CPSM) management functions *********************/ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); + +/* Data path state machine (DPSM) management functions ************************/ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); + +/* SDIO IO Cards mode management functions ************************************/ +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); + +/* CE-ATA mode management functions *******************************************/ +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); + +/* DMA transfers management functions *****************************************/ +void SDIO_DMACmd(FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_SDIO_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h index 915e4c626..2d9571f03 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h @@ -1,526 +1,526 @@ -/** - ****************************************************************************** - * @file stm32f2xx_spi.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the SPI - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_SPI_H -#define __STM32F2xx_SPI_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx)|| \ - ((MODE) == I2S_Mode_MasterRx)) -/** - * @} - */ - - -/** @defgroup SPI_I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup SPI_I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define I2S_IT_UDR ((uint8_t)0x53) -#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) - -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) - -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) - -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) - -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ - ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ - ((IT) == SPI_I2S_IT_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) - -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ - ((FLAG) == SPI_I2S_FLAG_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** @defgroup SPI_I2S_Legacy - * @{ - */ - -#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx -#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx -#define SPI_IT_TXE SPI_I2S_IT_TXE -#define SPI_IT_RXNE SPI_I2S_IT_RXNE -#define SPI_IT_ERR SPI_I2S_IT_ERR -#define SPI_IT_OVR SPI_I2S_IT_OVR -#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE -#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE -#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR -#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY -#define SPI_DeInit SPI_I2S_DeInit -#define SPI_ITConfig SPI_I2S_ITConfig -#define SPI_DMACmd SPI_I2S_DMACmd -#define SPI_SendData SPI_I2S_SendData -#define SPI_ReceiveData SPI_I2S_ReceiveData -#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus -#define SPI_ClearFlag SPI_I2S_ClearFlag -#define SPI_GetITStatus SPI_I2S_GetITStatus -#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the SPI configuration to the default reset state *****/ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); - -/* Initialization and Configuration functions *********************************/ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); - -/* Hardware CRC Calculation functions *****************************************/ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); - -/* DMA transfers management functions *****************************************/ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /*__STM32F2xx_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_spi.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the SPI + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_SPI_H +#define __STM32F2xx_SPI_H + +#if defined(__cplusplus) && !defined(SIMU) + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx)|| \ + ((MODE) == I2S_Mode_MasterRx)) +/** + * @} + */ + + +/** @defgroup SPI_I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup SPI_I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ + ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define I2S_IT_UDR ((uint8_t)0x53) +#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) + +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) + +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) + +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) + +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ + ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ + ((IT) == SPI_I2S_IT_TIFRFE)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) + +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ + ((FLAG) == SPI_I2S_FLAG_TIFRFE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** @defgroup SPI_I2S_Legacy + * @{ + */ + +#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx +#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx +#define SPI_IT_TXE SPI_I2S_IT_TXE +#define SPI_IT_RXNE SPI_I2S_IT_RXNE +#define SPI_IT_ERR SPI_I2S_IT_ERR +#define SPI_IT_OVR SPI_I2S_IT_OVR +#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE +#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE +#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR +#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY +#define SPI_DeInit SPI_I2S_DeInit +#define SPI_ITConfig SPI_I2S_ITConfig +#define SPI_DMACmd SPI_I2S_DMACmd +#define SPI_SendData SPI_I2S_SendData +#define SPI_ReceiveData SPI_I2S_ReceiveData +#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus +#define SPI_ClearFlag SPI_I2S_ClearFlag +#define SPI_GetITStatus SPI_I2S_GetITStatus +#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the SPI configuration to the default reset state *****/ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); + +/* Initialization and Configuration functions *********************************/ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); + +/* Hardware CRC Calculation functions *****************************************/ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); + +/* DMA transfers management functions *****************************************/ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#if defined(__cplusplus) && !defined(SIMU) +} +#endif + +#endif /*__STM32F2xx_SPI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h index ab45e12a0..de6f3a00f 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h @@ -1,179 +1,179 @@ -/** - ****************************************************************************** - * @file stm32f2xx_syscfg.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the SYSCFG firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_SYSCFG_H -#define __STM32F2xx_SYSCFG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SYSCFG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SYSCFG_Exported_Constants - * @{ - */ - -/** @defgroup SYSCFG_EXTI_Port_Sources - * @{ - */ -#define EXTI_PortSourceGPIOA ((uint8_t)0x00) -#define EXTI_PortSourceGPIOB ((uint8_t)0x01) -#define EXTI_PortSourceGPIOC ((uint8_t)0x02) -#define EXTI_PortSourceGPIOD ((uint8_t)0x03) -#define EXTI_PortSourceGPIOE ((uint8_t)0x04) -#define EXTI_PortSourceGPIOF ((uint8_t)0x05) -#define EXTI_PortSourceGPIOG ((uint8_t)0x06) -#define EXTI_PortSourceGPIOH ((uint8_t)0x07) -#define EXTI_PortSourceGPIOI ((uint8_t)0x08) - -#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOI)) -/** - * @} - */ - - -/** @defgroup SYSCFG_EXTI_Pin_Sources - * @{ - */ -#define EXTI_PinSource0 ((uint8_t)0x00) -#define EXTI_PinSource1 ((uint8_t)0x01) -#define EXTI_PinSource2 ((uint8_t)0x02) -#define EXTI_PinSource3 ((uint8_t)0x03) -#define EXTI_PinSource4 ((uint8_t)0x04) -#define EXTI_PinSource5 ((uint8_t)0x05) -#define EXTI_PinSource6 ((uint8_t)0x06) -#define EXTI_PinSource7 ((uint8_t)0x07) -#define EXTI_PinSource8 ((uint8_t)0x08) -#define EXTI_PinSource9 ((uint8_t)0x09) -#define EXTI_PinSource10 ((uint8_t)0x0A) -#define EXTI_PinSource11 ((uint8_t)0x0B) -#define EXTI_PinSource12 ((uint8_t)0x0C) -#define EXTI_PinSource13 ((uint8_t)0x0D) -#define EXTI_PinSource14 ((uint8_t)0x0E) -#define EXTI_PinSource15 ((uint8_t)0x0F) -#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ - ((PINSOURCE) == EXTI_PinSource1) || \ - ((PINSOURCE) == EXTI_PinSource2) || \ - ((PINSOURCE) == EXTI_PinSource3) || \ - ((PINSOURCE) == EXTI_PinSource4) || \ - ((PINSOURCE) == EXTI_PinSource5) || \ - ((PINSOURCE) == EXTI_PinSource6) || \ - ((PINSOURCE) == EXTI_PinSource7) || \ - ((PINSOURCE) == EXTI_PinSource8) || \ - ((PINSOURCE) == EXTI_PinSource9) || \ - ((PINSOURCE) == EXTI_PinSource10) || \ - ((PINSOURCE) == EXTI_PinSource11) || \ - ((PINSOURCE) == EXTI_PinSource12) || \ - ((PINSOURCE) == EXTI_PinSource13) || \ - ((PINSOURCE) == EXTI_PinSource14) || \ - ((PINSOURCE) == EXTI_PinSource15)) -/** - * @} - */ - - -/** @defgroup SYSCFG_Memory_Remap_Config - * @{ - */ -#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) -#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) -#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) -#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) - -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_FSMC)) -/** - * @} - */ - - -/** @defgroup SYSCFG_ETHERNET_Media_Interface - * @{ - */ -#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) -#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) - -#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ - ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void SYSCFG_DeInit(void); -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); -void SYSCFG_CompensationCellCmd(FunctionalState NewState); -FlagStatus SYSCFG_GetCompensationCellStatus(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_SYSCFG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_syscfg.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the SYSCFG firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_SYSCFG_H +#define __STM32F2xx_SYSCFG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SYSCFG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SYSCFG_Exported_Constants + * @{ + */ + +/** @defgroup SYSCFG_EXTI_Port_Sources + * @{ + */ +#define EXTI_PortSourceGPIOA ((uint8_t)0x00) +#define EXTI_PortSourceGPIOB ((uint8_t)0x01) +#define EXTI_PortSourceGPIOC ((uint8_t)0x02) +#define EXTI_PortSourceGPIOD ((uint8_t)0x03) +#define EXTI_PortSourceGPIOE ((uint8_t)0x04) +#define EXTI_PortSourceGPIOF ((uint8_t)0x05) +#define EXTI_PortSourceGPIOG ((uint8_t)0x06) +#define EXTI_PortSourceGPIOH ((uint8_t)0x07) +#define EXTI_PortSourceGPIOI ((uint8_t)0x08) + +#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOI)) +/** + * @} + */ + + +/** @defgroup SYSCFG_EXTI_Pin_Sources + * @{ + */ +#define EXTI_PinSource0 ((uint8_t)0x00) +#define EXTI_PinSource1 ((uint8_t)0x01) +#define EXTI_PinSource2 ((uint8_t)0x02) +#define EXTI_PinSource3 ((uint8_t)0x03) +#define EXTI_PinSource4 ((uint8_t)0x04) +#define EXTI_PinSource5 ((uint8_t)0x05) +#define EXTI_PinSource6 ((uint8_t)0x06) +#define EXTI_PinSource7 ((uint8_t)0x07) +#define EXTI_PinSource8 ((uint8_t)0x08) +#define EXTI_PinSource9 ((uint8_t)0x09) +#define EXTI_PinSource10 ((uint8_t)0x0A) +#define EXTI_PinSource11 ((uint8_t)0x0B) +#define EXTI_PinSource12 ((uint8_t)0x0C) +#define EXTI_PinSource13 ((uint8_t)0x0D) +#define EXTI_PinSource14 ((uint8_t)0x0E) +#define EXTI_PinSource15 ((uint8_t)0x0F) +#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ + ((PINSOURCE) == EXTI_PinSource1) || \ + ((PINSOURCE) == EXTI_PinSource2) || \ + ((PINSOURCE) == EXTI_PinSource3) || \ + ((PINSOURCE) == EXTI_PinSource4) || \ + ((PINSOURCE) == EXTI_PinSource5) || \ + ((PINSOURCE) == EXTI_PinSource6) || \ + ((PINSOURCE) == EXTI_PinSource7) || \ + ((PINSOURCE) == EXTI_PinSource8) || \ + ((PINSOURCE) == EXTI_PinSource9) || \ + ((PINSOURCE) == EXTI_PinSource10) || \ + ((PINSOURCE) == EXTI_PinSource11) || \ + ((PINSOURCE) == EXTI_PinSource12) || \ + ((PINSOURCE) == EXTI_PinSource13) || \ + ((PINSOURCE) == EXTI_PinSource14) || \ + ((PINSOURCE) == EXTI_PinSource15)) +/** + * @} + */ + + +/** @defgroup SYSCFG_Memory_Remap_Config + * @{ + */ +#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) +#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) +#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) +#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) + +#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ + ((REMAP) == SYSCFG_MemoryRemap_FSMC)) +/** + * @} + */ + + +/** @defgroup SYSCFG_ETHERNET_Media_Interface + * @{ + */ +#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) +#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) + +#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ + ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void SYSCFG_DeInit(void); +void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); +void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); +void SYSCFG_CompensationCellCmd(FunctionalState NewState); +FlagStatus SYSCFG_GetCompensationCellStatus(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_SYSCFG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h index 62590b64c..2c48f2ad1 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h @@ -1,1150 +1,1150 @@ -/** - ****************************************************************************** - * @file stm32f2xx_tim.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_TIM_H -#define __STM32F2xx_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief TIM Time Base Init structure definition - * @note This structure is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_State */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief BDTR structure definition - * @note This structure is used only with TIM1 and TIM8. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - (((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14))) -/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - ((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14)) - -/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)) -/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8)) -/* LIST4: TIM1 and TIM8 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8)) -/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8)) -/* LIST6: TIM2, TIM5 and TIM11 */ -#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ - ((TIMx) == TIM5) || \ - ((TIMx) == TIM11)) - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) - -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_State - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_State - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define TIM_DMABase_OR ((uint16_t)0x0013) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ -/** @defgroup TIM_Remap - * @{ - */ - -#define TIM2_TIM8_TRGO ((uint16_t)0x0000) -#define TIM2_ETH_PTP ((uint16_t)0x0400) -#define TIM2_USBFS_SOF ((uint16_t)0x0800) -#define TIM2_USBHS_SOF ((uint16_t)0x0C00) - -#define TIM5_GPIO ((uint16_t)0x0000) -#define TIM5_LSI ((uint16_t)0x0040) -#define TIM5_LSE ((uint16_t)0x0080) -#define TIM5_RTC ((uint16_t)0x00C0) - -#define TIM11_GPIO ((uint16_t)0x0000) -#define TIM11_HSE ((uint16_t)0x0002) - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ - ((TIM_REMAP) == TIM2_ETH_PTP)||\ - ((TIM_REMAP) == TIM2_USBFS_SOF)||\ - ((TIM_REMAP) == TIM2_USBHS_SOF)||\ - ((TIM_REMAP) == TIM5_GPIO)||\ - ((TIM_REMAP) == TIM5_LSI)||\ - ((TIM_REMAP) == TIM5_LSE)||\ - ((TIM_REMAP) == TIM5_RTC)||\ - ((TIM_REMAP) == TIM11_GPIO)||\ - ((TIM_REMAP) == TIM11_HSE)) - -/** - * @} - */ -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_Legacy - * @{ - */ - -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* TimeBase management ********************************************************/ -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Output Compare management **************************************************/ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); - -/* Input Capture management ***************************************************/ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); - -/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Interrupts, DMA and flags management ***************************************/ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Clocks management **********************************************************/ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - -/* Synchronization management *************************************************/ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - -/* Specific interface management **********************************************/ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Specific remapping management **********************************************/ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_TIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_tim.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the TIM firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_TIM_H +#define __STM32F2xx_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief TIM Time Base Init structure definition + * @note This structure is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_State */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief BDTR structure definition + * @note This structure is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10) || \ + ((PERIPH) == TIM11) || \ + ((PERIPH) == TIM12) || \ + (((PERIPH) == TIM13) || \ + ((PERIPH) == TIM14))) +/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10) || \ + ((PERIPH) == TIM11) || \ + ((PERIPH) == TIM12) || \ + ((PERIPH) == TIM13) || \ + ((PERIPH) == TIM14)) + +/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)) +/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) +/* LIST4: TIM1 and TIM8 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) +/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8)) +/* LIST6: TIM2, TIM5 and TIM11 */ +#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ + ((TIMx) == TIM5) || \ + ((TIMx) == TIM11)) + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) + +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_State + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_State + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)|| \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define TIM_DMABase_OR ((uint16_t)0x0013) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR) || \ + ((BASE) == TIM_DMABase_OR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ +/** @defgroup TIM_Remap + * @{ + */ + +#define TIM2_TIM8_TRGO ((uint16_t)0x0000) +#define TIM2_ETH_PTP ((uint16_t)0x0400) +#define TIM2_USBFS_SOF ((uint16_t)0x0800) +#define TIM2_USBHS_SOF ((uint16_t)0x0C00) + +#define TIM5_GPIO ((uint16_t)0x0000) +#define TIM5_LSI ((uint16_t)0x0040) +#define TIM5_LSE ((uint16_t)0x0080) +#define TIM5_RTC ((uint16_t)0x00C0) + +#define TIM11_GPIO ((uint16_t)0x0000) +#define TIM11_HSE ((uint16_t)0x0002) + +#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ + ((TIM_REMAP) == TIM2_ETH_PTP)||\ + ((TIM_REMAP) == TIM2_USBFS_SOF)||\ + ((TIM_REMAP) == TIM2_USBHS_SOF)||\ + ((TIM_REMAP) == TIM5_GPIO)||\ + ((TIM_REMAP) == TIM5_LSI)||\ + ((TIM_REMAP) == TIM5_LSE)||\ + ((TIM_REMAP) == TIM5_RTC)||\ + ((TIM_REMAP) == TIM11_GPIO)||\ + ((TIM_REMAP) == TIM11_HSE)) + +/** + * @} + */ +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_Legacy + * @{ + */ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* TimeBase management ********************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Output Compare management **************************************************/ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); + +/* Input Capture management ***************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); + +/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Interrupts, DMA and flags management ***************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Clocks management **********************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); + +/* Synchronization management *************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); + +/* Specific interface management **********************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Specific remapping management **********************************************/ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_TIM_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h index 2d51f3401..663f380be 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h @@ -1,429 +1,429 @@ -/** - ****************************************************************************** - * @file stm32f2xx_usart.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_USART_H -#define __STM32F2xx_USART_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 - Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5) || \ - ((PERIPH) == USART6)) - -#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == USART6)) - -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -/** @defgroup USART_Legacy - * @{ - */ -#define USART_IT_ORE USART_IT_ORE_ER -/** - * @} - */ - -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the USART configuration to the default reset state ***/ -void USART_DeInit(USART_TypeDef* USARTx); - -/* Initialization and Configuration functions *********************************/ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); - -/* Multi-Processor Communication functions ************************************/ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* LIN mode functions *********************************************************/ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendBreak(USART_TypeDef* USARTx); - -/* Half-duplex mode function **************************************************/ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Smartcard mode functions ***************************************************/ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); - -/* IrDA mode functions ********************************************************/ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /* __STM32F2xx_USART_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_usart.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_USART_H +#define __STM32F2xx_USART_H + +#if defined(__cplusplus) && !defined(SIMU) + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 + Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ + + uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4) || \ + ((PERIPH) == UART5) || \ + ((PERIPH) == USART6)) + +#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == USART6)) + +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +/** @defgroup USART_Legacy + * @{ + */ +#define USART_IT_ORE USART_IT_ORE_ER +/** + * @} + */ + +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the USART configuration to the default reset state ***/ +void USART_DeInit(USART_TypeDef* USARTx); + +/* Initialization and Configuration functions *********************************/ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); + +/* Multi-Processor Communication functions ************************************/ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* LIN mode functions *********************************************************/ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendBreak(USART_TypeDef* USARTx); + +/* Half-duplex mode function **************************************************/ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Smartcard mode functions ***************************************************/ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); + +/* IrDA mode functions ********************************************************/ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* DMA transfers management functions *****************************************/ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#if defined(__cplusplus) && !defined(SIMU) +} +#endif + +#endif /* __STM32F2xx_USART_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_wwdg.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_wwdg.h index c4c1969dc..4cf5f03f2 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_wwdg.h +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_wwdg.h @@ -1,111 +1,111 @@ -/** - ****************************************************************************** - * @file stm32f2xx_wwdg.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the WWDG firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_WWDG_H -#define __STM32F2xx_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the WWDG configuration to the default reset state ****/ -void WWDG_DeInit(void); - -/* Prescaler, Refresh window and Counter configuration functions **************/ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); - -/* WWDG activation function ***************************************************/ -void WWDG_Enable(uint8_t Counter); - -/* Interrupts and flags management functions **********************************/ -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_wwdg.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the WWDG firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_WWDG_H +#define __STM32F2xx_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the WWDG configuration to the default reset state ****/ +void WWDG_DeInit(void); + +/* Prescaler, Refresh window and Counter configuration functions **************/ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); + +/* WWDG activation function ***************************************************/ +void WWDG_Enable(uint8_t Counter); + +/* Interrupts and flags management functions **********************************/ +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c index 7555a3d89..7d011629b 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c @@ -1,249 +1,249 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - * - * @verbatim - * - * =================================================================== - * How to configure Interrupts using driver - * =================================================================== - * - * This section provide functions allowing to configure the NVIC interrupts (IRQ). - * The Cortex-M3 exceptions are managed by CMSIS functions. - * - * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() - * function according to the following table. - - * The table below gives the allowed values of the pre-emption priority and subpriority according - * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - * ========================================================================================================================== - * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - * ========================================================================================================================== - * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - * | | | 4 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - * | | | 3 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - * | | | 2 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - * | | | 1 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - * | | | 0 bits for subpriority - * ========================================================================================================================== - * - * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() - * - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * - * @note IRQ priority order (sorted by highest to lowest priority): - * - Lowest pre-emption priority - * - Lowest subpriority - * - Lowest hardware priority (IRQ number) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "misc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); - - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. - * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. - * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. - * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + * + * @verbatim + * + * =================================================================== + * How to configure Interrupts using driver + * =================================================================== + * + * This section provide functions allowing to configure the NVIC interrupts (IRQ). + * The Cortex-M3 exceptions are managed by CMSIS functions. + * + * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() + * function according to the following table. + + * The table below gives the allowed values of the pre-emption priority and subpriority according + * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + * ========================================================================================================================== + * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + * ========================================================================================================================== + * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + * | | | 4 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + * | | | 3 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + * | | | 2 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + * | | | 1 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + * | | | 0 bits for subpriority + * ========================================================================================================================== + * + * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() + * + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * + * @note IRQ priority order (sorted by highest to lowest priority): + * - Lowest pre-emption priority + * - Lowest subpriority + * - Lowest hardware priority (IRQ number) + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); + + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. + * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. + * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. + * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. + * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c index e1d05597a..37ead2645 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c @@ -1,1748 +1,1748 @@ -/** - ****************************************************************************** - * @file stm32f2xx_adc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * - Initialization and Configuration (in addition to ADC multi mode - * selection) - * - Analog Watchdog configuration - * - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT - * management - * - Regular Channels Configuration - * - Regular Channels DMA Configuration - * - Injected channels Configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - - * 1. Enable the ADC interface clock using - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); - * - * 2. ADC pins configuration - * - Enable the clock for the ADC GPIOs using the following function: - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - Configure these ADC pins in analog mode using GPIO_Init(); - * - * 3. Configure the ADC Prescaler, conversion resolution and data - * alignment using the ADC_Init() function. - * 4. Activate the ADC peripheral using ADC_Cmd() function. - * - * Regular channels group configuration - * ==================================== - * - To configure the ADC regular channels group features, use - * ADC_Init() and ADC_RegularChannelConfig() functions. - * - To activate the continuous mode, use the ADC_continuousModeCmd() - * function. - * - To configurate and activate the Discontinuous mode, use the - * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. - * - To read the ADC converted values, use the ADC_GetConversionValue() - * function. - * - * Multi mode ADCs Regular channels configuration - * =============================================== - * - Refer to "Regular channels group configuration" description to - * configure the ADC1, ADC2 and ADC3 regular channels. - * - Select the Multi mode ADC regular channels features (dual or - * triple mode) using ADC_CommonInit() function and configure - * the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() - * functions. - * - Read the ADCs converted values using the - * ADC_GetMultiModeConversionValue() function. - * - * DMA for Regular channels group features configuration - * ====================================================== - * - To enable the DMA mode for regular channels group, use the - * ADC_DMACmd() function. - * - To enable the generation of DMA requests continuously at the end - * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() - * function. - * - * Injected channels group configuration - * ===================================== - * - To configure the ADC Injected channels group features, use - * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() - * functions. - * - To activate the continuous mode, use the ADC_continuousModeCmd() - * function. - * - To activate the Injected Discontinuous mode, use the - * ADC_InjectedDiscModeCmd() function. - * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() - * function. - * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() - * function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_adc.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) - -/* ADC EXTEN mask */ -#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) - -/* ADC JEXTEN mask */ -#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_SET ((uint32_t)0x0000001F) -#define SQR2_SQ_SET ((uint32_t)0x0000001F) -#define SQR1_SQ_SET ((uint32_t)0x0000001F) - -/* ADC L Mask */ -#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_SET ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_SET ((uint32_t)0x00300000) -#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_SET ((uint32_t)0x00000007) -#define SMPR2_SMP_SET ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_OFFSET ((uint8_t)0x28) - -/* ADC CDR register base address */ -#define CDR_ADDRESS ((uint32_t)0x40012308) - -/* ADC CCR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** @defgroup ADC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to: - - Initialize and configure the ADC Prescaler - - ADC Conversion Resolution (12bit..6bit) - - Scan Conversion Mode (multichannels or one channel) for regular group - - ADC Continuous Conversion Mode (Continuous or Single conversion) for - regular group - - External trigger Edge and source of regular group, - - Converted data alignment (left or right) - - The number of ADC conversions that will be done using the sequencer for - regular channel group - - Multi ADC mode selection - - Direct memory access mode selection for multi ADC mode - - Delay between 2 sampling phases (used in dual or triple interleaved modes) - - Enable or disable the ADC peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes all ADCs peripherals registers to their default reset - * values. - * @param None - * @retval None - */ -void ADC_DeInit(void) -{ - /* Enable all ADCs reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); - - /* Release all ADCs from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @note This function is used to configure the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - - /* Clear RES and SCAN bits */ - tmpreg1 &= CR1_CLEAR_MASK; - - /* Configure ADCx: scan conversion mode and resolution */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - /* Set RES bit according to ADC_Resolution value */ - tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ - ADC_InitStruct->ADC_Resolution); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - - /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_MASK; - - /* Configure ADCx: external trigger event and edge, data alignment and - continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ - ADC_InitStruct->ADC_ExternalTrigConv | - ADC_InitStruct->ADC_ExternalTrigConvEdge | \ - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - - /* Clear L bits */ - tmpreg1 &= SQR1_L_RESET; - - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfConversion value */ - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); - tmpreg1 |= ((uint32_t)tmpreg2 << 20); - - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @note This function is used to initialize the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; - - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - - /* Initialize the ADC_ExternalTrigConvEdge member */ - ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; - - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - - /* Initialize the ADC_NbrOfConversion member */ - ADC_InitStruct->ADC_NbrOfConversion = 1; -} - -/** - * @brief Initializes the ADCs peripherals according to the specified parameters - * in the ADC_CommonInitStruct. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * that contains the configuration information for All ADCs peripherals. - * @retval None - */ -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - uint32_t tmpreg1 = 0; - /* Check the parameters */ - assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); - assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); - assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); - assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); - /*---------------------------- ADC CCR Configuration -----------------*/ - /* Get the ADC CCR value */ - tmpreg1 = ADC->CCR; - - /* Clear MULTI, DELAY, DMA and ADCPRE bits */ - tmpreg1 &= CR_CLEAR_MASK; - - /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, - and DMA access mode for multimode */ - /* Set MULTI bits according to ADC_Mode value */ - /* Set ADCPRE bits according to ADC_Prescaler value */ - /* Set DMA bits according to ADC_DMAAccessMode value */ - /* Set DELAY bits according to ADC_TwoSamplingDelay value */ - tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | - ADC_CommonInitStruct->ADC_Prescaler | - ADC_CommonInitStruct->ADC_DMAAccessMode | - ADC_CommonInitStruct->ADC_TwoSamplingDelay); - - /* Write to ADC CCR */ - ADC->CCR = tmpreg1; -} - -/** - * @brief Fills each ADC_CommonInitStruct member with its default value. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * which will be initialized. - * @retval None - */ -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; - - /* initialize the ADC_Prescaler member */ - ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; - - /* Initialize the ADC_DMAAccessMode member */ - ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; - - /* Initialize the ADC_TwoSamplingDelay member */ - ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group2 Analog Watchdog configuration functions - * @brief Analog Watchdog configuration functions - * -@verbatim - =============================================================================== - Analog Watchdog configuration functions - =============================================================================== - - This section provides functions allowing to configure the Analog Watchdog - (AWD) feature in the ADC. - - A typical configuration Analog Watchdog is done following these steps : - 1. the ADC guarded channel(s) is (are) selected using the - ADC_AnalogWatchdogSingleChannelConfig() function. - 2. The Analog watchdog lower and higher threshold are configured using the - ADC_AnalogWatchdogThresholdsConfig() function. - 3. The Analog watchdog is enabled and configured to enable the check, on one - or more channels, using the ADC_AnalogWatchdogCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the analog watchdog on single/all regular or - * injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear AWDEN, JAWDEN and AWDSGL bits */ - tmpreg &= CR1_AWDMode_RESET; - - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12-bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12-bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_RESET; - - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} -/** - * @} - */ - -/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) - * and VBAT (Voltage BATtery) management functions - * @brief Temperature Sensor, Vrefint and VBAT management functions - * -@verbatim - =============================================================================== - Temperature Sensor, Vrefint and VBAT management functions - =============================================================================== - - This section provides functions allowing to enable/ disable the internal - connections between the ADC and the Temperature Sensor, the Vrefint and the - Vbat sources. - - A typical configuration to get the Temperature sensor and Vrefint channels - voltages is done following these steps : - 1. Enable the internal connection of Temperature sensor and Vrefint sources - with the ADC channels using ADC_TempSensorVrefintCmd() function. - 2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using - ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions - 3. Get the voltage values, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - - A typical configuration to get the VBAT channel voltage is done following - these steps : - 1. Enable the internal connection of VBAT source with the ADC channel using - ADC_VBATCmd() function. - 2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or - ADC_InjectedChannelConfig() functions - 3. Get the voltage value, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - -@endverbatim - * @{ - */ - - -/** - * @brief Enables or disables the temperature sensor and Vrefint channels. - * @param NewState: new state of the temperature sensor and Vrefint channels. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); - } -} - -/** - * @brief Enables or disables the VBAT (Voltage Battery) channel. - * @param NewState: new state of the VBAT channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VBATCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the VBAT channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_VBATE; - } - else - { - /* Disable the VBAT channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group4 Regular Channels Configuration functions - * @brief Regular Channels Configuration functions - * -@verbatim - =============================================================================== - Regular Channels Configuration functions - =============================================================================== - - This section provides functions allowing to manage the ADC's regular channels, - it is composed of 2 sub sections : - - 1. Configuration and management functions for regular channels: This subsection - provides functions allowing to configure the ADC regular channels : - - Configure the rank in the regular group sequencer for each channel - - Configure the sampling time for each channel - - select the conversion Trigger for regular channels - - select the desired EOC event behavior configuration - - Activate the continuous Mode (*) - - Activate the Discontinuous Mode - Please Note that the following features for regular channels are configurated - using the ADC_Init() function : - - scan mode activation - - continuous mode activation (**) - - External trigger source - - External trigger edge - - number of conversion in the regular channels group sequencer. - - @note (*) and (**) are performing the same configuration - - 2. Get the conversion data: This subsection provides an important function in - the ADC peripheral since it returns the converted data of the current - regular channel. When the Conversion value is read, the EOC Flag is - automatically cleared. - - @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions - results data (in the selected multi mode) can be returned in the same - time using ADC_GetMultiModeConversionValue() function. - - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables the selected ADC software start conversion of the regular channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Enable the selected ADC conversion for regular group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; -} - -/** - * @brief Gets the selected ADC Software start regular conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - - /* Return the SWSTART bit status */ - return bitstatus; -} - - -/** - * @brief Enables or disables the EOC on each regular channel conversion - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC EOC flag rising - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; - } - else - { - /* Disable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); - } -} - -/** - * @brief Enables or disables the ADC continuous conversion mode - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC continuous conversion mode - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC continuous conversion mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; - } - else - { - /* Disable the selected ADC continuous conversion mode */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); - } -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular group - * channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel count value. - * This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_RESET; - - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group channel - * for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on - * regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results - * data in the selected multi mode. - * @param None - * @retval The Data conversion value. - * @note In dual mode, the value returned by this function is as following - * Data[15:0] : these bits contain the regular data of ADC1. - * Data[31:16]: these bits contain the regular data of ADC2. - * @note In triple mode, the value returned by this function is as following - * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. - * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. - */ -uint32_t ADC_GetMultiModeConversionValue(void) -{ - /* Return the multi mode conversion value */ - return (*(__IO uint32_t *) CDR_ADDRESS); -} -/** - * @} - */ - -/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions - * @brief Regular Channels DMA Configuration functions - * -@verbatim - =============================================================================== - Regular Channels DMA Configuration functions - =============================================================================== - - This section provides functions allowing to configure the DMA for ADC regular - channels. - Since converted regular channel values are stored into a unique data register, - it is useful to use DMA for conversion of more than one regular channel. This - avoids the loss of the data already stored in the ADC Data register. - - When the DMA mode is enabled (using the ADC_DMACmd() function), after each - conversion of a regular channel, a DMA request is generated. - - Depending on the "DMA disable selection for Independent ADC mode" - configuration (using the ADC_DMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - - No new DMA request is issued to the DMA controller (feature DISABLED) - - Requests can continue to be generated (feature ENABLED). - - Depending on the "DMA disable selection for multi ADC mode" configuration - (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - - No new DMA request is issued to the DMA controller (feature DISABLED) - - Requests can continue to be generated (feature ENABLED). - -@endverbatim - * @{ - */ - - /** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @note if Enabled, DMA requests are issued as long as data are converted and - * DMA mode for multi ADC mode (selected using ADC_CommonInit() function - * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is - * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. - * @retval None - */ -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADC->CCR |= (uint32_t)ADC_CCR_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group6 Injected channels Configuration functions - * @brief Injected channels Configuration functions - * -@verbatim - =============================================================================== - Injected channels Configuration functions - =============================================================================== - - This section provide functions allowing to configure the ADC Injected channels, - it is composed of 2 sub sections : - - 1. Configuration functions for Injected channels: This subsection provides - functions allowing to configure the ADC injected channels : - - Configure the rank in the injected group sequencer for each channel - - Configure the sampling time for each channel - - Activate the Auto injected Mode - - Activate the Discontinuous Mode - - scan mode activation - - External/software trigger source - - External trigger edge - - injected channels sequencer. - - 2. Get the Specified Injected channel conversion data: This subsection - provides an important function in the ADC peripheral since it returns the - converted data of the specific injected channel. - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the injected group sequencer. - * This parameter must be between 1 to 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - - /* Clear the old injected sequence length JL bits */ - tmpreg1 &= JSQR_JL_RESET; - - /* Set the injected sequence length JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - - /** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - - /* Get the old register value */ - tmpreg = ADCx->CR2; - - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_RESET; - - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Configures the ADCx external trigger edge for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge - * to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for - * injected conversion - * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge - * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge - * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising - * and falling edge - * @retval None - */ -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external trigger edge for injected group */ - tmpreg &= CR2_JEXTEN_RESET; - /* Set the new external trigger edge for injected group */ - tmpreg |= ADC_ExternalTrigInjecConvEdge; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables the selected ADC software start conversion of the injected channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC conversion for injected group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on injected - * group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); - } -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_OFFSET; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup ADC_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the ADC Interrupts and - to get the status and clear flags and Interrupts pending bits. - - Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into - 3 groups: - - I. Flags and Interrupts for ADC regular channels - ================================================= - Flags : - ---------- - 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost - - 2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending - on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of: - ==> a regular CHANNEL conversion - ==> sequence of regular GROUP conversions . - - 3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL - conversion starts. - - Interrupts : - ------------ - 1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event. - 2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of - conversion event. - - - II. Flags and Interrupts for ADC Injected channels - ================================================= - Flags : - ---------- - 1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at - the end of injected GROUP conversion - - 2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when - injected GROUP conversion starts. - - Interrupts : - ------------ - 1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of - conversion event. - - III. General Flags and Interrupts for the ADC - ================================================= - Flags : - ---------- - 1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage - crosses the programmed thresholds values. - - Interrupts : - ------------ - 1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. - - - The user should identify which mode will be used in his application to manage - the ADC controller events: Polling mode or Interrupt mode. - - In the Polling Mode it is advised to use the following functions: - - ADC_GetFlagStatus() : to check if flags events occur. - - ADC_ClearFlag() : to clear the flags events. - - In the Interrupt Mode it is advised to use the following functions: - - ADC_ITConfig() : to enable or disable the interrupt source. - - ADC_GetITStatus() : to check if Interrupt occurs. - - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt enable - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint32_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - itmask = (uint32_t)0x01 << itmask; - - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; - - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_adc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) peripheral: + * - Initialization and Configuration (in addition to ADC multi mode + * selection) + * - Analog Watchdog configuration + * - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT + * management + * - Regular Channels Configuration + * - Regular Channels DMA Configuration + * - Injected channels Configuration + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + + * 1. Enable the ADC interface clock using + * RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); + * + * 2. ADC pins configuration + * - Enable the clock for the ADC GPIOs using the following function: + * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + * - Configure these ADC pins in analog mode using GPIO_Init(); + * + * 3. Configure the ADC Prescaler, conversion resolution and data + * alignment using the ADC_Init() function. + * 4. Activate the ADC peripheral using ADC_Cmd() function. + * + * Regular channels group configuration + * ==================================== + * - To configure the ADC regular channels group features, use + * ADC_Init() and ADC_RegularChannelConfig() functions. + * - To activate the continuous mode, use the ADC_continuousModeCmd() + * function. + * - To configurate and activate the Discontinuous mode, use the + * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. + * - To read the ADC converted values, use the ADC_GetConversionValue() + * function. + * + * Multi mode ADCs Regular channels configuration + * =============================================== + * - Refer to "Regular channels group configuration" description to + * configure the ADC1, ADC2 and ADC3 regular channels. + * - Select the Multi mode ADC regular channels features (dual or + * triple mode) using ADC_CommonInit() function and configure + * the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() + * functions. + * - Read the ADCs converted values using the + * ADC_GetMultiModeConversionValue() function. + * + * DMA for Regular channels group features configuration + * ====================================================== + * - To enable the DMA mode for regular channels group, use the + * ADC_DMACmd() function. + * - To enable the generation of DMA requests continuously at the end + * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() + * function. + * + * Injected channels group configuration + * ===================================== + * - To configure the ADC Injected channels group features, use + * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() + * functions. + * - To activate the continuous mode, use the ADC_continuousModeCmd() + * function. + * - To activate the Injected Discontinuous mode, use the + * ADC_InjectedDiscModeCmd() function. + * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() + * function. + * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() + * function. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) + +/* ADC EXTEN mask */ +#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) + +/* ADC JEXTEN mask */ +#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_SET ((uint32_t)0x0000001F) +#define SQR2_SQ_SET ((uint32_t)0x0000001F) +#define SQR1_SQ_SET ((uint32_t)0x0000001F) + +/* ADC L Mask */ +#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_SET ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_SET ((uint32_t)0x00300000) +#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_SET ((uint32_t)0x00000007) +#define SMPR2_SMP_SET ((uint32_t)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_OFFSET ((uint8_t)0x28) + +/* ADC CDR register base address */ +#define CDR_ADDRESS ((uint32_t)0x40012308) + +/* ADC CCR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** @defgroup ADC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + This section provides functions allowing to: + - Initialize and configure the ADC Prescaler + - ADC Conversion Resolution (12bit..6bit) + - Scan Conversion Mode (multichannels or one channel) for regular group + - ADC Continuous Conversion Mode (Continuous or Single conversion) for + regular group + - External trigger Edge and source of regular group, + - Converted data alignment (left or right) + - The number of ADC conversions that will be done using the sequencer for + regular channel group + - Multi ADC mode selection + - Direct memory access mode selection for multi ADC mode + - Delay between 2 sampling phases (used in dual or triple interleaved modes) + - Enable or disable the ADC peripheral + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes all ADCs peripherals registers to their default reset + * values. + * @param None + * @retval None + */ +void ADC_DeInit(void) +{ + /* Enable all ADCs reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); + + /* Release all ADCs from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @note This function is used to configure the global features of the ADC ( + * Resolution and Data Alignment), however, the rest of the configuration + * parameters are specific to the regular channels group (scan mode + * activation, continuous mode activation, External trigger source and + * edge, number of conversion in the regular channels group sequencer). + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + + /* Clear RES and SCAN bits */ + tmpreg1 &= CR1_CLEAR_MASK; + + /* Configure ADCx: scan conversion mode and resolution */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + /* Set RES bit according to ADC_Resolution value */ + tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ + ADC_InitStruct->ADC_Resolution); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + + /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_MASK; + + /* Configure ADCx: external trigger event and edge, data alignment and + continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ + ADC_InitStruct->ADC_ExternalTrigConv | + ADC_InitStruct->ADC_ExternalTrigConvEdge | \ + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + + /* Clear L bits */ + tmpreg1 &= SQR1_L_RESET; + + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfConversion value */ + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); + tmpreg1 |= ((uint32_t)tmpreg2 << 20); + + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @note This function is used to initialize the global features of the ADC ( + * Resolution and Data Alignment), however, the rest of the configuration + * parameters are specific to the regular channels group (scan mode + * activation, continuous mode activation, External trigger source and + * edge, number of conversion in the regular channels group sequencer). + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; + + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + + /* Initialize the ADC_ExternalTrigConvEdge member */ + ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + + /* Initialize the ADC_NbrOfConversion member */ + ADC_InitStruct->ADC_NbrOfConversion = 1; +} + +/** + * @brief Initializes the ADCs peripherals according to the specified parameters + * in the ADC_CommonInitStruct. + * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure + * that contains the configuration information for All ADCs peripherals. + * @retval None + */ +void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) +{ + uint32_t tmpreg1 = 0; + /* Check the parameters */ + assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); + assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); + assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); + assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); + /*---------------------------- ADC CCR Configuration -----------------*/ + /* Get the ADC CCR value */ + tmpreg1 = ADC->CCR; + + /* Clear MULTI, DELAY, DMA and ADCPRE bits */ + tmpreg1 &= CR_CLEAR_MASK; + + /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, + and DMA access mode for multimode */ + /* Set MULTI bits according to ADC_Mode value */ + /* Set ADCPRE bits according to ADC_Prescaler value */ + /* Set DMA bits according to ADC_DMAAccessMode value */ + /* Set DELAY bits according to ADC_TwoSamplingDelay value */ + tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | + ADC_CommonInitStruct->ADC_Prescaler | + ADC_CommonInitStruct->ADC_DMAAccessMode | + ADC_CommonInitStruct->ADC_TwoSamplingDelay); + + /* Write to ADC CCR */ + ADC->CCR = tmpreg1; +} + +/** + * @brief Fills each ADC_CommonInitStruct member with its default value. + * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure + * which will be initialized. + * @retval None + */ +void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) +{ + /* Initialize the ADC_Mode member */ + ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; + + /* initialize the ADC_Prescaler member */ + ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; + + /* Initialize the ADC_DMAAccessMode member */ + ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + + /* Initialize the ADC_TwoSamplingDelay member */ + ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); + } +} +/** + * @} + */ + +/** @defgroup ADC_Group2 Analog Watchdog configuration functions + * @brief Analog Watchdog configuration functions + * +@verbatim + =============================================================================== + Analog Watchdog configuration functions + =============================================================================== + + This section provides functions allowing to configure the Analog Watchdog + (AWD) feature in the ADC. + + A typical configuration Analog Watchdog is done following these steps : + 1. the ADC guarded channel(s) is (are) selected using the + ADC_AnalogWatchdogSingleChannelConfig() function. + 2. The Analog watchdog lower and higher threshold are configured using the + ADC_AnalogWatchdogThresholdsConfig() function. + 3. The Analog watchdog is enabled and configured to enable the check, on one + or more channels, using the ADC_AnalogWatchdogCmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the analog watchdog on single/all regular or + * injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel + * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel + * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel + * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel + * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel + * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels + * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + + /* Clear AWDEN, JAWDEN and AWDSGL bits */ + tmpreg &= CR1_AWDMode_RESET; + + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12-bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12-bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_RESET; + + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} +/** + * @} + */ + +/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) + * and VBAT (Voltage BATtery) management functions + * @brief Temperature Sensor, Vrefint and VBAT management functions + * +@verbatim + =============================================================================== + Temperature Sensor, Vrefint and VBAT management functions + =============================================================================== + + This section provides functions allowing to enable/ disable the internal + connections between the ADC and the Temperature Sensor, the Vrefint and the + Vbat sources. + + A typical configuration to get the Temperature sensor and Vrefint channels + voltages is done following these steps : + 1. Enable the internal connection of Temperature sensor and Vrefint sources + with the ADC channels using ADC_TempSensorVrefintCmd() function. + 2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using + ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions + 3. Get the voltage values, using ADC_GetConversionValue() or + ADC_GetInjectedConversionValue(). + + A typical configuration to get the VBAT channel voltage is done following + these steps : + 1. Enable the internal connection of VBAT source with the ADC channel using + ADC_VBATCmd() function. + 2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or + ADC_InjectedChannelConfig() functions + 3. Get the voltage value, using ADC_GetConversionValue() or + ADC_GetInjectedConversionValue(). + +@endverbatim + * @{ + */ + + +/** + * @brief Enables or disables the temperature sensor and Vrefint channels. + * @param NewState: new state of the temperature sensor and Vrefint channels. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); + } +} + +/** + * @brief Enables or disables the VBAT (Voltage Battery) channel. + * @param NewState: new state of the VBAT channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_VBATCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the VBAT channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_VBATE; + } + else + { + /* Disable the VBAT channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group4 Regular Channels Configuration functions + * @brief Regular Channels Configuration functions + * +@verbatim + =============================================================================== + Regular Channels Configuration functions + =============================================================================== + + This section provides functions allowing to manage the ADC's regular channels, + it is composed of 2 sub sections : + + 1. Configuration and management functions for regular channels: This subsection + provides functions allowing to configure the ADC regular channels : + - Configure the rank in the regular group sequencer for each channel + - Configure the sampling time for each channel + - select the conversion Trigger for regular channels + - select the desired EOC event behavior configuration + - Activate the continuous Mode (*) + - Activate the Discontinuous Mode + Please Note that the following features for regular channels are configurated + using the ADC_Init() function : + - scan mode activation + - continuous mode activation (**) + - External trigger source + - External trigger edge + - number of conversion in the regular channels group sequencer. + + @note (*) and (**) are performing the same configuration + + 2. Get the conversion data: This subsection provides an important function in + the ADC peripheral since it returns the converted data of the current + regular channel. When the Conversion value is read, the EOC Flag is + automatically cleared. + + @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions + results data (in the selected multi mode) can be returned in the same + time using ADC_GetMultiModeConversionValue() function. + + +@endverbatim + * @{ + */ +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles + * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles + * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles + * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles + * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles + * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles + * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles + * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); + + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); + + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/** + * @brief Enables the selected ADC software start conversion of the regular channels. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Enable the selected ADC conversion for regular group */ + ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; +} + +/** + * @brief Gets the selected ADC Software start regular conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + + /* Return the SWSTART bit status */ + return bitstatus; +} + + +/** + * @brief Enables or disables the EOC on each regular channel conversion + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC EOC flag rising + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC EOC rising on each regular channel conversion */ + ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; + } + else + { + /* Disable the selected ADC EOC rising on each regular channel conversion */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); + } +} + +/** + * @brief Enables or disables the ADC continuous conversion mode + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC continuous conversion mode + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC continuous conversion mode */ + ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; + } + else + { + /* Disable the selected ADC continuous conversion mode */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); + } +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular group + * channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Number: specifies the discontinuous mode regular channel count value. + * This number must be between 1 and 8. + * @retval None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_RESET; + + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group channel + * for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode on + * regular group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results + * data in the selected multi mode. + * @param None + * @retval The Data conversion value. + * @note In dual mode, the value returned by this function is as following + * Data[15:0] : these bits contain the regular data of ADC1. + * Data[31:16]: these bits contain the regular data of ADC2. + * @note In triple mode, the value returned by this function is as following + * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. + * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. + */ +uint32_t ADC_GetMultiModeConversionValue(void) +{ + /* Return the multi mode conversion value */ + return (*(__IO uint32_t *) CDR_ADDRESS); +} +/** + * @} + */ + +/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions + * @brief Regular Channels DMA Configuration functions + * +@verbatim + =============================================================================== + Regular Channels DMA Configuration functions + =============================================================================== + + This section provides functions allowing to configure the DMA for ADC regular + channels. + Since converted regular channel values are stored into a unique data register, + it is useful to use DMA for conversion of more than one regular channel. This + avoids the loss of the data already stored in the ADC Data register. + + When the DMA mode is enabled (using the ADC_DMACmd() function), after each + conversion of a regular channel, a DMA request is generated. + + Depending on the "DMA disable selection for Independent ADC mode" + configuration (using the ADC_DMARequestAfterLastTransferCmd() function), + at the end of the last DMA transfer, two possibilities are allowed: + - No new DMA request is issued to the DMA controller (feature DISABLED) + - Requests can continue to be generated (feature ENABLED). + + Depending on the "DMA disable selection for multi ADC mode" configuration + (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), + at the end of the last DMA transfer, two possibilities are allowed: + - No new DMA request is issued to the DMA controller (feature DISABLED) + - Requests can continue to be generated (feature ENABLED). + +@endverbatim + * @{ + */ + + /** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); + } +} + +/** + * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC DMA request after last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; + } + else + { + /* Disable the selected ADC DMA request after last transfer */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); + } +} + +/** + * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode + * @param NewState: new state of the selected ADC DMA request after last transfer. + * This parameter can be: ENABLE or DISABLE. + * @note if Enabled, DMA requests are issued as long as data are converted and + * DMA mode for multi ADC mode (selected using ADC_CommonInit() function + * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is + * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. + * @retval None + */ +void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + ADC->CCR |= (uint32_t)ADC_CCR_DDS; + } + else + { + /* Disable the selected ADC DMA request after last transfer */ + ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); + } +} +/** + * @} + */ + +/** @defgroup ADC_Group6 Injected channels Configuration functions + * @brief Injected channels Configuration functions + * +@verbatim + =============================================================================== + Injected channels Configuration functions + =============================================================================== + + This section provide functions allowing to configure the ADC Injected channels, + it is composed of 2 sub sections : + + 1. Configuration functions for Injected channels: This subsection provides + functions allowing to configure the ADC injected channels : + - Configure the rank in the injected group sequencer for each channel + - Configure the sampling time for each channel + - Activate the Auto injected Mode + - Activate the Discontinuous Mode + - scan mode activation + - External/software trigger source + - External trigger edge + - injected channels sequencer. + + 2. Get the Specified Injected channel conversion data: This subsection + provides an important function in the ADC peripheral since it returns the + converted data of the specific injected channel. + +@endverbatim + * @{ + */ +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @param Rank: The rank in the injected group sequencer. + * This parameter must be between 1 to 4. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles + * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles + * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles + * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles + * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles + * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles + * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles + * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Length: The sequencer length. + * This parameter must be a number between 1 to 4. + * @retval None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + + /* Clear the old injected sequence length JL bits */ + tmpreg1 &= JSQR_JL_RESET; + + /* Set the injected sequence length JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @param Offset: the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t *) tmp = (uint32_t)Offset; +} + + /** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected + * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected + * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected + * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected + * @retval None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + + /* Get the old register value */ + tmpreg = ADCx->CR2; + + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_RESET; + + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Configures the ADCx external trigger edge for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge + * to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for + * injected conversion + * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge + * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge + * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising + * and falling edge + * @retval None + */ +void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external trigger edge for injected group */ + tmpreg &= CR2_JEXTEN_RESET; + /* Set the new external trigger edge for injected group */ + tmpreg |= ADC_ExternalTrigInjecConvEdge; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Enables the selected ADC software start conversion of the injected channels. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Enable the selected ADC conversion for injected group */ + ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode on injected + * group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); + } +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @retval The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDR_OFFSET; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} +/** + * @} + */ + +/** @defgroup ADC_Group7 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides functions allowing to configure the ADC Interrupts and + to get the status and clear flags and Interrupts pending bits. + + Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into + 3 groups: + + I. Flags and Interrupts for ADC regular channels + ================================================= + Flags : + ---------- + 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost + + 2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending + on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of: + ==> a regular CHANNEL conversion + ==> sequence of regular GROUP conversions . + + 3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL + conversion starts. + + Interrupts : + ------------ + 1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event. + 2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of + conversion event. + + + II. Flags and Interrupts for ADC Injected channels + ================================================= + Flags : + ---------- + 1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at + the end of injected GROUP conversion + + 2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when + injected GROUP conversion starts. + + Interrupts : + ------------ + 1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of + conversion event. + + III. General Flags and Interrupts for the ADC + ================================================= + Flags : + ---------- + 1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage + crosses the programmed thresholds values. + + Interrupts : + ------------ + 1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. + + + The user should identify which mode will be used in his application to manage + the ADC controller events: Polling mode or Interrupt mode. + + In the Polling Mode it is advised to use the following functions: + - ADC_GetFlagStatus() : to check if flags events occur. + - ADC_ClearFlag() : to clear the flags events. + + In the Interrupt Mode it is advised to use the following functions: + - ADC_ITConfig() : to enable or disable the interrupt source. + - ADC_GetITStatus() : to check if Interrupt occurs. + - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). +@endverbatim + * @{ + */ +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt enable + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint32_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + itmask = (uint32_t)0x01 << itmask; + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @arg ADC_FLAG_OVR: Overrun flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @arg ADC_FLAG_OVR: Overrun flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + + /* Clear the selected ADC flags */ + ADCx->SR = ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt mask + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; + + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt mask + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(uint32_t)itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c index 5198acee5..433a9476a 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c @@ -1,1704 +1,1704 @@ -/** - ****************************************************************************** - * @file stm32f2xx_can.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Controller area network (CAN) peripheral: - * - Initialization and Configuration - * - CAN Frames Transmission - * - CAN Frames Reception - * - Operation modes switch - * - Error management - * - Interrupts and flags - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - - * 1. Enable the CAN controller interface clock using - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 - * and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 - * @note In case you are using CAN2 only, you have to enable the CAN1 clock. - * - * 2. CAN pins configuration - * - Enable the clock for the CAN GPIOs using the following function: - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - Connect the involved CAN pins to AF9 using the following function - * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); - * - Configure these CAN pins in alternate function mode by calling - * the function GPIO_Init(); - * - * 3. Initialise and configure the CAN using CAN_Init() and - * CAN_FilterInit() functions. - * - * 4. Transmit the desired CAN frame using CAN_Transmit() function. - * - * 5. Check the transmission of a CAN frame using CAN_TransmitStatus() - * function. - * - * 6. Cancel the transmission of a CAN frame using CAN_CancelTransmit() - * function. - * - * 7. Receive a CAN frame using CAN_Recieve() function. - * - * 8. Release the receive FIFOs using CAN_FIFORelease() function. - * - * 9. Return the number of pending received frames using - * CAN_MessagePending() function. - * - * 10. To control CAN events you can use one of the following two methods: - * - Check on CAN flags using the CAN_GetFlagStatus() function. - * - Use CAN interrupts through the function CAN_ITConfig() at - * initialization phase and CAN_GetITStatus() function into - * interrupt routines to check if the event has occurred or not. - * After checking on a flag you should clear it using CAN_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using CAN_ClearITPendingBit() function. - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_can.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CAN Master Control Register bits */ -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) - -/* Flags in TSR register */ -#define CAN_FLAGS_TSR ((uint32_t)0x08000000) -/* Flags in RF1R register */ -#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) -/* Flags in RF0R register */ -#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) -/* Flags in MSR register */ -#define CAN_FLAGS_MSR ((uint32_t)0x01000000) -/* Flags in ESR register */ -#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** @defgroup CAN_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the CAN peripherals : Prescaler, operating mode, the maximum number - of time quanta to perform resynchronization, the number of time quanta in - Bit Segment 1 and 2 and many other modes. - Refer to @ref CAN_InitTypeDef for more details. - - Configures the CAN reception filter. - - Select the start bank filter for slave CAN. - - Enables or disables the Debug Freeze mode for CAN - - Enables or disables the CAN Time Trigger Operation communication mode - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - if (CANx == CAN1) - { - /* Enable CAN1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } - else - { - /* Enable CAN2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains - * the configuration information for the CAN peripheral. - * @retval Constant indicates initialization succeed which will be - * CAN_InitStatus_Failed or CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* Exit from sleep mode */ - CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - CANx->MCR |= CAN_MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* Check acknowledge */ - if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= CAN_MCR_TTCM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= CAN_MCR_ABOM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= CAN_MCR_AWUM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= CAN_MCR_NART; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= CAN_MCR_RFLM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= CAN_MCR_TXFP; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0; - - while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that - * contains the configuration information. - * @retval None - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. - * @retval None - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -/** - * @brief Select the start bank filter for slave CAN. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - - /* Enter Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Select the start slave bank */ - CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; - - /* Leave Initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - - -/** - * @brief Enables or disables the CAN Time TriggerOperation communication mode. - * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. - * When enabled, Time stamp (TIME[15:0]) value is sent in the last two - * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] - * in data byte 7. - * @retval None - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TTCM mode */ - CANx->MCR |= CAN_MCR_TTCM; - - /* Set TGT bits */ - CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); - } - else - { - /* Disable the TTCM mode */ - CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); - - /* Reset TGT bits */ - CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group2 CAN Frames Transmission functions - * @brief CAN Frames Transmission functions - * -@verbatim - =============================================================================== - CAN Frames Transmission functions - =============================================================================== - This section provides functions allowing to - - Initiate and transmit a CAN frame message (if there is an empty mailbox). - - Check the transmission status of a CAN Frame - - Cancel a transmit request - -@endverbatim - * @{ - */ - -/** - * @brief Initiates and transmits a CAN frame message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. - * @retval The number of the mailbox that is used for transmission or - * CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission status of a CAN Frame. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for transmission. - * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, - * CAN_TxStatus_Failed in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); - break; - case (CAN_TXMAILBOX_1): - state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); - break; - case (CAN_TXMAILBOX_2): - state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); - break; - default: - state = CAN_TxStatus_Failed; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CAN_TxStatus_Pending; - break; - /* transmit failed */ - case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; - break; - /* transmit succeeded */ - case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; - break; - default: state = CAN_TxStatus_Failed; - break; - } - return (uint8_t) state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @retval None - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; - break; - case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; - break; - case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; - break; - default: - break; - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group3 CAN Frames Reception functions - * @brief CAN Frames Reception functions - * -@verbatim - =============================================================================== - CAN Frames Reception functions - =============================================================================== - This section provides functions allowing to - - Receive a correct CAN frame - - Release a specified receive FIFO (2 FIFOs are available) - - Return the number of the pending received CAN frames - -@endverbatim - * @{ - */ - -/** - * @brief Receives a correct CAN frame. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive frame which contains CAN Id, - * CAN DLC, CAN data and FMI number. - * @retval None - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Releases the specified receive FIFO. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending received messages. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage : which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} -/** - * @} - */ - - -/** @defgroup CAN_Group4 CAN Operation modes functions - * @brief CAN Operation modes functions - * -@verbatim - =============================================================================== - CAN Operation modes functions - =============================================================================== - This section provides functions allowing to select the CAN Operation modes - - sleep mode - - normal mode - - initialization mode - -@endverbatim - * @{ - */ - - -/** - * @brief Selects the CAN Operation mode. - * @param CAN_OperatingMode: CAN Operating Mode. - * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. - * @retval status of the requested mode which can be - * - CAN_ModeStatus_Failed: CAN failed entering the specific mode - * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - - /* Timeout for INAK or also for SLAK bits*/ - uint32_t timeout = INAK_TIMEOUT; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - /* Request initialisation */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - /* Request leave initialisation and sleep mode and enter Normal mode */ - CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - /* Request Sleep mode */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/** - * @brief Enters the Sleep (low power) mode. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CAN_Sleep_Ok; - } - /* return sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes up the CAN peripheral from sleep mode . - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* wake up done : Sleep mode exited */ - wakeupstatus = CAN_WakeUp_Ok; - } - /* return wakeup status */ - return (uint8_t)wakeupstatus; -} -/** - * @} - */ - - -/** @defgroup CAN_Group5 CAN Bus Error management functions - * @brief CAN Bus Error management functions - * -@verbatim - =============================================================================== - CAN Bus Error management functions - =============================================================================== - This section provides functions allowing to - - Return the CANx's last error code (LEC) - - Return the CANx Receive Error Counter (REC) - - Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). - - @note If TEC is greater than 255, The CAN is in bus-off state. - @note if REC or TEC are greater than 96, an Error warning flag occurs. - @note if REC or TEC are greater than 127, an Error Passive Flag occurs. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the CANx's last error code (LEC). - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval Error code: - * - CAN_ERRORCODE_NoErr: No Error - * - CAN_ERRORCODE_StuffErr: Stuff Error - * - CAN_ERRORCODE_FormErr: Form Error - * - CAN_ERRORCODE_ACKErr : Acknowledgment Error - * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error - * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error - * - CAN_ERRORCODE_CRCErr: CRC Error - * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error - */ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the error code*/ - errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); - - /* Return the error code*/ - return errorcode; -} - -/** - * @brief Returns the CANx Receive Error Counter (REC). - * @note In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the Receive Error Counter*/ - counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); - - /* Return the Receive Error Counter*/ - return counter; -} - - -/** - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); - - /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - return counter; -} -/** - * @} - */ - -/** @defgroup CAN_Group6 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the CAN Interrupts and - to get the status and clear flags and Interrupts pending bits. - - The CAN provides 14 Interrupts sources and 15 Flags: - - =============== - Flags : - =============== - The 15 flags can be divided on 4 groups: - - A. Transmit Flags - ----------------------- - CAN_FLAG_RQCP0, - CAN_FLAG_RQCP1, - CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags - Set when when the last request (transmit or abort) has - been performed. - - B. Receive Flags - ----------------------- - - CAN_FLAG_FMP0, - CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags - set to signal that messages are pending in the receive - FIFO. - These Flags are cleared only by hardware. - - CAN_FLAG_FF0, - CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags - set when three messages are stored in the selected - FIFO. - - CAN_FLAG_FOV0 - CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags - set when a new message has been received and passed - the filter while the FIFO was full. - - C. Operating Mode Flags - ----------------------- - CAN_FLAG_WKU : Wake up Flag - set to signal that a SOF bit has been detected while - the CAN hardware was in Sleep mode. - - CAN_FLAG_SLAK : Sleep acknowledge Flag - Set to signal that the CAN has entered Sleep Mode. - - D. Error Flags - ----------------------- - CAN_FLAG_EWG : Error Warning Flag - Set when the warning limit has been reached (Receive - Error Counter or Transmit Error Counter greater than 96). - This Flag is cleared only by hardware. - - CAN_FLAG_EPV : Error Passive Flag - Set when the Error Passive limit has been reached - (Receive Error Counter or Transmit Error Counter - greater than 127). - This Flag is cleared only by hardware. - - CAN_FLAG_BOF : Bus-Off Flag - set when CAN enters the bus-off state. The bus-off - state is entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - - CAN_FLAG_LEC : Last error code Flag - set If a message has been transferred (reception or - transmission) with error, and the error code is hold. - - =============== - Interrupts : - =============== - The 14 interrupts can be divided on 4 groups: - - A. Transmit interrupt - ----------------------- - CAN_IT_TME : Transmit mailbox empty Interrupt - if enabled, this interrupt source is pending when - no transmit request are pending for Tx mailboxes. - - B. Receive Interrupts - ----------------------- - CAN_IT_FMP0, - CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts - if enabled, these interrupt sources are pending when - messages are pending in the receive FIFO. - The corresponding interrupt pending bits are cleared - only by hardware. - - CAN_IT_FF0, - CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts - if enabled, these interrupt sources are pending when - three messages are stored in the selected FIFO. - - CAN_IT_FOV0, - CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts - if enabled, these interrupt sources are pending when - a new message has been received and passed the filter - while the FIFO was full. - - C. Operating Mode Interrupts - ------------------------------- - CAN_IT_WKU : Wake-up Interrupt - if enabled, this interrupt source is pending when - a SOF bit has been detected while the CAN hardware was - in Sleep mode. - - CAN_IT_SLK : Sleep acknowledge Interrupt - if enabled, this interrupt source is pending when - the CAN has entered Sleep Mode. - - D. Error Interrupts - ----------------------- - CAN_IT_EWG : Error warning Interrupt - if enabled, this interrupt source is pending when - the warning limit has been reached (Receive Error - Counter or Transmit Error Counter=96). - - CAN_IT_EPV : Error passive Interrupt - if enabled, this interrupt source is pending when - the Error Passive limit has been reached (Receive - Error Counter or Transmit Error Counter>127). - - CAN_IT_BOF : Bus-off Interrupt - if enabled, this interrupt source is pending when - CAN enters the bus-off state. The bus-off state is - entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - - CAN_IT_LEC : Last error code Interrupt - if enabled, this interrupt source is pending when - a message has been transferred (reception or - transmission) with error, and the error code is hold. - - CAN_IT_ERR : Error Interrupt - if enabled, this interrupt source is pending when - an error condition is pending. - - - Managing the CAN controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the CAN controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - CAN_GetFlagStatus() : to check if flags events occur. - - CAN_ClearFlag() : to clear the flags events. - - - - 2. In the Interrupt Mode it is advised to use the following functions: - - CAN_ITConfig() : to enable or disable the interrupt source. - - CAN_GetITStatus() : to check if Interrupt occurs. - - CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). - @note This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts - pending bits since there are cleared only by hardware. - -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified CANx interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CANx interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CANx interrupt */ - CANx->IER &= ~CAN_IT; - } -} -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); - - - if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ - { - /* Check the status of the specified CAN flag */ - if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval None - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); - - if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ - { - /* Clear the selected CAN flags */ - CANx->ESR = (uint32_t)RESET; - } - else /* MSR or TSR or RF0R or RF1R */ - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF0R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF1R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) - { - /* Transmit Flags */ - CANx->TSR = (uint32_t)(flagtmp); - } - else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ - { - /* Operating mode Flags */ - CANx->MSR = (uint32_t)(flagtmp); - } - } -} - -/** - * @brief Checks whether the specified CANx interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval The current state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - - /* check the interrupt enable bit */ - if((CANx->IER & CAN_IT) != RESET) - { - /* in case the Interrupt is enabled, .... */ - switch (CAN_IT) - { - case CAN_IT_TME: - /* Check CAN_TSR_RQCPx bits */ - itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); - break; - case CAN_IT_FMP0: - /* Check CAN_RF0R_FMP0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); - break; - case CAN_IT_FF0: - /* Check CAN_RF0R_FULL0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); - break; - case CAN_IT_FOV0: - /* Check CAN_RF0R_FOVR0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); - break; - case CAN_IT_FMP1: - /* Check CAN_RF1R_FMP1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); - break; - case CAN_IT_FF1: - /* Check CAN_RF1R_FULL1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); - break; - case CAN_IT_FOV1: - /* Check CAN_RF1R_FOVR1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); - break; - case CAN_IT_WKU: - /* Check CAN_MSR_WKUI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); - break; - case CAN_IT_SLK: - /* Check CAN_MSR_SLAKI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); - break; - case CAN_IT_EWG: - /* Check CAN_ESR_EWGF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); - break; - case CAN_IT_EPV: - /* Check CAN_ESR_EPVF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); - break; - case CAN_IT_BOF: - /* Check CAN_ESR_BOFF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); - break; - case CAN_IT_LEC: - /* Check CAN_ESR_LEC bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); - break; - case CAN_IT_ERR: - /* Check CAN_MSR_ERRI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); - break; - default: - /* in case of error, return RESET */ - itstatus = RESET; - break; - } - } - else - { - /* in case the Interrupt is not enabled, return RESET */ - itstatus = RESET; - } - - /* Return the CAN_IT status */ - return itstatus; -} - -/** - * @brief Clears the CANx's interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval None - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_IT(CAN_IT)); - - switch (CAN_IT) - { - case CAN_IT_TME: - /* Clear CAN_TSR_RQCPx (rc_w1)*/ - CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; - break; - case CAN_IT_FF0: - /* Clear CAN_RF0R_FULL0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FULL0; - break; - case CAN_IT_FOV0: - /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FOVR0; - break; - case CAN_IT_FF1: - /* Clear CAN_RF1R_FULL1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FULL1; - break; - case CAN_IT_FOV1: - /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FOVR1; - break; - case CAN_IT_WKU: - /* Clear CAN_MSR_WKUI (rc_w1)*/ - CANx->MSR = CAN_MSR_WKUI; - break; - case CAN_IT_SLK: - /* Clear CAN_MSR_SLAKI (rc_w1)*/ - CANx->MSR = CAN_MSR_SLAKI; - break; - case CAN_IT_EWG: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_EPV: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_BOF: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_LEC: - /* Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - break; - case CAN_IT_ERR: - /*Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ - break; - default: - break; - } -} - /** - * @} - */ - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_can.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Controller area network (CAN) peripheral: + * - Initialization and Configuration + * - CAN Frames Transmission + * - CAN Frames Reception + * - Operation modes switch + * - Error management + * - Interrupts and flags + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + + * 1. Enable the CAN controller interface clock using + * RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 + * and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 + * @note In case you are using CAN2 only, you have to enable the CAN1 clock. + * + * 2. CAN pins configuration + * - Enable the clock for the CAN GPIOs using the following function: + * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + * - Connect the involved CAN pins to AF9 using the following function + * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); + * - Configure these CAN pins in alternate function mode by calling + * the function GPIO_Init(); + * + * 3. Initialise and configure the CAN using CAN_Init() and + * CAN_FilterInit() functions. + * + * 4. Transmit the desired CAN frame using CAN_Transmit() function. + * + * 5. Check the transmission of a CAN frame using CAN_TransmitStatus() + * function. + * + * 6. Cancel the transmission of a CAN frame using CAN_CancelTransmit() + * function. + * + * 7. Receive a CAN frame using CAN_Recieve() function. + * + * 8. Release the receive FIFOs using CAN_FIFORelease() function. + * + * 9. Return the number of pending received frames using + * CAN_MessagePending() function. + * + * 10. To control CAN events you can use one of the following two methods: + * - Check on CAN flags using the CAN_GetFlagStatus() function. + * - Use CAN interrupts through the function CAN_ITConfig() at + * initialization phase and CAN_GetITStatus() function into + * interrupt routines to check if the event has occurred or not. + * After checking on a flag you should clear it using CAN_ClearFlag() + * function. And after checking on an interrupt event you should + * clear it using CAN_ClearITPendingBit() function. + * + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_can.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CAN + * @brief CAN driver modules + * @{ + */ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* CAN Master Control Register bits */ +#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSR register */ +#define CAN_FLAGS_TSR ((uint32_t)0x08000000) +/* Flags in RF1R register */ +#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) +/* Flags in RF0R register */ +#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) +/* Flags in MSR register */ +#define CAN_FLAGS_MSR ((uint32_t)0x01000000) +/* Flags in ESR register */ +#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/** @defgroup CAN_Private_Functions + * @{ + */ + +/** @defgroup CAN_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + This section provides functions allowing to + - Initialize the CAN peripherals : Prescaler, operating mode, the maximum number + of time quanta to perform resynchronization, the number of time quanta in + Bit Segment 1 and 2 and many other modes. + Refer to @ref CAN_InitTypeDef for more details. + - Configures the CAN reception filter. + - Select the start bank filter for slave CAN. + - Enables or disables the Debug Freeze mode for CAN + - Enables or disables the CAN Time Trigger Operation communication mode + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval None. + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if (CANx == CAN1) + { + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + /* Enable CAN2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains + * the configuration information for the CAN peripheral. + * @retval Constant indicates initialization succeed which will be + * CAN_InitStatus_Failed or CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* Exit from sleep mode */ + CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + CANx->MCR |= CAN_MCR_INRQ ; + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* Check acknowledge */ + if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->MCR |= CAN_MCR_TTCM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->MCR |= CAN_MCR_ABOM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->MCR |= CAN_MCR_AWUM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->MCR |= CAN_MCR_NART; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->MCR |= CAN_MCR_RFLM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->MCR |= CAN_MCR_TXFP; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + + /* Request leave initialisation */ + CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Wait the acknowledge */ + wait_ack = 0; + + while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that + * contains the configuration information. + * @retval None + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FA1R |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Fills each CAN_InitStruct member with its default value. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. + * @retval None + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/** + * @brief Select the start bank filter for slave CAN. + * @param CAN_BankNumber: Select the start slave bank filter from 1..27. + * @retval None + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); + + /* Enter Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Select the start slave bank */ + CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; + + /* Leave Initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFOs can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; + } +} + + +/** + * @brief Enables or disables the CAN Time TriggerOperation communication mode. + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. + * When enabled, Time stamp (TIME[15:0]) value is sent in the last two + * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] + * in data byte 7. + * @retval None + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCR |= CAN_MCR_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); + } +} +/** + * @} + */ + + +/** @defgroup CAN_Group2 CAN Frames Transmission functions + * @brief CAN Frames Transmission functions + * +@verbatim + =============================================================================== + CAN Frames Transmission functions + =============================================================================== + This section provides functions allowing to + - Initiate and transmit a CAN frame message (if there is an empty mailbox). + - Check the transmission status of a CAN Frame + - Cancel a transmit request + +@endverbatim + * @{ + */ + +/** + * @brief Initiates and transmits a CAN frame message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. + * @retval The number of the mailbox that is used for transmission or + * CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission status of a CAN Frame. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for transmission. + * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, + * CAN_TxStatus_Failed in an other case. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); + break; + case (CAN_TXMAILBOX_1): + state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); + break; + case (CAN_TXMAILBOX_2): + state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); + break; + default: + state = CAN_TxStatus_Failed; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): state = CAN_TxStatus_Pending; + break; + /* transmit failed */ + case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; + break; + /* transmit succeeded */ + case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; + break; + default: state = CAN_TxStatus_Failed; + break; + } + return (uint8_t) state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param Mailbox: Mailbox number. + * @retval None + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; + break; + case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; + break; + case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; + break; + default: + break; + } +} +/** + * @} + */ + + +/** @defgroup CAN_Group3 CAN Frames Reception functions + * @brief CAN Frames Reception functions + * +@verbatim + =============================================================================== + CAN Frames Reception functions + =============================================================================== + This section provides functions allowing to + - Receive a correct CAN frame + - Release a specified receive FIFO (2 FIFOs are available) + - Return the number of the pending received CAN frames + +@endverbatim + * @{ + */ + +/** + * @brief Receives a correct CAN frame. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive frame which contains CAN Id, + * CAN DLC, CAN data and FMI number. + * @retval None + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Releases the specified receive FIFO. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Returns the number of pending received messages. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval NbMessage : which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} +/** + * @} + */ + + +/** @defgroup CAN_Group4 CAN Operation modes functions + * @brief CAN Operation modes functions + * +@verbatim + =============================================================================== + CAN Operation modes functions + =============================================================================== + This section provides functions allowing to select the CAN Operation modes + - sleep mode + - normal mode + - initialization mode + +@endverbatim + * @{ + */ + + +/** + * @brief Selects the CAN Operation mode. + * @param CAN_OperatingMode: CAN Operating Mode. + * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. + * @retval status of the requested mode which can be + * - CAN_ModeStatus_Failed: CAN failed entering the specific mode + * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INAK_TIMEOUT; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + /* Request initialisation */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) + { + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + /* Request Sleep mode */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t) status; +} + +/** + * @brief Enters the Sleep (low power) mode. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) + { + /* Sleep mode not entered */ + sleepstatus = CAN_Sleep_Ok; + } + /* return sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode . + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Sleep mode status */ + while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) + { + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WakeUp_Ok; + } + /* return wakeup status */ + return (uint8_t)wakeupstatus; +} +/** + * @} + */ + + +/** @defgroup CAN_Group5 CAN Bus Error management functions + * @brief CAN Bus Error management functions + * +@verbatim + =============================================================================== + CAN Bus Error management functions + =============================================================================== + This section provides functions allowing to + - Return the CANx's last error code (LEC) + - Return the CANx Receive Error Counter (REC) + - Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). + + @note If TEC is greater than 255, The CAN is in bus-off state. + @note if REC or TEC are greater than 96, an Error warning flag occurs. + @note if REC or TEC are greater than 127, an Error Passive Flag occurs. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval Error code: + * - CAN_ERRORCODE_NoErr: No Error + * - CAN_ERRORCODE_StuffErr: Stuff Error + * - CAN_ERRORCODE_FormErr: Form Error + * - CAN_ERRORCODE_ACKErr : Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error + * - CAN_ERRORCODE_CRCErr: CRC Error + * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); + + /* Return the error code*/ + return errorcode; +} + +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} +/** + * @} + */ + +/** @defgroup CAN_Group6 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides functions allowing to configure the CAN Interrupts and + to get the status and clear flags and Interrupts pending bits. + + The CAN provides 14 Interrupts sources and 15 Flags: + + =============== + Flags : + =============== + The 15 flags can be divided on 4 groups: + + A. Transmit Flags + ----------------------- + CAN_FLAG_RQCP0, + CAN_FLAG_RQCP1, + CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags + Set when when the last request (transmit or abort) has + been performed. + + B. Receive Flags + ----------------------- + + CAN_FLAG_FMP0, + CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags + set to signal that messages are pending in the receive + FIFO. + These Flags are cleared only by hardware. + + CAN_FLAG_FF0, + CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags + set when three messages are stored in the selected + FIFO. + + CAN_FLAG_FOV0 + CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags + set when a new message has been received and passed + the filter while the FIFO was full. + + C. Operating Mode Flags + ----------------------- + CAN_FLAG_WKU : Wake up Flag + set to signal that a SOF bit has been detected while + the CAN hardware was in Sleep mode. + + CAN_FLAG_SLAK : Sleep acknowledge Flag + Set to signal that the CAN has entered Sleep Mode. + + D. Error Flags + ----------------------- + CAN_FLAG_EWG : Error Warning Flag + Set when the warning limit has been reached (Receive + Error Counter or Transmit Error Counter greater than 96). + This Flag is cleared only by hardware. + + CAN_FLAG_EPV : Error Passive Flag + Set when the Error Passive limit has been reached + (Receive Error Counter or Transmit Error Counter + greater than 127). + This Flag is cleared only by hardware. + + CAN_FLAG_BOF : Bus-Off Flag + set when CAN enters the bus-off state. The bus-off + state is entered on TEC overflow, greater than 255. + This Flag is cleared only by hardware. + + CAN_FLAG_LEC : Last error code Flag + set If a message has been transferred (reception or + transmission) with error, and the error code is hold. + + =============== + Interrupts : + =============== + The 14 interrupts can be divided on 4 groups: + + A. Transmit interrupt + ----------------------- + CAN_IT_TME : Transmit mailbox empty Interrupt + if enabled, this interrupt source is pending when + no transmit request are pending for Tx mailboxes. + + B. Receive Interrupts + ----------------------- + CAN_IT_FMP0, + CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts + if enabled, these interrupt sources are pending when + messages are pending in the receive FIFO. + The corresponding interrupt pending bits are cleared + only by hardware. + + CAN_IT_FF0, + CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts + if enabled, these interrupt sources are pending when + three messages are stored in the selected FIFO. + + CAN_IT_FOV0, + CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts + if enabled, these interrupt sources are pending when + a new message has been received and passed the filter + while the FIFO was full. + + C. Operating Mode Interrupts + ------------------------------- + CAN_IT_WKU : Wake-up Interrupt + if enabled, this interrupt source is pending when + a SOF bit has been detected while the CAN hardware was + in Sleep mode. + + CAN_IT_SLK : Sleep acknowledge Interrupt + if enabled, this interrupt source is pending when + the CAN has entered Sleep Mode. + + D. Error Interrupts + ----------------------- + CAN_IT_EWG : Error warning Interrupt + if enabled, this interrupt source is pending when + the warning limit has been reached (Receive Error + Counter or Transmit Error Counter=96). + + CAN_IT_EPV : Error passive Interrupt + if enabled, this interrupt source is pending when + the Error Passive limit has been reached (Receive + Error Counter or Transmit Error Counter>127). + + CAN_IT_BOF : Bus-off Interrupt + if enabled, this interrupt source is pending when + CAN enters the bus-off state. The bus-off state is + entered on TEC overflow, greater than 255. + This Flag is cleared only by hardware. + + CAN_IT_LEC : Last error code Interrupt + if enabled, this interrupt source is pending when + a message has been transferred (reception or + transmission) with error, and the error code is hold. + + CAN_IT_ERR : Error Interrupt + if enabled, this interrupt source is pending when + an error condition is pending. + + + Managing the CAN controller events : + ------------------------------------ + The user should identify which mode will be used in his application to manage + the CAN controller events: Polling mode or Interrupt mode. + + 1. In the Polling Mode it is advised to use the following functions: + - CAN_GetFlagStatus() : to check if flags events occur. + - CAN_ClearFlag() : to clear the flags events. + + + + 2. In the Interrupt Mode it is advised to use the following functions: + - CAN_ITConfig() : to enable or disable the interrupt source. + - CAN_GetITStatus() : to check if Interrupt occurs. + - CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). + @note This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts + pending bits since there are cleared only by hardware. + +@endverbatim + * @{ + */ +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->IER &= ~CAN_IT; + } +} +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag + * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag + * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @arg CAN_FLAG_LEC: Last error code Flag + * @retval The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + + if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag + * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag + * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_LEC: Last error code Flag + * @retval None + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ + { + /* Clear the selected CAN flags */ + CANx->ESR = (uint32_t)RESET; + } + else /* MSR or TSR or RF0R or RF1R */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF0R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF1R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSR = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSR = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @retval The current state of CAN_IT (SET or RESET). + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + + /* check the interrupt enable bit */ + if((CANx->IER & CAN_IT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_IT) + { + case CAN_IT_TME: + /* Check CAN_TSR_RQCPx bits */ + itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); + break; + case CAN_IT_FMP0: + /* Check CAN_RF0R_FMP0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); + break; + case CAN_IT_FF0: + /* Check CAN_RF0R_FULL0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); + break; + case CAN_IT_FOV0: + /* Check CAN_RF0R_FOVR0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); + break; + case CAN_IT_FMP1: + /* Check CAN_RF1R_FMP1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); + break; + case CAN_IT_FF1: + /* Check CAN_RF1R_FULL1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); + break; + case CAN_IT_FOV1: + /* Check CAN_RF1R_FOVR1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); + break; + case CAN_IT_WKU: + /* Check CAN_MSR_WKUI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); + break; + case CAN_IT_SLK: + /* Check CAN_MSR_SLAKI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); + break; + case CAN_IT_EWG: + /* Check CAN_ESR_EWGF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); + break; + case CAN_IT_EPV: + /* Check CAN_ESR_EPVF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); + break; + case CAN_IT_BOF: + /* Check CAN_ESR_BOFF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); + break; + case CAN_IT_LEC: + /* Check CAN_ESR_LEC bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); + break; + case CAN_IT_ERR: + /* Check CAN_MSR_ERRI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); + break; + default: + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_IT status */ + return itstatus; +} + +/** + * @brief Clears the CANx's interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @retval None + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_TME: + /* Clear CAN_TSR_RQCPx (rc_w1)*/ + CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; + break; + case CAN_IT_FF0: + /* Clear CAN_RF0R_FULL0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FULL0; + break; + case CAN_IT_FOV0: + /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FOVR0; + break; + case CAN_IT_FF1: + /* Clear CAN_RF1R_FULL1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FULL1; + break; + case CAN_IT_FOV1: + /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FOVR1; + break; + case CAN_IT_WKU: + /* Clear CAN_MSR_WKUI (rc_w1)*/ + CANx->MSR = CAN_MSR_WKUI; + break; + case CAN_IT_SLK: + /* Clear CAN_MSR_SLAKI (rc_w1)*/ + CANx->MSR = CAN_MSR_SLAKI; + break; + case CAN_IT_EWG: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_EPV: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_BOF: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_LEC: + /* Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + break; + case CAN_IT_ERR: + /*Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ + break; + default: + break; + } +} + /** + * @} + */ + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg: specifies the CAN interrupt register to check. + * @param It_Bit: specifies the interrupt source bit to check. + * @retval The new state of the CAN Interrupt (SET or RESET). + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c index 450875963..427377058 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c @@ -1,133 +1,133 @@ -/** - ****************************************************************************** - * @file stm32f2xx_crc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides all the CRC firmware functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_crc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Resets the CRC Data register (DR). - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DR = Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDR = IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_crc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides all the CRC firmware functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_crc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DR). + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CRC_CR_RESET; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c index d78bf55a8..d97a8c16c 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c @@ -1,856 +1,856 @@ -/** - ****************************************************************************** - * @file stm32f2xx_cryp.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Cryptographic processor (CRYP) peripheral: - * - Initialization and Configuration functions - * - Data treatment functions - * - Context swapping functions - * - DMA interface function - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable the CRYP controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - * - * 2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if - * needed CRYP_IVInit(). - * - * 3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. - * - * 4. Enable the CRYP controller using the CRYP_Cmd() function. - * - * 5. If using DMA for Data input and output transfer, - * Activate the needed DMA Requests using CRYP_DMACmd() function - - * 6. If DMA is not used for data transfer, use CRYP_DataIn() and - * CRYP_DataOut() functions to enter data to IN FIFO and get result - * from OUT FIFO. - * - * 7. To control CRYP events you can use one of the following - * two methods: - * - Check on CRYP flags using the CRYP_GetFlagStatus() function. - * - Use CRYP interrupts through the function CRYP_ITConfig() at - * initialization phase and CRYP_GetITStatus() function into - * interrupt routines in processing phase. - * - * 8. Save and restore Cryptographic processor context using - * CRYP_SaveContext() and CRYP_RestoreContext() functions. - * - * - * =================================================================== - * Procedure to perform an encryption or a decryption - * =================================================================== - * - * Initialization - * =============== - * 1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and - * CRYP_IVInit functions: - * - Configure the key size (128-, 192- or 256-bit, in the AES only) - * - Enter the symmetric key - * - Configure the data type - * - In case of decryption in AES-ECB or AES-CBC, you must prepare - * the key: configure the key preparation mode. Then Enable the CRYP - * peripheral using CRYP_Cmd() function: the BUSY flag is set. - * Wait until BUSY flag is reset : the key is prepared for decryption - * - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the - * AES in ECB/CBC/CTR) - * - Configure the direction (encryption/decryption). - * - Write the initialization vectors (in CBC or CTR modes only) - * - * 2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function - * - * - * Basic Processing mode (polling mode) - * ==================================== - * 1. Enable the cryptographic processor using CRYP_Cmd() function. - * - * 2. Write the first blocks in the input FIFO (2 to 8 words) using - * CRYP_DataIn() function. - * - * 3. Repeat the following sequence until the complete message has been - * processed: - * - * a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() - * function), then read the OUT-FIFO using CRYP_DataOut() function - * (1 block or until the FIFO is empty) - * - * b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() - * function then write the IN FIFO using CRYP_DataIn() function - * (1 block or until the FIFO is full) - * - * 4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and - * both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is - * reset). You can disable the peripheral using CRYP_Cmd() function. - * - * Interrupts Processing mode - * =========================== - * In this mode, Processing is done when the data are transferred by the - * CPU during interrupts. - * - * 1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using - * CRYP_ITConfig() function. - * - * 2. Enable the cryptographic processor using CRYP_Cmd() function. - * - * 3. In the CRYP_IT_INI interrupt handler : load the input message into the - * IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a - * time, or load data until the IN FIFO is full. When the last word of - * the message has been entered into the IN FIFO, disable the CRYP_IT_INI - * interrupt (using CRYP_ITConfig() function). - * - * 4. In the CRYP_IT_OUTI interrupt handler : read the output message from - * the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or - * 4 words) at a time or read data until the FIFO is empty. - * When the last word has been read, INIM=0, BUSY=0 and both FIFOs are - * empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). - * You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() - * function) and you can disable the peripheral using CRYP_Cmd() function. - * - * DMA Processing mode - * ==================== - * In this mode, Processing is done when the DMA is used to transfer the - * data from/to the memory. - * - * 1. Configure the DMA controller to transfer the input data from the - * memory using DMA_Init() function. - * The transfer length is the length of the message. - * As message padding is not managed by the peripheral, the message - * length must be an entire number of blocks. The data are transferred - * in burst mode. The burst length is 4 words in the AES and 2 or 4 - * words in the DES/TDES. The DMA should be configured to set an - * interrupt on transfer completion of the output data to indicate that - * the processing is finished. - * Refer to DMA peripheral driver for more details. - * - * 2. Enable the cryptographic processor using CRYP_Cmd() function. - * Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT - * using CRYP_DMACmd() function. - * - * 3. All the transfers and processing are managed by the DMA and the - * cryptographic processor. The DMA transfer complete interrupt indicates - * that the processing is complete. Both FIFOs are normally empty and - * CRYP_FLAG_BUSY flag is reset. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_cryp.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define FLAG_MASK ((uint8_t)0x20) -#define MAX_TIMEOUT ((uint16_t)0xFFFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the cryptographic Processor using CRYP_Init() function - - Encrypt or Decrypt - - mode : TDES-ECB, TDES-CBC, - DES-ECB, DES-CBC, - AES-ECB, AES-CBC, AES-CTR, AES-Key - - DataType : 32-bit data, 16-bit data, bit data or bit-string - - Key Size (only in AES modes) - - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function - - Configure the Initialization Vectors(IV) for CBC and CTR modes using - CRYP_IVInit() function. - - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. - - Enable or disable the CRYP Processor using CRYP_Cmd() function - - -@endverbatim - * @{ - */ -/** - * @brief Deinitializes the CRYP peripheral registers to their default reset values - * @param None - * @retval None - */ -void CRYP_DeInit(void) -{ - /* Enable CRYP reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE); - - /* Release CRYP from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE); -} - -/** - * @brief Initializes the CRYP peripheral according to the specified parameters - * in the CRYP_InitStruct. - * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains - * the configuration information for the CRYP peripheral. - * @retval None - */ -void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode)); - assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType)); - assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir)); - - /* Select Algorithm mode*/ - CRYP->CR &= ~CRYP_CR_ALGOMODE; - CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode; - - /* Select dataType */ - CRYP->CR &= ~CRYP_CR_DATATYPE; - CRYP->CR |= CRYP_InitStruct->CRYP_DataType; - - /* select Key size (used only with AES algorithm) */ - if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key)) - { - assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); - CRYP->CR &= ~CRYP_CR_KEYSIZE; - CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be - configured once the key has - been prepared */ - } - - /* Select data Direction */ - CRYP->CR &= ~CRYP_CR_ALGODIR; - CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir; -} - -/** - * @brief Fills each CRYP_InitStruct member with its default value. - * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct) -{ - /* Initialize the CRYP_AlgoDir member */ - CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - - /* initialize the CRYP_AlgoMode member */ - CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; - - /* initialize the CRYP_DataType member */ - CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b; - - /* Initialize the CRYP_KeySize member */ - CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b; -} - -/** - * @brief Initializes the CRYP Keys according to the specified parameters in - * the CRYP_KeyInitStruct. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that - * contains the configuration information for the CRYP Keys. - * @retval None - */ -void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - /* Key Initialisation */ - CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; - CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; - CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; - CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; - CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; - CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; - CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; - CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; -} - -/** - * @brief Fills each CRYP_KeyInitStruct member with its default value. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure - * which will be initialized. - * @retval None - */ -void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - CRYP_KeyInitStruct->CRYP_Key0Left = 0; - CRYP_KeyInitStruct->CRYP_Key0Right = 0; - CRYP_KeyInitStruct->CRYP_Key1Left = 0; - CRYP_KeyInitStruct->CRYP_Key1Right = 0; - CRYP_KeyInitStruct->CRYP_Key2Left = 0; - CRYP_KeyInitStruct->CRYP_Key2Right = 0; - CRYP_KeyInitStruct->CRYP_Key3Left = 0; - CRYP_KeyInitStruct->CRYP_Key3Right = 0; -} -/** - * @brief Initializes the CRYP Initialization Vectors(IV) according to the - * specified parameters in the CRYP_IVInitStruct. - * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains - * the configuration information for the CRYP Initialization Vectors(IV). - * @retval None - */ -void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) -{ - CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left; - CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right; - CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left; - CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right; -} - -/** - * @brief Fills each CRYP_IVInitStruct member with its default value. - * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization - * Vectors(IV) structure which will be initialized. - * @retval None - */ -void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) -{ - CRYP_IVInitStruct->CRYP_IV0Left = 0; - CRYP_IVInitStruct->CRYP_IV0Right = 0; - CRYP_IVInitStruct->CRYP_IV1Left = 0; - CRYP_IVInitStruct->CRYP_IV1Right = 0; -} - -/** - * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the - * FIFOs are reset) - * @note The FIFOs must be flushed only when BUSY flag is reset. - * @param None - * @retval None - */ -void CRYP_FIFOFlush(void) -{ - /* Reset the read and write pointers of the FIFOs */ - CRYP->CR |= CRYP_CR_FFLUSH; -} - -/** - * @brief Enables or disables the CRYP peripheral. - * @param NewState: new state of the CRYP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Cryptographic processor */ - CRYP->CR |= CRYP_CR_CRYPEN; - } - else - { - /* Disable the Cryptographic processor */ - CRYP->CR &= ~CRYP_CR_CRYPEN; - } -} -/** - * @} - */ - -/** @defgroup CRYP_Group2 CRYP Data processing functions - * @brief CRYP Data processing functions - * -@verbatim - =============================================================================== - CRYP Data processing functions - =============================================================================== - This section provides functions allowing the encryption and decryption - operations: - - Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. - - Get the data result from the OUT FIFO : using CRYP_DataOut() function. - -@endverbatim - * @{ - */ - -/** - * @brief Writes data in the Data Input register (DIN). - * @note After the DIN register has been read once or several times, - * the FIFO must be flushed (using CRYP_FIFOFlush() function). - * @param Data: data to write in Data Input register - * @retval None - */ -void CRYP_DataIn(uint32_t Data) -{ - CRYP->DR = Data; -} - -/** - * @brief Returns the last data entered into the output FIFO. - * @param None - * @retval Last data entered into the output FIFO. - */ -uint32_t CRYP_DataOut(void) -{ - return CRYP->DOUT; -} -/** - * @} - */ - -/** @defgroup CRYP_Group3 Context swapping functions - * @brief Context swapping functions - * -@verbatim - =============================================================================== - Context swapping functions - =============================================================================== - - This section provides functions allowing to save and store CRYP Context - - It is possible to interrupt an encryption/ decryption/ key generation process - to perform another processing with a higher priority, and to complete the - interrupted process later on, when the higher-priority task is complete. To do - so, the context of the interrupted task must be saved from the CRYP registers - to memory, and then be restored from memory to the CRYP registers. - - 1. To save the current context, use CRYP_SaveContext() function - 2. To restore the saved context, use CRYP_RestoreContext() function - - -@endverbatim - * @{ - */ - -/** - * @brief Saves the CRYP peripheral Context. - * @note This function stops DMA transfer before to save the context. After - * restoring the context, you have to enable the DMA again (if the DMA - * was previously used). - * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains - * the repository for current context. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that - * contains the configuration information for the CRYP Keys. - * @retval None - */ -ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, - CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - __IO uint32_t timeout = 0; - uint32_t ckeckmask = 0, bitstatus; - ErrorStatus status = ERROR; - - /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */ - CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN; - - /* Wait until both the IN and OUT FIFOs are empty - (IFEM=1 and OFNE=0 in the CRYP_SR register) and the - BUSY bit is cleared. */ - - if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */ - { - ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ; - } - else /* AES or DES */ - { - ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE; - } - - do - { - bitstatus = CRYP->SR & ckeckmask; - timeout++; - } - while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM)); - - if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM) - { - status = ERROR; - } - else - { - /* Stop DMA transfers on the OUT FIFO by - - writing the DOEN bit to 0 in the CRYP_DMACR register - - and clear the CRYPEN bit. */ - - CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; - CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; - - /* Save the current configuration (bits [9:2] in the CRYP_CR register) */ - CRYP_ContextSave->CR_bits9to2 = CRYP->CR & (CRYP_CR_KEYSIZE | - CRYP_CR_DATATYPE | - CRYP_CR_ALGOMODE | - CRYP_CR_ALGODIR); - - /* and, if not in ECB mode, the initialization vectors. */ - CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; - CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR; - CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR; - CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR; - - /* save The key value */ - CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; - CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; - CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; - CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; - CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; - CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; - CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; - CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; - - /* When needed, save the DMA status (pointers for IN and OUT messages, - number of remaining bytes, etc.) */ - - status = SUCCESS; - } - - return status; -} - -/** - * @brief Restores the CRYP peripheral Context. - * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function, - * after restoring the context, you have to enable the DMA again (if the - * DMA was previously used). - * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains - * the repository for saved context. - * @note The data that were saved during context saving must be rewrited into - * the IN FIFO. - * @retval None - */ -void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) -{ - - /* Configure the processor with the saved configuration */ - CRYP->CR = CRYP_ContextRestore->CR_bits9to2; - - /* restore The key value */ - CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; - CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR; - CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR; - CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR; - CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR; - CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR; - CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR; - CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR; - - /* and the initialization vectors. */ - CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR; - CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR; - CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; - CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; - - /* Enable the cryptographic processor */ - CRYP->CR |= CRYP_CR_CRYPEN; -} -/** - * @} - */ - -/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function - * @brief CRYP's DMA interface Configuration function - * -@verbatim - =============================================================================== - CRYP's DMA interface Configuration function - =============================================================================== - - This section provides functions allowing to configure the DMA interface for - CRYP data input and output transfer. - - When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be - transferred: - - From memory to the CRYP IN FIFO using the DMA peripheral by enabling - the CRYP_DMAReq_DataIN request. - - From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling - the CRYP_DMAReq_DataOUT request. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRYP DMA interface. - * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer - * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer - * @param NewState: new state of the selected CRYP DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CRYP DMA request */ - CRYP->DMACR |= CRYP_DMAReq; - } - else - { - /* Disable the selected CRYP DMA request */ - CRYP->DMACR &= (uint8_t)~CRYP_DMAReq; - } -} -/** - * @} - */ - -/** @defgroup CRYP_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the CRYP Interrupts and - to get the status and Interrupts pending bits. - - The CRYP provides 2 Interrupts sources and 7 Flags: - - Flags : - ------- - - 1. CRYP_FLAG_IFEM : Set when Input FIFO is empty. - This Flag is cleared only by hardware. - - 2. CRYP_FLAG_IFNF : Set when Input FIFO is not full. - This Flag is cleared only by hardware. - - - 3. CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending - it gives the raw interrupt state prior to masking - of the input FIFO service interrupt. - This Flag is cleared only by hardware. - - 4. CRYP_FLAG_OFNE : Set when Output FIFO not empty. - This Flag is cleared only by hardware. - - 5. CRYP_FLAG_OFFU : Set when Output FIFO is full. - This Flag is cleared only by hardware. - - 6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending - it gives the raw interrupt state prior to masking - of the output FIFO service interrupt. - This Flag is cleared only by hardware. - - 7. CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a - block of data or a key preparation (for AES - decryption). - This Flag is cleared only by hardware. - To clear it, the CRYP core must be disabled and the - last processing has completed. - - Interrupts : - ------------ - - 1. CRYP_IT_INI : The input FIFO service interrupt is asserted when there - are less than 4 words in the input FIFO. - This interrupt is associated to CRYP_FLAG_INRIS flag. - - @note This interrupt is cleared by performing write operations - to the input FIFO until it holds 4 or more words. The - input FIFO service interrupt INMIS is enabled with the - CRYP enable bit. Consequently, when CRYP is disabled, the - INMIS signal is low even if the input FIFO is empty. - - - - 2. CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there - is one or more (32-bit word) data items in the output FIFO. - This interrupt is associated to CRYP_FLAG_OUTRIS flag. - - @note This interrupt is cleared by reading data from the output - FIFO until there is no valid (32-bit) word left (that is, - the interrupt follows the state of the OFNE (output FIFO - not empty) flag). - - - Managing the CRYP controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the CRYP controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - CRYP_GetFlagStatus() : to check if flags events occur. - - @note The CRYPT flags do not need to be cleared since they are cleared as - soon as the associated event are reset. - - - 2. In the Interrupt Mode it is advised to use the following functions: - - CRYP_ITConfig() : to enable or disable the interrupt source. - - CRYP_GetITStatus() : to check if Interrupt occurs. - - @note The CRYPT interrupts have no pending bits, the interrupt is cleared as - soon as the associated event is reset. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified CRYP interrupts. - * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRYP_IT_INI: Input FIFO interrupt - * @arg CRYP_IT_OUTI: Output FIFO interrupt - * @param NewState: new state of the specified CRYP interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRYP_CONFIG_IT(CRYP_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CRYP interrupt */ - CRYP->IMSCR |= CRYP_IT; - } - else - { - /* Disable the selected CRYP interrupt */ - CRYP->IMSCR &= (uint8_t)~CRYP_IT; - } -} - -/** - * @brief Checks whether the specified CRYP interrupt has occurred or not. - * @note This function checks the status of the masked interrupt (i.e the - * interrupt should be previously enabled). - * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check. - * This parameter can be one of the following values: - * @arg CRYP_IT_INI: Input FIFO interrupt - * @arg CRYP_IT_OUTI: Output FIFO interrupt - * @retval The new state of CRYP_IT (SET or RESET). - */ -ITStatus CRYP_GetITStatus(uint8_t CRYP_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_CRYP_GET_IT(CRYP_IT)); - - /* Check the status of the specified CRYP interrupt */ - if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET) - { - /* CRYP_IT is set */ - bitstatus = SET; - } - else - { - /* CRYP_IT is reset */ - bitstatus = RESET; - } - /* Return the CRYP_IT status */ - return bitstatus; -} - -/** - * @brief Checks whether the specified CRYP flag is set or not. - * @param CRYP_FLAG: specifies the CRYP flag to check. - * This parameter can be one of the following values: - * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag. - * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag. - * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag. - * @arg CRYP_FLAG_OFFU: Output FIFO Full flag. - * @arg CRYP_FLAG_BUSY: Busy flag. - * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag. - * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag. - * @retval The new state of CRYP_FLAG (SET or RESET). - */ -FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tempreg = 0; - - /* Check the parameters */ - assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG)); - - /* check if the FLAG is in RISR register */ - if ((CRYP_FLAG & FLAG_MASK) != 0x00) - { - tempreg = CRYP->RISR; - } - else /* The FLAG is in SR register */ - { - tempreg = CRYP->SR; - } - - - /* Check the status of the specified CRYP flag */ - if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET) - { - /* CRYP_FLAG is set */ - bitstatus = SET; - } - else - { - /* CRYP_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the CRYP_FLAG status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_cryp.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Cryptographic processor (CRYP) peripheral: + * - Initialization and Configuration functions + * - Data treatment functions + * - Context swapping functions + * - DMA interface function + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable the CRYP controller clock using + * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. + * + * 2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if + * needed CRYP_IVInit(). + * + * 3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. + * + * 4. Enable the CRYP controller using the CRYP_Cmd() function. + * + * 5. If using DMA for Data input and output transfer, + * Activate the needed DMA Requests using CRYP_DMACmd() function + + * 6. If DMA is not used for data transfer, use CRYP_DataIn() and + * CRYP_DataOut() functions to enter data to IN FIFO and get result + * from OUT FIFO. + * + * 7. To control CRYP events you can use one of the following + * two methods: + * - Check on CRYP flags using the CRYP_GetFlagStatus() function. + * - Use CRYP interrupts through the function CRYP_ITConfig() at + * initialization phase and CRYP_GetITStatus() function into + * interrupt routines in processing phase. + * + * 8. Save and restore Cryptographic processor context using + * CRYP_SaveContext() and CRYP_RestoreContext() functions. + * + * + * =================================================================== + * Procedure to perform an encryption or a decryption + * =================================================================== + * + * Initialization + * =============== + * 1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and + * CRYP_IVInit functions: + * - Configure the key size (128-, 192- or 256-bit, in the AES only) + * - Enter the symmetric key + * - Configure the data type + * - In case of decryption in AES-ECB or AES-CBC, you must prepare + * the key: configure the key preparation mode. Then Enable the CRYP + * peripheral using CRYP_Cmd() function: the BUSY flag is set. + * Wait until BUSY flag is reset : the key is prepared for decryption + * - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the + * AES in ECB/CBC/CTR) + * - Configure the direction (encryption/decryption). + * - Write the initialization vectors (in CBC or CTR modes only) + * + * 2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function + * + * + * Basic Processing mode (polling mode) + * ==================================== + * 1. Enable the cryptographic processor using CRYP_Cmd() function. + * + * 2. Write the first blocks in the input FIFO (2 to 8 words) using + * CRYP_DataIn() function. + * + * 3. Repeat the following sequence until the complete message has been + * processed: + * + * a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() + * function), then read the OUT-FIFO using CRYP_DataOut() function + * (1 block or until the FIFO is empty) + * + * b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() + * function then write the IN FIFO using CRYP_DataIn() function + * (1 block or until the FIFO is full) + * + * 4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and + * both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is + * reset). You can disable the peripheral using CRYP_Cmd() function. + * + * Interrupts Processing mode + * =========================== + * In this mode, Processing is done when the data are transferred by the + * CPU during interrupts. + * + * 1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using + * CRYP_ITConfig() function. + * + * 2. Enable the cryptographic processor using CRYP_Cmd() function. + * + * 3. In the CRYP_IT_INI interrupt handler : load the input message into the + * IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a + * time, or load data until the IN FIFO is full. When the last word of + * the message has been entered into the IN FIFO, disable the CRYP_IT_INI + * interrupt (using CRYP_ITConfig() function). + * + * 4. In the CRYP_IT_OUTI interrupt handler : read the output message from + * the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or + * 4 words) at a time or read data until the FIFO is empty. + * When the last word has been read, INIM=0, BUSY=0 and both FIFOs are + * empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). + * You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() + * function) and you can disable the peripheral using CRYP_Cmd() function. + * + * DMA Processing mode + * ==================== + * In this mode, Processing is done when the DMA is used to transfer the + * data from/to the memory. + * + * 1. Configure the DMA controller to transfer the input data from the + * memory using DMA_Init() function. + * The transfer length is the length of the message. + * As message padding is not managed by the peripheral, the message + * length must be an entire number of blocks. The data are transferred + * in burst mode. The burst length is 4 words in the AES and 2 or 4 + * words in the DES/TDES. The DMA should be configured to set an + * interrupt on transfer completion of the output data to indicate that + * the processing is finished. + * Refer to DMA peripheral driver for more details. + * + * 2. Enable the cryptographic processor using CRYP_Cmd() function. + * Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT + * using CRYP_DMACmd() function. + * + * 3. All the transfers and processing are managed by the DMA and the + * cryptographic processor. The DMA transfer complete interrupt indicates + * that the processing is complete. Both FIFOs are normally empty and + * CRYP_FLAG_BUSY flag is reset. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define FLAG_MASK ((uint8_t)0x20) +#define MAX_TIMEOUT ((uint16_t)0xFFFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + This section provides functions allowing to + - Initialize the cryptographic Processor using CRYP_Init() function + - Encrypt or Decrypt + - mode : TDES-ECB, TDES-CBC, + DES-ECB, DES-CBC, + AES-ECB, AES-CBC, AES-CTR, AES-Key + - DataType : 32-bit data, 16-bit data, bit data or bit-string + - Key Size (only in AES modes) + - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function + - Configure the Initialization Vectors(IV) for CBC and CTR modes using + CRYP_IVInit() function. + - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. + - Enable or disable the CRYP Processor using CRYP_Cmd() function + + +@endverbatim + * @{ + */ +/** + * @brief Deinitializes the CRYP peripheral registers to their default reset values + * @param None + * @retval None + */ +void CRYP_DeInit(void) +{ + /* Enable CRYP reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE); + + /* Release CRYP from reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE); +} + +/** + * @brief Initializes the CRYP peripheral according to the specified parameters + * in the CRYP_InitStruct. + * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains + * the configuration information for the CRYP peripheral. + * @retval None + */ +void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode)); + assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType)); + assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir)); + + /* Select Algorithm mode*/ + CRYP->CR &= ~CRYP_CR_ALGOMODE; + CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode; + + /* Select dataType */ + CRYP->CR &= ~CRYP_CR_DATATYPE; + CRYP->CR |= CRYP_InitStruct->CRYP_DataType; + + /* select Key size (used only with AES algorithm) */ + if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) || + (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) || + (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) || + (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key)) + { + assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); + CRYP->CR &= ~CRYP_CR_KEYSIZE; + CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be + configured once the key has + been prepared */ + } + + /* Select data Direction */ + CRYP->CR &= ~CRYP_CR_ALGODIR; + CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir; +} + +/** + * @brief Fills each CRYP_InitStruct member with its default value. + * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct) +{ + /* Initialize the CRYP_AlgoDir member */ + CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + + /* initialize the CRYP_AlgoMode member */ + CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; + + /* initialize the CRYP_DataType member */ + CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b; + + /* Initialize the CRYP_KeySize member */ + CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b; +} + +/** + * @brief Initializes the CRYP Keys according to the specified parameters in + * the CRYP_KeyInitStruct. + * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that + * contains the configuration information for the CRYP Keys. + * @retval None + */ +void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) +{ + /* Key Initialisation */ + CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; + CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; + CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; + CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; + CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; + CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; + CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; + CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; +} + +/** + * @brief Fills each CRYP_KeyInitStruct member with its default value. + * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure + * which will be initialized. + * @retval None + */ +void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) +{ + CRYP_KeyInitStruct->CRYP_Key0Left = 0; + CRYP_KeyInitStruct->CRYP_Key0Right = 0; + CRYP_KeyInitStruct->CRYP_Key1Left = 0; + CRYP_KeyInitStruct->CRYP_Key1Right = 0; + CRYP_KeyInitStruct->CRYP_Key2Left = 0; + CRYP_KeyInitStruct->CRYP_Key2Right = 0; + CRYP_KeyInitStruct->CRYP_Key3Left = 0; + CRYP_KeyInitStruct->CRYP_Key3Right = 0; +} +/** + * @brief Initializes the CRYP Initialization Vectors(IV) according to the + * specified parameters in the CRYP_IVInitStruct. + * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains + * the configuration information for the CRYP Initialization Vectors(IV). + * @retval None + */ +void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) +{ + CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left; + CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right; + CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left; + CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right; +} + +/** + * @brief Fills each CRYP_IVInitStruct member with its default value. + * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization + * Vectors(IV) structure which will be initialized. + * @retval None + */ +void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) +{ + CRYP_IVInitStruct->CRYP_IV0Left = 0; + CRYP_IVInitStruct->CRYP_IV0Right = 0; + CRYP_IVInitStruct->CRYP_IV1Left = 0; + CRYP_IVInitStruct->CRYP_IV1Right = 0; +} + +/** + * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the + * FIFOs are reset) + * @note The FIFOs must be flushed only when BUSY flag is reset. + * @param None + * @retval None + */ +void CRYP_FIFOFlush(void) +{ + /* Reset the read and write pointers of the FIFOs */ + CRYP->CR |= CRYP_CR_FFLUSH; +} + +/** + * @brief Enables or disables the CRYP peripheral. + * @param NewState: new state of the CRYP peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRYP_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Cryptographic processor */ + CRYP->CR |= CRYP_CR_CRYPEN; + } + else + { + /* Disable the Cryptographic processor */ + CRYP->CR &= ~CRYP_CR_CRYPEN; + } +} +/** + * @} + */ + +/** @defgroup CRYP_Group2 CRYP Data processing functions + * @brief CRYP Data processing functions + * +@verbatim + =============================================================================== + CRYP Data processing functions + =============================================================================== + This section provides functions allowing the encryption and decryption + operations: + - Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. + - Get the data result from the OUT FIFO : using CRYP_DataOut() function. + +@endverbatim + * @{ + */ + +/** + * @brief Writes data in the Data Input register (DIN). + * @note After the DIN register has been read once or several times, + * the FIFO must be flushed (using CRYP_FIFOFlush() function). + * @param Data: data to write in Data Input register + * @retval None + */ +void CRYP_DataIn(uint32_t Data) +{ + CRYP->DR = Data; +} + +/** + * @brief Returns the last data entered into the output FIFO. + * @param None + * @retval Last data entered into the output FIFO. + */ +uint32_t CRYP_DataOut(void) +{ + return CRYP->DOUT; +} +/** + * @} + */ + +/** @defgroup CRYP_Group3 Context swapping functions + * @brief Context swapping functions + * +@verbatim + =============================================================================== + Context swapping functions + =============================================================================== + + This section provides functions allowing to save and store CRYP Context + + It is possible to interrupt an encryption/ decryption/ key generation process + to perform another processing with a higher priority, and to complete the + interrupted process later on, when the higher-priority task is complete. To do + so, the context of the interrupted task must be saved from the CRYP registers + to memory, and then be restored from memory to the CRYP registers. + + 1. To save the current context, use CRYP_SaveContext() function + 2. To restore the saved context, use CRYP_RestoreContext() function + + +@endverbatim + * @{ + */ + +/** + * @brief Saves the CRYP peripheral Context. + * @note This function stops DMA transfer before to save the context. After + * restoring the context, you have to enable the DMA again (if the DMA + * was previously used). + * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains + * the repository for current context. + * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that + * contains the configuration information for the CRYP Keys. + * @retval None + */ +ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, + CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) +{ + __IO uint32_t timeout = 0; + uint32_t ckeckmask = 0, bitstatus; + ErrorStatus status = ERROR; + + /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */ + CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN; + + /* Wait until both the IN and OUT FIFOs are empty + (IFEM=1 and OFNE=0 in the CRYP_SR register) and the + BUSY bit is cleared. */ + + if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */ + { + ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ; + } + else /* AES or DES */ + { + ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE; + } + + do + { + bitstatus = CRYP->SR & ckeckmask; + timeout++; + } + while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM)); + + if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM) + { + status = ERROR; + } + else + { + /* Stop DMA transfers on the OUT FIFO by + - writing the DOEN bit to 0 in the CRYP_DMACR register + - and clear the CRYPEN bit. */ + + CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; + CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; + + /* Save the current configuration (bits [9:2] in the CRYP_CR register) */ + CRYP_ContextSave->CR_bits9to2 = CRYP->CR & (CRYP_CR_KEYSIZE | + CRYP_CR_DATATYPE | + CRYP_CR_ALGOMODE | + CRYP_CR_ALGODIR); + + /* and, if not in ECB mode, the initialization vectors. */ + CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; + CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR; + CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR; + CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR; + + /* save The key value */ + CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; + CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; + CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; + CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; + CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; + CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; + CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; + CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; + + /* When needed, save the DMA status (pointers for IN and OUT messages, + number of remaining bytes, etc.) */ + + status = SUCCESS; + } + + return status; +} + +/** + * @brief Restores the CRYP peripheral Context. + * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function, + * after restoring the context, you have to enable the DMA again (if the + * DMA was previously used). + * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains + * the repository for saved context. + * @note The data that were saved during context saving must be rewrited into + * the IN FIFO. + * @retval None + */ +void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) +{ + + /* Configure the processor with the saved configuration */ + CRYP->CR = CRYP_ContextRestore->CR_bits9to2; + + /* restore The key value */ + CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; + CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR; + CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR; + CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR; + CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR; + CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR; + CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR; + CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR; + + /* and the initialization vectors. */ + CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR; + CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR; + CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; + CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; + + /* Enable the cryptographic processor */ + CRYP->CR |= CRYP_CR_CRYPEN; +} +/** + * @} + */ + +/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function + * @brief CRYP's DMA interface Configuration function + * +@verbatim + =============================================================================== + CRYP's DMA interface Configuration function + =============================================================================== + + This section provides functions allowing to configure the DMA interface for + CRYP data input and output transfer. + + When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be + transferred: + - From memory to the CRYP IN FIFO using the DMA peripheral by enabling + the CRYP_DMAReq_DataIN request. + - From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling + the CRYP_DMAReq_DataOUT request. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the CRYP DMA interface. + * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer + * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer + * @param NewState: new state of the selected CRYP DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CRYP DMA request */ + CRYP->DMACR |= CRYP_DMAReq; + } + else + { + /* Disable the selected CRYP DMA request */ + CRYP->DMACR &= (uint8_t)~CRYP_DMAReq; + } +} +/** + * @} + */ + +/** @defgroup CRYP_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides functions allowing to configure the CRYP Interrupts and + to get the status and Interrupts pending bits. + + The CRYP provides 2 Interrupts sources and 7 Flags: + + Flags : + ------- + + 1. CRYP_FLAG_IFEM : Set when Input FIFO is empty. + This Flag is cleared only by hardware. + + 2. CRYP_FLAG_IFNF : Set when Input FIFO is not full. + This Flag is cleared only by hardware. + + + 3. CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending + it gives the raw interrupt state prior to masking + of the input FIFO service interrupt. + This Flag is cleared only by hardware. + + 4. CRYP_FLAG_OFNE : Set when Output FIFO not empty. + This Flag is cleared only by hardware. + + 5. CRYP_FLAG_OFFU : Set when Output FIFO is full. + This Flag is cleared only by hardware. + + 6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending + it gives the raw interrupt state prior to masking + of the output FIFO service interrupt. + This Flag is cleared only by hardware. + + 7. CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a + block of data or a key preparation (for AES + decryption). + This Flag is cleared only by hardware. + To clear it, the CRYP core must be disabled and the + last processing has completed. + + Interrupts : + ------------ + + 1. CRYP_IT_INI : The input FIFO service interrupt is asserted when there + are less than 4 words in the input FIFO. + This interrupt is associated to CRYP_FLAG_INRIS flag. + + @note This interrupt is cleared by performing write operations + to the input FIFO until it holds 4 or more words. The + input FIFO service interrupt INMIS is enabled with the + CRYP enable bit. Consequently, when CRYP is disabled, the + INMIS signal is low even if the input FIFO is empty. + + + + 2. CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there + is one or more (32-bit word) data items in the output FIFO. + This interrupt is associated to CRYP_FLAG_OUTRIS flag. + + @note This interrupt is cleared by reading data from the output + FIFO until there is no valid (32-bit) word left (that is, + the interrupt follows the state of the OFNE (output FIFO + not empty) flag). + + + Managing the CRYP controller events : + ------------------------------------ + The user should identify which mode will be used in his application to manage + the CRYP controller events: Polling mode or Interrupt mode. + + 1. In the Polling Mode it is advised to use the following functions: + - CRYP_GetFlagStatus() : to check if flags events occur. + + @note The CRYPT flags do not need to be cleared since they are cleared as + soon as the associated event are reset. + + + 2. In the Interrupt Mode it is advised to use the following functions: + - CRYP_ITConfig() : to enable or disable the interrupt source. + - CRYP_GetITStatus() : to check if Interrupt occurs. + + @note The CRYPT interrupts have no pending bits, the interrupt is cleared as + soon as the associated event is reset. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified CRYP interrupts. + * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CRYP_IT_INI: Input FIFO interrupt + * @arg CRYP_IT_OUTI: Output FIFO interrupt + * @param NewState: new state of the specified CRYP interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CRYP_CONFIG_IT(CRYP_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CRYP interrupt */ + CRYP->IMSCR |= CRYP_IT; + } + else + { + /* Disable the selected CRYP interrupt */ + CRYP->IMSCR &= (uint8_t)~CRYP_IT; + } +} + +/** + * @brief Checks whether the specified CRYP interrupt has occurred or not. + * @note This function checks the status of the masked interrupt (i.e the + * interrupt should be previously enabled). + * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check. + * This parameter can be one of the following values: + * @arg CRYP_IT_INI: Input FIFO interrupt + * @arg CRYP_IT_OUTI: Output FIFO interrupt + * @retval The new state of CRYP_IT (SET or RESET). + */ +ITStatus CRYP_GetITStatus(uint8_t CRYP_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_CRYP_GET_IT(CRYP_IT)); + + /* Check the status of the specified CRYP interrupt */ + if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET) + { + /* CRYP_IT is set */ + bitstatus = SET; + } + else + { + /* CRYP_IT is reset */ + bitstatus = RESET; + } + /* Return the CRYP_IT status */ + return bitstatus; +} + +/** + * @brief Checks whether the specified CRYP flag is set or not. + * @param CRYP_FLAG: specifies the CRYP flag to check. + * This parameter can be one of the following values: + * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag. + * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag. + * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag. + * @arg CRYP_FLAG_OFFU: Output FIFO Full flag. + * @arg CRYP_FLAG_BUSY: Busy flag. + * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag. + * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag. + * @retval The new state of CRYP_FLAG (SET or RESET). + */ +FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tempreg = 0; + + /* Check the parameters */ + assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG)); + + /* check if the FLAG is in RISR register */ + if ((CRYP_FLAG & FLAG_MASK) != 0x00) + { + tempreg = CRYP->RISR; + } + else /* The FLAG is in SR register */ + { + tempreg = CRYP->SR; + } + + + /* Check the status of the specified CRYP flag */ + if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET) + { + /* CRYP_FLAG is set */ + bitstatus = SET; + } + else + { + /* CRYP_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the CRYP_FLAG status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c index 25520e8f8..a13aca304 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c @@ -1,644 +1,644 @@ -/** - ****************************************************************************** - * @file stm32f2xx_cryp_aes.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides high level functions to encrypt and decrypt an - * input message using AES in ECB/CBC/CTR modes. - * It uses the stm32f2xx_cryp.c/.h drivers to access the STM32F2xx CRYP - * peripheral. - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The CRYP controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - * - * 2. Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() - * function. - * - * 3. Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() - * function. - * - * 4. Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() - * function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_cryp.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group6 High Level AES functions - * @brief High Level AES functions - * -@verbatim - =============================================================================== - High Level AES functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using AES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for AES algorithm. - * @param Keysize: length of the Key, must be a 128, 192 or 256. - * @param Input: pointer to the Input buffer. - * @param Ilength: length of the Input buffer, must be a multiple of 16. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize, - uint8_t* Input, uint32_t Ilength, uint8_t* Output) -{ - CRYP_InitTypeDef AES_CRYP_InitStructure; - CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); - - switch(Keysize) - { - case 128: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 192: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 256: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; - AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - default: - break; - } - - /*------------------ AES Decryption ------------------*/ - if(Mode == MODE_DECRYPT) /* AES decryption */ - { - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Crypto Init for Key preparation for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; - CRYP_Init(&AES_CRYP_InitStructure); - - /* Key Initialisation */ - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - /* wait until the Busy flag is RESET */ - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - else - { - /* Crypto Init for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - } - /*------------------ AES Encryption ------------------*/ - else /* AES encryption */ - { - - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&AES_CRYP_InitStructure); - - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_cryp.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group6 High Level AES functions + * @brief High Level AES functions + * +@verbatim + =============================================================================== + High Level AES functions + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Encrypt and decrypt using AES in ECB Mode + * @param Mode: encryption or decryption Mode. + * This parameter can be one of the following values: + * @arg MODE_ENCRYPT: Encryption + * @arg MODE_DECRYPT: Decryption + * @param Key: Key used for AES algorithm. + * @param Keysize: length of the Key, must be a 128, 192 or 256. + * @param Input: pointer to the Input buffer. + * @param Ilength: length of the Input buffer, must be a multiple of 16. + * @param Output: pointer to the returned buffer. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Operation done + * - ERROR: Operation failed + */ +ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize, + uint8_t* Input, uint32_t Ilength, uint8_t* Output) +{ + CRYP_InitTypeDef AES_CRYP_InitStructure; + CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t keyaddr = (uint32_t)Key; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + uint32_t i = 0; + + /* Crypto structures initialisation*/ + CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); + + switch(Keysize) + { + case 128: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + case 192: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; + AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + case 256: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; + AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + default: + break; + } + + /*------------------ AES Decryption ------------------*/ + if(Mode == MODE_DECRYPT) /* AES decryption */ + { + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Crypto Init for Key preparation for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; + CRYP_Init(&AES_CRYP_InitStructure); + + /* Key Initialisation */ + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + /* wait until the Busy flag is RESET */ + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + else + { + /* Crypto Init for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + } + } + /*------------------ AES Encryption ------------------*/ + else /* AES encryption */ + { + + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* Crypto Init for Encryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + } + + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&AES_CRYP_InitStructure); + + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_cryp.h" - - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group8 High Level DES functions - * @brief High Level DES functions - * -@verbatim - =============================================================================== - High Level DES functions - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using DES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for DES algorithm. - * @param Ilength: length of the Input buffer, must be a multiple of 8. - * @param Input: pointer to the Input buffer. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, - uint32_t Ilength, uint8_t *Output) -{ - CRYP_InitTypeDef DES_CRYP_InitStructure; - CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - if( Mode == MODE_ENCRYPT ) /* DES encryption */ - { - DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */ - { - DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - - DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB; - DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&DES_CRYP_InitStructure); - - /* Key Initialisation */ - DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - CRYP_KeyInit(& DES_CRYP_KeyInitStructure); - - /* Flush IN/OUT FIFO */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_cryp.h" + + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group8 High Level DES functions + * @brief High Level DES functions + * +@verbatim + =============================================================================== + High Level DES functions + =============================================================================== +@endverbatim + * @{ + */ + +/** + * @brief Encrypt and decrypt using DES in ECB Mode + * @param Mode: encryption or decryption Mode. + * This parameter can be one of the following values: + * @arg MODE_ENCRYPT: Encryption + * @arg MODE_DECRYPT: Decryption + * @param Key: Key used for DES algorithm. + * @param Ilength: length of the Input buffer, must be a multiple of 8. + * @param Input: pointer to the Input buffer. + * @param Output: pointer to the returned buffer. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Operation done + * - ERROR: Operation failed + */ +ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, + uint32_t Ilength, uint8_t *Output) +{ + CRYP_InitTypeDef DES_CRYP_InitStructure; + CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t keyaddr = (uint32_t)Key; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + uint32_t i = 0; + + /* Crypto structures initialisation*/ + CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure); + + /* Crypto Init for Encryption process */ + if( Mode == MODE_ENCRYPT ) /* DES encryption */ + { + DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + } + else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */ + { + DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + } + + DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB; + DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&DES_CRYP_InitStructure); + + /* Key Initialisation */ + DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + CRYP_KeyInit(& DES_CRYP_KeyInitStructure); + + /* Flush IN/OUT FIFO */ + CRYP_FIFOFlush(); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_cryp.h" - - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group7 High Level TDES functions - * @brief High Level TDES functions - * -@verbatim - =============================================================================== - High Level TDES functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using TDES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for TDES algorithm. - * @param Ilength: length of the Input buffer, must be a multiple of 8. - * @param Input: pointer to the Input buffer. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, - uint32_t Ilength, uint8_t *Output) -{ - CRYP_InitTypeDef TDES_CRYP_InitStructure; - CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - if(Mode == MODE_ENCRYPT) /* TDES encryption */ - { - TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */ - { - TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - - TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; - TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&TDES_CRYP_InitStructure); - - /* Key Initialisation */ - TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - CRYP_KeyInit(& TDES_CRYP_KeyInitStructure); - - /* Flush IN/OUT FIFO */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_cryp.h" + + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group7 High Level TDES functions + * @brief High Level TDES functions + * +@verbatim + =============================================================================== + High Level TDES functions + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Encrypt and decrypt using TDES in ECB Mode + * @param Mode: encryption or decryption Mode. + * This parameter can be one of the following values: + * @arg MODE_ENCRYPT: Encryption + * @arg MODE_DECRYPT: Decryption + * @param Key: Key used for TDES algorithm. + * @param Ilength: length of the Input buffer, must be a multiple of 8. + * @param Input: pointer to the Input buffer. + * @param Output: pointer to the returned buffer. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Operation done + * - ERROR: Operation failed + */ +ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, + uint32_t Ilength, uint8_t *Output) +{ + CRYP_InitTypeDef TDES_CRYP_InitStructure; + CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t keyaddr = (uint32_t)Key; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + uint32_t i = 0; + + /* Crypto structures initialisation*/ + CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure); + + /* Crypto Init for Encryption process */ + if(Mode == MODE_ENCRYPT) /* TDES encryption */ + { + TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + } + else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */ + { + TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + } + + TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; + TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&TDES_CRYP_InitStructure); + + /* Key Initialisation */ + TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + CRYP_KeyInit(& TDES_CRYP_KeyInitStructure); + + /* Flush IN/OUT FIFO */ + CRYP_FIFOFlush(); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_dac.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** @defgroup DAC_Group1 DAC channels configuration - * @brief DAC channels configuration: trigger, output buffer, data format - * -@verbatim - =============================================================================== - DAC channels configuration: trigger, output buffer, data format - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified parameters - * in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains - * the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); - -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, - wave generation, mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ - DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @note When the DAC channel is enabled the trigger source can no more be modified. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel DAC. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup DAC_Group2 DMA management functions - * @brief DMA management functions - * -@verbatim - =============================================================================== - DMA management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, - * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be - * already configured. - * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be - * already configured. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); - } -} -/** - * @} - */ - -/** @defgroup DAC_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} - -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's pending flags. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's interrupt pending bits. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_dac.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Digital-to-Analog Converter (DAC) peripheral: + * - DAC channels configuration: trigger, output buffer, data format + * - DMA management + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * DAC Peripheral features + * =================================================================== + * + * DAC Channels + * ============= + * The device integrates two 12-bit Digital Analog Converters that can + * be used independently or simultaneously (dual mode): + * 1- DAC channel1 with DAC_OUT1 (PA4) as output + * 1- DAC channel2 with DAC_OUT2 (PA5) as output + * + * DAC Triggers + * ============= + * Digital to Analog conversion can be non-triggered using DAC_Trigger_None + * and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register + * using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions. + * + * Digital to Analog conversion can be triggered by: + * 1- External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. + * The used pin (GPIOx_Pin9) must be configured in input mode. + * + * 2- Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 + * (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...) + * The timer TRGO event should be selected using TIM_SelectOutputTrigger() + * + * 3- Software using DAC_Trigger_Software + * + * DAC Buffer mode feature + * ======================== + * Each DAC channel integrates an output buffer that can be used to + * reduce the output impedance, and to drive external loads directly + * without having to add an external operational amplifier. + * To enable, the output buffer use + * DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + * + * Refer to the device datasheet for more details about output + * impedance value with and without output buffer. + * + * DAC wave generation feature + * ============================= + * Both DAC channels can be used to generate + * 1- Noise wave using DAC_WaveGeneration_Noise + * 2- Triangle wave using DAC_WaveGeneration_Triangle + * + * Wave generation can be disabled using DAC_WaveGeneration_None + * + * DAC data format + * ================ + * The DAC data format can be: + * 1- 8-bit right alignment using DAC_Align_8b_R + * 2- 12-bit left alignment using DAC_Align_12b_L + * 3- 12-bit right alignment using DAC_Align_12b_R + * + * DAC data value to voltage correspondence + * ======================================== + * The analog output voltage on each DAC channel pin is determined + * by the following equation: + * DAC_OUTx = VREF+ * DOR / 4095 + * with DOR is the Data Output Register + * VEF+ is the input voltage reference (refer to the device datasheet) + * e.g. To set DAC_OUT1 to 0.7V, use + * DAC_SetChannel1Data(DAC_Align_12b_R, 868); + * Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + * + * DMA requests + * ============= + * A DMA1 request can be generated when an external trigger (but not + * a software trigger) occurs if DMA1 requests are enabled using + * DAC_DMACmd() + * DMA1 requests are mapped as following: + * 1- DAC channel1 : mapped on DMA1 Stream5 channel7 which must be + * already configured + * 2- DAC channel2 : mapped on DMA1 Stream6 channel7 which must be + * already configured + * + * =================================================================== + * How to use this driver + * =================================================================== + * - DAC APB clock must be enabled to get write access to DAC + * registers using + * RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) + * - Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. + * - Configure the DAC channel using DAC_Init() function + * - Enable the DAC channel using DAC_Cmd() function + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_dac.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* CR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** @defgroup DAC_Group1 DAC channels configuration + * @brief DAC channels configuration: trigger, output buffer, data format + * +@verbatim + =============================================================================== + DAC channels configuration: trigger, output buffer, data format + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified parameters + * in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains + * the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); + +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, + wave generation, mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ + DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @note When the DAC channel is enabled the trigger source can no more be modified. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= (DAC_CR_EN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_SET; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignment for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel DAC. + * @param DAC_Align: Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} +/** + * @} + */ + +/** @defgroup DAC_Group2 DMA management functions + * @brief DMA management functions + * +@verbatim + =============================================================================== + DMA management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, + * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be + * already configured. + * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be + * already configured. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); + } +} +/** + * @} + */ + +/** @defgroup DAC_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} + +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's pending flags. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's interrupt pending bits. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c index 08000ceaf..160f2b4b4 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c @@ -1,180 +1,180 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dbgmcu.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides all the DBGMCU firmware functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_dbgmcu.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @brief Configures low power mode behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @param NewState: new state of the specified low power mode in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB1 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted - * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted - * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted - * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted - * @arg DBGMCU_RTC_STOP: RTC Wakeup counter stopped when Core is halted. - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB1FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB1FZ &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB2 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted - * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted - * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted - * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted - * @param NewState: new state of the specified peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB2FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB2FZ &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_dbgmcu.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides all the DBGMCU firmware functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_dbgmcu.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); +} + +/** + * @brief Configures low power mode behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @param NewState: new state of the specified low power mode in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/** + * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB1 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted + * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @arg DBGMCU_RTC_STOP: RTC Wakeup counter stopped when Core is halted. + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB1FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB1FZ &= ~DBGMCU_Periph; + } +} + +/** + * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB2 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted + * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted + * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted + * @param NewState: new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB2FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB2FZ &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c index 09685a624..5bf4c9cc1 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c @@ -1,540 +1,540 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dcmi.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the DCMI peripheral: - * - Initialization and Configuration - * - Image capture functions - * - Interrupts and flags management - * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * The sequence below describes how to use this driver to capture image - * from a camera module connected to the DCMI Interface. - * This sequence does not take into account the configuration of the - * camera module, which should be made before to configure and enable - * the DCMI to capture images. - * - * 1. Enable the clock for the DCMI and associated GPIOs using the following functions: - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - * 2. DCMI pins configuration - * - Connect the involved DCMI pins to AF13 using the following function - * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); - * - Configure these DCMI pins in alternate function mode by calling the function - * GPIO_Init(); - * - * 3. Declare a DCMI_InitTypeDef structure, for example: - * DCMI_InitTypeDef DCMI_InitStructure; - * and fill the DCMI_InitStructure variable with the allowed values - * of the structure member. - * - * 4. Initialize the DCMI interface by calling the function - * DCMI_Init(&DCMI_InitStructure); - * - * 5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR - * register to the destination memory buffer. - * - * 6. Enable DCMI interface using the function - * DCMI_Cmd(ENABLE); - * - * 7. Start the image capture using the function - * DCMI_CaptureCmd(ENABLE); - * - * 8. At this stage the DCMI interface waits for the first start of frame, - * then a DMA request is generated continuously/once (depending on the - * mode used, Continuous/Snapshot) to transfer the received data into - * the destination memory. - * - * @note If you need to capture only a rectangular window from the received - * image, you have to use the DCMI_CROPConfig() function to configure - * the coordinates and size of the window to be captured, then enable - * the Crop feature using DCMI_CROPCmd(ENABLE); - * In this case, the Crop configuration should be made before to enable - * and start the DCMI interface. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_dcmi.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DCMI - * @brief DCMI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DCMI_Private_Functions - * @{ - */ - -/** @defgroup DCMI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DCMI registers to their default reset values. - * @param None - * @retval None - */ -void DCMI_DeInit(void) -{ - DCMI->CR = 0x0; - DCMI->IER = 0x0; - DCMI->ICR = 0x1F; - DCMI->ESCR = 0x0; - DCMI->ESUR = 0x0; - DCMI->CWSTRTR = 0x0; - DCMI->CWSIZER = 0x0; -} - -/** - * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. - * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains - * the configuration information for the DCMI. - * @retval None - */ -void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct) -{ - uint32_t temp = 0x0; - - /* Check the parameters */ - assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode)); - assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode)); - assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity)); - assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity)); - assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity)); - assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate)); - assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode)); - - /* The DCMI configuration registers should be programmed correctly before - enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */ - DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE); - - /* Reset the old DCMI configuration */ - temp = DCMI->CR; - - temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL | - DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | - DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); - - /* Sets the new configuration of the DCMI peripheral */ - temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode | - DCMI_InitStruct->DCMI_SynchroMode | - DCMI_InitStruct->DCMI_PCKPolarity | - DCMI_InitStruct->DCMI_VSPolarity | - DCMI_InitStruct->DCMI_HSPolarity | - DCMI_InitStruct->DCMI_CaptureRate | - DCMI_InitStruct->DCMI_ExtendedDataMode); - - DCMI->CR = temp; -} - -/** - * @brief Fills each DCMI_InitStruct member with its default value. - * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct) -{ - /* Set the default configuration */ - DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous; - DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware; - DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; - DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low; - DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low; - DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; - DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; -} - -/** - * @brief Initializes the DCMI peripheral CROP mode according to the specified - * parameters in the DCMI_CROPInitStruct. - * @note This function should be called before to enable and start the DCMI interface. - * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that - * contains the configuration information for the DCMI peripheral CROP mode. - * @retval None - */ -void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct) -{ - /* Sets the CROP window coordinates */ - DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount | - ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16)); - - /* Sets the CROP window size */ - DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount | - ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16)); -} - -/** - * @brief Enables or disables the DCMI Crop feature. - * @note This function should be called before to enable and start the DCMI interface. - * @param NewState: new state of the DCMI Crop feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_CROPCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI Crop feature */ - DCMI->CR |= (uint32_t)DCMI_CR_CROP; - } - else - { - /* Disable the DCMI Crop feature */ - DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; - } -} - -/** - * @brief Sets the embedded synchronization codes - * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that - * contains the embedded synchronization codes for the DCMI peripheral. - * @retval None - */ -void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct) -{ - DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode | - ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)| - ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)| - ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24)); -} - -/** - * @brief Enables or disables the DCMI JPEG format. - * @note The Crop and Embedded Synchronization features cannot be used in this mode. - * @param NewState: new state of the DCMI JPEG format. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_JPEGCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI JPEG format */ - DCMI->CR |= (uint32_t)DCMI_CR_JPEG; - } - else - { - /* Disable the DCMI JPEG format */ - DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG; - } -} -/** - * @} - */ - -/** @defgroup DCMI_Group2 Image capture functions - * @brief Image capture functions - * -@verbatim - =============================================================================== - Image capture functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the DCMI interface. - * @param NewState: new state of the DCMI interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI by setting ENABLE bit */ - DCMI->CR |= (uint32_t)DCMI_CR_ENABLE; - } - else - { - /* Disable the DCMI by clearing ENABLE bit */ - DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE; - } -} - -/** - * @brief Enables or disables the DCMI Capture. - * @param NewState: new state of the DCMI capture. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_CaptureCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI Capture */ - DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE; - } - else - { - /* Disable the DCMI Capture */ - DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE; - } -} - -/** - * @brief Reads the data stored in the DR register. - * @param None - * @retval Data register value - */ -uint32_t DCMI_ReadData(void) -{ - return DCMI->DR; -} -/** - * @} - */ - -/** @defgroup DCMI_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the DCMI interface interrupts. - * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @param NewState: new state of the specified DCMI interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DCMI_CONFIG_IT(DCMI_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - DCMI->IER |= DCMI_IT; - } - else - { - /* Disable the Interrupt sources */ - DCMI->IER &= (uint16_t)(~DCMI_IT); - } -} - -/** - * @brief Checks whether the DCMI interface flag is set or not. - * @param DCMI_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask - * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask - * @arg DCMI_FLAG_LINERI: Line Raw flag mask - * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask - * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask - * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask - * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask - * @arg DCMI_FLAG_LINEMI: Line Masked flag mask - * @arg DCMI_FLAG_HSYNC: HSYNC flag mask - * @arg DCMI_FLAG_VSYNC: VSYNC flag mask - * @arg DCMI_FLAG_FNE: Fifo not empty flag mask - * @retval The new state of DCMI_FLAG (SET or RESET). - */ -FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t dcmireg, tempreg = 0; - - /* Check the parameters */ - assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG)); - - /* Get the DCMI register index */ - dcmireg = (((uint16_t)DCMI_FLAG) >> 12); - - if (dcmireg == 0x00) /* The FLAG is in RISR register */ - { - tempreg= DCMI->RISR; - } - else if (dcmireg == 0x02) /* The FLAG is in SR register */ - { - tempreg = DCMI->SR; - } - else /* The FLAG is in MISR register */ - { - tempreg = DCMI->MISR; - } - - if ((tempreg & DCMI_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the DCMI_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DCMI's pending flags. - * @param DCMI_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask - * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask - * @arg DCMI_FLAG_LINERI: Line Raw flag mask - * @retval None - */ -void DCMI_ClearFlag(uint16_t DCMI_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG)); - - /* Clear the flag by writing in the ICR register 1 in the corresponding - Flag position*/ - - DCMI->ICR = DCMI_FLAG; -} - -/** - * @brief Checks whether the DCMI interrupt has occurred or not. - * @param DCMI_IT: specifies the DCMI interrupt source to check. - * This parameter can be one of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval The new state of DCMI_IT (SET or RESET). - */ -ITStatus DCMI_GetITStatus(uint16_t DCMI_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itstatus = 0; - - /* Check the parameters */ - assert_param(IS_DCMI_GET_IT(DCMI_IT)); - - itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */ - - if ((itstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the DCMI's interrupt pending bits. - * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval None - */ -void DCMI_ClearITPendingBit(uint16_t DCMI_IT) -{ - /* Clear the interrupt pending Bit by writing in the ICR register 1 in the - corresponding pending Bit position*/ - - DCMI->ICR = DCMI_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_dcmi.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the DCMI peripheral: + * - Initialization and Configuration + * - Image capture functions + * - Interrupts and flags management + * + * @verbatim + * + * + * =================================================================== + * How to use this driver + * =================================================================== + * + * The sequence below describes how to use this driver to capture image + * from a camera module connected to the DCMI Interface. + * This sequence does not take into account the configuration of the + * camera module, which should be made before to configure and enable + * the DCMI to capture images. + * + * 1. Enable the clock for the DCMI and associated GPIOs using the following functions: + * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); + * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + * + * 2. DCMI pins configuration + * - Connect the involved DCMI pins to AF13 using the following function + * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); + * - Configure these DCMI pins in alternate function mode by calling the function + * GPIO_Init(); + * + * 3. Declare a DCMI_InitTypeDef structure, for example: + * DCMI_InitTypeDef DCMI_InitStructure; + * and fill the DCMI_InitStructure variable with the allowed values + * of the structure member. + * + * 4. Initialize the DCMI interface by calling the function + * DCMI_Init(&DCMI_InitStructure); + * + * 5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR + * register to the destination memory buffer. + * + * 6. Enable DCMI interface using the function + * DCMI_Cmd(ENABLE); + * + * 7. Start the image capture using the function + * DCMI_CaptureCmd(ENABLE); + * + * 8. At this stage the DCMI interface waits for the first start of frame, + * then a DMA request is generated continuously/once (depending on the + * mode used, Continuous/Snapshot) to transfer the received data into + * the destination memory. + * + * @note If you need to capture only a rectangular window from the received + * image, you have to use the DCMI_CROPConfig() function to configure + * the coordinates and size of the window to be captured, then enable + * the Crop feature using DCMI_CROPCmd(ENABLE); + * In this case, the Crop configuration should be made before to enable + * and start the DCMI interface. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DCMI + * @brief DCMI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DCMI_Private_Functions + * @{ + */ + +/** @defgroup DCMI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DCMI registers to their default reset values. + * @param None + * @retval None + */ +void DCMI_DeInit(void) +{ + DCMI->CR = 0x0; + DCMI->IER = 0x0; + DCMI->ICR = 0x1F; + DCMI->ESCR = 0x0; + DCMI->ESUR = 0x0; + DCMI->CWSTRTR = 0x0; + DCMI->CWSIZER = 0x0; +} + +/** + * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. + * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains + * the configuration information for the DCMI. + * @retval None + */ +void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct) +{ + uint32_t temp = 0x0; + + /* Check the parameters */ + assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode)); + assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode)); + assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity)); + assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity)); + assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity)); + assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate)); + assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode)); + + /* The DCMI configuration registers should be programmed correctly before + enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */ + DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE); + + /* Reset the old DCMI configuration */ + temp = DCMI->CR; + + temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL | + DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | + DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); + + /* Sets the new configuration of the DCMI peripheral */ + temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode | + DCMI_InitStruct->DCMI_SynchroMode | + DCMI_InitStruct->DCMI_PCKPolarity | + DCMI_InitStruct->DCMI_VSPolarity | + DCMI_InitStruct->DCMI_HSPolarity | + DCMI_InitStruct->DCMI_CaptureRate | + DCMI_InitStruct->DCMI_ExtendedDataMode); + + DCMI->CR = temp; +} + +/** + * @brief Fills each DCMI_InitStruct member with its default value. + * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct) +{ + /* Set the default configuration */ + DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous; + DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware; + DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; + DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low; + DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low; + DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; + DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; +} + +/** + * @brief Initializes the DCMI peripheral CROP mode according to the specified + * parameters in the DCMI_CROPInitStruct. + * @note This function should be called before to enable and start the DCMI interface. + * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that + * contains the configuration information for the DCMI peripheral CROP mode. + * @retval None + */ +void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct) +{ + /* Sets the CROP window coordinates */ + DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount | + ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16)); + + /* Sets the CROP window size */ + DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount | + ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16)); +} + +/** + * @brief Enables or disables the DCMI Crop feature. + * @note This function should be called before to enable and start the DCMI interface. + * @param NewState: new state of the DCMI Crop feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_CROPCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI Crop feature */ + DCMI->CR |= (uint32_t)DCMI_CR_CROP; + } + else + { + /* Disable the DCMI Crop feature */ + DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; + } +} + +/** + * @brief Sets the embedded synchronization codes + * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that + * contains the embedded synchronization codes for the DCMI peripheral. + * @retval None + */ +void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct) +{ + DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode | + ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)| + ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)| + ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24)); +} + +/** + * @brief Enables or disables the DCMI JPEG format. + * @note The Crop and Embedded Synchronization features cannot be used in this mode. + * @param NewState: new state of the DCMI JPEG format. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_JPEGCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI JPEG format */ + DCMI->CR |= (uint32_t)DCMI_CR_JPEG; + } + else + { + /* Disable the DCMI JPEG format */ + DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG; + } +} +/** + * @} + */ + +/** @defgroup DCMI_Group2 Image capture functions + * @brief Image capture functions + * +@verbatim + =============================================================================== + Image capture functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the DCMI interface. + * @param NewState: new state of the DCMI interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI by setting ENABLE bit */ + DCMI->CR |= (uint32_t)DCMI_CR_ENABLE; + } + else + { + /* Disable the DCMI by clearing ENABLE bit */ + DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE; + } +} + +/** + * @brief Enables or disables the DCMI Capture. + * @param NewState: new state of the DCMI capture. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_CaptureCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI Capture */ + DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE; + } + else + { + /* Disable the DCMI Capture */ + DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE; + } +} + +/** + * @brief Reads the data stored in the DR register. + * @param None + * @retval Data register value + */ +uint32_t DCMI_ReadData(void) +{ + return DCMI->DR; +} +/** + * @} + */ + +/** @defgroup DCMI_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the DCMI interface interrupts. + * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVF: Overflow interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @param NewState: new state of the specified DCMI interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DCMI_CONFIG_IT(DCMI_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + DCMI->IER |= DCMI_IT; + } + else + { + /* Disable the Interrupt sources */ + DCMI->IER &= (uint16_t)(~DCMI_IT); + } +} + +/** + * @brief Checks whether the DCMI interface flag is set or not. + * @param DCMI_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask + * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask + * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask + * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask + * @arg DCMI_FLAG_LINERI: Line Raw flag mask + * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask + * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask + * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask + * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask + * @arg DCMI_FLAG_LINEMI: Line Masked flag mask + * @arg DCMI_FLAG_HSYNC: HSYNC flag mask + * @arg DCMI_FLAG_VSYNC: VSYNC flag mask + * @arg DCMI_FLAG_FNE: Fifo not empty flag mask + * @retval The new state of DCMI_FLAG (SET or RESET). + */ +FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t dcmireg, tempreg = 0; + + /* Check the parameters */ + assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG)); + + /* Get the DCMI register index */ + dcmireg = (((uint16_t)DCMI_FLAG) >> 12); + + if (dcmireg == 0x00) /* The FLAG is in RISR register */ + { + tempreg= DCMI->RISR; + } + else if (dcmireg == 0x02) /* The FLAG is in SR register */ + { + tempreg = DCMI->SR; + } + else /* The FLAG is in MISR register */ + { + tempreg = DCMI->MISR; + } + + if ((tempreg & DCMI_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the DCMI_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DCMI's pending flags. + * @param DCMI_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask + * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask + * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask + * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask + * @arg DCMI_FLAG_LINERI: Line Raw flag mask + * @retval None + */ +void DCMI_ClearFlag(uint16_t DCMI_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG)); + + /* Clear the flag by writing in the ICR register 1 in the corresponding + Flag position*/ + + DCMI->ICR = DCMI_FLAG; +} + +/** + * @brief Checks whether the DCMI interrupt has occurred or not. + * @param DCMI_IT: specifies the DCMI interrupt source to check. + * This parameter can be one of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVF: Overflow interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @retval The new state of DCMI_IT (SET or RESET). + */ +ITStatus DCMI_GetITStatus(uint16_t DCMI_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itstatus = 0; + + /* Check the parameters */ + assert_param(IS_DCMI_GET_IT(DCMI_IT)); + + itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */ + + if ((itstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the DCMI's interrupt pending bits. + * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVF: Overflow interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @retval None + */ +void DCMI_ClearITPendingBit(uint16_t DCMI_IT) +{ + /* Clear the interrupt pending Bit by writing in the ICR register 1 in the + corresponding pending Bit position*/ + + DCMI->ICR = DCMI_IT; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c index 9e8ec04cf..92f9e8584 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c @@ -1,1289 +1,1289 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dma.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access controller (DMA): - * - Initialization and Configuration - * - Data Counter - * - Double Buffer mode configuration and command - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) - * function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) - * function for DMA2. - * - * 2. Enable and configure the peripheral to be connected to the DMA Stream - * (except for internal SRAM / FLASH memories: no initialization is - * necessary). - * - * 3. For a given Stream, program the required configuration through following parameters: - * Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination - * data formats, Circular or Normal mode, Stream Priority level, Source and Destination - * Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or - * Destination (if needed) using the DMA_Init() function. - * To avoid filling un-nesecessary fields, you can call DMA_StructInit() function - * to initialize a given structure with default values (reset values), the modify - * only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats). - * - * 4. Enable the NVIC and the corresponding interrupt(s) using the function - * DMA_ITConfig() if you need to use DMA interrupts. - * - * 5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring - * the second Memory address and the first Memory to be used through the function - * DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function - * DMA_DoubleBufferModeCmd(). These operations must be done before step 6. - * - * 6. Enable the DMA stream using the DMA_Cmd() function. - * - * 7. Activate the needed Stream Request using PPP_DMACmd() function for - * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) - * The function allowing this operation is provided in each PPP peripheral - * driver (ie. SPI_DMACmd for SPI peripheral). - * Once the Stream is enabled, it is not possible to modify its configuration - * unless the stream is stopped and disabled. - * After enabling the Stream, it is advised to monitor the EN bit status using - * the function DMA_GetCmdStatus(). In case of configuration errors or bus errors - * this bit will remain reset and all transfers on this Stream will remain on hold. - * - * 8. Optionally, you can configure the number of data to be transferred - * when the Stream is disabled (ie. after each Transfer Complete event - * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). - * And you can get the number of remaining data to be transferred using - * the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is - * enabled and running). - * - * 9. To control DMA events you can use one of the following - * two methods: - * a- Check on DMA Stream flags using the function DMA_GetFlagStatus(). - * b- Use DMA interrupts through the function DMA_ITConfig() at initialization - * phase and DMA_GetITStatus() function into interrupt routines in - * communication phase. - * After checking on a flag you should clear it using DMA_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using DMA_ClearITPendingBit() function. - * - * 10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify - * the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that - * the Memory Address to be modified is not the one currently in use by DMA Stream. - * This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). - * - * 11. Optionally, Pause-Resume operations may be performed: - * The DMA_Cmd() function may be used to perform Pause-Resume operation. When a - * transfer is ongoing, calling this function to disable the Stream will cause the - * transfer to be paused. All configuration registers and the number of remaining - * data will be preserved. When calling again this function to re-enable the Stream, - * the transfer will be resumed from the point where it was paused. - * - * @note Memory-to-Memory transfer is possible by setting the address of the memory into - * the Peripheral registers. In this mode, Circular mode and Double Buffer mode - * are not allowed. - * - * @note The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is - * possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set - * Half-Word data size for the peripheral to access its data register and set Word data size - * for the Memory to gain in access time. Each two Half-words will be packed and written in - * a single access to a Word in the Memory). - * - * @note When FIFO is disabled, it is not allowed to configure different Data Sizes for Source - * and Destination. In this case the Peripheral Data Size will be applied to both Source - * and Destination. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_dma.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \ - DMA_SxCR_TEIE | DMA_SxCR_DMEIE) - -#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \ - DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \ - DMA_LISR_TCIF0) - -#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6) -#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16) -#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22) -#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000) -#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C -#define HIGH_ISR_MASK (uint32_t)0x20000000 -#define RESERVED_MASK (uint32_t)0x0F7D0F7D - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** @defgroup DMA_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This subsection provides functions allowing to initialize the DMA Stream source - and destination addresses, incrementation and data sizes, transfer direction, - buffer size, circular/normal mode selection, memory-to-memory mode selection - and Stream priority value. - - The DMA_Init() function follows the DMA configuration procedures as described in - reference manual (RM0033) except the first point: waiting on EN bit to be reset. - This condition should be checked by user application using the function DMA_GetCmdStatus() - before calling the DMA_Init() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the DMAy Streamx registers to their default reset values. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval None - */ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Disable the selected DMAy Streamx */ - DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN); - - /* Reset DMAy Streamx control register */ - DMAy_Streamx->CR = 0; - - /* Reset DMAy Streamx Number of Data to Transfer register */ - DMAy_Streamx->NDTR = 0; - - /* Reset DMAy Streamx peripheral address register */ - DMAy_Streamx->PAR = 0; - - /* Reset DMAy Streamx memory 0 address register */ - DMAy_Streamx->M0AR = 0; - - /* Reset DMAy Streamx memory 1 address register */ - DMAy_Streamx->M1AR = 0; - - /* Reset DMAy Streamx FIFO control register */ - DMAy_Streamx->FCR = (uint32_t)0x00000021; - - /* Reset interrupt pending bits for the selected stream */ - if (DMAy_Streamx == DMA1_Stream0) - { - /* Reset interrupt pending bits for DMA1 Stream0 */ - DMA1->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream1) - { - /* Reset interrupt pending bits for DMA1 Stream1 */ - DMA1->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream2) - { - /* Reset interrupt pending bits for DMA1 Stream2 */ - DMA1->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream3) - { - /* Reset interrupt pending bits for DMA1 Stream3 */ - DMA1->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream4) - { - /* Reset interrupt pending bits for DMA1 Stream4 */ - DMA1->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream5) - { - /* Reset interrupt pending bits for DMA1 Stream5 */ - DMA1->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream6) - { - /* Reset interrupt pending bits for DMA1 Stream6 */ - DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream7) - { - /* Reset interrupt pending bits for DMA1 Stream7 */ - DMA1->HIFCR = DMA_Stream7_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream0) - { - /* Reset interrupt pending bits for DMA2 Stream0 */ - DMA2->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream1) - { - /* Reset interrupt pending bits for DMA2 Stream1 */ - DMA2->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream2) - { - /* Reset interrupt pending bits for DMA2 Stream2 */ - DMA2->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream3) - { - /* Reset interrupt pending bits for DMA2 Stream3 */ - DMA2->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream4) - { - /* Reset interrupt pending bits for DMA2 Stream4 */ - DMA2->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream5) - { - /* Reset interrupt pending bits for DMA2 Stream5 */ - DMA2->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream6) - { - /* Reset interrupt pending bits for DMA2 Stream6 */ - DMA2->HIFCR = DMA_Stream6_IT_MASK; - } - else - { - if (DMAy_Streamx == DMA2_Stream7) - { - /* Reset interrupt pending bits for DMA2 Stream7 */ - DMA2->HIFCR = DMA_Stream7_IT_MASK; - } - } -} - -/** - * @brief Initializes the DMAy Streamx according to the specified parameters in - * the DMA_InitStruct structure. - * @note Before calling this function, it is recommended to check that the Stream - * is actually disabled using the function DMA_GetCmdStatus(). - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel)); - assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode)); - assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold)); - assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst)); - assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst)); - - /*------------------------- DMAy Streamx CR Configuration ------------------*/ - /* Get the DMAy_Streamx CR value */ - tmpreg = DMAy_Streamx->CR; - - /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ - DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ - DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ - DMA_SxCR_DIR)); - - /* Configure DMAy Streamx: */ - /* Set CHSEL bits according to DMA_CHSEL value */ - /* Set DIR bits according to DMA_DIR value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PL bits according to DMA_Priority value */ - /* Set MBURST bits according to DMA_MemoryBurst value */ - /* Set PBURST bits according to DMA_PeripheralBurst value */ - tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority | - DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst; - - /* Write to DMAy Streamx CR register */ - DMAy_Streamx->CR = tmpreg; - - /*------------------------- DMAy Streamx FCR Configuration -----------------*/ - /* Get the DMAy_Streamx FCR value */ - tmpreg = DMAy_Streamx->FCR; - - /* Clear DMDIS and FTH bits */ - tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); - - /* Configure DMAy Streamx FIFO: - Set DMDIS bits according to DMA_FIFOMode value - Set FTH bits according to DMA_FIFOThreshold value */ - tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold; - - /* Write to DMAy Streamx CR */ - DMAy_Streamx->FCR = tmpreg; - - /*------------------------- DMAy Streamx NDTR Configuration ----------------*/ - /* Write to DMAy Streamx NDTR register */ - DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize; - - /*------------------------- DMAy Streamx PAR Configuration -----------------*/ - /* Write to DMAy Streamx PAR */ - DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - - /*------------------------- DMAy Streamx M0AR Configuration ----------------*/ - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ - /*-------------- Reset DMA init structure parameters values ----------------*/ - /* Initialize the DMA_Channel member */ - DMA_InitStruct->DMA_Channel = 0; - - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - - /* Initialize the DMA_Memory0BaseAddr member */ - DMA_InitStruct->DMA_Memory0BaseAddr = 0; - - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - - /* Initialize the DMA_FIFOMode member */ - DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable; - - /* Initialize the DMA_FIFOThreshold member */ - DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; - - /* Initialize the DMA_MemoryBurst member */ - DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single; - - /* Initialize the DMA_PeripheralBurst member */ - DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single; -} - -/** - * @brief Enables or disables the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx. - * This parameter can be: ENABLE or DISABLE. - * - * @note This function may be used to perform Pause-Resume operation. When a - * transfer is ongoing, calling this function to disable the Stream will - * cause the transfer to be paused. All configuration registers and the - * number of remaining data will be preserved. When calling again this - * function to re-enable the Stream, the transfer will be resumed from - * the point where it was paused. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling the - * stream, it is recommended to check (or wait until) the DMA Stream is - * effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer of - * this single data is finished. - * - * @retval None - */ -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Streamx by setting EN bit */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN; - } - else - { - /* Disable the selected DMAy Streamx by clearing EN bit */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN; - } -} - -/** - * @brief Configures, when the PINC (Peripheral Increment address mode) bit is - * set, if the peripheral address should be incremented with the data - * size (configured with PSIZE bits) or by a fixed offset equal to 4 - * (32-bit aligned addresses). - * - * @note This function has no effect if the Peripheral Increment mode is disabled. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_Pincos: specifies the Peripheral increment offset size. - * This parameter can be one of the following values: - * @arg DMA_PINCOS_Psize: Peripheral address increment is done - * accordingly to PSIZE parameter. - * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is - * fixed to 4 (32-bit aligned addresses). - * @retval None - */ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos)); - - /* Check the needed Peripheral increment offset */ - if(DMA_Pincos != DMA_PINCOS_Psize) - { - /* Configure DMA_SxCR_PINCOS bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; - } - else - { - /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; - } -} - -/** - * @brief Configures, when the DMAy Streamx is disabled, the flow controller for - * the next transactions (Peripheral or Memory). - * - * @note Before enabling this feature, check if the used peripheral supports - * the Flow Controller mode or not. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FlowCtrl: specifies the DMA flow controller. - * This parameter can be one of the following values: - * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is - * the DMA controller. - * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller - * is the peripheral. - * @retval None - */ -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl)); - - /* Check the needed flow controller */ - if(DMA_FlowCtrl != DMA_FlowCtrl_Memory) - { - /* Configure DMA_SxCR_PFCTRL bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; - } - else - { - /* Clear the PFCTRL bit: Memory is the flow controller */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; - } -} -/** - * @} - */ - -/** @defgroup DMA_Group2 Data Counter functions - * @brief Data Counter functions - * -@verbatim - =============================================================================== - Data Counter functions - =============================================================================== - - This subsection provides function allowing to configure and read the buffer size - (number of data to be transferred). - - The DMA data counter can be written only when the DMA Stream is disabled - (ie. after transfer complete event). - - The following function can be used to write the Stream data counter value: - - void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); - -@note It is advised to use this function rather than DMA_Init() in situations where - only the Data buffer needs to be reloaded. - -@note If the Source and Destination Data Sizes are different, then the value written in - data counter, expressing the number of transfers, is relative to the number of - transfers from the Peripheral point of view. - ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value - to be configured in the data counter is the number of Half-Words to be transferred - from/to the peripheral. - - The DMA data counter can be read to indicate the number of remaining transfers for - the relative DMA Stream. This counter is decremented at the end of each data - transfer and when the transfer is complete: - - If Normal mode is selected: the counter is set to 0. - - If Circular mode is selected: the counter is reloaded with the initial value - (configured before enabling the DMA Stream) - - The following function can be used to read the Stream data counter value: - - uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -@endverbatim - * @{ - */ - -/** - * @brief Writes the number of data units to be transferred on the DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Counter: Number of data units to be transferred (from 0 to 65535) - * Number of data items depends only on the Peripheral data format. - * - * @note If Peripheral data format is Bytes: number of data units is equal - * to total number of bytes to be transferred. - * - * @note If Peripheral data format is Half-Word: number of data units is - * equal to total number of bytes to be transferred / 2. - * - * @note If Peripheral data format is Word: number of data units is equal - * to total number of bytes to be transferred / 4. - * - * @note In Memory-to-Memory transfer mode, the memory buffer pointed by - * DMAy_SxPAR register is considered as Peripheral. - * - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Write the number of data units to be transferred */ - DMAy_Streamx->NDTR = (uint16_t)Counter; -} - -/** - * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Return the number of remaining data units for DMAy Streamx */ - return ((uint16_t)(DMAy_Streamx->NDTR)); -} -/** - * @} - */ - -/** @defgroup DMA_Group3 Double Buffer mode functions - * @brief Double Buffer mode functions - * -@verbatim - =============================================================================== - Double Buffer mode functions - =============================================================================== - - This subsection provides function allowing to configure and control the double - buffer mode parameters. - - The Double Buffer mode can be used only when Circular mode is enabled. - The Double Buffer mode cannot be used when transferring data from Memory to Memory. - - The Double Buffer mode allows to set two different Memory addresses from/to which - the DMA controller will access alternatively (after completing transfer to/from target - memory 0, it will start transfer to/from target memory 1). - This allows to reduce software overhead for double buffering and reduce the CPU - access time. - - Two functions must be called before calling the DMA_Init() function: - - void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory); - - void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - - DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first - Memory target from/to which the transfer will start after enabling the DMA Stream. - Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable - it when it should not be used). - - - Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is - stopped) to modify on of the target Memories addresses or to check wich Memory target is currently - used: - - void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget); - - uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - - DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories. - The Memory of which the base address will be modified must not be currently be used by the DMA Stream - (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address - of target Memory 0 and vice versa). - To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which - returns the index of the Memory target currently in use by the DMA Stream. - -@endverbatim - * @{ - */ - -/** - * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode - * and the current memory target. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) - * @param DMA_CurrentMemory: specifies which memory will be first buffer for - * the transactions when the Stream will be enabled. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: Memory 0 is the current buffer. - * @arg DMA_Memory_1: Memory 1 is the current buffer. - * - * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init(). - * - * @retval None - */ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory)); - - if (DMA_CurrentMemory != DMA_Memory_0) - { - /* Set Memory 1 as current memory address */ - DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); - } - else - { - /* Set Memory 0 as current memory address */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); - } - - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = Memory1BaseAddr; -} - -/** - * @brief Enables or disables the double buffer mode for the selected DMA stream. - * @note This function can be called only when the DMA Stream is disabled. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx double buffer mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Configure the Double Buffer mode */ - if (NewState != DISABLE) - { - /* Enable the Double buffer mode */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM; - } - else - { - /* Disable the Double buffer mode */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM; - } -} - -/** - * @brief Configures the Memory address for the next buffer transfer in double - * buffer mode (for dynamic use). This function can be called when the - * DMA Stream is enabled and when the transfer is ongoing. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param MemoryBaseAddr: The base address of the target memory buffer - * @param DMA_MemoryTarget: Next memory target to be used. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: To use the memory address 0 - * @arg DMA_Memory_1: To use the memory address 1 - * - * @note It is not allowed to modify the Base Address of a target Memory when - * this target is involved in the current transfer. ie. If the DMA Stream - * is currently transferring to/from Memory 1, then it not possible to - * modify Base address of Memory 1, but it is possible to modify Base - * address of Memory 0. - * To know which Memory is currently used, you can use the function - * DMA_GetCurrentMemoryTarget(). - * - * @retval None - */ -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget)); - - /* Check the Memory target to be configured */ - if (DMA_MemoryTarget != DMA_Memory_0) - { - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = MemoryBaseAddr; - } - else - { - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = MemoryBaseAddr; - } -} - -/** - * @brief Returns the current memory target used by double buffer transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The memory target number: 0 for Memory0 or 1 for Memory1. - */ -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the current memory target */ - if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0) - { - /* Current memory buffer used is Memory 1 */ - tmp = 1; - } - else - { - /* Current memory buffer used is Memory 0 */ - tmp = 0; - } - return tmp; -} -/** - * @} - */ - -/** @defgroup DMA_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This subsection provides functions allowing to - - Check the DMA enable status - - Check the FIFO status - - Configure the DMA Interrupts sources and check or clear the flags or pending bits status. - - 1. DMA Enable status: - After configuring the DMA Stream (DMA_Init() function) and enabling the stream, - it is recommended to check (or wait until) the DMA Stream is effectively enabled. - A Stream may remain disabled if a configuration parameter is wrong. - After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA - Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, - the current data will be transferred and the Stream will be effectively disabled only after - this data transfer completion. - To monitor this state it is possible to use the following function: - - FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - 2. FIFO Status: - It is possible to monitor the FIFO status when a transfer is ongoing using the following - function: - - uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - 3. DMA Interrupts and Flags: - The user should identify which mode will be used in his application to manage the - DMA controller events: Polling mode or Interrupt mode. - - Polling Mode - ============= - Each DMA stream can be managed through 4 event Flags: - (x : DMA Stream number ) - 1. DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. - 2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. - 3. DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. - 4. DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. - 5. DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . - - In this Mode it is advised to use the following functions: - - FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - - void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - - Interrupt Mode - =============== - Each DMA Stream can be managed through 4 Interrupts: - - Interrupt Source - ---------------- - 1. DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. - 2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. - 3. DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. - 4. DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. - 5. DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. - - In this Mode it is advised to use the following functions: - - void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); - - ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - - void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -@endverbatim - * @{ - */ - -/** - * @brief Returns the status of EN bit for the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling - * the stream, it is recommended to check (or wait until) the DMA Stream - * is effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer - * of this single data is finished. - * - * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). - */ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - FunctionalState state = DISABLE; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0) - { - /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */ - state = ENABLE; - } - else - { - /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - state = DISABLE; - } - return state; -} - -/** - * @brief Returns the current DMAy Streamx FIFO filled level. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The FIFO filling state. - * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full - * and not empty. - * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. - * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. - * - DMA_FIFOStatus_Empty: when FIFO is empty - * - DMA_FIFOStatus_Full: when FIFO is full - */ -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the FIFO level bits */ - tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS)); - - return tmpreg; -} - -/** - * @brief Checks whether the specified DMAy Streamx flag is set or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the flag is in HISR or LISR */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR; - } - - /* Mask the reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA flag */ - if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) - { - /* DMA_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMA_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMA_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's pending flags. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear flag bits */ - DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear flag bits */ - DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } -} - -/** - * @brief Enables or disables the specified DMAy Streamx interrupts. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @arg DMA_IT_FE: FIFO error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Check if the DMA_IT parameter contains a FIFO interrupt */ - if ((DMA_IT & DMA_IT_FE) != 0) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE; - } - else - { - /* Disable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; - } - } - - /* Check if the DMA_IT parameter contains a Transfer interrupt */ - if (DMA_IT != DMA_IT_FE) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA transfer interrupts */ - DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - else - { - /* Disable the selected DMA transfer interrupts */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - } -} - -/** - * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - ITStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the interrupt enable bit is in the CR or FCR register */ - if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET) - { - /* Get the interrupt enable position mask in CR register */ - tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); - - /* Check the enable bit in CR register */ - enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg); - } - else - { - /* Check the enable bit in FCR register */ - enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); - } - - /* Check if the interrupt pending flag is in LISR or HISR */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR ; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR ; - } - - /* mask all reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA interrupt */ - if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* DMA_IT is set */ - bitstatus = SET; - } - else - { - /* DMA_IT is reset */ - bitstatus = RESET; - } - - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's interrupt pending bits. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear interrupt bits */ - DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear interrupt bits */ - DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_dma.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access controller (DMA): + * - Initialization and Configuration + * - Data Counter + * - Double Buffer mode configuration and command + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) + * function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) + * function for DMA2. + * + * 2. Enable and configure the peripheral to be connected to the DMA Stream + * (except for internal SRAM / FLASH memories: no initialization is + * necessary). + * + * 3. For a given Stream, program the required configuration through following parameters: + * Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination + * data formats, Circular or Normal mode, Stream Priority level, Source and Destination + * Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or + * Destination (if needed) using the DMA_Init() function. + * To avoid filling un-nesecessary fields, you can call DMA_StructInit() function + * to initialize a given structure with default values (reset values), the modify + * only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats). + * + * 4. Enable the NVIC and the corresponding interrupt(s) using the function + * DMA_ITConfig() if you need to use DMA interrupts. + * + * 5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring + * the second Memory address and the first Memory to be used through the function + * DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function + * DMA_DoubleBufferModeCmd(). These operations must be done before step 6. + * + * 6. Enable the DMA stream using the DMA_Cmd() function. + * + * 7. Activate the needed Stream Request using PPP_DMACmd() function for + * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) + * The function allowing this operation is provided in each PPP peripheral + * driver (ie. SPI_DMACmd for SPI peripheral). + * Once the Stream is enabled, it is not possible to modify its configuration + * unless the stream is stopped and disabled. + * After enabling the Stream, it is advised to monitor the EN bit status using + * the function DMA_GetCmdStatus(). In case of configuration errors or bus errors + * this bit will remain reset and all transfers on this Stream will remain on hold. + * + * 8. Optionally, you can configure the number of data to be transferred + * when the Stream is disabled (ie. after each Transfer Complete event + * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). + * And you can get the number of remaining data to be transferred using + * the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is + * enabled and running). + * + * 9. To control DMA events you can use one of the following + * two methods: + * a- Check on DMA Stream flags using the function DMA_GetFlagStatus(). + * b- Use DMA interrupts through the function DMA_ITConfig() at initialization + * phase and DMA_GetITStatus() function into interrupt routines in + * communication phase. + * After checking on a flag you should clear it using DMA_ClearFlag() + * function. And after checking on an interrupt event you should + * clear it using DMA_ClearITPendingBit() function. + * + * 10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify + * the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that + * the Memory Address to be modified is not the one currently in use by DMA Stream. + * This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). + * + * 11. Optionally, Pause-Resume operations may be performed: + * The DMA_Cmd() function may be used to perform Pause-Resume operation. When a + * transfer is ongoing, calling this function to disable the Stream will cause the + * transfer to be paused. All configuration registers and the number of remaining + * data will be preserved. When calling again this function to re-enable the Stream, + * the transfer will be resumed from the point where it was paused. + * + * @note Memory-to-Memory transfer is possible by setting the address of the memory into + * the Peripheral registers. In this mode, Circular mode and Double Buffer mode + * are not allowed. + * + * @note The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + * possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + * Half-Word data size for the peripheral to access its data register and set Word data size + * for the Memory to gain in access time. Each two Half-words will be packed and written in + * a single access to a Word in the Memory). + * + * @note When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + * and Destination. In this case the Peripheral Data Size will be applied to both Source + * and Destination. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_dma.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Masks Definition */ +#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \ + DMA_SxCR_TEIE | DMA_SxCR_DMEIE) + +#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \ + DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \ + DMA_LISR_TCIF0) + +#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6) +#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16) +#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22) +#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000) +#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000) +#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000) +#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000) +#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C +#define HIGH_ISR_MASK (uint32_t)0x20000000 +#define RESERVED_MASK (uint32_t)0x0F7D0F7D + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** @defgroup DMA_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + + This subsection provides functions allowing to initialize the DMA Stream source + and destination addresses, incrementation and data sizes, transfer direction, + buffer size, circular/normal mode selection, memory-to-memory mode selection + and Stream priority value. + + The DMA_Init() function follows the DMA configuration procedures as described in + reference manual (RM0033) except the first point: waiting on EN bit to be reset. + This condition should be checked by user application using the function DMA_GetCmdStatus() + before calling the DMA_Init() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the DMAy Streamx registers to their default reset values. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval None + */ +void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Disable the selected DMAy Streamx */ + DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN); + + /* Reset DMAy Streamx control register */ + DMAy_Streamx->CR = 0; + + /* Reset DMAy Streamx Number of Data to Transfer register */ + DMAy_Streamx->NDTR = 0; + + /* Reset DMAy Streamx peripheral address register */ + DMAy_Streamx->PAR = 0; + + /* Reset DMAy Streamx memory 0 address register */ + DMAy_Streamx->M0AR = 0; + + /* Reset DMAy Streamx memory 1 address register */ + DMAy_Streamx->M1AR = 0; + + /* Reset DMAy Streamx FIFO control register */ + DMAy_Streamx->FCR = (uint32_t)0x00000021; + + /* Reset interrupt pending bits for the selected stream */ + if (DMAy_Streamx == DMA1_Stream0) + { + /* Reset interrupt pending bits for DMA1 Stream0 */ + DMA1->LIFCR = DMA_Stream0_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream1) + { + /* Reset interrupt pending bits for DMA1 Stream1 */ + DMA1->LIFCR = DMA_Stream1_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream2) + { + /* Reset interrupt pending bits for DMA1 Stream2 */ + DMA1->LIFCR = DMA_Stream2_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream3) + { + /* Reset interrupt pending bits for DMA1 Stream3 */ + DMA1->LIFCR = DMA_Stream3_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream4) + { + /* Reset interrupt pending bits for DMA1 Stream4 */ + DMA1->HIFCR = DMA_Stream4_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream5) + { + /* Reset interrupt pending bits for DMA1 Stream5 */ + DMA1->HIFCR = DMA_Stream5_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream6) + { + /* Reset interrupt pending bits for DMA1 Stream6 */ + DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream7) + { + /* Reset interrupt pending bits for DMA1 Stream7 */ + DMA1->HIFCR = DMA_Stream7_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream0) + { + /* Reset interrupt pending bits for DMA2 Stream0 */ + DMA2->LIFCR = DMA_Stream0_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream1) + { + /* Reset interrupt pending bits for DMA2 Stream1 */ + DMA2->LIFCR = DMA_Stream1_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream2) + { + /* Reset interrupt pending bits for DMA2 Stream2 */ + DMA2->LIFCR = DMA_Stream2_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream3) + { + /* Reset interrupt pending bits for DMA2 Stream3 */ + DMA2->LIFCR = DMA_Stream3_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream4) + { + /* Reset interrupt pending bits for DMA2 Stream4 */ + DMA2->HIFCR = DMA_Stream4_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream5) + { + /* Reset interrupt pending bits for DMA2 Stream5 */ + DMA2->HIFCR = DMA_Stream5_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream6) + { + /* Reset interrupt pending bits for DMA2 Stream6 */ + DMA2->HIFCR = DMA_Stream6_IT_MASK; + } + else + { + if (DMAy_Streamx == DMA2_Stream7) + { + /* Reset interrupt pending bits for DMA2 Stream7 */ + DMA2->HIFCR = DMA_Stream7_IT_MASK; + } + } +} + +/** + * @brief Initializes the DMAy Streamx according to the specified parameters in + * the DMA_InitStruct structure. + * @note Before calling this function, it is recommended to check that the Stream + * is actually disabled using the function DMA_GetCmdStatus(). + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel)); + assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode)); + assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst)); + + /*------------------------- DMAy Streamx CR Configuration ------------------*/ + /* Get the DMAy_Streamx CR value */ + tmpreg = DMAy_Streamx->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR)); + + /* Configure DMAy Streamx: */ + /* Set CHSEL bits according to DMA_CHSEL value */ + /* Set DIR bits according to DMA_DIR value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PL bits according to DMA_Priority value */ + /* Set MBURST bits according to DMA_MemoryBurst value */ + /* Set PBURST bits according to DMA_PeripheralBurst value */ + tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority | + DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst; + + /* Write to DMAy Streamx CR register */ + DMAy_Streamx->CR = tmpreg; + + /*------------------------- DMAy Streamx FCR Configuration -----------------*/ + /* Get the DMAy_Streamx FCR value */ + tmpreg = DMAy_Streamx->FCR; + + /* Clear DMDIS and FTH bits */ + tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Configure DMAy Streamx FIFO: + Set DMDIS bits according to DMA_FIFOMode value + Set FTH bits according to DMA_FIFOThreshold value */ + tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold; + + /* Write to DMAy Streamx CR */ + DMAy_Streamx->FCR = tmpreg; + + /*------------------------- DMAy Streamx NDTR Configuration ----------------*/ + /* Write to DMAy Streamx NDTR register */ + DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize; + + /*------------------------- DMAy Streamx PAR Configuration -----------------*/ + /* Write to DMAy Streamx PAR */ + DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + + /*------------------------- DMAy Streamx M0AR Configuration ----------------*/ + /* Write to DMAy Streamx M0AR */ + DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ + /*-------------- Reset DMA init structure parameters values ----------------*/ + /* Initialize the DMA_Channel member */ + DMA_InitStruct->DMA_Channel = 0; + + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + + /* Initialize the DMA_Memory0BaseAddr member */ + DMA_InitStruct->DMA_Memory0BaseAddr = 0; + + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory; + + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + + /* Initialize the DMA_FIFOMode member */ + DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable; + + /* Initialize the DMA_FIFOThreshold member */ + DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; + + /* Initialize the DMA_MemoryBurst member */ + DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single; + + /* Initialize the DMA_PeripheralBurst member */ + DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single; +} + +/** + * @brief Enables or disables the specified DMAy Streamx. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param NewState: new state of the DMAy Streamx. + * This parameter can be: ENABLE or DISABLE. + * + * @note This function may be used to perform Pause-Resume operation. When a + * transfer is ongoing, calling this function to disable the Stream will + * cause the transfer to be paused. All configuration registers and the + * number of remaining data will be preserved. When calling again this + * function to re-enable the Stream, the transfer will be resumed from + * the point where it was paused. + * + * @note After configuring the DMA Stream (DMA_Init() function) and enabling the + * stream, it is recommended to check (or wait until) the DMA Stream is + * effectively enabled. A Stream may remain disabled if a configuration + * parameter is wrong. + * After disabling a DMA Stream, it is also recommended to check (or wait + * until) the DMA Stream is effectively disabled. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * + * @retval None + */ +void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Streamx by setting EN bit */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN; + } + else + { + /* Disable the selected DMAy Streamx by clearing EN bit */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN; + } +} + +/** + * @brief Configures, when the PINC (Peripheral Increment address mode) bit is + * set, if the peripheral address should be incremented with the data + * size (configured with PSIZE bits) or by a fixed offset equal to 4 + * (32-bit aligned addresses). + * + * @note This function has no effect if the Peripheral Increment mode is disabled. + * + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_Pincos: specifies the Peripheral increment offset size. + * This parameter can be one of the following values: + * @arg DMA_PINCOS_Psize: Peripheral address increment is done + * accordingly to PSIZE parameter. + * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is + * fixed to 4 (32-bit aligned addresses). + * @retval None + */ +void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos)); + + /* Check the needed Peripheral increment offset */ + if(DMA_Pincos != DMA_PINCOS_Psize) + { + /* Configure DMA_SxCR_PINCOS bit with the input parameter */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; + } + else + { + /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; + } +} + +/** + * @brief Configures, when the DMAy Streamx is disabled, the flow controller for + * the next transactions (Peripheral or Memory). + * + * @note Before enabling this feature, check if the used peripheral supports + * the Flow Controller mode or not. + * + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_FlowCtrl: specifies the DMA flow controller. + * This parameter can be one of the following values: + * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is + * the DMA controller. + * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller + * is the peripheral. + * @retval None + */ +void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl)); + + /* Check the needed flow controller */ + if(DMA_FlowCtrl != DMA_FlowCtrl_Memory) + { + /* Configure DMA_SxCR_PFCTRL bit with the input parameter */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; + } + else + { + /* Clear the PFCTRL bit: Memory is the flow controller */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; + } +} +/** + * @} + */ + +/** @defgroup DMA_Group2 Data Counter functions + * @brief Data Counter functions + * +@verbatim + =============================================================================== + Data Counter functions + =============================================================================== + + This subsection provides function allowing to configure and read the buffer size + (number of data to be transferred). + + The DMA data counter can be written only when the DMA Stream is disabled + (ie. after transfer complete event). + + The following function can be used to write the Stream data counter value: + - void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); + +@note It is advised to use this function rather than DMA_Init() in situations where + only the Data buffer needs to be reloaded. + +@note If the Source and Destination Data Sizes are different, then the value written in + data counter, expressing the number of transfers, is relative to the number of + transfers from the Peripheral point of view. + ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value + to be configured in the data counter is the number of Half-Words to be transferred + from/to the peripheral. + + The DMA data counter can be read to indicate the number of remaining transfers for + the relative DMA Stream. This counter is decremented at the end of each data + transfer and when the transfer is complete: + - If Normal mode is selected: the counter is set to 0. + - If Circular mode is selected: the counter is reloaded with the initial value + (configured before enabling the DMA Stream) + + The following function can be used to read the Stream data counter value: + - uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); + +@endverbatim + * @{ + */ + +/** + * @brief Writes the number of data units to be transferred on the DMAy Streamx. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param Counter: Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @note In Memory-to-Memory transfer mode, the memory buffer pointed by + * DMAy_SxPAR register is considered as Peripheral. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Write the number of data units to be transferred */ + DMAy_Streamx->NDTR = (uint16_t)Counter; +} + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Return the number of remaining data units for DMAy Streamx */ + return ((uint16_t)(DMAy_Streamx->NDTR)); +} +/** + * @} + */ + +/** @defgroup DMA_Group3 Double Buffer mode functions + * @brief Double Buffer mode functions + * +@verbatim + =============================================================================== + Double Buffer mode functions + =============================================================================== + + This subsection provides function allowing to configure and control the double + buffer mode parameters. + + The Double Buffer mode can be used only when Circular mode is enabled. + The Double Buffer mode cannot be used when transferring data from Memory to Memory. + + The Double Buffer mode allows to set two different Memory addresses from/to which + the DMA controller will access alternatively (after completing transfer to/from target + memory 0, it will start transfer to/from target memory 1). + This allows to reduce software overhead for double buffering and reduce the CPU + access time. + + Two functions must be called before calling the DMA_Init() function: + - void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, + uint32_t DMA_CurrentMemory); + - void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); + + DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first + Memory target from/to which the transfer will start after enabling the DMA Stream. + Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable + it when it should not be used). + + + Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is + stopped) to modify on of the target Memories addresses or to check wich Memory target is currently + used: + - void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, + uint32_t DMA_MemoryTarget); + - uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); + + DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories. + The Memory of which the base address will be modified must not be currently be used by the DMA Stream + (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address + of target Memory 0 and vice versa). + To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which + returns the index of the Memory target currently in use by the DMA Stream. + +@endverbatim + * @{ + */ + +/** + * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode + * and the current memory target. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) + * @param DMA_CurrentMemory: specifies which memory will be first buffer for + * the transactions when the Stream will be enabled. + * This parameter can be one of the following values: + * @arg DMA_Memory_0: Memory 0 is the current buffer. + * @arg DMA_Memory_1: Memory 1 is the current buffer. + * + * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init(). + * + * @retval None + */ +void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, + uint32_t DMA_CurrentMemory) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory)); + + if (DMA_CurrentMemory != DMA_Memory_0) + { + /* Set Memory 1 as current memory address */ + DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); + } + else + { + /* Set Memory 0 as current memory address */ + DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); + } + + /* Write to DMAy Streamx M1AR */ + DMAy_Streamx->M1AR = Memory1BaseAddr; +} + +/** + * @brief Enables or disables the double buffer mode for the selected DMA stream. + * @note This function can be called only when the DMA Stream is disabled. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param NewState: new state of the DMAy Streamx double buffer mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Configure the Double Buffer mode */ + if (NewState != DISABLE) + { + /* Enable the Double buffer mode */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM; + } + else + { + /* Disable the Double buffer mode */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM; + } +} + +/** + * @brief Configures the Memory address for the next buffer transfer in double + * buffer mode (for dynamic use). This function can be called when the + * DMA Stream is enabled and when the transfer is ongoing. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param MemoryBaseAddr: The base address of the target memory buffer + * @param DMA_MemoryTarget: Next memory target to be used. + * This parameter can be one of the following values: + * @arg DMA_Memory_0: To use the memory address 0 + * @arg DMA_Memory_1: To use the memory address 1 + * + * @note It is not allowed to modify the Base Address of a target Memory when + * this target is involved in the current transfer. ie. If the DMA Stream + * is currently transferring to/from Memory 1, then it not possible to + * modify Base address of Memory 1, but it is possible to modify Base + * address of Memory 0. + * To know which Memory is currently used, you can use the function + * DMA_GetCurrentMemoryTarget(). + * + * @retval None + */ +void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, + uint32_t DMA_MemoryTarget) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget)); + + /* Check the Memory target to be configured */ + if (DMA_MemoryTarget != DMA_Memory_0) + { + /* Write to DMAy Streamx M1AR */ + DMAy_Streamx->M1AR = MemoryBaseAddr; + } + else + { + /* Write to DMAy Streamx M0AR */ + DMAy_Streamx->M0AR = MemoryBaseAddr; + } +} + +/** + * @brief Returns the current memory target used by double buffer transfer. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval The memory target number: 0 for Memory0 or 1 for Memory1. + */ +uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Get the current memory target */ + if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0) + { + /* Current memory buffer used is Memory 1 */ + tmp = 1; + } + else + { + /* Current memory buffer used is Memory 0 */ + tmp = 0; + } + return tmp; +} +/** + * @} + */ + +/** @defgroup DMA_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This subsection provides functions allowing to + - Check the DMA enable status + - Check the FIFO status + - Configure the DMA Interrupts sources and check or clear the flags or pending bits status. + + 1. DMA Enable status: + After configuring the DMA Stream (DMA_Init() function) and enabling the stream, + it is recommended to check (or wait until) the DMA Stream is effectively enabled. + A Stream may remain disabled if a configuration parameter is wrong. + After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA + Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, + the current data will be transferred and the Stream will be effectively disabled only after + this data transfer completion. + To monitor this state it is possible to use the following function: + - FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); + + 2. FIFO Status: + It is possible to monitor the FIFO status when a transfer is ongoing using the following + function: + - uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); + + 3. DMA Interrupts and Flags: + The user should identify which mode will be used in his application to manage the + DMA controller events: Polling mode or Interrupt mode. + + Polling Mode + ============= + Each DMA stream can be managed through 4 event Flags: + (x : DMA Stream number ) + 1. DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. + 2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. + 3. DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. + 4. DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. + 5. DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . + + In this Mode it is advised to use the following functions: + - FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); + - void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); + + Interrupt Mode + =============== + Each DMA Stream can be managed through 4 Interrupts: + + Interrupt Source + ---------------- + 1. DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. + 2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. + 3. DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. + 4. DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. + 5. DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. + + In this Mode it is advised to use the following functions: + - void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); + - ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); + - void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); + +@endverbatim + * @{ + */ + +/** + * @brief Returns the status of EN bit for the specified DMAy Streamx. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * + * @note After configuring the DMA Stream (DMA_Init() function) and enabling + * the stream, it is recommended to check (or wait until) the DMA Stream + * is effectively enabled. A Stream may remain disabled if a configuration + * parameter is wrong. + * After disabling a DMA Stream, it is also recommended to check (or wait + * until) the DMA Stream is effectively disabled. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer + * of this single data is finished. + * + * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). + */ +FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx) +{ + FunctionalState state = DISABLE; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0) + { + /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */ + state = ENABLE; + } + else + { + /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + state = DISABLE; + } + return state; +} + +/** + * @brief Returns the current DMAy Streamx FIFO filled level. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Get the FIFO level bits */ + tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS)); + + return tmpreg; +} + +/** + * @brief Checks whether the specified DMAy Streamx flag is set or not. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag + * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag + * @arg DMA_FLAG_TEIFx: Streamx transfer error flag + * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag + * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag + * Where x can be 0 to 7 to select the DMA Stream. + * @retval The new state of DMA_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + DMA_TypeDef* DMAy; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if the flag is in HISR or LISR */ + if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Get DMAy HISR register value */ + tmpreg = DMAy->HISR; + } + else + { + /* Get DMAy LISR register value */ + tmpreg = DMAy->LISR; + } + + /* Mask the reserved bits */ + tmpreg &= (uint32_t)RESERVED_MASK; + + /* Check the status of the specified DMA flag */ + if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Streamx's pending flags. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag + * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag + * @arg DMA_FLAG_TEIFx: Streamx transfer error flag + * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag + * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag + * Where x can be 0 to 7 to select the DMA Stream. + * @retval None + */ +void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) +{ + DMA_TypeDef* DMAy; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if LIFCR or HIFCR register is targeted */ + if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Set DMAy HIFCR register clear flag bits */ + DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); + } + else + { + /* Set DMAy LIFCR register clear flag bits */ + DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); + } +} + +/** + * @brief Enables or disables the specified DMAy Streamx interrupts. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @arg DMA_IT_FE: FIFO error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Check if the DMA_IT parameter contains a FIFO interrupt */ + if ((DMA_IT & DMA_IT_FE) != 0) + { + if (NewState != DISABLE) + { + /* Enable the selected DMA FIFO interrupts */ + DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE; + } + else + { + /* Disable the selected DMA FIFO interrupts */ + DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; + } + } + + /* Check if the DMA_IT parameter contains a Transfer interrupt */ + if (DMA_IT != DMA_IT_FE) + { + if (NewState != DISABLE) + { + /* Enable the selected DMA transfer interrupts */ + DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); + } + else + { + /* Disable the selected DMA transfer interrupts */ + DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); + } + } +} + +/** + * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_IT: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt + * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt + * @arg DMA_IT_TEIFx: Streamx transfer error interrupt + * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt + * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt + * Where x can be 0 to 7 to select the DMA Stream. + * @retval The new state of DMA_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) +{ + ITStatus bitstatus = RESET; + DMA_TypeDef* DMAy; + uint32_t tmpreg = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if the interrupt enable bit is in the CR or FCR register */ + if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET) + { + /* Get the interrupt enable position mask in CR register */ + tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); + + /* Check the enable bit in CR register */ + enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg); + } + else + { + /* Check the enable bit in FCR register */ + enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); + } + + /* Check if the interrupt pending flag is in LISR or HISR */ + if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Get DMAy HISR register value */ + tmpreg = DMAy->HISR ; + } + else + { + /* Get DMAy LISR register value */ + tmpreg = DMAy->LISR ; + } + + /* mask all reserved bits */ + tmpreg &= (uint32_t)RESERVED_MASK; + + /* Check the status of the specified DMA interrupt */ + if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Streamx's interrupt pending bits. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_IT: specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt + * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt + * @arg DMA_IT_TEIFx: Streamx transfer error interrupt + * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt + * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt + * Where x can be 0 to 7 to select the DMA Stream. + * @retval None + */ +void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) +{ + DMA_TypeDef* DMAy; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if LIFCR or HIFCR register is targeted */ + if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Set DMAy HIFCR register clear interrupt bits */ + DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); + } + else + { + /* Set DMAy LIFCR register clear interrupt bits */ + DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c index 2964a84a6..9cf97ee91 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c @@ -1,312 +1,312 @@ -/** - ****************************************************************************** - * @file stm32f2xx_exti.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the EXTI peripheral: - * - Initialization and Configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * EXTI features - * =================================================================== - * - * External interrupt/event lines are mapped as following: - * 1- All available GPIO pins are connected to the 16 external - * interrupt/event lines from EXTI0 to EXTI15. - * 2- EXTI line 16 is connected to the PVD Output - * 3- EXTI line 17 is connected to the RTC Alarm event - * 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event - * 5- EXTI line 19 is connected to the Ethernet Wakeup event - * 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event - * 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events - * 8- EXTI line 22 is connected to the RTC Wakeup event - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * In order to use an I/O pin as an external interrupt source, follow - * steps below: - * 1- Configure the I/O in input mode using GPIO_Init() - * 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() - * 3- Select the mode(interrupt, event) and configure the trigger - * selection (Rising, falling or both) using EXTI_Init() - * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() - * - * @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx - * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_exti.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** @defgroup EXTI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x007FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param EXTI_Line: specifies the EXTI line on which the software interrupt - * will be generated. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @} - */ - -/** @defgroup EXTI_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - enablestatus = EXTI->IMR & EXTI_Line; - if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_exti.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the EXTI peripheral: + * - Initialization and Configuration + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * EXTI features + * =================================================================== + * + * External interrupt/event lines are mapped as following: + * 1- All available GPIO pins are connected to the 16 external + * interrupt/event lines from EXTI0 to EXTI15. + * 2- EXTI line 16 is connected to the PVD Output + * 3- EXTI line 17 is connected to the RTC Alarm event + * 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event + * 5- EXTI line 19 is connected to the Ethernet Wakeup event + * 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event + * 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events + * 8- EXTI line 22 is connected to the RTC Wakeup event + * + * =================================================================== + * How to use this driver + * =================================================================== + * + * In order to use an I/O pin as an external interrupt source, follow + * steps below: + * 1- Configure the I/O in input mode using GPIO_Init() + * 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() + * 3- Select the mode(interrupt, event) and configure the trigger + * selection (Rising, falling or both) using EXTI_Init() + * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() + * + * @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx + * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_exti.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** @defgroup EXTI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x007FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param EXTI_Line: specifies the EXTI line on which the software interrupt + * will be generated. + * This parameter can be any combination of EXTI_Linex where x can be (0..22) + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @} + */ + +/** @defgroup EXTI_Group2 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be EXTI_Linex where x can be(0..22) + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..22) + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be EXTI_Linex where x can be(0..22) + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..22) + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c index 59a2c8d5b..ff0f65eb6 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c @@ -1,1060 +1,1060 @@ -/** - ****************************************************************************** - * @file stm32f2xx_flash.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * - FLASH Interface configuration - * - FLASH Memory Programming - * - Option Bytes Programming - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * This driver provides functions to configure and program the FLASH - * memory of all STM32F2xx devices. - * These functions are split in 4 groups: - * - * 1. FLASH Interface configuration functions: this group includes the - * management of the following features: - * - Set the latency - * - Enable/Disable the prefetch buffer - * - Enable/Disable the Instruction cache and the Data cache - * - Reset the Instruction cache and the Data cache - * - * 2. FLASH Memory Programming functions: this group includes all needed - * functions to erase and program the main memory: - * - Lock and Unlock the FLASH interface - * - Erase function: Erase sector, erase all sectors - * - Program functions: byte, half word, word and double word - * - * 3. Option Bytes Programming functions: this group includes all needed - * functions to manage the Option Bytes: - * - Set/Reset the write protection - * - Set the Read protection Level - * - Set the BOR level - * - Program the user Option Bytes - * - Launch the Option Bytes loader - * - * 4. Interrupts and flags management functions: this group - * includes all needed functions to: - * - Enable/Disable the FLASH interrupt sources - * - Get flags status - * - Clear flags - * - Get FLASH operation status - * - Wait for last FLASH operation - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_flash.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** @defgroup FLASH_Group1 FLASH Interface configuration functions - * @brief FLASH Interface configuration functions - * - -@verbatim - =============================================================================== - FLASH Interface configuration functions - =============================================================================== - - This group includes the following functions: - - void FLASH_SetLatency(uint32_t FLASH_Latency) - To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| - |***************|****************|****************|*****************|*****************|*****************************+ - | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |Max Parallelism| x32 | x16 | x8 | x64 | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |PSIZE[1:0] | 10 | 01 | 00 | 11 | - +-------------------------------------------------------------------------------------------------------------------+ - - - void FLASH_PrefetchBufferCmd(FunctionalState NewState) - - void FLASH_InstructionCacheCmd(FunctionalState NewState) - - void FLASH_DataCacheCmd(FunctionalState NewState) - - void FLASH_InstructionCacheReset(void) - - void FLASH_DataCacheReset(void) - - The unlock sequence is not needed for these functions. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @arg FLASH_Latency_3: FLASH Three Latency cycles - * @arg FLASH_Latency_4: FLASH Four Latency cycles - * @arg FLASH_Latency_5: FLASH Five Latency cycles - * @arg FLASH_Latency_6: FLASH Six Latency cycles - * @arg FLASH_Latency_7: FLASH Seven Latency cycles - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */ - *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param NewState: new state of the Prefetch Buffer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_PrefetchBufferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Enable or disable the Prefetch Buffer */ - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_PRFTEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_PRFTEN); - } -} - -/** - * @brief Enables or disables the Instruction Cache feature. - * @param NewState: new state of the Instruction Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_InstructionCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_ICEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_ICEN); - } -} - -/** - * @brief Enables or disables the Data Cache feature. - * @param NewState: new state of the Data Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_DataCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_DCEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_DCEN); - } -} - -/** - * @brief Resets the Instruction Cache. - * @note This function must be used only when the Instruction Cache is disabled. - * @param None - * @retval None - */ -void FLASH_InstructionCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_ICRST; -} - -/** - * @brief Resets the Data Cache. - * @note This function must be used only when the Data Cache is disabled. - * @param None - * @retval None - */ -void FLASH_DataCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_DCRST; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group2 FLASH Memory Programming functions - * @brief FLASH Memory Programming functions - * -@verbatim - =============================================================================== - FLASH Memory Programming functions - =============================================================================== - - This group includes the following functions: - - void FLASH_Unlock(void) - - void FLASH_Lock(void) - - FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) - - FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) - - FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) - - FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) - - FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) - - FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) - - Any operation of erase or program should follow these steps: - 1. Call the FLASH_Unlock() function to enable the FLASH control register access - - 2. Call the desired function to erase sector(s) or program data - - 3. Call the FLASH_Lock() function to disable the FLASH control register access - (recommended to protect the FLASH memory against possible unwanted operation) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - } -} - -/** - * @brief Locks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - FLASH->CR |= FLASH_CR_LOCK; -} - -/** - * @brief Erases a specified FLASH Sector. - * - * @param FLASH_Sector: The Sector number to be erased. - * This parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11 - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(FLASH_Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR &= SECTOR_MASK; - FLASH->CR |= FLASH_CR_SER | FLASH_Sector; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH Sectors. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER); - - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Programs a double word (64-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V and an External Vpp is present. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint64_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a word (32-bit) at a specified address. - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @note This function must be used when the device voltage range is from 2.7V to 3.6V. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint32_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word (16-bit) at a specified address. - * @note This function must be used when the device voltage range is from 2.1V to 3.6V. - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_HALF_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a byte (8-bit) at a specified address. - * @note This function can be used within all the device supply voltage ranges. - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_BYTE; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint8_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - - /* Return the Program Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group3 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - =============================================================================== - Option Bytes Programming functions - =============================================================================== - - This group includes the following functions: - - void FLASH_OB_Unlock(void) - - void FLASH_OB_Lock(void) - - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - - void FLASH_OB_RDPConfig(uint8_t OB_RDP) - - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - - void FLASH_OB_BORConfig(uint8_t OB_BOR) - - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) - - FLASH_Status FLASH_OB_Launch(void) - - uint32_t FLASH_OB_GetUser(void) - - uint8_t FLASH_OB_GetWRP(void) - - uint8_t FLASH_OB_GetRDP(void) - - uint8_t FLASH_OB_GetBOR(void) - - Any operation of erase or program should follow these steps: - 1. Call the FLASH_OB_Unlock() function to enable the FLASH option control register access - - 2. Call one or several functions to program the desired Option Bytes: - - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable - the desired sector write protection - - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level - - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure - the user Option Bytes. - - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level - - 3. Once all needed Option Bytes to be programmed are correctly written, call the - FLASH_OB_Launch() function to launch the Option Bytes programming process. - - @note When changing the IWDG mode from HW to SW or from SW to HW, a system - reset is needed to make the change effective. - - 4. Call the FLASH_OB_Lock() function to disable the FLASH option control register - access (recommended to protect the Option Bytes against possible unwanted operations) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Unlock(void) -{ - if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) - { - /* Authorizes the Option Byte register programming */ - FLASH->OPTKEYR = FLASH_OPT_KEY1; - FLASH->OPTKEYR = FLASH_OPT_KEY2; - } -} - -/** - * @brief Locks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; -} - -/** - * @brief Enables or disables the write protection of the desired sectors - * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 - * @arg OB_WRP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); - } - else - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP; - } - } -} - -/** - * @brief Sets the read protection level. - * @param OB_RDP: specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg OB_RDP_Level_2: Full chip protection - * - * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * - * @retval None - */ -void FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; - - } -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval None - */ -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - uint8_t optiontmp = 0xFF; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); - - /* Update User Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); - } -} - -/** - * @brief Sets the BOR Level. - * @param OB_BOR: specifies the Option Bytes BOR Reset Level. - * This parameter can be one of the following values: - * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V - * @retval None - */ -void FLASH_OB_BORConfig(uint8_t OB_BOR) -{ - /* Check the parameters */ - assert_param(IS_OB_BOR(OB_BOR)); - - /* Set the BOR Level */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; - -} - -/** - * @brief Launch the option byte loading. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_OB_Launch(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Set the OPTSTRT bit in OPTCR register */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @param None - * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)(FLASH->OPTCR >> 5); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH Read Protection level. - * @param None - * @retval FLASH ReadOut Protection Status: - * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set - * - RESET, when OB_RDP_Level_0 is set - */ -FlagStatus FLASH_OB_GetRDP(void) -{ - FlagStatus readstatus = RESET; - - if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0)) - { - readstatus = SET; - } - else - { - readstatus = RESET; - } - return readstatus; -} - -/** - * @brief Returns the FLASH BOR level. - * @param None - * @retval The FLASH BOR level: - * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V - */ -uint8_t FLASH_OB_GetBOR(void) -{ - /* Return the FLASH BOR level */ - return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); -} - -/** - * @} - */ - -/** @defgroup FLASH_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); - - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_PROGRAM; - } - else - { - if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_OPERATION; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - } - /* Return the FLASH Status */ - return flashstatus; -} - -/** - * @brief Waits for a FLASH operation to complete. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(void) -{ - __IO FLASH_Status status = FLASH_COMPLETE; - - /* Check for the FLASH Status */ - status = FLASH_GetStatus(); - - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - while(status == FLASH_BUSY) - { - status = FLASH_GetStatus(); - } - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_flash.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * - FLASH Interface configuration + * - FLASH Memory Programming + * - Option Bytes Programming + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * + * This driver provides functions to configure and program the FLASH + * memory of all STM32F2xx devices. + * These functions are split in 4 groups: + * + * 1. FLASH Interface configuration functions: this group includes the + * management of the following features: + * - Set the latency + * - Enable/Disable the prefetch buffer + * - Enable/Disable the Instruction cache and the Data cache + * - Reset the Instruction cache and the Data cache + * + * 2. FLASH Memory Programming functions: this group includes all needed + * functions to erase and program the main memory: + * - Lock and Unlock the FLASH interface + * - Erase function: Erase sector, erase all sectors + * - Program functions: byte, half word, word and double word + * + * 3. Option Bytes Programming functions: this group includes all needed + * functions to manage the Option Bytes: + * - Set/Reset the write protection + * - Set the Read protection Level + * - Set the BOR level + * - Program the user Option Bytes + * - Launch the Option Bytes loader + * + * 4. Interrupts and flags management functions: this group + * includes all needed functions to: + * - Enable/Disable the FLASH interrupt sources + * - Get flags status + * - Clear flags + * - Get FLASH operation status + * - Wait for last FLASH operation + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_flash.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SECTOR_MASK ((uint32_t)0xFFFFFF07) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** @defgroup FLASH_Group1 FLASH Interface configuration functions + * @brief FLASH Interface configuration functions + * + +@verbatim + =============================================================================== + FLASH Interface configuration functions + =============================================================================== + + This group includes the following functions: + - void FLASH_SetLatency(uint32_t FLASH_Latency) + To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| + |***************|****************|****************|*****************|*****************|*****************************+ + | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | + |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| + |Max Parallelism| x32 | x16 | x8 | x64 | + |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| + |PSIZE[1:0] | 10 | 01 | 00 | 11 | + +-------------------------------------------------------------------------------------------------------------------+ + + - void FLASH_PrefetchBufferCmd(FunctionalState NewState) + - void FLASH_InstructionCacheCmd(FunctionalState NewState) + - void FLASH_DataCacheCmd(FunctionalState NewState) + - void FLASH_InstructionCacheReset(void) + - void FLASH_DataCacheReset(void) + + The unlock sequence is not needed for these functions. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the code latency value. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @arg FLASH_Latency_2: FLASH Two Latency cycles + * @arg FLASH_Latency_3: FLASH Three Latency cycles + * @arg FLASH_Latency_4: FLASH Four Latency cycles + * @arg FLASH_Latency_5: FLASH Five Latency cycles + * @arg FLASH_Latency_6: FLASH Six Latency cycles + * @arg FLASH_Latency_7: FLASH Seven Latency cycles + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */ + *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @param NewState: new state of the Prefetch Buffer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_PrefetchBufferCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Enable or disable the Prefetch Buffer */ + if(NewState != DISABLE) + { + FLASH->ACR |= FLASH_ACR_PRFTEN; + } + else + { + FLASH->ACR &= (~FLASH_ACR_PRFTEN); + } +} + +/** + * @brief Enables or disables the Instruction Cache feature. + * @param NewState: new state of the Instruction Cache. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_InstructionCacheCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + FLASH->ACR |= FLASH_ACR_ICEN; + } + else + { + FLASH->ACR &= (~FLASH_ACR_ICEN); + } +} + +/** + * @brief Enables or disables the Data Cache feature. + * @param NewState: new state of the Data Cache. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_DataCacheCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + FLASH->ACR |= FLASH_ACR_DCEN; + } + else + { + FLASH->ACR &= (~FLASH_ACR_DCEN); + } +} + +/** + * @brief Resets the Instruction Cache. + * @note This function must be used only when the Instruction Cache is disabled. + * @param None + * @retval None + */ +void FLASH_InstructionCacheReset(void) +{ + FLASH->ACR |= FLASH_ACR_ICRST; +} + +/** + * @brief Resets the Data Cache. + * @note This function must be used only when the Data Cache is disabled. + * @param None + * @retval None + */ +void FLASH_DataCacheReset(void) +{ + FLASH->ACR |= FLASH_ACR_DCRST; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group2 FLASH Memory Programming functions + * @brief FLASH Memory Programming functions + * +@verbatim + =============================================================================== + FLASH Memory Programming functions + =============================================================================== + + This group includes the following functions: + - void FLASH_Unlock(void) + - void FLASH_Lock(void) + - FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) + - FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) + - FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) + - FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) + - FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) + - FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) + + Any operation of erase or program should follow these steps: + 1. Call the FLASH_Unlock() function to enable the FLASH control register access + + 2. Call the desired function to erase sector(s) or program data + + 3. Call the FLASH_Lock() function to disable the FLASH control register access + (recommended to protect the FLASH memory against possible unwanted operation) + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the FLASH control register access + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + if((FLASH->CR & FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + } +} + +/** + * @brief Locks the FLASH control register access + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + FLASH->CR |= FLASH_CR_LOCK; +} + +/** + * @brief Erases a specified FLASH Sector. + * + * @param FLASH_Sector: The Sector number to be erased. + * This parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11 + * + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0x0; + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(FLASH_Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == VoltageRange_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == VoltageRange_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == VoltageRange_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the sector */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR &= SECTOR_MASK; + FLASH->CR |= FLASH_CR_SER | FLASH_Sector; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the SER Bit */ + FLASH->CR &= (~FLASH_CR_SER); + FLASH->CR &= SECTOR_MASK; + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH Sectors. + * + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0x0; + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == VoltageRange_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == VoltageRange_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == VoltageRange_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_CR_MER); + + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Programs a double word (64-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V and an External Vpp is present. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint64_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a word (32-bit) at a specified address. + * @param Address: specifies the address to be programmed. + * This parameter can be any address in Program memory zone or in OTP zone. + * @note This function must be used when the device voltage range is from 2.7V to 3.6V. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint32_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word (16-bit) at a specified address. + * @note This function must be used when the device voltage range is from 2.1V to 3.6V. + * @param Address: specifies the address to be programmed. + * This parameter can be any address in Program memory zone or in OTP zone. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_HALF_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a byte (8-bit) at a specified address. + * @note This function can be used within all the device supply voltage ranges. + * @param Address: specifies the address to be programmed. + * This parameter can be any address in Program memory zone or in OTP zone. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_BYTE; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint8_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + + /* Return the Program Status */ + return status; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group3 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + =============================================================================== + Option Bytes Programming functions + =============================================================================== + + This group includes the following functions: + - void FLASH_OB_Unlock(void) + - void FLASH_OB_Lock(void) + - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) + - void FLASH_OB_RDPConfig(uint8_t OB_RDP) + - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) + - void FLASH_OB_BORConfig(uint8_t OB_BOR) + - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) + - FLASH_Status FLASH_OB_Launch(void) + - uint32_t FLASH_OB_GetUser(void) + - uint8_t FLASH_OB_GetWRP(void) + - uint8_t FLASH_OB_GetRDP(void) + - uint8_t FLASH_OB_GetBOR(void) + + Any operation of erase or program should follow these steps: + 1. Call the FLASH_OB_Unlock() function to enable the FLASH option control register access + + 2. Call one or several functions to program the desired Option Bytes: + - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable + the desired sector write protection + - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level + - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure + the user Option Bytes. + - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level + + 3. Once all needed Option Bytes to be programmed are correctly written, call the + FLASH_OB_Launch() function to launch the Option Bytes programming process. + + @note When changing the IWDG mode from HW to SW or from SW to HW, a system + reset is needed to make the change effective. + + 4. Call the FLASH_OB_Lock() function to disable the FLASH option control register + access (recommended to protect the Option Bytes against possible unwanted operations) + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the FLASH Option Control Registers access. + * @param None + * @retval None + */ +void FLASH_OB_Unlock(void) +{ + if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) + { + /* Authorizes the Option Byte register programming */ + FLASH->OPTKEYR = FLASH_OPT_KEY1; + FLASH->OPTKEYR = FLASH_OPT_KEY2; + } +} + +/** + * @brief Locks the FLASH Option Control Registers access. + * @param None + * @retval None + */ +void FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; +} + +/** + * @brief Enables or disables the write protection of the desired sectors + * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 + * @arg OB_WRP_Sector_All + * @param Newstate: new state of the Write Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_WRP(OB_WRP)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + if(NewState != DISABLE) + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); + } + else + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP; + } + } +} + +/** + * @brief Sets the read protection level. + * @param OB_RDP: specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_Level_0: No protection + * @arg OB_RDP_Level_1: Read protection of the memory + * @arg OB_RDP_Level_2: Full chip protection + * + * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * + * @retval None + */ +void FLASH_OB_RDPConfig(uint8_t OB_RDP) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_RDP(OB_RDP)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; + + } +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param OB_IWDG: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval None + */ +void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) +{ + uint8_t optiontmp = 0xFF; + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); + + /* Update User Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); + } +} + +/** + * @brief Sets the BOR Level. + * @param OB_BOR: specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V + * @retval None + */ +void FLASH_OB_BORConfig(uint8_t OB_BOR) +{ + /* Check the parameters */ + assert_param(IS_OB_BOR(OB_BOR)); + + /* Set the BOR Level */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; + +} + +/** + * @brief Launch the option byte loading. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_OB_Launch(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Set the OPTSTRT bit in OPTCR register */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @param None + * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)(FLASH->OPTCR >> 5); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes value. + * @param None + * @retval The FLASH Write Protection Option Bytes value + */ +uint16_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @param None + * @retval FLASH ReadOut Protection Status: + * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set + * - RESET, when OB_RDP_Level_0 is set + */ +FlagStatus FLASH_OB_GetRDP(void) +{ + FlagStatus readstatus = RESET; + + if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0)) + { + readstatus = SET; + } + else + { + readstatus = RESET; + } + return readstatus; +} + +/** + * @brief Returns the FLASH BOR level. + * @param None + * @retval The FLASH BOR level: + * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V + */ +uint8_t FLASH_OB_GetBOR(void) +{ + /* Return the FLASH BOR level */ + return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); +} + +/** + * @} + */ + +/** @defgroup FLASH_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERR: FLASH Error Interrupt + * @arg FLASH_IT_EOP: FLASH end of operation Interrupt + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR: FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); + + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR: FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +} + +/** + * @brief Returns the FLASH Status. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_PROGRAM; + } + else + { + if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_OPERATION; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + } + /* Return the FLASH Status */ + return flashstatus; +} + +/** + * @brief Waits for a FLASH operation to complete. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(void) +{ + __IO FLASH_Status status = FLASH_COMPLETE; + + /* Check for the FLASH Status */ + status = FLASH_GetStatus(); + + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + while(status == FLASH_BUSY) + { + status = FLASH_GetStatus(); + } + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c index 84a38f064..357188281 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c @@ -1,987 +1,987 @@ -/** - ****************************************************************************** - * @file stm32f2xx_fsmc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the FSMC peripheral: - * - Interface with SRAM, PSRAM, NOR and OneNAND memories - * - Interface with NAND memories - * - Interface with 16-bit PC Card compatible memories - * - Interrupts and flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_fsmc.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* --------------------- FSMC registers bit mask ---------------------------- */ -/* FSMC BCRx Mask */ -#define BCR_MBKEN_SET ((uint32_t)0x00000001) -#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_SET ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_SET ((uint32_t)0x00000004) -#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_SET ((uint32_t)0x00000040) -#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) -#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** @defgroup FSMC_Group1 NOR/SRAM Controller functions - * @brief NOR/SRAM Controller functions - * -@verbatim - =============================================================================== - NOR/SRAM Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_NORSRAMInitTypeDef structure, for example: - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - and fill the FSMC_NORSRAMInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the NOR/SRAM Controller by calling the function - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - 5. Then enable the NOR/SRAM Bank, for example: - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure - * that contains the configuration information for the FSMC NOR/SRAM - * specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Bank1 NOR/SRAM control register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; - } - /* Bank1 NOR/SRAM timing register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group2 NAND Controller functions - * @brief NAND Controller functions - * -@verbatim - =============================================================================== - NAND Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - 8-bit or 16-bit NAND memory connected to the NAND Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_NANDInitTypeDef structure, for example: - FSMC_NANDInitTypeDef FSMC_NANDInitStructure; - and fill the FSMC_NANDInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the NAND Controller by calling the function - FSMC_NANDInit(&FSMC_NANDInitStructure); - - 5. Then enable the NAND Bank, for example: - FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the NAND Bank. - -@note To enable the Error Correction Code (ECC), you have to use the function - FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); - and to get the current ECC value you have to use the function - ECCval = FSMC_GetECC(FSMC_Bank3_NAND); - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified parameters - * in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that - * contains the configuration information for the FSMC NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MEMORYTYPE_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which - * will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_SET; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET; - } - } -} -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_SET; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} -/** - * @} - */ - -/** @defgroup FSMC_Group3 PCCARD Controller functions - * @brief PCCARD Controller functions - * -@verbatim - =============================================================================== - PCCARD Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - 16-bit PC Card compatible memory connected to the PCCARD Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_PCCARDInitTypeDef structure, for example: - FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; - and fill the FSMC_PCCARDInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the PCCARD Controller by calling the function - FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); - - 5. Then enable the PCCARD Bank: - FSMC_PCCARDCmd(ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the PCCARD Bank. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified parameters - * in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure - * that contains the configuration information for the FSMC PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_SET; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMC's pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMC's interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_fsmc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the FSMC peripheral: + * - Interface with SRAM, PSRAM, NOR and OneNAND memories + * - Interface with NAND memories + * - Interface with 16-bit PC Card compatible memories + * - Interrupts and flags management + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup FSMC + * @brief FSMC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* --------------------- FSMC registers bit mask ---------------------------- */ +/* FSMC BCRx Mask */ +#define BCR_MBKEN_SET ((uint32_t)0x00000001) +#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_SET ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_SET ((uint32_t)0x00000004) +#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_SET ((uint32_t)0x00000040) +#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) +#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FSMC_Private_Functions + * @{ + */ + +/** @defgroup FSMC_Group1 NOR/SRAM Controller functions + * @brief NOR/SRAM Controller functions + * +@verbatim + =============================================================================== + NOR/SRAM Controller functions + =============================================================================== + + The following sequence should be followed to configure the FSMC to interface with + SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: + + 1. Enable the clock for the FSMC and associated GPIOs using the following functions: + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + 2. FSMC pins configuration + - Connect the involved FSMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); + - Configure these FSMC pins in alternate function mode by calling the function + GPIO_Init(); + + 3. Declare a FSMC_NORSRAMInitTypeDef structure, for example: + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + and fill the FSMC_NORSRAMInitStructure variable with the allowed values of + the structure member. + + 4. Initialize the NOR/SRAM Controller by calling the function + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + 5. Then enable the NOR/SRAM Bank, for example: + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); + + 6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @retval None + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure + * that contains the configuration information for the FSMC NOR/SRAM + * specified Banks. + * @retval None + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; + } + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/** + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; + } +} +/** + * @} + */ + +/** @defgroup FSMC_Group2 NAND Controller functions + * @brief NAND Controller functions + * +@verbatim + =============================================================================== + NAND Controller functions + =============================================================================== + + The following sequence should be followed to configure the FSMC to interface with + 8-bit or 16-bit NAND memory connected to the NAND Bank: + + 1. Enable the clock for the FSMC and associated GPIOs using the following functions: + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + 2. FSMC pins configuration + - Connect the involved FSMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); + - Configure these FSMC pins in alternate function mode by calling the function + GPIO_Init(); + + 3. Declare a FSMC_NANDInitTypeDef structure, for example: + FSMC_NANDInitTypeDef FSMC_NANDInitStructure; + and fill the FSMC_NANDInitStructure variable with the allowed values of + the structure member. + + 4. Initialize the NAND Controller by calling the function + FSMC_NANDInit(&FSMC_NANDInitStructure); + + 5. Then enable the NAND Bank, for example: + FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); + + 6. At this stage you can read/write from/to the memory connected to the NAND Bank. + +@note To enable the Error Correction Code (ECC), you have to use the function + FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); + and to get the current ECC value you have to use the function + ECCval = FSMC_GetECC(FSMC_Bank3_NAND); + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval None + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Initializes the FSMC NAND Banks according to the specified parameters + * in the FSMC_NANDInitStruct. + * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that + * contains the configuration information for the FSMC NAND specified Banks. + * @retval None + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MEMORYTYPE_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + + +/** + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which + * will be initialized. + * @retval None + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_SET; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_SET; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET; + } + } +} +/** + * @brief Enables or disables the FSMC NAND ECC feature. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_SET; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_SET; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} +/** + * @} + */ + +/** @defgroup FSMC_Group3 PCCARD Controller functions + * @brief PCCARD Controller functions + * +@verbatim + =============================================================================== + PCCARD Controller functions + =============================================================================== + + The following sequence should be followed to configure the FSMC to interface with + 16-bit PC Card compatible memory connected to the PCCARD Bank: + + 1. Enable the clock for the FSMC and associated GPIOs using the following functions: + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + 2. FSMC pins configuration + - Connect the involved FSMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); + - Configure these FSMC pins in alternate function mode by calling the function + GPIO_Init(); + + 3. Declare a FSMC_PCCARDInitTypeDef structure, for example: + FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; + and fill the FSMC_PCCARDInitStructure variable with the allowed values of + the structure member. + + 4. Initialize the PCCARD Controller by calling the function + FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); + + 5. Then enable the PCCARD Bank: + FSMC_PCCARDCmd(ENABLE); + + 6. At this stage you can read/write from/to the memory connected to the PCCARD Bank. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FSMC PCCARD Bank according to the specified parameters + * in the FSMC_PCCARDInitStruct. + * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure + * that contains the configuration information for the FSMC PCCARD Bank. + * @retval None + */ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FSMC_PCCARDInitStruct member with its default value. + * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_SET; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET; + } +} +/** + * @} + */ + +/** @defgroup FSMC_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified FSMC interrupts. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @param NewState: new state of the specified FSMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FSMC flag is set or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. + * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. + * @retval The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FSMC's pending flags. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. + * @retval None + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/** + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FSMC's interrupt pending bits. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval None + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c index aaf8dcb4d..c53371e3d 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c @@ -1,566 +1,566 @@ -/** - ****************************************************************************** - * @file stm32f2xx_gpio.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * - Initialization and Configuration - * - GPIO Read and Write - * - GPIO Alternate functions configuration - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable the GPIO AHB clock using the following function - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - * 2. Configure the GPIO pin(s) using GPIO_Init() - * Four possible configuration are available for each pin: - * - Input: Floating, Pull-up, Pull-down. - * - Output: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * In output mode, the speed is configurable: 2 MHz, 25 MHz, - * 50 MHz or 100 MHz. - * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * - Analog: required mode when a pin is to be used as ADC channel - * or DAC output. - * - * 3- Peripherals alternate function: - * - For ADC and DAC, configure the desired pin in analog mode using - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; - * - For other peripherals (TIM, USART...): - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function mode using - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - * - * 5. To set/reset the level of a pin configured in output mode use - * GPIO_SetBits()/GPIO_ResetBits() - * - * 6. During and just after reset, the alternate functions are not - * active and the GPIO pins are configured in input floating mode - * (except JTAG pins). - * - * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as - * general-purpose (PC14 and PC15, respectively) when the LSE - * oscillator is off. The LSE has priority over the GPIO function. - * - * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as - * general-purpose PH0 and PH1, respectively, when the HSE - * oscillator is off. The HSE has priority over the GPIO function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_gpio.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** @defgroup GPIO_Group1 Initialization and Configuration - * @brief Initialization and Configuration - * -@verbatim - =============================================================================== - Initialization and Configuration - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset values. - * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); - } - else if (GPIOx == GPIOG) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); - } - else if (GPIOx == GPIOH) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); - } - else - { - if (GPIOx == GPIOI) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); - } - } -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - /* -------------------------Configure the port pins---------------- */ - /*-- GPIO Mode Configuration --*/ - for (pinpos = 0x00; pinpos < 0x10; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); - GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); - - if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) - { - /* Check Speed mode parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - - /* Speed mode configuration */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); - GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); - - /* Check Output mode parameters */ - assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); - - /* Output mode configuration*/ - GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; - GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); - } - - /* Pull-up Pull down resistor configuration*/ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); - GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); - } - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group2 GPIO Read and Write - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - GPIO Read and Write - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRL = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRH = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRRL = GPIO_Pin; - } - else - { - GPIOx->BSRRH = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Toggles the specified GPIO pins.. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the pins to be toggled. - * @retval None - */ -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function - * @brief GPIO Alternate functions configuration function - * -@verbatim - =============================================================================== - GPIO Alternate functions configuration function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_PinSource: specifies the pin for the Alternate function. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @param GPIO_AFSelection: selects the pin to used as Alternate function. - * This parameter can be one of the following values: - * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) - * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) - * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) - * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) - * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) - * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 - * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 - * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 - * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 - * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 - * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 - * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 - * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 - * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 - * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 - * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 - * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 - * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 - * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 - * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 - * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 - * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 - * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 - * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 - * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 - * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 - * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 - * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 - * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 - * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 - * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 - * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 - * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 - * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 - * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 - * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 - * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 - * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 - * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 - * @retval None - */ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) -{ - uint32_t temp = 0x00; - uint32_t temp_2 = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - assert_param(IS_GPIO_AF(GPIO_AF)); - - temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; - GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_gpio.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the GPIO peripheral: + * - Initialization and Configuration + * - GPIO Read and Write + * - GPIO Alternate functions configuration + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable the GPIO AHB clock using the following function + * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + * + * 2. Configure the GPIO pin(s) using GPIO_Init() + * Four possible configuration are available for each pin: + * - Input: Floating, Pull-up, Pull-down. + * - Output: Push-Pull (Pull-up, Pull-down or no Pull) + * Open Drain (Pull-up, Pull-down or no Pull). + * In output mode, the speed is configurable: 2 MHz, 25 MHz, + * 50 MHz or 100 MHz. + * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) + * Open Drain (Pull-up, Pull-down or no Pull). + * - Analog: required mode when a pin is to be used as ADC channel + * or DAC output. + * + * 3- Peripherals alternate function: + * - For ADC and DAC, configure the desired pin in analog mode using + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; + * - For other peripherals (TIM, USART...): + * - Connect the pin to the desired peripherals' Alternate + * Function (AF) using GPIO_PinAFConfig() function + * - Configure the desired pin in alternate function mode using + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * + * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() + * + * 5. To set/reset the level of a pin configured in output mode use + * GPIO_SetBits()/GPIO_ResetBits() + * + * 6. During and just after reset, the alternate functions are not + * active and the GPIO pins are configured in input floating mode + * (except JTAG pins). + * + * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as + * general-purpose (PC14 and PC15, respectively) when the LSE + * oscillator is off. The LSE has priority over the GPIO function. + * + * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as + * general-purpose PH0 and PH1, respectively, when the HSE + * oscillator is off. The HSE has priority over the GPIO function. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** @defgroup GPIO_Group1 Initialization and Configuration + * @brief Initialization and Configuration + * +@verbatim + =============================================================================== + Initialization and Configuration + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); + } + else if (GPIOx == GPIOG) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); + } + else if (GPIOx == GPIOH) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); + } + else + { + if (GPIOx == GPIOI) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); + } + } +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + + /* -------------------------Configure the port pins---------------- */ + /*-- GPIO Mode Configuration --*/ + for (pinpos = 0x00; pinpos < 0x10; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); + GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); + + if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) + { + /* Check Speed mode parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + + /* Speed mode configuration */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); + GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); + + /* Check Output mode parameters */ + assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); + + /* Output mode configuration*/ + GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; + GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); + } + + /* Pull-up Pull down resistor configuration*/ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); + GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); + } + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; + GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group2 GPIO Read and Write + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + GPIO Read and Write + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @note This functions uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRL = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @note This functions uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRH = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRRL = GPIO_Pin; + } + else + { + GPIOx->BSRRH = GPIO_Pin ; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Toggles the specified GPIO pins.. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR ^= GPIO_Pin; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function + * @brief GPIO Alternate functions configuration function + * +@verbatim + =============================================================================== + GPIO Alternate functions configuration function + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_PinSource: specifies the pin for the Alternate function. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @param GPIO_AFSelection: selects the pin to used as Alternate function. + * This parameter can be one of the following values: + * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) + * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) + * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) + * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) + * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) + * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 + * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 + * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 + * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 + * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 + * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 + * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 + * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 + * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 + * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 + * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 + * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 + * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 + * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 + * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 + * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 + * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 + * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 + * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 + * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 + * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 + * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 + * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 + * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 + * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 + * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 + * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 + * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 + * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 + * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 + * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 + * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 + * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 + * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 + * @retval None + */ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) +{ + uint32_t temp = 0x00; + uint32_t temp_2 = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + assert_param(IS_GPIO_AF(GPIO_AF)); + + temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; + GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c index 74ac28047..c5c799b98 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c @@ -1,706 +1,706 @@ -/** - ****************************************************************************** - * @file stm32f2xx_hash.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the HASH / HMAC Processor (HASH) peripheral: - * - Initialization and Configuration functions - * - Message Digest generation functions - * - context swapping functions - * - DMA interface function - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * HASH operation : - * ---------------- - * 1. Enable the HASH controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. - * - * 2. Initialise the HASH using HASH_Init() function. - * - * 3 . Reset the HASH processor core, so that the HASH will be ready - * to compute he message digest of a new message by using - * HASH_Reset() function. - * - * 4. Enable the HASH controller using the HASH_Cmd() function. - * - * 5. if using DMA for Data input transfer, Activate the DMA Request - * using HASH_DMACmd() function - * - * 6. if DMA is not used for data transfer, use HASH_DataIn() function - * to enter data to IN FIFO. - * - * - * 7. Configure the Number of valid bits in last word of the message - * using HASH_SetLastWordValidBitsNbr() function. - * - * 8. if the message length is not an exact multiple of 512 bits, - * then the function HASH_StartDigest() must be called to - * launch the computation of the final digest. - * - * 9. Once computed, the digest can be read using HASH_GetDigest() - * function. - * - * 10. To control HASH events you can use one of the following - * two methods: - * a- Check on HASH flags using the HASH_GetFlagStatus() function. - * b- Use HASH interrupts through the function HASH_ITConfig() at - * initialization phase and HASH_GetITStatus() function into - * interrupt routines in hashing phase. - * After checking on a flag you should clear it using HASH_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using HASH_ClearITPendingBit() function. - * - * 11. Save and restore hash processor context using - * HASH_SaveContext() and HASH_RestoreContext() functions. - * - * - * - * HMAC operation : - * ---------------- - * The HMAC algorithm is used for message authentication, by - * irreversibly binding the message being processed to a key chosen - * by the user. - * For HMAC specifications, refer to "HMAC: keyed-hashing for message - * authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" - * - * Basically, the HMAC algorithm consists of two nested hash operations: - * HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] - * where: - * - "pad" is a sequence of zeroes needed to extend the key to the - * length of the underlying hash function data block (that is - * 512 bits for both the SHA-1 and MD5 hash algorithms) - * - "|" represents the concatenation operator - * - * - * To compute the HMAC, four different phases are required: - * - * 1. Initialise the HASH using HASH_Init() function to do HMAC - * operation. - * - * 2. The key (to be used for the inner hash function) is then given - * to the core. This operation follows the same mechanism as the - * one used to send the message in the hash operation (that is, - * by HASH_DataIn() function and, finally, - * HASH_StartDigest() function. - * - * 3. Once the last word has been entered and computation has started, - * the hash processor elaborates the key. It is then ready to - * accept the message text using the same mechanism as the one - * used to send the message in the hash operation. - * - * 4. After the first hash round, the hash processor returns "ready" - * to indicate that it is ready to receive the key to be used for - * the outer hash function (normally, this key is the same as the - * one used for the inner hash function). When the last word of - * the key is entered and computation starts, the HMAC result is - * made available using HASH_GetDigest() function. - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_hash.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the HASH peripheral - - Configure the HASH Processor - - MD5/SHA1, - - HASH/HMAC, - - datatype - - HMAC Key (if mode = HMAC) - - Reset the HASH Processor - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the HASH peripheral registers to their default reset values - * @param None - * @retval None - */ -void HASH_DeInit(void) -{ - /* Enable HASH reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE); - /* Release HASH from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE); -} - -/** - * @brief Initializes the HASH peripheral according to the specified parameters - * in the HASH_InitStruct structure. - * @note the hash processor is reset when calling this function so that the - * HASH will be ready to compute the message digest of a new message. - * There is no need to call HASH_Reset() function. - * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains - * the configuration information for the HASH peripheral. - * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only - * if the algorithm mode is HMAC. - * @retval None - */ -void HASH_Init(HASH_InitTypeDef* HASH_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection)); - assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType)); - assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode)); - - /* Configure the Algorithm used, algorithm mode and the datatype */ - HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE); - HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \ - HASH_InitStruct->HASH_DataType | \ - HASH_InitStruct->HASH_AlgoMode); - - /* if algorithm mode is HMAC, set the Key */ - if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) - { - assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType)); - HASH->CR &= ~HASH_CR_LKEY; - HASH->CR |= HASH_InitStruct->HASH_HMACKeyType; - } - - /* Reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_CR_INIT; -} - -/** - * @brief Fills each HASH_InitStruct member with its default value. - * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will - * be initialized. - * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1, - * Data type selected is 32b and HMAC Key Type is short key. - * @retval None - */ -void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct) -{ - /* Initialize the HASH_AlgoSelection member */ - HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1; - - /* Initialize the HASH_AlgoMode member */ - HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH; - - /* Initialize the HASH_DataType member */ - HASH_InitStruct->HASH_DataType = HASH_DataType_32b; - - /* Initialize the HASH_HMACKeyType member */ - HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; -} - -/** - * @brief Resets the HASH processor core, so that the HASH will be ready - * to compute the message digest of a new message. - * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation - * completion interrupt status) bit corresponding to HASH_IT_DCI - * interrupt and HASH_FLAG_DCIS flag. - * @param None - * @retval None - */ -void HASH_Reset(void) -{ - /* Reset the HASH processor core */ - HASH->CR |= HASH_CR_INIT; -} -/** - * @} - */ - -/** @defgroup HASH_Group2 Message Digest generation functions - * @brief Message Digest generation functions - * -@verbatim - =============================================================================== - Message Digest generation functions - =============================================================================== - This section provides functions allowing the generation of message digest: - - Push data in the IN FIFO : using HASH_DataIn() - - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() - - set the last word valid bits number using HASH_SetLastWordValidBitsNbr() - - start digest calculation : using HASH_StartDigest() - - Get the Digest message : using HASH_GetDigest() - -@endverbatim - * @{ - */ - - -/** - * @brief Configure the Number of valid bits in last word of the message - * @param ValidNumber: Number of valid bits in last word of the message. - * This parameter must be a number between 0 and 0x1F. - * - 0x00: All 32 bits of the last data written are valid - * - 0x01: Only bit [0] of the last data written is valid - * - 0x02: Only bits[1:0] of the last data written are valid - * - 0x03: Only bits[2:0] of the last data written are valid - * - ... - * - 0x1F: Only bits[30:0] of the last data written are valid - * @note The Number of valid bits must be set before to start the message - * digest competition (in Hash and HMAC) and key treatment(in HMAC). - * @retval None - */ -void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber) -{ - /* Check the parameters */ - assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber)); - - /* Configure the Number of valid bits in last word of the message */ - HASH->STR &= ~(HASH_STR_NBW); - HASH->STR |= ValidNumber; -} - -/** - * @brief Writes data in the Data Input FIFO - * @param Data: new data of the message to be processed. - * @retval None - */ -void HASH_DataIn(uint32_t Data) -{ - /* Write in the DIN register a new data */ - HASH->DIN = Data; -} - -/** - * @brief Returns the number of words already pushed into the IN FIFO. - * @param None - * @retval The value of words already pushed into the IN FIFO. - */ -uint8_t HASH_GetInFIFOWordsNbr(void) -{ - /* Return the value of NBW bits */ - return ((HASH->CR & HASH_CR_NBW) >> 8); -} - -/** - * @brief Provides the message digest result. - * @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used - * and is read as zero. - * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will - * hold the message digest result - * @retval None - */ -void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest) -{ - /* Get the data field */ - HASH_MessageDigest->Data[0] = HASH->HR[0]; - HASH_MessageDigest->Data[1] = HASH->HR[1]; - HASH_MessageDigest->Data[2] = HASH->HR[2]; - HASH_MessageDigest->Data[3] = HASH->HR[3]; - HASH_MessageDigest->Data[4] = HASH->HR[4]; -} - -/** - * @brief Starts the message padding and calculation of the final message - * @param None - * @retval None - */ -void HASH_StartDigest(void) -{ - /* Start the Digest calculation */ - HASH->STR |= HASH_STR_DCAL; -} -/** - * @} - */ - -/** @defgroup HASH_Group3 Context swapping functions - * @brief Context swapping functions - * -@verbatim - =============================================================================== - Context swapping functions - =============================================================================== - - This section provides functions allowing to save and store HASH Context - - It is possible to interrupt a HASH/HMAC process to perform another processing - with a higher priority, and to complete the interrupted process later on, when - the higher priority task is complete. To do so, the context of the interrupted - task must be saved from the HASH registers to memory, and then be restored - from memory to the HASH registers. - - 1. To save the current context, use HASH_SaveContext() function - 2. To restore the saved context, use HASH_RestoreContext() function - - -@endverbatim - * @{ - */ - -/** - * @brief Save the Hash peripheral Context. - * @note The context can be saved only when no block is currently being - * processed. So user must wait for DINIS = 1 (the last block has been - * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not - * full and no processing is ongoing). - * @param HASH_ContextSave: pointer to a HASH_Context structure that contains - * the repository for current context. - * @retval None - */ -void HASH_SaveContext(HASH_Context* HASH_ContextSave) -{ - uint8_t i = 0; - - /* save context registers */ - HASH_ContextSave->HASH_IMR = HASH->IMR; - HASH_ContextSave->HASH_STR = HASH->STR; - HASH_ContextSave->HASH_CR = HASH->CR; - for(i=0; i<=50;i++) - { - HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; - } -} - -/** - * @brief Restore the Hash peripheral Context. - * @note After calling this function, user can restart the processing from the - * point where it has been interrupted. - * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains - * the repository for saved context. - * @retval None - */ -void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) -{ - uint8_t i = 0; - - /* restore context registers */ - HASH->IMR = HASH_ContextRestore->HASH_IMR; - HASH->STR = HASH_ContextRestore->HASH_STR; - HASH->CR = HASH_ContextRestore->HASH_CR; - - /* Initialize the hash processor */ - HASH->CR |= HASH_CR_INIT; - - /* continue restoring context registers */ - for(i=0; i<=50;i++) - { - HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; - } -} -/** - * @} - */ - -/** @defgroup HASH_Group4 HASH's DMA interface Configuration function - * @brief HASH's DMA interface Configuration function - * -@verbatim - =============================================================================== - HASH's DMA interface Configuration function - =============================================================================== - - This section provides functions allowing to configure the DMA interface for - HASH/ HMAC data input transfer. - - When the DMA mode is enabled (using the HASH_DMACmd() function), data can be - sent to the IN FIFO using the DMA peripheral. - - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the HASH DMA interface. - * @note The DMA is disabled by hardware after the end of transfer. - * @param NewState: new state of the selected HASH DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the HASH DMA request */ - HASH->CR |= HASH_CR_DMAE; - } - else - { - /* Disable the HASH DMA request */ - HASH->CR &= ~HASH_CR_DMAE; - } -} -/** - * @} - */ - -/** @defgroup HASH_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the HASH Interrupts and - to get the status and clear flags and Interrupts pending bits. - - The HASH provides 2 Interrupts sources and 5 Flags: - - Flags : - ---------- - 1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO - which means that a new block (512 bit) can be entered - into the input buffer. - - 2. HASH_FLAG_DCIS : set when Digest calculation is complete - - 3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or - a transfer is ongoing. - This Flag is cleared only by hardware. - - 4. HASH_FLAG_BUSY : set when The hash core is processing a block of data - This Flag is cleared only by hardware. - - 5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that - the Data IN FIFO contains at least one word of data. - This Flag is cleared only by hardware. - - Interrupts : - ------------ - - 1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16 - locations are free in the Data IN FIFO which means that - a new block (512 bit) can be entered into the input buffer. - This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DINI) function. - - 2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest - calculation is complete. - This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DCI) function. - - Managing the HASH controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the HASH controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - HASH_GetFlagStatus() : to check if flags events occur. - - HASH_ClearFlag() : to clear the flags events. - - 2. In the Interrupt Mode it is advised to use the following functions: - - HASH_ITConfig() : to enable or disable the interrupt source. - - HASH_GetITStatus() : to check if Interrupt occurs. - - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified HASH interrupts. - * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @param NewState: new state of the specified HASH interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_HASH_IT(HASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected HASH interrupt */ - HASH->IMR |= HASH_IT; - } - else - { - /* Disable the selected HASH interrupt */ - HASH->IMR &= (uint8_t) ~HASH_IT; - } -} - -/** - * @brief Checks whether the specified HASH flag is set or not. - * @param HASH_FLAG: specifies the HASH flag to check. - * This parameter can be one of the following values: - * @arg HASH_FLAG_DINIS: Data input interrupt status flag - * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag - * @arg HASH_FLAG_BUSY: Busy flag - * @arg HASH_FLAG_DMAS: DMAS Status flag - * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag - * @retval The new state of HASH_FLAG (SET or RESET) - */ -FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tempreg = 0; - - /* Check the parameters */ - assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); - - /* check if the FLAG is in CR register */ - if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET ) - { - tempreg = HASH->CR; - } - else /* The FLAG is in SR register */ - { - tempreg = HASH->SR; - } - - /* Check the status of the specified HASH flag */ - if ((tempreg & HASH_FLAG) != (uint16_t)RESET) - { - /* HASH is set */ - bitstatus = SET; - } - else - { - /* HASH_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the HASH_FLAG status */ - return bitstatus; -} -/** - * @brief Clears the HASH flags. - * @param HASH_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg HASH_FLAG_DINIS: Data Input Flag - * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag - * @retval None - */ -void HASH_ClearFlag(uint16_t HASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); - - /* Clear the selected HASH flags */ - HASH->SR = ~(uint32_t)HASH_FLAG; -} -/** - * @brief Checks whether the specified HASH interrupt has occurred or not. - * @param HASH_IT: specifies the HASH interrupt source to check. - * This parameter can be one of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @retval The new state of HASH_IT (SET or RESET). - */ -ITStatus HASH_GetITStatus(uint8_t HASH_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_HASH_GET_IT(HASH_IT)); - - - /* Check the status of the specified HASH interrupt */ - tmpreg = HASH->SR; - - if (((HASH->IMR & tmpreg) & HASH_IT) != RESET) - { - /* HASH_IT is set */ - bitstatus = SET; - } - else - { - /* HASH_IT is reset */ - bitstatus = RESET; - } - /* Return the HASH_IT status */ - return bitstatus; -} - -/** - * @brief Clears the HASH interrupt pending bit(s). - * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear. - * This parameter can be any combination of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @retval None - */ -void HASH_ClearITPendingBit(uint8_t HASH_IT) -{ - /* Check the parameters */ - assert_param(IS_HASH_IT(HASH_IT)); - - /* Clear the selected HASH interrupt pending bit */ - HASH->SR = (uint8_t)~HASH_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_hash.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the HASH / HMAC Processor (HASH) peripheral: + * - Initialization and Configuration functions + * - Message Digest generation functions + * - context swapping functions + * - DMA interface function + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * HASH operation : + * ---------------- + * 1. Enable the HASH controller clock using + * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. + * + * 2. Initialise the HASH using HASH_Init() function. + * + * 3 . Reset the HASH processor core, so that the HASH will be ready + * to compute he message digest of a new message by using + * HASH_Reset() function. + * + * 4. Enable the HASH controller using the HASH_Cmd() function. + * + * 5. if using DMA for Data input transfer, Activate the DMA Request + * using HASH_DMACmd() function + * + * 6. if DMA is not used for data transfer, use HASH_DataIn() function + * to enter data to IN FIFO. + * + * + * 7. Configure the Number of valid bits in last word of the message + * using HASH_SetLastWordValidBitsNbr() function. + * + * 8. if the message length is not an exact multiple of 512 bits, + * then the function HASH_StartDigest() must be called to + * launch the computation of the final digest. + * + * 9. Once computed, the digest can be read using HASH_GetDigest() + * function. + * + * 10. To control HASH events you can use one of the following + * two methods: + * a- Check on HASH flags using the HASH_GetFlagStatus() function. + * b- Use HASH interrupts through the function HASH_ITConfig() at + * initialization phase and HASH_GetITStatus() function into + * interrupt routines in hashing phase. + * After checking on a flag you should clear it using HASH_ClearFlag() + * function. And after checking on an interrupt event you should + * clear it using HASH_ClearITPendingBit() function. + * + * 11. Save and restore hash processor context using + * HASH_SaveContext() and HASH_RestoreContext() functions. + * + * + * + * HMAC operation : + * ---------------- + * The HMAC algorithm is used for message authentication, by + * irreversibly binding the message being processed to a key chosen + * by the user. + * For HMAC specifications, refer to "HMAC: keyed-hashing for message + * authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" + * + * Basically, the HMAC algorithm consists of two nested hash operations: + * HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] + * where: + * - "pad" is a sequence of zeroes needed to extend the key to the + * length of the underlying hash function data block (that is + * 512 bits for both the SHA-1 and MD5 hash algorithms) + * - "|" represents the concatenation operator + * + * + * To compute the HMAC, four different phases are required: + * + * 1. Initialise the HASH using HASH_Init() function to do HMAC + * operation. + * + * 2. The key (to be used for the inner hash function) is then given + * to the core. This operation follows the same mechanism as the + * one used to send the message in the hash operation (that is, + * by HASH_DataIn() function and, finally, + * HASH_StartDigest() function. + * + * 3. Once the last word has been entered and computation has started, + * the hash processor elaborates the key. It is then ready to + * accept the message text using the same mechanism as the one + * used to send the message in the hash operation. + * + * 4. After the first hash round, the hash processor returns "ready" + * to indicate that it is ready to receive the key to be used for + * the outer hash function (normally, this key is the same as the + * one used for the inner hash function). When the last word of + * the key is entered and computation starts, the HMAC result is + * made available using HASH_GetDigest() function. + * + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_hash.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup HASH + * @brief HASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HASH_Private_Functions + * @{ + */ + +/** @defgroup HASH_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + This section provides functions allowing to + - Initialize the HASH peripheral + - Configure the HASH Processor + - MD5/SHA1, + - HASH/HMAC, + - datatype + - HMAC Key (if mode = HMAC) + - Reset the HASH Processor + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the HASH peripheral registers to their default reset values + * @param None + * @retval None + */ +void HASH_DeInit(void) +{ + /* Enable HASH reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE); + /* Release HASH from reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE); +} + +/** + * @brief Initializes the HASH peripheral according to the specified parameters + * in the HASH_InitStruct structure. + * @note the hash processor is reset when calling this function so that the + * HASH will be ready to compute the message digest of a new message. + * There is no need to call HASH_Reset() function. + * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains + * the configuration information for the HASH peripheral. + * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only + * if the algorithm mode is HMAC. + * @retval None + */ +void HASH_Init(HASH_InitTypeDef* HASH_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection)); + assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType)); + assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode)); + + /* Configure the Algorithm used, algorithm mode and the datatype */ + HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE); + HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \ + HASH_InitStruct->HASH_DataType | \ + HASH_InitStruct->HASH_AlgoMode); + + /* if algorithm mode is HMAC, set the Key */ + if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) + { + assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType)); + HASH->CR &= ~HASH_CR_LKEY; + HASH->CR |= HASH_InitStruct->HASH_HMACKeyType; + } + + /* Reset the HASH processor core, so that the HASH will be ready to compute + the message digest of a new message */ + HASH->CR |= HASH_CR_INIT; +} + +/** + * @brief Fills each HASH_InitStruct member with its default value. + * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will + * be initialized. + * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1, + * Data type selected is 32b and HMAC Key Type is short key. + * @retval None + */ +void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct) +{ + /* Initialize the HASH_AlgoSelection member */ + HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1; + + /* Initialize the HASH_AlgoMode member */ + HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH; + + /* Initialize the HASH_DataType member */ + HASH_InitStruct->HASH_DataType = HASH_DataType_32b; + + /* Initialize the HASH_HMACKeyType member */ + HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; +} + +/** + * @brief Resets the HASH processor core, so that the HASH will be ready + * to compute the message digest of a new message. + * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation + * completion interrupt status) bit corresponding to HASH_IT_DCI + * interrupt and HASH_FLAG_DCIS flag. + * @param None + * @retval None + */ +void HASH_Reset(void) +{ + /* Reset the HASH processor core */ + HASH->CR |= HASH_CR_INIT; +} +/** + * @} + */ + +/** @defgroup HASH_Group2 Message Digest generation functions + * @brief Message Digest generation functions + * +@verbatim + =============================================================================== + Message Digest generation functions + =============================================================================== + This section provides functions allowing the generation of message digest: + - Push data in the IN FIFO : using HASH_DataIn() + - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() + - set the last word valid bits number using HASH_SetLastWordValidBitsNbr() + - start digest calculation : using HASH_StartDigest() + - Get the Digest message : using HASH_GetDigest() + +@endverbatim + * @{ + */ + + +/** + * @brief Configure the Number of valid bits in last word of the message + * @param ValidNumber: Number of valid bits in last word of the message. + * This parameter must be a number between 0 and 0x1F. + * - 0x00: All 32 bits of the last data written are valid + * - 0x01: Only bit [0] of the last data written is valid + * - 0x02: Only bits[1:0] of the last data written are valid + * - 0x03: Only bits[2:0] of the last data written are valid + * - ... + * - 0x1F: Only bits[30:0] of the last data written are valid + * @note The Number of valid bits must be set before to start the message + * digest competition (in Hash and HMAC) and key treatment(in HMAC). + * @retval None + */ +void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber) +{ + /* Check the parameters */ + assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber)); + + /* Configure the Number of valid bits in last word of the message */ + HASH->STR &= ~(HASH_STR_NBW); + HASH->STR |= ValidNumber; +} + +/** + * @brief Writes data in the Data Input FIFO + * @param Data: new data of the message to be processed. + * @retval None + */ +void HASH_DataIn(uint32_t Data) +{ + /* Write in the DIN register a new data */ + HASH->DIN = Data; +} + +/** + * @brief Returns the number of words already pushed into the IN FIFO. + * @param None + * @retval The value of words already pushed into the IN FIFO. + */ +uint8_t HASH_GetInFIFOWordsNbr(void) +{ + /* Return the value of NBW bits */ + return ((HASH->CR & HASH_CR_NBW) >> 8); +} + +/** + * @brief Provides the message digest result. + * @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used + * and is read as zero. + * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will + * hold the message digest result + * @retval None + */ +void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest) +{ + /* Get the data field */ + HASH_MessageDigest->Data[0] = HASH->HR[0]; + HASH_MessageDigest->Data[1] = HASH->HR[1]; + HASH_MessageDigest->Data[2] = HASH->HR[2]; + HASH_MessageDigest->Data[3] = HASH->HR[3]; + HASH_MessageDigest->Data[4] = HASH->HR[4]; +} + +/** + * @brief Starts the message padding and calculation of the final message + * @param None + * @retval None + */ +void HASH_StartDigest(void) +{ + /* Start the Digest calculation */ + HASH->STR |= HASH_STR_DCAL; +} +/** + * @} + */ + +/** @defgroup HASH_Group3 Context swapping functions + * @brief Context swapping functions + * +@verbatim + =============================================================================== + Context swapping functions + =============================================================================== + + This section provides functions allowing to save and store HASH Context + + It is possible to interrupt a HASH/HMAC process to perform another processing + with a higher priority, and to complete the interrupted process later on, when + the higher priority task is complete. To do so, the context of the interrupted + task must be saved from the HASH registers to memory, and then be restored + from memory to the HASH registers. + + 1. To save the current context, use HASH_SaveContext() function + 2. To restore the saved context, use HASH_RestoreContext() function + + +@endverbatim + * @{ + */ + +/** + * @brief Save the Hash peripheral Context. + * @note The context can be saved only when no block is currently being + * processed. So user must wait for DINIS = 1 (the last block has been + * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not + * full and no processing is ongoing). + * @param HASH_ContextSave: pointer to a HASH_Context structure that contains + * the repository for current context. + * @retval None + */ +void HASH_SaveContext(HASH_Context* HASH_ContextSave) +{ + uint8_t i = 0; + + /* save context registers */ + HASH_ContextSave->HASH_IMR = HASH->IMR; + HASH_ContextSave->HASH_STR = HASH->STR; + HASH_ContextSave->HASH_CR = HASH->CR; + for(i=0; i<=50;i++) + { + HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; + } +} + +/** + * @brief Restore the Hash peripheral Context. + * @note After calling this function, user can restart the processing from the + * point where it has been interrupted. + * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains + * the repository for saved context. + * @retval None + */ +void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) +{ + uint8_t i = 0; + + /* restore context registers */ + HASH->IMR = HASH_ContextRestore->HASH_IMR; + HASH->STR = HASH_ContextRestore->HASH_STR; + HASH->CR = HASH_ContextRestore->HASH_CR; + + /* Initialize the hash processor */ + HASH->CR |= HASH_CR_INIT; + + /* continue restoring context registers */ + for(i=0; i<=50;i++) + { + HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; + } +} +/** + * @} + */ + +/** @defgroup HASH_Group4 HASH's DMA interface Configuration function + * @brief HASH's DMA interface Configuration function + * +@verbatim + =============================================================================== + HASH's DMA interface Configuration function + =============================================================================== + + This section provides functions allowing to configure the DMA interface for + HASH/ HMAC data input transfer. + + When the DMA mode is enabled (using the HASH_DMACmd() function), data can be + sent to the IN FIFO using the DMA peripheral. + + + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the HASH DMA interface. + * @note The DMA is disabled by hardware after the end of transfer. + * @param NewState: new state of the selected HASH DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void HASH_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the HASH DMA request */ + HASH->CR |= HASH_CR_DMAE; + } + else + { + /* Disable the HASH DMA request */ + HASH->CR &= ~HASH_CR_DMAE; + } +} +/** + * @} + */ + +/** @defgroup HASH_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides functions allowing to configure the HASH Interrupts and + to get the status and clear flags and Interrupts pending bits. + + The HASH provides 2 Interrupts sources and 5 Flags: + + Flags : + ---------- + 1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO + which means that a new block (512 bit) can be entered + into the input buffer. + + 2. HASH_FLAG_DCIS : set when Digest calculation is complete + + 3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or + a transfer is ongoing. + This Flag is cleared only by hardware. + + 4. HASH_FLAG_BUSY : set when The hash core is processing a block of data + This Flag is cleared only by hardware. + + 5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that + the Data IN FIFO contains at least one word of data. + This Flag is cleared only by hardware. + + Interrupts : + ------------ + + 1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16 + locations are free in the Data IN FIFO which means that + a new block (512 bit) can be entered into the input buffer. + This interrupt source is cleared using + HASH_ClearITPendingBit(HASH_IT_DINI) function. + + 2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest + calculation is complete. + This interrupt source is cleared using + HASH_ClearITPendingBit(HASH_IT_DCI) function. + + Managing the HASH controller events : + ------------------------------------ + The user should identify which mode will be used in his application to manage + the HASH controller events: Polling mode or Interrupt mode. + + 1. In the Polling Mode it is advised to use the following functions: + - HASH_GetFlagStatus() : to check if flags events occur. + - HASH_ClearFlag() : to clear the flags events. + + 2. In the Interrupt Mode it is advised to use the following functions: + - HASH_ITConfig() : to enable or disable the interrupt source. + - HASH_GetITStatus() : to check if Interrupt occurs. + - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified HASH interrupts. + * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg HASH_IT_DINI: Data Input interrupt + * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt + * @param NewState: new state of the specified HASH interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_HASH_IT(HASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected HASH interrupt */ + HASH->IMR |= HASH_IT; + } + else + { + /* Disable the selected HASH interrupt */ + HASH->IMR &= (uint8_t) ~HASH_IT; + } +} + +/** + * @brief Checks whether the specified HASH flag is set or not. + * @param HASH_FLAG: specifies the HASH flag to check. + * This parameter can be one of the following values: + * @arg HASH_FLAG_DINIS: Data input interrupt status flag + * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag + * @arg HASH_FLAG_BUSY: Busy flag + * @arg HASH_FLAG_DMAS: DMAS Status flag + * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag + * @retval The new state of HASH_FLAG (SET or RESET) + */ +FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tempreg = 0; + + /* Check the parameters */ + assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); + + /* check if the FLAG is in CR register */ + if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET ) + { + tempreg = HASH->CR; + } + else /* The FLAG is in SR register */ + { + tempreg = HASH->SR; + } + + /* Check the status of the specified HASH flag */ + if ((tempreg & HASH_FLAG) != (uint16_t)RESET) + { + /* HASH is set */ + bitstatus = SET; + } + else + { + /* HASH_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the HASH_FLAG status */ + return bitstatus; +} +/** + * @brief Clears the HASH flags. + * @param HASH_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg HASH_FLAG_DINIS: Data Input Flag + * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag + * @retval None + */ +void HASH_ClearFlag(uint16_t HASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); + + /* Clear the selected HASH flags */ + HASH->SR = ~(uint32_t)HASH_FLAG; +} +/** + * @brief Checks whether the specified HASH interrupt has occurred or not. + * @param HASH_IT: specifies the HASH interrupt source to check. + * This parameter can be one of the following values: + * @arg HASH_IT_DINI: Data Input interrupt + * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt + * @retval The new state of HASH_IT (SET or RESET). + */ +ITStatus HASH_GetITStatus(uint8_t HASH_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_HASH_GET_IT(HASH_IT)); + + + /* Check the status of the specified HASH interrupt */ + tmpreg = HASH->SR; + + if (((HASH->IMR & tmpreg) & HASH_IT) != RESET) + { + /* HASH_IT is set */ + bitstatus = SET; + } + else + { + /* HASH_IT is reset */ + bitstatus = RESET; + } + /* Return the HASH_IT status */ + return bitstatus; +} + +/** + * @brief Clears the HASH interrupt pending bit(s). + * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear. + * This parameter can be any combination of the following values: + * @arg HASH_IT_DINI: Data Input interrupt + * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt + * @retval None + */ +void HASH_ClearITPendingBit(uint8_t HASH_IT) +{ + /* Check the parameters */ + assert_param(IS_HASH_IT(HASH_IT)); + + /* Clear the selected HASH interrupt pending bit */ + HASH->SR = (uint8_t)~HASH_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c index 6cb343737..21b929f4f 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c @@ -1,320 +1,320 @@ -/** - ****************************************************************************** - * @file stm32f2xx_hash_md5.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides high level functions to compute the HASH MD5 and - * HMAC MD5 Digest of an input message. - * It uses the stm32f2xx_hash.c/.h drivers to access the STM32F2xx HASH - * peripheral. - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The HASH controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. - * - * 2. Calculate the HASH MD5 Digest using HASH_MD5() function. - * - * 3. Calculate the HMAC MD5 Digest using HMAC_MD5() function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_hash.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group7 High Level MD5 functions - * @brief High Level MD5 Hash and HMAC functions - * -@verbatim - =============================================================================== - High Level MD5 Hash and HMAC functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Compute the HASH MD5 digest. - * @param Input: pointer to the Input buffer to be treated. - * @param Ilen: length of the Input buffer. - * @param Output: the returned digest - * @retval An ErrorStatus enumeration value: - * - SUCCESS: digest computation done - * - ERROR: digest computation failed - */ -ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]) -{ - HASH_InitTypeDef MD5_HASH_InitStructure; - HASH_MsgDigest MD5_MessageDigest; - __IO uint16_t nbvalidbitsdata = 0; - uint32_t i = 0; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - - /* Number of valid bits in last word of the Input data */ - nbvalidbitsdata = 8 * (Ilen % 4); - - /* HASH peripheral initialization */ - HASH_DeInit(); - - /* HASH Configuration */ - MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; - MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; - MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; - HASH_Init(&MD5_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the data */ - HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); - - /* Write the Input block in the IN FIFO */ - for(i=0; i 64) - { - /* HMAC long Key */ - MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; - } - else - { - /* HMAC short Key */ - MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; - } - HASH_Init(&MD5_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the Key */ - HASH_SetLastWordValidBitsNbr(nbvalidbitskey); - - /* Write the Key */ - for(i=0; i
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_hash.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup HASH + * @brief HASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HASH_Private_Functions + * @{ + */ + +/** @defgroup HASH_Group7 High Level MD5 functions + * @brief High Level MD5 Hash and HMAC functions + * +@verbatim + =============================================================================== + High Level MD5 Hash and HMAC functions + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Compute the HASH MD5 digest. + * @param Input: pointer to the Input buffer to be treated. + * @param Ilen: length of the Input buffer. + * @param Output: the returned digest + * @retval An ErrorStatus enumeration value: + * - SUCCESS: digest computation done + * - ERROR: digest computation failed + */ +ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]) +{ + HASH_InitTypeDef MD5_HASH_InitStructure; + HASH_MsgDigest MD5_MessageDigest; + __IO uint16_t nbvalidbitsdata = 0; + uint32_t i = 0; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + + + /* Number of valid bits in last word of the Input data */ + nbvalidbitsdata = 8 * (Ilen % 4); + + /* HASH peripheral initialization */ + HASH_DeInit(); + + /* HASH Configuration */ + MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; + MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; + MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; + HASH_Init(&MD5_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the data */ + HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); + + /* Write the Input block in the IN FIFO */ + for(i=0; i 64) + { + /* HMAC long Key */ + MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; + } + else + { + /* HMAC short Key */ + MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; + } + HASH_Init(&MD5_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the Key */ + HASH_SetLastWordValidBitsNbr(nbvalidbitskey); + + /* Write the Key */ + for(i=0; i
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_hash.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group6 High Level SHA1 functions - * @brief High Level SHA1 Hash and HMAC functions - * -@verbatim - =============================================================================== - High Level SHA1 Hash and HMAC functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Compute the HASH SHA1 digest. - * @param Input: pointer to the Input buffer to be treated. - * @param Ilen: length of the Input buffer. - * @param Output: the returned digest - * @retval An ErrorStatus enumeration value: - * - SUCCESS: digest computation done - * - ERROR: digest computation failed - */ -ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) -{ - HASH_InitTypeDef SHA1_HASH_InitStructure; - HASH_MsgDigest SHA1_MessageDigest; - __IO uint16_t nbvalidbitsdata = 0; - uint32_t i = 0; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - /* Number of valid bits in last word of the Input data */ - nbvalidbitsdata = 8 * (Ilen % 4); - - /* HASH peripheral initialization */ - HASH_DeInit(); - - /* HASH Configuration */ - SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; - SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; - SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; - HASH_Init(&SHA1_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the data */ - HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); - - /* Write the Input block in the IN FIFO */ - for(i=0; i 64) - { - /* HMAC long Key */ - SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; - } - else - { - /* HMAC short Key */ - SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; - } - HASH_Init(&SHA1_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the Key */ - HASH_SetLastWordValidBitsNbr(nbvalidbitskey); - - /* Write the Key */ - for(i=0; i
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_hash.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup HASH + * @brief HASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HASH_Private_Functions + * @{ + */ + +/** @defgroup HASH_Group6 High Level SHA1 functions + * @brief High Level SHA1 Hash and HMAC functions + * +@verbatim + =============================================================================== + High Level SHA1 Hash and HMAC functions + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Compute the HASH SHA1 digest. + * @param Input: pointer to the Input buffer to be treated. + * @param Ilen: length of the Input buffer. + * @param Output: the returned digest + * @retval An ErrorStatus enumeration value: + * - SUCCESS: digest computation done + * - ERROR: digest computation failed + */ +ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) +{ + HASH_InitTypeDef SHA1_HASH_InitStructure; + HASH_MsgDigest SHA1_MessageDigest; + __IO uint16_t nbvalidbitsdata = 0; + uint32_t i = 0; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + + /* Number of valid bits in last word of the Input data */ + nbvalidbitsdata = 8 * (Ilen % 4); + + /* HASH peripheral initialization */ + HASH_DeInit(); + + /* HASH Configuration */ + SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; + SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; + SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; + HASH_Init(&SHA1_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the data */ + HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); + + /* Write the Input block in the IN FIFO */ + for(i=0; i 64) + { + /* HMAC long Key */ + SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; + } + else + { + /* HMAC short Key */ + SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; + } + HASH_Init(&SHA1_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the Key */ + HASH_SetLastWordValidBitsNbr(nbvalidbitskey); + + /* Write the Key */ + for(i=0; iGPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * Recommended configuration is Push-Pull, Pull-up, Open-Drain. - * Add an external pull up if necessary (typically 4.7 KOhm). - * - * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged - * Address using the I2C_Init() function. - * - * 5. Optionally you can enable/configure the following parameters without - * re-initialization (i.e there is no need to call again I2C_Init() function): - * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function - * - Enable the dual addressing mode using I2C_DualAddressCmd() function - * - Enable the general call using the I2C_GeneralCallCmd() function - * - Enable the clock stretching using I2C_StretchClockCmd() function - * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() - * function. - * - Configure the NACK position for Master Receiver mode in case of - * 2 bytes reception using the function I2C_NACKPositionConfig(). - * - Enable the PEC Calculation using I2C_CalculatePEC() function - * - For SMBus Mode: - * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function - * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function - * - * 6. Enable the NVIC and the corresponding interrupt using the function - * I2C_ITConfig() if you need to use interrupt mode. - * - * 7. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using I2C_DMACmd() or - * I2C_DMALastTransferCmd() function. - * @note When using DMA mode, I2C interrupts may be used at the same time to - * control the communication flow (Start/Stop/Ack... events and errors). - * - * 8. Enable the I2C using the I2C_Cmd() function. - * - * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the - * transfers. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_i2c.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral - input clock) must be a multiple of 10 MHz */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & I2C_CCR_CCR) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | I2C_CCR_FS); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= I2C_CR1_START; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= I2C_CR1_STOP; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); - } -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a Transmitter - * or a Receiver. - * This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= I2C_OAR1_ADD0; - } - else - { - /* Reset the address bit0 for write */ - Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= I2C_CR1_ACK; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= I2C_OAR2_ENDUAL; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable generall call */ - I2Cx->CR1 |= I2C_CR1_ENGC; - } - else - { - /* Disable generall call */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); - } -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @note When software reset is enabled, the I2C IOs are released (this can - * be useful to recover from bus errors). - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= I2C_CR1_SWRST; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= I2C_CR1_NOSTRETCH; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - -/** - * @brief Selects the specified I2C NACK position in master receiver mode. - * @note This function is useful in I2C Master Receiver mode when the number - * of data to be received is equal to 2. In this case, this function - * should be called (with parameter I2C_NACKPosition_Next) before data - * reception starts,as described in the 2-byte reception procedure - * recommended in Reference Manual in Section: Master receiver. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_NACKPosition: specifies the NACK position. - * This parameter can be one of the following values: - * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last - * received byte. - * @arg I2C_NACKPosition_Current: indicates that current byte is the last - * received byte. - * - * @note This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * - * @retval None - */ -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); - - /* Check the input parameter */ - if (I2C_NACKPosition == I2C_NACKPosition_Next) - { - /* Next byte in shift register is the last received byte */ - I2Cx->CR1 |= I2C_NACKPosition_Next; - } - else - { - /* Current byte in shift register is the last received byte */ - I2Cx->CR1 &= I2C_NACKPosition_Current; - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= I2C_CR1_ENARP; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); - } -} -/** - * @} - */ - -/** @defgroup I2C_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @} - */ - -/** @defgroup I2C_Group3 PEC management functions - * @brief PEC management functions - * -@verbatim - =============================================================================== - PEC management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= I2C_CR1_PEC; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * - * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() - * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() - * is intended to used in I2C mode. - * - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= I2C_CR1_ENPEC; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @} - */ - -/** @defgroup I2C_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - This section provides functions allowing to configure the I2C DMA channels - requests. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= I2C_CR2_DMAEN; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); - } -} - -/** - * @brief Specifies that the next DMA transfer is the last one. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= I2C_CR2_LAST; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); - } -} - -/** - * @} - */ - -/** @defgroup I2C_Group5 Interrupts events and flags management functions - * @brief Interrupts, events and flags management functions - * -@verbatim - =============================================================================== - Interrupts, events and flags management functions - =============================================================================== - This section provides functions allowing to configure the I2C Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - - When to use - - This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0033). - - It is also suitable for users who need to define their own events. - - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - @note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - - When to use - - This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - - The returned value could be compared to events already defined in - the library (stm32f2xx_i2c.h) or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - - At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - - When to use - - This function could be used for specific applications or in debug - phase. - - It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor - one single event. - - For detailed description of Events, please refer to section I2C_Events in - stm32f2xx_i2c.h file. - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4 - * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5 - * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9 - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f2xx_i2c.h file. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Check whether the last event contains the I2C_EVENT */ - if ((lastevent & I2C_EVENT) == I2C_EVENT) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f2xx_i2c.h file. - * - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Return status */ - return lastevent; -} - -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_MASK; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_MASK; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_MASK; - - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's interrupt pending bits. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_MASK; - - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_i2c.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Inter-integrated circuit (I2C) + * - Initialization and Configuration + * - Data transfers + * - PEC management + * - DMA transfers management + * - Interrupts, events and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE) + * function for I2C1, I2C2 or I2C3. + * + * 2. Enable SDA, SCL and SMBA (when used) GPIO clocks using + * RCC_AHBPeriphClockCmd() function. + * + * 3. Peripherals alternate function: + * - Connect the pin to the desired peripherals' Alternate + * Function (AF) using GPIO_PinAFConfig() function + * - Configure the desired pin in alternate function by: + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * Recommended configuration is Push-Pull, Pull-up, Open-Drain. + * Add an external pull up if necessary (typically 4.7 KOhm). + * + * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged + * Address using the I2C_Init() function. + * + * 5. Optionally you can enable/configure the following parameters without + * re-initialization (i.e there is no need to call again I2C_Init() function): + * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function + * - Enable the dual addressing mode using I2C_DualAddressCmd() function + * - Enable the general call using the I2C_GeneralCallCmd() function + * - Enable the clock stretching using I2C_StretchClockCmd() function + * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() + * function. + * - Configure the NACK position for Master Receiver mode in case of + * 2 bytes reception using the function I2C_NACKPositionConfig(). + * - Enable the PEC Calculation using I2C_CalculatePEC() function + * - For SMBus Mode: + * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function + * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function + * + * 6. Enable the NVIC and the corresponding interrupt using the function + * I2C_ITConfig() if you need to use interrupt mode. + * + * 7. When using the DMA mode + * - Configure the DMA using DMA_Init() function + * - Active the needed channel Request using I2C_DMACmd() or + * I2C_DMALastTransferCmd() function. + * @note When using DMA mode, I2C interrupts may be used at the same time to + * control the communication flow (Start/Stop/Ack... events and errors). + * + * 8. Enable the I2C using the I2C_Cmd() function. + * + * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the + * transfers. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TRISE */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral + input clock) must be a multiple of 10 MHz */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + + /* Test if CCR value is under 0x1*/ + if ((result & I2C_CCR_CCR) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= (uint16_t)(result | I2C_CCR_FS); + /* Set Maximum Rise Time for fast mode */ + I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= I2C_CR1_START; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= I2C_CR1_STOP; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); + } +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param Address: specifies the slave address which will be transmitted + * @param I2C_Direction: specifies whether the I2C device will be a Transmitter + * or a Receiver. + * This parameter can be one of the following values + * @arg I2C_Direction_Transmitter: Transmitter mode + * @arg I2C_Direction_Receiver: Receiver mode + * @retval None. + */ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= I2C_OAR1_ADD0; + } + else + { + /* Reset the address bit0 for write */ + Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= I2C_CR1_ACK; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param Address: specifies the 7bit I2C own address2. + * @retval None. + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); + + /* Set I2Cx Own address2 */ + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= I2C_OAR2_ENDUAL; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= I2C_CR1_ENGC; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); + } +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @note When software reset is enabled, the I2C IOs are released (this can + * be useful to recover from bus errors). + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= I2C_CR1_SWRST; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= I2C_CR1_NOSTRETCH; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_DutyCycle: specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 + * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @retval None + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + +/** + * @brief Selects the specified I2C NACK position in master receiver mode. + * @note This function is useful in I2C Master Receiver mode when the number + * of data to be received is equal to 2. In this case, this function + * should be called (with parameter I2C_NACKPosition_Next) before data + * reception starts,as described in the 2-byte reception procedure + * recommended in Reference Manual in Section: Master receiver. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_NACKPosition: specifies the NACK position. + * This parameter can be one of the following values: + * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last + * received byte. + * @arg I2C_NACKPosition_Current: indicates that current byte is the last + * received byte. + * + * @note This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * + * @retval None + */ +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); + + /* Check the input parameter */ + if (I2C_NACKPosition == I2C_NACKPosition_Next) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CR1 |= I2C_NACKPosition_Next; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CR1 &= I2C_NACKPosition_Current; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_SMBusAlert: specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low + * @arg I2C_SMBusAlert_High: SMBAlert pin driven high + * @retval None + */ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= I2C_CR1_ENARP; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); + } +} +/** + * @} + */ + +/** @defgroup I2C_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + Data transfers functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @} + */ + +/** @defgroup I2C_Group3 PEC management functions + * @brief PEC management functions + * +@verbatim + =============================================================================== + PEC management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= I2C_CR1_PEC; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_PECPosition: specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PECPosition_Next: indicates that the next byte is PEC + * @arg I2C_PECPosition_Current: indicates that current byte is PEC + * + * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() + * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() + * is intended to used in I2C mode. + * + * @retval None + */ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* Next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= I2C_CR1_ENPEC; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @retval The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->SR2) >> 8); +} + +/** + * @} + */ + +/** @defgroup I2C_Group4 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + DMA transfers management functions + =============================================================================== + This section provides functions allowing to configure the I2C DMA channels + requests. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); + } +} + +/** + * @brief Specifies that the next DMA transfer is the last one. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CR2 |= I2C_CR2_LAST; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); + } +} + +/** + * @} + */ + +/** @defgroup I2C_Group5 Interrupts events and flags management functions + * @brief Interrupts, events and flags management functions + * +@verbatim + =============================================================================== + Interrupts, events and flags management functions + =============================================================================== + This section provides functions allowing to configure the I2C Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + =============================================================================== + I2C State Monitoring Functions + =============================================================================== + This I2C driver provides three different ways for I2C state monitoring + depending on the application requirements and constraints: + + + 1. Basic state monitoring (Using I2C_CheckEvent() function) + ----------------------------------------------------------- + It compares the status registers (SR1 and SR2) content to a given event + (can be the combination of one or more flags). + It returns SUCCESS if the current status includes the given flags + and returns ERROR if one or more flags are missing in the current status. + + - When to use + - This function is suitable for most applications as well as for startup + activity since the events are fully described in the product reference + manual (RM0033). + - It is also suitable for users who need to define their own events. + + - Limitations + - If an error occurs (ie. error flags are set besides to the monitored + flags), the I2C_CheckEvent() function may return SUCCESS despite + the communication hold or corrupted real state. + In this case, it is advised to use error interrupts to monitor + the error events and handle them in the interrupt IRQ handler. + + @note + For error management, it is advised to use the following functions: + - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + Where x is the peripheral instance (I2C1, I2C2 ...) + - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the + I2Cx_ER_IRQHandler() function in order to determine which error occurred. + - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + and/or I2C_GenerateStop() in order to clear the error flag and source + and return to correct communication status. + + + 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) + -------------------------------------------------------------------- + Using the function I2C_GetLastEvent() which returns the image of both status + registers in a single word (uint32_t) (Status Register 2 value is shifted left + by 16 bits and concatenated to Status Register 1). + + - When to use + - This function is suitable for the same applications above but it + allows to overcome the mentioned limitation of I2C_GetFlagStatus() + function. + - The returned value could be compared to events already defined in + the library (stm32f2xx_i2c.h) or to custom values defined by user. + This function is suitable when multiple flags are monitored at the + same time. + - At the opposite of I2C_CheckEvent() function, this function allows + user to choose when an event is accepted (when all events flags are + set and no other flags are set or just when the needed flags are set + like I2C_CheckEvent() function. + + - Limitations + - User may need to define his own events. + - Same remark concerning the error management is applicable for this + function if user decides to check only regular communication flags + (and ignores error flags). + + + 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) + ----------------------------------------------------------------------- + + Using the function I2C_GetFlagStatus() which simply returns the status of + one single flag (ie. I2C_FLAG_RXNE ...). + + - When to use + - This function could be used for specific applications or in debug + phase. + - It is suitable when only one flag checking is needed (most I2C + events are monitored through multiple flags). + - Limitations: + - When calling this function, the Status register is accessed. + Some flags are cleared when the status register is accessed. + So checking the status of one Flag, may clear other ones. + - Function may need to be called twice or more in order to monitor + one single event. + + For detailed description of Events, please refer to section I2C_Events in + stm32f2xx_i2c.h file. + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_BUF: Buffer interrupt mask + * @arg I2C_IT_EVT: Event interrupt mask + * @arg I2C_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (uint16_t)~I2C_IT; + } +} + +/* + =============================================================================== + 1. Basic state monitoring + =============================================================================== + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9 + * + * @note For detailed description of Events, please refer to section I2C_Events + * in stm32f2xx_i2c.h file. + * + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/* + =============================================================================== + 2. Advanced state monitoring + =============================================================================== + */ + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * + * @note For detailed description of Events, please refer to section I2C_Events + * in stm32f2xx_i2c.h file. + * + * @retval The last event + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Return status */ + return lastevent; +} + +/* + =============================================================================== + 3. Flag-based state monitoring + =============================================================================== + */ + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_FLAG_SB: Start bit flag (Master mode) + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_MASK; + + if(i2creg != 0) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx SR2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx SR2 register address */ + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @note STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * @note ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DR register. + * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * @note ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR + * register (I2C_SendData()). + * + * @retval None + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_MASK; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert flag + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_IT_PECERR: PEC error in reception flag + * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure flag + * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_IT_BERR: Bus error flag + * @arg I2C_IT_TXE: Data register empty flag (Transmitter) + * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag + * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) + * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_IT_BTF: Byte transfer finished flag + * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_IT_SB: Start bit flag (Master mode) + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_MASK; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's interrupt pending bits. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert interrupt + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt + * @arg I2C_IT_PECERR: PEC error in reception interrupt + * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure interrupt + * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) + * @arg I2C_IT_BERR: Bus error interrupt + * + * @note STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * @note ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DR register. + * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * @note ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * @note SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DR register (I2C_SendData()). + * @retval None + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_MASK; + + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c index de89eac04..3939a1791 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c @@ -1,269 +1,269 @@ -/** - ****************************************************************************** - * @file stm32f2xx_iwdg.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Independent watchdog (IWDG) peripheral: - * - Prescaler and Counter configuration - * - IWDG activation - * - Flag management - * - * @verbatim - * - * =================================================================== - * IWDG features - * =================================================================== - * - * The IWDG can be started by either software or hardware (configurable - * through option byte). - * - * The IWDG is clocked by its own dedicated low-speed clock (LSI) and - * thus stays active even if the main clock fails. - * Once the IWDG is started, the LSI is forced ON and cannot be disabled - * (LSI cannot be disabled too), and the counter starts counting down from - * the reset value of 0xFFF. When it reaches the end of count value (0x000) - * a system reset is generated. - * The IWDG counter should be reloaded at regular intervals to prevent - * an MCU reset. - * - * The IWDG is implemented in the VDD voltage domain that is still functional - * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - * - * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG - * reset occurs. - * - * Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - * The IWDG timeout may vary due to LSI frequency dispersion. STM32F2xx - * devices provide the capability to measure the LSI frequency (LSI clock - * connected internally to TIM5 CH4 input capture). The measured value - * can be used to have an IWDG timeout with an acceptable accuracy. - * For more information, please refer to the STM32F2xx Reference manual - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable write access to IWDG_PR and IWDG_RLR registers using - * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function - * - * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function - * - * 3. Configure the IWDG counter value using IWDG_SetReload() function. - * This value will be loaded in the IWDG counter each time the counter - * is reloaded, then the IWDG will start counting down from this value. - * - * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used - * in software mode (no need to enable the LSI, it will be enabled - * by hardware) - * - * 5. Then the application program must reload the IWDG counter at regular - * intervals during normal operation to prevent an MCU reset, using - * IWDG_ReloadCounter() function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_iwdg.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint16_t)0xAAAA) -#define KR_KEY_ENABLE ((uint16_t)0xCCCC) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions - * @brief Prescaler and Counter configuration functions - * -@verbatim - =============================================================================== - Prescaler and Counter configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_RELOAD; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group2 IWDG activation function - * @brief IWDG activation function - * -@verbatim - =============================================================================== - IWDG activation function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_ENABLE; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group3 Flag management function - * @brief Flag management function - * -@verbatim - =============================================================================== - Flag management function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_iwdg.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Independent watchdog (IWDG) peripheral: + * - Prescaler and Counter configuration + * - IWDG activation + * - Flag management + * + * @verbatim + * + * =================================================================== + * IWDG features + * =================================================================== + * + * The IWDG can be started by either software or hardware (configurable + * through option byte). + * + * The IWDG is clocked by its own dedicated low-speed clock (LSI) and + * thus stays active even if the main clock fails. + * Once the IWDG is started, the LSI is forced ON and cannot be disabled + * (LSI cannot be disabled too), and the counter starts counting down from + * the reset value of 0xFFF. When it reaches the end of count value (0x000) + * a system reset is generated. + * The IWDG counter should be reloaded at regular intervals to prevent + * an MCU reset. + * + * The IWDG is implemented in the VDD voltage domain that is still functional + * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + * + * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG + * reset occurs. + * + * Min-max timeout value @32KHz (LSI): ~125us / ~32.7s + * The IWDG timeout may vary due to LSI frequency dispersion. STM32F2xx + * devices provide the capability to measure the LSI frequency (LSI clock + * connected internally to TIM5 CH4 input capture). The measured value + * can be used to have an IWDG timeout with an acceptable accuracy. + * For more information, please refer to the STM32F2xx Reference manual + * + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable write access to IWDG_PR and IWDG_RLR registers using + * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function + * + * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function + * + * 3. Configure the IWDG counter value using IWDG_SetReload() function. + * This value will be loaded in the IWDG counter each time the counter + * is reloaded, then the IWDG will start counting down from this value. + * + * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used + * in software mode (no need to enable the LSI, it will be enabled + * by hardware) + * + * 5. Then the application program must reload the IWDG counter at regular + * intervals during normal operation to prevent an MCU reset, using + * IWDG_ReloadCounter() function. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_iwdg.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_RELOAD ((uint16_t)0xAAAA) +#define KR_KEY_ENABLE ((uint16_t)0xCCCC) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions + * @brief Prescaler and Counter configuration functions + * +@verbatim + =============================================================================== + Prescaler and Counter configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_RELOAD; +} + +/** + * @} + */ + +/** @defgroup IWDG_Group2 IWDG activation function + * @brief IWDG activation function + * +@verbatim + =============================================================================== + IWDG activation function + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_ENABLE; +} + +/** + * @} + */ + +/** @defgroup IWDG_Group3 Flag management function + * @brief Flag management function + * +@verbatim + =============================================================================== + Flag management function + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c index 1c84cf75d..99ad2dc83 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c @@ -1,620 +1,620 @@ -/** - ****************************************************************************** - * @file stm32f2xx_pwr.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * - Backup Domain Access - * - PVD configuration - * - WakeUp pin configuration - * - Backup Regulator configuration - * - FLASH Power Down configuration - * - Low Power modes configuration - * - Flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_pwr.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* Alias word address of FPDS bit */ -#define FPDS_BitNumber 0x09 -#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* Alias word address of BRE bit */ -#define BRE_BitNumber 0x09 -#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** @defgroup PWR_Group1 Backup Domain Access function - * @brief Backup Domain Access function - * -@verbatim - =============================================================================== - Backup Domain Access function - =============================================================================== - - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - - Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - - Enable access to RTC domain using the PWR_BackupAccessCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @param NewState: new state of the access to the backup domain. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group2 PVD configuration functions - * @brief PVD configuration functions - * -@verbatim - =============================================================================== - PVD configuration functions - =============================================================================== - - - The PVD is used to monitor the VDD power supply by comparing it to a threshold - selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the - PVD threshold. This event is internally connected to the EXTI line16 - and can generate an interrupt if enabled through the EXTI registers. - - The PVD is stopped in Standby mode. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_0 - * @arg PWR_PVDLevel_1 - * @arg PWR_PVDLevel_2 - * @arg PWR_PVDLevel_3 - * @arg PWR_PVDLevel_4 - * @arg PWR_PVDLevel_5 - * @arg PWR_PVDLevel_6 - * @arg PWR_PVDLevel_7 - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - - tmpreg = PWR->CR; - - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group3 WakeUp pin configuration functions - * @brief WakeUp pin configuration functions - * -@verbatim - =============================================================================== - WakeUp pin configuration functions - =============================================================================== - - - WakeUp pin is used to wakeup the system from Standby mode. This pin is - forced in input pull down configuration and is active on rising edges. - - There is only one WakeUp pin: WakeUp Pin 1 on PA.00. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group4 Backup Regulator configuration functions - * @brief Backup Regulator configuration functions - * -@verbatim - =============================================================================== - Backup Regulator configuration functions - =============================================================================== - - - The backup domain includes 4 Kbytes of backup SRAM accessible only from the - CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained - even in Standby or VBAT mode when the low power backup regulator is enabled. - It can be considered as an internal EEPROM when VBAT is always present. - You can use the PWR_BackupRegulatorCmd() function to enable the low power - backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is - ready or not. - - - When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to - save battery life. - - - The backup SRAM is not mass erased by an tamper event. It is read protected - to prevent confidential data, such as cryptographic private key, from being - accessed. The backup SRAM can be erased only through the Flash interface when - a protection level change from level 1 to level 0 is requested. - Refer to the description of Read protection (RDP) in the Flash programming manual. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Backup Regulator. - * @param NewState: new state of the Backup Regulator. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupRegulatorCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group5 FLASH Power Down configuration functions - * @brief FLASH Power Down configuration functions - * -@verbatim - =============================================================================== - FLASH Power Down configuration functions - =============================================================================== - - - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd() - function, the Flash memory also enters power down mode when the device enters - Stop mode. When the Flash memory is in power down mode, an additional startup - delay is incurred when waking up from Stop mode. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Flash Power Down in STOP mode. - * @param NewState: new state of the Flash power mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_FlashPowerDownCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group6 Low Power modes configuration functions - * @brief Low Power modes configuration functions - * -@verbatim - =============================================================================== - Low Power modes configuration functions - =============================================================================== - - The devices feature 3 low-power modes: - - Sleep mode: Cortex-M3 core stopped, peripherals kept running. - - Stop mode: all clocks are stopped, regulator running, regulator in low power mode - - Standby mode: 1.2V domain powered off. - - Sleep mode - =========== - - Entry: - - The Sleep mode is entered by using the __WFI() or __WFE() functions. - - Exit: - - Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - Stop mode - ========== - In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before - entering the Stop mode. It can be switched on again by software after exiting - the Stop mode using the PWR_FlashPowerDownCmd() function. - - - Entry: - - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) - function with regulator in LowPower or with Regulator ON. - - Exit: - - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - - Standby mode - ============ - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. - The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby - circuitry. - - The voltage regulator is OFF. - - - Entry: - - The Standby mode is entered using the PWR_EnterSTANDBYMode() function. - - Exit: - - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - Auto-wakeup (AWU) from low-power mode - ===================================== - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - - RTC auto-wakeup (AWU) from the Stop mode - ---------------------------------------- - - - To wake up from the Stop mode with an RTC alarm event, it is necessary to: - - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - - To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - - Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: - - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - - RTC auto-wakeup (AWU) from the Standby mode - ------------------------------------------- - - To wake up from the Standby mode with an RTC alarm event, it is necessary to: - - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - - To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - - Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: - - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enters STOP mode. - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDSR bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDSR bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. - * - WKUP pin 1 (PA0) if enabled. - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Clear Wakeup flag */ - PWR->CR |= PWR_CR_CWUF; - - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @} - */ - -/** @defgroup PWR_Group7 Flags management functions - * @brief Flags management functions - * -@verbatim - =============================================================================== - Flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A - * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_pwr.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * - Backup Domain Access + * - PVD configuration + * - WakeUp pin configuration + * - Backup Regulator configuration + * - FLASH Power Down configuration + * - Low Power modes configuration + * - Flags management + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* Alias word address of FPDS bit */ +#define FPDS_BitNumber 0x09 +#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* Alias word address of BRE bit */ +#define BRE_BitNumber 0x09 +#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** @defgroup PWR_Group1 Backup Domain Access function + * @brief Backup Domain Access function + * +@verbatim + =============================================================================== + Backup Domain Access function + =============================================================================== + + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + - Enable the Power Controller (PWR) APB1 interface clock using the + RCC_APB1PeriphClockCmd() function. + - Enable access to RTC domain using the PWR_BackupAccessCmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @param NewState: new state of the access to the backup domain. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group2 PVD configuration functions + * @brief PVD configuration functions + * +@verbatim + =============================================================================== + PVD configuration functions + =============================================================================== + + - The PVD is used to monitor the VDD power supply by comparing it to a threshold + selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the + PVD threshold. This event is internally connected to the EXTI line16 + and can generate an interrupt if enabled through the EXTI registers. + - The PVD is stopped in Standby mode. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_0 + * @arg PWR_PVDLevel_1 + * @arg PWR_PVDLevel_2 + * @arg PWR_PVDLevel_3 + * @arg PWR_PVDLevel_4 + * @arg PWR_PVDLevel_5 + * @arg PWR_PVDLevel_6 + * @arg PWR_PVDLevel_7 + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + + tmpreg = PWR->CR; + + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_MASK; + + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group3 WakeUp pin configuration functions + * @brief WakeUp pin configuration functions + * +@verbatim + =============================================================================== + WakeUp pin configuration functions + =============================================================================== + + - WakeUp pin is used to wakeup the system from Standby mode. This pin is + forced in input pull down configuration and is active on rising edges. + - There is only one WakeUp pin: WakeUp Pin 1 on PA.00. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group4 Backup Regulator configuration functions + * @brief Backup Regulator configuration functions + * +@verbatim + =============================================================================== + Backup Regulator configuration functions + =============================================================================== + + - The backup domain includes 4 Kbytes of backup SRAM accessible only from the + CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained + even in Standby or VBAT mode when the low power backup regulator is enabled. + It can be considered as an internal EEPROM when VBAT is always present. + You can use the PWR_BackupRegulatorCmd() function to enable the low power + backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is + ready or not. + + - When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to + save battery life. + + - The backup SRAM is not mass erased by an tamper event. It is read protected + to prevent confidential data, such as cryptographic private key, from being + accessed. The backup SRAM can be erased only through the Flash interface when + a protection level change from level 1 to level 0 is requested. + Refer to the description of Read protection (RDP) in the Flash programming manual. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the Backup Regulator. + * @param NewState: new state of the Backup Regulator. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupRegulatorCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group5 FLASH Power Down configuration functions + * @brief FLASH Power Down configuration functions + * +@verbatim + =============================================================================== + FLASH Power Down configuration functions + =============================================================================== + + - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd() + function, the Flash memory also enters power down mode when the device enters + Stop mode. When the Flash memory is in power down mode, an additional startup + delay is incurred when waking up from Stop mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the Flash Power Down in STOP mode. + * @param NewState: new state of the Flash power mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_FlashPowerDownCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group6 Low Power modes configuration functions + * @brief Low Power modes configuration functions + * +@verbatim + =============================================================================== + Low Power modes configuration functions + =============================================================================== + + The devices feature 3 low-power modes: + - Sleep mode: Cortex-M3 core stopped, peripherals kept running. + - Stop mode: all clocks are stopped, regulator running, regulator in low power mode + - Standby mode: 1.2V domain powered off. + + Sleep mode + =========== + - Entry: + - The Sleep mode is entered by using the __WFI() or __WFE() functions. + - Exit: + - Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + Stop mode + ========== + In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption In Stop mode, FLASH can be powered off before + entering the Stop mode. It can be switched on again by software after exiting + the Stop mode using the PWR_FlashPowerDownCmd() function. + + - Entry: + - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) + function with regulator in LowPower or with Regulator ON. + - Exit: + - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + Standby mode + ============ + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. + The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby + circuitry. + + The voltage regulator is OFF. + + - Entry: + - The Standby mode is entered using the PWR_EnterSTANDBYMode() function. + - Exit: + - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + Auto-wakeup (AWU) from low-power mode + ===================================== + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event, a time-stamp event, or a comparator event, + without depending on an external interrupt (Auto-wakeup mode). + + - RTC auto-wakeup (AWU) from the Stop mode + ---------------------------------------- + + - To wake up from the Stop mode with an RTC alarm event, it is necessary to: + - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function + - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + - To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to: + - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function + - Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: + - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function + - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), + RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + + - RTC auto-wakeup (AWU) from the Standby mode + ------------------------------------------- + - To wake up from the Standby mode with an RTC alarm event, it is necessary to: + - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function + - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + - To wake up from the Standby mode with an RTC Tamper or time stamp event, it + is necessary to: + - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function + - Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: + - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function + - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), + RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enters STOP mode. + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDSR bits */ + tmpreg &= CR_DS_MASK; + + /* Set LPDSR bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters STANDBY mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. + * - WKUP pin 1 (PA0) if enabled. + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wakeup flag */ + PWR->CR |= PWR_CR_CWUF; + + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @} + */ + +/** @defgroup PWR_Group7 Flags management functions + * @brief Flags management functions + * +@verbatim + =============================================================================== + Flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A + * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c index c5b26daf8..2dd960a33 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c @@ -1,1817 +1,1817 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rcc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Reset and clock control (RCC) peripheral: - * - Internal/external clocks, PLL, CSS and MCO configuration - * - System, AHB and APB busses clocks configuration - * - Peripheral clocks configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * RCC specific features - * =================================================================== - * - * After reset the device is running from Internal High Speed oscillator - * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache - * and I-Cache are disabled, and all peripherals are off except internal - * SRAM, Flash and JTAG. - * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; - * all peripherals mapped on these busses are running at HSI speed. - * - The clock for all peripherals is switched off, except the SRAM and FLASH. - * - All GPIOs are in input floating state, except the JTAG pins which - * are assigned to be used for debug purpose. - * - * Once the device started from reset, the user application has to: - * - Configure the clock source to be used to drive the System clock - * (if the application needs higher frequency/performance) - * - Configure the System clock frequency and Flash settings - * - Configure the AHB and APB busses prescalers - * - Enable the clock for the peripheral(s) to be used - * - Configure the clock source(s) for peripherals which clocks are not - * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) -/* Alias word address of PLLI2SON bit */ -#define PLLI2SON_BitNumber 0x1A -#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) - -/* --- CFGR Register ---*/ -/* Alias word address of I2SSRC bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x08) -#define I2SSRC_BitNumber 0x17 -#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) - -/* --- BDCR Register ---*/ -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x70) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x74) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) -/* ---------------------- RCC registers bit mask ------------------------ */ -/* CFGR register bit mask */ -#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) -#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) - -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/* CR register byte 3 (Bits[23:16]) base address */ -#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions - * @brief Internal and external clocks, PLL, CSS and MCO configuration functions - * -@verbatim - =============================================================================== - Internal/external clocks, PLL, CSS and MCO configuration functions - =============================================================================== - - This section provide functions allowing to configure the internal/external clocks, - PLLs, CSS and MCO pins. - - 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - 5. PLL (clocked by HSI or HSE), featuring two different output clocks: - - The first output is used to generate the high speed system clock (up to 120 MHz) - - The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - - 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve - high-quality audio performance on the I2S interface. - - 7. CSS (Clock security system), once enable and if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) - exception vector. - - 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL - clock (through a configurable prescaler) on PA8 pin. - - 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S - clock (through a configurable prescaler) on PC9 pin. - -@endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL and PLLI2S OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the Clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint8_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; - - /* Set the new HSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; -} - -/** - * @brief Waits for HSE start-up. - * @note This functions waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached - * and this flag is not set. The timeout value is defined by the constant - * HSE_STARTUP_TIMEOUT in stm32f2xx.h file. You can tailor it depending - * on the HSE crystal used in your application. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t startupcounter = 0; - ErrorStatus status = ERROR; - FlagStatus hsestatus = RESET; - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - startupcounter++; - } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - - tmpreg = RCC->CR; - - /* Clear HSITRIM[4:0] bits */ - tmpreg &= ~RCC_CR_HSITRIM; - - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @param NewState: new state of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch (RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * - * @param PLLM: specifies the division factor for PLL VCO input clock - * This parameter must be a number between 0 and 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * - * @param PLLN: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLP: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on - * the System clock frequency. - * - * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between 4 and 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(PLLM)); - assert_param(IS_RCC_PLLN_VALUE(PLLN)); - assert_param(IS_RCC_PLLP_VALUE(PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); - - RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | - (PLLQ << 24); -} - -/** - * @brief Enables or disables the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note PLLI2S is available only in Silicon RevisionB and RevisionY. - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); -} - -/** - * @brief Enables or disables the PLLI2S. - * @note PLLI2S is available only in RevisionB and RevisionY - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLI2SCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. - * @param NewState: new state of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO1 pin(PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCO1Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source - * @param RCC_MCO1Div: specifies the MCO1 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO1Div_1: no division applied to MCO1 clock - * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock - * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock - * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock - * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock - * @retval None - */ -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); - assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ - tmpreg &= CFGR_MCO1_RESET_MASK; - - /* Select MCO1 clock source and prescaler */ - tmpreg |= RCC_MCO1Source | RCC_MCO1Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Selects the clock source to output on MCO2 pin(PC9). - * @note PC9 should be configured in alternate function mode. - * @param RCC_MCO2Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source - * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCO2Div: specifies the MCO2 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO2Div_1: no division applied to MCO2 clock - * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock - * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock - * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock - * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock - * @retval None - */ -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); - assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO2 and MCO2PRE[2:0] bits */ - tmpreg &= CFGR_MCO2_RESET_MASK; - - /* Select MCO2 clock source and prescaler */ - tmpreg |= RCC_MCO2Source | RCC_MCO2Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @} - */ - -/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions - * @brief System, AHB and APB busses clocks configuration functions - * -@verbatim - =============================================================================== - System, AHB and APB busses clocks configuration functions - =============================================================================== - - This section provide functions allowing to configure the System, AHB, APB1 and - APB2 busses clocks. - - 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable prescaler - and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). - APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through - configurable prescalers and used to clock the peripherals mapped on these busses. - You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. - -@note All the peripheral clocks are derived from the System clock (SYSCLK) except: - - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. - You have to use RCC_I2SCLKConfig() function to configure this clock. - - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() - functions to configure this clock. - - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly, while the SDIO require a frequency equal or lower than - to 48. This clock is derived of the main PLL through PLLQ divider. - - IWDG clock which is always the LSI clock. - - 2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz. - Depending on the device voltage range, the maximum frequency should be - adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| - +-------------------------------------------------------------------------------------+ - - -@endverbatim - * @{ - */ - -/** - * @brief Configures the system clock (SYSCLK). - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - - tmpreg = RCC->CFGR; - - /* Clear SW[1:0] bits */ - tmpreg &= ~RCC_CFGR_SW; - - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @note Depending on the device voltage range, the software has to set correctly - * these bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above - * "CPU, AHB and APB busses clocks configuration functions") - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - - tmpreg = RCC->CFGR; - - /* Clear HPRE[3:0] bits */ - tmpreg &= ~RCC_CFGR_HPRE; - - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE1[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE1; - - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE2[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE2; - - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, - * PCLK1 and PCLK2. - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function - * must be called to update the structure's field. Otherwise, any - * configuration based on this function will be incorrect. - * - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; - break; - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ - - /* Get HCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_HPRE; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE1; - tmp = tmp >> 10; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE2; - tmp = tmp >> 13; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; -} - -/** - * @} - */ - -/** @defgroup RCC_Group3 Peripheral clocks configuration functions - * @brief Peripheral clocks configuration functions - * -@verbatim - =============================================================================== - Peripheral clocks configuration functions - =============================================================================== - - This section provide functions allowing to configure the Peripheral clocks. - - 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. - - 2. After restart from Reset or wakeup from STANDBY, all peripherals are off - except internal SRAM, Flash and JTAG. Before to start using a peripheral you - have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd() - , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. - - 3. To reset the peripherals configuration (to the default state after device reset) - you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and - RCC_APB1PeriphResetCmd() functions. - - 4. To further reduce power consumption in SLEEP mode the peripheral clocks can - be disabled prior to executing the WFI or WFE instructions. You can do this - using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and - RCC_APB1PeriphClockLPModeCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using PWR_BackupAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using RCC_BackupResetCmd() function, or by - * a Power On Reset (POR). - * - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - * - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - - if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) - { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ - tmpreg = RCC->CFGR; - - /* Clear RTCPRE[4:0] bits */ - tmpreg &= ~RCC_CFGR_RTCPRE; - - /* Configure HSE division factor for RTC clock */ - tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); - - /* Store the new value */ - RCC->CFGR = tmpreg; - } - - /* Select the RTC clock source */ - RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock source was selected - * using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Forces or releases the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the I2S clock source (I2SCLK). - * - * @note This function must be called before enabling the I2S APB clock. - * @note This function applies only to Silicon RevisionB and RevisionY. - * - * @param RCC_I2SCLKSource: specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source - * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as I2S clock source - * @retval None - */ -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - - *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; -} - -/** - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1ENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1ENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2ENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2ENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3ENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3ENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases AHB1 peripheral reset. - * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB1RSTR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1RSTR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Forces or releases AHB2 peripheral reset. - * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2RSTR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2RSTR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Forces or releases AHB3 peripheral reset. - * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3RSTR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3RSTR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1LPENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1LPENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB2LPENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2LPENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB3LPENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3LPENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1LPENR |= RCC_APB1Periph; - } - else - { - RCC->APB1LPENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2LPENR |= RCC_APB2Periph; - } - else - { - RCC->APB2LPENR &= ~RCC_APB2Periph; - } -} - -/** - * @} - */ - -/** @defgroup RCC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: main PLL clock ready - * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_MASK; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= RCC_CSR_RMVF; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_rcc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Reset and clock control (RCC) peripheral: + * - Internal/external clocks, PLL, CSS and MCO configuration + * - System, AHB and APB busses clocks configuration + * - Peripheral clocks configuration + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * RCC specific features + * =================================================================== + * + * After reset the device is running from Internal High Speed oscillator + * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + * and I-Cache are disabled, and all peripherals are off except internal + * SRAM, Flash and JTAG. + * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; + * all peripherals mapped on these busses are running at HSI speed. + * - The clock for all peripherals is switched off, except the SRAM and FLASH. + * - All GPIOs are in input floating state, except the JTAG pins which + * are assigned to be used for debug purpose. + * + * Once the device started from reset, the user application has to: + * - Configure the clock source to be used to drive the System clock + * (if the application needs higher frequency/performance) + * - Configure the System clock frequency and Flash settings + * - Configure the AHB and APB busses prescalers + * - Enable the clock for the peripheral(s) to be used + * - Configure the clock source(s) for peripherals which clocks are not + * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) +/* Alias word address of PLLI2SON bit */ +#define PLLI2SON_BitNumber 0x1A +#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) + +/* --- CFGR Register ---*/ +/* Alias word address of I2SSRC bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x08) +#define I2SSRC_BitNumber 0x17 +#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) + +/* --- BDCR Register ---*/ +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x70) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x74) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) +/* ---------------------- RCC registers bit mask ------------------------ */ +/* CFGR register bit mask */ +#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) +#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) + +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CR register byte 3 (Bits[23:16]) base address */ +#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions + * @brief Internal and external clocks, PLL, CSS and MCO configuration functions + * +@verbatim + =============================================================================== + Internal/external clocks, PLL, CSS and MCO configuration functions + =============================================================================== + + This section provide functions allowing to configure the internal/external clocks, + PLLs, CSS and MCO pins. + + 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + 5. PLL (clocked by HSI or HSE), featuring two different output clocks: + - The first output is used to generate the high speed system clock (up to 120 MHz) + - The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + + 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve + high-quality audio performance on the I2S interface. + + 7. CSS (Clock security system), once enable and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) + exception vector. + + 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL and PLLI2S OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the Clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint8_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; + + /* Set the new HSE configuration -------------------------------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; +} + +/** + * @brief Waits for HSE start-up. + * @note This functions waits on HSERDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * HSE_STARTUP_TIMEOUT in stm32f2xx.h file. You can tailor it depending + * on the HSE crystal used in your application. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t startupcounter = 0; + ErrorStatus status = ERROR; + FlagStatus hsestatus = RESET; + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + startupcounter++; + } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->CR; + + /* Clear HSITRIM[4:0] bits */ + tmpreg &= ~RCC_CR_HSITRIM; + + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @param NewState: new state of the HSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch (RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param RCC_PLLSource: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * + * @param PLLM: specifies the division factor for PLL VCO input clock + * This parameter must be a number between 0 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + * @param PLLN: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLP: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on + * the System clock frequency. + * + * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between 4 and 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(PLLM)); + assert_param(IS_RCC_PLLN_VALUE(PLLN)); + assert_param(IS_RCC_PLLP_VALUE(PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); + + RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | + (PLLQ << 24); +} + +/** + * @brief Enables or disables the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLLI2S clock multiplication and division factors. + * + * @note PLLI2S is available only in Silicon RevisionB and RevisionY. + * @note This function must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLI2SR: specifies the division factor for I2S clock + * This parameter must be a number between 2 and 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @retval None + */ +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); + + RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); +} + +/** + * @brief Enables or disables the PLLI2S. + * @note PLLI2S is available only in RevisionB and RevisionY + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLI2SCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. + * @param NewState: new state of the Clock Security System. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8). + * @note PA8 should be configured in alternate function mode. + * @param RCC_MCO1Source: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source + * @param RCC_MCO1Div: specifies the MCO1 prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO1Div_1: no division applied to MCO1 clock + * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock + * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock + * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock + * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock + * @retval None + */ +void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); + assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); + + tmpreg = RCC->CFGR; + + /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ + tmpreg &= CFGR_MCO1_RESET_MASK; + + /* Select MCO1 clock source and prescaler */ + tmpreg |= RCC_MCO1Source | RCC_MCO1Div; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Selects the clock source to output on MCO2 pin(PC9). + * @note PC9 should be configured in alternate function mode. + * @param RCC_MCO2Source: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source + * @param RCC_MCO2Div: specifies the MCO2 prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO2Div_1: no division applied to MCO2 clock + * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock + * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock + * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock + * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock + * @retval None + */ +void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); + assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); + + tmpreg = RCC->CFGR; + + /* Clear MCO2 and MCO2PRE[2:0] bits */ + tmpreg &= CFGR_MCO2_RESET_MASK; + + /* Select MCO2 clock source and prescaler */ + tmpreg |= RCC_MCO2Source | RCC_MCO2Div; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @} + */ + +/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions + * @brief System, AHB and APB busses clocks configuration functions + * +@verbatim + =============================================================================== + System, AHB and APB busses clocks configuration functions + =============================================================================== + + This section provide functions allowing to configure the System, AHB, APB1 and + APB2 busses clocks. + + 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable prescaler + and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). + APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through + configurable prescalers and used to clock the peripherals mapped on these busses. + You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. + +@note All the peripheral clocks are derived from the System clock (SYSCLK) except: + - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or + from an external clock mapped on the I2S_CKIN pin. + You have to use RCC_I2SCLKConfig() function to configure this clock. + - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() + functions to configure this clock. + - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly, while the SDIO require a frequency equal or lower than + to 48. This clock is derived of the main PLL through PLLQ divider. + - IWDG clock which is always the LSI clock. + + 2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz. + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| + +-------------------------------------------------------------------------------------+ + + +@endverbatim + * @{ + */ + +/** + * @brief Configures the system clock (SYSCLK). + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use RCC_GetSYSCLKSource() function to know which clock is + * currently used as system clock source. + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= ~RCC_CFGR_SW; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @note Depending on the device voltage range, the software has to set correctly + * these bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above + * "CPU, AHB and APB busses clocks configuration functions") + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[3:0] bits */ + tmpreg &= ~RCC_CFGR_HPRE; + + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE1[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE1; + + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE2[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE2; + + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, + * PCLK1 and PCLK2. + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function + * must be called to update the structure's field. Otherwise, any + * configuration based on this function will be incorrect. + * + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; + break; + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ + + /* Get HCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_HPRE; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE1; + tmp = tmp >> 10; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE2; + tmp = tmp >> 13; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; +} + +/** + * @} + */ + +/** @defgroup RCC_Group3 Peripheral clocks configuration functions + * @brief Peripheral clocks configuration functions + * +@verbatim + =============================================================================== + Peripheral clocks configuration functions + =============================================================================== + + This section provide functions allowing to configure the Peripheral clocks. + + 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. + + 2. After restart from Reset or wakeup from STANDBY, all peripherals are off + except internal SRAM, Flash and JTAG. Before to start using a peripheral you + have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd() + , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. + + 3. To reset the peripherals configuration (to the default state after device reset) + you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and + RCC_APB1PeriphResetCmd() functions. + + 4. To further reduce power consumption in SLEEP mode the peripheral clocks can + be disabled prior to executing the WFI or WFE instructions. You can do this + using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and + RCC_APB1PeriphClockLPModeCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using PWR_BackupAccessCmd(ENABLE) function before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using RCC_BackupResetCmd() function, or by + * a Power On Reset (POR). + * + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) + { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ + tmpreg = RCC->CFGR; + + /* Clear RTCPRE[4:0] bits */ + tmpreg &= ~RCC_CFGR_RTCPRE; + + /* Configure HSE division factor for RTC clock */ + tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); + + /* Store the new value */ + RCC->CFGR = tmpreg; + } + + /* Select the RTC clock source */ + RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock source was selected + * using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Forces or releases the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the I2S clock source (I2SCLK). + * + * @note This function must be called before enabling the I2S APB clock. + * @note This function applies only to Silicon RevisionB and RevisionY. + * + * @param RCC_I2SCLKSource: specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source + * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as I2S clock source + * @retval None + */ +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); + + *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; +} + +/** + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock + * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock + * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB1ENR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1ENR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2ENR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2ENR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. + * This parameter must be: RCC_AHB3Periph_FSMC + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3ENR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3ENR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases AHB1 peripheral reset. + * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB1RSTR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1RSTR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Forces or releases AHB2 peripheral reset. + * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2RSTR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2RSTR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Forces or releases AHB3 peripheral reset. + * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. + * This parameter must be: RCC_AHB3Periph_FSMC + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3RSTR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3RSTR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock + * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock + * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB1LPENR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1LPENR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB2LPENR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2LPENR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. + * This parameter must be: RCC_AHB3Periph_FSMC + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB3LPENR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3LPENR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1LPENR |= RCC_APB1Periph; + } + else + { + RCC->APB1LPENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2LPENR |= RCC_APB2Periph; + } + else + { + RCC->APB2LPENR &= ~RCC_APB2Periph; + } +} + +/** + * @} + */ + +/** @defgroup RCC_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: main PLL clock ready + * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= RCC_CSR_RMVF; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c index 99d88b22d..9f0d6c291 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c @@ -1,405 +1,405 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rng.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Random Number Generator (RNG) peripheral: - * - Initialization and Configuration - * - Get 32 bit Random number - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The RNG controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. - * - * 2. Activate the RNG peripheral using RNG_Cmd() function. - * - * 3. Wait until the 32 bit Random number Generator contains a valid - * random data (using polling/interrupt mode). For more details, - * refer to "Interrupts and flags management functions" module - * description. - * - * 4. Get the 32 bit Random number using RNG_GetRandomNumber() function - * - * 5. To get another 32 bit Random number, go to step 3. - * - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_rng.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RNG - * @brief RNG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RNG_Private_Functions - * @{ - */ - -/** @defgroup RNG_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the RNG peripheral - - Enable or disable the RNG peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RNG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void RNG_DeInit(void) -{ - /* Enable RNG reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); - - /* Release RNG from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE); -} - -/** - * @brief Enables or disables the RNG peripheral. - * @param NewState: new state of the RNG peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG */ - RNG->CR |= RNG_CR_RNGEN; - } - else - { - /* Disable the RNG */ - RNG->CR &= ~RNG_CR_RNGEN; - } -} -/** - * @} - */ - -/** @defgroup RNG_Group2 Get 32 bit Random number function - * @brief Get 32 bit Random number function - * - -@verbatim - =============================================================================== - Get 32 bit Random number function - =============================================================================== - This section provides a function allowing to get the 32 bit Random number - - @note Before to call this function you have to wait till DRDY flag is set, - using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - -@endverbatim - * @{ - */ - - -/** - * @brief Returns a 32-bit random number. - * - * @note Before to call this function you have to wait till DRDY (data ready) - * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - * @note Each time the the Random number data is read (using RNG_GetRandomNumber() - * function), the RNG_FLAG_DRDY flag is automatically cleared. - * @note In the case of a seed error, the generation of random numbers is - * interrupted for as long as the SECS bit is '1'. If a number is - * available in the RNG_DR register, it must not be used because it may - * not have enough entropy. In this case, it is recommended to clear the - * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable - * and enable the RNG peripheral (using RNG_Cmd() function) to - * reinitialize and restart the RNG. - * @note In the case of a clock error, the RNG is no more able to generate - * random numbers because the PLL48CLK clock is not correct. User have - * to check that the clock controller is correctly configured to provide - * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) - * function) . The clock error has no impact on the previously generated - * random numbers, and the RNG_DR register contents can be used. - * - * @param None - * @retval 32-bit random number. - */ -uint32_t RNG_GetRandomNumber(void) -{ - /* Return the 32 bit random number from the DR register */ - return RNG->DR; -} - - -/** - * @} - */ - -/** @defgroup RNG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the RNG Interrupts and - to get the status and clear flags and Interrupts pending bits. - - The RNG provides 3 Interrupts sources and 3 Flags: - - Flags : - ---------- - 1. RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid - random data. it is cleared by reading the valid data - (using RNG_GetRandomNumber() function). - - 2. RNG_FLAG_CECS : In the case of a seed error detection. - - 3. RNG_FLAG_SECS : In the case of a clock error detection. - - - Interrupts : - ------------ - if enabled, an RNG interrupt is pending : - - 1. In the case of the RNG_DR register contains valid random data. - This interrupt source is cleared once the RNG_DR register has been read - (using RNG_GetRandomNumber() function) until a new valid value is - computed. - - or - 2. In the case of a seed error : One of the following faulty sequences has - been detected: - - More than 64 consecutive bits at the same value (0 or 1) - - More than 32 consecutive alternance of 0 and 1 (0101010101...01) - This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) - function. - - or - 3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source) - was not correctly detected (fPLL48CLK< fHCLK/16). - This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI) - function. - @note In this case, User have to check that the clock controller is - correctly configured to provide the RNG clock. - - Managing the RNG controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the RNG controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - RNG_GetFlagStatus() : to check if flags events occur. - - RNG_ClearFlag() : to clear the flags events. - - @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only - by reading the Random number data. - - 2. In the Interrupt Mode it is advised to use the following functions: - - RNG_ITConfig() : to enable or disable the interrupt source. - - RNG_GetITStatus() : to check if Interrupt occurs. - - RNG_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the RNG interrupt. - * @note The RNG provides 3 interrupt sources, - * - Computed data is ready event (DRDY), and - * - Seed error Interrupt (SEI) and - * - Clock error Interrupt (CEI), - * all these interrupts sources are enabled by setting the IE bit in - * CR register. However, each interrupt have its specific status bit - * (see RNG_GetITStatus() function) and clear bit except the DRDY event - * (see RNG_ClearITPendingBit() function). - * @param NewState: new state of the RNG interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG interrupt */ - RNG->CR |= RNG_CR_IE; - } - else - { - /* Disable the RNG interrupt */ - RNG->CR &= ~RNG_CR_IE; - } -} - -/** - * @brief Checks whether the specified RNG flag is set or not. - * @param RNG_FLAG: specifies the RNG flag to check. - * This parameter can be one of the following values: - * @arg RNG_FLAG_DRDY: Data Ready flag. - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @retval The new state of RNG_FLAG (SET or RESET). - */ -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_FLAG(RNG_FLAG)); - - /* Check the status of the specified RNG flag */ - if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET) - { - /* RNG_FLAG is set */ - bitstatus = SET; - } - else - { - /* RNG_FLAG is reset */ - bitstatus = RESET; - } - /* Return the RNG_FLAG status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG flags. - * @param RNG_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. - * This flag is cleared only by reading the Random number data (using - * RNG_GetRandomNumber() function). - * @retval None - */ -void RNG_ClearFlag(uint8_t RNG_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG)); - /* Clear the selected RNG flags */ - RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); -} - -/** - * @brief Checks whether the specified RNG interrupt has occurred or not. - * @param RNG_IT: specifies the RNG interrupt source to check. - * This parameter can be one of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval The new state of RNG_IT (SET or RESET). - */ -ITStatus RNG_GetITStatus(uint8_t RNG_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_IT(RNG_IT)); - - /* Check the status of the specified RNG interrupt */ - if ((RNG->SR & RNG_IT) != (uint8_t)RESET) - { - /* RNG_IT is set */ - bitstatus = SET; - } - else - { - /* RNG_IT is reset */ - bitstatus = RESET; - } - /* Return the RNG_IT status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG interrupt pending bit(s). - * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear. - * This parameter can be any combination of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval None - */ -void RNG_ClearITPendingBit(uint8_t RNG_IT) -{ - /* Check the parameters */ - assert_param(IS_RNG_IT(RNG_IT)); - - /* Clear the selected RNG interrupt pending bit */ - RNG->SR = (uint8_t)~RNG_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_rng.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Random Number Generator (RNG) peripheral: + * - Initialization and Configuration + * - Get 32 bit Random number + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable The RNG controller clock using + * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. + * + * 2. Activate the RNG peripheral using RNG_Cmd() function. + * + * 3. Wait until the 32 bit Random number Generator contains a valid + * random data (using polling/interrupt mode). For more details, + * refer to "Interrupts and flags management functions" module + * description. + * + * 4. Get the 32 bit Random number using RNG_GetRandomNumber() function + * + * 5. To get another 32 bit Random number, go to step 3. + * + * + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RNG + * @brief RNG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RNG_Private_Functions + * @{ + */ + +/** @defgroup RNG_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + This section provides functions allowing to + - Initialize the RNG peripheral + - Enable or disable the RNG peripheral + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the RNG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void RNG_DeInit(void) +{ + /* Enable RNG reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); + + /* Release RNG from reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE); +} + +/** + * @brief Enables or disables the RNG peripheral. + * @param NewState: new state of the RNG peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RNG_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the RNG */ + RNG->CR |= RNG_CR_RNGEN; + } + else + { + /* Disable the RNG */ + RNG->CR &= ~RNG_CR_RNGEN; + } +} +/** + * @} + */ + +/** @defgroup RNG_Group2 Get 32 bit Random number function + * @brief Get 32 bit Random number function + * + +@verbatim + =============================================================================== + Get 32 bit Random number function + =============================================================================== + This section provides a function allowing to get the 32 bit Random number + + @note Before to call this function you have to wait till DRDY flag is set, + using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. + +@endverbatim + * @{ + */ + + +/** + * @brief Returns a 32-bit random number. + * + * @note Before to call this function you have to wait till DRDY (data ready) + * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. + * @note Each time the the Random number data is read (using RNG_GetRandomNumber() + * function), the RNG_FLAG_DRDY flag is automatically cleared. + * @note In the case of a seed error, the generation of random numbers is + * interrupted for as long as the SECS bit is '1'. If a number is + * available in the RNG_DR register, it must not be used because it may + * not have enough entropy. In this case, it is recommended to clear the + * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable + * and enable the RNG peripheral (using RNG_Cmd() function) to + * reinitialize and restart the RNG. + * @note In the case of a clock error, the RNG is no more able to generate + * random numbers because the PLL48CLK clock is not correct. User have + * to check that the clock controller is correctly configured to provide + * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) + * function) . The clock error has no impact on the previously generated + * random numbers, and the RNG_DR register contents can be used. + * + * @param None + * @retval 32-bit random number. + */ +uint32_t RNG_GetRandomNumber(void) +{ + /* Return the 32 bit random number from the DR register */ + return RNG->DR; +} + + +/** + * @} + */ + +/** @defgroup RNG_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides functions allowing to configure the RNG Interrupts and + to get the status and clear flags and Interrupts pending bits. + + The RNG provides 3 Interrupts sources and 3 Flags: + + Flags : + ---------- + 1. RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid + random data. it is cleared by reading the valid data + (using RNG_GetRandomNumber() function). + + 2. RNG_FLAG_CECS : In the case of a seed error detection. + + 3. RNG_FLAG_SECS : In the case of a clock error detection. + + + Interrupts : + ------------ + if enabled, an RNG interrupt is pending : + + 1. In the case of the RNG_DR register contains valid random data. + This interrupt source is cleared once the RNG_DR register has been read + (using RNG_GetRandomNumber() function) until a new valid value is + computed. + + or + 2. In the case of a seed error : One of the following faulty sequences has + been detected: + - More than 64 consecutive bits at the same value (0 or 1) + - More than 32 consecutive alternance of 0 and 1 (0101010101...01) + This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) + function. + + or + 3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source) + was not correctly detected (fPLL48CLK< fHCLK/16). + This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI) + function. + @note In this case, User have to check that the clock controller is + correctly configured to provide the RNG clock. + + Managing the RNG controller events : + ------------------------------------ + The user should identify which mode will be used in his application to manage + the RNG controller events: Polling mode or Interrupt mode. + + 1. In the Polling Mode it is advised to use the following functions: + - RNG_GetFlagStatus() : to check if flags events occur. + - RNG_ClearFlag() : to clear the flags events. + + @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only + by reading the Random number data. + + 2. In the Interrupt Mode it is advised to use the following functions: + - RNG_ITConfig() : to enable or disable the interrupt source. + - RNG_GetITStatus() : to check if Interrupt occurs. + - RNG_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). + + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the RNG interrupt. + * @note The RNG provides 3 interrupt sources, + * - Computed data is ready event (DRDY), and + * - Seed error Interrupt (SEI) and + * - Clock error Interrupt (CEI), + * all these interrupts sources are enabled by setting the IE bit in + * CR register. However, each interrupt have its specific status bit + * (see RNG_GetITStatus() function) and clear bit except the DRDY event + * (see RNG_ClearITPendingBit() function). + * @param NewState: new state of the RNG interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RNG_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the RNG interrupt */ + RNG->CR |= RNG_CR_IE; + } + else + { + /* Disable the RNG interrupt */ + RNG->CR &= ~RNG_CR_IE; + } +} + +/** + * @brief Checks whether the specified RNG flag is set or not. + * @param RNG_FLAG: specifies the RNG flag to check. + * This parameter can be one of the following values: + * @arg RNG_FLAG_DRDY: Data Ready flag. + * @arg RNG_FLAG_CECS: Clock Error Current flag. + * @arg RNG_FLAG_SECS: Seed Error Current flag. + * @retval The new state of RNG_FLAG (SET or RESET). + */ +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RNG_GET_FLAG(RNG_FLAG)); + + /* Check the status of the specified RNG flag */ + if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET) + { + /* RNG_FLAG is set */ + bitstatus = SET; + } + else + { + /* RNG_FLAG is reset */ + bitstatus = RESET; + } + /* Return the RNG_FLAG status */ + return bitstatus; +} + + +/** + * @brief Clears the RNG flags. + * @param RNG_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RNG_FLAG_CECS: Clock Error Current flag. + * @arg RNG_FLAG_SECS: Seed Error Current flag. + * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. + * This flag is cleared only by reading the Random number data (using + * RNG_GetRandomNumber() function). + * @retval None + */ +void RNG_ClearFlag(uint8_t RNG_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG)); + /* Clear the selected RNG flags */ + RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); +} + +/** + * @brief Checks whether the specified RNG interrupt has occurred or not. + * @param RNG_IT: specifies the RNG interrupt source to check. + * This parameter can be one of the following values: + * @arg RNG_IT_CEI: Clock Error Interrupt. + * @arg RNG_IT_SEI: Seed Error Interrupt. + * @retval The new state of RNG_IT (SET or RESET). + */ +ITStatus RNG_GetITStatus(uint8_t RNG_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RNG_GET_IT(RNG_IT)); + + /* Check the status of the specified RNG interrupt */ + if ((RNG->SR & RNG_IT) != (uint8_t)RESET) + { + /* RNG_IT is set */ + bitstatus = SET; + } + else + { + /* RNG_IT is reset */ + bitstatus = RESET; + } + /* Return the RNG_IT status */ + return bitstatus; +} + + +/** + * @brief Clears the RNG interrupt pending bit(s). + * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear. + * This parameter can be any combination of the following values: + * @arg RNG_IT_CEI: Clock Error Interrupt. + * @arg RNG_IT_SEI: Seed Error Interrupt. + * @retval None + */ +void RNG_ClearITPendingBit(uint8_t RNG_IT) +{ + /* Check the parameters */ + assert_param(IS_RNG_IT(RNG_IT)); + + /* Clear the selected RNG interrupt pending bit */ + RNG->SR = (uint8_t)~RNG_IT; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c index 7ec11f0e2..00c6aa68a 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c @@ -1,2244 +1,2244 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rtc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * - Initialization - * - Calendar (Time and Date) configuration - * - Alarms (Alarm A and Alarm B) configuration - * - WakeUp Timer configuration - * - Daylight Saving configuration - * - Output pin Configuration - * - Coarse Calibration configuration - * - TimeStamp configuration - * - Tampers configuration - * - Backup Data Registers configuration - * - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * Backup Domain Operating Condition - * =================================================================== - * The real-time clock (RTC), the RTC backup registers, and the backup - * SRAM (BKP SRAM) can be powered from the VBAT voltage when the main - * VDD supply is powered off. - * To retain the content of the RTC backup registers, backup SRAM, - * and supply the RTC when VDD is turned off, VBAT pin can be connected - * to an optional standby voltage supplied by a battery or by another - * source. - * - * To allow the RTC to operate even when the main digital supply (VDD) - * is turned off, the VBAT pin powers the following blocks: - * 1 - The RTC - * 2 - The LSE oscillator - * 3 - The backup SRAM when the low power backup regulator is enabled - * 4 - PC13 to PC15 I/Os, plus PI8 I/O (when available) - * - * When the backup domain is supplied by VDD (analog switch connected - * to VDD), the following functions are available: - * 1 - PC14 and PC15 can be used as either GPIO or LSE pins - * 2 - PC13 can be used as a GPIO or as the RTC_AF1 pin - * 3 - PI8 can be used as a GPIO or as the RTC_AF2 pin - * - * When the backup domain is supplied by VBAT (analog switch connected - * to VBAT because VDD is not present), the following functions are available: - * 1 - PC14 and PC15 can be used as LSE pins only - * 2 - PC13 can be used as the RTC_AF1 pin - * 3 - PI8 can be used as the RTC_AF2 pin - * - * =================================================================== - * Backup Domain Reset - * =================================================================== - * The backup domain reset sets all RTC registers and the RCC_BDCR - * register to their reset values. The BKPSRAM is not affected by this - * reset. The only way of resetting the BKPSRAM is through the Flash - * interface by requesting a protection level change from 1 to 0. - * A backup domain reset is generated when one of the following events - * occurs: - * 1 - Software reset, triggered by setting the BDRST bit in the - * RCC Backup domain control register (RCC_BDCR). You can use the - * RCC_BackupResetCmd(). - * 2 - VDD or VBAT power on, if both supplies have previously been - * powered off. - * - * =================================================================== - * Backup Domain Access - * =================================================================== - * After reset, the backup domain (RTC registers, RTC backup data - * registers and backup SRAM) is protected against possible unwanted - * write accesses. - * To enable access to the RTC Domain and RTC registers, proceed as follows: - * - Enable the Power Controller (PWR) APB1 interface clock using the - * RCC_APB1PeriphClockCmd() function. - * - Enable access to RTC domain using the PWR_BackupAccessCmd() function. - * - Select the RTC clock source using the RCC_RTCCLKConfig() function. - * - Enable RTC Clock using the RCC_RTCCLKCmd() function. - * - * =================================================================== - * RTC Driver: how to use it - * =================================================================== - * - Enable the RTC domain access (see description in the section above) - * - Configure the RTC Prescaler (Asynchronous and Synchronous) and - * RTC hour format using the RTC_Init() function. - * - * Time and Date configuration - * =========================== - * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime() - * and RTC_SetDate() functions. - * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() - * functions. - * - Use the RTC_DayLightSavingConfig() function to add or sub one - * hour to the RTC Calendar. - * - * Alarm configuration - * =================== - * - To configure the RTC Alarm use the RTC_SetAlarm() function. - * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function - * - To read the RTC Alarm, use the RTC_GetAlarm() function. - * - * RTC Wakeup configuration - * ======================== - * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() - * function. - * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() - * function - * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function - * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() - * function. - * - * Outputs configuration - * ===================== - * The RTC has 2 different outputs: - * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B - * and WaKeUp signals. - * To output the selected RTC signal on RTC_AF1 pin, use the - * RTC_OutputConfig() function. - * - AFO_CALIB: this output is used to manage the RTC Clock divided - * by 64 (512Hz) signal. - * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() - * function. - * - * Coarse Calibration configuration - * ================================= - * - Configure the RTC Coarse Calibration Value and the corresponding - * sign using the RTC_CoarseCalibConfig() function. - * - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() - * function - * - * TimeStamp configuration - * ======================= - * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp - * using the RTC_TimeStampCmd() function. - * - To read the RTC TimeStamp Time and Date register, use the - * RTC_GetTimeStamp() function. - * - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) - * or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in - * RTC_TAFCR register. You can use the RTC_TamperPinSelection() - * function to select the corresponding pin. - * - * Tamper configuration - * ==================== - * - Configure the RTC Tamper trigger using the RTC_TamperConfig() - * function. - * - Enable the RTC Tamper using the RTC_TamperCmd() function. - * - The TIMESTAMP alternate function can be mapped to either RTC_AF1 - * or RTC_AF2 depending on the value of the TSINSEL bit in the - * RTC_TAFCR register. You can use the RTC_TimeStampPinSelection() - * function to select the corresponding pin. - * - * Backup Data Registers configuration - * =================================== - * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() - * function. - * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() - * function. - * - * =================================================================== - * RTC and low power modes - * =================================================================== - * The MCU can be woken up from a low power mode by an RTC alternate - * function. - * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - * RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - * These RTC alternate functions can wake up the system from the Stop - * and Standby lowpower modes. - * The system can also wake up from low power modes without depending - * on an external interrupt (Auto-wakeup mode), by using the RTC alarm - * or the RTC wakeup events. - * The RTC provides a programmable time base for waking up from the - * Stop or Standby mode at regular intervals. - * Wakeup from STOP and Standby modes is possible only when the RTC - * clock source is LSE or LSI. - * - * =================================================================== - * Selection of RTC_AF1 alternate functions - * =================================================================== - * The RTC_AF1 pin (PC13) can be used for the following purposes: - * - AFO_ALARM output - * - AFO_CALIB output - * - AFI_TAMPER - * - AFI_TIMESTAMP - * - * +-------------------------------------------------------------------------------------------------------------+ - * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - * | and function | | | | | selection | selection |Configuration | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Alarm out | | | | | Don't | Don't | | - * | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Alarm out | | | | | Don't | Don't | | - * | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Calibration out | | | | | Don't | Don't | | - * | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TAMPER input | | | | | | Don't | | - * | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP and | | | | | | | | - * | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | - * | floating | | | | | | | | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP input | | | | | Don't | | | - * | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | - * +-------------------------------------------------------------------------------------------------------------+ - * - * - * =================================================================== - * Selection of RTC_AF2 alternate functions - * =================================================================== - * The RTC_AF2 pin (PI8) can be used for the following purposes: - * - AFI_TAMPER - * - AFI_TIMESTAMP - * - * +---------------------------------------------------------------------------------------+ - * | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - * | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - * | and function | | | selection | selection |Configuration | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TAMPER input | | | | Don't | | - * | floating | 1 | 0 | 1 | care | Don't care | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP and | | | | | | - * | TAMPER input | 1 | 1 | 1 | 1 | Don't care | - * | floating | | | | | | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP input | | | Don't | | | - * | floating | 0 | 1 | care | 1 | Don't care | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | - * +---------------------------------------------------------------------------------------+ - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_rtc.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F )) - -#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) -#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static uint8_t RTC_ByteToBcd2(uint8_t Value); -static uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** @defgroup RTC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This section provide functions allowing to initialize and configure the RTC - Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers - Write protection, enter and exit the RTC initialization mode, RTC registers - synchronization check and reference clock detection enable. - - 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is - split into 2 programmable prescalers to minimize power consumption. - - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. - - When both prescalers are used, it is recommended to configure the asynchronous - prescaler to a high value to minimize consumption. - - 2. All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - - 3. To Configure the RTC Calendar, user application should enter initialization - mode. In this mode, the calendar counter is stopped and its value can be - updated. When the initialization sequence is complete, the calendar restarts - counting after 4 RTCCLK cycles. - - 4. To read the calendar through the shadow registers after Calendar initialization, - calendar update or after wakeup from low power modes the software must first - clear the RSF flag. The software must then wait until it is set again before - reading the calendar, which means that the calendar registers have been - correctly copied into the RTC_TR and RTC_DR shadow registers. - The RTC_WaitForSynchro() function implements the above software sequence - (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data - * registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are deinitialized - * - ERROR: RTC registers are not deinitialized - */ -ErrorStatus RTC_DeInit(void) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - RTC->TR = (uint32_t)0x00000000; - RTC->DR = (uint32_t)0x00002101; - /* Reset All CR bits except CR[2:0] */ - RTC->CR &= (uint32_t)0x00000007; - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - /* Reset all RTC CR register bits */ - RTC->CR &= (uint32_t)0x00000000; - RTC->WUTR = (uint32_t)0x0000FFFF; - RTC->PRER = (uint32_t)0x007F00FF; - RTC->CALIBR = (uint32_t)0x00000000; - RTC->ALRMAR = (uint32_t)0x00000000; - RTC->ALRMBR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - RTC->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - RTC->TAFCR = 0x00000000; - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Clear RTC CR FMT Bit */ - RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); - /* Set RTC_CR register */ - RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); - - /* Configure the RTC PRER */ - RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); - RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_InitStruct member with its default value. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) -{ - /* Initialize the RTC_HourFormat member */ - RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; - - /* Initialize the RTC_AsynchPrediv member */ - RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; - - /* Initialize the RTC_SynchPrediv member */ - RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; -} - -/** - * @brief Enables or disables the RTC registers write protection. - * @note All the RTC registers are write protected except for RTC_ISR[13:8], - * RTC_TAFCR and RTC_BKPxR. - * @note Writing a wrong key reactivates the write protection. - * @note The protection mechanism is not affected by system reset. - * @param NewState: new state of the write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_WriteProtectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - } -} - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus RTC_EnterInitMode(void) -{ - __IO uint32_t initcounter = 0x00; - ErrorStatus status = ERROR; - uint32_t initstatus = 0x00; - - /* Check if the Initialization mode is set */ - if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do - { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_INITF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - } - else - { - status = SUCCESS; - } - - return (status); -} - -/** - * @brief Exits the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval None - */ -void RTC_ExitInitMode(void) -{ - /* Exit Initialization mode */ - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; -} - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus RTC_WaitForSynchro(void) -{ - __IO uint32_t synchrocounter = 0; - ErrorStatus status = ERROR; - uint32_t synchrostatus = 0x00; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear RSF flag */ - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Wait the registers to be synchronised */ - do - { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_RSF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (status); -} - -/** - * @brief Enables or disables the RTC reference clock detection. - * @param NewState: new state of the RTC reference clock. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC reference clock detection is enabled - * - ERROR: RTC reference clock detection is disabled - */ -ErrorStatus RTC_RefClockCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the RTC reference clock detection */ - RTC->CR |= RTC_CR_REFCKON; - } - else - { - /* Disable the RTC reference clock detection */ - RTC->CR &= ~RTC_CR_REFCKON; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group2 Time and Date configuration functions - * @brief Time and Date configuration functions - * -@verbatim - =============================================================================== - Time and Date configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC Calendar - (Time and Date). - -@endverbatim - * @{ - */ - -/** - * @brief Set the RTC current time. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ - ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); - } - else - { - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ - (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_TR register */ - RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_TimeStruct member with its default value - * (Time = 00h:00min:00sec). - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->RTC_H12 = RTC_H12_AM; - RTC_TimeStruct->RTC_Hours = 0; - RTC_TimeStruct->RTC_Minutes = 0; - RTC_TimeStruct->RTC_Seconds = 0; -} - -/** - * @brief Get the RTC current Time. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contain the returned current time configuration. - * @retval None - */ -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); - RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); - } -} - -/** - * @brief Set the RTC current date. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains - * the date configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Date register is configured - * - ERROR: RTC Date register is not configured - */ -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) - { - RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; - } - if (RTC_Format == RTC_Format_BIN) - { - assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); - assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); - assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - assert_param(IS_RTC_MONTH(tmpreg)); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - assert_param(IS_RTC_DATE(tmpreg)); - } - assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ - (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_DateStruct->RTC_Date) | \ - (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ - ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_DR register */ - RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_DateStruct member with its default value - * (Monday, January 01 xx00). - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) -{ - /* Monday, January 01 xx00 */ - RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; - RTC_DateStruct->RTC_Date = 1; - RTC_DateStruct->RTC_Month = RTC_Month_January; - RTC_DateStruct->RTC_Year = 0; -} - -/** - * @brief Get the RTC current date. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will - * contain the returned current date configuration. - * @retval None - */ -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); - RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); - RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group3 Alarms configuration functions - * @brief Alarms (Alarm A and Alarm B) configuration functions - * -@verbatim - =============================================================================== - Alarms (Alarm A and Alarm B) configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC Alarms. - -@endverbatim - * @{ - */ - -/** - * @brief Set the specified RTC Alarm. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the RTC_AlarmCmd(DISABLE)). - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval None - */ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm register */ - if (RTC_Alarm == RTC_Alarm_A) - { - RTC->ALRMAR = (uint32_t)tmpreg; - } - else - { - RTC->ALRMBR = (uint32_t)tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Fills each RTC_AlarmStruct member with its default value - * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = - * all fields are masked). - * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which - * will be initialized. - * @retval None - */ -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; - - /* Alarm Date Settings : Date = 1st day of the month */ - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; - RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will - * contains the output alarm configuration values. - * @retval None - */ -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)(RTC->ALRMAR); - } - else - { - tmpreg = (uint32_t)(RTC->ALRMBR); - } - - /* Fill the structure with the read parameters */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ - RTC_ALRMAR_HU)) >> 16); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ - RTC_ALRMAR_MNU)) >> 8); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ - RTC_ALRMAR_SU)); - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); - - if (RTC_Format == RTC_Format_BIN) - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Hours); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Minutes); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Seconds); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - } -} - -/** - * @brief Enables or disables the specified RTC Alarm. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be any combination of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param NewState: new state of the specified alarm. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Alarm is enabled/disabled - * - ERROR: RTC Alarm is not enabled/disabled - */ -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) -{ - __IO uint32_t alarmcounter = 0x00; - uint32_t alarmstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm state */ - if (NewState != DISABLE) - { - RTC->CR |= (uint32_t)RTC_Alarm; - - status = SUCCESS; - } - else - { - /* Disable the Alarm in RTC_CR register */ - RTC->CR &= (uint32_t)~RTC_Alarm; - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - do - { - alarmstatus = RTC->ISR & (RTC_Alarm >> 8); - alarmcounter++; - } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); - - if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group4 WakeUp Timer configuration functions - * @brief WakeUp Timer configuration functions - * -@verbatim - =============================================================================== - WakeUp Timer configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC WakeUp. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Wakeup clock source. - * @note The WakeUp Clock source can only be changed when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpClock: Wakeup Clock source. - * This parameter can be one of the following values: - * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 - * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 - * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 - * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 - * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE - * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE - * @retval None - */ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the Wakeup Timer clock source bits in CR register */ - RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - RTC->CR |= (uint32_t)RTC_WakeUpClock; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the RTC Wakeup counter. - * @note The RTC WakeUp counter can only be written when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpCounter: specifies the WakeUp counter. - * This parameter can be a value from 0x0000 to 0xFFFF. - * @retval None - */ -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Wakeup Timer counter */ - RTC->WUTR = (uint32_t)RTC_WakeUpCounter; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC WakeUp timer counter value. - * @param None - * @retval The RTC WakeUp Counter value. - */ -uint32_t RTC_GetWakeUpCounter(void) -{ - /* Get the counter value */ - return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Enables or Disables the RTC WakeUp timer. - * @param NewState: new state of the WakeUp timer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the Wakeup Timer */ - RTC->CR |= (uint32_t)RTC_CR_WUTE; - status = SUCCESS; - } - else - { - /* Disable the Wakeup Timer */ - RTC->CR &= (uint32_t)~RTC_CR_WUTE; - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group5 Daylight Saving configuration functions - * @brief Daylight Saving configuration functions - * -@verbatim - =============================================================================== - Daylight Saving configuration functions - =============================================================================== - - This section provide functions allowing to configure the RTC DayLight Saving. - -@endverbatim - * @{ - */ - -/** - * @brief Adds or substract one hour from the current time. - * @param RTC_DayLightSaveOperation: the value of hour adjustment. - * This parameter can be one of the following values: - * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) - * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) - * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit - * in CR register to store the operation. - * This parameter can be one of the following values: - * @arg RTC_StoreOperation_Reset: BCK Bit Reset - * @arg RTC_StoreOperation_Set: BCK Bit Set - * @retval None - */ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) -{ - /* Check the parameters */ - assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_BCK); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC Day Light Saving stored operation. - * @param None - * @retval RTC Day Light Saving stored operation. - * - RTC_StoreOperation_Reset - * - RTC_StoreOperation_Set - */ -uint32_t RTC_GetStoreOperation(void) -{ - return (RTC->CR & RTC_CR_BCK); -} - -/** - * @} - */ - -/** @defgroup RTC_Group6 Output pin Configuration function - * @brief Output pin Configuration function - * -@verbatim - =============================================================================== - Output pin Configuration function - =============================================================================== - - This section provide functions allowing to configure the RTC Output source. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC output source (AFO_ALARM). - * @param RTC_Output: Specifies which signal will be routed to the RTC output. - * This parameter can be one of the following values: - * @arg RTC_Output_Disable: No output selected - * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output - * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output - * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output - * @param RTC_OutputPolarity: Specifies the polarity of the output signal. - * This parameter can be one of the following: - * @arg RTC_OutputPolarity_High: The output pin is high when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @arg RTC_OutputPolarity_Low: The output pin is low when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @retval None - */ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT(RTC_Output)); - assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); - - /* Configure the output selection and polarity */ - RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group7 Coarse Calibration configuration functions - * @brief Coarse Calibration configuration functions - * -@verbatim - =============================================================================== - Coarse Calibration configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Coarse calibration parameters. - * @param RTC_CalibSign: specifies the sign of the coarse calibration value. - * This parameter can be one of the following values: - * @arg RTC_CalibSign_Positive: The value sign is positive - * @arg RTC_CalibSign_Negative: The value sign is negative - * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). - * - * @note This Calibration value should be between 0 and 63 when using negative - * sign with a 2-ppm step. - * - * @note This Calibration value should be between 0 and 126 when using positive - * sign with a 4-ppm step. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are initialized - * - ERROR: RTC Coarse calibration are not initialized - */ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); - assert_param(IS_RTC_CALIB_VALUE(Value)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the coarse calibration value */ - RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the Coarse calibration process. - * @param NewState: new state of the Coarse calibration. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are enabled/disabled - * - ERROR: RTC Coarse calibration are not enabled/disabled - */ -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the Coarse Calibration */ - RTC->CR |= (uint32_t)RTC_CR_DCE; - } - else - { - /* Disable the Coarse Calibration */ - RTC->CR &= (uint32_t)~RTC_CR_DCE; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the RTC clock to be output through the relative pin. - * @param NewState: new state of the digital calibration Output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_CalibOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the RTC clock output */ - RTC->CR |= (uint32_t)RTC_CR_COE; - } - else - { - /* Disable the RTC clock output */ - RTC->CR &= (uint32_t)~RTC_CR_COE; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - - -/** @defgroup RTC_Group8 TimeStamp configuration functions - * @brief TimeStamp configuration functions - * -@verbatim - =============================================================================== - TimeStamp configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or Disables the RTC TimeStamp functionality with the - * specified time stamp pin stimulating edge. - * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following: - * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising - * edge of the related pin. - * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the - * falling edge of the related pin. - * @param NewState: new state of the TimeStamp. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Get the new configuration */ - if (NewState != DISABLE) - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); - } - else - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Time Stamp TSEDGE and Enable bits */ - RTC->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Get the RTC TimeStamp value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contains the TimeStamp time values. - * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will - * contains the TimeStamp date values. - * @retval None - */ -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - - /* Fill the Date structure fields with the read parameters */ - RTC_StampDateStruct->RTC_Year = 0; - RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the Time structure parameters to Binary format */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); - - /* Convert the Date structure parameters to Binary format */ - RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); - RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group9 Tampers configuration functions - * @brief Tampers configuration functions - * -@verbatim - =============================================================================== - Tampers configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the select Tamper pin edge. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that - * stimulates tamper event. - * This parameter can be one of the following values: - * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. - * @retval None - */ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); - - if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); - } - else - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); - } -} - -/** - * @brief Enables or Disables the Tamper detection. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param NewState: new state of the tamper pin. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_Tamper; - } - else - { - /* Disable the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_Tamper; - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group10 Backup Data Registers configuration functions - * @brief Backup Data Registers configuration functions - * -@verbatim - =============================================================================== - Backup Data Registers configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval None - */ -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @} - */ - -/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions - * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config - * configuration functions - * -@verbatim - =============================================================================== - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Selects the RTC Tamper Pin. - * @param RTC_TamperPin: specifies the RTC Tamper Pin. - * This parameter can be one of the following values: - * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin. - * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin. - * @retval None - */ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TamperPin); -} - -/** - * @brief Selects the RTC TimeStamp Pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. - * @retval None - */ -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); -} - -/** - * @brief Configures the RTC Output Pin mode. - * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. - * This parameter can be one of the following values: - * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in - * Open Drain mode. - * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in - * Push Pull mode. - * @retval None - */ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); - RTC->TAFCR |= (uint32_t)(RTC_OutputType); -} - -/** - * @} - */ - -/** @defgroup RTC_Group12 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - All RTC interrupts are connected to the EXTI controller. - - - To enable the RTC Alarm interrupt, the following sequence is required: - - Configure and enable the EXTI Line 17 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using - the RTC_SetAlarm() and RTC_AlarmCmd() functions. - - - To enable the RTC Wakeup interrupt, the following sequence is required: - - Configure and enable the EXTI Line 22 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to generate the RTC wakeup timer event using the - RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - - To enable the RTC Tamper interrupt, the following sequence is required: - - Configure and enable the EXTI Line 21 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to detect the RTC tamper event using the - RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - - - To enable the RTC TimeStamp interrupt, the following sequence is required: - - Configure and enable the EXTI Line 21 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to detect the RTC time-stamp event using the - RTC_TimeStampCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt mask - * @arg RTC_IT_WUT: WakeUp Timer interrupt mask - * @arg RTC_IT_ALRB: Alarm B interrupt mask - * @arg RTC_IT_ALRA: Alarm A interrupt mask - * @arg RTC_IT_TAMP: Tamper event interrupt mask - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_CONFIG_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); - } - else - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_INITF: Initialization mode flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_INITS: Registers Configured flag - * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag - * @arg RTC_FLAG_ALRBWF: Alarm B Write flag - * @arg RTC_FLAG_ALRAWF: Alarm A write flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - /* Get all the flags */ - tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); - - /* Return the status of the flag */ - if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the RTC flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @retval None - */ -void RTC_ClearFlag(uint32_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the Flags in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupt source to check. - * This parameter can be one of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval The new state of RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint32_t RTC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - /* Get the TAMPER Interrupt enable bit and pending bit */ - tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); - - /* Get the Interrupt enable Status */ - enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15))); - - /* Get the Interrupt pending bit */ - tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); - - /* Get the status of the Interrupt */ - if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the RTC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint32_t RTC_IT) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_IT(RTC_IT)); - - /* Get the RTC_ISR Interrupt pending bits mask */ - tmpreg = (uint32_t)(RTC_IT >> 4); - - /* Clear the interrupt pending bits in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @} - */ - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted. - * @retval Converted byte - */ -static uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint8_t bcdhigh = 0; - - while (Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted. - * @retval Converted word - */ -static uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint8_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_rtc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * - Initialization + * - Calendar (Time and Date) configuration + * - Alarms (Alarm A and Alarm B) configuration + * - WakeUp Timer configuration + * - Daylight Saving configuration + * - Output pin Configuration + * - Coarse Calibration configuration + * - TimeStamp configuration + * - Tampers configuration + * - Backup Data Registers configuration + * - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * Backup Domain Operating Condition + * =================================================================== + * The real-time clock (RTC), the RTC backup registers, and the backup + * SRAM (BKP SRAM) can be powered from the VBAT voltage when the main + * VDD supply is powered off. + * To retain the content of the RTC backup registers, backup SRAM, + * and supply the RTC when VDD is turned off, VBAT pin can be connected + * to an optional standby voltage supplied by a battery or by another + * source. + * + * To allow the RTC to operate even when the main digital supply (VDD) + * is turned off, the VBAT pin powers the following blocks: + * 1 - The RTC + * 2 - The LSE oscillator + * 3 - The backup SRAM when the low power backup regulator is enabled + * 4 - PC13 to PC15 I/Os, plus PI8 I/O (when available) + * + * When the backup domain is supplied by VDD (analog switch connected + * to VDD), the following functions are available: + * 1 - PC14 and PC15 can be used as either GPIO or LSE pins + * 2 - PC13 can be used as a GPIO or as the RTC_AF1 pin + * 3 - PI8 can be used as a GPIO or as the RTC_AF2 pin + * + * When the backup domain is supplied by VBAT (analog switch connected + * to VBAT because VDD is not present), the following functions are available: + * 1 - PC14 and PC15 can be used as LSE pins only + * 2 - PC13 can be used as the RTC_AF1 pin + * 3 - PI8 can be used as the RTC_AF2 pin + * + * =================================================================== + * Backup Domain Reset + * =================================================================== + * The backup domain reset sets all RTC registers and the RCC_BDCR + * register to their reset values. The BKPSRAM is not affected by this + * reset. The only way of resetting the BKPSRAM is through the Flash + * interface by requesting a protection level change from 1 to 0. + * A backup domain reset is generated when one of the following events + * occurs: + * 1 - Software reset, triggered by setting the BDRST bit in the + * RCC Backup domain control register (RCC_BDCR). You can use the + * RCC_BackupResetCmd(). + * 2 - VDD or VBAT power on, if both supplies have previously been + * powered off. + * + * =================================================================== + * Backup Domain Access + * =================================================================== + * After reset, the backup domain (RTC registers, RTC backup data + * registers and backup SRAM) is protected against possible unwanted + * write accesses. + * To enable access to the RTC Domain and RTC registers, proceed as follows: + * - Enable the Power Controller (PWR) APB1 interface clock using the + * RCC_APB1PeriphClockCmd() function. + * - Enable access to RTC domain using the PWR_BackupAccessCmd() function. + * - Select the RTC clock source using the RCC_RTCCLKConfig() function. + * - Enable RTC Clock using the RCC_RTCCLKCmd() function. + * + * =================================================================== + * RTC Driver: how to use it + * =================================================================== + * - Enable the RTC domain access (see description in the section above) + * - Configure the RTC Prescaler (Asynchronous and Synchronous) and + * RTC hour format using the RTC_Init() function. + * + * Time and Date configuration + * =========================== + * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime() + * and RTC_SetDate() functions. + * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() + * functions. + * - Use the RTC_DayLightSavingConfig() function to add or sub one + * hour to the RTC Calendar. + * + * Alarm configuration + * =================== + * - To configure the RTC Alarm use the RTC_SetAlarm() function. + * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function + * - To read the RTC Alarm, use the RTC_GetAlarm() function. + * + * RTC Wakeup configuration + * ======================== + * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() + * function. + * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() + * function + * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function + * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() + * function. + * + * Outputs configuration + * ===================== + * The RTC has 2 different outputs: + * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B + * and WaKeUp signals. + * To output the selected RTC signal on RTC_AF1 pin, use the + * RTC_OutputConfig() function. + * - AFO_CALIB: this output is used to manage the RTC Clock divided + * by 64 (512Hz) signal. + * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() + * function. + * + * Coarse Calibration configuration + * ================================= + * - Configure the RTC Coarse Calibration Value and the corresponding + * sign using the RTC_CoarseCalibConfig() function. + * - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() + * function + * + * TimeStamp configuration + * ======================= + * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp + * using the RTC_TimeStampCmd() function. + * - To read the RTC TimeStamp Time and Date register, use the + * RTC_GetTimeStamp() function. + * - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) + * or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in + * RTC_TAFCR register. You can use the RTC_TamperPinSelection() + * function to select the corresponding pin. + * + * Tamper configuration + * ==================== + * - Configure the RTC Tamper trigger using the RTC_TamperConfig() + * function. + * - Enable the RTC Tamper using the RTC_TamperCmd() function. + * - The TIMESTAMP alternate function can be mapped to either RTC_AF1 + * or RTC_AF2 depending on the value of the TSINSEL bit in the + * RTC_TAFCR register. You can use the RTC_TimeStampPinSelection() + * function to select the corresponding pin. + * + * Backup Data Registers configuration + * =================================== + * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() + * function. + * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() + * function. + * + * =================================================================== + * RTC and low power modes + * =================================================================== + * The MCU can be woken up from a low power mode by an RTC alternate + * function. + * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + * RTC wakeup, RTC tamper event detection and RTC time stamp event detection. + * These RTC alternate functions can wake up the system from the Stop + * and Standby lowpower modes. + * The system can also wake up from low power modes without depending + * on an external interrupt (Auto-wakeup mode), by using the RTC alarm + * or the RTC wakeup events. + * The RTC provides a programmable time base for waking up from the + * Stop or Standby mode at regular intervals. + * Wakeup from STOP and Standby modes is possible only when the RTC + * clock source is LSE or LSI. + * + * =================================================================== + * Selection of RTC_AF1 alternate functions + * =================================================================== + * The RTC_AF1 pin (PC13) can be used for the following purposes: + * - AFO_ALARM output + * - AFO_CALIB output + * - AFI_TAMPER + * - AFI_TIMESTAMP + * + * +-------------------------------------------------------------------------------------------------------------+ + * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | + * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | + * | and function | | | | | selection | selection |Configuration | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | Alarm out | | | | | Don't | Don't | | + * | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | Alarm out | | | | | Don't | Don't | | + * | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | Calibration out | | | | | Don't | Don't | | + * | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | TAMPER input | | | | | | Don't | | + * | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | TIMESTAMP and | | | | | | | | + * | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | + * | floating | | | | | | | | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | TIMESTAMP input | | | | | Don't | | | + * | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | + * +-------------------------------------------------------------------------------------------------------------+ + * + * + * =================================================================== + * Selection of RTC_AF2 alternate functions + * =================================================================== + * The RTC_AF2 pin (PI8) can be used for the following purposes: + * - AFI_TAMPER + * - AFI_TIMESTAMP + * + * +---------------------------------------------------------------------------------------+ + * | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | + * | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | + * | and function | | | selection | selection |Configuration | + * |-----------------|-----------|--------------|------------|--------------|--------------| + * | TAMPER input | | | | Don't | | + * | floating | 1 | 0 | 1 | care | Don't care | + * |-----------------|-----------|--------------|------------|--------------|--------------| + * | TIMESTAMP and | | | | | | + * | TAMPER input | 1 | 1 | 1 | 1 | Don't care | + * | floating | | | | | | + * |-----------------|-----------|--------------|------------|--------------|--------------| + * | TIMESTAMP input | | | Don't | | | + * | floating | 0 | 1 | care | 1 | Don't care | + * |-----------------|-----------|--------------|------------|--------------|--------------| + * | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | + * +---------------------------------------------------------------------------------------+ + * + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) +#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ + RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ + RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ + RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F )) + +#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) +#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** @defgroup RTC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + + This section provide functions allowing to initialize and configure the RTC + Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers + Write protection, enter and exit the RTC initialization mode, RTC registers + synchronization check and reference clock detection enable. + + 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is + split into 2 programmable prescalers to minimize power consumption. + - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. + - When both prescalers are used, it is recommended to configure the asynchronous + prescaler to a high value to minimize consumption. + + 2. All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + + 3. To Configure the RTC Calendar, user application should enter initialization + mode. In this mode, the calendar counter is stopped and its value can be + updated. When the initialization sequence is complete, the calendar restarts + counting after 4 RTCCLK cycles. + + 4. To read the calendar through the shadow registers after Calendar initialization, + calendar update or after wakeup from low power modes the software must first + clear the RSF flag. The software must then wait until it is set again before + reading the calendar, which means that the calendar registers have been + correctly copied into the RTC_TR and RTC_DR shadow registers. + The RTC_WaitForSynchro() function implements the above software sequence + (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are deinitialized + * - ERROR: RTC registers are not deinitialized + */ +ErrorStatus RTC_DeInit(void) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Reset TR, DR and CR registers */ + RTC->TR = (uint32_t)0x00000000; + RTC->DR = (uint32_t)0x00002101; + /* Reset All CR bits except CR[2:0] */ + RTC->CR &= (uint32_t)0x00000007; + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; + wutcounter++; + } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) + { + status = ERROR; + } + else + { + /* Reset all RTC CR register bits */ + RTC->CR &= (uint32_t)0x00000000; + RTC->WUTR = (uint32_t)0x0000FFFF; + RTC->PRER = (uint32_t)0x007F00FF; + RTC->CALIBR = (uint32_t)0x00000000; + RTC->ALRMAR = (uint32_t)0x00000000; + RTC->ALRMBR = (uint32_t)0x00000000; + + /* Reset ISR register and exit initialization mode */ + RTC->ISR = (uint32_t)0x00000000; + + /* Reset Tamper and alternate functions configuration register */ + RTC->TAFCR = 0x00000000; + + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Clear RTC CR FMT Bit */ + RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); + /* Set RTC_CR register */ + RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); + + /* Configure the RTC PRER */ + RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); + RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_InitStruct member with its default value. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) +{ + /* Initialize the RTC_HourFormat member */ + RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; + + /* Initialize the RTC_AsynchPrediv member */ + RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; + + /* Initialize the RTC_SynchPrediv member */ + RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; +} + +/** + * @brief Enables or disables the RTC registers write protection. + * @note All the RTC registers are write protected except for RTC_ISR[13:8], + * RTC_TAFCR and RTC_BKPxR. + * @note Writing a wrong key reactivates the write protection. + * @note The protection mechanism is not affected by system reset. + * @param NewState: new state of the write protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_WriteProtectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + } +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus RTC_EnterInitMode(void) +{ + __IO uint32_t initcounter = 0x00; + ErrorStatus status = ERROR; + uint32_t initstatus = 0x00; + + /* Check if the Initialization mode is set */ + if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + RTC->ISR = (uint32_t)RTC_INIT_MASK; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do + { + initstatus = RTC->ISR & RTC_ISR_INITF; + initcounter++; + } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_INITF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + } + else + { + status = SUCCESS; + } + + return (status); +} + +/** + * @brief Exits the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @param None + * @retval None + */ +void RTC_ExitInitMode(void) +{ + /* Exit Initialization mode */ + RTC->ISR &= (uint32_t)~RTC_ISR_INIT; +} + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus RTC_WaitForSynchro(void) +{ + __IO uint32_t synchrocounter = 0; + ErrorStatus status = ERROR; + uint32_t synchrostatus = 0x00; + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear RSF flag */ + RTC->ISR &= (uint32_t)RTC_RSF_MASK; + + /* Wait the registers to be synchronised */ + do + { + synchrostatus = RTC->ISR & RTC_ISR_RSF; + synchrocounter++; + } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_RSF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return (status); +} + +/** + * @brief Enables or disables the RTC reference clock detection. + * @param NewState: new state of the RTC reference clock. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC reference clock detection is enabled + * - ERROR: RTC reference clock detection is disabled + */ +ErrorStatus RTC_RefClockCmd(FunctionalState NewState) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (NewState != DISABLE) + { + /* Enable the RTC reference clock detection */ + RTC->CR |= RTC_CR_REFCKON; + } + else + { + /* Disable the RTC reference clock detection */ + RTC->CR &= ~RTC_CR_REFCKON; + } + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @} + */ + +/** @defgroup RTC_Group2 Time and Date configuration functions + * @brief Time and Date configuration functions + * +@verbatim + =============================================================================== + Time and Date configuration functions + =============================================================================== + + This section provide functions allowing to program and read the RTC Calendar + (Time and Date). + +@endverbatim + * @{ + */ + +/** + * @brief Set the RTC current time. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == RTC_Format_BIN) + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + RTC_TimeStruct->RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); + } + else + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + RTC_TimeStruct->RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ + ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); + } + else + { + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ + (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_TR register */ + RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_TimeStruct member with its default value + * (Time = 00h:00min:00sec). + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->RTC_H12 = RTC_H12_AM; + RTC_TimeStruct->RTC_Hours = 0; + RTC_TimeStruct->RTC_Minutes = 0; + RTC_TimeStruct->RTC_Seconds = 0; +} + +/** + * @brief Get the RTC current Time. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contain the returned current time configuration. + * @retval None + */ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); + RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); + RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); + RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); + RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); + } +} + +/** + * @brief Set the RTC current date. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * the date configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Date register is configured + * - ERROR: RTC Date register is not configured + */ +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) + { + RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; + } + if (RTC_Format == RTC_Format_BIN) + { + assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); + assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); + assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); + tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); + assert_param(IS_RTC_MONTH(tmpreg)); + tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); + assert_param(IS_RTC_DATE(tmpreg)); + } + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ + (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_DateStruct->RTC_Date) | \ + (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); + } + else + { + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ + ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_DR register */ + RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_DateStruct member with its default value + * (Monday, January 01 xx00). + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; + RTC_DateStruct->RTC_Date = 1; + RTC_DateStruct->RTC_Month = RTC_Month_January; + RTC_DateStruct->RTC_Year = 0; +} + +/** + * @brief Get the RTC current date. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will + * contain the returned current date configuration. + * @retval None + */ +void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); + RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); + RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); + RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); + RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); + RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group3 Alarms configuration functions + * @brief Alarms (Alarm A and Alarm B) configuration functions + * +@verbatim + =============================================================================== + Alarms (Alarm A and Alarm B) configuration functions + =============================================================================== + + This section provide functions allowing to program and read the RTC Alarms. + +@endverbatim + * @{ + */ + +/** + * @brief Set the specified RTC Alarm. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the RTC_AlarmCmd(DISABLE)). + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval None + */ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); + + if (RTC_Format == RTC_Format_BIN) + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); + + if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + } + else + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); + + if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + } + else + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + } + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + else + { + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm register */ + if (RTC_Alarm == RTC_Alarm_A) + { + RTC->ALRMAR = (uint32_t)tmpreg; + } + else + { + RTC->ALRMBR = (uint32_t)tmpreg; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Fills each RTC_AlarmStruct member with its default value + * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = + * all fields are masked). + * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which + * will be initialized. + * @retval None + */ +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; + + /* Alarm Date Settings : Date = 1st day of the month */ + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; + RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will + * contains the output alarm configuration values. + * @retval None + */ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM(RTC_Alarm)); + + /* Get the RTC_ALRMxR register */ + if (RTC_Alarm == RTC_Alarm_A) + { + tmpreg = (uint32_t)(RTC->ALRMAR); + } + else + { + tmpreg = (uint32_t)(RTC->ALRMBR); + } + + /* Fill the structure with the read parameters */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ + RTC_ALRMAR_HU)) >> 16); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ + RTC_ALRMAR_MNU)) >> 8); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ + RTC_ALRMAR_SU)); + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); + + if (RTC_Format == RTC_Format_BIN) + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Hours); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Minutes); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Seconds); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + } +} + +/** + * @brief Enables or disables the specified RTC Alarm. + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be any combination of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param NewState: new state of the specified alarm. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Alarm is enabled/disabled + * - ERROR: RTC Alarm is not enabled/disabled + */ +ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) +{ + __IO uint32_t alarmcounter = 0x00; + uint32_t alarmstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm state */ + if (NewState != DISABLE) + { + RTC->CR |= (uint32_t)RTC_Alarm; + + status = SUCCESS; + } + else + { + /* Disable the Alarm in RTC_CR register */ + RTC->CR &= (uint32_t)~RTC_Alarm; + + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ + do + { + alarmstatus = RTC->ISR & (RTC_Alarm >> 8); + alarmcounter++; + } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); + + if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @} + */ + +/** @defgroup RTC_Group4 WakeUp Timer configuration functions + * @brief WakeUp Timer configuration functions + * +@verbatim + =============================================================================== + WakeUp Timer configuration functions + =============================================================================== + + This section provide functions allowing to program and read the RTC WakeUp. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Wakeup clock source. + * @note The WakeUp Clock source can only be changed when the RTC WakeUp + * is disabled (Use the RTC_WakeUpCmd(DISABLE)). + * @param RTC_WakeUpClock: Wakeup Clock source. + * This parameter can be one of the following values: + * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 + * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 + * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 + * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 + * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE + * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE + * @retval None + */ +void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) +{ + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the Wakeup Timer clock source bits in CR register */ + RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + RTC->CR |= (uint32_t)RTC_WakeUpClock; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Configures the RTC Wakeup counter. + * @note The RTC WakeUp counter can only be written when the RTC WakeUp + * is disabled (Use the RTC_WakeUpCmd(DISABLE)). + * @param RTC_WakeUpCounter: specifies the WakeUp counter. + * This parameter can be a value from 0x0000 to 0xFFFF. + * @retval None + */ +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) +{ + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Wakeup Timer counter */ + RTC->WUTR = (uint32_t)RTC_WakeUpCounter; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Returns the RTC WakeUp timer counter value. + * @param None + * @retval The RTC WakeUp Counter value. + */ +uint32_t RTC_GetWakeUpCounter(void) +{ + /* Get the counter value */ + return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); +} + +/** + * @brief Enables or Disables the RTC WakeUp timer. + * @param NewState: new state of the WakeUp timer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Enable the Wakeup Timer */ + RTC->CR |= (uint32_t)RTC_CR_WUTE; + status = SUCCESS; + } + else + { + /* Disable the Wakeup Timer */ + RTC->CR &= (uint32_t)~RTC_CR_WUTE; + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; + wutcounter++; + } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @} + */ + +/** @defgroup RTC_Group5 Daylight Saving configuration functions + * @brief Daylight Saving configuration functions + * +@verbatim + =============================================================================== + Daylight Saving configuration functions + =============================================================================== + + This section provide functions allowing to configure the RTC DayLight Saving. + +@endverbatim + * @{ + */ + +/** + * @brief Adds or substract one hour from the current time. + * @param RTC_DayLightSaveOperation: the value of hour adjustment. + * This parameter can be one of the following values: + * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) + * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) + * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit + * in CR register to store the operation. + * This parameter can be one of the following values: + * @arg RTC_StoreOperation_Reset: BCK Bit Reset + * @arg RTC_StoreOperation_Set: BCK Bit Set + * @retval None + */ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) +{ + /* Check the parameters */ + assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the bits to be configured */ + RTC->CR &= (uint32_t)~(RTC_CR_BCK); + + /* Configure the RTC_CR register */ + RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Returns the RTC Day Light Saving stored operation. + * @param None + * @retval RTC Day Light Saving stored operation. + * - RTC_StoreOperation_Reset + * - RTC_StoreOperation_Set + */ +uint32_t RTC_GetStoreOperation(void) +{ + return (RTC->CR & RTC_CR_BCK); +} + +/** + * @} + */ + +/** @defgroup RTC_Group6 Output pin Configuration function + * @brief Output pin Configuration function + * +@verbatim + =============================================================================== + Output pin Configuration function + =============================================================================== + + This section provide functions allowing to configure the RTC Output source. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC output source (AFO_ALARM). + * @param RTC_Output: Specifies which signal will be routed to the RTC output. + * This parameter can be one of the following values: + * @arg RTC_Output_Disable: No output selected + * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output + * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output + * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output + * @param RTC_OutputPolarity: Specifies the polarity of the output signal. + * This parameter can be one of the following: + * @arg RTC_OutputPolarity_High: The output pin is high when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL) + * @arg RTC_OutputPolarity_Low: The output pin is low when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL) + * @retval None + */ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT(RTC_Output)); + assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the bits to be configured */ + RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); + + /* Configure the output selection and polarity */ + RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @} + */ + +/** @defgroup RTC_Group7 Coarse Calibration configuration functions + * @brief Coarse Calibration configuration functions + * +@verbatim + =============================================================================== + Coarse Calibration configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Coarse calibration parameters. + * @param RTC_CalibSign: specifies the sign of the coarse calibration value. + * This parameter can be one of the following values: + * @arg RTC_CalibSign_Positive: The value sign is positive + * @arg RTC_CalibSign_Negative: The value sign is negative + * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). + * + * @note This Calibration value should be between 0 and 63 when using negative + * sign with a 2-ppm step. + * + * @note This Calibration value should be between 0 and 126 when using positive + * sign with a 4-ppm step. + * + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Coarse calibration are initialized + * - ERROR: RTC Coarse calibration are not initialized + */ +ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); + assert_param(IS_RTC_CALIB_VALUE(Value)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the coarse calibration value */ + RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Enables or disables the Coarse calibration process. + * @param NewState: new state of the Coarse calibration. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Coarse calibration are enabled/disabled + * - ERROR: RTC Coarse calibration are not enabled/disabled + */ +ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (NewState != DISABLE) + { + /* Enable the Coarse Calibration */ + RTC->CR |= (uint32_t)RTC_CR_DCE; + } + else + { + /* Disable the Coarse Calibration */ + RTC->CR &= (uint32_t)~RTC_CR_DCE; + } + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Enables or disables the RTC clock to be output through the relative pin. + * @param NewState: new state of the digital calibration Output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_CalibOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Enable the RTC clock output */ + RTC->CR |= (uint32_t)RTC_CR_COE; + } + else + { + /* Disable the RTC clock output */ + RTC->CR &= (uint32_t)~RTC_CR_COE; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @} + */ + + +/** @defgroup RTC_Group8 TimeStamp configuration functions + * @brief TimeStamp configuration functions + * +@verbatim + =============================================================================== + TimeStamp configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or Disables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge. + * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following: + * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the + * falling edge of the related pin. + * @param NewState: new state of the TimeStamp. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Get the new configuration */ + if (NewState != DISABLE) + { + tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); + } + else + { + tmpreg |= (uint32_t)(RTC_TimeStampEdge); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CR = (uint32_t)tmpreg; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Get the RTC TimeStamp value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contains the TimeStamp time values. + * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will + * contains the TimeStamp date values. + * @retval None + */ +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, + RTC_DateTypeDef* RTC_StampDateStruct) +{ + uint32_t tmptime = 0, tmpdate = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); + RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); + + /* Fill the Date structure fields with the read parameters */ + RTC_StampDateStruct->RTC_Year = 0; + RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); + RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the Time structure parameters to Binary format */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); + + /* Convert the Date structure parameters to Binary format */ + RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); + RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group9 Tampers configuration functions + * @brief Tampers configuration functions + * +@verbatim + =============================================================================== + Tampers configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the select Tamper pin edge. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be RTC_Tamper_1. + * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that + * stimulates tamper event. + * This parameter can be one of the following values: + * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. + * @retval None + */ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + + if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) + { + /* Configure the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); + } + else + { + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); + } +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be RTC_Tamper_1. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TAFCR |= (uint32_t)RTC_Tamper; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TAFCR &= (uint32_t)~RTC_Tamper; + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group10 Backup Data Registers configuration functions + * @brief Backup Data Registers configuration functions + * +@verbatim + =============================================================================== + Backup Data Registers configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @param RTC_BKP_DR: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @param Data: Data to be written in the specified RTC Backup data register. + * @retval None + */ +void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + + tmp = RTC_BASE + 0x50; + tmp += (RTC_BKP_DR * 4); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param RTC_BKP_DR: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @retval None + */ +uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + + tmp = RTC_BASE + 0x50; + tmp += (RTC_BKP_DR * 4); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions + * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config + * configuration functions + * +@verbatim + =============================================================================== + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration + functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Selects the RTC Tamper Pin. + * @param RTC_TamperPin: specifies the RTC Tamper Pin. + * This parameter can be one of the following values: + * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin. + * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin. + * @retval None + */ +void RTC_TamperPinSelection(uint32_t RTC_TamperPin) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL); + RTC->TAFCR |= (uint32_t)(RTC_TamperPin); +} + +/** + * @brief Selects the RTC TimeStamp Pin. + * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin. + * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. + * @retval None + */ +void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin) +{ + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL); + RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); +} + +/** + * @brief Configures the RTC Output Pin mode. + * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in + * Open Drain mode. + * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in + * Push Pull mode. + * @retval None + */ +void RTC_OutputTypeConfig(uint32_t RTC_OutputType) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); + RTC->TAFCR |= (uint32_t)(RTC_OutputType); +} + +/** + * @} + */ + +/** @defgroup RTC_Group12 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + All RTC interrupts are connected to the EXTI controller. + + - To enable the RTC Alarm interrupt, the following sequence is required: + - Configure and enable the EXTI Line 17 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() + function. + - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using + the RTC_SetAlarm() and RTC_AlarmCmd() functions. + + - To enable the RTC Wakeup interrupt, the following sequence is required: + - Configure and enable the EXTI Line 22 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init() + function. + - Configure the RTC to generate the RTC wakeup timer event using the + RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + + - To enable the RTC Tamper interrupt, the following sequence is required: + - Configure and enable the EXTI Line 21 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() + function. + - Configure the RTC to detect the RTC tamper event using the + RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. + + - To enable the RTC TimeStamp interrupt, the following sequence is required: + - Configure and enable the EXTI Line 21 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() + function. + - Configure the RTC to detect the RTC time-stamp event using the + RTC_TimeStampCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt mask + * @arg RTC_IT_WUT: WakeUp Timer interrupt mask + * @arg RTC_IT_ALRB: Alarm B interrupt mask + * @arg RTC_IT_ALRA: Alarm A interrupt mask + * @arg RTC_IT_TAMP: Tamper event interrupt mask + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_CONFIG_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); + } + else + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_WUTF: WakeUp Timer flag + * @arg RTC_FLAG_ALRBF: Alarm B flag + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_INITF: Initialization mode flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_INITS: Registers Configured flag + * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag + * @arg RTC_FLAG_ALRBWF: Alarm B Write flag + * @arg RTC_FLAG_ALRAWF: Alarm A write flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + /* Get all the flags */ + tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); + + /* Return the status of the flag */ + if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG: specifies the RTC flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_WUTF: WakeUp Timer flag + * @arg RTC_FLAG_ALRBF: Alarm B flag + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @retval None + */ +void RTC_ClearFlag(uint32_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the Flags in the RTC_ISR register */ + RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_IT: specifies the RTC interrupt source to check. + * This parameter can be one of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt + * @arg RTC_IT_WUT: WakeUp Timer interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_TAMP1: Tamper 1 event interrupt + * @retval The new state of RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint32_t RTC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + /* Get the TAMPER Interrupt enable bit and pending bit */ + tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); + + /* Get the Interrupt enable Status */ + enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15))); + + /* Get the Interrupt pending bit */ + tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); + + /* Get the status of the Interrupt */ + if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_IT: specifies the RTC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt + * @arg RTC_IT_WUT: WakeUp Timer interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_TAMP1: Tamper 1 event interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint32_t RTC_IT) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_IT(RTC_IT)); + + /* Get the RTC_ISR Interrupt pending bits mask */ + tmpreg = (uint32_t)(RTC_IT >> 4); + + /* Clear the interrupt pending bits in the RTC_ISR register */ + RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); +} + +/** + * @} + */ + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value: Byte to be converted. + * @retval Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + + while (Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value: BCD value to be converted. + * @retval Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint8_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c index 515b24652..a4fafe50a 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c @@ -1,1010 +1,1010 @@ -/** - ****************************************************************************** - * @file stm32f2xx_sdio.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Secure digital input/output interface (SDIO) - * peripheral: - * - Initialization and Configuration - * - Command path state machine (CPSM) management - * - Data path state machine (DPSM) management - * - SDIO IO Cards mode management - * - CE-ATA mode management - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output - * of PLL (PLL48CLK). Before to start working with SDIO peripheral - * make sure that the PLL is well configured. - * The SDIO peripheral uses two clock signals: - * - SDIO adapter clock (SDIOCLK = 48 MHz) - * - APB2 bus clock (PCLK2) - * PCLK2 and SDIO_CK clock frequencies must respect the following condition: - * Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) - * - * 2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). - * - * 3. According to the SDIO mode, enable the GPIO clocks using - * RCC_AHB1PeriphClockCmd() function. - * The I/O can be one of the following configurations: - * - 1-bit data length: SDIO_CMD, SDIO_CK and D0. - * - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. - * - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. - * - * 4. Peripheral's alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, - * hardware, flow control and the Clock Divider using the SDIO_Init() - * function. - * - * 6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) - * function. - * - * 7. Enable the clock using the SDIO_ClockCmd() function. - * - * 8. Enable the NVIC and the corresponding interrupt using the function - * SDIO_ITConfig() if you need to use interrupt mode. - * - * 9. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using SDIO_DMACmd() function - * - * 10. Enable the DMA using the DMA_Cmd() function, when using DMA mode. - * - * 11. To control the CPSM (Command Path State Machine) and send - * commands to the card use the SDIO_SendCommand(), - * SDIO_GetCommandResponse() and SDIO_GetResponse() functions. - * First, user has to fill the command structure (pointer to - * SDIO_CmdInitTypeDef) according to the selected command to be sent. - * The parameters that should be filled are: - * - Command Argument - * - Command Index - * - Command Response type - * - Command Wait - * - CPSM Status (Enable or Disable) - * - * To check if the command is well received, read the SDIO_CMDRESP - * register using the SDIO_GetCommandResponse(). - * The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the - * SDIO_GetResponse() function. - * - * 12. To control the DPSM (Data Path State Machine) and send/receive - * data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), - * SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. - * - * Read Operations - * --------------- - * a) First, user has to fill the data structure (pointer to - * SDIO_DataInitTypeDef) according to the selected data type to - * be received. - * The parameters that should be filled are: - * - Data TimeOut - * - Data Length - * - Data Block size - * - Data Transfer direction: should be from card (To SDIO) - * - Data Transfer mode - * - DPSM Status (Enable or Disable) - * - * b) Configure the SDIO resources to receive the data from the card - * according to selected transfer mode (Refer to Step 8, 9 and 10). - * - * c) Send the selected Read command (refer to step 11). - * - * d) Use the SDIO flags/interrupts to check the transfer status. - * - * Write Operations - * --------------- - * a) First, user has to fill the data structure (pointer to - * SDIO_DataInitTypeDef) according to the selected data type to - * be received. - * The parameters that should be filled are: - * - Data TimeOut - * - Data Length - * - Data Block size - * - Data Transfer direction: should be to card (To CARD) - * - Data Transfer mode - * - DPSM Status (Enable or Disable) - * - * b) Configure the SDIO resources to send the data to the card - * according to selected transfer mode (Refer to Step 8, 9 and 10). - * - * c) Send the selected Write command (refer to step 11). - * - * d) Use the SDIO flags/interrupts to check the transfer status. - * - * - * @endverbatim - * - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_sdio.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ -/* --- CLKCR Register ---*/ -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** @defgroup SDIO_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF: SDIO Power OFF - * @arg SDIO_PowerState_ON: SDIO Power ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER = SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can be one of the - * following values: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions - * @brief Command path state machine (CPSM) management functions - * -@verbatim - =============================================================================== - Command path state machine (CPSM) management functions - =============================================================================== - - This section provide functions allowing to program and read the Command path - state machine (CPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO - * command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions - * @brief Data path state machine (DPSM) management functions - * -@verbatim - =============================================================================== - Data path state machine (DPSM) management functions - =============================================================================== - - This section provide functions allowing to program and read the Data path - state machine (DPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure - * that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure - * which will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions - * @brief SDIO IO Cards mode management functions - * -@verbatim - =============================================================================== - SDIO IO Cards mode management functions - =============================================================================== - - This section provide functions allowing to program and read the SDIO IO Cards. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parameter can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group5 CE-ATA mode management functions - * @brief CE-ATA mode management functions - * -@verbatim - =============================================================================== - CE-ATA mode management functions - =============================================================================== - - This section provide functions allowing to program and read the CE-ATA card. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group6 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - - This section provide functions allowing to program SDIO DMA transfer. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_sdio.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Secure digital input/output interface (SDIO) + * peripheral: + * - Initialization and Configuration + * - Command path state machine (CPSM) management + * - Data path state machine (DPSM) management + * - SDIO IO Cards mode management + * - CE-ATA mode management + * - DMA transfers management + * - Interrupts and flags management + * + * @verbatim + * + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output + * of PLL (PLL48CLK). Before to start working with SDIO peripheral + * make sure that the PLL is well configured. + * The SDIO peripheral uses two clock signals: + * - SDIO adapter clock (SDIOCLK = 48 MHz) + * - APB2 bus clock (PCLK2) + * PCLK2 and SDIO_CK clock frequencies must respect the following condition: + * Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) + * + * 2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). + * + * 3. According to the SDIO mode, enable the GPIO clocks using + * RCC_AHB1PeriphClockCmd() function. + * The I/O can be one of the following configurations: + * - 1-bit data length: SDIO_CMD, SDIO_CK and D0. + * - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. + * - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. + * + * 4. Peripheral's alternate function: + * - Connect the pin to the desired peripherals' Alternate + * Function (AF) using GPIO_PinAFConfig() function + * - Configure the desired pin in alternate function by: + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * + * 5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, + * hardware, flow control and the Clock Divider using the SDIO_Init() + * function. + * + * 6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) + * function. + * + * 7. Enable the clock using the SDIO_ClockCmd() function. + * + * 8. Enable the NVIC and the corresponding interrupt using the function + * SDIO_ITConfig() if you need to use interrupt mode. + * + * 9. When using the DMA mode + * - Configure the DMA using DMA_Init() function + * - Active the needed channel Request using SDIO_DMACmd() function + * + * 10. Enable the DMA using the DMA_Cmd() function, when using DMA mode. + * + * 11. To control the CPSM (Command Path State Machine) and send + * commands to the card use the SDIO_SendCommand(), + * SDIO_GetCommandResponse() and SDIO_GetResponse() functions. + * First, user has to fill the command structure (pointer to + * SDIO_CmdInitTypeDef) according to the selected command to be sent. + * The parameters that should be filled are: + * - Command Argument + * - Command Index + * - Command Response type + * - Command Wait + * - CPSM Status (Enable or Disable) + * + * To check if the command is well received, read the SDIO_CMDRESP + * register using the SDIO_GetCommandResponse(). + * The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the + * SDIO_GetResponse() function. + * + * 12. To control the DPSM (Data Path State Machine) and send/receive + * data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), + * SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. + * + * Read Operations + * --------------- + * a) First, user has to fill the data structure (pointer to + * SDIO_DataInitTypeDef) according to the selected data type to + * be received. + * The parameters that should be filled are: + * - Data TimeOut + * - Data Length + * - Data Block size + * - Data Transfer direction: should be from card (To SDIO) + * - Data Transfer mode + * - DPSM Status (Enable or Disable) + * + * b) Configure the SDIO resources to receive the data from the card + * according to selected transfer mode (Refer to Step 8, 9 and 10). + * + * c) Send the selected Read command (refer to step 11). + * + * d) Use the SDIO flags/interrupts to check the transfer status. + * + * Write Operations + * --------------- + * a) First, user has to fill the data structure (pointer to + * SDIO_DataInitTypeDef) according to the selected data type to + * be received. + * The parameters that should be filled are: + * - Data TimeOut + * - Data Length + * - Data Block size + * - Data Transfer direction: should be to card (To CARD) + * - Data Transfer mode + * - DPSM Status (Enable or Disable) + * + * b) Configure the SDIO resources to send the data to the card + * according to selected transfer mode (Refer to Step 8, 9 and 10). + * + * c) Send the selected Write command (refer to step 11). + * + * d) Use the SDIO flags/interrupts to check the transfer status. + * + * + * @endverbatim + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ +/* --- CLKCR Register ---*/ +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMD Register ---*/ +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SDIO_Private_Functions + * @{ + */ + +/** @defgroup SDIO_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default reset values. + * @param None + * @retval None + */ +void SDIO_DeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * @retval None + */ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param NewState: new state of the SDIO Clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState: new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_PowerState_OFF: SDIO Power OFF + * @arg SDIO_PowerState_ON: SDIO Power ON + * @retval None + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER = SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @param None + * @retval Power status of the controller. The returned value can be one of the + * following values: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/** + * @} + */ + +/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions + * @brief Command path state machine (CPSM) management functions + * +@verbatim + =============================================================================== + Command path state machine (CPSM) management functions + =============================================================================== + + This section provide functions allowing to program and read the Command path + state machine (CPSM). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for the SDIO + * command. + * @retval None + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * @retval None + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/** + * @brief Returns command index of last command for which response received. + * @param None + * @retval Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @} + */ + +/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions + * @brief Data path state machine (DPSM) management functions + * +@verbatim + =============================================================================== + Data path state machine (DPSM) management functions + =============================================================================== + + This section provide functions allowing to program and read the Data path + state machine (DPSM). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure + * that contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure + * which will be initialized. + * @retval None + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param None + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/** + * @brief Read one data word from Rx FIFO. + * @param None + * @retval Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/** + * @brief Write one data word to Tx FIFO. + * @param Data: 32-bit data word to write. + * @retval None + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read from FIFO. + * @param None + * @retval Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions + * @brief SDIO IO Cards mode management functions + * +@verbatim + =============================================================================== + SDIO IO Cards mode management functions + =============================================================================== + + This section provide functions allowing to program and read the SDIO IO Cards. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param NewState: new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param NewState: new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parameter can be: + * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 + * @retval None + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param NewState: new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param NewState: new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group5 CE-ATA mode management functions + * @brief CE-ATA mode management functions + * +@verbatim + =============================================================================== + CE-ATA mode management functions + =============================================================================== + + This section provide functions allowing to program and read the CE-ATA card. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the command completion signal. + * @param NewState: new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param NewState: new state of CE-ATA interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param NewState: new state of CE-ATA command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group6 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + DMA transfers management functions + =============================================================================== + + This section provide functions allowing to program SDIO DMA transfer. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SDIO DMA request. + * @param NewState: new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group7 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @param NewState: new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's interrupt pending bits. + * @param SDIO_IT: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c index 0a42a0f2c..df2f66610 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c @@ -1,1183 +1,1183 @@ -/** - ****************************************************************************** - * @file stm32f2xx_spi.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial peripheral interface (SPI): - * - Initialization and Configuration - * - Data transfers functions - * - Hardware CRC Calculation - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable peripheral clock using the following functions - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 - * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3. - * - * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() - * function. - * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO - * clock should also be enabled. - * - * 3. Peripherals alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * In I2S mode, if an external clock source is used then the I2S CKIN pin - * should be also configured in Alternate function Push-pull pull-up mode. - * - * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave - * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - * function. - * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio - * frequency and Polarity using I2S_Init() function. - * For I2S mode, make sure that either: - * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), - * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY). - * or - * - External clock source is configured using the function - * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant - * I2S_EXTERNAL_CLOCK_VAL in the stm32f2xx_conf.h file. - * - * 5. Enable the NVIC and the corresponding interrupt using the function - * SPI_ITConfig() if you need to use interrupt mode. - * - * 6. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using SPI_I2S_DMACmd() function - * - * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using - * I2S_Cmd(). - * - * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. - * - * 9. Optionally, you can enable/configure the following parameters without - * re-initialization (i.e there is no need to call again SPI_Init() function): - * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) - * is programmed as Data direction parameter using the SPI_Init() function - * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx - * using the SPI_BiDirectionalLineConfig() function. - * - When SPI_NSS_Soft is selected as Slave Select Management parameter - * using the SPI_Init() function it can be possible to manage the - * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. - * - Reconfigure the data size using the SPI_DataSizeConfig() function - * - Enable or disable the SS output using the SPI_SSOutputCmd() function - * - * 10. To use the CRC Hardware calculation feature refer to the Peripheral - * CRC hardware Calculation subsection. - * - * - * @note This driver supports only the I2S clock scheme available in Silicon - * RevisionB and RevisionY. - * - * @note In I2S mode: if an external clock is used as source clock for the I2S, - * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should - * be enabled and set to the value of the source clock frequency (in Hz). - * - * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() - * just after calling the function SPI_Init(). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "../inc/stm32f2xx_spi.h" -#include "../inc/stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* SPI registers Masks */ -#define CR1_CLEAR_MASK ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) - -/* RCC PLLs masks */ -#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) -#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) - -#define SPI_CR2_FRF ((uint16_t)0x0010) -#define SPI_SR_TIFRFE ((uint16_t)0x0100) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** @defgroup SPI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This section provides a set of functions allowing to initialize the SPI Direction, - SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud - Rate Prescaler, SPI First Bit and SPI CRC Polynomial. - - The SPI_Init() function follows the SPI configuration procedures for Master mode - and Slave mode (details for these procedures are available in reference manual - (RM0033)). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the SPIx peripheral registers to their default reset values. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * - * @note The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. - * - * @note if an external clock is used as source clock for the I2S, then the define - * I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should be enabled and set - * to the value of the the source clock frequency (in Hz). - * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; -#ifndef I2S_EXTERNAL_CLOCK_VAL - uint32_t pllm = 0, plln = 0, pllr = 0; -#endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) *******************/ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */ - - /* If an external I2S clock has to be used, this define should be set - in the project configuration or in the stm32f2xx_conf.h file */ - #ifdef I2S_EXTERNAL_CLOCK_VAL - /* Set external clock as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) - { - RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; - } - - /* Set the I2S clock to the external clock value */ - i2sclk = I2S_EXTERNAL_CLOCK_VAL; - - #else /* There is no define for External I2S clock source */ - /* Set PLLI2S as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) - { - RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; - } - - /* Get the PLLI2SN value */ - plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ - (RCC_PLLI2SCFGR_PLLI2SN >> 6)); - - /* Get the PLLI2SR value */ - pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ - (RCC_PLLI2SCFGR_PLLI2SR >> 28)); - - /* Get the PLLM value */ - pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - - /* Get the I2S source clock value */ - i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); - #endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Compute the Real divider depending on the MCLK output state, with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the flatting point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= SPI_CR1_SPE; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; - } - else - { - /* Disable the selected SPI peripheral in I2S mode */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA - * are not taken into consideration and are configured by hardware - * respectively to the TI mode requirements. - * - * @param SPIx: where x can be 1, 2 or 3 - * @param NewState: new state of the selected SPI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TI mode for the selected SPI peripheral */ - SPIx->CR2 |= SPI_CR2_FRF; - } - else - { - /* Disable the TI mode for the selected SPI peripheral */ - SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - - This section provides a set of functions allowing to manage the SPI data transfers - - In reception, data are received and then stored into an internal Rx buffer while - In transmission, data are first stored into an internal Tx buffer before being - transmitted. - - The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SPI_DR - can be done using SPI_I2S_SendData() function and stores the written data into - Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @} - */ - -/** @defgroup SPI_Group3 Hardware CRC Calculation functions - * @brief Hardware CRC Calculation functions - * -@verbatim - =============================================================================== - Hardware CRC Calculation functions - =============================================================================== - - This section provides a set of functions allowing to manage the SPI CRC hardware - calculation - - SPI communication using CRC is possible through the following procedure: - 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, - Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - 2. Enable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the SPI using the SPI_Cmd() function - 4. Before writing the last data to the TX buffer, set the CRCNext bit using the - SPI_TransmitCRC() function to indicate that after transmission of the last - data, the CRC should be transmitted. - 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT - bit is reset. The CRC is also received and compared against the SPI_RXCRCR - value. - If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt - can be generated when the SPI_I2S_IT_ERR interrupt is enabled. - -@note It is advised not to read the calculated CRC values during the communication. - -@note When the SPI is in slave mode, be careful to enable CRC calculation only - when the clock is stable, that is, when the clock is in the steady state. - If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive - to the SCK slave input clock as soon as CRCEN is set, and this, whatever - the value of the SPE bit. - -@note With high bitrate frequencies, be careful when transmitting the CRC. - As the number of used CPU cycles has to be as low as possible in the CRC - transfer phase, it is forbidden to call software functions in the CRC - transmission sequence to avoid errors in the last data and CRC reception. - In fact, CRCNEXT bit has to be written before the end of the transmission/reception - of the last data. - -@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the - degradation of the SPI speed performance due to CPU accesses impacting the - SPI bandwidth. - -@note When the STM32F2xx is configured as slave and the NSS hardware mode is - used, the NSS pin needs to be kept low between the data phase and the CRC - phase. - -@note When the SPI is configured in slave mode with the CRC feature enabled, CRC - calculation takes place even if a high level is applied on the NSS pin. - This may happen for example in case of a multi-slave environment where the - communication master addresses slaves alternately. - -@note Between a slave de-selection (high level on NSS) and a new slave selection - (low level on NSS), the CRC value should be cleared on both master and slave - sides in order to resynchronize the master and slave for their respective - CRC calculation. - -@note To clear the CRC, follow the procedure below: - 1. Disable SPI using the SPI_Cmd() function - 2. Disable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the CRC calculation using the SPI_CalculateCRC() function. - 4. Enable SPI using the SPI_Cmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= SPI_CR1_CRCEN; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); - } -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= SPI_CR1_CRCNEXT; -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @} - */ - -/** @defgroup SPI_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides a set of functions allowing to configure the SPI Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - Polling Mode - ============= - In Polling Mode, the SPI/I2S communication can be managed by 9 flags: - 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register - 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. - 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur - 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur - 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur - 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. - 8. I2S_FLAG_UDR: to indicate an Underrun error occurs. - 9. I2S_FLAG_CHSIDE: to indicate Channel Side. - -@note Do not use the BSY flag to handle each data transmission or reception. It is - better to use the TXE and RXNE flags instead. - - In this Mode it is advised to use the following functions: - - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - Interrupt Mode - =============== - In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources - and 7 pending bits: - Pending Bits: - ------------- - 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register - 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) - 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) - 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur - 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). - 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). - - Interrupt Source: - ----------------- - 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty - interrupt. - 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. - - In this Mode it is advised to use the following functions: - - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - DMA Mode - ======== - In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: - 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request - 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - In this Mode it is advised to use the following function: - - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Checks whether the specified SPIx/I2Sx flag is set or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg SPI_I2S_FLAG_TIFRFE: Format Error. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - - /* Check the status of the specified SPI flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * - * @note OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun interrupt. - * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S_IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI_I2S_IT IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR interrupt pending bit. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * - * @note OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_spi.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Serial peripheral interface (SPI): + * - Initialization and Configuration + * - Data transfers functions + * - Hardware CRC Calculation + * - DMA transfers management + * - Interrupts and flags management + * + * @verbatim + * + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable peripheral clock using the following functions + * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 + * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 + * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3. + * + * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() + * function. + * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO + * clock should also be enabled. + * + * 3. Peripherals alternate function: + * - Connect the pin to the desired peripherals' Alternate + * Function (AF) using GPIO_PinAFConfig() function + * - Configure the desired pin in alternate function by: + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * In I2S mode, if an external clock source is used then the I2S CKIN pin + * should be also configured in Alternate function Push-pull pull-up mode. + * + * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave + * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + * function. + * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio + * frequency and Polarity using I2S_Init() function. + * For I2S mode, make sure that either: + * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), + * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY). + * or + * - External clock source is configured using the function + * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant + * I2S_EXTERNAL_CLOCK_VAL in the stm32f2xx_conf.h file. + * + * 5. Enable the NVIC and the corresponding interrupt using the function + * SPI_ITConfig() if you need to use interrupt mode. + * + * 6. When using the DMA mode + * - Configure the DMA using DMA_Init() function + * - Active the needed channel Request using SPI_I2S_DMACmd() function + * + * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using + * I2S_Cmd(). + * + * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. + * + * 9. Optionally, you can enable/configure the following parameters without + * re-initialization (i.e there is no need to call again SPI_Init() function): + * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) + * is programmed as Data direction parameter using the SPI_Init() function + * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx + * using the SPI_BiDirectionalLineConfig() function. + * - When SPI_NSS_Soft is selected as Slave Select Management parameter + * using the SPI_Init() function it can be possible to manage the + * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. + * - Reconfigure the data size using the SPI_DataSizeConfig() function + * - Enable or disable the SS output using the SPI_SSOutputCmd() function + * + * 10. To use the CRC Hardware calculation feature refer to the Peripheral + * CRC hardware Calculation subsection. + * + * + * @note This driver supports only the I2S clock scheme available in Silicon + * RevisionB and RevisionY. + * + * @note In I2S mode: if an external clock is used as source clock for the I2S, + * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should + * be enabled and set to the value of the source clock frequency (in Hz). + * + * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() + * just after calling the function SPI_Init(). + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/stm32f2xx_spi.h" +#include "../inc/stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* SPI registers Masks */ +#define CR1_CLEAR_MASK ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) + +/* RCC PLLs masks */ +#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) +#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) + +#define SPI_CR2_FRF ((uint16_t)0x0010) +#define SPI_SR_TIFRFE ((uint16_t)0x0100) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** @defgroup SPI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + + This section provides a set of functions allowing to initialize the SPI Direction, + SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud + Rate Prescaler, SPI First Bit and SPI CRC Polynomial. + + The SPI_Init() function follows the SPI configuration procedures for Master mode + and Slave mode (details for these procedures are available in reference manual + (RM0033)). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the SPIx peripheral registers to their default reset values. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * + * @note The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. + * + * @note if an external clock is used as source clock for the I2S, then the define + * I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should be enabled and set + * to the value of the the source clock frequency (in Hz). + * + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0, i2sclk = 0; +#ifndef I2S_EXTERNAL_CLOCK_VAL + uint32_t pllm = 0, plln = 0, pllr = 0; +#endif /* I2S_EXTERNAL_CLOCK_VAL */ + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) *******************/ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */ + + /* If an external I2S clock has to be used, this define should be set + in the project configuration or in the stm32f2xx_conf.h file */ + #ifdef I2S_EXTERNAL_CLOCK_VAL + /* Set external clock as I2S clock source */ + if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) + { + RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; + } + + /* Set the I2S clock to the external clock value */ + i2sclk = I2S_EXTERNAL_CLOCK_VAL; + + #else /* There is no define for External I2S clock source */ + /* Set PLLI2S as I2S clock source */ + if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) + { + RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; + } + + /* Get the PLLI2SN value */ + plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ + (RCC_PLLI2SCFGR_PLLI2SN >> 6)); + + /* Get the PLLI2SR value */ + pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ + (RCC_PLLI2SCFGR_PLLI2SR >> 28)); + + /* Get the PLLM value */ + pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + + /* Get the I2S source clock value */ + i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); + #endif /* I2S_EXTERNAL_CLOCK_VAL */ + + /* Compute the Real divider depending on the MCLK output state, with a floating point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the flatting point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= SPI_CR1_SPE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; + } + else + { + /* Disable the selected SPI peripheral in I2S mode */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * + * @note This function can be called only after the SPI_Init() function has + * been called. + * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA + * are not taken into consideration and are configured by hardware + * respectively to the TI mode requirements. + * + * @param SPIx: where x can be 1, 2 or 3 + * @param NewState: new state of the selected SPI TI communication mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TI mode for the selected SPI peripheral */ + SPIx->CR2 |= SPI_CR2_FRF; + } + else + { + /* Disable the TI mode for the selected SPI peripheral */ + SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; + } +} + +/** + * @} + */ + +/** @defgroup SPI_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + Data transfers functions + =============================================================================== + + This section provides a set of functions allowing to manage the SPI data transfers + + In reception, data are received and then stored into an internal Rx buffer while + In transmission, data are first stored into an internal Tx buffer before being + transmitted. + + The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() + function and returns the Rx buffered value. Whereas a write access to the SPI_DR + can be done using SPI_I2S_SendData() function and stores the written data into + Tx buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param Data: Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @} + */ + +/** @defgroup SPI_Group3 Hardware CRC Calculation functions + * @brief Hardware CRC Calculation functions + * +@verbatim + =============================================================================== + Hardware CRC Calculation functions + =============================================================================== + + This section provides a set of functions allowing to manage the SPI CRC hardware + calculation + + SPI communication using CRC is possible through the following procedure: + 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, + Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + function. + 2. Enable the CRC calculation using the SPI_CalculateCRC() function. + 3. Enable the SPI using the SPI_Cmd() function + 4. Before writing the last data to the TX buffer, set the CRCNext bit using the + SPI_TransmitCRC() function to indicate that after transmission of the last + data, the CRC should be transmitted. + 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT + bit is reset. The CRC is also received and compared against the SPI_RXCRCR + value. + If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt + can be generated when the SPI_I2S_IT_ERR interrupt is enabled. + +@note It is advised not to read the calculated CRC values during the communication. + +@note When the SPI is in slave mode, be careful to enable CRC calculation only + when the clock is stable, that is, when the clock is in the steady state. + If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive + to the SCK slave input clock as soon as CRCEN is set, and this, whatever + the value of the SPE bit. + +@note With high bitrate frequencies, be careful when transmitting the CRC. + As the number of used CPU cycles has to be as low as possible in the CRC + transfer phase, it is forbidden to call software functions in the CRC + transmission sequence to avoid errors in the last data and CRC reception. + In fact, CRCNEXT bit has to be written before the end of the transmission/reception + of the last data. + +@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the + degradation of the SPI speed performance due to CPU accesses impacting the + SPI bandwidth. + +@note When the STM32F2xx is configured as slave and the NSS hardware mode is + used, the NSS pin needs to be kept low between the data phase and the CRC + phase. + +@note When the SPI is configured in slave mode with the CRC feature enabled, CRC + calculation takes place even if a high level is applied on the NSS pin. + This may happen for example in case of a multi-slave environment where the + communication master addresses slaves alternately. + +@note Between a slave de-selection (high level on NSS) and a new slave selection + (low level on NSS), the CRC value should be cleared on both master and slave + sides in order to resynchronize the master and slave for their respective + CRC calculation. + +@note To clear the CRC, follow the procedure below: + 1. Disable SPI using the SPI_Cmd() function + 2. Disable the CRC calculation using the SPI_CalculateCRC() function. + 3. Enable the CRC calculation using the SPI_CalculateCRC() function. + 4. Enable SPI using the SPI_Cmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= SPI_CR1_CRCEN; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); + } +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= SPI_CR1_CRCNEXT; +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @} + */ + +/** @defgroup SPI_Group4 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + DMA transfers management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @} + */ + +/** @defgroup SPI_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides a set of functions allowing to configure the SPI Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + Polling Mode + ============= + In Polling Mode, the SPI/I2S communication can be managed by 9 flags: + 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register + 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register + 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. + 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur + 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur + 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur + 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. + 8. I2S_FLAG_UDR: to indicate an Underrun error occurs. + 9. I2S_FLAG_CHSIDE: to indicate Channel Side. + +@note Do not use the BSY flag to handle each data transmission or reception. It is + better to use the TXE and RXNE flags instead. + + In this Mode it is advised to use the following functions: + - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + + Interrupt Mode + =============== + In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources + and 7 pending bits: + Pending Bits: + ------------- + 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register + 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register + 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) + 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) + 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur + 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). + 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). + + Interrupt Source: + ----------------- + 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty + interrupt. + 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. + + In this Mode it is advised to use the following functions: + - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); + - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + + DMA Mode + ======== + In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: + 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request + 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request + + In this Mode it is advised to use the following function: + - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Checks whether the specified SPIx/I2Sx flag is set or not. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_FLAG: specifies the SPI flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg SPI_I2S_FLAG_TIFRFE: Format Error. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + + /* Check the status of the specified SPI flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * + * @note OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * @note UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_IT: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun interrupt. + * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI_I2S_IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI_I2S_IT IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR interrupt pending bit. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * + * @note OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI_I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c index 83c9da675..ba87ffa52 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c @@ -1,210 +1,210 @@ -/** - ****************************************************************************** - * @file stm32f2xx_syscfg.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the SYSCFG peripheral. - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * This driver provides functions for: - * - * 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() - * - * 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() - * - * 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() - * - * @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers, - * using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_syscfg.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SYSCFG - * @brief SYSCFG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) -/* --- PMC Register ---*/ -/* Alias word address of MII_RMII_SEL bit */ -#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) -#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) - -/* --- CMPCR Register ---*/ -/* Alias word address of CMP_PD bit */ -#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) -#define CMP_PD_BitNumber ((uint8_t)0x00) -#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SYSCFG_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) - * registers to their default reset values. - * @param None - * @retval None - */ -void SYSCFG_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); -} - -/** - * @brief Changes the mapping of the specified pin. - * @param SYSCFG_Memory: selects the memory remapping. - * This parameter can be one of the following values: - * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 - * - * @note In remap mode, the FSMC addressing is fixed to the remap address area only - * (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) and FSMC control registers are not - * accessible. The FSMC remap function must be disabled to allows addressing - * other memory devices through the FSMC and/or to access FSMC control - * registers. - * - * @retval None - */ -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); - - SYSCFG->MEMRMP = SYSCFG_MemoryRemap; -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for - * EXTI lines where x can be (A..I). - * @param EXTI_PinSourcex: specifies the EXTI line to be configured. - * This parameter can be EXTI_PinSourcex where x can be (0..15, except - * for EXTI_PortSourceGPIOI x can be (0..11). - * @retval None - */ -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) -{ - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); - assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); - - tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); -} - -/** - * @brief Selects the ETHERNET media interface - * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected - * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected - * @retval None - */ -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) -{ - assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); - /* Configure MII_RMII selection bit */ - *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; -} - -/** - * @brief Enables or disables the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @param NewState: new state of the I/O Compensation Cell. - * This parameter can be one of the following values: - * @arg ENABLE: I/O compensation cell enabled - * @arg DISABLE: I/O compensation cell power-down mode - * @retval None - */ -void SYSCFG_CompensationCellCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the I/O Compensation Cell ready flag is set or not. - * @param None - * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) - */ -FlagStatus SYSCFG_GetCompensationCellStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_syscfg.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the SYSCFG peripheral. + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * + * This driver provides functions for: + * + * 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() + * + * 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() + * + * 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() + * + * @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers, + * using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SYSCFG + * @brief SYSCFG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) +/* --- PMC Register ---*/ +/* Alias word address of MII_RMII_SEL bit */ +#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) +#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) +#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) + +/* --- CMPCR Register ---*/ +/* Alias word address of CMP_PD bit */ +#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) +#define CMP_PD_BitNumber ((uint8_t)0x00) +#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SYSCFG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) + * registers to their default reset values. + * @param None + * @retval None + */ +void SYSCFG_DeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); +} + +/** + * @brief Changes the mapping of the specified pin. + * @param SYSCFG_Memory: selects the memory remapping. + * This parameter can be one of the following values: + * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 + * + * @note In remap mode, the FSMC addressing is fixed to the remap address area only + * (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) and FSMC control registers are not + * accessible. The FSMC remap function must be disabled to allows addressing + * other memory devices through the FSMC and/or to access FSMC control + * registers. + * + * @retval None + */ +void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); + + SYSCFG->MEMRMP = SYSCFG_MemoryRemap; +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for + * EXTI lines where x can be (A..I). + * @param EXTI_PinSourcex: specifies the EXTI line to be configured. + * This parameter can be EXTI_PinSourcex where x can be (0..15, except + * for EXTI_PortSourceGPIOI x can be (0..11). + * @retval None + */ +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) +{ + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); + assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); + + tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); +} + +/** + * @brief Selects the ETHERNET media interface + * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. + * This parameter can be one of the following values: + * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected + * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected + * @retval None + */ +void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) +{ + assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); + /* Configure MII_RMII selection bit */ + *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; +} + +/** + * @brief Enables or disables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @param NewState: new state of the I/O Compensation Cell. + * This parameter can be one of the following values: + * @arg ENABLE: I/O compensation cell enabled + * @arg DISABLE: I/O compensation cell power-down mode + * @retval None + */ +void SYSCFG_CompensationCellCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; +} + +/** + * @brief Checks whether the I/O Compensation Cell ready flag is set or not. + * @param None + * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) + */ +FlagStatus SYSCFG_GetCompensationCellStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c index a9f6e6b16..f16077088 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c @@ -1,3358 +1,3358 @@ -/** - ****************************************************************************** - * @file stm32f2xx_tim.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the TIM peripheral: - * - TimeBase management - * - Output Compare management - * - Input Capture management - * - Advanced-control timers (TIM1 and TIM8) specific features - * - Interrupts, DMA and flags management - * - Clocks management - * - Synchronization management - * - Specific interface management - * - Specific remapping management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * This driver provides functions to configure and program the TIM - * of all STM32F2xx devices. - * These functions are split in 9 groups: - * - * 1. TIM TimeBase management: this group includes all needed functions - * to configure the TM Timebase unit: - * - Set/Get Prescaler - * - Set/Get Autoreload - * - Counter modes configuration - * - Set Clock division - * - Select the One Pulse mode - * - Update Request Configuration - * - Update Disable Configuration - * - Auto-Preload Configuration - * - Enable/Disable the counter - * - * 2. TIM Output Compare management: this group includes all needed - * functions to configure the Capture/Compare unit used in Output - * compare mode: - * - Configure each channel, independently, in Output Compare mode - * - Select the output compare modes - * - Select the Polarities of each channel - * - Set/Get the Capture/Compare register values - * - Select the Output Compare Fast mode - * - Select the Output Compare Forced mode - * - Output Compare-Preload Configuration - * - Clear Output Compare Reference - * - Select the OCREF Clear signal - * - Enable/Disable the Capture/Compare Channels - * - * 3. TIM Input Capture management: this group includes all needed - * functions to configure the Capture/Compare unit used in - * Input Capture mode: - * - Configure each channel in input capture mode - * - Configure Channel1/2 in PWM Input mode - * - Set the Input Capture Prescaler - * - Get the Capture/Compare values - * - * 4. Advanced-control timers (TIM1 and TIM8) specific features - * - Configures the Break input, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable) - * - Enable/Disable the TIM peripheral Main Outputs - * - Select the Commutation event - * - Set/Reset the Capture Compare Preload Control bit - * - * 5. TIM interrupts, DMA and flags management - * - Enable/Disable interrupt sources - * - Get flags status - * - Clear flags/ Pending bits - * - Enable/Disable DMA requests - * - Configure DMA burst mode - * - Select CaptureCompare DMA request - * - * 6. TIM clocks management: this group includes all needed functions - * to configure the clock controller unit: - * - Select internal/External clock - * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx - * - * 7. TIM synchronization management: this group includes all needed - * functions to configure the Synchronization unit: - * - Select Input Trigger - * - Select Output Trigger - * - Select Master Slave Mode - * - ETR Configuration when used as external trigger - * - * 8. TIM specific interface management, this group includes all - * needed functions to use the specific TIM interface: - * - Encoder Interface Configuration - * - Select Hall Sensor - * - * 9. TIM specific remapping management includes the Remapping - * configuration of specific timers - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_tim.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_MASK ((uint16_t)0x00FF) -#define CCMR_OFFSET ((uint16_t)0x0018) -#define CCER_CCE_SET ((uint16_t)0x0001) -#define CCER_CCNE_SET ((uint16_t)0x0004) -#define CCMR_OC13M_MASK ((uint16_t)0xFF8F) -#define CCMR_OC24M_MASK ((uint16_t)0x8FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** @defgroup TIM_Group1 TimeBase management functions - * @brief TimeBase management functions - * -@verbatim - =============================================================================== - TimeBase management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Timing(Time base) Mode - =================================================================== - To use the Timer in Timing(Time base) mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Fill the TIM_TimeBaseInitStruct with the desired parameters. - - 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit - with the corresponding configuration - - 4. Enable the NVIC if you need to generate the update interrupt. - - 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) - - 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval None - - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if (TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if (TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else if (TIMx == TIM11) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); - } - else if (TIMx == TIM12) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); - } - else if (TIMx == TIM13) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); - } - else - { - if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM8)|| - (TIMx == TIM2) || (TIMx == TIM3)|| - (TIMx == TIM4) || (TIMx == TIM5)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM8)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediatly */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); - - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Counter Register value - */ -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Global: Source of update is the counter - * overflow/underflow or the setting of UG bit, or an update - * generation through the slave mode controller. - * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; - } -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); - - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group2 Output Compare management functions - * @brief Output Compare management functions - * -@verbatim - =============================================================================== - Output Compare management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Output Compare Mode - =================================================================== - To use the Timer in Output Compare mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Configure the TIM pins by configuring the corresponding GPIO pins - - 2. Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - - Autoreload value = 0xFFFF - - Prescaler value = 0x0000 - - Counter mode = Up counting - - Clock Division = TIM_CKD_DIV1 - - 3. Fill the TIM_OCInitStruct with the desired parameters including: - - The TIM Output Compare mode: TIM_OCMode - - TIM Output State: TIM_OutputState - - TIM Pulse value: TIM_Pulse - - TIM Output Compare Polarity : TIM_OCPolarity - - 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the - corresponding configuration - - 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - - Note2: In case of PWM mode, this function is mandatory: - TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); - - Note3: If the corresponding interrupt or DMA request are needed, the user should: - 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). - 2. Enable the corresponding interrupt (or DMA request) using the function - TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIMx Channel1 according to the specified parameters in - * the TIM_OCInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NE; - - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x00000000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. If needed, user has to enable this channel using - * TIM_CCxCmd() and TIM_CCxNCmd() functions. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_OFFSET; - - tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - tmpccer |= TIM_OCNPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_SET << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_SET << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} -/** - * @} - */ - -/** @defgroup TIM_Group3 Input Capture management functions - * @brief Input Capture management functions - * -@verbatim - =============================================================================== - Input Capture management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Input Capture Mode - =================================================================== - To use the Timer in Input Capture mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Configure the TIM pins by configuring the corresponding GPIO pins - - 2. Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - - Autoreload value = 0xFFFF - - Prescaler value = 0x0000 - - Counter mode = Up counting - - Clock Division = TIM_CKD_DIV1 - - 3. Fill the TIM_ICInitStruct with the desired parameters including: - - TIM Channel: TIM_Channel - - TIM Input Capture polarity: TIM_ICPolarity - - TIM Input Capture selection: TIM_ICSelection - - TIM Input Capture Prescaler: TIM_ICPrescaler - - TIM Input CApture filter value: TIM_ICFilter - - 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the - corresponding configuration and to measure only frequency or duty cycle of the input signal, - or, - Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the - corresponding configuration and to measure the frequency and the duty cycle of the input signal - - 5. Enable the NVIC or the DMA to read the measured frequency. - - 6. Enable the corresponding interrupt (or DMA request) to read the Captured value, - using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - - 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - 8. Use TIM_GetCapturex(TIMx); to read the captured value. - - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Configures the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval Capture Compare 2 Register value. - */ -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} -/** - * @} - */ - -/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features - * @brief Advanced-control timers (TIM1 and TIM8) specific features - * -@verbatim - =============================================================================== - Advanced-control timers (TIM1 and TIM8) specific features - =============================================================================== - - =================================================================== - TIM Driver: how to use the Break feature - =================================================================== - After configuring the Timer channel(s) in the appropriate Output Compare mode: - - 1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer - Break Polarity, dead time, Lock level, the OSSI/OSSR State and the - AOE(automatic output enable). - - 2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer - - 3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) - - 4. Once the break even occurs, the Timer's output signals are put in reset - state or in a known state (according to the configuration made in - TIM_BDTRConfig() function). - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group5 Interrupts DMA and flags management functions - * @brief Interrupts, DMA and flags management functions - * -@verbatim - =============================================================================== - Interrupts, DMA and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used - * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, - * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. - * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can - * be used: TIM_IT_Update or TIM_IT_CC1 - * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 - * - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM1_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_RCR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_BDTR - * @arg TIM_DMABase_DCR - * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group6 Clocks management functions - * @brief Clocks management functions - * -@verbatim - =============================================================================== - Clocks management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_InputTriggerSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter: specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - tmpsmcr |= TIM_TS_ETRF; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} -/** - * @} - */ - -/** @defgroup TIM_Group7 Synchronization management functions - * @brief Synchronization management functions - * -@verbatim - =============================================================================== - Synchronization management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in synchronization Mode - =================================================================== - Case of two/several Timers - ************************** - 1. Configure the Master Timers using the following functions: - - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); - - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); - 2. Configure the Slave Timers using the following functions: - - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - - Case of Timers and external trigger(ETR pin) - ******************************************** - 1. Configure the External trigger using this function: - - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - 2. Configure the Slave Timers using the following functions: - - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - -@endverbatim - * @{ - */ - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This parameter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs(TRGO) - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize - * the counter and triggers an update of the registers - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO) - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_MASK; - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @} - */ - -/** @defgroup TIM_Group8 Specific interface management functions - * @brief Specific interface management functions - * -@verbatim - =============================================================================== - Specific interface management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group9 Specific remapping management function - * @brief Specific remapping management function - * -@verbatim - =============================================================================== - Specific remapping management function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. - * @param TIM_Remap: specifies the TIM input remapping source. - * This parameter can be one of the following values: - * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) - * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output. - * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. - * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. - * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. - * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. - * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. - * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock - * (HSE divided by a programmable prescaler) - * @retval None - */ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_REMAP(TIM_Remap)); - - /* Set the Timer remapping configuration */ - TIMx->OR = TIM_Remap; -} -/** - * @} - */ - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_tim.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the TIM peripheral: + * - TimeBase management + * - Output Compare management + * - Input Capture management + * - Advanced-control timers (TIM1 and TIM8) specific features + * - Interrupts, DMA and flags management + * - Clocks management + * - Synchronization management + * - Specific interface management + * - Specific remapping management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * This driver provides functions to configure and program the TIM + * of all STM32F2xx devices. + * These functions are split in 9 groups: + * + * 1. TIM TimeBase management: this group includes all needed functions + * to configure the TM Timebase unit: + * - Set/Get Prescaler + * - Set/Get Autoreload + * - Counter modes configuration + * - Set Clock division + * - Select the One Pulse mode + * - Update Request Configuration + * - Update Disable Configuration + * - Auto-Preload Configuration + * - Enable/Disable the counter + * + * 2. TIM Output Compare management: this group includes all needed + * functions to configure the Capture/Compare unit used in Output + * compare mode: + * - Configure each channel, independently, in Output Compare mode + * - Select the output compare modes + * - Select the Polarities of each channel + * - Set/Get the Capture/Compare register values + * - Select the Output Compare Fast mode + * - Select the Output Compare Forced mode + * - Output Compare-Preload Configuration + * - Clear Output Compare Reference + * - Select the OCREF Clear signal + * - Enable/Disable the Capture/Compare Channels + * + * 3. TIM Input Capture management: this group includes all needed + * functions to configure the Capture/Compare unit used in + * Input Capture mode: + * - Configure each channel in input capture mode + * - Configure Channel1/2 in PWM Input mode + * - Set the Input Capture Prescaler + * - Get the Capture/Compare values + * + * 4. Advanced-control timers (TIM1 and TIM8) specific features + * - Configures the Break input, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable) + * - Enable/Disable the TIM peripheral Main Outputs + * - Select the Commutation event + * - Set/Reset the Capture Compare Preload Control bit + * + * 5. TIM interrupts, DMA and flags management + * - Enable/Disable interrupt sources + * - Get flags status + * - Clear flags/ Pending bits + * - Enable/Disable DMA requests + * - Configure DMA burst mode + * - Select CaptureCompare DMA request + * + * 6. TIM clocks management: this group includes all needed functions + * to configure the clock controller unit: + * - Select internal/External clock + * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx + * + * 7. TIM synchronization management: this group includes all needed + * functions to configure the Synchronization unit: + * - Select Input Trigger + * - Select Output Trigger + * - Select Master Slave Mode + * - ETR Configuration when used as external trigger + * + * 8. TIM specific interface management, this group includes all + * needed functions to use the specific TIM interface: + * - Encoder Interface Configuration + * - Select Hall Sensor + * + * 9. TIM specific remapping management includes the Remapping + * configuration of specific timers + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_tim.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_MASK ((uint16_t)0x00FF) +#define CCMR_OFFSET ((uint16_t)0x0018) +#define CCER_CCE_SET ((uint16_t)0x0001) +#define CCER_CCNE_SET ((uint16_t)0x0004) +#define CCMR_OC13M_MASK ((uint16_t)0xFF8F) +#define CCMR_OC24M_MASK ((uint16_t)0x8FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** @defgroup TIM_Group1 TimeBase management functions + * @brief TimeBase management functions + * +@verbatim + =============================================================================== + TimeBase management functions + =============================================================================== + + =================================================================== + TIM Driver: how to use it in Timing(Time base) Mode + =================================================================== + To use the Timer in Timing(Time base) mode, the following steps are mandatory: + + 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function + + 2. Fill the TIM_TimeBaseInitStruct with the desired parameters. + + 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit + with the corresponding configuration + + 4. Enable the NVIC if you need to generate the update interrupt. + + 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) + + 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + Note1: All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval None + + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if (TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if (TIMx == TIM11) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); + } + else if (TIMx == TIM12) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); + } + else if (TIMx == TIM13) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); + } + else + { + if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM8)|| + (TIMx == TIM2) || (TIMx == TIM3)|| + (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter(only for TIM1 and TIM8) value immediatly */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + + tmpcr1 = TIMx->CR1; + + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); + + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval Counter Register value + */ +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Global: Source of update is the counter + * overflow/underflow or the setting of UG bit, or an update + * generation through the slave mode controller. + * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; + } +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); + + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group2 Output Compare management functions + * @brief Output Compare management functions + * +@verbatim + =============================================================================== + Output Compare management functions + =============================================================================== + + =================================================================== + TIM Driver: how to use it in Output Compare Mode + =================================================================== + To use the Timer in Output Compare mode, the following steps are mandatory: + + 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function + + 2. Configure the TIM pins by configuring the corresponding GPIO pins + + 2. Configure the Time base unit as described in the first part of this driver, + if needed, else the Timer will run with the default configuration: + - Autoreload value = 0xFFFF + - Prescaler value = 0x0000 + - Counter mode = Up counting + - Clock Division = TIM_CKD_DIV1 + + 3. Fill the TIM_OCInitStruct with the desired parameters including: + - The TIM Output Compare mode: TIM_OCMode + - TIM Output State: TIM_OutputState + - TIM Pulse value: TIM_Pulse + - TIM Output Compare Polarity : TIM_OCPolarity + + 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the + corresponding configuration + + 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + Note1: All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + + Note2: In case of PWM mode, this function is mandatory: + TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); + + Note3: If the corresponding interrupt or DMA request are needed, the user should: + 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). + 2. Enable the corresponding interrupt (or DMA request) using the function + TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIMx Channel1 according to the specified parameters in + * the TIM_OCInitStruct. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; + tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NE; + + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; + tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NE; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; + tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NE; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; + tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x00000000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. If needed, user has to enable this channel using + * TIM_CCxCmd() and TIM_CCxNCmd() functions. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_OFFSET; + + tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; + + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; + + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; + + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; + + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)(~TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NP; + tmpccer |= TIM_OCNPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)(~TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NP; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC3P; + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NP; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC4P; + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_SET << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_SET << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} +/** + * @} + */ + +/** @defgroup TIM_Group3 Input Capture management functions + * @brief Input Capture management functions + * +@verbatim + =============================================================================== + Input Capture management functions + =============================================================================== + + =================================================================== + TIM Driver: how to use it in Input Capture Mode + =================================================================== + To use the Timer in Input Capture mode, the following steps are mandatory: + + 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function + + 2. Configure the TIM pins by configuring the corresponding GPIO pins + + 2. Configure the Time base unit as described in the first part of this driver, + if needed, else the Timer will run with the default configuration: + - Autoreload value = 0xFFFF + - Prescaler value = 0x0000 + - Counter mode = Up counting + - Clock Division = TIM_CKD_DIV1 + + 3. Fill the TIM_ICInitStruct with the desired parameters including: + - TIM Channel: TIM_Channel + - TIM Input Capture polarity: TIM_ICPolarity + - TIM Input Capture selection: TIM_ICSelection + - TIM Input Capture Prescaler: TIM_ICPrescaler + - TIM Input CApture filter value: TIM_ICFilter + + 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the + corresponding configuration and to measure only frequency or duty cycle of the input signal, + or, + Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the + corresponding configuration and to measure the frequency and the duty cycle of the input signal + + 5. Enable the NVIC or the DMA to read the measured frequency. + + 6. Enable the corresponding interrupt (or DMA request) to read the Captured value, + using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) + + 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + 8. Use TIM_GetCapturex(TIMx); to read the captured value. + + Note1: All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM peripheral according to the specified parameters + * in the TIM_ICInitStruct. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Configures the TIM peripheral according to the specified parameters + * in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @retval Capture Compare 2 Register value. + */ +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} +/** + * @} + */ + +/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features + * @brief Advanced-control timers (TIM1 and TIM8) specific features + * +@verbatim + =============================================================================== + Advanced-control timers (TIM1 and TIM8) specific features + =============================================================================== + + =================================================================== + TIM Driver: how to use the Break feature + =================================================================== + After configuring the Timer channel(s) in the appropriate Output Compare mode: + + 1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer + Break Polarity, dead time, Lock level, the OSSI/OSSR State and the + AOE(automatic output enable). + + 2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer + + 3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) + + 4. Once the break even occurs, the Timer's output signals are put in reset + state or in a known state (according to the configuration made in + TIM_BDTRConfig() function). + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group5 Interrupts DMA and flags management functions + * @brief Interrupts, DMA and flags management functions + * +@verbatim + =============================================================================== + Interrupts, DMA and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used + * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, + * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. + * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can + * be used: TIM_IT_Update or TIM_IT_CC1 + * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 + * + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * + * @note TIM6 and TIM7 can only generate an update event. + * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag + * + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. + * + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag + * + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note TIM6 and TIM7 can generate only an update interrupt. + * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. + * + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note TIM6 and TIM7 can generate only an update interrupt. + * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR1 + * @arg TIM_DMABase_CR2 + * @arg TIM_DMABase_SMCR + * @arg TIM_DMABase_DIER + * @arg TIM1_DMABase_SR + * @arg TIM_DMABase_EGR + * @arg TIM_DMABase_CCMR1 + * @arg TIM_DMABase_CCMR2 + * @arg TIM_DMABase_CCER + * @arg TIM_DMABase_CNT + * @arg TIM_DMABase_PSC + * @arg TIM_DMABase_ARR + * @arg TIM_DMABase_RCR + * @arg TIM_DMABase_CCR1 + * @arg TIM_DMABase_CCR2 + * @arg TIM_DMABase_CCR3 + * @arg TIM_DMABase_CCR4 + * @arg TIM_DMABase_BDTR + * @arg TIM_DMABase_DCR + * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value + * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group6 Clocks management functions + * @brief Clocks management functions + * +@verbatim + =============================================================================== + Clocks management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_InputTriggerSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter: specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; + + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)~TIM_SMCR_TS; + tmpsmcr |= TIM_TS_ETRF; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} +/** + * @} + */ + +/** @defgroup TIM_Group7 Synchronization management functions + * @brief Synchronization management functions + * +@verbatim + =============================================================================== + Synchronization management functions + =============================================================================== + + =================================================================== + TIM Driver: how to use it in synchronization Mode + =================================================================== + Case of two/several Timers + ************************** + 1. Configure the Master Timers using the following functions: + - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); + - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); + 2. Configure the Slave Timers using the following functions: + - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); + - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + + Case of Timers and external trigger(ETR pin) + ******************************************** + 1. Configure the External trigger using this function: + - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); + 2. Configure the Slave Timers using the following functions: + - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); + - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + +@endverbatim + * @{ + */ + +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)~TIM_SMCR_TS; + + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. + * + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This parameter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs(TRGO) + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize + * the counter and triggers an update of the registers + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; + + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO) + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_MASK; + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @} + */ + +/** @defgroup TIM_Group8 Specific interface management functions + * @brief Specific interface management functions + * +@verbatim + =============================================================================== + Specific interface management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group9 Specific remapping management function + * @brief Specific remapping management function + * +@verbatim + =============================================================================== + Specific remapping management function + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. + * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. + * @param TIM_Remap: specifies the TIM input remapping source. + * This parameter can be one of the following values: + * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) + * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output. + * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. + * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. + * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. + * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. + * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. + * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock + * (HSE divided by a programmable prescaler) + * @retval None + */ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_REMAP(TIM_Remap)); + + /* Set the Timer remapping configuration */ + TIMx->OR = TIM_Remap; +} +/** + * @} + */ + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input and set the filter */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + + /* Select the Input and set the filter */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + + /* Select the Input and set the filter */ + tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + + /* Select the Input and set the filter */ + tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c index 015fdd929..8f41b581d 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c @@ -1,1469 +1,1469 @@ -/** - ****************************************************************************** - * @file stm32f2xx_usart.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Universal synchronous asynchronous receiver - * transmitter (USART): - * - Initialization and Configuration - * - Data transfers - * - Multi-Processor Communication - * - LIN mode - * - Half-duplex mode - * - Smartcard mode - * - IrDA mode - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable peripheral clock using the follwoing functions - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5. - * - * 2. According to the USART mode, enable the GPIO clocks using - * RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, - * or/and SCLK). - * - * 3. Peripheral's alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - * flow control and Mode(Receiver/Transmitter) using the USART_Init() - * function. - * - * 5. For synchronous mode, enable the clock and program the polarity, - * phase and last bit using the USART_ClockInit() function. - * - * 5. Enable the NVIC and the corresponding interrupt using the function - * USART_ITConfig() if you need to use interrupt mode. - * - * 6. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using USART_DMACmd() function - * - * 7. Enable the USART using the USART_Cmd() function. - * - * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. - * - * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections - * for more details - * - * In order to reach higher communication baudrates, it is possible to - * enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). - * This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) - * and before calling the function USART_Init(). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_usart.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ -#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ - USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE)) - -/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ -#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ - USART_CR2_CPHA | USART_CR2_LBCL)) - -/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ -#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) - -/*!< USART Interrupts mask */ -#define IT_MASK ((uint16_t)0x001F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** @defgroup USART_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - - For the asynchronous mode only these parameters can be configured: - - Baud Rate - - Word Length - - Stop Bit - - Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - - Hardware flow control - - Receiver/transmitter modes - - The USART_Init() function follows the USART asynchronous configuration procedure - (details for the procedure are available in reference manual (RM0033)). - - - For the synchronous mode in addition to the asynchronous mode parameters these - parameters should be also configured: - - USART Clock Enabled - - USART polarity - - USART phase - - USART LastBit - - These parameters can be configured using the USART_ClockInit() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - else - { - if (USARTx == USART6) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains - * the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - RCC_ClocksTypeDef RCC_ClocksStatus; - - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - - /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ - if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - - /* Clear STOP[13:12] bits */ - tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); - - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : - Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); - - /* Configure the USART Word Length, Parity and mode: - Set the M bits according to USART_WordLength value - Set PCE and PS bits according to USART_Parity value - Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - - /* Clear CTSE and RTSE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); - - /* Configure the USART HFC : - Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate */ - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if ((USARTx == USART1) || (USARTx == USART6)) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - /* Determine the fractional part */ - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - /* Implement the fractional part in the register */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - /* Write to USART BRR register */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_UE; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); - } -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_Prescaler: specifies the prescaler clock. - * @note The function is used for IrDA mode with UART4 and UART5. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= USART_GTPR_GT; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @note This function has to be called before calling USART_Init() function - * in order to have correct baudrate Divider value. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART 8x oversampling mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_OVER8; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_ONEBIT; - } - else - { - /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART data - transfers. - - During an USART reception, data shifts in least significant bit first through - the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) - between the internal bus and the received shift register. - - When a transmission is taking place, a write instruction to the USART_DR register - stores the data in the TDR register and which is copied in the shift register - at the end of the current transmission. - - The read access of the USART_DR register can be done using the USART_ReceiveData() - function and returns the RDR buffered value. Whereas a write access to the USART_DR - can be done using USART_SendData() function and stores the written data into - TDR buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @} - */ - -/** @defgroup USART_Group3 MultiProcessor Communication functions - * @brief Multi-Processor Communication functions - * -@verbatim - =============================================================================== - Multi-Processor Communication functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - multiprocessor communication. - - For instance one of the USARTs can be the master, its TX output is connected to - the RX input of the other USART. The others are slaves, their respective TX outputs - are logically ANDed together and connected to the RX input of the master. - - USART multiprocessor communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - 2. Configures the USART address using the USART_SetAddress() function. - 3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) - using USART_WakeUpConfig() function only for the slaves. - 4. Enable the USART using the USART_Cmd() function. - 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. - - The USART Slave exit from mute mode when receive the wake up condition. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the address of the USART node. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_RWU; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); - } -} -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @} - */ - -/** @defgroup USART_Group4 LIN mode functions - * @brief LIN mode functions - * -@verbatim - =============================================================================== - LIN mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART LIN - Mode communication. - - In LIN mode, 8-bit data format with 1 stop bit is required in accordance with - the LIN standard. - - Only this LIN Feature is supported by the USART IP: - - LIN Master Synchronous Break send capability and LIN slave break detection - capability : 13-bit break generation and 10/11 bit break detection - - - USART LIN Master transmitter communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Enable the LIN mode using the USART_LINCmd() function. - 4. Send the break character using USART_SendBreak() function. - - USART LIN Master receiver communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig() - function. - 4. Enable the LIN mode using the USART_LINCmd() function. - - -@note In LIN mode, the following bits must be kept cleared: - - CLKEN in the USART_CR2 register, - - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART's LIN mode. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_LINEN; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); - } -} - -/** - * @brief Transmits break characters. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= USART_CR1_SBK; -} - -/** - * @} - */ - -/** @defgroup USART_Group5 Halfduplex mode function - * @brief Half-duplex mode function - * -@verbatim - =============================================================================== - Half-duplex mode function - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - Half-duplex communication. - - The USART can be configured to follow a single-wire half-duplex protocol where - the TX and RX lines are internally connected. - - USART Half duplex communication is possible through the following procedure: - 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - 2. Configures the USART address using the USART_SetAddress() function. - 3. Enable the USART using the USART_Cmd() function. - 4. Enable the half duplex mode using USART_HalfDuplexCmd() function. - - -@note The RX pin is no longer used -@note In Half-duplex mode the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register. - - SCEN and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's Half Duplex communication. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_HDSEL; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); - } -} - -/** - * @} - */ - - -/** @defgroup USART_Group6 Smartcard mode functions - * @brief Smartcard mode functions - * -@verbatim - =============================================================================== - Smartcard mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - Smartcard communication. - - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. - - The USART can provide a clock to the smartcard through the SCLK output. - In smartcard mode, SCLK is not associated to the communication but is simply derived - from the internal peripheral input clock through a 5-bit prescaler. - - Smartcard communication is possible through the following procedure: - 1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function. - 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function. - 3. Program the USART clock using the USART_ClockInit() function as following: - - USART Clock enabled - - USART CPOL Low - - USART CPHA on first edge - - USART Last Bit Clock Enabled - 4. Program the Smartcard interface using the USART_Init() function as following: - - Word Length = 9 Bits - - 1.5 Stop Bit - - Even parity - - BaudRate = 12096 baud - - Hardware flow control disabled (RTS and CTS signals) - - Tx and Rx enabled - 5. Optionally you can enable the parity error interrupt using the USART_ITConfig() - function - 6. Enable the USART using the USART_Cmd() function. - 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. - 8. Enable the Smartcard interface using the USART_SmartCardCmd() function. - - Please refer to the ISO 7816-3 specification for more details. - - -@note It is also possible to choose 0.5 stop bit for receiving but it is recommended - to use 1.5 stop bits for both transmitting and receiving to avoid switching - between the two configurations. -@note In smartcard mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register. - - HDSEL and IREN bits in the USART_CR3 register. -@note Smartcard mode is available on USART peripherals only (not available on UART4 - and UART5 peripherals). - -@endverbatim - * @{ - */ - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param USART_GuardTime: specifies the guard time. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= USART_GTPR_PSC; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Enables or disables the USART's Smart Card mode. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_SCEN; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_NACK; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group7 IrDA mode functions - * @brief IrDA mode functions - * -@verbatim - =============================================================================== - IrDA mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - IrDA communication. - - IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver - is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. - While receiving data, transmission should be avoided as the data to be transmitted - could be corrupted. - - IrDA communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver - modes and hardware flow control values using the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Configures the IrDA pulse width by configuring the prescaler using - the USART_SetPrescaler() function. - 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode - using the USART_IrDAConfig() function. - 5. Enable the IrDA using the USART_IrDACmd() function. - -@note A pulse of width less than two and greater than one PSC period(s) may or may - not be rejected. -@note The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and - reception (IrDA is a half duplex protocol). -@note In IrDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register. - - SCEN and HDSEL bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_IREN; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group8 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's DMA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup USART_Group9 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This subsection provides a set of functions allowing to configure the USART - Interrupts sources, DMA channels requests and check or clear the flags or - pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - Polling Mode - ============= - In Polling Mode, the SPI communication can be managed by 10 flags: - 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register - 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register - 3. USART_FLAG_TC : to indicate the status of the transmit operation - 4. USART_FLAG_IDLE : to indicate the status of the Idle Line - 5. USART_FLAG_CTS : to indicate the status of the nCTS input - 6. USART_FLAG_LBD : to indicate the status of the LIN break detection - 7. USART_FLAG_NE : to indicate if a noise error occur - 8. USART_FLAG_FE : to indicate if a frame error occur - 9. USART_FLAG_PE : to indicate if a parity error occur - 10. USART_FLAG_ORE : to indicate if an Overrun error occur - - In this Mode it is advised to use the following functions: - - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - Interrupt Mode - =============== - In Interrupt Mode, the USART communication can be managed by 8 interrupt sources - and 10 pending bits: - - Pending Bits: - ------------- - 1. USART_IT_TXE : to indicate the status of the transmit buffer register - 2. USART_IT_RXNE : to indicate the status of the receive buffer register - 3. USART_IT_TC : to indicate the status of the transmit operation - 4. USART_IT_IDLE : to indicate the status of the Idle Line - 5. USART_IT_CTS : to indicate the status of the nCTS input - 6. USART_IT_LBD : to indicate the status of the LIN break detection - 7. USART_IT_NE : to indicate if a noise error occur - 8. USART_IT_FE : to indicate if a frame error occur - 9. USART_IT_PE : to indicate if a parity error occur - 10. USART_IT_ORE : to indicate if an Overrun error occur - - Interrupt Source: - ----------------- - 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty - interrupt. - 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - 3. USART_IT_TC : specifies the interrupt source for the Transmit complete - interrupt. - 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. - 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. - 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection - interrupt. - 7. USART_IT_PE : specifies the interrupt source for the parity error interrupt. - 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt. - -@note Some parameters are coded in order to use them as interrupt source or as pending bits. - - In this Mode it is advised to use the following functions: - - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); - - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); - - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - - DMA Mode - ======== - In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: - 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request - 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - In this Mode it is advised to use the following function: - - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_MASK; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if (USART_FLAG == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * @note RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * @note TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS : CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD : LIN Break detection interrupt - * @arg USART_IT_TXE : Transmit Data Register empty interrupt - * @arg USART_IT_TC : Transmission complete interrupt - * @arg USART_IT_RXNE : Receive Data register not empty interrupt - * @arg USART_IT_IDLE : Idle line detection interrupt - * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set - * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set - * @arg USART_IT_NE : Noise Error interrupt - * @arg USART_IT_FE : Framing Error interrupt - * @arg USART_IT_PE : Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_MASK; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * @note RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * @note TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_usart.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Universal synchronous asynchronous receiver + * transmitter (USART): + * - Initialization and Configuration + * - Data transfers + * - Multi-Processor Communication + * - LIN mode + * - Half-duplex mode + * - Smartcard mode + * - IrDA mode + * - DMA transfers management + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable peripheral clock using the follwoing functions + * RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 + * RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5. + * + * 2. According to the USART mode, enable the GPIO clocks using + * RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, + * or/and SCLK). + * + * 3. Peripheral's alternate function: + * - Connect the pin to the desired peripherals' Alternate + * Function (AF) using GPIO_PinAFConfig() function + * - Configure the desired pin in alternate function by: + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * + * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + * flow control and Mode(Receiver/Transmitter) using the USART_Init() + * function. + * + * 5. For synchronous mode, enable the clock and program the polarity, + * phase and last bit using the USART_ClockInit() function. + * + * 5. Enable the NVIC and the corresponding interrupt using the function + * USART_ITConfig() if you need to use interrupt mode. + * + * 6. When using the DMA mode + * - Configure the DMA using DMA_Init() function + * - Active the needed channel Request using USART_DMACmd() function + * + * 7. Enable the USART using the USART_Cmd() function. + * + * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. + * + * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections + * for more details + * + * In order to reach higher communication baudrates, it is possible to + * enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). + * This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) + * and before calling the function USART_Init(). + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_usart.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ +#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ + USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE)) + +/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ +#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) + +/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ +#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) + +/*!< USART Interrupts mask */ +#define IT_MASK ((uint16_t)0x001F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** @defgroup USART_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + + This subsection provides a set of functions allowing to initialize the USART + in asynchronous and in synchronous modes. + - For the asynchronous mode only these parameters can be configured: + - Baud Rate + - Word Length + - Stop Bit + - Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + - Hardware flow control + - Receiver/transmitter modes + + The USART_Init() function follows the USART asynchronous configuration procedure + (details for the procedure are available in reference manual (RM0033)). + + - For the synchronous mode in addition to the asynchronous mode parameters these + parameters should be also configured: + - USART Clock Enabled + - USART polarity + - USART phase + - USART LastBit + + These parameters can be configured using the USART_ClockInit() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else if (USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + else + { + if (USARTx == USART6) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains + * the configuration information for the specified USART peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + + /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ + if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + + /* Clear STOP[13:12] bits */ + tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); + + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : + Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); + + /* Configure the USART Word Length, Parity and mode: + Set the M bits according to USART_WordLength value + Set PCE and PS bits according to USART_Parity value + Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + + /* Write to USART CR1 */ + USARTx->CR1 = (uint16_t)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + + /* Clear CTSE and RTSE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); + + /* Configure the USART HFC : + Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + + /* Write to USART CR3 */ + USARTx->CR3 = (uint16_t)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate */ + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if ((USARTx == USART1) || (USARTx == USART6)) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + /* Write to USART BRR register */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that + * contains the configuration information for the specified USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_UE; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); + } +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_Prescaler: specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= USART_GTPR_GT; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @note This function has to be called before calling USART_Init() function + * in order to have correct baudrate Divider value. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART 8x oversampling mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_OVER8; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); + } +} + +/** + * @brief Enables or disables the USART's one bit sampling method. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_ONEBIT; + } + else + { + /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + Data transfers functions + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART data + transfers. + + During an USART reception, data shifts in least significant bit first through + the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) + between the internal bus and the received shift register. + + When a transmission is taking place, a write instruction to the USART_DR register + stores the data in the TDR register and which is copied in the shift register + at the end of the current transmission. + + The read access of the USART_DR register can be done using the USART_ReceiveData() + function and returns the RDR buffered value. Whereas a write access to the USART_DR + can be done using USART_SendData() function and stores the written data into + TDR buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +} + +/** + * @} + */ + +/** @defgroup USART_Group3 MultiProcessor Communication functions + * @brief Multi-Processor Communication functions + * +@verbatim + =============================================================================== + Multi-Processor Communication functions + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART + multiprocessor communication. + + For instance one of the USARTs can be the master, its TX output is connected to + the RX input of the other USART. The others are slaves, their respective TX outputs + are logically ANDed together and connected to the RX input of the master. + + USART multiprocessor communication is possible through the following procedure: + 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter + or Mode receiver and hardware flow control values using the USART_Init() + function. + 2. Configures the USART address using the USART_SetAddress() function. + 3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) + using USART_WakeUpConfig() function only for the slaves. + 4. Enable the USART using the USART_Cmd() function. + 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. + + The USART Slave exit from mute mode when receive the wake up condition. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the address of the USART node. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_RWU; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); + } +} +/** + * @brief Selects the USART WakeUp method. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @} + */ + +/** @defgroup USART_Group4 LIN mode functions + * @brief LIN mode functions + * +@verbatim + =============================================================================== + LIN mode functions + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART LIN + Mode communication. + + In LIN mode, 8-bit data format with 1 stop bit is required in accordance with + the LIN standard. + + Only this LIN Feature is supported by the USART IP: + - LIN Master Synchronous Break send capability and LIN slave break detection + capability : 13-bit break generation and 10/11 bit break detection + + + USART LIN Master transmitter communication is possible through the following procedure: + 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + 2. Enable the USART using the USART_Cmd() function. + 3. Enable the LIN mode using the USART_LINCmd() function. + 4. Send the break character using USART_SendBreak() function. + + USART LIN Master receiver communication is possible through the following procedure: + 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + 2. Enable the USART using the USART_Cmd() function. + 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig() + function. + 4. Enable the LIN mode using the USART_LINCmd() function. + + +@note In LIN mode, the following bits must be kept cleared: + - CLKEN in the USART_CR2 register, + - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART's LIN mode. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= USART_CR2_LINEN; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); + } +} + +/** + * @brief Transmits break characters. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @retval None + */ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= USART_CR1_SBK; +} + +/** + * @} + */ + +/** @defgroup USART_Group5 Halfduplex mode function + * @brief Half-duplex mode function + * +@verbatim + =============================================================================== + Half-duplex mode function + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART + Half-duplex communication. + + The USART can be configured to follow a single-wire half-duplex protocol where + the TX and RX lines are internally connected. + + USART Half duplex communication is possible through the following procedure: + 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter + or Mode receiver and hardware flow control values using the USART_Init() + function. + 2. Configures the USART address using the USART_SetAddress() function. + 3. Enable the USART using the USART_Cmd() function. + 4. Enable the half duplex mode using USART_HalfDuplexCmd() function. + + +@note The RX pin is no longer used +@note In Half-duplex mode the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register. + - SCEN and IREN bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's Half Duplex communication. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_HDSEL; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); + } +} + +/** + * @} + */ + + +/** @defgroup USART_Group6 Smartcard mode functions + * @brief Smartcard mode functions + * +@verbatim + =============================================================================== + Smartcard mode functions + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART + Smartcard communication. + + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. + + The USART can provide a clock to the smartcard through the SCLK output. + In smartcard mode, SCLK is not associated to the communication but is simply derived + from the internal peripheral input clock through a 5-bit prescaler. + + Smartcard communication is possible through the following procedure: + 1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function. + 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function. + 3. Program the USART clock using the USART_ClockInit() function as following: + - USART Clock enabled + - USART CPOL Low + - USART CPHA on first edge + - USART Last Bit Clock Enabled + 4. Program the Smartcard interface using the USART_Init() function as following: + - Word Length = 9 Bits + - 1.5 Stop Bit + - Even parity + - BaudRate = 12096 baud + - Hardware flow control disabled (RTS and CTS signals) + - Tx and Rx enabled + 5. Optionally you can enable the parity error interrupt using the USART_ITConfig() + function + 6. Enable the USART using the USART_Cmd() function. + 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. + 8. Enable the Smartcard interface using the USART_SmartCardCmd() function. + + Please refer to the ISO 7816-3 specification for more details. + + +@note It is also possible to choose 0.5 stop bit for receiving but it is recommended + to use 1.5 stop bits for both transmitting and receiving to avoid switching + between the two configurations. +@note In smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register. + - HDSEL and IREN bits in the USART_CR3 register. +@note Smartcard mode is available on USART peripherals only (not available on UART4 + and UART5 peripherals). + +@endverbatim + * @{ + */ + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= USART_GTPR_PSC; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Enables or disables the USART's Smart Card mode. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_SCEN; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_NACK; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group7 IrDA mode functions + * @brief IrDA mode functions + * +@verbatim + =============================================================================== + IrDA mode functions + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART + IrDA communication. + + IrDA is a half duplex communication protocol. If the Transmitter is busy, any data + on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver + is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. + While receiving data, transmission should be avoided as the data to be transmitted + could be corrupted. + + IrDA communication is possible through the following procedure: + 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver + modes and hardware flow control values using the USART_Init() function. + 2. Enable the USART using the USART_Cmd() function. + 3. Configures the IrDA pulse width by configuring the prescaler using + the USART_SetPrescaler() function. + 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode + using the USART_IrDAConfig() function. + 5. Enable the IrDA using the USART_IrDACmd() function. + +@note A pulse of width less than two and greater than one PSC period(s) may or may + not be rejected. +@note The receiver set up time should be managed by software. The IrDA physical layer + specification specifies a minimum of 10 ms delay between transmission and + reception (IrDA is a half duplex protocol). +@note In IrDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register. + - SCEN and HDSEL bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_IREN; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group8 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + DMA transfers management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's DMA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @} + */ + +/** @defgroup USART_Group9 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This subsection provides a set of functions allowing to configure the USART + Interrupts sources, DMA channels requests and check or clear the flags or + pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + Polling Mode + ============= + In Polling Mode, the SPI communication can be managed by 10 flags: + 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register + 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register + 3. USART_FLAG_TC : to indicate the status of the transmit operation + 4. USART_FLAG_IDLE : to indicate the status of the Idle Line + 5. USART_FLAG_CTS : to indicate the status of the nCTS input + 6. USART_FLAG_LBD : to indicate the status of the LIN break detection + 7. USART_FLAG_NE : to indicate if a noise error occur + 8. USART_FLAG_FE : to indicate if a frame error occur + 9. USART_FLAG_PE : to indicate if a parity error occur + 10. USART_FLAG_ORE : to indicate if an Overrun error occur + + In this Mode it is advised to use the following functions: + - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); + - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); + + Interrupt Mode + =============== + In Interrupt Mode, the USART communication can be managed by 8 interrupt sources + and 10 pending bits: + + Pending Bits: + ------------- + 1. USART_IT_TXE : to indicate the status of the transmit buffer register + 2. USART_IT_RXNE : to indicate the status of the receive buffer register + 3. USART_IT_TC : to indicate the status of the transmit operation + 4. USART_IT_IDLE : to indicate the status of the Idle Line + 5. USART_IT_CTS : to indicate the status of the nCTS input + 6. USART_IT_LBD : to indicate the status of the LIN break detection + 7. USART_IT_NE : to indicate if a noise error occur + 8. USART_IT_FE : to indicate if a frame error occur + 9. USART_IT_PE : to indicate if a parity error occur + 10. USART_IT_ORE : to indicate if an Overrun error occur + + Interrupt Source: + ----------------- + 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty + interrupt. + 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + 3. USART_IT_TC : specifies the interrupt source for the Transmit complete + interrupt. + 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. + 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. + 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection + interrupt. + 7. USART_IT_PE : specifies the interrupt source for the parity error interrupt. + 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt. + +@note Some parameters are coded in order to use them as interrupt source or as pending bits. + + In this Mode it is advised to use the following functions: + - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); + - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); + - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + + DMA Mode + ======== + In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: + 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request + 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request + + In this Mode it is advised to use the following function: + - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_MASK; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + + /* The CTS flag is not available for UART4 and UART5 */ + if (USART_FLAG == USART_FLAG_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * @note RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * @note TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + * + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + + /* The CTS flag is not available for UART4 and UART5 */ + if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + USARTx->SR = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS : CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD : LIN Break detection interrupt + * @arg USART_IT_TXE : Transmit Data Register empty interrupt + * @arg USART_IT_TC : Transmission complete interrupt + * @arg USART_IT_RXNE : Receive Data register not empty interrupt + * @arg USART_IT_IDLE : Idle line detection interrupt + * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set + * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set + * @arg USART_IT_NE : Noise Error interrupt + * @arg USART_IT_FE : Framing Error interrupt + * @arg USART_IT_PE : Parity Error interrupt + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_IT & IT_MASK; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->SR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetITStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * @note RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * @note TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * @note TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + * + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->SR = (uint16_t)~itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c index c893fb383..4d715dcba 100644 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c +++ b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c @@ -1,309 +1,309 @@ -/** - ****************************************************************************** - * @file stm32f2xx_wwdg.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Window watchdog (WWDG) peripheral: - * - Prescaler, Refresh window and Counter configuration - * - WWDG activation - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * WWDG features - * =================================================================== - * - * Once enabled the WWDG generates a system reset on expiry of a programmed - * time period, unless the program refreshes the counter (downcounter) - * before to reach 0x3F value (i.e. a reset is generated when the counter - * value rolls over from 0x40 to 0x3F). - * An MCU reset is also generated if the counter value is refreshed - * before the counter has reached the refresh window value. This - * implies that the counter must be refreshed in a limited window. - * - * Once enabled the WWDG cannot be disabled except by a system reset. - * - * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - * reset occurs. - * - * The WWDG counter input clock is derived from the APB clock divided - * by a programmable prescaler. - * - * WWDG counter clock = PCLK1 / Prescaler - * WWDG timeout = (WWDG counter clock) * (counter value) - * - * Min-max timeout value @30 MHz(PCLK1): ~136.5 us / ~69.9 ms - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function - * - * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function - * - * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function - * - * 4. Set the WWDG counter value and start it using WWDG_Enable() function. - * When the WWDG is enabled the counter value should be configured to - * a value greater than 0x40 to prevent generating an immediate reset. - * - * 5. Optionally you can enable the Early wakeup interrupt which is - * generated when the counter reach 0x40. - * Once enabled this interrupt cannot be disabled except by a system reset. - * - * 6. Then the application program must refresh the WWDG counter at regular - * intervals during normal operation to prevent an MCU reset, using - * WWDG_SetCounter() function. This operation must occur only when - * the counter value is lower than the refresh window value, - * programmed using WWDG_SetWindowValue(). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_wwdg.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ----------- WWDG registers bit address in the alias region ----------- */ -#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) -/* Alias word address of EWI bit */ -#define CFR_OFFSET (WWDG_OFFSET + 0x04) -#define EWI_BitNumber 0x09 -#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) - -/* --------------------- WWDG registers bit mask ------------------------ */ -/* CFR register bit mask */ -#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) -#define CFR_W_MASK ((uint32_t)0xFFFFFF80) -#define BIT_MASK ((uint8_t)0x7F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions - * @brief Prescaler, Refresh window and Counter configuration functions - * -@verbatim - =============================================================================== - Prescaler, Refresh window and Counter configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_MASK; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_MASK; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_MASK; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_MASK; -} -/** - * @} - */ - -/** @defgroup WWDG_Group2 WWDG activation functions - * @brief WWDG activation functions - * -@verbatim - =============================================================================== - WWDG activation function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = WWDG_CR_WDGA | Counter; -} -/** - * @} - */ - -/** @defgroup WWDG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((WWDG->SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f2xx_wwdg.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Window watchdog (WWDG) peripheral: + * - Prescaler, Refresh window and Counter configuration + * - WWDG activation + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * WWDG features + * =================================================================== + * + * Once enabled the WWDG generates a system reset on expiry of a programmed + * time period, unless the program refreshes the counter (downcounter) + * before to reach 0x3F value (i.e. a reset is generated when the counter + * value rolls over from 0x40 to 0x3F). + * An MCU reset is also generated if the counter value is refreshed + * before the counter has reached the refresh window value. This + * implies that the counter must be refreshed in a limited window. + * + * Once enabled the WWDG cannot be disabled except by a system reset. + * + * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG + * reset occurs. + * + * The WWDG counter input clock is derived from the APB clock divided + * by a programmable prescaler. + * + * WWDG counter clock = PCLK1 / Prescaler + * WWDG timeout = (WWDG counter clock) * (counter value) + * + * Min-max timeout value @30 MHz(PCLK1): ~136.5 us / ~69.9 ms + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function + * + * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function + * + * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function + * + * 4. Set the WWDG counter value and start it using WWDG_Enable() function. + * When the WWDG is enabled the counter value should be configured to + * a value greater than 0x40 to prevent generating an immediate reset. + * + * 5. Optionally you can enable the Early wakeup interrupt which is + * generated when the counter reach 0x40. + * Once enabled this interrupt cannot be disabled except by a system reset. + * + * 6. Then the application program must refresh the WWDG counter at regular + * intervals during normal operation to prevent an MCU reset, using + * WWDG_SetCounter() function. This operation must occur only when + * the counter value is lower than the refresh window value, + * programmed using WWDG_SetWindowValue(). + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_wwdg.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ +/* CFR register bit mask */ +#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) +#define CFR_W_MASK ((uint32_t)0xFFFFFF80) +#define BIT_MASK ((uint8_t)0x7F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions + * @brief Prescaler, Refresh window and Counter configuration functions + * +@verbatim + =============================================================================== + Prescaler, Refresh window and Counter configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_MASK; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_MASK; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_MASK; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @note Once enabled this interrupt cannot be disabled except by a system reset. + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent generating + * an immediate reset) + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_MASK; +} +/** + * @} + */ + +/** @defgroup WWDG_Group2 WWDG activation functions + * @brief WWDG activation functions + * +@verbatim + =============================================================================== + WWDG activation function + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent generating + * an immediate reset) + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = WWDG_CR_WDGA | Counter; +} +/** + * @} + */ + +/** @defgroup WWDG_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((WWDG->SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h index 270149af6..89c096493 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h @@ -1,9179 +1,9179 @@ -/** - ****************************************************************************** - * @file stm32f4xx.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F4xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral�s drivers in application code(i.e. - * code will be based on direct access to peripheral�s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral�s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx - * @{ - */ - -#ifndef __STM32F4xx_H -#define __STM32F4xx_H - -#define assert_param(xx) - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE) - /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, - STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, - STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ - - /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, - STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */ - - /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, - STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, - STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, - STM32F439IG and STM32F439II Devices */ - - /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC - STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */ - - /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ -#endif - -/* Old STM32F40XX definition, maintained for legacy purpose */ -#ifdef STM32F40XX - #define STM32F40_41xxx -#endif /* STM32F40XX */ - -/* Old STM32F427X definition, maintained for legacy purpose */ -#ifdef STM32F427X - #define STM32F427_437xx -#endif /* STM32F427X */ - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE) - #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER */ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief STM32F4XX Standard Peripherals Library version number V1.4.0 - */ -#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F4XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ - -/** - * @brief STM32F4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - -#if defined (STM32F40_41xxx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81 /*!< FPU global interrupt */ -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ -#endif /* STM32F427_437xx */ - -#if defined (STM32F429_439xx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - LTDC_IRQn = 88, /*!< LTDC global Interrupt */ - LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ - DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ -#endif /* STM32F429_439xx */ - -#if defined (STM32F401xx) || defined (STM32F411xE) - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ -#if defined (STM32F401xx) - SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ -#endif /* STM32F411xE */ -#if defined (STM32F411xE) - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85 /*!< SPI5 global Interrupt */ -#endif /* STM32F411xE */ -#endif /* STM32F401xx || STM32F411xE */ - -} IRQn_Type; - -/** - * @} - */ - -#include "../../../../Include/core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32f4xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief DMA2D Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ - __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ - __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ - __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ - __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ - __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ - __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ - __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ - __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ - __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ - __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ - __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ - __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ - __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ - __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ - __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ - __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ - __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ - __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ - __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ - uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ - __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ - __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ -} DMA2D_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ - __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ -} FLASH_TypeDef; - -#if defined (STM32F40_41xxx) -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -/** - * @brief Flexible Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; - -/** - * @brief Flexible Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FMC_Bank1E_TypeDef; - -/** - * @brief Flexible Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FMC_Bank2_TypeDef; - -/** - * @brief Flexible Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FMC_Bank3_TypeDef; - -/** - * @brief Flexible Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FMC_Bank4_TypeDef; - -/** - * @brief Flexible Memory Controller Bank5_6 - */ - -typedef struct -{ - __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ - __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ - __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ - __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ - __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ -} FMC_Bank5_6_TypeDef; -#endif /* STM32F427_437xx || STM32F429_439xx */ - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ - uint16_t RESERVED9; /*!< Reserved, 0x26 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief LCD-TFT Display Controller - */ - -typedef struct -{ - uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ - __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ - __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ - __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ - __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ - __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ - __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ - uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ - __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ - uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ - __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ - __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ - __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ - __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ - __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ - __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ -} LTDC_TypeDef; - -/** - * @brief LCD-TFT Display layer x Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ - __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ - __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ - __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ - __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ - __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ - __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ - __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ - uint32_t RESERVED0[2]; /*!< Reserved */ - __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ - __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ - __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ - uint32_t RESERVED1[3]; /*!< Reserved */ - __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ - -} LTDC_Layer_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ - __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ - __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - - -/** - * @brief Serial Audio Interface - */ - -typedef struct -{ - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED11; /*!< Reserved, 0x46 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - uint16_t RESERVED14; /*!< Reserved, 0x52 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Crypto Processor - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ - __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ - __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ - __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ - __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ - __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ - __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ - __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ - __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ - __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ - __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ - __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ - __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ - __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ - __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ - __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ - __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ - __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ - __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ - __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ - __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ - __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ - __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ - __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ - __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ - __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ - __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ - __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ - __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ - __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ - __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ - __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ - __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ - __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ -} CRYP_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ -} HASH_TypeDef; - -/** - * @brief HASH_DIGEST - */ - -typedef struct -{ - __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ -} HASH_DIGEST_TypeDef; - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ -#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ -#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ -#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ -#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ - -#if defined (STM32F40_41xxx) -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define UART7_BASE (APB1PERIPH_BASE + 0x7800) -#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) -#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) -#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) -#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) -#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) -#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) -#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) -#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) -#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) -#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -#if defined (STM32F40_41xxx) -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -/*!< FMC Bankx registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) -#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) -#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) -#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define UART7 ((USART_TypeDef *) UART7_BASE) -#define UART8 ((USART_TypeDef *) UART8_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SPI4 ((SPI_TypeDef *) SPI4_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SPI5 ((SPI_TypeDef *) SPI5_BASE) -#define SPI6 ((SPI_TypeDef *) SPI6_BASE) -#define SAI1 ((SAI_TypeDef *) SAI1_BASE) -#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) -#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) -#define LTDC ((LTDC_TypeDef *)LTDC_BASE) -#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) -#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) -#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) -#if !defined WIN32 && defined __GNUC__ -#define CRC ((CRC_TypeDef *) CRC_BASE) -#endif -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define CRYP ((CRYP_TypeDef *) CRYP_BASE) -#define HASH ((HASH_TypeDef *) HASH_BASE) -#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) - -#if defined (STM32F40_41xxx) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) -#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) -#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) -#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) -#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) -#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!
© COPYRIGHT 2014 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#define assert_param(xx) + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE) + /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, + STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, + STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + + /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, + STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */ + + /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, + STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, + STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, + STM32F439IG and STM32F439II Devices */ + + /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC + STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */ + + /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ +#endif + +/* Old STM32F40XX definition, maintained for legacy purpose */ +#ifdef STM32F40XX + #define STM32F40_41xxx +#endif /* STM32F40XX */ + +/* Old STM32F427X definition, maintained for legacy purpose */ +#ifdef STM32F427X + #define STM32F427_437xx +#endif /* STM32F427X */ + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE) + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER */ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief STM32F4XX Standard Peripherals Library version number V1.4.0 + */ +#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F4XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + +#if defined (STM32F40_41xxx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ +#endif /* STM32F427_437xx */ + +#if defined (STM32F429_439xx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ +#endif /* STM32F429_439xx */ + +#if defined (STM32F401xx) || defined (STM32F411xE) + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ +#if defined (STM32F401xx) + SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ +#endif /* STM32F411xE */ +#if defined (STM32F411xE) + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85 /*!< SPI5 global Interrupt */ +#endif /* STM32F411xE */ +#endif /* STM32F401xx || STM32F411xE */ + +} IRQn_Type; + +/** + * @} + */ + +#include "../../../../Include/core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +#if defined (STM32F40_41xxx) +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FMC_Bank4_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; +#endif /* STM32F427_437xx || STM32F429_439xx */ + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ + uint16_t RESERVED9; /*!< Reserved, 0x26 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + uint16_t RESERVED11; /*!< Reserved, 0x46 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED12; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED13; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED14; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ + +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ + +#if defined (STM32F40_41xxx) +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +#if defined (STM32F40_41xxx) +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) +#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) +#endif /* STM32F427_437xx || STM32F429_439xx */ + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) +#if !defined WIN32 && defined __GNUC__ +#define CRC ((CRC_TypeDef *) CRC_BASE) +#endif +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#if defined (STM32F40_41xxx) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!
© COPYRIGHT 2014 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F4XX_H -#define __SYSTEM_STM32F4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F4xx_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f40_41xxx.s b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f40_41xxx.s index 4fb8604f7..25fd9cf8c 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f40_41xxx.s +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f40_41xxx.s @@ -1,527 +1,527 @@ -/** - ****************************************************************************** - * @file startup_stm32f40_41xxx.s - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief STM32F40xxx/41xxx Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM324xG-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/*Paint Main Stack */ - ldr r2, = _main_stack_start -PaintMainStack: - movs r3, #0x55555555 - str r3, [r2], #4 -LoopPaintMainStack: - ldr r3, = _estack - cmp r2, r3 - bcc PaintMainStack - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call C++ constructors for static objects */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word CRYP_IRQHandler /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CRYP_IRQHandler - .thumb_set CRYP_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file startup_stm32f40_41xxx.s + * @author MCD Application Team + * @version V1.3.0 + * @date 08-November-2013 + * @brief STM32F40xxx/41xxx Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM324xG-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2013 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/*Paint Main Stack */ + ldr r2, = _main_stack_start +PaintMainStack: + movs r3, #0x55555555 + str r3, [r2], #4 +LoopPaintMainStack: + ldr r3, = _estack + cmp r2, r3 + bcc PaintMainStack + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call C++ constructors for static objects */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_common_tables.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_common_tables.h index 9c37ab4e5..7a59b5923 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_common_tables.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_common_tables.h @@ -1,93 +1,93 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2013 ARM Limited. All rights reserved. -* -* $Date: 17. January 2013 -* $Revision: V1.4.1 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const q31_t realCoefAQ31[1024]; -extern const q31_t realCoefBQ31[1024]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoefQ31[6144]; -extern const q15_t twiddleCoefQ15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -#endif /* ARM_COMMON_TABLES_H */ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_const_structs.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_const_structs.h index 406f737dc..8d7fac0f0 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_const_structs.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_const_structs.h @@ -1,85 +1,85 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2013 ARM Limited. All rights reserved. -* -* $Date: 17. January 2013 -* $Revision: V1.4.1 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { - 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { - 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { - 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { - 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { - 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { - 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { - 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { - 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { - 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH - }; - -#endif +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { + 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { + 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { + 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { + 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { + 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { + 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { + 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { + 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { + 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH + }; + +#endif diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_math.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_math.h index 59662ae1a..65304c127 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_math.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_math.h @@ -1,7306 +1,7306 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2013 ARM Limited. All rights reserved. -* -* $Date: 17. January 2013 -* $Revision: V1.4.1 -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * - * The library has been developed and tested with MDK-ARM version 4.60. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * - * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM0b_math.uvproj - * - arm_cortexM0l_math.uvproj - * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj - * - arm_cortexM4b_math.uvproj - * - arm_cortexM4l_math.uvproj - * - arm_cortexM4bf_math.uvproj - * - arm_cortexM4lf_math.uvproj - * - * - * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - * Copyright Notice - * - * Copyright (C) 2010-2013 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) -#include "core_cm4.h" -#elif defined (ARM_MATH_CM3) -#include "core_cm3.h" -#elif defined (ARM_MATH_CM0) -#include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" -#define ARM_MATH_CM0_FAMILY -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __ICCARM__ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t __packed -#elif defined __GNUC__ -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#else -#error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) - -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) - -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ( - q31_t data); - - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((short) x * (short) (y >> 16)) - - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((short) x * (short) (y >> 16)) + - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) y)) + - ((short) x * (short) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } - - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); - -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in > 0) - { - -// #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - -#if defined ( __CC_ARM ) //Keil -//SMMLAR - #define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMLSR - #define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMULR - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -//Enter low optimization region - place directly above function definition - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) //IAR - //SMMLA - #define multAcc_32x32_keep32_R(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - - //SMMLS - #define multSub_32x32_keep32_R(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - -//Enter low optimization region - place directly above function definition - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - //SMMLA - #define multAcc_32x32_keep32_R(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - - //SMMLS - #define multSub_32x32_keep32_R(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - - #define LOW_OPTIMIZATION_EXIT - - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * Copyright Notice + * + * Copyright (C) 2010-2013 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" +#define ARM_MATH_CM0_FAMILY +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +#if defined ( __CC_ARM ) //Keil +//SMMLAR + #define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR + #define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0.h index 1b6b54ef4..ab31de0ee 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0.h @@ -1,682 +1,682 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0plus.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0plus.h index d1c392314..5cea74e9a 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0plus.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0plus.h @@ -1,793 +1,793 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm3.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm3.h index 0e215fc05..122c9aa4a 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm3.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm3.h @@ -1,1627 +1,1627 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4.h index a05f6ff89..6a29982b6 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4.h @@ -1,1777 +1,1777 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#else - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - #define __DSB() -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cm4_simd.h" /* Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#else + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + #define __DSB() +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cm4_simd.h" /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4_simd.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4_simd.h index af1831ee1..83db95b5f 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4_simd.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4_simd.h @@ -1,673 +1,673 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmFunc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmFunc.h index 139bc3c5e..0a18fafc3 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmFunc.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmFunc.h @@ -1,636 +1,636 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmInstr.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmInstr.h index 8946c2c49..d213f0eed 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmInstr.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmInstr.h @@ -1,688 +1,688 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc000.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc000.h index 1da223c55..1a2a0f2e3 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc000.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc000.h @@ -1,813 +1,813 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (0) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000 - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1]; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154]; - __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/* SCB Security Features Register Definitions */ -#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ -#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ - -#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ -#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2]; - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (0) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000 + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/* SCB Security Features Register Definitions */ +#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ +#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ + +#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ +#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc300.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc300.h index 23d4a0b1c..cc34d6fc0 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc300.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc300.h @@ -1,1598 +1,1598 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000 - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000 + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h index 5821a8bf7..bb61b4010 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h @@ -1,178 +1,178 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be an enumerator of @ref IRQn_Type - enumeration (For the complete STM32 Devices IRQ Channels - list, please refer to stm32f4xx.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup MISC_Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup MISC_System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup MISC_Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup MISC_SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be an enumerator of @ref IRQn_Type + enumeration (For the complete STM32 Devices IRQ Channels + list, please refer to stm32f4xx.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup MISC_Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup MISC_System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup MISC_Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup MISC_SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h index 5941c3f24..2ac904d21 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h @@ -1,656 +1,656 @@ -/** - ****************************************************************************** - * @file stm32f4xx_adc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_ADC_H -#define __STM32F4xx_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief ADC Init structure definition - */ -typedef struct -{ - uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. - This parameter can be a value of @ref ADC_resolution */ - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion - is performed in Scan (multichannels) - or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion - is performed in Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and - enable the trigger of a regular group. - This parameter can be a value of - @ref ADC_external_trigger_edge_for_regular_channels_conversion */ - uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger - the start of conversion of a regular group. - This parameter can be a value of - @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment - is left or right. This parameter can be - a value of @ref ADC_data_align */ - uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions - that will be done using the sequencer for - regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; - -/** - * @brief ADC Common Init structure definition - */ -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in - independent or multi mode. - This parameter can be a value of @ref ADC_Common_mode */ - uint32_t ADC_Prescaler; /*!< Select the frequency of the clock - to the ADC. The clock is common for all the ADCs. - This parameter can be a value of @ref ADC_Prescaler */ - uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access - mode for multi ADC mode. - This parameter can be a value of - @ref ADC_Direct_memory_access_mode_for_multi_mode */ - uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value of - @ref ADC_delay_between_2_sampling_phases */ - -}ADC_CommonInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants - * @{ - */ -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_Common_mode - * @{ - */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) -#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) -#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) -#define ADC_DualMode_RegSimult ((uint32_t)0x00000006) -#define ADC_DualMode_Interl ((uint32_t)0x00000007) -#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) -#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) -#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) -#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) -#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) -#define ADC_TripleMode_Interl ((uint32_t)0x00000017) -#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_DualMode_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult) || \ - ((MODE) == ADC_DualMode_Interl) || \ - ((MODE) == ADC_DualMode_AlterTrig) || \ - ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_TripleMode_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult) || \ - ((MODE) == ADC_TripleMode_Interl) || \ - ((MODE) == ADC_TripleMode_AlterTrig)) -/** - * @} - */ - - -/** @defgroup ADC_Prescaler - * @{ - */ -#define ADC_Prescaler_Div2 ((uint32_t)0x00000000) -#define ADC_Prescaler_Div4 ((uint32_t)0x00010000) -#define ADC_Prescaler_Div6 ((uint32_t)0x00020000) -#define ADC_Prescaler_Div8 ((uint32_t)0x00030000) -#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ - ((PRESCALER) == ADC_Prescaler_Div4) || \ - ((PRESCALER) == ADC_Prescaler_Div6) || \ - ((PRESCALER) == ADC_Prescaler_Div8)) -/** - * @} - */ - - -/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode - * @{ - */ -#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ -#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ -#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ -#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ -#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ - ((MODE) == ADC_DMAAccessMode_1) || \ - ((MODE) == ADC_DMAAccessMode_2) || \ - ((MODE) == ADC_DMAAccessMode_3)) - -/** - * @} - */ - - -/** @defgroup ADC_delay_between_2_sampling_phases - * @{ - */ -#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) -#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) -#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) -#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) -#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) -#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) -#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) -#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) -#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) -#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) -#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) -#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) -#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) -#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) -#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) -#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) -#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) - -/** - * @} - */ - - -/** @defgroup ADC_resolution - * @{ - */ -#define ADC_Resolution_12b ((uint32_t)0x00000000) -#define ADC_Resolution_10b ((uint32_t)0x01000000) -#define ADC_Resolution_8b ((uint32_t)0x02000000) -#define ADC_Resolution_6b ((uint32_t)0x03000000) -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ - ((RESOLUTION) == ADC_Resolution_10b) || \ - ((RESOLUTION) == ADC_Resolution_8b) || \ - ((RESOLUTION) == ADC_Resolution_6b)) - -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) -#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) -#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) -#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) -#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) -#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) -#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) -#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) -/** - * @} - */ - - -/** @defgroup ADC_data_align - * @{ - */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - - -/** @defgroup ADC_channels - * @{ - */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) -#define ADC_Channel_18 ((uint8_t)0x12) - -#if defined (STM32F40_41xxx) -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE) -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18) -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ - -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) -#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ - ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || \ - ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || \ - ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || \ - ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || \ - ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || \ - ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || \ - ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || \ - ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || \ - ((CHANNEL) == ADC_Channel_17) || \ - ((CHANNEL) == ADC_Channel_18)) -/** - * @} - */ - - -/** @defgroup ADC_sampling_times - * @{ - */ -#define ADC_SampleTime_3Cycles ((uint8_t)0x00) -#define ADC_SampleTime_15Cycles ((uint8_t)0x01) -#define ADC_SampleTime_28Cycles ((uint8_t)0x02) -#define ADC_SampleTime_56Cycles ((uint8_t)0x03) -#define ADC_SampleTime_84Cycles ((uint8_t)0x04) -#define ADC_SampleTime_112Cycles ((uint8_t)0x05) -#define ADC_SampleTime_144Cycles ((uint8_t)0x06) -#define ADC_SampleTime_480Cycles ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ - ((TIME) == ADC_SampleTime_15Cycles) || \ - ((TIME) == ADC_SampleTime_28Cycles) || \ - ((TIME) == ADC_SampleTime_56Cycles) || \ - ((TIME) == ADC_SampleTime_84Cycles) || \ - ((TIME) == ADC_SampleTime_112Cycles) || \ - ((TIME) == ADC_SampleTime_144Cycles) || \ - ((TIME) == ADC_SampleTime_480Cycles)) -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) -#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) -#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) -#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) - -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) -#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) -#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) -#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) -#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) -#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) -/** - * @} - */ - - -/** @defgroup ADC_injected_channel_selection - * @{ - */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - - -/** @defgroup ADC_interrupts_definition - * @{ - */ -#define ADC_IT_EOC ((uint16_t)0x0205) -#define ADC_IT_AWD ((uint16_t)0x0106) -#define ADC_IT_JEOC ((uint16_t)0x0407) -#define ADC_IT_OVR ((uint16_t)0x201A) -#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_flags_definition - * @{ - */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define ADC_FLAG_OVR ((uint8_t)0x20) - -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ - ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || \ - ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT) || \ - ((FLAG)== ADC_FLAG_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_thresholds - * @{ - */ -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_offset - * @{ - */ -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_length - * @{ - */ -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_injected_rank - * @{ - */ -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_rank - * @{ - */ -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the ADC configuration to the default reset state *****/ -void ADC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Analog Watchdog configuration functions ************************************/ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); - -/* Temperature Sensor, Vrefint and VBAT management functions ******************/ -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -void ADC_VBATCmd(FunctionalState NewState); - -/* Regular Channels Configuration functions ***********************************/ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetMultiModeConversionValue(void); - -/* Regular Channels DMA Configuration functions *******************************/ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); - -/* Injected channels Configuration functions **********************************/ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); - -/* Interrupts and flags management functions **********************************/ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_adc.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the ADC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_ADC_H +#define __STM32F4xx_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief ADC Init structure definition + */ +typedef struct +{ + uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. + This parameter can be a value of @ref ADC_resolution */ + FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion + is performed in Scan (multichannels) + or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion + is performed in Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and + enable the trigger of a regular group. + This parameter can be a value of + @ref ADC_external_trigger_edge_for_regular_channels_conversion */ + uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger + the start of conversion of a regular group. + This parameter can be a value of + @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment + is left or right. This parameter can be + a value of @ref ADC_data_align */ + uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions + that will be done using the sequencer for + regular channel group. + This parameter must range from 1 to 16. */ +}ADC_InitTypeDef; + +/** + * @brief ADC Common Init structure definition + */ +typedef struct +{ + uint32_t ADC_Mode; /*!< Configures the ADC to operate in + independent or multi mode. + This parameter can be a value of @ref ADC_Common_mode */ + uint32_t ADC_Prescaler; /*!< Select the frequency of the clock + to the ADC. The clock is common for all the ADCs. + This parameter can be a value of @ref ADC_Prescaler */ + uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access + mode for multi ADC mode. + This parameter can be a value of + @ref ADC_Direct_memory_access_mode_for_multi_mode */ + uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. + This parameter can be a value of + @ref ADC_delay_between_2_sampling_phases */ + +}ADC_CommonInitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants + * @{ + */ +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) + +/** @defgroup ADC_Common_mode + * @{ + */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) +#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) +#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) +#define ADC_DualMode_RegSimult ((uint32_t)0x00000006) +#define ADC_DualMode_Interl ((uint32_t)0x00000007) +#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) +#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) +#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) +#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) +#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) +#define ADC_TripleMode_Interl ((uint32_t)0x00000017) +#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ + ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_DualMode_InjecSimult) || \ + ((MODE) == ADC_DualMode_RegSimult) || \ + ((MODE) == ADC_DualMode_Interl) || \ + ((MODE) == ADC_DualMode_AlterTrig) || \ + ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ + ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_TripleMode_InjecSimult) || \ + ((MODE) == ADC_TripleMode_RegSimult) || \ + ((MODE) == ADC_TripleMode_Interl) || \ + ((MODE) == ADC_TripleMode_AlterTrig)) +/** + * @} + */ + + +/** @defgroup ADC_Prescaler + * @{ + */ +#define ADC_Prescaler_Div2 ((uint32_t)0x00000000) +#define ADC_Prescaler_Div4 ((uint32_t)0x00010000) +#define ADC_Prescaler_Div6 ((uint32_t)0x00020000) +#define ADC_Prescaler_Div8 ((uint32_t)0x00030000) +#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ + ((PRESCALER) == ADC_Prescaler_Div4) || \ + ((PRESCALER) == ADC_Prescaler_Div6) || \ + ((PRESCALER) == ADC_Prescaler_Div8)) +/** + * @} + */ + + +/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode + * @{ + */ +#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ +#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ +#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ +#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ +#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ + ((MODE) == ADC_DMAAccessMode_1) || \ + ((MODE) == ADC_DMAAccessMode_2) || \ + ((MODE) == ADC_DMAAccessMode_3)) + +/** + * @} + */ + + +/** @defgroup ADC_delay_between_2_sampling_phases + * @{ + */ +#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) +#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) +#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) +#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) +#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) +#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) +#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) +#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) +#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) +#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) +#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) +#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) +#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) +#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) +#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) +#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) +#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) + +/** + * @} + */ + + +/** @defgroup ADC_resolution + * @{ + */ +#define ADC_Resolution_12b ((uint32_t)0x00000000) +#define ADC_Resolution_10b ((uint32_t)0x01000000) +#define ADC_Resolution_8b ((uint32_t)0x02000000) +#define ADC_Resolution_6b ((uint32_t)0x03000000) +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ + ((RESOLUTION) == ADC_Resolution_10b) || \ + ((RESOLUTION) == ADC_Resolution_8b) || \ + ((RESOLUTION) == ADC_Resolution_6b)) + +/** + * @} + */ + + +/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion + * @{ + */ +#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) +#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) +#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) +#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) +#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) +/** + * @} + */ + + +/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion + * @{ + */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) +#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) +#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) +#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) +/** + * @} + */ + + +/** @defgroup ADC_data_align + * @{ + */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + + +/** @defgroup ADC_channels + * @{ + */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) +#define ADC_Channel_18 ((uint8_t)0x12) + +#if defined (STM32F40_41xxx) +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE) +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18) +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ + +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) +#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ + ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || \ + ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || \ + ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || \ + ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || \ + ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || \ + ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || \ + ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || \ + ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || \ + ((CHANNEL) == ADC_Channel_17) || \ + ((CHANNEL) == ADC_Channel_18)) +/** + * @} + */ + + +/** @defgroup ADC_sampling_times + * @{ + */ +#define ADC_SampleTime_3Cycles ((uint8_t)0x00) +#define ADC_SampleTime_15Cycles ((uint8_t)0x01) +#define ADC_SampleTime_28Cycles ((uint8_t)0x02) +#define ADC_SampleTime_56Cycles ((uint8_t)0x03) +#define ADC_SampleTime_84Cycles ((uint8_t)0x04) +#define ADC_SampleTime_112Cycles ((uint8_t)0x05) +#define ADC_SampleTime_144Cycles ((uint8_t)0x06) +#define ADC_SampleTime_480Cycles ((uint8_t)0x07) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ + ((TIME) == ADC_SampleTime_15Cycles) || \ + ((TIME) == ADC_SampleTime_28Cycles) || \ + ((TIME) == ADC_SampleTime_56Cycles) || \ + ((TIME) == ADC_SampleTime_84Cycles) || \ + ((TIME) == ADC_SampleTime_112Cycles) || \ + ((TIME) == ADC_SampleTime_144Cycles) || \ + ((TIME) == ADC_SampleTime_480Cycles)) +/** + * @} + */ + + +/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion + * @{ + */ +#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) +#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) +#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) +#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) + +/** + * @} + */ + + +/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion + * @{ + */ +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) +#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) +#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) +#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) +/** + * @} + */ + + +/** @defgroup ADC_injected_channel_selection + * @{ + */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) +/** + * @} + */ + + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** + * @} + */ + + +/** @defgroup ADC_interrupts_definition + * @{ + */ +#define ADC_IT_EOC ((uint16_t)0x0205) +#define ADC_IT_AWD ((uint16_t)0x0106) +#define ADC_IT_JEOC ((uint16_t)0x0407) +#define ADC_IT_OVR ((uint16_t)0x201A) +#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) +/** + * @} + */ + + +/** @defgroup ADC_flags_definition + * @{ + */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) +#define ADC_FLAG_OVR ((uint8_t)0x20) + +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ + ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || \ + ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT) || \ + ((FLAG)== ADC_FLAG_OVR)) +/** + * @} + */ + + +/** @defgroup ADC_thresholds + * @{ + */ +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) +/** + * @} + */ + + +/** @defgroup ADC_injected_offset + * @{ + */ +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) +/** + * @} + */ + + +/** @defgroup ADC_injected_length + * @{ + */ +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) +/** + * @} + */ + + +/** @defgroup ADC_injected_rank + * @{ + */ +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) +/** + * @} + */ + + +/** @defgroup ADC_regular_length + * @{ + */ +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + + +/** @defgroup ADC_regular_rank + * @{ + */ +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) +/** + * @} + */ + + +/** @defgroup ADC_regular_discontinuous_mode_number + * @{ + */ +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the ADC configuration to the default reset state *****/ +void ADC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); +void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +/* Analog Watchdog configuration functions ************************************/ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); + +/* Temperature Sensor, Vrefint and VBAT management functions ******************/ +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +void ADC_VBATCmd(FunctionalState NewState); + +/* Regular Channels Configuration functions ***********************************/ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetMultiModeConversionValue(void); + +/* Regular Channels DMA Configuration functions *******************************/ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); + +/* Injected channels Configuration functions **********************************/ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); +void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); + +/* Interrupts and flags management functions **********************************/ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h index 5733ac703..790e50027 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h @@ -1,644 +1,644 @@ -/** - ****************************************************************************** - * @file stm32f4xx_can.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the CAN firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CAN_H -#define __STM32F4xx_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ - ((PERIPH) == CAN2)) - -/** - * @brief CAN init structure definition - */ -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_InitStatus - * @{ - */ - -#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ - - -/* Legacy defines */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -/** - * @} - */ - -/** @defgroup CAN_operating_mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ - ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || \ - ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - - - /** - * @defgroup CAN_operating_mode - * @{ - */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ - - -#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ - ((MODE) == CAN_OperatingMode_Normal)|| \ - ((MODE) == CAN_OperatingMode_Sleep)) -/** - * @} - */ - -/** - * @defgroup CAN_operating_mode_status - * @{ - */ - -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) - -/* Legacy defines */ -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -/** - * @} - */ - -/** @defgroup CAN_Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ -#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ - ((IDTYPE) == CAN_Id_Extended)) - -/* Legacy defines */ -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ -#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) - -/* Legacy defines */ -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ -#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide - an empty mailbox */ -/* Legacy defines */ -#define CANTXFAILED CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ -#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/* Legacy defines */ -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ -#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/* Legacy defines */ -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok -/** - * @} - */ - -/** - * @defgroup CAN_Error_Code_constants - * @{ - */ -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ - -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ - -#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ - ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ - ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ - ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_SLAK )) - -#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ - ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) -/** - * @} - */ - - -/** @defgroup CAN_interrupts - * @{ - */ -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CAN configuration to the default reset state *****/ -void CAN_DeInit(CAN_TypeDef* CANx); - -/* Initialization and Configuration functions *********************************/ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); - -/* CAN Frames Transmission functions ******************************************/ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); - -/* CAN Frames Reception functions *********************************************/ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); - -/* Operation modes functions **************************************************/ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); - -/* CAN Bus Error management functions *****************************************/ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); - -/* Interrupts and flags management functions **********************************/ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_CAN_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_can.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the CAN firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_CAN_H +#define __STM32F4xx_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ + ((PERIPH) == CAN2)) + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_InitTypeDef; + +/** + * @brief CAN filter init structure definition + */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Constants + * @{ + */ + +/** @defgroup CAN_InitStatus + * @{ + */ + +#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ + + +/* Legacy defines */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +/** + * @} + */ + +/** @defgroup CAN_operating_mode + * @{ + */ + +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ + ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || \ + ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + + + /** + * @defgroup CAN_operating_mode + * @{ + */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ + + +#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ + ((MODE) == CAN_OperatingMode_Normal)|| \ + ((MODE) == CAN_OperatingMode_Sleep)) +/** + * @} + */ + +/** + * @defgroup CAN_operating_mode_status + * @{ + */ + +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ +#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ +#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler + * @{ + */ +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) +/** + * @} + */ + +/** @defgroup CAN_filter_number + * @{ + */ +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +/** + * @} + */ + +/** @defgroup CAN_filter_mode + * @{ + */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale + * @{ + */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO + * @{ + */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) + +/* Legacy defines */ +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +/** + * @} + */ + +/** @defgroup CAN_Start_bank_filter_for_slave_CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) +/** + * @} + */ + +/** @defgroup CAN_Tx + * @{ + */ +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) +/** + * @} + */ + +/** @defgroup CAN_identifier_type + * @{ + */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ + ((IDTYPE) == CAN_Id_Extended)) + +/* Legacy defines */ +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request + * @{ + */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) + +/* Legacy defines */ +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +/** + * @} + */ + +/** @defgroup CAN_transmit_constants + * @{ + */ +#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide + an empty mailbox */ +/* Legacy defines */ +#define CANTXFAILED CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +/** + * @} + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/* Legacy defines */ +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +/** + * @} + */ + +/** @defgroup CAN_wake_up_constants + * @{ + */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/* Legacy defines */ +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok +/** + * @} + */ + +/** + * @defgroup CAN_Error_Code_constants + * @{ + */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ +/** + * @} + */ + +/** @defgroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ + ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ + ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ + ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_SLAK )) + +#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ + ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + + +/** @defgroup CAN_interrupts + * @{ + */ +#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + + +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the CAN configuration to the default reset state *****/ +void CAN_DeInit(CAN_TypeDef* CANx); + +/* Initialization and Configuration functions *********************************/ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); + +/* CAN Frames Transmission functions ******************************************/ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); + +/* CAN Frames Reception functions *********************************************/ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); + +/* CAN Bus Error management functions *****************************************/ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_CAN_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h index fb9519317..9fb34f9e3 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h @@ -1,83 +1,83 @@ -/** - ****************************************************************************** - * @file stm32f4xx_crc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CRC_H -#define __STM32F4xx_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRC_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_CRC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_crc.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_CRC_H +#define __STM32F4xx_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_CRC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h index 110b7f305..2d70d8b2b 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h @@ -1,384 +1,384 @@ -/** - ****************************************************************************** - * @file stm32f4xx_cryp.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the Cryptographic - * processor(CRYP) firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CRYP_H -#define __STM32F4xx_CRYP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRYP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief CRYP Init structure definition - */ -typedef struct -{ - uint32_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a - value of @ref CRYP_Algorithm_Direction */ - uint32_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, - AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM. - This parameter can be a value of @ref CRYP_Algorithm_Mode */ - uint32_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit string. - This parameter can be a value of @ref CRYP_Data_Type */ - uint32_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit - key length. This parameter can be a value of - @ref CRYP_Key_Size_for_AES_only */ -}CRYP_InitTypeDef; - -/** - * @brief CRYP Key(s) structure definition - */ -typedef struct -{ - uint32_t CRYP_Key0Left; /*!< Key 0 Left */ - uint32_t CRYP_Key0Right; /*!< Key 0 Right */ - uint32_t CRYP_Key1Left; /*!< Key 1 left */ - uint32_t CRYP_Key1Right; /*!< Key 1 Right */ - uint32_t CRYP_Key2Left; /*!< Key 2 left */ - uint32_t CRYP_Key2Right; /*!< Key 2 Right */ - uint32_t CRYP_Key3Left; /*!< Key 3 left */ - uint32_t CRYP_Key3Right; /*!< Key 3 Right */ -}CRYP_KeyInitTypeDef; -/** - * @brief CRYP Initialization Vectors (IV) structure definition - */ -typedef struct -{ - uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */ - uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */ - uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */ - uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */ -}CRYP_IVInitTypeDef; - -/** - * @brief CRYP context swapping structure definition - */ -typedef struct -{ - /*!< Current Configuration */ - uint32_t CR_CurrentConfig; - /*!< IV */ - uint32_t CRYP_IV0LR; - uint32_t CRYP_IV0RR; - uint32_t CRYP_IV1LR; - uint32_t CRYP_IV1RR; - /*!< KEY */ - uint32_t CRYP_K0LR; - uint32_t CRYP_K0RR; - uint32_t CRYP_K1LR; - uint32_t CRYP_K1RR; - uint32_t CRYP_K2LR; - uint32_t CRYP_K2RR; - uint32_t CRYP_K3LR; - uint32_t CRYP_K3RR; - uint32_t CRYP_CSGCMCCMR[8]; - uint32_t CRYP_CSGCMR[8]; -}CRYP_Context; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRYP_Exported_Constants - * @{ - */ - -/** @defgroup CRYP_Algorithm_Direction - * @{ - */ -#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000) -#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004) -#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \ - ((ALGODIR) == CRYP_AlgoDir_Decrypt)) - -/** - * @} - */ - -/** @defgroup CRYP_Algorithm_Mode - * @{ - */ - -/*!< TDES Modes */ -#define CRYP_AlgoMode_TDES_ECB ((uint32_t)0x00000000) -#define CRYP_AlgoMode_TDES_CBC ((uint32_t)0x00000008) - -/*!< DES Modes */ -#define CRYP_AlgoMode_DES_ECB ((uint32_t)0x00000010) -#define CRYP_AlgoMode_DES_CBC ((uint32_t)0x00000018) - -/*!< AES Modes */ -#define CRYP_AlgoMode_AES_ECB ((uint32_t)0x00000020) -#define CRYP_AlgoMode_AES_CBC ((uint32_t)0x00000028) -#define CRYP_AlgoMode_AES_CTR ((uint32_t)0x00000030) -#define CRYP_AlgoMode_AES_Key ((uint32_t)0x00000038) -#define CRYP_AlgoMode_AES_GCM ((uint32_t)0x00080000) -#define CRYP_AlgoMode_AES_CCM ((uint32_t)0x00080008) - -#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ - ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CCM)) -/** - * @} - */ - -/** @defgroup CRYP_Phase - * @{ - */ - -/*!< The phases are valid only for AES-GCM and AES-CCM modes */ -#define CRYP_Phase_Init ((uint32_t)0x00000000) -#define CRYP_Phase_Header CRYP_CR_GCM_CCMPH_0 -#define CRYP_Phase_Payload CRYP_CR_GCM_CCMPH_1 -#define CRYP_Phase_Final CRYP_CR_GCM_CCMPH - -#define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init) || \ - ((PHASE) == CRYP_Phase_Header) || \ - ((PHASE) == CRYP_Phase_Payload) || \ - ((PHASE) == CRYP_Phase_Final)) - -/** - * @} - */ - -/** @defgroup CRYP_Data_Type - * @{ - */ -#define CRYP_DataType_32b ((uint16_t)0x0000) -#define CRYP_DataType_16b ((uint16_t)0x0040) -#define CRYP_DataType_8b ((uint16_t)0x0080) -#define CRYP_DataType_1b ((uint16_t)0x00C0) -#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \ - ((DATATYPE) == CRYP_DataType_16b)|| \ - ((DATATYPE) == CRYP_DataType_8b)|| \ - ((DATATYPE) == CRYP_DataType_1b)) -/** - * @} - */ - -/** @defgroup CRYP_Key_Size_for_AES_only - * @{ - */ -#define CRYP_KeySize_128b ((uint16_t)0x0000) -#define CRYP_KeySize_192b ((uint16_t)0x0100) -#define CRYP_KeySize_256b ((uint16_t)0x0200) -#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \ - ((KEYSIZE) == CRYP_KeySize_192b)|| \ - ((KEYSIZE) == CRYP_KeySize_256b)) -/** - * @} - */ - -/** @defgroup CRYP_flags_definition - * @{ - */ -#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently - processing a block of data - or a key preparation (for - AES decryption). */ -#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */ -#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */ -#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */ -#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw - interrupt status */ -#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */ -#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw - interrupt status */ - -#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \ - ((FLAG) == CRYP_FLAG_IFNF) || \ - ((FLAG) == CRYP_FLAG_OFNE) || \ - ((FLAG) == CRYP_FLAG_OFFU) || \ - ((FLAG) == CRYP_FLAG_BUSY) || \ - ((FLAG) == CRYP_FLAG_OUTRIS)|| \ - ((FLAG) == CRYP_FLAG_INRIS)) -/** - * @} - */ - -/** @defgroup CRYP_interrupts_definition - * @{ - */ -#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */ -#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */ -#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) -#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI)) - -/** - * @} - */ - -/** @defgroup CRYP_Encryption_Decryption_modes_definition - * @{ - */ -#define MODE_ENCRYPT ((uint8_t)0x01) -#define MODE_DECRYPT ((uint8_t)0x00) - -/** - * @} - */ - -/** @defgroup CRYP_DMA_transfer_requests - * @{ - */ -#define CRYP_DMAReq_DataIN ((uint8_t)0x01) -#define CRYP_DMAReq_DataOUT ((uint8_t)0x02) -#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CRYP configuration to the default reset state ****/ -void CRYP_DeInit(void); - -/* CRYP Initialization and Configuration functions ****************************/ -void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct); -void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct); -void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); -void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); -void CRYP_Cmd(FunctionalState NewState); -void CRYP_PhaseConfig(uint32_t CRYP_Phase); -void CRYP_FIFOFlush(void); -/* CRYP Data processing functions *********************************************/ -void CRYP_DataIn(uint32_t Data); -uint32_t CRYP_DataOut(void); - -/* CRYP Context swapping functions ********************************************/ -ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, - CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); - -/* CRYP DMA interface function ************************************************/ -void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); -ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); -FunctionalState CRYP_GetCmdStatus(void); -FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); - -/* High Level AES functions **************************************************/ -ErrorStatus CRYP_AES_ECB(uint8_t Mode, - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_CBC(uint8_t Mode, - uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_CTR(uint8_t Mode, - uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t ILength, - uint8_t *Header, uint32_t HLength, - uint8_t *Output, uint8_t *AuthTAG); - -ErrorStatus CRYP_AES_CCM(uint8_t Mode, - uint8_t* Nonce, uint32_t NonceSize, - uint8_t* Key, uint16_t Keysize, - uint8_t* Input, uint32_t ILength, - uint8_t* Header, uint32_t HLength, uint8_t *HBuffer, - uint8_t* Output, - uint8_t* AuthTAG, uint32_t TAGSize); - -/* High Level TDES functions **************************************************/ -ErrorStatus CRYP_TDES_ECB(uint8_t Mode, - uint8_t Key[24], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_TDES_CBC(uint8_t Mode, - uint8_t Key[24], - uint8_t InitVectors[8], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -/* High Level DES functions **************************************************/ -ErrorStatus CRYP_DES_ECB(uint8_t Mode, - uint8_t Key[8], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_DES_CBC(uint8_t Mode, - uint8_t Key[8], - uint8_t InitVectors[8], - uint8_t *Input,uint32_t Ilength, - uint8_t *Output); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_CRYP_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_cryp.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the Cryptographic + * processor(CRYP) firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_CRYP_H +#define __STM32F4xx_CRYP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRYP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief CRYP Init structure definition + */ +typedef struct +{ + uint32_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a + value of @ref CRYP_Algorithm_Direction */ + uint32_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, + AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM. + This parameter can be a value of @ref CRYP_Algorithm_Mode */ + uint32_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit string. + This parameter can be a value of @ref CRYP_Data_Type */ + uint32_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit + key length. This parameter can be a value of + @ref CRYP_Key_Size_for_AES_only */ +}CRYP_InitTypeDef; + +/** + * @brief CRYP Key(s) structure definition + */ +typedef struct +{ + uint32_t CRYP_Key0Left; /*!< Key 0 Left */ + uint32_t CRYP_Key0Right; /*!< Key 0 Right */ + uint32_t CRYP_Key1Left; /*!< Key 1 left */ + uint32_t CRYP_Key1Right; /*!< Key 1 Right */ + uint32_t CRYP_Key2Left; /*!< Key 2 left */ + uint32_t CRYP_Key2Right; /*!< Key 2 Right */ + uint32_t CRYP_Key3Left; /*!< Key 3 left */ + uint32_t CRYP_Key3Right; /*!< Key 3 Right */ +}CRYP_KeyInitTypeDef; +/** + * @brief CRYP Initialization Vectors (IV) structure definition + */ +typedef struct +{ + uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */ + uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */ + uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */ + uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */ +}CRYP_IVInitTypeDef; + +/** + * @brief CRYP context swapping structure definition + */ +typedef struct +{ + /*!< Current Configuration */ + uint32_t CR_CurrentConfig; + /*!< IV */ + uint32_t CRYP_IV0LR; + uint32_t CRYP_IV0RR; + uint32_t CRYP_IV1LR; + uint32_t CRYP_IV1RR; + /*!< KEY */ + uint32_t CRYP_K0LR; + uint32_t CRYP_K0RR; + uint32_t CRYP_K1LR; + uint32_t CRYP_K1RR; + uint32_t CRYP_K2LR; + uint32_t CRYP_K2RR; + uint32_t CRYP_K3LR; + uint32_t CRYP_K3RR; + uint32_t CRYP_CSGCMCCMR[8]; + uint32_t CRYP_CSGCMR[8]; +}CRYP_Context; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRYP_Exported_Constants + * @{ + */ + +/** @defgroup CRYP_Algorithm_Direction + * @{ + */ +#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000) +#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004) +#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \ + ((ALGODIR) == CRYP_AlgoDir_Decrypt)) + +/** + * @} + */ + +/** @defgroup CRYP_Algorithm_Mode + * @{ + */ + +/*!< TDES Modes */ +#define CRYP_AlgoMode_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_AlgoMode_TDES_CBC ((uint32_t)0x00000008) + +/*!< DES Modes */ +#define CRYP_AlgoMode_DES_ECB ((uint32_t)0x00000010) +#define CRYP_AlgoMode_DES_CBC ((uint32_t)0x00000018) + +/*!< AES Modes */ +#define CRYP_AlgoMode_AES_ECB ((uint32_t)0x00000020) +#define CRYP_AlgoMode_AES_CBC ((uint32_t)0x00000028) +#define CRYP_AlgoMode_AES_CTR ((uint32_t)0x00000030) +#define CRYP_AlgoMode_AES_Key ((uint32_t)0x00000038) +#define CRYP_AlgoMode_AES_GCM ((uint32_t)0x00080000) +#define CRYP_AlgoMode_AES_CCM ((uint32_t)0x00080008) + +#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ + ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ + ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \ + ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_CCM)) +/** + * @} + */ + +/** @defgroup CRYP_Phase + * @{ + */ + +/*!< The phases are valid only for AES-GCM and AES-CCM modes */ +#define CRYP_Phase_Init ((uint32_t)0x00000000) +#define CRYP_Phase_Header CRYP_CR_GCM_CCMPH_0 +#define CRYP_Phase_Payload CRYP_CR_GCM_CCMPH_1 +#define CRYP_Phase_Final CRYP_CR_GCM_CCMPH + +#define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init) || \ + ((PHASE) == CRYP_Phase_Header) || \ + ((PHASE) == CRYP_Phase_Payload) || \ + ((PHASE) == CRYP_Phase_Final)) + +/** + * @} + */ + +/** @defgroup CRYP_Data_Type + * @{ + */ +#define CRYP_DataType_32b ((uint16_t)0x0000) +#define CRYP_DataType_16b ((uint16_t)0x0040) +#define CRYP_DataType_8b ((uint16_t)0x0080) +#define CRYP_DataType_1b ((uint16_t)0x00C0) +#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \ + ((DATATYPE) == CRYP_DataType_16b)|| \ + ((DATATYPE) == CRYP_DataType_8b)|| \ + ((DATATYPE) == CRYP_DataType_1b)) +/** + * @} + */ + +/** @defgroup CRYP_Key_Size_for_AES_only + * @{ + */ +#define CRYP_KeySize_128b ((uint16_t)0x0000) +#define CRYP_KeySize_192b ((uint16_t)0x0100) +#define CRYP_KeySize_256b ((uint16_t)0x0200) +#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \ + ((KEYSIZE) == CRYP_KeySize_192b)|| \ + ((KEYSIZE) == CRYP_KeySize_256b)) +/** + * @} + */ + +/** @defgroup CRYP_flags_definition + * @{ + */ +#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently + processing a block of data + or a key preparation (for + AES decryption). */ +#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */ +#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */ +#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */ +#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw + interrupt status */ +#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */ +#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw + interrupt status */ + +#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \ + ((FLAG) == CRYP_FLAG_IFNF) || \ + ((FLAG) == CRYP_FLAG_OFNE) || \ + ((FLAG) == CRYP_FLAG_OFFU) || \ + ((FLAG) == CRYP_FLAG_BUSY) || \ + ((FLAG) == CRYP_FLAG_OUTRIS)|| \ + ((FLAG) == CRYP_FLAG_INRIS)) +/** + * @} + */ + +/** @defgroup CRYP_interrupts_definition + * @{ + */ +#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */ +#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */ +#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) +#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI)) + +/** + * @} + */ + +/** @defgroup CRYP_Encryption_Decryption_modes_definition + * @{ + */ +#define MODE_ENCRYPT ((uint8_t)0x01) +#define MODE_DECRYPT ((uint8_t)0x00) + +/** + * @} + */ + +/** @defgroup CRYP_DMA_transfer_requests + * @{ + */ +#define CRYP_DMAReq_DataIN ((uint8_t)0x01) +#define CRYP_DMAReq_DataOUT ((uint8_t)0x02) +#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the CRYP configuration to the default reset state ****/ +void CRYP_DeInit(void); + +/* CRYP Initialization and Configuration functions ****************************/ +void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct); +void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct); +void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); +void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); +void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); +void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); +void CRYP_Cmd(FunctionalState NewState); +void CRYP_PhaseConfig(uint32_t CRYP_Phase); +void CRYP_FIFOFlush(void); +/* CRYP Data processing functions *********************************************/ +void CRYP_DataIn(uint32_t Data); +uint32_t CRYP_DataOut(void); + +/* CRYP Context swapping functions ********************************************/ +ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, + CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); +void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); + +/* CRYP DMA interface function ************************************************/ +void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); +ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); +FunctionalState CRYP_GetCmdStatus(void); +FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); + +/* High Level AES functions **************************************************/ +ErrorStatus CRYP_AES_ECB(uint8_t Mode, + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_AES_CBC(uint8_t Mode, + uint8_t InitVectors[16], + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_AES_CTR(uint8_t Mode, + uint8_t InitVectors[16], + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16], + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t ILength, + uint8_t *Header, uint32_t HLength, + uint8_t *Output, uint8_t *AuthTAG); + +ErrorStatus CRYP_AES_CCM(uint8_t Mode, + uint8_t* Nonce, uint32_t NonceSize, + uint8_t* Key, uint16_t Keysize, + uint8_t* Input, uint32_t ILength, + uint8_t* Header, uint32_t HLength, uint8_t *HBuffer, + uint8_t* Output, + uint8_t* AuthTAG, uint32_t TAGSize); + +/* High Level TDES functions **************************************************/ +ErrorStatus CRYP_TDES_ECB(uint8_t Mode, + uint8_t Key[24], + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_TDES_CBC(uint8_t Mode, + uint8_t Key[24], + uint8_t InitVectors[8], + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +/* High Level DES functions **************************************************/ +ErrorStatus CRYP_DES_ECB(uint8_t Mode, + uint8_t Key[8], + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_DES_CBC(uint8_t Mode, + uint8_t Key[8], + uint8_t InitVectors[8], + uint8_t *Input,uint32_t Ilength, + uint8_t *Output); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_CRYP_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h index e185a2a6a..13ce2e80b 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h @@ -1,304 +1,304 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dac.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DAC_H -#define __STM32F4xx_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ - -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignement - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ - -/** @defgroup DAC_interrupts_definition - * @{ - */ -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DAC configuration to the default reset state *****/ -void DAC_DeInit(void); - -/* DAC channels configuration: trigger, output buffer, data format functions */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); - -/* DMA management functions ***************************************************/ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_DAC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_dac.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_DAC_H +#define __STM32F4xx_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ + +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** @defgroup DAC_interrupts_definition + * @{ + */ +#define DAC_IT_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the DAC configuration to the default reset state *****/ +void DAC_DeInit(void); + +/* DAC channels configuration: trigger, output buffer, data format functions */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +/* DMA management functions ***************************************************/ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_DAC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h index 6c9cb9724..971cd60b3 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h @@ -1,109 +1,109 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dbgmcu.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the DBGMCU firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DBGMCU_H -#define __STM32F4xx_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) -#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040) -#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080) -#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100) -#define DBGMCU_RTC_STOP ((uint32_t)0x00000400) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) -#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000) -#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000) -#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000) -#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_DBGMCU_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_dbgmcu.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the DBGMCU firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_DBGMCU_H +#define __STM32F4xx_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) + +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) +#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040) +#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080) +#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100) +#define DBGMCU_RTC_STOP ((uint32_t)0x00000400) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) +#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000) +#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00)) + +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) +#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000) +#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_DBGMCU_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h index 8e46d49be..fa7150090 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h @@ -1,312 +1,312 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dcmi.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the DCMI firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DCMI_H -#define __STM32F4xx_DCMI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DCMI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief DCMI Init structure definition - */ -typedef struct -{ - uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot. - This parameter can be a value of @ref DCMI_Capture_Mode */ - - uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. - This parameter can be a value of @ref DCMI_Synchronization_Mode */ - - uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. - This parameter can be a value of @ref DCMI_PIXCK_Polarity */ - - uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_VSYNC_Polarity */ - - uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_HSYNC_Polarity */ - - uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. - This parameter can be a value of @ref DCMI_Capture_Rate */ - - uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. - This parameter can be a value of @ref DCMI_Extended_Data_Mode */ -} DCMI_InitTypeDef; - -/** - * @brief DCMI CROP Init structure definition - */ -typedef struct -{ - uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture - will start. This parameter can be a value between 0x00 and 0x1FFF */ - - uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture. - This parameter can be a value between 0x00 and 0x3FFF */ - - uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point. - This parameter can be a value between 0x00 and 0x3FFF */ - - uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting - point on the same line. - This parameter can be a value between 0x00 and 0x3FFF */ -} DCMI_CROPInitTypeDef; - -/** - * @brief DCMI Embedded Synchronisation CODE Init structure definition - */ -typedef struct -{ - uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ - uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */ - uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */ - uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ -} DCMI_CodesInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DCMI_Exported_Constants - * @{ - */ - -/** @defgroup DCMI_Capture_Mode - * @{ - */ -#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously - into the destination memory through the DMA */ -#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of - frame and then transfers a single frame through the DMA */ -#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \ - ((MODE) == DCMI_CaptureMode_SnapShot)) -/** - * @} - */ - - -/** @defgroup DCMI_Synchronization_Mode - * @{ - */ -#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop) - is synchronized with the HSYNC/VSYNC signals */ -#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with - synchronization codes embedded in the data flow */ -#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \ - ((MODE) == DCMI_SynchroMode_Embedded)) -/** - * @} - */ - - -/** @defgroup DCMI_PIXCK_Polarity - * @{ - */ -#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */ -#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */ -#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \ - ((POLARITY) == DCMI_PCKPolarity_Rising)) -/** - * @} - */ - - -/** @defgroup DCMI_VSYNC_Polarity - * @{ - */ -#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */ -#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */ -#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \ - ((POLARITY) == DCMI_VSPolarity_High)) -/** - * @} - */ - - -/** @defgroup DCMI_HSYNC_Polarity - * @{ - */ -#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */ -#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */ -#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \ - ((POLARITY) == DCMI_HSPolarity_High)) -/** - * @} - */ - - -/** @defgroup DCMI_Capture_Rate - * @{ - */ -#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */ -#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */ -#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */ -#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \ - ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\ - ((RATE) == DCMI_CaptureRate_1of4_Frame)) -/** - * @} - */ - - -/** @defgroup DCMI_Extended_Data_Mode - * @{ - */ -#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */ -#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \ - ((DATA) == DCMI_ExtendedDataMode_10b) ||\ - ((DATA) == DCMI_ExtendedDataMode_12b) ||\ - ((DATA) == DCMI_ExtendedDataMode_14b)) -/** - * @} - */ - - -/** @defgroup DCMI_interrupt_sources - * @{ - */ -#define DCMI_IT_FRAME ((uint16_t)0x0001) -#define DCMI_IT_OVF ((uint16_t)0x0002) -#define DCMI_IT_ERR ((uint16_t)0x0004) -#define DCMI_IT_VSYNC ((uint16_t)0x0008) -#define DCMI_IT_LINE ((uint16_t)0x0010) -#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000)) -#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \ - ((IT) == DCMI_IT_OVF) || \ - ((IT) == DCMI_IT_ERR) || \ - ((IT) == DCMI_IT_VSYNC) || \ - ((IT) == DCMI_IT_LINE)) -/** - * @} - */ - - -/** @defgroup DCMI_Flags - * @{ - */ -/** - * @brief DCMI SR register - */ -#define DCMI_FLAG_HSYNC ((uint16_t)0x2001) -#define DCMI_FLAG_VSYNC ((uint16_t)0x2002) -#define DCMI_FLAG_FNE ((uint16_t)0x2004) -/** - * @brief DCMI RISR register - */ -#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001) -#define DCMI_FLAG_OVFRI ((uint16_t)0x0002) -#define DCMI_FLAG_ERRRI ((uint16_t)0x0004) -#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008) -#define DCMI_FLAG_LINERI ((uint16_t)0x0010) -/** - * @brief DCMI MISR register - */ -#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001) -#define DCMI_FLAG_OVFMI ((uint16_t)0x1002) -#define DCMI_FLAG_ERRMI ((uint16_t)0x1004) -#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008) -#define DCMI_FLAG_LINEMI ((uint16_t)0x1010) -#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \ - ((FLAG) == DCMI_FLAG_VSYNC) || \ - ((FLAG) == DCMI_FLAG_FNE) || \ - ((FLAG) == DCMI_FLAG_FRAMERI) || \ - ((FLAG) == DCMI_FLAG_OVFRI) || \ - ((FLAG) == DCMI_FLAG_ERRRI) || \ - ((FLAG) == DCMI_FLAG_VSYNCRI) || \ - ((FLAG) == DCMI_FLAG_LINERI) || \ - ((FLAG) == DCMI_FLAG_FRAMEMI) || \ - ((FLAG) == DCMI_FLAG_OVFMI) || \ - ((FLAG) == DCMI_FLAG_ERRMI) || \ - ((FLAG) == DCMI_FLAG_VSYNCMI) || \ - ((FLAG) == DCMI_FLAG_LINEMI)) - -#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DCMI configuration to the default reset state ****/ -void DCMI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct); -void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct); -void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct); -void DCMI_CROPCmd(FunctionalState NewState); -void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct); -void DCMI_JPEGCmd(FunctionalState NewState); - -/* Image capture functions ****************************************************/ -void DCMI_Cmd(FunctionalState NewState); -void DCMI_CaptureCmd(FunctionalState NewState); -uint32_t DCMI_ReadData(void); - -/* Interrupts and flags management functions **********************************/ -void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState); -FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG); -void DCMI_ClearFlag(uint16_t DCMI_FLAG); -ITStatus DCMI_GetITStatus(uint16_t DCMI_IT); -void DCMI_ClearITPendingBit(uint16_t DCMI_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_DCMI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_dcmi.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the DCMI firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_DCMI_H +#define __STM32F4xx_DCMI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DCMI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief DCMI Init structure definition + */ +typedef struct +{ + uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot. + This parameter can be a value of @ref DCMI_Capture_Mode */ + + uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. + This parameter can be a value of @ref DCMI_Synchronization_Mode */ + + uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. + This parameter can be a value of @ref DCMI_PIXCK_Polarity */ + + uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. + This parameter can be a value of @ref DCMI_VSYNC_Polarity */ + + uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. + This parameter can be a value of @ref DCMI_HSYNC_Polarity */ + + uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. + This parameter can be a value of @ref DCMI_Capture_Rate */ + + uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. + This parameter can be a value of @ref DCMI_Extended_Data_Mode */ +} DCMI_InitTypeDef; + +/** + * @brief DCMI CROP Init structure definition + */ +typedef struct +{ + uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture + will start. This parameter can be a value between 0x00 and 0x1FFF */ + + uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture. + This parameter can be a value between 0x00 and 0x3FFF */ + + uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point. + This parameter can be a value between 0x00 and 0x3FFF */ + + uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting + point on the same line. + This parameter can be a value between 0x00 and 0x3FFF */ +} DCMI_CROPInitTypeDef; + +/** + * @brief DCMI Embedded Synchronisation CODE Init structure definition + */ +typedef struct +{ + uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ + uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */ + uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */ + uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ +} DCMI_CodesInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DCMI_Exported_Constants + * @{ + */ + +/** @defgroup DCMI_Capture_Mode + * @{ + */ +#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously + into the destination memory through the DMA */ +#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of + frame and then transfers a single frame through the DMA */ +#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \ + ((MODE) == DCMI_CaptureMode_SnapShot)) +/** + * @} + */ + + +/** @defgroup DCMI_Synchronization_Mode + * @{ + */ +#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop) + is synchronized with the HSYNC/VSYNC signals */ +#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with + synchronization codes embedded in the data flow */ +#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \ + ((MODE) == DCMI_SynchroMode_Embedded)) +/** + * @} + */ + + +/** @defgroup DCMI_PIXCK_Polarity + * @{ + */ +#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */ +#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */ +#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \ + ((POLARITY) == DCMI_PCKPolarity_Rising)) +/** + * @} + */ + + +/** @defgroup DCMI_VSYNC_Polarity + * @{ + */ +#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */ +#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */ +#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \ + ((POLARITY) == DCMI_VSPolarity_High)) +/** + * @} + */ + + +/** @defgroup DCMI_HSYNC_Polarity + * @{ + */ +#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */ +#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */ +#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \ + ((POLARITY) == DCMI_HSPolarity_High)) +/** + * @} + */ + + +/** @defgroup DCMI_Capture_Rate + * @{ + */ +#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */ +#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */ +#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */ +#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \ + ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\ + ((RATE) == DCMI_CaptureRate_1of4_Frame)) +/** + * @} + */ + + +/** @defgroup DCMI_Extended_Data_Mode + * @{ + */ +#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */ +#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */ +#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */ +#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */ +#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \ + ((DATA) == DCMI_ExtendedDataMode_10b) ||\ + ((DATA) == DCMI_ExtendedDataMode_12b) ||\ + ((DATA) == DCMI_ExtendedDataMode_14b)) +/** + * @} + */ + + +/** @defgroup DCMI_interrupt_sources + * @{ + */ +#define DCMI_IT_FRAME ((uint16_t)0x0001) +#define DCMI_IT_OVF ((uint16_t)0x0002) +#define DCMI_IT_ERR ((uint16_t)0x0004) +#define DCMI_IT_VSYNC ((uint16_t)0x0008) +#define DCMI_IT_LINE ((uint16_t)0x0010) +#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000)) +#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \ + ((IT) == DCMI_IT_OVF) || \ + ((IT) == DCMI_IT_ERR) || \ + ((IT) == DCMI_IT_VSYNC) || \ + ((IT) == DCMI_IT_LINE)) +/** + * @} + */ + + +/** @defgroup DCMI_Flags + * @{ + */ +/** + * @brief DCMI SR register + */ +#define DCMI_FLAG_HSYNC ((uint16_t)0x2001) +#define DCMI_FLAG_VSYNC ((uint16_t)0x2002) +#define DCMI_FLAG_FNE ((uint16_t)0x2004) +/** + * @brief DCMI RISR register + */ +#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001) +#define DCMI_FLAG_OVFRI ((uint16_t)0x0002) +#define DCMI_FLAG_ERRRI ((uint16_t)0x0004) +#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008) +#define DCMI_FLAG_LINERI ((uint16_t)0x0010) +/** + * @brief DCMI MISR register + */ +#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001) +#define DCMI_FLAG_OVFMI ((uint16_t)0x1002) +#define DCMI_FLAG_ERRMI ((uint16_t)0x1004) +#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008) +#define DCMI_FLAG_LINEMI ((uint16_t)0x1010) +#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \ + ((FLAG) == DCMI_FLAG_VSYNC) || \ + ((FLAG) == DCMI_FLAG_FNE) || \ + ((FLAG) == DCMI_FLAG_FRAMERI) || \ + ((FLAG) == DCMI_FLAG_OVFRI) || \ + ((FLAG) == DCMI_FLAG_ERRRI) || \ + ((FLAG) == DCMI_FLAG_VSYNCRI) || \ + ((FLAG) == DCMI_FLAG_LINERI) || \ + ((FLAG) == DCMI_FLAG_FRAMEMI) || \ + ((FLAG) == DCMI_FLAG_OVFMI) || \ + ((FLAG) == DCMI_FLAG_ERRMI) || \ + ((FLAG) == DCMI_FLAG_VSYNCMI) || \ + ((FLAG) == DCMI_FLAG_LINEMI)) + +#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the DCMI configuration to the default reset state ****/ +void DCMI_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct); +void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct); +void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct); +void DCMI_CROPCmd(FunctionalState NewState); +void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct); +void DCMI_JPEGCmd(FunctionalState NewState); + +/* Image capture functions ****************************************************/ +void DCMI_Cmd(FunctionalState NewState); +void DCMI_CaptureCmd(FunctionalState NewState); +uint32_t DCMI_ReadData(void); + +/* Interrupts and flags management functions **********************************/ +void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState); +FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG); +void DCMI_ClearFlag(uint16_t DCMI_FLAG); +ITStatus DCMI_GetITStatus(uint16_t DCMI_IT); +void DCMI_ClearITPendingBit(uint16_t DCMI_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_DCMI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h index 74a75095f..0536d02c5 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h @@ -1,609 +1,609 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DMA_H -#define __STM32F4xx_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA Init structure definition - */ - -typedef struct -{ - uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. - This parameter can be a value of @ref DMA_channel */ - - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ - - uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. - This memory is the default memory used when double buffer mode is - not enabled. */ - - uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. - This parameter can be a value of @ref DMA_circular_normal_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Stream */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. - This parameter can be a value of @ref DMA_fifo_direct_mode - @note The Direct mode (FIFO mode disabled) cannot be used if the - memory-to-memory data transfer is configured on the selected Stream */ - - uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref DMA_fifo_threshold_level */ - - uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_memory_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ - - uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_peripheral_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ - ((PERIPH) == DMA1_Stream1) || \ - ((PERIPH) == DMA1_Stream2) || \ - ((PERIPH) == DMA1_Stream3) || \ - ((PERIPH) == DMA1_Stream4) || \ - ((PERIPH) == DMA1_Stream5) || \ - ((PERIPH) == DMA1_Stream6) || \ - ((PERIPH) == DMA1_Stream7) || \ - ((PERIPH) == DMA2_Stream0) || \ - ((PERIPH) == DMA2_Stream1) || \ - ((PERIPH) == DMA2_Stream2) || \ - ((PERIPH) == DMA2_Stream3) || \ - ((PERIPH) == DMA2_Stream4) || \ - ((PERIPH) == DMA2_Stream5) || \ - ((PERIPH) == DMA2_Stream6) || \ - ((PERIPH) == DMA2_Stream7)) - -#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \ - ((CONTROLLER) == DMA2)) - -/** @defgroup DMA_channel - * @{ - */ -#define DMA_Channel_0 ((uint32_t)0x00000000) -#define DMA_Channel_1 ((uint32_t)0x02000000) -#define DMA_Channel_2 ((uint32_t)0x04000000) -#define DMA_Channel_3 ((uint32_t)0x06000000) -#define DMA_Channel_4 ((uint32_t)0x08000000) -#define DMA_Channel_5 ((uint32_t)0x0A000000) -#define DMA_Channel_6 ((uint32_t)0x0C000000) -#define DMA_Channel_7 ((uint32_t)0x0E000000) - -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ - ((CHANNEL) == DMA_Channel_1) || \ - ((CHANNEL) == DMA_Channel_2) || \ - ((CHANNEL) == DMA_Channel_3) || \ - ((CHANNEL) == DMA_Channel_4) || \ - ((CHANNEL) == DMA_Channel_5) || \ - ((CHANNEL) == DMA_Channel_6) || \ - ((CHANNEL) == DMA_Channel_7)) -/** - * @} - */ - - -/** @defgroup DMA_data_transfer_direction - * @{ - */ -#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) -#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) -#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ - ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ - ((DIRECTION) == DMA_DIR_MemoryToMemory)) -/** - * @} - */ - - -/** @defgroup DMA_data_buffer_size - * @{ - */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ - ((STATE) == DMA_PeripheralInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000400) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ - ((STATE) == DMA_MemoryInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_data_size - * @{ - */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - - -/** @defgroup DMA_memory_data_size - * @{ - */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word )) -/** - * @} - */ - - -/** @defgroup DMA_circular_normal_mode - * @{ - */ -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define DMA_Mode_Circular ((uint32_t)0x00000100) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \ - ((MODE) == DMA_Mode_Circular)) -/** - * @} - */ - - -/** @defgroup DMA_priority_level - * @{ - */ -#define DMA_Priority_Low ((uint32_t)0x00000000) -#define DMA_Priority_Medium ((uint32_t)0x00010000) -#define DMA_Priority_High ((uint32_t)0x00020000) -#define DMA_Priority_VeryHigh ((uint32_t)0x00030000) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_VeryHigh)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_direct_mode - * @{ - */ -#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) -#define DMA_FIFOMode_Enable ((uint32_t)0x00000004) - -#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ - ((STATE) == DMA_FIFOMode_Enable)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_threshold_level - * @{ - */ -#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) -#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) -#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) -#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) - -#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ - ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_Full)) -/** - * @} - */ - - -/** @defgroup DMA_memory_burst - * @{ - */ -#define DMA_MemoryBurst_Single ((uint32_t)0x00000000) -#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) -#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) -#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) - -#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ - ((BURST) == DMA_MemoryBurst_INC4) || \ - ((BURST) == DMA_MemoryBurst_INC8) || \ - ((BURST) == DMA_MemoryBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_burst - * @{ - */ -#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) -#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) -#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) -#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) - -#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ - ((BURST) == DMA_PeripheralBurst_INC4) || \ - ((BURST) == DMA_PeripheralBurst_INC8) || \ - ((BURST) == DMA_PeripheralBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_status_level - * @{ - */ -#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) -#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) -#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) -#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) -#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) -#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) - -#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ - ((STATUS) == DMA_FIFOStatus_HalfFull) || \ - ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ - ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ - ((STATUS) == DMA_FIFOStatus_Full) || \ - ((STATUS) == DMA_FIFOStatus_Empty)) -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) -#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) -#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) -#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) -#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) -#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) -#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) -#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) -#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) -#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) -#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) -#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) -#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) -#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) -#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) -#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) -#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) -#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) -#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) -#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) -#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) -#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) -#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) -#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) -#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) -#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) -#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) -#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) -#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) -#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) -#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) -#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) -#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) -#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) -#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) -#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) -#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) -#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) -#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) -#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) - -#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ - (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ - ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ - ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ - ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ - ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ - ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ - ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ - ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ - ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ - ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ - ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ - ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ - ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ - ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ - ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ - ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ - ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ - ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ - ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ - ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions - * @{ - */ -#define DMA_IT_TC ((uint32_t)0x00000010) -#define DMA_IT_HT ((uint32_t)0x00000008) -#define DMA_IT_TE ((uint32_t)0x00000004) -#define DMA_IT_DME ((uint32_t)0x00000002) -#define DMA_IT_FE ((uint32_t)0x00000080) - -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - - -/** @defgroup DMA_interrupts_definitions - * @{ - */ -#define DMA_IT_FEIF0 ((uint32_t)0x90000001) -#define DMA_IT_DMEIF0 ((uint32_t)0x10001004) -#define DMA_IT_TEIF0 ((uint32_t)0x10002008) -#define DMA_IT_HTIF0 ((uint32_t)0x10004010) -#define DMA_IT_TCIF0 ((uint32_t)0x10008020) -#define DMA_IT_FEIF1 ((uint32_t)0x90000040) -#define DMA_IT_DMEIF1 ((uint32_t)0x10001100) -#define DMA_IT_TEIF1 ((uint32_t)0x10002200) -#define DMA_IT_HTIF1 ((uint32_t)0x10004400) -#define DMA_IT_TCIF1 ((uint32_t)0x10008800) -#define DMA_IT_FEIF2 ((uint32_t)0x90010000) -#define DMA_IT_DMEIF2 ((uint32_t)0x10041000) -#define DMA_IT_TEIF2 ((uint32_t)0x10082000) -#define DMA_IT_HTIF2 ((uint32_t)0x10104000) -#define DMA_IT_TCIF2 ((uint32_t)0x10208000) -#define DMA_IT_FEIF3 ((uint32_t)0x90400000) -#define DMA_IT_DMEIF3 ((uint32_t)0x11001000) -#define DMA_IT_TEIF3 ((uint32_t)0x12002000) -#define DMA_IT_HTIF3 ((uint32_t)0x14004000) -#define DMA_IT_TCIF3 ((uint32_t)0x18008000) -#define DMA_IT_FEIF4 ((uint32_t)0xA0000001) -#define DMA_IT_DMEIF4 ((uint32_t)0x20001004) -#define DMA_IT_TEIF4 ((uint32_t)0x20002008) -#define DMA_IT_HTIF4 ((uint32_t)0x20004010) -#define DMA_IT_TCIF4 ((uint32_t)0x20008020) -#define DMA_IT_FEIF5 ((uint32_t)0xA0000040) -#define DMA_IT_DMEIF5 ((uint32_t)0x20001100) -#define DMA_IT_TEIF5 ((uint32_t)0x20002200) -#define DMA_IT_HTIF5 ((uint32_t)0x20004400) -#define DMA_IT_TCIF5 ((uint32_t)0x20008800) -#define DMA_IT_FEIF6 ((uint32_t)0xA0010000) -#define DMA_IT_DMEIF6 ((uint32_t)0x20041000) -#define DMA_IT_TEIF6 ((uint32_t)0x20082000) -#define DMA_IT_HTIF6 ((uint32_t)0x20104000) -#define DMA_IT_TCIF6 ((uint32_t)0x20208000) -#define DMA_IT_FEIF7 ((uint32_t)0xA0400000) -#define DMA_IT_DMEIF7 ((uint32_t)0x21001000) -#define DMA_IT_TEIF7 ((uint32_t)0x22002000) -#define DMA_IT_HTIF7 ((uint32_t)0x24004000) -#define DMA_IT_TCIF7 ((uint32_t)0x28008000) - -#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ - (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ - (((IT) & 0x40820082) == 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \ - ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ - ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ - ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ - ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ - ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ - ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ - ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ - ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ - ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ - ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ - ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ - ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ - ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ - ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ - ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ - ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ - ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ - ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ - ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_increment_offset - * @{ - */ -#define DMA_PINCOS_Psize ((uint32_t)0x00000000) -#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) - -#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ - ((SIZE) == DMA_PINCOS_WordAligned)) -/** - * @} - */ - - -/** @defgroup DMA_flow_controller_definitions - * @{ - */ -#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) -#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) - -#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ - ((CTRL) == DMA_FlowCtrl_Peripheral)) -/** - * @} - */ - - -/** @defgroup DMA_memory_targets_definitions - * @{ - */ -#define DMA_Memory_0 ((uint32_t)0x00000000) -#define DMA_Memory_1 ((uint32_t)0x00080000) - -#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DMA configuration to the default reset state *****/ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Initialization and Configuration functions *********************************/ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - -/* Optional Configuration functions *******************************************/ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos); -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl); - -/* Data Counter functions *****************************************************/ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Double Buffer mode functions ***********************************************/ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory); -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget); -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Interrupts and flags management functions **********************************/ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_DMA_H */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_dma.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_DMA_H +#define __STM32F4xx_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. + This parameter can be a value of @ref DMA_channel */ + + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ + + uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. + This memory is the default memory used when double buffer mode is + not enabled. */ + + uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_circular_normal_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. + This parameter can be a value of @ref DMA_fifo_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected Stream */ + + uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_fifo_threshold_level */ + + uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptable + transaction. This parameter can be a value of @ref DMA_memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptable + transaction. This parameter can be a value of @ref DMA_peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ + ((PERIPH) == DMA1_Stream1) || \ + ((PERIPH) == DMA1_Stream2) || \ + ((PERIPH) == DMA1_Stream3) || \ + ((PERIPH) == DMA1_Stream4) || \ + ((PERIPH) == DMA1_Stream5) || \ + ((PERIPH) == DMA1_Stream6) || \ + ((PERIPH) == DMA1_Stream7) || \ + ((PERIPH) == DMA2_Stream0) || \ + ((PERIPH) == DMA2_Stream1) || \ + ((PERIPH) == DMA2_Stream2) || \ + ((PERIPH) == DMA2_Stream3) || \ + ((PERIPH) == DMA2_Stream4) || \ + ((PERIPH) == DMA2_Stream5) || \ + ((PERIPH) == DMA2_Stream6) || \ + ((PERIPH) == DMA2_Stream7)) + +#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \ + ((CONTROLLER) == DMA2)) + +/** @defgroup DMA_channel + * @{ + */ +#define DMA_Channel_0 ((uint32_t)0x00000000) +#define DMA_Channel_1 ((uint32_t)0x02000000) +#define DMA_Channel_2 ((uint32_t)0x04000000) +#define DMA_Channel_3 ((uint32_t)0x06000000) +#define DMA_Channel_4 ((uint32_t)0x08000000) +#define DMA_Channel_5 ((uint32_t)0x0A000000) +#define DMA_Channel_6 ((uint32_t)0x0C000000) +#define DMA_Channel_7 ((uint32_t)0x0E000000) + +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ + ((CHANNEL) == DMA_Channel_1) || \ + ((CHANNEL) == DMA_Channel_2) || \ + ((CHANNEL) == DMA_Channel_3) || \ + ((CHANNEL) == DMA_Channel_4) || \ + ((CHANNEL) == DMA_Channel_5) || \ + ((CHANNEL) == DMA_Channel_6) || \ + ((CHANNEL) == DMA_Channel_7)) +/** + * @} + */ + + +/** @defgroup DMA_data_transfer_direction + * @{ + */ +#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) +#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) +#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ + ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ + ((DIRECTION) == DMA_DIR_MemoryToMemory)) +/** + * @} + */ + + +/** @defgroup DMA_data_buffer_size + * @{ + */ +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** + * @} + */ + + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000400) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_data_size + * @{ + */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + + +/** @defgroup DMA_memory_data_size + * @{ + */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word )) +/** + * @} + */ + + +/** @defgroup DMA_circular_normal_mode + * @{ + */ +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define DMA_Mode_Circular ((uint32_t)0x00000100) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \ + ((MODE) == DMA_Mode_Circular)) +/** + * @} + */ + + +/** @defgroup DMA_priority_level + * @{ + */ +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define DMA_Priority_Medium ((uint32_t)0x00010000) +#define DMA_Priority_High ((uint32_t)0x00020000) +#define DMA_Priority_VeryHigh ((uint32_t)0x00030000) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_VeryHigh)) +/** + * @} + */ + + +/** @defgroup DMA_fifo_direct_mode + * @{ + */ +#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) +#define DMA_FIFOMode_Enable ((uint32_t)0x00000004) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ + ((STATE) == DMA_FIFOMode_Enable)) +/** + * @} + */ + + +/** @defgroup DMA_fifo_threshold_level + * @{ + */ +#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) +#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) +#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) +#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ + ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ + ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ + ((THRESHOLD) == DMA_FIFOThreshold_Full)) +/** + * @} + */ + + +/** @defgroup DMA_memory_burst + * @{ + */ +#define DMA_MemoryBurst_Single ((uint32_t)0x00000000) +#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) +#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) +#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ + ((BURST) == DMA_MemoryBurst_INC4) || \ + ((BURST) == DMA_MemoryBurst_INC8) || \ + ((BURST) == DMA_MemoryBurst_INC16)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_burst + * @{ + */ +#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) +#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) +#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) +#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ + ((BURST) == DMA_PeripheralBurst_INC4) || \ + ((BURST) == DMA_PeripheralBurst_INC8) || \ + ((BURST) == DMA_PeripheralBurst_INC16)) +/** + * @} + */ + + +/** @defgroup DMA_fifo_status_level + * @{ + */ +#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) +#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) +#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) +#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) +#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) +#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) + +#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ + ((STATUS) == DMA_FIFOStatus_HalfFull) || \ + ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ + ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ + ((STATUS) == DMA_FIFOStatus_Full) || \ + ((STATUS) == DMA_FIFOStatus_Empty)) +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) +#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) +#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) +#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) +#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) +#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) +#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) +#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) +#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) +#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) +#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) +#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) +#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) +#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) +#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) +#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) +#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) +#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) +#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) +#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) +#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) +#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) +#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) +#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) +#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) +#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) +#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) +#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) +#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) +#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) +#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) +#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) +#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) +#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) +#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) +#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) +#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) +#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) +#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) +#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) + +#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ + (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ + ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ + ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ + ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ + ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ + ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ + ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ + ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ + ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ + ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ + ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ + ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ + ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ + ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ + ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ + ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ + ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ + ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ + ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ + ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions + * @{ + */ +#define DMA_IT_TC ((uint32_t)0x00000010) +#define DMA_IT_HT ((uint32_t)0x00000008) +#define DMA_IT_TE ((uint32_t)0x00000004) +#define DMA_IT_DME ((uint32_t)0x00000002) +#define DMA_IT_FE ((uint32_t)0x00000080) + +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + + +/** @defgroup DMA_interrupts_definitions + * @{ + */ +#define DMA_IT_FEIF0 ((uint32_t)0x90000001) +#define DMA_IT_DMEIF0 ((uint32_t)0x10001004) +#define DMA_IT_TEIF0 ((uint32_t)0x10002008) +#define DMA_IT_HTIF0 ((uint32_t)0x10004010) +#define DMA_IT_TCIF0 ((uint32_t)0x10008020) +#define DMA_IT_FEIF1 ((uint32_t)0x90000040) +#define DMA_IT_DMEIF1 ((uint32_t)0x10001100) +#define DMA_IT_TEIF1 ((uint32_t)0x10002200) +#define DMA_IT_HTIF1 ((uint32_t)0x10004400) +#define DMA_IT_TCIF1 ((uint32_t)0x10008800) +#define DMA_IT_FEIF2 ((uint32_t)0x90010000) +#define DMA_IT_DMEIF2 ((uint32_t)0x10041000) +#define DMA_IT_TEIF2 ((uint32_t)0x10082000) +#define DMA_IT_HTIF2 ((uint32_t)0x10104000) +#define DMA_IT_TCIF2 ((uint32_t)0x10208000) +#define DMA_IT_FEIF3 ((uint32_t)0x90400000) +#define DMA_IT_DMEIF3 ((uint32_t)0x11001000) +#define DMA_IT_TEIF3 ((uint32_t)0x12002000) +#define DMA_IT_HTIF3 ((uint32_t)0x14004000) +#define DMA_IT_TCIF3 ((uint32_t)0x18008000) +#define DMA_IT_FEIF4 ((uint32_t)0xA0000001) +#define DMA_IT_DMEIF4 ((uint32_t)0x20001004) +#define DMA_IT_TEIF4 ((uint32_t)0x20002008) +#define DMA_IT_HTIF4 ((uint32_t)0x20004010) +#define DMA_IT_TCIF4 ((uint32_t)0x20008020) +#define DMA_IT_FEIF5 ((uint32_t)0xA0000040) +#define DMA_IT_DMEIF5 ((uint32_t)0x20001100) +#define DMA_IT_TEIF5 ((uint32_t)0x20002200) +#define DMA_IT_HTIF5 ((uint32_t)0x20004400) +#define DMA_IT_TCIF5 ((uint32_t)0x20008800) +#define DMA_IT_FEIF6 ((uint32_t)0xA0010000) +#define DMA_IT_DMEIF6 ((uint32_t)0x20041000) +#define DMA_IT_TEIF6 ((uint32_t)0x20082000) +#define DMA_IT_HTIF6 ((uint32_t)0x20104000) +#define DMA_IT_TCIF6 ((uint32_t)0x20208000) +#define DMA_IT_FEIF7 ((uint32_t)0xA0400000) +#define DMA_IT_DMEIF7 ((uint32_t)0x21001000) +#define DMA_IT_TEIF7 ((uint32_t)0x22002000) +#define DMA_IT_HTIF7 ((uint32_t)0x24004000) +#define DMA_IT_TCIF7 ((uint32_t)0x28008000) + +#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ + (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ + (((IT) & 0x40820082) == 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \ + ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ + ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ + ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ + ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ + ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ + ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ + ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ + ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ + ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ + ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ + ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ + ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ + ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ + ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ + ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ + ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ + ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ + ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ + ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_increment_offset + * @{ + */ +#define DMA_PINCOS_Psize ((uint32_t)0x00000000) +#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) + +#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ + ((SIZE) == DMA_PINCOS_WordAligned)) +/** + * @} + */ + + +/** @defgroup DMA_flow_controller_definitions + * @{ + */ +#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) +#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) + +#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ + ((CTRL) == DMA_FlowCtrl_Peripheral)) +/** + * @} + */ + + +/** @defgroup DMA_memory_targets_definitions + * @{ + */ +#define DMA_Memory_0 ((uint32_t)0x00000000) +#define DMA_Memory_1 ((uint32_t)0x00080000) + +#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the DMA configuration to the default reset state *****/ +void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx); + +/* Initialization and Configuration functions *********************************/ +void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); + +/* Optional Configuration functions *******************************************/ +void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos); +void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl); + +/* Data Counter functions *****************************************************/ +void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); +uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); + +/* Double Buffer mode functions ***********************************************/ +void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, + uint32_t DMA_CurrentMemory); +void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); +void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, + uint32_t DMA_MemoryTarget); +uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); + +/* Interrupts and flags management functions **********************************/ +FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); +uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); +FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); +void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); +void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); +ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); +void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_DMA_H */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h index 1dc95de1c..4c065a5a5 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h @@ -1,475 +1,475 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma2d.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the DMA2D firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DMA2D_H -#define __STM32F4xx_DMA2D_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA2D - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA2D Init structure definition - */ - -typedef struct -{ - uint32_t DMA2D_Mode; /*!< configures the DMA2D transfer mode. - This parameter can be one value of @ref DMA2D_MODE */ - - uint32_t DMA2D_CMode; /*!< configures the color format of the output image. - This parameter can be one value of @ref DMA2D_CMODE */ - - uint32_t DMA2D_OutputBlue; /*!< configures the blue value of the output image. - This parameter must range: - - from 0x00 to 0xFF if ARGB8888 color mode is slected - - from 0x00 to 0xFF if RGB888 color mode is slected - - from 0x00 to 0x1F if RGB565 color mode is slected - - from 0x00 to 0x1F if ARGB1555 color mode is slected - - from 0x00 to 0x0F if ARGB4444 color mode is slected */ - - uint32_t DMA2D_OutputGreen; /*!< configures the green value of the output image. - This parameter must range: - - from 0x00 to 0xFF if ARGB8888 color mode is slected - - from 0x00 to 0xFF if RGB888 color mode is slected - - from 0x00 to 0x2F if RGB565 color mode is slected - - from 0x00 to 0x1F if ARGB1555 color mode is slected - - from 0x00 to 0x0F if ARGB4444 color mode is slected */ - - uint32_t DMA2D_OutputRed; /*!< configures the red value of the output image. - This parameter must range: - - from 0x00 to 0xFF if ARGB8888 color mode is slected - - from 0x00 to 0xFF if RGB888 color mode is slected - - from 0x00 to 0x1F if RGB565 color mode is slected - - from 0x00 to 0x1F if ARGB1555 color mode is slected - - from 0x00 to 0x0F if ARGB4444 color mode is slected */ - - uint32_t DMA2D_OutputAlpha; /*!< configures the alpha channel of the output color. - This parameter must range: - - from 0x00 to 0xFF if ARGB8888 color mode is slected - - from 0x00 to 0x01 if ARGB1555 color mode is slected - - from 0x00 to 0x0F if ARGB4444 color mode is slected */ - - uint32_t DMA2D_OutputMemoryAdd; /*!< Specifies the memory address. This parameter - must be range from 0x00000000 to 0xFFFFFFFF. */ - - uint32_t DMA2D_OutputOffset; /*!< Specifies the Offset value. This parameter must be range from - 0x0000 to 0x3FFF. */ - - uint32_t DMA2D_NumberOfLine; /*!< Configures the number of line of the area to be transfered. - This parameter must range from 0x0000 to 0xFFFF */ - - uint32_t DMA2D_PixelPerLine; /*!< Configures the number pixel per line of the area to be transfered. - This parameter must range from 0x0000 to 0x3FFF */ -} DMA2D_InitTypeDef; - - - -typedef struct -{ - uint32_t DMA2D_FGMA; /*!< configures the DMA2D foreground memory address. - This parameter must be range from 0x00000000 to 0xFFFFFFFF. */ - - uint32_t DMA2D_FGO; /*!< configures the DMA2D foreground offset. - This parameter must be range from 0x0000 to 0x3FFF. */ - - uint32_t DMA2D_FGCM; /*!< configures the DMA2D foreground color mode . - This parameter can be one value of @ref DMA2D_FGCM */ - - uint32_t DMA2D_FG_CLUT_CM; /*!< configures the DMA2D foreground CLUT color mode. - This parameter can be one value of @ref DMA2D_FG_CLUT_CM */ - - uint32_t DMA2D_FG_CLUT_SIZE; /*!< configures the DMA2D foreground CLUT size. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t DMA2D_FGPFC_ALPHA_MODE; /*!< configures the DMA2D foreground alpha mode. - This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */ - - uint32_t DMA2D_FGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D foreground alpha value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_FGC_BLUE; /*!< Specifies the DMA2D foreground blue value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_FGC_GREEN; /*!< Specifies the DMA2D foreground green value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_FGC_RED; /*!< Specifies the DMA2D foreground red value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_FGCMAR; /*!< Configures the DMA2D foreground CLUT memory address. - This parameter must range from 0x00000000 to 0xFFFFFFFF. */ -} DMA2D_FG_InitTypeDef; - - -typedef struct -{ - uint32_t DMA2D_BGMA; /*!< configures the DMA2D background memory address. - This parameter must be range from 0x00000000 to 0xFFFFFFFF. */ - - uint32_t DMA2D_BGO; /*!< configures the DMA2D background offset. - This parameter must be range from 0x0000 to 0x3FFF. */ - - uint32_t DMA2D_BGCM; /*!< configures the DMA2D background color mode . - This parameter can be one value of @ref DMA2D_FGCM */ - - uint32_t DMA2D_BG_CLUT_CM; /*!< configures the DMA2D background CLUT color mode. - This parameter can be one value of @ref DMA2D_FG_CLUT_CM */ - - uint32_t DMA2D_BG_CLUT_SIZE; /*!< configures the DMA2D background CLUT size. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t DMA2D_BGPFC_ALPHA_MODE; /*!< configures the DMA2D background alpha mode. - This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */ - - uint32_t DMA2D_BGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D background alpha value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_BGC_BLUE; /*!< Specifies the DMA2D background blue value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_BGC_GREEN; /*!< Specifies the DMA2D background green value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_BGC_RED; /*!< Specifies the DMA2D background red value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_BGCMAR; /*!< Configures the DMA2D background CLUT memory address. - This parameter must range from 0x00000000 to 0xFFFFFFFF. */ -} DMA2D_BG_InitTypeDef; - - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA2D_Exported_Constants - * @{ - */ - -/** @defgroup DMA2D_MODE - * @{ - */ - - -#define DMA2D_M2M ((uint32_t)0x00000000) -#define DMA2D_M2M_PFC ((uint32_t)0x00010000) -#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) -#define DMA2D_R2M ((uint32_t)0x00030000) - -#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ - ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) - - -/** - * @} - */ - -/** @defgroup DMA2D_CMODE - * @{ - */ -#define DMA2D_ARGB8888 ((uint32_t)0x00000000) -#define DMA2D_RGB888 ((uint32_t)0x00000001) -#define DMA2D_RGB565 ((uint32_t)0x00000002) -#define DMA2D_ARGB1555 ((uint32_t)0x00000003) -#define DMA2D_ARGB4444 ((uint32_t)0x00000004) - -#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \ - ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \ - ((MODE_ARGB) == DMA2D_ARGB4444)) - - -/** - * @} - */ - -/** @defgroup DMA2D_OUTPUT_COLOR - * @{ - */ -#define DMA2D_Output_Color ((uint32_t)0x000000FF) - -#define IS_DMA2D_OGREEN(OGREEN) ((OGREEN) <= DMA2D_Output_Color) -#define IS_DMA2D_ORED(ORED) ((ORED) <= DMA2D_Output_Color) -#define IS_DMA2D_OBLUE(OBLUE) ((OBLUE) <= DMA2D_Output_Color) -#define IS_DMA2D_OALPHA(OALPHA) ((OALPHA) <= DMA2D_Output_Color) - -/** - * @} - */ - -/** @defgroup DMA2D_OUTPUT_OFFSET - * @{ - */ -#define DMA2D_OUTPUT_OFFSET ((uint32_t)0x00003FFF) - -#define IS_DMA2D_OUTPUT_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OUTPUT_OFFSET) - - -/** - * @} - */ - -/** @defgroup DMA2D_SIZE - * @{ - */ - -#define DMA2D_pixel ((uint32_t)0x00003FFF) -#define DMA2D_Line ((uint32_t)0x0000FFFF) - -#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_Line) -#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_pixel) - - -/** - * @} - */ - -/** @defgroup DMA2D_OFFSET - * @{ - */ -#define OFFSET ((uint32_t)0x00003FFF) - -#define IS_DMA2D_FGO(FGO) ((FGO) <= OFFSET) - -#define IS_DMA2D_BGO(BGO) ((BGO) <= OFFSET) - -/** - * @} - */ - - -/** @defgroup DMA2D_FGCM - * @{ - */ - -#define CM_ARGB8888 ((uint32_t)0x00000000) -#define CM_RGB888 ((uint32_t)0x00000001) -#define CM_RGB565 ((uint32_t)0x00000002) -#define CM_ARGB1555 ((uint32_t)0x00000003) -#define CM_ARGB4444 ((uint32_t)0x00000004) -#define CM_L8 ((uint32_t)0x00000005) -#define CM_AL44 ((uint32_t)0x00000006) -#define CM_AL88 ((uint32_t)0x00000007) -#define CM_L4 ((uint32_t)0x00000008) -#define CM_A8 ((uint32_t)0x00000009) -#define CM_A4 ((uint32_t)0x0000000A) - -#define IS_DMA2D_FGCM(FGCM) (((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \ - ((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \ - ((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \ - ((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \ - ((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \ - ((FGCM) == CM_A4)) - -#define IS_DMA2D_BGCM(BGCM) (((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \ - ((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \ - ((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \ - ((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \ - ((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \ - ((BGCM) == CM_A4)) - -/** - * @} - */ - -/** @defgroup DMA2D_FG_CLUT_CM - * @{ - */ - -#define CLUT_CM_ARGB8888 ((uint32_t)0x00000000) -#define CLUT_CM_RGB888 ((uint32_t)0x00000001) - -#define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM) (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888)) - -#define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM) (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888)) - -/** - * @} - */ - -/** @defgroup DMA2D_FG_COLOR_VALUE - * @{ - */ - -#define COLOR_VALUE ((uint32_t)0x000000FF) - -#define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE) ((FG_CLUT_SIZE) <= COLOR_VALUE) - -#define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE) ((FG_ALPHA_VALUE) <= COLOR_VALUE) -#define IS_DMA2D_FGC_BLUE(FGC_BLUE) ((FGC_BLUE) <= COLOR_VALUE) -#define IS_DMA2D_FGC_GREEN(FGC_GREEN) ((FGC_GREEN) <= COLOR_VALUE) -#define IS_DMA2D_FGC_RED(FGC_RED) ((FGC_RED) <= COLOR_VALUE) - -#define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE) ((BG_CLUT_SIZE) <= COLOR_VALUE) - -#define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE) ((BG_ALPHA_VALUE) <= COLOR_VALUE) -#define IS_DMA2D_BGC_BLUE(BGC_BLUE) ((BGC_BLUE) <= COLOR_VALUE) -#define IS_DMA2D_BGC_GREEN(BGC_GREEN) ((BGC_GREEN) <= COLOR_VALUE) -#define IS_DMA2D_BGC_RED(BGC_RED) ((BGC_RED) <= COLOR_VALUE) - -/** - * @} - */ - -/** DMA2D_FGPFC_ALPHA_MODE - * @{ - */ - -#define NO_MODIF_ALPHA_VALUE ((uint32_t)0x00000000) -#define REPLACE_ALPHA_VALUE ((uint32_t)0x00000001) -#define COMBINE_ALPHA_VALUE ((uint32_t)0x00000002) - -#define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE) (((FG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \ - ((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \ - ((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE)) - -#define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE) (((BG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \ - ((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \ - ((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE)) - -/** - * @} - */ - -/** @defgroup DMA2D_Interrupts - * @{ - */ - -#define DMA2D_IT_CE DMA2D_CR_CEIE -#define DMA2D_IT_CTC DMA2D_CR_CTCIE -#define DMA2D_IT_CAE DMA2D_CR_CAEIE -#define DMA2D_IT_TW DMA2D_CR_TWIE -#define DMA2D_IT_TC DMA2D_CR_TCIE -#define DMA2D_IT_TE DMA2D_CR_TEIE - -#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ - ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ - ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) - -/** - * @} - */ - -/** @defgroup DMA2D_Flag - * @{ - */ - -#define DMA2D_FLAG_CE DMA2D_ISR_CEIF -#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF -#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF -#define DMA2D_FLAG_TW DMA2D_ISR_TWIF -#define DMA2D_FLAG_TC DMA2D_ISR_TCIF -#define DMA2D_FLAG_TE DMA2D_ISR_TEIF - - -#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ - ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ - ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) - - -/** - * @} - */ - -/** @defgroup DMA2D_DeadTime - * @{ - */ - -#define DEADTIME ((uint32_t)0x000000FF) - -#define IS_DMA2D_DEAD_TIME(DEAD_TIME) ((DEAD_TIME) <= DEADTIME) - - -#define LINE_WATERMARK DMA2D_LWR_LW - -#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the DMA2D configuration to the default reset state *****/ -void DMA2D_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct); -void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct); -void DMA2D_StartTransfer(void); -void DMA2D_AbortTransfer(void); -void DMA2D_Suspend(FunctionalState NewState); -void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct); -void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct); -void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct); -void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct); -void DMA2D_FGStart(FunctionalState NewState); -void DMA2D_BGStart(FunctionalState NewState); -void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState); -void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig); - -/* Interrupts and flags management functions **********************************/ -void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState); -FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG); -void DMA2D_ClearFlag(uint32_t DMA2D_FLAG); -ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT); -void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_DMA2D_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_dma2d.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the DMA2D firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_DMA2D_H +#define __STM32F4xx_DMA2D_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA2D + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DMA2D Init structure definition + */ + +typedef struct +{ + uint32_t DMA2D_Mode; /*!< configures the DMA2D transfer mode. + This parameter can be one value of @ref DMA2D_MODE */ + + uint32_t DMA2D_CMode; /*!< configures the color format of the output image. + This parameter can be one value of @ref DMA2D_CMODE */ + + uint32_t DMA2D_OutputBlue; /*!< configures the blue value of the output image. + This parameter must range: + - from 0x00 to 0xFF if ARGB8888 color mode is slected + - from 0x00 to 0xFF if RGB888 color mode is slected + - from 0x00 to 0x1F if RGB565 color mode is slected + - from 0x00 to 0x1F if ARGB1555 color mode is slected + - from 0x00 to 0x0F if ARGB4444 color mode is slected */ + + uint32_t DMA2D_OutputGreen; /*!< configures the green value of the output image. + This parameter must range: + - from 0x00 to 0xFF if ARGB8888 color mode is slected + - from 0x00 to 0xFF if RGB888 color mode is slected + - from 0x00 to 0x2F if RGB565 color mode is slected + - from 0x00 to 0x1F if ARGB1555 color mode is slected + - from 0x00 to 0x0F if ARGB4444 color mode is slected */ + + uint32_t DMA2D_OutputRed; /*!< configures the red value of the output image. + This parameter must range: + - from 0x00 to 0xFF if ARGB8888 color mode is slected + - from 0x00 to 0xFF if RGB888 color mode is slected + - from 0x00 to 0x1F if RGB565 color mode is slected + - from 0x00 to 0x1F if ARGB1555 color mode is slected + - from 0x00 to 0x0F if ARGB4444 color mode is slected */ + + uint32_t DMA2D_OutputAlpha; /*!< configures the alpha channel of the output color. + This parameter must range: + - from 0x00 to 0xFF if ARGB8888 color mode is slected + - from 0x00 to 0x01 if ARGB1555 color mode is slected + - from 0x00 to 0x0F if ARGB4444 color mode is slected */ + + uint32_t DMA2D_OutputMemoryAdd; /*!< Specifies the memory address. This parameter + must be range from 0x00000000 to 0xFFFFFFFF. */ + + uint32_t DMA2D_OutputOffset; /*!< Specifies the Offset value. This parameter must be range from + 0x0000 to 0x3FFF. */ + + uint32_t DMA2D_NumberOfLine; /*!< Configures the number of line of the area to be transfered. + This parameter must range from 0x0000 to 0xFFFF */ + + uint32_t DMA2D_PixelPerLine; /*!< Configures the number pixel per line of the area to be transfered. + This parameter must range from 0x0000 to 0x3FFF */ +} DMA2D_InitTypeDef; + + + +typedef struct +{ + uint32_t DMA2D_FGMA; /*!< configures the DMA2D foreground memory address. + This parameter must be range from 0x00000000 to 0xFFFFFFFF. */ + + uint32_t DMA2D_FGO; /*!< configures the DMA2D foreground offset. + This parameter must be range from 0x0000 to 0x3FFF. */ + + uint32_t DMA2D_FGCM; /*!< configures the DMA2D foreground color mode . + This parameter can be one value of @ref DMA2D_FGCM */ + + uint32_t DMA2D_FG_CLUT_CM; /*!< configures the DMA2D foreground CLUT color mode. + This parameter can be one value of @ref DMA2D_FG_CLUT_CM */ + + uint32_t DMA2D_FG_CLUT_SIZE; /*!< configures the DMA2D foreground CLUT size. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t DMA2D_FGPFC_ALPHA_MODE; /*!< configures the DMA2D foreground alpha mode. + This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */ + + uint32_t DMA2D_FGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D foreground alpha value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_FGC_BLUE; /*!< Specifies the DMA2D foreground blue value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_FGC_GREEN; /*!< Specifies the DMA2D foreground green value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_FGC_RED; /*!< Specifies the DMA2D foreground red value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_FGCMAR; /*!< Configures the DMA2D foreground CLUT memory address. + This parameter must range from 0x00000000 to 0xFFFFFFFF. */ +} DMA2D_FG_InitTypeDef; + + +typedef struct +{ + uint32_t DMA2D_BGMA; /*!< configures the DMA2D background memory address. + This parameter must be range from 0x00000000 to 0xFFFFFFFF. */ + + uint32_t DMA2D_BGO; /*!< configures the DMA2D background offset. + This parameter must be range from 0x0000 to 0x3FFF. */ + + uint32_t DMA2D_BGCM; /*!< configures the DMA2D background color mode . + This parameter can be one value of @ref DMA2D_FGCM */ + + uint32_t DMA2D_BG_CLUT_CM; /*!< configures the DMA2D background CLUT color mode. + This parameter can be one value of @ref DMA2D_FG_CLUT_CM */ + + uint32_t DMA2D_BG_CLUT_SIZE; /*!< configures the DMA2D background CLUT size. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t DMA2D_BGPFC_ALPHA_MODE; /*!< configures the DMA2D background alpha mode. + This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */ + + uint32_t DMA2D_BGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D background alpha value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_BGC_BLUE; /*!< Specifies the DMA2D background blue value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_BGC_GREEN; /*!< Specifies the DMA2D background green value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_BGC_RED; /*!< Specifies the DMA2D background red value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_BGCMAR; /*!< Configures the DMA2D background CLUT memory address. + This parameter must range from 0x00000000 to 0xFFFFFFFF. */ +} DMA2D_BG_InitTypeDef; + + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA2D_Exported_Constants + * @{ + */ + +/** @defgroup DMA2D_MODE + * @{ + */ + + +#define DMA2D_M2M ((uint32_t)0x00000000) +#define DMA2D_M2M_PFC ((uint32_t)0x00010000) +#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) +#define DMA2D_R2M ((uint32_t)0x00030000) + +#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ + ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) + + +/** + * @} + */ + +/** @defgroup DMA2D_CMODE + * @{ + */ +#define DMA2D_ARGB8888 ((uint32_t)0x00000000) +#define DMA2D_RGB888 ((uint32_t)0x00000001) +#define DMA2D_RGB565 ((uint32_t)0x00000002) +#define DMA2D_ARGB1555 ((uint32_t)0x00000003) +#define DMA2D_ARGB4444 ((uint32_t)0x00000004) + +#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \ + ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \ + ((MODE_ARGB) == DMA2D_ARGB4444)) + + +/** + * @} + */ + +/** @defgroup DMA2D_OUTPUT_COLOR + * @{ + */ +#define DMA2D_Output_Color ((uint32_t)0x000000FF) + +#define IS_DMA2D_OGREEN(OGREEN) ((OGREEN) <= DMA2D_Output_Color) +#define IS_DMA2D_ORED(ORED) ((ORED) <= DMA2D_Output_Color) +#define IS_DMA2D_OBLUE(OBLUE) ((OBLUE) <= DMA2D_Output_Color) +#define IS_DMA2D_OALPHA(OALPHA) ((OALPHA) <= DMA2D_Output_Color) + +/** + * @} + */ + +/** @defgroup DMA2D_OUTPUT_OFFSET + * @{ + */ +#define DMA2D_OUTPUT_OFFSET ((uint32_t)0x00003FFF) + +#define IS_DMA2D_OUTPUT_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OUTPUT_OFFSET) + + +/** + * @} + */ + +/** @defgroup DMA2D_SIZE + * @{ + */ + +#define DMA2D_pixel ((uint32_t)0x00003FFF) +#define DMA2D_Line ((uint32_t)0x0000FFFF) + +#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_Line) +#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_pixel) + + +/** + * @} + */ + +/** @defgroup DMA2D_OFFSET + * @{ + */ +#define OFFSET ((uint32_t)0x00003FFF) + +#define IS_DMA2D_FGO(FGO) ((FGO) <= OFFSET) + +#define IS_DMA2D_BGO(BGO) ((BGO) <= OFFSET) + +/** + * @} + */ + + +/** @defgroup DMA2D_FGCM + * @{ + */ + +#define CM_ARGB8888 ((uint32_t)0x00000000) +#define CM_RGB888 ((uint32_t)0x00000001) +#define CM_RGB565 ((uint32_t)0x00000002) +#define CM_ARGB1555 ((uint32_t)0x00000003) +#define CM_ARGB4444 ((uint32_t)0x00000004) +#define CM_L8 ((uint32_t)0x00000005) +#define CM_AL44 ((uint32_t)0x00000006) +#define CM_AL88 ((uint32_t)0x00000007) +#define CM_L4 ((uint32_t)0x00000008) +#define CM_A8 ((uint32_t)0x00000009) +#define CM_A4 ((uint32_t)0x0000000A) + +#define IS_DMA2D_FGCM(FGCM) (((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \ + ((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \ + ((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \ + ((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \ + ((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \ + ((FGCM) == CM_A4)) + +#define IS_DMA2D_BGCM(BGCM) (((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \ + ((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \ + ((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \ + ((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \ + ((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \ + ((BGCM) == CM_A4)) + +/** + * @} + */ + +/** @defgroup DMA2D_FG_CLUT_CM + * @{ + */ + +#define CLUT_CM_ARGB8888 ((uint32_t)0x00000000) +#define CLUT_CM_RGB888 ((uint32_t)0x00000001) + +#define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM) (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888)) + +#define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM) (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888)) + +/** + * @} + */ + +/** @defgroup DMA2D_FG_COLOR_VALUE + * @{ + */ + +#define COLOR_VALUE ((uint32_t)0x000000FF) + +#define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE) ((FG_CLUT_SIZE) <= COLOR_VALUE) + +#define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE) ((FG_ALPHA_VALUE) <= COLOR_VALUE) +#define IS_DMA2D_FGC_BLUE(FGC_BLUE) ((FGC_BLUE) <= COLOR_VALUE) +#define IS_DMA2D_FGC_GREEN(FGC_GREEN) ((FGC_GREEN) <= COLOR_VALUE) +#define IS_DMA2D_FGC_RED(FGC_RED) ((FGC_RED) <= COLOR_VALUE) + +#define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE) ((BG_CLUT_SIZE) <= COLOR_VALUE) + +#define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE) ((BG_ALPHA_VALUE) <= COLOR_VALUE) +#define IS_DMA2D_BGC_BLUE(BGC_BLUE) ((BGC_BLUE) <= COLOR_VALUE) +#define IS_DMA2D_BGC_GREEN(BGC_GREEN) ((BGC_GREEN) <= COLOR_VALUE) +#define IS_DMA2D_BGC_RED(BGC_RED) ((BGC_RED) <= COLOR_VALUE) + +/** + * @} + */ + +/** DMA2D_FGPFC_ALPHA_MODE + * @{ + */ + +#define NO_MODIF_ALPHA_VALUE ((uint32_t)0x00000000) +#define REPLACE_ALPHA_VALUE ((uint32_t)0x00000001) +#define COMBINE_ALPHA_VALUE ((uint32_t)0x00000002) + +#define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE) (((FG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \ + ((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \ + ((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE)) + +#define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE) (((BG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \ + ((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \ + ((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE)) + +/** + * @} + */ + +/** @defgroup DMA2D_Interrupts + * @{ + */ + +#define DMA2D_IT_CE DMA2D_CR_CEIE +#define DMA2D_IT_CTC DMA2D_CR_CTCIE +#define DMA2D_IT_CAE DMA2D_CR_CAEIE +#define DMA2D_IT_TW DMA2D_CR_TWIE +#define DMA2D_IT_TC DMA2D_CR_TCIE +#define DMA2D_IT_TE DMA2D_CR_TEIE + +#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ + ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ + ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) + +/** + * @} + */ + +/** @defgroup DMA2D_Flag + * @{ + */ + +#define DMA2D_FLAG_CE DMA2D_ISR_CEIF +#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF +#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF +#define DMA2D_FLAG_TW DMA2D_ISR_TWIF +#define DMA2D_FLAG_TC DMA2D_ISR_TCIF +#define DMA2D_FLAG_TE DMA2D_ISR_TEIF + + +#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ + ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ + ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) + + +/** + * @} + */ + +/** @defgroup DMA2D_DeadTime + * @{ + */ + +#define DEADTIME ((uint32_t)0x000000FF) + +#define IS_DMA2D_DEAD_TIME(DEAD_TIME) ((DEAD_TIME) <= DEADTIME) + + +#define LINE_WATERMARK DMA2D_LWR_LW + +#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the DMA2D configuration to the default reset state *****/ +void DMA2D_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct); +void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct); +void DMA2D_StartTransfer(void); +void DMA2D_AbortTransfer(void); +void DMA2D_Suspend(FunctionalState NewState); +void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct); +void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct); +void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct); +void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct); +void DMA2D_FGStart(FunctionalState NewState); +void DMA2D_BGStart(FunctionalState NewState); +void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState); +void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig); + +/* Interrupts and flags management functions **********************************/ +void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState); +FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG); +void DMA2D_ClearFlag(uint32_t DMA2D_FLAG); +ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT); +void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_DMA2D_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h index 588ed291b..15eea4881 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h @@ -1,183 +1,183 @@ -/** - ****************************************************************************** - * @file stm32f4xx_exti.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_EXTI_H -#define __STM32F4xx_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination value of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTITrigger_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ -#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ -#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) - -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ - ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ - ((LINE) == EXTI_Line22)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the EXTI configuration to the default reset state *****/ -void EXTI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); - -/* Interrupts and flags management functions **********************************/ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_EXTI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_exti.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the EXTI firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_EXTI_H +#define __STM32F4xx_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination value of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTITrigger_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ + +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) + +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ + ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ + ((LINE) == EXTI_Line22)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the EXTI configuration to the default reset state *****/ +void EXTI_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); + +/* Interrupts and flags management functions **********************************/ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_EXTI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h index 0ca14fd6a..ea850387c 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h @@ -1,488 +1,488 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FLASH_H -#define __STM32F4xx_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_RD, - FLASH_ERROR_PGS, - FLASH_ERROR_PGP, - FLASH_ERROR_PGA, - FLASH_ERROR_WRP, - FLASH_ERROR_PROGRAM, - FLASH_ERROR_OPERATION, - FLASH_COMPLETE -}FLASH_Status; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ -#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ -#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ -#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ -#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ -#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ -#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ -#define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */ -#define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */ -#define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */ -#define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */ -#define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */ -#define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */ -#define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */ -#define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */ - - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2) || \ - ((LATENCY) == FLASH_Latency_3) || \ - ((LATENCY) == FLASH_Latency_4) || \ - ((LATENCY) == FLASH_Latency_5) || \ - ((LATENCY) == FLASH_Latency_6) || \ - ((LATENCY) == FLASH_Latency_7) || \ - ((LATENCY) == FLASH_Latency_8) || \ - ((LATENCY) == FLASH_Latency_9) || \ - ((LATENCY) == FLASH_Latency_10) || \ - ((LATENCY) == FLASH_Latency_11) || \ - ((LATENCY) == FLASH_Latency_12) || \ - ((LATENCY) == FLASH_Latency_13) || \ - ((LATENCY) == FLASH_Latency_14) || \ - ((LATENCY) == FLASH_Latency_15)) -/** - * @} - */ - -/** @defgroup FLASH_Voltage_Range - * @{ - */ -#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ -#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F401xx) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) -#endif /* STM32F401xx */ - -#if defined (STM32F411xE) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) -#endif /* STM32F411xE */ - -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ -#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ -#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ -#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ -#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ -#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ -#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ -#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ -#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ -#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ -#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ -#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ -#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ -#define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */ -#define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */ -#define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */ -#define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */ -#define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */ -#define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */ -#define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */ -#define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */ -#define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */ -#define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */ -#define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */ -#define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */ -#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -/** - * @} - */ - -/** @defgroup Selection_Protection_Mode - * @{ - */ -#define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */ -#define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */ -#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable)) -/** - * @} - */ - -/** @defgroup Option_Bytes_PC_ReadWrite_Protection - * @{ - */ -#define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ -#define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ -#define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ -#define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ -#define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ -#define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ -#define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */ -#define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */ -#define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */ -#define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */ -#define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */ -#define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */ -#define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */ -#define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */ -#define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */ -#define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */ -#define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */ -#define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */ -#define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */ -#define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */ -#define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */ -#define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */ -#define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */ -#define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */ -#define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ - -#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_Read_Protection - * @{ - */ -#define OB_RDP_Level_0 ((uint8_t)0xAA) -#define OB_RDP_Level_1 ((uint8_t)0x55) -/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ -#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ - ((LEVEL) == OB_RDP_Level_1))/*||\ - ((LEVEL) == OB_RDP_Level_2))*/ -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_IWatchdog - * @{ - */ -#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_nRST_STOP - * @{ - */ -#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) -/** - * @} - */ - - -/** @defgroup FLASH_Option_Bytes_nRST_STDBY - * @{ - */ -#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) -/** - * @} - */ - -/** @defgroup FLASH_BOR_Reset_Level - * @{ - */ -#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ -#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ - ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) -/** - * @} - */ - -/** @defgroup FLASH_Dual_Boot - * @{ - */ -#define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */ -#define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */ -#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ -#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ -#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ -#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ -#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */ -#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ - ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ - ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ - ((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR)) -/** - * @} - */ - -/** @defgroup FLASH_Program_Parallelism - * @{ - */ -#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) -#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) -#define FLASH_PSIZE_WORD ((uint32_t)0x00000200) -#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) -#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) -/** - * @} - */ - -/** @defgroup FLASH_Keys - * @{ - */ -#define RDP_KEY ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) -#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) -#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) -/** - * @} - */ - -/** - * @brief ACR register byte 0 (Bits[7:0]) base address - */ -#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) -/** - * @brief OPTCR register byte 0 (Bits[7:0]) base address - */ -#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) -/** - * @brief OPTCR register byte 1 (Bits[15:8]) base address - */ -#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) -/** - * @brief OPTCR register byte 2 (Bits[23:16]) base address - */ -#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) -/** - * @brief OPTCR register byte 3 (Bits[31:24]) base address - */ -#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17) - -/** - * @brief OPTCR1 register byte 0 (Bits[7:0]) base address - */ -#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_PrefetchBufferCmd(FunctionalState NewState); -void FLASH_InstructionCacheCmd(FunctionalState NewState); -void FLASH_DataCacheCmd(FunctionalState NewState); -void FLASH_InstructionCacheReset(void); -void FLASH_DataCacheReset(void); - -/* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange); -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); - -/* Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); -void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState); -void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP); -void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState); -void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState); -void FLASH_OB_RDPConfig(uint8_t OB_RDP); -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -void FLASH_OB_BORConfig(uint8_t OB_BOR); -void FLASH_OB_BootConfig(uint8_t OB_BOOT); -FLASH_Status FLASH_OB_Launch(void); -uint8_t FLASH_OB_GetUser(void); -uint16_t FLASH_OB_GetWRP(void); -uint16_t FLASH_OB_GetWRP1(void); -uint16_t FLASH_OB_GetPCROP(void); -uint16_t FLASH_OB_GetPCROP1(void); -FlagStatus FLASH_OB_GetRDP(void); -uint8_t FLASH_OB_GetBOR(void); - -/* Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_flash.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_FLASH_H +#define __STM32F4xx_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief FLASH Status + */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_RD, + FLASH_ERROR_PGS, + FLASH_ERROR_PGP, + FLASH_ERROR_PGA, + FLASH_ERROR_WRP, + FLASH_ERROR_PROGRAM, + FLASH_ERROR_OPERATION, + FLASH_COMPLETE +}FLASH_Status; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ +#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ +#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ +#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ +#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ +#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ +#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ +#define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */ +#define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */ +#define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */ +#define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */ +#define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */ +#define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */ +#define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */ +#define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */ + + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2) || \ + ((LATENCY) == FLASH_Latency_3) || \ + ((LATENCY) == FLASH_Latency_4) || \ + ((LATENCY) == FLASH_Latency_5) || \ + ((LATENCY) == FLASH_Latency_6) || \ + ((LATENCY) == FLASH_Latency_7) || \ + ((LATENCY) == FLASH_Latency_8) || \ + ((LATENCY) == FLASH_Latency_9) || \ + ((LATENCY) == FLASH_Latency_10) || \ + ((LATENCY) == FLASH_Latency_11) || \ + ((LATENCY) == FLASH_Latency_12) || \ + ((LATENCY) == FLASH_Latency_13) || \ + ((LATENCY) == FLASH_Latency_14) || \ + ((LATENCY) == FLASH_Latency_15)) +/** + * @} + */ + +/** @defgroup FLASH_Voltage_Range + * @{ + */ +#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ +#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\ + (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined (STM32F40_41xxx) +#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\ + (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F401xx) +#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\ + (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) +#endif /* STM32F401xx */ + +#if defined (STM32F411xE) +#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\ + (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) +#endif /* STM32F411xE */ + +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ +#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ +#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ +#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ +#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ +#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ +#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ +#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ +#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ +#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ +#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ +#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ +#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ +#define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */ +#define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */ +#define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */ +#define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */ +#define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */ +#define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */ +#define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */ +#define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */ +#define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */ +#define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */ +#define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */ +#define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */ +#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ + +#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) +/** + * @} + */ + +/** @defgroup Selection_Protection_Mode + * @{ + */ +#define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */ +#define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */ +#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable)) +/** + * @} + */ + +/** @defgroup Option_Bytes_PC_ReadWrite_Protection + * @{ + */ +#define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ +#define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ +#define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ +#define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ +#define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ +#define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ +#define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */ +#define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */ +#define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */ +#define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */ +#define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */ +#define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */ +#define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */ +#define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */ +#define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */ +#define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */ +#define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */ +#define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */ +#define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */ +#define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */ +#define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */ +#define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */ +#define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */ +#define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */ +#define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ + +#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_Read_Protection + * @{ + */ +#define OB_RDP_Level_0 ((uint8_t)0xAA) +#define OB_RDP_Level_1 ((uint8_t)0x55) +/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 + it's no more possible to go back to level 1 or 0 */ +#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ + ((LEVEL) == OB_RDP_Level_1))/*||\ + ((LEVEL) == OB_RDP_Level_2))*/ +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_IWatchdog + * @{ + */ +#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_nRST_STOP + * @{ + */ +#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) +/** + * @} + */ + + +/** @defgroup FLASH_Option_Bytes_nRST_STDBY + * @{ + */ +#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) +/** + * @} + */ + +/** @defgroup FLASH_BOR_Reset_Level + * @{ + */ +#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ + ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) +/** + * @} + */ + +/** @defgroup FLASH_Dual_Boot + * @{ + */ +#define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */ +#define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */ +#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled)) +/** + * @} + */ + +/** @defgroup FLASH_Interrupts + * @{ + */ +#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ +#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */ +#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ + ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ + ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ + ((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR)) +/** + * @} + */ + +/** @defgroup FLASH_Program_Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) +#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) +#define FLASH_PSIZE_WORD ((uint32_t)0x00000200) +#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) +#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) +/** + * @} + */ + +/** @defgroup FLASH_Keys + * @{ + */ +#define RDP_KEY ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) +#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) +#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) +/** + * @} + */ + +/** + * @brief ACR register byte 0 (Bits[7:0]) base address + */ +#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) +/** + * @brief OPTCR register byte 0 (Bits[7:0]) base address + */ +#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) +/** + * @brief OPTCR register byte 1 (Bits[15:8]) base address + */ +#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) +/** + * @brief OPTCR register byte 2 (Bits[23:16]) base address + */ +#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) +/** + * @brief OPTCR register byte 3 (Bits[31:24]) base address + */ +#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17) + +/** + * @brief OPTCR1 register byte 0 (Bits[7:0]) base address + */ +#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* FLASH Interface configuration functions ************************************/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_PrefetchBufferCmd(FunctionalState NewState); +void FLASH_InstructionCacheCmd(FunctionalState NewState); +void FLASH_DataCacheCmd(FunctionalState NewState); +void FLASH_InstructionCacheReset(void); +void FLASH_DataCacheReset(void); + +/* FLASH Memory Programming functions *****************************************/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); +FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); +FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange); +FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange); +FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); + +/* Option Bytes Programming functions *****************************************/ +void FLASH_OB_Unlock(void); +void FLASH_OB_Lock(void); +void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); +void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState); +void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP); +void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState); +void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState); +void FLASH_OB_RDPConfig(uint8_t OB_RDP); +void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); +void FLASH_OB_BORConfig(uint8_t OB_BOR); +void FLASH_OB_BootConfig(uint8_t OB_BOOT); +FLASH_Status FLASH_OB_Launch(void); +uint8_t FLASH_OB_GetUser(void); +uint16_t FLASH_OB_GetWRP(void); +uint16_t FLASH_OB_GetWRP1(void); +uint16_t FLASH_OB_GetPCROP(void); +uint16_t FLASH_OB_GetPCROP1(void); +FlagStatus FLASH_OB_GetRDP(void); +uint8_t FLASH_OB_GetBOR(void); + +/* Interrupts and flags management functions **********************************/ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_FLASH_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h index 9035cb886..8ac175aed 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h @@ -1,103 +1,103 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash_ramfunc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief Header file of FLASH RAMFUNC driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FLASH_RAMFUNC_H -#define __STM32F4xx_FLASH_RAMFUNC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH RAMFUNC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC void - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc void - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC void __attribute__((section(".RamFunc"))) - -#endif -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState); -__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState); - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_FLASH_RAMFUNC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f4xx_flash_ramfunc.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief Header file of FLASH RAMFUNC driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_FLASH_RAMFUNC_H +#define __STM32F4xx_FLASH_RAMFUNC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH RAMFUNC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC void + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc void + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC void __attribute__((section(".RamFunc"))) + +#endif +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState); +__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState); + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_FLASH_RAMFUNC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h index a2157f4d0..d071b1ab5 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h @@ -1,1143 +1,1143 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fmc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the FMC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FMC_H -#define __STM32F4xx_FMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FMC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ -typedef struct -{ - uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 15. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 1 and 15. - @note This parameter is not used with synchronous NOR Flash memories.*/ - - uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 1 and 255. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 15. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 15 in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ -}FMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FMC NOR/SRAM Init structure definition - */ -typedef struct -{ - uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ - - uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ - - uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FMC_Memory_Type */ - - uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ - - uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ - - uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ - - uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FMC_Wrap_Mode */ - - uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ - - uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ - - uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ - - uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ - - uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ - - uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ - - uint32_t FMC_ContinousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ - - - FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/ - - FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/ -}FMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FMC NAND and PCCARD Banks - */ -typedef struct -{ - uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 255.*/ - - uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0 and 255 */ - - uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command de-assertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0 and 255 */ - - uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0 and 255 */ -}FMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FMC NAND Init structure definition - */ -typedef struct -{ - uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FMC_NAND_Bank */ - - uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FMC_Wait_feature */ - - uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FMC_NAND_Data_Width */ - - uint32_t FMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FMC_ECC */ - - uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FMC_ECC_Page_Size */ - - uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 255. */ - - uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0 and 255 */ - - FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ - - FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ -}FMC_NANDInitTypeDef; - -/** - * @brief FMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FMC_Wait_feature */ - - uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 255. */ - - uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0 and 255 */ - - - FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ - - FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ - - FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */ -}FMC_PCCARDInitTypeDef; - -/** - * @brief Timing parameters for FMC SDRAM Banks - */ - -typedef struct -{ - uint32_t FMC_LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and - an active or Refresh command in number of memory clock cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to - issuing the Activate command in number of memory clock cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock - cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command - and the delay between two consecutive Refresh commands in number of - memory clock cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_RPDelay; /*!< Defines the delay between a Precharge Command and an other command - in number of memory clock cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command - in number of memory clock cycles. - This parameter can be a value between 1 and 16. */ - -}FMC_SDRAMTimingInitTypeDef; - -/** - * @brief Command parameters for FMC SDRAM Banks - */ - - -typedef struct -{ - uint32_t FMC_CommandMode; /*!< Defines the command issued to the SDRAM device. - This parameter can be a value of @ref FMC_Command_Mode. */ - - uint32_t FMC_CommandTarget; /*!< Defines which bank (1 or 2) the command will be issued to. - This parameter can be a value of @ref FMC_Command_Target. */ - - uint32_t FMC_AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued - in auto refresh mode. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ - -}FMC_SDRAMCommandTypeDef; - -/** - * @brief FMC SDRAM Init structure definition - */ - -typedef struct -{ - uint32_t FMC_Bank; /*!< Specifies the SDRAM memory bank that will be used. - This parameter can be a value of @ref FMC_SDRAM_Bank */ - - uint32_t FMC_ColumnBitsNumber; /*!< Defines the number of bits of column address. - This parameter can be a value of @ref FMC_ColumnBits_Number. */ - - uint32_t FMC_RowBitsNumber; /*!< Defines the number of bits of column address.. - This parameter can be a value of @ref FMC_RowBits_Number. */ - - uint32_t FMC_SDMemoryDataWidth; /*!< Defines the memory device width. - This parameter can be a value of @ref FMC_SDMemory_Data_Width. */ - - uint32_t FMC_InternalBankNumber; /*!< Defines the number of bits of column address. - This parameter can be of @ref FMC_InternalBank_Number. */ - - uint32_t FMC_CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. - This parameter can be a value of @ref FMC_CAS_Latency. */ - - uint32_t FMC_WriteProtection; /*!< Enables the SDRAM bank to be accessed in write mode. - This parameter can be a value of @ref FMC_Write_Protection. */ - - uint32_t FMC_SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM Banks and they allow to disable - the clock before changing frequency. - This parameter can be a value of @ref FMC_SDClock_Period. */ - - uint32_t FMC_ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands - during the CAS latency and stores data in the Read FIFO. - This parameter can be a value of @ref FMC_Read_Burst. */ - - uint32_t FMC_ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. - This parameter can be a value of @ref FMC_ReadPipe_Delay. */ - - FMC_SDRAMTimingInitTypeDef* FMC_SDRAMTimingStruct; /*!< Timing Parameters for write and read access*/ - -}FMC_SDRAMInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FMC_Exported_Constants - * @{ - */ - -/** @defgroup FMC_NORSRAM_Bank - * @{ - */ -#define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) - -#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \ - ((BANK) == FMC_Bank1_NORSRAM2) || \ - ((BANK) == FMC_Bank1_NORSRAM3) || \ - ((BANK) == FMC_Bank1_NORSRAM4)) -/** - * @} - */ - -/** @defgroup FMC_NAND_Bank - * @{ - */ -#define FMC_Bank2_NAND ((uint32_t)0x00000010) -#define FMC_Bank3_NAND ((uint32_t)0x00000100) - -#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ - ((BANK) == FMC_Bank3_NAND)) -/** - * @} - */ - -/** @defgroup FMC_PCCARD_Bank - * @{ - */ -#define FMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Bank - * @{ - */ -#define FMC_Bank1_SDRAM ((uint32_t)0x00000000) -#define FMC_Bank2_SDRAM ((uint32_t)0x00000001) - -#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_Bank1_SDRAM) || \ - ((BANK) == FMC_Bank2_SDRAM)) - -/** - * @} - */ - - -/** @defgroup FMC_NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FMC_DataAddressMux_Enable ((uint32_t)0x00000002) - -#define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \ - ((MUX) == FMC_DataAddressMux_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Memory_Type - * @{ - */ - -#define FMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FMC_MemoryType_NOR ((uint32_t)0x00000008) - -#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \ - ((MEMORY) == FMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FMC_MemoryType_NOR)) -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_Data_Width - * @{ - */ - -#define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define FMC_NORSRAM_MemoryDataWidth_32b ((uint32_t)0x00000020) - -#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \ - ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b) || \ - ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_32b)) -/** - * @} - */ - -/** @defgroup FMC_Burst_Access_Mode - * @{ - */ - -#define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100) - -#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \ - ((STATE) == FMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FMC_AsynchronousWait - * @{ - */ -#define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000) - -#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \ - ((STATE) == FMC_AsynchronousWait_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Wait_Signal_Polarity - * @{ - */ -#define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200) - -#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FMC_WaitSignalPolarity_High)) -/** - * @} - */ - -/** @defgroup FMC_Wrap_Mode - * @{ - */ -#define FMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FMC_WrapMode_Enable ((uint32_t)0x00000400) - -#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \ - ((MODE) == FMC_WrapMode_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Wait_Timing - * @{ - */ -#define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) - -#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FMC_WaitSignalActive_DuringWaitState)) -/** - * @} - */ - -/** @defgroup FMC_Write_Operation - * @{ - */ -#define FMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FMC_WriteOperation_Enable ((uint32_t)0x00001000) - -#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \ - ((OPERATION) == FMC_WriteOperation_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Wait_Signal - * @{ - */ -#define FMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FMC_WaitSignal_Enable ((uint32_t)0x00002000) - -#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \ - ((SIGNAL) == FMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Extended_Mode - * @{ - */ -#define FMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \ - ((MODE) == FMC_ExtendedMode_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Write_Burst - * @{ - */ - -#define FMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FMC_WriteBurst_Enable ((uint32_t)0x00080000) - -#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \ - ((BURST) == FMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Continous_Clock - * @{ - */ - -#define FMC_CClock_SyncOnly ((uint32_t)0x00000000) -#define FMC_CClock_SyncAsync ((uint32_t)0x00100000) - -#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \ - ((CCLOCK) == FMC_CClock_SyncAsync)) -/** - * @} - */ - -/** @defgroup FMC_Address_Setup_Time - * @{ - */ -#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15) -/** - * @} - */ - -/** @defgroup FMC_Address_Hold_Time - * @{ - */ -#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15)) -/** - * @} - */ - -/** @defgroup FMC_Data_Setup_Time - * @{ - */ -#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255)) -/** - * @} - */ - -/** @defgroup FMC_Bus_Turn_around_Duration - * @{ - */ -#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15) -/** - * @} - */ - -/** @defgroup FMC_CLK_Division - * @{ - */ -#define IS_FMC_CLK_DIV(DIV) (((DIV) > 0) && ((DIV) <= 15)) -/** - * @} - */ - -/** @defgroup FMC_Data_Latency - * @{ - */ -#define IS_FMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 15) -/** - * @} - */ - -/** @defgroup FMC_Access_Mode - * @{ - */ -#define FMC_AccessMode_A ((uint32_t)0x00000000) -#define FMC_AccessMode_B ((uint32_t)0x10000000) -#define FMC_AccessMode_C ((uint32_t)0x20000000) -#define FMC_AccessMode_D ((uint32_t)0x30000000) - -#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \ - ((MODE) == FMC_AccessMode_B) || \ - ((MODE) == FMC_AccessMode_C) || \ - ((MODE) == FMC_AccessMode_D)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FMC_Wait_feature - * @{ - */ -#define FMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FMC_Waitfeature_Enable ((uint32_t)0x00000002) - -#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \ - ((FEATURE) == FMC_Waitfeature_Enable)) -/** - * @} - */ - -/** @defgroup FMC_NAND_Data_Width - * @{ - */ -#define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010) - -#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \ - ((WIDTH) == FMC_NAND_MemoryDataWidth_16b)) -/** - * @} - */ - -/** @defgroup FMC_ECC - * @{ - */ -#define FMC_ECC_Disable ((uint32_t)0x00000000) -#define FMC_ECC_Enable ((uint32_t)0x00000040) - -#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \ - ((STATE) == FMC_ECC_Enable)) -/** - * @} - */ - -/** @defgroup FMC_ECC_Page_Size - * @{ - */ -#define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) - -#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FMC_ECCPageSize_8192Bytes)) -/** - * @} - */ - -/** @defgroup FMC_TCLR_Setup_Time - * @{ - */ -#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** @defgroup FMC_TAR_Setup_Time - * @{ - */ -#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Setup_Time - * @{ - */ -#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Wait_Setup_Time - * @{ - */ -#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Hold_Setup_Time - * @{ - */ -#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** @defgroup FMC_HiZ_Setup_Time - * @{ - */ -#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup FMC_NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FMC_ColumnBits_Number - * @{ - */ -#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) -#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) -#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) -#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) - -#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_ColumnBits_Number_8b) || \ - ((COLUMN) == FMC_ColumnBits_Number_9b) || \ - ((COLUMN) == FMC_ColumnBits_Number_10b) || \ - ((COLUMN) == FMC_ColumnBits_Number_11b)) - -/** - * @} - */ - -/** @defgroup FMC_RowBits_Number - * @{ - */ -#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) -#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) -#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) - -#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_RowBits_Number_11b) || \ - ((ROW) == FMC_RowBits_Number_12b) || \ - ((ROW) == FMC_RowBits_Number_13b)) - -/** - * @} - */ - -/** @defgroup FMC_SDMemory_Data_Width - * @{ - */ -#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) -#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) -#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) - -#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDMemory_Width_8b) || \ - ((WIDTH) == FMC_SDMemory_Width_16b) || \ - ((WIDTH) == FMC_SDMemory_Width_32b)) - -/** - * @} - */ - -/** @defgroup FMC_InternalBank_Number - * @{ - */ -#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) -#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) - -#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_InternalBank_Number_2) || \ - ((NUMBER) == FMC_InternalBank_Number_4)) - -/** - * @} - */ - - -/** @defgroup FMC_CAS_Latency - * @{ - */ -#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) -#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) -#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) - -#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_CAS_Latency_1) || \ - ((LATENCY) == FMC_CAS_Latency_2) || \ - ((LATENCY) == FMC_CAS_Latency_3)) - -/** - * @} - */ - -/** @defgroup FMC_Write_Protection - * @{ - */ -#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) -#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) - -#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_Write_Protection_Disable) || \ - ((WRITE) == FMC_Write_Protection_Enable)) - -/** - * @} - */ - - -/** @defgroup FMC_SDClock_Period - * @{ - */ -#define FMC_SDClock_Disable ((uint32_t)0x00000000) -#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) -#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) - -#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDClock_Disable) || \ - ((PERIOD) == FMC_SDClock_Period_2) || \ - ((PERIOD) == FMC_SDClock_Period_3)) - -/** - * @} - */ - -/** @defgroup FMC_Read_Burst - * @{ - */ -#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) -#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) - -#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_Read_Burst_Disable) || \ - ((RBURST) == FMC_Read_Burst_Enable)) - -/** - * @} - */ - -/** @defgroup FMC_ReadPipe_Delay - * @{ - */ -#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) -#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) -#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) - -#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_ReadPipe_Delay_0) || \ - ((DELAY) == FMC_ReadPipe_Delay_1) || \ - ((DELAY) == FMC_ReadPipe_Delay_2)) - -/** - * @} - */ - -/** @defgroup FMC_LoadToActive_Delay - * @{ - */ -#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_ExitSelfRefresh_Delay - * @{ - */ -#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_SelfRefresh_Time - * @{ - */ -#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_RowCycle_Delay - * @{ - */ -#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_Write_Recovery_Time - * @{ - */ -#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_RP_Delay - * @{ - */ -#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_RCD_Delay - * @{ - */ -#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) - -/** - * @} - */ - -/** @defgroup FMC_Command_Mode - * @{ - */ -#define FMC_Command_Mode_normal ((uint32_t)0x00000000) -#define FMC_Command_Mode_CLK_Enabled ((uint32_t)0x00000001) -#define FMC_Command_Mode_PALL ((uint32_t)0x00000002) -#define FMC_Command_Mode_AutoRefresh ((uint32_t)0x00000003) -#define FMC_Command_Mode_LoadMode ((uint32_t)0x00000004) -#define FMC_Command_Mode_Selfrefresh ((uint32_t)0x00000005) -#define FMC_Command_Mode_PowerDown ((uint32_t)0x00000006) - -#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_Command_Mode_normal) || \ - ((COMMAND) == FMC_Command_Mode_CLK_Enabled) || \ - ((COMMAND) == FMC_Command_Mode_PALL) || \ - ((COMMAND) == FMC_Command_Mode_AutoRefresh) || \ - ((COMMAND) == FMC_Command_Mode_LoadMode) || \ - ((COMMAND) == FMC_Command_Mode_Selfrefresh) || \ - ((COMMAND) == FMC_Command_Mode_PowerDown)) - -/** - * @} - */ - -/** @defgroup FMC_Command_Target - * @{ - */ -#define FMC_Command_Target_bank2 ((uint32_t)0x00000008) -#define FMC_Command_Target_bank1 ((uint32_t)0x00000010) -#define FMC_Command_Target_bank1_2 ((uint32_t)0x00000018) - -#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_Command_Target_bank1) || \ - ((TARGET) == FMC_Command_Target_bank2) || \ - ((TARGET) == FMC_Command_Target_bank1_2)) - -/** - * @} - */ - -/** @defgroup FMC_AutoRefresh_Number - * @{ - */ -#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16)) - -/** - * @} - */ - -/** @defgroup FMC_ModeRegister_Definition - * @{ - */ -#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191) - -/** - * @} - */ - - -/** @defgroup FMC_Mode_Status - * @{ - */ -#define FMC_NormalMode_Status ((uint32_t)0x00000000) -#define FMC_SelfRefreshMode_Status FMC_SDSR_MODES1_0 -#define FMC_PowerDownMode_Status FMC_SDSR_MODES1_1 - -#define IS_FMC_MODE_STATUS(STATUS) (((STATUS) == FMC_NormalMode_Status) || \ - ((STATUS) == FMC_SelfRefreshMode_Status) || \ - ((STATUS) == FMC_PowerDownMode_Status)) - - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_Interrupt_sources - * @{ - */ -#define FMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FMC_IT_Level ((uint32_t)0x00000010) -#define FMC_IT_FallingEdge ((uint32_t)0x00000020) -#define FMC_IT_Refresh ((uint32_t)0x00004000) - -#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \ - ((IT) == FMC_IT_Level) || \ - ((IT) == FMC_IT_FallingEdge) || \ - ((IT) == FMC_IT_Refresh)) - -#define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ - ((BANK) == FMC_Bank3_NAND) || \ - ((BANK) == FMC_Bank4_PCCARD) || \ - ((BANK) == FMC_Bank1_SDRAM) || \ - ((BANK) == FMC_Bank2_SDRAM)) -/** - * @} - */ - -/** @defgroup FMC_Flags - * @{ - */ -#define FMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FMC_FLAG_Level ((uint32_t)0x00000002) -#define FMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define FMC_FLAG_Refresh FMC_SDSR_RE -#define FMC_FLAG_Busy FMC_SDSR_BUSY - -#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \ - ((FLAG) == FMC_FLAG_Level) || \ - ((FLAG) == FMC_FLAG_FallingEdge) || \ - ((FLAG) == FMC_FLAG_FEMPT) || \ - ((FLAG) == FMC_FLAG_Refresh) || \ - ((FLAG) == FMC_SDSR_BUSY)) - -#define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ - ((BANK) == FMC_Bank3_NAND) || \ - ((BANK) == FMC_Bank4_PCCARD) || \ - ((BANK) == FMC_Bank1_SDRAM) || \ - ((BANK) == FMC_Bank2_SDRAM) || \ - ((BANK) == (FMC_Bank1_SDRAM | FMC_Bank2_SDRAM))) - -#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) - - -/** - * @} - */ - -/** @defgroup FMC_Refresh_count - * @{ - */ -#define IS_FMC_REFRESH_COUNT(COUNT) ((COUNT) <= 8191) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* NOR/SRAM Controller functions **********************************************/ -void FMC_NORSRAMDeInit(uint32_t FMC_Bank); -void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); -void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); -void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState); - -/* NAND Controller functions **************************************************/ -void FMC_NANDDeInit(uint32_t FMC_Bank); -void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); -void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); -void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState); -void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState); -uint32_t FMC_GetECC(uint32_t FMC_Bank); - -/* PCCARD Controller functions ************************************************/ -void FMC_PCCARDDeInit(void); -void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); -void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); -void FMC_PCCARDCmd(FunctionalState NewState); - -/* SDRAM Controller functions ************************************************/ -void FMC_SDRAMDeInit(uint32_t FMC_Bank); -void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct); -void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct); -void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct); -uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank); -void FMC_SetRefreshCount(uint32_t FMC_Count); -void FMC_SetAutoRefresh_Number(uint32_t FMC_Number); -void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState); -FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG); -void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG); -ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT); -void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_FMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_fmc.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the FMC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_FMC_H +#define __STM32F4xx_FMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FMC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ +typedef struct +{ + uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 1 and 15. + @note This parameter is not used with synchronous NOR Flash memories.*/ + + uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 1 and 255. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 15. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 15. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 15 in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FMC_Access_Mode */ +}FMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FMC NOR/SRAM Init structure definition + */ +typedef struct +{ + uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FMC_NORSRAM_Bank */ + + uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + + uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FMC_Memory_Type */ + + uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + + uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FMC_Burst_Access_Mode */ + + uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + + uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FMC_Wrap_Mode */ + + uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FMC_Wait_Timing */ + + uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ + + uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal */ + + uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FMC_Extended_Mode */ + + uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FMC_AsynchronousWait */ + + uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FMC_Write_Burst */ + + uint32_t FMC_ContinousClock; /*!< Enables or disables the FMC clock output to external memory devices. + This parameter is only enabled through the FMC_BCR1 register, and don't care + through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ + + + FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/ + + FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/ +}FMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FMC NAND and PCCARD Banks + */ +typedef struct +{ + uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 255.*/ + + uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0 and 255 */ + + uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command de-assertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0 and 255 */ + + uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0 and 255 */ +}FMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FMC NAND Init structure definition + */ +typedef struct +{ + uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FMC_NAND_Bank */ + + uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FMC_Wait_feature */ + + uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FMC_NAND_Data_Width */ + + uint32_t FMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FMC_ECC */ + + uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FMC_ECC_Page_Size */ + + uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 255. */ + + uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0 and 255 */ + + FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ + + FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ +}FMC_NANDInitTypeDef; + +/** + * @brief FMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FMC_Wait_feature */ + + uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 255. */ + + uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0 and 255 */ + + + FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ + + FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ + + FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */ +}FMC_PCCARDInitTypeDef; + +/** + * @brief Timing parameters for FMC SDRAM Banks + */ + +typedef struct +{ + uint32_t FMC_LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and + an active or Refresh command in number of memory clock cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to + issuing the Activate command in number of memory clock cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock + cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command + and the delay between two consecutive Refresh commands in number of + memory clock cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_RPDelay; /*!< Defines the delay between a Precharge Command and an other command + in number of memory clock cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command + in number of memory clock cycles. + This parameter can be a value between 1 and 16. */ + +}FMC_SDRAMTimingInitTypeDef; + +/** + * @brief Command parameters for FMC SDRAM Banks + */ + + +typedef struct +{ + uint32_t FMC_CommandMode; /*!< Defines the command issued to the SDRAM device. + This parameter can be a value of @ref FMC_Command_Mode. */ + + uint32_t FMC_CommandTarget; /*!< Defines which bank (1 or 2) the command will be issued to. + This parameter can be a value of @ref FMC_Command_Target. */ + + uint32_t FMC_AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued + in auto refresh mode. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ + +}FMC_SDRAMCommandTypeDef; + +/** + * @brief FMC SDRAM Init structure definition + */ + +typedef struct +{ + uint32_t FMC_Bank; /*!< Specifies the SDRAM memory bank that will be used. + This parameter can be a value of @ref FMC_SDRAM_Bank */ + + uint32_t FMC_ColumnBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_ColumnBits_Number. */ + + uint32_t FMC_RowBitsNumber; /*!< Defines the number of bits of column address.. + This parameter can be a value of @ref FMC_RowBits_Number. */ + + uint32_t FMC_SDMemoryDataWidth; /*!< Defines the memory device width. + This parameter can be a value of @ref FMC_SDMemory_Data_Width. */ + + uint32_t FMC_InternalBankNumber; /*!< Defines the number of bits of column address. + This parameter can be of @ref FMC_InternalBank_Number. */ + + uint32_t FMC_CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. + This parameter can be a value of @ref FMC_CAS_Latency. */ + + uint32_t FMC_WriteProtection; /*!< Enables the SDRAM bank to be accessed in write mode. + This parameter can be a value of @ref FMC_Write_Protection. */ + + uint32_t FMC_SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM Banks and they allow to disable + the clock before changing frequency. + This parameter can be a value of @ref FMC_SDClock_Period. */ + + uint32_t FMC_ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands + during the CAS latency and stores data in the Read FIFO. + This parameter can be a value of @ref FMC_Read_Burst. */ + + uint32_t FMC_ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. + This parameter can be a value of @ref FMC_ReadPipe_Delay. */ + + FMC_SDRAMTimingInitTypeDef* FMC_SDRAMTimingStruct; /*!< Timing Parameters for write and read access*/ + +}FMC_SDRAMInitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FMC_Exported_Constants + * @{ + */ + +/** @defgroup FMC_NORSRAM_Bank + * @{ + */ +#define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) + +#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \ + ((BANK) == FMC_Bank1_NORSRAM2) || \ + ((BANK) == FMC_Bank1_NORSRAM3) || \ + ((BANK) == FMC_Bank1_NORSRAM4)) +/** + * @} + */ + +/** @defgroup FMC_NAND_Bank + * @{ + */ +#define FMC_Bank2_NAND ((uint32_t)0x00000010) +#define FMC_Bank3_NAND ((uint32_t)0x00000100) + +#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ + ((BANK) == FMC_Bank3_NAND)) +/** + * @} + */ + +/** @defgroup FMC_PCCARD_Bank + * @{ + */ +#define FMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Bank + * @{ + */ +#define FMC_Bank1_SDRAM ((uint32_t)0x00000000) +#define FMC_Bank2_SDRAM ((uint32_t)0x00000001) + +#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_Bank1_SDRAM) || \ + ((BANK) == FMC_Bank2_SDRAM)) + +/** + * @} + */ + + +/** @defgroup FMC_NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FMC_DataAddressMux_Enable ((uint32_t)0x00000002) + +#define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \ + ((MUX) == FMC_DataAddressMux_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Memory_Type + * @{ + */ + +#define FMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FMC_MemoryType_NOR ((uint32_t)0x00000008) + +#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \ + ((MEMORY) == FMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FMC_MemoryType_NOR)) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Data_Width + * @{ + */ + +#define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define FMC_NORSRAM_MemoryDataWidth_32b ((uint32_t)0x00000020) + +#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \ + ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b) || \ + ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_32b)) +/** + * @} + */ + +/** @defgroup FMC_Burst_Access_Mode + * @{ + */ + +#define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100) + +#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \ + ((STATE) == FMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FMC_AsynchronousWait + * @{ + */ +#define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000) + +#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \ + ((STATE) == FMC_AsynchronousWait_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal_Polarity + * @{ + */ +#define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200) + +#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FMC_WaitSignalPolarity_High)) +/** + * @} + */ + +/** @defgroup FMC_Wrap_Mode + * @{ + */ +#define FMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FMC_WrapMode_Enable ((uint32_t)0x00000400) + +#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \ + ((MODE) == FMC_WrapMode_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Wait_Timing + * @{ + */ +#define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) + +#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FMC_WaitSignalActive_DuringWaitState)) +/** + * @} + */ + +/** @defgroup FMC_Write_Operation + * @{ + */ +#define FMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FMC_WriteOperation_Enable ((uint32_t)0x00001000) + +#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \ + ((OPERATION) == FMC_WriteOperation_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal + * @{ + */ +#define FMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FMC_WaitSignal_Enable ((uint32_t)0x00002000) + +#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \ + ((SIGNAL) == FMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Extended_Mode + * @{ + */ +#define FMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \ + ((MODE) == FMC_ExtendedMode_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Write_Burst + * @{ + */ + +#define FMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FMC_WriteBurst_Enable ((uint32_t)0x00080000) + +#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \ + ((BURST) == FMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Continous_Clock + * @{ + */ + +#define FMC_CClock_SyncOnly ((uint32_t)0x00000000) +#define FMC_CClock_SyncAsync ((uint32_t)0x00100000) + +#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \ + ((CCLOCK) == FMC_CClock_SyncAsync)) +/** + * @} + */ + +/** @defgroup FMC_Address_Setup_Time + * @{ + */ +#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15) +/** + * @} + */ + +/** @defgroup FMC_Address_Hold_Time + * @{ + */ +#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15)) +/** + * @} + */ + +/** @defgroup FMC_Data_Setup_Time + * @{ + */ +#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255)) +/** + * @} + */ + +/** @defgroup FMC_Bus_Turn_around_Duration + * @{ + */ +#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15) +/** + * @} + */ + +/** @defgroup FMC_CLK_Division + * @{ + */ +#define IS_FMC_CLK_DIV(DIV) (((DIV) > 0) && ((DIV) <= 15)) +/** + * @} + */ + +/** @defgroup FMC_Data_Latency + * @{ + */ +#define IS_FMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 15) +/** + * @} + */ + +/** @defgroup FMC_Access_Mode + * @{ + */ +#define FMC_AccessMode_A ((uint32_t)0x00000000) +#define FMC_AccessMode_B ((uint32_t)0x10000000) +#define FMC_AccessMode_C ((uint32_t)0x20000000) +#define FMC_AccessMode_D ((uint32_t)0x30000000) + +#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \ + ((MODE) == FMC_AccessMode_B) || \ + ((MODE) == FMC_AccessMode_C) || \ + ((MODE) == FMC_AccessMode_D)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FMC_Wait_feature + * @{ + */ +#define FMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FMC_Waitfeature_Enable ((uint32_t)0x00000002) + +#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \ + ((FEATURE) == FMC_Waitfeature_Enable)) +/** + * @} + */ + +/** @defgroup FMC_NAND_Data_Width + * @{ + */ +#define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010) + +#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \ + ((WIDTH) == FMC_NAND_MemoryDataWidth_16b)) +/** + * @} + */ + +/** @defgroup FMC_ECC + * @{ + */ +#define FMC_ECC_Disable ((uint32_t)0x00000000) +#define FMC_ECC_Enable ((uint32_t)0x00000040) + +#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \ + ((STATE) == FMC_ECC_Enable)) +/** + * @} + */ + +/** @defgroup FMC_ECC_Page_Size + * @{ + */ +#define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) + +#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FMC_ECCPageSize_8192Bytes)) +/** + * @} + */ + +/** @defgroup FMC_TCLR_Setup_Time + * @{ + */ +#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_TAR_Setup_Time + * @{ + */ +#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_Setup_Time + * @{ + */ +#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_Wait_Setup_Time + * @{ + */ +#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_Hold_Setup_Time + * @{ + */ +#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_HiZ_Setup_Time + * @{ + */ +#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup FMC_NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FMC_ColumnBits_Number + * @{ + */ +#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) +#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) +#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) +#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) + +#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_ColumnBits_Number_8b) || \ + ((COLUMN) == FMC_ColumnBits_Number_9b) || \ + ((COLUMN) == FMC_ColumnBits_Number_10b) || \ + ((COLUMN) == FMC_ColumnBits_Number_11b)) + +/** + * @} + */ + +/** @defgroup FMC_RowBits_Number + * @{ + */ +#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) +#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) +#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) + +#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_RowBits_Number_11b) || \ + ((ROW) == FMC_RowBits_Number_12b) || \ + ((ROW) == FMC_RowBits_Number_13b)) + +/** + * @} + */ + +/** @defgroup FMC_SDMemory_Data_Width + * @{ + */ +#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) +#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) +#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) + +#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDMemory_Width_8b) || \ + ((WIDTH) == FMC_SDMemory_Width_16b) || \ + ((WIDTH) == FMC_SDMemory_Width_32b)) + +/** + * @} + */ + +/** @defgroup FMC_InternalBank_Number + * @{ + */ +#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) +#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) + +#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_InternalBank_Number_2) || \ + ((NUMBER) == FMC_InternalBank_Number_4)) + +/** + * @} + */ + + +/** @defgroup FMC_CAS_Latency + * @{ + */ +#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) +#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) +#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) + +#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_CAS_Latency_1) || \ + ((LATENCY) == FMC_CAS_Latency_2) || \ + ((LATENCY) == FMC_CAS_Latency_3)) + +/** + * @} + */ + +/** @defgroup FMC_Write_Protection + * @{ + */ +#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) +#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) + +#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_Write_Protection_Disable) || \ + ((WRITE) == FMC_Write_Protection_Enable)) + +/** + * @} + */ + + +/** @defgroup FMC_SDClock_Period + * @{ + */ +#define FMC_SDClock_Disable ((uint32_t)0x00000000) +#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) +#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) + +#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDClock_Disable) || \ + ((PERIOD) == FMC_SDClock_Period_2) || \ + ((PERIOD) == FMC_SDClock_Period_3)) + +/** + * @} + */ + +/** @defgroup FMC_Read_Burst + * @{ + */ +#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) +#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) + +#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_Read_Burst_Disable) || \ + ((RBURST) == FMC_Read_Burst_Enable)) + +/** + * @} + */ + +/** @defgroup FMC_ReadPipe_Delay + * @{ + */ +#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) +#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) +#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) + +#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_ReadPipe_Delay_0) || \ + ((DELAY) == FMC_ReadPipe_Delay_1) || \ + ((DELAY) == FMC_ReadPipe_Delay_2)) + +/** + * @} + */ + +/** @defgroup FMC_LoadToActive_Delay + * @{ + */ +#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_ExitSelfRefresh_Delay + * @{ + */ +#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SelfRefresh_Time + * @{ + */ +#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_RowCycle_Delay + * @{ + */ +#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_Write_Recovery_Time + * @{ + */ +#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_RP_Delay + * @{ + */ +#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_RCD_Delay + * @{ + */ +#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) + +/** + * @} + */ + +/** @defgroup FMC_Command_Mode + * @{ + */ +#define FMC_Command_Mode_normal ((uint32_t)0x00000000) +#define FMC_Command_Mode_CLK_Enabled ((uint32_t)0x00000001) +#define FMC_Command_Mode_PALL ((uint32_t)0x00000002) +#define FMC_Command_Mode_AutoRefresh ((uint32_t)0x00000003) +#define FMC_Command_Mode_LoadMode ((uint32_t)0x00000004) +#define FMC_Command_Mode_Selfrefresh ((uint32_t)0x00000005) +#define FMC_Command_Mode_PowerDown ((uint32_t)0x00000006) + +#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_Command_Mode_normal) || \ + ((COMMAND) == FMC_Command_Mode_CLK_Enabled) || \ + ((COMMAND) == FMC_Command_Mode_PALL) || \ + ((COMMAND) == FMC_Command_Mode_AutoRefresh) || \ + ((COMMAND) == FMC_Command_Mode_LoadMode) || \ + ((COMMAND) == FMC_Command_Mode_Selfrefresh) || \ + ((COMMAND) == FMC_Command_Mode_PowerDown)) + +/** + * @} + */ + +/** @defgroup FMC_Command_Target + * @{ + */ +#define FMC_Command_Target_bank2 ((uint32_t)0x00000008) +#define FMC_Command_Target_bank1 ((uint32_t)0x00000010) +#define FMC_Command_Target_bank1_2 ((uint32_t)0x00000018) + +#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_Command_Target_bank1) || \ + ((TARGET) == FMC_Command_Target_bank2) || \ + ((TARGET) == FMC_Command_Target_bank1_2)) + +/** + * @} + */ + +/** @defgroup FMC_AutoRefresh_Number + * @{ + */ +#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16)) + +/** + * @} + */ + +/** @defgroup FMC_ModeRegister_Definition + * @{ + */ +#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191) + +/** + * @} + */ + + +/** @defgroup FMC_Mode_Status + * @{ + */ +#define FMC_NormalMode_Status ((uint32_t)0x00000000) +#define FMC_SelfRefreshMode_Status FMC_SDSR_MODES1_0 +#define FMC_PowerDownMode_Status FMC_SDSR_MODES1_1 + +#define IS_FMC_MODE_STATUS(STATUS) (((STATUS) == FMC_NormalMode_Status) || \ + ((STATUS) == FMC_SelfRefreshMode_Status) || \ + ((STATUS) == FMC_PowerDownMode_Status)) + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_Interrupt_sources + * @{ + */ +#define FMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FMC_IT_Level ((uint32_t)0x00000010) +#define FMC_IT_FallingEdge ((uint32_t)0x00000020) +#define FMC_IT_Refresh ((uint32_t)0x00004000) + +#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \ + ((IT) == FMC_IT_Level) || \ + ((IT) == FMC_IT_FallingEdge) || \ + ((IT) == FMC_IT_Refresh)) + +#define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ + ((BANK) == FMC_Bank3_NAND) || \ + ((BANK) == FMC_Bank4_PCCARD) || \ + ((BANK) == FMC_Bank1_SDRAM) || \ + ((BANK) == FMC_Bank2_SDRAM)) +/** + * @} + */ + +/** @defgroup FMC_Flags + * @{ + */ +#define FMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FMC_FLAG_Level ((uint32_t)0x00000002) +#define FMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define FMC_FLAG_Refresh FMC_SDSR_RE +#define FMC_FLAG_Busy FMC_SDSR_BUSY + +#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \ + ((FLAG) == FMC_FLAG_Level) || \ + ((FLAG) == FMC_FLAG_FallingEdge) || \ + ((FLAG) == FMC_FLAG_FEMPT) || \ + ((FLAG) == FMC_FLAG_Refresh) || \ + ((FLAG) == FMC_SDSR_BUSY)) + +#define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ + ((BANK) == FMC_Bank3_NAND) || \ + ((BANK) == FMC_Bank4_PCCARD) || \ + ((BANK) == FMC_Bank1_SDRAM) || \ + ((BANK) == FMC_Bank2_SDRAM) || \ + ((BANK) == (FMC_Bank1_SDRAM | FMC_Bank2_SDRAM))) + +#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) + + +/** + * @} + */ + +/** @defgroup FMC_Refresh_count + * @{ + */ +#define IS_FMC_REFRESH_COUNT(COUNT) ((COUNT) <= 8191) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* NOR/SRAM Controller functions **********************************************/ +void FMC_NORSRAMDeInit(uint32_t FMC_Bank); +void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); +void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); +void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState); + +/* NAND Controller functions **************************************************/ +void FMC_NANDDeInit(uint32_t FMC_Bank); +void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); +void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); +void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState); +void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState); +uint32_t FMC_GetECC(uint32_t FMC_Bank); + +/* PCCARD Controller functions ************************************************/ +void FMC_PCCARDDeInit(void); +void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); +void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); +void FMC_PCCARDCmd(FunctionalState NewState); + +/* SDRAM Controller functions ************************************************/ +void FMC_SDRAMDeInit(uint32_t FMC_Bank); +void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct); +void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct); +void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct); +uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank); +void FMC_SetRefreshCount(uint32_t FMC_Count); +void FMC_SetAutoRefresh_Number(uint32_t FMC_Number); +void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState); +FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG); +void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG); +ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT); +void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_FMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h index fb819047c..deb0b0d24 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h @@ -1,675 +1,675 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fsmc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the FSMC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FSMC_H -#define __STM32F4xx_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FSMC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FSMC NOR/SRAM Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the data bus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/ -}FSMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FSMC NAND and PCCARD Banks - */ -typedef struct -{ - uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command de-assertion - for NAND Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - data bus is kept in HiZ after the start of a NAND Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FSMC NAND Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - -/** - * @brief FSMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ -}FSMC_PCCARDInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FSMC_Exported_Constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank - * @{ - */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Bank - * @{ - */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) -#define FSMC_Bank3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Bank - * @{ - */ -#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ - ((BANK) == FSMC_Bank1_NORSRAM2) || \ - ((BANK) == FSMC_Bank1_NORSRAM3) || \ - ((BANK) == FSMC_Bank1_NORSRAM4)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND)) - -#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -/** @defgroup FSMC_NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) -#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ - ((MUX) == FSMC_DataAddressMux_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type - * @{ - */ - -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) -#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ - ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FSMC_MemoryType_NOR)) -/** - * @} - */ - -/** @defgroup FSMC_Data_Width - * @{ - */ - -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ - ((WIDTH) == FSMC_MemoryDataWidth_16b)) -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode - * @{ - */ - -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) -#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ - ((STATE) == FSMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_AsynchronousWait - * @{ - */ -#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) -#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ - ((STATE) == FSMC_AsynchronousWait_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity - * @{ - */ -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) -#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FSMC_WaitSignalPolarity_High)) -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode - * @{ - */ -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) -#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ - ((MODE) == FSMC_WrapMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing - * @{ - */ -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation - * @{ - */ -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) -#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ - ((OPERATION) == FSMC_WriteOperation_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal - * @{ - */ -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) -#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ - ((SIGNAL) == FSMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode - * @{ - */ -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ - ((MODE) == FSMC_ExtendedMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst - * @{ - */ - -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) -#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ - ((BURST) == FSMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time - * @{ - */ -#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time - * @{ - */ -#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time - * @{ - */ -#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration - * @{ - */ -#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division - * @{ - */ -#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency - * @{ - */ -#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode - * @{ - */ -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) -#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ - ((MODE) == FSMC_AccessMode_B) || \ - ((MODE) == FSMC_AccessMode_C) || \ - ((MODE) == FSMC_AccessMode_D)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FSMC_NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FSMC_Wait_feature - * @{ - */ -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ - ((FEATURE) == FSMC_Waitfeature_Enable)) -/** - * @} - */ - - -/** @defgroup FSMC_ECC - * @{ - */ -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ - ((STATE) == FSMC_ECC_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size - * @{ - */ -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_8192Bytes)) -/** - * @} - */ - -/** @defgroup FSMC_TCLR_Setup_Time - * @{ - */ -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time - * @{ - */ -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time - * @{ - */ -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time - * @{ - */ -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time - * @{ - */ -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time - * @{ - */ -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Interrupt_sources - * @{ - */ -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) -#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ - ((IT) == FSMC_IT_Level) || \ - ((IT) == FSMC_IT_FallingEdge)) -/** - * @} - */ - -/** @defgroup FSMC_Flags - * @{ - */ -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ - ((FLAG) == FSMC_FLAG_Level) || \ - ((FLAG) == FSMC_FLAG_FallingEdge) || \ - ((FLAG) == FSMC_FLAG_FEMPT)) - -#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* NOR/SRAM Controller functions **********************************************/ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); - -/* NAND Controller functions **************************************************/ -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); - -/* PCCARD Controller functions ************************************************/ -void FSMC_PCCARDDeInit(void); -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDCmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_FSMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_fsmc.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the FSMC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_FSMC_H +#define __STM32F4xx_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note This parameter is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the data bus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ +typedef struct +{ + uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command de-assertion + for NAND Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + data bus is kept in HiZ after the start of a NAND Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank + * @{ + */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Bank + * @{ + */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FSMC_PCCARD_Bank + * @{ + */ +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +/** @defgroup FSMC_NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_AsynchronousWait + * @{ + */ +#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) +#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ + ((STATE) == FSMC_AsynchronousWait_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) +/** + * @} + */ + + +/** @defgroup FSMC_ECC + * @{ + */ +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* NOR/SRAM Controller functions **********************************************/ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); + +/* NAND Controller functions **************************************************/ +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); + +/* PCCARD Controller functions ************************************************/ +void FSMC_PCCARDDeInit(void); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_PCCARDCmd(FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h index a96e6c084..e7a9456ed 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h @@ -1,502 +1,502 @@ -/** - ****************************************************************************** - * @file stm32f4xx_gpio.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the GPIO firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_GPIO_H -#define __STM32F4xx_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG) || \ - ((PERIPH) == GPIOH) || \ - ((PERIPH) == GPIOI) || \ - ((PERIPH) == GPIOJ) || \ - ((PERIPH) == GPIOK)) - -/** - * @brief GPIO Configuration Mode enumeration - */ -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ - GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ -}GPIOMode_TypeDef; -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ - ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) - -/** - * @brief GPIO Output type enumeration - */ -typedef enum -{ - GPIO_OType_PP = 0x00, - GPIO_OType_OD = 0x01 -}GPIOOType_TypeDef; -#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) - - -/** - * @brief GPIO Output Maximum frequency enumeration - */ -typedef enum -{ - GPIO_Low_Speed = 0x00, /*!< Low speed */ - GPIO_Medium_Speed = 0x01, /*!< Medium speed */ - GPIO_Fast_Speed = 0x02, /*!< Fast speed */ - GPIO_High_Speed = 0x03 /*!< High speed */ -}GPIOSpeed_TypeDef; - -/* Add legacy definition */ -#define GPIO_Speed_2MHz GPIO_Low_Speed -#define GPIO_Speed_25MHz GPIO_Medium_Speed -#define GPIO_Speed_50MHz GPIO_Fast_Speed -#define GPIO_Speed_100MHz GPIO_High_Speed - -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \ - ((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed)) - -/** - * @brief GPIO Configuration PullUp PullDown enumeration - */ -typedef enum -{ - GPIO_PuPd_NOPULL = 0x00, - GPIO_PuPd_UP = 0x01, - GPIO_PuPd_DOWN = 0x02 -}GPIOPuPd_TypeDef; -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ - ((PUPD) == GPIO_PuPd_DOWN)) - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIOOType_TypeDef */ - - GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIOPuPd_TypeDef */ -}GPIO_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ -#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) -/** - * @} - */ - - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) -/** - * @} - */ - -/** @defgroup GPIO_Alternat_function_selection_define - * @{ - */ -/** - * @brief AF 0 selection - */ -#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */ -#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ -#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ -#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F411xE Devices) */ -#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */ -#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F411xE Devices) */ -#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */ - -/** - * @brief AF 7 selection Legacy - */ -#define GPIO_AF_I2S3ext GPIO_AF7_SPI3 - -/** - * @brief AF 8 selection - */ -#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ -#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ - -#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */ -#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#if defined (STM32F40_41xxx) -#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ - -#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#if defined (STM32F40_41xxx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ - ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ - ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ - ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC)) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F401xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4)) -#endif /* STM32F401xx */ - -#if defined (STM32F411xE) -#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14)) -#endif /* STM32F411xE */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ - ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ - ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ - ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \ - ((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \ - ((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \ - ((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \ - ((AF) == GPIO_AF_LTDC)) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -/** - * @} - */ - -/** @defgroup GPIO_Legacy - * @{ - */ - -#define GPIO_Mode_AIN GPIO_Mode_AN - -#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS -#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS -#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the GPIO configuration to the default reset state ****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); - -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Read and Write functions **********************************************/ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Alternate functions configuration function ****************************/ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_GPIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_gpio.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the GPIO firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_GPIO_H +#define __STM32F4xx_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG) || \ + ((PERIPH) == GPIOH) || \ + ((PERIPH) == GPIOI) || \ + ((PERIPH) == GPIOJ) || \ + ((PERIPH) == GPIOK)) + +/** + * @brief GPIO Configuration Mode enumeration + */ +typedef enum +{ + GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ + GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ + GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ +}GPIOMode_TypeDef; +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ + ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) + +/** + * @brief GPIO Output type enumeration + */ +typedef enum +{ + GPIO_OType_PP = 0x00, + GPIO_OType_OD = 0x01 +}GPIOOType_TypeDef; +#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) + + +/** + * @brief GPIO Output Maximum frequency enumeration + */ +typedef enum +{ + GPIO_Low_Speed = 0x00, /*!< Low speed */ + GPIO_Medium_Speed = 0x01, /*!< Medium speed */ + GPIO_Fast_Speed = 0x02, /*!< Fast speed */ + GPIO_High_Speed = 0x03 /*!< High speed */ +}GPIOSpeed_TypeDef; + +/* Add legacy definition */ +#define GPIO_Speed_2MHz GPIO_Low_Speed +#define GPIO_Speed_25MHz GPIO_Medium_Speed +#define GPIO_Speed_50MHz GPIO_Fast_Speed +#define GPIO_Speed_100MHz GPIO_High_Speed + +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \ + ((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed)) + +/** + * @brief GPIO Configuration PullUp PullDown enumeration + */ +typedef enum +{ + GPIO_PuPd_NOPULL = 0x00, + GPIO_PuPd_UP = 0x01, + GPIO_PuPd_DOWN = 0x02 +}GPIOPuPd_TypeDef; +#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ + ((PUPD) == GPIO_PuPd_DOWN)) + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIOOType_TypeDef */ + + GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIOPuPd_TypeDef */ +}GPIO_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ +#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) +/** + * @} + */ + + +/** @defgroup GPIO_Pin_sources + * @{ + */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) +/** + * @} + */ + +/** @defgroup GPIO_Alternat_function_selection_define + * @{ + */ +/** + * @brief AF 0 selection + */ +#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */ +#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F411xE Devices) */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F411xE Devices) */ +#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */ + +/** + * @brief AF 7 selection Legacy + */ +#define GPIO_AF_I2S3ext GPIO_AF7_SPI3 + +/** + * @brief AF 8 selection + */ +#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#if defined (STM32F40_41xxx) +#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ + +#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#if defined (STM32F40_41xxx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ + ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ + ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ + ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC)) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F401xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4)) +#endif /* STM32F401xx */ + +#if defined (STM32F411xE) +#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14)) +#endif /* STM32F411xE */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ + ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ + ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ + ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \ + ((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \ + ((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \ + ((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \ + ((AF) == GPIO_AF_LTDC)) +#endif /* STM32F427_437xx || STM32F429_439xx */ + +/** + * @} + */ + +/** @defgroup GPIO_Legacy + * @{ + */ + +#define GPIO_Mode_AIN GPIO_Mode_AN + +#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS +#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS +#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the GPIO configuration to the default reset state ****/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); + +/* Initialization and Configuration functions *********************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Read and Write functions **********************************************/ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Alternate functions configuration function ****************************/ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_GPIO_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h index d9522931d..6994e1b9f 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h @@ -1,257 +1,257 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hash.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the HASH - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HASH_H -#define __STM32F4xx_HASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup HASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HASH Init structure definition - */ -typedef struct -{ - uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter - can be a value of @ref HASH_Algo_Selection */ - uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value - of @ref HASH_processor_Algorithm_Mode */ - uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or - bit string. This parameter can be a value of - @ref HASH_Data_Type */ - uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter - can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ -}HASH_InitTypeDef; - -/** - * @brief HASH message digest result structure definition - */ -typedef struct -{ - uint32_t Data[8]; /*!< Message digest result : 8x 32bit wors for SHA-256, - 7x 32bit wors for SHA-224, - 5x 32bit words for SHA-1 or - 4x 32bit words for MD5 */ -} HASH_MsgDigest; - -/** - * @brief HASH context swapping structure definition - */ -typedef struct -{ - uint32_t HASH_IMR; - uint32_t HASH_STR; - uint32_t HASH_CR; - uint32_t HASH_CSR[54]; -}HASH_Context; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HASH_Exported_Constants - * @{ - */ - -/** @defgroup HASH_Algo_Selection - * @{ - */ -#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */ -#define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ -#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ -#define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ - -#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ - ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \ - ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \ - ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) -/** - * @} - */ - -/** @defgroup HASH_processor_Algorithm_Mode - * @{ - */ -#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ -#define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ - -#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ - ((ALGOMODE) == HASH_AlgoMode_HMAC)) -/** - * @} - */ - -/** @defgroup HASH_Data_Type - * @{ - */ -#define HASH_DataType_32b ((uint32_t)0x0000) /*!< 32-bit data. No swapping */ -#define HASH_DataType_16b HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ -#define HASH_DataType_8b HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ -#define HASH_DataType_1b HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ - -#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ - ((DATATYPE) == HASH_DataType_16b)|| \ - ((DATATYPE) == HASH_DataType_8b) || \ - ((DATATYPE) == HASH_DataType_1b)) -/** - * @} - */ - -/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode - * @{ - */ -#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ -#define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */ - -#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ - ((KEYTYPE) == HASH_HMACKeyType_LongKey)) -/** - * @} - */ - -/** @defgroup Number_of_valid_bits_in_last_word_of_the_message - * @{ - */ -#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F) - -/** - * @} - */ - -/** @defgroup HASH_interrupts_definition - * @{ - */ -#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */ -#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */ - -#define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) - -/** - * @} - */ - -/** @defgroup HASH_flags_definition - * @{ - */ -#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */ -#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ -#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ -#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */ -#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */ - -#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ - ((FLAG) == HASH_FLAG_DCIS) || \ - ((FLAG) == HASH_FLAG_DMAS) || \ - ((FLAG) == HASH_FLAG_BUSY) || \ - ((FLAG) == HASH_FLAG_DINNE)) - -#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \ - ((FLAG) == HASH_FLAG_DCIS)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the HASH configuration to the default reset state ****/ -void HASH_DeInit(void); - -/* HASH Configuration function ************************************************/ -void HASH_Init(HASH_InitTypeDef* HASH_InitStruct); -void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct); -void HASH_Reset(void); - -/* HASH Message Digest generation functions ***********************************/ -void HASH_DataIn(uint32_t Data); -uint8_t HASH_GetInFIFOWordsNbr(void); -void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); -void HASH_StartDigest(void); -void HASH_AutoStartDigest(FunctionalState NewState); -void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); - -/* HASH Context swapping functions ********************************************/ -void HASH_SaveContext(HASH_Context* HASH_ContextSave); -void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); - -/* HASH DMA interface function ************************************************/ -void HASH_DMACmd(FunctionalState NewState); - -/* HASH Interrupts and flags management functions *****************************/ -void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState); -FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG); -void HASH_ClearFlag(uint32_t HASH_FLAG); -ITStatus HASH_GetITStatus(uint32_t HASH_IT); -void HASH_ClearITPendingBit(uint32_t HASH_IT); - -/* High Level SHA1 functions **************************************************/ -ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); -ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, - uint8_t *Input, uint32_t Ilen, - uint8_t Output[20]); - -/* High Level MD5 functions ***************************************************/ -ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); -ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, - uint8_t *Input, uint32_t Ilen, - uint8_t Output[16]); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_HASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_hash.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the HASH + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HASH_H +#define __STM32F4xx_HASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup HASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HASH Init structure definition + */ +typedef struct +{ + uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter + can be a value of @ref HASH_Algo_Selection */ + uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value + of @ref HASH_processor_Algorithm_Mode */ + uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or + bit string. This parameter can be a value of + @ref HASH_Data_Type */ + uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter + can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ +}HASH_InitTypeDef; + +/** + * @brief HASH message digest result structure definition + */ +typedef struct +{ + uint32_t Data[8]; /*!< Message digest result : 8x 32bit wors for SHA-256, + 7x 32bit wors for SHA-224, + 5x 32bit words for SHA-1 or + 4x 32bit words for MD5 */ +} HASH_MsgDigest; + +/** + * @brief HASH context swapping structure definition + */ +typedef struct +{ + uint32_t HASH_IMR; + uint32_t HASH_STR; + uint32_t HASH_CR; + uint32_t HASH_CSR[54]; +}HASH_Context; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HASH_Exported_Constants + * @{ + */ + +/** @defgroup HASH_Algo_Selection + * @{ + */ +#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */ +#define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ +#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ +#define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ + +#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ + ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \ + ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \ + ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) +/** + * @} + */ + +/** @defgroup HASH_processor_Algorithm_Mode + * @{ + */ +#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ +#define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ + +#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ + ((ALGOMODE) == HASH_AlgoMode_HMAC)) +/** + * @} + */ + +/** @defgroup HASH_Data_Type + * @{ + */ +#define HASH_DataType_32b ((uint32_t)0x0000) /*!< 32-bit data. No swapping */ +#define HASH_DataType_16b HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ +#define HASH_DataType_8b HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ +#define HASH_DataType_1b HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ + +#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ + ((DATATYPE) == HASH_DataType_16b)|| \ + ((DATATYPE) == HASH_DataType_8b) || \ + ((DATATYPE) == HASH_DataType_1b)) +/** + * @} + */ + +/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode + * @{ + */ +#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ +#define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */ + +#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ + ((KEYTYPE) == HASH_HMACKeyType_LongKey)) +/** + * @} + */ + +/** @defgroup Number_of_valid_bits_in_last_word_of_the_message + * @{ + */ +#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F) + +/** + * @} + */ + +/** @defgroup HASH_interrupts_definition + * @{ + */ +#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */ +#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */ + +#define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) + +/** + * @} + */ + +/** @defgroup HASH_flags_definition + * @{ + */ +#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */ +#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ +#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ +#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */ +#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */ + +#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ + ((FLAG) == HASH_FLAG_DCIS) || \ + ((FLAG) == HASH_FLAG_DMAS) || \ + ((FLAG) == HASH_FLAG_BUSY) || \ + ((FLAG) == HASH_FLAG_DINNE)) + +#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \ + ((FLAG) == HASH_FLAG_DCIS)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the HASH configuration to the default reset state ****/ +void HASH_DeInit(void); + +/* HASH Configuration function ************************************************/ +void HASH_Init(HASH_InitTypeDef* HASH_InitStruct); +void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct); +void HASH_Reset(void); + +/* HASH Message Digest generation functions ***********************************/ +void HASH_DataIn(uint32_t Data); +uint8_t HASH_GetInFIFOWordsNbr(void); +void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); +void HASH_StartDigest(void); +void HASH_AutoStartDigest(FunctionalState NewState); +void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); + +/* HASH Context swapping functions ********************************************/ +void HASH_SaveContext(HASH_Context* HASH_ContextSave); +void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); + +/* HASH DMA interface function ************************************************/ +void HASH_DMACmd(FunctionalState NewState); + +/* HASH Interrupts and flags management functions *****************************/ +void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState); +FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG); +void HASH_ClearFlag(uint32_t HASH_FLAG); +ITStatus HASH_GetITStatus(uint32_t HASH_IT); +void HASH_ClearITPendingBit(uint32_t HASH_IT); + +/* High Level SHA1 functions **************************************************/ +ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); +ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, + uint8_t *Input, uint32_t Ilen, + uint8_t Output[20]); + +/* High Level MD5 functions ***************************************************/ +ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); +ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, + uint8_t *Input, uint32_t Ilen, + uint8_t Output[16]); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_HASH_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h index 5a4a386af..c8d1a3698 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h @@ -1,711 +1,711 @@ -/** - ****************************************************************************** - * @file stm32f4xx_i2c.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_I2C_H -#define __STM32F4xx_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2) || \ - ((PERIPH) == I2C3)) - -/** @defgroup I2C_Digital_Filter - * @{ - */ - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) -/** - * @} - */ - - -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_NACK_position - * @{ - */ - -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ - ((POSITION) == I2C_NACKPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/** - =============================================================================== - I2C Master Events (Events grouped in order of communication) - =============================================================================== - */ - -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/** - =============================================================================== - I2C Slave Events (Events grouped in order of communication) - =============================================================================== - */ - - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of transfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/* - =============================================================================== - End of Events Description - =============================================================================== - */ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the I2C configuration to the default reset state *****/ -void I2C_DeInit(I2C_TypeDef* I2Cx); - -/* Initialization and Configuration functions *********************************/ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter); -void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); - -/* PEC management functions ***************************************************/ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); - -/* DMA transfers management functions *****************************************/ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Interrupts, events and flags management functions **************************/ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); - -/* - =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - - When to use - - This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0090). - - It is also suitable for users who need to define their own events. - - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - Note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - - When to use - - This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - - The returned value could be compared to events already defined in - this file or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - - At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - - When to use - - This function could be used for specific applications or in debug - phase. - - It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor - one single event. - */ - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_I2C_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_i2c.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the I2C firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_I2C_H +#define __STM32F4xx_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2) || \ + ((PERIPH) == I2C3)) + +/** @defgroup I2C_Digital_Filter + * @{ + */ + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +/** + * @} + */ + + +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ + ((CYCLE) == I2C_DutyCycle_2)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ + ((STATE) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_DR ((uint8_t)0x10) +#define I2C_Register_SR1 ((uint8_t)0x14) +#define I2C_Register_SR2 ((uint8_t)0x18) +#define I2C_Register_CCR ((uint8_t)0x1C) +#define I2C_Register_TRISE ((uint8_t)0x20) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_DR) || \ + ((REGISTER) == I2C_Register_SR1) || \ + ((REGISTER) == I2C_Register_SR2) || \ + ((REGISTER) == I2C_Register_CCR) || \ + ((REGISTER) == I2C_Register_TRISE)) +/** + * @} + */ + +/** @defgroup I2C_NACK_position + * @{ + */ + +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ + ((POSITION) == I2C_NACKPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) +#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ + ((ALERT) == I2C_SMBusAlert_High)) +/** + * @} + */ + +/** @defgroup I2C_PEC_position + * @{ + */ + +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ + ((POSITION) == I2C_PECPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ + ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ + ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ + ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +/** + * @brief SR2 register flags + */ + +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/** + * @brief SR1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ + ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ + ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ + ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ + ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ + ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ + ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ + ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_SB)) +/** + * @} + */ + +/** @defgroup I2C_Events + * @{ + */ + +/** + =============================================================================== + I2C Master Events (Events grouped in order of communication) + =============================================================================== + */ + +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateSTART() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* --EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_Send7bitAddress() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_ReceiveData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/** + =============================================================================== + I2C Slave Events (Events grouped in order of communication) + =============================================================================== + */ + + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_AcknowledgeConfig()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of transfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +/* + =============================================================================== + End of Events Description + =============================================================================== + */ + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ + ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @defgroup I2C_clock_speed + * @{ + */ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the I2C configuration to the default reset state *****/ +void I2C_DeInit(I2C_TypeDef* I2Cx); + +/* Initialization and Configuration functions *********************************/ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter); +void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); + +/* PEC management functions ***************************************************/ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); + +/* DMA transfers management functions *****************************************/ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); + +/* Interrupts, events and flags management functions **************************/ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); + +/* + =============================================================================== + I2C State Monitoring Functions + =============================================================================== + This I2C driver provides three different ways for I2C state monitoring + depending on the application requirements and constraints: + + + 1. Basic state monitoring (Using I2C_CheckEvent() function) + ----------------------------------------------------------- + It compares the status registers (SR1 and SR2) content to a given event + (can be the combination of one or more flags). + It returns SUCCESS if the current status includes the given flags + and returns ERROR if one or more flags are missing in the current status. + + - When to use + - This function is suitable for most applications as well as for startup + activity since the events are fully described in the product reference + manual (RM0090). + - It is also suitable for users who need to define their own events. + + - Limitations + - If an error occurs (ie. error flags are set besides to the monitored + flags), the I2C_CheckEvent() function may return SUCCESS despite + the communication hold or corrupted real state. + In this case, it is advised to use error interrupts to monitor + the error events and handle them in the interrupt IRQ handler. + + Note + For error management, it is advised to use the following functions: + - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + Where x is the peripheral instance (I2C1, I2C2 ...) + - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the + I2Cx_ER_IRQHandler() function in order to determine which error occurred. + - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + and/or I2C_GenerateStop() in order to clear the error flag and source + and return to correct communication status. + + + 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) + -------------------------------------------------------------------- + Using the function I2C_GetLastEvent() which returns the image of both status + registers in a single word (uint32_t) (Status Register 2 value is shifted left + by 16 bits and concatenated to Status Register 1). + + - When to use + - This function is suitable for the same applications above but it + allows to overcome the mentioned limitation of I2C_GetFlagStatus() + function. + - The returned value could be compared to events already defined in + this file or to custom values defined by user. + This function is suitable when multiple flags are monitored at the + same time. + - At the opposite of I2C_CheckEvent() function, this function allows + user to choose when an event is accepted (when all events flags are + set and no other flags are set or just when the needed flags are set + like I2C_CheckEvent() function. + + - Limitations + - User may need to define his own events. + - Same remark concerning the error management is applicable for this + function if user decides to check only regular communication flags + (and ignores error flags). + + + 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) + ----------------------------------------------------------------------- + + Using the function I2C_GetFlagStatus() which simply returns the status of + one single flag (ie. I2C_FLAG_RXNE ...). + + - When to use + - This function could be used for specific applications or in debug + phase. + - It is suitable when only one flag checking is needed (most I2C + events are monitored through multiple flags). + - Limitations: + - When calling this function, the Status register is accessed. + Some flags are cleared when the status register is accessed. + So checking the status of one Flag, may clear other ones. + - Function may need to be called twice or more in order to monitor + one single event. + */ + +/* + =============================================================================== + 1. Basic state monitoring + =============================================================================== + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/* + =============================================================================== + 2. Advanced state monitoring + =============================================================================== + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/* + =============================================================================== + 3. Flag-based state monitoring + =============================================================================== + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_I2C_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h index 2650bd8e2..44d25432b 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h @@ -1,131 +1,131 @@ -/** - ****************************************************************************** - * @file stm32f4xx_iwdg.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_IWDG_H -#define __STM32F4xx_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Prescaler and Counter configuration functions ******************************/ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); - -/* IWDG activation function ***************************************************/ -void IWDG_Enable(void); - -/* Flag management function ***************************************************/ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_IWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_iwdg.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IWDG_H +#define __STM32F4xx_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Prescaler and Counter configuration functions ******************************/ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); + +/* IWDG activation function ***************************************************/ +void IWDG_Enable(void); + +/* Flag management function ***************************************************/ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h index e94d2d09e..8e76c5281 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h @@ -1,531 +1,531 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ltdc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the LTDC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LTDC_H -#define __STM32F4xx_LTDC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup LTDC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief LTDC Init structure definition - */ - -typedef struct -{ - uint32_t LTDC_HSPolarity; /*!< configures the horizontal synchronization polarity. - This parameter can be one value of @ref LTDC_HSPolarity */ - - uint32_t LTDC_VSPolarity; /*!< configures the vertical synchronization polarity. - This parameter can be one value of @ref LTDC_VSPolarity */ - - uint32_t LTDC_DEPolarity; /*!< configures the data enable polarity. This parameter can - be one of value of @ref LTDC_DEPolarity */ - - uint32_t LTDC_PCPolarity; /*!< configures the pixel clock polarity. This parameter can - be one of value of @ref LTDC_PCPolarity */ - - uint32_t LTDC_HorizontalSync; /*!< configures the number of Horizontal synchronization - width. This parameter must range from 0x000 to 0xFFF. */ - - uint32_t LTDC_VerticalSync; /*!< configures the number of Vertical synchronization - heigh. This parameter must range from 0x000 to 0x7FF. */ - - uint32_t LTDC_AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. - This parameter must range from LTDC_HorizontalSync to 0xFFF. */ - - uint32_t LTDC_AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh. - This parameter must range from LTDC_VerticalSync to 0x7FF. */ - - uint32_t LTDC_AccumulatedActiveW; /*!< configures the accumulated active width. This parameter - must range from LTDC_AccumulatedHBP to 0xFFF. */ - - uint32_t LTDC_AccumulatedActiveH; /*!< configures the accumulated active heigh. This parameter - must range from LTDC_AccumulatedVBP to 0x7FF. */ - - uint32_t LTDC_TotalWidth; /*!< configures the total width. This parameter - must range from LTDC_AccumulatedActiveW to 0xFFF. */ - - uint32_t LTDC_TotalHeigh; /*!< configures the total heigh. This parameter - must range from LTDC_AccumulatedActiveH to 0x7FF. */ - - uint32_t LTDC_BackgroundRedValue; /*!< configures the background red value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_BackgroundGreenValue; /*!< configures the background green value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_BackgroundBlueValue; /*!< configures the background blue value. - This parameter must range from 0x00 to 0xFF. */ -} LTDC_InitTypeDef; - -/** - * @brief LTDC Layer structure definition - */ - -typedef struct -{ - uint32_t LTDC_HorizontalStart; /*!< Configures the Window Horizontal Start Position. - This parameter must range from 0x000 to 0xFFF. */ - - uint32_t LTDC_HorizontalStop; /*!< Configures the Window Horizontal Stop Position. - This parameter must range from 0x0000 to 0xFFFF. */ - - uint32_t LTDC_VerticalStart; /*!< Configures the Window vertical Start Position. - This parameter must range from 0x000 to 0xFFF. */ - - uint32_t LTDC_VerticalStop; /*!< Configures the Window vaertical Stop Position. - This parameter must range from 0x0000 to 0xFFFF. */ - - uint32_t LTDC_PixelFormat; /*!< Specifies the pixel format. This parameter can be - one of value of @ref LTDC_Pixelformat */ - - uint32_t LTDC_ConstantAlpha; /*!< Specifies the constant alpha used for blending. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_DefaultColorBlue; /*!< Configures the default blue value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_DefaultColorGreen; /*!< Configures the default green value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_DefaultColorRed; /*!< Configures the default red value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_DefaultColorAlpha; /*!< Configures the default alpha value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_BlendingFactor_1; /*!< Select the blending factor 1. This parameter - can be one of value of @ref LTDC_BlendingFactor1 */ - - uint32_t LTDC_BlendingFactor_2; /*!< Select the blending factor 2. This parameter - can be one of value of @ref LTDC_BlendingFactor2 */ - - uint32_t LTDC_CFBStartAdress; /*!< Configures the color frame buffer address */ - - uint32_t LTDC_CFBLineLength; /*!< Configures the color frame buffer line length. - This parameter must range from 0x0000 to 0x1FFF. */ - - uint32_t LTDC_CFBPitch; /*!< Configures the color frame buffer pitch in bytes. - This parameter must range from 0x0000 to 0x1FFF. */ - - uint32_t LTDC_CFBLineNumber; /*!< Specifies the number of line in frame buffer. - This parameter must range from 0x000 to 0x7FF. */ -} LTDC_Layer_InitTypeDef; - -/** - * @brief LTDC Position structure definition - */ - -typedef struct -{ - uint32_t LTDC_POSX; /*!< Current X Position */ - uint32_t LTDC_POSY; /*!< Current Y Position */ -} LTDC_PosTypeDef; - -typedef struct -{ - uint32_t LTDC_BlueWidth; /*!< Blue width */ - uint32_t LTDC_GreenWidth; /*!< Green width */ - uint32_t LTDC_RedWidth; /*!< Red width */ -} LTDC_RGBTypeDef; - -typedef struct -{ - uint32_t LTDC_ColorKeyBlue; /*!< Configures the color key blue value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_ColorKeyGreen; /*!< Configures the color key green value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_ColorKeyRed; /*!< Configures the color key red value. - This parameter must range from 0x00 to 0xFF. */ -} LTDC_ColorKeying_InitTypeDef; - -typedef struct -{ - uint32_t LTDC_CLUTAdress; /*!< Configures the CLUT address. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_BlueValue; /*!< Configures the blue value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_GreenValue; /*!< Configures the green value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_RedValue; /*!< Configures the red value. - This parameter must range from 0x00 to 0xFF. */ -} LTDC_CLUT_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup LTDC_Exported_Constants - * @} - */ - -/** @defgroup LTDC_SYNC - * @{ - */ - -#define LTDC_HorizontalSYNC ((uint32_t)0x00000FFF) -#define LTDC_VerticalSYNC ((uint32_t)0x000007FF) - -#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HorizontalSYNC) -#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VerticalSYNC) -#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HorizontalSYNC) -#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VerticalSYNC) -#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HorizontalSYNC) -#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC) -#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC) -#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC) - -/** - * @} - */ - -/** @defgroup LTDC_HSPolarity - * @{ - */ -#define LTDC_HSPolarity_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */ -#define LTDC_HSPolarity_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ - -#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \ - ((HSPOL) == LTDC_HSPolarity_AH)) - -/** - * @} - */ - -/** @defgroup LTDC_VSPolarity - * @{ - */ -#define LTDC_VSPolarity_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */ -#define LTDC_VSPolarity_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ - -#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \ - ((VSPOL) == LTDC_VSPolarity_AH)) - -/** - * @} - */ - -/** @defgroup LTDC_DEPolarity - * @{ - */ -#define LTDC_DEPolarity_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */ -#define LTDC_DEPolarity_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ - -#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_VSPolarity_AL) || \ - ((DEPOL) == LTDC_DEPolarity_AH)) - -/** - * @} - */ - -/** @defgroup LTDC_PCPolarity - * @{ - */ -#define LTDC_PCPolarity_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */ -#define LTDC_PCPolarity_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ - -#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPolarity_IPC) || \ - ((PCPOL) == LTDC_PCPolarity_IIPC)) - -/** - * @} - */ - -/** @defgroup LTDC_Reload - * @{ - */ -#define LTDC_IMReload LTDC_SRCR_IMR /*!< Immediately Reload. */ -#define LTDC_VBReload LTDC_SRCR_VBR /*!< Vertical Blanking Reload. */ - -#define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \ - ((RELOAD) == LTDC_VBReload)) - -/** - * @} - */ - -/** @defgroup LTDC_Back_Color - * @{ - */ - -#define LTDC_Back_Color ((uint32_t)0x000000FF) - -#define IS_LTDC_BackBlueValue(BBLUE) ((BBLUE) <= LTDC_Back_Color) -#define IS_LTDC_BackGreenValue(BGREEN) ((BGREEN) <= LTDC_Back_Color) -#define IS_LTDC_BackRedValue(BRED) ((BRED) <= LTDC_Back_Color) - -/** - * @} - */ - -/** @defgroup LTDC_Position - * @{ - */ - -#define LTDC_POS_CY LTDC_CPSR_CYPOS -#define LTDC_POS_CX LTDC_CPSR_CXPOS - -#define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY)) - - -/** - * @} - */ - -/** @defgroup LTDC_LIPosition - * @{ - */ - -#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF) - -/** - * @} - */ - -/** @defgroup LTDC_CurrentStatus - * @{ - */ - -#define LTDC_CD_VDES LTDC_CDSR_VDES -#define LTDC_CD_HDES LTDC_CDSR_HDES -#define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS -#define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS - - -#define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \ - ((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC)) - - -/** - * @} - */ - -/** @defgroup LTDC_Interrupts - * @{ - */ - -#define LTDC_IT_LI LTDC_IER_LIE -#define LTDC_IT_FU LTDC_IER_FUIE -#define LTDC_IT_TERR LTDC_IER_TERRIE -#define LTDC_IT_RR LTDC_IER_RRIE - -#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00)) - -/** - * @} - */ - -/** @defgroup LTDC_Flag - * @{ - */ - -#define LTDC_FLAG_LI LTDC_ISR_LIF -#define LTDC_FLAG_FU LTDC_ISR_FUIF -#define LTDC_FLAG_TERR LTDC_ISR_TERRIF -#define LTDC_FLAG_RR LTDC_ISR_RRIF - - -#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \ - ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR)) - -/** - * @} - */ - -/** @defgroup LTDC_Pixelformat - * @{ - */ -#define LTDC_Pixelformat_ARGB8888 ((uint32_t)0x00000000) -#define LTDC_Pixelformat_RGB888 ((uint32_t)0x00000001) -#define LTDC_Pixelformat_RGB565 ((uint32_t)0x00000002) -#define LTDC_Pixelformat_ARGB1555 ((uint32_t)0x00000003) -#define LTDC_Pixelformat_ARGB4444 ((uint32_t)0x00000004) -#define LTDC_Pixelformat_L8 ((uint32_t)0x00000005) -#define LTDC_Pixelformat_AL44 ((uint32_t)0x00000006) -#define LTDC_Pixelformat_AL88 ((uint32_t)0x00000007) - -#define IS_LTDC_Pixelformat(Pixelformat) (((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888) || \ - ((Pixelformat) == LTDC_Pixelformat_RGB565) || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \ - ((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8) || \ - ((Pixelformat) == LTDC_Pixelformat_AL44) || ((Pixelformat) == LTDC_Pixelformat_AL88)) - -/** - * @} - */ - -/** @defgroup LTDC_BlendingFactor1 - * @{ - */ - -#define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400) -#define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600) - -#define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA)) - -/** - * @} - */ - -/** @defgroup LTDC_BlendingFactor2 - * @{ - */ - -#define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005) -#define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007) - -#define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA)) - - -/** - * @} - */ - - -/** @defgroup LTDC_LAYER_Config - * @{ - */ - -#define LTDC_STOPPosition ((uint32_t)0x0000FFFF) -#define LTDC_STARTPosition ((uint32_t)0x00000FFF) - -#define LTDC_DefaultColorConfig ((uint32_t)0x000000FF) -#define LTDC_ColorFrameBuffer ((uint32_t)0x00001FFF) -#define LTDC_LineNumber ((uint32_t)0x000007FF) - -#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPosition) -#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPosition) -#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPosition) -#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPosition) - -#define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR) ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig) - -#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_ColorFrameBuffer) -#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer) - -#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber) - - - -/** - * @} - */ - -/** @defgroup LTDC_colorkeying_Config - * @{ - */ - -#define LTDC_colorkeyingConfig ((uint32_t)0x000000FF) - -#define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig) - - -/** - * @} - */ - -/** @defgroup LTDC_CLUT_Config - * @{ - */ - -#define LTDC_CLUTWR ((uint32_t)0x000000FF) - -#define IS_LTDC_CLUTWR(CLUTWR) ((CLUTWR) <= LTDC_CLUTWR) - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the LTDC configuration to the default reset state *****/ -void LTDC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct); -void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct); -void LTDC_Cmd(FunctionalState NewState); -void LTDC_DitherCmd(FunctionalState NewState); -LTDC_RGBTypeDef LTDC_GetRGBWidth(void); -void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct); -void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig); -void LTDC_ReloadConfig(uint32_t LTDC_Reload); -void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct); -void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct); -void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState); -LTDC_PosTypeDef LTDC_GetPosStatus(void); -void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct); -FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD); -void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState); -void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct); -void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState); -void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct); -void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct); -void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY); -void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha); -void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address); -void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height); -void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat); - -/* Interrupts and flags management functions **********************************/ -void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState); -FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG); -void LTDC_ClearFlag(uint32_t LTDC_FLAG); -ITStatus LTDC_GetITStatus(uint32_t LTDC_IT); -void LTDC_ClearITPendingBit(uint32_t LTDC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LTDC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_ltdc.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the LTDC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LTDC_H +#define __STM32F4xx_LTDC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LTDC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief LTDC Init structure definition + */ + +typedef struct +{ + uint32_t LTDC_HSPolarity; /*!< configures the horizontal synchronization polarity. + This parameter can be one value of @ref LTDC_HSPolarity */ + + uint32_t LTDC_VSPolarity; /*!< configures the vertical synchronization polarity. + This parameter can be one value of @ref LTDC_VSPolarity */ + + uint32_t LTDC_DEPolarity; /*!< configures the data enable polarity. This parameter can + be one of value of @ref LTDC_DEPolarity */ + + uint32_t LTDC_PCPolarity; /*!< configures the pixel clock polarity. This parameter can + be one of value of @ref LTDC_PCPolarity */ + + uint32_t LTDC_HorizontalSync; /*!< configures the number of Horizontal synchronization + width. This parameter must range from 0x000 to 0xFFF. */ + + uint32_t LTDC_VerticalSync; /*!< configures the number of Vertical synchronization + heigh. This parameter must range from 0x000 to 0x7FF. */ + + uint32_t LTDC_AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. + This parameter must range from LTDC_HorizontalSync to 0xFFF. */ + + uint32_t LTDC_AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh. + This parameter must range from LTDC_VerticalSync to 0x7FF. */ + + uint32_t LTDC_AccumulatedActiveW; /*!< configures the accumulated active width. This parameter + must range from LTDC_AccumulatedHBP to 0xFFF. */ + + uint32_t LTDC_AccumulatedActiveH; /*!< configures the accumulated active heigh. This parameter + must range from LTDC_AccumulatedVBP to 0x7FF. */ + + uint32_t LTDC_TotalWidth; /*!< configures the total width. This parameter + must range from LTDC_AccumulatedActiveW to 0xFFF. */ + + uint32_t LTDC_TotalHeigh; /*!< configures the total heigh. This parameter + must range from LTDC_AccumulatedActiveH to 0x7FF. */ + + uint32_t LTDC_BackgroundRedValue; /*!< configures the background red value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_BackgroundGreenValue; /*!< configures the background green value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_BackgroundBlueValue; /*!< configures the background blue value. + This parameter must range from 0x00 to 0xFF. */ +} LTDC_InitTypeDef; + +/** + * @brief LTDC Layer structure definition + */ + +typedef struct +{ + uint32_t LTDC_HorizontalStart; /*!< Configures the Window Horizontal Start Position. + This parameter must range from 0x000 to 0xFFF. */ + + uint32_t LTDC_HorizontalStop; /*!< Configures the Window Horizontal Stop Position. + This parameter must range from 0x0000 to 0xFFFF. */ + + uint32_t LTDC_VerticalStart; /*!< Configures the Window vertical Start Position. + This parameter must range from 0x000 to 0xFFF. */ + + uint32_t LTDC_VerticalStop; /*!< Configures the Window vaertical Stop Position. + This parameter must range from 0x0000 to 0xFFFF. */ + + uint32_t LTDC_PixelFormat; /*!< Specifies the pixel format. This parameter can be + one of value of @ref LTDC_Pixelformat */ + + uint32_t LTDC_ConstantAlpha; /*!< Specifies the constant alpha used for blending. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_DefaultColorBlue; /*!< Configures the default blue value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_DefaultColorGreen; /*!< Configures the default green value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_DefaultColorRed; /*!< Configures the default red value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_DefaultColorAlpha; /*!< Configures the default alpha value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_BlendingFactor_1; /*!< Select the blending factor 1. This parameter + can be one of value of @ref LTDC_BlendingFactor1 */ + + uint32_t LTDC_BlendingFactor_2; /*!< Select the blending factor 2. This parameter + can be one of value of @ref LTDC_BlendingFactor2 */ + + uint32_t LTDC_CFBStartAdress; /*!< Configures the color frame buffer address */ + + uint32_t LTDC_CFBLineLength; /*!< Configures the color frame buffer line length. + This parameter must range from 0x0000 to 0x1FFF. */ + + uint32_t LTDC_CFBPitch; /*!< Configures the color frame buffer pitch in bytes. + This parameter must range from 0x0000 to 0x1FFF. */ + + uint32_t LTDC_CFBLineNumber; /*!< Specifies the number of line in frame buffer. + This parameter must range from 0x000 to 0x7FF. */ +} LTDC_Layer_InitTypeDef; + +/** + * @brief LTDC Position structure definition + */ + +typedef struct +{ + uint32_t LTDC_POSX; /*!< Current X Position */ + uint32_t LTDC_POSY; /*!< Current Y Position */ +} LTDC_PosTypeDef; + +typedef struct +{ + uint32_t LTDC_BlueWidth; /*!< Blue width */ + uint32_t LTDC_GreenWidth; /*!< Green width */ + uint32_t LTDC_RedWidth; /*!< Red width */ +} LTDC_RGBTypeDef; + +typedef struct +{ + uint32_t LTDC_ColorKeyBlue; /*!< Configures the color key blue value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_ColorKeyGreen; /*!< Configures the color key green value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_ColorKeyRed; /*!< Configures the color key red value. + This parameter must range from 0x00 to 0xFF. */ +} LTDC_ColorKeying_InitTypeDef; + +typedef struct +{ + uint32_t LTDC_CLUTAdress; /*!< Configures the CLUT address. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_BlueValue; /*!< Configures the blue value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_GreenValue; /*!< Configures the green value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_RedValue; /*!< Configures the red value. + This parameter must range from 0x00 to 0xFF. */ +} LTDC_CLUT_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup LTDC_Exported_Constants + * @} + */ + +/** @defgroup LTDC_SYNC + * @{ + */ + +#define LTDC_HorizontalSYNC ((uint32_t)0x00000FFF) +#define LTDC_VerticalSYNC ((uint32_t)0x000007FF) + +#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HorizontalSYNC) +#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VerticalSYNC) +#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HorizontalSYNC) +#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VerticalSYNC) +#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HorizontalSYNC) +#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC) +#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC) +#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC) + +/** + * @} + */ + +/** @defgroup LTDC_HSPolarity + * @{ + */ +#define LTDC_HSPolarity_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPolarity_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ + +#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \ + ((HSPOL) == LTDC_HSPolarity_AH)) + +/** + * @} + */ + +/** @defgroup LTDC_VSPolarity + * @{ + */ +#define LTDC_VSPolarity_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPolarity_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ + +#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \ + ((VSPOL) == LTDC_VSPolarity_AH)) + +/** + * @} + */ + +/** @defgroup LTDC_DEPolarity + * @{ + */ +#define LTDC_DEPolarity_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */ +#define LTDC_DEPolarity_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ + +#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_VSPolarity_AL) || \ + ((DEPOL) == LTDC_DEPolarity_AH)) + +/** + * @} + */ + +/** @defgroup LTDC_PCPolarity + * @{ + */ +#define LTDC_PCPolarity_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */ +#define LTDC_PCPolarity_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ + +#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPolarity_IPC) || \ + ((PCPOL) == LTDC_PCPolarity_IIPC)) + +/** + * @} + */ + +/** @defgroup LTDC_Reload + * @{ + */ +#define LTDC_IMReload LTDC_SRCR_IMR /*!< Immediately Reload. */ +#define LTDC_VBReload LTDC_SRCR_VBR /*!< Vertical Blanking Reload. */ + +#define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \ + ((RELOAD) == LTDC_VBReload)) + +/** + * @} + */ + +/** @defgroup LTDC_Back_Color + * @{ + */ + +#define LTDC_Back_Color ((uint32_t)0x000000FF) + +#define IS_LTDC_BackBlueValue(BBLUE) ((BBLUE) <= LTDC_Back_Color) +#define IS_LTDC_BackGreenValue(BGREEN) ((BGREEN) <= LTDC_Back_Color) +#define IS_LTDC_BackRedValue(BRED) ((BRED) <= LTDC_Back_Color) + +/** + * @} + */ + +/** @defgroup LTDC_Position + * @{ + */ + +#define LTDC_POS_CY LTDC_CPSR_CYPOS +#define LTDC_POS_CX LTDC_CPSR_CXPOS + +#define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY)) + + +/** + * @} + */ + +/** @defgroup LTDC_LIPosition + * @{ + */ + +#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF) + +/** + * @} + */ + +/** @defgroup LTDC_CurrentStatus + * @{ + */ + +#define LTDC_CD_VDES LTDC_CDSR_VDES +#define LTDC_CD_HDES LTDC_CDSR_HDES +#define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS +#define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS + + +#define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \ + ((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC)) + + +/** + * @} + */ + +/** @defgroup LTDC_Interrupts + * @{ + */ + +#define LTDC_IT_LI LTDC_IER_LIE +#define LTDC_IT_FU LTDC_IER_FUIE +#define LTDC_IT_TERR LTDC_IER_TERRIE +#define LTDC_IT_RR LTDC_IER_RRIE + +#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00)) + +/** + * @} + */ + +/** @defgroup LTDC_Flag + * @{ + */ + +#define LTDC_FLAG_LI LTDC_ISR_LIF +#define LTDC_FLAG_FU LTDC_ISR_FUIF +#define LTDC_FLAG_TERR LTDC_ISR_TERRIF +#define LTDC_FLAG_RR LTDC_ISR_RRIF + + +#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \ + ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR)) + +/** + * @} + */ + +/** @defgroup LTDC_Pixelformat + * @{ + */ +#define LTDC_Pixelformat_ARGB8888 ((uint32_t)0x00000000) +#define LTDC_Pixelformat_RGB888 ((uint32_t)0x00000001) +#define LTDC_Pixelformat_RGB565 ((uint32_t)0x00000002) +#define LTDC_Pixelformat_ARGB1555 ((uint32_t)0x00000003) +#define LTDC_Pixelformat_ARGB4444 ((uint32_t)0x00000004) +#define LTDC_Pixelformat_L8 ((uint32_t)0x00000005) +#define LTDC_Pixelformat_AL44 ((uint32_t)0x00000006) +#define LTDC_Pixelformat_AL88 ((uint32_t)0x00000007) + +#define IS_LTDC_Pixelformat(Pixelformat) (((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888) || \ + ((Pixelformat) == LTDC_Pixelformat_RGB565) || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \ + ((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8) || \ + ((Pixelformat) == LTDC_Pixelformat_AL44) || ((Pixelformat) == LTDC_Pixelformat_AL88)) + +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor1 + * @{ + */ + +#define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400) +#define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600) + +#define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA)) + +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor2 + * @{ + */ + +#define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005) +#define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007) + +#define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA)) + + +/** + * @} + */ + + +/** @defgroup LTDC_LAYER_Config + * @{ + */ + +#define LTDC_STOPPosition ((uint32_t)0x0000FFFF) +#define LTDC_STARTPosition ((uint32_t)0x00000FFF) + +#define LTDC_DefaultColorConfig ((uint32_t)0x000000FF) +#define LTDC_ColorFrameBuffer ((uint32_t)0x00001FFF) +#define LTDC_LineNumber ((uint32_t)0x000007FF) + +#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPosition) +#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPosition) +#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPosition) +#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPosition) + +#define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR) ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig) + +#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_ColorFrameBuffer) +#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer) + +#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber) + + + +/** + * @} + */ + +/** @defgroup LTDC_colorkeying_Config + * @{ + */ + +#define LTDC_colorkeyingConfig ((uint32_t)0x000000FF) + +#define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig) + + +/** + * @} + */ + +/** @defgroup LTDC_CLUT_Config + * @{ + */ + +#define LTDC_CLUTWR ((uint32_t)0x000000FF) + +#define IS_LTDC_CLUTWR(CLUTWR) ((CLUTWR) <= LTDC_CLUTWR) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the LTDC configuration to the default reset state *****/ +void LTDC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct); +void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct); +void LTDC_Cmd(FunctionalState NewState); +void LTDC_DitherCmd(FunctionalState NewState); +LTDC_RGBTypeDef LTDC_GetRGBWidth(void); +void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct); +void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig); +void LTDC_ReloadConfig(uint32_t LTDC_Reload); +void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct); +void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct); +void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState); +LTDC_PosTypeDef LTDC_GetPosStatus(void); +void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct); +FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD); +void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState); +void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct); +void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState); +void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct); +void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct); +void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY); +void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha); +void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address); +void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height); +void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat); + +/* Interrupts and flags management functions **********************************/ +void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState); +FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG); +void LTDC_ClearFlag(uint32_t LTDC_FLAG); +ITStatus LTDC_GetITStatus(uint32_t LTDC_IT); +void LTDC_ClearITPendingBit(uint32_t LTDC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LTDC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h index 62f0204b3..2b4336821 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h @@ -1,212 +1,212 @@ -/** - ****************************************************************************** - * @file stm32f4xx_pwr.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_PWR_H -#define __STM32F4xx_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level - * @{ - */ -#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ - ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ - ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ - ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) -/** - * @} - */ - - -/** @defgroup PWR_Regulator_state_in_STOP_mode - * @{ - */ -#define PWR_MainRegulator_ON ((uint32_t)0x00000000) -#define PWR_LowPowerRegulator_ON PWR_CR_LPDS - -/* --- PWR_Legacy ---*/ -#define PWR_Regulator_ON PWR_MainRegulator_ON -#define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON - -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \ - ((REGULATOR) == PWR_LowPowerRegulator_ON)) - -/** - * @} - */ - -/** @defgroup PWR_Regulator_state_in_UnderDrive_mode - * @{ - */ -#define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS -#define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) - -#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \ - ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON)) - -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry - * @{ - */ -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) -/** - * @} - */ - -/** @defgroup PWR_Regulator_Voltage_Scale - * @{ - */ -#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000) -#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000) -#define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000) -#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \ - ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \ - ((VOLTAGE) == PWR_Regulator_Voltage_Scale3)) -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_BRR PWR_CSR_BRR -#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY -#define PWR_FLAG_ODRDY PWR_CSR_ODRDY -#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY -#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY - -/* --- FLAG Legacy ---*/ -#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY - -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \ - ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \ - ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY)) - - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_UDRDY)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the PWR configuration to the default reset state ******/ -void PWR_DeInit(void); - -/* Backup Domain Access function **********************************************/ -void PWR_BackupAccessCmd(FunctionalState NewState); - -/* PVD configuration functions ************************************************/ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_PVDCmd(FunctionalState NewState); - -/* WakeUp pins configuration functions ****************************************/ -void PWR_WakeUpPinCmd(FunctionalState NewState); - -/* Main and Backup Regulators configuration functions *************************/ -void PWR_BackupRegulatorCmd(FunctionalState NewState); -void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage); -void PWR_OverDriveCmd(FunctionalState NewState); -void PWR_OverDriveSWCmd(FunctionalState NewState); -void PWR_UnderDriveCmd(FunctionalState NewState); -void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState); -void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState); - -/* FLASH Power Down configuration functions ***********************************/ -void PWR_FlashPowerDownCmd(FunctionalState NewState); - -/* Low Power modes configuration functions ************************************/ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); - -/* Flags management functions *************************************************/ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_pwr.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_PWR_H +#define __STM32F4xx_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level + * @{ + */ +#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 + +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ + ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ + ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ + ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) +/** + * @} + */ + + +/** @defgroup PWR_Regulator_state_in_STOP_mode + * @{ + */ +#define PWR_MainRegulator_ON ((uint32_t)0x00000000) +#define PWR_LowPowerRegulator_ON PWR_CR_LPDS + +/* --- PWR_Legacy ---*/ +#define PWR_Regulator_ON PWR_MainRegulator_ON +#define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \ + ((REGULATOR) == PWR_LowPowerRegulator_ON)) + +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_UnderDrive_mode + * @{ + */ +#define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS +#define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) + +#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \ + ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON)) + +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry + * @{ + */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) +/** + * @} + */ + +/** @defgroup PWR_Regulator_Voltage_Scale + * @{ + */ +#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000) +#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000) +#define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000) +#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \ + ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \ + ((VOLTAGE) == PWR_Regulator_Voltage_Scale3)) +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_BRR PWR_CSR_BRR +#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY +#define PWR_FLAG_ODRDY PWR_CSR_ODRDY +#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY +#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY + +/* --- FLAG Legacy ---*/ +#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY + +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \ + ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \ + ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY)) + + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_UDRDY)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the PWR configuration to the default reset state ******/ +void PWR_DeInit(void); + +/* Backup Domain Access function **********************************************/ +void PWR_BackupAccessCmd(FunctionalState NewState); + +/* PVD configuration functions ************************************************/ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_PVDCmd(FunctionalState NewState); + +/* WakeUp pins configuration functions ****************************************/ +void PWR_WakeUpPinCmd(FunctionalState NewState); + +/* Main and Backup Regulators configuration functions *************************/ +void PWR_BackupRegulatorCmd(FunctionalState NewState); +void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage); +void PWR_OverDriveCmd(FunctionalState NewState); +void PWR_OverDriveSWCmd(FunctionalState NewState); +void PWR_UnderDriveCmd(FunctionalState NewState); +void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState); +void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState); + +/* FLASH Power Down configuration functions ***********************************/ +void PWR_FlashPowerDownCmd(FunctionalState NewState); + +/* Low Power modes configuration functions ************************************/ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); + +/* Flags management functions *************************************************/ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_PWR_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h index 8b0c5cd34..c70da591a 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h @@ -1,630 +1,630 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rcc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the RCC firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RCC_H -#define __STM32F4xx_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup RCC_HSE_configuration - * @{ - */ -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_Bypass ((uint8_t)0x05) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Dual_Mode_Selection - * @{ - */ -#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) -#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) -#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \ - ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source - * @{ - */ -#define RCC_PLLSource_HSI ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE ((uint32_t)0x00400000) -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ - ((SOURCE) == RCC_PLLSource_HSE)) -#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) -#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) -#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) - -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) -#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63) - -#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - -#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) -#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) - -#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) -#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) -#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) -#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) -#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\ - ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ - ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ - ((VALUE) == RCC_PLLSAIDivR_Div16)) - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source - * @{ - */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source - * @{ - */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source - * @{ - */ -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00001000) -#define RCC_HCLK_Div4 ((uint32_t)0x00001400) -#define RCC_HCLK_Div8 ((uint32_t)0x00001800) -#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_Source - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) -#define RCC_IT_PLLSAIRDY ((uint8_t)0x40) -#define RCC_IT_CSS ((uint8_t)0x80) - -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) -#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00) - -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration - * @{ - */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source - * @{ - */ -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) -#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) -#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) -#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) -#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) -#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) -#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) -#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) -#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) -#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) -#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) -#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) -#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) -#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) -#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) -#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) -#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) -#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) -#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) -#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) -#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) -#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) -#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) -#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) -#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) -#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) -#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) -#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) -#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) -#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) -/** - * @} - */ - -/** @defgroup RCC_I2S_Clock_Source - * @{ - */ -#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) -#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) - -#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_SAI_BlockA_Clock_Source - * @{ - */ -#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) -#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) -#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) - -#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ - ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ - ((SOURCE) == RCC_SAIACLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_SAI_BlockB_Clock_Source - * @{ - */ -#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) -#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) -#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) - -#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ - ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ - ((SOURCE) == RCC_SAIBCLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_TIM_PRescaler_Selection - * @{ - */ -#define RCC_TIMPrescDesactivated ((uint8_t)0x00) -#define RCC_TIMPrescActivated ((uint8_t)0x01) - -#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripherals - * @{ - */ -#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) -#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) -#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) -#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) -#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) -#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) -#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) -#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) -#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) -#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) -#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) -#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) -#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) -#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) -#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) -#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) -#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) -#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) -#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) -#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) -#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) -#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) -#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) -#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) -#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) -#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) -#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) - -#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripherals - * @{ - */ -#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) -#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) -#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) -#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) -#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) -#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_AHB3_Peripherals - * @{ - */ -#if defined (STM32F40_41xxx) -#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripherals - * @{ - */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) -#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripherals - * @{ - */ -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) -#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) -#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) -#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) -#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) -#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) -#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) -#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000) -#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) -#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) -#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) -#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) -#define RCC_MCO1Div_1 ((uint32_t)0x00000000) -#define RCC_MCO1Div_2 ((uint32_t)0x04000000) -#define RCC_MCO1Div_3 ((uint32_t)0x05000000) -#define RCC_MCO1Div_4 ((uint32_t)0x06000000) -#define RCC_MCO1Div_5 ((uint32_t)0x07000000) -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ - ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) - -#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ - ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ - ((DIV) == RCC_MCO1Div_5)) -/** - * @} - */ - -/** @defgroup RCC_MCO2_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) -#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) -#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) -#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) -#define RCC_MCO2Div_1 ((uint32_t)0x00000000) -#define RCC_MCO2Div_2 ((uint32_t)0x20000000) -#define RCC_MCO2Div_3 ((uint32_t)0x28000000) -#define RCC_MCO2Div_4 ((uint32_t)0x30000000) -#define RCC_MCO2Div_5 ((uint32_t)0x38000000) -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ - ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) - -#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ - ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ - ((DIV) == RCC_MCO2Div_5)) -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) -#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_BORRST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ - ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ - ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) - -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RCC clock configuration to the default reset state */ -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); -void RCC_PLLCmd(FunctionalState NewState); - -#if defined (STM32F40_41xxx) || defined (STM32F401xx) -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); -#elif defined (STM32F411xE) -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM); -#elif defined (STM32F427_437xx) || defined (STM32F429_439xx) -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR); -#else -#endif /* STM32F40_41xxx || STM32F401xx */ - -void RCC_PLLI2SCmd(FunctionalState NewState); -void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR); -void RCC_PLLSAICmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); - -/* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); - -/* Peripheral clocks configuration functions **********************************/ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); -void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ); -void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ); -void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); -void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); -void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR); -void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler); - -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_LSEModeConfig(uint8_t Mode); - -/* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_RCC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_rcc.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the RCC firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_RCC_H +#define __STM32F4xx_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup RCC_HSE_configuration + * @{ + */ +#define RCC_HSE_OFF ((uint8_t)0x00) +#define RCC_HSE_ON ((uint8_t)0x01) +#define RCC_HSE_Bypass ((uint8_t)0x05) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Dual_Mode_Selection + * @{ + */ +#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) +#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source + * @{ + */ +#define RCC_PLLSource_HSI ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE ((uint32_t)0x00400000) +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ + ((SOURCE) == RCC_PLLSource_HSE)) +#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) +#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) + +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) +#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63) + +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) +#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) + +#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) +#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) +#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) +#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) +#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\ + ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ + ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ + ((VALUE) == RCC_PLLSAIDivR_Div16)) + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source + * @{ + */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source + * @{ + */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source + * @{ + */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00001000) +#define RCC_HCLK_Div4 ((uint32_t)0x00001400) +#define RCC_HCLK_Div8 ((uint32_t)0x00001800) +#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_Source + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) +#define RCC_IT_PLLSAIRDY ((uint8_t)0x40) +#define RCC_IT_CSS ((uint8_t)0x80) + +#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) +#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration + * @{ + */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source + * @{ + */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) +#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) +#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) +#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) +#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) +#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) +#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) +#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) +#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) +#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) +#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) +#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) +#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) +#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) +#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) +#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) +#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) +#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) +#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) +#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) +#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) +#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) +#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) +#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) +#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) +#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) +#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) +#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) +#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) +#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) +/** + * @} + */ + +/** @defgroup RCC_I2S_Clock_Source + * @{ + */ +#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) +#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) + +#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) +/** + * @} + */ + +/** @defgroup RCC_SAI_BlockA_Clock_Source + * @{ + */ +#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) +#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) + +#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ + ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ + ((SOURCE) == RCC_SAIACLKSource_Ext)) +/** + * @} + */ + +/** @defgroup RCC_SAI_BlockB_Clock_Source + * @{ + */ +#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) +#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) + +#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ + ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ + ((SOURCE) == RCC_SAIBCLKSource_Ext)) +/** + * @} + */ + +/** @defgroup RCC_TIM_PRescaler_Selection + * @{ + */ +#define RCC_TIMPrescDesactivated ((uint8_t)0x00) +#define RCC_TIMPrescActivated ((uint8_t)0x01) + +#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripherals + * @{ + */ +#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) +#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) +#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) +#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) +#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) +#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) +#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) +#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) +#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) +#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) +#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) +#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) +#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) +#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) +#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) +#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) +#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) +#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) +#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) +#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) +#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) +#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) +#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) +#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) +#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) +#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) +#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) + +#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripherals + * @{ + */ +#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) +#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) +#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) +#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) +#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) +#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_AHB3_Peripherals + * @{ + */ +#if defined (STM32F40_41xxx) +#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripherals + * @{ + */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) +#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripherals + * @{ + */ +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) +#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) +#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) +#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) +#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) +#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) +#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) +#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000) +#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source_Prescaler + * @{ + */ +#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) +#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) +#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) +#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) +#define RCC_MCO1Div_1 ((uint32_t)0x00000000) +#define RCC_MCO1Div_2 ((uint32_t)0x04000000) +#define RCC_MCO1Div_3 ((uint32_t)0x05000000) +#define RCC_MCO1Div_4 ((uint32_t)0x06000000) +#define RCC_MCO1Div_5 ((uint32_t)0x07000000) +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ + ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) + +#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ + ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ + ((DIV) == RCC_MCO1Div_5)) +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source_Prescaler + * @{ + */ +#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) +#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) +#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) +#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) +#define RCC_MCO2Div_1 ((uint32_t)0x00000000) +#define RCC_MCO2Div_2 ((uint32_t)0x20000000) +#define RCC_MCO2Div_3 ((uint32_t)0x28000000) +#define RCC_MCO2Div_4 ((uint32_t)0x30000000) +#define RCC_MCO2Div_5 ((uint32_t)0x38000000) +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) + +#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ + ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ + ((DIV) == RCC_MCO2Div_5)) +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) +#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_BORRST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ + ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ + ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RCC clock configuration to the default reset state */ +void RCC_DeInit(void); + +/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ +void RCC_HSEConfig(uint8_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); +void RCC_PLLCmd(FunctionalState NewState); + +#if defined (STM32F40_41xxx) || defined (STM32F401xx) +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); +#elif defined (STM32F411xE) +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM); +#elif defined (STM32F427_437xx) || defined (STM32F429_439xx) +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR); +#else +#endif /* STM32F40_41xxx || STM32F401xx */ + +void RCC_PLLI2SCmd(FunctionalState NewState); +void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR); +void RCC_PLLSAICmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); +void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); + +/* System, AHB and APB busses clocks configuration functions ******************/ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); + +/* Peripheral clocks configuration functions **********************************/ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); +void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ); +void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ); +void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); +void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); +void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR); +void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler); + +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_LSEModeConfig(uint8_t Mode); + +/* Interrupts and flags management functions **********************************/ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_RCC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h index b97f832cb..58b468d9c 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h @@ -1,120 +1,120 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rng.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the Random - * Number Generator(RNG) firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RNG_H -#define __STM32F4xx_RNG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RNG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RNG_Exported_Constants - * @{ - */ - -/** @defgroup RNG_flags_definition - * @{ - */ -#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ -#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ -#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ - -#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ - ((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -/** - * @} - */ - -/** @defgroup RNG_interrupts_definition - * @{ - */ -#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ -#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ - -#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) -#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RNG configuration to the default reset state *****/ -void RNG_DeInit(void); - -/* Configuration function *****************************************************/ -void RNG_Cmd(FunctionalState NewState); - -/* Get 32 bit Random number function ******************************************/ -uint32_t RNG_GetRandomNumber(void); - -/* Interrupts and flags management functions **********************************/ -void RNG_ITConfig(FunctionalState NewState); -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); -void RNG_ClearFlag(uint8_t RNG_FLAG); -ITStatus RNG_GetITStatus(uint8_t RNG_IT); -void RNG_ClearITPendingBit(uint8_t RNG_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_RNG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_rng.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the Random + * Number Generator(RNG) firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_RNG_H +#define __STM32F4xx_RNG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RNG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RNG_Exported_Constants + * @{ + */ + +/** @defgroup RNG_flags_definition + * @{ + */ +#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ +#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ +#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ + +#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ + ((RNG_FLAG) == RNG_FLAG_CECS) || \ + ((RNG_FLAG) == RNG_FLAG_SECS)) +#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ + ((RNG_FLAG) == RNG_FLAG_SECS)) +/** + * @} + */ + +/** @defgroup RNG_interrupts_definition + * @{ + */ +#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ +#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ + +#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) +#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RNG configuration to the default reset state *****/ +void RNG_DeInit(void); + +/* Configuration function *****************************************************/ +void RNG_Cmd(FunctionalState NewState); + +/* Get 32 bit Random number function ******************************************/ +uint32_t RNG_GetRandomNumber(void); + +/* Interrupts and flags management functions **********************************/ +void RNG_ITConfig(FunctionalState NewState); +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); +void RNG_ClearFlag(uint8_t RNG_FLAG); +ITStatus RNG_GetITStatus(uint8_t RNG_IT); +void RNG_ClearITPendingBit(uint8_t RNG_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_RNG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h index c9348f22a..de3c06be8 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h @@ -1,881 +1,881 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rtc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RTC_H -#define __STM32F4xx_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be set to a value lower than 0x7F */ - - uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be set to a value lower than 0x7FFF */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. - This parameter must be set to a value in the 0-12 range - if the RTC_HourFormat_12 is selected or 0-23 range if - the RTC_HourFormat_24 is selected. */ - - uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t RTC_Date; /*!< Specifies the RTC Date. - This parameter must be set to a value in the 1-31 range. */ - - uint8_t RTC_Year; /*!< Specifies the RTC Date Year. - This parameter must be set to a value in the 0-99 range. */ -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter - must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this - parameter can be a value of @ref RTC_WeekDay_Definitions */ -}RTC_AlarmTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - - -/** @defgroup RTC_Hour_Formats - * @{ - */ -#define RTC_HourFormat_24 ((uint32_t)0x00000000) -#define RTC_HourFormat_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ - ((FORMAT) == RTC_HourFormat_24)) -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) - -/** - * @} - */ - - -/** @defgroup RTC_Synchronous_Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) - -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) - -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions - * @{ - */ -#define RTC_H12_AM ((uint8_t)0x00) -#define RTC_H12_PM ((uint8_t)0x40) -#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) - -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_Month_January ((uint8_t)0x01) -#define RTC_Month_February ((uint8_t)0x02) -#define RTC_Month_March ((uint8_t)0x03) -#define RTC_Month_April ((uint8_t)0x04) -#define RTC_Month_May ((uint8_t)0x05) -#define RTC_Month_June ((uint8_t)0x06) -#define RTC_Month_July ((uint8_t)0x07) -#define RTC_Month_August ((uint8_t)0x08) -#define RTC_Month_September ((uint8_t)0x09) -#define RTC_Month_October ((uint8_t)0x10) -#define RTC_Month_November ((uint8_t)0x11) -#define RTC_Month_December ((uint8_t)0x12) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions - * @{ - */ - -#define RTC_Weekday_Monday ((uint8_t)0x01) -#define RTC_Weekday_Tuesday ((uint8_t)0x02) -#define RTC_Weekday_Wednesday ((uint8_t)0x03) -#define RTC_Weekday_Thursday ((uint8_t)0x04) -#define RTC_Weekday_Friday ((uint8_t)0x05) -#define RTC_Weekday_Saturday ((uint8_t)0x06) -#define RTC_Weekday_Sunday ((uint8_t)0x07) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) -/** - * @} - */ - - -/** @defgroup RTC_Alarm_Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions - * @{ - */ -#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) -#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ - ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions - * @{ - */ -#define RTC_AlarmMask_None ((uint32_t)0x00000000) -#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) -#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) -#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) -#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) -#define RTC_AlarmMask_All ((uint32_t)0x80808080) -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions - * @{ - */ -#define RTC_Alarm_A ((uint32_t)0x00000100) -#define RTC_Alarm_B ((uint32_t)0x00000200) -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) -#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) - -/** - * @} - */ - - /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions - * @{ - */ -#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match - to activate alarm. */ -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ - ((MASK) == RTC_AlarmSubSecondMask_None)) -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Value - * @{ - */ - -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Wakeup_Timer_Definitions - * @{ - */ -#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) -#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) -#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) -#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) -#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) -#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTC_Time_Stamp_Edges_definitions - * @{ - */ -#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) -#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) -#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ - ((EDGE) == RTC_TimeStampEdge_Falling)) -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions - * @{ - */ -#define RTC_Output_Disable ((uint32_t)0x00000000) -#define RTC_Output_AlarmA ((uint32_t)0x00200000) -#define RTC_Output_AlarmB ((uint32_t)0x00400000) -#define RTC_Output_WakeUp ((uint32_t)0x00600000) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ - ((OUTPUT) == RTC_Output_AlarmA) || \ - ((OUTPUT) == RTC_Output_AlarmB) || \ - ((OUTPUT) == RTC_Output_WakeUp)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions - * @{ - */ -#define RTC_OutputPolarity_High ((uint32_t)0x00000000) -#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ - ((POL) == RTC_OutputPolarity_Low)) -/** - * @} - */ - - -/** @defgroup RTC_Digital_Calibration_Definitions - * @{ - */ -#define RTC_CalibSign_Positive ((uint32_t)0x00000000) -#define RTC_CalibSign_Negative ((uint32_t)0x00000080) -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ - ((SIGN) == RTC_CalibSign_Negative)) -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) - -/** - * @} - */ - - /** @defgroup RTC_Calib_Output_selection_Definitions - * @{ - */ -#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) -#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ - ((OUTPUT) == RTC_CalibOutput_1Hz)) -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_period_Definitions - * @{ - */ -#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 8s, else 2exp18 RTCCLK seconds */ -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions - * @{ - */ -#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0]. - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0]. */ -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ - ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions - * @{ - */ -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) - -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions - * @{ - */ -#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) -#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ - ((SAVE) == RTC_DayLightSaving_ADD1H)) - -#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) -#define RTC_StoreOperation_Set ((uint32_t)0x00040000) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ - ((OPERATION) == RTC_StoreOperation_Set)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Trigger_Definitions - * @{ - */ -#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) -#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) -#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) -#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ - ((TRIGGER) == RTC_TamperTrigger_HighLevel)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Filter_Definitions - * @{ - */ -#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ - -#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active leve. */ -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ - ((FILTER) == RTC_TamperFilter_2Sample) || \ - ((FILTER) == RTC_TamperFilter_4Sample) || \ - ((FILTER) == RTC_TamperFilter_8Sample)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions - * @{ - */ -#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) - -/** - * @} - */ - - /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions - * @{ - */ -#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pins_Definitions - * @{ - */ -#define RTC_Tamper_1 RTC_TAFCR_TAMP1E -#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pin_Selection - * @{ - */ -#define RTC_TamperPin_PC13 ((uint32_t)0x00000000) -#define RTC_TamperPin_PI8 ((uint32_t)0x00010000) -#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ - ((PIN) == RTC_TamperPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_TimeStamp_Pin_Selection - * @{ - */ -#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) -#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) -#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ - ((PIN) == RTC_TimeStampPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT - * @{ - */ -#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) -#define RTC_OutputType_PushPull ((uint32_t)0x00040000) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ - ((TYPE) == RTC_OutputType_PushPull)) - -/** - * @} - */ - -/** @defgroup RTC_Add_1_Second_Parameter_Definitions - * @{ - */ -#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) -#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ - ((SEL) == RTC_ShiftAdd1S_Set)) -/** - * @} - */ - -/** @defgroup RTC_Substract_Fraction_Of_Second_Value - * @{ - */ -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Backup_Registers_Definitions - * @{ - */ - -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4) || \ - ((BKP) == RTC_BKP_DR5) || \ - ((BKP) == RTC_BKP_DR6) || \ - ((BKP) == RTC_BKP_DR7) || \ - ((BKP) == RTC_BKP_DR8) || \ - ((BKP) == RTC_BKP_DR9) || \ - ((BKP) == RTC_BKP_DR10) || \ - ((BKP) == RTC_BKP_DR11) || \ - ((BKP) == RTC_BKP_DR12) || \ - ((BKP) == RTC_BKP_DR13) || \ - ((BKP) == RTC_BKP_DR14) || \ - ((BKP) == RTC_BKP_DR15) || \ - ((BKP) == RTC_BKP_DR16) || \ - ((BKP) == RTC_BKP_DR17) || \ - ((BKP) == RTC_BKP_DR18) || \ - ((BKP) == RTC_BKP_DR19)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions - * @{ - */ -#define RTC_Format_BIN ((uint32_t)0x000000000) -#define RTC_Format_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) - -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions - * @{ - */ -#define RTC_FLAG_RECALPF ((uint32_t)0x00010000) -#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) -#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) -#define RTC_FLAG_TSF ((uint32_t)0x00000800) -#define RTC_FLAG_WUTF ((uint32_t)0x00000400) -#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) -#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) -#define RTC_FLAG_INITF ((uint32_t)0x00000040) -#define RTC_FLAG_RSF ((uint32_t)0x00000020) -#define RTC_FLAG_INITS ((uint32_t)0x00000010) -#define RTC_FLAG_SHPF ((uint32_t)0x00000008) -#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) -#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) -#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ - ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ - ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ - ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ - ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ - ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \ - ((FLAG) == RTC_FLAG_SHPF)) -#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRB ((uint32_t)0x00002000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) - -#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ - ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ - ((IT) == RTC_IT_TAMP1)) -#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Legacy - * @{ - */ -#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig -#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RTC configuration to the default reset state *****/ -ErrorStatus RTC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); -void RTC_WriteProtectionCmd(FunctionalState NewState); -ErrorStatus RTC_EnterInitMode(void); -void RTC_ExitInitMode(void); -ErrorStatus RTC_WaitForSynchro(void); -ErrorStatus RTC_RefClockCmd(FunctionalState NewState); -void RTC_BypassShadowCmd(FunctionalState NewState); - -/* Time and Date configuration functions **************************************/ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -uint32_t RTC_GetSubSecond(void); -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); - -/* Alarms (Alarm A and Alarm B) configuration functions **********************/ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); - -/* WakeUp Timer configuration functions ***************************************/ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); -uint32_t RTC_GetWakeUpCounter(void); -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); - -/* Daylight Saving configuration functions ************************************/ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); -uint32_t RTC_GetStoreOperation(void); - -/* Output pin Configuration function ******************************************/ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); - -/* Digital Calibration configuration functions *********************************/ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); -void RTC_CalibOutputCmd(FunctionalState NewState); -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue); - -/* TimeStamp configuration functions ******************************************/ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct); -uint32_t RTC_GetTimeStampSubSecond(void); - -/* Tampers configuration functions ********************************************/ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); -void RTC_TamperPullUpCmd(FunctionalState NewState); - -/* Backup Data Registers configuration functions ******************************/ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); - -/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - functions ******************************************************************/ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin); -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); -void RTC_OutputTypeConfig(uint32_t RTC_OutputType); - -/* RTC_Shift_control_synchonisation_functions *********************************/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); - -/* Interrupts and flags management functions **********************************/ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); -void RTC_ClearFlag(uint32_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint32_t RTC_IT); -void RTC_ClearITPendingBit(uint32_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_rtc.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_RTC_H +#define __STM32F4xx_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be set to a value lower than 0x7F */ + + uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be set to a value lower than 0x7FFF */ +}RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. + This parameter must be set to a value in the 0-12 range + if the RTC_HourFormat_12 is selected or 0-23 range if + the RTC_HourFormat_24 is selected. */ + + uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ +}RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t RTC_Date; /*!< Specifies the RTC Date. + This parameter must be set to a value in the 1-31 range. */ + + uint8_t RTC_Year; /*!< Specifies the RTC Date Year. + This parameter must be set to a value in the 0-99 range. */ +}RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter + must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this + parameter can be a value of @ref RTC_WeekDay_Definitions */ +}RTC_AlarmTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + + +/** @defgroup RTC_Hour_Formats + * @{ + */ +#define RTC_HourFormat_24 ((uint32_t)0x00000000) +#define RTC_HourFormat_12 ((uint32_t)0x00000040) +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ + ((FORMAT) == RTC_HourFormat_24)) +/** + * @} + */ + +/** @defgroup RTC_Asynchronous_Predivider + * @{ + */ +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) + +/** + * @} + */ + + +/** @defgroup RTC_Synchronous_Predivider + * @{ + */ +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) + +/** + * @} + */ + +/** @defgroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) + +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_H12_AM ((uint8_t)0x00) +#define RTC_H12_PM ((uint8_t)0x40) +#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) + +/** + * @} + */ + +/** @defgroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) + +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_Month_January ((uint8_t)0x01) +#define RTC_Month_February ((uint8_t)0x02) +#define RTC_Month_March ((uint8_t)0x03) +#define RTC_Month_April ((uint8_t)0x04) +#define RTC_Month_May ((uint8_t)0x05) +#define RTC_Month_June ((uint8_t)0x06) +#define RTC_Month_July ((uint8_t)0x07) +#define RTC_Month_August ((uint8_t)0x08) +#define RTC_Month_September ((uint8_t)0x09) +#define RTC_Month_October ((uint8_t)0x10) +#define RTC_Month_November ((uint8_t)0x11) +#define RTC_Month_December ((uint8_t)0x12) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions + * @{ + */ + +#define RTC_Weekday_Monday ((uint8_t)0x01) +#define RTC_Weekday_Tuesday ((uint8_t)0x02) +#define RTC_Weekday_Wednesday ((uint8_t)0x03) +#define RTC_Weekday_Thursday ((uint8_t)0x04) +#define RTC_Weekday_Friday ((uint8_t)0x05) +#define RTC_Weekday_Saturday ((uint8_t)0x06) +#define RTC_Weekday_Sunday ((uint8_t)0x07) +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) +/** + * @} + */ + + +/** @defgroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmDateWeekDay_Definitions + * @{ + */ +#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) +#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ + ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_AlarmMask_None ((uint32_t)0x00000000) +#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) +#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) +#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) +#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) +#define RTC_AlarmMask_All ((uint32_t)0x80808080) +#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions + * @{ + */ +#define RTC_Alarm_A ((uint32_t)0x00000100) +#define RTC_Alarm_B ((uint32_t)0x00000200) +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) +#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) + +/** + * @} + */ + + /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions + * @{ + */ +#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm + comparison.Only SS[13:0] are compared */ +#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match + to activate alarm. */ +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ + ((MASK) == RTC_AlarmSubSecondMask_None)) +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_Value + * @{ + */ + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) + +/** + * @} + */ + +/** @defgroup RTC_Wakeup_Timer_Definitions + * @{ + */ +#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) +#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) +#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) +#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) +#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) +#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ + ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ + ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +/** + * @} + */ + +/** @defgroup RTC_Time_Stamp_Edges_definitions + * @{ + */ +#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) +#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) +#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ + ((EDGE) == RTC_TimeStampEdge_Falling)) +/** + * @} + */ + +/** @defgroup RTC_Output_selection_Definitions + * @{ + */ +#define RTC_Output_Disable ((uint32_t)0x00000000) +#define RTC_Output_AlarmA ((uint32_t)0x00200000) +#define RTC_Output_AlarmB ((uint32_t)0x00400000) +#define RTC_Output_WakeUp ((uint32_t)0x00600000) + +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ + ((OUTPUT) == RTC_Output_AlarmA) || \ + ((OUTPUT) == RTC_Output_AlarmB) || \ + ((OUTPUT) == RTC_Output_WakeUp)) + +/** + * @} + */ + +/** @defgroup RTC_Output_Polarity_Definitions + * @{ + */ +#define RTC_OutputPolarity_High ((uint32_t)0x00000000) +#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ + ((POL) == RTC_OutputPolarity_Low)) +/** + * @} + */ + + +/** @defgroup RTC_Digital_Calibration_Definitions + * @{ + */ +#define RTC_CalibSign_Positive ((uint32_t)0x00000000) +#define RTC_CalibSign_Negative ((uint32_t)0x00000080) +#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ + ((SIGN) == RTC_CalibSign_Negative)) +#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) + +/** + * @} + */ + + /** @defgroup RTC_Calib_Output_selection_Definitions + * @{ + */ +#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) +#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ + ((OUTPUT) == RTC_CalibOutput_1Hz)) +/** + * @} + */ + +/** @defgroup RTC_Smooth_calib_period_Definitions + * @{ + */ +#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 32s, else 2exp20 RTCCLK seconds */ +#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 16s, else 2exp19 RTCCLK seconds */ +#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 8s, else 2exp18 RTCCLK seconds */ +#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ + ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ + ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) + +/** + * @} + */ + +/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions + * @{ + */ +#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0]. + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0]. */ +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ + ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) + +/** + * @} + */ + +/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions + * @{ + */ +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) + +/** + * @} + */ + +/** @defgroup RTC_DayLightSaving_Definitions + * @{ + */ +#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) +#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ + ((SAVE) == RTC_DayLightSaving_ADD1H)) + +#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) +#define RTC_StoreOperation_Set ((uint32_t)0x00040000) +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ + ((OPERATION) == RTC_StoreOperation_Set)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Trigger_Definitions + * @{ + */ +#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) +#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) +#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) +#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ + ((TRIGGER) == RTC_TamperTrigger_HighLevel)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Filter_Definitions + * @{ + */ +#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ + +#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 + consecutive samples at the active leve. */ +#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ + ((FILTER) == RTC_TamperFilter_2Sample) || \ + ((FILTER) == RTC_TamperFilter_4Sample) || \ + ((FILTER) == RTC_TamperFilter_8Sample)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions + * @{ + */ +#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) + +/** + * @} + */ + + /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions + * @{ + */ +#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ + +#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pins_Definitions + * @{ + */ +#define RTC_Tamper_1 RTC_TAFCR_TAMP1E +#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pin_Selection + * @{ + */ +#define RTC_TamperPin_PC13 ((uint32_t)0x00000000) +#define RTC_TamperPin_PI8 ((uint32_t)0x00010000) +#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ + ((PIN) == RTC_TamperPin_PI8)) +/** + * @} + */ + +/** @defgroup RTC_TimeStamp_Pin_Selection + * @{ + */ +#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) +#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) +#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ + ((PIN) == RTC_TimeStampPin_PI8)) +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT + * @{ + */ +#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) +#define RTC_OutputType_PushPull ((uint32_t)0x00040000) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ + ((TYPE) == RTC_OutputType_PushPull)) + +/** + * @} + */ + +/** @defgroup RTC_Add_1_Second_Parameter_Definitions + * @{ + */ +#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) +#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ + ((SEL) == RTC_ShiftAdd1S_Set)) +/** + * @} + */ + +/** @defgroup RTC_Substract_Fraction_Of_Second_Value + * @{ + */ +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) + +/** + * @} + */ + +/** @defgroup RTC_Backup_Registers_Definitions + * @{ + */ + +#define RTC_BKP_DR0 ((uint32_t)0x00000000) +#define RTC_BKP_DR1 ((uint32_t)0x00000001) +#define RTC_BKP_DR2 ((uint32_t)0x00000002) +#define RTC_BKP_DR3 ((uint32_t)0x00000003) +#define RTC_BKP_DR4 ((uint32_t)0x00000004) +#define RTC_BKP_DR5 ((uint32_t)0x00000005) +#define RTC_BKP_DR6 ((uint32_t)0x00000006) +#define RTC_BKP_DR7 ((uint32_t)0x00000007) +#define RTC_BKP_DR8 ((uint32_t)0x00000008) +#define RTC_BKP_DR9 ((uint32_t)0x00000009) +#define RTC_BKP_DR10 ((uint32_t)0x0000000A) +#define RTC_BKP_DR11 ((uint32_t)0x0000000B) +#define RTC_BKP_DR12 ((uint32_t)0x0000000C) +#define RTC_BKP_DR13 ((uint32_t)0x0000000D) +#define RTC_BKP_DR14 ((uint32_t)0x0000000E) +#define RTC_BKP_DR15 ((uint32_t)0x0000000F) +#define RTC_BKP_DR16 ((uint32_t)0x00000010) +#define RTC_BKP_DR17 ((uint32_t)0x00000011) +#define RTC_BKP_DR18 ((uint32_t)0x00000012) +#define RTC_BKP_DR19 ((uint32_t)0x00000013) +#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ + ((BKP) == RTC_BKP_DR1) || \ + ((BKP) == RTC_BKP_DR2) || \ + ((BKP) == RTC_BKP_DR3) || \ + ((BKP) == RTC_BKP_DR4) || \ + ((BKP) == RTC_BKP_DR5) || \ + ((BKP) == RTC_BKP_DR6) || \ + ((BKP) == RTC_BKP_DR7) || \ + ((BKP) == RTC_BKP_DR8) || \ + ((BKP) == RTC_BKP_DR9) || \ + ((BKP) == RTC_BKP_DR10) || \ + ((BKP) == RTC_BKP_DR11) || \ + ((BKP) == RTC_BKP_DR12) || \ + ((BKP) == RTC_BKP_DR13) || \ + ((BKP) == RTC_BKP_DR14) || \ + ((BKP) == RTC_BKP_DR15) || \ + ((BKP) == RTC_BKP_DR16) || \ + ((BKP) == RTC_BKP_DR17) || \ + ((BKP) == RTC_BKP_DR18) || \ + ((BKP) == RTC_BKP_DR19)) +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions + * @{ + */ +#define RTC_Format_BIN ((uint32_t)0x000000000) +#define RTC_Format_BCD ((uint32_t)0x000000001) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) + +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_RECALPF ((uint32_t)0x00010000) +#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) +#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) +#define RTC_FLAG_TSF ((uint32_t)0x00000800) +#define RTC_FLAG_WUTF ((uint32_t)0x00000400) +#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) +#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) +#define RTC_FLAG_INITF ((uint32_t)0x00000040) +#define RTC_FLAG_RSF ((uint32_t)0x00000020) +#define RTC_FLAG_INITS ((uint32_t)0x00000010) +#define RTC_FLAG_SHPF ((uint32_t)0x00000008) +#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) +#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) +#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ + ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ + ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ + ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ + ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ + ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \ + ((FLAG) == RTC_FLAG_SHPF)) +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions + * @{ + */ +#define RTC_IT_TS ((uint32_t)0x00008000) +#define RTC_IT_WUT ((uint32_t)0x00004000) +#define RTC_IT_ALRB ((uint32_t)0x00002000) +#define RTC_IT_ALRA ((uint32_t)0x00001000) +#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TAMP1 ((uint32_t)0x00020000) + +#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ + ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ + ((IT) == RTC_IT_TAMP1)) +#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup RTC_Legacy + * @{ + */ +#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig +#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RTC configuration to the default reset state *****/ +ErrorStatus RTC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); +void RTC_WriteProtectionCmd(FunctionalState NewState); +ErrorStatus RTC_EnterInitMode(void); +void RTC_ExitInitMode(void); +ErrorStatus RTC_WaitForSynchro(void); +ErrorStatus RTC_RefClockCmd(FunctionalState NewState); +void RTC_BypassShadowCmd(FunctionalState NewState); + +/* Time and Date configuration functions **************************************/ +ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +uint32_t RTC_GetSubSecond(void); +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); +void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); + +/* Alarms (Alarm A and Alarm B) configuration functions **********************/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); +void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); + +/* WakeUp Timer configuration functions ***************************************/ +void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); +uint32_t RTC_GetWakeUpCounter(void); +ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); + +/* Daylight Saving configuration functions ************************************/ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void); + +/* Output pin Configuration function ******************************************/ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); + +/* Digital Calibration configuration functions *********************************/ +ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); +ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); +void RTC_CalibOutputCmd(FunctionalState NewState); +void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); +ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue); + +/* TimeStamp configuration functions ******************************************/ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, + RTC_DateTypeDef* RTC_StampDateStruct); +uint32_t RTC_GetTimeStampSubSecond(void); + +/* Tampers configuration functions ********************************************/ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); +void RTC_TamperPullUpCmd(FunctionalState NewState); + +/* Backup Data Registers configuration functions ******************************/ +void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); +uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); + +/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration + functions ******************************************************************/ +void RTC_TamperPinSelection(uint32_t RTC_TamperPin); +void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); +void RTC_OutputTypeConfig(uint32_t RTC_OutputType); + +/* RTC_Shift_control_synchonisation_functions *********************************/ +ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); + +/* Interrupts and flags management functions **********************************/ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +void RTC_ClearFlag(uint32_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint32_t RTC_IT); +void RTC_ClearITPendingBit(uint32_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_RTC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h index a6eb21772..a7805d570 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h @@ -1,611 +1,611 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sai.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the SAI - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SAI_H -#define __STM32F4xx_SAI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SAI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SAI Block Init structure definition - */ - -typedef struct -{ - uint32_t SAI_AudioMode; /*!< Specifies the SAI Block Audio Mode. - This parameter can be a value of @ref SAI_Block_Mode */ - - uint32_t SAI_Protocol; /*!< Specifies the SAI Block Protocol. - This parameter can be a value of @ref SAI_Block_Protocol */ - - uint32_t SAI_DataSize; /*!< Specifies the SAI Block data size. - This parameter can be a value of @ref SAI_Block_Data_Size - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission - @note this value has no meaning when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. - This parameter can be a value of @ref SAI_Block_Clock_Strobing */ - - uint32_t SAI_Synchro; /*!< Specifies SAI Block synchronization - This parameter can be a value of @ref SAI_Block_Synchronization */ - - uint32_t SAI_OUTDRIV; /*!< Specifies when SAI Block outputs are driven. - This parameter can be a value of @ref SAI_Block_Output_Drive - @note this value has to be set before enabling the audio block - but after the audio block configuration. */ - - uint32_t SAI_NoDivider; /*!< Specifies whether Master Clock will be divided or not. - This parameter can be a value of @ref SAI_Block_NoDivider */ - - uint32_t SAI_MasterDivider; /*!< Specifies SAI Block Master Clock Divider. - @note the Master Clock Frequency is calculated accordingly to the - following formula : MCLK_x = SAI_CK_x/(MCKDIV[3:0]*2)*/ - - uint32_t SAI_FIFOThreshold; /*!< Specifies SAI Block FIFO Threshold. - This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ -}SAI_InitTypeDef; - -/** - * @brief SAI Block Frame Init structure definition - */ - -typedef struct -{ - - uint32_t SAI_FrameLength; /*!< Specifies the Frame Length, the number of SCK clocks - for each audio frame. - This parameter must be a number between 8 and 256. - @note If master Clock MCLK_x pin is declared as an output, the frame length - should be Aligned to a number equal to power of 2 in order to keep - in an audio frame, an integer number of MCLK pulses by bit Clock. - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. - This Parameter specifies the length in number of bit clock (SCK + 1) - of the active level of FS signal in audio frame. - This parameter must be a number between 1 and 128. - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_FSDefinition; /*!< Specifies the Frame Synchronization definition. - This parameter can be a value of @ref SAI_Block_FS_Definition - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_FSPolarity; /*!< Specifies the Frame Synchronization Polarity. - This parameter can be a value of @ref SAI_Block_FS_Polarity - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_FSOffset; /*!< Specifies the Frame Synchronization Offset. - This parameter can be a value of @ref SAI_Block_FS_Offset - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - -}SAI_FrameInitTypeDef; - -/** - * @brief SAI Block Slot Init Structure definition - */ - -typedef struct -{ - uint32_t SAI_FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot. - This parameter must be a number between 0 and 24. - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_SlotSize; /*!< Specifies the Slot Size. - This parameter can be a value of @ref SAI_Block_Slot_Size - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_SlotNumber; /*!< Specifies the number of slot in the audio frame. - This parameter must be a number between 1 and 16. - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_SlotActive; /*!< Specifies the slots in audio frame that will be activated. - This parameter can be a value of @ ref SAI_Block_Slot_Active - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ -}SAI_SlotInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SAI_Exported_Constants - * @{ - */ - -#define IS_SAI_PERIPH(PERIPH) ((PERIPH) == SAI1) - -#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \ - ((PERIPH) == SAI1_Block_B)) - - -/** @defgroup SAI_Block_Mode - * @{ - */ -#define SAI_Mode_MasterTx ((uint32_t)0x00000000) -#define SAI_Mode_MasterRx ((uint32_t)0x00000001) -#define SAI_Mode_SlaveTx ((uint32_t)0x00000002) -#define SAI_Mode_SlaveRx ((uint32_t)0x00000003) -#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_Mode_MasterTx) || \ - ((MODE) == SAI_Mode_MasterRx) || \ - ((MODE) == SAI_Mode_SlaveTx) || \ - ((MODE) == SAI_Mode_SlaveRx)) -/** - * @} - */ - -/** @defgroup SAI_Block_Protocol - * @{ - */ - -#define SAI_Free_Protocol ((uint32_t)0x00000000) -#define SAI_SPDIF_Protocol ((uint32_t)SAI_xCR1_PRTCFG_0) -#define SAI_AC97_Protocol ((uint32_t)SAI_xCR1_PRTCFG_1) -#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_Free_Protocol) || \ - ((PROTOCOL) == SAI_SPDIF_Protocol) || \ - ((PROTOCOL) == SAI_AC97_Protocol)) -/** - * @} - */ - -/** @defgroup SAI_Block_Data_Size - * @{ - */ - -#define SAI_DataSize_8b ((uint32_t)0x00000040) -#define SAI_DataSize_10b ((uint32_t)0x00000060) -#define SAI_DataSize_16b ((uint32_t)0x00000080) -#define SAI_DataSize_20b ((uint32_t)0x000000A0) -#define SAI_DataSize_24b ((uint32_t)0x000000C0) -#define SAI_DataSize_32b ((uint32_t)0x000000E0) -#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DataSize_8b) || \ - ((DATASIZE) == SAI_DataSize_10b) || \ - ((DATASIZE) == SAI_DataSize_16b) || \ - ((DATASIZE) == SAI_DataSize_20b) || \ - ((DATASIZE) == SAI_DataSize_24b) || \ - ((DATASIZE) == SAI_DataSize_32b)) -/** - * @} - */ - -/** @defgroup SAI_Block_MSB_LSB_transmission - * @{ - */ - -#define SAI_FirstBit_MSB ((uint32_t)0x00000000) -#define SAI_FirstBit_LSB ((uint32_t)SAI_xCR1_LSBFIRST) -#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FirstBit_MSB) || \ - ((BIT) == SAI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SAI_Block_Clock_Strobing - * @{ - */ - -#define SAI_ClockStrobing_FallingEdge ((uint32_t)0x00000000) -#define SAI_ClockStrobing_RisingEdge ((uint32_t)SAI_xCR1_CKSTR) -#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_ClockStrobing_FallingEdge) || \ - ((CLOCK) == SAI_ClockStrobing_RisingEdge)) -/** - * @} - */ - -/** @defgroup SAI_Block_Synchronization - * @{ - */ - -#define SAI_Asynchronous ((uint32_t)0x00000000) -#define SAI_Synchronous ((uint32_t)SAI_xCR1_SYNCEN_0) -#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_Synchronous) || \ - ((SYNCHRO) == SAI_Asynchronous)) -/** - * @} - */ - -/** @defgroup SAI_Block_Output_Drive - * @{ - */ - -#define SAI_OutputDrive_Disabled ((uint32_t)0x00000000) -#define SAI_OutputDrive_Enabled ((uint32_t)SAI_xCR1_OUTDRIV) -#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OutputDrive_Disabled) || \ - ((DRIVE) == SAI_OutputDrive_Enabled)) -/** - * @} - */ - - - -/** @defgroup SAI_Block_NoDivider - * @{ - */ - -#define SAI_MasterDivider_Enabled ((uint32_t)0x00000000) -#define SAI_MasterDivider_Disabled ((uint32_t)SAI_xCR1_NODIV) -#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MasterDivider_Enabled) || \ - ((NODIVIDER) == SAI_MasterDivider_Disabled)) -/** - * @} - */ - - -/** @defgroup SAI_Block_Master_Divider - * @{ - */ -#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) - -/** - * @} - */ - -/** @defgroup SAI_Block_Frame_Length - * @{ - */ -#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) - -/** - * @} - */ - -/** @defgroup SAI_Block_Active_FrameLength - * @{ - */ -#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) - -/** - * @} - */ - -/** @defgroup SAI_Block_FS_Definition - * @{ - */ - -#define SAI_FS_StartFrame ((uint32_t)0x00000000) -#define I2S_FS_ChannelIdentification ((uint32_t)SAI_xFRCR_FSDEF) -#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_StartFrame) || \ - ((DEFINITION) == I2S_FS_ChannelIdentification)) -/** - * @} - */ - -/** @defgroup SAI_Block_FS_Polarity - * @{ - */ - -#define SAI_FS_ActiveLow ((uint32_t)0x00000000) -#define SAI_FS_ActiveHigh ((uint32_t)SAI_xFRCR_FSPO) -#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ActiveLow) || \ - ((POLARITY) == SAI_FS_ActiveHigh)) -/** - * @} - */ - -/** @defgroup SAI_Block_FS_Offset - * @{ - */ - -#define SAI_FS_FirstBit ((uint32_t)0x00000000) -#define SAI_FS_BeforeFirstBit ((uint32_t)SAI_xFRCR_FSOFF) -#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FirstBit) || \ - ((OFFSET) == SAI_FS_BeforeFirstBit)) -/** - * @} - */ - -/** @defgroup SAI_Block_Slot_FirstBit_Offset - * @{ - */ -#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) - -/** - * @} - */ - - /** @defgroup SAI_Block_Slot_Size - * @{ - */ -#define SAI_SlotSize_DataSize ((uint32_t)0x00000000) -#define SAI_SlotSize_16b ((uint32_t)SAI_xSLOTR_SLOTSZ_0) -#define SAI_SlotSize_32b ((uint32_t)SAI_xSLOTR_SLOTSZ_1) -#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SlotSize_DataSize) || \ - ((SIZE) == SAI_SlotSize_16b) || \ - ((SIZE) == SAI_SlotSize_32b)) - -/** - * @} - */ - -/** @defgroup SAI_Block_Slot_Number - * @{ - */ -#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) - -/** - * @} - */ - -/** @defgroup SAI_Block_Slot_Active - * @{ - */ -#define SAI_Slot_NotActive ((uint32_t)0x00000000) -#define SAI_SlotActive_0 ((uint32_t)0x00010000) -#define SAI_SlotActive_1 ((uint32_t)0x00020000) -#define SAI_SlotActive_2 ((uint32_t)0x00040000) -#define SAI_SlotActive_3 ((uint32_t)0x00080000) -#define SAI_SlotActive_4 ((uint32_t)0x00100000) -#define SAI_SlotActive_5 ((uint32_t)0x00200000) -#define SAI_SlotActive_6 ((uint32_t)0x00400000) -#define SAI_SlotActive_7 ((uint32_t)0x00800000) -#define SAI_SlotActive_8 ((uint32_t)0x01000000) -#define SAI_SlotActive_9 ((uint32_t)0x02000000) -#define SAI_SlotActive_10 ((uint32_t)0x04000000) -#define SAI_SlotActive_11 ((uint32_t)0x08000000) -#define SAI_SlotActive_12 ((uint32_t)0x10000000) -#define SAI_SlotActive_13 ((uint32_t)0x20000000) -#define SAI_SlotActive_14 ((uint32_t)0x40000000) -#define SAI_SlotActive_15 ((uint32_t)0x80000000) -#define SAI_SlotActive_ALL ((uint32_t)0xFFFF0000) - -#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0) - -/** - * @} - */ - -/** @defgroup SAI_Mono_Streo_Mode - * @{ - */ - -#define SAI_MonoMode ((uint32_t)SAI_xCR1_MONO) -#define SAI_StreoMode ((uint32_t)0x00000000) -#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MonoMode) ||\ - ((MODE) == SAI_StreoMode)) -/** - * @} - */ - -/** @defgroup SAI_TRIState_Management - * @{ - */ - -#define SAI_Output_NotReleased ((uint32_t)0x00000000) -#define SAI_Output_Released ((uint32_t)SAI_xCR2_TRIS) -#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_Output_NotReleased) ||\ - ((STATE) == SAI_Output_Released)) -/** - * @} - */ - -/** @defgroup SAI_Block_Fifo_Threshold - * @{ - */ - -#define SAI_Threshold_FIFOEmpty ((uint32_t)0x00000000) -#define SAI_FIFOThreshold_1QuarterFull ((uint32_t)0x00000001) -#define SAI_FIFOThreshold_HalfFull ((uint32_t)0x00000002) -#define SAI_FIFOThreshold_3QuartersFull ((uint32_t)0x00000003) -#define SAI_FIFOThreshold_Full ((uint32_t)0x00000004) -#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_Threshold_FIFOEmpty) || \ - ((THRESHOLD) == SAI_FIFOThreshold_1QuarterFull) || \ - ((THRESHOLD) == SAI_FIFOThreshold_HalfFull) || \ - ((THRESHOLD) == SAI_FIFOThreshold_3QuartersFull) || \ - ((THRESHOLD) == SAI_FIFOThreshold_Full)) -/** - * @} - */ - -/** @defgroup SAI_Block_Companding_Mode - * @{ - */ - -#define SAI_NoCompanding ((uint32_t)0x00000000) -#define SAI_ULaw_1CPL_Companding ((uint32_t)0x00008000) -#define SAI_ALaw_1CPL_Companding ((uint32_t)0x0000C000) -#define SAI_ULaw_2CPL_Companding ((uint32_t)0x0000A000) -#define SAI_ALaw_2CPL_Companding ((uint32_t)0x0000E000) -#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NoCompanding) || \ - ((MODE) == SAI_ULaw_1CPL_Companding) || \ - ((MODE) == SAI_ALaw_1CPL_Companding) || \ - ((MODE) == SAI_ULaw_2CPL_Companding) || \ - ((MODE) == SAI_ALaw_2CPL_Companding)) -/** - * @} - */ - -/** @defgroup SAI_Block_Mute_Value - * @{ - */ - -#define SAI_ZeroValue ((uint32_t)0x00000000) -#define SAI_LastSentValue ((uint32_t)SAI_xCR2_MUTEVAL) -#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZeroValue) || \ - ((VALUE) == SAI_LastSentValue)) -/** - * @} - */ - -/** @defgroup SAI_Block_Mute_Frame_Counter - * @{ - */ - -#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) - -/** - * @} - */ - -/** @defgroup SAI_Block_Interrupts_Definition - * @{ - */ - -#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) -#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) -#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) -#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) -#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) -#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) -#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) - -#define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \ - ((IT) == SAI_IT_MUTEDET) || \ - ((IT) == SAI_IT_WCKCFG) || \ - ((IT) == SAI_IT_FREQ) || \ - ((IT) == SAI_IT_CNRDY) || \ - ((IT) == SAI_IT_AFSDET) || \ - ((IT) == SAI_IT_LFSDET)) -/** - * @} - */ - -/** @defgroup SAI_Block_Flags_Definition - * @{ - */ - -#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) -#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) -#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) -#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) -#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) -#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) -#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) - -#define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \ - ((FLAG) == SAI_FLAG_MUTEDET) || \ - ((FLAG) == SAI_FLAG_WCKCFG) || \ - ((FLAG) == SAI_FLAG_FREQ) || \ - ((FLAG) == SAI_FLAG_CNRDY) || \ - ((FLAG) == SAI_FLAG_AFSDET) || \ - ((FLAG) == SAI_FLAG_LFSDET)) - -#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \ - ((FLAG) == SAI_FLAG_MUTEDET) || \ - ((FLAG) == SAI_FLAG_WCKCFG) || \ - ((FLAG) == SAI_FLAG_FREQ) || \ - ((FLAG) == SAI_FLAG_CNRDY) || \ - ((FLAG) == SAI_FLAG_AFSDET) || \ - ((FLAG) == SAI_FLAG_LFSDET)) -/** - * @} - */ - -/** @defgroup SAI_Block_Fifo_Status_Level - * @{ - */ -#define SAI_FIFOStatus_Empty ((uint32_t)0x00000000) -#define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000) -#define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000) -#define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000) -#define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000) -#define SAI_FIFOStatus_Full ((uint32_t)0x00050000) - -#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \ - ((STATUS) == SAI_FIFOStatus_HalfFull) || \ - ((STATUS) == SAI_FIFOStatus_1QuarterFull) || \ - ((STATUS) == SAI_FIFOStatus_3QuartersFull) || \ - ((STATUS) == SAI_FIFOStatus_Full) || \ - ((STATUS) == SAI_FIFOStatus_Empty)) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the SAI configuration to the default reset state *****/ -void SAI_DeInit(SAI_TypeDef* SAIx); - -/* Initialization and Configuration functions *********************************/ -void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct); -void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct); -void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct); -void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct); -void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct); -void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct); - -void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); -void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode); -void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState); -void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode); -void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); -void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue); -void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter); -void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x); - -/* Data transfers functions ***************************************************/ -void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data); -uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x); - -/* DMA transfers management functions *****************************************/ -void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState); -FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); -void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); -ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); -void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); -FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x); -uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_SAI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_sai.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the SAI + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_SAI_H +#define __STM32F4xx_SAI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SAI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief SAI Block Init structure definition + */ + +typedef struct +{ + uint32_t SAI_AudioMode; /*!< Specifies the SAI Block Audio Mode. + This parameter can be a value of @ref SAI_Block_Mode */ + + uint32_t SAI_Protocol; /*!< Specifies the SAI Block Protocol. + This parameter can be a value of @ref SAI_Block_Protocol */ + + uint32_t SAI_DataSize; /*!< Specifies the SAI Block data size. + This parameter can be a value of @ref SAI_Block_Data_Size + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission + @note this value has no meaning when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. + This parameter can be a value of @ref SAI_Block_Clock_Strobing */ + + uint32_t SAI_Synchro; /*!< Specifies SAI Block synchronization + This parameter can be a value of @ref SAI_Block_Synchronization */ + + uint32_t SAI_OUTDRIV; /*!< Specifies when SAI Block outputs are driven. + This parameter can be a value of @ref SAI_Block_Output_Drive + @note this value has to be set before enabling the audio block + but after the audio block configuration. */ + + uint32_t SAI_NoDivider; /*!< Specifies whether Master Clock will be divided or not. + This parameter can be a value of @ref SAI_Block_NoDivider */ + + uint32_t SAI_MasterDivider; /*!< Specifies SAI Block Master Clock Divider. + @note the Master Clock Frequency is calculated accordingly to the + following formula : MCLK_x = SAI_CK_x/(MCKDIV[3:0]*2)*/ + + uint32_t SAI_FIFOThreshold; /*!< Specifies SAI Block FIFO Threshold. + This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ +}SAI_InitTypeDef; + +/** + * @brief SAI Block Frame Init structure definition + */ + +typedef struct +{ + + uint32_t SAI_FrameLength; /*!< Specifies the Frame Length, the number of SCK clocks + for each audio frame. + This parameter must be a number between 8 and 256. + @note If master Clock MCLK_x pin is declared as an output, the frame length + should be Aligned to a number equal to power of 2 in order to keep + in an audio frame, an integer number of MCLK pulses by bit Clock. + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. + This Parameter specifies the length in number of bit clock (SCK + 1) + of the active level of FS signal in audio frame. + This parameter must be a number between 1 and 128. + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_FSDefinition; /*!< Specifies the Frame Synchronization definition. + This parameter can be a value of @ref SAI_Block_FS_Definition + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_FSPolarity; /*!< Specifies the Frame Synchronization Polarity. + This parameter can be a value of @ref SAI_Block_FS_Polarity + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_FSOffset; /*!< Specifies the Frame Synchronization Offset. + This parameter can be a value of @ref SAI_Block_FS_Offset + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + +}SAI_FrameInitTypeDef; + +/** + * @brief SAI Block Slot Init Structure definition + */ + +typedef struct +{ + uint32_t SAI_FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot. + This parameter must be a number between 0 and 24. + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_SlotSize; /*!< Specifies the Slot Size. + This parameter can be a value of @ref SAI_Block_Slot_Size + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_SlotNumber; /*!< Specifies the number of slot in the audio frame. + This parameter must be a number between 1 and 16. + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_SlotActive; /*!< Specifies the slots in audio frame that will be activated. + This parameter can be a value of @ ref SAI_Block_Slot_Active + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ +}SAI_SlotInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SAI_Exported_Constants + * @{ + */ + +#define IS_SAI_PERIPH(PERIPH) ((PERIPH) == SAI1) + +#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \ + ((PERIPH) == SAI1_Block_B)) + + +/** @defgroup SAI_Block_Mode + * @{ + */ +#define SAI_Mode_MasterTx ((uint32_t)0x00000000) +#define SAI_Mode_MasterRx ((uint32_t)0x00000001) +#define SAI_Mode_SlaveTx ((uint32_t)0x00000002) +#define SAI_Mode_SlaveRx ((uint32_t)0x00000003) +#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_Mode_MasterTx) || \ + ((MODE) == SAI_Mode_MasterRx) || \ + ((MODE) == SAI_Mode_SlaveTx) || \ + ((MODE) == SAI_Mode_SlaveRx)) +/** + * @} + */ + +/** @defgroup SAI_Block_Protocol + * @{ + */ + +#define SAI_Free_Protocol ((uint32_t)0x00000000) +#define SAI_SPDIF_Protocol ((uint32_t)SAI_xCR1_PRTCFG_0) +#define SAI_AC97_Protocol ((uint32_t)SAI_xCR1_PRTCFG_1) +#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_Free_Protocol) || \ + ((PROTOCOL) == SAI_SPDIF_Protocol) || \ + ((PROTOCOL) == SAI_AC97_Protocol)) +/** + * @} + */ + +/** @defgroup SAI_Block_Data_Size + * @{ + */ + +#define SAI_DataSize_8b ((uint32_t)0x00000040) +#define SAI_DataSize_10b ((uint32_t)0x00000060) +#define SAI_DataSize_16b ((uint32_t)0x00000080) +#define SAI_DataSize_20b ((uint32_t)0x000000A0) +#define SAI_DataSize_24b ((uint32_t)0x000000C0) +#define SAI_DataSize_32b ((uint32_t)0x000000E0) +#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DataSize_8b) || \ + ((DATASIZE) == SAI_DataSize_10b) || \ + ((DATASIZE) == SAI_DataSize_16b) || \ + ((DATASIZE) == SAI_DataSize_20b) || \ + ((DATASIZE) == SAI_DataSize_24b) || \ + ((DATASIZE) == SAI_DataSize_32b)) +/** + * @} + */ + +/** @defgroup SAI_Block_MSB_LSB_transmission + * @{ + */ + +#define SAI_FirstBit_MSB ((uint32_t)0x00000000) +#define SAI_FirstBit_LSB ((uint32_t)SAI_xCR1_LSBFIRST) +#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FirstBit_MSB) || \ + ((BIT) == SAI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup SAI_Block_Clock_Strobing + * @{ + */ + +#define SAI_ClockStrobing_FallingEdge ((uint32_t)0x00000000) +#define SAI_ClockStrobing_RisingEdge ((uint32_t)SAI_xCR1_CKSTR) +#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_ClockStrobing_FallingEdge) || \ + ((CLOCK) == SAI_ClockStrobing_RisingEdge)) +/** + * @} + */ + +/** @defgroup SAI_Block_Synchronization + * @{ + */ + +#define SAI_Asynchronous ((uint32_t)0x00000000) +#define SAI_Synchronous ((uint32_t)SAI_xCR1_SYNCEN_0) +#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_Synchronous) || \ + ((SYNCHRO) == SAI_Asynchronous)) +/** + * @} + */ + +/** @defgroup SAI_Block_Output_Drive + * @{ + */ + +#define SAI_OutputDrive_Disabled ((uint32_t)0x00000000) +#define SAI_OutputDrive_Enabled ((uint32_t)SAI_xCR1_OUTDRIV) +#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OutputDrive_Disabled) || \ + ((DRIVE) == SAI_OutputDrive_Enabled)) +/** + * @} + */ + + + +/** @defgroup SAI_Block_NoDivider + * @{ + */ + +#define SAI_MasterDivider_Enabled ((uint32_t)0x00000000) +#define SAI_MasterDivider_Disabled ((uint32_t)SAI_xCR1_NODIV) +#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MasterDivider_Enabled) || \ + ((NODIVIDER) == SAI_MasterDivider_Disabled)) +/** + * @} + */ + + +/** @defgroup SAI_Block_Master_Divider + * @{ + */ +#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) + +/** + * @} + */ + +/** @defgroup SAI_Block_Frame_Length + * @{ + */ +#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) + +/** + * @} + */ + +/** @defgroup SAI_Block_Active_FrameLength + * @{ + */ +#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) + +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Definition + * @{ + */ + +#define SAI_FS_StartFrame ((uint32_t)0x00000000) +#define I2S_FS_ChannelIdentification ((uint32_t)SAI_xFRCR_FSDEF) +#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_StartFrame) || \ + ((DEFINITION) == I2S_FS_ChannelIdentification)) +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Polarity + * @{ + */ + +#define SAI_FS_ActiveLow ((uint32_t)0x00000000) +#define SAI_FS_ActiveHigh ((uint32_t)SAI_xFRCR_FSPO) +#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ActiveLow) || \ + ((POLARITY) == SAI_FS_ActiveHigh)) +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Offset + * @{ + */ + +#define SAI_FS_FirstBit ((uint32_t)0x00000000) +#define SAI_FS_BeforeFirstBit ((uint32_t)SAI_xFRCR_FSOFF) +#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FirstBit) || \ + ((OFFSET) == SAI_FS_BeforeFirstBit)) +/** + * @} + */ + +/** @defgroup SAI_Block_Slot_FirstBit_Offset + * @{ + */ +#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) + +/** + * @} + */ + + /** @defgroup SAI_Block_Slot_Size + * @{ + */ +#define SAI_SlotSize_DataSize ((uint32_t)0x00000000) +#define SAI_SlotSize_16b ((uint32_t)SAI_xSLOTR_SLOTSZ_0) +#define SAI_SlotSize_32b ((uint32_t)SAI_xSLOTR_SLOTSZ_1) +#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SlotSize_DataSize) || \ + ((SIZE) == SAI_SlotSize_16b) || \ + ((SIZE) == SAI_SlotSize_32b)) + +/** + * @} + */ + +/** @defgroup SAI_Block_Slot_Number + * @{ + */ +#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) + +/** + * @} + */ + +/** @defgroup SAI_Block_Slot_Active + * @{ + */ +#define SAI_Slot_NotActive ((uint32_t)0x00000000) +#define SAI_SlotActive_0 ((uint32_t)0x00010000) +#define SAI_SlotActive_1 ((uint32_t)0x00020000) +#define SAI_SlotActive_2 ((uint32_t)0x00040000) +#define SAI_SlotActive_3 ((uint32_t)0x00080000) +#define SAI_SlotActive_4 ((uint32_t)0x00100000) +#define SAI_SlotActive_5 ((uint32_t)0x00200000) +#define SAI_SlotActive_6 ((uint32_t)0x00400000) +#define SAI_SlotActive_7 ((uint32_t)0x00800000) +#define SAI_SlotActive_8 ((uint32_t)0x01000000) +#define SAI_SlotActive_9 ((uint32_t)0x02000000) +#define SAI_SlotActive_10 ((uint32_t)0x04000000) +#define SAI_SlotActive_11 ((uint32_t)0x08000000) +#define SAI_SlotActive_12 ((uint32_t)0x10000000) +#define SAI_SlotActive_13 ((uint32_t)0x20000000) +#define SAI_SlotActive_14 ((uint32_t)0x40000000) +#define SAI_SlotActive_15 ((uint32_t)0x80000000) +#define SAI_SlotActive_ALL ((uint32_t)0xFFFF0000) + +#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0) + +/** + * @} + */ + +/** @defgroup SAI_Mono_Streo_Mode + * @{ + */ + +#define SAI_MonoMode ((uint32_t)SAI_xCR1_MONO) +#define SAI_StreoMode ((uint32_t)0x00000000) +#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MonoMode) ||\ + ((MODE) == SAI_StreoMode)) +/** + * @} + */ + +/** @defgroup SAI_TRIState_Management + * @{ + */ + +#define SAI_Output_NotReleased ((uint32_t)0x00000000) +#define SAI_Output_Released ((uint32_t)SAI_xCR2_TRIS) +#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_Output_NotReleased) ||\ + ((STATE) == SAI_Output_Released)) +/** + * @} + */ + +/** @defgroup SAI_Block_Fifo_Threshold + * @{ + */ + +#define SAI_Threshold_FIFOEmpty ((uint32_t)0x00000000) +#define SAI_FIFOThreshold_1QuarterFull ((uint32_t)0x00000001) +#define SAI_FIFOThreshold_HalfFull ((uint32_t)0x00000002) +#define SAI_FIFOThreshold_3QuartersFull ((uint32_t)0x00000003) +#define SAI_FIFOThreshold_Full ((uint32_t)0x00000004) +#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_Threshold_FIFOEmpty) || \ + ((THRESHOLD) == SAI_FIFOThreshold_1QuarterFull) || \ + ((THRESHOLD) == SAI_FIFOThreshold_HalfFull) || \ + ((THRESHOLD) == SAI_FIFOThreshold_3QuartersFull) || \ + ((THRESHOLD) == SAI_FIFOThreshold_Full)) +/** + * @} + */ + +/** @defgroup SAI_Block_Companding_Mode + * @{ + */ + +#define SAI_NoCompanding ((uint32_t)0x00000000) +#define SAI_ULaw_1CPL_Companding ((uint32_t)0x00008000) +#define SAI_ALaw_1CPL_Companding ((uint32_t)0x0000C000) +#define SAI_ULaw_2CPL_Companding ((uint32_t)0x0000A000) +#define SAI_ALaw_2CPL_Companding ((uint32_t)0x0000E000) +#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NoCompanding) || \ + ((MODE) == SAI_ULaw_1CPL_Companding) || \ + ((MODE) == SAI_ALaw_1CPL_Companding) || \ + ((MODE) == SAI_ULaw_2CPL_Companding) || \ + ((MODE) == SAI_ALaw_2CPL_Companding)) +/** + * @} + */ + +/** @defgroup SAI_Block_Mute_Value + * @{ + */ + +#define SAI_ZeroValue ((uint32_t)0x00000000) +#define SAI_LastSentValue ((uint32_t)SAI_xCR2_MUTEVAL) +#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZeroValue) || \ + ((VALUE) == SAI_LastSentValue)) +/** + * @} + */ + +/** @defgroup SAI_Block_Mute_Frame_Counter + * @{ + */ + +#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) + +/** + * @} + */ + +/** @defgroup SAI_Block_Interrupts_Definition + * @{ + */ + +#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) +#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) +#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) +#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) +#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) +#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) +#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) + +#define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \ + ((IT) == SAI_IT_MUTEDET) || \ + ((IT) == SAI_IT_WCKCFG) || \ + ((IT) == SAI_IT_FREQ) || \ + ((IT) == SAI_IT_CNRDY) || \ + ((IT) == SAI_IT_AFSDET) || \ + ((IT) == SAI_IT_LFSDET)) +/** + * @} + */ + +/** @defgroup SAI_Block_Flags_Definition + * @{ + */ + +#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) +#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) +#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) +#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) +#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) +#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) +#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) + +#define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \ + ((FLAG) == SAI_FLAG_MUTEDET) || \ + ((FLAG) == SAI_FLAG_WCKCFG) || \ + ((FLAG) == SAI_FLAG_FREQ) || \ + ((FLAG) == SAI_FLAG_CNRDY) || \ + ((FLAG) == SAI_FLAG_AFSDET) || \ + ((FLAG) == SAI_FLAG_LFSDET)) + +#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \ + ((FLAG) == SAI_FLAG_MUTEDET) || \ + ((FLAG) == SAI_FLAG_WCKCFG) || \ + ((FLAG) == SAI_FLAG_FREQ) || \ + ((FLAG) == SAI_FLAG_CNRDY) || \ + ((FLAG) == SAI_FLAG_AFSDET) || \ + ((FLAG) == SAI_FLAG_LFSDET)) +/** + * @} + */ + +/** @defgroup SAI_Block_Fifo_Status_Level + * @{ + */ +#define SAI_FIFOStatus_Empty ((uint32_t)0x00000000) +#define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000) +#define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000) +#define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000) +#define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000) +#define SAI_FIFOStatus_Full ((uint32_t)0x00050000) + +#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \ + ((STATUS) == SAI_FIFOStatus_HalfFull) || \ + ((STATUS) == SAI_FIFOStatus_1QuarterFull) || \ + ((STATUS) == SAI_FIFOStatus_3QuartersFull) || \ + ((STATUS) == SAI_FIFOStatus_Full) || \ + ((STATUS) == SAI_FIFOStatus_Empty)) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the SAI configuration to the default reset state *****/ +void SAI_DeInit(SAI_TypeDef* SAIx); + +/* Initialization and Configuration functions *********************************/ +void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct); +void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct); +void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct); +void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct); +void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct); +void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct); + +void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); +void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode); +void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState); +void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode); +void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); +void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue); +void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter); +void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x); + +/* Data transfers functions ***************************************************/ +void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data); +uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x); + +/* DMA transfers management functions *****************************************/ +void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState); +FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); +void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); +ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); +void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); +FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x); +uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_SAI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h index 1fa3b3bc4..485362ed1 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h @@ -1,536 +1,536 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sdio.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the SDIO firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SDIO_H -#define __STM32F4xx_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - -typedef struct -{ - uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ - -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ - ((EDGE) == SDIO_ClockEdge_Falling)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass - * @{ - */ - -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ - ((BYPASS) == SDIO_ClockBypass_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Power_Save - * @{ - */ - -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ - ((SAVE) == SDIO_ClockPowerSave_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Bus_Wide - * @{ - */ - -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ - ((WIDE) == SDIO_BusWide_8b)) - -/** - * @} - */ - -/** @defgroup SDIO_Hardware_Flow_Control - * @{ - */ - -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ - ((CONTROL) == SDIO_HardwareFlowControl_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ - -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) -#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) -/** - * @} - */ - - -/** @defgroup SDIO_Interrupt_sources - * @{ - */ - -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup SDIO_Command_Index - * @{ - */ - -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ - -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ - ((RESPONSE) == SDIO_Response_Short) || \ - ((RESPONSE) == SDIO_Response_Long)) -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ - -#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ -#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ -#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ - ((WAIT) == SDIO_Wait_Pend)) -/** - * @} - */ - -/** @defgroup SDIO_CPSM_State - * @{ - */ - -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ - -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDIO_Data_Length - * @{ - */ - -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ - -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ - ((SIZE) == SDIO_DataBlockSize_2b) || \ - ((SIZE) == SDIO_DataBlockSize_4b) || \ - ((SIZE) == SDIO_DataBlockSize_8b) || \ - ((SIZE) == SDIO_DataBlockSize_16b) || \ - ((SIZE) == SDIO_DataBlockSize_32b) || \ - ((SIZE) == SDIO_DataBlockSize_64b) || \ - ((SIZE) == SDIO_DataBlockSize_128b) || \ - ((SIZE) == SDIO_DataBlockSize_256b) || \ - ((SIZE) == SDIO_DataBlockSize_512b) || \ - ((SIZE) == SDIO_DataBlockSize_1024b) || \ - ((SIZE) == SDIO_DataBlockSize_2048b) || \ - ((SIZE) == SDIO_DataBlockSize_4096b) || \ - ((SIZE) == SDIO_DataBlockSize_8192b) || \ - ((SIZE) == SDIO_DataBlockSize_16384b)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ - -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ - ((DIR) == SDIO_TransferDir_ToSDIO)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Type - * @{ - */ - -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ - ((MODE) == SDIO_TransferMode_Block)) -/** - * @} - */ - -/** @defgroup SDIO_DPSM_State - * @{ - */ - -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Flags - * @{ - */ - -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_TXUNDERR) || \ - ((FLAG) == SDIO_FLAG_RXOVERR) || \ - ((FLAG) == SDIO_FLAG_CMDREND) || \ - ((FLAG) == SDIO_FLAG_CMDSENT) || \ - ((FLAG) == SDIO_FLAG_DATAEND) || \ - ((FLAG) == SDIO_FLAG_STBITERR) || \ - ((FLAG) == SDIO_FLAG_DBCKEND) || \ - ((FLAG) == SDIO_FLAG_CMDACT) || \ - ((FLAG) == SDIO_FLAG_TXACT) || \ - ((FLAG) == SDIO_FLAG_RXACT) || \ - ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOF) || \ - ((FLAG) == SDIO_FLAG_RXFIFOF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOE) || \ - ((FLAG) == SDIO_FLAG_TXDAVL) || \ - ((FLAG) == SDIO_FLAG_RXDAVL) || \ - ((FLAG) == SDIO_FLAG_SDIOIT) || \ - ((FLAG) == SDIO_FLAG_CEATAEND)) - -#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) - -#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ - ((IT) == SDIO_IT_DCRCFAIL) || \ - ((IT) == SDIO_IT_CTIMEOUT) || \ - ((IT) == SDIO_IT_DTIMEOUT) || \ - ((IT) == SDIO_IT_TXUNDERR) || \ - ((IT) == SDIO_IT_RXOVERR) || \ - ((IT) == SDIO_IT_CMDREND) || \ - ((IT) == SDIO_IT_CMDSENT) || \ - ((IT) == SDIO_IT_DATAEND) || \ - ((IT) == SDIO_IT_STBITERR) || \ - ((IT) == SDIO_IT_DBCKEND) || \ - ((IT) == SDIO_IT_CMDACT) || \ - ((IT) == SDIO_IT_TXACT) || \ - ((IT) == SDIO_IT_RXACT) || \ - ((IT) == SDIO_IT_TXFIFOHE) || \ - ((IT) == SDIO_IT_RXFIFOHF) || \ - ((IT) == SDIO_IT_TXFIFOF) || \ - ((IT) == SDIO_IT_RXFIFOF) || \ - ((IT) == SDIO_IT_TXFIFOE) || \ - ((IT) == SDIO_IT_RXFIFOE) || \ - ((IT) == SDIO_IT_TXDAVL) || \ - ((IT) == SDIO_IT_RXDAVL) || \ - ((IT) == SDIO_IT_SDIOIT) || \ - ((IT) == SDIO_IT_CEATAEND)) - -#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ - -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ - ((MODE) == SDIO_ReadWaitMode_DATA2)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/* Function used to set the SDIO configuration to the default reset state ****/ -void SDIO_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); - -/* Command path state machine (CPSM) management functions *********************/ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); - -/* Data path state machine (DPSM) management functions ************************/ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); - -/* SDIO IO Cards mode management functions ************************************/ -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); - -/* CE-ATA mode management functions *******************************************/ -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void SDIO_DMACmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_SDIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_sdio.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the SDIO firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_SDIO_H +#define __STM32F4xx_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_sources + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/* Function used to set the SDIO configuration to the default reset state ****/ +void SDIO_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); + +/* Command path state machine (CPSM) management functions *********************/ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); + +/* Data path state machine (DPSM) management functions ************************/ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); + +/* SDIO IO Cards mode management functions ************************************/ +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); + +/* CE-ATA mode management functions *******************************************/ +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); + +/* DMA transfers management functions *****************************************/ +void SDIO_DMACmd(FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_SDIO_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h index 11997749d..fda14d687 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h @@ -1,549 +1,549 @@ -/** - ****************************************************************************** - * @file stm32f4xx_spi.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the SPI - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SPI_H -#define __STM32F4xx_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == SPI4) || \ - ((PERIPH) == SPI5) || \ - ((PERIPH) == SPI6)) - -#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == SPI4) || \ - ((PERIPH) == SPI5) || \ - ((PERIPH) == SPI6) || \ - ((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - -#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx)|| \ - ((MODE) == I2S_Mode_MasterRx)) -/** - * @} - */ - - -/** @defgroup SPI_I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup SPI_I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define I2S_IT_UDR ((uint8_t)0x53) -#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) - -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) - -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) - -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) - -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ - ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ - ((IT) == SPI_I2S_IT_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) - -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ - ((FLAG) == SPI_I2S_FLAG_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** @defgroup SPI_I2S_Legacy - * @{ - */ - -#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx -#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx -#define SPI_IT_TXE SPI_I2S_IT_TXE -#define SPI_IT_RXNE SPI_I2S_IT_RXNE -#define SPI_IT_ERR SPI_I2S_IT_ERR -#define SPI_IT_OVR SPI_I2S_IT_OVR -#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE -#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE -#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR -#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY -#define SPI_DeInit SPI_I2S_DeInit -#define SPI_ITConfig SPI_I2S_ITConfig -#define SPI_DMACmd SPI_I2S_DMACmd -#define SPI_SendData SPI_I2S_SendData -#define SPI_ReceiveData SPI_I2S_ReceiveData -#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus -#define SPI_ClearFlag SPI_I2S_ClearFlag -#define SPI_GetITStatus SPI_I2S_GetITStatus -#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the SPI configuration to the default reset state *****/ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); - -/* Initialization and Configuration functions *********************************/ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - -void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct); - -/* Data transfers functions ***************************************************/ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); - -/* Hardware CRC Calculation functions *****************************************/ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); - -/* DMA transfers management functions *****************************************/ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_spi.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the SPI + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_SPI_H +#define __STM32F4xx_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3) || \ + ((PERIPH) == SPI4) || \ + ((PERIPH) == SPI5) || \ + ((PERIPH) == SPI6)) + +#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3) || \ + ((PERIPH) == SPI4) || \ + ((PERIPH) == SPI5) || \ + ((PERIPH) == SPI6) || \ + ((PERIPH) == I2S2ext) || \ + ((PERIPH) == I2S3ext)) + +#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3) || \ + ((PERIPH) == I2S2ext) || \ + ((PERIPH) == I2S3ext)) + +#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \ + ((PERIPH) == I2S3ext)) + + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx)|| \ + ((MODE) == I2S_Mode_MasterRx)) +/** + * @} + */ + + +/** @defgroup SPI_I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup SPI_I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ + ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define I2S_IT_UDR ((uint8_t)0x53) +#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) + +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) + +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) + +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) + +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ + ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ + ((IT) == SPI_I2S_IT_TIFRFE)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) + +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ + ((FLAG) == SPI_I2S_FLAG_TIFRFE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** @defgroup SPI_I2S_Legacy + * @{ + */ + +#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx +#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx +#define SPI_IT_TXE SPI_I2S_IT_TXE +#define SPI_IT_RXNE SPI_I2S_IT_RXNE +#define SPI_IT_ERR SPI_I2S_IT_ERR +#define SPI_IT_OVR SPI_I2S_IT_OVR +#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE +#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE +#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR +#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY +#define SPI_DeInit SPI_I2S_DeInit +#define SPI_ITConfig SPI_I2S_ITConfig +#define SPI_DMACmd SPI_I2S_DMACmd +#define SPI_SendData SPI_I2S_SendData +#define SPI_ReceiveData SPI_I2S_ReceiveData +#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus +#define SPI_ClearFlag SPI_I2S_ClearFlag +#define SPI_GetITStatus SPI_I2S_GetITStatus +#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the SPI configuration to the default reset state *****/ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); + +/* Initialization and Configuration functions *********************************/ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + +void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct); + +/* Data transfers functions ***************************************************/ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); + +/* Hardware CRC Calculation functions *****************************************/ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); + +/* DMA transfers management functions *****************************************/ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_SPI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h index 181c9d9e5..efbf5b2bd 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h @@ -1,210 +1,210 @@ -/** - ****************************************************************************** - * @file stm32f4xx_syscfg.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the SYSCFG firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SYSCFG_H -#define __STM32F4xx_SYSCFG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SYSCFG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SYSCFG_Exported_Constants - * @{ - */ - -/** @defgroup SYSCFG_EXTI_Port_Sources - * @{ - */ -#define EXTI_PortSourceGPIOA ((uint8_t)0x00) -#define EXTI_PortSourceGPIOB ((uint8_t)0x01) -#define EXTI_PortSourceGPIOC ((uint8_t)0x02) -#define EXTI_PortSourceGPIOD ((uint8_t)0x03) -#define EXTI_PortSourceGPIOE ((uint8_t)0x04) -#define EXTI_PortSourceGPIOF ((uint8_t)0x05) -#define EXTI_PortSourceGPIOG ((uint8_t)0x06) -#define EXTI_PortSourceGPIOH ((uint8_t)0x07) -#define EXTI_PortSourceGPIOI ((uint8_t)0x08) -#define EXTI_PortSourceGPIOJ ((uint8_t)0x09) -#define EXTI_PortSourceGPIOK ((uint8_t)0x0A) - -#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOI) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOK)) - -/** - * @} - */ - - -/** @defgroup SYSCFG_EXTI_Pin_Sources - * @{ - */ -#define EXTI_PinSource0 ((uint8_t)0x00) -#define EXTI_PinSource1 ((uint8_t)0x01) -#define EXTI_PinSource2 ((uint8_t)0x02) -#define EXTI_PinSource3 ((uint8_t)0x03) -#define EXTI_PinSource4 ((uint8_t)0x04) -#define EXTI_PinSource5 ((uint8_t)0x05) -#define EXTI_PinSource6 ((uint8_t)0x06) -#define EXTI_PinSource7 ((uint8_t)0x07) -#define EXTI_PinSource8 ((uint8_t)0x08) -#define EXTI_PinSource9 ((uint8_t)0x09) -#define EXTI_PinSource10 ((uint8_t)0x0A) -#define EXTI_PinSource11 ((uint8_t)0x0B) -#define EXTI_PinSource12 ((uint8_t)0x0C) -#define EXTI_PinSource13 ((uint8_t)0x0D) -#define EXTI_PinSource14 ((uint8_t)0x0E) -#define EXTI_PinSource15 ((uint8_t)0x0F) -#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ - ((PINSOURCE) == EXTI_PinSource1) || \ - ((PINSOURCE) == EXTI_PinSource2) || \ - ((PINSOURCE) == EXTI_PinSource3) || \ - ((PINSOURCE) == EXTI_PinSource4) || \ - ((PINSOURCE) == EXTI_PinSource5) || \ - ((PINSOURCE) == EXTI_PinSource6) || \ - ((PINSOURCE) == EXTI_PinSource7) || \ - ((PINSOURCE) == EXTI_PinSource8) || \ - ((PINSOURCE) == EXTI_PinSource9) || \ - ((PINSOURCE) == EXTI_PinSource10) || \ - ((PINSOURCE) == EXTI_PinSource11) || \ - ((PINSOURCE) == EXTI_PinSource12) || \ - ((PINSOURCE) == EXTI_PinSource13) || \ - ((PINSOURCE) == EXTI_PinSource14) || \ - ((PINSOURCE) == EXTI_PinSource15)) -/** - * @} - */ - - -/** @defgroup SYSCFG_Memory_Remap_Config - * @{ - */ -#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) -#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) -#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) -#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04) - -#if defined (STM32F40_41xxx) -#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_FSMC)) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F401xx) || defined (STM32F411xE) -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM)) -#endif /* STM32F401xx || STM32F411xE */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_FMC)) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -/** - * @} - */ - - -/** @defgroup SYSCFG_ETHERNET_Media_Interface - * @{ - */ -#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) -#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) - -#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ - ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void SYSCFG_DeInit(void); -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); -void SYSCFG_MemorySwappingBank(FunctionalState NewState); -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); -void SYSCFG_CompensationCellCmd(FunctionalState NewState); -FlagStatus SYSCFG_GetCompensationCellStatus(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_SYSCFG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_syscfg.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the SYSCFG firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_SYSCFG_H +#define __STM32F4xx_SYSCFG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SYSCFG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SYSCFG_Exported_Constants + * @{ + */ + +/** @defgroup SYSCFG_EXTI_Port_Sources + * @{ + */ +#define EXTI_PortSourceGPIOA ((uint8_t)0x00) +#define EXTI_PortSourceGPIOB ((uint8_t)0x01) +#define EXTI_PortSourceGPIOC ((uint8_t)0x02) +#define EXTI_PortSourceGPIOD ((uint8_t)0x03) +#define EXTI_PortSourceGPIOE ((uint8_t)0x04) +#define EXTI_PortSourceGPIOF ((uint8_t)0x05) +#define EXTI_PortSourceGPIOG ((uint8_t)0x06) +#define EXTI_PortSourceGPIOH ((uint8_t)0x07) +#define EXTI_PortSourceGPIOI ((uint8_t)0x08) +#define EXTI_PortSourceGPIOJ ((uint8_t)0x09) +#define EXTI_PortSourceGPIOK ((uint8_t)0x0A) + +#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOI) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOK)) + +/** + * @} + */ + + +/** @defgroup SYSCFG_EXTI_Pin_Sources + * @{ + */ +#define EXTI_PinSource0 ((uint8_t)0x00) +#define EXTI_PinSource1 ((uint8_t)0x01) +#define EXTI_PinSource2 ((uint8_t)0x02) +#define EXTI_PinSource3 ((uint8_t)0x03) +#define EXTI_PinSource4 ((uint8_t)0x04) +#define EXTI_PinSource5 ((uint8_t)0x05) +#define EXTI_PinSource6 ((uint8_t)0x06) +#define EXTI_PinSource7 ((uint8_t)0x07) +#define EXTI_PinSource8 ((uint8_t)0x08) +#define EXTI_PinSource9 ((uint8_t)0x09) +#define EXTI_PinSource10 ((uint8_t)0x0A) +#define EXTI_PinSource11 ((uint8_t)0x0B) +#define EXTI_PinSource12 ((uint8_t)0x0C) +#define EXTI_PinSource13 ((uint8_t)0x0D) +#define EXTI_PinSource14 ((uint8_t)0x0E) +#define EXTI_PinSource15 ((uint8_t)0x0F) +#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ + ((PINSOURCE) == EXTI_PinSource1) || \ + ((PINSOURCE) == EXTI_PinSource2) || \ + ((PINSOURCE) == EXTI_PinSource3) || \ + ((PINSOURCE) == EXTI_PinSource4) || \ + ((PINSOURCE) == EXTI_PinSource5) || \ + ((PINSOURCE) == EXTI_PinSource6) || \ + ((PINSOURCE) == EXTI_PinSource7) || \ + ((PINSOURCE) == EXTI_PinSource8) || \ + ((PINSOURCE) == EXTI_PinSource9) || \ + ((PINSOURCE) == EXTI_PinSource10) || \ + ((PINSOURCE) == EXTI_PinSource11) || \ + ((PINSOURCE) == EXTI_PinSource12) || \ + ((PINSOURCE) == EXTI_PinSource13) || \ + ((PINSOURCE) == EXTI_PinSource14) || \ + ((PINSOURCE) == EXTI_PinSource15)) +/** + * @} + */ + + +/** @defgroup SYSCFG_Memory_Remap_Config + * @{ + */ +#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) +#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) +#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) +#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04) + +#if defined (STM32F40_41xxx) +#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02) +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined (STM32F40_41xxx) +#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ + ((REMAP) == SYSCFG_MemoryRemap_FSMC)) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F401xx) || defined (STM32F411xE) +#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM)) +#endif /* STM32F401xx || STM32F411xE */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ + ((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \ + ((REMAP) == SYSCFG_MemoryRemap_FMC)) +#endif /* STM32F427_437xx || STM32F429_439xx */ + +/** + * @} + */ + + +/** @defgroup SYSCFG_ETHERNET_Media_Interface + * @{ + */ +#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) +#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) + +#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ + ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void SYSCFG_DeInit(void); +void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); +void SYSCFG_MemorySwappingBank(FunctionalState NewState); +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); +void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); +void SYSCFG_CompensationCellCmd(FunctionalState NewState); +FlagStatus SYSCFG_GetCompensationCellStatus(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_SYSCFG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h index 3fc4d0db7..7254cb334 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h @@ -1,1150 +1,1150 @@ -/** - ****************************************************************************** - * @file stm32f4xx_tim.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_TIM_H -#define __STM32F4xx_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief TIM Time Base Init structure definition - * @note This structure is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_State */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief BDTR structure definition - * @note This structure is used only with TIM1 and TIM8. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - (((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14))) -/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - ((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14)) - -/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)) -/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8)) -/* LIST4: TIM1 and TIM8 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8)) -/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8)) -/* LIST6: TIM2, TIM5 and TIM11 */ -#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ - ((TIMx) == TIM5) || \ - ((TIMx) == TIM11)) - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) - -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_State - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_State - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define TIM_DMABase_OR ((uint16_t)0x0013) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ -/** @defgroup TIM_Remap - * @{ - */ - -#define TIM2_TIM8_TRGO ((uint16_t)0x0000) -#define TIM2_ETH_PTP ((uint16_t)0x0400) -#define TIM2_USBFS_SOF ((uint16_t)0x0800) -#define TIM2_USBHS_SOF ((uint16_t)0x0C00) - -#define TIM5_GPIO ((uint16_t)0x0000) -#define TIM5_LSI ((uint16_t)0x0040) -#define TIM5_LSE ((uint16_t)0x0080) -#define TIM5_RTC ((uint16_t)0x00C0) - -#define TIM11_GPIO ((uint16_t)0x0000) -#define TIM11_HSE ((uint16_t)0x0002) - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ - ((TIM_REMAP) == TIM2_ETH_PTP)||\ - ((TIM_REMAP) == TIM2_USBFS_SOF)||\ - ((TIM_REMAP) == TIM2_USBHS_SOF)||\ - ((TIM_REMAP) == TIM5_GPIO)||\ - ((TIM_REMAP) == TIM5_LSI)||\ - ((TIM_REMAP) == TIM5_LSE)||\ - ((TIM_REMAP) == TIM5_RTC)||\ - ((TIM_REMAP) == TIM11_GPIO)||\ - ((TIM_REMAP) == TIM11_HSE)) - -/** - * @} - */ -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_Legacy - * @{ - */ - -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* TimeBase management ********************************************************/ -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Output Compare management **************************************************/ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); - -/* Input Capture management ***************************************************/ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); - -/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Interrupts, DMA and flags management ***************************************/ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Clocks management **********************************************************/ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - -/* Synchronization management *************************************************/ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - -/* Specific interface management **********************************************/ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Specific remapping management **********************************************/ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_TIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_tim.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the TIM firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_TIM_H +#define __STM32F4xx_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief TIM Time Base Init structure definition + * @note This structure is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_State */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief BDTR structure definition + * @note This structure is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10) || \ + ((PERIPH) == TIM11) || \ + ((PERIPH) == TIM12) || \ + (((PERIPH) == TIM13) || \ + ((PERIPH) == TIM14))) +/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10) || \ + ((PERIPH) == TIM11) || \ + ((PERIPH) == TIM12) || \ + ((PERIPH) == TIM13) || \ + ((PERIPH) == TIM14)) + +/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)) +/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) +/* LIST4: TIM1 and TIM8 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) +/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8)) +/* LIST6: TIM2, TIM5 and TIM11 */ +#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ + ((TIMx) == TIM5) || \ + ((TIMx) == TIM11)) + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) + +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_State + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_State + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)|| \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define TIM_DMABase_OR ((uint16_t)0x0013) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR) || \ + ((BASE) == TIM_DMABase_OR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ +/** @defgroup TIM_Remap + * @{ + */ + +#define TIM2_TIM8_TRGO ((uint16_t)0x0000) +#define TIM2_ETH_PTP ((uint16_t)0x0400) +#define TIM2_USBFS_SOF ((uint16_t)0x0800) +#define TIM2_USBHS_SOF ((uint16_t)0x0C00) + +#define TIM5_GPIO ((uint16_t)0x0000) +#define TIM5_LSI ((uint16_t)0x0040) +#define TIM5_LSE ((uint16_t)0x0080) +#define TIM5_RTC ((uint16_t)0x00C0) + +#define TIM11_GPIO ((uint16_t)0x0000) +#define TIM11_HSE ((uint16_t)0x0002) + +#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ + ((TIM_REMAP) == TIM2_ETH_PTP)||\ + ((TIM_REMAP) == TIM2_USBFS_SOF)||\ + ((TIM_REMAP) == TIM2_USBHS_SOF)||\ + ((TIM_REMAP) == TIM5_GPIO)||\ + ((TIM_REMAP) == TIM5_LSI)||\ + ((TIM_REMAP) == TIM5_LSE)||\ + ((TIM_REMAP) == TIM5_RTC)||\ + ((TIM_REMAP) == TIM11_GPIO)||\ + ((TIM_REMAP) == TIM11_HSE)) + +/** + * @} + */ +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_Legacy + * @{ + */ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* TimeBase management ********************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Output Compare management **************************************************/ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); + +/* Input Capture management ***************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); + +/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Interrupts, DMA and flags management ***************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Clocks management **********************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); + +/* Synchronization management *************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); + +/* Specific interface management **********************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Specific remapping management **********************************************/ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_TIM_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h index ba7371b48..2dbdede9a 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h @@ -1,431 +1,431 @@ -/** - ****************************************************************************** - * @file stm32f4xx_usart.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_USART_H -#define __STM32F4xx_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 - Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5) || \ - ((PERIPH) == USART6) || \ - ((PERIPH) == UART7) || \ - ((PERIPH) == UART8)) - -#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == USART6)) - -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -/** @defgroup USART_Legacy - * @{ - */ -#define USART_IT_ORE USART_IT_ORE_ER -/** - * @} - */ - -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the USART configuration to the default reset state ***/ -void USART_DeInit(USART_TypeDef* USARTx); - -/* Initialization and Configuration functions *********************************/ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); - -/* Multi-Processor Communication functions ************************************/ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* LIN mode functions *********************************************************/ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendBreak(USART_TypeDef* USARTx); - -/* Half-duplex mode function **************************************************/ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Smartcard mode functions ***************************************************/ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); - -/* IrDA mode functions ********************************************************/ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_USART_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_usart.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_USART_H +#define __STM32F4xx_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 + Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ + + uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4) || \ + ((PERIPH) == UART5) || \ + ((PERIPH) == USART6) || \ + ((PERIPH) == UART7) || \ + ((PERIPH) == UART8)) + +#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == USART6)) + +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +/** @defgroup USART_Legacy + * @{ + */ +#define USART_IT_ORE USART_IT_ORE_ER +/** + * @} + */ + +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the USART configuration to the default reset state ***/ +void USART_DeInit(USART_TypeDef* USARTx); + +/* Initialization and Configuration functions *********************************/ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); + +/* Multi-Processor Communication functions ************************************/ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* LIN mode functions *********************************************************/ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendBreak(USART_TypeDef* USARTx); + +/* Half-duplex mode function **************************************************/ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Smartcard mode functions ***************************************************/ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); + +/* IrDA mode functions ********************************************************/ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* DMA transfers management functions *****************************************/ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_USART_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h index 552f97386..acd7850e4 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h @@ -1,111 +1,111 @@ -/** - ****************************************************************************** - * @file stm32f4xx_wwdg.h - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file contains all the functions prototypes for the WWDG firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_WWDG_H -#define __STM32F4xx_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the WWDG configuration to the default reset state ****/ -void WWDG_DeInit(void); - -/* Prescaler, Refresh window and Counter configuration functions **************/ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); - -/* WWDG activation function ***************************************************/ -void WWDG_Enable(uint8_t Counter); - -/* Interrupts and flags management functions **********************************/ -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_wwdg.h + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file contains all the functions prototypes for the WWDG firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_WWDG_H +#define __STM32F4xx_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the WWDG configuration to the default reset state ****/ +void WWDG_DeInit(void); + +/* Prescaler, Refresh window and Counter configuration functions **************/ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); + +/* WWDG activation function ***************************************************/ +void WWDG_Enable(uint8_t Counter); + +/* Interrupts and flags management functions **********************************/ +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c index 72532f744..dc7d808c9 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c @@ -1,249 +1,249 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - * - * @verbatim - * - * =================================================================== - * How to configure Interrupts using driver - * =================================================================== - * - * This section provide functions allowing to configure the NVIC interrupts (IRQ). - * The Cortex-M4 exceptions are managed by CMSIS functions. - * - * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() - * function according to the following table. - - * The table below gives the allowed values of the pre-emption priority and subpriority according - * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - * ========================================================================================================================== - * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - * ========================================================================================================================== - * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - * | | | 4 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - * | | | 3 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - * | | | 2 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - * | | | 1 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - * | | | 0 bits for subpriority - * ========================================================================================================================== - * - * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() - * - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * - * @note IRQ priority order (sorted by highest to lowest priority): - * - Lowest pre-emption priority - * - Lowest subpriority - * - Lowest hardware priority (IRQ number) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "misc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); - - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. - * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. - * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. - * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + * + * @verbatim + * + * =================================================================== + * How to configure Interrupts using driver + * =================================================================== + * + * This section provide functions allowing to configure the NVIC interrupts (IRQ). + * The Cortex-M4 exceptions are managed by CMSIS functions. + * + * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() + * function according to the following table. + + * The table below gives the allowed values of the pre-emption priority and subpriority according + * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + * ========================================================================================================================== + * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + * ========================================================================================================================== + * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + * | | | 4 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + * | | | 3 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + * | | | 2 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + * | | | 1 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + * | | | 0 bits for subpriority + * ========================================================================================================================== + * + * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() + * + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * + * @note IRQ priority order (sorted by highest to lowest priority): + * - Lowest pre-emption priority + * - Lowest subpriority + * - Lowest hardware priority (IRQ number) + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); + + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. + * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. + * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. + * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. + * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c index 187ff3330..50d0248a4 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c @@ -1,1745 +1,1745 @@ -/** - ****************************************************************************** - * @file stm32f4xx_adc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * + Initialization and Configuration (in addition to ADC multi mode - * selection) - * + Analog Watchdog configuration - * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT - * management - * + Regular Channels Configuration - * + Regular Channels DMA Configuration - * + Injected channels Configuration - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable the ADC interface clock using - RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); - - (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs using the following function: - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - (++) Configure these ADC pins in analog mode using GPIO_Init(); - - (#) Configure the ADC Prescaler, conversion resolution and data - alignment using the ADC_Init() function. - (#) Activate the ADC peripheral using ADC_Cmd() function. - - *** Regular channels group configuration *** - ============================================ - [..] - (+) To configure the ADC regular channels group features, use - ADC_Init() and ADC_RegularChannelConfig() functions. - (+) To activate the continuous mode, use the ADC_continuousModeCmd() - function. - (+) To configurate and activate the Discontinuous mode, use the - ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. - (+) To read the ADC converted values, use the ADC_GetConversionValue() - function. - - *** Multi mode ADCs Regular channels configuration *** - ====================================================== - [..] - (+) Refer to "Regular channels group configuration" description to - configure the ADC1, ADC2 and ADC3 regular channels. - (+) Select the Multi mode ADC regular channels features (dual or - triple mode) using ADC_CommonInit() function and configure - the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() - functions. - (+) Read the ADCs converted values using the - ADC_GetMultiModeConversionValue() function. - - *** DMA for Regular channels group features configuration *** - ============================================================= - [..] - (+) To enable the DMA mode for regular channels group, use the - ADC_DMACmd() function. - (+) To enable the generation of DMA requests continuously at the end - of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() - function. - - *** Injected channels group configuration *** - ============================================= - [..] - (+) To configure the ADC Injected channels group features, use - ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() - functions. - (+) To activate the continuous mode, use the ADC_continuousModeCmd() - function. - (+) To activate the Injected Discontinuous mode, use the - ADC_InjectedDiscModeCmd() function. - (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() - function. - (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() - function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_adc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) - -/* ADC EXTEN mask */ -#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) - -/* ADC JEXTEN mask */ -#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_SET ((uint32_t)0x0000001F) -#define SQR2_SQ_SET ((uint32_t)0x0000001F) -#define SQR1_SQ_SET ((uint32_t)0x0000001F) - -/* ADC L Mask */ -#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_SET ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_SET ((uint32_t)0x00300000) -#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_SET ((uint32_t)0x00000007) -#define SMPR2_SMP_SET ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_OFFSET ((uint8_t)0x28) - -/* ADC CDR register base address */ -#define CDR_ADDRESS ((uint32_t)0x40012308) - -/* ADC CCR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** @defgroup ADC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC Prescaler - (+) ADC Conversion Resolution (12bit..6bit) - (+) Scan Conversion Mode (multichannel or one channel) for regular group - (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for - regular group - (+) External trigger Edge and source of regular group, - (+) Converted data alignment (left or right) - (+) The number of ADC conversions that will be done using the sequencer for - regular channel group - (+) Multi ADC mode selection - (+) Direct memory access mode selection for multi ADC mode - (+) Delay between 2 sampling phases (used in dual or triple interleaved modes) - (+) Enable or disable the ADC peripheral -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes all ADCs peripherals registers to their default reset - * values. - * @param None - * @retval None - */ -void ADC_DeInit(void) -{ - /* Enable all ADCs reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); - - /* Release all ADCs from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @note This function is used to configure the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - - /* Clear RES and SCAN bits */ - tmpreg1 &= CR1_CLEAR_MASK; - - /* Configure ADCx: scan conversion mode and resolution */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - /* Set RES bit according to ADC_Resolution value */ - tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ - ADC_InitStruct->ADC_Resolution); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - - /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_MASK; - - /* Configure ADCx: external trigger event and edge, data alignment and - continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ - ADC_InitStruct->ADC_ExternalTrigConv | - ADC_InitStruct->ADC_ExternalTrigConvEdge | \ - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - - /* Clear L bits */ - tmpreg1 &= SQR1_L_RESET; - - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfConversion value */ - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); - tmpreg1 |= ((uint32_t)tmpreg2 << 20); - - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @note This function is used to initialize the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; - - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - - /* Initialize the ADC_ExternalTrigConvEdge member */ - ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; - - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - - /* Initialize the ADC_NbrOfConversion member */ - ADC_InitStruct->ADC_NbrOfConversion = 1; -} - -/** - * @brief Initializes the ADCs peripherals according to the specified parameters - * in the ADC_CommonInitStruct. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * that contains the configuration information for All ADCs peripherals. - * @retval None - */ -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - uint32_t tmpreg1 = 0; - /* Check the parameters */ - assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); - assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); - assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); - assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); - /*---------------------------- ADC CCR Configuration -----------------*/ - /* Get the ADC CCR value */ - tmpreg1 = ADC->CCR; - - /* Clear MULTI, DELAY, DMA and ADCPRE bits */ - tmpreg1 &= CR_CLEAR_MASK; - - /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, - and DMA access mode for multimode */ - /* Set MULTI bits according to ADC_Mode value */ - /* Set ADCPRE bits according to ADC_Prescaler value */ - /* Set DMA bits according to ADC_DMAAccessMode value */ - /* Set DELAY bits according to ADC_TwoSamplingDelay value */ - tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | - ADC_CommonInitStruct->ADC_Prescaler | - ADC_CommonInitStruct->ADC_DMAAccessMode | - ADC_CommonInitStruct->ADC_TwoSamplingDelay); - - /* Write to ADC CCR */ - ADC->CCR = tmpreg1; -} - -/** - * @brief Fills each ADC_CommonInitStruct member with its default value. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * which will be initialized. - * @retval None - */ -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; - - /* initialize the ADC_Prescaler member */ - ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; - - /* Initialize the ADC_DMAAccessMode member */ - ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; - - /* Initialize the ADC_TwoSamplingDelay member */ - ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group2 Analog Watchdog configuration functions - * @brief Analog Watchdog configuration functions - * -@verbatim - =============================================================================== - ##### Analog Watchdog configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the Analog Watchdog - (AWD) feature in the ADC. - - [..] A typical configuration Analog Watchdog is done following these steps : - (#) the ADC guarded channel(s) is (are) selected using the - ADC_AnalogWatchdogSingleChannelConfig() function. - (#) The Analog watchdog lower and higher threshold are configured using the - ADC_AnalogWatchdogThresholdsConfig() function. - (#) The Analog watchdog is enabled and configured to enable the check, on one - or more channels, using the ADC_AnalogWatchdogCmd() function. -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the analog watchdog on single/all regular or - * injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear AWDEN, JAWDEN and AWDSGL bits */ - tmpreg &= CR1_AWDMode_RESET; - - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12-bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12-bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_RESET; - - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} -/** - * @} - */ - -/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) - * and VBAT (Voltage BATtery) management functions - * @brief Temperature Sensor, Vrefint and VBAT management functions - * -@verbatim - =============================================================================== - ##### Temperature Sensor, Vrefint and VBAT management functions ##### - =============================================================================== - [..] This section provides functions allowing to enable/ disable the internal - connections between the ADC and the Temperature Sensor, the Vrefint and - the Vbat sources. - - [..] A typical configuration to get the Temperature sensor and Vrefint channels - voltages is done following these steps : - (#) Enable the internal connection of Temperature sensor and Vrefint sources - with the ADC channels using ADC_TempSensorVrefintCmd() function. - (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using - ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions - (#) Get the voltage values, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - - [..] A typical configuration to get the VBAT channel voltage is done following - these steps : - (#) Enable the internal connection of VBAT source with the ADC channel using - ADC_VBATCmd() function. - (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or - ADC_InjectedChannelConfig() functions - (#) Get the voltage value, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - -@endverbatim - * @{ - */ - - -/** - * @brief Enables or disables the temperature sensor and Vrefint channels. - * @param NewState: new state of the temperature sensor and Vrefint channels. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); - } -} - -/** - * @brief Enables or disables the VBAT (Voltage Battery) channel. - * - * @note the Battery voltage measured is equal to VBAT/2 on STM32F40xx and - * STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices - * - * @param NewState: new state of the VBAT channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VBATCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the VBAT channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_VBATE; - } - else - { - /* Disable the VBAT channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group4 Regular Channels Configuration functions - * @brief Regular Channels Configuration functions - * -@verbatim - =============================================================================== - ##### Regular Channels Configuration functions ##### - =============================================================================== - - [..] This section provides functions allowing to manage the ADC's regular channels, - it is composed of 2 sub sections : - - (#) Configuration and management functions for regular channels: This subsection - provides functions allowing to configure the ADC regular channels : - (++) Configure the rank in the regular group sequencer for each channel - (++) Configure the sampling time for each channel - (++) select the conversion Trigger for regular channels - (++) select the desired EOC event behavior configuration - (++) Activate the continuous Mode (*) - (++) Activate the Discontinuous Mode - -@@- Please Note that the following features for regular channels - are configurated using the ADC_Init() function : - (+@@) scan mode activation - (+@@) continuous mode activation (**) - (+@@) External trigger source - (+@@) External trigger edge - (+@@) number of conversion in the regular channels group sequencer. - - -@@- (*) and (**) are performing the same configuration - - (#) Get the conversion data: This subsection provides an important function in - the ADC peripheral since it returns the converted data of the current - regular channel. When the Conversion value is read, the EOC Flag is - automatically cleared. - - -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions - results data (in the selected multi mode) can be returned in the same - time using ADC_GetMultiModeConversionValue() function. - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables the selected ADC software start conversion of the regular channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Enable the selected ADC conversion for regular group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; -} - -/** - * @brief Gets the selected ADC Software start regular conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - - /* Return the SWSTART bit status */ - return bitstatus; -} - - -/** - * @brief Enables or disables the EOC on each regular channel conversion - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC EOC flag rising - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; - } - else - { - /* Disable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); - } -} - -/** - * @brief Enables or disables the ADC continuous conversion mode - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC continuous conversion mode - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC continuous conversion mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; - } - else - { - /* Disable the selected ADC continuous conversion mode */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); - } -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular group - * channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel count value. - * This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_RESET; - - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group channel - * for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on - * regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results - * data in the selected multi mode. - * @param None - * @retval The Data conversion value. - * @note In dual mode, the value returned by this function is as following - * Data[15:0] : these bits contain the regular data of ADC1. - * Data[31:16]: these bits contain the regular data of ADC2. - * @note In triple mode, the value returned by this function is as following - * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. - * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. - */ -uint32_t ADC_GetMultiModeConversionValue(void) -{ - /* Return the multi mode conversion value */ - return (*(__IO uint32_t *) CDR_ADDRESS); -} -/** - * @} - */ - -/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions - * @brief Regular Channels DMA Configuration functions - * -@verbatim - =============================================================================== - ##### Regular Channels DMA Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the DMA for ADC - regular channels. - Since converted regular channel values are stored into a unique data - register, it is useful to use DMA for conversion of more than one regular - channel. This avoids the loss of the data already stored in the ADC - Data register. - When the DMA mode is enabled (using the ADC_DMACmd() function), after each - conversion of a regular channel, a DMA request is generated. - [..] Depending on the "DMA disable selection for Independent ADC mode" - configuration (using the ADC_DMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - (+) No new DMA request is issued to the DMA controller (feature DISABLED) - (+) Requests can continue to be generated (feature ENABLED). - [..] Depending on the "DMA disable selection for multi ADC mode" configuration - (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - (+) No new DMA request is issued to the DMA controller (feature DISABLED) - (+) Requests can continue to be generated (feature ENABLED). - -@endverbatim - * @{ - */ - - /** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @note if Enabled, DMA requests are issued as long as data are converted and - * DMA mode for multi ADC mode (selected using ADC_CommonInit() function - * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is - * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. - * @retval None - */ -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADC->CCR |= (uint32_t)ADC_CCR_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group6 Injected channels Configuration functions - * @brief Injected channels Configuration functions - * -@verbatim - =============================================================================== - ##### Injected channels Configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure the ADC Injected channels, - it is composed of 2 sub sections : - - (#) Configuration functions for Injected channels: This subsection provides - functions allowing to configure the ADC injected channels : - (++) Configure the rank in the injected group sequencer for each channel - (++) Configure the sampling time for each channel - (++) Activate the Auto injected Mode - (++) Activate the Discontinuous Mode - (++) scan mode activation - (++) External/software trigger source - (++) External trigger edge - (++) injected channels sequencer. - - (#) Get the Specified Injected channel conversion data: This subsection - provides an important function in the ADC peripheral since it returns the - converted data of the specific injected channel. - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the injected group sequencer. - * This parameter must be between 1 to 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - - /* Clear the old injected sequence length JL bits */ - tmpreg1 &= JSQR_JL_RESET; - - /* Set the injected sequence length JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - - /** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - - /* Get the old register value */ - tmpreg = ADCx->CR2; - - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_RESET; - - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Configures the ADCx external trigger edge for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge - * to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for - * injected conversion - * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge - * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge - * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising - * and falling edge - * @retval None - */ -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external trigger edge for injected group */ - tmpreg &= CR2_JEXTEN_RESET; - /* Set the new external trigger edge for injected group */ - tmpreg |= ADC_ExternalTrigInjecConvEdge; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables the selected ADC software start conversion of the injected channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC conversion for injected group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on injected - * group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); - } -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_OFFSET; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup ADC_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the ADC Interrupts - and to get the status and clear flags and Interrupts pending bits. - - [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided - into 3 groups: - - *** Flags and Interrupts for ADC regular channels *** - ===================================================== - [..] - (+) Flags : - (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost - - (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate - (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) - the end of: - (+++) a regular CHANNEL conversion - (+++) sequence of regular GROUP conversions . - - (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular - CHANNEL conversion starts. - [..] - (+) Interrupts : - (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection - event. - (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end - of conversion event. - - - *** Flags and Interrupts for ADC Injected channels *** - ====================================================== - [..] - (+) Flags : - (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate - at the end of injected GROUP conversion - - (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when - injected GROUP conversion starts. - [..] - (+) Interrupts : - (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel - end of conversion event. - - *** General Flags and Interrupts for the ADC *** - ================================================ - [..] - (+)Flags : - (##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage - crosses the programmed thresholds values. - [..] - (+) Interrupts : - (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. - - - [..] The user should identify which mode will be used in his application to - manage the ADC controller events: Polling mode or Interrupt mode. - - [..] In the Polling Mode it is advised to use the following functions: - (+) ADC_GetFlagStatus() : to check if flags events occur. - (+) ADC_ClearFlag() : to clear the flags events. - - [..] In the Interrupt Mode it is advised to use the following functions: - (+) ADC_ITConfig() : to enable or disable the interrupt source. - (+) ADC_GetITStatus() : to check if Interrupt occurs. - (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt enable - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint32_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - itmask = (uint32_t)0x01 << itmask; - - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; - - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_adc.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) peripheral: + * + Initialization and Configuration (in addition to ADC multi mode + * selection) + * + Analog Watchdog configuration + * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT + * management + * + Regular Channels Configuration + * + Regular Channels DMA Configuration + * + Injected channels Configuration + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable the ADC interface clock using + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs using the following function: + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + (++) Configure these ADC pins in analog mode using GPIO_Init(); + + (#) Configure the ADC Prescaler, conversion resolution and data + alignment using the ADC_Init() function. + (#) Activate the ADC peripheral using ADC_Cmd() function. + + *** Regular channels group configuration *** + ============================================ + [..] + (+) To configure the ADC regular channels group features, use + ADC_Init() and ADC_RegularChannelConfig() functions. + (+) To activate the continuous mode, use the ADC_continuousModeCmd() + function. + (+) To configurate and activate the Discontinuous mode, use the + ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. + (+) To read the ADC converted values, use the ADC_GetConversionValue() + function. + + *** Multi mode ADCs Regular channels configuration *** + ====================================================== + [..] + (+) Refer to "Regular channels group configuration" description to + configure the ADC1, ADC2 and ADC3 regular channels. + (+) Select the Multi mode ADC regular channels features (dual or + triple mode) using ADC_CommonInit() function and configure + the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() + functions. + (+) Read the ADCs converted values using the + ADC_GetMultiModeConversionValue() function. + + *** DMA for Regular channels group features configuration *** + ============================================================= + [..] + (+) To enable the DMA mode for regular channels group, use the + ADC_DMACmd() function. + (+) To enable the generation of DMA requests continuously at the end + of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() + function. + + *** Injected channels group configuration *** + ============================================= + [..] + (+) To configure the ADC Injected channels group features, use + ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() + functions. + (+) To activate the continuous mode, use the ADC_continuousModeCmd() + function. + (+) To activate the Injected Discontinuous mode, use the + ADC_InjectedDiscModeCmd() function. + (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() + function. + (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() + function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_adc.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) + +/* ADC EXTEN mask */ +#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) + +/* ADC JEXTEN mask */ +#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_SET ((uint32_t)0x0000001F) +#define SQR2_SQ_SET ((uint32_t)0x0000001F) +#define SQR1_SQ_SET ((uint32_t)0x0000001F) + +/* ADC L Mask */ +#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_SET ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_SET ((uint32_t)0x00300000) +#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_SET ((uint32_t)0x00000007) +#define SMPR2_SMP_SET ((uint32_t)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_OFFSET ((uint8_t)0x28) + +/* ADC CDR register base address */ +#define CDR_ADDRESS ((uint32_t)0x40012308) + +/* ADC CCR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** @defgroup ADC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC Prescaler + (+) ADC Conversion Resolution (12bit..6bit) + (+) Scan Conversion Mode (multichannel or one channel) for regular group + (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for + regular group + (+) External trigger Edge and source of regular group, + (+) Converted data alignment (left or right) + (+) The number of ADC conversions that will be done using the sequencer for + regular channel group + (+) Multi ADC mode selection + (+) Direct memory access mode selection for multi ADC mode + (+) Delay between 2 sampling phases (used in dual or triple interleaved modes) + (+) Enable or disable the ADC peripheral +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes all ADCs peripherals registers to their default reset + * values. + * @param None + * @retval None + */ +void ADC_DeInit(void) +{ + /* Enable all ADCs reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); + + /* Release all ADCs from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @note This function is used to configure the global features of the ADC ( + * Resolution and Data Alignment), however, the rest of the configuration + * parameters are specific to the regular channels group (scan mode + * activation, continuous mode activation, External trigger source and + * edge, number of conversion in the regular channels group sequencer). + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + + /* Clear RES and SCAN bits */ + tmpreg1 &= CR1_CLEAR_MASK; + + /* Configure ADCx: scan conversion mode and resolution */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + /* Set RES bit according to ADC_Resolution value */ + tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ + ADC_InitStruct->ADC_Resolution); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + + /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_MASK; + + /* Configure ADCx: external trigger event and edge, data alignment and + continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ + ADC_InitStruct->ADC_ExternalTrigConv | + ADC_InitStruct->ADC_ExternalTrigConvEdge | \ + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + + /* Clear L bits */ + tmpreg1 &= SQR1_L_RESET; + + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfConversion value */ + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); + tmpreg1 |= ((uint32_t)tmpreg2 << 20); + + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @note This function is used to initialize the global features of the ADC ( + * Resolution and Data Alignment), however, the rest of the configuration + * parameters are specific to the regular channels group (scan mode + * activation, continuous mode activation, External trigger source and + * edge, number of conversion in the regular channels group sequencer). + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; + + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + + /* Initialize the ADC_ExternalTrigConvEdge member */ + ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + + /* Initialize the ADC_NbrOfConversion member */ + ADC_InitStruct->ADC_NbrOfConversion = 1; +} + +/** + * @brief Initializes the ADCs peripherals according to the specified parameters + * in the ADC_CommonInitStruct. + * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure + * that contains the configuration information for All ADCs peripherals. + * @retval None + */ +void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) +{ + uint32_t tmpreg1 = 0; + /* Check the parameters */ + assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); + assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); + assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); + assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); + /*---------------------------- ADC CCR Configuration -----------------*/ + /* Get the ADC CCR value */ + tmpreg1 = ADC->CCR; + + /* Clear MULTI, DELAY, DMA and ADCPRE bits */ + tmpreg1 &= CR_CLEAR_MASK; + + /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, + and DMA access mode for multimode */ + /* Set MULTI bits according to ADC_Mode value */ + /* Set ADCPRE bits according to ADC_Prescaler value */ + /* Set DMA bits according to ADC_DMAAccessMode value */ + /* Set DELAY bits according to ADC_TwoSamplingDelay value */ + tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | + ADC_CommonInitStruct->ADC_Prescaler | + ADC_CommonInitStruct->ADC_DMAAccessMode | + ADC_CommonInitStruct->ADC_TwoSamplingDelay); + + /* Write to ADC CCR */ + ADC->CCR = tmpreg1; +} + +/** + * @brief Fills each ADC_CommonInitStruct member with its default value. + * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure + * which will be initialized. + * @retval None + */ +void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) +{ + /* Initialize the ADC_Mode member */ + ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; + + /* initialize the ADC_Prescaler member */ + ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; + + /* Initialize the ADC_DMAAccessMode member */ + ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + + /* Initialize the ADC_TwoSamplingDelay member */ + ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); + } +} +/** + * @} + */ + +/** @defgroup ADC_Group2 Analog Watchdog configuration functions + * @brief Analog Watchdog configuration functions + * +@verbatim + =============================================================================== + ##### Analog Watchdog configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the Analog Watchdog + (AWD) feature in the ADC. + + [..] A typical configuration Analog Watchdog is done following these steps : + (#) the ADC guarded channel(s) is (are) selected using the + ADC_AnalogWatchdogSingleChannelConfig() function. + (#) The Analog watchdog lower and higher threshold are configured using the + ADC_AnalogWatchdogThresholdsConfig() function. + (#) The Analog watchdog is enabled and configured to enable the check, on one + or more channels, using the ADC_AnalogWatchdogCmd() function. +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the analog watchdog on single/all regular or + * injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel + * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel + * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel + * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel + * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel + * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels + * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + + /* Clear AWDEN, JAWDEN and AWDSGL bits */ + tmpreg &= CR1_AWDMode_RESET; + + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12-bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12-bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_RESET; + + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} +/** + * @} + */ + +/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) + * and VBAT (Voltage BATtery) management functions + * @brief Temperature Sensor, Vrefint and VBAT management functions + * +@verbatim + =============================================================================== + ##### Temperature Sensor, Vrefint and VBAT management functions ##### + =============================================================================== + [..] This section provides functions allowing to enable/ disable the internal + connections between the ADC and the Temperature Sensor, the Vrefint and + the Vbat sources. + + [..] A typical configuration to get the Temperature sensor and Vrefint channels + voltages is done following these steps : + (#) Enable the internal connection of Temperature sensor and Vrefint sources + with the ADC channels using ADC_TempSensorVrefintCmd() function. + (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using + ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions + (#) Get the voltage values, using ADC_GetConversionValue() or + ADC_GetInjectedConversionValue(). + + [..] A typical configuration to get the VBAT channel voltage is done following + these steps : + (#) Enable the internal connection of VBAT source with the ADC channel using + ADC_VBATCmd() function. + (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or + ADC_InjectedChannelConfig() functions + (#) Get the voltage value, using ADC_GetConversionValue() or + ADC_GetInjectedConversionValue(). + +@endverbatim + * @{ + */ + + +/** + * @brief Enables or disables the temperature sensor and Vrefint channels. + * @param NewState: new state of the temperature sensor and Vrefint channels. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); + } +} + +/** + * @brief Enables or disables the VBAT (Voltage Battery) channel. + * + * @note the Battery voltage measured is equal to VBAT/2 on STM32F40xx and + * STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices + * + * @param NewState: new state of the VBAT channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_VBATCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the VBAT channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_VBATE; + } + else + { + /* Disable the VBAT channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group4 Regular Channels Configuration functions + * @brief Regular Channels Configuration functions + * +@verbatim + =============================================================================== + ##### Regular Channels Configuration functions ##### + =============================================================================== + + [..] This section provides functions allowing to manage the ADC's regular channels, + it is composed of 2 sub sections : + + (#) Configuration and management functions for regular channels: This subsection + provides functions allowing to configure the ADC regular channels : + (++) Configure the rank in the regular group sequencer for each channel + (++) Configure the sampling time for each channel + (++) select the conversion Trigger for regular channels + (++) select the desired EOC event behavior configuration + (++) Activate the continuous Mode (*) + (++) Activate the Discontinuous Mode + -@@- Please Note that the following features for regular channels + are configurated using the ADC_Init() function : + (+@@) scan mode activation + (+@@) continuous mode activation (**) + (+@@) External trigger source + (+@@) External trigger edge + (+@@) number of conversion in the regular channels group sequencer. + + -@@- (*) and (**) are performing the same configuration + + (#) Get the conversion data: This subsection provides an important function in + the ADC peripheral since it returns the converted data of the current + regular channel. When the Conversion value is read, the EOC Flag is + automatically cleared. + + -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions + results data (in the selected multi mode) can be returned in the same + time using ADC_GetMultiModeConversionValue() function. + +@endverbatim + * @{ + */ +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles + * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles + * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles + * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles + * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles + * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles + * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles + * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); + + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); + + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/** + * @brief Enables the selected ADC software start conversion of the regular channels. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Enable the selected ADC conversion for regular group */ + ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; +} + +/** + * @brief Gets the selected ADC Software start regular conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + + /* Return the SWSTART bit status */ + return bitstatus; +} + + +/** + * @brief Enables or disables the EOC on each regular channel conversion + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC EOC flag rising + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC EOC rising on each regular channel conversion */ + ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; + } + else + { + /* Disable the selected ADC EOC rising on each regular channel conversion */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); + } +} + +/** + * @brief Enables or disables the ADC continuous conversion mode + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC continuous conversion mode + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC continuous conversion mode */ + ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; + } + else + { + /* Disable the selected ADC continuous conversion mode */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); + } +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular group + * channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Number: specifies the discontinuous mode regular channel count value. + * This number must be between 1 and 8. + * @retval None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_RESET; + + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group channel + * for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode on + * regular group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results + * data in the selected multi mode. + * @param None + * @retval The Data conversion value. + * @note In dual mode, the value returned by this function is as following + * Data[15:0] : these bits contain the regular data of ADC1. + * Data[31:16]: these bits contain the regular data of ADC2. + * @note In triple mode, the value returned by this function is as following + * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. + * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. + */ +uint32_t ADC_GetMultiModeConversionValue(void) +{ + /* Return the multi mode conversion value */ + return (*(__IO uint32_t *) CDR_ADDRESS); +} +/** + * @} + */ + +/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions + * @brief Regular Channels DMA Configuration functions + * +@verbatim + =============================================================================== + ##### Regular Channels DMA Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the DMA for ADC + regular channels. + Since converted regular channel values are stored into a unique data + register, it is useful to use DMA for conversion of more than one regular + channel. This avoids the loss of the data already stored in the ADC + Data register. + When the DMA mode is enabled (using the ADC_DMACmd() function), after each + conversion of a regular channel, a DMA request is generated. + [..] Depending on the "DMA disable selection for Independent ADC mode" + configuration (using the ADC_DMARequestAfterLastTransferCmd() function), + at the end of the last DMA transfer, two possibilities are allowed: + (+) No new DMA request is issued to the DMA controller (feature DISABLED) + (+) Requests can continue to be generated (feature ENABLED). + [..] Depending on the "DMA disable selection for multi ADC mode" configuration + (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), + at the end of the last DMA transfer, two possibilities are allowed: + (+) No new DMA request is issued to the DMA controller (feature DISABLED) + (+) Requests can continue to be generated (feature ENABLED). + +@endverbatim + * @{ + */ + + /** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); + } +} + +/** + * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC DMA request after last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; + } + else + { + /* Disable the selected ADC DMA request after last transfer */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); + } +} + +/** + * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode + * @param NewState: new state of the selected ADC DMA request after last transfer. + * This parameter can be: ENABLE or DISABLE. + * @note if Enabled, DMA requests are issued as long as data are converted and + * DMA mode for multi ADC mode (selected using ADC_CommonInit() function + * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is + * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. + * @retval None + */ +void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + ADC->CCR |= (uint32_t)ADC_CCR_DDS; + } + else + { + /* Disable the selected ADC DMA request after last transfer */ + ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); + } +} +/** + * @} + */ + +/** @defgroup ADC_Group6 Injected channels Configuration functions + * @brief Injected channels Configuration functions + * +@verbatim + =============================================================================== + ##### Injected channels Configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to configure the ADC Injected channels, + it is composed of 2 sub sections : + + (#) Configuration functions for Injected channels: This subsection provides + functions allowing to configure the ADC injected channels : + (++) Configure the rank in the injected group sequencer for each channel + (++) Configure the sampling time for each channel + (++) Activate the Auto injected Mode + (++) Activate the Discontinuous Mode + (++) scan mode activation + (++) External/software trigger source + (++) External trigger edge + (++) injected channels sequencer. + + (#) Get the Specified Injected channel conversion data: This subsection + provides an important function in the ADC peripheral since it returns the + converted data of the specific injected channel. + +@endverbatim + * @{ + */ +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @param Rank: The rank in the injected group sequencer. + * This parameter must be between 1 to 4. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles + * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles + * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles + * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles + * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles + * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles + * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles + * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Length: The sequencer length. + * This parameter must be a number between 1 to 4. + * @retval None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + + /* Clear the old injected sequence length JL bits */ + tmpreg1 &= JSQR_JL_RESET; + + /* Set the injected sequence length JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @param Offset: the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t *) tmp = (uint32_t)Offset; +} + + /** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected + * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected + * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected + * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected + * @retval None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + + /* Get the old register value */ + tmpreg = ADCx->CR2; + + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_RESET; + + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Configures the ADCx external trigger edge for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge + * to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for + * injected conversion + * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge + * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge + * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising + * and falling edge + * @retval None + */ +void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external trigger edge for injected group */ + tmpreg &= CR2_JEXTEN_RESET; + /* Set the new external trigger edge for injected group */ + tmpreg |= ADC_ExternalTrigInjecConvEdge; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Enables the selected ADC software start conversion of the injected channels. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Enable the selected ADC conversion for injected group */ + ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode on injected + * group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); + } +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @retval The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDR_OFFSET; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} +/** + * @} + */ + +/** @defgroup ADC_Group7 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure the ADC Interrupts + and to get the status and clear flags and Interrupts pending bits. + + [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided + into 3 groups: + + *** Flags and Interrupts for ADC regular channels *** + ===================================================== + [..] + (+) Flags : + (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost + + (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate + (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) + the end of: + (+++) a regular CHANNEL conversion + (+++) sequence of regular GROUP conversions . + + (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular + CHANNEL conversion starts. + [..] + (+) Interrupts : + (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection + event. + (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end + of conversion event. + + + *** Flags and Interrupts for ADC Injected channels *** + ====================================================== + [..] + (+) Flags : + (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate + at the end of injected GROUP conversion + + (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when + injected GROUP conversion starts. + [..] + (+) Interrupts : + (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel + end of conversion event. + + *** General Flags and Interrupts for the ADC *** + ================================================ + [..] + (+)Flags : + (##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage + crosses the programmed thresholds values. + [..] + (+) Interrupts : + (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. + + + [..] The user should identify which mode will be used in his application to + manage the ADC controller events: Polling mode or Interrupt mode. + + [..] In the Polling Mode it is advised to use the following functions: + (+) ADC_GetFlagStatus() : to check if flags events occur. + (+) ADC_ClearFlag() : to clear the flags events. + + [..] In the Interrupt Mode it is advised to use the following functions: + (+) ADC_ITConfig() : to enable or disable the interrupt source. + (+) ADC_GetITStatus() : to check if Interrupt occurs. + (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). +@endverbatim + * @{ + */ +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt enable + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint32_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + itmask = (uint32_t)0x01 << itmask; + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @arg ADC_FLAG_OVR: Overrun flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @arg ADC_FLAG_OVR: Overrun flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + + /* Clear the selected ADC flags */ + ADCx->SR = ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt mask + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; + + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt mask + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(uint32_t)itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c index a68223e28..5a82b4ab1 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c @@ -1,1700 +1,1700 @@ -/** - ****************************************************************************** - * @file stm32f4xx_can.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Controller area network (CAN) peripheral: - * + Initialization and Configuration - * + CAN Frames Transmission - * + CAN Frames Reception - * + Operation modes switch - * + Error management - * + Interrupts and flags - * -@verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable the CAN controller interface clock using - RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 - and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 - -@- In case you are using CAN2 only, you have to enable the CAN1 clock. - - (#) CAN pins configuration - (++) Enable the clock for the CAN GPIOs using the following function: - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - (++) Connect the involved CAN pins to AF9 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); - (++) Configure these CAN pins in alternate function mode by calling - the function GPIO_Init(); - - (#) Initialise and configure the CAN using CAN_Init() and - CAN_FilterInit() functions. - - (#) Transmit the desired CAN frame using CAN_Transmit() function. - - (#) Check the transmission of a CAN frame using CAN_TransmitStatus() - function. - - (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() - function. - - (#) Receive a CAN frame using CAN_Recieve() function. - - (#) Release the receive FIFOs using CAN_FIFORelease() function. - - (#) Return the number of pending received frames using - CAN_MessagePending() function. - - (#) To control CAN events you can use one of the following two methods: - (++) Check on CAN flags using the CAN_GetFlagStatus() function. - (++) Use CAN interrupts through the function CAN_ITConfig() at - initialization phase and CAN_GetITStatus() function into - interrupt routines to check if the event has occurred or not. - After checking on a flag you should clear it using CAN_ClearFlag() - function. And after checking on an interrupt event you should - clear it using CAN_ClearITPendingBit() function. - -@endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_can.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CAN Master Control Register bits */ -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) - -/* Flags in TSR register */ -#define CAN_FLAGS_TSR ((uint32_t)0x08000000) -/* Flags in RF1R register */ -#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) -/* Flags in RF0R register */ -#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) -/* Flags in MSR register */ -#define CAN_FLAGS_MSR ((uint32_t)0x01000000) -/* Flags in ESR register */ -#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** @defgroup CAN_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum - number of time quanta to perform resynchronization, the number of time - quanta in Bit Segment 1 and 2 and many other modes. - Refer to @ref CAN_InitTypeDef for more details. - (+) Configures the CAN reception filter. - (+) Select the start bank filter for slave CAN. - (+) Enables or disables the Debug Freeze mode for CAN - (+)Enables or disables the CAN Time Trigger Operation communication mode - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - if (CANx == CAN1) - { - /* Enable CAN1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } - else - { - /* Enable CAN2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains - * the configuration information for the CAN peripheral. - * @retval Constant indicates initialization succeed which will be - * CAN_InitStatus_Failed or CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* Exit from sleep mode */ - CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - CANx->MCR |= CAN_MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* Check acknowledge */ - if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= CAN_MCR_TTCM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= CAN_MCR_ABOM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= CAN_MCR_AWUM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= CAN_MCR_NART; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= CAN_MCR_RFLM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= CAN_MCR_TXFP; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0; - - while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that - * contains the configuration information. - * @retval None - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. - * @retval None - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -/** - * @brief Select the start bank filter for slave CAN. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - - /* Enter Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Select the start slave bank */ - CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; - - /* Leave Initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - - -/** - * @brief Enables or disables the CAN Time TriggerOperation communication mode. - * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. - * When enabled, Time stamp (TIME[15:0]) value is sent in the last two - * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] - * in data byte 7. - * @retval None - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TTCM mode */ - CANx->MCR |= CAN_MCR_TTCM; - - /* Set TGT bits */ - CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); - } - else - { - /* Disable the TTCM mode */ - CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); - - /* Reset TGT bits */ - CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group2 CAN Frames Transmission functions - * @brief CAN Frames Transmission functions - * -@verbatim - =============================================================================== - ##### CAN Frames Transmission functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initiate and transmit a CAN frame message (if there is an empty mailbox). - (+) Check the transmission status of a CAN Frame - (+) Cancel a transmit request - -@endverbatim - * @{ - */ - -/** - * @brief Initiates and transmits a CAN frame message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. - * @retval The number of the mailbox that is used for transmission or - * CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission status of a CAN Frame. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for transmission. - * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, - * CAN_TxStatus_Failed in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); - break; - case (CAN_TXMAILBOX_1): - state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); - break; - case (CAN_TXMAILBOX_2): - state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); - break; - default: - state = CAN_TxStatus_Failed; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CAN_TxStatus_Pending; - break; - /* transmit failed */ - case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; - break; - /* transmit succeeded */ - case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; - break; - default: state = CAN_TxStatus_Failed; - break; - } - return (uint8_t) state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @retval None - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; - break; - case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; - break; - case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; - break; - default: - break; - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group3 CAN Frames Reception functions - * @brief CAN Frames Reception functions - * -@verbatim - =============================================================================== - ##### CAN Frames Reception functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Receive a correct CAN frame - (+) Release a specified receive FIFO (2 FIFOs are available) - (+) Return the number of the pending received CAN frames - -@endverbatim - * @{ - */ - -/** - * @brief Receives a correct CAN frame. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive frame which contains CAN Id, - * CAN DLC, CAN data and FMI number. - * @retval None - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Releases the specified receive FIFO. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending received messages. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage : which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} -/** - * @} - */ - - -/** @defgroup CAN_Group4 CAN Operation modes functions - * @brief CAN Operation modes functions - * -@verbatim - =============================================================================== - ##### CAN Operation modes functions ##### - =============================================================================== - [..] This section provides functions allowing to select the CAN Operation modes - (+) sleep mode - (+) normal mode - (+) initialization mode - -@endverbatim - * @{ - */ - - -/** - * @brief Selects the CAN Operation mode. - * @param CAN_OperatingMode: CAN Operating Mode. - * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. - * @retval status of the requested mode which can be - * - CAN_ModeStatus_Failed: CAN failed entering the specific mode - * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - - /* Timeout for INAK or also for SLAK bits*/ - uint32_t timeout = INAK_TIMEOUT; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - /* Request initialisation */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - /* Request leave initialisation and sleep mode and enter Normal mode */ - CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - /* Request Sleep mode */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/** - * @brief Enters the Sleep (low power) mode. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CAN_Sleep_Ok; - } - /* return sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes up the CAN peripheral from sleep mode . - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* wake up done : Sleep mode exited */ - wakeupstatus = CAN_WakeUp_Ok; - } - /* return wakeup status */ - return (uint8_t)wakeupstatus; -} -/** - * @} - */ - - -/** @defgroup CAN_Group5 CAN Bus Error management functions - * @brief CAN Bus Error management functions - * -@verbatim - =============================================================================== - ##### CAN Bus Error management functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Return the CANx's last error code (LEC) - (+) Return the CANx Receive Error Counter (REC) - (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). - - -@- If TEC is greater than 255, The CAN is in bus-off state. - -@- if REC or TEC are greater than 96, an Error warning flag occurs. - -@- if REC or TEC are greater than 127, an Error Passive Flag occurs. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the CANx's last error code (LEC). - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval Error code: - * - CAN_ERRORCODE_NoErr: No Error - * - CAN_ERRORCODE_StuffErr: Stuff Error - * - CAN_ERRORCODE_FormErr: Form Error - * - CAN_ERRORCODE_ACKErr : Acknowledgment Error - * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error - * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error - * - CAN_ERRORCODE_CRCErr: CRC Error - * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error - */ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the error code*/ - errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); - - /* Return the error code*/ - return errorcode; -} - -/** - * @brief Returns the CANx Receive Error Counter (REC). - * @note In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the Receive Error Counter*/ - counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); - - /* Return the Receive Error Counter*/ - return counter; -} - - -/** - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); - - /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - return counter; -} -/** - * @} - */ - -/** @defgroup CAN_Group6 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the CAN Interrupts - and to get the status and clear flags and Interrupts pending bits. - - The CAN provides 14 Interrupts sources and 15 Flags: - - - *** Flags *** - ============= - [..] The 15 flags can be divided on 4 groups: - - (+) Transmit Flags - (++) CAN_FLAG_RQCP0, - (++) CAN_FLAG_RQCP1, - (++) CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags - Set when when the last request (transmit or abort) - has been performed. - - (+) Receive Flags - - - (++) CAN_FLAG_FMP0, - (++) CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags - set to signal that messages are pending in the receive - FIFO. - These Flags are cleared only by hardware. - - (++) CAN_FLAG_FF0, - (++) CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags - set when three messages are stored in the selected - FIFO. - - (++) CAN_FLAG_FOV0 - (++) CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags - set when a new message has been received and passed - the filter while the FIFO was full. - - (+) Operating Mode Flags - - (++) CAN_FLAG_WKU : Wake up Flag - set to signal that a SOF bit has been detected while - the CAN hardware was in Sleep mode. - - (++) CAN_FLAG_SLAK : Sleep acknowledge Flag - Set to signal that the CAN has entered Sleep Mode. - - (+) Error Flags - - (++) CAN_FLAG_EWG : Error Warning Flag - Set when the warning limit has been reached (Receive - Error Counter or Transmit Error Counter greater than 96). - This Flag is cleared only by hardware. - - (++) CAN_FLAG_EPV : Error Passive Flag - Set when the Error Passive limit has been reached - (Receive Error Counter or Transmit Error Counter - greater than 127). - This Flag is cleared only by hardware. - - (++) CAN_FLAG_BOF : Bus-Off Flag - set when CAN enters the bus-off state. The bus-off - state is entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - - (++) CAN_FLAG_LEC : Last error code Flag - set If a message has been transferred (reception or - transmission) with error, and the error code is hold. - - *** Interrupts *** - ================== - [..] The 14 interrupts can be divided on 4 groups: - - (+) Transmit interrupt - - (++) CAN_IT_TME : Transmit mailbox empty Interrupt - if enabled, this interrupt source is pending when - no transmit request are pending for Tx mailboxes. - - (+) Receive Interrupts - - (++) CAN_IT_FMP0, - (++) CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts - if enabled, these interrupt sources are pending - when messages are pending in the receive FIFO. - The corresponding interrupt pending bits are cleared - only by hardware. - - (++) CAN_IT_FF0, - (++) CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts - if enabled, these interrupt sources are pending - when three messages are stored in the selected FIFO. - - (++) CAN_IT_FOV0, - (++) CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts - if enabled, these interrupt sources are pending - when a new message has been received and passed - the filter while the FIFO was full. - - (+) Operating Mode Interrupts - - (++) CAN_IT_WKU : Wake-up Interrupt - if enabled, this interrupt source is pending when - a SOF bit has been detected while the CAN hardware - was in Sleep mode. - - (++) CAN_IT_SLK : Sleep acknowledge Interrupt - if enabled, this interrupt source is pending when - the CAN has entered Sleep Mode. - - (+) Error Interrupts - - (++) CAN_IT_EWG : Error warning Interrupt - if enabled, this interrupt source is pending when - the warning limit has been reached (Receive Error - Counter or Transmit Error Counter=96). - - (++) CAN_IT_EPV : Error passive Interrupt - if enabled, this interrupt source is pending when - the Error Passive limit has been reached (Receive - Error Counter or Transmit Error Counter>127). - - (++) CAN_IT_BOF : Bus-off Interrupt - if enabled, this interrupt source is pending when - CAN enters the bus-off state. The bus-off state is - entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - - (++) CAN_IT_LEC : Last error code Interrupt - if enabled, this interrupt source is pending when - a message has been transferred (reception or - transmission) with error, and the error code is hold. - - (++) CAN_IT_ERR : Error Interrupt - if enabled, this interrupt source is pending when - an error condition is pending. - - [..] Managing the CAN controller events : - - The user should identify which mode will be used in his application to - manage the CAN controller events: Polling mode or Interrupt mode. - - (#) In the Polling Mode it is advised to use the following functions: - (++) CAN_GetFlagStatus() : to check if flags events occur. - (++) CAN_ClearFlag() : to clear the flags events. - - - - (#) In the Interrupt Mode it is advised to use the following functions: - (++) CAN_ITConfig() : to enable or disable the interrupt source. - (++) CAN_GetITStatus() : to check if Interrupt occurs. - (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@@- This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts - pending bits since there are cleared only by hardware. - -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified CANx interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CANx interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CANx interrupt */ - CANx->IER &= ~CAN_IT; - } -} -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); - - - if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ - { - /* Check the status of the specified CAN flag */ - if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval None - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); - - if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ - { - /* Clear the selected CAN flags */ - CANx->ESR = (uint32_t)RESET; - } - else /* MSR or TSR or RF0R or RF1R */ - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF0R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF1R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) - { - /* Transmit Flags */ - CANx->TSR = (uint32_t)(flagtmp); - } - else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ - { - /* Operating mode Flags */ - CANx->MSR = (uint32_t)(flagtmp); - } - } -} - -/** - * @brief Checks whether the specified CANx interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval The current state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - - /* check the interrupt enable bit */ - if((CANx->IER & CAN_IT) != RESET) - { - /* in case the Interrupt is enabled, .... */ - switch (CAN_IT) - { - case CAN_IT_TME: - /* Check CAN_TSR_RQCPx bits */ - itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); - break; - case CAN_IT_FMP0: - /* Check CAN_RF0R_FMP0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); - break; - case CAN_IT_FF0: - /* Check CAN_RF0R_FULL0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); - break; - case CAN_IT_FOV0: - /* Check CAN_RF0R_FOVR0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); - break; - case CAN_IT_FMP1: - /* Check CAN_RF1R_FMP1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); - break; - case CAN_IT_FF1: - /* Check CAN_RF1R_FULL1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); - break; - case CAN_IT_FOV1: - /* Check CAN_RF1R_FOVR1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); - break; - case CAN_IT_WKU: - /* Check CAN_MSR_WKUI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); - break; - case CAN_IT_SLK: - /* Check CAN_MSR_SLAKI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); - break; - case CAN_IT_EWG: - /* Check CAN_ESR_EWGF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); - break; - case CAN_IT_EPV: - /* Check CAN_ESR_EPVF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); - break; - case CAN_IT_BOF: - /* Check CAN_ESR_BOFF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); - break; - case CAN_IT_LEC: - /* Check CAN_ESR_LEC bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); - break; - case CAN_IT_ERR: - /* Check CAN_MSR_ERRI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); - break; - default: - /* in case of error, return RESET */ - itstatus = RESET; - break; - } - } - else - { - /* in case the Interrupt is not enabled, return RESET */ - itstatus = RESET; - } - - /* Return the CAN_IT status */ - return itstatus; -} - -/** - * @brief Clears the CANx's interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval None - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_IT(CAN_IT)); - - switch (CAN_IT) - { - case CAN_IT_TME: - /* Clear CAN_TSR_RQCPx (rc_w1)*/ - CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; - break; - case CAN_IT_FF0: - /* Clear CAN_RF0R_FULL0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FULL0; - break; - case CAN_IT_FOV0: - /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FOVR0; - break; - case CAN_IT_FF1: - /* Clear CAN_RF1R_FULL1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FULL1; - break; - case CAN_IT_FOV1: - /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FOVR1; - break; - case CAN_IT_WKU: - /* Clear CAN_MSR_WKUI (rc_w1)*/ - CANx->MSR = CAN_MSR_WKUI; - break; - case CAN_IT_SLK: - /* Clear CAN_MSR_SLAKI (rc_w1)*/ - CANx->MSR = CAN_MSR_SLAKI; - break; - case CAN_IT_EWG: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_EPV: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_BOF: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_LEC: - /* Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - break; - case CAN_IT_ERR: - /*Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ - break; - default: - break; - } -} - /** - * @} - */ - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_can.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Controller area network (CAN) peripheral: + * + Initialization and Configuration + * + CAN Frames Transmission + * + CAN Frames Reception + * + Operation modes switch + * + Error management + * + Interrupts and flags + * +@verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable the CAN controller interface clock using + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 + and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 + -@- In case you are using CAN2 only, you have to enable the CAN1 clock. + + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs using the following function: + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + (++) Connect the involved CAN pins to AF9 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); + (++) Configure these CAN pins in alternate function mode by calling + the function GPIO_Init(); + + (#) Initialise and configure the CAN using CAN_Init() and + CAN_FilterInit() functions. + + (#) Transmit the desired CAN frame using CAN_Transmit() function. + + (#) Check the transmission of a CAN frame using CAN_TransmitStatus() + function. + + (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() + function. + + (#) Receive a CAN frame using CAN_Recieve() function. + + (#) Release the receive FIFOs using CAN_FIFORelease() function. + + (#) Return the number of pending received frames using + CAN_MessagePending() function. + + (#) To control CAN events you can use one of the following two methods: + (++) Check on CAN flags using the CAN_GetFlagStatus() function. + (++) Use CAN interrupts through the function CAN_ITConfig() at + initialization phase and CAN_GetITStatus() function into + interrupt routines to check if the event has occurred or not. + After checking on a flag you should clear it using CAN_ClearFlag() + function. And after checking on an interrupt event you should + clear it using CAN_ClearITPendingBit() function. + +@endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_can.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CAN + * @brief CAN driver modules + * @{ + */ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* CAN Master Control Register bits */ +#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSR register */ +#define CAN_FLAGS_TSR ((uint32_t)0x08000000) +/* Flags in RF1R register */ +#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) +/* Flags in RF0R register */ +#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) +/* Flags in MSR register */ +#define CAN_FLAGS_MSR ((uint32_t)0x01000000) +/* Flags in ESR register */ +#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/** @defgroup CAN_Private_Functions + * @{ + */ + +/** @defgroup CAN_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to + (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum + number of time quanta to perform resynchronization, the number of time + quanta in Bit Segment 1 and 2 and many other modes. + Refer to @ref CAN_InitTypeDef for more details. + (+) Configures the CAN reception filter. + (+) Select the start bank filter for slave CAN. + (+) Enables or disables the Debug Freeze mode for CAN + (+)Enables or disables the CAN Time Trigger Operation communication mode + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval None. + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if (CANx == CAN1) + { + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + /* Enable CAN2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains + * the configuration information for the CAN peripheral. + * @retval Constant indicates initialization succeed which will be + * CAN_InitStatus_Failed or CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* Exit from sleep mode */ + CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + CANx->MCR |= CAN_MCR_INRQ ; + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* Check acknowledge */ + if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->MCR |= CAN_MCR_TTCM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->MCR |= CAN_MCR_ABOM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->MCR |= CAN_MCR_AWUM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->MCR |= CAN_MCR_NART; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->MCR |= CAN_MCR_RFLM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->MCR |= CAN_MCR_TXFP; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + + /* Request leave initialisation */ + CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Wait the acknowledge */ + wait_ack = 0; + + while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that + * contains the configuration information. + * @retval None + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FA1R |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Fills each CAN_InitStruct member with its default value. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. + * @retval None + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/** + * @brief Select the start bank filter for slave CAN. + * @param CAN_BankNumber: Select the start slave bank filter from 1..27. + * @retval None + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); + + /* Enter Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Select the start slave bank */ + CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; + + /* Leave Initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFOs can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; + } +} + + +/** + * @brief Enables or disables the CAN Time TriggerOperation communication mode. + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. + * When enabled, Time stamp (TIME[15:0]) value is sent in the last two + * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] + * in data byte 7. + * @retval None + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCR |= CAN_MCR_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); + } +} +/** + * @} + */ + + +/** @defgroup CAN_Group2 CAN Frames Transmission functions + * @brief CAN Frames Transmission functions + * +@verbatim + =============================================================================== + ##### CAN Frames Transmission functions ##### + =============================================================================== + [..] This section provides functions allowing to + (+) Initiate and transmit a CAN frame message (if there is an empty mailbox). + (+) Check the transmission status of a CAN Frame + (+) Cancel a transmit request + +@endverbatim + * @{ + */ + +/** + * @brief Initiates and transmits a CAN frame message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. + * @retval The number of the mailbox that is used for transmission or + * CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission status of a CAN Frame. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for transmission. + * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, + * CAN_TxStatus_Failed in an other case. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); + break; + case (CAN_TXMAILBOX_1): + state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); + break; + case (CAN_TXMAILBOX_2): + state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); + break; + default: + state = CAN_TxStatus_Failed; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): state = CAN_TxStatus_Pending; + break; + /* transmit failed */ + case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; + break; + /* transmit succeeded */ + case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; + break; + default: state = CAN_TxStatus_Failed; + break; + } + return (uint8_t) state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param Mailbox: Mailbox number. + * @retval None + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; + break; + case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; + break; + case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; + break; + default: + break; + } +} +/** + * @} + */ + + +/** @defgroup CAN_Group3 CAN Frames Reception functions + * @brief CAN Frames Reception functions + * +@verbatim + =============================================================================== + ##### CAN Frames Reception functions ##### + =============================================================================== + [..] This section provides functions allowing to + (+) Receive a correct CAN frame + (+) Release a specified receive FIFO (2 FIFOs are available) + (+) Return the number of the pending received CAN frames + +@endverbatim + * @{ + */ + +/** + * @brief Receives a correct CAN frame. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive frame which contains CAN Id, + * CAN DLC, CAN data and FMI number. + * @retval None + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Releases the specified receive FIFO. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Returns the number of pending received messages. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval NbMessage : which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} +/** + * @} + */ + + +/** @defgroup CAN_Group4 CAN Operation modes functions + * @brief CAN Operation modes functions + * +@verbatim + =============================================================================== + ##### CAN Operation modes functions ##### + =============================================================================== + [..] This section provides functions allowing to select the CAN Operation modes + (+) sleep mode + (+) normal mode + (+) initialization mode + +@endverbatim + * @{ + */ + + +/** + * @brief Selects the CAN Operation mode. + * @param CAN_OperatingMode: CAN Operating Mode. + * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. + * @retval status of the requested mode which can be + * - CAN_ModeStatus_Failed: CAN failed entering the specific mode + * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INAK_TIMEOUT; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + /* Request initialisation */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) + { + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + /* Request Sleep mode */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t) status; +} + +/** + * @brief Enters the Sleep (low power) mode. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) + { + /* Sleep mode not entered */ + sleepstatus = CAN_Sleep_Ok; + } + /* return sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode . + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Sleep mode status */ + while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) + { + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WakeUp_Ok; + } + /* return wakeup status */ + return (uint8_t)wakeupstatus; +} +/** + * @} + */ + + +/** @defgroup CAN_Group5 CAN Bus Error management functions + * @brief CAN Bus Error management functions + * +@verbatim + =============================================================================== + ##### CAN Bus Error management functions ##### + =============================================================================== + [..] This section provides functions allowing to + (+) Return the CANx's last error code (LEC) + (+) Return the CANx Receive Error Counter (REC) + (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). + + -@- If TEC is greater than 255, The CAN is in bus-off state. + -@- if REC or TEC are greater than 96, an Error warning flag occurs. + -@- if REC or TEC are greater than 127, an Error Passive Flag occurs. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval Error code: + * - CAN_ERRORCODE_NoErr: No Error + * - CAN_ERRORCODE_StuffErr: Stuff Error + * - CAN_ERRORCODE_FormErr: Form Error + * - CAN_ERRORCODE_ACKErr : Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error + * - CAN_ERRORCODE_CRCErr: CRC Error + * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); + + /* Return the error code*/ + return errorcode; +} + +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} +/** + * @} + */ + +/** @defgroup CAN_Group6 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure the CAN Interrupts + and to get the status and clear flags and Interrupts pending bits. + + The CAN provides 14 Interrupts sources and 15 Flags: + + + *** Flags *** + ============= + [..] The 15 flags can be divided on 4 groups: + + (+) Transmit Flags + (++) CAN_FLAG_RQCP0, + (++) CAN_FLAG_RQCP1, + (++) CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags + Set when when the last request (transmit or abort) + has been performed. + + (+) Receive Flags + + + (++) CAN_FLAG_FMP0, + (++) CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags + set to signal that messages are pending in the receive + FIFO. + These Flags are cleared only by hardware. + + (++) CAN_FLAG_FF0, + (++) CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags + set when three messages are stored in the selected + FIFO. + + (++) CAN_FLAG_FOV0 + (++) CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags + set when a new message has been received and passed + the filter while the FIFO was full. + + (+) Operating Mode Flags + + (++) CAN_FLAG_WKU : Wake up Flag + set to signal that a SOF bit has been detected while + the CAN hardware was in Sleep mode. + + (++) CAN_FLAG_SLAK : Sleep acknowledge Flag + Set to signal that the CAN has entered Sleep Mode. + + (+) Error Flags + + (++) CAN_FLAG_EWG : Error Warning Flag + Set when the warning limit has been reached (Receive + Error Counter or Transmit Error Counter greater than 96). + This Flag is cleared only by hardware. + + (++) CAN_FLAG_EPV : Error Passive Flag + Set when the Error Passive limit has been reached + (Receive Error Counter or Transmit Error Counter + greater than 127). + This Flag is cleared only by hardware. + + (++) CAN_FLAG_BOF : Bus-Off Flag + set when CAN enters the bus-off state. The bus-off + state is entered on TEC overflow, greater than 255. + This Flag is cleared only by hardware. + + (++) CAN_FLAG_LEC : Last error code Flag + set If a message has been transferred (reception or + transmission) with error, and the error code is hold. + + *** Interrupts *** + ================== + [..] The 14 interrupts can be divided on 4 groups: + + (+) Transmit interrupt + + (++) CAN_IT_TME : Transmit mailbox empty Interrupt + if enabled, this interrupt source is pending when + no transmit request are pending for Tx mailboxes. + + (+) Receive Interrupts + + (++) CAN_IT_FMP0, + (++) CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts + if enabled, these interrupt sources are pending + when messages are pending in the receive FIFO. + The corresponding interrupt pending bits are cleared + only by hardware. + + (++) CAN_IT_FF0, + (++) CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts + if enabled, these interrupt sources are pending + when three messages are stored in the selected FIFO. + + (++) CAN_IT_FOV0, + (++) CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts + if enabled, these interrupt sources are pending + when a new message has been received and passed + the filter while the FIFO was full. + + (+) Operating Mode Interrupts + + (++) CAN_IT_WKU : Wake-up Interrupt + if enabled, this interrupt source is pending when + a SOF bit has been detected while the CAN hardware + was in Sleep mode. + + (++) CAN_IT_SLK : Sleep acknowledge Interrupt + if enabled, this interrupt source is pending when + the CAN has entered Sleep Mode. + + (+) Error Interrupts + + (++) CAN_IT_EWG : Error warning Interrupt + if enabled, this interrupt source is pending when + the warning limit has been reached (Receive Error + Counter or Transmit Error Counter=96). + + (++) CAN_IT_EPV : Error passive Interrupt + if enabled, this interrupt source is pending when + the Error Passive limit has been reached (Receive + Error Counter or Transmit Error Counter>127). + + (++) CAN_IT_BOF : Bus-off Interrupt + if enabled, this interrupt source is pending when + CAN enters the bus-off state. The bus-off state is + entered on TEC overflow, greater than 255. + This Flag is cleared only by hardware. + + (++) CAN_IT_LEC : Last error code Interrupt + if enabled, this interrupt source is pending when + a message has been transferred (reception or + transmission) with error, and the error code is hold. + + (++) CAN_IT_ERR : Error Interrupt + if enabled, this interrupt source is pending when + an error condition is pending. + + [..] Managing the CAN controller events : + + The user should identify which mode will be used in his application to + manage the CAN controller events: Polling mode or Interrupt mode. + + (#) In the Polling Mode it is advised to use the following functions: + (++) CAN_GetFlagStatus() : to check if flags events occur. + (++) CAN_ClearFlag() : to clear the flags events. + + + + (#) In the Interrupt Mode it is advised to use the following functions: + (++) CAN_ITConfig() : to enable or disable the interrupt source. + (++) CAN_GetITStatus() : to check if Interrupt occurs. + (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). + -@@- This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts + pending bits since there are cleared only by hardware. + +@endverbatim + * @{ + */ +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->IER &= ~CAN_IT; + } +} +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag + * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag + * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @arg CAN_FLAG_LEC: Last error code Flag + * @retval The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + + if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag + * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag + * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_LEC: Last error code Flag + * @retval None + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ + { + /* Clear the selected CAN flags */ + CANx->ESR = (uint32_t)RESET; + } + else /* MSR or TSR or RF0R or RF1R */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF0R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF1R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSR = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSR = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @retval The current state of CAN_IT (SET or RESET). + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + + /* check the interrupt enable bit */ + if((CANx->IER & CAN_IT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_IT) + { + case CAN_IT_TME: + /* Check CAN_TSR_RQCPx bits */ + itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); + break; + case CAN_IT_FMP0: + /* Check CAN_RF0R_FMP0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); + break; + case CAN_IT_FF0: + /* Check CAN_RF0R_FULL0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); + break; + case CAN_IT_FOV0: + /* Check CAN_RF0R_FOVR0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); + break; + case CAN_IT_FMP1: + /* Check CAN_RF1R_FMP1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); + break; + case CAN_IT_FF1: + /* Check CAN_RF1R_FULL1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); + break; + case CAN_IT_FOV1: + /* Check CAN_RF1R_FOVR1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); + break; + case CAN_IT_WKU: + /* Check CAN_MSR_WKUI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); + break; + case CAN_IT_SLK: + /* Check CAN_MSR_SLAKI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); + break; + case CAN_IT_EWG: + /* Check CAN_ESR_EWGF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); + break; + case CAN_IT_EPV: + /* Check CAN_ESR_EPVF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); + break; + case CAN_IT_BOF: + /* Check CAN_ESR_BOFF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); + break; + case CAN_IT_LEC: + /* Check CAN_ESR_LEC bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); + break; + case CAN_IT_ERR: + /* Check CAN_MSR_ERRI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); + break; + default: + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_IT status */ + return itstatus; +} + +/** + * @brief Clears the CANx's interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @retval None + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_TME: + /* Clear CAN_TSR_RQCPx (rc_w1)*/ + CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; + break; + case CAN_IT_FF0: + /* Clear CAN_RF0R_FULL0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FULL0; + break; + case CAN_IT_FOV0: + /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FOVR0; + break; + case CAN_IT_FF1: + /* Clear CAN_RF1R_FULL1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FULL1; + break; + case CAN_IT_FOV1: + /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FOVR1; + break; + case CAN_IT_WKU: + /* Clear CAN_MSR_WKUI (rc_w1)*/ + CANx->MSR = CAN_MSR_WKUI; + break; + case CAN_IT_SLK: + /* Clear CAN_MSR_SLAKI (rc_w1)*/ + CANx->MSR = CAN_MSR_SLAKI; + break; + case CAN_IT_EWG: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_EPV: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_BOF: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_LEC: + /* Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + break; + case CAN_IT_ERR: + /*Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ + break; + default: + break; + } +} + /** + * @} + */ + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg: specifies the CAN interrupt register to check. + * @param It_Bit: specifies the interrupt source bit to check. + * @retval The new state of the CAN Interrupt (SET or RESET). + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c index be2cac942..ac420eceb 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c @@ -1,133 +1,133 @@ -/** - ****************************************************************************** - * @file stm32f4xx_crc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides all the CRC firmware functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_crc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Resets the CRC Data register (DR). - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DR = Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDR = IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_crc.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides all the CRC firmware functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_crc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DR). + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CRC_CR_RESET; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c index 963e3ba56..548caec8c 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c @@ -1,934 +1,934 @@ -/** - ****************************************************************************** - * @file stm32f4xx_cryp.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Cryptographic processor (CRYP) peripheral: - * + Initialization and Configuration functions - * + Data treatment functions - * + Context swapping functions - * + DMA interface function - * + Interrupts and flags management - * -@verbatim - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable the CRYP controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - - (#) Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed - CRYP_IVInit(). - - (#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. - - (#) Enable the CRYP controller using the CRYP_Cmd() function. - - (#) If using DMA for Data input and output transfer, activate the needed DMA - Requests using CRYP_DMACmd() function - - (#) If DMA is not used for data transfer, use CRYP_DataIn() and CRYP_DataOut() - functions to enter data to IN FIFO and get result from OUT FIFO. - - (#) To control CRYP events you can use one of the following two methods: - (++) Check on CRYP flags using the CRYP_GetFlagStatus() function. - (++) Use CRYP interrupts through the function CRYP_ITConfig() at - initialization phase and CRYP_GetITStatus() function into interrupt - routines in processing phase. - - (#) Save and restore Cryptographic processor context using CRYP_SaveContext() - and CRYP_RestoreContext() functions. - - - *** Procedure to perform an encryption or a decryption *** - ========================================================== - - *** Initialization *** - ====================== - [..] - (#) Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and CRYP_IVInit - functions: - (++) Configure the key size (128-, 192- or 256-bit, in the AES only) - (++) Enter the symmetric key - (++) Configure the data type - (++) In case of decryption in AES-ECB or AES-CBC, you must prepare - the key: configure the key preparation mode. Then Enable the CRYP - peripheral using CRYP_Cmd() function: the BUSY flag is set. - Wait until BUSY flag is reset : the key is prepared for decryption - (++) Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the - AES in ECB/CBC/CTR) - (++) Configure the direction (encryption/decryption). - (++) Write the initialization vectors (in CBC or CTR modes only) - - (#) Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function - - - *** Basic Processing mode (polling mode) *** - ============================================ - [..] - (#) Enable the cryptographic processor using CRYP_Cmd() function. - - (#) Write the first blocks in the input FIFO (2 to 8 words) using - CRYP_DataIn() function. - - (#) Repeat the following sequence until the complete message has been - processed: - - (++) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() - function), then read the OUT-FIFO using CRYP_DataOut() function - (1 block or until the FIFO is empty) - - (++) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() - function then write the IN FIFO using CRYP_DataIn() function - (1 block or until the FIFO is full) - - (#) At the end of the processing, CRYP_FLAG_BUSY flag will be reset and - both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is - reset). You can disable the peripheral using CRYP_Cmd() function. - - *** Interrupts Processing mode *** - ================================== - [..] In this mode, Processing is done when the data are transferred by the - CPU during interrupts. - - (#) Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using CRYP_ITConfig() - function. - - (#) Enable the cryptographic processor using CRYP_Cmd() function. - - (#) In the CRYP_IT_INI interrupt handler : load the input message into the - IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a - time, or load data until the IN FIFO is full. When the last word of - the message has been entered into the IN FIFO, disable the CRYP_IT_INI - interrupt (using CRYP_ITConfig() function). - - (#) In the CRYP_IT_OUTI interrupt handler : read the output message from - the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or - 4 words) at a time or read data until the FIFO is empty. - When the last word has been read, INIM=0, BUSY=0 and both FIFOs are - empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). - You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() - function) and you can disable the peripheral using CRYP_Cmd() function. - - *** DMA Processing mode *** - =========================== - [..] In this mode, Processing is done when the DMA is used to transfer the - data from/to the memory. - - (#) Configure the DMA controller to transfer the input data from the - memory using DMA_Init() function. - The transfer length is the length of the message. - As message padding is not managed by the peripheral, the message - length must be an entire number of blocks. The data are transferred - in burst mode. The burst length is 4 words in the AES and 2 or 4 - words in the DES/TDES. The DMA should be configured to set an - interrupt on transfer completion of the output data to indicate that - the processing is finished. - Refer to DMA peripheral driver for more details. - - (#) Enable the cryptographic processor using CRYP_Cmd() function. - Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT - using CRYP_DMACmd() function. - - (#) All the transfers and processing are managed by the DMA and the - cryptographic processor. The DMA transfer complete interrupt indicates - that the processing is complete. Both FIFOs are normally empty and - CRYP_FLAG_BUSY flag is reset. - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define FLAG_MASK ((uint8_t)0x20) -#define MAX_TIMEOUT ((uint16_t)0xFFFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initialize the cryptographic Processor using CRYP_Init() function - (++) Encrypt or Decrypt - (++) mode : TDES-ECB, TDES-CBC, - DES-ECB, DES-CBC, - AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM, AES-CCM - (++) DataType : 32-bit data, 16-bit data, bit data or bit-string - (++) Key Size (only in AES modes) - (+) Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function - (+) Configure the Initialization Vectors(IV) for CBC and CTR modes using - CRYP_IVInit() function. - (+) Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. - (+) Enable or disable the CRYP Processor using CRYP_Cmd() function - -@endverbatim - * @{ - */ -/** - * @brief Deinitializes the CRYP peripheral registers to their default reset values - * @param None - * @retval None - */ -void CRYP_DeInit(void) -{ - /* Enable CRYP reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE); - - /* Release CRYP from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE); -} - -/** - * @brief Initializes the CRYP peripheral according to the specified parameters - * in the CRYP_InitStruct. - * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains - * the configuration information for the CRYP peripheral. - * @retval None - */ -void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode)); - assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType)); - assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir)); - - /* Select Algorithm mode*/ - CRYP->CR &= ~CRYP_CR_ALGOMODE; - CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode; - - /* Select dataType */ - CRYP->CR &= ~CRYP_CR_DATATYPE; - CRYP->CR |= CRYP_InitStruct->CRYP_DataType; - - /* select Key size (used only with AES algorithm) */ - if ((CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_ECB) && - (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_CBC) && - (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_ECB) && - (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_CBC)) - { - assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); - CRYP->CR &= ~CRYP_CR_KEYSIZE; - CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be - configured once the key has - been prepared */ - } - - /* Select data Direction */ - CRYP->CR &= ~CRYP_CR_ALGODIR; - CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir; -} - -/** - * @brief Fills each CRYP_InitStruct member with its default value. - * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct) -{ - /* Initialize the CRYP_AlgoDir member */ - CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - - /* initialize the CRYP_AlgoMode member */ - CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; - - /* initialize the CRYP_DataType member */ - CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b; - - /* Initialize the CRYP_KeySize member */ - CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b; -} - -/** - * @brief Initializes the CRYP Keys according to the specified parameters in - * the CRYP_KeyInitStruct. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that - * contains the configuration information for the CRYP Keys. - * @retval None - */ -void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - /* Key Initialisation */ - CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; - CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; - CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; - CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; - CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; - CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; - CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; - CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; -} - -/** - * @brief Fills each CRYP_KeyInitStruct member with its default value. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure - * which will be initialized. - * @retval None - */ -void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - CRYP_KeyInitStruct->CRYP_Key0Left = 0; - CRYP_KeyInitStruct->CRYP_Key0Right = 0; - CRYP_KeyInitStruct->CRYP_Key1Left = 0; - CRYP_KeyInitStruct->CRYP_Key1Right = 0; - CRYP_KeyInitStruct->CRYP_Key2Left = 0; - CRYP_KeyInitStruct->CRYP_Key2Right = 0; - CRYP_KeyInitStruct->CRYP_Key3Left = 0; - CRYP_KeyInitStruct->CRYP_Key3Right = 0; -} -/** - * @brief Initializes the CRYP Initialization Vectors(IV) according to the - * specified parameters in the CRYP_IVInitStruct. - * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains - * the configuration information for the CRYP Initialization Vectors(IV). - * @retval None - */ -void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) -{ - CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left; - CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right; - CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left; - CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right; -} - -/** - * @brief Fills each CRYP_IVInitStruct member with its default value. - * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization - * Vectors(IV) structure which will be initialized. - * @retval None - */ -void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) -{ - CRYP_IVInitStruct->CRYP_IV0Left = 0; - CRYP_IVInitStruct->CRYP_IV0Right = 0; - CRYP_IVInitStruct->CRYP_IV1Left = 0; - CRYP_IVInitStruct->CRYP_IV1Right = 0; -} - -/** - * @brief Configures the AES-CCM and AES-GCM phases - * @note This function is used only with AES-CCM or AES-GCM Algorithms - * @param CRYP_Phase: specifies the CRYP AES-CCM and AES-GCM phase to be configured. - * This parameter can be one of the following values: - * @arg CRYP_Phase_Init: Initialization phase - * @arg CRYP_Phase_Header: Header phase - * @arg CRYP_Phase_Payload: Payload phase - * @arg CRYP_Phase_Final: Final phase - * @retval None - */ -void CRYP_PhaseConfig(uint32_t CRYP_Phase) -{ uint32_t tempcr = 0; - - /* Check the parameter */ - assert_param(IS_CRYP_PHASE(CRYP_Phase)); - - /* Get the CR register */ - tempcr = CRYP->CR; - - /* Reset the phase configuration bits: GCMP_CCMPH */ - tempcr &= (uint32_t)(~CRYP_CR_GCM_CCMPH); - /* Set the selected phase */ - tempcr |= (uint32_t)CRYP_Phase; - - /* Set the CR register */ - CRYP->CR = tempcr; -} - -/** - * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the - * FIFOs are reset) - * @note The FIFOs must be flushed only when BUSY flag is reset. - * @param None - * @retval None - */ -void CRYP_FIFOFlush(void) -{ - /* Reset the read and write pointers of the FIFOs */ - CRYP->CR |= CRYP_CR_FFLUSH; -} - -/** - * @brief Enables or disables the CRYP peripheral. - * @param NewState: new state of the CRYP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Cryptographic processor */ - CRYP->CR |= CRYP_CR_CRYPEN; - } - else - { - /* Disable the Cryptographic processor */ - CRYP->CR &= ~CRYP_CR_CRYPEN; - } -} -/** - * @} - */ - -/** @defgroup CRYP_Group2 CRYP Data processing functions - * @brief CRYP Data processing functions - * -@verbatim - =============================================================================== - ##### CRYP Data processing functions ##### - =============================================================================== - [..] This section provides functions allowing the encryption and decryption - operations: - (+) Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. - (+) Get the data result from the OUT FIFO : using CRYP_DataOut() function. - -@endverbatim - * @{ - */ - -/** - * @brief Writes data in the Data Input register (DIN). - * @note After the DIN register has been read once or several times, - * the FIFO must be flushed (using CRYP_FIFOFlush() function). - * @param Data: data to write in Data Input register - * @retval None - */ -void CRYP_DataIn(uint32_t Data) -{ - CRYP->DR = Data; -} - -/** - * @brief Returns the last data entered into the output FIFO. - * @param None - * @retval Last data entered into the output FIFO. - */ -uint32_t CRYP_DataOut(void) -{ - return CRYP->DOUT; -} -/** - * @} - */ - -/** @defgroup CRYP_Group3 Context swapping functions - * @brief Context swapping functions - * -@verbatim - =============================================================================== - ##### Context swapping functions ##### - =============================================================================== - [..] This section provides functions allowing to save and store CRYP Context - - [..] It is possible to interrupt an encryption/ decryption/ key generation process - to perform another processing with a higher priority, and to complete the - interrupted process later on, when the higher-priority task is complete. To do - so, the context of the interrupted task must be saved from the CRYP registers - to memory, and then be restored from memory to the CRYP registers. - - (#) To save the current context, use CRYP_SaveContext() function - (#) To restore the saved context, use CRYP_RestoreContext() function - -@endverbatim - * @{ - */ - -/** - * @brief Saves the CRYP peripheral Context. - * @note This function stops DMA transfer before to save the context. After - * restoring the context, you have to enable the DMA again (if the DMA - * was previously used). - * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains - * the repository for current context. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that - * contains the configuration information for the CRYP Keys. - * @retval None - */ -ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, - CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - __IO uint32_t timeout = 0; - uint32_t ckeckmask = 0, bitstatus; - ErrorStatus status = ERROR; - - /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */ - CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN; - - /* Wait until both the IN and OUT FIFOs are empty - (IFEM=1 and OFNE=0 in the CRYP_SR register) and the - BUSY bit is cleared. */ - - if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */ - { - ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ; - } - else /* AES or DES */ - { - ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE; - } - - do - { - bitstatus = CRYP->SR & ckeckmask; - timeout++; - } - while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM)); - - if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM) - { - status = ERROR; - } - else - { - /* Stop DMA transfers on the OUT FIFO by - - writing the DOEN bit to 0 in the CRYP_DMACR register - - and clear the CRYPEN bit. */ - - CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; - CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; - - /* Save the current configuration (bit 19, bit[17:16] and bits [9:2] in the CRYP_CR register) */ - CRYP_ContextSave->CR_CurrentConfig = CRYP->CR & (CRYP_CR_GCM_CCMPH | - CRYP_CR_KEYSIZE | - CRYP_CR_DATATYPE | - CRYP_CR_ALGOMODE | - CRYP_CR_ALGODIR); - - /* and, if not in ECB mode, the initialization vectors. */ - CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; - CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR; - CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR; - CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR; - - /* save The key value */ - CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; - CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; - CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; - CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; - CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; - CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; - CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; - CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; - - /* Save the content of context swap registers */ - CRYP_ContextSave->CRYP_CSGCMCCMR[0] = CRYP->CSGCMCCM0R; - CRYP_ContextSave->CRYP_CSGCMCCMR[1] = CRYP->CSGCMCCM1R; - CRYP_ContextSave->CRYP_CSGCMCCMR[2] = CRYP->CSGCMCCM2R; - CRYP_ContextSave->CRYP_CSGCMCCMR[3] = CRYP->CSGCMCCM3R; - CRYP_ContextSave->CRYP_CSGCMCCMR[4] = CRYP->CSGCMCCM4R; - CRYP_ContextSave->CRYP_CSGCMCCMR[5] = CRYP->CSGCMCCM5R; - CRYP_ContextSave->CRYP_CSGCMCCMR[6] = CRYP->CSGCMCCM6R; - CRYP_ContextSave->CRYP_CSGCMCCMR[7] = CRYP->CSGCMCCM7R; - - CRYP_ContextSave->CRYP_CSGCMR[0] = CRYP->CSGCM0R; - CRYP_ContextSave->CRYP_CSGCMR[1] = CRYP->CSGCM1R; - CRYP_ContextSave->CRYP_CSGCMR[2] = CRYP->CSGCM2R; - CRYP_ContextSave->CRYP_CSGCMR[3] = CRYP->CSGCM3R; - CRYP_ContextSave->CRYP_CSGCMR[4] = CRYP->CSGCM4R; - CRYP_ContextSave->CRYP_CSGCMR[5] = CRYP->CSGCM5R; - CRYP_ContextSave->CRYP_CSGCMR[6] = CRYP->CSGCM6R; - CRYP_ContextSave->CRYP_CSGCMR[7] = CRYP->CSGCM7R; - - /* When needed, save the DMA status (pointers for IN and OUT messages, - number of remaining bytes, etc.) */ - - status = SUCCESS; - } - - return status; -} - -/** - * @brief Restores the CRYP peripheral Context. - * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function, - * after restoring the context, you have to enable the DMA again (if the - * DMA was previously used). - * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains - * the repository for saved context. - * @note The data that were saved during context saving must be rewrited into - * the IN FIFO. - * @retval None - */ -void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) -{ - - /* Configure the processor with the saved configuration */ - CRYP->CR = CRYP_ContextRestore->CR_CurrentConfig; - - /* restore The key value */ - CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; - CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR; - CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR; - CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR; - CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR; - CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR; - CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR; - CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR; - - /* and the initialization vectors. */ - CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR; - CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR; - CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; - CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; - - /* Restore the content of context swap registers */ - CRYP->CSGCMCCM0R = CRYP_ContextRestore->CRYP_CSGCMCCMR[0]; - CRYP->CSGCMCCM1R = CRYP_ContextRestore->CRYP_CSGCMCCMR[1]; - CRYP->CSGCMCCM2R = CRYP_ContextRestore->CRYP_CSGCMCCMR[2]; - CRYP->CSGCMCCM3R = CRYP_ContextRestore->CRYP_CSGCMCCMR[3]; - CRYP->CSGCMCCM4R = CRYP_ContextRestore->CRYP_CSGCMCCMR[4]; - CRYP->CSGCMCCM5R = CRYP_ContextRestore->CRYP_CSGCMCCMR[5]; - CRYP->CSGCMCCM6R = CRYP_ContextRestore->CRYP_CSGCMCCMR[6]; - CRYP->CSGCMCCM7R = CRYP_ContextRestore->CRYP_CSGCMCCMR[7]; - - CRYP->CSGCM0R = CRYP_ContextRestore->CRYP_CSGCMR[0]; - CRYP->CSGCM1R = CRYP_ContextRestore->CRYP_CSGCMR[1]; - CRYP->CSGCM2R = CRYP_ContextRestore->CRYP_CSGCMR[2]; - CRYP->CSGCM3R = CRYP_ContextRestore->CRYP_CSGCMR[3]; - CRYP->CSGCM4R = CRYP_ContextRestore->CRYP_CSGCMR[4]; - CRYP->CSGCM5R = CRYP_ContextRestore->CRYP_CSGCMR[5]; - CRYP->CSGCM6R = CRYP_ContextRestore->CRYP_CSGCMR[6]; - CRYP->CSGCM7R = CRYP_ContextRestore->CRYP_CSGCMR[7]; - - /* Enable the cryptographic processor */ - CRYP->CR |= CRYP_CR_CRYPEN; -} -/** - * @} - */ - -/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function - * @brief CRYP's DMA interface Configuration function - * -@verbatim - =============================================================================== - ##### CRYP's DMA interface Configuration function ##### - =============================================================================== - [..] This section provides functions allowing to configure the DMA interface for - CRYP data input and output transfer. - - [..] When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be - transferred: - (+) From memory to the CRYP IN FIFO using the DMA peripheral by enabling - the CRYP_DMAReq_DataIN request. - (+) From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling - the CRYP_DMAReq_DataOUT request. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRYP DMA interface. - * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer - * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer - * @param NewState: new state of the selected CRYP DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CRYP DMA request */ - CRYP->DMACR |= CRYP_DMAReq; - } - else - { - /* Disable the selected CRYP DMA request */ - CRYP->DMACR &= (uint8_t)~CRYP_DMAReq; - } -} -/** - * @} - */ - -/** @defgroup CRYP_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the CRYP Interrupts and - to get the status and Interrupts pending bits. - - [..] The CRYP provides 2 Interrupts sources and 7 Flags: - - *** Flags : *** - =============== - [..] - (#) CRYP_FLAG_IFEM : Set when Input FIFO is empty. This Flag is cleared only - by hardware. - - (#) CRYP_FLAG_IFNF : Set when Input FIFO is not full. This Flag is cleared - only by hardware. - - - (#) CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending it gives - the raw interrupt state prior to masking of the input FIFO service interrupt. - This Flag is cleared only by hardware. - - (#) CRYP_FLAG_OFNE : Set when Output FIFO not empty. This Flag is cleared - only by hardware. - - (#) CRYP_FLAG_OFFU : Set when Output FIFO is full. This Flag is cleared only - by hardware. - - (#) CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives - the raw interrupt state prior to masking of the output FIFO service interrupt. - This Flag is cleared only by hardware. - - (#) CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a block - of data or a key preparation (for AES decryption). This Flag is cleared - only by hardware. To clear it, the CRYP core must be disabled and the last - processing has completed. - - *** Interrupts : *** - ==================== - [..] - (#) CRYP_IT_INI : The input FIFO service interrupt is asserted when there - are less than 4 words in the input FIFO. This interrupt is associated to - CRYP_FLAG_INRIS flag. - - -@- This interrupt is cleared by performing write operations to the input FIFO - until it holds 4 or more words. The input FIFO service interrupt INMIS is - enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the - INMIS signal is low even if the input FIFO is empty. - - - - (#) CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there - is one or more (32-bit word) data items in the output FIFO. This interrupt - is associated to CRYP_FLAG_OUTRIS flag. - - -@- This interrupt is cleared by reading data from the output FIFO until there - is no valid (32-bit) word left (that is, the interrupt follows the state - of the OFNE (output FIFO not empty) flag). - - *** Managing the CRYP controller events : *** - ============================================= - [..] The user should identify which mode will be used in his application to manage - the CRYP controller events: Polling mode or Interrupt mode. - - (#) In the Polling Mode it is advised to use the following functions: - (++) CRYP_GetFlagStatus() : to check if flags events occur. - - -@@- The CRYPT flags do not need to be cleared since they are cleared as - soon as the associated event are reset. - - - (#) In the Interrupt Mode it is advised to use the following functions: - (++) CRYP_ITConfig() : to enable or disable the interrupt source. - (++) CRYP_GetITStatus() : to check if Interrupt occurs. - - -@@- The CRYPT interrupts have no pending bits, the interrupt is cleared as - soon as the associated event is reset. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified CRYP interrupts. - * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRYP_IT_INI: Input FIFO interrupt - * @arg CRYP_IT_OUTI: Output FIFO interrupt - * @param NewState: new state of the specified CRYP interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRYP_CONFIG_IT(CRYP_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CRYP interrupt */ - CRYP->IMSCR |= CRYP_IT; - } - else - { - /* Disable the selected CRYP interrupt */ - CRYP->IMSCR &= (uint8_t)~CRYP_IT; - } -} - -/** - * @brief Checks whether the specified CRYP interrupt has occurred or not. - * @note This function checks the status of the masked interrupt (i.e the - * interrupt should be previously enabled). - * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check. - * This parameter can be one of the following values: - * @arg CRYP_IT_INI: Input FIFO interrupt - * @arg CRYP_IT_OUTI: Output FIFO interrupt - * @retval The new state of CRYP_IT (SET or RESET). - */ -ITStatus CRYP_GetITStatus(uint8_t CRYP_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_CRYP_GET_IT(CRYP_IT)); - - /* Check the status of the specified CRYP interrupt */ - if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET) - { - /* CRYP_IT is set */ - bitstatus = SET; - } - else - { - /* CRYP_IT is reset */ - bitstatus = RESET; - } - /* Return the CRYP_IT status */ - return bitstatus; -} - -/** - * @brief Returns whether CRYP peripheral is enabled or disabled. - * @param none. - * @retval Current state of the CRYP peripheral (ENABLE or DISABLE). - */ -FunctionalState CRYP_GetCmdStatus(void) -{ - FunctionalState state = DISABLE; - - if ((CRYP->CR & CRYP_CR_CRYPEN) != 0) - { - /* CRYPEN bit is set */ - state = ENABLE; - } - else - { - /* CRYPEN bit is reset */ - state = DISABLE; - } - return state; -} - -/** - * @brief Checks whether the specified CRYP flag is set or not. - * @param CRYP_FLAG: specifies the CRYP flag to check. - * This parameter can be one of the following values: - * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag. - * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag. - * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag. - * @arg CRYP_FLAG_OFFU: Output FIFO Full flag. - * @arg CRYP_FLAG_BUSY: Busy flag. - * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag. - * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag. - * @retval The new state of CRYP_FLAG (SET or RESET). - */ -FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tempreg = 0; - - /* Check the parameters */ - assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG)); - - /* check if the FLAG is in RISR register */ - if ((CRYP_FLAG & FLAG_MASK) != 0x00) - { - tempreg = CRYP->RISR; - } - else /* The FLAG is in SR register */ - { - tempreg = CRYP->SR; - } - - - /* Check the status of the specified CRYP flag */ - if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET) - { - /* CRYP_FLAG is set */ - bitstatus = SET; - } - else - { - /* CRYP_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the CRYP_FLAG status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_cryp.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Cryptographic processor (CRYP) peripheral: + * + Initialization and Configuration functions + * + Data treatment functions + * + Context swapping functions + * + DMA interface function + * + Interrupts and flags management + * +@verbatim + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) Enable the CRYP controller clock using + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. + + (#) Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed + CRYP_IVInit(). + + (#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. + + (#) Enable the CRYP controller using the CRYP_Cmd() function. + + (#) If using DMA for Data input and output transfer, activate the needed DMA + Requests using CRYP_DMACmd() function + + (#) If DMA is not used for data transfer, use CRYP_DataIn() and CRYP_DataOut() + functions to enter data to IN FIFO and get result from OUT FIFO. + + (#) To control CRYP events you can use one of the following two methods: + (++) Check on CRYP flags using the CRYP_GetFlagStatus() function. + (++) Use CRYP interrupts through the function CRYP_ITConfig() at + initialization phase and CRYP_GetITStatus() function into interrupt + routines in processing phase. + + (#) Save and restore Cryptographic processor context using CRYP_SaveContext() + and CRYP_RestoreContext() functions. + + + *** Procedure to perform an encryption or a decryption *** + ========================================================== + + *** Initialization *** + ====================== + [..] + (#) Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and CRYP_IVInit + functions: + (++) Configure the key size (128-, 192- or 256-bit, in the AES only) + (++) Enter the symmetric key + (++) Configure the data type + (++) In case of decryption in AES-ECB or AES-CBC, you must prepare + the key: configure the key preparation mode. Then Enable the CRYP + peripheral using CRYP_Cmd() function: the BUSY flag is set. + Wait until BUSY flag is reset : the key is prepared for decryption + (++) Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the + AES in ECB/CBC/CTR) + (++) Configure the direction (encryption/decryption). + (++) Write the initialization vectors (in CBC or CTR modes only) + + (#) Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function + + + *** Basic Processing mode (polling mode) *** + ============================================ + [..] + (#) Enable the cryptographic processor using CRYP_Cmd() function. + + (#) Write the first blocks in the input FIFO (2 to 8 words) using + CRYP_DataIn() function. + + (#) Repeat the following sequence until the complete message has been + processed: + + (++) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() + function), then read the OUT-FIFO using CRYP_DataOut() function + (1 block or until the FIFO is empty) + + (++) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() + function then write the IN FIFO using CRYP_DataIn() function + (1 block or until the FIFO is full) + + (#) At the end of the processing, CRYP_FLAG_BUSY flag will be reset and + both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is + reset). You can disable the peripheral using CRYP_Cmd() function. + + *** Interrupts Processing mode *** + ================================== + [..] In this mode, Processing is done when the data are transferred by the + CPU during interrupts. + + (#) Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using CRYP_ITConfig() + function. + + (#) Enable the cryptographic processor using CRYP_Cmd() function. + + (#) In the CRYP_IT_INI interrupt handler : load the input message into the + IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a + time, or load data until the IN FIFO is full. When the last word of + the message has been entered into the IN FIFO, disable the CRYP_IT_INI + interrupt (using CRYP_ITConfig() function). + + (#) In the CRYP_IT_OUTI interrupt handler : read the output message from + the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or + 4 words) at a time or read data until the FIFO is empty. + When the last word has been read, INIM=0, BUSY=0 and both FIFOs are + empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). + You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() + function) and you can disable the peripheral using CRYP_Cmd() function. + + *** DMA Processing mode *** + =========================== + [..] In this mode, Processing is done when the DMA is used to transfer the + data from/to the memory. + + (#) Configure the DMA controller to transfer the input data from the + memory using DMA_Init() function. + The transfer length is the length of the message. + As message padding is not managed by the peripheral, the message + length must be an entire number of blocks. The data are transferred + in burst mode. The burst length is 4 words in the AES and 2 or 4 + words in the DES/TDES. The DMA should be configured to set an + interrupt on transfer completion of the output data to indicate that + the processing is finished. + Refer to DMA peripheral driver for more details. + + (#) Enable the cryptographic processor using CRYP_Cmd() function. + Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT + using CRYP_DMACmd() function. + + (#) All the transfers and processing are managed by the DMA and the + cryptographic processor. The DMA transfer complete interrupt indicates + that the processing is complete. Both FIFOs are normally empty and + CRYP_FLAG_BUSY flag is reset. + + @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_cryp.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define FLAG_MASK ((uint8_t)0x20) +#define MAX_TIMEOUT ((uint16_t)0xFFFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to + (+) Initialize the cryptographic Processor using CRYP_Init() function + (++) Encrypt or Decrypt + (++) mode : TDES-ECB, TDES-CBC, + DES-ECB, DES-CBC, + AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM, AES-CCM + (++) DataType : 32-bit data, 16-bit data, bit data or bit-string + (++) Key Size (only in AES modes) + (+) Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function + (+) Configure the Initialization Vectors(IV) for CBC and CTR modes using + CRYP_IVInit() function. + (+) Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. + (+) Enable or disable the CRYP Processor using CRYP_Cmd() function + +@endverbatim + * @{ + */ +/** + * @brief Deinitializes the CRYP peripheral registers to their default reset values + * @param None + * @retval None + */ +void CRYP_DeInit(void) +{ + /* Enable CRYP reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE); + + /* Release CRYP from reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE); +} + +/** + * @brief Initializes the CRYP peripheral according to the specified parameters + * in the CRYP_InitStruct. + * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains + * the configuration information for the CRYP peripheral. + * @retval None + */ +void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode)); + assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType)); + assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir)); + + /* Select Algorithm mode*/ + CRYP->CR &= ~CRYP_CR_ALGOMODE; + CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode; + + /* Select dataType */ + CRYP->CR &= ~CRYP_CR_DATATYPE; + CRYP->CR |= CRYP_InitStruct->CRYP_DataType; + + /* select Key size (used only with AES algorithm) */ + if ((CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_ECB) && + (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_CBC) && + (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_ECB) && + (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_CBC)) + { + assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); + CRYP->CR &= ~CRYP_CR_KEYSIZE; + CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be + configured once the key has + been prepared */ + } + + /* Select data Direction */ + CRYP->CR &= ~CRYP_CR_ALGODIR; + CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir; +} + +/** + * @brief Fills each CRYP_InitStruct member with its default value. + * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct) +{ + /* Initialize the CRYP_AlgoDir member */ + CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + + /* initialize the CRYP_AlgoMode member */ + CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; + + /* initialize the CRYP_DataType member */ + CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b; + + /* Initialize the CRYP_KeySize member */ + CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b; +} + +/** + * @brief Initializes the CRYP Keys according to the specified parameters in + * the CRYP_KeyInitStruct. + * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that + * contains the configuration information for the CRYP Keys. + * @retval None + */ +void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) +{ + /* Key Initialisation */ + CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; + CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; + CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; + CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; + CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; + CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; + CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; + CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; +} + +/** + * @brief Fills each CRYP_KeyInitStruct member with its default value. + * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure + * which will be initialized. + * @retval None + */ +void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) +{ + CRYP_KeyInitStruct->CRYP_Key0Left = 0; + CRYP_KeyInitStruct->CRYP_Key0Right = 0; + CRYP_KeyInitStruct->CRYP_Key1Left = 0; + CRYP_KeyInitStruct->CRYP_Key1Right = 0; + CRYP_KeyInitStruct->CRYP_Key2Left = 0; + CRYP_KeyInitStruct->CRYP_Key2Right = 0; + CRYP_KeyInitStruct->CRYP_Key3Left = 0; + CRYP_KeyInitStruct->CRYP_Key3Right = 0; +} +/** + * @brief Initializes the CRYP Initialization Vectors(IV) according to the + * specified parameters in the CRYP_IVInitStruct. + * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains + * the configuration information for the CRYP Initialization Vectors(IV). + * @retval None + */ +void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) +{ + CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left; + CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right; + CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left; + CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right; +} + +/** + * @brief Fills each CRYP_IVInitStruct member with its default value. + * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization + * Vectors(IV) structure which will be initialized. + * @retval None + */ +void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) +{ + CRYP_IVInitStruct->CRYP_IV0Left = 0; + CRYP_IVInitStruct->CRYP_IV0Right = 0; + CRYP_IVInitStruct->CRYP_IV1Left = 0; + CRYP_IVInitStruct->CRYP_IV1Right = 0; +} + +/** + * @brief Configures the AES-CCM and AES-GCM phases + * @note This function is used only with AES-CCM or AES-GCM Algorithms + * @param CRYP_Phase: specifies the CRYP AES-CCM and AES-GCM phase to be configured. + * This parameter can be one of the following values: + * @arg CRYP_Phase_Init: Initialization phase + * @arg CRYP_Phase_Header: Header phase + * @arg CRYP_Phase_Payload: Payload phase + * @arg CRYP_Phase_Final: Final phase + * @retval None + */ +void CRYP_PhaseConfig(uint32_t CRYP_Phase) +{ uint32_t tempcr = 0; + + /* Check the parameter */ + assert_param(IS_CRYP_PHASE(CRYP_Phase)); + + /* Get the CR register */ + tempcr = CRYP->CR; + + /* Reset the phase configuration bits: GCMP_CCMPH */ + tempcr &= (uint32_t)(~CRYP_CR_GCM_CCMPH); + /* Set the selected phase */ + tempcr |= (uint32_t)CRYP_Phase; + + /* Set the CR register */ + CRYP->CR = tempcr; +} + +/** + * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the + * FIFOs are reset) + * @note The FIFOs must be flushed only when BUSY flag is reset. + * @param None + * @retval None + */ +void CRYP_FIFOFlush(void) +{ + /* Reset the read and write pointers of the FIFOs */ + CRYP->CR |= CRYP_CR_FFLUSH; +} + +/** + * @brief Enables or disables the CRYP peripheral. + * @param NewState: new state of the CRYP peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRYP_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Cryptographic processor */ + CRYP->CR |= CRYP_CR_CRYPEN; + } + else + { + /* Disable the Cryptographic processor */ + CRYP->CR &= ~CRYP_CR_CRYPEN; + } +} +/** + * @} + */ + +/** @defgroup CRYP_Group2 CRYP Data processing functions + * @brief CRYP Data processing functions + * +@verbatim + =============================================================================== + ##### CRYP Data processing functions ##### + =============================================================================== + [..] This section provides functions allowing the encryption and decryption + operations: + (+) Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. + (+) Get the data result from the OUT FIFO : using CRYP_DataOut() function. + +@endverbatim + * @{ + */ + +/** + * @brief Writes data in the Data Input register (DIN). + * @note After the DIN register has been read once or several times, + * the FIFO must be flushed (using CRYP_FIFOFlush() function). + * @param Data: data to write in Data Input register + * @retval None + */ +void CRYP_DataIn(uint32_t Data) +{ + CRYP->DR = Data; +} + +/** + * @brief Returns the last data entered into the output FIFO. + * @param None + * @retval Last data entered into the output FIFO. + */ +uint32_t CRYP_DataOut(void) +{ + return CRYP->DOUT; +} +/** + * @} + */ + +/** @defgroup CRYP_Group3 Context swapping functions + * @brief Context swapping functions + * +@verbatim + =============================================================================== + ##### Context swapping functions ##### + =============================================================================== + [..] This section provides functions allowing to save and store CRYP Context + + [..] It is possible to interrupt an encryption/ decryption/ key generation process + to perform another processing with a higher priority, and to complete the + interrupted process later on, when the higher-priority task is complete. To do + so, the context of the interrupted task must be saved from the CRYP registers + to memory, and then be restored from memory to the CRYP registers. + + (#) To save the current context, use CRYP_SaveContext() function + (#) To restore the saved context, use CRYP_RestoreContext() function + +@endverbatim + * @{ + */ + +/** + * @brief Saves the CRYP peripheral Context. + * @note This function stops DMA transfer before to save the context. After + * restoring the context, you have to enable the DMA again (if the DMA + * was previously used). + * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains + * the repository for current context. + * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that + * contains the configuration information for the CRYP Keys. + * @retval None + */ +ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, + CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) +{ + __IO uint32_t timeout = 0; + uint32_t ckeckmask = 0, bitstatus; + ErrorStatus status = ERROR; + + /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */ + CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN; + + /* Wait until both the IN and OUT FIFOs are empty + (IFEM=1 and OFNE=0 in the CRYP_SR register) and the + BUSY bit is cleared. */ + + if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */ + { + ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ; + } + else /* AES or DES */ + { + ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE; + } + + do + { + bitstatus = CRYP->SR & ckeckmask; + timeout++; + } + while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM)); + + if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM) + { + status = ERROR; + } + else + { + /* Stop DMA transfers on the OUT FIFO by + - writing the DOEN bit to 0 in the CRYP_DMACR register + - and clear the CRYPEN bit. */ + + CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; + CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; + + /* Save the current configuration (bit 19, bit[17:16] and bits [9:2] in the CRYP_CR register) */ + CRYP_ContextSave->CR_CurrentConfig = CRYP->CR & (CRYP_CR_GCM_CCMPH | + CRYP_CR_KEYSIZE | + CRYP_CR_DATATYPE | + CRYP_CR_ALGOMODE | + CRYP_CR_ALGODIR); + + /* and, if not in ECB mode, the initialization vectors. */ + CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; + CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR; + CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR; + CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR; + + /* save The key value */ + CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; + CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; + CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; + CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; + CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; + CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; + CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; + CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; + + /* Save the content of context swap registers */ + CRYP_ContextSave->CRYP_CSGCMCCMR[0] = CRYP->CSGCMCCM0R; + CRYP_ContextSave->CRYP_CSGCMCCMR[1] = CRYP->CSGCMCCM1R; + CRYP_ContextSave->CRYP_CSGCMCCMR[2] = CRYP->CSGCMCCM2R; + CRYP_ContextSave->CRYP_CSGCMCCMR[3] = CRYP->CSGCMCCM3R; + CRYP_ContextSave->CRYP_CSGCMCCMR[4] = CRYP->CSGCMCCM4R; + CRYP_ContextSave->CRYP_CSGCMCCMR[5] = CRYP->CSGCMCCM5R; + CRYP_ContextSave->CRYP_CSGCMCCMR[6] = CRYP->CSGCMCCM6R; + CRYP_ContextSave->CRYP_CSGCMCCMR[7] = CRYP->CSGCMCCM7R; + + CRYP_ContextSave->CRYP_CSGCMR[0] = CRYP->CSGCM0R; + CRYP_ContextSave->CRYP_CSGCMR[1] = CRYP->CSGCM1R; + CRYP_ContextSave->CRYP_CSGCMR[2] = CRYP->CSGCM2R; + CRYP_ContextSave->CRYP_CSGCMR[3] = CRYP->CSGCM3R; + CRYP_ContextSave->CRYP_CSGCMR[4] = CRYP->CSGCM4R; + CRYP_ContextSave->CRYP_CSGCMR[5] = CRYP->CSGCM5R; + CRYP_ContextSave->CRYP_CSGCMR[6] = CRYP->CSGCM6R; + CRYP_ContextSave->CRYP_CSGCMR[7] = CRYP->CSGCM7R; + + /* When needed, save the DMA status (pointers for IN and OUT messages, + number of remaining bytes, etc.) */ + + status = SUCCESS; + } + + return status; +} + +/** + * @brief Restores the CRYP peripheral Context. + * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function, + * after restoring the context, you have to enable the DMA again (if the + * DMA was previously used). + * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains + * the repository for saved context. + * @note The data that were saved during context saving must be rewrited into + * the IN FIFO. + * @retval None + */ +void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) +{ + + /* Configure the processor with the saved configuration */ + CRYP->CR = CRYP_ContextRestore->CR_CurrentConfig; + + /* restore The key value */ + CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; + CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR; + CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR; + CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR; + CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR; + CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR; + CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR; + CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR; + + /* and the initialization vectors. */ + CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR; + CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR; + CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; + CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; + + /* Restore the content of context swap registers */ + CRYP->CSGCMCCM0R = CRYP_ContextRestore->CRYP_CSGCMCCMR[0]; + CRYP->CSGCMCCM1R = CRYP_ContextRestore->CRYP_CSGCMCCMR[1]; + CRYP->CSGCMCCM2R = CRYP_ContextRestore->CRYP_CSGCMCCMR[2]; + CRYP->CSGCMCCM3R = CRYP_ContextRestore->CRYP_CSGCMCCMR[3]; + CRYP->CSGCMCCM4R = CRYP_ContextRestore->CRYP_CSGCMCCMR[4]; + CRYP->CSGCMCCM5R = CRYP_ContextRestore->CRYP_CSGCMCCMR[5]; + CRYP->CSGCMCCM6R = CRYP_ContextRestore->CRYP_CSGCMCCMR[6]; + CRYP->CSGCMCCM7R = CRYP_ContextRestore->CRYP_CSGCMCCMR[7]; + + CRYP->CSGCM0R = CRYP_ContextRestore->CRYP_CSGCMR[0]; + CRYP->CSGCM1R = CRYP_ContextRestore->CRYP_CSGCMR[1]; + CRYP->CSGCM2R = CRYP_ContextRestore->CRYP_CSGCMR[2]; + CRYP->CSGCM3R = CRYP_ContextRestore->CRYP_CSGCMR[3]; + CRYP->CSGCM4R = CRYP_ContextRestore->CRYP_CSGCMR[4]; + CRYP->CSGCM5R = CRYP_ContextRestore->CRYP_CSGCMR[5]; + CRYP->CSGCM6R = CRYP_ContextRestore->CRYP_CSGCMR[6]; + CRYP->CSGCM7R = CRYP_ContextRestore->CRYP_CSGCMR[7]; + + /* Enable the cryptographic processor */ + CRYP->CR |= CRYP_CR_CRYPEN; +} +/** + * @} + */ + +/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function + * @brief CRYP's DMA interface Configuration function + * +@verbatim + =============================================================================== + ##### CRYP's DMA interface Configuration function ##### + =============================================================================== + [..] This section provides functions allowing to configure the DMA interface for + CRYP data input and output transfer. + + [..] When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be + transferred: + (+) From memory to the CRYP IN FIFO using the DMA peripheral by enabling + the CRYP_DMAReq_DataIN request. + (+) From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling + the CRYP_DMAReq_DataOUT request. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the CRYP DMA interface. + * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer + * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer + * @param NewState: new state of the selected CRYP DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CRYP DMA request */ + CRYP->DMACR |= CRYP_DMAReq; + } + else + { + /* Disable the selected CRYP DMA request */ + CRYP->DMACR &= (uint8_t)~CRYP_DMAReq; + } +} +/** + * @} + */ + +/** @defgroup CRYP_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure the CRYP Interrupts and + to get the status and Interrupts pending bits. + + [..] The CRYP provides 2 Interrupts sources and 7 Flags: + + *** Flags : *** + =============== + [..] + (#) CRYP_FLAG_IFEM : Set when Input FIFO is empty. This Flag is cleared only + by hardware. + + (#) CRYP_FLAG_IFNF : Set when Input FIFO is not full. This Flag is cleared + only by hardware. + + + (#) CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending it gives + the raw interrupt state prior to masking of the input FIFO service interrupt. + This Flag is cleared only by hardware. + + (#) CRYP_FLAG_OFNE : Set when Output FIFO not empty. This Flag is cleared + only by hardware. + + (#) CRYP_FLAG_OFFU : Set when Output FIFO is full. This Flag is cleared only + by hardware. + + (#) CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives + the raw interrupt state prior to masking of the output FIFO service interrupt. + This Flag is cleared only by hardware. + + (#) CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a block + of data or a key preparation (for AES decryption). This Flag is cleared + only by hardware. To clear it, the CRYP core must be disabled and the last + processing has completed. + + *** Interrupts : *** + ==================== + [..] + (#) CRYP_IT_INI : The input FIFO service interrupt is asserted when there + are less than 4 words in the input FIFO. This interrupt is associated to + CRYP_FLAG_INRIS flag. + + -@- This interrupt is cleared by performing write operations to the input FIFO + until it holds 4 or more words. The input FIFO service interrupt INMIS is + enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the + INMIS signal is low even if the input FIFO is empty. + + + + (#) CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there + is one or more (32-bit word) data items in the output FIFO. This interrupt + is associated to CRYP_FLAG_OUTRIS flag. + + -@- This interrupt is cleared by reading data from the output FIFO until there + is no valid (32-bit) word left (that is, the interrupt follows the state + of the OFNE (output FIFO not empty) flag). + + *** Managing the CRYP controller events : *** + ============================================= + [..] The user should identify which mode will be used in his application to manage + the CRYP controller events: Polling mode or Interrupt mode. + + (#) In the Polling Mode it is advised to use the following functions: + (++) CRYP_GetFlagStatus() : to check if flags events occur. + + -@@- The CRYPT flags do not need to be cleared since they are cleared as + soon as the associated event are reset. + + + (#) In the Interrupt Mode it is advised to use the following functions: + (++) CRYP_ITConfig() : to enable or disable the interrupt source. + (++) CRYP_GetITStatus() : to check if Interrupt occurs. + + -@@- The CRYPT interrupts have no pending bits, the interrupt is cleared as + soon as the associated event is reset. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified CRYP interrupts. + * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CRYP_IT_INI: Input FIFO interrupt + * @arg CRYP_IT_OUTI: Output FIFO interrupt + * @param NewState: new state of the specified CRYP interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CRYP_CONFIG_IT(CRYP_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CRYP interrupt */ + CRYP->IMSCR |= CRYP_IT; + } + else + { + /* Disable the selected CRYP interrupt */ + CRYP->IMSCR &= (uint8_t)~CRYP_IT; + } +} + +/** + * @brief Checks whether the specified CRYP interrupt has occurred or not. + * @note This function checks the status of the masked interrupt (i.e the + * interrupt should be previously enabled). + * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check. + * This parameter can be one of the following values: + * @arg CRYP_IT_INI: Input FIFO interrupt + * @arg CRYP_IT_OUTI: Output FIFO interrupt + * @retval The new state of CRYP_IT (SET or RESET). + */ +ITStatus CRYP_GetITStatus(uint8_t CRYP_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_CRYP_GET_IT(CRYP_IT)); + + /* Check the status of the specified CRYP interrupt */ + if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET) + { + /* CRYP_IT is set */ + bitstatus = SET; + } + else + { + /* CRYP_IT is reset */ + bitstatus = RESET; + } + /* Return the CRYP_IT status */ + return bitstatus; +} + +/** + * @brief Returns whether CRYP peripheral is enabled or disabled. + * @param none. + * @retval Current state of the CRYP peripheral (ENABLE or DISABLE). + */ +FunctionalState CRYP_GetCmdStatus(void) +{ + FunctionalState state = DISABLE; + + if ((CRYP->CR & CRYP_CR_CRYPEN) != 0) + { + /* CRYPEN bit is set */ + state = ENABLE; + } + else + { + /* CRYPEN bit is reset */ + state = DISABLE; + } + return state; +} + +/** + * @brief Checks whether the specified CRYP flag is set or not. + * @param CRYP_FLAG: specifies the CRYP flag to check. + * This parameter can be one of the following values: + * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag. + * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag. + * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag. + * @arg CRYP_FLAG_OFFU: Output FIFO Full flag. + * @arg CRYP_FLAG_BUSY: Busy flag. + * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag. + * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag. + * @retval The new state of CRYP_FLAG (SET or RESET). + */ +FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tempreg = 0; + + /* Check the parameters */ + assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG)); + + /* check if the FLAG is in RISR register */ + if ((CRYP_FLAG & FLAG_MASK) != 0x00) + { + tempreg = CRYP->RISR; + } + else /* The FLAG is in SR register */ + { + tempreg = CRYP->SR; + } + + + /* Check the status of the specified CRYP flag */ + if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET) + { + /* CRYP_FLAG is set */ + bitstatus = SET; + } + else + { + /* CRYP_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the CRYP_FLAG status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c index efcab7b1f..af8d7d1ed 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c @@ -1,1707 +1,1707 @@ -/** - ****************************************************************************** - * @file stm32f4xx_cryp_aes.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides high level functions to encrypt and decrypt an - * input message using AES in ECB/CBC/CTR/GCM/CCM modes. - * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP - * peripheral. - * AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices. - * For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available. - * -@verbatim - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable The CRYP controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - - (#) Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() function. - - (#) Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() function. - - (#) Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() function. - - (#) Encrypt and decrypt using AES in GCM Mode using CRYP_AES_GCM() function. - - (#) Encrypt and decrypt using AES in CCM Mode using CRYP_AES_CCM() function. - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group6 High Level AES functions - * @brief High Level AES functions - * -@verbatim - =============================================================================== - ##### High Level AES functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using AES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for AES algorithm. - * @param Keysize: length of the Key, must be a 128, 192 or 256. - * @param Input: pointer to the Input buffer. - * @param Ilength: length of the Input buffer, must be a multiple of 16. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize, - uint8_t* Input, uint32_t Ilength, uint8_t* Output) -{ - CRYP_InitTypeDef AES_CRYP_InitStructure; - CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); - - switch(Keysize) - { - case 128: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 192: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 256: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; - AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - default: - break; - } - - /*------------------ AES Decryption ------------------*/ - if(Mode == MODE_DECRYPT) /* AES decryption */ - { - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Crypto Init for Key preparation for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; - CRYP_Init(&AES_CRYP_InitStructure); - - /* Key Initialisation */ - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - /* wait until the Busy flag is RESET */ - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - else - { - /* Crypto Init for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - } - /*------------------ AES Encryption ------------------*/ - else /* AES encryption */ - { - - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&AES_CRYP_InitStructure); - - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(i=0; ((i>32)); - CRYP_DataIn(__REV(headerlength)); - CRYP_DataIn(__REV(inputlength>>32)); - CRYP_DataIn(__REV(inputlength)); - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - tagaddr = (uint32_t)AuthTAG; - /* Read the Auth TAG in the IN FIFO */ - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - } - /*------------------ AES Decryption ------------------*/ - else /* AES decryption */ - { - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Key Initialisation */ - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* CRYP Initialization Vectors */ - CRYP_IVInit(&AES_CRYP_IVInitStructure); - - /* Crypto Init for Key preparation for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_GCM; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&AES_CRYP_InitStructure); - - /***************************** Init phase *********************************/ - /* Select init phase */ - CRYP_PhaseConfig(CRYP_Phase_Init); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - /* Wait for CRYPEN bit to be 0 */ - while(CRYP_GetCmdStatus() == ENABLE) - { - } - - /***************************** header phase *******************************/ - if(HLength != 0) - { - /* Select header phase */ - CRYP_PhaseConfig(CRYP_Phase_Header); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; (loopcounter < HLength); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - } - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - } - - /**************************** payload phase *******************************/ - if(ILength != 0) - { - /* Select payload phase */ - CRYP_PhaseConfig(CRYP_Phase_Payload); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - else - { - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - } - } - } - - /***************************** final phase ********************************/ - /* Select final phase */ - CRYP_PhaseConfig(CRYP_Phase_Final); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - /* Write number of bits concatenated with header in the IN FIFO */ - CRYP_DataIn(__REV(headerlength>>32)); - CRYP_DataIn(__REV(headerlength)); - CRYP_DataIn(__REV(inputlength>>32)); - CRYP_DataIn(__REV(inputlength)); - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - tagaddr = (uint32_t)AuthTAG; - /* Read the Auth TAG in the IN FIFO */ - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - } - /* Disable Crypto */ - CRYP_Cmd(DISABLE); - - return status; -} - -/** - * @brief Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes - * are available only on STM32F437x Devices. - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Nonce: the nounce used for AES algorithm. It shall be unique for each processing. - * @param Key: Key used for AES algorithm. - * @param Keysize: length of the Key, must be a 128, 192 or 256. - * @param Input: pointer to the Input buffer. - * @param Ilength: length of the Input buffer in bytes, must be a multiple of 16. - * @param Header: pointer to the header buffer. - * @param Hlength: length of the header buffer in bytes. - * @param HBuffer: pointer to temporary buffer used to append the header - * HBuffer size must be equal to Hlength + 21 - * @param Output: pointer to the returned buffer. - * @param AuthTAG: pointer to the authentication TAG buffer. - * @param TAGSize: the size of the TAG (called also MAC). - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_AES_CCM(uint8_t Mode, - uint8_t* Nonce, uint32_t NonceSize, - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t ILength, - uint8_t *Header, uint32_t HLength, uint8_t *HBuffer, - uint8_t *Output, - uint8_t *AuthTAG, uint32_t TAGSize) -{ - CRYP_InitTypeDef AES_CRYP_InitStructure; - CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; - CRYP_IVInitTypeDef AES_CRYP_IVInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t headeraddr = (uint32_t)Header; - uint32_t tagaddr = (uint32_t)AuthTAG; - uint32_t headersize = HLength; - uint32_t loopcounter = 0; - uint32_t bufferidx = 0; - uint8_t blockb0[16] = {0};/* Block B0 */ - uint8_t ctr[16] = {0}; /* Counter */ - uint32_t temptag[4] = {0}; /* temporary TAG (MAC) */ - uint32_t ctraddr = (uint32_t)ctr; - uint32_t b0addr = (uint32_t)blockb0; - - /************************ Formatting the header block ***********************/ - if(headersize != 0) - { - /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ - if(headersize < 65280) - { - HBuffer[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF); - HBuffer[bufferidx++] = (uint8_t) ((headersize) & 0xFF); - headersize += 2; - } - else - { - /* header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - HBuffer[bufferidx++] = 0xFF; - HBuffer[bufferidx++] = 0xFE; - HBuffer[bufferidx++] = headersize & 0xff000000; - HBuffer[bufferidx++] = headersize & 0x00ff0000; - HBuffer[bufferidx++] = headersize & 0x0000ff00; - HBuffer[bufferidx++] = headersize & 0x000000ff; - headersize += 6; - } - /* Copy the header buffer in internal buffer "HBuffer" */ - for(loopcounter = 0; loopcounter < headersize; loopcounter++) - { - HBuffer[bufferidx++] = Header[loopcounter]; - } - /* Check if the header size is modulo 16 */ - if ((headersize % 16) != 0) - { - /* Padd the header buffer with 0s till the HBuffer length is modulo 16 */ - for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++) - { - HBuffer[loopcounter] = 0; - } - /* Set the header size to modulo 16 */ - headersize = ((headersize/16) + 1) * 16; - } - /* set the pointer headeraddr to HBuffer */ - headeraddr = (uint32_t)HBuffer; - } - /************************* Formatting the block B0 **************************/ - if(headersize != 0) - { - blockb0[0] = 0x40; - } - /* Flags byte */ - blockb0[0] |= 0u | (((( (uint8_t) TAGSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - NonceSize) - 1) & 0x07); - - for (loopcounter = 0; loopcounter < NonceSize; loopcounter++) - { - blockb0[loopcounter+1] = Nonce[loopcounter]; - } - for ( ; loopcounter < 13; loopcounter++) - { - blockb0[loopcounter+1] = 0; - } - - blockb0[14] = ((ILength >> 8) & 0xFF); - blockb0[15] = (ILength & 0xFF); - - /************************* Formatting the initial counter *******************/ - /* Byte 0: - Bits 7 and 6 are reserved and shall be set to 0 - Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks - are distinct from B0 - Bits 0, 1, and 2 contain the same encoding of q as in B0 - */ - ctr[0] = blockb0[0] & 0x07; - /* byte 1 to NonceSize is the IV (Nonce) */ - for(loopcounter = 1; loopcounter < NonceSize + 1; loopcounter++) - { - ctr[loopcounter] = blockb0[loopcounter]; - } - /* Set the LSB to 1 */ - ctr[15] |= 0x01; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); - - switch(Keysize) - { - case 128: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 192: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 256: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; - AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - default: - break; - } - - /* CRYP Initialization Vectors */ - AES_CRYP_IVInitStructure.CRYP_IV0Left = (__REV(*(uint32_t*)(ctraddr))); - ctraddr+=4; - AES_CRYP_IVInitStructure.CRYP_IV0Right= (__REV(*(uint32_t*)(ctraddr))); - ctraddr+=4; - AES_CRYP_IVInitStructure.CRYP_IV1Left = (__REV(*(uint32_t*)(ctraddr))); - ctraddr+=4; - AES_CRYP_IVInitStructure.CRYP_IV1Right= (__REV(*(uint32_t*)(ctraddr))); - - /*------------------ AES Encryption ------------------*/ - if(Mode == MODE_ENCRYPT) /* AES encryption */ - { - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Key Initialisation */ - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* CRYP Initialization Vectors */ - CRYP_IVInit(&AES_CRYP_IVInitStructure); - - /* Crypto Init for Key preparation for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&AES_CRYP_InitStructure); - - /***************************** Init phase *********************************/ - /* Select init phase */ - CRYP_PhaseConfig(CRYP_Phase_Init); - - b0addr = (uint32_t)blockb0; - /* Write the blockb0 block in the IN FIFO */ - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - /* Wait for CRYPEN bit to be 0 */ - while(CRYP_GetCmdStatus() == ENABLE) - { - } - /***************************** header phase *******************************/ - if(headersize != 0) - { - /* Select header phase */ - CRYP_PhaseConfig(CRYP_Phase_Header); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - } - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - } - - /**************************** payload phase *******************************/ - if(ILength != 0) - { - /* Select payload phase */ - CRYP_PhaseConfig(CRYP_Phase_Payload); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - else - { - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - } - } - } - - /***************************** final phase ********************************/ - /* Select final phase */ - CRYP_PhaseConfig(CRYP_Phase_Final); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - ctraddr = (uint32_t)ctr; - /* Write the counter block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */ - CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff); - - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - /* Read the Auth TAG in the IN FIFO */ - temptag[0] = CRYP_DataOut(); - temptag[1] = CRYP_DataOut(); - temptag[2] = CRYP_DataOut(); - temptag[3] = CRYP_DataOut(); - } - /*------------------ AES Decryption ------------------*/ - else /* AES decryption */ - { - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Key Initialisation */ - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* CRYP Initialization Vectors */ - CRYP_IVInit(&AES_CRYP_IVInitStructure); - - /* Crypto Init for Key preparation for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&AES_CRYP_InitStructure); - - /***************************** Init phase *********************************/ - /* Select init phase */ - CRYP_PhaseConfig(CRYP_Phase_Init); - - b0addr = (uint32_t)blockb0; - /* Write the blockb0 block in the IN FIFO */ - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - /* Wait for CRYPEN bit to be 0 */ - while(CRYP_GetCmdStatus() == ENABLE) - { - } - - /***************************** header phase *******************************/ - if(headersize != 0) - { - /* Select header phase */ - CRYP_PhaseConfig(CRYP_Phase_Header); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - } - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - } - - /**************************** payload phase *******************************/ - if(ILength != 0) - { - /* Select payload phase */ - CRYP_PhaseConfig(CRYP_Phase_Payload); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - else - { - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - } - } - } - - /***************************** final phase ********************************/ - /* Select final phase */ - CRYP_PhaseConfig(CRYP_Phase_Final); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - ctraddr = (uint32_t)ctr; - /* Write the counter block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */ - CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff); - - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - /* Read the Authentaication TAG (MAC) in the IN FIFO */ - temptag[0] = CRYP_DataOut(); - temptag[1] = CRYP_DataOut(); - temptag[2] = CRYP_DataOut(); - temptag[3] = CRYP_DataOut(); - } - - /* Copy temporary authentication TAG in user TAG buffer */ - for(loopcounter = 0; (loopcounter < TAGSize); loopcounter++) - { - /* Set the authentication TAG buffer */ - *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter); - } - - /* Disable Crypto */ - CRYP_Cmd(DISABLE); - - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f4xx_cryp_aes.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides high level functions to encrypt and decrypt an + * input message using AES in ECB/CBC/CTR/GCM/CCM modes. + * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP + * peripheral. + * AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices. + * For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available. + * +@verbatim + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) Enable The CRYP controller clock using + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. + + (#) Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() function. + + (#) Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() function. + + (#) Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() function. + + (#) Encrypt and decrypt using AES in GCM Mode using CRYP_AES_GCM() function. + + (#) Encrypt and decrypt using AES in CCM Mode using CRYP_AES_CCM() function. + +@endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_cryp.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group6 High Level AES functions + * @brief High Level AES functions + * +@verbatim + =============================================================================== + ##### High Level AES functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Encrypt and decrypt using AES in ECB Mode + * @param Mode: encryption or decryption Mode. + * This parameter can be one of the following values: + * @arg MODE_ENCRYPT: Encryption + * @arg MODE_DECRYPT: Decryption + * @param Key: Key used for AES algorithm. + * @param Keysize: length of the Key, must be a 128, 192 or 256. + * @param Input: pointer to the Input buffer. + * @param Ilength: length of the Input buffer, must be a multiple of 16. + * @param Output: pointer to the returned buffer. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Operation done + * - ERROR: Operation failed + */ +ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize, + uint8_t* Input, uint32_t Ilength, uint8_t* Output) +{ + CRYP_InitTypeDef AES_CRYP_InitStructure; + CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t keyaddr = (uint32_t)Key; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + uint32_t i = 0; + + /* Crypto structures initialisation*/ + CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); + + switch(Keysize) + { + case 128: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + case 192: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; + AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + case 256: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; + AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + default: + break; + } + + /*------------------ AES Decryption ------------------*/ + if(Mode == MODE_DECRYPT) /* AES decryption */ + { + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Crypto Init for Key preparation for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; + CRYP_Init(&AES_CRYP_InitStructure); + + /* Key Initialisation */ + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + /* wait until the Busy flag is RESET */ + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + else + { + /* Crypto Init for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + } + } + /*------------------ AES Encryption ------------------*/ + else /* AES encryption */ + { + + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* Crypto Init for Encryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + } + + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&AES_CRYP_InitStructure); + + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(i=0; ((i>32)); + CRYP_DataIn(__REV(headerlength)); + CRYP_DataIn(__REV(inputlength>>32)); + CRYP_DataIn(__REV(inputlength)); + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + tagaddr = (uint32_t)AuthTAG; + /* Read the Auth TAG in the IN FIFO */ + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + } + /*------------------ AES Decryption ------------------*/ + else /* AES decryption */ + { + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Key Initialisation */ + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* CRYP Initialization Vectors */ + CRYP_IVInit(&AES_CRYP_IVInitStructure); + + /* Crypto Init for Key preparation for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_GCM; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&AES_CRYP_InitStructure); + + /***************************** Init phase *********************************/ + /* Select init phase */ + CRYP_PhaseConfig(CRYP_Phase_Init); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + /* Wait for CRYPEN bit to be 0 */ + while(CRYP_GetCmdStatus() == ENABLE) + { + } + + /***************************** header phase *******************************/ + if(HLength != 0) + { + /* Select header phase */ + CRYP_PhaseConfig(CRYP_Phase_Header); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; (loopcounter < HLength); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + } + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + } + + /**************************** payload phase *******************************/ + if(ILength != 0) + { + /* Select payload phase */ + CRYP_PhaseConfig(CRYP_Phase_Payload); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + else + { + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + /* Read the Output block from the Output FIFO */ + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + } + } + } + + /***************************** final phase ********************************/ + /* Select final phase */ + CRYP_PhaseConfig(CRYP_Phase_Final); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + /* Write number of bits concatenated with header in the IN FIFO */ + CRYP_DataIn(__REV(headerlength>>32)); + CRYP_DataIn(__REV(headerlength)); + CRYP_DataIn(__REV(inputlength>>32)); + CRYP_DataIn(__REV(inputlength)); + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + tagaddr = (uint32_t)AuthTAG; + /* Read the Auth TAG in the IN FIFO */ + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + } + /* Disable Crypto */ + CRYP_Cmd(DISABLE); + + return status; +} + +/** + * @brief Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes + * are available only on STM32F437x Devices. + * @param Mode: encryption or decryption Mode. + * This parameter can be one of the following values: + * @arg MODE_ENCRYPT: Encryption + * @arg MODE_DECRYPT: Decryption + * @param Nonce: the nounce used for AES algorithm. It shall be unique for each processing. + * @param Key: Key used for AES algorithm. + * @param Keysize: length of the Key, must be a 128, 192 or 256. + * @param Input: pointer to the Input buffer. + * @param Ilength: length of the Input buffer in bytes, must be a multiple of 16. + * @param Header: pointer to the header buffer. + * @param Hlength: length of the header buffer in bytes. + * @param HBuffer: pointer to temporary buffer used to append the header + * HBuffer size must be equal to Hlength + 21 + * @param Output: pointer to the returned buffer. + * @param AuthTAG: pointer to the authentication TAG buffer. + * @param TAGSize: the size of the TAG (called also MAC). + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Operation done + * - ERROR: Operation failed + */ +ErrorStatus CRYP_AES_CCM(uint8_t Mode, + uint8_t* Nonce, uint32_t NonceSize, + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t ILength, + uint8_t *Header, uint32_t HLength, uint8_t *HBuffer, + uint8_t *Output, + uint8_t *AuthTAG, uint32_t TAGSize) +{ + CRYP_InitTypeDef AES_CRYP_InitStructure; + CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; + CRYP_IVInitTypeDef AES_CRYP_IVInitStructure; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t keyaddr = (uint32_t)Key; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + uint32_t headeraddr = (uint32_t)Header; + uint32_t tagaddr = (uint32_t)AuthTAG; + uint32_t headersize = HLength; + uint32_t loopcounter = 0; + uint32_t bufferidx = 0; + uint8_t blockb0[16] = {0};/* Block B0 */ + uint8_t ctr[16] = {0}; /* Counter */ + uint32_t temptag[4] = {0}; /* temporary TAG (MAC) */ + uint32_t ctraddr = (uint32_t)ctr; + uint32_t b0addr = (uint32_t)blockb0; + + /************************ Formatting the header block ***********************/ + if(headersize != 0) + { + /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ + if(headersize < 65280) + { + HBuffer[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF); + HBuffer[bufferidx++] = (uint8_t) ((headersize) & 0xFF); + headersize += 2; + } + else + { + /* header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ + HBuffer[bufferidx++] = 0xFF; + HBuffer[bufferidx++] = 0xFE; + HBuffer[bufferidx++] = headersize & 0xff000000; + HBuffer[bufferidx++] = headersize & 0x00ff0000; + HBuffer[bufferidx++] = headersize & 0x0000ff00; + HBuffer[bufferidx++] = headersize & 0x000000ff; + headersize += 6; + } + /* Copy the header buffer in internal buffer "HBuffer" */ + for(loopcounter = 0; loopcounter < headersize; loopcounter++) + { + HBuffer[bufferidx++] = Header[loopcounter]; + } + /* Check if the header size is modulo 16 */ + if ((headersize % 16) != 0) + { + /* Padd the header buffer with 0s till the HBuffer length is modulo 16 */ + for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++) + { + HBuffer[loopcounter] = 0; + } + /* Set the header size to modulo 16 */ + headersize = ((headersize/16) + 1) * 16; + } + /* set the pointer headeraddr to HBuffer */ + headeraddr = (uint32_t)HBuffer; + } + /************************* Formatting the block B0 **************************/ + if(headersize != 0) + { + blockb0[0] = 0x40; + } + /* Flags byte */ + blockb0[0] |= 0u | (((( (uint8_t) TAGSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - NonceSize) - 1) & 0x07); + + for (loopcounter = 0; loopcounter < NonceSize; loopcounter++) + { + blockb0[loopcounter+1] = Nonce[loopcounter]; + } + for ( ; loopcounter < 13; loopcounter++) + { + blockb0[loopcounter+1] = 0; + } + + blockb0[14] = ((ILength >> 8) & 0xFF); + blockb0[15] = (ILength & 0xFF); + + /************************* Formatting the initial counter *******************/ + /* Byte 0: + Bits 7 and 6 are reserved and shall be set to 0 + Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks + are distinct from B0 + Bits 0, 1, and 2 contain the same encoding of q as in B0 + */ + ctr[0] = blockb0[0] & 0x07; + /* byte 1 to NonceSize is the IV (Nonce) */ + for(loopcounter = 1; loopcounter < NonceSize + 1; loopcounter++) + { + ctr[loopcounter] = blockb0[loopcounter]; + } + /* Set the LSB to 1 */ + ctr[15] |= 0x01; + + /* Crypto structures initialisation*/ + CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); + + switch(Keysize) + { + case 128: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + case 192: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; + AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + case 256: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; + AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + default: + break; + } + + /* CRYP Initialization Vectors */ + AES_CRYP_IVInitStructure.CRYP_IV0Left = (__REV(*(uint32_t*)(ctraddr))); + ctraddr+=4; + AES_CRYP_IVInitStructure.CRYP_IV0Right= (__REV(*(uint32_t*)(ctraddr))); + ctraddr+=4; + AES_CRYP_IVInitStructure.CRYP_IV1Left = (__REV(*(uint32_t*)(ctraddr))); + ctraddr+=4; + AES_CRYP_IVInitStructure.CRYP_IV1Right= (__REV(*(uint32_t*)(ctraddr))); + + /*------------------ AES Encryption ------------------*/ + if(Mode == MODE_ENCRYPT) /* AES encryption */ + { + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Key Initialisation */ + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* CRYP Initialization Vectors */ + CRYP_IVInit(&AES_CRYP_IVInitStructure); + + /* Crypto Init for Key preparation for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&AES_CRYP_InitStructure); + + /***************************** Init phase *********************************/ + /* Select init phase */ + CRYP_PhaseConfig(CRYP_Phase_Init); + + b0addr = (uint32_t)blockb0; + /* Write the blockb0 block in the IN FIFO */ + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + /* Wait for CRYPEN bit to be 0 */ + while(CRYP_GetCmdStatus() == ENABLE) + { + } + /***************************** header phase *******************************/ + if(headersize != 0) + { + /* Select header phase */ + CRYP_PhaseConfig(CRYP_Phase_Header); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + } + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + } + + /**************************** payload phase *******************************/ + if(ILength != 0) + { + /* Select payload phase */ + CRYP_PhaseConfig(CRYP_Phase_Payload); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + else + { + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + /* Read the Output block from the Output FIFO */ + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + } + } + } + + /***************************** final phase ********************************/ + /* Select final phase */ + CRYP_PhaseConfig(CRYP_Phase_Final); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + ctraddr = (uint32_t)ctr; + /* Write the counter block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */ + CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff); + + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + /* Read the Auth TAG in the IN FIFO */ + temptag[0] = CRYP_DataOut(); + temptag[1] = CRYP_DataOut(); + temptag[2] = CRYP_DataOut(); + temptag[3] = CRYP_DataOut(); + } + /*------------------ AES Decryption ------------------*/ + else /* AES decryption */ + { + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Key Initialisation */ + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* CRYP Initialization Vectors */ + CRYP_IVInit(&AES_CRYP_IVInitStructure); + + /* Crypto Init for Key preparation for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&AES_CRYP_InitStructure); + + /***************************** Init phase *********************************/ + /* Select init phase */ + CRYP_PhaseConfig(CRYP_Phase_Init); + + b0addr = (uint32_t)blockb0; + /* Write the blockb0 block in the IN FIFO */ + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + /* Wait for CRYPEN bit to be 0 */ + while(CRYP_GetCmdStatus() == ENABLE) + { + } + + /***************************** header phase *******************************/ + if(headersize != 0) + { + /* Select header phase */ + CRYP_PhaseConfig(CRYP_Phase_Header); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + } + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + } + + /**************************** payload phase *******************************/ + if(ILength != 0) + { + /* Select payload phase */ + CRYP_PhaseConfig(CRYP_Phase_Payload); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + else + { + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + /* Read the Output block from the Output FIFO */ + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + } + } + } + + /***************************** final phase ********************************/ + /* Select final phase */ + CRYP_PhaseConfig(CRYP_Phase_Final); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + ctraddr = (uint32_t)ctr; + /* Write the counter block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */ + CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff); + + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + /* Read the Authentaication TAG (MAC) in the IN FIFO */ + temptag[0] = CRYP_DataOut(); + temptag[1] = CRYP_DataOut(); + temptag[2] = CRYP_DataOut(); + temptag[3] = CRYP_DataOut(); + } + + /* Copy temporary authentication TAG in user TAG buffer */ + for(loopcounter = 0; (loopcounter < TAGSize); loopcounter++) + { + /* Set the authentication TAG buffer */ + *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter); + } + + /* Disable Crypto */ + CRYP_Cmd(DISABLE); + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c index c73635aea..04d5e95a6 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c @@ -1,308 +1,308 @@ -/** - ****************************************************************************** - * @file stm32f4xx_cryp_des.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides high level functions to encrypt and decrypt an - * input message using DES in ECB/CBC modes. - * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP - * peripheral. - * -@verbatim - - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable The CRYP controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - - (#) Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB() function. - - (#) Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() function. - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" - - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group8 High Level DES functions - * @brief High Level DES functions - * -@verbatim - =============================================================================== - ##### High Level DES functions ##### - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using DES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for DES algorithm. - * @param Ilength: length of the Input buffer, must be a multiple of 8. - * @param Input: pointer to the Input buffer. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, - uint32_t Ilength, uint8_t *Output) -{ - CRYP_InitTypeDef DES_CRYP_InitStructure; - CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - if( Mode == MODE_ENCRYPT ) /* DES encryption */ - { - DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */ - { - DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - - DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB; - DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&DES_CRYP_InitStructure); - - /* Key Initialisation */ - DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - CRYP_KeyInit(& DES_CRYP_KeyInitStructure); - - /* Flush IN/OUT FIFO */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - for(i=0; ((i
© COPYRIGHT 2014 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_cryp.h" + + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group8 High Level DES functions + * @brief High Level DES functions + * +@verbatim + =============================================================================== + ##### High Level DES functions ##### + =============================================================================== +@endverbatim + * @{ + */ + +/** + * @brief Encrypt and decrypt using DES in ECB Mode + * @param Mode: encryption or decryption Mode. + * This parameter can be one of the following values: + * @arg MODE_ENCRYPT: Encryption + * @arg MODE_DECRYPT: Decryption + * @param Key: Key used for DES algorithm. + * @param Ilength: length of the Input buffer, must be a multiple of 8. + * @param Input: pointer to the Input buffer. + * @param Output: pointer to the returned buffer. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Operation done + * - ERROR: Operation failed + */ +ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, + uint32_t Ilength, uint8_t *Output) +{ + CRYP_InitTypeDef DES_CRYP_InitStructure; + CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t keyaddr = (uint32_t)Key; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + uint32_t i = 0; + + /* Crypto structures initialisation*/ + CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure); + + /* Crypto Init for Encryption process */ + if( Mode == MODE_ENCRYPT ) /* DES encryption */ + { + DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + } + else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */ + { + DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + } + + DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB; + DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&DES_CRYP_InitStructure); + + /* Key Initialisation */ + DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + CRYP_KeyInit(& DES_CRYP_KeyInitStructure); + + /* Flush IN/OUT FIFO */ + CRYP_FIFOFlush(); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + for(i=0; ((i
© COPYRIGHT 2014 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" - - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group7 High Level TDES functions - * @brief High Level TDES functions - * -@verbatim - =============================================================================== - ##### High Level TDES functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using TDES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for TDES algorithm. - * @param Ilength: length of the Input buffer, must be a multiple of 8. - * @param Input: pointer to the Input buffer. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, - uint32_t Ilength, uint8_t *Output) -{ - CRYP_InitTypeDef TDES_CRYP_InitStructure; - CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - if(Mode == MODE_ENCRYPT) /* TDES encryption */ - { - TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */ - { - TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - - TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; - TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&TDES_CRYP_InitStructure); - - /* Key Initialisation */ - TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - CRYP_KeyInit(& TDES_CRYP_KeyInitStructure); - - /* Flush IN/OUT FIFO */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embedd - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - for(i=0; ((i
© COPYRIGHT 2014 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_cryp.h" + + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group7 High Level TDES functions + * @brief High Level TDES functions + * +@verbatim + =============================================================================== + ##### High Level TDES functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Encrypt and decrypt using TDES in ECB Mode + * @param Mode: encryption or decryption Mode. + * This parameter can be one of the following values: + * @arg MODE_ENCRYPT: Encryption + * @arg MODE_DECRYPT: Decryption + * @param Key: Key used for TDES algorithm. + * @param Ilength: length of the Input buffer, must be a multiple of 8. + * @param Input: pointer to the Input buffer. + * @param Output: pointer to the returned buffer. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Operation done + * - ERROR: Operation failed + */ +ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, + uint32_t Ilength, uint8_t *Output) +{ + CRYP_InitTypeDef TDES_CRYP_InitStructure; + CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t keyaddr = (uint32_t)Key; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + uint32_t i = 0; + + /* Crypto structures initialisation*/ + CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure); + + /* Crypto Init for Encryption process */ + if(Mode == MODE_ENCRYPT) /* TDES encryption */ + { + TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + } + else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */ + { + TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + } + + TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; + TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&TDES_CRYP_InitStructure); + + /* Key Initialisation */ + TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + CRYP_KeyInit(& TDES_CRYP_KeyInitStructure); + + /* Flush IN/OUT FIFO */ + CRYP_FIFOFlush(); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + for(i=0; ((i
© COPYRIGHT 2014 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dac.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** @defgroup DAC_Group1 DAC channels configuration - * @brief DAC channels configuration: trigger, output buffer, data format - * -@verbatim - =============================================================================== - ##### DAC channels configuration: trigger, output buffer, data format ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified parameters - * in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains - * the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); - -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, - wave generation, mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ - DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @note When the DAC channel is enabled the trigger source can no more be modified. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel DAC. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup DAC_Group2 DMA management functions - * @brief DMA management functions - * -@verbatim - =============================================================================== - ##### DMA management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, - * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be - * already configured. - * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be - * already configured. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); - } -} -/** - * @} - */ - -/** @defgroup DAC_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} - -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's pending flags. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's interrupt pending bits. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_dac.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Digital-to-Analog Converter (DAC) peripheral: + * + DAC channels configuration: trigger, output buffer, data format + * + DMA management + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### DAC Peripheral features ##### + =============================================================================== + [..] + *** DAC Channels *** + ==================== + [..] + The device integrates two 12-bit Digital Analog Converters that can + be used independently or simultaneously (dual mode): + (#) DAC channel1 with DAC_OUT1 (PA4) as output + (#) DAC channel2 with DAC_OUT2 (PA5) as output + + *** DAC Triggers *** + ==================== + [..] + Digital to Analog conversion can be non-triggered using DAC_Trigger_None + and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register + using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions. + [..] + Digital to Analog conversion can be triggered by: + (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. + The used pin (GPIOx_Pin9) must be configured in input mode. + + (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 + (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...) + The timer TRGO event should be selected using TIM_SelectOutputTrigger() + + (#) Software using DAC_Trigger_Software + + *** DAC Buffer mode feature *** + =============================== + [..] + Each DAC channel integrates an output buffer that can be used to + reduce the output impedance, and to drive external loads directly + without having to add an external operational amplifier. + To enable, the output buffer use + DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + [..] + (@) Refer to the device datasheet for more details about output + impedance value with and without output buffer. + + *** DAC wave generation feature *** + =================================== + [..] + Both DAC channels can be used to generate + (#) Noise wave using DAC_WaveGeneration_Noise + (#) Triangle wave using DAC_WaveGeneration_Triangle + + -@- Wave generation can be disabled using DAC_WaveGeneration_None + + *** DAC data format *** + ======================= + [..] + The DAC data format can be: + (#) 8-bit right alignment using DAC_Align_8b_R + (#) 12-bit left alignment using DAC_Align_12b_L + (#) 12-bit right alignment using DAC_Align_12b_R + + *** DAC data value to voltage correspondence *** + ================================================ + [..] + The analog output voltage on each DAC channel pin is determined + by the following equation: + DAC_OUTx = VREF+ * DOR / 4095 + with DOR is the Data Output Register + VEF+ is the input voltage reference (refer to the device datasheet) + e.g. To set DAC_OUT1 to 0.7V, use + DAC_SetChannel1Data(DAC_Align_12b_R, 868); + Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + + *** DMA requests *** + ===================== + [..] + A DMA1 request can be generated when an external trigger (but not + a software trigger) occurs if DMA1 requests are enabled using + DAC_DMACmd() + [..] + DMA1 requests are mapped as following: + (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be + already configured + (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be + already configured + + + ##### How to use this driver ##### + =============================================================================== + [..] + (+) DAC APB clock must be enabled to get write access to DAC + registers using + RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) + (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. + (+) Configure the DAC channel using DAC_Init() function + (+) Enable the DAC channel using DAC_Cmd() function + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_dac.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* CR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** @defgroup DAC_Group1 DAC channels configuration + * @brief DAC channels configuration: trigger, output buffer, data format + * +@verbatim + =============================================================================== + ##### DAC channels configuration: trigger, output buffer, data format ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified parameters + * in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains + * the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); + +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, + wave generation, mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ + DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @note When the DAC channel is enabled the trigger source can no more be modified. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= (DAC_CR_EN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_SET; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignment for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel DAC. + * @param DAC_Align: Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} +/** + * @} + */ + +/** @defgroup DAC_Group2 DMA management functions + * @brief DMA management functions + * +@verbatim + =============================================================================== + ##### DMA management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, + * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be + * already configured. + * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be + * already configured. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); + } +} +/** + * @} + */ + +/** @defgroup DAC_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} + +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's pending flags. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's interrupt pending bits. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c index 91fe34c3d..4cc691f48 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c @@ -1,180 +1,180 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dbgmcu.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides all the DBGMCU firmware functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dbgmcu.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @brief Configures low power mode behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @param NewState: new state of the specified low power mode in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB1 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted - * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted - * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted - * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted - * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted. - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB1FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB1FZ &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB2 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted - * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted - * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted - * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted - * @param NewState: new state of the specified peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB2FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB2FZ &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_dbgmcu.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides all the DBGMCU firmware functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_dbgmcu.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); +} + +/** + * @brief Configures low power mode behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @param NewState: new state of the specified low power mode in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/** + * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB1 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted + * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted. + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB1FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB1FZ &= ~DBGMCU_Periph; + } +} + +/** + * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB2 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted + * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted + * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted + * @param NewState: new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB2FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB2FZ &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c index 0f23f3ce9..0993dd6ac 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c @@ -1,538 +1,538 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dcmi.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the DCMI peripheral: - * + Initialization and Configuration - * + Image capture functions - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The sequence below describes how to use this driver to capture image - from a camera module connected to the DCMI Interface. - This sequence does not take into account the configuration of the - camera module, which should be made before to configure and enable - the DCMI to capture images. - - (#) Enable the clock for the DCMI and associated GPIOs using the following - functions: - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) DCMI pins configuration - (++) Connect the involved DCMI pins to AF13 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); - (++) Configure these DCMI pins in alternate function mode by calling - the function GPIO_Init(); - - (#) Declare a DCMI_InitTypeDef structure, for example: - DCMI_InitTypeDef DCMI_InitStructure; - and fill the DCMI_InitStructure variable with the allowed values - of the structure member. - - (#) Initialize the DCMI interface by calling the function - DCMI_Init(&DCMI_InitStructure); - - (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR - register to the destination memory buffer. - - (#) Enable DCMI interface using the function - DCMI_Cmd(ENABLE); - - (#) Start the image capture using the function - DCMI_CaptureCmd(ENABLE); - - (#) At this stage the DCMI interface waits for the first start of frame, - then a DMA request is generated continuously/once (depending on the - mode used, Continuous/Snapshot) to transfer the received data into - the destination memory. - - -@- If you need to capture only a rectangular window from the received - image, you have to use the DCMI_CROPConfig() function to configure - the coordinates and size of the window to be captured, then enable - the Crop feature using DCMI_CROPCmd(ENABLE); - In this case, the Crop configuration should be made before to enable - and start the DCMI interface. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dcmi.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DCMI - * @brief DCMI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DCMI_Private_Functions - * @{ - */ - -/** @defgroup DCMI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DCMI registers to their default reset values. - * @param None - * @retval None - */ -void DCMI_DeInit(void) -{ - DCMI->CR = 0x0; - DCMI->IER = 0x0; - DCMI->ICR = 0x1F; - DCMI->ESCR = 0x0; - DCMI->ESUR = 0x0; - DCMI->CWSTRTR = 0x0; - DCMI->CWSIZER = 0x0; -} - -/** - * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. - * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains - * the configuration information for the DCMI. - * @retval None - */ -void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct) -{ - uint32_t temp = 0x0; - - /* Check the parameters */ - assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode)); - assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode)); - assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity)); - assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity)); - assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity)); - assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate)); - assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode)); - - /* The DCMI configuration registers should be programmed correctly before - enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */ - DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE); - - /* Reset the old DCMI configuration */ - temp = DCMI->CR; - - temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL | - DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | - DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); - - /* Sets the new configuration of the DCMI peripheral */ - temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode | - DCMI_InitStruct->DCMI_SynchroMode | - DCMI_InitStruct->DCMI_PCKPolarity | - DCMI_InitStruct->DCMI_VSPolarity | - DCMI_InitStruct->DCMI_HSPolarity | - DCMI_InitStruct->DCMI_CaptureRate | - DCMI_InitStruct->DCMI_ExtendedDataMode); - - DCMI->CR = temp; -} - -/** - * @brief Fills each DCMI_InitStruct member with its default value. - * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct) -{ - /* Set the default configuration */ - DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous; - DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware; - DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; - DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low; - DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low; - DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; - DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; -} - -/** - * @brief Initializes the DCMI peripheral CROP mode according to the specified - * parameters in the DCMI_CROPInitStruct. - * @note This function should be called before to enable and start the DCMI interface. - * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that - * contains the configuration information for the DCMI peripheral CROP mode. - * @retval None - */ -void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct) -{ - /* Sets the CROP window coordinates */ - DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount | - ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16)); - - /* Sets the CROP window size */ - DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount | - ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16)); -} - -/** - * @brief Enables or disables the DCMI Crop feature. - * @note This function should be called before to enable and start the DCMI interface. - * @param NewState: new state of the DCMI Crop feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_CROPCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI Crop feature */ - DCMI->CR |= (uint32_t)DCMI_CR_CROP; - } - else - { - /* Disable the DCMI Crop feature */ - DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; - } -} - -/** - * @brief Sets the embedded synchronization codes - * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that - * contains the embedded synchronization codes for the DCMI peripheral. - * @retval None - */ -void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct) -{ - DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode | - ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)| - ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)| - ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24)); -} - -/** - * @brief Enables or disables the DCMI JPEG format. - * @note The Crop and Embedded Synchronization features cannot be used in this mode. - * @param NewState: new state of the DCMI JPEG format. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_JPEGCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI JPEG format */ - DCMI->CR |= (uint32_t)DCMI_CR_JPEG; - } - else - { - /* Disable the DCMI JPEG format */ - DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG; - } -} -/** - * @} - */ - -/** @defgroup DCMI_Group2 Image capture functions - * @brief Image capture functions - * -@verbatim - =============================================================================== - ##### Image capture functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the DCMI interface. - * @param NewState: new state of the DCMI interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI by setting ENABLE bit */ - DCMI->CR |= (uint32_t)DCMI_CR_ENABLE; - } - else - { - /* Disable the DCMI by clearing ENABLE bit */ - DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE; - } -} - -/** - * @brief Enables or disables the DCMI Capture. - * @param NewState: new state of the DCMI capture. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_CaptureCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI Capture */ - DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE; - } - else - { - /* Disable the DCMI Capture */ - DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE; - } -} - -/** - * @brief Reads the data stored in the DR register. - * @param None - * @retval Data register value - */ -uint32_t DCMI_ReadData(void) -{ - return DCMI->DR; -} -/** - * @} - */ - -/** @defgroup DCMI_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the DCMI interface interrupts. - * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @param NewState: new state of the specified DCMI interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DCMI_CONFIG_IT(DCMI_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - DCMI->IER |= DCMI_IT; - } - else - { - /* Disable the Interrupt sources */ - DCMI->IER &= (uint16_t)(~DCMI_IT); - } -} - -/** - * @brief Checks whether the DCMI interface flag is set or not. - * @param DCMI_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask - * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask - * @arg DCMI_FLAG_LINERI: Line Raw flag mask - * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask - * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask - * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask - * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask - * @arg DCMI_FLAG_LINEMI: Line Masked flag mask - * @arg DCMI_FLAG_HSYNC: HSYNC flag mask - * @arg DCMI_FLAG_VSYNC: VSYNC flag mask - * @arg DCMI_FLAG_FNE: Fifo not empty flag mask - * @retval The new state of DCMI_FLAG (SET or RESET). - */ -FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t dcmireg, tempreg = 0; - - /* Check the parameters */ - assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG)); - - /* Get the DCMI register index */ - dcmireg = (((uint16_t)DCMI_FLAG) >> 12); - - if (dcmireg == 0x00) /* The FLAG is in RISR register */ - { - tempreg= DCMI->RISR; - } - else if (dcmireg == 0x02) /* The FLAG is in SR register */ - { - tempreg = DCMI->SR; - } - else /* The FLAG is in MISR register */ - { - tempreg = DCMI->MISR; - } - - if ((tempreg & DCMI_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the DCMI_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DCMI's pending flags. - * @param DCMI_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask - * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask - * @arg DCMI_FLAG_LINERI: Line Raw flag mask - * @retval None - */ -void DCMI_ClearFlag(uint16_t DCMI_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG)); - - /* Clear the flag by writing in the ICR register 1 in the corresponding - Flag position*/ - - DCMI->ICR = DCMI_FLAG; -} - -/** - * @brief Checks whether the DCMI interrupt has occurred or not. - * @param DCMI_IT: specifies the DCMI interrupt source to check. - * This parameter can be one of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval The new state of DCMI_IT (SET or RESET). - */ -ITStatus DCMI_GetITStatus(uint16_t DCMI_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itstatus = 0; - - /* Check the parameters */ - assert_param(IS_DCMI_GET_IT(DCMI_IT)); - - itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */ - - if ((itstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the DCMI's interrupt pending bits. - * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval None - */ -void DCMI_ClearITPendingBit(uint16_t DCMI_IT) -{ - /* Clear the interrupt pending Bit by writing in the ICR register 1 in the - corresponding pending Bit position*/ - - DCMI->ICR = DCMI_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_dcmi.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the DCMI peripheral: + * + Initialization and Configuration + * + Image capture functions + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The sequence below describes how to use this driver to capture image + from a camera module connected to the DCMI Interface. + This sequence does not take into account the configuration of the + camera module, which should be made before to configure and enable + the DCMI to capture images. + + (#) Enable the clock for the DCMI and associated GPIOs using the following + functions: + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) DCMI pins configuration + (++) Connect the involved DCMI pins to AF13 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); + (++) Configure these DCMI pins in alternate function mode by calling + the function GPIO_Init(); + + (#) Declare a DCMI_InitTypeDef structure, for example: + DCMI_InitTypeDef DCMI_InitStructure; + and fill the DCMI_InitStructure variable with the allowed values + of the structure member. + + (#) Initialize the DCMI interface by calling the function + DCMI_Init(&DCMI_InitStructure); + + (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR + register to the destination memory buffer. + + (#) Enable DCMI interface using the function + DCMI_Cmd(ENABLE); + + (#) Start the image capture using the function + DCMI_CaptureCmd(ENABLE); + + (#) At this stage the DCMI interface waits for the first start of frame, + then a DMA request is generated continuously/once (depending on the + mode used, Continuous/Snapshot) to transfer the received data into + the destination memory. + + -@- If you need to capture only a rectangular window from the received + image, you have to use the DCMI_CROPConfig() function to configure + the coordinates and size of the window to be captured, then enable + the Crop feature using DCMI_CROPCmd(ENABLE); + In this case, the Crop configuration should be made before to enable + and start the DCMI interface. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_dcmi.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DCMI + * @brief DCMI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DCMI_Private_Functions + * @{ + */ + +/** @defgroup DCMI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DCMI registers to their default reset values. + * @param None + * @retval None + */ +void DCMI_DeInit(void) +{ + DCMI->CR = 0x0; + DCMI->IER = 0x0; + DCMI->ICR = 0x1F; + DCMI->ESCR = 0x0; + DCMI->ESUR = 0x0; + DCMI->CWSTRTR = 0x0; + DCMI->CWSIZER = 0x0; +} + +/** + * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. + * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains + * the configuration information for the DCMI. + * @retval None + */ +void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct) +{ + uint32_t temp = 0x0; + + /* Check the parameters */ + assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode)); + assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode)); + assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity)); + assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity)); + assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity)); + assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate)); + assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode)); + + /* The DCMI configuration registers should be programmed correctly before + enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */ + DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE); + + /* Reset the old DCMI configuration */ + temp = DCMI->CR; + + temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL | + DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | + DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); + + /* Sets the new configuration of the DCMI peripheral */ + temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode | + DCMI_InitStruct->DCMI_SynchroMode | + DCMI_InitStruct->DCMI_PCKPolarity | + DCMI_InitStruct->DCMI_VSPolarity | + DCMI_InitStruct->DCMI_HSPolarity | + DCMI_InitStruct->DCMI_CaptureRate | + DCMI_InitStruct->DCMI_ExtendedDataMode); + + DCMI->CR = temp; +} + +/** + * @brief Fills each DCMI_InitStruct member with its default value. + * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct) +{ + /* Set the default configuration */ + DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous; + DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware; + DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; + DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low; + DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low; + DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; + DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; +} + +/** + * @brief Initializes the DCMI peripheral CROP mode according to the specified + * parameters in the DCMI_CROPInitStruct. + * @note This function should be called before to enable and start the DCMI interface. + * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that + * contains the configuration information for the DCMI peripheral CROP mode. + * @retval None + */ +void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct) +{ + /* Sets the CROP window coordinates */ + DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount | + ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16)); + + /* Sets the CROP window size */ + DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount | + ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16)); +} + +/** + * @brief Enables or disables the DCMI Crop feature. + * @note This function should be called before to enable and start the DCMI interface. + * @param NewState: new state of the DCMI Crop feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_CROPCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI Crop feature */ + DCMI->CR |= (uint32_t)DCMI_CR_CROP; + } + else + { + /* Disable the DCMI Crop feature */ + DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; + } +} + +/** + * @brief Sets the embedded synchronization codes + * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that + * contains the embedded synchronization codes for the DCMI peripheral. + * @retval None + */ +void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct) +{ + DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode | + ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)| + ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)| + ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24)); +} + +/** + * @brief Enables or disables the DCMI JPEG format. + * @note The Crop and Embedded Synchronization features cannot be used in this mode. + * @param NewState: new state of the DCMI JPEG format. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_JPEGCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI JPEG format */ + DCMI->CR |= (uint32_t)DCMI_CR_JPEG; + } + else + { + /* Disable the DCMI JPEG format */ + DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG; + } +} +/** + * @} + */ + +/** @defgroup DCMI_Group2 Image capture functions + * @brief Image capture functions + * +@verbatim + =============================================================================== + ##### Image capture functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the DCMI interface. + * @param NewState: new state of the DCMI interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI by setting ENABLE bit */ + DCMI->CR |= (uint32_t)DCMI_CR_ENABLE; + } + else + { + /* Disable the DCMI by clearing ENABLE bit */ + DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE; + } +} + +/** + * @brief Enables or disables the DCMI Capture. + * @param NewState: new state of the DCMI capture. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_CaptureCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI Capture */ + DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE; + } + else + { + /* Disable the DCMI Capture */ + DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE; + } +} + +/** + * @brief Reads the data stored in the DR register. + * @param None + * @retval Data register value + */ +uint32_t DCMI_ReadData(void) +{ + return DCMI->DR; +} +/** + * @} + */ + +/** @defgroup DCMI_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the DCMI interface interrupts. + * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVF: Overflow interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @param NewState: new state of the specified DCMI interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DCMI_CONFIG_IT(DCMI_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + DCMI->IER |= DCMI_IT; + } + else + { + /* Disable the Interrupt sources */ + DCMI->IER &= (uint16_t)(~DCMI_IT); + } +} + +/** + * @brief Checks whether the DCMI interface flag is set or not. + * @param DCMI_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask + * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask + * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask + * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask + * @arg DCMI_FLAG_LINERI: Line Raw flag mask + * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask + * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask + * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask + * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask + * @arg DCMI_FLAG_LINEMI: Line Masked flag mask + * @arg DCMI_FLAG_HSYNC: HSYNC flag mask + * @arg DCMI_FLAG_VSYNC: VSYNC flag mask + * @arg DCMI_FLAG_FNE: Fifo not empty flag mask + * @retval The new state of DCMI_FLAG (SET or RESET). + */ +FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t dcmireg, tempreg = 0; + + /* Check the parameters */ + assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG)); + + /* Get the DCMI register index */ + dcmireg = (((uint16_t)DCMI_FLAG) >> 12); + + if (dcmireg == 0x00) /* The FLAG is in RISR register */ + { + tempreg= DCMI->RISR; + } + else if (dcmireg == 0x02) /* The FLAG is in SR register */ + { + tempreg = DCMI->SR; + } + else /* The FLAG is in MISR register */ + { + tempreg = DCMI->MISR; + } + + if ((tempreg & DCMI_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the DCMI_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DCMI's pending flags. + * @param DCMI_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask + * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask + * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask + * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask + * @arg DCMI_FLAG_LINERI: Line Raw flag mask + * @retval None + */ +void DCMI_ClearFlag(uint16_t DCMI_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG)); + + /* Clear the flag by writing in the ICR register 1 in the corresponding + Flag position*/ + + DCMI->ICR = DCMI_FLAG; +} + +/** + * @brief Checks whether the DCMI interrupt has occurred or not. + * @param DCMI_IT: specifies the DCMI interrupt source to check. + * This parameter can be one of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVF: Overflow interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @retval The new state of DCMI_IT (SET or RESET). + */ +ITStatus DCMI_GetITStatus(uint16_t DCMI_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itstatus = 0; + + /* Check the parameters */ + assert_param(IS_DCMI_GET_IT(DCMI_IT)); + + itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */ + + if ((itstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the DCMI's interrupt pending bits. + * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVF: Overflow interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @retval None + */ +void DCMI_ClearITPendingBit(uint16_t DCMI_IT) +{ + /* Clear the interrupt pending Bit by writing in the ICR register 1 in the + corresponding pending Bit position*/ + + DCMI->ICR = DCMI_IT; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c index 7882a5245..046f7950e 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c @@ -1,1301 +1,1301 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access controller (DMA): - * + Initialization and Configuration - * + Data Counter - * + Double Buffer mode configuration and command - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) - function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) - function for DMA2. - - (#) Enable and configure the peripheral to be connected to the DMA Stream - (except for internal SRAM / FLASH memories: no initialization is - necessary). - - (#) For a given Stream, program the required configuration through following parameters: - Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination - data formats, Circular or Normal mode, Stream Priority level, Source and Destination - Incrementation mode, FIFO mode and its Threshold (if needed), Burst - mode for Source and/or Destination (if needed) using the DMA_Init() function. - To avoid filling unneccessary fields, you can call DMA_StructInit() function - to initialize a given structure with default values (reset values), the modify - only necessary fields - (ie. Source and Destination addresses, Transfer size and Data Formats). - - (#) Enable the NVIC and the corresponding interrupt(s) using the function - DMA_ITConfig() if you need to use DMA interrupts. - - (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring - the second Memory address and the first Memory to be used through the function - DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function - DMA_DoubleBufferModeCmd(). These operations must be done before step 6. - - (#) Enable the DMA stream using the DMA_Cmd() function. - - (#) Activate the needed Stream Request using PPP_DMACmd() function for - any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) - The function allowing this operation is provided in each PPP peripheral - driver (ie. SPI_DMACmd for SPI peripheral). - Once the Stream is enabled, it is not possible to modify its configuration - unless the stream is stopped and disabled. - After enabling the Stream, it is advised to monitor the EN bit status using - the function DMA_GetCmdStatus(). In case of configuration errors or bus errors - this bit will remain reset and all transfers on this Stream will remain on hold. - - (#) Optionally, you can configure the number of data to be transferred - when the Stream is disabled (ie. after each Transfer Complete event - or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). - And you can get the number of remaining data to be transferred using - the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is - enabled and running). - - (#) To control DMA events you can use one of the following two methods: - (##) Check on DMA Stream flags using the function DMA_GetFlagStatus(). - (##) Use DMA interrupts through the function DMA_ITConfig() at initialization - phase and DMA_GetITStatus() function into interrupt routines in - communication phase. - [..] - After checking on a flag you should clear it using DMA_ClearFlag() - function. And after checking on an interrupt event you should - clear it using DMA_ClearITPendingBit() function. - - (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify - the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that - the Memory Address to be modified is not the one currently in use by DMA Stream. - This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). - - (#) Optionally, Pause-Resume operations may be performed: - The DMA_Cmd() function may be used to perform Pause-Resume operation. - When a transfer is ongoing, calling this function to disable the - Stream will cause the transfer to be paused. All configuration registers - and the number of remaining data will be preserved. When calling again - this function to re-enable the Stream, the transfer will be resumed from - the point where it was paused. - - -@- Memory-to-Memory transfer is possible by setting the address of the memory into - the Peripheral registers. In this mode, Circular mode and Double Buffer mode - are not allowed. - - -@- The FIFO is used mainly to reduce bus usage and to allow data - packing/unpacking: it is possible to set different Data Sizes for - the Peripheral and the Memory (ie. you can set Half-Word data size - for the peripheral to access its data register and set Word data size - for the Memory to gain in access time. Each two Half-words will be - packed and written in a single access to a Word in the Memory). - - -@- When FIFO is disabled, it is not allowed to configure different - Data Sizes for Source and Destination. In this case the Peripheral - Data Size will be applied to both Source and Destination. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dma.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \ - DMA_SxCR_TEIE | DMA_SxCR_DMEIE) - -#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \ - DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \ - DMA_LISR_TCIF0) - -#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6) -#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16) -#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22) -#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000) -#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C -#define HIGH_ISR_MASK (uint32_t)0x20000000 -#define RESERVED_MASK (uint32_t)0x0F7D0F7D - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** @defgroup DMA_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to initialize the DMA Stream source - and destination addresses, incrementation and data sizes, transfer direction, - buffer size, circular/normal mode selection, memory-to-memory mode selection - and Stream priority value. - [..] - The DMA_Init() function follows the DMA configuration procedures as described in - reference manual (RM0090) except the first point: waiting on EN bit to be reset. - This condition should be checked by user application using the function DMA_GetCmdStatus() - before calling the DMA_Init() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the DMAy Streamx registers to their default reset values. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval None - */ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Disable the selected DMAy Streamx */ - DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN); - - /* Reset DMAy Streamx control register */ - DMAy_Streamx->CR = 0; - - /* Reset DMAy Streamx Number of Data to Transfer register */ - DMAy_Streamx->NDTR = 0; - - /* Reset DMAy Streamx peripheral address register */ - DMAy_Streamx->PAR = 0; - - /* Reset DMAy Streamx memory 0 address register */ - DMAy_Streamx->M0AR = 0; - - /* Reset DMAy Streamx memory 1 address register */ - DMAy_Streamx->M1AR = 0; - - /* Reset DMAy Streamx FIFO control register */ - DMAy_Streamx->FCR = (uint32_t)0x00000021; - - /* Reset interrupt pending bits for the selected stream */ - if (DMAy_Streamx == DMA1_Stream0) - { - /* Reset interrupt pending bits for DMA1 Stream0 */ - DMA1->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream1) - { - /* Reset interrupt pending bits for DMA1 Stream1 */ - DMA1->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream2) - { - /* Reset interrupt pending bits for DMA1 Stream2 */ - DMA1->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream3) - { - /* Reset interrupt pending bits for DMA1 Stream3 */ - DMA1->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream4) - { - /* Reset interrupt pending bits for DMA1 Stream4 */ - DMA1->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream5) - { - /* Reset interrupt pending bits for DMA1 Stream5 */ - DMA1->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream6) - { - /* Reset interrupt pending bits for DMA1 Stream6 */ - DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream7) - { - /* Reset interrupt pending bits for DMA1 Stream7 */ - DMA1->HIFCR = DMA_Stream7_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream0) - { - /* Reset interrupt pending bits for DMA2 Stream0 */ - DMA2->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream1) - { - /* Reset interrupt pending bits for DMA2 Stream1 */ - DMA2->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream2) - { - /* Reset interrupt pending bits for DMA2 Stream2 */ - DMA2->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream3) - { - /* Reset interrupt pending bits for DMA2 Stream3 */ - DMA2->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream4) - { - /* Reset interrupt pending bits for DMA2 Stream4 */ - DMA2->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream5) - { - /* Reset interrupt pending bits for DMA2 Stream5 */ - DMA2->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream6) - { - /* Reset interrupt pending bits for DMA2 Stream6 */ - DMA2->HIFCR = DMA_Stream6_IT_MASK; - } - else - { - if (DMAy_Streamx == DMA2_Stream7) - { - /* Reset interrupt pending bits for DMA2 Stream7 */ - DMA2->HIFCR = DMA_Stream7_IT_MASK; - } - } -} - -/** - * @brief Initializes the DMAy Streamx according to the specified parameters in - * the DMA_InitStruct structure. - * @note Before calling this function, it is recommended to check that the Stream - * is actually disabled using the function DMA_GetCmdStatus(). - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel)); - assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode)); - assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold)); - assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst)); - assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst)); - - /*------------------------- DMAy Streamx CR Configuration ------------------*/ - /* Get the DMAy_Streamx CR value */ - tmpreg = DMAy_Streamx->CR; - - /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ - DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ - DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ - DMA_SxCR_DIR)); - - /* Configure DMAy Streamx: */ - /* Set CHSEL bits according to DMA_CHSEL value */ - /* Set DIR bits according to DMA_DIR value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PL bits according to DMA_Priority value */ - /* Set MBURST bits according to DMA_MemoryBurst value */ - /* Set PBURST bits according to DMA_PeripheralBurst value */ - tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority | - DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst; - - /* Write to DMAy Streamx CR register */ - DMAy_Streamx->CR = tmpreg; - - /*------------------------- DMAy Streamx FCR Configuration -----------------*/ - /* Get the DMAy_Streamx FCR value */ - tmpreg = DMAy_Streamx->FCR; - - /* Clear DMDIS and FTH bits */ - tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); - - /* Configure DMAy Streamx FIFO: - Set DMDIS bits according to DMA_FIFOMode value - Set FTH bits according to DMA_FIFOThreshold value */ - tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold; - - /* Write to DMAy Streamx CR */ - DMAy_Streamx->FCR = tmpreg; - - /*------------------------- DMAy Streamx NDTR Configuration ----------------*/ - /* Write to DMAy Streamx NDTR register */ - DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize; - - /*------------------------- DMAy Streamx PAR Configuration -----------------*/ - /* Write to DMAy Streamx PAR */ - DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - - /*------------------------- DMAy Streamx M0AR Configuration ----------------*/ - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ - /*-------------- Reset DMA init structure parameters values ----------------*/ - /* Initialize the DMA_Channel member */ - DMA_InitStruct->DMA_Channel = 0; - - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - - /* Initialize the DMA_Memory0BaseAddr member */ - DMA_InitStruct->DMA_Memory0BaseAddr = 0; - - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - - /* Initialize the DMA_FIFOMode member */ - DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable; - - /* Initialize the DMA_FIFOThreshold member */ - DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; - - /* Initialize the DMA_MemoryBurst member */ - DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single; - - /* Initialize the DMA_PeripheralBurst member */ - DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single; -} - -/** - * @brief Enables or disables the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx. - * This parameter can be: ENABLE or DISABLE. - * - * @note This function may be used to perform Pause-Resume operation. When a - * transfer is ongoing, calling this function to disable the Stream will - * cause the transfer to be paused. All configuration registers and the - * number of remaining data will be preserved. When calling again this - * function to re-enable the Stream, the transfer will be resumed from - * the point where it was paused. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling the - * stream, it is recommended to check (or wait until) the DMA Stream is - * effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer of - * this single data is finished. - * - * @retval None - */ -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Streamx by setting EN bit */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN; - } - else - { - /* Disable the selected DMAy Streamx by clearing EN bit */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN; - } -} - -/** - * @brief Configures, when the PINC (Peripheral Increment address mode) bit is - * set, if the peripheral address should be incremented with the data - * size (configured with PSIZE bits) or by a fixed offset equal to 4 - * (32-bit aligned addresses). - * - * @note This function has no effect if the Peripheral Increment mode is disabled. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_Pincos: specifies the Peripheral increment offset size. - * This parameter can be one of the following values: - * @arg DMA_PINCOS_Psize: Peripheral address increment is done - * accordingly to PSIZE parameter. - * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is - * fixed to 4 (32-bit aligned addresses). - * @retval None - */ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos)); - - /* Check the needed Peripheral increment offset */ - if(DMA_Pincos != DMA_PINCOS_Psize) - { - /* Configure DMA_SxCR_PINCOS bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; - } - else - { - /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; - } -} - -/** - * @brief Configures, when the DMAy Streamx is disabled, the flow controller for - * the next transactions (Peripheral or Memory). - * - * @note Before enabling this feature, check if the used peripheral supports - * the Flow Controller mode or not. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FlowCtrl: specifies the DMA flow controller. - * This parameter can be one of the following values: - * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is - * the DMA controller. - * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller - * is the peripheral. - * @retval None - */ -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl)); - - /* Check the needed flow controller */ - if(DMA_FlowCtrl != DMA_FlowCtrl_Memory) - { - /* Configure DMA_SxCR_PFCTRL bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; - } - else - { - /* Clear the PFCTRL bit: Memory is the flow controller */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; - } -} -/** - * @} - */ - -/** @defgroup DMA_Group2 Data Counter functions - * @brief Data Counter functions - * -@verbatim - =============================================================================== - ##### Data Counter functions ##### - =============================================================================== - [..] - This subsection provides function allowing to configure and read the buffer size - (number of data to be transferred). - [..] - The DMA data counter can be written only when the DMA Stream is disabled - (ie. after transfer complete event). - [..] - The following function can be used to write the Stream data counter value: - (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); - -@- It is advised to use this function rather than DMA_Init() in situations - where only the Data buffer needs to be reloaded. - -@- If the Source and Destination Data Sizes are different, then the value - written in data counter, expressing the number of transfers, is relative - to the number of transfers from the Peripheral point of view. - ie. If Memory data size is Word, Peripheral data size is Half-Words, - then the value to be configured in the data counter is the number - of Half-Words to be transferred from/to the peripheral. - [..] - The DMA data counter can be read to indicate the number of remaining transfers for - the relative DMA Stream. This counter is decremented at the end of each data - transfer and when the transfer is complete: - (+) If Normal mode is selected: the counter is set to 0. - (+) If Circular mode is selected: the counter is reloaded with the initial value - (configured before enabling the DMA Stream) - [..] - The following function can be used to read the Stream data counter value: - (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -@endverbatim - * @{ - */ - -/** - * @brief Writes the number of data units to be transferred on the DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Counter: Number of data units to be transferred (from 0 to 65535) - * Number of data items depends only on the Peripheral data format. - * - * @note If Peripheral data format is Bytes: number of data units is equal - * to total number of bytes to be transferred. - * - * @note If Peripheral data format is Half-Word: number of data units is - * equal to total number of bytes to be transferred / 2. - * - * @note If Peripheral data format is Word: number of data units is equal - * to total number of bytes to be transferred / 4. - * - * @note In Memory-to-Memory transfer mode, the memory buffer pointed by - * DMAy_SxPAR register is considered as Peripheral. - * - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Write the number of data units to be transferred */ - DMAy_Streamx->NDTR = (uint16_t)Counter; -} - -/** - * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Return the number of remaining data units for DMAy Streamx */ - return ((uint16_t)(DMAy_Streamx->NDTR)); -} -/** - * @} - */ - -/** @defgroup DMA_Group3 Double Buffer mode functions - * @brief Double Buffer mode functions - * -@verbatim - =============================================================================== - ##### Double Buffer mode functions ##### - =============================================================================== - [..] - This subsection provides function allowing to configure and control the double - buffer mode parameters. - - [..] - The Double Buffer mode can be used only when Circular mode is enabled. - The Double Buffer mode cannot be used when transferring data from Memory to Memory. - - [..] - The Double Buffer mode allows to set two different Memory addresses from/to which - the DMA controller will access alternatively (after completing transfer to/from - target memory 0, it will start transfer to/from target memory 1). - This allows to reduce software overhead for double buffering and reduce the CPU - access time. - - [..] - Two functions must be called before calling the DMA_Init() function: - (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, - uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory); - (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - - [..] - DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address - and the first Memory target from/to which the transfer will start after - enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called - to enable the Double Buffer mode (or disable it when it should not be used). - - [..] - Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is - stopped) to modify on of the target Memories addresses or to check wich Memory target is currently - used: - (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, - uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget); - (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - - [..] - DMA_MemoryTargetConfig() can be called to modify the base address of one of - the two target Memories. - The Memory of which the base address will be modified must not be currently - be used by the DMA Stream (ie. if the DMA Stream is currently transferring - from Memory 1 then you can only modify base address of target Memory 0 and vice versa). - To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which - returns the index of the Memory target currently in use by the DMA Stream. - -@endverbatim - * @{ - */ - -/** - * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode - * and the current memory target. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) - * @param DMA_CurrentMemory: specifies which memory will be first buffer for - * the transactions when the Stream will be enabled. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: Memory 0 is the current buffer. - * @arg DMA_Memory_1: Memory 1 is the current buffer. - * - * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init(). - * - * @retval None - */ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory)); - - if (DMA_CurrentMemory != DMA_Memory_0) - { - /* Set Memory 1 as current memory address */ - DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); - } - else - { - /* Set Memory 0 as current memory address */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); - } - - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = Memory1BaseAddr; -} - -/** - * @brief Enables or disables the double buffer mode for the selected DMA stream. - * @note This function can be called only when the DMA Stream is disabled. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx double buffer mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Configure the Double Buffer mode */ - if (NewState != DISABLE) - { - /* Enable the Double buffer mode */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM; - } - else - { - /* Disable the Double buffer mode */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM; - } -} - -/** - * @brief Configures the Memory address for the next buffer transfer in double - * buffer mode (for dynamic use). This function can be called when the - * DMA Stream is enabled and when the transfer is ongoing. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param MemoryBaseAddr: The base address of the target memory buffer - * @param DMA_MemoryTarget: Next memory target to be used. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: To use the memory address 0 - * @arg DMA_Memory_1: To use the memory address 1 - * - * @note It is not allowed to modify the Base Address of a target Memory when - * this target is involved in the current transfer. ie. If the DMA Stream - * is currently transferring to/from Memory 1, then it not possible to - * modify Base address of Memory 1, but it is possible to modify Base - * address of Memory 0. - * To know which Memory is currently used, you can use the function - * DMA_GetCurrentMemoryTarget(). - * - * @retval None - */ -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget)); - - /* Check the Memory target to be configured */ - if (DMA_MemoryTarget != DMA_Memory_0) - { - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = MemoryBaseAddr; - } - else - { - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = MemoryBaseAddr; - } -} - -/** - * @brief Returns the current memory target used by double buffer transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The memory target number: 0 for Memory0 or 1 for Memory1. - */ -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the current memory target */ - if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0) - { - /* Current memory buffer used is Memory 1 */ - tmp = 1; - } - else - { - /* Current memory buffer used is Memory 0 */ - tmp = 0; - } - return tmp; -} -/** - * @} - */ - -/** @defgroup DMA_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA enable status - (+) Check the FIFO status - (+) Configure the DMA Interrupts sources and check or clear the flags or - pending bits status. - - [..] - (#) DMA Enable status: - After configuring the DMA Stream (DMA_Init() function) and enabling - the stream, it is recommended to check (or wait until) the DMA Stream - is effectively enabled. A Stream may remain disabled if a configuration - parameter is wrong. After disabling a DMA Stream, it is also recommended - to check (or wait until) the DMA Stream is effectively disabled. - If a Stream is disabled while a data transfer is ongoing, the current - data will be transferred and the Stream will be effectively disabled - only after this data transfer completion. - To monitor this state it is possible to use the following function: - (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - (#) FIFO Status: - It is possible to monitor the FIFO status when a transfer is ongoing - using the following function: - (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - (#) DMA Interrupts and Flags: - The user should identify which mode will be used in his application - to manage the DMA controller events: Polling mode or Interrupt mode. - - *** Polling Mode *** - ==================== - [..] - Each DMA stream can be managed through 4 event Flags: - (x : DMA Stream number ) - (#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. - (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. - (#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. - (#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. - (#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . - [..] - In this Mode it is advised to use the following functions: - (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - (+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - - *** Interrupt Mode *** - ====================== - [..] - Each DMA Stream can be managed through 4 Interrupts: - - *** Interrupt Source *** - ======================== - [..] - (#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. - (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. - (#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. - (#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. - (#) DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. - [..] - In this Mode it is advised to use the following functions: - (+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); - (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -@endverbatim - * @{ - */ - -/** - * @brief Returns the status of EN bit for the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling - * the stream, it is recommended to check (or wait until) the DMA Stream - * is effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer - * of this single data is finished. - * - * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). - */ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - FunctionalState state = DISABLE; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0) - { - /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */ - state = ENABLE; - } - else - { - /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - state = DISABLE; - } - return state; -} - -/** - * @brief Returns the current DMAy Streamx FIFO filled level. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The FIFO filling state. - * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full - * and not empty. - * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. - * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. - * - DMA_FIFOStatus_Empty: when FIFO is empty - * - DMA_FIFOStatus_Full: when FIFO is full - */ -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the FIFO level bits */ - tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS)); - - return tmpreg; -} - -/** - * @brief Checks whether the specified DMAy Streamx flag is set or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the flag is in HISR or LISR */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR; - } - - /* Mask the reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA flag */ - if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) - { - /* DMA_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMA_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMA_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's pending flags. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear flag bits */ - DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear flag bits */ - DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } -} - -/** - * @brief Enables or disables the specified DMAy Streamx interrupts. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @arg DMA_IT_FE: FIFO error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Check if the DMA_IT parameter contains a FIFO interrupt */ - if ((DMA_IT & DMA_IT_FE) != 0) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE; - } - else - { - /* Disable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; - } - } - - /* Check if the DMA_IT parameter contains a Transfer interrupt */ - if (DMA_IT != DMA_IT_FE) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA transfer interrupts */ - DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - else - { - /* Disable the selected DMA transfer interrupts */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - } -} - -/** - * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - ITStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the interrupt enable bit is in the CR or FCR register */ - if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET) - { - /* Get the interrupt enable position mask in CR register */ - tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); - - /* Check the enable bit in CR register */ - enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg); - } - else - { - /* Check the enable bit in FCR register */ - enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); - } - - /* Check if the interrupt pending flag is in LISR or HISR */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR ; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR ; - } - - /* mask all reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA interrupt */ - if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* DMA_IT is set */ - bitstatus = SET; - } - else - { - /* DMA_IT is reset */ - bitstatus = RESET; - } - - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's interrupt pending bits. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear interrupt bits */ - DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear interrupt bits */ - DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_dma.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access controller (DMA): + * + Initialization and Configuration + * + Data Counter + * + Double Buffer mode configuration and command + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) + function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) + function for DMA2. + + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM / FLASH memories: no initialization is + necessary). + + (#) For a given Stream, program the required configuration through following parameters: + Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination + data formats, Circular or Normal mode, Stream Priority level, Source and Destination + Incrementation mode, FIFO mode and its Threshold (if needed), Burst + mode for Source and/or Destination (if needed) using the DMA_Init() function. + To avoid filling unneccessary fields, you can call DMA_StructInit() function + to initialize a given structure with default values (reset values), the modify + only necessary fields + (ie. Source and Destination addresses, Transfer size and Data Formats). + + (#) Enable the NVIC and the corresponding interrupt(s) using the function + DMA_ITConfig() if you need to use DMA interrupts. + + (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring + the second Memory address and the first Memory to be used through the function + DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function + DMA_DoubleBufferModeCmd(). These operations must be done before step 6. + + (#) Enable the DMA stream using the DMA_Cmd() function. + + (#) Activate the needed Stream Request using PPP_DMACmd() function for + any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) + The function allowing this operation is provided in each PPP peripheral + driver (ie. SPI_DMACmd for SPI peripheral). + Once the Stream is enabled, it is not possible to modify its configuration + unless the stream is stopped and disabled. + After enabling the Stream, it is advised to monitor the EN bit status using + the function DMA_GetCmdStatus(). In case of configuration errors or bus errors + this bit will remain reset and all transfers on this Stream will remain on hold. + + (#) Optionally, you can configure the number of data to be transferred + when the Stream is disabled (ie. after each Transfer Complete event + or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). + And you can get the number of remaining data to be transferred using + the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is + enabled and running). + + (#) To control DMA events you can use one of the following two methods: + (##) Check on DMA Stream flags using the function DMA_GetFlagStatus(). + (##) Use DMA interrupts through the function DMA_ITConfig() at initialization + phase and DMA_GetITStatus() function into interrupt routines in + communication phase. + [..] + After checking on a flag you should clear it using DMA_ClearFlag() + function. And after checking on an interrupt event you should + clear it using DMA_ClearITPendingBit() function. + + (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify + the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that + the Memory Address to be modified is not the one currently in use by DMA Stream. + This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). + + (#) Optionally, Pause-Resume operations may be performed: + The DMA_Cmd() function may be used to perform Pause-Resume operation. + When a transfer is ongoing, calling this function to disable the + Stream will cause the transfer to be paused. All configuration registers + and the number of remaining data will be preserved. When calling again + this function to re-enable the Stream, the transfer will be resumed from + the point where it was paused. + + -@- Memory-to-Memory transfer is possible by setting the address of the memory into + the Peripheral registers. In this mode, Circular mode and Double Buffer mode + are not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data + packing/unpacking: it is possible to set different Data Sizes for + the Peripheral and the Memory (ie. you can set Half-Word data size + for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two Half-words will be + packed and written in a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different + Data Sizes for Source and Destination. In this case the Peripheral + Data Size will be applied to both Source and Destination. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_dma.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Masks Definition */ +#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \ + DMA_SxCR_TEIE | DMA_SxCR_DMEIE) + +#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \ + DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \ + DMA_LISR_TCIF0) + +#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6) +#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16) +#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22) +#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000) +#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000) +#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000) +#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000) +#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C +#define HIGH_ISR_MASK (uint32_t)0x20000000 +#define RESERVED_MASK (uint32_t)0x0F7D0F7D + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** @defgroup DMA_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to initialize the DMA Stream source + and destination addresses, incrementation and data sizes, transfer direction, + buffer size, circular/normal mode selection, memory-to-memory mode selection + and Stream priority value. + [..] + The DMA_Init() function follows the DMA configuration procedures as described in + reference manual (RM0090) except the first point: waiting on EN bit to be reset. + This condition should be checked by user application using the function DMA_GetCmdStatus() + before calling the DMA_Init() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the DMAy Streamx registers to their default reset values. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval None + */ +void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Disable the selected DMAy Streamx */ + DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN); + + /* Reset DMAy Streamx control register */ + DMAy_Streamx->CR = 0; + + /* Reset DMAy Streamx Number of Data to Transfer register */ + DMAy_Streamx->NDTR = 0; + + /* Reset DMAy Streamx peripheral address register */ + DMAy_Streamx->PAR = 0; + + /* Reset DMAy Streamx memory 0 address register */ + DMAy_Streamx->M0AR = 0; + + /* Reset DMAy Streamx memory 1 address register */ + DMAy_Streamx->M1AR = 0; + + /* Reset DMAy Streamx FIFO control register */ + DMAy_Streamx->FCR = (uint32_t)0x00000021; + + /* Reset interrupt pending bits for the selected stream */ + if (DMAy_Streamx == DMA1_Stream0) + { + /* Reset interrupt pending bits for DMA1 Stream0 */ + DMA1->LIFCR = DMA_Stream0_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream1) + { + /* Reset interrupt pending bits for DMA1 Stream1 */ + DMA1->LIFCR = DMA_Stream1_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream2) + { + /* Reset interrupt pending bits for DMA1 Stream2 */ + DMA1->LIFCR = DMA_Stream2_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream3) + { + /* Reset interrupt pending bits for DMA1 Stream3 */ + DMA1->LIFCR = DMA_Stream3_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream4) + { + /* Reset interrupt pending bits for DMA1 Stream4 */ + DMA1->HIFCR = DMA_Stream4_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream5) + { + /* Reset interrupt pending bits for DMA1 Stream5 */ + DMA1->HIFCR = DMA_Stream5_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream6) + { + /* Reset interrupt pending bits for DMA1 Stream6 */ + DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream7) + { + /* Reset interrupt pending bits for DMA1 Stream7 */ + DMA1->HIFCR = DMA_Stream7_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream0) + { + /* Reset interrupt pending bits for DMA2 Stream0 */ + DMA2->LIFCR = DMA_Stream0_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream1) + { + /* Reset interrupt pending bits for DMA2 Stream1 */ + DMA2->LIFCR = DMA_Stream1_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream2) + { + /* Reset interrupt pending bits for DMA2 Stream2 */ + DMA2->LIFCR = DMA_Stream2_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream3) + { + /* Reset interrupt pending bits for DMA2 Stream3 */ + DMA2->LIFCR = DMA_Stream3_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream4) + { + /* Reset interrupt pending bits for DMA2 Stream4 */ + DMA2->HIFCR = DMA_Stream4_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream5) + { + /* Reset interrupt pending bits for DMA2 Stream5 */ + DMA2->HIFCR = DMA_Stream5_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream6) + { + /* Reset interrupt pending bits for DMA2 Stream6 */ + DMA2->HIFCR = DMA_Stream6_IT_MASK; + } + else + { + if (DMAy_Streamx == DMA2_Stream7) + { + /* Reset interrupt pending bits for DMA2 Stream7 */ + DMA2->HIFCR = DMA_Stream7_IT_MASK; + } + } +} + +/** + * @brief Initializes the DMAy Streamx according to the specified parameters in + * the DMA_InitStruct structure. + * @note Before calling this function, it is recommended to check that the Stream + * is actually disabled using the function DMA_GetCmdStatus(). + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel)); + assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode)); + assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst)); + + /*------------------------- DMAy Streamx CR Configuration ------------------*/ + /* Get the DMAy_Streamx CR value */ + tmpreg = DMAy_Streamx->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR)); + + /* Configure DMAy Streamx: */ + /* Set CHSEL bits according to DMA_CHSEL value */ + /* Set DIR bits according to DMA_DIR value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PL bits according to DMA_Priority value */ + /* Set MBURST bits according to DMA_MemoryBurst value */ + /* Set PBURST bits according to DMA_PeripheralBurst value */ + tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority | + DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst; + + /* Write to DMAy Streamx CR register */ + DMAy_Streamx->CR = tmpreg; + + /*------------------------- DMAy Streamx FCR Configuration -----------------*/ + /* Get the DMAy_Streamx FCR value */ + tmpreg = DMAy_Streamx->FCR; + + /* Clear DMDIS and FTH bits */ + tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Configure DMAy Streamx FIFO: + Set DMDIS bits according to DMA_FIFOMode value + Set FTH bits according to DMA_FIFOThreshold value */ + tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold; + + /* Write to DMAy Streamx CR */ + DMAy_Streamx->FCR = tmpreg; + + /*------------------------- DMAy Streamx NDTR Configuration ----------------*/ + /* Write to DMAy Streamx NDTR register */ + DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize; + + /*------------------------- DMAy Streamx PAR Configuration -----------------*/ + /* Write to DMAy Streamx PAR */ + DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + + /*------------------------- DMAy Streamx M0AR Configuration ----------------*/ + /* Write to DMAy Streamx M0AR */ + DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ + /*-------------- Reset DMA init structure parameters values ----------------*/ + /* Initialize the DMA_Channel member */ + DMA_InitStruct->DMA_Channel = 0; + + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + + /* Initialize the DMA_Memory0BaseAddr member */ + DMA_InitStruct->DMA_Memory0BaseAddr = 0; + + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory; + + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + + /* Initialize the DMA_FIFOMode member */ + DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable; + + /* Initialize the DMA_FIFOThreshold member */ + DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; + + /* Initialize the DMA_MemoryBurst member */ + DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single; + + /* Initialize the DMA_PeripheralBurst member */ + DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single; +} + +/** + * @brief Enables or disables the specified DMAy Streamx. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param NewState: new state of the DMAy Streamx. + * This parameter can be: ENABLE or DISABLE. + * + * @note This function may be used to perform Pause-Resume operation. When a + * transfer is ongoing, calling this function to disable the Stream will + * cause the transfer to be paused. All configuration registers and the + * number of remaining data will be preserved. When calling again this + * function to re-enable the Stream, the transfer will be resumed from + * the point where it was paused. + * + * @note After configuring the DMA Stream (DMA_Init() function) and enabling the + * stream, it is recommended to check (or wait until) the DMA Stream is + * effectively enabled. A Stream may remain disabled if a configuration + * parameter is wrong. + * After disabling a DMA Stream, it is also recommended to check (or wait + * until) the DMA Stream is effectively disabled. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * + * @retval None + */ +void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Streamx by setting EN bit */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN; + } + else + { + /* Disable the selected DMAy Streamx by clearing EN bit */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN; + } +} + +/** + * @brief Configures, when the PINC (Peripheral Increment address mode) bit is + * set, if the peripheral address should be incremented with the data + * size (configured with PSIZE bits) or by a fixed offset equal to 4 + * (32-bit aligned addresses). + * + * @note This function has no effect if the Peripheral Increment mode is disabled. + * + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_Pincos: specifies the Peripheral increment offset size. + * This parameter can be one of the following values: + * @arg DMA_PINCOS_Psize: Peripheral address increment is done + * accordingly to PSIZE parameter. + * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is + * fixed to 4 (32-bit aligned addresses). + * @retval None + */ +void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos)); + + /* Check the needed Peripheral increment offset */ + if(DMA_Pincos != DMA_PINCOS_Psize) + { + /* Configure DMA_SxCR_PINCOS bit with the input parameter */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; + } + else + { + /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; + } +} + +/** + * @brief Configures, when the DMAy Streamx is disabled, the flow controller for + * the next transactions (Peripheral or Memory). + * + * @note Before enabling this feature, check if the used peripheral supports + * the Flow Controller mode or not. + * + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_FlowCtrl: specifies the DMA flow controller. + * This parameter can be one of the following values: + * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is + * the DMA controller. + * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller + * is the peripheral. + * @retval None + */ +void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl)); + + /* Check the needed flow controller */ + if(DMA_FlowCtrl != DMA_FlowCtrl_Memory) + { + /* Configure DMA_SxCR_PFCTRL bit with the input parameter */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; + } + else + { + /* Clear the PFCTRL bit: Memory is the flow controller */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; + } +} +/** + * @} + */ + +/** @defgroup DMA_Group2 Data Counter functions + * @brief Data Counter functions + * +@verbatim + =============================================================================== + ##### Data Counter functions ##### + =============================================================================== + [..] + This subsection provides function allowing to configure and read the buffer size + (number of data to be transferred). + [..] + The DMA data counter can be written only when the DMA Stream is disabled + (ie. after transfer complete event). + [..] + The following function can be used to write the Stream data counter value: + (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); + -@- It is advised to use this function rather than DMA_Init() in situations + where only the Data buffer needs to be reloaded. + -@- If the Source and Destination Data Sizes are different, then the value + written in data counter, expressing the number of transfers, is relative + to the number of transfers from the Peripheral point of view. + ie. If Memory data size is Word, Peripheral data size is Half-Words, + then the value to be configured in the data counter is the number + of Half-Words to be transferred from/to the peripheral. + [..] + The DMA data counter can be read to indicate the number of remaining transfers for + the relative DMA Stream. This counter is decremented at the end of each data + transfer and when the transfer is complete: + (+) If Normal mode is selected: the counter is set to 0. + (+) If Circular mode is selected: the counter is reloaded with the initial value + (configured before enabling the DMA Stream) + [..] + The following function can be used to read the Stream data counter value: + (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); + +@endverbatim + * @{ + */ + +/** + * @brief Writes the number of data units to be transferred on the DMAy Streamx. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param Counter: Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @note In Memory-to-Memory transfer mode, the memory buffer pointed by + * DMAy_SxPAR register is considered as Peripheral. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Write the number of data units to be transferred */ + DMAy_Streamx->NDTR = (uint16_t)Counter; +} + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Return the number of remaining data units for DMAy Streamx */ + return ((uint16_t)(DMAy_Streamx->NDTR)); +} +/** + * @} + */ + +/** @defgroup DMA_Group3 Double Buffer mode functions + * @brief Double Buffer mode functions + * +@verbatim + =============================================================================== + ##### Double Buffer mode functions ##### + =============================================================================== + [..] + This subsection provides function allowing to configure and control the double + buffer mode parameters. + + [..] + The Double Buffer mode can be used only when Circular mode is enabled. + The Double Buffer mode cannot be used when transferring data from Memory to Memory. + + [..] + The Double Buffer mode allows to set two different Memory addresses from/to which + the DMA controller will access alternatively (after completing transfer to/from + target memory 0, it will start transfer to/from target memory 1). + This allows to reduce software overhead for double buffering and reduce the CPU + access time. + + [..] + Two functions must be called before calling the DMA_Init() function: + (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, + uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory); + (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); + + [..] + DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address + and the first Memory target from/to which the transfer will start after + enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called + to enable the Double Buffer mode (or disable it when it should not be used). + + [..] + Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is + stopped) to modify on of the target Memories addresses or to check wich Memory target is currently + used: + (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, + uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget); + (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); + + [..] + DMA_MemoryTargetConfig() can be called to modify the base address of one of + the two target Memories. + The Memory of which the base address will be modified must not be currently + be used by the DMA Stream (ie. if the DMA Stream is currently transferring + from Memory 1 then you can only modify base address of target Memory 0 and vice versa). + To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which + returns the index of the Memory target currently in use by the DMA Stream. + +@endverbatim + * @{ + */ + +/** + * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode + * and the current memory target. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) + * @param DMA_CurrentMemory: specifies which memory will be first buffer for + * the transactions when the Stream will be enabled. + * This parameter can be one of the following values: + * @arg DMA_Memory_0: Memory 0 is the current buffer. + * @arg DMA_Memory_1: Memory 1 is the current buffer. + * + * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init(). + * + * @retval None + */ +void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, + uint32_t DMA_CurrentMemory) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory)); + + if (DMA_CurrentMemory != DMA_Memory_0) + { + /* Set Memory 1 as current memory address */ + DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); + } + else + { + /* Set Memory 0 as current memory address */ + DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); + } + + /* Write to DMAy Streamx M1AR */ + DMAy_Streamx->M1AR = Memory1BaseAddr; +} + +/** + * @brief Enables or disables the double buffer mode for the selected DMA stream. + * @note This function can be called only when the DMA Stream is disabled. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param NewState: new state of the DMAy Streamx double buffer mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Configure the Double Buffer mode */ + if (NewState != DISABLE) + { + /* Enable the Double buffer mode */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM; + } + else + { + /* Disable the Double buffer mode */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM; + } +} + +/** + * @brief Configures the Memory address for the next buffer transfer in double + * buffer mode (for dynamic use). This function can be called when the + * DMA Stream is enabled and when the transfer is ongoing. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param MemoryBaseAddr: The base address of the target memory buffer + * @param DMA_MemoryTarget: Next memory target to be used. + * This parameter can be one of the following values: + * @arg DMA_Memory_0: To use the memory address 0 + * @arg DMA_Memory_1: To use the memory address 1 + * + * @note It is not allowed to modify the Base Address of a target Memory when + * this target is involved in the current transfer. ie. If the DMA Stream + * is currently transferring to/from Memory 1, then it not possible to + * modify Base address of Memory 1, but it is possible to modify Base + * address of Memory 0. + * To know which Memory is currently used, you can use the function + * DMA_GetCurrentMemoryTarget(). + * + * @retval None + */ +void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, + uint32_t DMA_MemoryTarget) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget)); + + /* Check the Memory target to be configured */ + if (DMA_MemoryTarget != DMA_Memory_0) + { + /* Write to DMAy Streamx M1AR */ + DMAy_Streamx->M1AR = MemoryBaseAddr; + } + else + { + /* Write to DMAy Streamx M0AR */ + DMAy_Streamx->M0AR = MemoryBaseAddr; + } +} + +/** + * @brief Returns the current memory target used by double buffer transfer. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval The memory target number: 0 for Memory0 or 1 for Memory1. + */ +uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Get the current memory target */ + if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0) + { + /* Current memory buffer used is Memory 1 */ + tmp = 1; + } + else + { + /* Current memory buffer used is Memory 0 */ + tmp = 0; + } + return tmp; +} +/** + * @} + */ + +/** @defgroup DMA_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA enable status + (+) Check the FIFO status + (+) Configure the DMA Interrupts sources and check or clear the flags or + pending bits status. + + [..] + (#) DMA Enable status: + After configuring the DMA Stream (DMA_Init() function) and enabling + the stream, it is recommended to check (or wait until) the DMA Stream + is effectively enabled. A Stream may remain disabled if a configuration + parameter is wrong. After disabling a DMA Stream, it is also recommended + to check (or wait until) the DMA Stream is effectively disabled. + If a Stream is disabled while a data transfer is ongoing, the current + data will be transferred and the Stream will be effectively disabled + only after this data transfer completion. + To monitor this state it is possible to use the following function: + (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); + + (#) FIFO Status: + It is possible to monitor the FIFO status when a transfer is ongoing + using the following function: + (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); + + (#) DMA Interrupts and Flags: + The user should identify which mode will be used in his application + to manage the DMA controller events: Polling mode or Interrupt mode. + + *** Polling Mode *** + ==================== + [..] + Each DMA stream can be managed through 4 event Flags: + (x : DMA Stream number ) + (#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. + (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. + (#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. + (#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. + (#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . + [..] + In this Mode it is advised to use the following functions: + (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); + (+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); + + *** Interrupt Mode *** + ====================== + [..] + Each DMA Stream can be managed through 4 Interrupts: + + *** Interrupt Source *** + ======================== + [..] + (#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. + (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. + (#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. + (#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. + (#) DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. + [..] + In this Mode it is advised to use the following functions: + (+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); + (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); + (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); + +@endverbatim + * @{ + */ + +/** + * @brief Returns the status of EN bit for the specified DMAy Streamx. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * + * @note After configuring the DMA Stream (DMA_Init() function) and enabling + * the stream, it is recommended to check (or wait until) the DMA Stream + * is effectively enabled. A Stream may remain disabled if a configuration + * parameter is wrong. + * After disabling a DMA Stream, it is also recommended to check (or wait + * until) the DMA Stream is effectively disabled. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer + * of this single data is finished. + * + * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). + */ +FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx) +{ + FunctionalState state = DISABLE; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0) + { + /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */ + state = ENABLE; + } + else + { + /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + state = DISABLE; + } + return state; +} + +/** + * @brief Returns the current DMAy Streamx FIFO filled level. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Get the FIFO level bits */ + tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS)); + + return tmpreg; +} + +/** + * @brief Checks whether the specified DMAy Streamx flag is set or not. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag + * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag + * @arg DMA_FLAG_TEIFx: Streamx transfer error flag + * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag + * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag + * Where x can be 0 to 7 to select the DMA Stream. + * @retval The new state of DMA_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + DMA_TypeDef* DMAy; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if the flag is in HISR or LISR */ + if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Get DMAy HISR register value */ + tmpreg = DMAy->HISR; + } + else + { + /* Get DMAy LISR register value */ + tmpreg = DMAy->LISR; + } + + /* Mask the reserved bits */ + tmpreg &= (uint32_t)RESERVED_MASK; + + /* Check the status of the specified DMA flag */ + if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Streamx's pending flags. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag + * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag + * @arg DMA_FLAG_TEIFx: Streamx transfer error flag + * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag + * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag + * Where x can be 0 to 7 to select the DMA Stream. + * @retval None + */ +void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) +{ + DMA_TypeDef* DMAy; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if LIFCR or HIFCR register is targeted */ + if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Set DMAy HIFCR register clear flag bits */ + DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); + } + else + { + /* Set DMAy LIFCR register clear flag bits */ + DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); + } +} + +/** + * @brief Enables or disables the specified DMAy Streamx interrupts. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @arg DMA_IT_FE: FIFO error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Check if the DMA_IT parameter contains a FIFO interrupt */ + if ((DMA_IT & DMA_IT_FE) != 0) + { + if (NewState != DISABLE) + { + /* Enable the selected DMA FIFO interrupts */ + DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE; + } + else + { + /* Disable the selected DMA FIFO interrupts */ + DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; + } + } + + /* Check if the DMA_IT parameter contains a Transfer interrupt */ + if (DMA_IT != DMA_IT_FE) + { + if (NewState != DISABLE) + { + /* Enable the selected DMA transfer interrupts */ + DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); + } + else + { + /* Disable the selected DMA transfer interrupts */ + DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); + } + } +} + +/** + * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_IT: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt + * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt + * @arg DMA_IT_TEIFx: Streamx transfer error interrupt + * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt + * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt + * Where x can be 0 to 7 to select the DMA Stream. + * @retval The new state of DMA_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) +{ + ITStatus bitstatus = RESET; + DMA_TypeDef* DMAy; + uint32_t tmpreg = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if the interrupt enable bit is in the CR or FCR register */ + if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET) + { + /* Get the interrupt enable position mask in CR register */ + tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); + + /* Check the enable bit in CR register */ + enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg); + } + else + { + /* Check the enable bit in FCR register */ + enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); + } + + /* Check if the interrupt pending flag is in LISR or HISR */ + if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Get DMAy HISR register value */ + tmpreg = DMAy->HISR ; + } + else + { + /* Get DMAy LISR register value */ + tmpreg = DMAy->LISR ; + } + + /* mask all reserved bits */ + tmpreg &= (uint32_t)RESERVED_MASK; + + /* Check the status of the specified DMA interrupt */ + if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Streamx's interrupt pending bits. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_IT: specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt + * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt + * @arg DMA_IT_TEIFx: Streamx transfer error interrupt + * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt + * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt + * Where x can be 0 to 7 to select the DMA Stream. + * @retval None + */ +void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) +{ + DMA_TypeDef* DMAy; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if LIFCR or HIFCR register is targeted */ + if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Set DMAy HIFCR register clear interrupt bits */ + DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); + } + else + { + /* Set DMAy LIFCR register clear interrupt bits */ + DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c index 821c27e10..6869aab8f 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c @@ -1,784 +1,784 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma2d.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the DMA2D controller (DMA2D) peripheral: - * + Initialization and configuration - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable DMA2D clock using - RCC_APB2PeriphResetCmd(RCC_APB2Periph_DMA2D, ENABLE) function. - - (#) Configures DMA2D - (++) transfer mode - (++) pixel format, line_number, pixel_per_line - (++) output memory address - (++) alpha value - (++) output offset - (++) Default color (RGB) - - (#) Configures Foreground or/and background - (++) memory address - (++) alpha value - (++) offset and default color - - (#) Call the DMA2D_Start() to enable the DMA2D controller. - - @endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dma2d.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA2D - * @brief DMA2D driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -#define CR_MASK ((uint32_t)0xFFFCE0FC) /* DMA2D CR Mask */ -#define PFCCR_MASK ((uint32_t)0x00FC00C0) /* DMA2D FGPFCCR Mask */ -#define DEAD_MASK ((uint32_t)0xFFFF00FE) /* DMA2D DEAD Mask */ - -/** @defgroup DMA2D_Private_Functions - * @{ - */ - -/** @defgroup DMA2D_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DMA2D - (+) Start/Abort/Suspend Transfer - (+) Initialize, configure and set Foreground and background - (+) configure and enable DeadTime - (+) configure lineWatermark - - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DMA2D peripheral registers to their default reset - * values. - * @param None - * @retval None - */ - -void DMA2D_DeInit(void) -{ - /* Enable DMA2D reset state */ - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, ENABLE); - /* Release DMA2D from reset state */ - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, DISABLE); -} - - -/** - * @brief Initializes the DMA2D peripheral according to the specified parameters - * in the DMA2D_InitStruct. - * @note This function can be used only when the DMA2D is disabled. - * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure that contains - * the configuration information for the specified DMA2D peripheral. - * @retval None - */ -void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct) -{ - - uint32_t outgreen = 0; - uint32_t outred = 0; - uint32_t outalpha = 0; - uint32_t pixline = 0; - - /* Check the parameters */ - assert_param(IS_DMA2D_MODE(DMA2D_InitStruct->DMA2D_Mode)); - assert_param(IS_DMA2D_CMODE(DMA2D_InitStruct->DMA2D_CMode)); - assert_param(IS_DMA2D_OGREEN(DMA2D_InitStruct->DMA2D_OutputGreen)); - assert_param(IS_DMA2D_ORED(DMA2D_InitStruct->DMA2D_OutputRed)); - assert_param(IS_DMA2D_OBLUE(DMA2D_InitStruct->DMA2D_OutputBlue)); - assert_param(IS_DMA2D_OALPHA(DMA2D_InitStruct->DMA2D_OutputAlpha)); - assert_param(IS_DMA2D_OUTPUT_OFFSET(DMA2D_InitStruct->DMA2D_OutputOffset)); - assert_param(IS_DMA2D_LINE(DMA2D_InitStruct->DMA2D_NumberOfLine)); - assert_param(IS_DMA2D_PIXEL(DMA2D_InitStruct->DMA2D_PixelPerLine)); - - /* Configures the DMA2D operation mode */ - DMA2D->CR &= (uint32_t)CR_MASK; - DMA2D->CR |= (DMA2D_InitStruct->DMA2D_Mode); - - /* Configures the color mode of the output image */ - DMA2D->OPFCCR &= ~(uint32_t)DMA2D_OPFCCR_CM; - DMA2D->OPFCCR |= (DMA2D_InitStruct->DMA2D_CMode); - - /* Configures the output color */ - - if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB8888) - { - outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8; - outred = DMA2D_InitStruct->DMA2D_OutputRed << 16; - outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 24; - } - else - - if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB888) - { - outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8; - outred = DMA2D_InitStruct->DMA2D_OutputRed << 16; - outalpha = (uint32_t)0x00000000; - } - - else - - if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB565) - { - outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5; - outred = DMA2D_InitStruct->DMA2D_OutputRed << 11; - outalpha = (uint32_t)0x00000000; - } - - else - - if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB1555) - { - outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5; - outred = DMA2D_InitStruct->DMA2D_OutputRed << 10; - outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 15; - } - - else /* DMA2D_CMode = DMA2D_ARGB4444 */ - { - outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 4; - outred = DMA2D_InitStruct->DMA2D_OutputRed << 8; - outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 12; - } - DMA2D->OCOLR |= ((outgreen) | (outred) | (DMA2D_InitStruct->DMA2D_OutputBlue) | (outalpha)); - - /* Configures the output memory address */ - DMA2D->OMAR = (DMA2D_InitStruct->DMA2D_OutputMemoryAdd); - - /* Configure the line Offset */ - DMA2D->OOR &= ~(uint32_t)DMA2D_OOR_LO; - DMA2D->OOR |= (DMA2D_InitStruct->DMA2D_OutputOffset); - - /* Configure the number of line and pixel per line */ - pixline = DMA2D_InitStruct->DMA2D_PixelPerLine << 16; - DMA2D->NLR &= ~(DMA2D_NLR_NL | DMA2D_NLR_PL); - DMA2D->NLR |= ((DMA2D_InitStruct->DMA2D_NumberOfLine) | (pixline)); - -/** - * @brief Fills each DMA2D_InitStruct member with its default value. - * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure which will - * be initialized. - * @retval None - */ -} -void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct) -{ - /* Initialize the transfer mode member */ - DMA2D_InitStruct->DMA2D_Mode = DMA2D_M2M; - - /* Initialize the output color mode members */ - DMA2D_InitStruct->DMA2D_CMode = DMA2D_ARGB8888; - - /* Initialize the alpha and RGB values */ - DMA2D_InitStruct->DMA2D_OutputGreen = 0x00; - DMA2D_InitStruct->DMA2D_OutputBlue = 0x00; - DMA2D_InitStruct->DMA2D_OutputRed = 0x00; - DMA2D_InitStruct->DMA2D_OutputAlpha = 0x00; - - /* Initialize the output memory address */ - DMA2D_InitStruct->DMA2D_OutputMemoryAdd = 0x00; - - /* Initialize the output offset */ - DMA2D_InitStruct->DMA2D_OutputOffset = 0x00; - - /* Initialize the number of line and the number of pixel per line */ - DMA2D_InitStruct->DMA2D_NumberOfLine = 0x00; - DMA2D_InitStruct->DMA2D_PixelPerLine = 0x00; -} - -/** - * @brief Start the DMA2D transfer. - * @param - * @retval None - */ - -void DMA2D_StartTransfer(void) -{ - /* Start DMA2D transfer by setting START bit */ - DMA2D->CR |= (uint32_t)DMA2D_CR_START; -} - -/** - * @brief Aboart the DMA2D transfer. - * @param - * @retval None - */ - -void DMA2D_AbortTransfer(void) -{ - /* Start DMA2D transfer by setting START bit */ - DMA2D->CR |= (uint32_t)DMA2D_CR_ABORT; - -} - -/** - * @brief Stop or continue the DMA2D transfer. - * @param NewState: new state of the DMA2D peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA2D_Suspend(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Suspend DMA2D transfer by setting STOP bit */ - DMA2D->CR |= (uint32_t)DMA2D_CR_SUSP; - } - else - { - /* Continue DMA2D transfer by clearing STOP bit */ - DMA2D->CR &= ~(uint32_t)DMA2D_CR_SUSP; - } -} - -/** - * @brief Configures the Foreground according to the specified parameters - * in the DMA2D_FGStruct. - * @note This function can be used only when the transfer is disabled. - * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure that contains - * the configuration information for the specified Background. - * @retval None - */ -void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct) -{ - - uint32_t fg_clutcolormode = 0; - uint32_t fg_clutsize = 0; - uint32_t fg_alpha_mode = 0; - uint32_t fg_alphavalue = 0; - uint32_t fg_colorgreen = 0; - uint32_t fg_colorred = 0; - - assert_param(IS_DMA2D_FGO(DMA2D_FG_InitStruct->DMA2D_FGO)); - assert_param(IS_DMA2D_FGCM(DMA2D_FG_InitStruct->DMA2D_FGCM)); - assert_param(IS_DMA2D_FG_CLUT_CM(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM)); - assert_param(IS_DMA2D_FG_CLUT_SIZE(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE)); - assert_param(IS_DMA2D_FG_ALPHA_MODE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE)); - assert_param(IS_DMA2D_FG_ALPHA_VALUE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE)); - assert_param(IS_DMA2D_FGC_BLUE(DMA2D_FG_InitStruct->DMA2D_FGC_BLUE)); - assert_param(IS_DMA2D_FGC_GREEN(DMA2D_FG_InitStruct->DMA2D_FGC_GREEN)); - assert_param(IS_DMA2D_FGC_RED(DMA2D_FG_InitStruct->DMA2D_FGC_RED)); - - /* Configures the FG memory address */ - DMA2D->FGMAR = (DMA2D_FG_InitStruct->DMA2D_FGMA); - - /* Configures the FG offset */ - DMA2D->FGOR &= ~(uint32_t)DMA2D_FGOR_LO; - DMA2D->FGOR |= (DMA2D_FG_InitStruct->DMA2D_FGO); - - /* Configures foreground Pixel Format Convertor */ - DMA2D->FGPFCCR &= (uint32_t)PFCCR_MASK; - fg_clutcolormode = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM << 4; - fg_clutsize = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE << 8; - fg_alpha_mode = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE << 16; - fg_alphavalue = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE << 24; - DMA2D->FGPFCCR |= (DMA2D_FG_InitStruct->DMA2D_FGCM | fg_clutcolormode | fg_clutsize | \ - fg_alpha_mode | fg_alphavalue); - - /* Configures foreground color */ - DMA2D->FGCOLR &= ~(DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_RED); - fg_colorgreen = DMA2D_FG_InitStruct->DMA2D_FGC_GREEN << 8; - fg_colorred = DMA2D_FG_InitStruct->DMA2D_FGC_RED << 16; - DMA2D->FGCOLR |= (DMA2D_FG_InitStruct->DMA2D_FGC_BLUE | fg_colorgreen | fg_colorred); - - /* Configures foreground CLUT memory address */ - DMA2D->FGCMAR = DMA2D_FG_InitStruct->DMA2D_FGCMAR; -} - -/** - * @brief Fills each DMA2D_FGStruct member with its default value. - * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct) -{ - /*!< Initialize the DMA2D foreground memory address */ - DMA2D_FG_InitStruct->DMA2D_FGMA = 0x00; - - /*!< Initialize the DMA2D foreground offset */ - DMA2D_FG_InitStruct->DMA2D_FGO = 0x00; - - /*!< Initialize the DMA2D foreground color mode */ - DMA2D_FG_InitStruct->DMA2D_FGCM = CM_ARGB8888; - - /*!< Initialize the DMA2D foreground CLUT color mode */ - DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM = CLUT_CM_ARGB8888; - - /*!< Initialize the DMA2D foreground CLUT size */ - DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE = 0x00; - - /*!< Initialize the DMA2D foreground alpha mode */ - DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; - - /*!< Initialize the DMA2D foreground alpha value */ - DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE = 0x00; - - /*!< Initialize the DMA2D foreground blue value */ - DMA2D_FG_InitStruct->DMA2D_FGC_BLUE = 0x00; - - /*!< Initialize the DMA2D foreground green value */ - DMA2D_FG_InitStruct->DMA2D_FGC_GREEN = 0x00; - - /*!< Initialize the DMA2D foreground red value */ - DMA2D_FG_InitStruct->DMA2D_FGC_RED = 0x00; - - /*!< Initialize the DMA2D foreground CLUT memory address */ - DMA2D_FG_InitStruct->DMA2D_FGCMAR = 0x00; -} - - -/** - * @brief Configures the Background according to the specified parameters - * in the DMA2D_BGStruct. - * @note This function can be used only when the transfer is disabled. - * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure that contains - * the configuration information for the specified Background. - * @retval None - */ -void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct) -{ - - uint32_t bg_clutcolormode = 0; - uint32_t bg_clutsize = 0; - uint32_t bg_alpha_mode = 0; - uint32_t bg_alphavalue = 0; - uint32_t bg_colorgreen = 0; - uint32_t bg_colorred = 0; - - assert_param(IS_DMA2D_BGO(DMA2D_BG_InitStruct->DMA2D_BGO)); - assert_param(IS_DMA2D_BGCM(DMA2D_BG_InitStruct->DMA2D_BGCM)); - assert_param(IS_DMA2D_BG_CLUT_CM(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM)); - assert_param(IS_DMA2D_BG_CLUT_SIZE(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE)); - assert_param(IS_DMA2D_BG_ALPHA_MODE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE)); - assert_param(IS_DMA2D_BG_ALPHA_VALUE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE)); - assert_param(IS_DMA2D_BGC_BLUE(DMA2D_BG_InitStruct->DMA2D_BGC_BLUE)); - assert_param(IS_DMA2D_BGC_GREEN(DMA2D_BG_InitStruct->DMA2D_BGC_GREEN)); - assert_param(IS_DMA2D_BGC_RED(DMA2D_BG_InitStruct->DMA2D_BGC_RED)); - - /* Configures the BG memory address */ - DMA2D->BGMAR = (DMA2D_BG_InitStruct->DMA2D_BGMA); - - /* Configures the BG offset */ - DMA2D->BGOR &= ~(uint32_t)DMA2D_BGOR_LO; - DMA2D->BGOR |= (DMA2D_BG_InitStruct->DMA2D_BGO); - - /* Configures background Pixel Format Convertor */ - DMA2D->BGPFCCR &= (uint32_t)PFCCR_MASK; - bg_clutcolormode = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM << 4; - bg_clutsize = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE << 8; - bg_alpha_mode = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE << 16; - bg_alphavalue = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE << 24; - DMA2D->BGPFCCR |= (DMA2D_BG_InitStruct->DMA2D_BGCM | bg_clutcolormode | bg_clutsize | \ - bg_alpha_mode | bg_alphavalue); - - /* Configures background color */ - DMA2D->BGCOLR &= ~(DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_RED); - bg_colorgreen = DMA2D_BG_InitStruct->DMA2D_BGC_GREEN << 8; - bg_colorred = DMA2D_BG_InitStruct->DMA2D_BGC_RED << 16; - DMA2D->BGCOLR |= (DMA2D_BG_InitStruct->DMA2D_BGC_BLUE | bg_colorgreen | bg_colorred); - - /* Configures background CLUT memory address */ - DMA2D->BGCMAR = DMA2D_BG_InitStruct->DMA2D_BGCMAR; - -} - -/** - * @brief Fills each DMA2D_BGStruct member with its default value. - * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct) -{ - /*!< Initialize the DMA2D background memory address */ - DMA2D_BG_InitStruct->DMA2D_BGMA = 0x00; - - /*!< Initialize the DMA2D background offset */ - DMA2D_BG_InitStruct->DMA2D_BGO = 0x00; - - /*!< Initialize the DMA2D background color mode */ - DMA2D_BG_InitStruct->DMA2D_BGCM = CM_ARGB8888; - - /*!< Initialize the DMA2D background CLUT color mode */ - DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM = CLUT_CM_ARGB8888; - - /*!< Initialize the DMA2D background CLUT size */ - DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE = 0x00; - - /*!< Initialize the DMA2D background alpha mode */ - DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; - - /*!< Initialize the DMA2D background alpha value */ - DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE = 0x00; - - /*!< Initialize the DMA2D background blue value */ - DMA2D_BG_InitStruct->DMA2D_BGC_BLUE = 0x00; - - /*!< Initialize the DMA2D background green value */ - DMA2D_BG_InitStruct->DMA2D_BGC_GREEN = 0x00; - - /*!< Initialize the DMA2D background red value */ - DMA2D_BG_InitStruct->DMA2D_BGC_RED = 0x00; - - /*!< Initialize the DMA2D background CLUT memory address */ - DMA2D_BG_InitStruct->DMA2D_BGCMAR = 0x00; -} - -/** - * @brief Start the automatic loading of the CLUT or abort the transfer. - * @param NewState: new state of the DMA2D peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void DMA2D_FGStart(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Start the automatic loading of the CLUT */ - DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START; - } - else - { - /* abort the transfer */ - DMA2D->FGPFCCR &= (uint32_t)~DMA2D_FGPFCCR_START; - } -} - -/** - * @brief Start the automatic loading of the CLUT or abort the transfer. - * @param NewState: new state of the DMA2D peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void DMA2D_BGStart(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Start the automatic loading of the CLUT */ - DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START; - } - else - { - /* abort the transfer */ - DMA2D->BGPFCCR &= (uint32_t)~DMA2D_BGPFCCR_START; - } -} - -/** - * @brief Configures the DMA2D dead time. - * @param DMA2D_DeadTime: specifies the DMA2D dead time. - * This parameter can be one of the following values: - * @retval None - */ -void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState) -{ - uint32_t DeadTime; - - /* Check the parameters */ - assert_param(IS_DMA2D_DEAD_TIME(DMA2D_DeadTime)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable and Configures the dead time */ - DMA2D->AMTCR &= (uint32_t)DEAD_MASK; - DeadTime = DMA2D_DeadTime << 8; - DMA2D->AMTCR |= (DeadTime | DMA2D_AMTCR_EN); - } - else - { - DMA2D->AMTCR &= ~(uint32_t)DMA2D_AMTCR_EN; - } -} - -/** - * @brief Define the configuration of the line watermark . - * @param DMA2D_LWatermarkConfig: Line Watermark configuration. - * @retval None - */ - -void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LineWatermark(DMA2D_LWatermarkConfig)); - - /* Sets the Line watermark configuration */ - DMA2D->LWR = (uint32_t)DMA2D_LWatermarkConfig; -} - -/** - * @} - */ - -/** @defgroup DMA2D_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the DMA2D - Interrupts and to get the status and clear flags and Interrupts - pending bits. - [..] The DMA2D provides 6 Interrupts sources and 6 Flags - - *** Flags *** - ============= - [..] - (+) DMA2D_FLAG_CE : Configuration Error Interrupt flag - (+) DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag - (+) DMA2D_FLAG_TW: Transfer Watermark Interrupt flag - (+) DMA2D_FLAG_TC: Transfer Complete interrupt flag - (+) DMA2D_FLAG_TE: Transfer Error interrupt flag - (+) DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag - - *** Interrupts *** - ================== - [..] - (+) DMA2D_IT_CE: Configuration Error Interrupt is generated when a wrong - configuration is detected - (+) DMA2D_IT_CAE: CLUT Access Error Interrupt - (+) DMA2D_IT_TW: Transfer Watermark Interrupt is generated when - the programmed watermark is reached - (+) DMA2D_IT_TE: Transfer Error interrupt is generated when the CPU trying - to access the CLUT while a CLUT loading or a DMA2D1 transfer - is on going - (+) DMA2D_IT_CTC: CLUT Transfer Complete Interrupt - (+) DMA2D_IT_TC: Transfer Complete interrupt -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified DMA2D's interrupts. - * @param DMA2D_IT: specifies the DMA2D interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable. - * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable. - * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable. - * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable. - * @arg DMA2D_IT_TC: Transfer Complete interrupt enable. - * @arg DMA2D_IT_TE: Transfer Error interrupt enable. - * @param NewState: new state of the specified DMA2D interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_IT(DMA2D_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMA2D interrupts */ - DMA2D->CR |= DMA2D_IT; - } - else - { - /* Disable the selected DMA2D interrupts */ - DMA2D->CR &= (uint32_t)~DMA2D_IT; - } -} - -/** - * @brief Checks whether the specified DMA2D's flag is set or not. - * @param DMA2D_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag. - * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag. - * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag. - * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag. - * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag. - * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag. - * @retval The new state of DMA2D_FLAG (SET or RESET). - */ - -FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG)); - - /* Check the status of the specified DMA2D flag */ - if (((DMA2D->ISR) & DMA2D_FLAG) != (uint32_t)RESET) - { - /* DMA2D_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMA2D_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DMA2D_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMA2D's pending flags. - * @param DMA2D_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag. - * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag. - * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag. - * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag. - * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag. - * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag. - * @retval None - */ -void DMA2D_ClearFlag(uint32_t DMA2D_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG)); - - /* Clear the corresponding DMA2D flag */ - DMA2D->IFCR = (uint32_t)DMA2D_FLAG; -} - -/** - * @brief Checks whether the specified DMA2D's interrupt has occurred or not. - * @param DMA2D_IT: specifies the DMA2D interrupts sources to check. - * This parameter can be one of the following values: - * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable. - * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable. - * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable. - * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable. - * @arg DMA2D_IT_TC: Transfer Complete interrupt enable. - * @arg DMA2D_IT_TE: Transfer Error interrupt enable. - * @retval The new state of the DMA2D_IT (SET or RESET). - */ -ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT) -{ - ITStatus bitstatus = RESET; - uint32_t DMA2D_IT_FLAG = DMA2D_IT >> 8; - - /* Check the parameters */ - assert_param(IS_DMA2D_IT(DMA2D_IT)); - - if ((DMA2D->ISR & DMA2D_IT_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - if (((DMA2D->CR & DMA2D_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the DMA2D's interrupt pending bits. - * @param DMA2D_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DMA2D_IT_CE: Configuration Error Interrupt. - * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt. - * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt. - * @arg DMA2D_IT_TW: Transfer Watermark Interrupt. - * @arg DMA2D_IT_TC: Transfer Complete interrupt. - * @arg DMA2D_IT_TE: Transfer Error interrupt. - * @retval None - */ -void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_IT(DMA2D_IT)); - DMA2D_IT = DMA2D_IT >> 8; - - /* Clear the corresponding DMA2D Interrupt */ - DMA2D->IFCR = (uint32_t)DMA2D_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_dma2d.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the DMA2D controller (DMA2D) peripheral: + * + Initialization and configuration + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable DMA2D clock using + RCC_APB2PeriphResetCmd(RCC_APB2Periph_DMA2D, ENABLE) function. + + (#) Configures DMA2D + (++) transfer mode + (++) pixel format, line_number, pixel_per_line + (++) output memory address + (++) alpha value + (++) output offset + (++) Default color (RGB) + + (#) Configures Foreground or/and background + (++) memory address + (++) alpha value + (++) offset and default color + + (#) Call the DMA2D_Start() to enable the DMA2D controller. + + @endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_dma2d.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA2D + * @brief DMA2D driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +#define CR_MASK ((uint32_t)0xFFFCE0FC) /* DMA2D CR Mask */ +#define PFCCR_MASK ((uint32_t)0x00FC00C0) /* DMA2D FGPFCCR Mask */ +#define DEAD_MASK ((uint32_t)0xFFFF00FE) /* DMA2D DEAD Mask */ + +/** @defgroup DMA2D_Private_Functions + * @{ + */ + +/** @defgroup DMA2D_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DMA2D + (+) Start/Abort/Suspend Transfer + (+) Initialize, configure and set Foreground and background + (+) configure and enable DeadTime + (+) configure lineWatermark + + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DMA2D peripheral registers to their default reset + * values. + * @param None + * @retval None + */ + +void DMA2D_DeInit(void) +{ + /* Enable DMA2D reset state */ + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, ENABLE); + /* Release DMA2D from reset state */ + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, DISABLE); +} + + +/** + * @brief Initializes the DMA2D peripheral according to the specified parameters + * in the DMA2D_InitStruct. + * @note This function can be used only when the DMA2D is disabled. + * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure that contains + * the configuration information for the specified DMA2D peripheral. + * @retval None + */ +void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct) +{ + + uint32_t outgreen = 0; + uint32_t outred = 0; + uint32_t outalpha = 0; + uint32_t pixline = 0; + + /* Check the parameters */ + assert_param(IS_DMA2D_MODE(DMA2D_InitStruct->DMA2D_Mode)); + assert_param(IS_DMA2D_CMODE(DMA2D_InitStruct->DMA2D_CMode)); + assert_param(IS_DMA2D_OGREEN(DMA2D_InitStruct->DMA2D_OutputGreen)); + assert_param(IS_DMA2D_ORED(DMA2D_InitStruct->DMA2D_OutputRed)); + assert_param(IS_DMA2D_OBLUE(DMA2D_InitStruct->DMA2D_OutputBlue)); + assert_param(IS_DMA2D_OALPHA(DMA2D_InitStruct->DMA2D_OutputAlpha)); + assert_param(IS_DMA2D_OUTPUT_OFFSET(DMA2D_InitStruct->DMA2D_OutputOffset)); + assert_param(IS_DMA2D_LINE(DMA2D_InitStruct->DMA2D_NumberOfLine)); + assert_param(IS_DMA2D_PIXEL(DMA2D_InitStruct->DMA2D_PixelPerLine)); + + /* Configures the DMA2D operation mode */ + DMA2D->CR &= (uint32_t)CR_MASK; + DMA2D->CR |= (DMA2D_InitStruct->DMA2D_Mode); + + /* Configures the color mode of the output image */ + DMA2D->OPFCCR &= ~(uint32_t)DMA2D_OPFCCR_CM; + DMA2D->OPFCCR |= (DMA2D_InitStruct->DMA2D_CMode); + + /* Configures the output color */ + + if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB8888) + { + outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8; + outred = DMA2D_InitStruct->DMA2D_OutputRed << 16; + outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 24; + } + else + + if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB888) + { + outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8; + outred = DMA2D_InitStruct->DMA2D_OutputRed << 16; + outalpha = (uint32_t)0x00000000; + } + + else + + if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB565) + { + outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5; + outred = DMA2D_InitStruct->DMA2D_OutputRed << 11; + outalpha = (uint32_t)0x00000000; + } + + else + + if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB1555) + { + outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5; + outred = DMA2D_InitStruct->DMA2D_OutputRed << 10; + outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 15; + } + + else /* DMA2D_CMode = DMA2D_ARGB4444 */ + { + outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 4; + outred = DMA2D_InitStruct->DMA2D_OutputRed << 8; + outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 12; + } + DMA2D->OCOLR |= ((outgreen) | (outred) | (DMA2D_InitStruct->DMA2D_OutputBlue) | (outalpha)); + + /* Configures the output memory address */ + DMA2D->OMAR = (DMA2D_InitStruct->DMA2D_OutputMemoryAdd); + + /* Configure the line Offset */ + DMA2D->OOR &= ~(uint32_t)DMA2D_OOR_LO; + DMA2D->OOR |= (DMA2D_InitStruct->DMA2D_OutputOffset); + + /* Configure the number of line and pixel per line */ + pixline = DMA2D_InitStruct->DMA2D_PixelPerLine << 16; + DMA2D->NLR &= ~(DMA2D_NLR_NL | DMA2D_NLR_PL); + DMA2D->NLR |= ((DMA2D_InitStruct->DMA2D_NumberOfLine) | (pixline)); + +/** + * @brief Fills each DMA2D_InitStruct member with its default value. + * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure which will + * be initialized. + * @retval None + */ +} +void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct) +{ + /* Initialize the transfer mode member */ + DMA2D_InitStruct->DMA2D_Mode = DMA2D_M2M; + + /* Initialize the output color mode members */ + DMA2D_InitStruct->DMA2D_CMode = DMA2D_ARGB8888; + + /* Initialize the alpha and RGB values */ + DMA2D_InitStruct->DMA2D_OutputGreen = 0x00; + DMA2D_InitStruct->DMA2D_OutputBlue = 0x00; + DMA2D_InitStruct->DMA2D_OutputRed = 0x00; + DMA2D_InitStruct->DMA2D_OutputAlpha = 0x00; + + /* Initialize the output memory address */ + DMA2D_InitStruct->DMA2D_OutputMemoryAdd = 0x00; + + /* Initialize the output offset */ + DMA2D_InitStruct->DMA2D_OutputOffset = 0x00; + + /* Initialize the number of line and the number of pixel per line */ + DMA2D_InitStruct->DMA2D_NumberOfLine = 0x00; + DMA2D_InitStruct->DMA2D_PixelPerLine = 0x00; +} + +/** + * @brief Start the DMA2D transfer. + * @param + * @retval None + */ + +void DMA2D_StartTransfer(void) +{ + /* Start DMA2D transfer by setting START bit */ + DMA2D->CR |= (uint32_t)DMA2D_CR_START; +} + +/** + * @brief Aboart the DMA2D transfer. + * @param + * @retval None + */ + +void DMA2D_AbortTransfer(void) +{ + /* Start DMA2D transfer by setting START bit */ + DMA2D->CR |= (uint32_t)DMA2D_CR_ABORT; + +} + +/** + * @brief Stop or continue the DMA2D transfer. + * @param NewState: new state of the DMA2D peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA2D_Suspend(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Suspend DMA2D transfer by setting STOP bit */ + DMA2D->CR |= (uint32_t)DMA2D_CR_SUSP; + } + else + { + /* Continue DMA2D transfer by clearing STOP bit */ + DMA2D->CR &= ~(uint32_t)DMA2D_CR_SUSP; + } +} + +/** + * @brief Configures the Foreground according to the specified parameters + * in the DMA2D_FGStruct. + * @note This function can be used only when the transfer is disabled. + * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure that contains + * the configuration information for the specified Background. + * @retval None + */ +void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct) +{ + + uint32_t fg_clutcolormode = 0; + uint32_t fg_clutsize = 0; + uint32_t fg_alpha_mode = 0; + uint32_t fg_alphavalue = 0; + uint32_t fg_colorgreen = 0; + uint32_t fg_colorred = 0; + + assert_param(IS_DMA2D_FGO(DMA2D_FG_InitStruct->DMA2D_FGO)); + assert_param(IS_DMA2D_FGCM(DMA2D_FG_InitStruct->DMA2D_FGCM)); + assert_param(IS_DMA2D_FG_CLUT_CM(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM)); + assert_param(IS_DMA2D_FG_CLUT_SIZE(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE)); + assert_param(IS_DMA2D_FG_ALPHA_MODE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE)); + assert_param(IS_DMA2D_FG_ALPHA_VALUE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE)); + assert_param(IS_DMA2D_FGC_BLUE(DMA2D_FG_InitStruct->DMA2D_FGC_BLUE)); + assert_param(IS_DMA2D_FGC_GREEN(DMA2D_FG_InitStruct->DMA2D_FGC_GREEN)); + assert_param(IS_DMA2D_FGC_RED(DMA2D_FG_InitStruct->DMA2D_FGC_RED)); + + /* Configures the FG memory address */ + DMA2D->FGMAR = (DMA2D_FG_InitStruct->DMA2D_FGMA); + + /* Configures the FG offset */ + DMA2D->FGOR &= ~(uint32_t)DMA2D_FGOR_LO; + DMA2D->FGOR |= (DMA2D_FG_InitStruct->DMA2D_FGO); + + /* Configures foreground Pixel Format Convertor */ + DMA2D->FGPFCCR &= (uint32_t)PFCCR_MASK; + fg_clutcolormode = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM << 4; + fg_clutsize = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE << 8; + fg_alpha_mode = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE << 16; + fg_alphavalue = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE << 24; + DMA2D->FGPFCCR |= (DMA2D_FG_InitStruct->DMA2D_FGCM | fg_clutcolormode | fg_clutsize | \ + fg_alpha_mode | fg_alphavalue); + + /* Configures foreground color */ + DMA2D->FGCOLR &= ~(DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_RED); + fg_colorgreen = DMA2D_FG_InitStruct->DMA2D_FGC_GREEN << 8; + fg_colorred = DMA2D_FG_InitStruct->DMA2D_FGC_RED << 16; + DMA2D->FGCOLR |= (DMA2D_FG_InitStruct->DMA2D_FGC_BLUE | fg_colorgreen | fg_colorred); + + /* Configures foreground CLUT memory address */ + DMA2D->FGCMAR = DMA2D_FG_InitStruct->DMA2D_FGCMAR; +} + +/** + * @brief Fills each DMA2D_FGStruct member with its default value. + * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct) +{ + /*!< Initialize the DMA2D foreground memory address */ + DMA2D_FG_InitStruct->DMA2D_FGMA = 0x00; + + /*!< Initialize the DMA2D foreground offset */ + DMA2D_FG_InitStruct->DMA2D_FGO = 0x00; + + /*!< Initialize the DMA2D foreground color mode */ + DMA2D_FG_InitStruct->DMA2D_FGCM = CM_ARGB8888; + + /*!< Initialize the DMA2D foreground CLUT color mode */ + DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM = CLUT_CM_ARGB8888; + + /*!< Initialize the DMA2D foreground CLUT size */ + DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE = 0x00; + + /*!< Initialize the DMA2D foreground alpha mode */ + DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; + + /*!< Initialize the DMA2D foreground alpha value */ + DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE = 0x00; + + /*!< Initialize the DMA2D foreground blue value */ + DMA2D_FG_InitStruct->DMA2D_FGC_BLUE = 0x00; + + /*!< Initialize the DMA2D foreground green value */ + DMA2D_FG_InitStruct->DMA2D_FGC_GREEN = 0x00; + + /*!< Initialize the DMA2D foreground red value */ + DMA2D_FG_InitStruct->DMA2D_FGC_RED = 0x00; + + /*!< Initialize the DMA2D foreground CLUT memory address */ + DMA2D_FG_InitStruct->DMA2D_FGCMAR = 0x00; +} + + +/** + * @brief Configures the Background according to the specified parameters + * in the DMA2D_BGStruct. + * @note This function can be used only when the transfer is disabled. + * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure that contains + * the configuration information for the specified Background. + * @retval None + */ +void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct) +{ + + uint32_t bg_clutcolormode = 0; + uint32_t bg_clutsize = 0; + uint32_t bg_alpha_mode = 0; + uint32_t bg_alphavalue = 0; + uint32_t bg_colorgreen = 0; + uint32_t bg_colorred = 0; + + assert_param(IS_DMA2D_BGO(DMA2D_BG_InitStruct->DMA2D_BGO)); + assert_param(IS_DMA2D_BGCM(DMA2D_BG_InitStruct->DMA2D_BGCM)); + assert_param(IS_DMA2D_BG_CLUT_CM(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM)); + assert_param(IS_DMA2D_BG_CLUT_SIZE(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE)); + assert_param(IS_DMA2D_BG_ALPHA_MODE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE)); + assert_param(IS_DMA2D_BG_ALPHA_VALUE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE)); + assert_param(IS_DMA2D_BGC_BLUE(DMA2D_BG_InitStruct->DMA2D_BGC_BLUE)); + assert_param(IS_DMA2D_BGC_GREEN(DMA2D_BG_InitStruct->DMA2D_BGC_GREEN)); + assert_param(IS_DMA2D_BGC_RED(DMA2D_BG_InitStruct->DMA2D_BGC_RED)); + + /* Configures the BG memory address */ + DMA2D->BGMAR = (DMA2D_BG_InitStruct->DMA2D_BGMA); + + /* Configures the BG offset */ + DMA2D->BGOR &= ~(uint32_t)DMA2D_BGOR_LO; + DMA2D->BGOR |= (DMA2D_BG_InitStruct->DMA2D_BGO); + + /* Configures background Pixel Format Convertor */ + DMA2D->BGPFCCR &= (uint32_t)PFCCR_MASK; + bg_clutcolormode = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM << 4; + bg_clutsize = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE << 8; + bg_alpha_mode = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE << 16; + bg_alphavalue = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE << 24; + DMA2D->BGPFCCR |= (DMA2D_BG_InitStruct->DMA2D_BGCM | bg_clutcolormode | bg_clutsize | \ + bg_alpha_mode | bg_alphavalue); + + /* Configures background color */ + DMA2D->BGCOLR &= ~(DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_RED); + bg_colorgreen = DMA2D_BG_InitStruct->DMA2D_BGC_GREEN << 8; + bg_colorred = DMA2D_BG_InitStruct->DMA2D_BGC_RED << 16; + DMA2D->BGCOLR |= (DMA2D_BG_InitStruct->DMA2D_BGC_BLUE | bg_colorgreen | bg_colorred); + + /* Configures background CLUT memory address */ + DMA2D->BGCMAR = DMA2D_BG_InitStruct->DMA2D_BGCMAR; + +} + +/** + * @brief Fills each DMA2D_BGStruct member with its default value. + * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct) +{ + /*!< Initialize the DMA2D background memory address */ + DMA2D_BG_InitStruct->DMA2D_BGMA = 0x00; + + /*!< Initialize the DMA2D background offset */ + DMA2D_BG_InitStruct->DMA2D_BGO = 0x00; + + /*!< Initialize the DMA2D background color mode */ + DMA2D_BG_InitStruct->DMA2D_BGCM = CM_ARGB8888; + + /*!< Initialize the DMA2D background CLUT color mode */ + DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM = CLUT_CM_ARGB8888; + + /*!< Initialize the DMA2D background CLUT size */ + DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE = 0x00; + + /*!< Initialize the DMA2D background alpha mode */ + DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; + + /*!< Initialize the DMA2D background alpha value */ + DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE = 0x00; + + /*!< Initialize the DMA2D background blue value */ + DMA2D_BG_InitStruct->DMA2D_BGC_BLUE = 0x00; + + /*!< Initialize the DMA2D background green value */ + DMA2D_BG_InitStruct->DMA2D_BGC_GREEN = 0x00; + + /*!< Initialize the DMA2D background red value */ + DMA2D_BG_InitStruct->DMA2D_BGC_RED = 0x00; + + /*!< Initialize the DMA2D background CLUT memory address */ + DMA2D_BG_InitStruct->DMA2D_BGCMAR = 0x00; +} + +/** + * @brief Start the automatic loading of the CLUT or abort the transfer. + * @param NewState: new state of the DMA2D peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void DMA2D_FGStart(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Start the automatic loading of the CLUT */ + DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START; + } + else + { + /* abort the transfer */ + DMA2D->FGPFCCR &= (uint32_t)~DMA2D_FGPFCCR_START; + } +} + +/** + * @brief Start the automatic loading of the CLUT or abort the transfer. + * @param NewState: new state of the DMA2D peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void DMA2D_BGStart(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Start the automatic loading of the CLUT */ + DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START; + } + else + { + /* abort the transfer */ + DMA2D->BGPFCCR &= (uint32_t)~DMA2D_BGPFCCR_START; + } +} + +/** + * @brief Configures the DMA2D dead time. + * @param DMA2D_DeadTime: specifies the DMA2D dead time. + * This parameter can be one of the following values: + * @retval None + */ +void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState) +{ + uint32_t DeadTime; + + /* Check the parameters */ + assert_param(IS_DMA2D_DEAD_TIME(DMA2D_DeadTime)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable and Configures the dead time */ + DMA2D->AMTCR &= (uint32_t)DEAD_MASK; + DeadTime = DMA2D_DeadTime << 8; + DMA2D->AMTCR |= (DeadTime | DMA2D_AMTCR_EN); + } + else + { + DMA2D->AMTCR &= ~(uint32_t)DMA2D_AMTCR_EN; + } +} + +/** + * @brief Define the configuration of the line watermark . + * @param DMA2D_LWatermarkConfig: Line Watermark configuration. + * @retval None + */ + +void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LineWatermark(DMA2D_LWatermarkConfig)); + + /* Sets the Line watermark configuration */ + DMA2D->LWR = (uint32_t)DMA2D_LWatermarkConfig; +} + +/** + * @} + */ + +/** @defgroup DMA2D_Group2 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure the DMA2D + Interrupts and to get the status and clear flags and Interrupts + pending bits. + [..] The DMA2D provides 6 Interrupts sources and 6 Flags + + *** Flags *** + ============= + [..] + (+) DMA2D_FLAG_CE : Configuration Error Interrupt flag + (+) DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag + (+) DMA2D_FLAG_TW: Transfer Watermark Interrupt flag + (+) DMA2D_FLAG_TC: Transfer Complete interrupt flag + (+) DMA2D_FLAG_TE: Transfer Error interrupt flag + (+) DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag + + *** Interrupts *** + ================== + [..] + (+) DMA2D_IT_CE: Configuration Error Interrupt is generated when a wrong + configuration is detected + (+) DMA2D_IT_CAE: CLUT Access Error Interrupt + (+) DMA2D_IT_TW: Transfer Watermark Interrupt is generated when + the programmed watermark is reached + (+) DMA2D_IT_TE: Transfer Error interrupt is generated when the CPU trying + to access the CLUT while a CLUT loading or a DMA2D1 transfer + is on going + (+) DMA2D_IT_CTC: CLUT Transfer Complete Interrupt + (+) DMA2D_IT_TC: Transfer Complete interrupt +@endverbatim + * @{ + */ +/** + * @brief Enables or disables the specified DMA2D's interrupts. + * @param DMA2D_IT: specifies the DMA2D interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable. + * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable. + * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable. + * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable. + * @arg DMA2D_IT_TC: Transfer Complete interrupt enable. + * @arg DMA2D_IT_TE: Transfer Error interrupt enable. + * @param NewState: new state of the specified DMA2D interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_IT(DMA2D_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA2D interrupts */ + DMA2D->CR |= DMA2D_IT; + } + else + { + /* Disable the selected DMA2D interrupts */ + DMA2D->CR &= (uint32_t)~DMA2D_IT; + } +} + +/** + * @brief Checks whether the specified DMA2D's flag is set or not. + * @param DMA2D_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag. + * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag. + * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag. + * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag. + * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag. + * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag. + * @retval The new state of DMA2D_FLAG (SET or RESET). + */ + +FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG)); + + /* Check the status of the specified DMA2D flag */ + if (((DMA2D->ISR) & DMA2D_FLAG) != (uint32_t)RESET) + { + /* DMA2D_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA2D_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DMA2D_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMA2D's pending flags. + * @param DMA2D_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag. + * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag. + * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag. + * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag. + * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag. + * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag. + * @retval None + */ +void DMA2D_ClearFlag(uint32_t DMA2D_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG)); + + /* Clear the corresponding DMA2D flag */ + DMA2D->IFCR = (uint32_t)DMA2D_FLAG; +} + +/** + * @brief Checks whether the specified DMA2D's interrupt has occurred or not. + * @param DMA2D_IT: specifies the DMA2D interrupts sources to check. + * This parameter can be one of the following values: + * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable. + * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable. + * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable. + * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable. + * @arg DMA2D_IT_TC: Transfer Complete interrupt enable. + * @arg DMA2D_IT_TE: Transfer Error interrupt enable. + * @retval The new state of the DMA2D_IT (SET or RESET). + */ +ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT) +{ + ITStatus bitstatus = RESET; + uint32_t DMA2D_IT_FLAG = DMA2D_IT >> 8; + + /* Check the parameters */ + assert_param(IS_DMA2D_IT(DMA2D_IT)); + + if ((DMA2D->ISR & DMA2D_IT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + if (((DMA2D->CR & DMA2D_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the DMA2D's interrupt pending bits. + * @param DMA2D_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg DMA2D_IT_CE: Configuration Error Interrupt. + * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt. + * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt. + * @arg DMA2D_IT_TW: Transfer Watermark Interrupt. + * @arg DMA2D_IT_TC: Transfer Complete interrupt. + * @arg DMA2D_IT_TE: Transfer Error interrupt. + * @retval None + */ +void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_IT(DMA2D_IT)); + DMA2D_IT = DMA2D_IT >> 8; + + /* Clear the corresponding DMA2D Interrupt */ + DMA2D->IFCR = (uint32_t)DMA2D_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c index 74bf92c7c..433a8bf3a 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c @@ -1,311 +1,311 @@ -/** - ****************************************************************************** - * @file stm32f4xx_exti.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the EXTI peripheral: - * + Initialization and Configuration - * + Interrupts and flags management - * -@verbatim - - =============================================================================== - ##### EXTI features ##### - =============================================================================== - - [..] External interrupt/event lines are mapped as following: - (#) All available GPIO pins are connected to the 16 external - interrupt/event lines from EXTI0 to EXTI15. - (#) EXTI line 16 is connected to the PVD Output - (#) EXTI line 17 is connected to the RTC Alarm event - (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event - (#) EXTI line 19 is connected to the Ethernet Wakeup event - (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event - (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events - (#) EXTI line 22 is connected to the RTC Wakeup event - - ##### How to use this driver ##### - =============================================================================== - - [..] In order to use an I/O pin as an external interrupt source, follow steps - below: - (#) Configure the I/O in input mode using GPIO_Init() - (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() - (#) Select the mode(interrupt, event) and configure the trigger - selection (Rising, falling or both) using EXTI_Init() - (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() - - [..] - (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx - registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_exti.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** @defgroup EXTI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x007FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param EXTI_Line: specifies the EXTI line on which the software interrupt - * will be generated. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @} - */ - -/** @defgroup EXTI_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; - -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_exti.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the EXTI peripheral: + * + Initialization and Configuration + * + Interrupts and flags management + * +@verbatim + + =============================================================================== + ##### EXTI features ##### + =============================================================================== + + [..] External interrupt/event lines are mapped as following: + (#) All available GPIO pins are connected to the 16 external + interrupt/event lines from EXTI0 to EXTI15. + (#) EXTI line 16 is connected to the PVD Output + (#) EXTI line 17 is connected to the RTC Alarm event + (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event + (#) EXTI line 19 is connected to the Ethernet Wakeup event + (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event + (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events + (#) EXTI line 22 is connected to the RTC Wakeup event + + ##### How to use this driver ##### + =============================================================================== + + [..] In order to use an I/O pin as an external interrupt source, follow steps + below: + (#) Configure the I/O in input mode using GPIO_Init() + (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() + (#) Select the mode(interrupt, event) and configure the trigger + selection (Rising, falling or both) using EXTI_Init() + (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() + + [..] + (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx + registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + +@endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_exti.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** @defgroup EXTI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x007FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param EXTI_Line: specifies the EXTI line on which the software interrupt + * will be generated. + * This parameter can be any combination of EXTI_Linex where x can be (0..22) + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @} + */ + +/** @defgroup EXTI_Group2 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be EXTI_Linex where x can be(0..22) + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..22) + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be EXTI_Linex where x can be(0..22) + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; + +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..22) + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c index df4c5c69c..c077b6bca 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c @@ -1,1612 +1,1612 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * + FLASH Interface configuration - * + FLASH Memory Programming - * + Option Bytes Programming - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - This driver provides functions to configure and program the FLASH memory - of all STM32F4xx devices. These functions are split in 4 groups: - - (#) FLASH Interface configuration functions: this group includes the - management of the following features: - (++) Set the latency - (++) Enable/Disable the prefetch buffer - (++) Enable/Disable the Instruction cache and the Data cache - (++) Reset the Instruction cache and the Data cache - - (#) FLASH Memory Programming functions: this group includes all needed - functions to erase and program the main memory: - (++) Lock and Unlock the FLASH interface - (++) Erase function: Erase sector, erase all sectors - (++) Program functions: byte, half word, word and double word - - (#) Option Bytes Programming functions: this group includes all needed - functions to manage the Option Bytes: - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Set the BOR level - (++) Program the user Option Bytes - (++) Launch the Option Bytes loader - - (#) Interrupts and flags management functions: this group - includes all needed functions to: - (++) Enable/Disable the FLASH interrupt sources - (++) Get flags status - (++) Clear flags - (++) Get FLASH operation status - (++) Wait for last FLASH operation - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_flash.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** @defgroup FLASH_Group1 FLASH Interface configuration functions - * @brief FLASH Interface configuration functions - * - -@verbatim - =============================================================================== - ##### FLASH Interface configuration functions ##### - =============================================================================== - [..] - This group includes the following functions: - (+) void FLASH_SetLatency(uint32_t FLASH_Latency) - To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. - [..] - For STM32F405xx/07xx and STM32F415xx/17xx devices - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| - +---------------|----------------|----------------|-----------------|-----------------+ - - [..] - For STM32F42xxx/43xxx devices - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| - |---------------|----------------|----------------|-----------------|-----------------| - |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| - +-------------------------------------------------------------------------------------+ - - [..] - For STM32F401x devices - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | - +-------------------------------------------------------------------------------------+ - - [..] - For STM32F411xE devices - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 | - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 | - +-------------------------------------------------------------------------------------+ - - [..] - +-------------------------------------------------------------------------------------------------------------------+ - | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |Max Parallelism| x32 | x16 | x8 | x64 | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |PSIZE[1:0] | 10 | 01 | 00 | 11 | - +-------------------------------------------------------------------------------------------------------------------+ - - -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: - (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz. - (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz. - [..] - On STM32F42xxx/43xxx devices: - (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz. - (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON. - (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON. - [..] - On STM32F401x devices: - (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz. - (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz. - [..] - On STM32F411xE devices: - (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz. - (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz. - (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz. - - For more details please refer product DataSheet - You can use PWR_MainRegulatorModeConfig() function to control VOS bits. - - (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState) - (+) void FLASH_InstructionCacheCmd(FunctionalState NewState) - (+) void FLASH_DataCacheCmd(FunctionalState NewState) - (+) void FLASH_InstructionCacheReset(void) - (+) void FLASH_DataCacheReset(void) - - [..] - The unlock sequence is not needed for these functions. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @arg FLASH_Latency_3: FLASH Three Latency cycles - * @arg FLASH_Latency_4: FLASH Four Latency cycles - * @arg FLASH_Latency_5: FLASH Five Latency cycles - * @arg FLASH_Latency_6: FLASH Six Latency cycles - * @arg FLASH_Latency_7: FLASH Seven Latency cycles - * @arg FLASH_Latency_8: FLASH Eight Latency cycles - * @arg FLASH_Latency_9: FLASH Nine Latency cycles - * @arg FLASH_Latency_10: FLASH Teen Latency cycles - * @arg FLASH_Latency_11: FLASH Eleven Latency cycles - * @arg FLASH_Latency_12: FLASH Twelve Latency cycles - * @arg FLASH_Latency_13: FLASH Thirteen Latency cycles - * @arg FLASH_Latency_14: FLASH Fourteen Latency cycles - * @arg FLASH_Latency_15: FLASH Fifteen Latency cycles - * - * @note For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx/411xE devices this parameter - * can be a value between FLASH_Latency_0 and FLASH_Latency_7. - * - * @note For STM32F42xxx/43xxx devices this parameter can be a value between - * FLASH_Latency_0 and FLASH_Latency_15. - * - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */ - *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param NewState: new state of the Prefetch Buffer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_PrefetchBufferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Enable or disable the Prefetch Buffer */ - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_PRFTEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_PRFTEN); - } -} - -/** - * @brief Enables or disables the Instruction Cache feature. - * @param NewState: new state of the Instruction Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_InstructionCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_ICEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_ICEN); - } -} - -/** - * @brief Enables or disables the Data Cache feature. - * @param NewState: new state of the Data Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_DataCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_DCEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_DCEN); - } -} - -/** - * @brief Resets the Instruction Cache. - * @note This function must be used only when the Instruction Cache is disabled. - * @param None - * @retval None - */ -void FLASH_InstructionCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_ICRST; -} - -/** - * @brief Resets the Data Cache. - * @note This function must be used only when the Data Cache is disabled. - * @param None - * @retval None - */ -void FLASH_DataCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_DCRST; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group2 FLASH Memory Programming functions - * @brief FLASH Memory Programming functions - * -@verbatim - =============================================================================== - ##### FLASH Memory Programming functions ##### - =============================================================================== - [..] - This group includes the following functions: - (+) void FLASH_Unlock(void) - (+) void FLASH_Lock(void) - (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) - (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) - (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) - (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) - (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) - (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) - The following functions can be used only for STM32F42xxx/43xxx devices. - (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) - (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) - [..] - Any operation of erase or program should follow these steps: - (#) Call the FLASH_Unlock() function to enable the FLASH control register access - - (#) Call the desired function to erase sector(s) or program data - - (#) Call the FLASH_Lock() function to disable the FLASH control register access - (recommended to protect the FLASH memory against possible unwanted operation) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - } -} - -/** - * @brief Locks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - FLASH->CR |= FLASH_CR_LOCK; -} - -/** - * @brief Erases a specified FLASH Sector. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param FLASH_Sector: The Sector number to be erased. - * - * @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can - * be a value between FLASH_Sector_0 and FLASH_Sector_11. - * - * For STM32F42xxx/43xxx devices this parameter can be a value between - * FLASH_Sector_0 and FLASH_Sector_23. - * - * For STM32F401xx devices this parameter can be a value between - * FLASH_Sector_0 and FLASH_Sector_5. - * - * For STM32F411xE devices this parameter can be a value between - * FLASH_Sector_0 and FLASH_Sector_7. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(FLASH_Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR &= SECTOR_MASK; - FLASH->CR |= FLASH_CR_SER | FLASH_Sector; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH Sectors. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2); - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2); -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE) - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER); -#endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */ - - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH Sectors in Bank 1. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER1; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER1); - - } - /* Return the Erase Status */ - return status; -} - - -/** - * @brief Erases all FLASH Sectors in Bank 2. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER2; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER2); - - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Programs a double word (64-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V and an External Vpp is present. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint64_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a word (32-bit) at a specified address. - * - * @note This function must be used when the device voltage range is from 2.7V to 3.6V. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint32_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word (16-bit) at a specified address. - * @note This function must be used when the device voltage range is from 2.1V to 3.6V. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_HALF_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a byte (8-bit) at a specified address. - * @note This function can be used within all the device supply voltage ranges. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_BYTE; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint8_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - - /* Return the Program Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group3 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - =============================================================================== - ##### Option Bytes Programming functions ##### - =============================================================================== - [..] - This group includes the following functions: - (+) void FLASH_OB_Unlock(void) - (+) void FLASH_OB_Lock(void) - (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) - (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect) - (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) - (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) - (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP) - (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - (+) void FLASH_OB_BORConfig(uint8_t OB_BOR) - (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) - (+) FLASH_Status FLASH_OB_Launch(void) - (+) uint32_t FLASH_OB_GetUser(void) - (+) uint8_t FLASH_OB_GetWRP(void) - (+) uint8_t FLASH_OB_GetWRP1(void) - (+) uint8_t FLASH_OB_GetPCROP(void) - (+) uint8_t FLASH_OB_GetPCROP1(void) - (+) uint8_t FLASH_OB_GetRDP(void) - (+) uint8_t FLASH_OB_GetBOR(void) - [..] - The following function can be used only for STM32F42xxx/43xxx devices. - (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT) - [..] - Any operation of erase or program should follow these steps: - (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control - register access - - (#) Call one or several functions to program the desired Option Bytes: - (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - => to Enable/Disable the desired sector write protection - (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read - Protection Level - (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - => to configure the user Option Bytes. - (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level - - (#) Once all needed Option Bytes to be programmed are correctly written, - call the FLASH_OB_Launch() function to launch the Option Bytes - programming process. - - -@- When changing the IWDG mode from HW to SW or from SW to HW, a system - reset is needed to make the change effective. - - (#) Call the FLASH_OB_Lock() function to disable the FLASH option control - register access (recommended to protect the Option Bytes against - possible unwanted operations) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Unlock(void) -{ - if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) - { - /* Authorizes the Option Byte register programming */ - FLASH->OPTKEYR = FLASH_OPT_KEY1; - FLASH->OPTKEYR = FLASH_OPT_KEY2; - } -} - -/** - * @brief Locks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; -} - -/** - * @brief Enables or disables the write protection of the desired sectors, for the first - * 1 Mb of the Flash - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * - * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 - * @arg OB_WRP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); - } - else - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP; - } - } -} - -/** - * @brief Enables or disables the write protection of the desired sectors, for the second - * 1 Mb of the Flash - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note When the memory read out protection is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * - * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23 - * @arg OB_WRP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP); - } - else - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP; - } - } -} - -/** - * @brief Select the Protection Mode (SPRMOD). - * - * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. - * - * @note After PCROP activation, Option Byte modification is not possible. - * Exception made for the global Read Out Protection modification level (level1 to level0) - * @note Once SPRMOD bit is active unprotection of a protected sector is not possible - * - * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * - * @note Some Precautions should be taken when activating the PCROP feature : - * The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1 - * and WRPi = 1 (default value), then the user sector i is read/write protected. - * In order to avoid activation of PCROP Mode for undesired sectors, please follow the - * below safety sequence : - * - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function - * for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2 - * - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function - * - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function. - * - * @param OB_PCROP: Select the Protection Mode of nWPRi bits - * This parameter can be one of the following values: - * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors. - * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors. - * @retval None - */ -void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP) -{ - uint8_t optiontmp = 0xFF; - - /* Check the parameters */ - assert_param(IS_OB_PCROP_SELECT(OB_PcROP)); - - /* Mask SPRMOD bit */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); - /* Update Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp); - -} - -/** - * @brief Enables or disables the read/write protection (PCROP) of the desired - * sectors, for the first 1 MB of the Flash. - * - * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. - * - * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for - * STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and - * OB_PCROP_Sector5 for STM32F401xx/411xE devices. - * @arg OB_PCROP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_PCROP(OB_PCROP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; - } - else - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP); - } - } -} - -/** - * @brief Enables or disables the read/write protection (PCROP) of the desired - * sectors - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23 - * @arg OB_PCROP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_PCROP(OB_PCROP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; - } - else - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP); - } - } -} - - -/** - * @brief Sets the read protection level. - * @param OB_RDP: specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg OB_RDP_Level_2: Full chip protection - * - * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * - * @retval None - */ -void FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; - - } -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval None - */ -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - uint8_t optiontmp = 0xFF; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) - /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE) - /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); -#endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */ - - /* Update User Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); - } -} - -/** - * @brief Configure the Dual Bank Boot. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param OB_BOOT: specifies the Dual Bank Boot Option byte. - * This parameter can be one of the following values: - * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable - * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled - * @retval None - */ -void FLASH_OB_BootConfig(uint8_t OB_BOOT) -{ - /* Check the parameters */ - assert_param(IS_OB_BOOT(OB_BOOT)); - - /* Set Dual Bank Boot */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT; - -} - -/** - * @brief Sets the BOR Level. - * @param OB_BOR: specifies the Option Bytes BOR Reset Level. - * This parameter can be one of the following values: - * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V - * @retval None - */ -void FLASH_OB_BORConfig(uint8_t OB_BOR) -{ - /* Check the parameters */ - assert_param(IS_OB_BOR(OB_BOR)); - - /* Set the BOR Level */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; - -} - -/** - * @brief Launch the option byte loading. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_OB_Launch(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Set the OPTSTRT bit in OPTCR register */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @param None - * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)(FLASH->OPTCR >> 5); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetWRP1(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. - * - * @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices. - * - * @param None - * @retval The FLASH PC Read/Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetPCROP(void) -{ - /* Return the FLASH PC Read/write protection Register value */ - return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param None - * @retval The FLASH PC Read/Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetPCROP1(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH Read Protection level. - * @param None - * @retval FLASH ReadOut Protection Status: - * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set - * - RESET, when OB_RDP_Level_0 is set - */ -FlagStatus FLASH_OB_GetRDP(void) -{ - FlagStatus readstatus = RESET; - - if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0)) - { - readstatus = SET; - } - else - { - readstatus = RESET; - } - return readstatus; -} - -/** - * @brief Returns the FLASH BOR level. - * @param None - * @retval The FLASH BOR level: - * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V - */ -uint8_t FLASH_OB_GetBOR(void) -{ - /* Return the FLASH BOR level */ - return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); -} - -/** - * @} - */ - -/** @defgroup FLASH_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices) - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); - - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices) - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_RD; - } - else - { - if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_PROGRAM; - } - else - { - if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_OPERATION; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - } - } - /* Return the FLASH Status */ - return flashstatus; -} - -/** - * @brief Waits for a FLASH operation to complete. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(void) -{ - __IO FLASH_Status status = FLASH_COMPLETE; - - /* Check for the FLASH Status */ - status = FLASH_GetStatus(); - - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - while(status == FLASH_BUSY) - { - status = FLASH_GetStatus(); - } - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_flash.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * + FLASH Interface configuration + * + FLASH Memory Programming + * + Option Bytes Programming + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + This driver provides functions to configure and program the FLASH memory + of all STM32F4xx devices. These functions are split in 4 groups: + + (#) FLASH Interface configuration functions: this group includes the + management of the following features: + (++) Set the latency + (++) Enable/Disable the prefetch buffer + (++) Enable/Disable the Instruction cache and the Data cache + (++) Reset the Instruction cache and the Data cache + + (#) FLASH Memory Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase sector, erase all sectors + (++) Program functions: byte, half word, word and double word + + (#) Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Set the BOR level + (++) Program the user Option Bytes + (++) Launch the Option Bytes loader + + (#) Interrupts and flags management functions: this group + includes all needed functions to: + (++) Enable/Disable the FLASH interrupt sources + (++) Get flags status + (++) Clear flags + (++) Get FLASH operation status + (++) Wait for last FLASH operation + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_flash.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SECTOR_MASK ((uint32_t)0xFFFFFF07) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** @defgroup FLASH_Group1 FLASH Interface configuration functions + * @brief FLASH Interface configuration functions + * + +@verbatim + =============================================================================== + ##### FLASH Interface configuration functions ##### + =============================================================================== + [..] + This group includes the following functions: + (+) void FLASH_SetLatency(uint32_t FLASH_Latency) + To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. + [..] + For STM32F405xx/07xx and STM32F415xx/17xx devices + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| + +---------------|----------------|----------------|-----------------|-----------------+ + + [..] + For STM32F42xxx/43xxx devices + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| + |---------------|----------------|----------------|-----------------|-----------------| + |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| + +-------------------------------------------------------------------------------------+ + + [..] + For STM32F401x devices + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | + +-------------------------------------------------------------------------------------+ + + [..] + For STM32F411xE devices + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 | + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 | + +-------------------------------------------------------------------------------------+ + + [..] + +-------------------------------------------------------------------------------------------------------------------+ + | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | + |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| + |Max Parallelism| x32 | x16 | x8 | x64 | + |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| + |PSIZE[1:0] | 10 | 01 | 00 | 11 | + +-------------------------------------------------------------------------------------------------------------------+ + + -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: + (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz. + (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz. + [..] + On STM32F42xxx/43xxx devices: + (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz. + (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON. + (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON. + [..] + On STM32F401x devices: + (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz. + (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz. + [..] + On STM32F411xE devices: + (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz. + (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz. + (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz. + + For more details please refer product DataSheet + You can use PWR_MainRegulatorModeConfig() function to control VOS bits. + + (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState) + (+) void FLASH_InstructionCacheCmd(FunctionalState NewState) + (+) void FLASH_DataCacheCmd(FunctionalState NewState) + (+) void FLASH_InstructionCacheReset(void) + (+) void FLASH_DataCacheReset(void) + + [..] + The unlock sequence is not needed for these functions. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the code latency value. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @arg FLASH_Latency_2: FLASH Two Latency cycles + * @arg FLASH_Latency_3: FLASH Three Latency cycles + * @arg FLASH_Latency_4: FLASH Four Latency cycles + * @arg FLASH_Latency_5: FLASH Five Latency cycles + * @arg FLASH_Latency_6: FLASH Six Latency cycles + * @arg FLASH_Latency_7: FLASH Seven Latency cycles + * @arg FLASH_Latency_8: FLASH Eight Latency cycles + * @arg FLASH_Latency_9: FLASH Nine Latency cycles + * @arg FLASH_Latency_10: FLASH Teen Latency cycles + * @arg FLASH_Latency_11: FLASH Eleven Latency cycles + * @arg FLASH_Latency_12: FLASH Twelve Latency cycles + * @arg FLASH_Latency_13: FLASH Thirteen Latency cycles + * @arg FLASH_Latency_14: FLASH Fourteen Latency cycles + * @arg FLASH_Latency_15: FLASH Fifteen Latency cycles + * + * @note For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx/411xE devices this parameter + * can be a value between FLASH_Latency_0 and FLASH_Latency_7. + * + * @note For STM32F42xxx/43xxx devices this parameter can be a value between + * FLASH_Latency_0 and FLASH_Latency_15. + * + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */ + *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @param NewState: new state of the Prefetch Buffer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_PrefetchBufferCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Enable or disable the Prefetch Buffer */ + if(NewState != DISABLE) + { + FLASH->ACR |= FLASH_ACR_PRFTEN; + } + else + { + FLASH->ACR &= (~FLASH_ACR_PRFTEN); + } +} + +/** + * @brief Enables or disables the Instruction Cache feature. + * @param NewState: new state of the Instruction Cache. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_InstructionCacheCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + FLASH->ACR |= FLASH_ACR_ICEN; + } + else + { + FLASH->ACR &= (~FLASH_ACR_ICEN); + } +} + +/** + * @brief Enables or disables the Data Cache feature. + * @param NewState: new state of the Data Cache. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_DataCacheCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + FLASH->ACR |= FLASH_ACR_DCEN; + } + else + { + FLASH->ACR &= (~FLASH_ACR_DCEN); + } +} + +/** + * @brief Resets the Instruction Cache. + * @note This function must be used only when the Instruction Cache is disabled. + * @param None + * @retval None + */ +void FLASH_InstructionCacheReset(void) +{ + FLASH->ACR |= FLASH_ACR_ICRST; +} + +/** + * @brief Resets the Data Cache. + * @note This function must be used only when the Data Cache is disabled. + * @param None + * @retval None + */ +void FLASH_DataCacheReset(void) +{ + FLASH->ACR |= FLASH_ACR_DCRST; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group2 FLASH Memory Programming functions + * @brief FLASH Memory Programming functions + * +@verbatim + =============================================================================== + ##### FLASH Memory Programming functions ##### + =============================================================================== + [..] + This group includes the following functions: + (+) void FLASH_Unlock(void) + (+) void FLASH_Lock(void) + (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) + (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) + (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) + (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) + (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) + (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) + The following functions can be used only for STM32F42xxx/43xxx devices. + (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) + (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) + [..] + Any operation of erase or program should follow these steps: + (#) Call the FLASH_Unlock() function to enable the FLASH control register access + + (#) Call the desired function to erase sector(s) or program data + + (#) Call the FLASH_Lock() function to disable the FLASH control register access + (recommended to protect the FLASH memory against possible unwanted operation) + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the FLASH control register access + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + if((FLASH->CR & FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + } +} + +/** + * @brief Locks the FLASH control register access + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + FLASH->CR |= FLASH_CR_LOCK; +} + +/** + * @brief Erases a specified FLASH Sector. + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. + * + * @param FLASH_Sector: The Sector number to be erased. + * + * @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can + * be a value between FLASH_Sector_0 and FLASH_Sector_11. + * + * For STM32F42xxx/43xxx devices this parameter can be a value between + * FLASH_Sector_0 and FLASH_Sector_23. + * + * For STM32F401xx devices this parameter can be a value between + * FLASH_Sector_0 and FLASH_Sector_5. + * + * For STM32F411xE devices this parameter can be a value between + * FLASH_Sector_0 and FLASH_Sector_7. + * + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0x0; + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(FLASH_Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == VoltageRange_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == VoltageRange_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == VoltageRange_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the sector */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR &= SECTOR_MASK; + FLASH->CR |= FLASH_CR_SER | FLASH_Sector; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the SER Bit */ + FLASH->CR &= (~FLASH_CR_SER); + FLASH->CR &= SECTOR_MASK; + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH Sectors. + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. + * + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0x0; + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == VoltageRange_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == VoltageRange_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == VoltageRange_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all sectors */ +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2); + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2); +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE) + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_CR_MER); +#endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */ + + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH Sectors in Bank 1. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0x0; + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == VoltageRange_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == VoltageRange_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == VoltageRange_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR |= FLASH_CR_MER1; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_CR_MER1); + + } + /* Return the Erase Status */ + return status; +} + + +/** + * @brief Erases all FLASH Sectors in Bank 2. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0x0; + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == VoltageRange_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == VoltageRange_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == VoltageRange_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR |= FLASH_CR_MER2; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_CR_MER2); + + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Programs a double word (64-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V and an External Vpp is present. + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. + * + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint64_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a word (32-bit) at a specified address. + * + * @note This function must be used when the device voltage range is from 2.7V to 3.6V. + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. + * + * @param Address: specifies the address to be programmed. + * This parameter can be any address in Program memory zone or in OTP zone. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint32_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word (16-bit) at a specified address. + * @note This function must be used when the device voltage range is from 2.1V to 3.6V. + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. + * + * @param Address: specifies the address to be programmed. + * This parameter can be any address in Program memory zone or in OTP zone. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_HALF_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a byte (8-bit) at a specified address. + * @note This function can be used within all the device supply voltage ranges. + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. + * + * @param Address: specifies the address to be programmed. + * This parameter can be any address in Program memory zone or in OTP zone. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_BYTE; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint8_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + + /* Return the Program Status */ + return status; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group3 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + =============================================================================== + ##### Option Bytes Programming functions ##### + =============================================================================== + [..] + This group includes the following functions: + (+) void FLASH_OB_Unlock(void) + (+) void FLASH_OB_Lock(void) + (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) + (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) + (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect) + (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) + (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) + (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP) + (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) + (+) void FLASH_OB_BORConfig(uint8_t OB_BOR) + (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) + (+) FLASH_Status FLASH_OB_Launch(void) + (+) uint32_t FLASH_OB_GetUser(void) + (+) uint8_t FLASH_OB_GetWRP(void) + (+) uint8_t FLASH_OB_GetWRP1(void) + (+) uint8_t FLASH_OB_GetPCROP(void) + (+) uint8_t FLASH_OB_GetPCROP1(void) + (+) uint8_t FLASH_OB_GetRDP(void) + (+) uint8_t FLASH_OB_GetBOR(void) + [..] + The following function can be used only for STM32F42xxx/43xxx devices. + (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT) + [..] + Any operation of erase or program should follow these steps: + (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control + register access + + (#) Call one or several functions to program the desired Option Bytes: + (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) + => to Enable/Disable the desired sector write protection + (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read + Protection Level + (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) + => to configure the user Option Bytes. + (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level + + (#) Once all needed Option Bytes to be programmed are correctly written, + call the FLASH_OB_Launch() function to launch the Option Bytes + programming process. + + -@- When changing the IWDG mode from HW to SW or from SW to HW, a system + reset is needed to make the change effective. + + (#) Call the FLASH_OB_Lock() function to disable the FLASH option control + register access (recommended to protect the Option Bytes against + possible unwanted operations) + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the FLASH Option Control Registers access. + * @param None + * @retval None + */ +void FLASH_OB_Unlock(void) +{ + if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) + { + /* Authorizes the Option Byte register programming */ + FLASH->OPTKEYR = FLASH_OPT_KEY1; + FLASH->OPTKEYR = FLASH_OPT_KEY2; + } +} + +/** + * @brief Locks the FLASH Option Control Registers access. + * @param None + * @retval None + */ +void FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; +} + +/** + * @brief Enables or disables the write protection of the desired sectors, for the first + * 1 Mb of the Flash + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 + * @arg OB_WRP_Sector_All + * @param Newstate: new state of the Write Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_WRP(OB_WRP)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + if(NewState != DISABLE) + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); + } + else + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP; + } + } +} + +/** + * @brief Enables or disables the write protection of the desired sectors, for the second + * 1 Mb of the Flash + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note When the memory read out protection is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23 + * @arg OB_WRP_Sector_All + * @param Newstate: new state of the Write Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_WRP(OB_WRP)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + if(NewState != DISABLE) + { + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP); + } + else + { + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP; + } + } +} + +/** + * @brief Select the Protection Mode (SPRMOD). + * + * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. + * + * @note After PCROP activation, Option Byte modification is not possible. + * Exception made for the global Read Out Protection modification level (level1 to level0) + * @note Once SPRMOD bit is active unprotection of a protected sector is not possible + * + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * + * @note Some Precautions should be taken when activating the PCROP feature : + * The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1 + * and WRPi = 1 (default value), then the user sector i is read/write protected. + * In order to avoid activation of PCROP Mode for undesired sectors, please follow the + * below safety sequence : + * - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function + * for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2 + * - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function + * - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function. + * + * @param OB_PCROP: Select the Protection Mode of nWPRi bits + * This parameter can be one of the following values: + * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors. + * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors. + * @retval None + */ +void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP) +{ + uint8_t optiontmp = 0xFF; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_SELECT(OB_PcROP)); + + /* Mask SPRMOD bit */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + /* Update Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp); + +} + +/** + * @brief Enables or disables the read/write protection (PCROP) of the desired + * sectors, for the first 1 MB of the Flash. + * + * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. + * + * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for + * STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and + * OB_PCROP_Sector5 for STM32F401xx/411xE devices. + * @arg OB_PCROP_Sector_All + * @param Newstate: new state of the Write Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_PCROP(OB_PCROP)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + if(NewState != DISABLE) + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; + } + else + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP); + } + } +} + +/** + * @brief Enables or disables the read/write protection (PCROP) of the desired + * sectors + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23 + * @arg OB_PCROP_Sector_All + * @param Newstate: new state of the Write Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_PCROP(OB_PCROP)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + if(NewState != DISABLE) + { + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; + } + else + { + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP); + } + } +} + + +/** + * @brief Sets the read protection level. + * @param OB_RDP: specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_Level_0: No protection + * @arg OB_RDP_Level_1: Read protection of the memory + * @arg OB_RDP_Level_2: Full chip protection + * + * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * + * @retval None + */ +void FLASH_OB_RDPConfig(uint8_t OB_RDP) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_RDP(OB_RDP)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; + + } +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param OB_IWDG: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval None + */ +void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) +{ + uint8_t optiontmp = 0xFF; + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) + /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE) + /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); +#endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */ + + /* Update User Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); + } +} + +/** + * @brief Configure the Dual Bank Boot. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param OB_BOOT: specifies the Dual Bank Boot Option byte. + * This parameter can be one of the following values: + * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable + * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled + * @retval None + */ +void FLASH_OB_BootConfig(uint8_t OB_BOOT) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT(OB_BOOT)); + + /* Set Dual Bank Boot */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT; + +} + +/** + * @brief Sets the BOR Level. + * @param OB_BOR: specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V + * @retval None + */ +void FLASH_OB_BORConfig(uint8_t OB_BOR) +{ + /* Check the parameters */ + assert_param(IS_OB_BOR(OB_BOR)); + + /* Set the BOR Level */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; + +} + +/** + * @brief Launch the option byte loading. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_OB_Launch(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Set the OPTSTRT bit in OPTCR register */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @param None + * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)(FLASH->OPTCR >> 5); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes value. + * @param None + * @retval The FLASH Write Protection Option Bytes value + */ +uint16_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes value. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param None + * @retval The FLASH Write Protection Option Bytes value + */ +uint16_t FLASH_OB_GetWRP1(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); +} + +/** + * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. + * + * @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices. + * + * @param None + * @retval The FLASH PC Read/Write Protection Option Bytes value + */ +uint16_t FLASH_OB_GetPCROP(void) +{ + /* Return the FLASH PC Read/write protection Register value */ + return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); +} + +/** + * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param None + * @retval The FLASH PC Read/Write Protection Option Bytes value + */ +uint16_t FLASH_OB_GetPCROP1(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @param None + * @retval FLASH ReadOut Protection Status: + * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set + * - RESET, when OB_RDP_Level_0 is set + */ +FlagStatus FLASH_OB_GetRDP(void) +{ + FlagStatus readstatus = RESET; + + if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0)) + { + readstatus = SET; + } + else + { + readstatus = RESET; + } + return readstatus; +} + +/** + * @brief Returns the FLASH BOR level. + * @param None + * @retval The FLASH BOR level: + * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V + */ +uint8_t FLASH_OB_GetBOR(void) +{ + /* Return the FLASH BOR level */ + return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); +} + +/** + * @} + */ + +/** @defgroup FLASH_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERR: FLASH Error Interrupt + * @arg FLASH_IT_EOP: FLASH end of operation Interrupt + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR: FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices) + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); + + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR: FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices) + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +} + +/** + * @brief Returns the FLASH Status. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_RD; + } + else + { + if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_PROGRAM; + } + else + { + if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_OPERATION; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + } + } + /* Return the FLASH Status */ + return flashstatus; +} + +/** + * @brief Waits for a FLASH operation to complete. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(void) +{ + __IO FLASH_Status status = FLASH_COMPLETE; + + /* Check for the FLASH Status */ + status = FLASH_GetStatus(); + + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + while(status == FLASH_BUSY) + { + status = FLASH_GetStatus(); + } + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c index 6ed3b321b..11e81b643 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c @@ -1,158 +1,158 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash_ramfunc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief FLASH RAMFUNC module driver. - * This file provides a FLASH firmware functions which should be - * executed from internal SRAM - * + Stop/Start the flash interface while System Run - * + Enable/Disable the flash sleep while System Run - * - @verbatim - ============================================================================== - ##### APIs executed from Internal RAM ##### - ============================================================================== - [..] - *** ARM Compiler *** - -------------------- - [..] RAM functions are defined using the toolchain options. - Functions that are be executed in RAM should reside in a separate - source module. Using the 'Options for File' dialog you can simply change - the 'Code / Const' area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the - Options for Target' dialog. - - *** ICCARM Compiler *** - ----------------------- - [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". - - *** GNU Compiler *** - -------------------- - [..] RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_flash_ramfunc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH RAMFUNC - * @brief FLASH RAMFUNC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_RAMFUNC_Private_Functions - * @{ - */ - -/** @defgroup FLASH_RAMFUNC_Group1 Peripheral features functions executed from internal RAM - * @brief Peripheral Extended features functions - * -@verbatim - - =============================================================================== - ##### ramfunc functions ##### - =============================================================================== - [..] - This subsection provides a set of functions that should be executed from RAM - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Start/Stop the flash interface while System Run - * @note This mode is only available for STM32F411xx devices. - * @note This mode could n't be set while executing with the flash itself. - * It should be done with specific routine executed from RAM. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState) -{ - if (NewState != DISABLE) - { - /* Start the flash interface while System Run */ - CLEAR_BIT(PWR->CR, PWR_CR_FISSR); - } - else - { - /* Stop the flash interface while System Run */ - SET_BIT(PWR->CR, PWR_CR_FISSR); - } -} - -/** - * @brief Enable/Disable the flash sleep while System Run - * @note This mode is only available for STM32F411xx devices. - * @note This mode could n't be set while executing with the flash itself. - * It should be done with specific routine executed from RAM. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState) -{ - if (NewState != DISABLE) - { - /* Enable the flash sleep while System Run */ - SET_BIT(PWR->CR, PWR_CR_FMSSR); - } - else - { - /* Disable the flash sleep while System Run */ - CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_flash_ramfunc.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief FLASH RAMFUNC module driver. + * This file provides a FLASH firmware functions which should be + * executed from internal SRAM + * + Stop/Start the flash interface while System Run + * + Enable/Disable the flash sleep while System Run + * + @verbatim + ============================================================================== + ##### APIs executed from Internal RAM ##### + ============================================================================== + [..] + *** ARM Compiler *** + -------------------- + [..] RAM functions are defined using the toolchain options. + Functions that are be executed in RAM should reside in a separate + source module. Using the 'Options for File' dialog you can simply change + the 'Code / Const' area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the + Options for Target' dialog. + + *** ICCARM Compiler *** + ----------------------- + [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". + + *** GNU Compiler *** + -------------------- + [..] RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_flash_ramfunc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH RAMFUNC + * @brief FLASH RAMFUNC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_RAMFUNC_Private_Functions + * @{ + */ + +/** @defgroup FLASH_RAMFUNC_Group1 Peripheral features functions executed from internal RAM + * @brief Peripheral Extended features functions + * +@verbatim + + =============================================================================== + ##### ramfunc functions ##### + =============================================================================== + [..] + This subsection provides a set of functions that should be executed from RAM + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start/Stop the flash interface while System Run + * @note This mode is only available for STM32F411xx devices. + * @note This mode could n't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + /* Start the flash interface while System Run */ + CLEAR_BIT(PWR->CR, PWR_CR_FISSR); + } + else + { + /* Stop the flash interface while System Run */ + SET_BIT(PWR->CR, PWR_CR_FISSR); + } +} + +/** + * @brief Enable/Disable the flash sleep while System Run + * @note This mode is only available for STM32F411xx devices. + * @note This mode could n't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + /* Enable the flash sleep while System Run */ + SET_BIT(PWR->CR, PWR_CR_FMSSR); + } + else + { + /* Disable the flash sleep while System Run */ + CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c index 1f255114a..fd81167eb 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c @@ -1,1367 +1,1367 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fmc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the FMC peripheral: - * + Interface with SRAM, PSRAM, NOR and OneNAND memories - * + Interface with NAND memories - * + Interface with 16-bit PC Card compatible memories - * + Interface with SDRAM memories - * + Interrupts and flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_fmc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FMC - * @brief FMC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -const FMC_NORSRAMTimingInitTypeDef FMC_DefaultTimingStruct = {0x0F, /* FMC_AddressSetupTime */ - 0x0F, /* FMC_AddressHoldTime */ - 0xFF, /* FMC_DataSetupTime */ - 0x0F, /* FMC_BusTurnAroundDuration */ - 0x0F, /* FMC_CLKDivision */ - 0x0F, /* FMC_DataLatency */ - FMC_AccessMode_A /* FMC_AccessMode */ - }; -/* --------------------- FMC registers bit mask ---------------------------- */ -/* FMC BCRx Mask */ -#define BCR_MBKEN_SET ((uint32_t)0x00000001) -#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_SET ((uint32_t)0x00000040) - -/* FMC PCRx Mask */ -#define PCR_PBKEN_SET ((uint32_t)0x00000004) -#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_SET ((uint32_t)0x00000040) -#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) -#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) - -/* FMC SDCRx write protection Mask*/ -#define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF) - -/* FMC SDCMR Mask*/ -#define SDCMR_CTB1_RESET ((uint32_t)0x003FFFEF) -#define SDCMR_CTB2_RESET ((uint32_t)0x003FFFF7) -#define SDCMR_CTB1_2_RESET ((uint32_t)0x003FFFE7) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FMC_Private_Functions - * @{ - */ - -/** @defgroup FMC_Group1 NOR/SRAM Controller functions - * @brief NOR/SRAM Controller functions - * -@verbatim - =============================================================================== - ##### NOR and SRAM Controller functions ##### - =============================================================================== - - [..] The following sequence should be followed to configure the FMC to interface - with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: - - (#) Enable the clock for the FMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FMC pins configuration - (++) Connect the involved FMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); - (++) Configure these FMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FMC_NORSRAMInitTypeDef structure, for example: - FMC_NORSRAMInitTypeDef FMC_NORSRAMInitStructure; - and fill the FMC_NORSRAMInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the NOR/SRAM Controller by calling the function - FMC_NORSRAMInit(&FMC_NORSRAMInitStructure); - - (#) Then enable the NOR/SRAM Bank, for example: - FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FMC NOR/SRAM Banks registers to their default - * reset values. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 - * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 - * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 - * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 - * @retval None - */ -void FMC_NORSRAMDeInit(uint32_t FMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); - - /* FMC_Bank1_NORSRAM1 */ - if(FMC_Bank == FMC_Bank1_NORSRAM1) - { - FMC_Bank1->BTCR[FMC_Bank] = 0x000030DB; - } - /* FMC_Bank1_NORSRAM2, FMC_Bank1_NORSRAM3 or FMC_Bank1_NORSRAM4 */ - else - { - FMC_Bank1->BTCR[FMC_Bank] = 0x000030D2; - } - FMC_Bank1->BTCR[FMC_Bank + 1] = 0x0FFFFFFF; - FMC_Bank1E->BWTR[FMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Initializes the FMC NOR/SRAM Banks according to the specified - * parameters in the FMC_NORSRAMInitStruct. - * @param FMC_NORSRAMInitStruct : pointer to a FMC_NORSRAMInitTypeDef structure - * that contains the configuration information for the FMC NOR/SRAM - * specified Banks. - * @retval None - */ -void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank)); - assert_param(IS_FMC_MUX(FMC_NORSRAMInitStruct->FMC_DataAddressMux)); - assert_param(IS_FMC_MEMORY(FMC_NORSRAMInitStruct->FMC_MemoryType)); - assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(FMC_NORSRAMInitStruct->FMC_MemoryDataWidth)); - assert_param(IS_FMC_BURSTMODE(FMC_NORSRAMInitStruct->FMC_BurstAccessMode)); - assert_param(IS_FMC_WAIT_POLARITY(FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity)); - assert_param(IS_FMC_WRAP_MODE(FMC_NORSRAMInitStruct->FMC_WrapMode)); - assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(FMC_NORSRAMInitStruct->FMC_WaitSignalActive)); - assert_param(IS_FMC_WRITE_OPERATION(FMC_NORSRAMInitStruct->FMC_WriteOperation)); - assert_param(IS_FMC_WAITE_SIGNAL(FMC_NORSRAMInitStruct->FMC_WaitSignal)); - assert_param(IS_FMC_EXTENDED_MODE(FMC_NORSRAMInitStruct->FMC_ExtendedMode)); - assert_param(IS_FMC_ASYNWAIT(FMC_NORSRAMInitStruct->FMC_AsynchronousWait)); - assert_param(IS_FMC_WRITE_BURST(FMC_NORSRAMInitStruct->FMC_WriteBurst)); - assert_param(IS_FMC_CONTINOUS_CLOCK(FMC_NORSRAMInitStruct->FMC_ContinousClock)); - assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime)); - assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration)); - assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)); - assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency)); - assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode)); - - /* NOR/SRAM Bank control register configuration */ - FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] = - (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux | - FMC_NORSRAMInitStruct->FMC_MemoryType | - FMC_NORSRAMInitStruct->FMC_MemoryDataWidth | - FMC_NORSRAMInitStruct->FMC_BurstAccessMode | - FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity | - FMC_NORSRAMInitStruct->FMC_WrapMode | - FMC_NORSRAMInitStruct->FMC_WaitSignalActive | - FMC_NORSRAMInitStruct->FMC_WriteOperation | - FMC_NORSRAMInitStruct->FMC_WaitSignal | - FMC_NORSRAMInitStruct->FMC_ExtendedMode | - FMC_NORSRAMInitStruct->FMC_AsynchronousWait | - FMC_NORSRAMInitStruct->FMC_WriteBurst | - FMC_NORSRAMInitStruct->FMC_ContinousClock; - - - if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR) - { - FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET; - } - - /* Configure Continuous clock feature when bank2..4 is used */ - if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1)) - { - tmpr = (uint32_t)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((uint32_t)0x0F) << 20)); - - FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_NORSRAMInitStruct->FMC_ContinousClock; - FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_BurstAccessMode_Enable; - FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (uint32_t)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20)); - } - - /* NOR/SRAM Bank timing register configuration */ - FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] = - (uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime | - (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) | - (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) | - (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) | - ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision) << 20) | - ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency) << 24) | - FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode; - - /* NOR/SRAM Bank timing register for write configuration, if extended mode is used */ - if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable) - { - assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime)); - assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision)); - assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency)); - assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode)); - - FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = - (uint32_t)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime | - (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )| - (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) | - ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) | - ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency) << 24) | - FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode; - } - else - { - FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 0x0FFFFFFF; - } - -} - -/** - * @brief Fills each FMC_NORSRAMInitStruct member with its default value. - * @param FMC_NORSRAMInitStruct: pointer to a FMC_NORSRAMInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FMC_NORSRAMInitStruct->FMC_Bank = FMC_Bank1_NORSRAM1; - FMC_NORSRAMInitStruct->FMC_DataAddressMux = FMC_DataAddressMux_Enable; - FMC_NORSRAMInitStruct->FMC_MemoryType = FMC_MemoryType_SRAM; - FMC_NORSRAMInitStruct->FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b; - FMC_NORSRAMInitStruct->FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; - FMC_NORSRAMInitStruct->FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; - FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; - FMC_NORSRAMInitStruct->FMC_WrapMode = FMC_WrapMode_Disable; - FMC_NORSRAMInitStruct->FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; - FMC_NORSRAMInitStruct->FMC_WriteOperation = FMC_WriteOperation_Enable; - FMC_NORSRAMInitStruct->FMC_WaitSignal = FMC_WaitSignal_Enable; - FMC_NORSRAMInitStruct->FMC_ExtendedMode = FMC_ExtendedMode_Disable; - FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable; - FMC_NORSRAMInitStruct->FMC_ContinousClock = FMC_CClock_SyncOnly; - - FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)&FMC_DefaultTimingStruct; - FMC_NORSRAMInitStruct->FMC_WriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)&FMC_DefaultTimingStruct; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 - * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 - * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 - * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FMC_Bank1->BTCR[FMC_Bank] |= BCR_MBKEN_SET; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FMC_Bank1->BTCR[FMC_Bank] &= BCR_MBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FMC_Group2 NAND Controller functions - * @brief NAND Controller functions - * -@verbatim - =============================================================================== - ##### NAND Controller functions ##### - =============================================================================== - - [..] The following sequence should be followed to configure the FMC to interface - with 8-bit or 16-bit NAND memory connected to the NAND Bank: - - (#) Enable the clock for the FMC and associated GPIOs using the following functions: - (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); - (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FMC pins configuration - (++) Connect the involved FMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); - (++) Configure these FMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FMC_NANDInitTypeDef structure, for example: - FMC_NANDInitTypeDef FMC_NANDInitStructure; - and fill the FMC_NANDInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the NAND Controller by calling the function - FMC_NANDInit(&FMC_NANDInitStructure); - - (#) Then enable the NAND Bank, for example: - FMC_NANDCmd(FMC_Bank3_NAND, ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the NAND Bank. - - [..] - (@) To enable the Error Correction Code (ECC), you have to use the function - FMC_NANDECCCmd(FMC_Bank3_NAND, ENABLE); - [..] - (@) and to get the current ECC value you have to use the function - ECCval = FMC_GetECC(FMC_Bank3_NAND); - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FMC NAND Banks registers to their default reset values. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @retval None - */ -void FMC_NANDDeInit(uint32_t FMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FMC_NAND_BANK(FMC_Bank)); - - if(FMC_Bank == FMC_Bank2_NAND) - { - /* Set the FMC_Bank2 registers to their reset values */ - FMC_Bank2->PCR2 = 0x00000018; - FMC_Bank2->SR2 = 0x00000040; - FMC_Bank2->PMEM2 = 0xFCFCFCFC; - FMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FMC_Bank3_NAND */ - else - { - /* Set the FMC_Bank3 registers to their reset values */ - FMC_Bank3->PCR3 = 0x00000018; - FMC_Bank3->SR3 = 0x00000040; - FMC_Bank3->PMEM3 = 0xFCFCFCFC; - FMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Initializes the FMC NAND Banks according to the specified parameters - * in the FMC_NANDInitStruct. - * @param FMC_NANDInitStruct : pointer to a FMC_NANDInitTypeDef structure that - * contains the configuration information for the FMC NAND specified Banks. - * @retval None - */ -void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank)); - assert_param(IS_FMC_WAIT_FEATURE(FMC_NANDInitStruct->FMC_Waitfeature)); - assert_param(IS_FMC_NAND_MEMORY_WIDTH(FMC_NANDInitStruct->FMC_MemoryDataWidth)); - assert_param(IS_FMC_ECC_STATE(FMC_NANDInitStruct->FMC_ECC)); - assert_param(IS_FMC_ECCPAGE_SIZE(FMC_NANDInitStruct->FMC_ECCPageSize)); - assert_param(IS_FMC_TCLR_TIME(FMC_NANDInitStruct->FMC_TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(FMC_NANDInitStruct->FMC_TARSetupTime)); - assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); - assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); - assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); - assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); - - /* Set the tmppcr value according to FMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature | - PCR_MEMORYTYPE_NAND | - FMC_NANDInitStruct->FMC_MemoryDataWidth | - FMC_NANDInitStruct->FMC_ECC | - FMC_NANDInitStruct->FMC_ECCPageSize | - (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )| - (FMC_NANDInitStruct->FMC_TARSetupTime << 13); - - /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | - (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | - (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| - (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | - (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | - (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| - (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); - - if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND) - { - /* FMC_Bank2_NAND registers configuration */ - FMC_Bank2->PCR2 = tmppcr; - FMC_Bank2->PMEM2 = tmppmem; - FMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FMC_Bank3_NAND registers configuration */ - FMC_Bank3->PCR3 = tmppcr; - FMC_Bank3->PMEM3 = tmppmem; - FMC_Bank3->PATT3 = tmppatt; - } -} - - -/** - * @brief Fills each FMC_NANDInitStruct member with its default value. - * @param FMC_NANDInitStruct: pointer to a FMC_NANDInitTypeDef structure which - * will be initialized. - * @retval None - */ -void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FMC_NANDInitStruct->FMC_Bank = FMC_Bank2_NAND; - FMC_NANDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; - FMC_NANDInitStruct->FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_16b; - FMC_NANDInitStruct->FMC_ECC = FMC_ECC_Disable; - FMC_NANDInitStruct->FMC_ECCPageSize = FMC_ECCPageSize_256Bytes; - FMC_NANDInitStruct->FMC_TCLRSetupTime = 0x0; - FMC_NANDInitStruct->FMC_TARSetupTime = 0x0; - FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; - FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; - FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; - FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; - FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; - FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; - FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; - FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FMC_NAND_BANK(FMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->PCR2 |= PCR_PBKEN_SET; - } - else - { - FMC_Bank3->PCR3 |= PCR_PBKEN_SET; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->PCR2 &= PCR_PBKEN_RESET; - } - else - { - FMC_Bank3->PCR3 &= PCR_PBKEN_RESET; - } - } -} -/** - * @brief Enables or disables the FMC NAND ECC feature. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @param NewState: new state of the FMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FMC_NAND_BANK(FMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->PCR2 |= PCR_ECCEN_SET; - } - else - { - FMC_Bank3->PCR3 |= PCR_ECCEN_SET; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->PCR2 &= PCR_ECCEN_RESET; - } - else - { - FMC_Bank3->PCR3 &= PCR_ECCEN_RESET; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FMC_GetECC(uint32_t FMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FMC_Bank == FMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} -/** - * @} - */ - -/** @defgroup FMC_Group3 PCCARD Controller functions - * @brief PCCARD Controller functions - * -@verbatim - =============================================================================== - ##### PCCARD Controller functions ##### - =============================================================================== - - [..] he following sequence should be followed to configure the FMC to interface - with 16-bit PC Card compatible memory connected to the PCCARD Bank: - - (#) Enable the clock for the FMC and associated GPIOs using the following functions: - (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); - (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FMC pins configuration - (++) Connect the involved FMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); - (++) Configure these FMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FMC_PCCARDInitTypeDef structure, for example: - FMC_PCCARDInitTypeDef FMC_PCCARDInitStructure; - and fill the FMC_PCCARDInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the PCCARD Controller by calling the function - FMC_PCCARDInit(&FMC_PCCARDInitStructure); - - (#) Then enable the PCCARD Bank: - FMC_PCCARDCmd(ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank. - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FMC_PCCARDDeInit(void) -{ - /* Set the FMC_Bank4 registers to their reset values */ - FMC_Bank4->PCR4 = 0x00000018; - FMC_Bank4->SR4 = 0x00000000; - FMC_Bank4->PMEM4 = 0xFCFCFCFC; - FMC_Bank4->PATT4 = 0xFCFCFCFC; - FMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FMC PCCARD Bank according to the specified parameters - * in the FMC_PCCARDInitStruct. - * @param FMC_PCCARDInitStruct : pointer to a FMC_PCCARDInitTypeDef structure - * that contains the configuration information for the FMC PCCARD Bank. - * @retval None - */ -void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature)); - assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(FMC_PCCARDInitStruct->FMC_TARSetupTime)); - - assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); - assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); - - assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); - assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); - assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime)); - assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */ - FMC_Bank4->PCR4 = (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature | - FMC_NAND_MemoryDataWidth_16b | - (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) | - (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */ - FMC_Bank4->PMEM4 = (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | - (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | - (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| - (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */ - FMC_Bank4->PATT4 = (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | - (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | - (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| - (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */ - FMC_Bank4->PIO4 = (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime | - (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) | - (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)| - (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FMC_PCCARDInitStruct member with its default value. - * @param FMC_PCCARDInitStruct: pointer to a FMC_PCCARDInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FMC_PCCARDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; - FMC_PCCARDInitStruct->FMC_TCLRSetupTime = 0; - FMC_PCCARDInitStruct->FMC_TARSetupTime = 0; - FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; - FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; - FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; - FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; - FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; - FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; - FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; - FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; - FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime = 252; - FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime = 252; - FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime = 252; - FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime = 252; -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FMC_Bank4->PCR4 |= PCR_PBKEN_SET; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FMC_Bank4->PCR4 &= PCR_PBKEN_RESET; - } -} - -/** - * @} - */ - -/** @defgroup FMC_Group4 SDRAM Controller functions - * @brief SDRAM Controller functions - * -@verbatim - =============================================================================== - ##### SDRAM Controller functions ##### - =============================================================================== - - [..] The following sequence should be followed to configure the FMC to interface - with SDRAM memory connected to the SDRAM Bank 1 or SDRAM bank 2: - - (#) Enable the clock for the FMC and associated GPIOs using the following functions: - (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); - (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FMC pins configuration - (++) Connect the involved FMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); - (++) Configure these FMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FMC_SDRAMInitTypeDef structure, for example: - FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; - and fill the FMC_SDRAMInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the SDRAM Controller by calling the function - FMC_SDRAMInit(&FMC_SDRAMInitStructure); - - (#) Declare a FMC_SDRAMCommandTypeDef structure, for example: - FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; - and fill the FMC_SDRAMCommandStructure variable with the allowed values of - the structure member. - - (#) Configure the SDCMR register with the desired command parameters by calling - the function FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - (#) At this stage, the SDRAM memory is ready for any valid command. - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FMC SDRAM Banks registers to their default - * reset values. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @retval None - */ -void FMC_SDRAMDeInit(uint32_t FMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FMC_SDRAM_BANK(FMC_Bank)); - - FMC_Bank5_6->SDCR[FMC_Bank] = 0x000002D0; - FMC_Bank5_6->SDTR[FMC_Bank] = 0x0FFFFFFF; - FMC_Bank5_6->SDCMR = 0x00000000; - FMC_Bank5_6->SDRTR = 0x00000000; - FMC_Bank5_6->SDSR = 0x00000000; -} - -/** - * @brief Initializes the FMC SDRAM Banks according to the specified - * parameters in the FMC_SDRAMInitStruct. - * @param FMC_SDRAMInitStruct : pointer to a FMC_SDRAMInitTypeDef structure - * that contains the configuration information for the FMC SDRAM - * specified Banks. - * @retval None - */ -void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct) -{ - /* temporary registers */ - uint32_t tmpr1 = 0; - uint32_t tmpr2 = 0; - uint32_t tmpr3 = 0; - uint32_t tmpr4 = 0; - - /* Check the parameters */ - - /* Control parameters */ - assert_param(IS_FMC_SDRAM_BANK(FMC_SDRAMInitStruct->FMC_Bank)); - assert_param(IS_FMC_COLUMNBITS_NUMBER(FMC_SDRAMInitStruct->FMC_ColumnBitsNumber)); - assert_param(IS_FMC_ROWBITS_NUMBER(FMC_SDRAMInitStruct->FMC_RowBitsNumber)); - assert_param(IS_FMC_SDMEMORY_WIDTH(FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth)); - assert_param(IS_FMC_INTERNALBANK_NUMBER(FMC_SDRAMInitStruct->FMC_InternalBankNumber)); - assert_param(IS_FMC_CAS_LATENCY(FMC_SDRAMInitStruct->FMC_CASLatency)); - assert_param(IS_FMC_WRITE_PROTECTION(FMC_SDRAMInitStruct->FMC_WriteProtection)); - assert_param(IS_FMC_SDCLOCK_PERIOD(FMC_SDRAMInitStruct->FMC_SDClockPeriod)); - assert_param(IS_FMC_READ_BURST(FMC_SDRAMInitStruct->FMC_ReadBurst)); - assert_param(IS_FMC_READPIPE_DELAY(FMC_SDRAMInitStruct->FMC_ReadPipeDelay)); - - /* Timing parameters */ - assert_param(IS_FMC_LOADTOACTIVE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)); - assert_param(IS_FMC_EXITSELFREFRESH_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)); - assert_param(IS_FMC_SELFREFRESH_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)); - assert_param(IS_FMC_ROWCYCLE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)); - assert_param(IS_FMC_WRITE_RECOVERY_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)); - assert_param(IS_FMC_RP_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)); - assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)); - - /* SDRAM bank control register configuration */ - tmpr1 = (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber | - FMC_SDRAMInitStruct->FMC_RowBitsNumber | - FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth | - FMC_SDRAMInitStruct->FMC_InternalBankNumber | - FMC_SDRAMInitStruct->FMC_CASLatency | - FMC_SDRAMInitStruct->FMC_WriteProtection | - FMC_SDRAMInitStruct->FMC_SDClockPeriod | - FMC_SDRAMInitStruct->FMC_ReadBurst | - FMC_SDRAMInitStruct->FMC_ReadPipeDelay; - - if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM ) - { - FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1; - } - else /* SDCR2 "don't care" bits configuration */ - { - tmpr3 = (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod | - FMC_SDRAMInitStruct->FMC_ReadBurst | - FMC_SDRAMInitStruct->FMC_ReadPipeDelay; - - FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM] = tmpr3; - FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1; - } - /* SDRAM bank timing register configuration */ - if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM ) - { - tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24); - - FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2; - } - else /* SDTR "don't care bits configuration */ - { - tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16); - - tmpr4 = (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20); - - FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4; - FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2; - } - -} - -/** - * @brief Fills each FMC_SDRAMInitStruct member with its default value. - * @param FMC_SDRAMInitStruct: pointer to a FMC_SDRAMInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct) -{ - /* Reset SDRAM Init structure parameters values */ - FMC_SDRAMInitStruct->FMC_Bank = FMC_Bank1_SDRAM; - FMC_SDRAMInitStruct->FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; - FMC_SDRAMInitStruct->FMC_RowBitsNumber = FMC_RowBits_Number_11b; - FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; - FMC_SDRAMInitStruct->FMC_InternalBankNumber = FMC_InternalBank_Number_4; - FMC_SDRAMInitStruct->FMC_CASLatency = FMC_CAS_Latency_1; - FMC_SDRAMInitStruct->FMC_WriteProtection = FMC_Write_Protection_Enable; - FMC_SDRAMInitStruct->FMC_SDClockPeriod = FMC_SDClock_Disable; - FMC_SDRAMInitStruct->FMC_ReadBurst = FMC_Read_Burst_Disable; - FMC_SDRAMInitStruct->FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0; - - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay = 16; - -} - -/** - * @brief Configures the SDRAM memory command issued when the device is accessed. - * @param FMC_SDRAMCommandStruct: pointer to a FMC_SDRAMCommandTypeDef structure - * which will be configured. - * @retval None - */ -void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct) -{ - uint32_t tmpr = 0x0; - - /* check parameters */ - assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode)); - assert_param(IS_FMC_COMMAND_TARGET(FMC_SDRAMCommandStruct->FMC_CommandTarget)); - assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)); - assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)); - - tmpr = (uint32_t)(FMC_SDRAMCommandStruct->FMC_CommandMode | - FMC_SDRAMCommandStruct->FMC_CommandTarget | - (((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) | - ((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9)); - - FMC_Bank5_6->SDCMR = tmpr; - -} - - -/** - * @brief Returns the indicated FMC SDRAM bank mode status. - * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be - * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. - * @retval The FMC SDRAM bank mode status - */ -uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank) -{ - uint32_t tmpreg = 0; - - /* Check the parameter */ - assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank)); - - /* Get the busy flag status */ - if(SDRAM_Bank == FMC_Bank1_SDRAM) - { - tmpreg = (uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1); - } - else - { - tmpreg = ((uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2); - } - - /* Return the mode status */ - return tmpreg; -} - -/** - * @brief defines the SDRAM Memory Refresh rate. - * @param FMC_Count: specifies the Refresh timer count. - * @retval None - */ -void FMC_SetRefreshCount(uint32_t FMC_Count) -{ - /* check the parameters */ - assert_param(IS_FMC_REFRESH_COUNT(FMC_Count)); - - FMC_Bank5_6->SDRTR |= (FMC_Count<<1); - -} - -/** - * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. - * @param FMC_Number: specifies the auto Refresh number. - * @retval None - */ -void FMC_SetAutoRefresh_Number(uint32_t FMC_Number) -{ - /* check the parameters */ - assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number)); - - FMC_Bank5_6->SDCMR |= (FMC_Number << 5); -} - -/** - * @brief Enables or disables write protection to the specified FMC SDRAM Bank. - * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be - * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. - * @param NewState: new state of the write protection flag. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState) -{ - /* Check the parameter */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank)); - - if (NewState != DISABLE) - { - FMC_Bank5_6->SDCR[SDRAM_Bank] |= FMC_Write_Protection_Enable; - } - else - { - FMC_Bank5_6->SDCR[SDRAM_Bank] &= SDCR_WriteProtection_RESET; - } - -} - -/** - * @} - */ - -/** @defgroup FMC_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FMC interrupts. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @param FMC_IT: specifies the FMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FMC_IT_Level: Level edge detection interrupt. - * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. - * @arg FMC_IT_Refresh: Refresh error detection interrupt. - * @param NewState: new state of the specified FMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState) -{ - assert_param(IS_FMC_IT_BANK(FMC_Bank)); - assert_param(IS_FMC_IT(FMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FMC_Bank2 interrupts */ - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->SR2 |= FMC_IT; - } - /* Enable the selected FMC_Bank3 interrupts */ - else if (FMC_Bank == FMC_Bank3_NAND) - { - FMC_Bank3->SR3 |= FMC_IT; - } - /* Enable the selected FMC_Bank4 interrupts */ - else if (FMC_Bank == FMC_Bank4_PCCARD) - { - FMC_Bank4->SR4 |= FMC_IT; - } - /* Enable the selected FMC_Bank5_6 interrupt */ - else - { - /* Enables the interrupt if the refresh error flag is set */ - FMC_Bank5_6->SDRTR |= FMC_IT; - } - } - else - { - /* Disable the selected FMC_Bank2 interrupts */ - if(FMC_Bank == FMC_Bank2_NAND) - { - - FMC_Bank2->SR2 &= (uint32_t)~FMC_IT; - } - /* Disable the selected FMC_Bank3 interrupts */ - else if (FMC_Bank == FMC_Bank3_NAND) - { - FMC_Bank3->SR3 &= (uint32_t)~FMC_IT; - } - /* Disable the selected FMC_Bank4 interrupts */ - else if(FMC_Bank == FMC_Bank4_PCCARD) - { - FMC_Bank4->SR4 &= (uint32_t)~FMC_IT; - } - /* Disable the selected FMC_Bank5_6 interrupt */ - else - { - /* Disables the interrupt if the refresh error flag is not set */ - FMC_Bank5_6->SDRTR &= (uint32_t)~FMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FMC flag is set or not. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @arg FMC_Bank1_SDRAM | FMC_Bank2_SDRAM: FMC Bank1 or Bank2 SDRAM - * @param FMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FMC_FLAG_Level: Level detection Flag. - * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. - * @arg FMC_FLAG_FEMPT: Fifo empty Flag. - * @arg FMC_FLAG_Refresh: Refresh error Flag. - * @arg FMC_FLAG_Busy: Busy status Flag. - * @retval The new state of FMC_FLAG (SET or RESET). - */ -FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); - assert_param(IS_FMC_GET_FLAG(FMC_FLAG)); - - if(FMC_Bank == FMC_Bank2_NAND) - { - tmpsr = FMC_Bank2->SR2; - } - else if(FMC_Bank == FMC_Bank3_NAND) - { - tmpsr = FMC_Bank3->SR3; - } - else if(FMC_Bank == FMC_Bank4_PCCARD) - { - tmpsr = FMC_Bank4->SR4; - } - else - { - tmpsr = FMC_Bank5_6->SDSR; - } - - /* Get the flag status */ - if ((tmpsr & FMC_FLAG) != FMC_FLAG ) - { - bitstatus = RESET; - } - else - { - bitstatus = SET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FMC's pending flags. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @param FMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FMC_FLAG_Level: Level detection Flag. - * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. - * @arg FMC_FLAG_Refresh: Refresh error Flag. - * @retval None - */ -void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); - assert_param(IS_FMC_CLEAR_FLAG(FMC_FLAG)) ; - - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->SR2 &= (~FMC_FLAG); - } - else if(FMC_Bank == FMC_Bank3_NAND) - { - FMC_Bank3->SR3 &= (~FMC_FLAG); - } - else if(FMC_Bank == FMC_Bank4_PCCARD) - { - FMC_Bank4->SR4 &= (~FMC_FLAG); - } - /* FMC_Bank5_6 SDRAM*/ - else - { - FMC_Bank5_6->SDRTR &= (~FMC_FLAG); - } - -} - -/** - * @brief Checks whether the specified FMC interrupt has occurred or not. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @param FMC_IT: specifies the FMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FMC_IT_Level: Level edge detection interrupt. - * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. - * @arg FMC_IT_Refresh: Refresh error detection interrupt. - * @retval The new state of FMC_IT (SET or RESET). - */ -ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0; - uint32_t tmpsr2 = 0x0; - uint32_t itstatus = 0x0; - uint32_t itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FMC_IT_BANK(FMC_Bank)); - assert_param(IS_FMC_GET_IT(FMC_IT)); - - if(FMC_Bank == FMC_Bank2_NAND) - { - tmpsr = FMC_Bank2->SR2; - } - else if(FMC_Bank == FMC_Bank3_NAND) - { - tmpsr = FMC_Bank3->SR3; - } - else if(FMC_Bank == FMC_Bank4_PCCARD) - { - tmpsr = FMC_Bank4->SR4; - } - /* FMC_Bank5_6 SDRAM*/ - else - { - tmpsr = FMC_Bank5_6->SDRTR; - tmpsr2 = FMC_Bank5_6->SDSR; - } - - /* get the IT enable bit status*/ - itenable = tmpsr & FMC_IT; - - /* get the corresponding IT Flag status*/ - if((FMC_Bank == FMC_Bank1_SDRAM) || (FMC_Bank == FMC_Bank2_SDRAM)) - { - itstatus = tmpsr2 & FMC_SDSR_RE; - } - else - { - itstatus = tmpsr & (FMC_IT >> 3); - } - - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FMC's interrupt pending bits. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @param FMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FMC_IT_Level: Level edge detection interrupt. - * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. - * @arg FMC_IT_Refresh: Refresh error detection interrupt. - * @retval None - */ -void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FMC_IT_BANK(FMC_Bank)); - assert_param(IS_FMC_IT(FMC_IT)); - - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->SR2 &= ~(FMC_IT >> 3); - } - else if(FMC_Bank == FMC_Bank3_NAND) - { - FMC_Bank3->SR3 &= ~(FMC_IT >> 3); - } - else if(FMC_Bank == FMC_Bank4_PCCARD) - { - FMC_Bank4->SR4 &= ~(FMC_IT >> 3); - } - /* FMC_Bank5_6 SDRAM*/ - else - { - FMC_Bank5_6->SDRTR |= FMC_SDRTR_CRE; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_fmc.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the FMC peripheral: + * + Interface with SRAM, PSRAM, NOR and OneNAND memories + * + Interface with NAND memories + * + Interface with 16-bit PC Card compatible memories + * + Interface with SDRAM memories + * + Interrupts and flags management + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_fmc.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup FMC + * @brief FMC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +const FMC_NORSRAMTimingInitTypeDef FMC_DefaultTimingStruct = {0x0F, /* FMC_AddressSetupTime */ + 0x0F, /* FMC_AddressHoldTime */ + 0xFF, /* FMC_DataSetupTime */ + 0x0F, /* FMC_BusTurnAroundDuration */ + 0x0F, /* FMC_CLKDivision */ + 0x0F, /* FMC_DataLatency */ + FMC_AccessMode_A /* FMC_AccessMode */ + }; +/* --------------------- FMC registers bit mask ---------------------------- */ +/* FMC BCRx Mask */ +#define BCR_MBKEN_SET ((uint32_t)0x00000001) +#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_SET ((uint32_t)0x00000040) + +/* FMC PCRx Mask */ +#define PCR_PBKEN_SET ((uint32_t)0x00000004) +#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_SET ((uint32_t)0x00000040) +#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) +#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) + +/* FMC SDCRx write protection Mask*/ +#define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF) + +/* FMC SDCMR Mask*/ +#define SDCMR_CTB1_RESET ((uint32_t)0x003FFFEF) +#define SDCMR_CTB2_RESET ((uint32_t)0x003FFFF7) +#define SDCMR_CTB1_2_RESET ((uint32_t)0x003FFFE7) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FMC_Private_Functions + * @{ + */ + +/** @defgroup FMC_Group1 NOR/SRAM Controller functions + * @brief NOR/SRAM Controller functions + * +@verbatim + =============================================================================== + ##### NOR and SRAM Controller functions ##### + =============================================================================== + + [..] The following sequence should be followed to configure the FMC to interface + with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: + + (#) Enable the clock for the FMC and associated GPIOs using the following functions: + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) FMC pins configuration + (++) Connect the involved FMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); + (++) Configure these FMC pins in alternate function mode by calling the function + GPIO_Init(); + + (#) Declare a FMC_NORSRAMInitTypeDef structure, for example: + FMC_NORSRAMInitTypeDef FMC_NORSRAMInitStructure; + and fill the FMC_NORSRAMInitStructure variable with the allowed values of + the structure member. + + (#) Initialize the NOR/SRAM Controller by calling the function + FMC_NORSRAMInit(&FMC_NORSRAMInitStructure); + + (#) Then enable the NOR/SRAM Bank, for example: + FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE); + + (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the FMC NOR/SRAM Banks registers to their default + * reset values. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 + * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 + * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 + * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 + * @retval None + */ +void FMC_NORSRAMDeInit(uint32_t FMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); + + /* FMC_Bank1_NORSRAM1 */ + if(FMC_Bank == FMC_Bank1_NORSRAM1) + { + FMC_Bank1->BTCR[FMC_Bank] = 0x000030DB; + } + /* FMC_Bank1_NORSRAM2, FMC_Bank1_NORSRAM3 or FMC_Bank1_NORSRAM4 */ + else + { + FMC_Bank1->BTCR[FMC_Bank] = 0x000030D2; + } + FMC_Bank1->BTCR[FMC_Bank + 1] = 0x0FFFFFFF; + FMC_Bank1E->BWTR[FMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Initializes the FMC NOR/SRAM Banks according to the specified + * parameters in the FMC_NORSRAMInitStruct. + * @param FMC_NORSRAMInitStruct : pointer to a FMC_NORSRAMInitTypeDef structure + * that contains the configuration information for the FMC NOR/SRAM + * specified Banks. + * @retval None + */ +void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank)); + assert_param(IS_FMC_MUX(FMC_NORSRAMInitStruct->FMC_DataAddressMux)); + assert_param(IS_FMC_MEMORY(FMC_NORSRAMInitStruct->FMC_MemoryType)); + assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(FMC_NORSRAMInitStruct->FMC_MemoryDataWidth)); + assert_param(IS_FMC_BURSTMODE(FMC_NORSRAMInitStruct->FMC_BurstAccessMode)); + assert_param(IS_FMC_WAIT_POLARITY(FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity)); + assert_param(IS_FMC_WRAP_MODE(FMC_NORSRAMInitStruct->FMC_WrapMode)); + assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(FMC_NORSRAMInitStruct->FMC_WaitSignalActive)); + assert_param(IS_FMC_WRITE_OPERATION(FMC_NORSRAMInitStruct->FMC_WriteOperation)); + assert_param(IS_FMC_WAITE_SIGNAL(FMC_NORSRAMInitStruct->FMC_WaitSignal)); + assert_param(IS_FMC_EXTENDED_MODE(FMC_NORSRAMInitStruct->FMC_ExtendedMode)); + assert_param(IS_FMC_ASYNWAIT(FMC_NORSRAMInitStruct->FMC_AsynchronousWait)); + assert_param(IS_FMC_WRITE_BURST(FMC_NORSRAMInitStruct->FMC_WriteBurst)); + assert_param(IS_FMC_CONTINOUS_CLOCK(FMC_NORSRAMInitStruct->FMC_ContinousClock)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode)); + + /* NOR/SRAM Bank control register configuration */ + FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] = + (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux | + FMC_NORSRAMInitStruct->FMC_MemoryType | + FMC_NORSRAMInitStruct->FMC_MemoryDataWidth | + FMC_NORSRAMInitStruct->FMC_BurstAccessMode | + FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity | + FMC_NORSRAMInitStruct->FMC_WrapMode | + FMC_NORSRAMInitStruct->FMC_WaitSignalActive | + FMC_NORSRAMInitStruct->FMC_WriteOperation | + FMC_NORSRAMInitStruct->FMC_WaitSignal | + FMC_NORSRAMInitStruct->FMC_ExtendedMode | + FMC_NORSRAMInitStruct->FMC_AsynchronousWait | + FMC_NORSRAMInitStruct->FMC_WriteBurst | + FMC_NORSRAMInitStruct->FMC_ContinousClock; + + + if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR) + { + FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET; + } + + /* Configure Continuous clock feature when bank2..4 is used */ + if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1)) + { + tmpr = (uint32_t)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((uint32_t)0x0F) << 20)); + + FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_NORSRAMInitStruct->FMC_ContinousClock; + FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_BurstAccessMode_Enable; + FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (uint32_t)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20)); + } + + /* NOR/SRAM Bank timing register configuration */ + FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] = + (uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime | + (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) | + (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) | + (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) | + ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision) << 20) | + ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency) << 24) | + FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode; + + /* NOR/SRAM Bank timing register for write configuration, if extended mode is used */ + if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable) + { + assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime)); + assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode)); + + FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = + (uint32_t)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime | + (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )| + (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) | + ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) | + ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency) << 24) | + FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode; + } + else + { + FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 0x0FFFFFFF; + } + +} + +/** + * @brief Fills each FMC_NORSRAMInitStruct member with its default value. + * @param FMC_NORSRAMInitStruct: pointer to a FMC_NORSRAMInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FMC_NORSRAMInitStruct->FMC_Bank = FMC_Bank1_NORSRAM1; + FMC_NORSRAMInitStruct->FMC_DataAddressMux = FMC_DataAddressMux_Enable; + FMC_NORSRAMInitStruct->FMC_MemoryType = FMC_MemoryType_SRAM; + FMC_NORSRAMInitStruct->FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b; + FMC_NORSRAMInitStruct->FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; + FMC_NORSRAMInitStruct->FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; + FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; + FMC_NORSRAMInitStruct->FMC_WrapMode = FMC_WrapMode_Disable; + FMC_NORSRAMInitStruct->FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; + FMC_NORSRAMInitStruct->FMC_WriteOperation = FMC_WriteOperation_Enable; + FMC_NORSRAMInitStruct->FMC_WaitSignal = FMC_WaitSignal_Enable; + FMC_NORSRAMInitStruct->FMC_ExtendedMode = FMC_ExtendedMode_Disable; + FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable; + FMC_NORSRAMInitStruct->FMC_ContinousClock = FMC_CClock_SyncOnly; + + FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)&FMC_DefaultTimingStruct; + FMC_NORSRAMInitStruct->FMC_WriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)&FMC_DefaultTimingStruct; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 + * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 + * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 + * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FMC_Bank1->BTCR[FMC_Bank] |= BCR_MBKEN_SET; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FMC_Bank1->BTCR[FMC_Bank] &= BCR_MBKEN_RESET; + } +} +/** + * @} + */ + +/** @defgroup FMC_Group2 NAND Controller functions + * @brief NAND Controller functions + * +@verbatim + =============================================================================== + ##### NAND Controller functions ##### + =============================================================================== + + [..] The following sequence should be followed to configure the FMC to interface + with 8-bit or 16-bit NAND memory connected to the NAND Bank: + + (#) Enable the clock for the FMC and associated GPIOs using the following functions: + (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); + (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) FMC pins configuration + (++) Connect the involved FMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); + (++) Configure these FMC pins in alternate function mode by calling the function + GPIO_Init(); + + (#) Declare a FMC_NANDInitTypeDef structure, for example: + FMC_NANDInitTypeDef FMC_NANDInitStructure; + and fill the FMC_NANDInitStructure variable with the allowed values of + the structure member. + + (#) Initialize the NAND Controller by calling the function + FMC_NANDInit(&FMC_NANDInitStructure); + + (#) Then enable the NAND Bank, for example: + FMC_NANDCmd(FMC_Bank3_NAND, ENABLE); + + (#) At this stage you can read/write from/to the memory connected to the NAND Bank. + + [..] + (@) To enable the Error Correction Code (ECC), you have to use the function + FMC_NANDECCCmd(FMC_Bank3_NAND, ENABLE); + [..] + (@) and to get the current ECC value you have to use the function + ECCval = FMC_GetECC(FMC_Bank3_NAND); + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the FMC NAND Banks registers to their default reset values. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @retval None + */ +void FMC_NANDDeInit(uint32_t FMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FMC_NAND_BANK(FMC_Bank)); + + if(FMC_Bank == FMC_Bank2_NAND) + { + /* Set the FMC_Bank2 registers to their reset values */ + FMC_Bank2->PCR2 = 0x00000018; + FMC_Bank2->SR2 = 0x00000040; + FMC_Bank2->PMEM2 = 0xFCFCFCFC; + FMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FMC_Bank3_NAND */ + else + { + /* Set the FMC_Bank3 registers to their reset values */ + FMC_Bank3->PCR3 = 0x00000018; + FMC_Bank3->SR3 = 0x00000040; + FMC_Bank3->PMEM3 = 0xFCFCFCFC; + FMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Initializes the FMC NAND Banks according to the specified parameters + * in the FMC_NANDInitStruct. + * @param FMC_NANDInitStruct : pointer to a FMC_NANDInitTypeDef structure that + * contains the configuration information for the FMC NAND specified Banks. + * @retval None + */ +void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank)); + assert_param(IS_FMC_WAIT_FEATURE(FMC_NANDInitStruct->FMC_Waitfeature)); + assert_param(IS_FMC_NAND_MEMORY_WIDTH(FMC_NANDInitStruct->FMC_MemoryDataWidth)); + assert_param(IS_FMC_ECC_STATE(FMC_NANDInitStruct->FMC_ECC)); + assert_param(IS_FMC_ECCPAGE_SIZE(FMC_NANDInitStruct->FMC_ECCPageSize)); + assert_param(IS_FMC_TCLR_TIME(FMC_NANDInitStruct->FMC_TCLRSetupTime)); + assert_param(IS_FMC_TAR_TIME(FMC_NANDInitStruct->FMC_TARSetupTime)); + assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); + assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); + assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); + assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); + + /* Set the tmppcr value according to FMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature | + PCR_MEMORYTYPE_NAND | + FMC_NANDInitStruct->FMC_MemoryDataWidth | + FMC_NANDInitStruct->FMC_ECC | + FMC_NANDInitStruct->FMC_ECCPageSize | + (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )| + (FMC_NANDInitStruct->FMC_TARSetupTime << 13); + + /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | + (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | + (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| + (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | + (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | + (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| + (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); + + if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND) + { + /* FMC_Bank2_NAND registers configuration */ + FMC_Bank2->PCR2 = tmppcr; + FMC_Bank2->PMEM2 = tmppmem; + FMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FMC_Bank3_NAND registers configuration */ + FMC_Bank3->PCR3 = tmppcr; + FMC_Bank3->PMEM3 = tmppmem; + FMC_Bank3->PATT3 = tmppatt; + } +} + + +/** + * @brief Fills each FMC_NANDInitStruct member with its default value. + * @param FMC_NANDInitStruct: pointer to a FMC_NANDInitTypeDef structure which + * will be initialized. + * @retval None + */ +void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FMC_NANDInitStruct->FMC_Bank = FMC_Bank2_NAND; + FMC_NANDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; + FMC_NANDInitStruct->FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_16b; + FMC_NANDInitStruct->FMC_ECC = FMC_ECC_Disable; + FMC_NANDInitStruct->FMC_ECCPageSize = FMC_ECCPageSize_256Bytes; + FMC_NANDInitStruct->FMC_TCLRSetupTime = 0x0; + FMC_NANDInitStruct->FMC_TARSetupTime = 0x0; + FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; + FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; + FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; + FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; + FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; + FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; + FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; + FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FMC_NAND_BANK(FMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->PCR2 |= PCR_PBKEN_SET; + } + else + { + FMC_Bank3->PCR3 |= PCR_PBKEN_SET; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->PCR2 &= PCR_PBKEN_RESET; + } + else + { + FMC_Bank3->PCR3 &= PCR_PBKEN_RESET; + } + } +} +/** + * @brief Enables or disables the FMC NAND ECC feature. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @param NewState: new state of the FMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FMC_NAND_BANK(FMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->PCR2 |= PCR_ECCEN_SET; + } + else + { + FMC_Bank3->PCR3 |= PCR_ECCEN_SET; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->PCR2 &= PCR_ECCEN_RESET; + } + else + { + FMC_Bank3->PCR3 &= PCR_ECCEN_RESET; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FMC_GetECC(uint32_t FMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FMC_Bank == FMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} +/** + * @} + */ + +/** @defgroup FMC_Group3 PCCARD Controller functions + * @brief PCCARD Controller functions + * +@verbatim + =============================================================================== + ##### PCCARD Controller functions ##### + =============================================================================== + + [..] he following sequence should be followed to configure the FMC to interface + with 16-bit PC Card compatible memory connected to the PCCARD Bank: + + (#) Enable the clock for the FMC and associated GPIOs using the following functions: + (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); + (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) FMC pins configuration + (++) Connect the involved FMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); + (++) Configure these FMC pins in alternate function mode by calling the function + GPIO_Init(); + + (#) Declare a FMC_PCCARDInitTypeDef structure, for example: + FMC_PCCARDInitTypeDef FMC_PCCARDInitStructure; + and fill the FMC_PCCARDInitStructure variable with the allowed values of + the structure member. + + (#) Initialize the PCCARD Controller by calling the function + FMC_PCCARDInit(&FMC_PCCARDInitStructure); + + (#) Then enable the PCCARD Bank: + FMC_PCCARDCmd(ENABLE); + + (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank. + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the FMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FMC_PCCARDDeInit(void) +{ + /* Set the FMC_Bank4 registers to their reset values */ + FMC_Bank4->PCR4 = 0x00000018; + FMC_Bank4->SR4 = 0x00000000; + FMC_Bank4->PMEM4 = 0xFCFCFCFC; + FMC_Bank4->PATT4 = 0xFCFCFCFC; + FMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FMC PCCARD Bank according to the specified parameters + * in the FMC_PCCARDInitStruct. + * @param FMC_PCCARDInitStruct : pointer to a FMC_PCCARDInitTypeDef structure + * that contains the configuration information for the FMC PCCARD Bank. + * @retval None + */ +void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature)); + assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime)); + assert_param(IS_FMC_TAR_TIME(FMC_PCCARDInitStruct->FMC_TARSetupTime)); + + assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); + assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); + + assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); + assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); + assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime)); + assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */ + FMC_Bank4->PCR4 = (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature | + FMC_NAND_MemoryDataWidth_16b | + (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) | + (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */ + FMC_Bank4->PMEM4 = (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | + (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | + (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| + (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */ + FMC_Bank4->PATT4 = (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | + (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | + (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| + (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */ + FMC_Bank4->PIO4 = (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime | + (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) | + (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)| + (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FMC_PCCARDInitStruct member with its default value. + * @param FMC_PCCARDInitStruct: pointer to a FMC_PCCARDInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FMC_PCCARDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; + FMC_PCCARDInitStruct->FMC_TCLRSetupTime = 0; + FMC_PCCARDInitStruct->FMC_TARSetupTime = 0; + FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; + FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; + FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; + FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; + FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; + FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; + FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; + FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; + FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime = 252; + FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime = 252; + FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime = 252; + FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime = 252; +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FMC_Bank4->PCR4 |= PCR_PBKEN_SET; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FMC_Bank4->PCR4 &= PCR_PBKEN_RESET; + } +} + +/** + * @} + */ + +/** @defgroup FMC_Group4 SDRAM Controller functions + * @brief SDRAM Controller functions + * +@verbatim + =============================================================================== + ##### SDRAM Controller functions ##### + =============================================================================== + + [..] The following sequence should be followed to configure the FMC to interface + with SDRAM memory connected to the SDRAM Bank 1 or SDRAM bank 2: + + (#) Enable the clock for the FMC and associated GPIOs using the following functions: + (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); + (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) FMC pins configuration + (++) Connect the involved FMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); + (++) Configure these FMC pins in alternate function mode by calling the function + GPIO_Init(); + + (#) Declare a FMC_SDRAMInitTypeDef structure, for example: + FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; + and fill the FMC_SDRAMInitStructure variable with the allowed values of + the structure member. + + (#) Initialize the SDRAM Controller by calling the function + FMC_SDRAMInit(&FMC_SDRAMInitStructure); + + (#) Declare a FMC_SDRAMCommandTypeDef structure, for example: + FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; + and fill the FMC_SDRAMCommandStructure variable with the allowed values of + the structure member. + + (#) Configure the SDCMR register with the desired command parameters by calling + the function FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + + (#) At this stage, the SDRAM memory is ready for any valid command. + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the FMC SDRAM Banks registers to their default + * reset values. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @retval None + */ +void FMC_SDRAMDeInit(uint32_t FMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FMC_SDRAM_BANK(FMC_Bank)); + + FMC_Bank5_6->SDCR[FMC_Bank] = 0x000002D0; + FMC_Bank5_6->SDTR[FMC_Bank] = 0x0FFFFFFF; + FMC_Bank5_6->SDCMR = 0x00000000; + FMC_Bank5_6->SDRTR = 0x00000000; + FMC_Bank5_6->SDSR = 0x00000000; +} + +/** + * @brief Initializes the FMC SDRAM Banks according to the specified + * parameters in the FMC_SDRAMInitStruct. + * @param FMC_SDRAMInitStruct : pointer to a FMC_SDRAMInitTypeDef structure + * that contains the configuration information for the FMC SDRAM + * specified Banks. + * @retval None + */ +void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct) +{ + /* temporary registers */ + uint32_t tmpr1 = 0; + uint32_t tmpr2 = 0; + uint32_t tmpr3 = 0; + uint32_t tmpr4 = 0; + + /* Check the parameters */ + + /* Control parameters */ + assert_param(IS_FMC_SDRAM_BANK(FMC_SDRAMInitStruct->FMC_Bank)); + assert_param(IS_FMC_COLUMNBITS_NUMBER(FMC_SDRAMInitStruct->FMC_ColumnBitsNumber)); + assert_param(IS_FMC_ROWBITS_NUMBER(FMC_SDRAMInitStruct->FMC_RowBitsNumber)); + assert_param(IS_FMC_SDMEMORY_WIDTH(FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth)); + assert_param(IS_FMC_INTERNALBANK_NUMBER(FMC_SDRAMInitStruct->FMC_InternalBankNumber)); + assert_param(IS_FMC_CAS_LATENCY(FMC_SDRAMInitStruct->FMC_CASLatency)); + assert_param(IS_FMC_WRITE_PROTECTION(FMC_SDRAMInitStruct->FMC_WriteProtection)); + assert_param(IS_FMC_SDCLOCK_PERIOD(FMC_SDRAMInitStruct->FMC_SDClockPeriod)); + assert_param(IS_FMC_READ_BURST(FMC_SDRAMInitStruct->FMC_ReadBurst)); + assert_param(IS_FMC_READPIPE_DELAY(FMC_SDRAMInitStruct->FMC_ReadPipeDelay)); + + /* Timing parameters */ + assert_param(IS_FMC_LOADTOACTIVE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)); + assert_param(IS_FMC_EXITSELFREFRESH_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)); + assert_param(IS_FMC_SELFREFRESH_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)); + assert_param(IS_FMC_ROWCYCLE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)); + assert_param(IS_FMC_WRITE_RECOVERY_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)); + assert_param(IS_FMC_RP_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)); + assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)); + + /* SDRAM bank control register configuration */ + tmpr1 = (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber | + FMC_SDRAMInitStruct->FMC_RowBitsNumber | + FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth | + FMC_SDRAMInitStruct->FMC_InternalBankNumber | + FMC_SDRAMInitStruct->FMC_CASLatency | + FMC_SDRAMInitStruct->FMC_WriteProtection | + FMC_SDRAMInitStruct->FMC_SDClockPeriod | + FMC_SDRAMInitStruct->FMC_ReadBurst | + FMC_SDRAMInitStruct->FMC_ReadPipeDelay; + + if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM ) + { + FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1; + } + else /* SDCR2 "don't care" bits configuration */ + { + tmpr3 = (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod | + FMC_SDRAMInitStruct->FMC_ReadBurst | + FMC_SDRAMInitStruct->FMC_ReadPipeDelay; + + FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM] = tmpr3; + FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1; + } + /* SDRAM bank timing register configuration */ + if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM ) + { + tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24); + + FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2; + } + else /* SDTR "don't care bits configuration */ + { + tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16); + + tmpr4 = (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20); + + FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4; + FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2; + } + +} + +/** + * @brief Fills each FMC_SDRAMInitStruct member with its default value. + * @param FMC_SDRAMInitStruct: pointer to a FMC_SDRAMInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct) +{ + /* Reset SDRAM Init structure parameters values */ + FMC_SDRAMInitStruct->FMC_Bank = FMC_Bank1_SDRAM; + FMC_SDRAMInitStruct->FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; + FMC_SDRAMInitStruct->FMC_RowBitsNumber = FMC_RowBits_Number_11b; + FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; + FMC_SDRAMInitStruct->FMC_InternalBankNumber = FMC_InternalBank_Number_4; + FMC_SDRAMInitStruct->FMC_CASLatency = FMC_CAS_Latency_1; + FMC_SDRAMInitStruct->FMC_WriteProtection = FMC_Write_Protection_Enable; + FMC_SDRAMInitStruct->FMC_SDClockPeriod = FMC_SDClock_Disable; + FMC_SDRAMInitStruct->FMC_ReadBurst = FMC_Read_Burst_Disable; + FMC_SDRAMInitStruct->FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0; + + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay = 16; + +} + +/** + * @brief Configures the SDRAM memory command issued when the device is accessed. + * @param FMC_SDRAMCommandStruct: pointer to a FMC_SDRAMCommandTypeDef structure + * which will be configured. + * @retval None + */ +void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct) +{ + uint32_t tmpr = 0x0; + + /* check parameters */ + assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode)); + assert_param(IS_FMC_COMMAND_TARGET(FMC_SDRAMCommandStruct->FMC_CommandTarget)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)); + assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)); + + tmpr = (uint32_t)(FMC_SDRAMCommandStruct->FMC_CommandMode | + FMC_SDRAMCommandStruct->FMC_CommandTarget | + (((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) | + ((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9)); + + FMC_Bank5_6->SDCMR = tmpr; + +} + + +/** + * @brief Returns the indicated FMC SDRAM bank mode status. + * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be + * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. + * @retval The FMC SDRAM bank mode status + */ +uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank) +{ + uint32_t tmpreg = 0; + + /* Check the parameter */ + assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank)); + + /* Get the busy flag status */ + if(SDRAM_Bank == FMC_Bank1_SDRAM) + { + tmpreg = (uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1); + } + else + { + tmpreg = ((uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2); + } + + /* Return the mode status */ + return tmpreg; +} + +/** + * @brief defines the SDRAM Memory Refresh rate. + * @param FMC_Count: specifies the Refresh timer count. + * @retval None + */ +void FMC_SetRefreshCount(uint32_t FMC_Count) +{ + /* check the parameters */ + assert_param(IS_FMC_REFRESH_COUNT(FMC_Count)); + + FMC_Bank5_6->SDRTR |= (FMC_Count<<1); + +} + +/** + * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. + * @param FMC_Number: specifies the auto Refresh number. + * @retval None + */ +void FMC_SetAutoRefresh_Number(uint32_t FMC_Number) +{ + /* check the parameters */ + assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number)); + + FMC_Bank5_6->SDCMR |= (FMC_Number << 5); +} + +/** + * @brief Enables or disables write protection to the specified FMC SDRAM Bank. + * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be + * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. + * @param NewState: new state of the write protection flag. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState) +{ + /* Check the parameter */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank)); + + if (NewState != DISABLE) + { + FMC_Bank5_6->SDCR[SDRAM_Bank] |= FMC_Write_Protection_Enable; + } + else + { + FMC_Bank5_6->SDCR[SDRAM_Bank] &= SDCR_WriteProtection_RESET; + } + +} + +/** + * @} + */ + +/** @defgroup FMC_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified FMC interrupts. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @param FMC_IT: specifies the FMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FMC_IT_Level: Level edge detection interrupt. + * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. + * @arg FMC_IT_Refresh: Refresh error detection interrupt. + * @param NewState: new state of the specified FMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState) +{ + assert_param(IS_FMC_IT_BANK(FMC_Bank)); + assert_param(IS_FMC_IT(FMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FMC_Bank2 interrupts */ + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->SR2 |= FMC_IT; + } + /* Enable the selected FMC_Bank3 interrupts */ + else if (FMC_Bank == FMC_Bank3_NAND) + { + FMC_Bank3->SR3 |= FMC_IT; + } + /* Enable the selected FMC_Bank4 interrupts */ + else if (FMC_Bank == FMC_Bank4_PCCARD) + { + FMC_Bank4->SR4 |= FMC_IT; + } + /* Enable the selected FMC_Bank5_6 interrupt */ + else + { + /* Enables the interrupt if the refresh error flag is set */ + FMC_Bank5_6->SDRTR |= FMC_IT; + } + } + else + { + /* Disable the selected FMC_Bank2 interrupts */ + if(FMC_Bank == FMC_Bank2_NAND) + { + + FMC_Bank2->SR2 &= (uint32_t)~FMC_IT; + } + /* Disable the selected FMC_Bank3 interrupts */ + else if (FMC_Bank == FMC_Bank3_NAND) + { + FMC_Bank3->SR3 &= (uint32_t)~FMC_IT; + } + /* Disable the selected FMC_Bank4 interrupts */ + else if(FMC_Bank == FMC_Bank4_PCCARD) + { + FMC_Bank4->SR4 &= (uint32_t)~FMC_IT; + } + /* Disable the selected FMC_Bank5_6 interrupt */ + else + { + /* Disables the interrupt if the refresh error flag is not set */ + FMC_Bank5_6->SDRTR &= (uint32_t)~FMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FMC flag is set or not. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @arg FMC_Bank1_SDRAM | FMC_Bank2_SDRAM: FMC Bank1 or Bank2 SDRAM + * @param FMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. + * @arg FMC_FLAG_Level: Level detection Flag. + * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. + * @arg FMC_FLAG_FEMPT: Fifo empty Flag. + * @arg FMC_FLAG_Refresh: Refresh error Flag. + * @arg FMC_FLAG_Busy: Busy status Flag. + * @retval The new state of FMC_FLAG (SET or RESET). + */ +FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); + assert_param(IS_FMC_GET_FLAG(FMC_FLAG)); + + if(FMC_Bank == FMC_Bank2_NAND) + { + tmpsr = FMC_Bank2->SR2; + } + else if(FMC_Bank == FMC_Bank3_NAND) + { + tmpsr = FMC_Bank3->SR3; + } + else if(FMC_Bank == FMC_Bank4_PCCARD) + { + tmpsr = FMC_Bank4->SR4; + } + else + { + tmpsr = FMC_Bank5_6->SDSR; + } + + /* Get the flag status */ + if ((tmpsr & FMC_FLAG) != FMC_FLAG ) + { + bitstatus = RESET; + } + else + { + bitstatus = SET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FMC's pending flags. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @param FMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. + * @arg FMC_FLAG_Level: Level detection Flag. + * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. + * @arg FMC_FLAG_Refresh: Refresh error Flag. + * @retval None + */ +void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); + assert_param(IS_FMC_CLEAR_FLAG(FMC_FLAG)) ; + + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->SR2 &= (~FMC_FLAG); + } + else if(FMC_Bank == FMC_Bank3_NAND) + { + FMC_Bank3->SR3 &= (~FMC_FLAG); + } + else if(FMC_Bank == FMC_Bank4_PCCARD) + { + FMC_Bank4->SR4 &= (~FMC_FLAG); + } + /* FMC_Bank5_6 SDRAM*/ + else + { + FMC_Bank5_6->SDRTR &= (~FMC_FLAG); + } + +} + +/** + * @brief Checks whether the specified FMC interrupt has occurred or not. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @param FMC_IT: specifies the FMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FMC_IT_Level: Level edge detection interrupt. + * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. + * @arg FMC_IT_Refresh: Refresh error detection interrupt. + * @retval The new state of FMC_IT (SET or RESET). + */ +ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0; + uint32_t tmpsr2 = 0x0; + uint32_t itstatus = 0x0; + uint32_t itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FMC_IT_BANK(FMC_Bank)); + assert_param(IS_FMC_GET_IT(FMC_IT)); + + if(FMC_Bank == FMC_Bank2_NAND) + { + tmpsr = FMC_Bank2->SR2; + } + else if(FMC_Bank == FMC_Bank3_NAND) + { + tmpsr = FMC_Bank3->SR3; + } + else if(FMC_Bank == FMC_Bank4_PCCARD) + { + tmpsr = FMC_Bank4->SR4; + } + /* FMC_Bank5_6 SDRAM*/ + else + { + tmpsr = FMC_Bank5_6->SDRTR; + tmpsr2 = FMC_Bank5_6->SDSR; + } + + /* get the IT enable bit status*/ + itenable = tmpsr & FMC_IT; + + /* get the corresponding IT Flag status*/ + if((FMC_Bank == FMC_Bank1_SDRAM) || (FMC_Bank == FMC_Bank2_SDRAM)) + { + itstatus = tmpsr2 & FMC_SDSR_RE; + } + else + { + itstatus = tmpsr & (FMC_IT >> 3); + } + + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FMC's interrupt pending bits. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @param FMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FMC_IT_Level: Level edge detection interrupt. + * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. + * @arg FMC_IT_Refresh: Refresh error detection interrupt. + * @retval None + */ +void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FMC_IT_BANK(FMC_Bank)); + assert_param(IS_FMC_IT(FMC_IT)); + + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->SR2 &= ~(FMC_IT >> 3); + } + else if(FMC_Bank == FMC_Bank3_NAND) + { + FMC_Bank3->SR3 &= ~(FMC_IT >> 3); + } + else if(FMC_Bank == FMC_Bank4_PCCARD) + { + FMC_Bank4->SR4 &= ~(FMC_IT >> 3); + } + /* FMC_Bank5_6 SDRAM*/ + else + { + FMC_Bank5_6->SDRTR |= FMC_SDRTR_CRE; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c index a5ca45497..38c23a584 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c @@ -1,985 +1,985 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fsmc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the FSMC peripheral: - * + Interface with SRAM, PSRAM, NOR and OneNAND memories - * + Interface with NAND memories - * + Interface with 16-bit PC Card compatible memories - * + Interrupts and flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_fsmc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -const FSMC_NORSRAMTimingInitTypeDef FSMC_DefaultTimingStruct = {0x0F, /* FSMC_AddressSetupTime */ - 0x0F, /* FSMC_AddressHoldTime */ - 0xFF, /* FSMC_DataSetupTime */ - 0x0F, /* FSMC_BusTurnAroundDuration */ - 0x0F, /* FSMC_CLKDivision */ - 0x0F, /* FSMC_DataLatency */ - FSMC_AccessMode_A /* FSMC_AccessMode */ - }; -/* Private define ------------------------------------------------------------*/ - -/* --------------------- FSMC registers bit mask ---------------------------- */ -/* FSMC BCRx Mask */ -#define BCR_MBKEN_SET ((uint32_t)0x00000001) -#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_SET ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_SET ((uint32_t)0x00000004) -#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_SET ((uint32_t)0x00000040) -#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) -#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** @defgroup FSMC_Group1 NOR/SRAM Controller functions - * @brief NOR/SRAM Controller functions - * -@verbatim - =============================================================================== - ##### NOR and SRAM Controller functions ##### - =============================================================================== - - [..] The following sequence should be followed to configure the FSMC to interface - with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: - - (#) Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FSMC pins configuration - (++) Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - (++) Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example: - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - and fill the FSMC_NORSRAMInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the NOR/SRAM Controller by calling the function - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - (#) Then enable the NOR/SRAM Bank, for example: - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure - * that contains the configuration information for the FSMC NOR/SRAM - * specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Bank1 NOR/SRAM control register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; - } - /* Bank1 NOR/SRAM timing register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group2 NAND Controller functions - * @brief NAND Controller functions - * -@verbatim - =============================================================================== - ##### NAND Controller functions ##### - =============================================================================== - - [..] The following sequence should be followed to configure the FSMC to interface - with 8-bit or 16-bit NAND memory connected to the NAND Bank: - - (#) Enable the clock for the FSMC and associated GPIOs using the following functions: - (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FSMC pins configuration - (++) Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - (++) Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FSMC_NANDInitTypeDef structure, for example: - FSMC_NANDInitTypeDef FSMC_NANDInitStructure; - and fill the FSMC_NANDInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the NAND Controller by calling the function - FSMC_NANDInit(&FSMC_NANDInitStructure); - - (#) Then enable the NAND Bank, for example: - FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the NAND Bank. - - [..] - (@) To enable the Error Correction Code (ECC), you have to use the function - FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); - [..] - (@) and to get the current ECC value you have to use the function - ECCval = FSMC_GetECC(FSMC_Bank3_NAND); - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified parameters - * in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that - * contains the configuration information for the FSMC NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MEMORYTYPE_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which - * will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_SET; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET; - } - } -} -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_SET; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} -/** - * @} - */ - -/** @defgroup FSMC_Group3 PCCARD Controller functions - * @brief PCCARD Controller functions - * -@verbatim - =============================================================================== - ##### PCCARD Controller functions ##### - =============================================================================== - - [..] he following sequence should be followed to configure the FSMC to interface - with 16-bit PC Card compatible memory connected to the PCCARD Bank: - - (#) Enable the clock for the FSMC and associated GPIOs using the following functions: - (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FSMC pins configuration - (++) Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - (++) Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FSMC_PCCARDInitTypeDef structure, for example: - FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; - and fill the FSMC_PCCARDInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the PCCARD Controller by calling the function - FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); - - (#) Then enable the PCCARD Bank: - FSMC_PCCARDCmd(ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank. - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified parameters - * in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure - * that contains the configuration information for the FSMC PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_SET; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMC's pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMC's interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_fsmc.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the FSMC peripheral: + * + Interface with SRAM, PSRAM, NOR and OneNAND memories + * + Interface with NAND memories + * + Interface with 16-bit PC Card compatible memories + * + Interrupts and flags management + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_fsmc.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup FSMC + * @brief FSMC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +const FSMC_NORSRAMTimingInitTypeDef FSMC_DefaultTimingStruct = {0x0F, /* FSMC_AddressSetupTime */ + 0x0F, /* FSMC_AddressHoldTime */ + 0xFF, /* FSMC_DataSetupTime */ + 0x0F, /* FSMC_BusTurnAroundDuration */ + 0x0F, /* FSMC_CLKDivision */ + 0x0F, /* FSMC_DataLatency */ + FSMC_AccessMode_A /* FSMC_AccessMode */ + }; +/* Private define ------------------------------------------------------------*/ + +/* --------------------- FSMC registers bit mask ---------------------------- */ +/* FSMC BCRx Mask */ +#define BCR_MBKEN_SET ((uint32_t)0x00000001) +#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_SET ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_SET ((uint32_t)0x00000004) +#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_SET ((uint32_t)0x00000040) +#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) +#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FSMC_Private_Functions + * @{ + */ + +/** @defgroup FSMC_Group1 NOR/SRAM Controller functions + * @brief NOR/SRAM Controller functions + * +@verbatim + =============================================================================== + ##### NOR and SRAM Controller functions ##### + =============================================================================== + + [..] The following sequence should be followed to configure the FSMC to interface + with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: + + (#) Enable the clock for the FSMC and associated GPIOs using the following functions: + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) FSMC pins configuration + (++) Connect the involved FSMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); + (++) Configure these FSMC pins in alternate function mode by calling the function + GPIO_Init(); + + (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example: + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + and fill the FSMC_NORSRAMInitStructure variable with the allowed values of + the structure member. + + (#) Initialize the NOR/SRAM Controller by calling the function + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + (#) Then enable the NOR/SRAM Bank, for example: + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); + + (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @retval None + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure + * that contains the configuration information for the FSMC NOR/SRAM + * specified Banks. + * @retval None + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; + } + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/** + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; + } +} +/** + * @} + */ + +/** @defgroup FSMC_Group2 NAND Controller functions + * @brief NAND Controller functions + * +@verbatim + =============================================================================== + ##### NAND Controller functions ##### + =============================================================================== + + [..] The following sequence should be followed to configure the FSMC to interface + with 8-bit or 16-bit NAND memory connected to the NAND Bank: + + (#) Enable the clock for the FSMC and associated GPIOs using the following functions: + (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) FSMC pins configuration + (++) Connect the involved FSMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); + (++) Configure these FSMC pins in alternate function mode by calling the function + GPIO_Init(); + + (#) Declare a FSMC_NANDInitTypeDef structure, for example: + FSMC_NANDInitTypeDef FSMC_NANDInitStructure; + and fill the FSMC_NANDInitStructure variable with the allowed values of + the structure member. + + (#) Initialize the NAND Controller by calling the function + FSMC_NANDInit(&FSMC_NANDInitStructure); + + (#) Then enable the NAND Bank, for example: + FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); + + (#) At this stage you can read/write from/to the memory connected to the NAND Bank. + + [..] + (@) To enable the Error Correction Code (ECC), you have to use the function + FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); + [..] + (@) and to get the current ECC value you have to use the function + ECCval = FSMC_GetECC(FSMC_Bank3_NAND); + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the FSMC NAND Banks registers to their default reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval None + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Initializes the FSMC NAND Banks according to the specified parameters + * in the FSMC_NANDInitStruct. + * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that + * contains the configuration information for the FSMC NAND specified Banks. + * @retval None + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MEMORYTYPE_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + + +/** + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which + * will be initialized. + * @retval None + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_SET; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_SET; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET; + } + } +} +/** + * @brief Enables or disables the FSMC NAND ECC feature. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_SET; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_SET; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} +/** + * @} + */ + +/** @defgroup FSMC_Group3 PCCARD Controller functions + * @brief PCCARD Controller functions + * +@verbatim + =============================================================================== + ##### PCCARD Controller functions ##### + =============================================================================== + + [..] he following sequence should be followed to configure the FSMC to interface + with 16-bit PC Card compatible memory connected to the PCCARD Bank: + + (#) Enable the clock for the FSMC and associated GPIOs using the following functions: + (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) FSMC pins configuration + (++) Connect the involved FSMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); + (++) Configure these FSMC pins in alternate function mode by calling the function + GPIO_Init(); + + (#) Declare a FSMC_PCCARDInitTypeDef structure, for example: + FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; + and fill the FSMC_PCCARDInitStructure variable with the allowed values of + the structure member. + + (#) Initialize the PCCARD Controller by calling the function + FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); + + (#) Then enable the PCCARD Bank: + FSMC_PCCARDCmd(ENABLE); + + (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank. + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the FSMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FSMC PCCARD Bank according to the specified parameters + * in the FSMC_PCCARDInitStruct. + * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure + * that contains the configuration information for the FSMC PCCARD Bank. + * @retval None + */ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FSMC_PCCARDInitStruct member with its default value. + * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_SET; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET; + } +} +/** + * @} + */ + +/** @defgroup FSMC_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified FSMC interrupts. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @param NewState: new state of the specified FSMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FSMC flag is set or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. + * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. + * @retval The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FSMC's pending flags. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. + * @retval None + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/** + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FSMC's interrupt pending bits. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval None + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c index ff3ac83aa..0523e5051 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c @@ -1,611 +1,611 @@ -/** - ****************************************************************************** - * @file stm32f4xx_gpio.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * + Initialization and Configuration - * + GPIO Read and Write - * + GPIO Alternate functions configuration - * -@verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) Configure the GPIO pin(s) using GPIO_Init() - Four possible configuration are available for each pin: - (++) Input: Floating, Pull-up, Pull-down. - (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) - Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed - is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz. - (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open - Drain (Pull-up, Pull-down or no Pull). - (++) Analog: required mode when a pin is to be used as ADC channel or DAC - output. - - (#) Peripherals alternate function: - (++) For ADC and DAC, configure the desired pin in analog mode using - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; - (+++) For other peripherals (TIM, USART...): - (+++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function - (+++) Configure the desired pin in alternate function mode using - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (+++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (+++) Call GPIO_Init() function - - (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - - (#) To set/reset the level of a pin configured in output mode use - GPIO_SetBits()/GPIO_ResetBits() - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_gpio.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** @defgroup GPIO_Group1 Initialization and Configuration - * @brief Initialization and Configuration - * -@verbatim - =============================================================================== - ##### Initialization and Configuration ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); - } - else if (GPIOx == GPIOG) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); - } - else if (GPIOx == GPIOH) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); - } - - else if (GPIOx == GPIOI) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); - } - else if (GPIOx == GPIOJ) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE); - } - else - { - if (GPIOx == GPIOK) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE); - } - } -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - /* ------------------------- Configure the port pins ---------------- */ - /*-- GPIO Mode Configuration --*/ - for (pinpos = 0x00; pinpos < 0x10; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); - GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); - - if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) - { - /* Check Speed mode parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - - /* Speed mode configuration */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); - GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); - - /* Check Output mode parameters */ - assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); - - /* Output mode configuration*/ - GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; - GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); - } - - /* Pull-up Pull down resistor configuration*/ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); - GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); - } - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group2 GPIO Read and Write - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - ##### GPIO Read and Write ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRL = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRH = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRRL = GPIO_Pin; - } - else - { - GPIOx->BSRRH = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Toggles the specified GPIO pins.. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: Specifies the pins to be toggled. - * @retval None - */ -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function - * @brief GPIO Alternate functions configuration function - * -@verbatim - =============================================================================== - ##### GPIO Alternate functions configuration function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_PinSource: specifies the pin for the Alternate function. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @param GPIO_AFSelection: selects the pin to used as Alternate function. - * This parameter can be one of the following values: - * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) - * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) - * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) - * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) - * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) - * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 - * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 - * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 - * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 - * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 - * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 - * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 - * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 - * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 - * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 - * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 - * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 - * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 - * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 - * @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5 - * @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5 - * @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5 - * @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices. - * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 - * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7 - * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 - * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 - * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 - * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 - * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 - * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 - * @arg GPIO_AF_UART7: Connect UART7 pins to AF8 - * @arg GPIO_AF_UART8: Connect UART8 pins to AF8 - * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 - * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 - * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 - * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 - * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 - * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 - * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 - * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 - * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 - * @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices. - * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 - * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 - * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 - * @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices. - * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 - * @retval None - */ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) -{ - uint32_t temp = 0x00; - uint32_t temp_2 = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - assert_param(IS_GPIO_AF(GPIO_AF)); - - temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; - GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_gpio.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the GPIO peripheral: + * + Initialization and Configuration + * + GPIO Read and Write + * + GPIO Alternate functions configuration + * +@verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) Configure the GPIO pin(s) using GPIO_Init() + Four possible configuration are available for each pin: + (++) Input: Floating, Pull-up, Pull-down. + (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) + Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed + is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz. + (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open + Drain (Pull-up, Pull-down or no Pull). + (++) Analog: required mode when a pin is to be used as ADC channel or DAC + output. + + (#) Peripherals alternate function: + (++) For ADC and DAC, configure the desired pin in analog mode using + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; + (+++) For other peripherals (TIM, USART...): + (+++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function + (+++) Configure the desired pin in alternate function mode using + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (+++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (+++) Call GPIO_Init() function + + (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() + + (#) To set/reset the level of a pin configured in output mode use + GPIO_SetBits()/GPIO_ResetBits() + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + +@endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_gpio.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** @defgroup GPIO_Group1 Initialization and Configuration + * @brief Initialization and Configuration + * +@verbatim + =============================================================================== + ##### Initialization and Configuration ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); + } + else if (GPIOx == GPIOG) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); + } + else if (GPIOx == GPIOH) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); + } + + else if (GPIOx == GPIOI) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); + } + else if (GPIOx == GPIOJ) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE); + } + else + { + if (GPIOx == GPIOK) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE); + } + } +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + + /* ------------------------- Configure the port pins ---------------- */ + /*-- GPIO Mode Configuration --*/ + for (pinpos = 0x00; pinpos < 0x10; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); + GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); + + if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) + { + /* Check Speed mode parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + + /* Speed mode configuration */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); + GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); + + /* Check Output mode parameters */ + assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); + + /* Output mode configuration*/ + GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; + GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); + } + + /* Pull-up Pull down resistor configuration*/ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); + GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); + } + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; + GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bit to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group2 GPIO Read and Write + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### GPIO Read and Write ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @note This functions uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRL = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @note This functions uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRH = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRRL = GPIO_Pin; + } + else + { + GPIOx->BSRRH = GPIO_Pin ; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Toggles the specified GPIO pins.. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR ^= GPIO_Pin; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function + * @brief GPIO Alternate functions configuration function + * +@verbatim + =============================================================================== + ##### GPIO Alternate functions configuration function ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_PinSource: specifies the pin for the Alternate function. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @param GPIO_AFSelection: selects the pin to used as Alternate function. + * This parameter can be one of the following values: + * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) + * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) + * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) + * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) + * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) + * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 + * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 + * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 + * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 + * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 + * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 + * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 + * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 + * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 + * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 + * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 + * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 + * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 + * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 + * @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5 + * @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5 + * @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5 + * @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices. + * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 + * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7 + * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 + * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 + * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 + * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 + * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 + * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 + * @arg GPIO_AF_UART7: Connect UART7 pins to AF8 + * @arg GPIO_AF_UART8: Connect UART8 pins to AF8 + * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 + * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 + * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 + * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 + * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 + * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 + * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 + * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 + * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 + * @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices. + * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 + * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 + * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 + * @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices. + * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 + * @retval None + */ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) +{ + uint32_t temp = 0x00; + uint32_t temp_2 = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + assert_param(IS_GPIO_AF(GPIO_AF)); + + temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; + GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c index 290e51fea..880889542 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c @@ -1,726 +1,726 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hash.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the HASH / HMAC Processor (HASH) peripheral: - * - Initialization and Configuration functions - * - Message Digest generation functions - * - context swapping functions - * - DMA interface function - * - Interrupts and flags management - * -@verbatim - =================================================================== - ##### How to use this driver ##### - =================================================================== - - *** HASH operation : *** - ======================== - [..] - (#) Enable the HASH controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. - - (#) Initialise the HASH using HASH_Init() function. - - (#) Reset the HASH processor core, so that the HASH will be ready - to compute he message digest of a new message by using HASH_Reset() function. - - (#) Enable the HASH controller using the HASH_Cmd() function. - - (#) if using DMA for Data input transfer, Activate the DMA Request - using HASH_DMACmd() function - - (#) if DMA is not used for data transfer, use HASH_DataIn() function - to enter data to IN FIFO. - - - (#) Configure the Number of valid bits in last word of the message - using HASH_SetLastWordValidBitsNbr() function. - - (#) if the message length is not an exact multiple of 512 bits, - then the function HASH_StartDigest() must be called to launch the computation - of the final digest. - - (#) Once computed, the digest can be read using HASH_GetDigest() function. - - (#) To control HASH events you can use one of the following wo methods: - (++) Check on HASH flags using the HASH_GetFlagStatus() function. - (++) Use HASH interrupts through the function HASH_ITConfig() at - initialization phase and HASH_GetITStatus() function into - interrupt routines in hashing phase. - After checking on a flag you should clear it using HASH_ClearFlag() - function. And after checking on an interrupt event you should - clear it using HASH_ClearITPendingBit() function. - - (#) Save and restore hash processor context using - HASH_SaveContext() and HASH_RestoreContext() functions. - - - - *** HMAC operation : *** - ======================== - [..] The HMAC algorithm is used for message authentication, by - irreversibly binding the message being processed to a key chosen - by the user. - For HMAC specifications, refer to "HMAC: keyed-hashing for message - authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" - - [..] Basically, the HMAC algorithm consists of two nested hash operations: - HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] - where: - (+) "pad" is a sequence of zeroes needed to extend the key to the - length of the underlying hash function data block (that is - 512 bits for both the SHA-1 and MD5 hash algorithms) - (+) "|" represents the concatenation operator - - - [..]To compute the HMAC, four different phases are required: - (#) Initialise the HASH using HASH_Init() function to do HMAC - operation. - - (#) The key (to be used for the inner hash function) is then given to the core. - This operation follows the same mechanism as the one used to send the - message in the hash operation (that is, by HASH_DataIn() function and, - finally, HASH_StartDigest() function. - - (#) Once the last word has been entered and computation has started, - the hash processor elaborates the key. It is then ready to accept the message - text using the same mechanism as the one used to send the message in the - hash operation. - - (#) After the first hash round, the hash processor returns "ready" to indicate - that it is ready to receive the key to be used for the outer hash function - (normally, this key is the same as the one used for the inner hash function). - When the last word of the key is entered and computation starts, the HMAC - result is made available using HASH_GetDigest() function. - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hash.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initialize the HASH peripheral - (+) Configure the HASH Processor - (+) MD5/SHA1, - (+) HASH/HMAC, - (+) datatype - (+) HMAC Key (if mode = HMAC) - (+) Reset the HASH Processor - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the HASH peripheral registers to their default reset values - * @param None - * @retval None - */ -void HASH_DeInit(void) -{ - /* Enable HASH reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE); - /* Release HASH from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE); -} - -/** - * @brief Initializes the HASH peripheral according to the specified parameters - * in the HASH_InitStruct structure. - * @note the hash processor is reset when calling this function so that the - * HASH will be ready to compute the message digest of a new message. - * There is no need to call HASH_Reset() function. - * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains - * the configuration information for the HASH peripheral. - * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only - * if the algorithm mode is HMAC. - * @retval None - */ -void HASH_Init(HASH_InitTypeDef* HASH_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection)); - assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType)); - assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode)); - - /* Configure the Algorithm used, algorithm mode and the datatype */ - HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE); - HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \ - HASH_InitStruct->HASH_DataType | \ - HASH_InitStruct->HASH_AlgoMode); - - /* if algorithm mode is HMAC, set the Key */ - if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) - { - assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType)); - HASH->CR &= ~HASH_CR_LKEY; - HASH->CR |= HASH_InitStruct->HASH_HMACKeyType; - } - - /* Reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_CR_INIT; -} - -/** - * @brief Fills each HASH_InitStruct member with its default value. - * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will - * be initialized. - * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1, - * Data type selected is 32b and HMAC Key Type is short key. - * @retval None - */ -void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct) -{ - /* Initialize the HASH_AlgoSelection member */ - HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1; - - /* Initialize the HASH_AlgoMode member */ - HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH; - - /* Initialize the HASH_DataType member */ - HASH_InitStruct->HASH_DataType = HASH_DataType_32b; - - /* Initialize the HASH_HMACKeyType member */ - HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; -} - -/** - * @brief Resets the HASH processor core, so that the HASH will be ready - * to compute the message digest of a new message. - * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation - * completion interrupt status) bit corresponding to HASH_IT_DCI - * interrupt and HASH_FLAG_DCIS flag. - * @param None - * @retval None - */ -void HASH_Reset(void) -{ - /* Reset the HASH processor core */ - HASH->CR |= HASH_CR_INIT; -} -/** - * @} - */ - -/** @defgroup HASH_Group2 Message Digest generation functions - * @brief Message Digest generation functions - * -@verbatim - =============================================================================== - ##### Message Digest generation functions ##### - =============================================================================== - [..] This section provides functions allowing the generation of message digest: - (+) Push data in the IN FIFO : using HASH_DataIn() - (+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() - (+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr() - (+) start digest calculation : using HASH_StartDigest() - (+) Get the Digest message : using HASH_GetDigest() - -@endverbatim - * @{ - */ - - -/** - * @brief Configure the Number of valid bits in last word of the message - * @param ValidNumber: Number of valid bits in last word of the message. - * This parameter must be a number between 0 and 0x1F. - * - 0x00: All 32 bits of the last data written are valid - * - 0x01: Only bit [0] of the last data written is valid - * - 0x02: Only bits[1:0] of the last data written are valid - * - 0x03: Only bits[2:0] of the last data written are valid - * - ... - * - 0x1F: Only bits[30:0] of the last data written are valid - * @note The Number of valid bits must be set before to start the message - * digest competition (in Hash and HMAC) and key treatment(in HMAC). - * @retval None - */ -void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber) -{ - /* Check the parameters */ - assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber)); - - /* Configure the Number of valid bits in last word of the message */ - HASH->STR &= ~(HASH_STR_NBW); - HASH->STR |= ValidNumber; -} - -/** - * @brief Writes data in the Data Input FIFO - * @param Data: new data of the message to be processed. - * @retval None - */ -void HASH_DataIn(uint32_t Data) -{ - /* Write in the DIN register a new data */ - HASH->DIN = Data; -} - -/** - * @brief Returns the number of words already pushed into the IN FIFO. - * @param None - * @retval The value of words already pushed into the IN FIFO. - */ -uint8_t HASH_GetInFIFOWordsNbr(void) -{ - /* Return the value of NBW bits */ - return ((HASH->CR & HASH_CR_NBW) >> 8); -} - -/** - * @brief Provides the message digest result. - * @note In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used - * and is read as zero. - * In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used - * and is read as zero. - * In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used - * and is read as zero. - * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will - * hold the message digest result - * @retval None - */ -void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest) -{ - /* Get the data field */ - HASH_MessageDigest->Data[0] = HASH->HR[0]; - HASH_MessageDigest->Data[1] = HASH->HR[1]; - HASH_MessageDigest->Data[2] = HASH->HR[2]; - HASH_MessageDigest->Data[3] = HASH->HR[3]; - HASH_MessageDigest->Data[4] = HASH->HR[4]; - HASH_MessageDigest->Data[5] = HASH_DIGEST->HR[5]; - HASH_MessageDigest->Data[6] = HASH_DIGEST->HR[6]; - HASH_MessageDigest->Data[7] = HASH_DIGEST->HR[7]; -} - -/** - * @brief Starts the message padding and calculation of the final message - * @param None - * @retval None - */ -void HASH_StartDigest(void) -{ - /* Start the Digest calculation */ - HASH->STR |= HASH_STR_DCAL; -} -/** - * @} - */ - -/** @defgroup HASH_Group3 Context swapping functions - * @brief Context swapping functions - * -@verbatim - =============================================================================== - ##### Context swapping functions ##### - =============================================================================== - - [..] This section provides functions allowing to save and store HASH Context - - [..] It is possible to interrupt a HASH/HMAC process to perform another processing - with a higher priority, and to complete the interrupted process later on, when - the higher priority task is complete. To do so, the context of the interrupted - task must be saved from the HASH registers to memory, and then be restored - from memory to the HASH registers. - - (#) To save the current context, use HASH_SaveContext() function - (#) To restore the saved context, use HASH_RestoreContext() function - - -@endverbatim - * @{ - */ - -/** - * @brief Save the Hash peripheral Context. - * @note The context can be saved only when no block is currently being - * processed. So user must wait for DINIS = 1 (the last block has been - * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not - * full and no processing is ongoing). - * @param HASH_ContextSave: pointer to a HASH_Context structure that contains - * the repository for current context. - * @retval None - */ -void HASH_SaveContext(HASH_Context* HASH_ContextSave) -{ - uint8_t i = 0; - - /* save context registers */ - HASH_ContextSave->HASH_IMR = HASH->IMR; - HASH_ContextSave->HASH_STR = HASH->STR; - HASH_ContextSave->HASH_CR = HASH->CR; - for(i=0; i<=53;i++) - { - HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; - } -} - -/** - * @brief Restore the Hash peripheral Context. - * @note After calling this function, user can restart the processing from the - * point where it has been interrupted. - * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains - * the repository for saved context. - * @retval None - */ -void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) -{ - uint8_t i = 0; - - /* restore context registers */ - HASH->IMR = HASH_ContextRestore->HASH_IMR; - HASH->STR = HASH_ContextRestore->HASH_STR; - HASH->CR = HASH_ContextRestore->HASH_CR; - - /* Initialize the hash processor */ - HASH->CR |= HASH_CR_INIT; - - /* continue restoring context registers */ - for(i=0; i<=53;i++) - { - HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; - } -} -/** - * @} - */ - -/** @defgroup HASH_Group4 HASH's DMA interface Configuration function - * @brief HASH's DMA interface Configuration function - * -@verbatim - =============================================================================== - ##### HASH's DMA interface Configuration function ##### - =============================================================================== - - [..] This section provides functions allowing to configure the DMA interface for - HASH/ HMAC data input transfer. - - [..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be - sent to the IN FIFO using the DMA peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables auto-start message padding and - * calculation of the final message digest at the end of DMA transfer. - * @param NewState: new state of the selected HASH DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_AutoStartDigest(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the auto start of the final message digest at the end of DMA transfer */ - HASH->CR &= ~HASH_CR_MDMAT; - } - else - { - /* Disable the auto start of the final message digest at the end of DMA transfer */ - HASH->CR |= HASH_CR_MDMAT; - } -} - -/** - * @brief Enables or disables the HASH DMA interface. - * @note The DMA is disabled by hardware after the end of transfer. - * @param NewState: new state of the selected HASH DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the HASH DMA request */ - HASH->CR |= HASH_CR_DMAE; - } - else - { - /* Disable the HASH DMA request */ - HASH->CR &= ~HASH_CR_DMAE; - } -} -/** - * @} - */ - -/** @defgroup HASH_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the HASH Interrupts and - to get the status and clear flags and Interrupts pending bits. - - [..] The HASH provides 2 Interrupts sources and 5 Flags: - - *** Flags : *** - =============== - [..] - (#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO - which means that a new block (512 bit) can be entered into the input buffer. - - (#) HASH_FLAG_DCIS : set when Digest calculation is complete - - (#) HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or - a transfer is ongoing. This Flag is cleared only by hardware. - - (#) HASH_FLAG_BUSY : set when The hash core is processing a block of data - This Flag is cleared only by hardware. - - (#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that - the Data IN FIFO contains at least one word of data. This Flag is cleared - only by hardware. - - *** Interrupts : *** - ==================== - [..] - (#) HASH_IT_DINI : if enabled, this interrupt source is pending when 16 - locations are free in the Data IN FIFO which means that a new block (512 bit) - can be entered into the input buffer. This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DINI) function. - - (#) HASH_IT_DCI : if enabled, this interrupt source is pending when Digest - calculation is complete. This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DCI) function. - - *** Managing the HASH controller events : *** - ============================================= - [..] The user should identify which mode will be used in his application to manage - the HASH controller events: Polling mode or Interrupt mode. - - (#) In the Polling Mode it is advised to use the following functions: - (++) HASH_GetFlagStatus() : to check if flags events occur. - (++) HASH_ClearFlag() : to clear the flags events. - - (#) In the Interrupt Mode it is advised to use the following functions: - (++) HASH_ITConfig() : to enable or disable the interrupt source. - (++) HASH_GetITStatus() : to check if Interrupt occurs. - (++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified HASH interrupts. - * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @param NewState: new state of the specified HASH interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_HASH_IT(HASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected HASH interrupt */ - HASH->IMR |= HASH_IT; - } - else - { - /* Disable the selected HASH interrupt */ - HASH->IMR &= (uint32_t)(~HASH_IT); - } -} - -/** - * @brief Checks whether the specified HASH flag is set or not. - * @param HASH_FLAG: specifies the HASH flag to check. - * This parameter can be one of the following values: - * @arg HASH_FLAG_DINIS: Data input interrupt status flag - * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag - * @arg HASH_FLAG_BUSY: Busy flag - * @arg HASH_FLAG_DMAS: DMAS Status flag - * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag - * @retval The new state of HASH_FLAG (SET or RESET) - */ -FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tempreg = 0; - - /* Check the parameters */ - assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); - - /* check if the FLAG is in CR register */ - if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint32_t)RESET ) - { - tempreg = HASH->CR; - } - else /* The FLAG is in SR register */ - { - tempreg = HASH->SR; - } - - /* Check the status of the specified HASH flag */ - if ((tempreg & HASH_FLAG) != (uint32_t)RESET) - { - /* HASH is set */ - bitstatus = SET; - } - else - { - /* HASH_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the HASH_FLAG status */ - return bitstatus; -} -/** - * @brief Clears the HASH flags. - * @param HASH_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg HASH_FLAG_DINIS: Data Input Flag - * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag - * @retval None - */ -void HASH_ClearFlag(uint32_t HASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); - - /* Clear the selected HASH flags */ - HASH->SR = ~(uint32_t)HASH_FLAG; -} -/** - * @brief Checks whether the specified HASH interrupt has occurred or not. - * @param HASH_IT: specifies the HASH interrupt source to check. - * This parameter can be one of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @retval The new state of HASH_IT (SET or RESET). - */ -ITStatus HASH_GetITStatus(uint32_t HASH_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_HASH_GET_IT(HASH_IT)); - - - /* Check the status of the specified HASH interrupt */ - tmpreg = HASH->SR; - - if (((HASH->IMR & tmpreg) & HASH_IT) != RESET) - { - /* HASH_IT is set */ - bitstatus = SET; - } - else - { - /* HASH_IT is reset */ - bitstatus = RESET; - } - /* Return the HASH_IT status */ - return bitstatus; -} - -/** - * @brief Clears the HASH interrupt pending bit(s). - * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear. - * This parameter can be any combination of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @retval None - */ -void HASH_ClearITPendingBit(uint32_t HASH_IT) -{ - /* Check the parameters */ - assert_param(IS_HASH_IT(HASH_IT)); - - /* Clear the selected HASH interrupt pending bit */ - HASH->SR = (uint32_t)(~HASH_IT); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_hash.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the HASH / HMAC Processor (HASH) peripheral: + * - Initialization and Configuration functions + * - Message Digest generation functions + * - context swapping functions + * - DMA interface function + * - Interrupts and flags management + * +@verbatim + =================================================================== + ##### How to use this driver ##### + =================================================================== + + *** HASH operation : *** + ======================== + [..] + (#) Enable the HASH controller clock using + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. + + (#) Initialise the HASH using HASH_Init() function. + + (#) Reset the HASH processor core, so that the HASH will be ready + to compute he message digest of a new message by using HASH_Reset() function. + + (#) Enable the HASH controller using the HASH_Cmd() function. + + (#) if using DMA for Data input transfer, Activate the DMA Request + using HASH_DMACmd() function + + (#) if DMA is not used for data transfer, use HASH_DataIn() function + to enter data to IN FIFO. + + + (#) Configure the Number of valid bits in last word of the message + using HASH_SetLastWordValidBitsNbr() function. + + (#) if the message length is not an exact multiple of 512 bits, + then the function HASH_StartDigest() must be called to launch the computation + of the final digest. + + (#) Once computed, the digest can be read using HASH_GetDigest() function. + + (#) To control HASH events you can use one of the following wo methods: + (++) Check on HASH flags using the HASH_GetFlagStatus() function. + (++) Use HASH interrupts through the function HASH_ITConfig() at + initialization phase and HASH_GetITStatus() function into + interrupt routines in hashing phase. + After checking on a flag you should clear it using HASH_ClearFlag() + function. And after checking on an interrupt event you should + clear it using HASH_ClearITPendingBit() function. + + (#) Save and restore hash processor context using + HASH_SaveContext() and HASH_RestoreContext() functions. + + + + *** HMAC operation : *** + ======================== + [..] The HMAC algorithm is used for message authentication, by + irreversibly binding the message being processed to a key chosen + by the user. + For HMAC specifications, refer to "HMAC: keyed-hashing for message + authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" + + [..] Basically, the HMAC algorithm consists of two nested hash operations: + HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] + where: + (+) "pad" is a sequence of zeroes needed to extend the key to the + length of the underlying hash function data block (that is + 512 bits for both the SHA-1 and MD5 hash algorithms) + (+) "|" represents the concatenation operator + + + [..]To compute the HMAC, four different phases are required: + (#) Initialise the HASH using HASH_Init() function to do HMAC + operation. + + (#) The key (to be used for the inner hash function) is then given to the core. + This operation follows the same mechanism as the one used to send the + message in the hash operation (that is, by HASH_DataIn() function and, + finally, HASH_StartDigest() function. + + (#) Once the last word has been entered and computation has started, + the hash processor elaborates the key. It is then ready to accept the message + text using the same mechanism as the one used to send the message in the + hash operation. + + (#) After the first hash round, the hash processor returns "ready" to indicate + that it is ready to receive the key to be used for the outer hash function + (normally, this key is the same as the one used for the inner hash function). + When the last word of the key is entered and computation starts, the HMAC + result is made available using HASH_GetDigest() function. + +@endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hash.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup HASH + * @brief HASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HASH_Private_Functions + * @{ + */ + +/** @defgroup HASH_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to + (+) Initialize the HASH peripheral + (+) Configure the HASH Processor + (+) MD5/SHA1, + (+) HASH/HMAC, + (+) datatype + (+) HMAC Key (if mode = HMAC) + (+) Reset the HASH Processor + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the HASH peripheral registers to their default reset values + * @param None + * @retval None + */ +void HASH_DeInit(void) +{ + /* Enable HASH reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE); + /* Release HASH from reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE); +} + +/** + * @brief Initializes the HASH peripheral according to the specified parameters + * in the HASH_InitStruct structure. + * @note the hash processor is reset when calling this function so that the + * HASH will be ready to compute the message digest of a new message. + * There is no need to call HASH_Reset() function. + * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains + * the configuration information for the HASH peripheral. + * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only + * if the algorithm mode is HMAC. + * @retval None + */ +void HASH_Init(HASH_InitTypeDef* HASH_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection)); + assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType)); + assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode)); + + /* Configure the Algorithm used, algorithm mode and the datatype */ + HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE); + HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \ + HASH_InitStruct->HASH_DataType | \ + HASH_InitStruct->HASH_AlgoMode); + + /* if algorithm mode is HMAC, set the Key */ + if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) + { + assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType)); + HASH->CR &= ~HASH_CR_LKEY; + HASH->CR |= HASH_InitStruct->HASH_HMACKeyType; + } + + /* Reset the HASH processor core, so that the HASH will be ready to compute + the message digest of a new message */ + HASH->CR |= HASH_CR_INIT; +} + +/** + * @brief Fills each HASH_InitStruct member with its default value. + * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will + * be initialized. + * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1, + * Data type selected is 32b and HMAC Key Type is short key. + * @retval None + */ +void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct) +{ + /* Initialize the HASH_AlgoSelection member */ + HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1; + + /* Initialize the HASH_AlgoMode member */ + HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH; + + /* Initialize the HASH_DataType member */ + HASH_InitStruct->HASH_DataType = HASH_DataType_32b; + + /* Initialize the HASH_HMACKeyType member */ + HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; +} + +/** + * @brief Resets the HASH processor core, so that the HASH will be ready + * to compute the message digest of a new message. + * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation + * completion interrupt status) bit corresponding to HASH_IT_DCI + * interrupt and HASH_FLAG_DCIS flag. + * @param None + * @retval None + */ +void HASH_Reset(void) +{ + /* Reset the HASH processor core */ + HASH->CR |= HASH_CR_INIT; +} +/** + * @} + */ + +/** @defgroup HASH_Group2 Message Digest generation functions + * @brief Message Digest generation functions + * +@verbatim + =============================================================================== + ##### Message Digest generation functions ##### + =============================================================================== + [..] This section provides functions allowing the generation of message digest: + (+) Push data in the IN FIFO : using HASH_DataIn() + (+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() + (+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr() + (+) start digest calculation : using HASH_StartDigest() + (+) Get the Digest message : using HASH_GetDigest() + +@endverbatim + * @{ + */ + + +/** + * @brief Configure the Number of valid bits in last word of the message + * @param ValidNumber: Number of valid bits in last word of the message. + * This parameter must be a number between 0 and 0x1F. + * - 0x00: All 32 bits of the last data written are valid + * - 0x01: Only bit [0] of the last data written is valid + * - 0x02: Only bits[1:0] of the last data written are valid + * - 0x03: Only bits[2:0] of the last data written are valid + * - ... + * - 0x1F: Only bits[30:0] of the last data written are valid + * @note The Number of valid bits must be set before to start the message + * digest competition (in Hash and HMAC) and key treatment(in HMAC). + * @retval None + */ +void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber) +{ + /* Check the parameters */ + assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber)); + + /* Configure the Number of valid bits in last word of the message */ + HASH->STR &= ~(HASH_STR_NBW); + HASH->STR |= ValidNumber; +} + +/** + * @brief Writes data in the Data Input FIFO + * @param Data: new data of the message to be processed. + * @retval None + */ +void HASH_DataIn(uint32_t Data) +{ + /* Write in the DIN register a new data */ + HASH->DIN = Data; +} + +/** + * @brief Returns the number of words already pushed into the IN FIFO. + * @param None + * @retval The value of words already pushed into the IN FIFO. + */ +uint8_t HASH_GetInFIFOWordsNbr(void) +{ + /* Return the value of NBW bits */ + return ((HASH->CR & HASH_CR_NBW) >> 8); +} + +/** + * @brief Provides the message digest result. + * @note In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used + * and is read as zero. + * In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used + * and is read as zero. + * In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used + * and is read as zero. + * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will + * hold the message digest result + * @retval None + */ +void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest) +{ + /* Get the data field */ + HASH_MessageDigest->Data[0] = HASH->HR[0]; + HASH_MessageDigest->Data[1] = HASH->HR[1]; + HASH_MessageDigest->Data[2] = HASH->HR[2]; + HASH_MessageDigest->Data[3] = HASH->HR[3]; + HASH_MessageDigest->Data[4] = HASH->HR[4]; + HASH_MessageDigest->Data[5] = HASH_DIGEST->HR[5]; + HASH_MessageDigest->Data[6] = HASH_DIGEST->HR[6]; + HASH_MessageDigest->Data[7] = HASH_DIGEST->HR[7]; +} + +/** + * @brief Starts the message padding and calculation of the final message + * @param None + * @retval None + */ +void HASH_StartDigest(void) +{ + /* Start the Digest calculation */ + HASH->STR |= HASH_STR_DCAL; +} +/** + * @} + */ + +/** @defgroup HASH_Group3 Context swapping functions + * @brief Context swapping functions + * +@verbatim + =============================================================================== + ##### Context swapping functions ##### + =============================================================================== + + [..] This section provides functions allowing to save and store HASH Context + + [..] It is possible to interrupt a HASH/HMAC process to perform another processing + with a higher priority, and to complete the interrupted process later on, when + the higher priority task is complete. To do so, the context of the interrupted + task must be saved from the HASH registers to memory, and then be restored + from memory to the HASH registers. + + (#) To save the current context, use HASH_SaveContext() function + (#) To restore the saved context, use HASH_RestoreContext() function + + +@endverbatim + * @{ + */ + +/** + * @brief Save the Hash peripheral Context. + * @note The context can be saved only when no block is currently being + * processed. So user must wait for DINIS = 1 (the last block has been + * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not + * full and no processing is ongoing). + * @param HASH_ContextSave: pointer to a HASH_Context structure that contains + * the repository for current context. + * @retval None + */ +void HASH_SaveContext(HASH_Context* HASH_ContextSave) +{ + uint8_t i = 0; + + /* save context registers */ + HASH_ContextSave->HASH_IMR = HASH->IMR; + HASH_ContextSave->HASH_STR = HASH->STR; + HASH_ContextSave->HASH_CR = HASH->CR; + for(i=0; i<=53;i++) + { + HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; + } +} + +/** + * @brief Restore the Hash peripheral Context. + * @note After calling this function, user can restart the processing from the + * point where it has been interrupted. + * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains + * the repository for saved context. + * @retval None + */ +void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) +{ + uint8_t i = 0; + + /* restore context registers */ + HASH->IMR = HASH_ContextRestore->HASH_IMR; + HASH->STR = HASH_ContextRestore->HASH_STR; + HASH->CR = HASH_ContextRestore->HASH_CR; + + /* Initialize the hash processor */ + HASH->CR |= HASH_CR_INIT; + + /* continue restoring context registers */ + for(i=0; i<=53;i++) + { + HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; + } +} +/** + * @} + */ + +/** @defgroup HASH_Group4 HASH's DMA interface Configuration function + * @brief HASH's DMA interface Configuration function + * +@verbatim + =============================================================================== + ##### HASH's DMA interface Configuration function ##### + =============================================================================== + + [..] This section provides functions allowing to configure the DMA interface for + HASH/ HMAC data input transfer. + + [..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be + sent to the IN FIFO using the DMA peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables auto-start message padding and + * calculation of the final message digest at the end of DMA transfer. + * @param NewState: new state of the selected HASH DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void HASH_AutoStartDigest(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the auto start of the final message digest at the end of DMA transfer */ + HASH->CR &= ~HASH_CR_MDMAT; + } + else + { + /* Disable the auto start of the final message digest at the end of DMA transfer */ + HASH->CR |= HASH_CR_MDMAT; + } +} + +/** + * @brief Enables or disables the HASH DMA interface. + * @note The DMA is disabled by hardware after the end of transfer. + * @param NewState: new state of the selected HASH DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void HASH_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the HASH DMA request */ + HASH->CR |= HASH_CR_DMAE; + } + else + { + /* Disable the HASH DMA request */ + HASH->CR &= ~HASH_CR_DMAE; + } +} +/** + * @} + */ + +/** @defgroup HASH_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure the HASH Interrupts and + to get the status and clear flags and Interrupts pending bits. + + [..] The HASH provides 2 Interrupts sources and 5 Flags: + + *** Flags : *** + =============== + [..] + (#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO + which means that a new block (512 bit) can be entered into the input buffer. + + (#) HASH_FLAG_DCIS : set when Digest calculation is complete + + (#) HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or + a transfer is ongoing. This Flag is cleared only by hardware. + + (#) HASH_FLAG_BUSY : set when The hash core is processing a block of data + This Flag is cleared only by hardware. + + (#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that + the Data IN FIFO contains at least one word of data. This Flag is cleared + only by hardware. + + *** Interrupts : *** + ==================== + [..] + (#) HASH_IT_DINI : if enabled, this interrupt source is pending when 16 + locations are free in the Data IN FIFO which means that a new block (512 bit) + can be entered into the input buffer. This interrupt source is cleared using + HASH_ClearITPendingBit(HASH_IT_DINI) function. + + (#) HASH_IT_DCI : if enabled, this interrupt source is pending when Digest + calculation is complete. This interrupt source is cleared using + HASH_ClearITPendingBit(HASH_IT_DCI) function. + + *** Managing the HASH controller events : *** + ============================================= + [..] The user should identify which mode will be used in his application to manage + the HASH controller events: Polling mode or Interrupt mode. + + (#) In the Polling Mode it is advised to use the following functions: + (++) HASH_GetFlagStatus() : to check if flags events occur. + (++) HASH_ClearFlag() : to clear the flags events. + + (#) In the Interrupt Mode it is advised to use the following functions: + (++) HASH_ITConfig() : to enable or disable the interrupt source. + (++) HASH_GetITStatus() : to check if Interrupt occurs. + (++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified HASH interrupts. + * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg HASH_IT_DINI: Data Input interrupt + * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt + * @param NewState: new state of the specified HASH interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_HASH_IT(HASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected HASH interrupt */ + HASH->IMR |= HASH_IT; + } + else + { + /* Disable the selected HASH interrupt */ + HASH->IMR &= (uint32_t)(~HASH_IT); + } +} + +/** + * @brief Checks whether the specified HASH flag is set or not. + * @param HASH_FLAG: specifies the HASH flag to check. + * This parameter can be one of the following values: + * @arg HASH_FLAG_DINIS: Data input interrupt status flag + * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag + * @arg HASH_FLAG_BUSY: Busy flag + * @arg HASH_FLAG_DMAS: DMAS Status flag + * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag + * @retval The new state of HASH_FLAG (SET or RESET) + */ +FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tempreg = 0; + + /* Check the parameters */ + assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); + + /* check if the FLAG is in CR register */ + if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint32_t)RESET ) + { + tempreg = HASH->CR; + } + else /* The FLAG is in SR register */ + { + tempreg = HASH->SR; + } + + /* Check the status of the specified HASH flag */ + if ((tempreg & HASH_FLAG) != (uint32_t)RESET) + { + /* HASH is set */ + bitstatus = SET; + } + else + { + /* HASH_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the HASH_FLAG status */ + return bitstatus; +} +/** + * @brief Clears the HASH flags. + * @param HASH_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg HASH_FLAG_DINIS: Data Input Flag + * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag + * @retval None + */ +void HASH_ClearFlag(uint32_t HASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); + + /* Clear the selected HASH flags */ + HASH->SR = ~(uint32_t)HASH_FLAG; +} +/** + * @brief Checks whether the specified HASH interrupt has occurred or not. + * @param HASH_IT: specifies the HASH interrupt source to check. + * This parameter can be one of the following values: + * @arg HASH_IT_DINI: Data Input interrupt + * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt + * @retval The new state of HASH_IT (SET or RESET). + */ +ITStatus HASH_GetITStatus(uint32_t HASH_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_HASH_GET_IT(HASH_IT)); + + + /* Check the status of the specified HASH interrupt */ + tmpreg = HASH->SR; + + if (((HASH->IMR & tmpreg) & HASH_IT) != RESET) + { + /* HASH_IT is set */ + bitstatus = SET; + } + else + { + /* HASH_IT is reset */ + bitstatus = RESET; + } + /* Return the HASH_IT status */ + return bitstatus; +} + +/** + * @brief Clears the HASH interrupt pending bit(s). + * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear. + * This parameter can be any combination of the following values: + * @arg HASH_IT_DINI: Data Input interrupt + * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt + * @retval None + */ +void HASH_ClearITPendingBit(uint32_t HASH_IT) +{ + /* Check the parameters */ + assert_param(IS_HASH_IT(HASH_IT)); + + /* Clear the selected HASH interrupt pending bit */ + HASH->SR = (uint32_t)(~HASH_IT); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c index 64691164f..0a5f1da06 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c @@ -1,320 +1,320 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hash_md5.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides high level functions to compute the HASH MD5 and - * HMAC MD5 Digest of an input message. - * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH - * peripheral. - * -@verbatim - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable The HASH controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. - - (#) Calculate the HASH MD5 Digest using HASH_MD5() function. - - (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function. - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hash.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group7 High Level MD5 functions - * @brief High Level MD5 Hash and HMAC functions - * -@verbatim - =============================================================================== - ##### High Level MD5 Hash and HMAC functions ##### - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Compute the HASH MD5 digest. - * @param Input: pointer to the Input buffer to be treated. - * @param Ilen: length of the Input buffer. - * @param Output: the returned digest - * @retval An ErrorStatus enumeration value: - * - SUCCESS: digest computation done - * - ERROR: digest computation failed - */ -ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]) -{ - HASH_InitTypeDef MD5_HASH_InitStructure; - HASH_MsgDigest MD5_MessageDigest; - __IO uint16_t nbvalidbitsdata = 0; - uint32_t i = 0; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - - /* Number of valid bits in last word of the Input data */ - nbvalidbitsdata = 8 * (Ilen % 4); - - /* HASH peripheral initialization */ - HASH_DeInit(); - - /* HASH Configuration */ - MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; - MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; - MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; - HASH_Init(&MD5_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the data */ - HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); - - /* Write the Input block in the IN FIFO */ - for(i=0; i 64) - { - /* HMAC long Key */ - MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; - } - else - { - /* HMAC short Key */ - MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; - } - HASH_Init(&MD5_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the Key */ - HASH_SetLastWordValidBitsNbr(nbvalidbitskey); - - /* Write the Key */ - for(i=0; i
© COPYRIGHT 2014 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hash.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup HASH + * @brief HASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HASH_Private_Functions + * @{ + */ + +/** @defgroup HASH_Group7 High Level MD5 functions + * @brief High Level MD5 Hash and HMAC functions + * +@verbatim + =============================================================================== + ##### High Level MD5 Hash and HMAC functions ##### + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Compute the HASH MD5 digest. + * @param Input: pointer to the Input buffer to be treated. + * @param Ilen: length of the Input buffer. + * @param Output: the returned digest + * @retval An ErrorStatus enumeration value: + * - SUCCESS: digest computation done + * - ERROR: digest computation failed + */ +ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]) +{ + HASH_InitTypeDef MD5_HASH_InitStructure; + HASH_MsgDigest MD5_MessageDigest; + __IO uint16_t nbvalidbitsdata = 0; + uint32_t i = 0; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + + + /* Number of valid bits in last word of the Input data */ + nbvalidbitsdata = 8 * (Ilen % 4); + + /* HASH peripheral initialization */ + HASH_DeInit(); + + /* HASH Configuration */ + MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; + MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; + MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; + HASH_Init(&MD5_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the data */ + HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); + + /* Write the Input block in the IN FIFO */ + for(i=0; i 64) + { + /* HMAC long Key */ + MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; + } + else + { + /* HMAC short Key */ + MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; + } + HASH_Init(&MD5_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the Key */ + HASH_SetLastWordValidBitsNbr(nbvalidbitskey); + + /* Write the Key */ + for(i=0; i
© COPYRIGHT 2014 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hash.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group6 High Level SHA1 functions - * @brief High Level SHA1 Hash and HMAC functions - * -@verbatim - =============================================================================== - ##### High Level SHA1 Hash and HMAC functions ##### - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Compute the HASH SHA1 digest. - * @param Input: pointer to the Input buffer to be treated. - * @param Ilen: length of the Input buffer. - * @param Output: the returned digest - * @retval An ErrorStatus enumeration value: - * - SUCCESS: digest computation done - * - ERROR: digest computation failed - */ -ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) -{ - HASH_InitTypeDef SHA1_HASH_InitStructure; - HASH_MsgDigest SHA1_MessageDigest; - __IO uint16_t nbvalidbitsdata = 0; - uint32_t i = 0; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - /* Number of valid bits in last word of the Input data */ - nbvalidbitsdata = 8 * (Ilen % 4); - - /* HASH peripheral initialization */ - HASH_DeInit(); - - /* HASH Configuration */ - SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; - SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; - SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; - HASH_Init(&SHA1_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the data */ - HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); - - /* Write the Input block in the IN FIFO */ - for(i=0; i 64) - { - /* HMAC long Key */ - SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; - } - else - { - /* HMAC short Key */ - SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; - } - HASH_Init(&SHA1_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the Key */ - HASH_SetLastWordValidBitsNbr(nbvalidbitskey); - - /* Write the Key */ - for(i=0; i
© COPYRIGHT 2014 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hash.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup HASH + * @brief HASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HASH_Private_Functions + * @{ + */ + +/** @defgroup HASH_Group6 High Level SHA1 functions + * @brief High Level SHA1 Hash and HMAC functions + * +@verbatim + =============================================================================== + ##### High Level SHA1 Hash and HMAC functions ##### + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Compute the HASH SHA1 digest. + * @param Input: pointer to the Input buffer to be treated. + * @param Ilen: length of the Input buffer. + * @param Output: the returned digest + * @retval An ErrorStatus enumeration value: + * - SUCCESS: digest computation done + * - ERROR: digest computation failed + */ +ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) +{ + HASH_InitTypeDef SHA1_HASH_InitStructure; + HASH_MsgDigest SHA1_MessageDigest; + __IO uint16_t nbvalidbitsdata = 0; + uint32_t i = 0; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + + /* Number of valid bits in last word of the Input data */ + nbvalidbitsdata = 8 * (Ilen % 4); + + /* HASH peripheral initialization */ + HASH_DeInit(); + + /* HASH Configuration */ + SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; + SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; + SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; + HASH_Init(&SHA1_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the data */ + HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); + + /* Write the Input block in the IN FIFO */ + for(i=0; i 64) + { + /* HMAC long Key */ + SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; + } + else + { + /* HMAC short Key */ + SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; + } + HASH_Init(&SHA1_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the Key */ + HASH_SetLastWordValidBitsNbr(nbvalidbitskey); + + /* Write the Key */ + for(i=0; iGPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function - Recommended configuration is Push-Pull, Pull-up, Open-Drain. - Add an external pull up if necessary (typically 4.7 KOhm). - - (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged - Address using the I2C_Init() function. - - (#) Optionally you can enable/configure the following parameters without - re-initialization (i.e there is no need to call again I2C_Init() function): - (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function - (++) Enable the dual addressing mode using I2C_DualAddressCmd() function - (++) Enable the general call using the I2C_GeneralCallCmd() function - (++) Enable the clock stretching using I2C_StretchClockCmd() function - (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() - function. - (++) Configure the NACK position for Master Receiver mode in case of - 2 bytes reception using the function I2C_NACKPositionConfig(). - (++) Enable the PEC Calculation using I2C_CalculatePEC() function - (++) For SMBus Mode: - (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function - (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function - - (#) Enable the NVIC and the corresponding interrupt using the function - I2C_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using I2C_DMACmd() or - I2C_DMALastTransferCmd() function. - -@@- When using DMA mode, I2C interrupts may be used at the same time to - control the communication flow (Start/Stop/Ack... events and errors). - - (#) Enable the I2C using the I2C_Cmd() function. - - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the - transfers. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_i2c.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral - input clock) must be a multiple of 10 MHz */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & I2C_CCR_CCR) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | I2C_CCR_FS); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - } -} - -/** - * @brief Enables or disables the Analog filter of I2C peripheral. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices. - * - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the Analog filter. - * This parameter can be: ENABLE or DISABLE. - * @note This function should be called before initializing and enabling - the I2C Peripheral. - * @retval None - */ -void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the analog filter */ - I2Cx->FLTR &= (uint16_t)~((uint16_t)I2C_FLTR_ANOFF); - } - else - { - /* Disable the analog filter */ - I2Cx->FLTR |= I2C_FLTR_ANOFF; - } -} - -/** - * @brief Configures the Digital noise filter of I2C peripheral. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices. - * - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_DigitalFilter: Coefficient of digital noise filter. - * This parameter can be a number between 0x00 and 0x0F. - * @note This function should be called before initializing and enabling - the I2C Peripheral. - * @retval None - */ -void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIGITAL_FILTER(I2C_DigitalFilter)); - - /* Get the old register value */ - tmpreg = I2Cx->FLTR; - - /* Reset I2Cx DNF bit [3:0] */ - tmpreg &= (uint16_t)~((uint16_t)I2C_FLTR_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= (uint16_t)((uint16_t)I2C_DigitalFilter & I2C_FLTR_DNF); - - /* Store the new register value */ - I2Cx->FLTR = tmpreg; -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= I2C_CR1_START; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= I2C_CR1_STOP; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); - } -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a Transmitter - * or a Receiver. - * This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= I2C_OAR1_ADD0; - } - else - { - /* Reset the address bit0 for write */ - Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= I2C_CR1_ACK; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= I2C_OAR2_ENDUAL; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable generall call */ - I2Cx->CR1 |= I2C_CR1_ENGC; - } - else - { - /* Disable generall call */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); - } -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @note When software reset is enabled, the I2C IOs are released (this can - * be useful to recover from bus errors). - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= I2C_CR1_SWRST; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= I2C_CR1_NOSTRETCH; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - -/** - * @brief Selects the specified I2C NACK position in master receiver mode. - * @note This function is useful in I2C Master Receiver mode when the number - * of data to be received is equal to 2. In this case, this function - * should be called (with parameter I2C_NACKPosition_Next) before data - * reception starts,as described in the 2-byte reception procedure - * recommended in Reference Manual in Section: Master receiver. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_NACKPosition: specifies the NACK position. - * This parameter can be one of the following values: - * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last - * received byte. - * @arg I2C_NACKPosition_Current: indicates that current byte is the last - * received byte. - * - * @note This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * - * @retval None - */ -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); - - /* Check the input parameter */ - if (I2C_NACKPosition == I2C_NACKPosition_Next) - { - /* Next byte in shift register is the last received byte */ - I2Cx->CR1 |= I2C_NACKPosition_Next; - } - else - { - /* Current byte in shift register is the last received byte */ - I2Cx->CR1 &= I2C_NACKPosition_Current; - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= I2C_CR1_ENARP; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); - } -} -/** - * @} - */ - -/** @defgroup I2C_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @} - */ - -/** @defgroup I2C_Group3 PEC management functions - * @brief PEC management functions - * -@verbatim - =============================================================================== - ##### PEC management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= I2C_CR1_PEC; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * - * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() - * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() - * is intended to used in I2C mode. - * - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= I2C_CR1_ENPEC; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @} - */ - -/** @defgroup I2C_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - This section provides functions allowing to configure the I2C DMA channels - requests. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= I2C_CR2_DMAEN; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); - } -} - -/** - * @brief Specifies that the next DMA transfer is the last one. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= I2C_CR2_LAST; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); - } -} - -/** - * @} - */ - -/** @defgroup I2C_Group5 Interrupts events and flags management functions - * @brief Interrupts, events and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts, events and flags management functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the I2C Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - - ##### I2C State Monitoring Functions ##### - =============================================================================== - [..] - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - (#) Basic state monitoring (Using I2C_CheckEvent() function) - - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - (++) When to use - (+++) This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0090). - (+++) It is also suitable for users who need to define their own events. - - (++) Limitations - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - -@@- For error management, it is advised to use the following functions: - (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - (#) Advanced state monitoring (Using the function I2C_GetLastEvent()) - - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - (++) When to use - (+++) This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - (+++) The returned value could be compared to events already defined in - the library (stm32f4xx_i2c.h) or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - (+++) At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - (++) Limitations - (+++) User may need to define his own events. - (+++) Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - (++) When to use - (+++) This function could be used for specific applications or in debug - phase. - (+++) It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - (++) Limitations: - (+++) When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - (+++) Function may need to be called twice or more in order to monitor - one single event. - - For detailed description of Events, please refer to section I2C_Events in - stm32f4xx_i2c.h file. - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4 - * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5 - * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9 - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f4xx_i2c.h file. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Check whether the last event contains the I2C_EVENT */ - if ((lastevent & I2C_EVENT) == I2C_EVENT) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f4xx_i2c.h file. - * - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Return status */ - return lastevent; -} - -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_MASK; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_MASK; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_MASK; - - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's interrupt pending bits. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_MASK; - - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_i2c.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Inter-integrated circuit (I2C) + * + Initialization and Configuration + * + Data transfers + * + PEC management + * + DMA transfers management + * + Interrupts, events and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE) + function for I2C1, I2C2 or I2C3. + + (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using + RCC_AHBPeriphClockCmd() function. + + (#) Peripherals alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function + Recommended configuration is Push-Pull, Pull-up, Open-Drain. + Add an external pull up if necessary (typically 4.7 KOhm). + + (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged + Address using the I2C_Init() function. + + (#) Optionally you can enable/configure the following parameters without + re-initialization (i.e there is no need to call again I2C_Init() function): + (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function + (++) Enable the dual addressing mode using I2C_DualAddressCmd() function + (++) Enable the general call using the I2C_GeneralCallCmd() function + (++) Enable the clock stretching using I2C_StretchClockCmd() function + (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() + function. + (++) Configure the NACK position for Master Receiver mode in case of + 2 bytes reception using the function I2C_NACKPositionConfig(). + (++) Enable the PEC Calculation using I2C_CalculatePEC() function + (++) For SMBus Mode: + (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function + (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function + + (#) Enable the NVIC and the corresponding interrupt using the function + I2C_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function + (++) Active the needed channel Request using I2C_DMACmd() or + I2C_DMALastTransferCmd() function. + -@@- When using DMA mode, I2C interrupts may be used at the same time to + control the communication flow (Start/Stop/Ack... events and errors). + + (#) Enable the I2C using the I2C_Cmd() function. + + (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the + transfers. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_i2c.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TRISE */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral + input clock) must be a multiple of 10 MHz */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + + /* Test if CCR value is under 0x1*/ + if ((result & I2C_CCR_CCR) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= (uint16_t)(result | I2C_CCR_FS); + /* Set Maximum Rise Time for fast mode */ + I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); + } +} + +/** + * @brief Enables or disables the Analog filter of I2C peripheral. + * + * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices. + * + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the Analog filter. + * This parameter can be: ENABLE or DISABLE. + * @note This function should be called before initializing and enabling + the I2C Peripheral. + * @retval None + */ +void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the analog filter */ + I2Cx->FLTR &= (uint16_t)~((uint16_t)I2C_FLTR_ANOFF); + } + else + { + /* Disable the analog filter */ + I2Cx->FLTR |= I2C_FLTR_ANOFF; + } +} + +/** + * @brief Configures the Digital noise filter of I2C peripheral. + * + * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices. + * + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_DigitalFilter: Coefficient of digital noise filter. + * This parameter can be a number between 0x00 and 0x0F. + * @note This function should be called before initializing and enabling + the I2C Peripheral. + * @retval None + */ +void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIGITAL_FILTER(I2C_DigitalFilter)); + + /* Get the old register value */ + tmpreg = I2Cx->FLTR; + + /* Reset I2Cx DNF bit [3:0] */ + tmpreg &= (uint16_t)~((uint16_t)I2C_FLTR_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= (uint16_t)((uint16_t)I2C_DigitalFilter & I2C_FLTR_DNF); + + /* Store the new register value */ + I2Cx->FLTR = tmpreg; +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= I2C_CR1_START; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= I2C_CR1_STOP; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); + } +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param Address: specifies the slave address which will be transmitted + * @param I2C_Direction: specifies whether the I2C device will be a Transmitter + * or a Receiver. + * This parameter can be one of the following values + * @arg I2C_Direction_Transmitter: Transmitter mode + * @arg I2C_Direction_Receiver: Receiver mode + * @retval None. + */ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= I2C_OAR1_ADD0; + } + else + { + /* Reset the address bit0 for write */ + Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= I2C_CR1_ACK; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param Address: specifies the 7bit I2C own address2. + * @retval None. + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); + + /* Set I2Cx Own address2 */ + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= I2C_OAR2_ENDUAL; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= I2C_CR1_ENGC; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); + } +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @note When software reset is enabled, the I2C IOs are released (this can + * be useful to recover from bus errors). + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= I2C_CR1_SWRST; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= I2C_CR1_NOSTRETCH; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_DutyCycle: specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 + * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @retval None + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + +/** + * @brief Selects the specified I2C NACK position in master receiver mode. + * @note This function is useful in I2C Master Receiver mode when the number + * of data to be received is equal to 2. In this case, this function + * should be called (with parameter I2C_NACKPosition_Next) before data + * reception starts,as described in the 2-byte reception procedure + * recommended in Reference Manual in Section: Master receiver. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_NACKPosition: specifies the NACK position. + * This parameter can be one of the following values: + * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last + * received byte. + * @arg I2C_NACKPosition_Current: indicates that current byte is the last + * received byte. + * + * @note This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * + * @retval None + */ +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); + + /* Check the input parameter */ + if (I2C_NACKPosition == I2C_NACKPosition_Next) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CR1 |= I2C_NACKPosition_Next; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CR1 &= I2C_NACKPosition_Current; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_SMBusAlert: specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low + * @arg I2C_SMBusAlert_High: SMBAlert pin driven high + * @retval None + */ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= I2C_CR1_ENARP; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); + } +} +/** + * @} + */ + +/** @defgroup I2C_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @} + */ + +/** @defgroup I2C_Group3 PEC management functions + * @brief PEC management functions + * +@verbatim + =============================================================================== + ##### PEC management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= I2C_CR1_PEC; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_PECPosition: specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PECPosition_Next: indicates that the next byte is PEC + * @arg I2C_PECPosition_Current: indicates that current byte is PEC + * + * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() + * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() + * is intended to used in I2C mode. + * + * @retval None + */ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* Next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= I2C_CR1_ENPEC; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @retval The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->SR2) >> 8); +} + +/** + * @} + */ + +/** @defgroup I2C_Group4 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + This section provides functions allowing to configure the I2C DMA channels + requests. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); + } +} + +/** + * @brief Specifies that the next DMA transfer is the last one. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CR2 |= I2C_CR2_LAST; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); + } +} + +/** + * @} + */ + +/** @defgroup I2C_Group5 Interrupts events and flags management functions + * @brief Interrupts, events and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts, events and flags management functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the I2C Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + + ##### I2C State Monitoring Functions ##### + =============================================================================== + [..] + This I2C driver provides three different ways for I2C state monitoring + depending on the application requirements and constraints: + + + (#) Basic state monitoring (Using I2C_CheckEvent() function) + + It compares the status registers (SR1 and SR2) content to a given event + (can be the combination of one or more flags). + It returns SUCCESS if the current status includes the given flags + and returns ERROR if one or more flags are missing in the current status. + + (++) When to use + (+++) This function is suitable for most applications as well as for startup + activity since the events are fully described in the product reference + manual (RM0090). + (+++) It is also suitable for users who need to define their own events. + + (++) Limitations + If an error occurs (ie. error flags are set besides to the monitored + flags), the I2C_CheckEvent() function may return SUCCESS despite + the communication hold or corrupted real state. + In this case, it is advised to use error interrupts to monitor + the error events and handle them in the interrupt IRQ handler. + + -@@- For error management, it is advised to use the following functions: + (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + Where x is the peripheral instance (I2C1, I2C2 ...) + (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the + I2Cx_ER_IRQHandler() function in order to determine which error occurred. + (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + and/or I2C_GenerateStop() in order to clear the error flag and source + and return to correct communication status. + + + (#) Advanced state monitoring (Using the function I2C_GetLastEvent()) + + Using the function I2C_GetLastEvent() which returns the image of both status + registers in a single word (uint32_t) (Status Register 2 value is shifted left + by 16 bits and concatenated to Status Register 1). + + (++) When to use + (+++) This function is suitable for the same applications above but it + allows to overcome the mentioned limitation of I2C_GetFlagStatus() + function. + (+++) The returned value could be compared to events already defined in + the library (stm32f4xx_i2c.h) or to custom values defined by user. + This function is suitable when multiple flags are monitored at the + same time. + (+++) At the opposite of I2C_CheckEvent() function, this function allows + user to choose when an event is accepted (when all events flags are + set and no other flags are set or just when the needed flags are set + like I2C_CheckEvent() function. + + (++) Limitations + (+++) User may need to define his own events. + (+++) Same remark concerning the error management is applicable for this + function if user decides to check only regular communication flags + (and ignores error flags). + + + (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus()) + + Using the function I2C_GetFlagStatus() which simply returns the status of + one single flag (ie. I2C_FLAG_RXNE ...). + + (++) When to use + (+++) This function could be used for specific applications or in debug + phase. + (+++) It is suitable when only one flag checking is needed (most I2C + events are monitored through multiple flags). + (++) Limitations: + (+++) When calling this function, the Status register is accessed. + Some flags are cleared when the status register is accessed. + So checking the status of one Flag, may clear other ones. + (+++) Function may need to be called twice or more in order to monitor + one single event. + + For detailed description of Events, please refer to section I2C_Events in + stm32f4xx_i2c.h file. + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_BUF: Buffer interrupt mask + * @arg I2C_IT_EVT: Event interrupt mask + * @arg I2C_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (uint16_t)~I2C_IT; + } +} + +/* + =============================================================================== + 1. Basic state monitoring + =============================================================================== + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9 + * + * @note For detailed description of Events, please refer to section I2C_Events + * in stm32f4xx_i2c.h file. + * + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/* + =============================================================================== + 2. Advanced state monitoring + =============================================================================== + */ + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * + * @note For detailed description of Events, please refer to section I2C_Events + * in stm32f4xx_i2c.h file. + * + * @retval The last event + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Return status */ + return lastevent; +} + +/* + =============================================================================== + 3. Flag-based state monitoring + =============================================================================== + */ + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_FLAG_SB: Start bit flag (Master mode) + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_MASK; + + if(i2creg != 0) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx SR2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx SR2 register address */ + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @note STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * @note ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DR register. + * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * @note ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR + * register (I2C_SendData()). + * + * @retval None + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_MASK; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert flag + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_IT_PECERR: PEC error in reception flag + * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure flag + * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_IT_BERR: Bus error flag + * @arg I2C_IT_TXE: Data register empty flag (Transmitter) + * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag + * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) + * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_IT_BTF: Byte transfer finished flag + * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_IT_SB: Start bit flag (Master mode) + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_MASK; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's interrupt pending bits. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert interrupt + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt + * @arg I2C_IT_PECERR: PEC error in reception interrupt + * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure interrupt + * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) + * @arg I2C_IT_BERR: Bus error interrupt + * + * @note STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * @note ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DR register. + * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * @note ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * @note SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DR register (I2C_SendData()). + * @retval None + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_MASK; + + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c index 08b31b936..4adc69b36 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c @@ -1,266 +1,266 @@ -/** - ****************************************************************************** - * @file stm32f4xx_iwdg.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Independent watchdog (IWDG) peripheral: - * + Prescaler and Counter configuration - * + IWDG activation - * + Flag management - * - @verbatim - =============================================================================== - ##### IWDG features ##### - =============================================================================== - [..] - The IWDG can be started by either software or hardware (configurable - through option byte). - - The IWDG is clocked by its own dedicated low-speed clock (LSI) and - thus stays active even if the main clock fails. - Once the IWDG is started, the LSI is forced ON and cannot be disabled - (LSI cannot be disabled too), and the counter starts counting down from - the reset value of 0xFFF. When it reaches the end of count value (0x000) - a system reset is generated. - The IWDG counter should be reloaded at regular intervals to prevent - an MCU reset. - - The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - - IWDGRST flag in RCC_CSR register can be used to inform when a IWDG - reset occurs. - - Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx - devices provide the capability to measure the LSI frequency (LSI clock - connected internally to TIM5 CH4 input capture). The measured value - can be used to have an IWDG timeout with an acceptable accuracy. - For more information, please refer to the STM32F4xx Reference manual - - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable write access to IWDG_PR and IWDG_RLR registers using - IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function - - (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function - - (#) Configure the IWDG counter value using IWDG_SetReload() function. - This value will be loaded in the IWDG counter each time the counter - is reloaded, then the IWDG will start counting down from this value. - - (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used - in software mode (no need to enable the LSI, it will be enabled - by hardware) - - (#) Then the application program must reload the IWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - IWDG_ReloadCounter() function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_iwdg.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint16_t)0xAAAA) -#define KR_KEY_ENABLE ((uint16_t)0xCCCC) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions - * @brief Prescaler and Counter configuration functions - * -@verbatim - =============================================================================== - ##### Prescaler and Counter configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_RELOAD; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group2 IWDG activation function - * @brief IWDG activation function - * -@verbatim - =============================================================================== - ##### IWDG activation function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_ENABLE; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group3 Flag management function - * @brief Flag management function - * -@verbatim - =============================================================================== - ##### Flag management function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_iwdg.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Independent watchdog (IWDG) peripheral: + * + Prescaler and Counter configuration + * + IWDG activation + * + Flag management + * + @verbatim + =============================================================================== + ##### IWDG features ##### + =============================================================================== + [..] + The IWDG can be started by either software or hardware (configurable + through option byte). + + The IWDG is clocked by its own dedicated low-speed clock (LSI) and + thus stays active even if the main clock fails. + Once the IWDG is started, the LSI is forced ON and cannot be disabled + (LSI cannot be disabled too), and the counter starts counting down from + the reset value of 0xFFF. When it reaches the end of count value (0x000) + a system reset is generated. + The IWDG counter should be reloaded at regular intervals to prevent + an MCU reset. + + The IWDG is implemented in the VDD voltage domain that is still functional + in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + + IWDGRST flag in RCC_CSR register can be used to inform when a IWDG + reset occurs. + + Min-max timeout value @32KHz (LSI): ~125us / ~32.7s + The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx + devices provide the capability to measure the LSI frequency (LSI clock + connected internally to TIM5 CH4 input capture). The measured value + can be used to have an IWDG timeout with an acceptable accuracy. + For more information, please refer to the STM32F4xx Reference manual + + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable write access to IWDG_PR and IWDG_RLR registers using + IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function + + (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function + + (#) Configure the IWDG counter value using IWDG_SetReload() function. + This value will be loaded in the IWDG counter each time the counter + is reloaded, then the IWDG will start counting down from this value. + + (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used + in software mode (no need to enable the LSI, it will be enabled + by hardware) + + (#) Then the application program must reload the IWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + IWDG_ReloadCounter() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_iwdg.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_RELOAD ((uint16_t)0xAAAA) +#define KR_KEY_ENABLE ((uint16_t)0xCCCC) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions + * @brief Prescaler and Counter configuration functions + * +@verbatim + =============================================================================== + ##### Prescaler and Counter configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_RELOAD; +} + +/** + * @} + */ + +/** @defgroup IWDG_Group2 IWDG activation function + * @brief IWDG activation function + * +@verbatim + =============================================================================== + ##### IWDG activation function ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_ENABLE; +} + +/** + * @} + */ + +/** @defgroup IWDG_Group3 Flag management function + * @brief Flag management function + * +@verbatim + =============================================================================== + ##### Flag management function ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c index d42b21b4c..ded1928a8 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c @@ -1,1110 +1,1110 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ltdc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the LTDC controller (LTDC) peripheral: - * + Initialization and configuration - * + Interrupts and flags management - * - * @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable LTDC clock using - RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE) function. - (#) Configures LTDC - (++) Configure the required Pixel clock following the panel datasheet - (++) Configure the Synchronous timings: VSYNC, HSYNC, Vertical and - Horizontal back proch, active data area and the front proch - timings - (++) Configure the synchronous signals and clock polarity in the - LTDC_GCR register - (#) Configures Layer1/2 parameters - (++) The Layer window horizontal and vertical position in the LTDC_LxWHPCR and - LTDC_WVPCR registers. The layer window must be in the active data area. - (++) The pixel input format in the LTDC_LxPFCR register - (++) The color frame buffer start address in the LTDC_LxCFBAR register - (++) The line length and pitch of the color frame buffer in the - LTDC_LxCFBLR register - (++) The number of lines of the color frame buffer in - the LTDC_LxCFBLNR register - (++) if needed, load the CLUT with the RGB values and the address - in the LTDC_LxCLUTWR register - (++) If needed, configure the default color and the blending factors - respectively in the LTDC_LxDCCR and LTDC_LxBFCR registers - - (++) If needed, Dithering and color keying can be be enabled respectively - in the LTDC_GCR and LTDC_LxCKCR registers. It can be also enabled - on the fly. - (#) Enable Layer1/2 and if needed the CLUT in the LTDC_LxCR register - - (#) Reload the shadow registers to active register through - the LTDC_SRCR register. - -@- All layer parameters can be be modified on the fly except the CLUT. - The new configuration has to be either reloaded immediately - or during vertical blanking period by configuring the LTDC_SRCR register. - (#) Call the LTDC_Cmd() to enable the LTDC controller. - - @endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_ltdc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup LTDC - * @brief LTDC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -#define GCR_MASK ((uint32_t)0x0FFE888F) /* LTDC GCR Mask */ - - -/** @defgroup LTDC_Private_Functions - * @{ - */ - -/** @defgroup LTDC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the LTDC - (+) Enable or Disable Dither - (+) Define the position of the line interrupt - (+) reload layers registers with new parameters - (+) Initialize and configure layer1 and layer2 - (+) Set and configure the color keying functionality - (+) Configure and Enables or disables CLUT - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the LTDC peripheral registers to their default reset - * values. - * @param None - * @retval None - */ - -void LTDC_DeInit(void) -{ - /* Enable LTDC reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE); - /* Release LTDC from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, DISABLE); -} - -/** - * @brief Initializes the LTDC peripheral according to the specified parameters - * in the LTDC_InitStruct. - * @note This function can be used only when the LTDC is disabled. - * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure that contains - * the configuration information for the specified LTDC peripheral. - * @retval None - */ - -void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct) -{ - uint32_t horizontalsync = 0; - uint32_t accumulatedHBP = 0; - uint32_t accumulatedactiveW = 0; - uint32_t totalwidth = 0; - uint32_t backgreen = 0; - uint32_t backred = 0; - - /* Check function parameters */ - assert_param(IS_LTDC_HSYNC(LTDC_InitStruct->LTDC_HorizontalSync)); - assert_param(IS_LTDC_VSYNC(LTDC_InitStruct->LTDC_VerticalSync)); - assert_param(IS_LTDC_AHBP(LTDC_InitStruct->LTDC_AccumulatedHBP)); - assert_param(IS_LTDC_AVBP(LTDC_InitStruct->LTDC_AccumulatedVBP)); - assert_param(IS_LTDC_AAH(LTDC_InitStruct->LTDC_AccumulatedActiveH)); - assert_param(IS_LTDC_AAW(LTDC_InitStruct->LTDC_AccumulatedActiveW)); - assert_param(IS_LTDC_TOTALH(LTDC_InitStruct->LTDC_TotalHeigh)); - assert_param(IS_LTDC_TOTALW(LTDC_InitStruct->LTDC_TotalWidth)); - assert_param(IS_LTDC_HSPOL(LTDC_InitStruct->LTDC_HSPolarity)); - assert_param(IS_LTDC_VSPOL(LTDC_InitStruct->LTDC_VSPolarity)); - assert_param(IS_LTDC_DEPOL(LTDC_InitStruct->LTDC_DEPolarity)); - assert_param(IS_LTDC_PCPOL(LTDC_InitStruct->LTDC_PCPolarity)); - assert_param(IS_LTDC_BackBlueValue(LTDC_InitStruct->LTDC_BackgroundBlueValue)); - assert_param(IS_LTDC_BackGreenValue(LTDC_InitStruct->LTDC_BackgroundGreenValue)); - assert_param(IS_LTDC_BackRedValue(LTDC_InitStruct->LTDC_BackgroundRedValue)); - - /* Sets Synchronization size */ - LTDC->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); - horizontalsync = (LTDC_InitStruct->LTDC_HorizontalSync << 16); - LTDC->SSCR |= (horizontalsync | LTDC_InitStruct->LTDC_VerticalSync); - - /* Sets Accumulated Back porch */ - LTDC->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); - accumulatedHBP = (LTDC_InitStruct->LTDC_AccumulatedHBP << 16); - LTDC->BPCR |= (accumulatedHBP | LTDC_InitStruct->LTDC_AccumulatedVBP); - - /* Sets Accumulated Active Width */ - LTDC->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); - accumulatedactiveW = (LTDC_InitStruct->LTDC_AccumulatedActiveW << 16); - LTDC->AWCR |= (accumulatedactiveW | LTDC_InitStruct->LTDC_AccumulatedActiveH); - - /* Sets Total Width */ - LTDC->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); - totalwidth = (LTDC_InitStruct->LTDC_TotalWidth << 16); - LTDC->TWCR |= (totalwidth | LTDC_InitStruct->LTDC_TotalHeigh); - - LTDC->GCR &= (uint32_t)GCR_MASK; - LTDC->GCR |= (uint32_t)(LTDC_InitStruct->LTDC_HSPolarity | LTDC_InitStruct->LTDC_VSPolarity | \ - LTDC_InitStruct->LTDC_DEPolarity | LTDC_InitStruct->LTDC_PCPolarity); - - /* sets the background color value */ - backgreen = (LTDC_InitStruct->LTDC_BackgroundGreenValue << 8); - backred = (LTDC_InitStruct->LTDC_BackgroundRedValue << 16); - - LTDC->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); - LTDC->BCCR |= (backred | backgreen | LTDC_InitStruct->LTDC_BackgroundBlueValue); -} - -/** - * @brief Fills each LTDC_InitStruct member with its default value. - * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct) -{ - /*--------------- Reset LTDC init structure parameters values ----------------*/ - LTDC_InitStruct->LTDC_HSPolarity = LTDC_HSPolarity_AL; /*!< Initialize the LTDC_HSPolarity member */ - LTDC_InitStruct->LTDC_VSPolarity = LTDC_VSPolarity_AL; /*!< Initialize the LTDC_VSPolarity member */ - LTDC_InitStruct->LTDC_DEPolarity = LTDC_DEPolarity_AL; /*!< Initialize the LTDC_DEPolarity member */ - LTDC_InitStruct->LTDC_PCPolarity = LTDC_PCPolarity_IPC; /*!< Initialize the LTDC_PCPolarity member */ - LTDC_InitStruct->LTDC_HorizontalSync = 0x00; /*!< Initialize the LTDC_HorizontalSync member */ - LTDC_InitStruct->LTDC_VerticalSync = 0x00; /*!< Initialize the LTDC_VerticalSync member */ - LTDC_InitStruct->LTDC_AccumulatedHBP = 0x00; /*!< Initialize the LTDC_AccumulatedHBP member */ - LTDC_InitStruct->LTDC_AccumulatedVBP = 0x00; /*!< Initialize the LTDC_AccumulatedVBP member */ - LTDC_InitStruct->LTDC_AccumulatedActiveW = 0x00; /*!< Initialize the LTDC_AccumulatedActiveW member */ - LTDC_InitStruct->LTDC_AccumulatedActiveH = 0x00; /*!< Initialize the LTDC_AccumulatedActiveH member */ - LTDC_InitStruct->LTDC_TotalWidth = 0x00; /*!< Initialize the LTDC_TotalWidth member */ - LTDC_InitStruct->LTDC_TotalHeigh = 0x00; /*!< Initialize the LTDC_TotalHeigh member */ - LTDC_InitStruct->LTDC_BackgroundRedValue = 0x00; /*!< Initialize the LTDC_BackgroundRedValue member */ - LTDC_InitStruct->LTDC_BackgroundGreenValue = 0x00; /*!< Initialize the LTDC_BackgroundGreenValue member */ - LTDC_InitStruct->LTDC_BackgroundBlueValue = 0x00; /*!< Initialize the LTDC_BackgroundBlueValue member */ -} - -/** - * @brief Enables or disables the LTDC Controller. - * @param NewState: new state of the LTDC peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void LTDC_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable LTDC by setting LTDCEN bit */ - LTDC->GCR |= (uint32_t)LTDC_GCR_LTDCEN; - } - else - { - /* Disable LTDC by clearing LTDCEN bit */ - LTDC->GCR &= ~(uint32_t)LTDC_GCR_LTDCEN; - } -} - -/** - * @brief Enables or disables Dither. - * @param NewState: new state of the Dither. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void LTDC_DitherCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Dither by setting DTEN bit */ - LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN; - } - else - { - /* Disable Dither by clearing DTEN bit */ - LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN; - } -} - -/** - * @brief Get the dither RGB width. - * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure that contains - * the Dither RGB width. - * @retval None - */ - -LTDC_RGBTypeDef LTDC_GetRGBWidth(void) -{ - LTDC_RGBTypeDef LTDC_RGB_InitStruct; - - LTDC->GCR &= (uint32_t)GCR_MASK; - - LTDC_RGB_InitStruct.LTDC_BlueWidth = (uint32_t)((LTDC->GCR >> 4) & 0x7); - LTDC_RGB_InitStruct.LTDC_GreenWidth = (uint32_t)((LTDC->GCR >> 8) & 0x7); - LTDC_RGB_InitStruct.LTDC_RedWidth = (uint32_t)((LTDC->GCR >> 12) & 0x7); - - return LTDC_RGB_InitStruct; -} - -/** - * @brief Fills each LTDC_RGBStruct member with its default value. - * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct) -{ - LTDC_RGB_InitStruct->LTDC_BlueWidth = 0x02; - LTDC_RGB_InitStruct->LTDC_GreenWidth = 0x02; - LTDC_RGB_InitStruct->LTDC_RedWidth = 0x02; -} - - -/** - * @brief Define the position of the line interrupt . - * @param LTDC_LIPositionConfig: Line Interrupt Position. - * @retval None - */ - -void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LIPOS(LTDC_LIPositionConfig)); - - /* Sets the Line Interrupt position */ - LTDC->LIPCR = (uint32_t)LTDC_LIPositionConfig; -} - -/** - * @brief reload layers registers with new parameters - * @param LTDC_Reload: specifies the type of reload. - * This parameter can be one of the following values: - * @arg LTDC_IMReload: Vertical blanking reload. - * @arg LTDC_VBReload: Immediate reload. - * @retval None - */ - -void LTDC_ReloadConfig(uint32_t LTDC_Reload) -{ - /* Check the parameters */ - assert_param(IS_LTDC_RELOAD(LTDC_Reload)); - - /* Sets the Reload type */ - LTDC->SRCR = (uint32_t)LTDC_Reload; -} - - -/** - * @brief Initializes the LTDC Layer according to the specified parameters - * in the LTDC_LayerStruct. - * @note This function can be used only when the LTDC is disabled. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @param LTDC_LayerStruct: pointer to a LTDC_LayerTypeDef structure that contains - * the configuration information for the specified LTDC peripheral. - * @retval None - */ - -void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct) -{ - - uint32_t whsppos = 0; - uint32_t wvsppos = 0; - uint32_t dcgreen = 0; - uint32_t dcred = 0; - uint32_t dcalpha = 0; - uint32_t cfbp = 0; - -/* Check the parameters */ - assert_param(IS_LTDC_Pixelformat(LTDC_Layer_InitStruct->LTDC_PixelFormat)); - assert_param(IS_LTDC_BlendingFactor1(LTDC_Layer_InitStruct->LTDC_BlendingFactor_1)); - assert_param(IS_LTDC_BlendingFactor2(LTDC_Layer_InitStruct->LTDC_BlendingFactor_2)); - assert_param(IS_LTDC_HCONFIGST(LTDC_Layer_InitStruct->LTDC_HorizontalStart)); - assert_param(IS_LTDC_HCONFIGSP(LTDC_Layer_InitStruct->LTDC_HorizontalStop)); - assert_param(IS_LTDC_VCONFIGST(LTDC_Layer_InitStruct->LTDC_VerticalStart)); - assert_param(IS_LTDC_VCONFIGSP(LTDC_Layer_InitStruct->LTDC_VerticalStop)); - assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorBlue)); - assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorGreen)); - assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorRed)); - assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha)); - assert_param(IS_LTDC_CFBP(LTDC_Layer_InitStruct->LTDC_CFBPitch)); - assert_param(IS_LTDC_CFBLL(LTDC_Layer_InitStruct->LTDC_CFBLineLength)); - assert_param(IS_LTDC_CFBLNBR(LTDC_Layer_InitStruct->LTDC_CFBLineNumber)); - - /* Configures the horizontal start and stop position */ - whsppos = LTDC_Layer_InitStruct->LTDC_HorizontalStop << 16; - LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); - LTDC_Layerx->WHPCR = (LTDC_Layer_InitStruct->LTDC_HorizontalStart | whsppos); - - /* Configures the vertical start and stop position */ - wvsppos = LTDC_Layer_InitStruct->LTDC_VerticalStop << 16; - LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); - LTDC_Layerx->WVPCR = (LTDC_Layer_InitStruct->LTDC_VerticalStart | wvsppos); - - /* Specifies the pixel format */ - LTDC_Layerx->PFCR &= ~(LTDC_LxPFCR_PF); - LTDC_Layerx->PFCR = (LTDC_Layer_InitStruct->LTDC_PixelFormat); - - /* Configures the default color values */ - dcgreen = (LTDC_Layer_InitStruct->LTDC_DefaultColorGreen << 8); - dcred = (LTDC_Layer_InitStruct->LTDC_DefaultColorRed << 16); - dcalpha = (LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha << 24); - LTDC_Layerx->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); - LTDC_Layerx->DCCR = (LTDC_Layer_InitStruct->LTDC_DefaultColorBlue | dcgreen | \ - dcred | dcalpha); - - /* Specifies the constant alpha value */ - LTDC_Layerx->CACR &= ~(LTDC_LxCACR_CONSTA); - LTDC_Layerx->CACR = (LTDC_Layer_InitStruct->LTDC_ConstantAlpha); - - /* Specifies the blending factors */ - LTDC_Layerx->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); - LTDC_Layerx->BFCR = (LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 | LTDC_Layer_InitStruct->LTDC_BlendingFactor_2); - - /* Configures the color frame buffer start address */ - LTDC_Layerx->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); - LTDC_Layerx->CFBAR = (LTDC_Layer_InitStruct->LTDC_CFBStartAdress); - - /* Configures the color frame buffer pitch in byte */ - cfbp = (LTDC_Layer_InitStruct->LTDC_CFBPitch << 16); - LTDC_Layerx->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); - LTDC_Layerx->CFBLR = (LTDC_Layer_InitStruct->LTDC_CFBLineLength | cfbp); - - /* Configures the frame buffer line number */ - LTDC_Layerx->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); - LTDC_Layerx->CFBLNR = (LTDC_Layer_InitStruct->LTDC_CFBLineNumber); - -} - -/** - * @brief Fills each LTDC_Layer_InitStruct member with its default value. - * @param LTDC_Layer_InitStruct: pointer to a LTDC_LayerTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct) -{ - /*--------------- Reset Layer structure parameters values -------------------*/ - - /*!< Initialize the horizontal limit member */ - LTDC_Layer_InitStruct->LTDC_HorizontalStart = 0x00; - LTDC_Layer_InitStruct->LTDC_HorizontalStop = 0x00; - - /*!< Initialize the vertical limit member */ - LTDC_Layer_InitStruct->LTDC_VerticalStart = 0x00; - LTDC_Layer_InitStruct->LTDC_VerticalStop = 0x00; - - /*!< Initialize the pixel format member */ - LTDC_Layer_InitStruct->LTDC_PixelFormat = LTDC_Pixelformat_ARGB8888; - - /*!< Initialize the constant alpha value */ - LTDC_Layer_InitStruct->LTDC_ConstantAlpha = 0xFF; - - /*!< Initialize the default color values */ - LTDC_Layer_InitStruct->LTDC_DefaultColorBlue = 0x00; - LTDC_Layer_InitStruct->LTDC_DefaultColorGreen = 0x00; - LTDC_Layer_InitStruct->LTDC_DefaultColorRed = 0x00; - LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha = 0x00; - - /*!< Initialize the blending factors */ - LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 = LTDC_BlendingFactor1_PAxCA; - LTDC_Layer_InitStruct->LTDC_BlendingFactor_2 = LTDC_BlendingFactor2_PAxCA; - - /*!< Initialize the frame buffer start address */ - LTDC_Layer_InitStruct->LTDC_CFBStartAdress = 0x00; - - /*!< Initialize the frame buffer pitch and line length */ - LTDC_Layer_InitStruct->LTDC_CFBLineLength = 0x00; - LTDC_Layer_InitStruct->LTDC_CFBPitch = 0x00; - - /*!< Initialize the frame buffer line number */ - LTDC_Layer_InitStruct->LTDC_CFBLineNumber = 0x00; -} - - -/** - * @brief Enables or disables the LTDC_Layer Controller. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @param NewState: new state of the LTDC_Layer peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable LTDC_Layer by setting LEN bit */ - LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_LEN; - } - else - { - /* Disable LTDC_Layer by clearing LEN bit */ - LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_LEN; - } -} - - -/** - * @brief Get the current position. - * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure that contains - * the current position. - * @retval None - */ - -LTDC_PosTypeDef LTDC_GetPosStatus(void) -{ - LTDC_PosTypeDef LTDC_Pos_InitStruct; - - LTDC->CPSR &= ~(LTDC_CPSR_CYPOS | LTDC_CPSR_CXPOS); - - LTDC_Pos_InitStruct.LTDC_POSX = (uint32_t)(LTDC->CPSR >> 16); - LTDC_Pos_InitStruct.LTDC_POSY = (uint32_t)(LTDC->CPSR & 0xFFFF); - - return LTDC_Pos_InitStruct; -} - -/** - * @brief Fills each LTDC_Pos_InitStruct member with its default value. - * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct) -{ - LTDC_Pos_InitStruct->LTDC_POSX = 0x00; - LTDC_Pos_InitStruct->LTDC_POSY = 0x00; -} - -/** - * @brief Checks whether the specified LTDC's flag is set or not. - * @param LTDC_CD: specifies the flag to check. - * This parameter can be one of the following values: - * @arg LTDC_CD_VDES: vertical data enable current status. - * @arg LTDC_CD_HDES: horizontal data enable current status. - * @arg LTDC_CD_VSYNC: Vertical Synchronization current status. - * @arg LTDC_CD_HSYNC: Horizontal Synchronization current status. - * @retval The new state of LTDC_CD (SET or RESET). - */ - -FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD) -{ - FlagStatus bitstatus; - - /* Check the parameters */ - assert_param(IS_LTDC_GET_CD(LTDC_CD)); - - if ((LTDC->CDSR & LTDC_CD) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Set and configure the color keying. - * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef - * structure that contains the color keying configuration. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval None - */ - -void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState) -{ - uint32_t ckgreen = 0; - uint32_t ckred = 0; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue)); - assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen)); - assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed)); - - if (NewState != DISABLE) - { - /* Enable LTDC color keying by setting COLKEN bit */ - LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_COLKEN; - - /* Sets the color keying values */ - ckgreen = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen << 8); - ckred = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed << 16); - LTDC_Layerx->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); - LTDC_Layerx->CKCR |= (LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue | ckgreen | ckred); - } - else - { - /* Disable LTDC color keying by clearing COLKEN bit */ - LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; - } - - /* Reload shadow register */ - LTDC->SRCR = LTDC_IMReload; -} - -/** - * @brief Fills each LTDC_colorkeying_InitStruct member with its default value. - * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct) -{ - /*!< Initialize the color keying values */ - LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue = 0x00; - LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen = 0x00; - LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed = 0x00; -} - - -/** - * @brief Enables or disables CLUT. - * @param NewState: new state of CLUT. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable CLUT by setting CLUTEN bit */ - LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_CLUTEN; - } - else - { - /* Disable CLUT by clearing CLUTEN bit */ - LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; - } - - /* Reload shadow register */ - LTDC->SRCR = LTDC_IMReload; -} - -/** - * @brief configure the CLUT. - * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure that contains - * the CLUT configuration. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval None - */ - -void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct) -{ - uint32_t green = 0; - uint32_t red = 0; - uint32_t clutadd = 0; - - /* Check the parameters */ - assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_CLUTAdress)); - assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_RedValue)); - assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_GreenValue)); - assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_BlueValue)); - - /* Specifies the CLUT address and RGB value */ - green = (LTDC_CLUT_InitStruct->LTDC_GreenValue << 8); - red = (LTDC_CLUT_InitStruct->LTDC_RedValue << 16); - clutadd = (LTDC_CLUT_InitStruct->LTDC_CLUTAdress << 24); - LTDC_Layerx->CLUTWR = (clutadd | LTDC_CLUT_InitStruct->LTDC_BlueValue | \ - green | red); -} - -/** - * @brief Fills each LTDC_CLUT_InitStruct member with its default value. - * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct) -{ - /*!< Initialize the CLUT adress and RGB values */ - LTDC_CLUT_InitStruct->LTDC_CLUTAdress = 0x00; - LTDC_CLUT_InitStruct->LTDC_BlueValue = 0x00; - LTDC_CLUT_InitStruct->LTDC_GreenValue = 0x00; - LTDC_CLUT_InitStruct->LTDC_RedValue = 0x00; -} - - -/** - * @brief reconfigure the layer position. - * @param OffsetX: horizontal offset from start active width . - * @param OffsetY: vertical offset from start active height. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval Reload of the shadow registers values must be applied after layer - * position reconfiguration. - */ - -void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY) -{ - - uint32_t tempreg, temp; - uint32_t horizontal_start; - uint32_t horizontal_stop; - uint32_t vertical_start; - uint32_t vertical_stop; - - LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); - LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); - - /* Reconfigures the horizontal and vertical start position */ - tempreg = LTDC->BPCR; - horizontal_start = (tempreg >> 16) + 1 + OffsetX; - vertical_start = (tempreg & 0xFFFF) + 1 + OffsetY; - - /* Reconfigures the horizontal and vertical stop position */ - /* Get the number of byte per pixel */ - - tempreg = LTDC_Layerx->PFCR; - - if (tempreg == LTDC_Pixelformat_ARGB8888) - { - temp = 4; - } - else if (tempreg == LTDC_Pixelformat_RGB888) - { - temp = 3; - } - else if ((tempreg == LTDC_Pixelformat_ARGB4444) || - (tempreg == LTDC_Pixelformat_RGB565) || - (tempreg == LTDC_Pixelformat_ARGB1555) || - (tempreg == LTDC_Pixelformat_AL88)) - { - temp = 2; - } - else - { - temp = 1; - } - - tempreg = LTDC_Layerx->CFBLR; - horizontal_stop = (((tempreg & 0x1FFF) - 3)/temp) + horizontal_start - 1; - - tempreg = LTDC_Layerx->CFBLNR; - vertical_stop = (tempreg & 0x7FF) + vertical_start - 1; - - LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16); - LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16); -} - -/** - * @brief reconfigure constant alpha. - * @param ConstantAlpha: constant alpha value. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval Reload of the shadow registers values must be applied after constant - * alpha reconfiguration. - */ - -void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha) -{ - /* reconfigure the constant alpha value */ - LTDC_Layerx->CACR = ConstantAlpha; -} - -/** - * @brief reconfigure layer address. - * @param Address: The color frame buffer start address. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval Reload of the shadow registers values must be applied after layer - * address reconfiguration. - */ - -void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address) -{ - /* Reconfigures the color frame buffer start address */ - LTDC_Layerx->CFBAR = Address; -} - -/** - * @brief reconfigure layer size. - * @param Width: layer window width. - * @param Height: layer window height. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval Reload of the shadow registers values must be applied after layer - * size reconfiguration. - */ - -void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height) -{ - - uint8_t temp; - uint32_t tempreg; - uint32_t horizontal_start; - uint32_t horizontal_stop; - uint32_t vertical_start; - uint32_t vertical_stop; - - tempreg = LTDC_Layerx->PFCR; - - if (tempreg == LTDC_Pixelformat_ARGB8888) - { - temp = 4; - } - else if (tempreg == LTDC_Pixelformat_RGB888) - { - temp = 3; - } - else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \ - (tempreg == LTDC_Pixelformat_RGB565) || \ - (tempreg == LTDC_Pixelformat_ARGB1555) || \ - (tempreg == LTDC_Pixelformat_AL88)) - { - temp = 2; - } - else - { - temp = 1; - } - - /* update horizontal and vertical stop */ - tempreg = LTDC_Layerx->WHPCR; - horizontal_start = (tempreg & 0x1FFF); - horizontal_stop = Width + horizontal_start - 1; - - tempreg = LTDC_Layerx->WVPCR; - vertical_start = (tempreg & 0x1FFF); - vertical_stop = Height + vertical_start - 1; - - LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16); - LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16); - - /* Reconfigures the color frame buffer pitch in byte */ - LTDC_Layerx->CFBLR = ((Width * temp) << 16) | ((Width * temp) + 3); - - /* Reconfigures the frame buffer line number */ - LTDC_Layerx->CFBLNR = Height; - -} - -/** - * @brief reconfigure layer pixel format. - * @param PixelFormat: reconfigure the pixel format, this parameter can be - * one of the following values:@ref LTDC_Pixelformat. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval Reload of the shadow registers values must be applied after layer - * pixel format reconfiguration. - */ - -void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat) -{ - - uint8_t temp; - uint32_t tempreg; - - tempreg = LTDC_Layerx->PFCR; - - if (tempreg == LTDC_Pixelformat_ARGB8888) - { - temp = 4; - } - else if (tempreg == LTDC_Pixelformat_RGB888) - { - temp = 3; - } - else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \ - (tempreg == LTDC_Pixelformat_RGB565) || \ - (tempreg == LTDC_Pixelformat_ARGB1555) || \ - (tempreg == LTDC_Pixelformat_AL88)) - { - temp = 2; - } - else - { - temp = 1; - } - - tempreg = (LTDC_Layerx->CFBLR >> 16); - tempreg = (tempreg / temp); - - if (PixelFormat == LTDC_Pixelformat_ARGB8888) - { - temp = 4; - } - else if (PixelFormat == LTDC_Pixelformat_RGB888) - { - temp = 3; - } - else if ((PixelFormat == LTDC_Pixelformat_ARGB4444) || \ - (PixelFormat == LTDC_Pixelformat_RGB565) || \ - (PixelFormat == LTDC_Pixelformat_ARGB1555) || \ - (PixelFormat == LTDC_Pixelformat_AL88)) - { - temp = 2; - } - else - { - temp = 1; - } - - /* Reconfigures the color frame buffer pitch in byte */ - LTDC_Layerx->CFBLR = ((tempreg * temp) << 16) | ((tempreg * temp) + 3); - - /* Reconfigures the color frame buffer start address */ - LTDC_Layerx->PFCR = PixelFormat; - -} - -/** - * @} - */ - -/** @defgroup LTDC_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the LTDC Interrupts - and to get the status and clear flags and Interrupts pending bits. - - [..] The LTDC provides 4 Interrupts sources and 4 Flags - - *** Flags *** - ============= - [..] - (+) LTDC_FLAG_LI: Line Interrupt flag. - (+) LTDC_FLAG_FU: FIFO Underrun Interrupt flag. - (+) LTDC_FLAG_TERR: Transfer Error Interrupt flag. - (+) LTDC_FLAG_RR: Register Reload interrupt flag. - - *** Interrupts *** - ================== - [..] - (+) LTDC_IT_LI: Line Interrupt is generated when a programmed line - is reached. The line interrupt position is programmed in - the LTDC_LIPR register. - (+) LTDC_IT_FU: FIFO Underrun interrupt is generated when a pixel is requested - from an empty layer FIFO - (+) LTDC_IT_TERR: Transfer Error interrupt is generated when an AHB bus - error occurs during data transfer. - (+) LTDC_IT_RR: Register Reload interrupt is generated when the shadow - registers reload was performed during the vertical blanking - period. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified LTDC's interrupts. - * @param LTDC_IT: specifies the LTDC interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg LTDC_IT_LI: Line Interrupt Enable. - * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable. - * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable. - * @arg LTDC_IT_RR: Register Reload interrupt enable. - * @param NewState: new state of the specified LTDC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_LTDC_IT(LTDC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - LTDC->IER |= LTDC_IT; - } - else - { - LTDC->IER &= (uint32_t)~LTDC_IT; - } -} - -/** - * @brief Checks whether the specified LTDC's flag is set or not. - * @param LTDC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg LTDC_FLAG_LI: Line Interrupt flag. - * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag. - * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag. - * @arg LTDC_FLAG_RR: Register Reload interrupt flag. - * @retval The new state of LTDC_FLAG (SET or RESET). - */ -FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_LTDC_FLAG(LTDC_FLAG)); - - if ((LTDC->ISR & LTDC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the LTDC's pending flags. - * @param LTDC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg LTDC_FLAG_LI: Line Interrupt flag. - * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag. - * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag. - * @arg LTDC_FLAG_RR: Register Reload interrupt flag. - * @retval None - */ -void LTDC_ClearFlag(uint32_t LTDC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_LTDC_FLAG(LTDC_FLAG)); - - /* Clear the corresponding LTDC flag */ - LTDC->ICR = (uint32_t)LTDC_FLAG; -} - -/** - * @brief Checks whether the specified LTDC's interrupt has occurred or not. - * @param LTDC_IT: specifies the LTDC interrupts sources to check. - * This parameter can be one of the following values: - * @arg LTDC_IT_LI: Line Interrupt Enable. - * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable. - * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable. - * @arg LTDC_IT_RR: Register Reload interrupt Enable. - * @retval The new state of the LTDC_IT (SET or RESET). - */ -ITStatus LTDC_GetITStatus(uint32_t LTDC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_LTDC_IT(LTDC_IT)); - - if ((LTDC->ISR & LTDC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - if (((LTDC->IER & LTDC_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - - -/** - * @brief Clears the LTDC's interrupt pending bits. - * @param LTDC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg LTDC_IT_LIE: Line Interrupt. - * @arg LTDC_IT_FUIE: FIFO Underrun Interrupt. - * @arg LTDC_IT_TERRIE: Transfer Error Interrupt. - * @arg LTDC_IT_RRIE: Register Reload interrupt. - * @retval None - */ -void LTDC_ClearITPendingBit(uint32_t LTDC_IT) -{ - /* Check the parameters */ - assert_param(IS_LTDC_IT(LTDC_IT)); - - /* Clear the corresponding LTDC Interrupt */ - LTDC->ICR = (uint32_t)LTDC_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_ltdc.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the LTDC controller (LTDC) peripheral: + * + Initialization and configuration + * + Interrupts and flags management + * + * @verbatim + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable LTDC clock using + RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE) function. + (#) Configures LTDC + (++) Configure the required Pixel clock following the panel datasheet + (++) Configure the Synchronous timings: VSYNC, HSYNC, Vertical and + Horizontal back proch, active data area and the front proch + timings + (++) Configure the synchronous signals and clock polarity in the + LTDC_GCR register + (#) Configures Layer1/2 parameters + (++) The Layer window horizontal and vertical position in the LTDC_LxWHPCR and + LTDC_WVPCR registers. The layer window must be in the active data area. + (++) The pixel input format in the LTDC_LxPFCR register + (++) The color frame buffer start address in the LTDC_LxCFBAR register + (++) The line length and pitch of the color frame buffer in the + LTDC_LxCFBLR register + (++) The number of lines of the color frame buffer in + the LTDC_LxCFBLNR register + (++) if needed, load the CLUT with the RGB values and the address + in the LTDC_LxCLUTWR register + (++) If needed, configure the default color and the blending factors + respectively in the LTDC_LxDCCR and LTDC_LxBFCR registers + + (++) If needed, Dithering and color keying can be be enabled respectively + in the LTDC_GCR and LTDC_LxCKCR registers. It can be also enabled + on the fly. + (#) Enable Layer1/2 and if needed the CLUT in the LTDC_LxCR register + + (#) Reload the shadow registers to active register through + the LTDC_SRCR register. + -@- All layer parameters can be be modified on the fly except the CLUT. + The new configuration has to be either reloaded immediately + or during vertical blanking period by configuring the LTDC_SRCR register. + (#) Call the LTDC_Cmd() to enable the LTDC controller. + + @endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_ltdc.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup LTDC + * @brief LTDC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +#define GCR_MASK ((uint32_t)0x0FFE888F) /* LTDC GCR Mask */ + + +/** @defgroup LTDC_Private_Functions + * @{ + */ + +/** @defgroup LTDC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + (+) Enable or Disable Dither + (+) Define the position of the line interrupt + (+) reload layers registers with new parameters + (+) Initialize and configure layer1 and layer2 + (+) Set and configure the color keying functionality + (+) Configure and Enables or disables CLUT + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the LTDC peripheral registers to their default reset + * values. + * @param None + * @retval None + */ + +void LTDC_DeInit(void) +{ + /* Enable LTDC reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE); + /* Release LTDC from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, DISABLE); +} + +/** + * @brief Initializes the LTDC peripheral according to the specified parameters + * in the LTDC_InitStruct. + * @note This function can be used only when the LTDC is disabled. + * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure that contains + * the configuration information for the specified LTDC peripheral. + * @retval None + */ + +void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct) +{ + uint32_t horizontalsync = 0; + uint32_t accumulatedHBP = 0; + uint32_t accumulatedactiveW = 0; + uint32_t totalwidth = 0; + uint32_t backgreen = 0; + uint32_t backred = 0; + + /* Check function parameters */ + assert_param(IS_LTDC_HSYNC(LTDC_InitStruct->LTDC_HorizontalSync)); + assert_param(IS_LTDC_VSYNC(LTDC_InitStruct->LTDC_VerticalSync)); + assert_param(IS_LTDC_AHBP(LTDC_InitStruct->LTDC_AccumulatedHBP)); + assert_param(IS_LTDC_AVBP(LTDC_InitStruct->LTDC_AccumulatedVBP)); + assert_param(IS_LTDC_AAH(LTDC_InitStruct->LTDC_AccumulatedActiveH)); + assert_param(IS_LTDC_AAW(LTDC_InitStruct->LTDC_AccumulatedActiveW)); + assert_param(IS_LTDC_TOTALH(LTDC_InitStruct->LTDC_TotalHeigh)); + assert_param(IS_LTDC_TOTALW(LTDC_InitStruct->LTDC_TotalWidth)); + assert_param(IS_LTDC_HSPOL(LTDC_InitStruct->LTDC_HSPolarity)); + assert_param(IS_LTDC_VSPOL(LTDC_InitStruct->LTDC_VSPolarity)); + assert_param(IS_LTDC_DEPOL(LTDC_InitStruct->LTDC_DEPolarity)); + assert_param(IS_LTDC_PCPOL(LTDC_InitStruct->LTDC_PCPolarity)); + assert_param(IS_LTDC_BackBlueValue(LTDC_InitStruct->LTDC_BackgroundBlueValue)); + assert_param(IS_LTDC_BackGreenValue(LTDC_InitStruct->LTDC_BackgroundGreenValue)); + assert_param(IS_LTDC_BackRedValue(LTDC_InitStruct->LTDC_BackgroundRedValue)); + + /* Sets Synchronization size */ + LTDC->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); + horizontalsync = (LTDC_InitStruct->LTDC_HorizontalSync << 16); + LTDC->SSCR |= (horizontalsync | LTDC_InitStruct->LTDC_VerticalSync); + + /* Sets Accumulated Back porch */ + LTDC->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); + accumulatedHBP = (LTDC_InitStruct->LTDC_AccumulatedHBP << 16); + LTDC->BPCR |= (accumulatedHBP | LTDC_InitStruct->LTDC_AccumulatedVBP); + + /* Sets Accumulated Active Width */ + LTDC->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); + accumulatedactiveW = (LTDC_InitStruct->LTDC_AccumulatedActiveW << 16); + LTDC->AWCR |= (accumulatedactiveW | LTDC_InitStruct->LTDC_AccumulatedActiveH); + + /* Sets Total Width */ + LTDC->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); + totalwidth = (LTDC_InitStruct->LTDC_TotalWidth << 16); + LTDC->TWCR |= (totalwidth | LTDC_InitStruct->LTDC_TotalHeigh); + + LTDC->GCR &= (uint32_t)GCR_MASK; + LTDC->GCR |= (uint32_t)(LTDC_InitStruct->LTDC_HSPolarity | LTDC_InitStruct->LTDC_VSPolarity | \ + LTDC_InitStruct->LTDC_DEPolarity | LTDC_InitStruct->LTDC_PCPolarity); + + /* sets the background color value */ + backgreen = (LTDC_InitStruct->LTDC_BackgroundGreenValue << 8); + backred = (LTDC_InitStruct->LTDC_BackgroundRedValue << 16); + + LTDC->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); + LTDC->BCCR |= (backred | backgreen | LTDC_InitStruct->LTDC_BackgroundBlueValue); +} + +/** + * @brief Fills each LTDC_InitStruct member with its default value. + * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct) +{ + /*--------------- Reset LTDC init structure parameters values ----------------*/ + LTDC_InitStruct->LTDC_HSPolarity = LTDC_HSPolarity_AL; /*!< Initialize the LTDC_HSPolarity member */ + LTDC_InitStruct->LTDC_VSPolarity = LTDC_VSPolarity_AL; /*!< Initialize the LTDC_VSPolarity member */ + LTDC_InitStruct->LTDC_DEPolarity = LTDC_DEPolarity_AL; /*!< Initialize the LTDC_DEPolarity member */ + LTDC_InitStruct->LTDC_PCPolarity = LTDC_PCPolarity_IPC; /*!< Initialize the LTDC_PCPolarity member */ + LTDC_InitStruct->LTDC_HorizontalSync = 0x00; /*!< Initialize the LTDC_HorizontalSync member */ + LTDC_InitStruct->LTDC_VerticalSync = 0x00; /*!< Initialize the LTDC_VerticalSync member */ + LTDC_InitStruct->LTDC_AccumulatedHBP = 0x00; /*!< Initialize the LTDC_AccumulatedHBP member */ + LTDC_InitStruct->LTDC_AccumulatedVBP = 0x00; /*!< Initialize the LTDC_AccumulatedVBP member */ + LTDC_InitStruct->LTDC_AccumulatedActiveW = 0x00; /*!< Initialize the LTDC_AccumulatedActiveW member */ + LTDC_InitStruct->LTDC_AccumulatedActiveH = 0x00; /*!< Initialize the LTDC_AccumulatedActiveH member */ + LTDC_InitStruct->LTDC_TotalWidth = 0x00; /*!< Initialize the LTDC_TotalWidth member */ + LTDC_InitStruct->LTDC_TotalHeigh = 0x00; /*!< Initialize the LTDC_TotalHeigh member */ + LTDC_InitStruct->LTDC_BackgroundRedValue = 0x00; /*!< Initialize the LTDC_BackgroundRedValue member */ + LTDC_InitStruct->LTDC_BackgroundGreenValue = 0x00; /*!< Initialize the LTDC_BackgroundGreenValue member */ + LTDC_InitStruct->LTDC_BackgroundBlueValue = 0x00; /*!< Initialize the LTDC_BackgroundBlueValue member */ +} + +/** + * @brief Enables or disables the LTDC Controller. + * @param NewState: new state of the LTDC peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void LTDC_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable LTDC by setting LTDCEN bit */ + LTDC->GCR |= (uint32_t)LTDC_GCR_LTDCEN; + } + else + { + /* Disable LTDC by clearing LTDCEN bit */ + LTDC->GCR &= ~(uint32_t)LTDC_GCR_LTDCEN; + } +} + +/** + * @brief Enables or disables Dither. + * @param NewState: new state of the Dither. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void LTDC_DitherCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Dither by setting DTEN bit */ + LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN; + } + else + { + /* Disable Dither by clearing DTEN bit */ + LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN; + } +} + +/** + * @brief Get the dither RGB width. + * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure that contains + * the Dither RGB width. + * @retval None + */ + +LTDC_RGBTypeDef LTDC_GetRGBWidth(void) +{ + LTDC_RGBTypeDef LTDC_RGB_InitStruct; + + LTDC->GCR &= (uint32_t)GCR_MASK; + + LTDC_RGB_InitStruct.LTDC_BlueWidth = (uint32_t)((LTDC->GCR >> 4) & 0x7); + LTDC_RGB_InitStruct.LTDC_GreenWidth = (uint32_t)((LTDC->GCR >> 8) & 0x7); + LTDC_RGB_InitStruct.LTDC_RedWidth = (uint32_t)((LTDC->GCR >> 12) & 0x7); + + return LTDC_RGB_InitStruct; +} + +/** + * @brief Fills each LTDC_RGBStruct member with its default value. + * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct) +{ + LTDC_RGB_InitStruct->LTDC_BlueWidth = 0x02; + LTDC_RGB_InitStruct->LTDC_GreenWidth = 0x02; + LTDC_RGB_InitStruct->LTDC_RedWidth = 0x02; +} + + +/** + * @brief Define the position of the line interrupt . + * @param LTDC_LIPositionConfig: Line Interrupt Position. + * @retval None + */ + +void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LIPOS(LTDC_LIPositionConfig)); + + /* Sets the Line Interrupt position */ + LTDC->LIPCR = (uint32_t)LTDC_LIPositionConfig; +} + +/** + * @brief reload layers registers with new parameters + * @param LTDC_Reload: specifies the type of reload. + * This parameter can be one of the following values: + * @arg LTDC_IMReload: Vertical blanking reload. + * @arg LTDC_VBReload: Immediate reload. + * @retval None + */ + +void LTDC_ReloadConfig(uint32_t LTDC_Reload) +{ + /* Check the parameters */ + assert_param(IS_LTDC_RELOAD(LTDC_Reload)); + + /* Sets the Reload type */ + LTDC->SRCR = (uint32_t)LTDC_Reload; +} + + +/** + * @brief Initializes the LTDC Layer according to the specified parameters + * in the LTDC_LayerStruct. + * @note This function can be used only when the LTDC is disabled. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @param LTDC_LayerStruct: pointer to a LTDC_LayerTypeDef structure that contains + * the configuration information for the specified LTDC peripheral. + * @retval None + */ + +void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct) +{ + + uint32_t whsppos = 0; + uint32_t wvsppos = 0; + uint32_t dcgreen = 0; + uint32_t dcred = 0; + uint32_t dcalpha = 0; + uint32_t cfbp = 0; + +/* Check the parameters */ + assert_param(IS_LTDC_Pixelformat(LTDC_Layer_InitStruct->LTDC_PixelFormat)); + assert_param(IS_LTDC_BlendingFactor1(LTDC_Layer_InitStruct->LTDC_BlendingFactor_1)); + assert_param(IS_LTDC_BlendingFactor2(LTDC_Layer_InitStruct->LTDC_BlendingFactor_2)); + assert_param(IS_LTDC_HCONFIGST(LTDC_Layer_InitStruct->LTDC_HorizontalStart)); + assert_param(IS_LTDC_HCONFIGSP(LTDC_Layer_InitStruct->LTDC_HorizontalStop)); + assert_param(IS_LTDC_VCONFIGST(LTDC_Layer_InitStruct->LTDC_VerticalStart)); + assert_param(IS_LTDC_VCONFIGSP(LTDC_Layer_InitStruct->LTDC_VerticalStop)); + assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorBlue)); + assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorGreen)); + assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorRed)); + assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha)); + assert_param(IS_LTDC_CFBP(LTDC_Layer_InitStruct->LTDC_CFBPitch)); + assert_param(IS_LTDC_CFBLL(LTDC_Layer_InitStruct->LTDC_CFBLineLength)); + assert_param(IS_LTDC_CFBLNBR(LTDC_Layer_InitStruct->LTDC_CFBLineNumber)); + + /* Configures the horizontal start and stop position */ + whsppos = LTDC_Layer_InitStruct->LTDC_HorizontalStop << 16; + LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + LTDC_Layerx->WHPCR = (LTDC_Layer_InitStruct->LTDC_HorizontalStart | whsppos); + + /* Configures the vertical start and stop position */ + wvsppos = LTDC_Layer_InitStruct->LTDC_VerticalStop << 16; + LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + LTDC_Layerx->WVPCR = (LTDC_Layer_InitStruct->LTDC_VerticalStart | wvsppos); + + /* Specifies the pixel format */ + LTDC_Layerx->PFCR &= ~(LTDC_LxPFCR_PF); + LTDC_Layerx->PFCR = (LTDC_Layer_InitStruct->LTDC_PixelFormat); + + /* Configures the default color values */ + dcgreen = (LTDC_Layer_InitStruct->LTDC_DefaultColorGreen << 8); + dcred = (LTDC_Layer_InitStruct->LTDC_DefaultColorRed << 16); + dcalpha = (LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha << 24); + LTDC_Layerx->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); + LTDC_Layerx->DCCR = (LTDC_Layer_InitStruct->LTDC_DefaultColorBlue | dcgreen | \ + dcred | dcalpha); + + /* Specifies the constant alpha value */ + LTDC_Layerx->CACR &= ~(LTDC_LxCACR_CONSTA); + LTDC_Layerx->CACR = (LTDC_Layer_InitStruct->LTDC_ConstantAlpha); + + /* Specifies the blending factors */ + LTDC_Layerx->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); + LTDC_Layerx->BFCR = (LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 | LTDC_Layer_InitStruct->LTDC_BlendingFactor_2); + + /* Configures the color frame buffer start address */ + LTDC_Layerx->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); + LTDC_Layerx->CFBAR = (LTDC_Layer_InitStruct->LTDC_CFBStartAdress); + + /* Configures the color frame buffer pitch in byte */ + cfbp = (LTDC_Layer_InitStruct->LTDC_CFBPitch << 16); + LTDC_Layerx->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); + LTDC_Layerx->CFBLR = (LTDC_Layer_InitStruct->LTDC_CFBLineLength | cfbp); + + /* Configures the frame buffer line number */ + LTDC_Layerx->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); + LTDC_Layerx->CFBLNR = (LTDC_Layer_InitStruct->LTDC_CFBLineNumber); + +} + +/** + * @brief Fills each LTDC_Layer_InitStruct member with its default value. + * @param LTDC_Layer_InitStruct: pointer to a LTDC_LayerTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct) +{ + /*--------------- Reset Layer structure parameters values -------------------*/ + + /*!< Initialize the horizontal limit member */ + LTDC_Layer_InitStruct->LTDC_HorizontalStart = 0x00; + LTDC_Layer_InitStruct->LTDC_HorizontalStop = 0x00; + + /*!< Initialize the vertical limit member */ + LTDC_Layer_InitStruct->LTDC_VerticalStart = 0x00; + LTDC_Layer_InitStruct->LTDC_VerticalStop = 0x00; + + /*!< Initialize the pixel format member */ + LTDC_Layer_InitStruct->LTDC_PixelFormat = LTDC_Pixelformat_ARGB8888; + + /*!< Initialize the constant alpha value */ + LTDC_Layer_InitStruct->LTDC_ConstantAlpha = 0xFF; + + /*!< Initialize the default color values */ + LTDC_Layer_InitStruct->LTDC_DefaultColorBlue = 0x00; + LTDC_Layer_InitStruct->LTDC_DefaultColorGreen = 0x00; + LTDC_Layer_InitStruct->LTDC_DefaultColorRed = 0x00; + LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha = 0x00; + + /*!< Initialize the blending factors */ + LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 = LTDC_BlendingFactor1_PAxCA; + LTDC_Layer_InitStruct->LTDC_BlendingFactor_2 = LTDC_BlendingFactor2_PAxCA; + + /*!< Initialize the frame buffer start address */ + LTDC_Layer_InitStruct->LTDC_CFBStartAdress = 0x00; + + /*!< Initialize the frame buffer pitch and line length */ + LTDC_Layer_InitStruct->LTDC_CFBLineLength = 0x00; + LTDC_Layer_InitStruct->LTDC_CFBPitch = 0x00; + + /*!< Initialize the frame buffer line number */ + LTDC_Layer_InitStruct->LTDC_CFBLineNumber = 0x00; +} + + +/** + * @brief Enables or disables the LTDC_Layer Controller. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @param NewState: new state of the LTDC_Layer peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable LTDC_Layer by setting LEN bit */ + LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_LEN; + } + else + { + /* Disable LTDC_Layer by clearing LEN bit */ + LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_LEN; + } +} + + +/** + * @brief Get the current position. + * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure that contains + * the current position. + * @retval None + */ + +LTDC_PosTypeDef LTDC_GetPosStatus(void) +{ + LTDC_PosTypeDef LTDC_Pos_InitStruct; + + LTDC->CPSR &= ~(LTDC_CPSR_CYPOS | LTDC_CPSR_CXPOS); + + LTDC_Pos_InitStruct.LTDC_POSX = (uint32_t)(LTDC->CPSR >> 16); + LTDC_Pos_InitStruct.LTDC_POSY = (uint32_t)(LTDC->CPSR & 0xFFFF); + + return LTDC_Pos_InitStruct; +} + +/** + * @brief Fills each LTDC_Pos_InitStruct member with its default value. + * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct) +{ + LTDC_Pos_InitStruct->LTDC_POSX = 0x00; + LTDC_Pos_InitStruct->LTDC_POSY = 0x00; +} + +/** + * @brief Checks whether the specified LTDC's flag is set or not. + * @param LTDC_CD: specifies the flag to check. + * This parameter can be one of the following values: + * @arg LTDC_CD_VDES: vertical data enable current status. + * @arg LTDC_CD_HDES: horizontal data enable current status. + * @arg LTDC_CD_VSYNC: Vertical Synchronization current status. + * @arg LTDC_CD_HSYNC: Horizontal Synchronization current status. + * @retval The new state of LTDC_CD (SET or RESET). + */ + +FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD) +{ + FlagStatus bitstatus; + + /* Check the parameters */ + assert_param(IS_LTDC_GET_CD(LTDC_CD)); + + if ((LTDC->CDSR & LTDC_CD) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Set and configure the color keying. + * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef + * structure that contains the color keying configuration. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval None + */ + +void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState) +{ + uint32_t ckgreen = 0; + uint32_t ckred = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue)); + assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen)); + assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed)); + + if (NewState != DISABLE) + { + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Sets the color keying values */ + ckgreen = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen << 8); + ckred = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed << 16); + LTDC_Layerx->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_Layerx->CKCR |= (LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue | ckgreen | ckred); + } + else + { + /* Disable LTDC color keying by clearing COLKEN bit */ + LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + } + + /* Reload shadow register */ + LTDC->SRCR = LTDC_IMReload; +} + +/** + * @brief Fills each LTDC_colorkeying_InitStruct member with its default value. + * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct) +{ + /*!< Initialize the color keying values */ + LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue = 0x00; + LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen = 0x00; + LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed = 0x00; +} + + +/** + * @brief Enables or disables CLUT. + * @param NewState: new state of CLUT. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable CLUT by setting CLUTEN bit */ + LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + } + else + { + /* Disable CLUT by clearing CLUTEN bit */ + LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + } + + /* Reload shadow register */ + LTDC->SRCR = LTDC_IMReload; +} + +/** + * @brief configure the CLUT. + * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure that contains + * the CLUT configuration. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval None + */ + +void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct) +{ + uint32_t green = 0; + uint32_t red = 0; + uint32_t clutadd = 0; + + /* Check the parameters */ + assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_CLUTAdress)); + assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_RedValue)); + assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_GreenValue)); + assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_BlueValue)); + + /* Specifies the CLUT address and RGB value */ + green = (LTDC_CLUT_InitStruct->LTDC_GreenValue << 8); + red = (LTDC_CLUT_InitStruct->LTDC_RedValue << 16); + clutadd = (LTDC_CLUT_InitStruct->LTDC_CLUTAdress << 24); + LTDC_Layerx->CLUTWR = (clutadd | LTDC_CLUT_InitStruct->LTDC_BlueValue | \ + green | red); +} + +/** + * @brief Fills each LTDC_CLUT_InitStruct member with its default value. + * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct) +{ + /*!< Initialize the CLUT adress and RGB values */ + LTDC_CLUT_InitStruct->LTDC_CLUTAdress = 0x00; + LTDC_CLUT_InitStruct->LTDC_BlueValue = 0x00; + LTDC_CLUT_InitStruct->LTDC_GreenValue = 0x00; + LTDC_CLUT_InitStruct->LTDC_RedValue = 0x00; +} + + +/** + * @brief reconfigure the layer position. + * @param OffsetX: horizontal offset from start active width . + * @param OffsetY: vertical offset from start active height. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval Reload of the shadow registers values must be applied after layer + * position reconfiguration. + */ + +void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY) +{ + + uint32_t tempreg, temp; + uint32_t horizontal_start; + uint32_t horizontal_stop; + uint32_t vertical_start; + uint32_t vertical_stop; + + LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + + /* Reconfigures the horizontal and vertical start position */ + tempreg = LTDC->BPCR; + horizontal_start = (tempreg >> 16) + 1 + OffsetX; + vertical_start = (tempreg & 0xFFFF) + 1 + OffsetY; + + /* Reconfigures the horizontal and vertical stop position */ + /* Get the number of byte per pixel */ + + tempreg = LTDC_Layerx->PFCR; + + if (tempreg == LTDC_Pixelformat_ARGB8888) + { + temp = 4; + } + else if (tempreg == LTDC_Pixelformat_RGB888) + { + temp = 3; + } + else if ((tempreg == LTDC_Pixelformat_ARGB4444) || + (tempreg == LTDC_Pixelformat_RGB565) || + (tempreg == LTDC_Pixelformat_ARGB1555) || + (tempreg == LTDC_Pixelformat_AL88)) + { + temp = 2; + } + else + { + temp = 1; + } + + tempreg = LTDC_Layerx->CFBLR; + horizontal_stop = (((tempreg & 0x1FFF) - 3)/temp) + horizontal_start - 1; + + tempreg = LTDC_Layerx->CFBLNR; + vertical_stop = (tempreg & 0x7FF) + vertical_start - 1; + + LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16); + LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16); +} + +/** + * @brief reconfigure constant alpha. + * @param ConstantAlpha: constant alpha value. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval Reload of the shadow registers values must be applied after constant + * alpha reconfiguration. + */ + +void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha) +{ + /* reconfigure the constant alpha value */ + LTDC_Layerx->CACR = ConstantAlpha; +} + +/** + * @brief reconfigure layer address. + * @param Address: The color frame buffer start address. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval Reload of the shadow registers values must be applied after layer + * address reconfiguration. + */ + +void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address) +{ + /* Reconfigures the color frame buffer start address */ + LTDC_Layerx->CFBAR = Address; +} + +/** + * @brief reconfigure layer size. + * @param Width: layer window width. + * @param Height: layer window height. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval Reload of the shadow registers values must be applied after layer + * size reconfiguration. + */ + +void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height) +{ + + uint8_t temp; + uint32_t tempreg; + uint32_t horizontal_start; + uint32_t horizontal_stop; + uint32_t vertical_start; + uint32_t vertical_stop; + + tempreg = LTDC_Layerx->PFCR; + + if (tempreg == LTDC_Pixelformat_ARGB8888) + { + temp = 4; + } + else if (tempreg == LTDC_Pixelformat_RGB888) + { + temp = 3; + } + else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \ + (tempreg == LTDC_Pixelformat_RGB565) || \ + (tempreg == LTDC_Pixelformat_ARGB1555) || \ + (tempreg == LTDC_Pixelformat_AL88)) + { + temp = 2; + } + else + { + temp = 1; + } + + /* update horizontal and vertical stop */ + tempreg = LTDC_Layerx->WHPCR; + horizontal_start = (tempreg & 0x1FFF); + horizontal_stop = Width + horizontal_start - 1; + + tempreg = LTDC_Layerx->WVPCR; + vertical_start = (tempreg & 0x1FFF); + vertical_stop = Height + vertical_start - 1; + + LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16); + LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16); + + /* Reconfigures the color frame buffer pitch in byte */ + LTDC_Layerx->CFBLR = ((Width * temp) << 16) | ((Width * temp) + 3); + + /* Reconfigures the frame buffer line number */ + LTDC_Layerx->CFBLNR = Height; + +} + +/** + * @brief reconfigure layer pixel format. + * @param PixelFormat: reconfigure the pixel format, this parameter can be + * one of the following values:@ref LTDC_Pixelformat. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval Reload of the shadow registers values must be applied after layer + * pixel format reconfiguration. + */ + +void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat) +{ + + uint8_t temp; + uint32_t tempreg; + + tempreg = LTDC_Layerx->PFCR; + + if (tempreg == LTDC_Pixelformat_ARGB8888) + { + temp = 4; + } + else if (tempreg == LTDC_Pixelformat_RGB888) + { + temp = 3; + } + else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \ + (tempreg == LTDC_Pixelformat_RGB565) || \ + (tempreg == LTDC_Pixelformat_ARGB1555) || \ + (tempreg == LTDC_Pixelformat_AL88)) + { + temp = 2; + } + else + { + temp = 1; + } + + tempreg = (LTDC_Layerx->CFBLR >> 16); + tempreg = (tempreg / temp); + + if (PixelFormat == LTDC_Pixelformat_ARGB8888) + { + temp = 4; + } + else if (PixelFormat == LTDC_Pixelformat_RGB888) + { + temp = 3; + } + else if ((PixelFormat == LTDC_Pixelformat_ARGB4444) || \ + (PixelFormat == LTDC_Pixelformat_RGB565) || \ + (PixelFormat == LTDC_Pixelformat_ARGB1555) || \ + (PixelFormat == LTDC_Pixelformat_AL88)) + { + temp = 2; + } + else + { + temp = 1; + } + + /* Reconfigures the color frame buffer pitch in byte */ + LTDC_Layerx->CFBLR = ((tempreg * temp) << 16) | ((tempreg * temp) + 3); + + /* Reconfigures the color frame buffer start address */ + LTDC_Layerx->PFCR = PixelFormat; + +} + +/** + * @} + */ + +/** @defgroup LTDC_Group2 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure the LTDC Interrupts + and to get the status and clear flags and Interrupts pending bits. + + [..] The LTDC provides 4 Interrupts sources and 4 Flags + + *** Flags *** + ============= + [..] + (+) LTDC_FLAG_LI: Line Interrupt flag. + (+) LTDC_FLAG_FU: FIFO Underrun Interrupt flag. + (+) LTDC_FLAG_TERR: Transfer Error Interrupt flag. + (+) LTDC_FLAG_RR: Register Reload interrupt flag. + + *** Interrupts *** + ================== + [..] + (+) LTDC_IT_LI: Line Interrupt is generated when a programmed line + is reached. The line interrupt position is programmed in + the LTDC_LIPR register. + (+) LTDC_IT_FU: FIFO Underrun interrupt is generated when a pixel is requested + from an empty layer FIFO + (+) LTDC_IT_TERR: Transfer Error interrupt is generated when an AHB bus + error occurs during data transfer. + (+) LTDC_IT_RR: Register Reload interrupt is generated when the shadow + registers reload was performed during the vertical blanking + period. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified LTDC's interrupts. + * @param LTDC_IT: specifies the LTDC interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt Enable. + * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable. + * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable. + * @arg LTDC_IT_RR: Register Reload interrupt enable. + * @param NewState: new state of the specified LTDC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_LTDC_IT(LTDC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + LTDC->IER |= LTDC_IT; + } + else + { + LTDC->IER &= (uint32_t)~LTDC_IT; + } +} + +/** + * @brief Checks whether the specified LTDC's flag is set or not. + * @param LTDC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag. + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag. + * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag. + * @arg LTDC_FLAG_RR: Register Reload interrupt flag. + * @retval The new state of LTDC_FLAG (SET or RESET). + */ +FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_LTDC_FLAG(LTDC_FLAG)); + + if ((LTDC->ISR & LTDC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the LTDC's pending flags. + * @param LTDC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag. + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag. + * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag. + * @arg LTDC_FLAG_RR: Register Reload interrupt flag. + * @retval None + */ +void LTDC_ClearFlag(uint32_t LTDC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_LTDC_FLAG(LTDC_FLAG)); + + /* Clear the corresponding LTDC flag */ + LTDC->ICR = (uint32_t)LTDC_FLAG; +} + +/** + * @brief Checks whether the specified LTDC's interrupt has occurred or not. + * @param LTDC_IT: specifies the LTDC interrupts sources to check. + * This parameter can be one of the following values: + * @arg LTDC_IT_LI: Line Interrupt Enable. + * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable. + * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable. + * @arg LTDC_IT_RR: Register Reload interrupt Enable. + * @retval The new state of the LTDC_IT (SET or RESET). + */ +ITStatus LTDC_GetITStatus(uint32_t LTDC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_LTDC_IT(LTDC_IT)); + + if ((LTDC->ISR & LTDC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + if (((LTDC->IER & LTDC_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + + +/** + * @brief Clears the LTDC's interrupt pending bits. + * @param LTDC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LIE: Line Interrupt. + * @arg LTDC_IT_FUIE: FIFO Underrun Interrupt. + * @arg LTDC_IT_TERRIE: Transfer Error Interrupt. + * @arg LTDC_IT_RRIE: Register Reload interrupt. + * @retval None + */ +void LTDC_ClearITPendingBit(uint32_t LTDC_IT) +{ + /* Check the parameters */ + assert_param(IS_LTDC_IT(LTDC_IT)); + + /* Clear the corresponding LTDC Interrupt */ + LTDC->ICR = (uint32_t)LTDC_IT; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c index 8fce4b19e..1c797825d 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c @@ -1,939 +1,939 @@ -/** - ****************************************************************************** - * @file stm32f4xx_pwr.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Backup Domain Access - * + PVD configuration - * + WakeUp pin configuration - * + Main and Backup Regulators configuration - * + FLASH Power Down configuration - * + Low Power modes configuration - * + Flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_pwr.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* Alias word address of FPDS bit */ -#define FPDS_BitNumber 0x09 -#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) - -/* Alias word address of PMODE bit */ -#define PMODE_BitNumber 0x0E -#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) - -/* Alias word address of ODEN bit */ -#define ODEN_BitNumber 0x10 -#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4)) - -/* Alias word address of ODSWEN bit */ -#define ODSWEN_BitNumber 0x11 -#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4)) - -/* Alias word address of MRLVDS bit */ -#define MRLVDS_BitNumber 0x0B -#define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4)) - -/* Alias word address of LPLVDS bit */ -#define LPLVDS_BitNumber 0x0A -#define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* Alias word address of BRE bit */ -#define BRE_BitNumber 0x09 -#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFF3FC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) -#define CR_VOS_MASK ((uint32_t)0xFFFF3FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** @defgroup PWR_Group1 Backup Domain Access function - * @brief Backup Domain Access function - * -@verbatim - =============================================================================== - ##### Backup Domain Access function ##### - =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @param NewState: new state of the access to the backup domain. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group2 PVD configuration functions - * @brief PVD configuration functions - * -@verbatim - =============================================================================== - ##### PVD configuration functions ##### - =============================================================================== - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled through the EXTI registers. - (+) The PVD is stopped in Standby mode. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_0 - * @arg PWR_PVDLevel_1 - * @arg PWR_PVDLevel_2 - * @arg PWR_PVDLevel_3 - * @arg PWR_PVDLevel_4 - * @arg PWR_PVDLevel_5 - * @arg PWR_PVDLevel_6 - * @arg PWR_PVDLevel_7 - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - - tmpreg = PWR->CR; - - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group3 WakeUp pin configuration functions - * @brief WakeUp pin configuration functions - * -@verbatim - =============================================================================== - ##### WakeUp pin configuration functions ##### - =============================================================================== - [..] - (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is - forced in input pull down configuration and is active on rising edges. - (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions - * @brief Main and Backup Regulators configuration functions - * -@verbatim - =============================================================================== - ##### Main and Backup Regulators configuration functions ##### - =============================================================================== - [..] - (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from - the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is - retained even in Standby or VBAT mode when the low power backup regulator - is enabled. It can be considered as an internal EEPROM when VBAT is - always present. You can use the PWR_BackupRegulatorCmd() function to - enable the low power backup regulator and use the PWR_GetFlagStatus - (PWR_FLAG_BRR) to check if it is ready or not. - - (+) When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to - save battery life. - - (+) The backup SRAM is not mass erased by an tamper event. It is read - protected to prevent confidential data, such as cryptographic private - key, from being accessed. The backup SRAM can be erased only through - the Flash interface when a protection level change from level 1 to - level 0 is requested. - -@- Refer to the description of Read protection (RDP) in the reference manual. - - (+) The main internal regulator can be configured to have a tradeoff between - performance and power consumption when the device does not operate at - the maximum frequency. - (+) For STM32F405xx/407xx and STM32F415xx/417xx Devices, the regulator can be - configured on the fly through PWR_MainRegulatorModeConfig() function which - configure VOS bit in PWR_CR register: - (++) When this bit is set (Regulator voltage output Scale 1 mode selected) - the System frequency can go up to 168 MHz. - (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) - the System frequency can go up to 144 MHz. - - (+) For STM32F42xxx/43xxx Devices, the regulator can be configured through - PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in - PWR_CR register: - which configure VOS[1:0] bits in PWR_CR register: - (++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected) - the System frequency can go up to 168 MHz. - (++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected) - the System frequency can go up to 144 MHz. - (++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected) - the System frequency can go up to 120 MHz. - - (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL - is OFF and the HSI or HSE clock source is selected as system clock. - The new value programmed is active only when the PLL is ON. - When the PLL is OFF, the voltage scale 3 is automatically selected. - Refer to the datasheets for more details. - - (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has - 2 operating modes available: - (++) Normal mode: The CPU and core logic operate at maximum frequency at a given - voltage scaling (scale 1, scale 2 or scale 3) - (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a - higher frequency than the normal mode for a given voltage scaling (scale 1, - scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and - PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow - the sequence described in Reference manual. - - (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator - supplies a low power voltage to the 1.2V domain, thus preserving the content of registers - and internal SRAM. 2 operating modes are available: - (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only - available when the main regulator or the low power regulator is used in Scale 3 or - low voltage mode. - (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only - available when the main regulator or the low power regulator is in low voltage mode. - This mode is enabled through PWR_UnderDriveCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Backup Regulator. - * @param NewState: new state of the Backup Regulator. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupRegulatorCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the main internal regulator output voltage. - * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). - * This parameter can be one of the following values: - * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, - * System frequency up to 168 MHz. - * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, - * System frequency up to 144 MHz. - * @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode, - * System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices) - * @retval None - */ -void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage)); - - tmpreg = PWR->CR; - - /* Clear VOS[15:14] bits */ - tmpreg &= CR_VOS_MASK; - - /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */ - tmpreg |= PWR_Regulator_Voltage; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Over-Drive. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx devices. - * This mode allows the CPU and the core logic to operate at a higher frequency - * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). - * - * @note It is recommended to enter or exit Over-drive mode when the application is not running - * critical tasks and when the system clock source is either HSI or HSE. - * During the Over-drive switch activation, no peripheral clocks should be enabled. - * The peripheral clocks must be enabled once the Over-drive mode is activated. - * - * @param NewState: new state of the Over Drive mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_OverDriveCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Set/Reset the ODEN bit to enable/disable the Over Drive mode */ - *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Over-Drive switching. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx devices. - * - * @param NewState: new state of the Over Drive switching mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_OverDriveSWCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */ - *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Under-Drive mode. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx devices. - * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main regulator or the low power regulator - * is in low voltage mode - * - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage regulator operates in Under-drive mode, an additional - * startup delay is induced when waking up from Stop mode. - * - * @param NewState: new state of the Under Drive mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_UnderDriveCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the UDEN[1:0] bits to enable the Under Drive mode */ - PWR->CR |= (uint32_t)PWR_CR_UDEN; - } - else - { - /* Reset the UDEN[1:0] bits to disable the Under Drive mode */ - PWR->CR &= (uint32_t)(~PWR_CR_UDEN); - } -} - -/** - * @brief Enables or disables the Main Regulator low voltage mode. - * - * @note This mode is only available for STM32F401xx/STM32F411xx devices. - * - * @param NewState: new state of the Under Drive mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; - } - else - { - *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; - } -} - -/** - * @brief Enables or disables the Low Power Regulator low voltage mode. - * - * @note This mode is only available for STM32F401xx/STM32F411xx devices. - * - * @param NewState: new state of the Under Drive mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; - } - else - { - *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; - } -} - -/** - * @} - */ - -/** @defgroup PWR_Group5 FLASH Power Down configuration functions - * @brief FLASH Power Down configuration functions - * -@verbatim - =============================================================================== - ##### FLASH Power Down configuration functions ##### - =============================================================================== - [..] - (+) By setting the FPDS bit in the PWR_CR register by using the - PWR_FlashPowerDownCmd() function, the Flash memory also enters power - down mode when the device enters Stop mode. When the Flash memory - is in power down mode, an additional startup delay is incurred when - waking up from Stop mode. -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Flash Power Down in STOP mode. - * @param NewState: new state of the Flash power mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_FlashPowerDownCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group6 Low Power modes configuration functions - * @brief Low Power modes configuration functions - * -@verbatim - =============================================================================== - ##### Low Power modes configuration functions ##### - =============================================================================== - [..] - The devices feature 3 low-power modes: - (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. - (+) Stop mode: all clocks are stopped, regulator running, regulator - in low power mode - (+) Standby mode: 1.2V domain powered off. - - *** Sleep mode *** - ================== - [..] - (+) Entry: - (++) The Sleep mode is entered by using the __WFI() or __WFE() functions. - (+) Exit: - (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Stop mode *** - ================= - [..] - In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before - entering the Stop mode. It can be switched on again by software after exiting - the Stop mode using the PWR_FlashPowerDownCmd() function. - - (+) Entry: - (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON) - function with: - (+++) Main regulator ON. - (+++) Low Power regulator ON. - (+) Exit: - (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - - *** Standby mode *** - ==================== - [..] - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. - The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby - circuitry. - - The voltage regulator is OFF. - - (+) Entry: - (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function. - (+) Exit: - (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - (#) RTC auto-wakeup (AWU) from the Stop mode - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: - (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - (+++) Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: - (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - (#) RTC auto-wakeup (AWU) from the Standby mode - - (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: - (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - (+++) Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: - (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enters STOP mode. - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_MainRegulator_ON: STOP mode with regulator ON - * @arg PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDS bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters in Under-Drive STOP mode. - * - * @note This mode is only available for STM32F42xxx/STM3243xxx devices. - * - * @note This mode can be selected only when the Under-Drive is already active - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @arg PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDS bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. - * - WKUP pin 1 (PA0) if enabled. - * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @} - */ - -/** @defgroup PWR_Group7 Flags management functions - * @brief Flags management functions - * -@verbatim - =============================================================================== - ##### Flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A - * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage - * scaling output selection is ready. - * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode - * is ready (STM32F42xxx/43xxx devices) - * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode - * switcching is ready (STM32F42xxx/43xxx devices) - * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode - * is enabled in Stop mode (STM32F42xxx/43xxx devices) - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @arg PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices) - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) - if (PWR_FLAG != PWR_FLAG_UDRDY) - { - PWR->CR |= PWR_FLAG << 2; - } - else - { - PWR->CSR |= PWR_FLAG_UDRDY; - } -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE) - PWR->CR |= PWR_FLAG << 2; -#endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_pwr.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Backup Domain Access + * + PVD configuration + * + WakeUp pin configuration + * + Main and Backup Regulators configuration + * + FLASH Power Down configuration + * + Low Power modes configuration + * + Flags management + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_pwr.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* Alias word address of FPDS bit */ +#define FPDS_BitNumber 0x09 +#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) + +/* Alias word address of PMODE bit */ +#define PMODE_BitNumber 0x0E +#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) + +/* Alias word address of ODEN bit */ +#define ODEN_BitNumber 0x10 +#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4)) + +/* Alias word address of ODSWEN bit */ +#define ODSWEN_BitNumber 0x11 +#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4)) + +/* Alias word address of MRLVDS bit */ +#define MRLVDS_BitNumber 0x0B +#define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4)) + +/* Alias word address of LPLVDS bit */ +#define LPLVDS_BitNumber 0x0A +#define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* Alias word address of BRE bit */ +#define BRE_BitNumber 0x09 +#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_DS_MASK ((uint32_t)0xFFFFF3FC) +#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) +#define CR_VOS_MASK ((uint32_t)0xFFFF3FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** @defgroup PWR_Group1 Backup Domain Access function + * @brief Backup Domain Access function + * +@verbatim + =============================================================================== + ##### Backup Domain Access function ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + RCC_APB1PeriphClockCmd() function. + (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @param NewState: new state of the access to the backup domain. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group2 PVD configuration functions + * @brief PVD configuration functions + * +@verbatim + =============================================================================== + ##### PVD configuration functions ##### + =============================================================================== + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled through the EXTI registers. + (+) The PVD is stopped in Standby mode. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_0 + * @arg PWR_PVDLevel_1 + * @arg PWR_PVDLevel_2 + * @arg PWR_PVDLevel_3 + * @arg PWR_PVDLevel_4 + * @arg PWR_PVDLevel_5 + * @arg PWR_PVDLevel_6 + * @arg PWR_PVDLevel_7 + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + + tmpreg = PWR->CR; + + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_MASK; + + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group3 WakeUp pin configuration functions + * @brief WakeUp pin configuration functions + * +@verbatim + =============================================================================== + ##### WakeUp pin configuration functions ##### + =============================================================================== + [..] + (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is + forced in input pull down configuration and is active on rising edges. + (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions + * @brief Main and Backup Regulators configuration functions + * +@verbatim + =============================================================================== + ##### Main and Backup Regulators configuration functions ##### + =============================================================================== + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from + the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is + retained even in Standby or VBAT mode when the low power backup regulator + is enabled. It can be considered as an internal EEPROM when VBAT is + always present. You can use the PWR_BackupRegulatorCmd() function to + enable the low power backup regulator and use the PWR_GetFlagStatus + (PWR_FLAG_BRR) to check if it is ready or not. + + (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to + save battery life. + + (+) The backup SRAM is not mass erased by an tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the reference manual. + + (+) The main internal regulator can be configured to have a tradeoff between + performance and power consumption when the device does not operate at + the maximum frequency. + (+) For STM32F405xx/407xx and STM32F415xx/417xx Devices, the regulator can be + configured on the fly through PWR_MainRegulatorModeConfig() function which + configure VOS bit in PWR_CR register: + (++) When this bit is set (Regulator voltage output Scale 1 mode selected) + the System frequency can go up to 168 MHz. + (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) + the System frequency can go up to 144 MHz. + + (+) For STM32F42xxx/43xxx Devices, the regulator can be configured through + PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in + PWR_CR register: + which configure VOS[1:0] bits in PWR_CR register: + (++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected) + the System frequency can go up to 168 MHz. + (++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected) + the System frequency can go up to 144 MHz. + (++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected) + the System frequency can go up to 120 MHz. + + (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL + is OFF and the HSI or HSE clock source is selected as system clock. + The new value programmed is active only when the PLL is ON. + When the PLL is OFF, the voltage scale 3 is automatically selected. + Refer to the datasheets for more details. + + (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has + 2 operating modes available: + (++) Normal mode: The CPU and core logic operate at maximum frequency at a given + voltage scaling (scale 1, scale 2 or scale 3) + (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a + higher frequency than the normal mode for a given voltage scaling (scale 1, + scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and + PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow + the sequence described in Reference manual. + + (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator + supplies a low power voltage to the 1.2V domain, thus preserving the content of registers + and internal SRAM. 2 operating modes are available: + (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only + available when the main regulator or the low power regulator is used in Scale 3 or + low voltage mode. + (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only + available when the main regulator or the low power regulator is in low voltage mode. + This mode is enabled through PWR_UnderDriveCmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the Backup Regulator. + * @param NewState: new state of the Backup Regulator. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupRegulatorCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the main internal regulator output voltage. + * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, + * System frequency up to 168 MHz. + * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, + * System frequency up to 144 MHz. + * @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode, + * System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices) + * @retval None + */ +void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage)); + + tmpreg = PWR->CR; + + /* Clear VOS[15:14] bits */ + tmpreg &= CR_VOS_MASK; + + /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */ + tmpreg |= PWR_Regulator_Voltage; + + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the Over-Drive. + * + * @note This function can be used only for STM32F42xxx/STM3243xxx devices. + * This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * + * @param NewState: new state of the Over Drive mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_OverDriveCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Set/Reset the ODEN bit to enable/disable the Over Drive mode */ + *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Over-Drive switching. + * + * @note This function can be used only for STM32F42xxx/STM3243xxx devices. + * + * @param NewState: new state of the Over Drive switching mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_OverDriveSWCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */ + *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Under-Drive mode. + * + * @note This function can be used only for STM32F42xxx/STM3243xxx devices. + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode + * + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * + * @param NewState: new state of the Under Drive mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_UnderDriveCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the UDEN[1:0] bits to enable the Under Drive mode */ + PWR->CR |= (uint32_t)PWR_CR_UDEN; + } + else + { + /* Reset the UDEN[1:0] bits to disable the Under Drive mode */ + PWR->CR &= (uint32_t)(~PWR_CR_UDEN); + } +} + +/** + * @brief Enables or disables the Main Regulator low voltage mode. + * + * @note This mode is only available for STM32F401xx/STM32F411xx devices. + * + * @param NewState: new state of the Under Drive mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; + } + else + { + *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; + } +} + +/** + * @brief Enables or disables the Low Power Regulator low voltage mode. + * + * @note This mode is only available for STM32F401xx/STM32F411xx devices. + * + * @param NewState: new state of the Under Drive mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; + } + else + { + *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; + } +} + +/** + * @} + */ + +/** @defgroup PWR_Group5 FLASH Power Down configuration functions + * @brief FLASH Power Down configuration functions + * +@verbatim + =============================================================================== + ##### FLASH Power Down configuration functions ##### + =============================================================================== + [..] + (+) By setting the FPDS bit in the PWR_CR register by using the + PWR_FlashPowerDownCmd() function, the Flash memory also enters power + down mode when the device enters Stop mode. When the Flash memory + is in power down mode, an additional startup delay is incurred when + waking up from Stop mode. +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the Flash Power Down in STOP mode. + * @param NewState: new state of the Flash power mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_FlashPowerDownCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group6 Low Power modes configuration functions + * @brief Low Power modes configuration functions + * +@verbatim + =============================================================================== + ##### Low Power modes configuration functions ##### + =============================================================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off. + + *** Sleep mode *** + ================== + [..] + (+) Entry: + (++) The Sleep mode is entered by using the __WFI() or __WFE() functions. + (+) Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption In Stop mode, FLASH can be powered off before + entering the Stop mode. It can be switched on again by software after exiting + the Stop mode using the PWR_FlashPowerDownCmd() function. + + (+) Entry: + (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON) + function with: + (+++) Main regulator ON. + (+++) Low Power regulator ON. + (+) Exit: + (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. + The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby + circuitry. + + The voltage regulator is OFF. + + (+) Entry: + (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event, a time-stamp event, or a comparator event, + without depending on an external interrupt (Auto-wakeup mode). + + (#) RTC auto-wakeup (AWU) from the Stop mode + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: + (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function + (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function + (+++) Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: + (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function + (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), + RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + + (#) RTC auto-wakeup (AWU) from the Standby mode + + (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: + (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function + (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function + (+++) Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: + (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function + (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), + RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enters STOP mode. + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MainRegulator_ON: STOP mode with regulator ON + * @arg PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_MASK; + + /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters in Under-Drive STOP mode. + * + * @note This mode is only available for STM32F42xxx/STM3243xxx devices. + * + * @note This mode can be selected only when the Under-Drive is already active + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @arg PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_MASK; + + /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters STANDBY mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. + * - WKUP pin 1 (PA0) if enabled. + * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @} + */ + +/** @defgroup PWR_Group7 Flags management functions + * @brief Flags management functions + * +@verbatim + =============================================================================== + ##### Flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A + * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage + * scaling output selection is ready. + * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode + * is ready (STM32F42xxx/43xxx devices) + * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode + * switcching is ready (STM32F42xxx/43xxx devices) + * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode + * is enabled in Stop mode (STM32F42xxx/43xxx devices) + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @arg PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices) + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) + if (PWR_FLAG != PWR_FLAG_UDRDY) + { + PWR->CR |= PWR_FLAG << 2; + } + else + { + PWR->CSR |= PWR_FLAG_UDRDY; + } +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE) + PWR->CR |= PWR_FLAG << 2; +#endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c index ac61bf214..202afaf75 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c @@ -1,2307 +1,2307 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rcc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Reset and clock control (RCC) peripheral: - * + Internal/external clocks, PLL, CSS and MCO configuration - * + System, AHB and APB busses clocks configuration - * + Peripheral clocks configuration - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### RCC specific features ##### - =============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache - and I-Cache are disabled, and all peripherals are off except internal - SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; - all peripherals mapped on these busses are running at HSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the JTAG pins which - are assigned to be used for debug purpose. - [..] - Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) -/* Alias word address of PLLI2SON bit */ -#define PLLI2SON_BitNumber 0x1A -#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) - -/* Alias word address of PLLSAION bit */ -#define PLLSAION_BitNumber 0x1C -#define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4)) - -/* --- CFGR Register ---*/ -/* Alias word address of I2SSRC bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x08) -#define I2SSRC_BitNumber 0x17 -#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) - -/* --- BDCR Register ---*/ -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x70) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) - -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x74) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - -/* --- DCKCFGR Register ---*/ -/* Alias word address of TIMPRE bit */ -#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) -#define TIMPRE_BitNumber 0x18 -#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) -/* ---------------------- RCC registers bit mask ------------------------ */ -/* CFGR register bit mask */ -#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) -#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) - -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/* CR register byte 3 (Bits[23:16]) base address */ -#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -static const __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions - * @brief Internal and external clocks, PLL, CSS and MCO configuration functions - * -@verbatim - =================================================================================== - ##### Internal and external clocks, PLL, CSS and MCO configuration functions ##### - =================================================================================== - [..] - This section provide functions allowing to configure the internal/external clocks, - PLLs, CSS and MCO pins. - - (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - (#) PLL (clocked by HSI or HSE), featuring two different output clocks: - (++) The first output is used to generate the high speed system clock (up to 168 MHz) - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - - (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve - high-quality audio performance on the I2S interface or SAI interface in case - of STM32F429x/439x devices. - - (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI - interface and LCD TFT controller available only for STM32F42xxx/43xxx devices. - - (#) CSS (Clock security system), once enable and if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) - exception vector. - - (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL - clock (through a configurable prescaler) on PA8 pin. - - (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S - clock (through a configurable prescaler) on PC9 pin. - @endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL and PLLI2S OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42/43xxx devices) bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset PLLI2SCFGR register */ - RCC->PLLI2SCFGR = 0x20003000; - - /* Reset PLLSAICFGR register, only available for STM32F42/43xxx devices */ - RCC->PLLSAICFGR = 0x24003000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - - /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */ - RCC->DCKCFGR = 0x00000000; -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the Clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint8_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; - - /* Set the new HSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; -} - -/** - * @brief Waits for HSE start-up. - * @note This functions waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached - * and this flag is not set. The timeout value is defined by the constant - * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending - * on the HSE crystal used in your application. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t startupcounter = 0; - ErrorStatus status = ERROR; - FlagStatus hsestatus = RESET; - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - startupcounter++; - } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - - tmpreg = RCC->CR; - - /* Clear HSITRIM[4:0] bits */ - tmpreg &= ~RCC_CR_HSITRIM; - - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @param NewState: new state of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch (RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * - * @param PLLM: specifies the division factor for PLL VCO input clock - * This parameter must be a number between 0 and 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * - * @param PLLN: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLP: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on - * the System clock frequency. - * - * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between 4 and 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(PLLM)); - assert_param(IS_RCC_PLLN_VALUE(PLLN)); - assert_param(IS_RCC_PLLP_VALUE(PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); - - RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | - (PLLQ << 24); -} - -/** - * @brief Enables or disables the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -#if defined (STM32F40_41xxx) || defined (STM32F401xx) -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx - * or STM32F401xx devices. - * - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); -} - -#elif defined (STM32F411xE) -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F411xE devices. - * - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLLI2S jitter. - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SM)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM; -} - -#elif defined (STM32F427_437xx) || defined (STM32F429_439xx) -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F42xxx/43xxx devices - * - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLI2SQ: specifies the division factor for SAI1 clock - * This parameter must be a number between 2 and 15. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28); -} -#else -#endif /* STM32F40_41xxx || STM32F401xx */ - -/** - * @brief Enables or disables the PLLI2S. - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLI2SCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLLSAI clock multiplication and division factors. - * - * @note This function can be used only for STM32F42xxx/43xxx devices - * - * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLSAIQ: specifies the division factor for SAI1 clock - * This parameter must be a number between 2 and 15. - * - * @param PLLSAIR: specifies the division factor for LTDC clock - * This parameter must be a number between 2 and 7. - * - * @retval None - */ -void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); - assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR)); - - RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28); -} - -/** - * @brief Enables or disables the PLLSAI. - * - * @note This function can be used only for STM32F42xxx/43xxx devices - * - * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLSAICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. - * @param NewState: new state of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO1 pin(PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCO1Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source - * @param RCC_MCO1Div: specifies the MCO1 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO1Div_1: no division applied to MCO1 clock - * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock - * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock - * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock - * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock - * @retval None - */ -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); - assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ - tmpreg &= CFGR_MCO1_RESET_MASK; - - /* Select MCO1 clock source and prescaler */ - tmpreg |= RCC_MCO1Source | RCC_MCO1Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Selects the clock source to output on MCO2 pin(PC9). - * @note PC9 should be configured in alternate function mode. - * @param RCC_MCO2Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source - * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCO2Div: specifies the MCO2 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO2Div_1: no division applied to MCO2 clock - * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock - * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock - * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock - * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock - * @retval None - */ -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); - assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO2 and MCO2PRE[2:0] bits */ - tmpreg &= CFGR_MCO2_RESET_MASK; - - /* Select MCO2 clock source and prescaler */ - tmpreg |= RCC_MCO2Source | RCC_MCO2Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @} - */ - -/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions - * @brief System, AHB and APB busses clocks configuration functions - * -@verbatim - =============================================================================== - ##### System, AHB and APB busses clocks configuration functions ##### - =============================================================================== - [..] - This section provide functions allowing to configure the System, AHB, APB1 and - APB2 busses clocks. - - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. - You have to use RCC_I2SCLKConfig() function to configure this clock. - (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() - functions to configure this clock. - (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly, while the SDIO require a frequency equal or lower than - to 48. This clock is derived of the main PLL through PLLQ divider. - (+@) IWDG clock which is always the LSI clock. - - (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency - of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending - on the device voltage range, the maximum frequency should be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| - +---------------|----------------|----------------|-----------------|-----------------+ - (#) For STM32F42xxx/43xxx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, - PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum - frequency should be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| - |---------------|----------------|----------------|-----------------|-----------------| - |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| - +-------------------------------------------------------------------------------------+ - - (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz, - PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum - frequency should be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | - +-------------------------------------------------------------------------------------+ - - (#) For STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz, - PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum - frequency should be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 | - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 | - +-------------------------------------------------------------------------------------+ - - -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: - (++) when VOS = '0', the maximum value of fHCLK = 144MHz. - (++) when VOS = '1', the maximum value of fHCLK = 168MHz. - [..] - On STM32F42xxx/43xxx devices: - (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz. - (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz. - (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz - [..] - On STM32F401x devices: - (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz. - (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz. - On STM32F411xE devices: - (++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz. - (++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz. - (++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz. - - You can use PWR_MainRegulatorModeConfig() function to control VOS bits. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the system clock (SYSCLK). - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - - tmpreg = RCC->CFGR; - - /* Clear SW[1:0] bits */ - tmpreg &= ~RCC_CFGR_SW; - - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @note Depending on the device voltage range, the software has to set correctly - * these bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above - * "CPU, AHB and APB busses clocks configuration functions") - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - - tmpreg = RCC->CFGR; - - /* Clear HPRE[3:0] bits */ - tmpreg &= ~RCC_CFGR_HPRE; - - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE1[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE1; - - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE2[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE2; - - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, - * PCLK1 and PCLK2. - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function - * must be called to update the structure's field. Otherwise, any - * configuration based on this function will be incorrect. - * - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; - break; - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ - - /* Get HCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_HPRE; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE1; - tmp = tmp >> 10; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE2; - tmp = tmp >> 13; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; -} - -/** - * @} - */ - -/** @defgroup RCC_Group3 Peripheral clocks configuration functions - * @brief Peripheral clocks configuration functions - * -@verbatim - =============================================================================== - ##### Peripheral clocks configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to configure the Peripheral clocks. - - (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided - by 2 to 31. - - (#) After restart from Reset or wakeup from STANDBY, all peripherals are off - except internal SRAM, Flash and JTAG. Before to start using a peripheral - you have to enable its interface clock. You can do this using - RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. - - (#) To reset the peripherals configuration (to the default state after device reset) - you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and - RCC_APB1PeriphResetCmd() functions. - - (#) To further reduce power consumption in SLEEP mode the peripheral clocks - can be disabled prior to executing the WFI or WFE instructions. - You can do this using RCC_AHBPeriphClockLPModeCmd(), - RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using PWR_BackupAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using RCC_BackupResetCmd() function, or by - * a Power On Reset (POR). - * - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - * - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - - if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) - { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ - tmpreg = RCC->CFGR; - - /* Clear RTCPRE[4:0] bits */ - tmpreg &= ~RCC_CFGR_RTCPRE; - - /* Configure HSE division factor for RTC clock */ - tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); - - /* Store the new value */ - RCC->CFGR = tmpreg; - } - - /* Select the RTC clock source */ - RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock source was selected - * using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Forces or releases the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the I2S clock source (I2SCLK). - * @note This function must be called before enabling the I2S APB clock. - * @param RCC_I2SCLKSource: specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source - * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as I2S clock source - * @retval None - */ -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - - *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; -} - -/** - * @brief Configures the SAI clock Divider coming from PLLI2S. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note This function must be called before enabling the PLLI2S. - * - * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock . - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ - * - * @retval None - */ -void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ)); - - tmpreg = RCC->DCKCFGR; - - /* Clear PLLI2SDIVQ[4:0] bits */ - tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ); - - /* Set PLLI2SDIVQ values */ - tmpreg |= (RCC_PLLI2SDivQ - 1); - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures the SAI clock Divider coming from PLLSAI. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note This function must be called before enabling the PLLSAI. - * - * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock . - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ - * - * @retval None - */ -void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ)); - - tmpreg = RCC->DCKCFGR; - - /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */ - tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ); - - /* Set PLLSAIDIVQ values */ - tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8); - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures SAI1BlockA clock source selection. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 Block A clock - * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 Block A clock - * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as SAI1 Block A clock - * @retval None - */ -void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource)); - - tmpreg = RCC->DCKCFGR; - - /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ - tmpreg &= ~RCC_DCKCFGR_SAI1ASRC; - - /* Set SAI Block A source selection value */ - tmpreg |= RCC_SAIBlockACLKSource; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures SAI1BlockB clock source selection. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 Block B clock - * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 Block B clock - * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as SAI1 Block B clock - * @retval None - */ -void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource)); - - tmpreg = RCC->DCKCFGR; - - /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */ - tmpreg &= ~RCC_DCKCFGR_SAI1BSRC; - - /* Set SAI Block B source selection value */ - tmpreg |= RCC_SAIBlockBCLKSource; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - - -/** - * @brief Configures the LTDC clock Divider coming from PLLSAI. - * - * @note The LTDC peripheral is only available with STM32F429xx/439xx Devices. - * - * @note This function must be called before enabling the PLLSAI. - * - * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock . - * This parameter must be a number between 2 and 16. - * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR - * - * @retval None - */ -void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR)); - - tmpreg = RCC->DCKCFGR; - - /* Clear PLLSAIDIVR[2:0] bits */ - tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR; - - /* Set PLLSAIDIVR values */ - tmpreg |= RCC_PLLSAIDivR; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures the Timers clocks prescalers selection. - * - * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. - * - * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection - * This parameter can be one of the following values: - * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1 or 2, - * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to - * division by 4 or more. - * - * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, - * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding - * to division by 8 or more. - * @retval None - */ -void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler) -{ - /* Check the parameters */ - assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler)); - - *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler; - -} - -/** - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1ENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1ENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2ENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2ENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3ENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3ENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @arg RCC_APB1Periph_UART7: UART7 clock - * @arg RCC_APB1Periph_UART8: UART8 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SPI4: SPI4 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @arg RCC_APB2Periph_SPI5: SPI5 clock - * @arg RCC_APB2Periph_SPI6: SPI6 clock - * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) - * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases AHB1 peripheral reset. - * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB1RSTR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1RSTR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Forces or releases AHB2 peripheral reset. - * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2RSTR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2RSTR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Forces or releases AHB3 peripheral reset. - * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. - * This parameter must be: RCC_AHB3Periph_FSMC - * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3RSTR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3RSTR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @arg RCC_APB1Periph_UART7: UART7 clock - * @arg RCC_APB1Periph_UART8: UART8 clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SPI4: SPI4 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @arg RCC_APB2Periph_SPI5: SPI5 clock - * @arg RCC_APB2Periph_SPI6: SPI6 clock - * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) - * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1LPENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1LPENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB2LPENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2LPENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * or RCC_AHB3Periph_FMC (STM32F429x/439x devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB3LPENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3LPENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @arg RCC_APB1Periph_UART7: UART7 clock - * @arg RCC_APB1Periph_UART8: UART8 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1LPENR |= RCC_APB1Periph; - } - else - { - RCC->APB1LPENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SPI4: SPI4 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @arg RCC_APB2Periph_SPI5: SPI5 clock - * @arg RCC_APB2Periph_SPI6: SPI6 clock - * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) - * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2LPENR |= RCC_APB2Periph; - } - else - { - RCC->APB2LPENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Configures the External Low Speed oscillator mode (LSE mode). - * @note This mode is only available for STM32F411xx devices. - * @param Mode: specifies the LSE mode. - * This parameter can be one of the following values: - * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode. - * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode. - * @retval None - */ -void RCC_LSEModeConfig(uint8_t Mode) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE_MODE(Mode)); - - if(Mode == RCC_LSE_HIGHDRIVE_MODE) - { - SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); - } - else - { - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); - } -} - -/** - * @} - */ - -/** @defgroup RCC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: main PLL clock ready - * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready - * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx devices) - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_MASK; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= RCC_CSR_RMVF; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx devices) - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_rcc.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Reset and clock control (RCC) peripheral: + * + Internal/external clocks, PLL, CSS and MCO configuration + * + System, AHB and APB busses clocks configuration + * + Peripheral clocks configuration + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### RCC specific features ##### + =============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) +/* Alias word address of PLLI2SON bit */ +#define PLLI2SON_BitNumber 0x1A +#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) + +/* Alias word address of PLLSAION bit */ +#define PLLSAION_BitNumber 0x1C +#define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4)) + +/* --- CFGR Register ---*/ +/* Alias word address of I2SSRC bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x08) +#define I2SSRC_BitNumber 0x17 +#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) + +/* --- BDCR Register ---*/ +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x70) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x74) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +/* --- DCKCFGR Register ---*/ +/* Alias word address of TIMPRE bit */ +#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) +#define TIMPRE_BitNumber 0x18 +#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) +/* ---------------------- RCC registers bit mask ------------------------ */ +/* CFGR register bit mask */ +#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) +#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) + +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CR register byte 3 (Bits[23:16]) base address */ +#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static const __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions + * @brief Internal and external clocks, PLL, CSS and MCO configuration functions + * +@verbatim + =================================================================================== + ##### Internal and external clocks, PLL, CSS and MCO configuration functions ##### + =================================================================================== + [..] + This section provide functions allowing to configure the internal/external clocks, + PLLs, CSS and MCO pins. + + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + (++) The first output is used to generate the high speed system clock (up to 168 MHz) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + + (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve + high-quality audio performance on the I2S interface or SAI interface in case + of STM32F429x/439x devices. + + (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI + interface and LCD TFT controller available only for STM32F42xxx/43xxx devices. + + (#) CSS (Clock security system), once enable and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) + exception vector. + + (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + @endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL and PLLI2S OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42/43xxx devices) bits */ + RCC->CR &= (uint32_t)0xEAF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset PLLI2SCFGR register */ + RCC->PLLI2SCFGR = 0x20003000; + + /* Reset PLLSAICFGR register, only available for STM32F42/43xxx devices */ + RCC->PLLSAICFGR = 0x24003000; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */ + RCC->DCKCFGR = 0x00000000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the Clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint8_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; + + /* Set the new HSE configuration -------------------------------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; +} + +/** + * @brief Waits for HSE start-up. + * @note This functions waits on HSERDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending + * on the HSE crystal used in your application. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t startupcounter = 0; + ErrorStatus status = ERROR; + FlagStatus hsestatus = RESET; + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + startupcounter++; + } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->CR; + + /* Clear HSITRIM[4:0] bits */ + tmpreg &= ~RCC_CR_HSITRIM; + + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @param NewState: new state of the HSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch (RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param RCC_PLLSource: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * + * @param PLLM: specifies the division factor for PLL VCO input clock + * This parameter must be a number between 0 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + * @param PLLN: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLP: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on + * the System clock frequency. + * + * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between 4 and 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(PLLM)); + assert_param(IS_RCC_PLLN_VALUE(PLLN)); + assert_param(IS_RCC_PLLP_VALUE(PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); + + RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | + (PLLQ << 24); +} + +/** + * @brief Enables or disables the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +#if defined (STM32F40_41xxx) || defined (STM32F401xx) +/** + * @brief Configures the PLLI2S clock multiplication and division factors. + * + * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx + * or STM32F401xx devices. + * + * @note This function must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLI2SR: specifies the division factor for I2S clock + * This parameter must be a number between 2 and 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @retval None + */ +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); + + RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); +} + +#elif defined (STM32F411xE) +/** + * @brief Configures the PLLI2S clock multiplication and division factors. + * + * @note This function can be used only for STM32F411xE devices. + * + * @note This function must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLLI2S jitter. + * + * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLI2SR: specifies the division factor for I2S clock + * This parameter must be a number between 2 and 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @retval None + */ +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); + assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SM)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); + + RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM; +} + +#elif defined (STM32F427_437xx) || defined (STM32F429_439xx) +/** + * @brief Configures the PLLI2S clock multiplication and division factors. + * + * @note This function can be used only for STM32F42xxx/43xxx devices + * + * @note This function must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLI2SQ: specifies the division factor for SAI1 clock + * This parameter must be a number between 2 and 15. + * + * @param PLLI2SR: specifies the division factor for I2S clock + * This parameter must be a number between 2 and 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices. + * + * @retval None + */ +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); + + RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28); +} +#else +#endif /* STM32F40_41xxx || STM32F401xx */ + +/** + * @brief Enables or disables the PLLI2S. + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLI2SCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLLSAI clock multiplication and division factors. + * + * @note This function can be used only for STM32F42xxx/43xxx devices + * + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLSAIQ: specifies the division factor for SAI1 clock + * This parameter must be a number between 2 and 15. + * + * @param PLLSAIR: specifies the division factor for LTDC clock + * This parameter must be a number between 2 and 7. + * + * @retval None + */ +void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR)); + + RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28); +} + +/** + * @brief Enables or disables the PLLSAI. + * + * @note This function can be used only for STM32F42xxx/43xxx devices + * + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLSAICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + * @param NewState: new state of the Clock Security System. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8). + * @note PA8 should be configured in alternate function mode. + * @param RCC_MCO1Source: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source + * @param RCC_MCO1Div: specifies the MCO1 prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO1Div_1: no division applied to MCO1 clock + * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock + * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock + * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock + * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock + * @retval None + */ +void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); + assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); + + tmpreg = RCC->CFGR; + + /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ + tmpreg &= CFGR_MCO1_RESET_MASK; + + /* Select MCO1 clock source and prescaler */ + tmpreg |= RCC_MCO1Source | RCC_MCO1Div; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Selects the clock source to output on MCO2 pin(PC9). + * @note PC9 should be configured in alternate function mode. + * @param RCC_MCO2Source: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source + * @param RCC_MCO2Div: specifies the MCO2 prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO2Div_1: no division applied to MCO2 clock + * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock + * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock + * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock + * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock + * @retval None + */ +void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); + assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); + + tmpreg = RCC->CFGR; + + /* Clear MCO2 and MCO2PRE[2:0] bits */ + tmpreg &= CFGR_MCO2_RESET_MASK; + + /* Select MCO2 clock source and prescaler */ + tmpreg |= RCC_MCO2Source | RCC_MCO2Div; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @} + */ + +/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions + * @brief System, AHB and APB busses clocks configuration functions + * +@verbatim + =============================================================================== + ##### System, AHB and APB busses clocks configuration functions ##### + =============================================================================== + [..] + This section provide functions allowing to configure the System, AHB, APB1 and + APB2 busses clocks. + + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or + from an external clock mapped on the I2S_CKIN pin. + You have to use RCC_I2SCLKConfig() function to configure this clock. + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() + functions to configure this clock. + (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly, while the SDIO require a frequency equal or lower than + to 48. This clock is derived of the main PLL through PLLQ divider. + (+@) IWDG clock which is always the LSI clock. + + (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency + of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending + on the device voltage range, the maximum frequency should be adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| + +---------------|----------------|----------------|-----------------|-----------------+ + (#) For STM32F42xxx/43xxx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, + PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum + frequency should be adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| + |---------------|----------------|----------------|-----------------|-----------------| + |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| + +-------------------------------------------------------------------------------------+ + + (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz, + PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum + frequency should be adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | + +-------------------------------------------------------------------------------------+ + + (#) For STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz, + PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum + frequency should be adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 | + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 | + +-------------------------------------------------------------------------------------+ + + -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: + (++) when VOS = '0', the maximum value of fHCLK = 144MHz. + (++) when VOS = '1', the maximum value of fHCLK = 168MHz. + [..] + On STM32F42xxx/43xxx devices: + (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz. + (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz. + (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz + [..] + On STM32F401x devices: + (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz. + (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz. + On STM32F411xE devices: + (++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz. + (++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz. + (++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz. + + You can use PWR_MainRegulatorModeConfig() function to control VOS bits. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the system clock (SYSCLK). + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use RCC_GetSYSCLKSource() function to know which clock is + * currently used as system clock source. + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= ~RCC_CFGR_SW; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @note Depending on the device voltage range, the software has to set correctly + * these bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above + * "CPU, AHB and APB busses clocks configuration functions") + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[3:0] bits */ + tmpreg &= ~RCC_CFGR_HPRE; + + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE1[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE1; + + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE2[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE2; + + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, + * PCLK1 and PCLK2. + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function + * must be called to update the structure's field. Otherwise, any + * configuration based on this function will be incorrect. + * + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; + break; + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ + + /* Get HCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_HPRE; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE1; + tmp = tmp >> 10; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE2; + tmp = tmp >> 13; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; +} + +/** + * @} + */ + +/** @defgroup RCC_Group3 Peripheral clocks configuration functions + * @brief Peripheral clocks configuration functions + * +@verbatim + =============================================================================== + ##### Peripheral clocks configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to configure the Peripheral clocks. + + (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided + by 2 to 31. + + (#) After restart from Reset or wakeup from STANDBY, all peripherals are off + except internal SRAM, Flash and JTAG. Before to start using a peripheral + you have to enable its interface clock. You can do this using + RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. + + (#) To reset the peripherals configuration (to the default state after device reset) + you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and + RCC_APB1PeriphResetCmd() functions. + + (#) To further reduce power consumption in SLEEP mode the peripheral clocks + can be disabled prior to executing the WFI or WFE instructions. + You can do this using RCC_AHBPeriphClockLPModeCmd(), + RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using PWR_BackupAccessCmd(ENABLE) function before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using RCC_BackupResetCmd() function, or by + * a Power On Reset (POR). + * + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) + { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ + tmpreg = RCC->CFGR; + + /* Clear RTCPRE[4:0] bits */ + tmpreg &= ~RCC_CFGR_RTCPRE; + + /* Configure HSE division factor for RTC clock */ + tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); + + /* Store the new value */ + RCC->CFGR = tmpreg; + } + + /* Select the RTC clock source */ + RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock source was selected + * using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Forces or releases the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S APB clock. + * @param RCC_I2SCLKSource: specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source + * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as I2S clock source + * @retval None + */ +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); + + *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; +} + +/** + * @brief Configures the SAI clock Divider coming from PLLI2S. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note This function must be called before enabling the PLLI2S. + * + * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock . + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ + * + * @retval None + */ +void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ)); + + tmpreg = RCC->DCKCFGR; + + /* Clear PLLI2SDIVQ[4:0] bits */ + tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ); + + /* Set PLLI2SDIVQ values */ + tmpreg |= (RCC_PLLI2SDivQ - 1); + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures the SAI clock Divider coming from PLLSAI. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note This function must be called before enabling the PLLSAI. + * + * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock . + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ + * + * @retval None + */ +void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ)); + + tmpreg = RCC->DCKCFGR; + + /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */ + tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ); + + /* Set PLLSAIDIVQ values */ + tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8); + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures SAI1BlockA clock source selection. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block A clock + * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block A clock + * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block A clock + * @retval None + */ +void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource)); + + tmpreg = RCC->DCKCFGR; + + /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ + tmpreg &= ~RCC_DCKCFGR_SAI1ASRC; + + /* Set SAI Block A source selection value */ + tmpreg |= RCC_SAIBlockACLKSource; + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures SAI1BlockB clock source selection. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block B clock + * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block B clock + * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block B clock + * @retval None + */ +void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource)); + + tmpreg = RCC->DCKCFGR; + + /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */ + tmpreg &= ~RCC_DCKCFGR_SAI1BSRC; + + /* Set SAI Block B source selection value */ + tmpreg |= RCC_SAIBlockBCLKSource; + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + + +/** + * @brief Configures the LTDC clock Divider coming from PLLSAI. + * + * @note The LTDC peripheral is only available with STM32F429xx/439xx Devices. + * + * @note This function must be called before enabling the PLLSAI. + * + * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock . + * This parameter must be a number between 2 and 16. + * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR + * + * @retval None + */ +void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR)); + + tmpreg = RCC->DCKCFGR; + + /* Clear PLLSAIDIVR[2:0] bits */ + tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR; + + /* Set PLLSAIDIVR values */ + tmpreg |= RCC_PLLSAIDivR; + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures the Timers clocks prescalers selection. + * + * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. + * + * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * division by 4 or more. + * + * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * to division by 8 or more. + * @retval None + */ +void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler) +{ + /* Check the parameters */ + assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler)); + + *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler; + +} + +/** + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock + * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock + * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock + * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB1ENR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1ENR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2ENR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2ENR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. + * This parameter must be: RCC_AHB3Periph_FSMC + * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3ENR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3ENR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_UART7: UART7 clock + * @arg RCC_APB1Periph_UART8: UART8 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SPI4: SPI4 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @arg RCC_APB2Periph_SPI5: SPI5 clock + * @arg RCC_APB2Periph_SPI6: SPI6 clock + * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) + * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases AHB1 peripheral reset. + * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB1RSTR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1RSTR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Forces or releases AHB2 peripheral reset. + * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2RSTR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2RSTR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Forces or releases AHB3 peripheral reset. + * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. + * This parameter must be: RCC_AHB3Periph_FSMC + * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3RSTR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3RSTR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_UART7: UART7 clock + * @arg RCC_APB1Periph_UART8: UART8 clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SPI4: SPI4 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @arg RCC_APB2Periph_SPI5: SPI5 clock + * @arg RCC_APB2Periph_SPI6: SPI6 clock + * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) + * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock + * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock + * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB1LPENR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1LPENR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB2LPENR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2LPENR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. + * This parameter must be: RCC_AHB3Periph_FSMC + * or RCC_AHB3Periph_FMC (STM32F429x/439x devices) + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB3LPENR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3LPENR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_UART7: UART7 clock + * @arg RCC_APB1Periph_UART8: UART8 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1LPENR |= RCC_APB1Periph; + } + else + { + RCC->APB1LPENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SPI4: SPI4 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @arg RCC_APB2Periph_SPI5: SPI5 clock + * @arg RCC_APB2Periph_SPI6: SPI6 clock + * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) + * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2LPENR |= RCC_APB2Periph; + } + else + { + RCC->APB2LPENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Configures the External Low Speed oscillator mode (LSE mode). + * @note This mode is only available for STM32F411xx devices. + * @param Mode: specifies the LSE mode. + * This parameter can be one of the following values: + * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode. + * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode. + * @retval None + */ +void RCC_LSEModeConfig(uint8_t Mode) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE_MODE(Mode)); + + if(Mode == RCC_LSE_HIGHDRIVE_MODE) + { + SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } + else + { + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } +} + +/** + * @} + */ + +/** @defgroup RCC_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: main PLL clock ready + * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready + * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx devices) + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= RCC_CSR_RMVF; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx devices) + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c index 7e271b2e5..ed851c71d 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c @@ -1,397 +1,397 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rng.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Random Number Generator (RNG) peripheral: - * + Initialization and Configuration - * + Get 32 bit Random number - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable The RNG controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. - - (#) Activate the RNG peripheral using RNG_Cmd() function. - - (#) Wait until the 32 bit Random number Generator contains a valid random data - (using polling/interrupt mode). For more details, refer to "Interrupts and - flags management functions" module description. - - (#) Get the 32 bit Random number using RNG_GetRandomNumber() function - - (#) To get another 32 bit Random number, go to step 3. - - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rng.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RNG - * @brief RNG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RNG_Private_Functions - * @{ - */ - -/** @defgroup RNG_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initialize the RNG peripheral - (+) Enable or disable the RNG peripheral - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the RNG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void RNG_DeInit(void) -{ - /* Enable RNG reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); - - /* Release RNG from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE); -} - -/** - * @brief Enables or disables the RNG peripheral. - * @param NewState: new state of the RNG peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG */ - RNG->CR |= RNG_CR_RNGEN; - } - else - { - /* Disable the RNG */ - RNG->CR &= ~RNG_CR_RNGEN; - } -} -/** - * @} - */ - -/** @defgroup RNG_Group2 Get 32 bit Random number function - * @brief Get 32 bit Random number function - * - -@verbatim - =============================================================================== - ##### Get 32 bit Random number function ##### - =============================================================================== - [..] This section provides a function allowing to get the 32 bit Random number - - (@) Before to call this function you have to wait till DRDY flag is set, - using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - -@endverbatim - * @{ - */ - - -/** - * @brief Returns a 32-bit random number. - * - * @note Before to call this function you have to wait till DRDY (data ready) - * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - * @note Each time the the Random number data is read (using RNG_GetRandomNumber() - * function), the RNG_FLAG_DRDY flag is automatically cleared. - * @note In the case of a seed error, the generation of random numbers is - * interrupted for as long as the SECS bit is '1'. If a number is - * available in the RNG_DR register, it must not be used because it may - * not have enough entropy. In this case, it is recommended to clear the - * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable - * and enable the RNG peripheral (using RNG_Cmd() function) to - * reinitialize and restart the RNG. - * @note In the case of a clock error, the RNG is no more able to generate - * random numbers because the PLL48CLK clock is not correct. User have - * to check that the clock controller is correctly configured to provide - * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) - * function) . The clock error has no impact on the previously generated - * random numbers, and the RNG_DR register contents can be used. - * - * @param None - * @retval 32-bit random number. - */ -uint32_t RNG_GetRandomNumber(void) -{ - /* Return the 32 bit random number from the DR register */ - return RNG->DR; -} - - -/** - * @} - */ - -/** @defgroup RNG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the RNG Interrupts and - to get the status and clear flags and Interrupts pending bits. - - [..] The RNG provides 3 Interrupts sources and 3 Flags: - - *** Flags : *** - =============== - [..] - (#) RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid - random data. it is cleared by reading the valid data(using - RNG_GetRandomNumber() function). - - (#) RNG_FLAG_CECS : In the case of a seed error detection. - - (#) RNG_FLAG_SECS : In the case of a clock error detection. - - *** Interrupts *** - ================== - [..] If enabled, an RNG interrupt is pending : - - (#) In the case of the RNG_DR register contains valid random data. - This interrupt source is cleared once the RNG_DR register has been read - (using RNG_GetRandomNumber() function) until a new valid value is - computed; or - (#) In the case of a seed error : One of the following faulty sequences has - been detected: - (++) More than 64 consecutive bits at the same value (0 or 1) - (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01) - This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) - function; or - (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source) - was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is - cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function. - -@- note In this case, User have to check that the clock controller is - correctly configured to provide the RNG clock. - - *** Managing the RNG controller events : *** - ============================================ - [..] The user should identify which mode will be used in his application to manage - the RNG controller events: Polling mode or Interrupt mode. - - (#) In the Polling Mode it is advised to use the following functions: - (++) RNG_GetFlagStatus() : to check if flags events occur. - (++) RNG_ClearFlag() : to clear the flags events. - - -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only - by reading the Random number data. - - (#) In the Interrupt Mode it is advised to use the following functions: - (++) RNG_ITConfig() : to enable or disable the interrupt source. - (++) RNG_GetITStatus() : to check if Interrupt occurs. - (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the RNG interrupt. - * @note The RNG provides 3 interrupt sources, - * - Computed data is ready event (DRDY), and - * - Seed error Interrupt (SEI) and - * - Clock error Interrupt (CEI), - * all these interrupts sources are enabled by setting the IE bit in - * CR register. However, each interrupt have its specific status bit - * (see RNG_GetITStatus() function) and clear bit except the DRDY event - * (see RNG_ClearITPendingBit() function). - * @param NewState: new state of the RNG interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG interrupt */ - RNG->CR |= RNG_CR_IE; - } - else - { - /* Disable the RNG interrupt */ - RNG->CR &= ~RNG_CR_IE; - } -} - -/** - * @brief Checks whether the specified RNG flag is set or not. - * @param RNG_FLAG: specifies the RNG flag to check. - * This parameter can be one of the following values: - * @arg RNG_FLAG_DRDY: Data Ready flag. - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @retval The new state of RNG_FLAG (SET or RESET). - */ -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_FLAG(RNG_FLAG)); - - /* Check the status of the specified RNG flag */ - if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET) - { - /* RNG_FLAG is set */ - bitstatus = SET; - } - else - { - /* RNG_FLAG is reset */ - bitstatus = RESET; - } - /* Return the RNG_FLAG status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG flags. - * @param RNG_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. - * This flag is cleared only by reading the Random number data (using - * RNG_GetRandomNumber() function). - * @retval None - */ -void RNG_ClearFlag(uint8_t RNG_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG)); - /* Clear the selected RNG flags */ - RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); -} - -/** - * @brief Checks whether the specified RNG interrupt has occurred or not. - * @param RNG_IT: specifies the RNG interrupt source to check. - * This parameter can be one of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval The new state of RNG_IT (SET or RESET). - */ -ITStatus RNG_GetITStatus(uint8_t RNG_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_IT(RNG_IT)); - - /* Check the status of the specified RNG interrupt */ - if ((RNG->SR & RNG_IT) != (uint8_t)RESET) - { - /* RNG_IT is set */ - bitstatus = SET; - } - else - { - /* RNG_IT is reset */ - bitstatus = RESET; - } - /* Return the RNG_IT status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG interrupt pending bit(s). - * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear. - * This parameter can be any combination of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval None - */ -void RNG_ClearITPendingBit(uint8_t RNG_IT) -{ - /* Check the parameters */ - assert_param(IS_RNG_IT(RNG_IT)); - - /* Clear the selected RNG interrupt pending bit */ - RNG->SR = (uint8_t)~RNG_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_rng.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Random Number Generator (RNG) peripheral: + * + Initialization and Configuration + * + Get 32 bit Random number + * + Interrupts and flags management + * +@verbatim + + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) Enable The RNG controller clock using + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. + + (#) Activate the RNG peripheral using RNG_Cmd() function. + + (#) Wait until the 32 bit Random number Generator contains a valid random data + (using polling/interrupt mode). For more details, refer to "Interrupts and + flags management functions" module description. + + (#) Get the 32 bit Random number using RNG_GetRandomNumber() function + + (#) To get another 32 bit Random number, go to step 3. + + +@endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_rng.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RNG + * @brief RNG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RNG_Private_Functions + * @{ + */ + +/** @defgroup RNG_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to + (+) Initialize the RNG peripheral + (+) Enable or disable the RNG peripheral + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the RNG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void RNG_DeInit(void) +{ + /* Enable RNG reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); + + /* Release RNG from reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE); +} + +/** + * @brief Enables or disables the RNG peripheral. + * @param NewState: new state of the RNG peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RNG_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the RNG */ + RNG->CR |= RNG_CR_RNGEN; + } + else + { + /* Disable the RNG */ + RNG->CR &= ~RNG_CR_RNGEN; + } +} +/** + * @} + */ + +/** @defgroup RNG_Group2 Get 32 bit Random number function + * @brief Get 32 bit Random number function + * + +@verbatim + =============================================================================== + ##### Get 32 bit Random number function ##### + =============================================================================== + [..] This section provides a function allowing to get the 32 bit Random number + + (@) Before to call this function you have to wait till DRDY flag is set, + using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. + +@endverbatim + * @{ + */ + + +/** + * @brief Returns a 32-bit random number. + * + * @note Before to call this function you have to wait till DRDY (data ready) + * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. + * @note Each time the the Random number data is read (using RNG_GetRandomNumber() + * function), the RNG_FLAG_DRDY flag is automatically cleared. + * @note In the case of a seed error, the generation of random numbers is + * interrupted for as long as the SECS bit is '1'. If a number is + * available in the RNG_DR register, it must not be used because it may + * not have enough entropy. In this case, it is recommended to clear the + * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable + * and enable the RNG peripheral (using RNG_Cmd() function) to + * reinitialize and restart the RNG. + * @note In the case of a clock error, the RNG is no more able to generate + * random numbers because the PLL48CLK clock is not correct. User have + * to check that the clock controller is correctly configured to provide + * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) + * function) . The clock error has no impact on the previously generated + * random numbers, and the RNG_DR register contents can be used. + * + * @param None + * @retval 32-bit random number. + */ +uint32_t RNG_GetRandomNumber(void) +{ + /* Return the 32 bit random number from the DR register */ + return RNG->DR; +} + + +/** + * @} + */ + +/** @defgroup RNG_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure the RNG Interrupts and + to get the status and clear flags and Interrupts pending bits. + + [..] The RNG provides 3 Interrupts sources and 3 Flags: + + *** Flags : *** + =============== + [..] + (#) RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid + random data. it is cleared by reading the valid data(using + RNG_GetRandomNumber() function). + + (#) RNG_FLAG_CECS : In the case of a seed error detection. + + (#) RNG_FLAG_SECS : In the case of a clock error detection. + + *** Interrupts *** + ================== + [..] If enabled, an RNG interrupt is pending : + + (#) In the case of the RNG_DR register contains valid random data. + This interrupt source is cleared once the RNG_DR register has been read + (using RNG_GetRandomNumber() function) until a new valid value is + computed; or + (#) In the case of a seed error : One of the following faulty sequences has + been detected: + (++) More than 64 consecutive bits at the same value (0 or 1) + (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01) + This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) + function; or + (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source) + was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is + cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function. + -@- note In this case, User have to check that the clock controller is + correctly configured to provide the RNG clock. + + *** Managing the RNG controller events : *** + ============================================ + [..] The user should identify which mode will be used in his application to manage + the RNG controller events: Polling mode or Interrupt mode. + + (#) In the Polling Mode it is advised to use the following functions: + (++) RNG_GetFlagStatus() : to check if flags events occur. + (++) RNG_ClearFlag() : to clear the flags events. + + -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only + by reading the Random number data. + + (#) In the Interrupt Mode it is advised to use the following functions: + (++) RNG_ITConfig() : to enable or disable the interrupt source. + (++) RNG_GetITStatus() : to check if Interrupt occurs. + (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the RNG interrupt. + * @note The RNG provides 3 interrupt sources, + * - Computed data is ready event (DRDY), and + * - Seed error Interrupt (SEI) and + * - Clock error Interrupt (CEI), + * all these interrupts sources are enabled by setting the IE bit in + * CR register. However, each interrupt have its specific status bit + * (see RNG_GetITStatus() function) and clear bit except the DRDY event + * (see RNG_ClearITPendingBit() function). + * @param NewState: new state of the RNG interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RNG_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the RNG interrupt */ + RNG->CR |= RNG_CR_IE; + } + else + { + /* Disable the RNG interrupt */ + RNG->CR &= ~RNG_CR_IE; + } +} + +/** + * @brief Checks whether the specified RNG flag is set or not. + * @param RNG_FLAG: specifies the RNG flag to check. + * This parameter can be one of the following values: + * @arg RNG_FLAG_DRDY: Data Ready flag. + * @arg RNG_FLAG_CECS: Clock Error Current flag. + * @arg RNG_FLAG_SECS: Seed Error Current flag. + * @retval The new state of RNG_FLAG (SET or RESET). + */ +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RNG_GET_FLAG(RNG_FLAG)); + + /* Check the status of the specified RNG flag */ + if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET) + { + /* RNG_FLAG is set */ + bitstatus = SET; + } + else + { + /* RNG_FLAG is reset */ + bitstatus = RESET; + } + /* Return the RNG_FLAG status */ + return bitstatus; +} + + +/** + * @brief Clears the RNG flags. + * @param RNG_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RNG_FLAG_CECS: Clock Error Current flag. + * @arg RNG_FLAG_SECS: Seed Error Current flag. + * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. + * This flag is cleared only by reading the Random number data (using + * RNG_GetRandomNumber() function). + * @retval None + */ +void RNG_ClearFlag(uint8_t RNG_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG)); + /* Clear the selected RNG flags */ + RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); +} + +/** + * @brief Checks whether the specified RNG interrupt has occurred or not. + * @param RNG_IT: specifies the RNG interrupt source to check. + * This parameter can be one of the following values: + * @arg RNG_IT_CEI: Clock Error Interrupt. + * @arg RNG_IT_SEI: Seed Error Interrupt. + * @retval The new state of RNG_IT (SET or RESET). + */ +ITStatus RNG_GetITStatus(uint8_t RNG_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RNG_GET_IT(RNG_IT)); + + /* Check the status of the specified RNG interrupt */ + if ((RNG->SR & RNG_IT) != (uint8_t)RESET) + { + /* RNG_IT is set */ + bitstatus = SET; + } + else + { + /* RNG_IT is reset */ + bitstatus = RESET; + } + /* Return the RNG_IT status */ + return bitstatus; +} + + +/** + * @brief Clears the RNG interrupt pending bit(s). + * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear. + * This parameter can be any combination of the following values: + * @arg RNG_IT_CEI: Clock Error Interrupt. + * @arg RNG_IT_SEI: Seed Error Interrupt. + * @retval None + */ +void RNG_ClearITPendingBit(uint8_t RNG_IT) +{ + /* Check the parameters */ + assert_param(IS_RNG_IT(RNG_IT)); + + /* Clear the selected RNG interrupt pending bit */ + RNG->SR = (uint8_t)~RNG_IT; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c index a7ecb6062..4861ade1d 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c @@ -1,2761 +1,2761 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rtc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization - * + Calendar (Time and Date) configuration - * + Alarms (Alarm A and Alarm B) configuration - * + WakeUp Timer configuration - * + Daylight Saving configuration - * + Output pin Configuration - * + Coarse digital Calibration configuration - * + Smooth digital Calibration configuration - * + TimeStamp configuration - * + Tampers configuration - * + Backup Data Registers configuration - * + Shift control synchronisation - * + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### Backup Domain Operating Condition ##### - =================================================================== - [..] The real-time clock (RTC), the RTC backup registers, and the backup - SRAM (BKP SRAM) can be powered from the VBAT voltage when the main - VDD supply is powered off. - To retain the content of the RTC backup registers, backup SRAM, and supply - the RTC when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - [..] To allow the RTC to operate even when the main digital supply (VDD) is turned - off, the VBAT pin powers the following blocks: - (#) The RTC - (#) The LSE oscillator - (#) The backup SRAM when the low power backup regulator is enabled - (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) - - [..] When the backup domain is supplied by VDD (analog switch connected to VDD), - the following functions are available: - (#) PC14 and PC15 can be used as either GPIO or LSE pins - (#) PC13 can be used as a GPIO or as the RTC_AF1 pin - (#) PI8 can be used as a GPIO or as the RTC_AF2 pin - - [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT - because VDD is not present), the following functions are available: - (#) PC14 and PC15 can be used as LSE pins only - (#) PC13 can be used as the RTC_AF1 pin - (#) PI8 can be used as the RTC_AF2 pin - - - ##### Backup Domain Reset ##### - =================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. The BKPSRAM is not affected by this reset. The only - way of resetting the BKPSRAM is through the Flash interface by requesting - a protection level change from 1 to 0. - [..] A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). You can use the - RCC_BackupResetCmd(). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - - - ##### Backup Domain Access ##### - =================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. - [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. - (+) Select the RTC clock source using the RCC_RTCCLKConfig() function. - (+) Enable RTC Clock using the RCC_RTCCLKCmd() function. - - - ##### How to use RTC Driver ##### - =================================================================== - [..] - (+) Enable the RTC domain access (see description in the section above) - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the RTC_Init() function. - - *** Time and Date configuration *** - =================================== - [..] - (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime() - and RTC_SetDate() functions. - (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() functions. - (+) Use the RTC_DayLightSavingConfig() function to add or sub one - hour to the RTC Calendar. - - *** Alarm configuration *** - =========================== - [..] - (+) To configure the RTC Alarm use the RTC_SetAlarm() function. - (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function - (+) To read the RTC Alarm, use the RTC_GetAlarm() function. - (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. - - *** RTC Wakeup configuration *** - ================================ - [..] - (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() - function. - (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() function - (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function - (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() - function. - - *** Outputs configuration *** - ============================= - [..] The RTC has 2 different outputs: - (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B - and WaKeUp signals. To output the selected RTC signal on RTC_AF1 pin, use the - RTC_OutputConfig() function. - (+) AFO_CALIB: this output is 512Hz signal or 1Hz. To output the RTC Clock on - RTC_AF1 pin, use the RTC_CalibOutputCmd() function. - - *** Smooth digital Calibration configuration *** - ================================================ - [..] - (+) Configure the RTC Original Digital Calibration Value and the corresponding - calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() - function. - - *** Coarse digital Calibration configuration *** - ================================================ - [..] - (+) Configure the RTC Coarse Calibration Value and the corresponding - sign using the RTC_CoarseCalibConfig() function. - (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() function - - *** TimeStamp configuration *** - =============================== - [..] - (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp using the RTC - _TimeStampCmd() function. - (+) To read the RTC TimeStamp Time and Date register, use the RTC_GetTimeStamp() - function. - (+) To read the RTC TimeStamp SubSecond register, use the - RTC_GetTimeStampSubSecond() function. - (+) The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) - or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in - RTC_TAFCR register. You can use the RTC_TamperPinSelection() function to - select the corresponding pin. - - *** Tamper configuration *** - ============================ - [..] - (+) Enable the RTC Tamper using the RTC_TamperCmd() function. - (+) Configure the Tamper filter count using RTC_TamperFilterConfig() - function. - (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper - filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() - function. - (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() - function. - (+) Configure the Tamper precharge or discharge duration using - RTC_TamperPinsPrechargeDuration() function. - (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. - (+) Enable the Time stamp on Tamper detection event using - TC_TSOnTamperDetecCmd() function. - (+) The TIMESTAMP alternate function can be mapped to either RTC_AF1 - or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR - register. You can use the RTC_TimeStampPinSelection() function to select - the corresponding pin. - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() - function. - (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() - function. - - - ##### RTC and low power modes ##### - =================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop and - Standby lowpower modes. - [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm - or the RTC wakeup events. - [..] The RTC provides a programmable time base for waking up from the - Stop or Standby mode at regular intervals. - Wakeup from STOP and Standby modes is possible only when the RTC clock source - is LSE or LSI. - - - ##### Selection of RTC_AF1 alternate functions ##### - =================================================================== - [..] The RTC_AF1 pin (PC13) can be used for the following purposes: - (+) AFO_ALARM output - (+) AFO_CALIB output - (+) AFI_TAMPER - (+) AFI_TIMESTAMP - - [..] - +-------------------------------------------------------------------------------------------------------------+ - | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - | and function | | | | | selection | selection |Configuration | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Alarm out | | | | | Don't | Don't | | - | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Alarm out | | | | | Don't | Don't | | - | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Calibration out | | | | | Don't | Don't | | - | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | TAMPER input | | | | | | Don't | | - | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP and | | | | | | | | - | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | - | floating | | | | | | | | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP input | | | | | Don't | | | - | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | - +-------------------------------------------------------------------------------------------------------------+ - - - ##### Selection of RTC_AF2 alternate functions ##### - =================================================================== - [..] The RTC_AF2 pin (PI8) can be used for the following purposes: - (+) AFI_TAMPER - (+) AFI_TIMESTAMP - [..] - +---------------------------------------------------------------------------------------+ - | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - | and function | | | selection | selection |Configuration | - |-----------------|-----------|--------------|------------|--------------|--------------| - | TAMPER input | | | | Don't | | - | floating | 1 | 0 | 1 | care | Don't care | - |-----------------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP and | | | | | | - | TAMPER input | 1 | 1 | 1 | 1 | Don't care | - | floating | | | | | | - |-----------------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP input | | | Don't | | | - | floating | 0 | 1 | care | 1 | Don't care | - |-----------------|-----------|--------------|------------|--------------|--------------| - | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | - +---------------------------------------------------------------------------------------+ - - -@endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rtc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ - RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) - -#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) -#define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000) -#define RECALPF_TIMEOUT ((uint32_t) 0x00020000) -#define SHPF_TIMEOUT ((uint32_t) 0x00001000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static uint8_t RTC_ByteToBcd2(uint8_t Value); -static uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** @defgroup RTC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to initialize and configure the RTC - Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers - Write protection, enter and exit the RTC initialization mode, RTC registers - synchronization check and reference clock detection enable. - - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is - split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize consumption. - - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - - (#) To Configure the RTC Calendar, user application should enter initialization - mode. In this mode, the calendar counter is stopped and its value can be - updated. When the initialization sequence is complete, the calendar restarts - counting after 4 RTCCLK cycles. - - (#) To read the calendar through the shadow registers after Calendar initialization, - calendar update or after wakeup from low power modes the software must first - clear the RSF flag. The software must then wait until it is set again before - reading the calendar, which means that the calendar registers have been - correctly copied into the RTC_TR and RTC_DR shadow registers. - The RTC_WaitForSynchro() function implements the above software sequence - (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data - * registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are deinitialized - * - ERROR: RTC registers are not deinitialized - */ -ErrorStatus RTC_DeInit(void) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - RTC->TR = (uint32_t)0x00000000; - RTC->DR = (uint32_t)0x00002101; - /* Reset All CR bits except CR[2:0] */ - RTC->CR &= (uint32_t)0x00000007; - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - /* Reset all RTC CR register bits */ - RTC->CR &= (uint32_t)0x00000000; - RTC->WUTR = (uint32_t)0x0000FFFF; - RTC->PRER = (uint32_t)0x007F00FF; - RTC->CALIBR = (uint32_t)0x00000000; - RTC->ALRMAR = (uint32_t)0x00000000; - RTC->ALRMBR = (uint32_t)0x00000000; - RTC->SHIFTR = (uint32_t)0x00000000; - RTC->CALR = (uint32_t)0x00000000; - RTC->ALRMASSR = (uint32_t)0x00000000; - RTC->ALRMBSSR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - RTC->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - RTC->TAFCR = 0x00000000; - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Clear RTC CR FMT Bit */ - RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); - /* Set RTC_CR register */ - RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); - - /* Configure the RTC PRER */ - RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); - RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_InitStruct member with its default value. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) -{ - /* Initialize the RTC_HourFormat member */ - RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; - - /* Initialize the RTC_AsynchPrediv member */ - RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; - - /* Initialize the RTC_SynchPrediv member */ - RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; -} - -/** - * @brief Enables or disables the RTC registers write protection. - * @note All the RTC registers are write protected except for RTC_ISR[13:8], - * RTC_TAFCR and RTC_BKPxR. - * @note Writing a wrong key reactivates the write protection. - * @note The protection mechanism is not affected by system reset. - * @param NewState: new state of the write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_WriteProtectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - } -} - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus RTC_EnterInitMode(void) -{ - __IO uint32_t initcounter = 0x00; - ErrorStatus status = ERROR; - uint32_t initstatus = 0x00; - - /* Check if the Initialization mode is set */ - if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do - { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_INITF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - } - else - { - status = SUCCESS; - } - - return (status); -} - -/** - * @brief Exits the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval None - */ -void RTC_ExitInitMode(void) -{ - /* Exit Initialization mode */ - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; -} - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus RTC_WaitForSynchro(void) -{ - __IO uint32_t synchrocounter = 0; - ErrorStatus status = ERROR; - uint32_t synchrostatus = 0x00; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear RSF flag */ - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Wait the registers to be synchronised */ - do - { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_RSF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (status); -} - -/** - * @brief Enables or disables the RTC reference clock detection. - * @param NewState: new state of the RTC reference clock. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC reference clock detection is enabled - * - ERROR: RTC reference clock detection is disabled - */ -ErrorStatus RTC_RefClockCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the RTC reference clock detection */ - RTC->CR |= RTC_CR_REFCKON; - } - else - { - /* Disable the RTC reference clock detection */ - RTC->CR &= ~RTC_CR_REFCKON; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or Disables the Bypass Shadow feature. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @param NewState: new state of the Bypass Shadow feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None -*/ -void RTC_BypassShadowCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Set the BYPSHAD bit */ - RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; - } - else - { - /* Reset the BYPSHAD bit */ - RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group2 Time and Date configuration functions - * @brief Time and Date configuration functions - * -@verbatim - =============================================================================== - ##### Time and Date configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to program and read the RTC Calendar - (Time and Date). - -@endverbatim - * @{ - */ - -/** - * @brief Set the RTC current time. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ - ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); - } - else - { - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ - (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_TR register */ - RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_TimeStruct member with its default value - * (Time = 00h:00min:00sec). - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->RTC_H12 = RTC_H12_AM; - RTC_TimeStruct->RTC_Hours = 0; - RTC_TimeStruct->RTC_Minutes = 0; - RTC_TimeStruct->RTC_Seconds = 0; -} - -/** - * @brief Get the RTC current Time. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contain the returned current time configuration. - * @retval None - */ -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); - RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); - } -} - -/** - * @brief Gets the RTC current Calendar Sub seconds value. - * @note This function freeze the Time and Date registers after reading the - * SSR register. - * @param None - * @retval RTC current Calendar Sub seconds value. - */ -uint32_t RTC_GetSubSecond(void) -{ - uint32_t tmpreg = 0; - - /* Get sub seconds values from the correspondent registers*/ - tmpreg = (uint32_t)(RTC->SSR); - - /* Read DR register to unfroze calendar registers */ - (void) (RTC->DR); - - return (tmpreg); -} - -/** - * @brief Set the RTC current date. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains - * the date configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Date register is configured - * - ERROR: RTC Date register is not configured - */ -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) - { - RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; - } - if (RTC_Format == RTC_Format_BIN) - { - assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); - assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); - assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - assert_param(IS_RTC_MONTH(tmpreg)); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - assert_param(IS_RTC_DATE(tmpreg)); - } - assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ - (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_DateStruct->RTC_Date) | \ - (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ - ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_DR register */ - RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_DateStruct member with its default value - * (Monday, January 01 xx00). - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) -{ - /* Monday, January 01 xx00 */ - RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; - RTC_DateStruct->RTC_Date = 1; - RTC_DateStruct->RTC_Month = RTC_Month_January; - RTC_DateStruct->RTC_Year = 0; -} - -/** - * @brief Get the RTC current date. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will - * contain the returned current date configuration. - * @retval None - */ -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); - RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); - RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group3 Alarms configuration functions - * @brief Alarms (Alarm A and Alarm B) configuration functions - * -@verbatim - =============================================================================== - ##### Alarms A and B configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to program and read the RTC Alarms. - -@endverbatim - * @{ - */ - -/** - * @brief Set the specified RTC Alarm. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the RTC_AlarmCmd(DISABLE)). - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval None - */ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm register */ - if (RTC_Alarm == RTC_Alarm_A) - { - RTC->ALRMAR = (uint32_t)tmpreg; - } - else - { - RTC->ALRMBR = (uint32_t)tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Fills each RTC_AlarmStruct member with its default value - * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = - * all fields are masked). - * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which - * will be initialized. - * @retval None - */ -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; - - /* Alarm Date Settings : Date = 1st day of the month */ - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; - RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will - * contains the output alarm configuration values. - * @retval None - */ -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)(RTC->ALRMAR); - } - else - { - tmpreg = (uint32_t)(RTC->ALRMBR); - } - - /* Fill the structure with the read parameters */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ - RTC_ALRMAR_HU)) >> 16); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ - RTC_ALRMAR_MNU)) >> 8); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ - RTC_ALRMAR_SU)); - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); - - if (RTC_Format == RTC_Format_BIN) - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Hours); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Minutes); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Seconds); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - } -} - -/** - * @brief Enables or disables the specified RTC Alarm. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be any combination of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param NewState: new state of the specified alarm. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Alarm is enabled/disabled - * - ERROR: RTC Alarm is not enabled/disabled - */ -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) -{ - __IO uint32_t alarmcounter = 0x00; - uint32_t alarmstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm state */ - if (NewState != DISABLE) - { - RTC->CR |= (uint32_t)RTC_Alarm; - - status = SUCCESS; - } - else - { - /* Disable the Alarm in RTC_CR register */ - RTC->CR &= (uint32_t)~RTC_Alarm; - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - do - { - alarmstatus = RTC->ISR & (RTC_Alarm >> 8); - alarmcounter++; - } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); - - if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Configure the RTC AlarmA/B Sub seconds value and mask.* - * @note This function is performed only when the Alarm is disabled. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmSubSecondValue: specifies the Sub seconds value. - * This parameter can be a value from 0 to 0x00007FFF. - * @param RTC_AlarmSubSecondMask: specifies the Sub seconds Mask. - * This parameter can be any combination of the following values: - * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. - * There is no comparison on sub seconds for Alarm. - * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison. - * Only SS[0] is compared - * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison. - * Only SS[1:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison. - * Only SS[2:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison. - * Only SS[3:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison. - * Only SS[4:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison. - * Only SS[5:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison. - * Only SS[6:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison. - * Only SS[7:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison. - * Only SS[8:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. - * Only SS[9:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. - * Only SS[10:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. - * Only SS[11:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. - * Only SS[12:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison. - * Only SS[13:0] are compared - * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match - * to activate alarm - * @retval None - */ -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm A or Alarm B Sub Second registers */ - tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); - - if (RTC_Alarm == RTC_Alarm_A) - { - /* Configure the Alarm A Sub Second register */ - RTC->ALRMASSR = tmpreg; - } - else - { - /* Configure the Alarm B Sub Second register */ - RTC->ALRMBSSR = tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - -} - -/** - * @brief Gets the RTC Alarm Sub seconds value. - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param None - * @retval RTC Alarm Sub seconds value. - */ -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) -{ - uint32_t tmpreg = 0; - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); - } - else - { - tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); - } - - return (tmpreg); -} - -/** - * @} - */ - -/** @defgroup RTC_Group4 WakeUp Timer configuration functions - * @brief WakeUp Timer configuration functions - * -@verbatim - =============================================================================== - ##### WakeUp Timer configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to program and read the RTC WakeUp. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Wakeup clock source. - * @note The WakeUp Clock source can only be changed when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpClock: Wakeup Clock source. - * This parameter can be one of the following values: - * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 - * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 - * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 - * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 - * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE - * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE - * @retval None - */ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the Wakeup Timer clock source bits in CR register */ - RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - RTC->CR |= (uint32_t)RTC_WakeUpClock; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the RTC Wakeup counter. - * @note The RTC WakeUp counter can only be written when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpCounter: specifies the WakeUp counter. - * This parameter can be a value from 0x0000 to 0xFFFF. - * @retval None - */ -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Wakeup Timer counter */ - RTC->WUTR = (uint32_t)RTC_WakeUpCounter; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC WakeUp timer counter value. - * @param None - * @retval The RTC WakeUp Counter value. - */ -uint32_t RTC_GetWakeUpCounter(void) -{ - /* Get the counter value */ - return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Enables or Disables the RTC WakeUp timer. - * @param NewState: new state of the WakeUp timer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the Wakeup Timer */ - RTC->CR |= (uint32_t)RTC_CR_WUTE; - status = SUCCESS; - } - else - { - /* Disable the Wakeup Timer */ - RTC->CR &= (uint32_t)~RTC_CR_WUTE; - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group5 Daylight Saving configuration functions - * @brief Daylight Saving configuration functions - * -@verbatim - =============================================================================== - ##### Daylight Saving configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure the RTC DayLight Saving. - -@endverbatim - * @{ - */ - -/** - * @brief Adds or substract one hour from the current time. - * @param RTC_DayLightSaveOperation: the value of hour adjustment. - * This parameter can be one of the following values: - * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) - * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) - * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit - * in CR register to store the operation. - * This parameter can be one of the following values: - * @arg RTC_StoreOperation_Reset: BCK Bit Reset - * @arg RTC_StoreOperation_Set: BCK Bit Set - * @retval None - */ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) -{ - /* Check the parameters */ - assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_BCK); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC Day Light Saving stored operation. - * @param None - * @retval RTC Day Light Saving stored operation. - * - RTC_StoreOperation_Reset - * - RTC_StoreOperation_Set - */ -uint32_t RTC_GetStoreOperation(void) -{ - return (RTC->CR & RTC_CR_BCK); -} - -/** - * @} - */ - -/** @defgroup RTC_Group6 Output pin Configuration function - * @brief Output pin Configuration function - * -@verbatim - =============================================================================== - ##### Output pin Configuration function ##### - =============================================================================== - - [..] This section provide functions allowing to configure the RTC Output source. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC output source (AFO_ALARM). - * @param RTC_Output: Specifies which signal will be routed to the RTC output. - * This parameter can be one of the following values: - * @arg RTC_Output_Disable: No output selected - * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output - * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output - * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output - * @param RTC_OutputPolarity: Specifies the polarity of the output signal. - * This parameter can be one of the following: - * @arg RTC_OutputPolarity_High: The output pin is high when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @arg RTC_OutputPolarity_Low: The output pin is low when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @retval None - */ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT(RTC_Output)); - assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); - - /* Configure the output selection and polarity */ - RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group7 Digital Calibration configuration functions - * @brief Coarse Calibration configuration functions - * -@verbatim - =============================================================================== - ##### Digital Calibration configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Coarse calibration parameters. - * @param RTC_CalibSign: specifies the sign of the coarse calibration value. - * This parameter can be one of the following values: - * @arg RTC_CalibSign_Positive: The value sign is positive - * @arg RTC_CalibSign_Negative: The value sign is negative - * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). - * - * @note This Calibration value should be between 0 and 63 when using negative - * sign with a 2-ppm step. - * - * @note This Calibration value should be between 0 and 126 when using positive - * sign with a 4-ppm step. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are initialized - * - ERROR: RTC Coarse calibration are not initialized - */ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); - assert_param(IS_RTC_CALIB_VALUE(Value)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the coarse calibration value */ - RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the Coarse calibration process. - * @param NewState: new state of the Coarse calibration. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are enabled/disabled - * - ERROR: RTC Coarse calibration are not enabled/disabled - */ -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the Coarse Calibration */ - RTC->CR |= (uint32_t)RTC_CR_DCE; - } - else - { - /* Disable the Coarse Calibration */ - RTC->CR &= (uint32_t)~RTC_CR_DCE; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the RTC clock to be output through the relative pin. - * @param NewState: new state of the digital calibration Output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_CalibOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the RTC clock output */ - RTC->CR |= (uint32_t)RTC_CR_COE; - } - else - { - /* Disable the RTC clock output */ - RTC->CR &= (uint32_t)~RTC_CR_COE; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param RTC_CalibOutput : Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. - * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz. - * @retval None -*/ -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /*clear flags before configuration */ - RTC->CR &= (uint32_t)~(RTC_CR_COSEL); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)RTC_CalibOutput; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the Smooth Calibration Settings. - * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period. - * This parameter can be can be one of the following values: - * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration period is 32s. - * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration period is 16s. - * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion period is 8s. - * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses. - * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. - * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Calib registers are configured - * - ERROR: RTC Calib registers are not configured -*/ -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue) -{ - ErrorStatus status = ERROR; - uint32_t recalpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* check if a calibration is pending*/ - if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) - { - /* wait until the Calibration is completed*/ - while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) - { - recalpfcount++; - } - } - - /* check if the calibration pending is completed or if there is no calibration operation at all*/ - if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) - { - /* Configure the Smooth calibration settings */ - RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); - - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - - -/** @defgroup RTC_Group8 TimeStamp configuration functions - * @brief TimeStamp configuration functions - * -@verbatim - =============================================================================== - ##### TimeStamp configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or Disables the RTC TimeStamp functionality with the - * specified time stamp pin stimulating edge. - * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following: - * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising - * edge of the related pin. - * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the - * falling edge of the related pin. - * @param NewState: new state of the TimeStamp. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Get the new configuration */ - if (NewState != DISABLE) - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); - } - else - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Time Stamp TSEDGE and Enable bits */ - RTC->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Get the RTC TimeStamp value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contains the TimeStamp time values. - * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will - * contains the TimeStamp date values. - * @retval None - */ -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - - /* Fill the Date structure fields with the read parameters */ - RTC_StampDateStruct->RTC_Year = 0; - RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the Time structure parameters to Binary format */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); - - /* Convert the Date structure parameters to Binary format */ - RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); - RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); - } -} - -/** - * @brief Get the RTC timestamp Sub seconds value. - * @param None - * @retval RTC current timestamp Sub seconds value. - */ -uint32_t RTC_GetTimeStampSubSecond(void) -{ - /* Get timestamp sub seconds values from the correspondent registers */ - return (uint32_t)(RTC->TSSSR); -} - -/** - * @} - */ - -/** @defgroup RTC_Group9 Tampers configuration functions - * @brief Tampers configuration functions - * -@verbatim - =============================================================================== - ##### Tampers configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the select Tamper pin edge. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that - * stimulates tamper event. - * This parameter can be one of the following values: - * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. - * @retval None - */ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); - - if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); - } - else - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); - } -} - -/** - * @brief Enables or Disables the Tamper detection. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param NewState: new state of the tamper pin. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_Tamper; - } - else - { - /* Disable the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_Tamper; - } -} - -/** - * @brief Configures the Tampers Filter. - * @param RTC_TamperFilter: Specifies the tampers filter. - * This parameter can be one of the following values: - * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. - * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive - * samples at the active level - * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive - * samples at the active level - * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive - * samples at the active level - * @retval None - */ -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); - - /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperFilter; -} - -/** - * @brief Configures the Tampers Sampling Frequency. - * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. - * This parameter can be one of the following values: - * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 32768 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 16384 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 8192 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 4096 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 2048 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 1024 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 512 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 256 - * @retval None - */ -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); - - /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; -} - -/** - * @brief Configures the Tampers Pins input Precharge Duration. - * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input - * Precharge Duration. - * This parameter can be one of the following values: - * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged before sampling during 1 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged before sampling during 2 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged before sampling during 4 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged before sampling during 8 RTCCLK cycle - * @retval None - */ -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); - - /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; -} - -/** - * @brief Enables or Disables the TimeStamp on Tamper Detection Event. - * @note The timestamp is valid even the TSE bit in tamper control register - * is reset. - * @param NewState: new state of the timestamp on tamper event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Save timestamp on tamper detection event */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; - } - else - { - /* Tamper detection does not cause a timestamp to be saved */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; - } -} - -/** - * @brief Enables or Disables the Precharge of Tamper pin. - * @param NewState: new state of tamper pull up. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperPullUpCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable precharge of the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; - } - else - { - /* Disable precharge of the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group10 Backup Data Registers configuration functions - * @brief Backup Data Registers configuration functions - * -@verbatim - =============================================================================== - ##### Backup Data Registers configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval None - */ -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @} - */ - -/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions - * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config - * configuration functions - * -@verbatim - ================================================================================================== - ##### RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions ##### - ================================================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Selects the RTC Tamper Pin. - * @param RTC_TamperPin: specifies the RTC Tamper Pin. - * This parameter can be one of the following values: - * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin. - * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin. - * @retval None - */ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TamperPin); -} - -/** - * @brief Selects the RTC TimeStamp Pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. - * @retval None - */ -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); -} - -/** - * @brief Configures the RTC Output Pin mode. - * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. - * This parameter can be one of the following values: - * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in - * Open Drain mode. - * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in - * Push Pull mode. - * @retval None - */ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); - RTC->TAFCR |= (uint32_t)(RTC_OutputType); -} - -/** - * @} - */ - -/** @defgroup RTC_Group12 Shift control synchronisation functions - * @brief Shift control synchronisation functions - * -@verbatim - =============================================================================== - ##### Shift control synchronisation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register - * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar. - * This parameter can be one of the following values : - * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar. - * @arg RTC_ShiftAdd1S_Reset: No effect. - * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Shift registers are configured - * - ERROR: RTC Shift registers are not configured -*/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) -{ - ErrorStatus status = ERROR; - uint32_t shpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Check if a Shift is pending*/ - if ((RTC->ISR & RTC_ISR_SHPF) != RESET) - { - /* Wait until the shift is completed*/ - while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) - { - shpfcount++; - } - } - - /* Check if the Shift pending is completed or if there is no Shift operation at all*/ - if ((RTC->ISR & RTC_ISR_SHPF) == RESET) - { - /* check if the reference clock detection is disabled */ - if((RTC->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = ERROR; - } - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - -/** @defgroup RTC_Group13 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] All RTC interrupts are connected to the EXTI controller. - - (+) To enable the RTC Alarm interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 17 in interrupt mode and select - the rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using - the RTC_SetAlarm() and RTC_AlarmCmd() functions. - - (+) To enable the RTC Wakeup interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 22 in interrupt mode and select the - rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to generate the RTC wakeup timer event using the - RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() - functions. - - (+) To enable the RTC Tamper interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 21 in interrupt mode and select - the rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to detect the RTC tamper event using the - RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - - (+) To enable the RTC TimeStamp interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 21 in interrupt mode and select the - rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to detect the RTC time stamp event using the - RTC_TimeStampCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt mask - * @arg RTC_IT_WUT: WakeUp Timer interrupt mask - * @arg RTC_IT_ALRB: Alarm B interrupt mask - * @arg RTC_IT_ALRA: Alarm A interrupt mask - * @arg RTC_IT_TAMP: Tamper event interrupt mask - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_CONFIG_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); - } - else - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RTC_FLAG_RECALPF: RECALPF event flag. - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_INITF: Initialization mode flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_INITS: Registers Configured flag - * @arg RTC_FLAG_SHPF: Shift operation pending flag. - * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag - * @arg RTC_FLAG_ALRBWF: Alarm B Write flag - * @arg RTC_FLAG_ALRAWF: Alarm A write flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - /* Get all the flags */ - tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); - - /* Return the status of the flag */ - if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the RTC flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @retval None - */ -void RTC_ClearFlag(uint32_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the Flags in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupt source to check. - * This parameter can be one of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval The new state of RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint32_t RTC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - /* Get the TAMPER Interrupt enable bit and pending bit */ - tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); - - /* Get the Interrupt enable Status */ - enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15))); - - /* Get the Interrupt pending bit */ - tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); - - /* Get the status of the Interrupt */ - if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the RTC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint32_t RTC_IT) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_IT(RTC_IT)); - - /* Get the RTC_ISR Interrupt pending bits mask */ - tmpreg = (uint32_t)(RTC_IT >> 4); - - /* Clear the interrupt pending bits in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @} - */ - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted. - * @retval Converted byte - */ -static uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint8_t bcdhigh = 0; - - while (Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted. - * @retval Converted word - */ -static uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint8_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_rtc.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * + Initialization + * + Calendar (Time and Date) configuration + * + Alarms (Alarm A and Alarm B) configuration + * + WakeUp Timer configuration + * + Daylight Saving configuration + * + Output pin Configuration + * + Coarse digital Calibration configuration + * + Smooth digital Calibration configuration + * + TimeStamp configuration + * + Tampers configuration + * + Backup Data Registers configuration + * + Shift control synchronisation + * + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration + * + Interrupts and flags management + * +@verbatim + + =================================================================== + ##### Backup Domain Operating Condition ##### + =================================================================== + [..] The real-time clock (RTC), the RTC backup registers, and the backup + SRAM (BKP SRAM) can be powered from the VBAT voltage when the main + VDD supply is powered off. + To retain the content of the RTC backup registers, backup SRAM, and supply + the RTC when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + [..] To allow the RTC to operate even when the main digital supply (VDD) is turned + off, the VBAT pin powers the following blocks: + (#) The RTC + (#) The LSE oscillator + (#) The backup SRAM when the low power backup regulator is enabled + (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) + + [..] When the backup domain is supplied by VDD (analog switch connected to VDD), + the following functions are available: + (#) PC14 and PC15 can be used as either GPIO or LSE pins + (#) PC13 can be used as a GPIO or as the RTC_AF1 pin + (#) PI8 can be used as a GPIO or as the RTC_AF2 pin + + [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT + because VDD is not present), the following functions are available: + (#) PC14 and PC15 can be used as LSE pins only + (#) PC13 can be used as the RTC_AF1 pin + (#) PI8 can be used as the RTC_AF2 pin + + + ##### Backup Domain Reset ##### + =================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR register + to their reset values. The BKPSRAM is not affected by this reset. The only + way of resetting the BKPSRAM is through the Flash interface by requesting + a protection level change from 1 to 0. + [..] A backup domain reset is generated when one of the following events occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). You can use the + RCC_BackupResetCmd(). + (#) VDD or VBAT power on, if both supplies have previously been powered off. + + + ##### Backup Domain Access ##### + =================================================================== + [..] After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted write + accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + RCC_APB1PeriphClockCmd() function. + (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. + (+) Select the RTC clock source using the RCC_RTCCLKConfig() function. + (+) Enable RTC Clock using the RCC_RTCCLKCmd() function. + + + ##### How to use RTC Driver ##### + =================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above) + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the RTC_Init() function. + + *** Time and Date configuration *** + =================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime() + and RTC_SetDate() functions. + (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() functions. + (+) Use the RTC_DayLightSavingConfig() function to add or sub one + hour to the RTC Calendar. + + *** Alarm configuration *** + =========================== + [..] + (+) To configure the RTC Alarm use the RTC_SetAlarm() function. + (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function + (+) To read the RTC Alarm, use the RTC_GetAlarm() function. + (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. + + *** RTC Wakeup configuration *** + ================================ + [..] + (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() + function. + (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() function + (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function + (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() + function. + + *** Outputs configuration *** + ============================= + [..] The RTC has 2 different outputs: + (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B + and WaKeUp signals. To output the selected RTC signal on RTC_AF1 pin, use the + RTC_OutputConfig() function. + (+) AFO_CALIB: this output is 512Hz signal or 1Hz. To output the RTC Clock on + RTC_AF1 pin, use the RTC_CalibOutputCmd() function. + + *** Smooth digital Calibration configuration *** + ================================================ + [..] + (+) Configure the RTC Original Digital Calibration Value and the corresponding + calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() + function. + + *** Coarse digital Calibration configuration *** + ================================================ + [..] + (+) Configure the RTC Coarse Calibration Value and the corresponding + sign using the RTC_CoarseCalibConfig() function. + (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() function + + *** TimeStamp configuration *** + =============================== + [..] + (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp using the RTC + _TimeStampCmd() function. + (+) To read the RTC TimeStamp Time and Date register, use the RTC_GetTimeStamp() + function. + (+) To read the RTC TimeStamp SubSecond register, use the + RTC_GetTimeStampSubSecond() function. + (+) The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) + or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in + RTC_TAFCR register. You can use the RTC_TamperPinSelection() function to + select the corresponding pin. + + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper using the RTC_TamperCmd() function. + (+) Configure the Tamper filter count using RTC_TamperFilterConfig() + function. + (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper + filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() + function. + (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() + function. + (+) Configure the Tamper precharge or discharge duration using + RTC_TamperPinsPrechargeDuration() function. + (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. + (+) Enable the Time stamp on Tamper detection event using + TC_TSOnTamperDetecCmd() function. + (+) The TIMESTAMP alternate function can be mapped to either RTC_AF1 + or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR + register. You can use the RTC_TimeStampPinSelection() function to select + the corresponding pin. + + *** Backup Data Registers configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() + function. + (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() + function. + + + ##### RTC and low power modes ##### + =================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + RTC wakeup, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby lowpower modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm + or the RTC wakeup events. + [..] The RTC provides a programmable time base for waking up from the + Stop or Standby mode at regular intervals. + Wakeup from STOP and Standby modes is possible only when the RTC clock source + is LSE or LSI. + + + ##### Selection of RTC_AF1 alternate functions ##### + =================================================================== + [..] The RTC_AF1 pin (PC13) can be used for the following purposes: + (+) AFO_ALARM output + (+) AFO_CALIB output + (+) AFI_TAMPER + (+) AFI_TIMESTAMP + + [..] + +-------------------------------------------------------------------------------------------------------------+ + | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | + | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | + | and function | | | | | selection | selection |Configuration | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | Alarm out | | | | | Don't | Don't | | + | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | Alarm out | | | | | Don't | Don't | | + | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | Calibration out | | | | | Don't | Don't | | + | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | TAMPER input | | | | | | Don't | | + | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | TIMESTAMP and | | | | | | | | + | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | + | floating | | | | | | | | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | TIMESTAMP input | | | | | Don't | | | + | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | + +-------------------------------------------------------------------------------------------------------------+ + + + ##### Selection of RTC_AF2 alternate functions ##### + =================================================================== + [..] The RTC_AF2 pin (PI8) can be used for the following purposes: + (+) AFI_TAMPER + (+) AFI_TIMESTAMP + [..] + +---------------------------------------------------------------------------------------+ + | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | + | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | + | and function | | | selection | selection |Configuration | + |-----------------|-----------|--------------|------------|--------------|--------------| + | TAMPER input | | | | Don't | | + | floating | 1 | 0 | 1 | care | Don't care | + |-----------------|-----------|--------------|------------|--------------|--------------| + | TIMESTAMP and | | | | | | + | TAMPER input | 1 | 1 | 1 | 1 | Don't care | + | floating | | | | | | + |-----------------|-----------|--------------|------------|--------------|--------------| + | TIMESTAMP input | | | Don't | | | + | floating | 0 | 1 | care | 1 | Don't care | + |-----------------|-----------|--------------|------------|--------------|--------------| + | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | + +---------------------------------------------------------------------------------------+ + + +@endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_rtc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) +#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ + RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ + RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ + RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ + RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) + +#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) +#define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000) +#define RECALPF_TIMEOUT ((uint32_t) 0x00020000) +#define SHPF_TIMEOUT ((uint32_t) 0x00001000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** @defgroup RTC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to initialize and configure the RTC + Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers + Write protection, enter and exit the RTC initialization mode, RTC registers + synchronization check and reference clock detection enable. + + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is + split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize consumption. + + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + + (#) To Configure the RTC Calendar, user application should enter initialization + mode. In this mode, the calendar counter is stopped and its value can be + updated. When the initialization sequence is complete, the calendar restarts + counting after 4 RTCCLK cycles. + + (#) To read the calendar through the shadow registers after Calendar initialization, + calendar update or after wakeup from low power modes the software must first + clear the RSF flag. The software must then wait until it is set again before + reading the calendar, which means that the calendar registers have been + correctly copied into the RTC_TR and RTC_DR shadow registers. + The RTC_WaitForSynchro() function implements the above software sequence + (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are deinitialized + * - ERROR: RTC registers are not deinitialized + */ +ErrorStatus RTC_DeInit(void) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Reset TR, DR and CR registers */ + RTC->TR = (uint32_t)0x00000000; + RTC->DR = (uint32_t)0x00002101; + /* Reset All CR bits except CR[2:0] */ + RTC->CR &= (uint32_t)0x00000007; + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; + wutcounter++; + } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) + { + status = ERROR; + } + else + { + /* Reset all RTC CR register bits */ + RTC->CR &= (uint32_t)0x00000000; + RTC->WUTR = (uint32_t)0x0000FFFF; + RTC->PRER = (uint32_t)0x007F00FF; + RTC->CALIBR = (uint32_t)0x00000000; + RTC->ALRMAR = (uint32_t)0x00000000; + RTC->ALRMBR = (uint32_t)0x00000000; + RTC->SHIFTR = (uint32_t)0x00000000; + RTC->CALR = (uint32_t)0x00000000; + RTC->ALRMASSR = (uint32_t)0x00000000; + RTC->ALRMBSSR = (uint32_t)0x00000000; + + /* Reset ISR register and exit initialization mode */ + RTC->ISR = (uint32_t)0x00000000; + + /* Reset Tamper and alternate functions configuration register */ + RTC->TAFCR = 0x00000000; + + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Clear RTC CR FMT Bit */ + RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); + /* Set RTC_CR register */ + RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); + + /* Configure the RTC PRER */ + RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); + RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_InitStruct member with its default value. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) +{ + /* Initialize the RTC_HourFormat member */ + RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; + + /* Initialize the RTC_AsynchPrediv member */ + RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; + + /* Initialize the RTC_SynchPrediv member */ + RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; +} + +/** + * @brief Enables or disables the RTC registers write protection. + * @note All the RTC registers are write protected except for RTC_ISR[13:8], + * RTC_TAFCR and RTC_BKPxR. + * @note Writing a wrong key reactivates the write protection. + * @note The protection mechanism is not affected by system reset. + * @param NewState: new state of the write protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_WriteProtectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + } +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus RTC_EnterInitMode(void) +{ + __IO uint32_t initcounter = 0x00; + ErrorStatus status = ERROR; + uint32_t initstatus = 0x00; + + /* Check if the Initialization mode is set */ + if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + RTC->ISR = (uint32_t)RTC_INIT_MASK; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do + { + initstatus = RTC->ISR & RTC_ISR_INITF; + initcounter++; + } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_INITF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + } + else + { + status = SUCCESS; + } + + return (status); +} + +/** + * @brief Exits the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @param None + * @retval None + */ +void RTC_ExitInitMode(void) +{ + /* Exit Initialization mode */ + RTC->ISR &= (uint32_t)~RTC_ISR_INIT; +} + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus RTC_WaitForSynchro(void) +{ + __IO uint32_t synchrocounter = 0; + ErrorStatus status = ERROR; + uint32_t synchrostatus = 0x00; + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear RSF flag */ + RTC->ISR &= (uint32_t)RTC_RSF_MASK; + + /* Wait the registers to be synchronised */ + do + { + synchrostatus = RTC->ISR & RTC_ISR_RSF; + synchrocounter++; + } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_RSF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return (status); +} + +/** + * @brief Enables or disables the RTC reference clock detection. + * @param NewState: new state of the RTC reference clock. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC reference clock detection is enabled + * - ERROR: RTC reference clock detection is disabled + */ +ErrorStatus RTC_RefClockCmd(FunctionalState NewState) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (NewState != DISABLE) + { + /* Enable the RTC reference clock detection */ + RTC->CR |= RTC_CR_REFCKON; + } + else + { + /* Disable the RTC reference clock detection */ + RTC->CR &= ~RTC_CR_REFCKON; + } + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Enables or Disables the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param NewState: new state of the Bypass Shadow feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None +*/ +void RTC_BypassShadowCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Set the BYPSHAD bit */ + RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; + } + else + { + /* Reset the BYPSHAD bit */ + RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @} + */ + +/** @defgroup RTC_Group2 Time and Date configuration functions + * @brief Time and Date configuration functions + * +@verbatim + =============================================================================== + ##### Time and Date configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to program and read the RTC Calendar + (Time and Date). + +@endverbatim + * @{ + */ + +/** + * @brief Set the RTC current time. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == RTC_Format_BIN) + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + RTC_TimeStruct->RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); + } + else + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + RTC_TimeStruct->RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ + ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); + } + else + { + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ + (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_TR register */ + RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) + { + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_TimeStruct member with its default value + * (Time = 00h:00min:00sec). + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->RTC_H12 = RTC_H12_AM; + RTC_TimeStruct->RTC_Hours = 0; + RTC_TimeStruct->RTC_Minutes = 0; + RTC_TimeStruct->RTC_Seconds = 0; +} + +/** + * @brief Get the RTC current Time. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contain the returned current time configuration. + * @retval None + */ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); + RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); + RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); + RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); + RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); + } +} + +/** + * @brief Gets the RTC current Calendar Sub seconds value. + * @note This function freeze the Time and Date registers after reading the + * SSR register. + * @param None + * @retval RTC current Calendar Sub seconds value. + */ +uint32_t RTC_GetSubSecond(void) +{ + uint32_t tmpreg = 0; + + /* Get sub seconds values from the correspondent registers*/ + tmpreg = (uint32_t)(RTC->SSR); + + /* Read DR register to unfroze calendar registers */ + (void) (RTC->DR); + + return (tmpreg); +} + +/** + * @brief Set the RTC current date. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * the date configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Date register is configured + * - ERROR: RTC Date register is not configured + */ +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) + { + RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; + } + if (RTC_Format == RTC_Format_BIN) + { + assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); + assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); + assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); + tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); + assert_param(IS_RTC_MONTH(tmpreg)); + tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); + assert_param(IS_RTC_DATE(tmpreg)); + } + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ + (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_DateStruct->RTC_Date) | \ + (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); + } + else + { + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ + ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_DR register */ + RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) + { + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_DateStruct member with its default value + * (Monday, January 01 xx00). + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; + RTC_DateStruct->RTC_Date = 1; + RTC_DateStruct->RTC_Month = RTC_Month_January; + RTC_DateStruct->RTC_Year = 0; +} + +/** + * @brief Get the RTC current date. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will + * contain the returned current date configuration. + * @retval None + */ +void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); + RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); + RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); + RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); + RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); + RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group3 Alarms configuration functions + * @brief Alarms (Alarm A and Alarm B) configuration functions + * +@verbatim + =============================================================================== + ##### Alarms A and B configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to program and read the RTC Alarms. + +@endverbatim + * @{ + */ + +/** + * @brief Set the specified RTC Alarm. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the RTC_AlarmCmd(DISABLE)). + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval None + */ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); + + if (RTC_Format == RTC_Format_BIN) + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); + + if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + } + else + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); + + if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + } + else + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + } + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + else + { + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm register */ + if (RTC_Alarm == RTC_Alarm_A) + { + RTC->ALRMAR = (uint32_t)tmpreg; + } + else + { + RTC->ALRMBR = (uint32_t)tmpreg; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Fills each RTC_AlarmStruct member with its default value + * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = + * all fields are masked). + * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which + * will be initialized. + * @retval None + */ +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; + + /* Alarm Date Settings : Date = 1st day of the month */ + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; + RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will + * contains the output alarm configuration values. + * @retval None + */ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM(RTC_Alarm)); + + /* Get the RTC_ALRMxR register */ + if (RTC_Alarm == RTC_Alarm_A) + { + tmpreg = (uint32_t)(RTC->ALRMAR); + } + else + { + tmpreg = (uint32_t)(RTC->ALRMBR); + } + + /* Fill the structure with the read parameters */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ + RTC_ALRMAR_HU)) >> 16); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ + RTC_ALRMAR_MNU)) >> 8); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ + RTC_ALRMAR_SU)); + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); + + if (RTC_Format == RTC_Format_BIN) + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Hours); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Minutes); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Seconds); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + } +} + +/** + * @brief Enables or disables the specified RTC Alarm. + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be any combination of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param NewState: new state of the specified alarm. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Alarm is enabled/disabled + * - ERROR: RTC Alarm is not enabled/disabled + */ +ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) +{ + __IO uint32_t alarmcounter = 0x00; + uint32_t alarmstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm state */ + if (NewState != DISABLE) + { + RTC->CR |= (uint32_t)RTC_Alarm; + + status = SUCCESS; + } + else + { + /* Disable the Alarm in RTC_CR register */ + RTC->CR &= (uint32_t)~RTC_Alarm; + + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ + do + { + alarmstatus = RTC->ISR & (RTC_Alarm >> 8); + alarmcounter++; + } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); + + if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Configure the RTC AlarmA/B Sub seconds value and mask.* + * @note This function is performed only when the Alarm is disabled. + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param RTC_AlarmSubSecondValue: specifies the Sub seconds value. + * This parameter can be a value from 0 to 0x00007FFF. + * @param RTC_AlarmSubSecondMask: specifies the Sub seconds Mask. + * This parameter can be any combination of the following values: + * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. + * There is no comparison on sub seconds for Alarm. + * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison. + * Only SS[0] is compared + * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison. + * Only SS[1:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison. + * Only SS[2:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison. + * Only SS[3:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison. + * Only SS[4:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison. + * Only SS[5:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison. + * Only SS[6:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison. + * Only SS[7:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison. + * Only SS[8:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. + * Only SS[9:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. + * Only SS[10:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. + * Only SS[11:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. + * Only SS[12:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison. + * Only SS[13:0] are compared + * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match + * to activate alarm + * @retval None + */ +void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm A or Alarm B Sub Second registers */ + tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); + + if (RTC_Alarm == RTC_Alarm_A) + { + /* Configure the Alarm A Sub Second register */ + RTC->ALRMASSR = tmpreg; + } + else + { + /* Configure the Alarm B Sub Second register */ + RTC->ALRMBSSR = tmpreg; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + +} + +/** + * @brief Gets the RTC Alarm Sub seconds value. + * @param RTC_Alarm: specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param None + * @retval RTC Alarm Sub seconds value. + */ +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) +{ + uint32_t tmpreg = 0; + + /* Get the RTC_ALRMxR register */ + if (RTC_Alarm == RTC_Alarm_A) + { + tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); + } + else + { + tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); + } + + return (tmpreg); +} + +/** + * @} + */ + +/** @defgroup RTC_Group4 WakeUp Timer configuration functions + * @brief WakeUp Timer configuration functions + * +@verbatim + =============================================================================== + ##### WakeUp Timer configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to program and read the RTC WakeUp. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Wakeup clock source. + * @note The WakeUp Clock source can only be changed when the RTC WakeUp + * is disabled (Use the RTC_WakeUpCmd(DISABLE)). + * @param RTC_WakeUpClock: Wakeup Clock source. + * This parameter can be one of the following values: + * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 + * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 + * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 + * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 + * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE + * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE + * @retval None + */ +void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) +{ + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the Wakeup Timer clock source bits in CR register */ + RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + RTC->CR |= (uint32_t)RTC_WakeUpClock; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Configures the RTC Wakeup counter. + * @note The RTC WakeUp counter can only be written when the RTC WakeUp + * is disabled (Use the RTC_WakeUpCmd(DISABLE)). + * @param RTC_WakeUpCounter: specifies the WakeUp counter. + * This parameter can be a value from 0x0000 to 0xFFFF. + * @retval None + */ +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) +{ + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Wakeup Timer counter */ + RTC->WUTR = (uint32_t)RTC_WakeUpCounter; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Returns the RTC WakeUp timer counter value. + * @param None + * @retval The RTC WakeUp Counter value. + */ +uint32_t RTC_GetWakeUpCounter(void) +{ + /* Get the counter value */ + return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); +} + +/** + * @brief Enables or Disables the RTC WakeUp timer. + * @param NewState: new state of the WakeUp timer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Enable the Wakeup Timer */ + RTC->CR |= (uint32_t)RTC_CR_WUTE; + status = SUCCESS; + } + else + { + /* Disable the Wakeup Timer */ + RTC->CR &= (uint32_t)~RTC_CR_WUTE; + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; + wutcounter++; + } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @} + */ + +/** @defgroup RTC_Group5 Daylight Saving configuration functions + * @brief Daylight Saving configuration functions + * +@verbatim + =============================================================================== + ##### Daylight Saving configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to configure the RTC DayLight Saving. + +@endverbatim + * @{ + */ + +/** + * @brief Adds or substract one hour from the current time. + * @param RTC_DayLightSaveOperation: the value of hour adjustment. + * This parameter can be one of the following values: + * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) + * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) + * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit + * in CR register to store the operation. + * This parameter can be one of the following values: + * @arg RTC_StoreOperation_Reset: BCK Bit Reset + * @arg RTC_StoreOperation_Set: BCK Bit Set + * @retval None + */ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) +{ + /* Check the parameters */ + assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the bits to be configured */ + RTC->CR &= (uint32_t)~(RTC_CR_BCK); + + /* Configure the RTC_CR register */ + RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Returns the RTC Day Light Saving stored operation. + * @param None + * @retval RTC Day Light Saving stored operation. + * - RTC_StoreOperation_Reset + * - RTC_StoreOperation_Set + */ +uint32_t RTC_GetStoreOperation(void) +{ + return (RTC->CR & RTC_CR_BCK); +} + +/** + * @} + */ + +/** @defgroup RTC_Group6 Output pin Configuration function + * @brief Output pin Configuration function + * +@verbatim + =============================================================================== + ##### Output pin Configuration function ##### + =============================================================================== + + [..] This section provide functions allowing to configure the RTC Output source. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC output source (AFO_ALARM). + * @param RTC_Output: Specifies which signal will be routed to the RTC output. + * This parameter can be one of the following values: + * @arg RTC_Output_Disable: No output selected + * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output + * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output + * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output + * @param RTC_OutputPolarity: Specifies the polarity of the output signal. + * This parameter can be one of the following: + * @arg RTC_OutputPolarity_High: The output pin is high when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL) + * @arg RTC_OutputPolarity_Low: The output pin is low when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL) + * @retval None + */ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT(RTC_Output)); + assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the bits to be configured */ + RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); + + /* Configure the output selection and polarity */ + RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @} + */ + +/** @defgroup RTC_Group7 Digital Calibration configuration functions + * @brief Coarse Calibration configuration functions + * +@verbatim + =============================================================================== + ##### Digital Calibration configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Coarse calibration parameters. + * @param RTC_CalibSign: specifies the sign of the coarse calibration value. + * This parameter can be one of the following values: + * @arg RTC_CalibSign_Positive: The value sign is positive + * @arg RTC_CalibSign_Negative: The value sign is negative + * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). + * + * @note This Calibration value should be between 0 and 63 when using negative + * sign with a 2-ppm step. + * + * @note This Calibration value should be between 0 and 126 when using positive + * sign with a 4-ppm step. + * + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Coarse calibration are initialized + * - ERROR: RTC Coarse calibration are not initialized + */ +ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); + assert_param(IS_RTC_CALIB_VALUE(Value)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the coarse calibration value */ + RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Enables or disables the Coarse calibration process. + * @param NewState: new state of the Coarse calibration. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Coarse calibration are enabled/disabled + * - ERROR: RTC Coarse calibration are not enabled/disabled + */ +ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (NewState != DISABLE) + { + /* Enable the Coarse Calibration */ + RTC->CR |= (uint32_t)RTC_CR_DCE; + } + else + { + /* Disable the Coarse Calibration */ + RTC->CR &= (uint32_t)~RTC_CR_DCE; + } + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Enables or disables the RTC clock to be output through the relative pin. + * @param NewState: new state of the digital calibration Output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_CalibOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Enable the RTC clock output */ + RTC->CR |= (uint32_t)RTC_CR_COE; + } + else + { + /* Disable the RTC clock output */ + RTC->CR &= (uint32_t)~RTC_CR_COE; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param RTC_CalibOutput : Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. + * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz. + * @retval None +*/ +void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /*clear flags before configuration */ + RTC->CR &= (uint32_t)~(RTC_CR_COSEL); + + /* Configure the RTC_CR register */ + RTC->CR |= (uint32_t)RTC_CalibOutput; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Configures the Smooth Calibration Settings. + * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period. + * This parameter can be can be one of the following values: + * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration period is 32s. + * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration period is 16s. + * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion period is 8s. + * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses. + * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. + * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Calib registers are configured + * - ERROR: RTC Calib registers are not configured +*/ +ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue) +{ + ErrorStatus status = ERROR; + uint32_t recalpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* check if a calibration is pending*/ + if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) + { + /* wait until the Calibration is completed*/ + while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) + { + recalpfcount++; + } + } + + /* check if the calibration pending is completed or if there is no calibration operation at all*/ + if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) + { + /* Configure the Smooth calibration settings */ + RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); + + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + + +/** @defgroup RTC_Group8 TimeStamp configuration functions + * @brief TimeStamp configuration functions + * +@verbatim + =============================================================================== + ##### TimeStamp configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or Disables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge. + * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following: + * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the + * falling edge of the related pin. + * @param NewState: new state of the TimeStamp. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Get the new configuration */ + if (NewState != DISABLE) + { + tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); + } + else + { + tmpreg |= (uint32_t)(RTC_TimeStampEdge); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CR = (uint32_t)tmpreg; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Get the RTC TimeStamp value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contains the TimeStamp time values. + * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will + * contains the TimeStamp date values. + * @retval None + */ +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, + RTC_DateTypeDef* RTC_StampDateStruct) +{ + uint32_t tmptime = 0, tmpdate = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); + RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); + + /* Fill the Date structure fields with the read parameters */ + RTC_StampDateStruct->RTC_Year = 0; + RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); + RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the Time structure parameters to Binary format */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); + + /* Convert the Date structure parameters to Binary format */ + RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); + RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); + } +} + +/** + * @brief Get the RTC timestamp Sub seconds value. + * @param None + * @retval RTC current timestamp Sub seconds value. + */ +uint32_t RTC_GetTimeStampSubSecond(void) +{ + /* Get timestamp sub seconds values from the correspondent registers */ + return (uint32_t)(RTC->TSSSR); +} + +/** + * @} + */ + +/** @defgroup RTC_Group9 Tampers configuration functions + * @brief Tampers configuration functions + * +@verbatim + =============================================================================== + ##### Tampers configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the select Tamper pin edge. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be RTC_Tamper_1. + * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that + * stimulates tamper event. + * This parameter can be one of the following values: + * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. + * @retval None + */ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + + if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) + { + /* Configure the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); + } + else + { + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); + } +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be RTC_Tamper_1. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TAFCR |= (uint32_t)RTC_Tamper; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TAFCR &= (uint32_t)~RTC_Tamper; + } +} + +/** + * @brief Configures the Tampers Filter. + * @param RTC_TamperFilter: Specifies the tampers filter. + * This parameter can be one of the following values: + * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. + * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive + * samples at the active level + * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive + * samples at the active level + * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive + * samples at the active level + * @retval None + */ +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); + + /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperFilter; +} + +/** + * @brief Configures the Tampers Sampling Frequency. + * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. + * This parameter can be one of the following values: + * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 32768 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 16384 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 8192 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 4096 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 2048 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 1024 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 512 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 256 + * @retval None + */ +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); + + /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; +} + +/** + * @brief Configures the Tampers Pins input Precharge Duration. + * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input + * Precharge Duration. + * This parameter can be one of the following values: + * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged before sampling during 1 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged before sampling during 2 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged before sampling during 4 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged before sampling during 8 RTCCLK cycle + * @retval None + */ +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); + + /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; +} + +/** + * @brief Enables or Disables the TimeStamp on Tamper Detection Event. + * @note The timestamp is valid even the TSE bit in tamper control register + * is reset. + * @param NewState: new state of the timestamp on tamper event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Save timestamp on tamper detection event */ + RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; + } + else + { + /* Tamper detection does not cause a timestamp to be saved */ + RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; + } +} + +/** + * @brief Enables or Disables the Precharge of Tamper pin. + * @param NewState: new state of tamper pull up. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperPullUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable precharge of the selected Tamper pin */ + RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; + } + else + { + /* Disable precharge of the selected Tamper pin */ + RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group10 Backup Data Registers configuration functions + * @brief Backup Data Registers configuration functions + * +@verbatim + =============================================================================== + ##### Backup Data Registers configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @param RTC_BKP_DR: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @param Data: Data to be written in the specified RTC Backup data register. + * @retval None + */ +void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + + tmp = RTC_BASE + 0x50; + tmp += (RTC_BKP_DR * 4); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param RTC_BKP_DR: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @retval None + */ +uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + + tmp = RTC_BASE + 0x50; + tmp += (RTC_BKP_DR * 4); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions + * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config + * configuration functions + * +@verbatim + ================================================================================================== + ##### RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions ##### + ================================================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Selects the RTC Tamper Pin. + * @param RTC_TamperPin: specifies the RTC Tamper Pin. + * This parameter can be one of the following values: + * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin. + * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin. + * @retval None + */ +void RTC_TamperPinSelection(uint32_t RTC_TamperPin) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL); + RTC->TAFCR |= (uint32_t)(RTC_TamperPin); +} + +/** + * @brief Selects the RTC TimeStamp Pin. + * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin. + * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. + * @retval None + */ +void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin) +{ + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL); + RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); +} + +/** + * @brief Configures the RTC Output Pin mode. + * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in + * Open Drain mode. + * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in + * Push Pull mode. + * @retval None + */ +void RTC_OutputTypeConfig(uint32_t RTC_OutputType) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); + RTC->TAFCR |= (uint32_t)(RTC_OutputType); +} + +/** + * @} + */ + +/** @defgroup RTC_Group12 Shift control synchronisation functions + * @brief Shift control synchronisation functions + * +@verbatim + =============================================================================== + ##### Shift control synchronisation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register + * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar. + * This parameter can be one of the following values : + * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar. + * @arg RTC_ShiftAdd1S_Reset: No effect. + * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Shift registers are configured + * - ERROR: RTC Shift registers are not configured +*/ +ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) +{ + ErrorStatus status = ERROR; + uint32_t shpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Check if a Shift is pending*/ + if ((RTC->ISR & RTC_ISR_SHPF) != RESET) + { + /* Wait until the shift is completed*/ + while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) + { + shpfcount++; + } + } + + /* Check if the Shift pending is completed or if there is no Shift operation at all*/ + if ((RTC->ISR & RTC_ISR_SHPF) == RESET) + { + /* check if the reference clock detection is disabled */ + if((RTC->CR & RTC_CR_REFCKON) == RESET) + { + /* Configure the Shift settings */ + RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); + + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = ERROR; + } + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + +/** @defgroup RTC_Group13 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] All RTC interrupts are connected to the EXTI controller. + + (+) To enable the RTC Alarm interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 17 in interrupt mode and select + the rising edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the + NVIC_Init() function. + (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using + the RTC_SetAlarm() and RTC_AlarmCmd() functions. + + (+) To enable the RTC Wakeup interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 22 in interrupt mode and select the + rising edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the + NVIC_Init() function. + (++) Configure the RTC to generate the RTC wakeup timer event using the + RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() + functions. + + (+) To enable the RTC Tamper interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 21 in interrupt mode and select + the rising edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the + NVIC_Init() function. + (++) Configure the RTC to detect the RTC tamper event using the + RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. + + (+) To enable the RTC TimeStamp interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 21 in interrupt mode and select the + rising edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the + NVIC_Init() function. + (++) Configure the RTC to detect the RTC time stamp event using the + RTC_TimeStampCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt mask + * @arg RTC_IT_WUT: WakeUp Timer interrupt mask + * @arg RTC_IT_ALRB: Alarm B interrupt mask + * @arg RTC_IT_ALRA: Alarm A interrupt mask + * @arg RTC_IT_TAMP: Tamper event interrupt mask + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_CONFIG_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); + } + else + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_RECALPF: RECALPF event flag. + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_WUTF: WakeUp Timer flag + * @arg RTC_FLAG_ALRBF: Alarm B flag + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_INITF: Initialization mode flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_INITS: Registers Configured flag + * @arg RTC_FLAG_SHPF: Shift operation pending flag. + * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag + * @arg RTC_FLAG_ALRBWF: Alarm B Write flag + * @arg RTC_FLAG_ALRAWF: Alarm A write flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + /* Get all the flags */ + tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); + + /* Return the status of the flag */ + if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG: specifies the RTC flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_WUTF: WakeUp Timer flag + * @arg RTC_FLAG_ALRBF: Alarm B flag + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @retval None + */ +void RTC_ClearFlag(uint32_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the Flags in the RTC_ISR register */ + RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_IT: specifies the RTC interrupt source to check. + * This parameter can be one of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt + * @arg RTC_IT_WUT: WakeUp Timer interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_TAMP1: Tamper 1 event interrupt + * @retval The new state of RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint32_t RTC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + /* Get the TAMPER Interrupt enable bit and pending bit */ + tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); + + /* Get the Interrupt enable Status */ + enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15))); + + /* Get the Interrupt pending bit */ + tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); + + /* Get the status of the Interrupt */ + if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_IT: specifies the RTC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt + * @arg RTC_IT_WUT: WakeUp Timer interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_TAMP1: Tamper 1 event interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint32_t RTC_IT) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_IT(RTC_IT)); + + /* Get the RTC_ISR Interrupt pending bits mask */ + tmpreg = (uint32_t)(RTC_IT >> 4); + + /* Clear the interrupt pending bits in the RTC_ISR register */ + RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); +} + +/** + * @} + */ + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value: Byte to be converted. + * @retval Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + + while (Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value: BCD value to be converted. + * @retval Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint8_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c index f02739d00..d05b519ec 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c @@ -1,1079 +1,1079 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sai.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial Audio Interface (SAI): - * + Initialization and Configuration - * + Data transfers functions - * + DMA transfers management - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - - (#) Enable peripheral clock using the following functions - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SAI1, ENABLE) for SAI1 - - (#) For each SAI Block A/B enable SCK, SD, FS and MCLK GPIO clocks - using RCC_AHB1PeriphClockCmd() function. - - (#) Peripherals alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function. - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function - -@@- If an external clock source is used then the I2S CKIN pin should be - also configured in Alternate function Push-pull pull-up mode. - - (#) The SAI clock can be generated from different clock source : - PLL I2S, PLL SAI or external clock source. - (++) The PLL I2S is configured using the following functions RCC_PLLI2SConfig(), - RCC_PLLI2SCmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY) and - RCC_SAIPLLI2SClkDivConfig() or; - - (++) The PLL SAI is configured using the following functions RCC_PLLSAIConfig(), - RCC_PLLSAICmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLSAIRDY) and - RCC_SAIPLLSAIClkDivConfig()or; - - (++) External clock source is configured using the function - RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the - define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. - - (#) Each SAI Block A or B has its own clock generator to make these two blocks - completely independent. The Clock generator is configured using RCC_SAIBlockACLKConfig() and - RCC_SAIBlockBCLKConfig() functions. - - (#) Each SAI Block A or B can be configured separetely : - (++) Program the Master clock divider, Audio mode, Protocol, Data Length, Clock Strobing Edge, - Synchronous mode, Output drive and FIFO Thresold using SAI_Init() function. - In case of master mode, program the Master clock divider (MCKDIV) using - the following formula : - (+++) MCLK_x = SAI_CK_x / (MCKDIV * 2) with MCLK_x = 256 * FS - (+++) FS = SAI_CK_x / (MCKDIV * 2) * 256 - (+++) MCKDIV = SAI_CK_x / FS * 512 - (++) Program the Frame Length, Frame active Length, FS Definition, FS Polarity, - FS Offset using SAI_FrameInit() function. - (++) Program the Slot First Bit Offset, Slot Size, Slot Number, Slot Active - using SAI_SlotInit() function. - - (#) Enable the NVIC and the corresponding interrupt using the function - SAI_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using SAI_DMACmd() function - - (#) Enable the SAI using the SAI_Cmd() function. - - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. - - (#) The SAI has some specific functions which can be useful depending - on the audio protocol selected. - (++) Enable Mute mode when the audio block is a transmitter using SAI_MuteModeCmd() - function and configure the value transmitted during mute using SAI_MuteValueConfig(). - (++) Detect the Mute mode when audio block is a receiver using SAI_MuteFrameCounterConfig(). - (++) Enable the MONO mode without any data preprocessing in memory when the number - of slot is equal to 2 using SAI_MonoModeConfig() function. - (++) Enable data companding algorithm (U law and A law) using SAI_CompandingModeConfig(). - (++) Choose the behavior of the SD line in output when an inactive slot is sent - on the data line using SAI_TRIStateConfig() function. - [..] - (@) In master TX mode: enabling the audio block immediately generates the bit clock - for the external slaves even if there is no data in the FIFO, However FS signal - generation is conditioned by the presence of data in the FIFO. - - (@) In master RX mode: enabling the audio block immediately generates the bit clock - and FS signal for the external slaves. - - (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: - (+@) First bit Offset <= (SLOT size - Data size) - (+@) Data size <= SLOT size - (+@) Number of SLOT x SLOT size = Frame length - (+@) The number of slots should be even when bit FSDEF in the SAI_xFRCR is set. - - @endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_sai.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SAI - * @brief SAI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* *SAI registers Masks */ -#define CR1_CLEAR_MASK ((uint32_t)0xFF07C010) -#define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000) -#define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SAI_Private_Functions - * @{ - */ - -/** @defgroup SAI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This section provides a set of functions allowing to initialize the SAI Audio - Block Mode, Audio Protocol, Data size, Synchronization between audio block, - Master clock Divider, Fifo threshold, Frame configuration, slot configuration, - Tristate mode, Companding mode and Mute mode. - [..] - The SAI_Init(), SAI_FrameInit() and SAI_SlotInit() functions follows the SAI Block - configuration procedures for Master mode and Slave mode (details for these procedures - are available in reference manual(RM0090). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the SAIx peripheral registers to their default reset values. - * @param SAIx: To select the SAIx peripheral, where x can be the different instances - * - * @retval None - */ -void SAI_DeInit(SAI_TypeDef* SAIx) -{ - /* Check the parameters */ - assert_param(IS_SAI_PERIPH(SAIx)); - - /* Enable SAI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, ENABLE); - /* Release SAI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, DISABLE); -} - -/** - * @brief Initializes the SAI Block x peripheral according to the specified - * parameters in the SAI_InitStruct. - * - * @note SAI clock is generated from a specific output of the PLLSAI or a specific - * output of the PLLI2S or from an alternate function bypassing the PLL I2S. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure that - * contains the configuration information for the specified SAI Block peripheral. - * @retval None - */ -void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Check the SAI Block parameters */ - assert_param(IS_SAI_BLOCK_MODE(SAI_InitStruct->SAI_AudioMode)); - assert_param(IS_SAI_BLOCK_PROTOCOL(SAI_InitStruct->SAI_Protocol)); - assert_param(IS_SAI_BLOCK_DATASIZE(SAI_InitStruct->SAI_DataSize)); - assert_param(IS_SAI_BLOCK_FIRST_BIT(SAI_InitStruct->SAI_FirstBit)); - assert_param(IS_SAI_BLOCK_CLOCK_STROBING(SAI_InitStruct->SAI_ClockStrobing)); - assert_param(IS_SAI_BLOCK_SYNCHRO(SAI_InitStruct->SAI_Synchro)); - assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(SAI_InitStruct->SAI_OUTDRIV)); - assert_param(IS_SAI_BLOCK_NODIVIDER(SAI_InitStruct->SAI_NoDivider)); - assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(SAI_InitStruct->SAI_MasterDivider)); - assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(SAI_InitStruct->SAI_FIFOThreshold)); - - /* SAI Block_x CR1 Configuration */ - /* Get the SAI Block_x CR1 value */ - tmpreg = SAI_Block_x->CR1; - /* Clear MODE, PRTCFG, DS, LSBFIRST, CKSTR, SYNCEN, OUTDRIV, NODIV, and MCKDIV bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SAI_Block_x: Audio mode, Protocol, Data Size, first transmitted bit, Clock strobing - edge, Synchronization mode, Output drive, Master Divider and FIFO level */ - /* Set MODE bits according to SAI_AudioMode value */ - /* Set PRTCFG bits according to SAI_Protocol value */ - /* Set DS bits according to SAI_DataSize value */ - /* Set LSBFIRST bit according to SAI_FirstBit value */ - /* Set CKSTR bit according to SAI_ClockStrobing value */ - /* Set SYNCEN bit according to SAI_Synchro value */ - /* Set OUTDRIV bit according to SAI_OUTDRIV value */ - /* Set NODIV bit according to SAI_NoDivider value */ - /* Set MCKDIV bits according to SAI_MasterDivider value */ - tmpreg |= (uint32_t)(SAI_InitStruct->SAI_AudioMode | SAI_InitStruct->SAI_Protocol | - SAI_InitStruct->SAI_DataSize | SAI_InitStruct->SAI_FirstBit | - SAI_InitStruct->SAI_ClockStrobing | SAI_InitStruct->SAI_Synchro | - SAI_InitStruct->SAI_OUTDRIV | SAI_InitStruct->SAI_NoDivider | - (uint32_t)((SAI_InitStruct->SAI_MasterDivider) << 20)); - /* Write to SAI_Block_x CR1 */ - SAI_Block_x->CR1 = tmpreg; - - /* SAI Block_x CR2 Configuration */ - /* Get the SAIBlock_x CR2 value */ - tmpreg = SAI_Block_x->CR2; - /* Clear FTH bits */ - tmpreg &= ~(SAI_xCR2_FTH); - /* Configure the FIFO Level */ - /* Set FTH bits according to SAI_FIFOThreshold value */ - tmpreg |= (uint32_t)(SAI_InitStruct->SAI_FIFOThreshold); - /* Write to SAI_Block_x CR2 */ - SAI_Block_x->CR2 = tmpreg; -} - -/** - * @brief Initializes the SAI Block Audio frame according to the specified - * parameters in the SAI_FrameInitStruct. - * - * @note this function has no meaning if the AC'97 or SPDIF audio protocol - * are selected. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_FrameInitStruct: pointer to an SAI_FrameInitTypeDef structure that - * contains the configuration of audio frame for a specified SAI Block - * @retval None - */ -void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Check the SAI Block frame parameters */ - assert_param(IS_SAI_BLOCK_FRAME_LENGTH(SAI_FrameInitStruct->SAI_FrameLength)); - assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(SAI_FrameInitStruct->SAI_ActiveFrameLength)); - assert_param(IS_SAI_BLOCK_FS_DEFINITION(SAI_FrameInitStruct->SAI_FSDefinition)); - assert_param(IS_SAI_BLOCK_FS_POLARITY(SAI_FrameInitStruct->SAI_FSPolarity)); - assert_param(IS_SAI_BLOCK_FS_OFFSET(SAI_FrameInitStruct->SAI_FSOffset)); - - /* SAI Block_x FRCR Configuration */ - /* Get the SAI Block_x FRCR value */ - tmpreg = SAI_Block_x->FRCR; - /* Clear FRL, FSALL, FSDEF, FSPOL, FSOFF bits */ - tmpreg &= FRCR_CLEAR_MASK; - /* Configure SAI_Block_x Frame: Frame Length, Active Frame Length, Frame Synchronization - Definition, Frame Synchronization Polarity and Frame Synchronization Polarity */ - /* Set FRL bits according to SAI_FrameLength value */ - /* Set FSALL bits according to SAI_ActiveFrameLength value */ - /* Set FSDEF bit according to SAI_FSDefinition value */ - /* Set FSPOL bit according to SAI_FSPolarity value */ - /* Set FSOFF bit according to SAI_FSOffset value */ - tmpreg |= (uint32_t)((uint32_t)(SAI_FrameInitStruct->SAI_FrameLength - 1) | - SAI_FrameInitStruct->SAI_FSOffset | - SAI_FrameInitStruct->SAI_FSDefinition | - SAI_FrameInitStruct->SAI_FSPolarity | - (uint32_t)((SAI_FrameInitStruct->SAI_ActiveFrameLength - 1) << 8)); - - /* Write to SAI_Block_x FRCR */ - SAI_Block_x->FRCR = tmpreg; -} - -/** - * @brief Initializes the SAI Block audio Slot according to the specified - * parameters in the SAI_SlotInitStruct. - * - * @note this function has no meaning if the AC'97 or SPDIF audio protocol - * are selected. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_SlotInitStruct: pointer to an SAI_SlotInitTypeDef structure that - * contains the configuration of audio slot for a specified SAI Block - * @retval None - */ -void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Check the SAI Block Slot parameters */ - assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(SAI_SlotInitStruct->SAI_FirstBitOffset)); - assert_param(IS_SAI_BLOCK_SLOT_SIZE(SAI_SlotInitStruct->SAI_SlotSize)); - assert_param(IS_SAI_BLOCK_SLOT_NUMBER(SAI_SlotInitStruct->SAI_SlotNumber)); - assert_param(IS_SAI_SLOT_ACTIVE(SAI_SlotInitStruct->SAI_SlotActive)); - - /* SAI Block_x SLOTR Configuration */ - /* Get the SAI Block_x SLOTR value */ - tmpreg = SAI_Block_x->SLOTR; - /* Clear FBOFF, SLOTSZ, NBSLOT, SLOTEN bits */ - tmpreg &= SLOTR_CLEAR_MASK; - /* Configure SAI_Block_x Slot: First bit offset, Slot size, Number of Slot in - audio frame and slots activated in audio frame */ - /* Set FBOFF bits according to SAI_FirstBitOffset value */ - /* Set SLOTSZ bits according to SAI_SlotSize value */ - /* Set NBSLOT bits according to SAI_SlotNumber value */ - /* Set SLOTEN bits according to SAI_SlotActive value */ - tmpreg |= (uint32_t)(SAI_SlotInitStruct->SAI_FirstBitOffset | - SAI_SlotInitStruct->SAI_SlotSize | - SAI_SlotInitStruct->SAI_SlotActive | - (uint32_t)((SAI_SlotInitStruct->SAI_SlotNumber - 1) << 8)); - - /* Write to SAI_Block_x SLOTR */ - SAI_Block_x->SLOTR = tmpreg; -} - -/** - * @brief Fills each SAI_InitStruct member with its default value. - * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct) -{ - /* Reset SAI init structure parameters values */ - /* Initialize the SAI_AudioMode member */ - SAI_InitStruct->SAI_AudioMode = SAI_Mode_MasterTx; - /* Initialize the SAI_Protocol member */ - SAI_InitStruct->SAI_Protocol = SAI_Free_Protocol; - /* Initialize the SAI_DataSize member */ - SAI_InitStruct->SAI_DataSize = SAI_DataSize_8b; - /* Initialize the SAI_FirstBit member */ - SAI_InitStruct->SAI_FirstBit = SAI_FirstBit_MSB; - /* Initialize the SAI_ClockStrobing member */ - SAI_InitStruct->SAI_ClockStrobing = SAI_ClockStrobing_FallingEdge; - /* Initialize the SAI_Synchro member */ - SAI_InitStruct->SAI_Synchro = SAI_Asynchronous; - /* Initialize the SAI_OUTDRIV member */ - SAI_InitStruct->SAI_OUTDRIV = SAI_OutputDrive_Disabled; - /* Initialize the SAI_NoDivider member */ - SAI_InitStruct->SAI_NoDivider = SAI_MasterDivider_Enabled; - /* Initialize the SAI_MasterDivider member */ - SAI_InitStruct->SAI_MasterDivider = 0; - /* Initialize the SAI_FIFOThreshold member */ - SAI_InitStruct->SAI_FIFOThreshold = SAI_Threshold_FIFOEmpty; -} - -/** - * @brief Fills each SAI_FrameInitStruct member with its default value. - * @param SAI_FrameInitStruct: pointer to a SAI_FrameInitTypeDef structure - * which will be initialized. - * @retval None - */ -void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct) -{ - /* Reset SAI Frame init structure parameters values */ - /* Initialize the SAI_FrameLength member */ - SAI_FrameInitStruct->SAI_FrameLength = 8; - /* Initialize the SAI_ActiveFrameLength member */ - SAI_FrameInitStruct->SAI_ActiveFrameLength = 1; - /* Initialize the SAI_FSDefinition member */ - SAI_FrameInitStruct->SAI_FSDefinition = SAI_FS_StartFrame; - /* Initialize the SAI_FSPolarity member */ - SAI_FrameInitStruct->SAI_FSPolarity = SAI_FS_ActiveLow; - /* Initialize the SAI_FSOffset member */ - SAI_FrameInitStruct->SAI_FSOffset = SAI_FS_FirstBit; -} - -/** - * @brief Fills each SAI_SlotInitStruct member with its default value. - * @param SAI_SlotInitStruct: pointer to a SAI_SlotInitTypeDef structure - * which will be initialized. - * @retval None - */ -void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct) -{ - /* Reset SAI Slot init structure parameters values */ - /* Initialize the SAI_FirstBitOffset member */ - SAI_SlotInitStruct->SAI_FirstBitOffset = 0; - /* Initialize the SAI_SlotSize member */ - SAI_SlotInitStruct->SAI_SlotSize = SAI_SlotSize_DataSize; - /* Initialize the SAI_SlotNumber member */ - SAI_SlotInitStruct->SAI_SlotNumber = 1; - /* Initialize the SAI_SlotActive member */ - SAI_SlotInitStruct->SAI_SlotActive = SAI_Slot_NotActive; - -} - -/** - * @brief Enables or disables the specified SAI Block peripheral. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param NewState: new state of the SAI_Block_x peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SAI peripheral */ - SAI_Block_x->CR1 |= SAI_xCR1_SAIEN; - } - else - { - /* Disable the selected SAI peripheral */ - SAI_Block_x->CR1 &= ~(SAI_xCR1_SAIEN); - } -} - -/** - * @brief Configures the mono mode for the selected SAI block. - * - * @note This function has a meaning only when the number of slot is equal to 2. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_MonoMode: specifies the SAI block mono mode. - * This parameter can be one of the following values: - * @arg SAI_MonoMode : Set mono audio mode - * @arg SAI_StreoMode : Set streo audio mode - * @retval None - */ -void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_MONO_STREO_MODE(SAI_MonoMode)); - /* Clear MONO bit */ - SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO); - /* Set new Mono Mode value */ - SAI_Block_x->CR1 |= SAI_MonoMode; -} - -/** - * @brief Configures the TRIState managment on data line for the selected SAI block. - * - * @note This function has a meaning only when the SAI block is configured in transmitter - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_TRIState: specifies the SAI block TRIState management. - * This parameter can be one of the following values: - * @arg SAI_Output_NotReleased : SD output line is still drived by the SAI. - * @arg SAI_Output_Released : SD output line is released (HI-Z) - * @retval None - */ -void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(SAI_TRIState)); - /* Clear MONO bit */ - SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO); - /* Set new Mono Mode value */ - SAI_Block_x->CR1 |= SAI_MonoMode; - -} - -/** - * @brief Configures the companding mode for the selected SAI block. - * - * @note The data expansion or data compression are determined by the state of - * SAI block selected (transmitter or receiver). - - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_CompandingMode: specifies the SAI block companding mode. - * This parameter can be one of the following values: - * @arg SAI_NoCompanding : no companding algorithm set - * @arg SAI_ULaw_1CPL_Companding : Set U law (algorithm 1's complement representation) - * @arg SAI_ALaw_1CPL_Companding : Set A law (algorithm 1's complement repesentation) - * @arg SAI_ULaw_2CPL_Companding : Set U law (algorithm 2's complement representation) - * @arg SAI_ALaw_2CPL_Companding : Set A law (algorithm 2's complement repesentation) - * @retval None - */ -void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_COMPANDING_MODE(SAI_CompandingMode)); - /* Clear Companding Mode bits */ - SAI_Block_x->CR2 &= ~(SAI_xCR2_COMP); - /* Set new Companding Mode value */ - SAI_Block_x->CR2 |= SAI_CompandingMode; -} - -/** - * @brief Enables or disables the Mute mode for the selected SAI block. - * - * @note This function has a meaning only when the audio block is transmitter - * @note Mute mode is applied for an entire frame for all the valid slot - * It becomes active at the end of an audio frame when set somewhere in a frame. - * Mute mode exit occurs at the end of the frame in which the bit MUTE has been set. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param NewState: new state of the SAIx block. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SAI block mute mode */ - SAI_Block_x->CR2 |= SAI_xCR2_MUTE; - } - else - { - /* Disable the selected SAI SS output */ - SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTE); - } -} - -/** - * @brief Configure the mute value for the selected SAI block. - * - * @note This function has a meaning only when the audio block is transmitter - * @note the configuration last value sent during mute mode has only a meaning - * when the number of slot is lower or equal to 2 and if the MUTE bit is set. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_MuteValue: specifies the SAI block mute value. - * This parameter can be one of the following values: - * @arg SAI_ZeroValue : bit value 0 is sent during Mute Mode - * @arg SAI_LastSentValue : Last value is sent during Mute Mode - * @retval None - */ -void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_MUTE_VALUE(SAI_MuteValue)); - - /* Clear Mute value bits */ - SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTEVAL); - /* Set new Mute value */ - SAI_Block_x->CR2 |= SAI_MuteValue; -} - -/** - * @brief Enables or disables the Mute mode for the selected SAI block. - * - * @note This function has a meaning only when the audio block is Receiver - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_MuteCounter: specifies the SAI block mute value. - * This parameter can be a number between 0 and 63. - - * @retval None - */ -void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_MUTE_COUNTER(SAI_MuteCounter)); - - /* Clear Mute value bits */ - SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTECNT); - /* Set new Mute value */ - SAI_Block_x->CR2 |= (SAI_MuteCounter << 7); -} - -/** - * @brief Reinitialize the FIFO pointer - * - * @note The FIFO pointers can be reinitialized at anytime The data present - * into the FIFO, if it is not empty, will be lost. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param NewState: new state of the selected SAI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* FIFO flush */ - SAI_Block_x->CR2 |= SAI_xCR2_FFLUSH; -} - -/** - * @} - */ - -/** @defgroup SAI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - [..] - This section provides a set of functions allowing to manage the SAI data transfers. - [..] - In reception, data are received and then stored into an internal FIFO while - In transmission, data are first stored into an internal FIFO before being - transmitted. - [..] - The read access of the SAI_xDR register can be done using the SAI_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SAI_DR - can be done using SAI_SendData() function and stores the written data into - Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the most recent received data by the SAI block x peripheral. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * - * @retval The value of the received data. - */ -uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Return the data in the DR register */ - return SAI_Block_x->DR; -} - -/** - * @brief Transmits a Data through the SAI block x peripheral. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * - * @param Data: Data to be transmitted. - * @retval None - */ -void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Write in the DR register the data to be sent */ - SAI_Block_x->DR = Data; -} - -/** - * @} - */ - -/** @defgroup SAI_Group3 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SAI Block x DMA interface. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param NewState: new state of the selected SAI block DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SAI block mute mode */ - SAI_Block_x->CR1 |= SAI_xCR1_DMAEN; - } - else - { - /* Disable the selected SAI SS output */ - SAI_Block_x->CR1 &= ~(SAI_xCR1_DMAEN); - } -} - -/** - * @} - */ - -/** @defgroup SAI_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] - This section provides a set of functions allowing to configure the SAI Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - *** Polling Mode *** - ==================== - [..] - In Polling Mode, the SAI communication can be managed by 7 flags: - (#) SAI_FLAG_FREQ : to indicate if there is a FIFO Request to write or to read. - (#) SAI_FLAG_MUTEDET : to indicate if a MUTE frame detected - (#) SAI_FLAG_OVRUDR : to indicate if an Overrun or Underrun error occur - (#) SAI_FLAG_AFSDET : to indicate if there is the detection of a audio frame - synchronisation (FS) earlier than expected - (#) SAI_FLAG_LFSDET : to indicate if there is the detection of a audio frame - synchronisation (FS) later than expected - (#) SAI_FLAG_CNRDY : to indicate if the codec is not ready to communicate during - the reception of the TAG 0 (slot0) of the AC97 audio frame - (#) SAI_FLAG_WCKCFG: to indicate if wrong clock configuration in master mode - error occurs. - [..] - In this Mode it is advised to use the following functions: - (+) FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); - (+) void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); - - *** Interrupt Mode *** - ====================== - [..] - In Interrupt Mode, the SAI communication can be managed by 7 interrupt sources - and 7 pending bits: - (+) Pending Bits: - (##) SAI_IT_FREQ : to indicate if there is a FIFO Request to write or to read. - (##) SAI_IT_MUTEDET : to indicate if a MUTE frame detected. - (##) SAI_IT_OVRUDR : to indicate if an Overrun or Underrun error occur. - (##) SAI_IT_AFSDET : to indicate if there is the detection of a audio frame - synchronisation (FS) earlier than expected. - (##) SAI_IT_LFSDET : to indicate if there is the detection of a audio frame - synchronisation (FS) later than expected. - (##) SAI_IT_CNRDY : to indicate if the codec is not ready to communicate during - the reception of the TAG 0 (slot0) of the AC97 audio frame. - (##) SAI_IT_WCKCFG: to indicate if wrong clock configuration in master mode - error occurs. - - (+) Interrupt Source: - (##) SAI_IT_FREQ : specifies the interrupt source for FIFO Request. - (##) SAI_IT_MUTEDET : specifies the interrupt source for MUTE frame detected. - (##) SAI_IT_OVRUDR : specifies the interrupt source for overrun or underrun error. - (##) SAI_IT_AFSDET : specifies the interrupt source for anticipated frame synchronization - detection interrupt. - (##) SAI_IT_LFSDET : specifies the interrupt source for late frame synchronization - detection interrupt. - (##) SAI_IT_CNRDY : specifies the interrupt source for codec not ready interrupt - (##) SAI_IT_WCKCFG: specifies the interrupt source for wrong clock configuration - interrupt. - [..] - In this Mode it is advised to use the following functions: - (+) void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState); - (+) ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); - (+) void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); - - *** DMA Mode *** - ================ - [..] - In DMA Mode, each SAI audio block has an independent DMA interface in order to - read or to write into the SAI_xDR register (to hit the internal FIFO). - There is one DMA channel by audio block following basic DMA request/acknowledge - protocol. - [..] - In this Mode it is advised to use the following function: - (+) void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); - [..] - This section provides also functions allowing to - (+) Check the SAI Block enable status - (+)Check the FIFO status - - *** SAI Block Enable status *** - =============================== - [..] - After disabling a SAI Block, it is recommended to check (or wait until) the SAI Block - is effectively disabled. If a Block is disabled while an audio frame transfer is ongoing - the current frame will be transferred and the block will be effectively disabled only at - the end of audio frame. - To monitor this state it is possible to use the following function: - (+) FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x); - - *** SAI Block FIFO status *** - ============================= - [..] - It is possible to monitor the FIFO status when a transfer is ongoing using the following - function: - (+) uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SAI Block interrupts. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SAI_IT_FREQ: FIFO Request interrupt mask - * @arg SAI_IT_MUTEDET: MUTE detection interrupt mask - * @arg SAI_IT_OVRUDR: overrun/underrun interrupt mask - * @arg SAI_IT_AFSDET: anticipated frame synchronization detection - * interrupt mask - * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt - * mask - * @arg SAI_IT_CNRDY: codec not ready interrupt mask - * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt mask - * @param NewState: new state of the specified SAI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected SAI Block interrupt */ - SAI_Block_x->IMR |= SAI_IT; - } - else - { - /* Disable the selected SAI Block interrupt */ - SAI_Block_x->IMR &= ~(SAI_IT); - } -} - -/** - * @brief Checks whether the specified SAI block x flag is set or not. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_FLAG: specifies the SAI block flag to check. - * This parameter can be one of the following values: - * @arg SAI_FLAG_FREQ: FIFO Request flag. - * @arg SAI_FLAG_MUTEDET: MUTE detection flag. - * @arg SAI_FLAG_OVRUDR: overrun/underrun flag. - * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag. - * @arg SAI_FLAG_CNRDY: codec not ready flag. - * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag. - * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag. - * @retval The new state of SAI_FLAG (SET or RESET). - */ -FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_GET_FLAG(SAI_FLAG)); - - /* Check the status of the specified SAI flag */ - if ((SAI_Block_x->SR & SAI_FLAG) != (uint32_t)RESET) - { - /* SAI_FLAG is set */ - bitstatus = SET; - } - else - { - /* SAI_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SAI_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the specified SAI Block x flag. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_FLAG: specifies the SAI block flag to check. - * This parameter can be one of the following values: - * @arg SAI_FLAG_MUTEDET: MUTE detection flag. - * @arg SAI_FLAG_OVRUDR: overrun/underrun flag. - * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag. - * @arg SAI_FLAG_CNRDY: codec not ready flag. - * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag. - * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag. - * - * @note FREQ (FIFO Request) flag is cleared : - * - When the audio block is transmitter and the FIFO is full or the FIFO - * has one data (one buffer mode) depending the bit FTH in the - * SAI_xCR2 register. - * - When the audio block is receiver and the FIFO is not empty - * - * @retval None - */ -void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_CLEAR_FLAG(SAI_FLAG)); - - /* Clear the selected SAI Block flag */ - SAI_Block_x->CLRFR |= SAI_FLAG; -} - -/** - * @brief Checks whether the specified SAI Block x interrupt has occurred or not. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SAI_IT_FREQ: FIFO Request interrupt - * @arg SAI_IT_MUTEDET: MUTE detection interrupt - * @arg SAI_IT_OVRUDR: overrun/underrun interrupt - * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt - * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt - * @arg SAI_IT_CNRDY: codec not ready interrupt - * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt - * - * @retval The new state of SAI_IT (SET or RESET). - */ -ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); - - /* Get the SAI_IT enable bit status */ - enablestatus = (SAI_Block_x->IMR & SAI_IT) ; - - /* Check the status of the specified SAI interrupt */ - if (((SAI_Block_x->SR & SAI_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* SAI_IT is set */ - bitstatus = SET; - } - else - { - /* SAI_IT is reset */ - bitstatus = RESET; - } - /* Return the SAI_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SAI Block x interrupt pending bit. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_IT: specifies the SAI Block interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg SAI_IT_MUTEDET: MUTE detection interrupt. - * @arg SAI_IT_OVRUDR: overrun/underrun interrupt. - * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt. - * @arg SAI_IT_CNRDY: codec not ready interrupt. - * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt. - * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt. - * - * @note FREQ (FIFO Request) flag is cleared : - * - When the audio block is transmitter and the FIFO is full or the FIFO - * has one data (one buffer mode) depending the bit FTH in the - * SAI_xCR2 register. - * - When the audio block is receiver and the FIFO is not empty - * - * @retval None - */ -void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); - - /* Clear the selected SAI Block x interrupt pending bit */ - SAI_Block_x->CLRFR |= SAI_IT; -} - -/** - * @brief Returns the status of EN bit for the specified SAI Block x. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * - * @note After disabling a SAI Block, it is recommended to check (or wait until) - * the SAI Block is effectively disabled. If a Block is disabled while - * an audio frame transfer is ongoing, the current frame will be - * transferred and the block will be effectively disabled only at - * the end of audio frame. - * - * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). - */ -FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x) -{ - FunctionalState state = DISABLE; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - if ((SAI_Block_x->CR1 & (uint32_t)SAI_xCR1_SAIEN) != 0) - { - /* The selected SAI Block x EN bit is set (audio frame transfer is ongoing) */ - state = ENABLE; - } - else - { - /* The selected SAI Block x EN bit is cleared (SAI Block is disabled and - all transfers are complete) */ - state = DISABLE; - } - return state; -} - -/** - * @brief Returns the current SAI Block x FIFO filled level. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * - * @retval The FIFO filling state. - * - SAI_FIFOStatus_Empty: when FIFO is empty - * - SAI_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full - * and not empty. - * - SAI_FIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - SAI_FIFOStatus_HalfFull: if more than 1 half-full. - * - SAI_FIFOStatus_3QuartersFull: if more than 3 quarters-full. - * - SAI_FIFOStatus_Full: when FIFO is full - */ -uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Get the FIFO level bits */ - tmpreg = (uint32_t)((SAI_Block_x->SR & SAI_xSR_FLVL)); - - return tmpreg; -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_sai.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Serial Audio Interface (SAI): + * + Initialization and Configuration + * + Data transfers functions + * + DMA transfers management + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + + (#) Enable peripheral clock using the following functions + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SAI1, ENABLE) for SAI1 + + (#) For each SAI Block A/B enable SCK, SD, FS and MCLK GPIO clocks + using RCC_AHB1PeriphClockCmd() function. + + (#) Peripherals alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function. + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function + -@@- If an external clock source is used then the I2S CKIN pin should be + also configured in Alternate function Push-pull pull-up mode. + + (#) The SAI clock can be generated from different clock source : + PLL I2S, PLL SAI or external clock source. + (++) The PLL I2S is configured using the following functions RCC_PLLI2SConfig(), + RCC_PLLI2SCmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY) and + RCC_SAIPLLI2SClkDivConfig() or; + + (++) The PLL SAI is configured using the following functions RCC_PLLSAIConfig(), + RCC_PLLSAICmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLSAIRDY) and + RCC_SAIPLLSAIClkDivConfig()or; + + (++) External clock source is configured using the function + RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the + define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. + + (#) Each SAI Block A or B has its own clock generator to make these two blocks + completely independent. The Clock generator is configured using RCC_SAIBlockACLKConfig() and + RCC_SAIBlockBCLKConfig() functions. + + (#) Each SAI Block A or B can be configured separetely : + (++) Program the Master clock divider, Audio mode, Protocol, Data Length, Clock Strobing Edge, + Synchronous mode, Output drive and FIFO Thresold using SAI_Init() function. + In case of master mode, program the Master clock divider (MCKDIV) using + the following formula : + (+++) MCLK_x = SAI_CK_x / (MCKDIV * 2) with MCLK_x = 256 * FS + (+++) FS = SAI_CK_x / (MCKDIV * 2) * 256 + (+++) MCKDIV = SAI_CK_x / FS * 512 + (++) Program the Frame Length, Frame active Length, FS Definition, FS Polarity, + FS Offset using SAI_FrameInit() function. + (++) Program the Slot First Bit Offset, Slot Size, Slot Number, Slot Active + using SAI_SlotInit() function. + + (#) Enable the NVIC and the corresponding interrupt using the function + SAI_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function + (++) Active the needed channel Request using SAI_DMACmd() function + + (#) Enable the SAI using the SAI_Cmd() function. + + (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. + + (#) The SAI has some specific functions which can be useful depending + on the audio protocol selected. + (++) Enable Mute mode when the audio block is a transmitter using SAI_MuteModeCmd() + function and configure the value transmitted during mute using SAI_MuteValueConfig(). + (++) Detect the Mute mode when audio block is a receiver using SAI_MuteFrameCounterConfig(). + (++) Enable the MONO mode without any data preprocessing in memory when the number + of slot is equal to 2 using SAI_MonoModeConfig() function. + (++) Enable data companding algorithm (U law and A law) using SAI_CompandingModeConfig(). + (++) Choose the behavior of the SD line in output when an inactive slot is sent + on the data line using SAI_TRIStateConfig() function. + [..] + (@) In master TX mode: enabling the audio block immediately generates the bit clock + for the external slaves even if there is no data in the FIFO, However FS signal + generation is conditioned by the presence of data in the FIFO. + + (@) In master RX mode: enabling the audio block immediately generates the bit clock + and FS signal for the external slaves. + + (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: + (+@) First bit Offset <= (SLOT size - Data size) + (+@) Data size <= SLOT size + (+@) Number of SLOT x SLOT size = Frame length + (+@) The number of slots should be even when bit FSDEF in the SAI_xFRCR is set. + + @endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_sai.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SAI + * @brief SAI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* *SAI registers Masks */ +#define CR1_CLEAR_MASK ((uint32_t)0xFF07C010) +#define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000) +#define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SAI_Private_Functions + * @{ + */ + +/** @defgroup SAI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This section provides a set of functions allowing to initialize the SAI Audio + Block Mode, Audio Protocol, Data size, Synchronization between audio block, + Master clock Divider, Fifo threshold, Frame configuration, slot configuration, + Tristate mode, Companding mode and Mute mode. + [..] + The SAI_Init(), SAI_FrameInit() and SAI_SlotInit() functions follows the SAI Block + configuration procedures for Master mode and Slave mode (details for these procedures + are available in reference manual(RM0090). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the SAIx peripheral registers to their default reset values. + * @param SAIx: To select the SAIx peripheral, where x can be the different instances + * + * @retval None + */ +void SAI_DeInit(SAI_TypeDef* SAIx) +{ + /* Check the parameters */ + assert_param(IS_SAI_PERIPH(SAIx)); + + /* Enable SAI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, ENABLE); + /* Release SAI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, DISABLE); +} + +/** + * @brief Initializes the SAI Block x peripheral according to the specified + * parameters in the SAI_InitStruct. + * + * @note SAI clock is generated from a specific output of the PLLSAI or a specific + * output of the PLLI2S or from an alternate function bypassing the PLL I2S. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure that + * contains the configuration information for the specified SAI Block peripheral. + * @retval None + */ +void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Check the SAI Block parameters */ + assert_param(IS_SAI_BLOCK_MODE(SAI_InitStruct->SAI_AudioMode)); + assert_param(IS_SAI_BLOCK_PROTOCOL(SAI_InitStruct->SAI_Protocol)); + assert_param(IS_SAI_BLOCK_DATASIZE(SAI_InitStruct->SAI_DataSize)); + assert_param(IS_SAI_BLOCK_FIRST_BIT(SAI_InitStruct->SAI_FirstBit)); + assert_param(IS_SAI_BLOCK_CLOCK_STROBING(SAI_InitStruct->SAI_ClockStrobing)); + assert_param(IS_SAI_BLOCK_SYNCHRO(SAI_InitStruct->SAI_Synchro)); + assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(SAI_InitStruct->SAI_OUTDRIV)); + assert_param(IS_SAI_BLOCK_NODIVIDER(SAI_InitStruct->SAI_NoDivider)); + assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(SAI_InitStruct->SAI_MasterDivider)); + assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(SAI_InitStruct->SAI_FIFOThreshold)); + + /* SAI Block_x CR1 Configuration */ + /* Get the SAI Block_x CR1 value */ + tmpreg = SAI_Block_x->CR1; + /* Clear MODE, PRTCFG, DS, LSBFIRST, CKSTR, SYNCEN, OUTDRIV, NODIV, and MCKDIV bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure SAI_Block_x: Audio mode, Protocol, Data Size, first transmitted bit, Clock strobing + edge, Synchronization mode, Output drive, Master Divider and FIFO level */ + /* Set MODE bits according to SAI_AudioMode value */ + /* Set PRTCFG bits according to SAI_Protocol value */ + /* Set DS bits according to SAI_DataSize value */ + /* Set LSBFIRST bit according to SAI_FirstBit value */ + /* Set CKSTR bit according to SAI_ClockStrobing value */ + /* Set SYNCEN bit according to SAI_Synchro value */ + /* Set OUTDRIV bit according to SAI_OUTDRIV value */ + /* Set NODIV bit according to SAI_NoDivider value */ + /* Set MCKDIV bits according to SAI_MasterDivider value */ + tmpreg |= (uint32_t)(SAI_InitStruct->SAI_AudioMode | SAI_InitStruct->SAI_Protocol | + SAI_InitStruct->SAI_DataSize | SAI_InitStruct->SAI_FirstBit | + SAI_InitStruct->SAI_ClockStrobing | SAI_InitStruct->SAI_Synchro | + SAI_InitStruct->SAI_OUTDRIV | SAI_InitStruct->SAI_NoDivider | + (uint32_t)((SAI_InitStruct->SAI_MasterDivider) << 20)); + /* Write to SAI_Block_x CR1 */ + SAI_Block_x->CR1 = tmpreg; + + /* SAI Block_x CR2 Configuration */ + /* Get the SAIBlock_x CR2 value */ + tmpreg = SAI_Block_x->CR2; + /* Clear FTH bits */ + tmpreg &= ~(SAI_xCR2_FTH); + /* Configure the FIFO Level */ + /* Set FTH bits according to SAI_FIFOThreshold value */ + tmpreg |= (uint32_t)(SAI_InitStruct->SAI_FIFOThreshold); + /* Write to SAI_Block_x CR2 */ + SAI_Block_x->CR2 = tmpreg; +} + +/** + * @brief Initializes the SAI Block Audio frame according to the specified + * parameters in the SAI_FrameInitStruct. + * + * @note this function has no meaning if the AC'97 or SPDIF audio protocol + * are selected. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_FrameInitStruct: pointer to an SAI_FrameInitTypeDef structure that + * contains the configuration of audio frame for a specified SAI Block + * @retval None + */ +void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Check the SAI Block frame parameters */ + assert_param(IS_SAI_BLOCK_FRAME_LENGTH(SAI_FrameInitStruct->SAI_FrameLength)); + assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(SAI_FrameInitStruct->SAI_ActiveFrameLength)); + assert_param(IS_SAI_BLOCK_FS_DEFINITION(SAI_FrameInitStruct->SAI_FSDefinition)); + assert_param(IS_SAI_BLOCK_FS_POLARITY(SAI_FrameInitStruct->SAI_FSPolarity)); + assert_param(IS_SAI_BLOCK_FS_OFFSET(SAI_FrameInitStruct->SAI_FSOffset)); + + /* SAI Block_x FRCR Configuration */ + /* Get the SAI Block_x FRCR value */ + tmpreg = SAI_Block_x->FRCR; + /* Clear FRL, FSALL, FSDEF, FSPOL, FSOFF bits */ + tmpreg &= FRCR_CLEAR_MASK; + /* Configure SAI_Block_x Frame: Frame Length, Active Frame Length, Frame Synchronization + Definition, Frame Synchronization Polarity and Frame Synchronization Polarity */ + /* Set FRL bits according to SAI_FrameLength value */ + /* Set FSALL bits according to SAI_ActiveFrameLength value */ + /* Set FSDEF bit according to SAI_FSDefinition value */ + /* Set FSPOL bit according to SAI_FSPolarity value */ + /* Set FSOFF bit according to SAI_FSOffset value */ + tmpreg |= (uint32_t)((uint32_t)(SAI_FrameInitStruct->SAI_FrameLength - 1) | + SAI_FrameInitStruct->SAI_FSOffset | + SAI_FrameInitStruct->SAI_FSDefinition | + SAI_FrameInitStruct->SAI_FSPolarity | + (uint32_t)((SAI_FrameInitStruct->SAI_ActiveFrameLength - 1) << 8)); + + /* Write to SAI_Block_x FRCR */ + SAI_Block_x->FRCR = tmpreg; +} + +/** + * @brief Initializes the SAI Block audio Slot according to the specified + * parameters in the SAI_SlotInitStruct. + * + * @note this function has no meaning if the AC'97 or SPDIF audio protocol + * are selected. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_SlotInitStruct: pointer to an SAI_SlotInitTypeDef structure that + * contains the configuration of audio slot for a specified SAI Block + * @retval None + */ +void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Check the SAI Block Slot parameters */ + assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(SAI_SlotInitStruct->SAI_FirstBitOffset)); + assert_param(IS_SAI_BLOCK_SLOT_SIZE(SAI_SlotInitStruct->SAI_SlotSize)); + assert_param(IS_SAI_BLOCK_SLOT_NUMBER(SAI_SlotInitStruct->SAI_SlotNumber)); + assert_param(IS_SAI_SLOT_ACTIVE(SAI_SlotInitStruct->SAI_SlotActive)); + + /* SAI Block_x SLOTR Configuration */ + /* Get the SAI Block_x SLOTR value */ + tmpreg = SAI_Block_x->SLOTR; + /* Clear FBOFF, SLOTSZ, NBSLOT, SLOTEN bits */ + tmpreg &= SLOTR_CLEAR_MASK; + /* Configure SAI_Block_x Slot: First bit offset, Slot size, Number of Slot in + audio frame and slots activated in audio frame */ + /* Set FBOFF bits according to SAI_FirstBitOffset value */ + /* Set SLOTSZ bits according to SAI_SlotSize value */ + /* Set NBSLOT bits according to SAI_SlotNumber value */ + /* Set SLOTEN bits according to SAI_SlotActive value */ + tmpreg |= (uint32_t)(SAI_SlotInitStruct->SAI_FirstBitOffset | + SAI_SlotInitStruct->SAI_SlotSize | + SAI_SlotInitStruct->SAI_SlotActive | + (uint32_t)((SAI_SlotInitStruct->SAI_SlotNumber - 1) << 8)); + + /* Write to SAI_Block_x SLOTR */ + SAI_Block_x->SLOTR = tmpreg; +} + +/** + * @brief Fills each SAI_InitStruct member with its default value. + * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct) +{ + /* Reset SAI init structure parameters values */ + /* Initialize the SAI_AudioMode member */ + SAI_InitStruct->SAI_AudioMode = SAI_Mode_MasterTx; + /* Initialize the SAI_Protocol member */ + SAI_InitStruct->SAI_Protocol = SAI_Free_Protocol; + /* Initialize the SAI_DataSize member */ + SAI_InitStruct->SAI_DataSize = SAI_DataSize_8b; + /* Initialize the SAI_FirstBit member */ + SAI_InitStruct->SAI_FirstBit = SAI_FirstBit_MSB; + /* Initialize the SAI_ClockStrobing member */ + SAI_InitStruct->SAI_ClockStrobing = SAI_ClockStrobing_FallingEdge; + /* Initialize the SAI_Synchro member */ + SAI_InitStruct->SAI_Synchro = SAI_Asynchronous; + /* Initialize the SAI_OUTDRIV member */ + SAI_InitStruct->SAI_OUTDRIV = SAI_OutputDrive_Disabled; + /* Initialize the SAI_NoDivider member */ + SAI_InitStruct->SAI_NoDivider = SAI_MasterDivider_Enabled; + /* Initialize the SAI_MasterDivider member */ + SAI_InitStruct->SAI_MasterDivider = 0; + /* Initialize the SAI_FIFOThreshold member */ + SAI_InitStruct->SAI_FIFOThreshold = SAI_Threshold_FIFOEmpty; +} + +/** + * @brief Fills each SAI_FrameInitStruct member with its default value. + * @param SAI_FrameInitStruct: pointer to a SAI_FrameInitTypeDef structure + * which will be initialized. + * @retval None + */ +void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct) +{ + /* Reset SAI Frame init structure parameters values */ + /* Initialize the SAI_FrameLength member */ + SAI_FrameInitStruct->SAI_FrameLength = 8; + /* Initialize the SAI_ActiveFrameLength member */ + SAI_FrameInitStruct->SAI_ActiveFrameLength = 1; + /* Initialize the SAI_FSDefinition member */ + SAI_FrameInitStruct->SAI_FSDefinition = SAI_FS_StartFrame; + /* Initialize the SAI_FSPolarity member */ + SAI_FrameInitStruct->SAI_FSPolarity = SAI_FS_ActiveLow; + /* Initialize the SAI_FSOffset member */ + SAI_FrameInitStruct->SAI_FSOffset = SAI_FS_FirstBit; +} + +/** + * @brief Fills each SAI_SlotInitStruct member with its default value. + * @param SAI_SlotInitStruct: pointer to a SAI_SlotInitTypeDef structure + * which will be initialized. + * @retval None + */ +void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct) +{ + /* Reset SAI Slot init structure parameters values */ + /* Initialize the SAI_FirstBitOffset member */ + SAI_SlotInitStruct->SAI_FirstBitOffset = 0; + /* Initialize the SAI_SlotSize member */ + SAI_SlotInitStruct->SAI_SlotSize = SAI_SlotSize_DataSize; + /* Initialize the SAI_SlotNumber member */ + SAI_SlotInitStruct->SAI_SlotNumber = 1; + /* Initialize the SAI_SlotActive member */ + SAI_SlotInitStruct->SAI_SlotActive = SAI_Slot_NotActive; + +} + +/** + * @brief Enables or disables the specified SAI Block peripheral. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param NewState: new state of the SAI_Block_x peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SAI peripheral */ + SAI_Block_x->CR1 |= SAI_xCR1_SAIEN; + } + else + { + /* Disable the selected SAI peripheral */ + SAI_Block_x->CR1 &= ~(SAI_xCR1_SAIEN); + } +} + +/** + * @brief Configures the mono mode for the selected SAI block. + * + * @note This function has a meaning only when the number of slot is equal to 2. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_MonoMode: specifies the SAI block mono mode. + * This parameter can be one of the following values: + * @arg SAI_MonoMode : Set mono audio mode + * @arg SAI_StreoMode : Set streo audio mode + * @retval None + */ +void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_MONO_STREO_MODE(SAI_MonoMode)); + /* Clear MONO bit */ + SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO); + /* Set new Mono Mode value */ + SAI_Block_x->CR1 |= SAI_MonoMode; +} + +/** + * @brief Configures the TRIState managment on data line for the selected SAI block. + * + * @note This function has a meaning only when the SAI block is configured in transmitter + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_TRIState: specifies the SAI block TRIState management. + * This parameter can be one of the following values: + * @arg SAI_Output_NotReleased : SD output line is still drived by the SAI. + * @arg SAI_Output_Released : SD output line is released (HI-Z) + * @retval None + */ +void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(SAI_TRIState)); + /* Clear MONO bit */ + SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO); + /* Set new Mono Mode value */ + SAI_Block_x->CR1 |= SAI_MonoMode; + +} + +/** + * @brief Configures the companding mode for the selected SAI block. + * + * @note The data expansion or data compression are determined by the state of + * SAI block selected (transmitter or receiver). + + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_CompandingMode: specifies the SAI block companding mode. + * This parameter can be one of the following values: + * @arg SAI_NoCompanding : no companding algorithm set + * @arg SAI_ULaw_1CPL_Companding : Set U law (algorithm 1's complement representation) + * @arg SAI_ALaw_1CPL_Companding : Set A law (algorithm 1's complement repesentation) + * @arg SAI_ULaw_2CPL_Companding : Set U law (algorithm 2's complement representation) + * @arg SAI_ALaw_2CPL_Companding : Set A law (algorithm 2's complement repesentation) + * @retval None + */ +void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_COMPANDING_MODE(SAI_CompandingMode)); + /* Clear Companding Mode bits */ + SAI_Block_x->CR2 &= ~(SAI_xCR2_COMP); + /* Set new Companding Mode value */ + SAI_Block_x->CR2 |= SAI_CompandingMode; +} + +/** + * @brief Enables or disables the Mute mode for the selected SAI block. + * + * @note This function has a meaning only when the audio block is transmitter + * @note Mute mode is applied for an entire frame for all the valid slot + * It becomes active at the end of an audio frame when set somewhere in a frame. + * Mute mode exit occurs at the end of the frame in which the bit MUTE has been set. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param NewState: new state of the SAIx block. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SAI block mute mode */ + SAI_Block_x->CR2 |= SAI_xCR2_MUTE; + } + else + { + /* Disable the selected SAI SS output */ + SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTE); + } +} + +/** + * @brief Configure the mute value for the selected SAI block. + * + * @note This function has a meaning only when the audio block is transmitter + * @note the configuration last value sent during mute mode has only a meaning + * when the number of slot is lower or equal to 2 and if the MUTE bit is set. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_MuteValue: specifies the SAI block mute value. + * This parameter can be one of the following values: + * @arg SAI_ZeroValue : bit value 0 is sent during Mute Mode + * @arg SAI_LastSentValue : Last value is sent during Mute Mode + * @retval None + */ +void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_MUTE_VALUE(SAI_MuteValue)); + + /* Clear Mute value bits */ + SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTEVAL); + /* Set new Mute value */ + SAI_Block_x->CR2 |= SAI_MuteValue; +} + +/** + * @brief Enables or disables the Mute mode for the selected SAI block. + * + * @note This function has a meaning only when the audio block is Receiver + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_MuteCounter: specifies the SAI block mute value. + * This parameter can be a number between 0 and 63. + + * @retval None + */ +void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_MUTE_COUNTER(SAI_MuteCounter)); + + /* Clear Mute value bits */ + SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTECNT); + /* Set new Mute value */ + SAI_Block_x->CR2 |= (SAI_MuteCounter << 7); +} + +/** + * @brief Reinitialize the FIFO pointer + * + * @note The FIFO pointers can be reinitialized at anytime The data present + * into the FIFO, if it is not empty, will be lost. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param NewState: new state of the selected SAI TI communication mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* FIFO flush */ + SAI_Block_x->CR2 |= SAI_xCR2_FFLUSH; +} + +/** + * @} + */ + +/** @defgroup SAI_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + [..] + This section provides a set of functions allowing to manage the SAI data transfers. + [..] + In reception, data are received and then stored into an internal FIFO while + In transmission, data are first stored into an internal FIFO before being + transmitted. + [..] + The read access of the SAI_xDR register can be done using the SAI_ReceiveData() + function and returns the Rx buffered value. Whereas a write access to the SAI_DR + can be done using SAI_SendData() function and stores the written data into + Tx buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the most recent received data by the SAI block x peripheral. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * + * @retval The value of the received data. + */ +uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Return the data in the DR register */ + return SAI_Block_x->DR; +} + +/** + * @brief Transmits a Data through the SAI block x peripheral. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * + * @param Data: Data to be transmitted. + * @retval None + */ +void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Write in the DR register the data to be sent */ + SAI_Block_x->DR = Data; +} + +/** + * @} + */ + +/** @defgroup SAI_Group3 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SAI Block x DMA interface. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param NewState: new state of the selected SAI block DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SAI block mute mode */ + SAI_Block_x->CR1 |= SAI_xCR1_DMAEN; + } + else + { + /* Disable the selected SAI SS output */ + SAI_Block_x->CR1 &= ~(SAI_xCR1_DMAEN); + } +} + +/** + * @} + */ + +/** @defgroup SAI_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] + This section provides a set of functions allowing to configure the SAI Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + *** Polling Mode *** + ==================== + [..] + In Polling Mode, the SAI communication can be managed by 7 flags: + (#) SAI_FLAG_FREQ : to indicate if there is a FIFO Request to write or to read. + (#) SAI_FLAG_MUTEDET : to indicate if a MUTE frame detected + (#) SAI_FLAG_OVRUDR : to indicate if an Overrun or Underrun error occur + (#) SAI_FLAG_AFSDET : to indicate if there is the detection of a audio frame + synchronisation (FS) earlier than expected + (#) SAI_FLAG_LFSDET : to indicate if there is the detection of a audio frame + synchronisation (FS) later than expected + (#) SAI_FLAG_CNRDY : to indicate if the codec is not ready to communicate during + the reception of the TAG 0 (slot0) of the AC97 audio frame + (#) SAI_FLAG_WCKCFG: to indicate if wrong clock configuration in master mode + error occurs. + [..] + In this Mode it is advised to use the following functions: + (+) FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); + (+) void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); + + *** Interrupt Mode *** + ====================== + [..] + In Interrupt Mode, the SAI communication can be managed by 7 interrupt sources + and 7 pending bits: + (+) Pending Bits: + (##) SAI_IT_FREQ : to indicate if there is a FIFO Request to write or to read. + (##) SAI_IT_MUTEDET : to indicate if a MUTE frame detected. + (##) SAI_IT_OVRUDR : to indicate if an Overrun or Underrun error occur. + (##) SAI_IT_AFSDET : to indicate if there is the detection of a audio frame + synchronisation (FS) earlier than expected. + (##) SAI_IT_LFSDET : to indicate if there is the detection of a audio frame + synchronisation (FS) later than expected. + (##) SAI_IT_CNRDY : to indicate if the codec is not ready to communicate during + the reception of the TAG 0 (slot0) of the AC97 audio frame. + (##) SAI_IT_WCKCFG: to indicate if wrong clock configuration in master mode + error occurs. + + (+) Interrupt Source: + (##) SAI_IT_FREQ : specifies the interrupt source for FIFO Request. + (##) SAI_IT_MUTEDET : specifies the interrupt source for MUTE frame detected. + (##) SAI_IT_OVRUDR : specifies the interrupt source for overrun or underrun error. + (##) SAI_IT_AFSDET : specifies the interrupt source for anticipated frame synchronization + detection interrupt. + (##) SAI_IT_LFSDET : specifies the interrupt source for late frame synchronization + detection interrupt. + (##) SAI_IT_CNRDY : specifies the interrupt source for codec not ready interrupt + (##) SAI_IT_WCKCFG: specifies the interrupt source for wrong clock configuration + interrupt. + [..] + In this Mode it is advised to use the following functions: + (+) void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState); + (+) ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); + (+) void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); + + *** DMA Mode *** + ================ + [..] + In DMA Mode, each SAI audio block has an independent DMA interface in order to + read or to write into the SAI_xDR register (to hit the internal FIFO). + There is one DMA channel by audio block following basic DMA request/acknowledge + protocol. + [..] + In this Mode it is advised to use the following function: + (+) void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); + [..] + This section provides also functions allowing to + (+) Check the SAI Block enable status + (+)Check the FIFO status + + *** SAI Block Enable status *** + =============================== + [..] + After disabling a SAI Block, it is recommended to check (or wait until) the SAI Block + is effectively disabled. If a Block is disabled while an audio frame transfer is ongoing + the current frame will be transferred and the block will be effectively disabled only at + the end of audio frame. + To monitor this state it is possible to use the following function: + (+) FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x); + + *** SAI Block FIFO status *** + ============================= + [..] + It is possible to monitor the FIFO status when a transfer is ongoing using the following + function: + (+) uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified SAI Block interrupts. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SAI_IT_FREQ: FIFO Request interrupt mask + * @arg SAI_IT_MUTEDET: MUTE detection interrupt mask + * @arg SAI_IT_OVRUDR: overrun/underrun interrupt mask + * @arg SAI_IT_AFSDET: anticipated frame synchronization detection + * interrupt mask + * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt + * mask + * @arg SAI_IT_CNRDY: codec not ready interrupt mask + * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt mask + * @param NewState: new state of the specified SAI interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected SAI Block interrupt */ + SAI_Block_x->IMR |= SAI_IT; + } + else + { + /* Disable the selected SAI Block interrupt */ + SAI_Block_x->IMR &= ~(SAI_IT); + } +} + +/** + * @brief Checks whether the specified SAI block x flag is set or not. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_FLAG: specifies the SAI block flag to check. + * This parameter can be one of the following values: + * @arg SAI_FLAG_FREQ: FIFO Request flag. + * @arg SAI_FLAG_MUTEDET: MUTE detection flag. + * @arg SAI_FLAG_OVRUDR: overrun/underrun flag. + * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag. + * @arg SAI_FLAG_CNRDY: codec not ready flag. + * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag. + * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag. + * @retval The new state of SAI_FLAG (SET or RESET). + */ +FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_GET_FLAG(SAI_FLAG)); + + /* Check the status of the specified SAI flag */ + if ((SAI_Block_x->SR & SAI_FLAG) != (uint32_t)RESET) + { + /* SAI_FLAG is set */ + bitstatus = SET; + } + else + { + /* SAI_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SAI_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the specified SAI Block x flag. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_FLAG: specifies the SAI block flag to check. + * This parameter can be one of the following values: + * @arg SAI_FLAG_MUTEDET: MUTE detection flag. + * @arg SAI_FLAG_OVRUDR: overrun/underrun flag. + * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag. + * @arg SAI_FLAG_CNRDY: codec not ready flag. + * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag. + * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag. + * + * @note FREQ (FIFO Request) flag is cleared : + * - When the audio block is transmitter and the FIFO is full or the FIFO + * has one data (one buffer mode) depending the bit FTH in the + * SAI_xCR2 register. + * - When the audio block is receiver and the FIFO is not empty + * + * @retval None + */ +void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_CLEAR_FLAG(SAI_FLAG)); + + /* Clear the selected SAI Block flag */ + SAI_Block_x->CLRFR |= SAI_FLAG; +} + +/** + * @brief Checks whether the specified SAI Block x interrupt has occurred or not. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SAI_IT_FREQ: FIFO Request interrupt + * @arg SAI_IT_MUTEDET: MUTE detection interrupt + * @arg SAI_IT_OVRUDR: overrun/underrun interrupt + * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt + * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt + * @arg SAI_IT_CNRDY: codec not ready interrupt + * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt + * + * @retval The new state of SAI_IT (SET or RESET). + */ +ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); + + /* Get the SAI_IT enable bit status */ + enablestatus = (SAI_Block_x->IMR & SAI_IT) ; + + /* Check the status of the specified SAI interrupt */ + if (((SAI_Block_x->SR & SAI_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + /* SAI_IT is set */ + bitstatus = SET; + } + else + { + /* SAI_IT is reset */ + bitstatus = RESET; + } + /* Return the SAI_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SAI Block x interrupt pending bit. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_IT: specifies the SAI Block interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg SAI_IT_MUTEDET: MUTE detection interrupt. + * @arg SAI_IT_OVRUDR: overrun/underrun interrupt. + * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt. + * @arg SAI_IT_CNRDY: codec not ready interrupt. + * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt. + * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt. + * + * @note FREQ (FIFO Request) flag is cleared : + * - When the audio block is transmitter and the FIFO is full or the FIFO + * has one data (one buffer mode) depending the bit FTH in the + * SAI_xCR2 register. + * - When the audio block is receiver and the FIFO is not empty + * + * @retval None + */ +void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); + + /* Clear the selected SAI Block x interrupt pending bit */ + SAI_Block_x->CLRFR |= SAI_IT; +} + +/** + * @brief Returns the status of EN bit for the specified SAI Block x. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * + * @note After disabling a SAI Block, it is recommended to check (or wait until) + * the SAI Block is effectively disabled. If a Block is disabled while + * an audio frame transfer is ongoing, the current frame will be + * transferred and the block will be effectively disabled only at + * the end of audio frame. + * + * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). + */ +FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x) +{ + FunctionalState state = DISABLE; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + if ((SAI_Block_x->CR1 & (uint32_t)SAI_xCR1_SAIEN) != 0) + { + /* The selected SAI Block x EN bit is set (audio frame transfer is ongoing) */ + state = ENABLE; + } + else + { + /* The selected SAI Block x EN bit is cleared (SAI Block is disabled and + all transfers are complete) */ + state = DISABLE; + } + return state; +} + +/** + * @brief Returns the current SAI Block x FIFO filled level. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * + * @retval The FIFO filling state. + * - SAI_FIFOStatus_Empty: when FIFO is empty + * - SAI_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - SAI_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - SAI_FIFOStatus_HalfFull: if more than 1 half-full. + * - SAI_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - SAI_FIFOStatus_Full: when FIFO is full + */ +uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Get the FIFO level bits */ + tmpreg = (uint32_t)((SAI_Block_x->SR & SAI_xSR_FLVL)); + + return tmpreg; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c index 0a0840659..ca1c89585 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c @@ -1,1011 +1,1011 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sdio.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Secure digital input/output interface (SDIO) - * peripheral: - * + Initialization and Configuration - * + Command path state machine (CPSM) management - * + Data path state machine (DPSM) management - * + SDIO IO Cards mode management - * + CE-ATA mode management - * + DMA transfers management - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL - (PLL48CLK). Before to start working with SDIO peripheral make sure that the - PLL is well configured. - The SDIO peripheral uses two clock signals: - (++) SDIO adapter clock (SDIOCLK = 48 MHz) - (++) APB2 bus clock (PCLK2) - - -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition: - Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) - - (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). - - (#) According to the SDIO mode, enable the GPIO clocks using - RCC_AHB1PeriphClockCmd() function. - The I/O can be one of the following configurations: - (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0. - (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. - (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. - - (#) Peripheral alternate function: - (++) Connect the pin to the desired peripherals' Alternate Function (AF) - using GPIO_PinAFConfig() function - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, - GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function - - (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, - hardware, flow control and the Clock Divider using the SDIO_Init() - function. - - (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) - function. - - (#) Enable the clock using the SDIO_ClockCmd() function. - - (#) Enable the NVIC and the corresponding interrupt using the function - SDIO_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using SDIO_DMACmd() function - - (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. - - (#) To control the CPSM (Command Path State Machine) and send - commands to the card use the SDIO_SendCommand(), - SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has - to fill the command structure (pointer to SDIO_CmdInitTypeDef) according - to the selected command to be sent. - The parameters that should be filled are: - (++) Command Argument - (++) Command Index - (++) Command Response type - (++) Command Wait - (++) CPSM Status (Enable or Disable). - - -@@- To check if the command is well received, read the SDIO_CMDRESP - register using the SDIO_GetCommandResponse(). - The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the - SDIO_GetResponse() function. - - (#) To control the DPSM (Data Path State Machine) and send/receive - data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), - SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. - - *** Read Operations *** - ======================= - [..] - (#) First, user has to fill the data structure (pointer to - SDIO_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be from card (To SDIO) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDIO resources to receive the data from the card - according to selected transfer mode (Refer to Step 8, 9 and 10). - - (#) Send the selected Read command (refer to step 11). - - (#) Use the SDIO flags/interrupts to check the transfer status. - - *** Write Operations *** - ======================== - [..] - (#) First, user has to fill the data structure (pointer to - SDIO_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be to card (To CARD) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDIO resources to send the data to the card according to - selected transfer mode (Refer to Step 8, 9 and 10). - - (#) Send the selected Write command (refer to step 11). - - (#) Use the SDIO flags/interrupts to check the transfer status. - - -@endverbatim - * - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_sdio.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ -/* --- CLKCR Register ---*/ -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** @defgroup SDIO_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF: SDIO Power OFF - * @arg SDIO_PowerState_ON: SDIO Power ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER = SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can be one of the - * following values: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions - * @brief Command path state machine (CPSM) management functions - * -@verbatim - =============================================================================== - ##### Command path state machine (CPSM) management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the Command path - state machine (CPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO - * command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions - * @brief Data path state machine (DPSM) management functions - * -@verbatim - =============================================================================== - ##### Data path state machine (DPSM) management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the Data path - state machine (DPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure - * that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure - * which will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions - * @brief SDIO IO Cards mode management functions - * -@verbatim - =============================================================================== - ##### SDIO IO Cards mode management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the SDIO IO Cards. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parameter can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group5 CE-ATA mode management functions - * @brief CE-ATA mode management functions - * -@verbatim - =============================================================================== - ##### CE-ATA mode management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the CE-ATA card. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group6 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - - This section provide functions allowing to program SDIO DMA transfer. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_sdio.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Secure digital input/output interface (SDIO) + * peripheral: + * + Initialization and Configuration + * + Command path state machine (CPSM) management + * + Data path state machine (DPSM) management + * + SDIO IO Cards mode management + * + CE-ATA mode management + * + DMA transfers management + * + Interrupts and flags management + * +@verbatim + + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL + (PLL48CLK). Before to start working with SDIO peripheral make sure that the + PLL is well configured. + The SDIO peripheral uses two clock signals: + (++) SDIO adapter clock (SDIOCLK = 48 MHz) + (++) APB2 bus clock (PCLK2) + + -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition: + Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) + + (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). + + (#) According to the SDIO mode, enable the GPIO clocks using + RCC_AHB1PeriphClockCmd() function. + The I/O can be one of the following configurations: + (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0. + (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. + (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. + + (#) Peripheral alternate function: + (++) Connect the pin to the desired peripherals' Alternate Function (AF) + using GPIO_PinAFConfig() function + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, + GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function + + (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, + hardware, flow control and the Clock Divider using the SDIO_Init() + function. + + (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) + function. + + (#) Enable the clock using the SDIO_ClockCmd() function. + + (#) Enable the NVIC and the corresponding interrupt using the function + SDIO_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function + (++) Active the needed channel Request using SDIO_DMACmd() function + + (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. + + (#) To control the CPSM (Command Path State Machine) and send + commands to the card use the SDIO_SendCommand(), + SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has + to fill the command structure (pointer to SDIO_CmdInitTypeDef) according + to the selected command to be sent. + The parameters that should be filled are: + (++) Command Argument + (++) Command Index + (++) Command Response type + (++) Command Wait + (++) CPSM Status (Enable or Disable). + + -@@- To check if the command is well received, read the SDIO_CMDRESP + register using the SDIO_GetCommandResponse(). + The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the + SDIO_GetResponse() function. + + (#) To control the DPSM (Data Path State Machine) and send/receive + data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), + SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. + + *** Read Operations *** + ======================= + [..] + (#) First, user has to fill the data structure (pointer to + SDIO_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be from card (To SDIO) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDIO resources to receive the data from the card + according to selected transfer mode (Refer to Step 8, 9 and 10). + + (#) Send the selected Read command (refer to step 11). + + (#) Use the SDIO flags/interrupts to check the transfer status. + + *** Write Operations *** + ======================== + [..] + (#) First, user has to fill the data structure (pointer to + SDIO_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be to card (To CARD) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDIO resources to send the data to the card according to + selected transfer mode (Refer to Step 8, 9 and 10). + + (#) Send the selected Write command (refer to step 11). + + (#) Use the SDIO flags/interrupts to check the transfer status. + + +@endverbatim + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_sdio.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ +/* --- CLKCR Register ---*/ +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMD Register ---*/ +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SDIO_Private_Functions + * @{ + */ + +/** @defgroup SDIO_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default reset values. + * @param None + * @retval None + */ +void SDIO_DeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * @retval None + */ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param NewState: new state of the SDIO Clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState: new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_PowerState_OFF: SDIO Power OFF + * @arg SDIO_PowerState_ON: SDIO Power ON + * @retval None + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER = SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @param None + * @retval Power status of the controller. The returned value can be one of the + * following values: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/** + * @} + */ + +/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions + * @brief Command path state machine (CPSM) management functions + * +@verbatim + =============================================================================== + ##### Command path state machine (CPSM) management functions ##### + =============================================================================== + + This section provide functions allowing to program and read the Command path + state machine (CPSM). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for the SDIO + * command. + * @retval None + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * @retval None + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/** + * @brief Returns command index of last command for which response received. + * @param None + * @retval Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @} + */ + +/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions + * @brief Data path state machine (DPSM) management functions + * +@verbatim + =============================================================================== + ##### Data path state machine (DPSM) management functions ##### + =============================================================================== + + This section provide functions allowing to program and read the Data path + state machine (DPSM). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure + * that contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure + * which will be initialized. + * @retval None + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param None + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/** + * @brief Read one data word from Rx FIFO. + * @param None + * @retval Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/** + * @brief Write one data word to Tx FIFO. + * @param Data: 32-bit data word to write. + * @retval None + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read from FIFO. + * @param None + * @retval Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions + * @brief SDIO IO Cards mode management functions + * +@verbatim + =============================================================================== + ##### SDIO IO Cards mode management functions ##### + =============================================================================== + + This section provide functions allowing to program and read the SDIO IO Cards. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param NewState: new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param NewState: new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parameter can be: + * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 + * @retval None + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param NewState: new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param NewState: new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group5 CE-ATA mode management functions + * @brief CE-ATA mode management functions + * +@verbatim + =============================================================================== + ##### CE-ATA mode management functions ##### + =============================================================================== + + This section provide functions allowing to program and read the CE-ATA card. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the command completion signal. + * @param NewState: new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param NewState: new state of CE-ATA interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param NewState: new state of CE-ATA command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group6 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + + This section provide functions allowing to program SDIO DMA transfer. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SDIO DMA request. + * @param NewState: new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group7 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @param NewState: new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's interrupt pending bits. + * @param SDIO_IT: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c index f250aadf3..fa7030708 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c @@ -1,1319 +1,1319 @@ -/** - ****************************************************************************** - * @file stm32f4xx_spi.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial peripheral interface (SPI): - * + Initialization and Configuration - * + Data transfers functions - * + Hardware CRC Calculation - * + DMA transfers management - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable peripheral clock using the following functions - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 - RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI4 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI5 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI6. - - (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() - function. In I2S mode, if an external clock source is used then the I2S - CKIN pin GPIO clock should also be enabled. - - (#) Peripherals alternate function: - (++) Connect the pin to the desired peripherals' Alternate Function (AF) - using GPIO_PinAFConfig() function - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, - GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function In I2S mode, if an external clock source is - used then the I2S CKIN pin should be also configured in Alternate - function Push-pull pull-up mode. - - (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave - Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio - frequency and Polarity using I2S_Init() function. For I2S mode, make sure - that either: - (++) I2S PLL is configured using the functions - RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), RCC_PLLI2SCmd(ENABLE) and - RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY); or - (++) External clock source is configured using the function - RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly - the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. - - (#) Enable the NVIC and the corresponding interrupt using the function - SPI_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using SPI_I2S_DMACmd() function - - (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using - I2S_Cmd(). - - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. - - (#) Optionally, you can enable/configure the following parameters without - re-initialization (i.e there is no need to call again SPI_Init() function): - (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) - is programmed as Data direction parameter using the SPI_Init() function - it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx - using the SPI_BiDirectionalLineConfig() function. - (++) When SPI_NSS_Soft is selected as Slave Select Management parameter - using the SPI_Init() function it can be possible to manage the - NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. - (++) Reconfigure the data size using the SPI_DataSizeConfig() function - (++) Enable or disable the SS output using the SPI_SSOutputCmd() function - - (#) To use the CRC Hardware calculation feature refer to the Peripheral - CRC hardware Calculation subsection. - - - [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI - peripheral is able to manage sending and receiving data simultaneously - using two data lines. Each SPI peripheral has an extended block called I2Sxext - (ie. I2S2ext for SPI2 and I2S3ext for SPI3). - The extension block is not a full SPI IP, it is used only as I2S slave to - implement full duplex mode. The extension block uses the same clock sources - as its master. - To configure I2S full duplex you have to: - - (#) Configure SPIx in I2S mode (I2S_Init() function) as described above. - - (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to - I2S_Init() function. - - (#) Call I2S_Cmd() for SPIx then for its extended block. - - (#) To configure interrupts or DMA requests and to get/clear flag status, - use I2Sxext instance for the extension block. - - [..] Functions that can be called with I2Sxext instances are: I2S_Cmd(), - I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), - SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), - SPI_I2S_ClearFlag(), SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). - - Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx): - - RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); - I2S_StructInit(&I2SInitStruct); - I2SInitStruct.Mode = I2S_Mode_MasterTx; - I2S_Init(SPI3, &I2SInitStruct); - I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) - I2S_Cmd(SPI3, ENABLE); - I2S_Cmd(SPI3ext, ENABLE); - ... - while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) - {} - SPI_I2S_SendData(SPI3, txdata[i]); - ... - while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) - {} - rxdata[i] = SPI_I2S_ReceiveData(I2S3ext); - ... - - [..] - (@) In I2S mode: if an external clock is used as source clock for the I2S, - then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should - be enabled and set to the value of the source clock frequency (in Hz). - - (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() - just after calling the function SPI_Init(). - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_spi.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* SPI registers Masks */ -#define CR1_CLEAR_MASK ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) - -/* RCC PLLs masks */ -#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) -#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) - -#define SPI_CR2_FRF ((uint16_t)0x0010) -#define SPI_SR_TIFRFE ((uint16_t)0x0100) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** @defgroup SPI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to initialize the SPI - Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS - Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial. - - [..] The SPI_Init() function follows the SPI configuration procedures for Master - mode and Slave mode (details for these procedures are available in reference - manual (RM0090)). - -@endverbatim - * @{ - */ - -/** - * @brief De-initialize the SPIx peripheral registers to their default reset values. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode. - * - * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized - * when the relative I2S peripheral is de-initialized (the extended block's clock - * is managed by the I2S peripheral clock). - * - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - else if (SPIx == SPI4) - { - /* Enable SPI4 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE); - /* Release SPI4 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE); - } - else if (SPIx == SPI5) - { - /* Enable SPI5 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE); - /* Release SPI5 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, DISABLE); - } - else - { - if (SPIx == SPI6) - { - /* Enable SPI6 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE); - /* Release SPI6 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * - * @note The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. - * - * @note if an external clock is used as source clock for the I2S, then the define - * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set - * to the value of the the source clock frequency (in Hz). - * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; -#ifndef I2S_EXTERNAL_CLOCK_VAL - uint32_t pllm = 0, plln = 0, pllr = 0; -#endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) *******************/ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get I2S source Clock frequency ****************************************/ - - /* If an external I2S clock has to be used, this define should be set - in the project configuration or in the stm32f4xx_conf.h file */ - #ifdef I2S_EXTERNAL_CLOCK_VAL - /* Set external clock as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) - { - RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; - } - - /* Set the I2S clock to the external clock value */ - i2sclk = I2S_EXTERNAL_CLOCK_VAL; - - #else /* There is no define for External I2S clock source */ - /* Set PLLI2S as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) - { - RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; - } - - /* Get the PLLI2SN value */ - plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ - (RCC_PLLI2SCFGR_PLLI2SN >> 6)); - - /* Get the PLLI2SR value */ - pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ - (RCC_PLLI2SCFGR_PLLI2SR >> 28)); - - /* Get the PLLM value */ - pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE) - { - /* Get the I2S source clock value */ - i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); - } - else - { /* Get the I2S source clock value */ - i2sclk = (uint32_t)(((HSI_VALUE / pllm) * plln) / pllr); - } - #endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Compute the Real divider depending on the MCLK output state, with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the flatting point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= SPI_CR1_SPE; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext - * for full duplex mode). - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; - } - else - { - /* Disable the selected SPI peripheral in I2S mode */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA - * are not taken into consideration and are configured by hardware - * respectively to the TI mode requirements. - * - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 - * @param NewState: new state of the selected SPI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TI mode for the selected SPI peripheral */ - SPIx->CR2 |= SPI_CR2_FRF; - } - else - { - /* Disable the TI mode for the selected SPI peripheral */ - SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; - } -} - -/** - * @brief Configures the full duplex mode for the I2Sx peripheral using its - * extension I2Sxext according to the specified parameters in the - * I2S_InitStruct. - * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block. - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified I2S peripheral - * extension. - * - * @note The structure pointed by I2S_InitStruct parameter should be the same - * used for the master I2S peripheral. In this case, if the master is - * configured as transmitter, the slave will be receiver and vice versa. - * Or you can force a different mode by modifying the field I2S_Mode to the - * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration. - * - * @note The I2S full duplex extension can be configured in slave mode only. - * - * @retval None - */ -void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, tmp = 0; - - /* Check the I2S parameters */ - assert_param(IS_I2S_EXT_PERIPH(I2Sxext)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; - I2Sxext->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = I2Sxext->I2SCFGR; - - /* Get the mode to be configured for the extended I2S */ - if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) - { - tmp = I2S_Mode_SlaveRx; - } - else - { - if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx)) - { - tmp = I2S_Mode_SlaveTx; - } - } - - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - I2Sxext->I2SCFGR = tmpreg; -} - -/** - * @} - */ - -/** @defgroup SPI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - - [..] This section provides a set of functions allowing to manage the SPI data - transfers. In reception, data are received and then stored into an internal - Rx buffer while. In transmission, data are first stored into an internal Tx - buffer before being transmitted. - - [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SPI_DR - can be done using SPI_I2S_SendData() function and stores the written data into - Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @} - */ - -/** @defgroup SPI_Group3 Hardware CRC Calculation functions - * @brief Hardware CRC Calculation functions - * -@verbatim - =============================================================================== - ##### Hardware CRC Calculation functions ##### - =============================================================================== - - [..] This section provides a set of functions allowing to manage the SPI CRC hardware - calculation - - [..] SPI communication using CRC is possible through the following procedure: - (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, - Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - (#) Enable the CRC calculation using the SPI_CalculateCRC() function. - (#) Enable the SPI using the SPI_Cmd() function - (#) Before writing the last data to the TX buffer, set the CRCNext bit using the - SPI_TransmitCRC() function to indicate that after transmission of the last - data, the CRC should be transmitted. - (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT - bit is reset. The CRC is also received and compared against the SPI_RXCRCR - value. - If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt - can be generated when the SPI_I2S_IT_ERR interrupt is enabled. - - [..] - (@) It is advised not to read the calculated CRC values during the communication. - - (@) When the SPI is in slave mode, be careful to enable CRC calculation only - when the clock is stable, that is, when the clock is in the steady state. - If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive - to the SCK slave input clock as soon as CRCEN is set, and this, whatever - the value of the SPE bit. - - (@) With high bitrate frequencies, be careful when transmitting the CRC. - As the number of used CPU cycles has to be as low as possible in the CRC - transfer phase, it is forbidden to call software functions in the CRC - transmission sequence to avoid errors in the last data and CRC reception. - In fact, CRCNEXT bit has to be written before the end of the transmission/reception - of the last data. - - (@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the - degradation of the SPI speed performance due to CPU accesses impacting the - SPI bandwidth. - - (@) When the STM32F4xx is configured as slave and the NSS hardware mode is - used, the NSS pin needs to be kept low between the data phase and the CRC - phase. - - (@) When the SPI is configured in slave mode with the CRC feature enabled, CRC - calculation takes place even if a high level is applied on the NSS pin. - This may happen for example in case of a multi-slave environment where the - communication master addresses slaves alternately. - - (@) Between a slave de-selection (high level on NSS) and a new slave selection - (low level on NSS), the CRC value should be cleared on both master and slave - sides in order to resynchronize the master and slave for their respective - CRC calculation. - - (@) To clear the CRC, follow the procedure below: - (#@) Disable SPI using the SPI_Cmd() function - (#@) Disable the CRC calculation using the SPI_CalculateCRC() function. - (#@) Enable the CRC calculation using the SPI_CalculateCRC() function. - (#@) Enable SPI using the SPI_Cmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= SPI_CR1_CRCEN; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); - } -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= SPI_CR1_CRCNEXT; -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @} - */ - -/** @defgroup SPI_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides a set of functions allowing to configure the SPI Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - *** Polling Mode *** - ==================== -[..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags: - (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register - (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register - (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. - (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur - (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur - (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur - (#) I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. - (#) I2S_FLAG_UDR: to indicate an Underrun error occurs. - (#) I2S_FLAG_CHSIDE: to indicate Channel Side. - - (@) Do not use the BSY flag to handle each data transmission or reception. It is - better to use the TXE and RXNE flags instead. - - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - *** Interrupt Mode *** - ====================== - [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources - and 7 pending bits: - (+) Pending Bits: - (##) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register - (##) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register - (##) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) - (##) SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) - (##) SPI_I2S_IT_OVR : to indicate if an Overrun error occur - (##) I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). - (##) I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). - - (+) Interrupt Source: - (##) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty - interrupt. - (##) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - (##) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. - - [..] In this Mode it is advised to use the following functions: - (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - *** DMA Mode *** - ================ - [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: - (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request - (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - [..] In this Mode it is advised to use the following function: - (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState - NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Checks whether the specified SPIx/I2Sx flag is set or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg SPI_I2S_FLAG_TIFRFE: Format Error. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - - /* Check the status of the specified SPI flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * - * @note OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun interrupt. - * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S_IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI_I2S_IT IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR interrupt pending bit. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * - * @note OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_spi.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Serial peripheral interface (SPI): + * + Initialization and Configuration + * + Data transfers functions + * + Hardware CRC Calculation + * + DMA transfers management + * + Interrupts and flags management + * +@verbatim + + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) Enable peripheral clock using the following functions + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 + RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3 + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI4 + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI5 + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI6. + + (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() + function. In I2S mode, if an external clock source is used then the I2S + CKIN pin GPIO clock should also be enabled. + + (#) Peripherals alternate function: + (++) Connect the pin to the desired peripherals' Alternate Function (AF) + using GPIO_PinAFConfig() function + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, + GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function In I2S mode, if an external clock source is + used then the I2S CKIN pin should be also configured in Alternate + function Push-pull pull-up mode. + + (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave + Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + function. + In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio + frequency and Polarity using I2S_Init() function. For I2S mode, make sure + that either: + (++) I2S PLL is configured using the functions + RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), RCC_PLLI2SCmd(ENABLE) and + RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY); or + (++) External clock source is configured using the function + RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly + the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. + + (#) Enable the NVIC and the corresponding interrupt using the function + SPI_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function + (++) Active the needed channel Request using SPI_I2S_DMACmd() function + + (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using + I2S_Cmd(). + + (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. + + (#) Optionally, you can enable/configure the following parameters without + re-initialization (i.e there is no need to call again SPI_Init() function): + (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) + is programmed as Data direction parameter using the SPI_Init() function + it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx + using the SPI_BiDirectionalLineConfig() function. + (++) When SPI_NSS_Soft is selected as Slave Select Management parameter + using the SPI_Init() function it can be possible to manage the + NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. + (++) Reconfigure the data size using the SPI_DataSizeConfig() function + (++) Enable or disable the SS output using the SPI_SSOutputCmd() function + + (#) To use the CRC Hardware calculation feature refer to the Peripheral + CRC hardware Calculation subsection. + + + [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI + peripheral is able to manage sending and receiving data simultaneously + using two data lines. Each SPI peripheral has an extended block called I2Sxext + (ie. I2S2ext for SPI2 and I2S3ext for SPI3). + The extension block is not a full SPI IP, it is used only as I2S slave to + implement full duplex mode. The extension block uses the same clock sources + as its master. + To configure I2S full duplex you have to: + + (#) Configure SPIx in I2S mode (I2S_Init() function) as described above. + + (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to + I2S_Init() function. + + (#) Call I2S_Cmd() for SPIx then for its extended block. + + (#) To configure interrupts or DMA requests and to get/clear flag status, + use I2Sxext instance for the extension block. + + [..] Functions that can be called with I2Sxext instances are: I2S_Cmd(), + I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), + SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), + SPI_I2S_ClearFlag(), SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). + + Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx): + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); + I2S_StructInit(&I2SInitStruct); + I2SInitStruct.Mode = I2S_Mode_MasterTx; + I2S_Init(SPI3, &I2SInitStruct); + I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) + I2S_Cmd(SPI3, ENABLE); + I2S_Cmd(SPI3ext, ENABLE); + ... + while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + {} + SPI_I2S_SendData(SPI3, txdata[i]); + ... + while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) + {} + rxdata[i] = SPI_I2S_ReceiveData(I2S3ext); + ... + + [..] + (@) In I2S mode: if an external clock is used as source clock for the I2S, + then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should + be enabled and set to the value of the source clock frequency (in Hz). + + (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() + just after calling the function SPI_Init(). + +@endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_spi.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* SPI registers Masks */ +#define CR1_CLEAR_MASK ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) + +/* RCC PLLs masks */ +#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) +#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) + +#define SPI_CR2_FRF ((uint16_t)0x0010) +#define SPI_SR_TIFRFE ((uint16_t)0x0100) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** @defgroup SPI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides a set of functions allowing to initialize the SPI + Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS + Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial. + + [..] The SPI_Init() function follows the SPI configuration procedures for Master + mode and Slave mode (details for these procedures are available in reference + manual (RM0090)). + +@endverbatim + * @{ + */ + +/** + * @brief De-initialize the SPIx peripheral registers to their default reset values. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 + * in SPI mode or 2 or 3 in I2S mode. + * + * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized + * when the relative I2S peripheral is de-initialized (the extended block's clock + * is managed by the I2S peripheral clock). + * + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + else if (SPIx == SPI4) + { + /* Enable SPI4 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE); + /* Release SPI4 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE); + } + else if (SPIx == SPI5) + { + /* Enable SPI5 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE); + /* Release SPI5 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, DISABLE); + } + else + { + if (SPIx == SPI6) + { + /* Enable SPI6 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE); + /* Release SPI6 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * + * @note The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. + * + * @note if an external clock is used as source clock for the I2S, then the define + * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set + * to the value of the the source clock frequency (in Hz). + * + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0, i2sclk = 0; +#ifndef I2S_EXTERNAL_CLOCK_VAL + uint32_t pllm = 0, plln = 0, pllr = 0; +#endif /* I2S_EXTERNAL_CLOCK_VAL */ + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) *******************/ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get I2S source Clock frequency ****************************************/ + + /* If an external I2S clock has to be used, this define should be set + in the project configuration or in the stm32f4xx_conf.h file */ + #ifdef I2S_EXTERNAL_CLOCK_VAL + /* Set external clock as I2S clock source */ + if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) + { + RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; + } + + /* Set the I2S clock to the external clock value */ + i2sclk = I2S_EXTERNAL_CLOCK_VAL; + + #else /* There is no define for External I2S clock source */ + /* Set PLLI2S as I2S clock source */ + if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) + { + RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; + } + + /* Get the PLLI2SN value */ + plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ + (RCC_PLLI2SCFGR_PLLI2SN >> 6)); + + /* Get the PLLI2SR value */ + pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ + (RCC_PLLI2SCFGR_PLLI2SR >> 28)); + + /* Get the PLLM value */ + pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE) + { + /* Get the I2S source clock value */ + i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); + } + else + { /* Get the I2S source clock value */ + i2sclk = (uint32_t)(((HSI_VALUE / pllm) * plln) / pllr); + } + #endif /* I2S_EXTERNAL_CLOCK_VAL */ + + /* Compute the Real divider depending on the MCLK output state, with a floating point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the flatting point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= SPI_CR1_SPE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext + * for full duplex mode). + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH_EXT(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; + } + else + { + /* Disable the selected SPI peripheral in I2S mode */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * + * @note This function can be called only after the SPI_Init() function has + * been called. + * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA + * are not taken into consideration and are configured by hardware + * respectively to the TI mode requirements. + * + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 + * @param NewState: new state of the selected SPI TI communication mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TI mode for the selected SPI peripheral */ + SPIx->CR2 |= SPI_CR2_FRF; + } + else + { + /* Disable the TI mode for the selected SPI peripheral */ + SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; + } +} + +/** + * @brief Configures the full duplex mode for the I2Sx peripheral using its + * extension I2Sxext according to the specified parameters in the + * I2S_InitStruct. + * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block. + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified I2S peripheral + * extension. + * + * @note The structure pointed by I2S_InitStruct parameter should be the same + * used for the master I2S peripheral. In this case, if the master is + * configured as transmitter, the slave will be receiver and vice versa. + * Or you can force a different mode by modifying the field I2S_Mode to the + * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration. + * + * @note The I2S full duplex extension can be configured in slave mode only. + * + * @retval None + */ +void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, tmp = 0; + + /* Check the I2S parameters */ + assert_param(IS_I2S_EXT_PERIPH(I2Sxext)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; + I2Sxext->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = I2Sxext->I2SCFGR; + + /* Get the mode to be configured for the extended I2S */ + if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) + { + tmp = I2S_Mode_SlaveRx; + } + else + { + if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx)) + { + tmp = I2S_Mode_SlaveTx; + } + } + + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + I2Sxext->I2SCFGR = tmpreg; +} + +/** + * @} + */ + +/** @defgroup SPI_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + + [..] This section provides a set of functions allowing to manage the SPI data + transfers. In reception, data are received and then stored into an internal + Rx buffer while. In transmission, data are first stored into an internal Tx + buffer before being transmitted. + + [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() + function and returns the Rx buffered value. Whereas a write access to the SPI_DR + can be done using SPI_I2S_SendData() function and stores the written data into + Tx buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 + * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 + * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. + * @param Data: Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @} + */ + +/** @defgroup SPI_Group3 Hardware CRC Calculation functions + * @brief Hardware CRC Calculation functions + * +@verbatim + =============================================================================== + ##### Hardware CRC Calculation functions ##### + =============================================================================== + + [..] This section provides a set of functions allowing to manage the SPI CRC hardware + calculation + + [..] SPI communication using CRC is possible through the following procedure: + (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, + Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + function. + (#) Enable the CRC calculation using the SPI_CalculateCRC() function. + (#) Enable the SPI using the SPI_Cmd() function + (#) Before writing the last data to the TX buffer, set the CRCNext bit using the + SPI_TransmitCRC() function to indicate that after transmission of the last + data, the CRC should be transmitted. + (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT + bit is reset. The CRC is also received and compared against the SPI_RXCRCR + value. + If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt + can be generated when the SPI_I2S_IT_ERR interrupt is enabled. + + [..] + (@) It is advised not to read the calculated CRC values during the communication. + + (@) When the SPI is in slave mode, be careful to enable CRC calculation only + when the clock is stable, that is, when the clock is in the steady state. + If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive + to the SCK slave input clock as soon as CRCEN is set, and this, whatever + the value of the SPE bit. + + (@) With high bitrate frequencies, be careful when transmitting the CRC. + As the number of used CPU cycles has to be as low as possible in the CRC + transfer phase, it is forbidden to call software functions in the CRC + transmission sequence to avoid errors in the last data and CRC reception. + In fact, CRCNEXT bit has to be written before the end of the transmission/reception + of the last data. + + (@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the + degradation of the SPI speed performance due to CPU accesses impacting the + SPI bandwidth. + + (@) When the STM32F4xx is configured as slave and the NSS hardware mode is + used, the NSS pin needs to be kept low between the data phase and the CRC + phase. + + (@) When the SPI is configured in slave mode with the CRC feature enabled, CRC + calculation takes place even if a high level is applied on the NSS pin. + This may happen for example in case of a multi-slave environment where the + communication master addresses slaves alternately. + + (@) Between a slave de-selection (high level on NSS) and a new slave selection + (low level on NSS), the CRC value should be cleared on both master and slave + sides in order to resynchronize the master and slave for their respective + CRC calculation. + + (@) To clear the CRC, follow the procedure below: + (#@) Disable SPI using the SPI_Cmd() function + (#@) Disable the CRC calculation using the SPI_CalculateCRC() function. + (#@) Enable the CRC calculation using the SPI_CalculateCRC() function. + (#@) Enable SPI using the SPI_Cmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= SPI_CR1_CRCEN; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); + } +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= SPI_CR1_CRCNEXT; +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @} + */ + +/** @defgroup SPI_Group4 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 + * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. + * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @} + */ + +/** @defgroup SPI_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + [..] This section provides a set of functions allowing to configure the SPI Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + *** Polling Mode *** + ==================== +[..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags: + (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register + (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register + (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. + (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur + (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur + (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur + (#) I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. + (#) I2S_FLAG_UDR: to indicate an Underrun error occurs. + (#) I2S_FLAG_CHSIDE: to indicate Channel Side. + + (@) Do not use the BSY flag to handle each data transmission or reception. It is + better to use the TXE and RXNE flags instead. + + [..] In this Mode it is advised to use the following functions: + (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + + *** Interrupt Mode *** + ====================== + [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources + and 7 pending bits: + (+) Pending Bits: + (##) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register + (##) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register + (##) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) + (##) SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) + (##) SPI_I2S_IT_OVR : to indicate if an Overrun error occur + (##) I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). + (##) I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). + + (+) Interrupt Source: + (##) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty + interrupt. + (##) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + (##) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. + + [..] In this Mode it is advised to use the following functions: + (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); + (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + + *** DMA Mode *** + ================ + [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: + (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request + (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request + + [..] In this Mode it is advised to use the following function: + (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState + NewState); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 + * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. + * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Checks whether the specified SPIx/I2Sx flag is set or not. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 + * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. + * @param SPI_I2S_FLAG: specifies the SPI flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg SPI_I2S_FLAG_TIFRFE: Format Error. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + + /* Check the status of the specified SPI flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 + * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * + * @note OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * @note UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 + * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. + * @param SPI_I2S_IT: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun interrupt. + * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI_I2S_IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI_I2S_IT IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 + * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR interrupt pending bit. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * + * @note OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI_I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c index 3f8a1f0cd..29f472dfa 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c @@ -1,240 +1,240 @@ -/** - ****************************************************************************** - * @file stm32f4xx_syscfg.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the SYSCFG peripheral. - * - @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] This driver provides functions for: - - (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() - - (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for - STM32F42xxx/43xxx devices Devices. - - (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() - - (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() - - -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers, - using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_syscfg.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SYSCFG - * @brief SYSCFG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) -/* --- MEMRMP Register ---*/ -/* Alias word address of UFB_MODE bit */ -#define MEMRMP_OFFSET SYSCFG_OFFSET -#define UFB_MODE_BitNumber ((uint8_t)0x8) -#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4)) - - -/* --- PMC Register ---*/ -/* Alias word address of MII_RMII_SEL bit */ -#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) -#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) - -/* --- CMPCR Register ---*/ -/* Alias word address of CMP_PD bit */ -#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) -#define CMP_PD_BitNumber ((uint8_t)0x00) -#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SYSCFG_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) - * registers to their default reset values. - * @param None - * @retval None - */ -void SYSCFG_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); -} - -/** - * @brief Changes the mapping of the specified pin. - * @param SYSCFG_Memory: selects the memory remapping. - * This parameter can be one of the following values: - * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices. - * @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices. - * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices. - * @retval None - */ -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); - - SYSCFG->MEMRMP = SYSCFG_MemoryRemap; -} - -/** - * @brief Enables or disables the Interal FLASH Bank Swapping. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param NewState: new state of Interal FLASH Bank swapping. - * This parameter can be one of the following values: - * @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) - * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) - * @arg DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) - and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) - * @retval None - */ -void SYSCFG_MemorySwappingBank(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) UFB_MODE_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for - * EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I) - * for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H) - * for STM32401xx devices. - * - * @param EXTI_PinSourcex: specifies the EXTI line to be configured. - * This parameter can be EXTI_PinSourcex where x can be (0..15, except - * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx - * and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can - * be (0..7) for STM32F42xxx/43xxx devices. - * - * @retval None - */ -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) -{ - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); - assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); - - tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); -} - -/** - * @brief Selects the ETHERNET media interface - * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected - * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected - * @retval None - */ -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) -{ - assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); - /* Configure MII_RMII selection bit */ - *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; -} - -/** - * @brief Enables or disables the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @param NewState: new state of the I/O Compensation Cell. - * This parameter can be one of the following values: - * @arg ENABLE: I/O compensation cell enabled - * @arg DISABLE: I/O compensation cell power-down mode - * @retval None - */ -void SYSCFG_CompensationCellCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the I/O Compensation Cell ready flag is set or not. - * @param None - * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) - */ -FlagStatus SYSCFG_GetCompensationCellStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_syscfg.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the SYSCFG peripheral. + * + @verbatim + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] This driver provides functions for: + + (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() + + (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for + STM32F42xxx/43xxx devices Devices. + + (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() + + (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() + + -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers, + using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_syscfg.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SYSCFG + * @brief SYSCFG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) +/* --- MEMRMP Register ---*/ +/* Alias word address of UFB_MODE bit */ +#define MEMRMP_OFFSET SYSCFG_OFFSET +#define UFB_MODE_BitNumber ((uint8_t)0x8) +#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4)) + + +/* --- PMC Register ---*/ +/* Alias word address of MII_RMII_SEL bit */ +#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) +#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) +#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) + +/* --- CMPCR Register ---*/ +/* Alias word address of CMP_PD bit */ +#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) +#define CMP_PD_BitNumber ((uint8_t)0x00) +#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SYSCFG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) + * registers to their default reset values. + * @param None + * @retval None + */ +void SYSCFG_DeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); +} + +/** + * @brief Changes the mapping of the specified pin. + * @param SYSCFG_Memory: selects the memory remapping. + * This parameter can be one of the following values: + * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices. + * @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices. + * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices. + * @retval None + */ +void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); + + SYSCFG->MEMRMP = SYSCFG_MemoryRemap; +} + +/** + * @brief Enables or disables the Interal FLASH Bank Swapping. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param NewState: new state of Interal FLASH Bank swapping. + * This parameter can be one of the following values: + * @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) + * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) + * @arg DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) + and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) + * @retval None + */ +void SYSCFG_MemorySwappingBank(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) UFB_MODE_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for + * EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I) + * for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H) + * for STM32401xx devices. + * + * @param EXTI_PinSourcex: specifies the EXTI line to be configured. + * This parameter can be EXTI_PinSourcex where x can be (0..15, except + * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx + * and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can + * be (0..7) for STM32F42xxx/43xxx devices. + * + * @retval None + */ +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) +{ + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); + assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); + + tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); +} + +/** + * @brief Selects the ETHERNET media interface + * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. + * This parameter can be one of the following values: + * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected + * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected + * @retval None + */ +void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) +{ + assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); + /* Configure MII_RMII selection bit */ + *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; +} + +/** + * @brief Enables or disables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @param NewState: new state of the I/O Compensation Cell. + * This parameter can be one of the following values: + * @arg ENABLE: I/O compensation cell enabled + * @arg DISABLE: I/O compensation cell power-down mode + * @retval None + */ +void SYSCFG_CompensationCellCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; +} + +/** + * @brief Checks whether the I/O Compensation Cell ready flag is set or not. + * @param None + * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) + */ +FlagStatus SYSCFG_GetCompensationCellStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c index 7ac3e4f7e..79bd26503 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c @@ -1,3365 +1,3365 @@ -/** - ****************************************************************************** - * @file stm32f4xx_tim.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the TIM peripheral: - * + TimeBase management - * + Output Compare management - * + Input Capture management - * + Advanced-control timers (TIM1 and TIM8) specific features - * + Interrupts, DMA and flags management - * + Clocks management - * + Synchronization management - * + Specific interface management - * + Specific remapping management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - This driver provides functions to configure and program the TIM - of all STM32F4xx devices. - These functions are split in 9 groups: - - (#) TIM TimeBase management: this group includes all needed functions - to configure the TM Timebase unit: - (++) Set/Get Prescaler - (++) Set/Get Autoreload - (++) Counter modes configuration - (++) Set Clock division - (++) Select the One Pulse mode - (++) Update Request Configuration - (++) Update Disable Configuration - (++) Auto-Preload Configuration - (++) Enable/Disable the counter - - (#) TIM Output Compare management: this group includes all needed - functions to configure the Capture/Compare unit used in Output - compare mode: - (++) Configure each channel, independently, in Output Compare mode - (++) Select the output compare modes - (++) Select the Polarities of each channel - (++) Set/Get the Capture/Compare register values - (++) Select the Output Compare Fast mode - (++) Select the Output Compare Forced mode - (++) Output Compare-Preload Configuration - (++) Clear Output Compare Reference - (++) Select the OCREF Clear signal - (++) Enable/Disable the Capture/Compare Channels - - (#) TIM Input Capture management: this group includes all needed - functions to configure the Capture/Compare unit used in - Input Capture mode: - (++) Configure each channel in input capture mode - (++) Configure Channel1/2 in PWM Input mode - (++) Set the Input Capture Prescaler - (++) Get the Capture/Compare values - - (#) Advanced-control timers (TIM1 and TIM8) specific features - (++) Configures the Break input, dead time, Lock level, the OSSI, - the OSSR State and the AOE(automatic output enable) - (++) Enable/Disable the TIM peripheral Main Outputs - (++) Select the Commutation event - (++) Set/Reset the Capture Compare Preload Control bit - - (#) TIM interrupts, DMA and flags management - (++) Enable/Disable interrupt sources - (++) Get flags status - (++) Clear flags/ Pending bits - (++) Enable/Disable DMA requests - (++) Configure DMA burst mode - (++) Select CaptureCompare DMA request - - (#) TIM clocks management: this group includes all needed functions - to configure the clock controller unit: - (++) Select internal/External clock - (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx - - (#) TIM synchronization management: this group includes all needed - functions to configure the Synchronization unit: - (++) Select Input Trigger - (++) Select Output Trigger - (++) Select Master Slave Mode - (++) ETR Configuration when used as external trigger - - (#) TIM specific interface management, this group includes all - needed functions to use the specific TIM interface: - (++) Encoder Interface Configuration - (++) Select Hall Sensor - - (#) TIM specific remapping management includes the Remapping - configuration of specific timers - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_tim.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_MASK ((uint16_t)0x00FF) -#define CCMR_OFFSET ((uint16_t)0x0018) -#define CCER_CCE_SET ((uint16_t)0x0001) -#define CCER_CCNE_SET ((uint16_t)0x0004) -#define CCMR_OC13M_MASK ((uint16_t)0xFF8F) -#define CCMR_OC24M_MASK ((uint16_t)0x8FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** @defgroup TIM_Group1 TimeBase management functions - * @brief TimeBase management functions - * -@verbatim - =============================================================================== - ##### TimeBase management functions ##### - =============================================================================== - - - ##### TIM Driver: how to use it in Timing(Time base) Mode ##### - =============================================================================== - [..] - To use the Timer in Timing(Time base) mode, the following steps are mandatory: - - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. - - (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit - with the corresponding configuration - - (#) Enable the NVIC if you need to generate the update interrupt. - - (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) - - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - -@- All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval None - - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if (TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if (TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else if (TIMx == TIM11) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); - } - else if (TIMx == TIM12) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); - } - else if (TIMx == TIM13) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); - } - else - { - if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM8)|| - (TIMx == TIM2) || (TIMx == TIM3)|| - (TIMx == TIM4) || (TIMx == TIM5)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM8)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediatly */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); - - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Counter Register value - */ -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Global: Source of update is the counter - * overflow/underflow or the setting of UG bit, or an update - * generation through the slave mode controller. - * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; - } -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); - - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group2 Output Compare management functions - * @brief Output Compare management functions - * -@verbatim - =============================================================================== - ##### Output Compare management functions ##### - =============================================================================== - - - ##### TIM Driver: how to use it in Output Compare Mode ##### - =============================================================================== - [..] - To use the Timer in Output Compare mode, the following steps are mandatory: - - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) - function - - (#) Configure the TIM pins by configuring the corresponding GPIO pins - - (#) Configure the Time base unit as described in the first part of this driver, - (++) if needed, else the Timer will run with the default configuration: - Autoreload value = 0xFFFF - (++) Prescaler value = 0x0000 - (++) Counter mode = Up counting - (++) Clock Division = TIM_CKD_DIV1 - - (#) Fill the TIM_OCInitStruct with the desired parameters including: - (++) The TIM Output Compare mode: TIM_OCMode - (++) TIM Output State: TIM_OutputState - (++) TIM Pulse value: TIM_Pulse - (++) TIM Output Compare Polarity : TIM_OCPolarity - - (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired - channel with the corresponding configuration - - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - -@- All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - - -@- In case of PWM mode, this function is mandatory: - TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); - - -@- If the corresponding interrupt or DMA request are needed, the user should: - (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). - (+@) Enable the corresponding interrupt (or DMA request) using the function - TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIMx Channel1 according to the specified parameters in - * the TIM_OCInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NE; - - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x00000000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. If needed, user has to enable this channel using - * TIM_CCxCmd() and TIM_CCxNCmd() functions. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_OFFSET; - - tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - tmpccer |= TIM_OCNPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_SET << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_SET << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} -/** - * @} - */ - -/** @defgroup TIM_Group3 Input Capture management functions - * @brief Input Capture management functions - * -@verbatim - =============================================================================== - ##### Input Capture management functions ##### - =============================================================================== - - ##### TIM Driver: how to use it in Input Capture Mode ##### - =============================================================================== - [..] - To use the Timer in Input Capture mode, the following steps are mandatory: - - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) - function - - (#) Configure the TIM pins by configuring the corresponding GPIO pins - - (#) Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - (++) Autoreload value = 0xFFFF - (++) Prescaler value = 0x0000 - (++) Counter mode = Up counting - (++) Clock Division = TIM_CKD_DIV1 - - (#) Fill the TIM_ICInitStruct with the desired parameters including: - (++) TIM Channel: TIM_Channel - (++) TIM Input Capture polarity: TIM_ICPolarity - (++) TIM Input Capture selection: TIM_ICSelection - (++) TIM Input Capture Prescaler: TIM_ICPrescaler - (++) TIM Input CApture filter value: TIM_ICFilter - - (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel - with the corresponding configuration and to measure only frequency - or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) - to configure the desired channels with the corresponding configuration - and to measure the frequency and the duty cycle of the input signal - - (#) Enable the NVIC or the DMA to read the measured frequency. - - (#) Enable the corresponding interrupt (or DMA request) to read the Captured - value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) - (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - (#) Use TIM_GetCapturex(TIMx); to read the captured value. - - -@- All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Configures the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval Capture Compare 2 Register value. - */ -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} -/** - * @} - */ - -/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features - * @brief Advanced-control timers (TIM1 and TIM8) specific features - * -@verbatim - =============================================================================== - ##### Advanced-control timers (TIM1 and TIM8) specific features ##### - =============================================================================== - - ##### TIM Driver: how to use the Break feature ##### - =============================================================================== - [..] - After configuring the Timer channel(s) in the appropriate Output Compare mode: - - (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer - Break Polarity, dead time, Lock level, the OSSI/OSSR State and the - AOE(automatic output enable). - - (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer - - (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) - - (#) Once the break even occurs, the Timer's output signals are put in reset - state or in a known state (according to the configuration made in - TIM_BDTRConfig() function). - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group5 Interrupts DMA and flags management functions - * @brief Interrupts, DMA and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts, DMA and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used - * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, - * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. - * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can - * be used: TIM_IT_Update or TIM_IT_CC1 - * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 - * - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM1_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_RCR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_BDTR - * @arg TIM_DMABase_DCR - * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group6 Clocks management functions - * @brief Clocks management functions - * -@verbatim - =============================================================================== - ##### Clocks management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_InputTriggerSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter: specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - tmpsmcr |= TIM_TS_ETRF; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} -/** - * @} - */ - -/** @defgroup TIM_Group7 Synchronization management functions - * @brief Synchronization management functions - * -@verbatim - =============================================================================== - ##### Synchronization management functions ##### - =============================================================================== - - ##### TIM Driver: how to use it in synchronization Mode ##### - =============================================================================== - [..] - - *** Case of two/several Timers *** - ================================== - [..] - (#) Configure the Master Timers using the following functions: - (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); - (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - - *** Case of Timers and external trigger(ETR pin) *** - ==================================================== - [..] - (#) Configure the External trigger using this function: - (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - -@endverbatim - * @{ - */ - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This parameter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs(TRGO) - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize - * the counter and triggers an update of the registers - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO) - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_MASK; - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @} - */ - -/** @defgroup TIM_Group8 Specific interface management functions - * @brief Specific interface management functions - * -@verbatim - =============================================================================== - ##### Specific interface management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group9 Specific remapping management function - * @brief Specific remapping management function - * -@verbatim - =============================================================================== - ##### Specific remapping management function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. - * @param TIM_Remap: specifies the TIM input remapping source. - * This parameter can be one of the following values: - * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) - * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output. - * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. - * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. - * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. - * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. - * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. - * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock - * (HSE divided by a programmable prescaler) - * @retval None - */ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_REMAP(TIM_Remap)); - - /* Set the Timer remapping configuration */ - TIMx->OR = TIM_Remap; -} -/** - * @} - */ - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_tim.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the TIM peripheral: + * + TimeBase management + * + Output Compare management + * + Input Capture management + * + Advanced-control timers (TIM1 and TIM8) specific features + * + Interrupts, DMA and flags management + * + Clocks management + * + Synchronization management + * + Specific interface management + * + Specific remapping management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + This driver provides functions to configure and program the TIM + of all STM32F4xx devices. + These functions are split in 9 groups: + + (#) TIM TimeBase management: this group includes all needed functions + to configure the TM Timebase unit: + (++) Set/Get Prescaler + (++) Set/Get Autoreload + (++) Counter modes configuration + (++) Set Clock division + (++) Select the One Pulse mode + (++) Update Request Configuration + (++) Update Disable Configuration + (++) Auto-Preload Configuration + (++) Enable/Disable the counter + + (#) TIM Output Compare management: this group includes all needed + functions to configure the Capture/Compare unit used in Output + compare mode: + (++) Configure each channel, independently, in Output Compare mode + (++) Select the output compare modes + (++) Select the Polarities of each channel + (++) Set/Get the Capture/Compare register values + (++) Select the Output Compare Fast mode + (++) Select the Output Compare Forced mode + (++) Output Compare-Preload Configuration + (++) Clear Output Compare Reference + (++) Select the OCREF Clear signal + (++) Enable/Disable the Capture/Compare Channels + + (#) TIM Input Capture management: this group includes all needed + functions to configure the Capture/Compare unit used in + Input Capture mode: + (++) Configure each channel in input capture mode + (++) Configure Channel1/2 in PWM Input mode + (++) Set the Input Capture Prescaler + (++) Get the Capture/Compare values + + (#) Advanced-control timers (TIM1 and TIM8) specific features + (++) Configures the Break input, dead time, Lock level, the OSSI, + the OSSR State and the AOE(automatic output enable) + (++) Enable/Disable the TIM peripheral Main Outputs + (++) Select the Commutation event + (++) Set/Reset the Capture Compare Preload Control bit + + (#) TIM interrupts, DMA and flags management + (++) Enable/Disable interrupt sources + (++) Get flags status + (++) Clear flags/ Pending bits + (++) Enable/Disable DMA requests + (++) Configure DMA burst mode + (++) Select CaptureCompare DMA request + + (#) TIM clocks management: this group includes all needed functions + to configure the clock controller unit: + (++) Select internal/External clock + (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx + + (#) TIM synchronization management: this group includes all needed + functions to configure the Synchronization unit: + (++) Select Input Trigger + (++) Select Output Trigger + (++) Select Master Slave Mode + (++) ETR Configuration when used as external trigger + + (#) TIM specific interface management, this group includes all + needed functions to use the specific TIM interface: + (++) Encoder Interface Configuration + (++) Select Hall Sensor + + (#) TIM specific remapping management includes the Remapping + configuration of specific timers + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_tim.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_MASK ((uint16_t)0x00FF) +#define CCMR_OFFSET ((uint16_t)0x0018) +#define CCER_CCE_SET ((uint16_t)0x0001) +#define CCER_CCNE_SET ((uint16_t)0x0004) +#define CCMR_OC13M_MASK ((uint16_t)0xFF8F) +#define CCMR_OC24M_MASK ((uint16_t)0x8FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** @defgroup TIM_Group1 TimeBase management functions + * @brief TimeBase management functions + * +@verbatim + =============================================================================== + ##### TimeBase management functions ##### + =============================================================================== + + + ##### TIM Driver: how to use it in Timing(Time base) Mode ##### + =============================================================================== + [..] + To use the Timer in Timing(Time base) mode, the following steps are mandatory: + + (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function + + (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. + + (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit + with the corresponding configuration + + (#) Enable the NVIC if you need to generate the update interrupt. + + (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) + + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + -@- All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval None + + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if (TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if (TIMx == TIM11) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); + } + else if (TIMx == TIM12) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); + } + else if (TIMx == TIM13) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); + } + else + { + if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM8)|| + (TIMx == TIM2) || (TIMx == TIM3)|| + (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter(only for TIM1 and TIM8) value immediatly */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + + tmpcr1 = TIMx->CR1; + + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); + + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval Counter Register value + */ +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Global: Source of update is the counter + * overflow/underflow or the setting of UG bit, or an update + * generation through the slave mode controller. + * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; + } +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); + + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group2 Output Compare management functions + * @brief Output Compare management functions + * +@verbatim + =============================================================================== + ##### Output Compare management functions ##### + =============================================================================== + + + ##### TIM Driver: how to use it in Output Compare Mode ##### + =============================================================================== + [..] + To use the Timer in Output Compare mode, the following steps are mandatory: + + (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) + function + + (#) Configure the TIM pins by configuring the corresponding GPIO pins + + (#) Configure the Time base unit as described in the first part of this driver, + (++) if needed, else the Timer will run with the default configuration: + Autoreload value = 0xFFFF + (++) Prescaler value = 0x0000 + (++) Counter mode = Up counting + (++) Clock Division = TIM_CKD_DIV1 + + (#) Fill the TIM_OCInitStruct with the desired parameters including: + (++) The TIM Output Compare mode: TIM_OCMode + (++) TIM Output State: TIM_OutputState + (++) TIM Pulse value: TIM_Pulse + (++) TIM Output Compare Polarity : TIM_OCPolarity + + (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired + channel with the corresponding configuration + + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + -@- All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + + -@- In case of PWM mode, this function is mandatory: + TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); + + -@- If the corresponding interrupt or DMA request are needed, the user should: + (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). + (+@) Enable the corresponding interrupt (or DMA request) using the function + TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIMx Channel1 according to the specified parameters in + * the TIM_OCInitStruct. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; + tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NE; + + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; + tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NE; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; + tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NE; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; + tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x00000000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. If needed, user has to enable this channel using + * TIM_CCxCmd() and TIM_CCxNCmd() functions. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_OFFSET; + + tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; + + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; + + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; + + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; + + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)(~TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NP; + tmpccer |= TIM_OCNPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)(~TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NP; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC3P; + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NP; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC4P; + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_SET << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_SET << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} +/** + * @} + */ + +/** @defgroup TIM_Group3 Input Capture management functions + * @brief Input Capture management functions + * +@verbatim + =============================================================================== + ##### Input Capture management functions ##### + =============================================================================== + + ##### TIM Driver: how to use it in Input Capture Mode ##### + =============================================================================== + [..] + To use the Timer in Input Capture mode, the following steps are mandatory: + + (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) + function + + (#) Configure the TIM pins by configuring the corresponding GPIO pins + + (#) Configure the Time base unit as described in the first part of this driver, + if needed, else the Timer will run with the default configuration: + (++) Autoreload value = 0xFFFF + (++) Prescaler value = 0x0000 + (++) Counter mode = Up counting + (++) Clock Division = TIM_CKD_DIV1 + + (#) Fill the TIM_ICInitStruct with the desired parameters including: + (++) TIM Channel: TIM_Channel + (++) TIM Input Capture polarity: TIM_ICPolarity + (++) TIM Input Capture selection: TIM_ICSelection + (++) TIM Input Capture Prescaler: TIM_ICPrescaler + (++) TIM Input CApture filter value: TIM_ICFilter + + (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel + with the corresponding configuration and to measure only frequency + or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) + to configure the desired channels with the corresponding configuration + and to measure the frequency and the duty cycle of the input signal + + (#) Enable the NVIC or the DMA to read the measured frequency. + + (#) Enable the corresponding interrupt (or DMA request) to read the Captured + value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) + (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) + + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + (#) Use TIM_GetCapturex(TIMx); to read the captured value. + + -@- All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM peripheral according to the specified parameters + * in the TIM_ICInitStruct. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Configures the TIM peripheral according to the specified parameters + * in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @retval Capture Compare 2 Register value. + */ +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} +/** + * @} + */ + +/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features + * @brief Advanced-control timers (TIM1 and TIM8) specific features + * +@verbatim + =============================================================================== + ##### Advanced-control timers (TIM1 and TIM8) specific features ##### + =============================================================================== + + ##### TIM Driver: how to use the Break feature ##### + =============================================================================== + [..] + After configuring the Timer channel(s) in the appropriate Output Compare mode: + + (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer + Break Polarity, dead time, Lock level, the OSSI/OSSR State and the + AOE(automatic output enable). + + (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer + + (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) + + (#) Once the break even occurs, the Timer's output signals are put in reset + state or in a known state (according to the configuration made in + TIM_BDTRConfig() function). + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group5 Interrupts DMA and flags management functions + * @brief Interrupts, DMA and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts, DMA and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used + * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, + * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. + * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can + * be used: TIM_IT_Update or TIM_IT_CC1 + * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 + * + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * + * @note TIM6 and TIM7 can only generate an update event. + * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag + * + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. + * + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag + * + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note TIM6 and TIM7 can generate only an update interrupt. + * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. + * + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note TIM6 and TIM7 can generate only an update interrupt. + * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR1 + * @arg TIM_DMABase_CR2 + * @arg TIM_DMABase_SMCR + * @arg TIM_DMABase_DIER + * @arg TIM1_DMABase_SR + * @arg TIM_DMABase_EGR + * @arg TIM_DMABase_CCMR1 + * @arg TIM_DMABase_CCMR2 + * @arg TIM_DMABase_CCER + * @arg TIM_DMABase_CNT + * @arg TIM_DMABase_PSC + * @arg TIM_DMABase_ARR + * @arg TIM_DMABase_RCR + * @arg TIM_DMABase_CCR1 + * @arg TIM_DMABase_CCR2 + * @arg TIM_DMABase_CCR3 + * @arg TIM_DMABase_CCR4 + * @arg TIM_DMABase_BDTR + * @arg TIM_DMABase_DCR + * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value + * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group6 Clocks management functions + * @brief Clocks management functions + * +@verbatim + =============================================================================== + ##### Clocks management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_InputTriggerSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter: specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; + + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)~TIM_SMCR_TS; + tmpsmcr |= TIM_TS_ETRF; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} +/** + * @} + */ + +/** @defgroup TIM_Group7 Synchronization management functions + * @brief Synchronization management functions + * +@verbatim + =============================================================================== + ##### Synchronization management functions ##### + =============================================================================== + + ##### TIM Driver: how to use it in synchronization Mode ##### + =============================================================================== + [..] + + *** Case of two/several Timers *** + ================================== + [..] + (#) Configure the Master Timers using the following functions: + (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); + (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); + (#) Configure the Slave Timers using the following functions: + (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); + (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + + *** Case of Timers and external trigger(ETR pin) *** + ==================================================== + [..] + (#) Configure the External trigger using this function: + (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); + (#) Configure the Slave Timers using the following functions: + (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); + (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + +@endverbatim + * @{ + */ + +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)~TIM_SMCR_TS; + + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. + * + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This parameter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs(TRGO) + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize + * the counter and triggers an update of the registers + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; + + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO) + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_MASK; + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @} + */ + +/** @defgroup TIM_Group8 Specific interface management functions + * @brief Specific interface management functions + * +@verbatim + =============================================================================== + ##### Specific interface management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group9 Specific remapping management function + * @brief Specific remapping management function + * +@verbatim + =============================================================================== + ##### Specific remapping management function ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. + * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. + * @param TIM_Remap: specifies the TIM input remapping source. + * This parameter can be one of the following values: + * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) + * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output. + * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. + * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. + * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. + * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. + * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. + * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock + * (HSE divided by a programmable prescaler) + * @retval None + */ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_REMAP(TIM_Remap)); + + /* Set the Timer remapping configuration */ + TIMx->OR = TIM_Remap; +} +/** + * @} + */ + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input and set the filter */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + + /* Select the Input and set the filter */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + + /* Select the Input and set the filter */ + tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + + /* Select the Input and set the filter */ + tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c index 01bdf5fdb..275747875 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c @@ -1,1486 +1,1486 @@ -/** - ****************************************************************************** - * @file stm32f4xx_usart.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Universal synchronous asynchronous receiver - * transmitter (USART): - * + Initialization and Configuration - * + Data transfers - * + Multi-Processor Communication - * + LIN mode - * + Half-duplex mode - * + Smartcard mode - * + IrDA mode - * + DMA transfers management - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable peripheral clock using the following functions - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, - UART4 or UART5. - - (#) According to the USART mode, enable the GPIO clocks using - RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, - or/and SCLK). - - (#) Peripheral's alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function - - (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) using the USART_Init() - function. - - (#) For synchronous mode, enable the clock and program the polarity, - phase and last bit using the USART_ClockInit() function. - - (#) Enable the NVIC and the corresponding interrupt using the function - USART_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using USART_DMACmd() function - - (#) Enable the USART using the USART_Cmd() function. - - (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. - - -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections - for more details - - [..] - In order to reach higher communication baudrates, it is possible to - enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). - This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) - and before calling the function USART_Init(). - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_usart.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ -#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ - USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE)) - -/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ -#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ - USART_CR2_CPHA | USART_CR2_LBCL)) - -/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ -#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) - -/*!< USART Interrupts mask */ -#define IT_MASK ((uint16_t)0x001F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** @defgroup USART_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - (++) Hardware flow control - (++) Receiver/transmitter modes - - [..] - The USART_Init() function follows the USART asynchronous configuration - procedure (details for the procedure are available in reference manual (RM0090)). - - (+) For the synchronous mode in addition to the asynchronous mode parameters these - parameters should be also configured: - (++) USART Clock Enabled - (++) USART polarity - (++) USART phase - (++) USART LastBit - - [..] - These parameters can be configured using the USART_ClockInit() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - else if (USARTx == USART6) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); - } - else if (USARTx == UART7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); - } - else - { - if (USARTx == UART8) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains - * the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - RCC_ClocksTypeDef RCC_ClocksStatus; - - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - - /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ - if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - - /* Clear STOP[13:12] bits */ - tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); - - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : - Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); - - /* Configure the USART Word Length, Parity and mode: - Set the M bits according to USART_WordLength value - Set PCE and PS bits according to USART_Parity value - Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - - /* Clear CTSE and RTSE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); - - /* Configure the USART HFC : - Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate */ - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if ((USARTx == USART1) || (USARTx == USART6)) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - /* Determine the fractional part */ - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - /* Implement the fractional part in the register */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - /* Write to USART BRR register */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_UE; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); - } -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_Prescaler: specifies the prescaler clock. - * @note The function is used for IrDA mode with UART4 and UART5. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= USART_GTPR_GT; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @note This function has to be called before calling USART_Init() function - * in order to have correct baudrate Divider value. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART 8x oversampling mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_OVER8; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_ONEBIT; - } - else - { - /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART data - transfers. - [..] - During an USART reception, data shifts in least significant bit first through - the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) - between the internal bus and the received shift register. - [..] - When a transmission is taking place, a write instruction to the USART_DR register - stores the data in the TDR register and which is copied in the shift register - at the end of the current transmission. - [..] - The read access of the USART_DR register can be done using the USART_ReceiveData() - function and returns the RDR buffered value. Whereas a write access to the USART_DR - can be done using USART_SendData() function and stores the written data into - TDR buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @} - */ - -/** @defgroup USART_Group3 MultiProcessor Communication functions - * @brief Multi-Processor Communication functions - * -@verbatim - =============================================================================== - ##### Multi-Processor Communication functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - multiprocessor communication. - [..] - For instance one of the USARTs can be the master, its TX output is connected - to the RX input of the other USART. The others are slaves, their respective - TX outputs are logically ANDed together and connected to the RX input of the - master. - [..] - USART multiprocessor communication is possible through the following procedure: - (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode - transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - (#) Configures the USART address using the USART_SetAddress() function. - (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) - using USART_WakeUpConfig() function only for the slaves. - (#) Enable the USART using the USART_Cmd() function. - (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. - [..] - The USART Slave exit from mute mode when receive the wake up condition. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the address of the USART node. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_RWU; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); - } -} -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @} - */ - -/** @defgroup USART_Group4 LIN mode functions - * @brief LIN mode functions - * -@verbatim - =============================================================================== - ##### LIN mode functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART LIN - Mode communication. - [..] - In LIN mode, 8-bit data format with 1 stop bit is required in accordance with - the LIN standard. - [..] - Only this LIN Feature is supported by the USART IP: - (+) LIN Master Synchronous Break send capability and LIN slave break detection - capability : 13-bit break generation and 10/11 bit break detection - - [..] - USART LIN Master transmitter communication is possible through the following - procedure: - (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Enable the LIN mode using the USART_LINCmd() function. - (#) Send the break character using USART_SendBreak() function. - [..] - USART LIN Master receiver communication is possible through the following procedure: - (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Configures the break detection length using the USART_LINBreakDetectLengthConfig() - function. - (#) Enable the LIN mode using the USART_LINCmd() function. - - -@- In LIN mode, the following bits must be kept cleared: - (+@) CLKEN in the USART_CR2 register, - (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART's LIN mode. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_LINEN; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); - } -} - -/** - * @brief Transmits break characters. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= USART_CR1_SBK; -} - -/** - * @} - */ - -/** @defgroup USART_Group5 Halfduplex mode function - * @brief Half-duplex mode function - * -@verbatim - =============================================================================== - ##### Half-duplex mode function ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - Half-duplex communication. - [..] - The USART can be configured to follow a single-wire half-duplex protocol where - the TX and RX lines are internally connected. - [..] - USART Half duplex communication is possible through the following procedure: - (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - (#) Configures the USART address using the USART_SetAddress() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Enable the half duplex mode using USART_HalfDuplexCmd() function. - - - -@- The RX pin is no longer used - -@- In Half-duplex mode the following bits must be kept cleared: - (+@) LINEN and CLKEN bits in the USART_CR2 register. - (+@) SCEN and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's Half Duplex communication. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_HDSEL; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); - } -} - -/** - * @} - */ - - -/** @defgroup USART_Group6 Smartcard mode functions - * @brief Smartcard mode functions - * -@verbatim - =============================================================================== - ##### Smartcard mode functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - Smartcard communication. - [..] - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. - [..] - The USART can provide a clock to the smartcard through the SCLK output. - In smartcard mode, SCLK is not associated to the communication but is simply derived - from the internal peripheral input clock through a 5-bit prescaler. - [..] - Smartcard communication is possible through the following procedure: - (#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function. - (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function. - (#) Program the USART clock using the USART_ClockInit() function as following: - (++) USART Clock enabled - (++) USART CPOL Low - (++) USART CPHA on first edge - (++) USART Last Bit Clock Enabled - (#) Program the Smartcard interface using the USART_Init() function as following: - (++) Word Length = 9 Bits - (++) 1.5 Stop Bit - (++) Even parity - (++) BaudRate = 12096 baud - (++) Hardware flow control disabled (RTS and CTS signals) - (++) Tx and Rx enabled - (#) POptionally you can enable the parity error interrupt using the USART_ITConfig() - function - (#) PEnable the USART using the USART_Cmd() function. - (#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function. - (#) PEnable the Smartcard interface using the USART_SmartCardCmd() function. - - Please refer to the ISO 7816-3 specification for more details. - - -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended - to use 1.5 stop bits for both transmitting and receiving to avoid switching - between the two configurations. - -@- In smartcard mode, the following bits must be kept cleared: - (+@) LINEN bit in the USART_CR2 register. - (+@) HDSEL and IREN bits in the USART_CR3 register. - -@- Smartcard mode is available on USART peripherals only (not available on UART4 - and UART5 peripherals). - -@endverbatim - * @{ - */ - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param USART_GuardTime: specifies the guard time. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= USART_GTPR_PSC; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Enables or disables the USART's Smart Card mode. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_SCEN; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_NACK; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group7 IrDA mode functions - * @brief IrDA mode functions - * -@verbatim - =============================================================================== - ##### IrDA mode functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - IrDA communication. - [..] - IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver - is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. - While receiving data, transmission should be avoided as the data to be transmitted - could be corrupted. - [..] - IrDA communication is possible through the following procedure: - (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver - modes and hardware flow control values using the USART_Init() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Configures the IrDA pulse width by configuring the prescaler using - the USART_SetPrescaler() function. - (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode - using the USART_IrDAConfig() function. - (#) Enable the IrDA using the USART_IrDACmd() function. - - -@- A pulse of width less than two and greater than one PSC period(s) may or may - not be rejected. - -@- The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and - reception (IrDA is a half duplex protocol). - -@- In IrDA mode, the following bits must be kept cleared: - (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register. - (+@) SCEN and HDSEL bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_IREN; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group8 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's DMA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup USART_Group9 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to configure the USART - Interrupts sources, DMA channels requests and check or clear the flags or - pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - *** Polling Mode *** - ==================== - [..] - In Polling Mode, the SPI communication can be managed by 10 flags: - (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register - (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register - (#) USART_FLAG_TC : to indicate the status of the transmit operation - (#) USART_FLAG_IDLE : to indicate the status of the Idle Line - (#) USART_FLAG_CTS : to indicate the status of the nCTS input - (#) USART_FLAG_LBD : to indicate the status of the LIN break detection - (#) USART_FLAG_NE : to indicate if a noise error occur - (#) USART_FLAG_FE : to indicate if a frame error occur - (#) USART_FLAG_PE : to indicate if a parity error occur - (#) USART_FLAG_ORE : to indicate if an Overrun error occur - [..] - In this Mode it is advised to use the following functions: - (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); - (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - *** Interrupt Mode *** - ====================== - [..] - In Interrupt Mode, the USART communication can be managed by 8 interrupt sources - and 10 pending bits: - - (#) Pending Bits: - - (##) USART_IT_TXE : to indicate the status of the transmit buffer register - (##) USART_IT_RXNE : to indicate the status of the receive buffer register - (##) USART_IT_TC : to indicate the status of the transmit operation - (##) USART_IT_IDLE : to indicate the status of the Idle Line - (##) USART_IT_CTS : to indicate the status of the nCTS input - (##) USART_IT_LBD : to indicate the status of the LIN break detection - (##) USART_IT_NE : to indicate if a noise error occur - (##) USART_IT_FE : to indicate if a frame error occur - (##) USART_IT_PE : to indicate if a parity error occur - (##) USART_IT_ORE : to indicate if an Overrun error occur - - (#) Interrupt Source: - - (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty - interrupt. - (##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - (##) USART_IT_TC : specifies the interrupt source for the Transmit complete - interrupt. - (##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. - (##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt. - (##) USART_IT_LBD : specifies the interrupt source for the LIN break detection - interrupt. - (##) USART_IT_PE : specifies the interrupt source for the parity error interrupt. - (##) USART_IT_ERR : specifies the interrupt source for the errors interrupt. - - -@@- Some parameters are coded in order to use them as interrupt source - or as pending bits. - [..] - In this Mode it is advised to use the following functions: - (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); - (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); - (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - - *** DMA Mode *** - ================ - [..] - In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: - (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request - (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request - [..] - In this Mode it is advised to use the following function: - (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_MASK; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if (USART_FLAG == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * @note RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * @note TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set - * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_MASK; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * @note RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * @note TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_usart.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Universal synchronous asynchronous receiver + * transmitter (USART): + * + Initialization and Configuration + * + Data transfers + * + Multi-Processor Communication + * + LIN mode + * + Half-duplex mode + * + Smartcard mode + * + IrDA mode + * + DMA transfers management + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable peripheral clock using the following functions + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, + UART4 or UART5. + + (#) According to the USART mode, enable the GPIO clocks using + RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, + or/and SCLK). + + (#) Peripheral's alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function + + (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) using the USART_Init() + function. + + (#) For synchronous mode, enable the clock and program the polarity, + phase and last bit using the USART_ClockInit() function. + + (#) Enable the NVIC and the corresponding interrupt using the function + USART_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function + (++) Active the needed channel Request using USART_DMACmd() function + + (#) Enable the USART using the USART_Cmd() function. + + (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. + + -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections + for more details + + [..] + In order to reach higher communication baudrates, it is possible to + enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). + This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) + and before calling the function USART_Init(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_usart.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ +#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ + USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE)) + +/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ +#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) + +/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ +#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) + +/*!< USART Interrupts mask */ +#define IT_MASK ((uint16_t)0x001F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** @defgroup USART_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in asynchronous and in synchronous modes. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + (++) Hardware flow control + (++) Receiver/transmitter modes + + [..] + The USART_Init() function follows the USART asynchronous configuration + procedure (details for the procedure are available in reference manual (RM0090)). + + (+) For the synchronous mode in addition to the asynchronous mode parameters these + parameters should be also configured: + (++) USART Clock Enabled + (++) USART polarity + (++) USART phase + (++) USART LastBit + + [..] + These parameters can be configured using the USART_ClockInit() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else if (USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + else if (USARTx == USART6) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); + } + else if (USARTx == UART7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); + } + else + { + if (USARTx == UART8) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains + * the configuration information for the specified USART peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + + /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ + if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + + /* Clear STOP[13:12] bits */ + tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); + + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : + Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); + + /* Configure the USART Word Length, Parity and mode: + Set the M bits according to USART_WordLength value + Set PCE and PS bits according to USART_Parity value + Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + + /* Write to USART CR1 */ + USARTx->CR1 = (uint16_t)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + + /* Clear CTSE and RTSE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); + + /* Configure the USART HFC : + Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + + /* Write to USART CR3 */ + USARTx->CR3 = (uint16_t)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate */ + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if ((USARTx == USART1) || (USARTx == USART6)) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + /* Write to USART BRR register */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that + * contains the configuration information for the specified USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_UE; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); + } +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_Prescaler: specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= USART_GTPR_GT; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @note This function has to be called before calling USART_Init() function + * in order to have correct baudrate Divider value. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART 8x oversampling mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_OVER8; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); + } +} + +/** + * @brief Enables or disables the USART's one bit sampling method. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_ONEBIT; + } + else + { + /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART data + transfers. + [..] + During an USART reception, data shifts in least significant bit first through + the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) + between the internal bus and the received shift register. + [..] + When a transmission is taking place, a write instruction to the USART_DR register + stores the data in the TDR register and which is copied in the shift register + at the end of the current transmission. + [..] + The read access of the USART_DR register can be done using the USART_ReceiveData() + function and returns the RDR buffered value. Whereas a write access to the USART_DR + can be done using USART_SendData() function and stores the written data into + TDR buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +} + +/** + * @} + */ + +/** @defgroup USART_Group3 MultiProcessor Communication functions + * @brief Multi-Processor Communication functions + * +@verbatim + =============================================================================== + ##### Multi-Processor Communication functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART + multiprocessor communication. + [..] + For instance one of the USARTs can be the master, its TX output is connected + to the RX input of the other USART. The others are slaves, their respective + TX outputs are logically ANDed together and connected to the RX input of the + master. + [..] + USART multiprocessor communication is possible through the following procedure: + (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode + transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + (#) Configures the USART address using the USART_SetAddress() function. + (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) + using USART_WakeUpConfig() function only for the slaves. + (#) Enable the USART using the USART_Cmd() function. + (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. + [..] + The USART Slave exit from mute mode when receive the wake up condition. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the address of the USART node. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_RWU; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); + } +} +/** + * @brief Selects the USART WakeUp method. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @} + */ + +/** @defgroup USART_Group4 LIN mode functions + * @brief LIN mode functions + * +@verbatim + =============================================================================== + ##### LIN mode functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART LIN + Mode communication. + [..] + In LIN mode, 8-bit data format with 1 stop bit is required in accordance with + the LIN standard. + [..] + Only this LIN Feature is supported by the USART IP: + (+) LIN Master Synchronous Break send capability and LIN slave break detection + capability : 13-bit break generation and 10/11 bit break detection + + [..] + USART LIN Master transmitter communication is possible through the following + procedure: + (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Enable the LIN mode using the USART_LINCmd() function. + (#) Send the break character using USART_SendBreak() function. + [..] + USART LIN Master receiver communication is possible through the following procedure: + (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Configures the break detection length using the USART_LINBreakDetectLengthConfig() + function. + (#) Enable the LIN mode using the USART_LINCmd() function. + + -@- In LIN mode, the following bits must be kept cleared: + (+@) CLKEN in the USART_CR2 register, + (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART's LIN mode. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= USART_CR2_LINEN; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); + } +} + +/** + * @brief Transmits break characters. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= USART_CR1_SBK; +} + +/** + * @} + */ + +/** @defgroup USART_Group5 Halfduplex mode function + * @brief Half-duplex mode function + * +@verbatim + =============================================================================== + ##### Half-duplex mode function ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART + Half-duplex communication. + [..] + The USART can be configured to follow a single-wire half-duplex protocol where + the TX and RX lines are internally connected. + [..] + USART Half duplex communication is possible through the following procedure: + (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter + or Mode receiver and hardware flow control values using the USART_Init() + function. + (#) Configures the USART address using the USART_SetAddress() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Enable the half duplex mode using USART_HalfDuplexCmd() function. + + + -@- The RX pin is no longer used + -@- In Half-duplex mode the following bits must be kept cleared: + (+@) LINEN and CLKEN bits in the USART_CR2 register. + (+@) SCEN and IREN bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's Half Duplex communication. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_HDSEL; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); + } +} + +/** + * @} + */ + + +/** @defgroup USART_Group6 Smartcard mode functions + * @brief Smartcard mode functions + * +@verbatim + =============================================================================== + ##### Smartcard mode functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART + Smartcard communication. + [..] + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. + [..] + The USART can provide a clock to the smartcard through the SCLK output. + In smartcard mode, SCLK is not associated to the communication but is simply derived + from the internal peripheral input clock through a 5-bit prescaler. + [..] + Smartcard communication is possible through the following procedure: + (#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function. + (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function. + (#) Program the USART clock using the USART_ClockInit() function as following: + (++) USART Clock enabled + (++) USART CPOL Low + (++) USART CPHA on first edge + (++) USART Last Bit Clock Enabled + (#) Program the Smartcard interface using the USART_Init() function as following: + (++) Word Length = 9 Bits + (++) 1.5 Stop Bit + (++) Even parity + (++) BaudRate = 12096 baud + (++) Hardware flow control disabled (RTS and CTS signals) + (++) Tx and Rx enabled + (#) POptionally you can enable the parity error interrupt using the USART_ITConfig() + function + (#) PEnable the USART using the USART_Cmd() function. + (#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function. + (#) PEnable the Smartcard interface using the USART_SmartCardCmd() function. + + Please refer to the ISO 7816-3 specification for more details. + + -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended + to use 1.5 stop bits for both transmitting and receiving to avoid switching + between the two configurations. + -@- In smartcard mode, the following bits must be kept cleared: + (+@) LINEN bit in the USART_CR2 register. + (+@) HDSEL and IREN bits in the USART_CR3 register. + -@- Smartcard mode is available on USART peripherals only (not available on UART4 + and UART5 peripherals). + +@endverbatim + * @{ + */ + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= USART_GTPR_PSC; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Enables or disables the USART's Smart Card mode. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_SCEN; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_NACK; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group7 IrDA mode functions + * @brief IrDA mode functions + * +@verbatim + =============================================================================== + ##### IrDA mode functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART + IrDA communication. + [..] + IrDA is a half duplex communication protocol. If the Transmitter is busy, any data + on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver + is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. + While receiving data, transmission should be avoided as the data to be transmitted + could be corrupted. + [..] + IrDA communication is possible through the following procedure: + (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver + modes and hardware flow control values using the USART_Init() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Configures the IrDA pulse width by configuring the prescaler using + the USART_SetPrescaler() function. + (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode + using the USART_IrDAConfig() function. + (#) Enable the IrDA using the USART_IrDACmd() function. + + -@- A pulse of width less than two and greater than one PSC period(s) may or may + not be rejected. + -@- The receiver set up time should be managed by software. The IrDA physical layer + specification specifies a minimum of 10 ms delay between transmission and + reception (IrDA is a half duplex protocol). + -@- In IrDA mode, the following bits must be kept cleared: + (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register. + (+@) SCEN and HDSEL bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_IREN; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group8 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's DMA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @} + */ + +/** @defgroup USART_Group9 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to configure the USART + Interrupts sources, DMA channels requests and check or clear the flags or + pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + *** Polling Mode *** + ==================== + [..] + In Polling Mode, the SPI communication can be managed by 10 flags: + (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register + (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register + (#) USART_FLAG_TC : to indicate the status of the transmit operation + (#) USART_FLAG_IDLE : to indicate the status of the Idle Line + (#) USART_FLAG_CTS : to indicate the status of the nCTS input + (#) USART_FLAG_LBD : to indicate the status of the LIN break detection + (#) USART_FLAG_NE : to indicate if a noise error occur + (#) USART_FLAG_FE : to indicate if a frame error occur + (#) USART_FLAG_PE : to indicate if a parity error occur + (#) USART_FLAG_ORE : to indicate if an Overrun error occur + [..] + In this Mode it is advised to use the following functions: + (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); + (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); + + *** Interrupt Mode *** + ====================== + [..] + In Interrupt Mode, the USART communication can be managed by 8 interrupt sources + and 10 pending bits: + + (#) Pending Bits: + + (##) USART_IT_TXE : to indicate the status of the transmit buffer register + (##) USART_IT_RXNE : to indicate the status of the receive buffer register + (##) USART_IT_TC : to indicate the status of the transmit operation + (##) USART_IT_IDLE : to indicate the status of the Idle Line + (##) USART_IT_CTS : to indicate the status of the nCTS input + (##) USART_IT_LBD : to indicate the status of the LIN break detection + (##) USART_IT_NE : to indicate if a noise error occur + (##) USART_IT_FE : to indicate if a frame error occur + (##) USART_IT_PE : to indicate if a parity error occur + (##) USART_IT_ORE : to indicate if an Overrun error occur + + (#) Interrupt Source: + + (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty + interrupt. + (##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + (##) USART_IT_TC : specifies the interrupt source for the Transmit complete + interrupt. + (##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. + (##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt. + (##) USART_IT_LBD : specifies the interrupt source for the LIN break detection + interrupt. + (##) USART_IT_PE : specifies the interrupt source for the parity error interrupt. + (##) USART_IT_ERR : specifies the interrupt source for the errors interrupt. + + -@@- Some parameters are coded in order to use them as interrupt source + or as pending bits. + [..] + In this Mode it is advised to use the following functions: + (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); + (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); + (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + + *** DMA Mode *** + ================ + [..] + In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: + (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request + (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request + [..] + In this Mode it is advised to use the following function: + (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_MASK; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + + /* The CTS flag is not available for UART4 and UART5 */ + if (USART_FLAG == USART_FLAG_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * @note RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * @note TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + * + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + + /* The CTS flag is not available for UART4 and UART5 */ + if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + USARTx->SR = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set + * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_IT & IT_MASK; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->SR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetITStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * @note RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * @note TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * @note TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + * + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->SR = (uint16_t)~itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c index 8e88af160..5ddbee869 100644 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c +++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c @@ -1,307 +1,307 @@ -/** - ****************************************************************************** - * @file stm32f4xx_wwdg.c - * @author MCD Application Team - * @version V1.4.0 - * @date 04-August-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Window watchdog (WWDG) peripheral: - * + Prescaler, Refresh window and Counter configuration - * + WWDG activation - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### WWDG features ##### - =============================================================================== - [..] - Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the counter (downcounter) - before to reach 0x3F value (i.e. a reset is generated when the counter - value rolls over from 0x40 to 0x3F). - An MCU reset is also generated if the counter value is refreshed - before the counter has reached the refresh window value. This - implies that the counter must be refreshed in a limited window. - - Once enabled the WWDG cannot be disabled except by a system reset. - - WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - reset occurs. - - The WWDG counter input clock is derived from the APB clock divided - by a programmable prescaler. - - WWDG counter clock = PCLK1 / Prescaler - WWDG timeout = (WWDG counter clock) * (counter value) - - Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms - - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function - - (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function - - (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function - - (#) Set the WWDG counter value and start it using WWDG_Enable() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - - (#) Optionally you can enable the Early wakeup interrupt which is - generated when the counter reach 0x40. - Once enabled this interrupt cannot be disabled except by a system reset. - - (#) Then the application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - WWDG_SetCounter() function. This operation must occur only when - the counter value is lower than the refresh window value, - programmed using WWDG_SetWindowValue(). - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_wwdg.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ----------- WWDG registers bit address in the alias region ----------- */ -#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) -/* Alias word address of EWI bit */ -#define CFR_OFFSET (WWDG_OFFSET + 0x04) -#define EWI_BitNumber 0x09 -#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) - -/* --------------------- WWDG registers bit mask ------------------------ */ -/* CFR register bit mask */ -#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) -#define CFR_W_MASK ((uint32_t)0xFFFFFF80) -#define BIT_MASK ((uint8_t)0x7F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions - * @brief Prescaler, Refresh window and Counter configuration functions - * -@verbatim - =============================================================================== - ##### Prescaler, Refresh window and Counter configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_MASK; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_MASK; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_MASK; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_MASK; -} -/** - * @} - */ - -/** @defgroup WWDG_Group2 WWDG activation functions - * @brief WWDG activation functions - * -@verbatim - =============================================================================== - ##### WWDG activation function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = WWDG_CR_WDGA | Counter; -} -/** - * @} - */ - -/** @defgroup WWDG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((WWDG->SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_wwdg.c + * @author MCD Application Team + * @version V1.4.0 + * @date 04-August-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Window watchdog (WWDG) peripheral: + * + Prescaler, Refresh window and Counter configuration + * + WWDG activation + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### WWDG features ##### + =============================================================================== + [..] + Once enabled the WWDG generates a system reset on expiry of a programmed + time period, unless the program refreshes the counter (downcounter) + before to reach 0x3F value (i.e. a reset is generated when the counter + value rolls over from 0x40 to 0x3F). + An MCU reset is also generated if the counter value is refreshed + before the counter has reached the refresh window value. This + implies that the counter must be refreshed in a limited window. + + Once enabled the WWDG cannot be disabled except by a system reset. + + WWDGRST flag in RCC_CSR register can be used to inform when a WWDG + reset occurs. + + The WWDG counter input clock is derived from the APB clock divided + by a programmable prescaler. + + WWDG counter clock = PCLK1 / Prescaler + WWDG timeout = (WWDG counter clock) * (counter value) + + Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms + + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function + + (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function + + (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function + + (#) Set the WWDG counter value and start it using WWDG_Enable() function. + When the WWDG is enabled the counter value should be configured to + a value greater than 0x40 to prevent generating an immediate reset. + + (#) Optionally you can enable the Early wakeup interrupt which is + generated when the counter reach 0x40. + Once enabled this interrupt cannot be disabled except by a system reset. + + (#) Then the application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + WWDG_SetCounter() function. This operation must occur only when + the counter value is lower than the refresh window value, + programmed using WWDG_SetWindowValue(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_wwdg.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ +/* CFR register bit mask */ +#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) +#define CFR_W_MASK ((uint32_t)0xFFFFFF80) +#define BIT_MASK ((uint8_t)0x7F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions + * @brief Prescaler, Refresh window and Counter configuration functions + * +@verbatim + =============================================================================== + ##### Prescaler, Refresh window and Counter configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_MASK; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_MASK; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_MASK; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @note Once enabled this interrupt cannot be disabled except by a system reset. + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent generating + * an immediate reset) + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_MASK; +} +/** + * @} + */ + +/** @defgroup WWDG_Group2 WWDG activation functions + * @brief WWDG activation functions + * +@verbatim + =============================================================================== + ##### WWDG activation function ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent generating + * an immediate reset) + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = WWDG_CR_WDGA | Counter; +} +/** + * @} + */ + +/** @defgroup WWDG_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((WWDG->SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h index 9dc72f7c6..84ce57bb2 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h @@ -1,164 +1,164 @@ -/** - ****************************************************************************** - * @file usbd_audio_core.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header file for the usbd_audio_core.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_AUDIO_CORE_H_ -#define __USB_AUDIO_CORE_H_ - -#include "usbd_ioreq.h" -#include "usbd_req.h" -#include "usbd_desc.h" - - - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_audio - * @brief This file is the Header file for USBD_audio.c - * @{ - */ - - -/** @defgroup usbd_audio_Exported_Defines - * @{ - */ - -/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 2) */ -#define AUDIO_OUT_PACKET (uint32_t)(((USBD_AUDIO_FREQ * 2 * 2) /1000)) - -/* Number of sub-packets in the audio transfer buffer. You can modify this value but always make sure - that it is an even number and higher than 3 */ -#define OUT_PACKET_NUM 4 -/* Total size of the audio transfer buffer */ -#define TOTAL_OUT_BUF_SIZE ((uint32_t)(AUDIO_OUT_PACKET * OUT_PACKET_NUM)) - -#define AUDIO_CONFIG_DESC_SIZE 109 -#define AUDIO_INTERFACE_DESC_SIZE 9 -#define USB_AUDIO_DESC_SIZ 0x09 -#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09 -#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07 - -#define AUDIO_DESCRIPTOR_TYPE 0x21 -#define USB_DEVICE_CLASS_AUDIO 0x01 -#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01 -#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02 -#define AUDIO_PROTOCOL_UNDEFINED 0x00 -#define AUDIO_STREAMING_GENERAL 0x01 -#define AUDIO_STREAMING_FORMAT_TYPE 0x02 - -/* Audio Descriptor Types */ -#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24 -#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25 - -/* Audio Control Interface Descriptor Subtypes */ -#define AUDIO_CONTROL_HEADER 0x01 -#define AUDIO_CONTROL_INPUT_TERMINAL 0x02 -#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03 -#define AUDIO_CONTROL_FEATURE_UNIT 0x06 - -#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C -#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09 -#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07 - -#define AUDIO_CONTROL_MUTE 0x0001 - -#define AUDIO_FORMAT_TYPE_I 0x01 -#define AUDIO_FORMAT_TYPE_III 0x03 - -#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 -#define AUDIO_ENDPOINT_GENERAL 0x01 - -#define AUDIO_REQ_GET_CUR 0x81 -#define AUDIO_REQ_SET_CUR 0x01 - -#define AUDIO_OUT_STREAMING_CTRL 0x02 - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ -typedef struct _Audio_Fops -{ - uint8_t (*Init) (uint32_t AudioFreq, uint32_t Volume, uint32_t options); - uint8_t (*DeInit) (uint32_t options); - uint8_t (*AudioCmd) (uint8_t* pbuf, uint32_t size, uint8_t cmd); - uint8_t (*VolumeCtl) (uint8_t vol); - uint8_t (*MuteCtl) (uint8_t cmd); - uint8_t (*PeriodicTC) (uint8_t cmd); - uint8_t (*GetState) (void); -}AUDIO_FOPS_TypeDef; -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ -#define AUDIO_PACKET_SZE(frq) (uint8_t)(((frq * 2 * 2)/1000) & 0xFF), \ - (uint8_t)((((frq * 2 * 2)/1000) >> 8) & 0xFF) -#define SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16)) -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_Class_cb_TypeDef AUDIO_cb; - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -/** - * @} - */ - -#endif /* __USB_AUDIO_CORE_H_ */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_audio_core.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header file for the usbd_audio_core.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +#ifndef __USB_AUDIO_CORE_H_ +#define __USB_AUDIO_CORE_H_ + +#include "usbd_ioreq.h" +#include "usbd_req.h" +#include "usbd_desc.h" + + + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup usbd_audio + * @brief This file is the Header file for USBD_audio.c + * @{ + */ + + +/** @defgroup usbd_audio_Exported_Defines + * @{ + */ + +/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 2) */ +#define AUDIO_OUT_PACKET (uint32_t)(((USBD_AUDIO_FREQ * 2 * 2) /1000)) + +/* Number of sub-packets in the audio transfer buffer. You can modify this value but always make sure + that it is an even number and higher than 3 */ +#define OUT_PACKET_NUM 4 +/* Total size of the audio transfer buffer */ +#define TOTAL_OUT_BUF_SIZE ((uint32_t)(AUDIO_OUT_PACKET * OUT_PACKET_NUM)) + +#define AUDIO_CONFIG_DESC_SIZE 109 +#define AUDIO_INTERFACE_DESC_SIZE 9 +#define USB_AUDIO_DESC_SIZ 0x09 +#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09 +#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07 + +#define AUDIO_DESCRIPTOR_TYPE 0x21 +#define USB_DEVICE_CLASS_AUDIO 0x01 +#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01 +#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02 +#define AUDIO_PROTOCOL_UNDEFINED 0x00 +#define AUDIO_STREAMING_GENERAL 0x01 +#define AUDIO_STREAMING_FORMAT_TYPE 0x02 + +/* Audio Descriptor Types */ +#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24 +#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25 + +/* Audio Control Interface Descriptor Subtypes */ +#define AUDIO_CONTROL_HEADER 0x01 +#define AUDIO_CONTROL_INPUT_TERMINAL 0x02 +#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03 +#define AUDIO_CONTROL_FEATURE_UNIT 0x06 + +#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C +#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09 +#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07 + +#define AUDIO_CONTROL_MUTE 0x0001 + +#define AUDIO_FORMAT_TYPE_I 0x01 +#define AUDIO_FORMAT_TYPE_III 0x03 + +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 +#define AUDIO_ENDPOINT_GENERAL 0x01 + +#define AUDIO_REQ_GET_CUR 0x81 +#define AUDIO_REQ_SET_CUR 0x01 + +#define AUDIO_OUT_STREAMING_CTRL 0x02 + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ +typedef struct _Audio_Fops +{ + uint8_t (*Init) (uint32_t AudioFreq, uint32_t Volume, uint32_t options); + uint8_t (*DeInit) (uint32_t options); + uint8_t (*AudioCmd) (uint8_t* pbuf, uint32_t size, uint8_t cmd); + uint8_t (*VolumeCtl) (uint8_t vol); + uint8_t (*MuteCtl) (uint8_t cmd); + uint8_t (*PeriodicTC) (uint8_t cmd); + uint8_t (*GetState) (void); +}AUDIO_FOPS_TypeDef; +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ +#define AUDIO_PACKET_SZE(frq) (uint8_t)(((frq * 2 * 2)/1000) & 0xFF), \ + (uint8_t)((((frq * 2 * 2)/1000) >> 8) & 0xFF) +#define SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16)) +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_Class_cb_TypeDef AUDIO_cb; + +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +/** + * @} + */ + +#endif /* __USB_AUDIO_CORE_H_ */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_out_if.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_out_if.h index 1f7abdc84..4f82cac3e 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_out_if.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_out_if.h @@ -1,125 +1,125 @@ -/** - ****************************************************************************** - * @file usbd_audio_out_if.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header file for the usbd_audio_out_if.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_AUDIO_OUT_IF_H_ -#define __USB_AUDIO_OUT_IF_H_ - -#ifdef STM32F2XX - #include "stm322xg_usb_audio_codec.h" -#elif defined(STM32F4XX) - #include "stm324xg_usb_audio_codec.h" -#elif defined(STM32F10X_CL) - #include "stm3210c_usb_audio_codec.h" -#endif /* STM32F2XX */ - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_audio - * @brief This file is the Header file for USBD_audio.c - * @{ - */ - - -/** @defgroup usbd_audio_Exported_Defines - * @{ - */ -/* Audio Commands enumeration */ -typedef enum -{ - AUDIO_CMD_PLAY = 1, - AUDIO_CMD_PAUSE, - AUDIO_CMD_STOP, -}AUDIO_CMD_TypeDef; - -/* Mute commands */ -#define AUDIO_MUTE 0x01 -#define AUDIO_UNMUTE 0x00 - -/* Functions return value */ -#define AUDIO_OK 0x00 -#define AUDIO_FAIL 0xFF - -/* Audio Machine States */ -#define AUDIO_STATE_INACTIVE 0x00 -#define AUDIO_STATE_ACTIVE 0x01 -#define AUDIO_STATE_PLAYING 0x02 -#define AUDIO_STATE_PAUSED 0x03 -#define AUDIO_STATE_STOPPED 0x04 -#define AUDIO_STATE_ERROR 0x05 - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern AUDIO_FOPS_TypeDef AUDIO_OUT_fops; - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -/** - * @} - */ - -#endif /* __USB_AUDIO_OUT_IF_H_ */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_audio_out_if.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header file for the usbd_audio_out_if.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +#ifndef __USB_AUDIO_OUT_IF_H_ +#define __USB_AUDIO_OUT_IF_H_ + +#ifdef STM32F2XX + #include "stm322xg_usb_audio_codec.h" +#elif defined(STM32F4XX) + #include "stm324xg_usb_audio_codec.h" +#elif defined(STM32F10X_CL) + #include "stm3210c_usb_audio_codec.h" +#endif /* STM32F2XX */ + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup usbd_audio + * @brief This file is the Header file for USBD_audio.c + * @{ + */ + + +/** @defgroup usbd_audio_Exported_Defines + * @{ + */ +/* Audio Commands enumeration */ +typedef enum +{ + AUDIO_CMD_PLAY = 1, + AUDIO_CMD_PAUSE, + AUDIO_CMD_STOP, +}AUDIO_CMD_TypeDef; + +/* Mute commands */ +#define AUDIO_MUTE 0x01 +#define AUDIO_UNMUTE 0x00 + +/* Functions return value */ +#define AUDIO_OK 0x00 +#define AUDIO_FAIL 0xFF + +/* Audio Machine States */ +#define AUDIO_STATE_INACTIVE 0x00 +#define AUDIO_STATE_ACTIVE 0x01 +#define AUDIO_STATE_PLAYING 0x02 +#define AUDIO_STATE_PAUSED 0x03 +#define AUDIO_STATE_STOPPED 0x04 +#define AUDIO_STATE_ERROR 0x05 + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern AUDIO_FOPS_TypeDef AUDIO_OUT_fops; + +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +/** + * @} + */ + +#endif /* __USB_AUDIO_OUT_IF_H_ */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/src/usbd_audio_core.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/src/usbd_audio_core.c index 520bab539..1a6769628 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/src/usbd_audio_core.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/src/usbd_audio_core.c @@ -1,673 +1,673 @@ -/** - ****************************************************************************** - * @file usbd_audio_core.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides the high layer firmware functions to manage the - * following functionalities of the USB Audio Class: - * - Initialization and Configuration of high and low layer - * - Enumeration as Audio Streaming Device - * - Audio Streaming data transfer - * - AudioControl requests management - * - Error management - * - * @verbatim - * - * =================================================================== - * Audio Class Driver Description - * =================================================================== - * This driver manages the Audio Class 1.0 following the "USB Device Class Definition for - * Audio Devices V1.0 Mar 18, 98". - * This driver implements the following aspects of the specification: - * - Device descriptor management - * - Configuration descriptor management - * - Standard AC Interface Descriptor management - * - 1 Audio Streaming Interface (with single channel, PCM, Stereo mode) - * - 1 Audio Streaming Endpoint - * - 1 Audio Terminal Input (1 channel) - * - Audio Class-Specific AC Interfaces - * - Audio Class-Specific AS Interfaces - * - AudioControl Requests: only SET_CUR and GET_CUR requests are supported (for Mute) - * - Audio Feature Unit (limited to Mute control) - * - Audio Synchronization type: Asynchronous - * - Single fixed audio sampling rate (configurable in usbd_conf.h file) - * - * @note - * The Audio Class 1.0 is based on USB Specification 1.0 and thus supports only - * Low and Full speed modes and does not allow High Speed transfers. - * Please refer to "USB Device Class Definition for Audio Devices V1.0 Mar 18, 98" - * for more details. - * - * These aspects may be enriched or modified for a specific user application. - * - * This driver doesn't implement the following aspects of the specification - * (but it is possible to manage these features with some modifications on this driver): - * - AudioControl Endpoint management - * - AudioControl requests other than SET_CUR and GET_CUR - * - Abstraction layer for AudioControl requests (only Mute functionality is managed) - * - Audio Synchronization type: Adaptive - * - Audio Compression modules and interfaces - * - MIDI interfaces and modules - * - Mixer/Selector/Processing/Extension Units (Feature unit is limited to Mute control) - * - Any other application-specific modules - * - Multiple and Variable audio sampling rates - * - Out Streaming Endpoint/Interface (microphone) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#include "usbd_audio_core.h" -#include "usbd_audio_out_if.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup usbd_audio - * @brief usbd core module - * @{ - */ - -/** @defgroup usbd_audio_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_Private_FunctionPrototypes - * @{ - */ - -/********************************************* - AUDIO Device library callbacks - *********************************************/ -static uint8_t usbd_audio_Init (void *pdev, uint8_t cfgidx); -static uint8_t usbd_audio_DeInit (void *pdev, uint8_t cfgidx); -static uint8_t usbd_audio_Setup (void *pdev, USB_SETUP_REQ *req); -static uint8_t usbd_audio_EP0_RxReady(void *pdev); -static uint8_t usbd_audio_DataIn (void *pdev, uint8_t epnum); -static uint8_t usbd_audio_DataOut (void *pdev, uint8_t epnum); -static uint8_t usbd_audio_SOF (void *pdev); -static uint8_t usbd_audio_OUT_Incplt (void *pdev); - -/********************************************* - AUDIO Requests management functions - *********************************************/ -static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req); -static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req); -static uint8_t *USBD_audio_GetCfgDesc (uint8_t speed, uint16_t *length); -/** - * @} - */ - -/** @defgroup usbd_audio_Private_Variables - * @{ - */ -/* Main Buffer for Audio Data Out transfers and its relative pointers */ -uint8_t IsocOutBuff [TOTAL_OUT_BUF_SIZE * 2]; -uint8_t* IsocOutWrPtr = IsocOutBuff; -uint8_t* IsocOutRdPtr = IsocOutBuff; - -/* Main Buffer for Audio Control Requests transfers and its relative variables */ -uint8_t AudioCtl[64]; -uint8_t AudioCtlCmd = 0; -uint32_t AudioCtlLen = 0; -uint8_t AudioCtlUnit = 0; - -static uint32_t PlayFlag = 0; - -static __IO uint32_t usbd_audio_AltSet = 0; -static uint8_t usbd_audio_CfgDesc[AUDIO_CONFIG_DESC_SIZE]; - -/* AUDIO interface class callbacks structure */ -USBD_Class_cb_TypeDef AUDIO_cb = -{ - usbd_audio_Init, - usbd_audio_DeInit, - usbd_audio_Setup, - NULL, /* EP0_TxSent */ - usbd_audio_EP0_RxReady, - usbd_audio_DataIn, - usbd_audio_DataOut, - usbd_audio_SOF, - NULL, - usbd_audio_OUT_Incplt, - USBD_audio_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_audio_GetCfgDesc, /* use same config as per FS */ -#endif -}; - -/* USB AUDIO device Configuration Descriptor */ -static uint8_t usbd_audio_CfgDesc[AUDIO_CONFIG_DESC_SIZE] = -{ - /* Configuration 1 */ - 0x09, /* bLength */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */ - LOBYTE(AUDIO_CONFIG_DESC_SIZE), /* wTotalLength 109 bytes*/ - HIBYTE(AUDIO_CONFIG_DESC_SIZE), - 0x02, /* bNumInterfaces */ - 0x01, /* bConfigurationValue */ - 0x00, /* iConfiguration */ - 0xC0, /* bmAttributes BUS Powred*/ - 0x32, /* bMaxPower = 100 mA*/ - /* 09 byte*/ - - /* USB Speaker Standard interface descriptor */ - AUDIO_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - 0x00, /* bInterfaceNumber */ - 0x00, /* bAlternateSetting */ - 0x00, /* bNumEndpoints */ - USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ - AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */ - AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ - 0x00, /* iInterface */ - /* 09 byte*/ - - /* USB Speaker Class-specific AC Interface Descriptor */ - AUDIO_INTERFACE_DESC_SIZE, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */ - 0x00, /* 1.00 */ /* bcdADC */ - 0x01, - 0x27, /* wTotalLength = 39*/ - 0x00, - 0x01, /* bInCollection */ - 0x01, /* baInterfaceNr */ - /* 09 byte*/ - - /* USB Speaker Input Terminal Descriptor */ - AUDIO_INPUT_TERMINAL_DESC_SIZE, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */ - 0x01, /* bTerminalID */ - 0x01, /* wTerminalType AUDIO_TERMINAL_USB_STREAMING 0x0101 */ - 0x01, - 0x00, /* bAssocTerminal */ - 0x01, /* bNrChannels */ - 0x00, /* wChannelConfig 0x0000 Mono */ - 0x00, - 0x00, /* iChannelNames */ - 0x00, /* iTerminal */ - /* 12 byte*/ - - /* USB Speaker Audio Feature Unit Descriptor */ - 0x09, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */ - AUDIO_OUT_STREAMING_CTRL, /* bUnitID */ - 0x01, /* bSourceID */ - 0x01, /* bControlSize */ - AUDIO_CONTROL_MUTE, /* bmaControls(0) */ - 0x00, /* bmaControls(1) */ - 0x00, /* iTerminal */ - /* 09 byte*/ - - /*USB Speaker Output Terminal Descriptor */ - 0x09, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */ - 0x03, /* bTerminalID */ - 0x01, /* wTerminalType 0x0301*/ - 0x03, - 0x00, /* bAssocTerminal */ - 0x02, /* bSourceID */ - 0x00, /* iTerminal */ - /* 09 byte*/ - - /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwith */ - /* Interface 1, Alternate Setting 0 */ - AUDIO_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - 0x01, /* bInterfaceNumber */ - 0x00, /* bAlternateSetting */ - 0x00, /* bNumEndpoints */ - USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ - AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ - AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ - 0x00, /* iInterface */ - /* 09 byte*/ - - /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */ - /* Interface 1, Alternate Setting 1 */ - AUDIO_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - 0x01, /* bInterfaceNumber */ - 0x01, /* bAlternateSetting */ - 0x01, /* bNumEndpoints */ - USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ - AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ - AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ - 0x00, /* iInterface */ - /* 09 byte*/ - - /* USB Speaker Audio Streaming Interface Descriptor */ - AUDIO_STREAMING_INTERFACE_DESC_SIZE, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ - 0x01, /* bTerminalLink */ - 0x01, /* bDelay */ - 0x01, /* wFormatTag AUDIO_FORMAT_PCM 0x0001*/ - 0x00, - /* 07 byte*/ - - /* USB Speaker Audio Type III Format Interface Descriptor */ - 0x0B, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ - AUDIO_FORMAT_TYPE_III, /* bFormatType */ - 0x02, /* bNrChannels */ - 0x02, /* bSubFrameSize : 2 Bytes per frame (16bits) */ - 16, /* bBitResolution (16-bits per sample) */ - 0x01, /* bSamFreqType only one frequency supported */ - SAMPLE_FREQ(USBD_AUDIO_FREQ), /* Audio sampling frequency coded on 3 bytes */ - /* 11 byte*/ - - /* Endpoint 1 - Standard Descriptor */ - AUDIO_STANDARD_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_OUT_EP, /* bEndpointAddress 1 out endpoint*/ - USB_ENDPOINT_TYPE_ISOCHRONOUS, /* bmAttributes */ - AUDIO_PACKET_SZE(USBD_AUDIO_FREQ), /* wMaxPacketSize in Bytes (Freq(Samples)*2(Stereo)*2(HalfWord)) */ - 0x01, /* bInterval */ - 0x00, /* bRefresh */ - 0x00, /* bSynchAddress */ - /* 09 byte*/ - - /* Endpoint - Audio Streaming Descriptor*/ - AUDIO_STREAMING_ENDPOINT_DESC_SIZE, /* bLength */ - AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ - 0x00, /* bmAttributes */ - 0x00, /* bLockDelayUnits */ - 0x00, /* wLockDelay */ - 0x00, - /* 07 byte*/ -} ; - -/** - * @} - */ - -/** @defgroup usbd_audio_Private_Functions - * @{ - */ - -/** -* @brief usbd_audio_Init -* Initializes the AUDIO interface. -* @param pdev: device instance -* @param cfgidx: Configuration index -* @retval status -*/ -static uint8_t usbd_audio_Init (void *pdev, - uint8_t cfgidx) -{ - /* Open EP OUT */ - DCD_EP_Open(pdev, - AUDIO_OUT_EP, - AUDIO_OUT_PACKET, - USB_OTG_EP_ISOC); - - /* Initialize the Audio output Hardware layer */ - if (AUDIO_OUT_fops.Init(USBD_AUDIO_FREQ, DEFAULT_VOLUME, 0) != USBD_OK) - { - return USBD_FAIL; - } - - /* Prepare Out endpoint to receive audio data */ - DCD_EP_PrepareRx(pdev, - AUDIO_OUT_EP, - (uint8_t*)IsocOutBuff, - AUDIO_OUT_PACKET); - - return USBD_OK; -} - -/** -* @brief usbd_audio_Init -* DeInitializes the AUDIO layer. -* @param pdev: device instance -* @param cfgidx: Configuration index -* @retval status -*/ -static uint8_t usbd_audio_DeInit (void *pdev, - uint8_t cfgidx) -{ - DCD_EP_Close (pdev , AUDIO_OUT_EP); - - /* DeInitialize the Audio output Hardware layer */ - if (AUDIO_OUT_fops.DeInit(0) != USBD_OK) - { - return USBD_FAIL; - } - - return USBD_OK; -} - -/** - * @brief usbd_audio_Setup - * Handles the Audio control request parsing. - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t usbd_audio_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len=USB_AUDIO_DESC_SIZ; - uint8_t *pbuf=usbd_audio_CfgDesc + 18; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - /* AUDIO Class Requests -------------------------------*/ - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - case AUDIO_REQ_GET_CUR: - AUDIO_Req_GetCurrent(pdev, req); - break; - - case AUDIO_REQ_SET_CUR: - AUDIO_Req_SetCurrent(pdev, req); - break; - - default: - USBD_CtlError (pdev, req); - return USBD_FAIL; - } - break; - - /* Standard Requests -------------------------------*/ - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - if( (req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE) - { -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pbuf = usbd_audio_Desc; -#else - pbuf = usbd_audio_CfgDesc + 18; -#endif - len = MIN(USB_AUDIO_DESC_SIZ , req->wLength); - } - - USBD_CtlSendData (pdev, - pbuf, - len); - break; - - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - (uint8_t *)&usbd_audio_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - if ((uint8_t)(req->wValue) < AUDIO_TOTAL_IF_NUM) - { - usbd_audio_AltSet = (uint8_t)(req->wValue); - } - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - break; - } - } - return USBD_OK; -} - -/** - * @brief usbd_audio_EP0_RxReady - * Handles audio control requests data. - * @param pdev: device instance - * @retval status - */ -static uint8_t usbd_audio_EP0_RxReady (void *pdev) -{ - /* Check if an AudioControl request has been issued */ - if (AudioCtlCmd == AUDIO_REQ_SET_CUR) - {/* In this driver, to simplify code, only SET_CUR request is managed */ - /* Check for which addressed unit the AudioControl request has been issued */ - if (AudioCtlUnit == AUDIO_OUT_STREAMING_CTRL) - {/* In this driver, to simplify code, only one unit is manage */ - /* Call the audio interface mute function */ - AUDIO_OUT_fops.MuteCtl(AudioCtl[0]); - - /* Reset the AudioCtlCmd variable to prevent re-entering this function */ - AudioCtlCmd = 0; - AudioCtlLen = 0; - } - } - - return USBD_OK; -} - -/** - * @brief usbd_audio_DataIn - * Handles the audio IN data stage. - * @param pdev: instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t usbd_audio_DataIn (void *pdev, uint8_t epnum) -{ - return USBD_OK; -} - -/** - * @brief usbd_audio_DataOut - * Handles the Audio Out data stage. - * @param pdev: instance - * @param epnum: endpoint number - * @retval status - */ -__IO uint32_t DataOutCounter = 0; -static uint8_t usbd_audio_DataOut (void *pdev, uint8_t epnum) -{ - DataOutCounter++; - if (epnum == AUDIO_OUT_EP) - { - /* Increment the Buffer pointer or roll it back when all buffers are full */ - if (IsocOutWrPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) - {/* All buffers are full: roll back */ - IsocOutWrPtr = IsocOutBuff; - } - else - {/* Increment the buffer pointer */ - IsocOutWrPtr += AUDIO_OUT_PACKET; - } - - /* Toggle the frame index */ - ((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].even_odd_frame = - (((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].even_odd_frame)? 0:1; - - /* Prepare Out endpoint to receive next audio packet */ - DCD_EP_PrepareRx(pdev, - AUDIO_OUT_EP, - (uint8_t*)(IsocOutWrPtr), - AUDIO_OUT_PACKET); - - /* Trigger the start of streaming only when half buffer is full */ - if ((PlayFlag == 0) && (IsocOutWrPtr >= (IsocOutBuff + ((AUDIO_OUT_PACKET * OUT_PACKET_NUM) / 2)))) - { - /* Enable start of Streaming */ - PlayFlag = 1; - } - } - - return USBD_OK; -} - -/** - * @brief usbd_audio_SOF - * Handles the SOF event (data buffer update and synchronization). - * @param pdev: instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t usbd_audio_SOF (void *pdev) -{ - /* Check if there are available data in stream buffer. - In this function, a single variable (PlayFlag) is used to avoid software delays. - The play operation must be executed as soon as possible after the SOF detection. */ - if (PlayFlag) - { - /* Start playing received packet */ - AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutRdPtr), /* Samples buffer pointer */ - AUDIO_OUT_PACKET, /* Number of samples in Bytes */ - AUDIO_CMD_PLAY); /* Command to be processed */ - - /* Increment the Buffer pointer or roll it back when all buffers all full */ - if (IsocOutRdPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) - {/* Roll back to the start of buffer */ - IsocOutRdPtr = IsocOutBuff; - } - else - {/* Increment to the next sub-buffer */ - IsocOutRdPtr += AUDIO_OUT_PACKET; - } - - /* If all available buffers have been consumed, stop playing */ - if (IsocOutRdPtr == IsocOutWrPtr) - { - /* Pause the audio stream */ - AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutBuff), /* Samples buffer pointer */ - AUDIO_OUT_PACKET, /* Number of samples in Bytes */ - AUDIO_CMD_PAUSE); /* Command to be processed */ - - /* Stop entering play loop */ - PlayFlag = 0; - - /* Reset buffer pointers */ - IsocOutRdPtr = IsocOutBuff; - IsocOutWrPtr = IsocOutBuff; - } - } - - return USBD_OK; -} - -/** - * @brief usbd_audio_OUT_Incplt - * Handles the iso out incomplete event. - * @param pdev: instance - * @retval status - */ -static uint8_t usbd_audio_OUT_Incplt (void *pdev) -{ - return USBD_OK; -} - -/****************************************************************************** - AUDIO Class requests management -******************************************************************************/ -/** - * @brief AUDIO_Req_GetCurrent - * Handles the GET_CUR Audio control request. - * @param pdev: instance - * @param req: setup class request - * @retval status - */ -static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req) -{ - /* Send the current mute state */ - USBD_CtlSendData (pdev, - AudioCtl, - req->wLength); -} - -/** - * @brief AUDIO_Req_SetCurrent - * Handles the SET_CUR Audio control request. - * @param pdev: instance - * @param req: setup class request - * @retval status - */ -static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req) -{ - if (req->wLength) - { - /* Prepare the reception of the buffer over EP0 */ - USBD_CtlPrepareRx (pdev, - AudioCtl, - req->wLength); - - /* Set the global variables indicating current request and its length - to the function usbd_audio_EP0_RxReady() which will process the request */ - AudioCtlCmd = AUDIO_REQ_SET_CUR; /* Set the request value */ - AudioCtlLen = req->wLength; /* Set the request data length */ - AudioCtlUnit = HIBYTE(req->wIndex); /* Set the request target unit */ - } -} - -/** - * @brief USBD_audio_GetCfgDesc - * Returns configuration descriptor. - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_audio_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (usbd_audio_CfgDesc); - return usbd_audio_CfgDesc; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_audio_core.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides the high layer firmware functions to manage the + * following functionalities of the USB Audio Class: + * - Initialization and Configuration of high and low layer + * - Enumeration as Audio Streaming Device + * - Audio Streaming data transfer + * - AudioControl requests management + * - Error management + * + * @verbatim + * + * =================================================================== + * Audio Class Driver Description + * =================================================================== + * This driver manages the Audio Class 1.0 following the "USB Device Class Definition for + * Audio Devices V1.0 Mar 18, 98". + * This driver implements the following aspects of the specification: + * - Device descriptor management + * - Configuration descriptor management + * - Standard AC Interface Descriptor management + * - 1 Audio Streaming Interface (with single channel, PCM, Stereo mode) + * - 1 Audio Streaming Endpoint + * - 1 Audio Terminal Input (1 channel) + * - Audio Class-Specific AC Interfaces + * - Audio Class-Specific AS Interfaces + * - AudioControl Requests: only SET_CUR and GET_CUR requests are supported (for Mute) + * - Audio Feature Unit (limited to Mute control) + * - Audio Synchronization type: Asynchronous + * - Single fixed audio sampling rate (configurable in usbd_conf.h file) + * + * @note + * The Audio Class 1.0 is based on USB Specification 1.0 and thus supports only + * Low and Full speed modes and does not allow High Speed transfers. + * Please refer to "USB Device Class Definition for Audio Devices V1.0 Mar 18, 98" + * for more details. + * + * These aspects may be enriched or modified for a specific user application. + * + * This driver doesn't implement the following aspects of the specification + * (but it is possible to manage these features with some modifications on this driver): + * - AudioControl Endpoint management + * - AudioControl requests other than SET_CUR and GET_CUR + * - Abstraction layer for AudioControl requests (only Mute functionality is managed) + * - Audio Synchronization type: Adaptive + * - Audio Compression modules and interfaces + * - MIDI interfaces and modules + * - Mixer/Selector/Processing/Extension Units (Feature unit is limited to Mute control) + * - Any other application-specific modules + * - Multiple and Variable audio sampling rates + * - Out Streaming Endpoint/Interface (microphone) + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +#include "usbd_audio_core.h" +#include "usbd_audio_out_if.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup usbd_audio + * @brief usbd core module + * @{ + */ + +/** @defgroup usbd_audio_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup usbd_audio_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup usbd_audio_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup usbd_audio_Private_FunctionPrototypes + * @{ + */ + +/********************************************* + AUDIO Device library callbacks + *********************************************/ +static uint8_t usbd_audio_Init (void *pdev, uint8_t cfgidx); +static uint8_t usbd_audio_DeInit (void *pdev, uint8_t cfgidx); +static uint8_t usbd_audio_Setup (void *pdev, USB_SETUP_REQ *req); +static uint8_t usbd_audio_EP0_RxReady(void *pdev); +static uint8_t usbd_audio_DataIn (void *pdev, uint8_t epnum); +static uint8_t usbd_audio_DataOut (void *pdev, uint8_t epnum); +static uint8_t usbd_audio_SOF (void *pdev); +static uint8_t usbd_audio_OUT_Incplt (void *pdev); + +/********************************************* + AUDIO Requests management functions + *********************************************/ +static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req); +static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req); +static uint8_t *USBD_audio_GetCfgDesc (uint8_t speed, uint16_t *length); +/** + * @} + */ + +/** @defgroup usbd_audio_Private_Variables + * @{ + */ +/* Main Buffer for Audio Data Out transfers and its relative pointers */ +uint8_t IsocOutBuff [TOTAL_OUT_BUF_SIZE * 2]; +uint8_t* IsocOutWrPtr = IsocOutBuff; +uint8_t* IsocOutRdPtr = IsocOutBuff; + +/* Main Buffer for Audio Control Requests transfers and its relative variables */ +uint8_t AudioCtl[64]; +uint8_t AudioCtlCmd = 0; +uint32_t AudioCtlLen = 0; +uint8_t AudioCtlUnit = 0; + +static uint32_t PlayFlag = 0; + +static __IO uint32_t usbd_audio_AltSet = 0; +static uint8_t usbd_audio_CfgDesc[AUDIO_CONFIG_DESC_SIZE]; + +/* AUDIO interface class callbacks structure */ +USBD_Class_cb_TypeDef AUDIO_cb = +{ + usbd_audio_Init, + usbd_audio_DeInit, + usbd_audio_Setup, + NULL, /* EP0_TxSent */ + usbd_audio_EP0_RxReady, + usbd_audio_DataIn, + usbd_audio_DataOut, + usbd_audio_SOF, + NULL, + usbd_audio_OUT_Incplt, + USBD_audio_GetCfgDesc, +#ifdef USB_OTG_HS_CORE + USBD_audio_GetCfgDesc, /* use same config as per FS */ +#endif +}; + +/* USB AUDIO device Configuration Descriptor */ +static uint8_t usbd_audio_CfgDesc[AUDIO_CONFIG_DESC_SIZE] = +{ + /* Configuration 1 */ + 0x09, /* bLength */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */ + LOBYTE(AUDIO_CONFIG_DESC_SIZE), /* wTotalLength 109 bytes*/ + HIBYTE(AUDIO_CONFIG_DESC_SIZE), + 0x02, /* bNumInterfaces */ + 0x01, /* bConfigurationValue */ + 0x00, /* iConfiguration */ + 0xC0, /* bmAttributes BUS Powred*/ + 0x32, /* bMaxPower = 100 mA*/ + /* 09 byte*/ + + /* USB Speaker Standard interface descriptor */ + AUDIO_INTERFACE_DESC_SIZE, /* bLength */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + 0x00, /* bInterfaceNumber */ + 0x00, /* bAlternateSetting */ + 0x00, /* bNumEndpoints */ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ + AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ + 0x00, /* iInterface */ + /* 09 byte*/ + + /* USB Speaker Class-specific AC Interface Descriptor */ + AUDIO_INTERFACE_DESC_SIZE, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */ + 0x00, /* 1.00 */ /* bcdADC */ + 0x01, + 0x27, /* wTotalLength = 39*/ + 0x00, + 0x01, /* bInCollection */ + 0x01, /* baInterfaceNr */ + /* 09 byte*/ + + /* USB Speaker Input Terminal Descriptor */ + AUDIO_INPUT_TERMINAL_DESC_SIZE, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */ + 0x01, /* bTerminalID */ + 0x01, /* wTerminalType AUDIO_TERMINAL_USB_STREAMING 0x0101 */ + 0x01, + 0x00, /* bAssocTerminal */ + 0x01, /* bNrChannels */ + 0x00, /* wChannelConfig 0x0000 Mono */ + 0x00, + 0x00, /* iChannelNames */ + 0x00, /* iTerminal */ + /* 12 byte*/ + + /* USB Speaker Audio Feature Unit Descriptor */ + 0x09, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */ + AUDIO_OUT_STREAMING_CTRL, /* bUnitID */ + 0x01, /* bSourceID */ + 0x01, /* bControlSize */ + AUDIO_CONTROL_MUTE, /* bmaControls(0) */ + 0x00, /* bmaControls(1) */ + 0x00, /* iTerminal */ + /* 09 byte*/ + + /*USB Speaker Output Terminal Descriptor */ + 0x09, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */ + 0x03, /* bTerminalID */ + 0x01, /* wTerminalType 0x0301*/ + 0x03, + 0x00, /* bAssocTerminal */ + 0x02, /* bSourceID */ + 0x00, /* iTerminal */ + /* 09 byte*/ + + /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwith */ + /* Interface 1, Alternate Setting 0 */ + AUDIO_INTERFACE_DESC_SIZE, /* bLength */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + 0x01, /* bInterfaceNumber */ + 0x00, /* bAlternateSetting */ + 0x00, /* bNumEndpoints */ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ + 0x00, /* iInterface */ + /* 09 byte*/ + + /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */ + /* Interface 1, Alternate Setting 1 */ + AUDIO_INTERFACE_DESC_SIZE, /* bLength */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + 0x01, /* bInterfaceNumber */ + 0x01, /* bAlternateSetting */ + 0x01, /* bNumEndpoints */ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ + 0x00, /* iInterface */ + /* 09 byte*/ + + /* USB Speaker Audio Streaming Interface Descriptor */ + AUDIO_STREAMING_INTERFACE_DESC_SIZE, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ + 0x01, /* bTerminalLink */ + 0x01, /* bDelay */ + 0x01, /* wFormatTag AUDIO_FORMAT_PCM 0x0001*/ + 0x00, + /* 07 byte*/ + + /* USB Speaker Audio Type III Format Interface Descriptor */ + 0x0B, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ + AUDIO_FORMAT_TYPE_III, /* bFormatType */ + 0x02, /* bNrChannels */ + 0x02, /* bSubFrameSize : 2 Bytes per frame (16bits) */ + 16, /* bBitResolution (16-bits per sample) */ + 0x01, /* bSamFreqType only one frequency supported */ + SAMPLE_FREQ(USBD_AUDIO_FREQ), /* Audio sampling frequency coded on 3 bytes */ + /* 11 byte*/ + + /* Endpoint 1 - Standard Descriptor */ + AUDIO_STANDARD_ENDPOINT_DESC_SIZE, /* bLength */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_OUT_EP, /* bEndpointAddress 1 out endpoint*/ + USB_ENDPOINT_TYPE_ISOCHRONOUS, /* bmAttributes */ + AUDIO_PACKET_SZE(USBD_AUDIO_FREQ), /* wMaxPacketSize in Bytes (Freq(Samples)*2(Stereo)*2(HalfWord)) */ + 0x01, /* bInterval */ + 0x00, /* bRefresh */ + 0x00, /* bSynchAddress */ + /* 09 byte*/ + + /* Endpoint - Audio Streaming Descriptor*/ + AUDIO_STREAMING_ENDPOINT_DESC_SIZE, /* bLength */ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ + 0x00, /* bmAttributes */ + 0x00, /* bLockDelayUnits */ + 0x00, /* wLockDelay */ + 0x00, + /* 07 byte*/ +} ; + +/** + * @} + */ + +/** @defgroup usbd_audio_Private_Functions + * @{ + */ + +/** +* @brief usbd_audio_Init +* Initializes the AUDIO interface. +* @param pdev: device instance +* @param cfgidx: Configuration index +* @retval status +*/ +static uint8_t usbd_audio_Init (void *pdev, + uint8_t cfgidx) +{ + /* Open EP OUT */ + DCD_EP_Open(pdev, + AUDIO_OUT_EP, + AUDIO_OUT_PACKET, + USB_OTG_EP_ISOC); + + /* Initialize the Audio output Hardware layer */ + if (AUDIO_OUT_fops.Init(USBD_AUDIO_FREQ, DEFAULT_VOLUME, 0) != USBD_OK) + { + return USBD_FAIL; + } + + /* Prepare Out endpoint to receive audio data */ + DCD_EP_PrepareRx(pdev, + AUDIO_OUT_EP, + (uint8_t*)IsocOutBuff, + AUDIO_OUT_PACKET); + + return USBD_OK; +} + +/** +* @brief usbd_audio_Init +* DeInitializes the AUDIO layer. +* @param pdev: device instance +* @param cfgidx: Configuration index +* @retval status +*/ +static uint8_t usbd_audio_DeInit (void *pdev, + uint8_t cfgidx) +{ + DCD_EP_Close (pdev , AUDIO_OUT_EP); + + /* DeInitialize the Audio output Hardware layer */ + if (AUDIO_OUT_fops.DeInit(0) != USBD_OK) + { + return USBD_FAIL; + } + + return USBD_OK; +} + +/** + * @brief usbd_audio_Setup + * Handles the Audio control request parsing. + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t usbd_audio_Setup (void *pdev, + USB_SETUP_REQ *req) +{ + uint16_t len=USB_AUDIO_DESC_SIZ; + uint8_t *pbuf=usbd_audio_CfgDesc + 18; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + /* AUDIO Class Requests -------------------------------*/ + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case AUDIO_REQ_GET_CUR: + AUDIO_Req_GetCurrent(pdev, req); + break; + + case AUDIO_REQ_SET_CUR: + AUDIO_Req_SetCurrent(pdev, req); + break; + + default: + USBD_CtlError (pdev, req); + return USBD_FAIL; + } + break; + + /* Standard Requests -------------------------------*/ + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + if( (req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE) + { +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + pbuf = usbd_audio_Desc; +#else + pbuf = usbd_audio_CfgDesc + 18; +#endif + len = MIN(USB_AUDIO_DESC_SIZ , req->wLength); + } + + USBD_CtlSendData (pdev, + pbuf, + len); + break; + + case USB_REQ_GET_INTERFACE : + USBD_CtlSendData (pdev, + (uint8_t *)&usbd_audio_AltSet, + 1); + break; + + case USB_REQ_SET_INTERFACE : + if ((uint8_t)(req->wValue) < AUDIO_TOTAL_IF_NUM) + { + usbd_audio_AltSet = (uint8_t)(req->wValue); + } + else + { + /* Call the error management function (command will be nacked */ + USBD_CtlError (pdev, req); + } + break; + } + } + return USBD_OK; +} + +/** + * @brief usbd_audio_EP0_RxReady + * Handles audio control requests data. + * @param pdev: device instance + * @retval status + */ +static uint8_t usbd_audio_EP0_RxReady (void *pdev) +{ + /* Check if an AudioControl request has been issued */ + if (AudioCtlCmd == AUDIO_REQ_SET_CUR) + {/* In this driver, to simplify code, only SET_CUR request is managed */ + /* Check for which addressed unit the AudioControl request has been issued */ + if (AudioCtlUnit == AUDIO_OUT_STREAMING_CTRL) + {/* In this driver, to simplify code, only one unit is manage */ + /* Call the audio interface mute function */ + AUDIO_OUT_fops.MuteCtl(AudioCtl[0]); + + /* Reset the AudioCtlCmd variable to prevent re-entering this function */ + AudioCtlCmd = 0; + AudioCtlLen = 0; + } + } + + return USBD_OK; +} + +/** + * @brief usbd_audio_DataIn + * Handles the audio IN data stage. + * @param pdev: instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t usbd_audio_DataIn (void *pdev, uint8_t epnum) +{ + return USBD_OK; +} + +/** + * @brief usbd_audio_DataOut + * Handles the Audio Out data stage. + * @param pdev: instance + * @param epnum: endpoint number + * @retval status + */ +__IO uint32_t DataOutCounter = 0; +static uint8_t usbd_audio_DataOut (void *pdev, uint8_t epnum) +{ + DataOutCounter++; + if (epnum == AUDIO_OUT_EP) + { + /* Increment the Buffer pointer or roll it back when all buffers are full */ + if (IsocOutWrPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) + {/* All buffers are full: roll back */ + IsocOutWrPtr = IsocOutBuff; + } + else + {/* Increment the buffer pointer */ + IsocOutWrPtr += AUDIO_OUT_PACKET; + } + + /* Toggle the frame index */ + ((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].even_odd_frame = + (((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].even_odd_frame)? 0:1; + + /* Prepare Out endpoint to receive next audio packet */ + DCD_EP_PrepareRx(pdev, + AUDIO_OUT_EP, + (uint8_t*)(IsocOutWrPtr), + AUDIO_OUT_PACKET); + + /* Trigger the start of streaming only when half buffer is full */ + if ((PlayFlag == 0) && (IsocOutWrPtr >= (IsocOutBuff + ((AUDIO_OUT_PACKET * OUT_PACKET_NUM) / 2)))) + { + /* Enable start of Streaming */ + PlayFlag = 1; + } + } + + return USBD_OK; +} + +/** + * @brief usbd_audio_SOF + * Handles the SOF event (data buffer update and synchronization). + * @param pdev: instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t usbd_audio_SOF (void *pdev) +{ + /* Check if there are available data in stream buffer. + In this function, a single variable (PlayFlag) is used to avoid software delays. + The play operation must be executed as soon as possible after the SOF detection. */ + if (PlayFlag) + { + /* Start playing received packet */ + AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutRdPtr), /* Samples buffer pointer */ + AUDIO_OUT_PACKET, /* Number of samples in Bytes */ + AUDIO_CMD_PLAY); /* Command to be processed */ + + /* Increment the Buffer pointer or roll it back when all buffers all full */ + if (IsocOutRdPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) + {/* Roll back to the start of buffer */ + IsocOutRdPtr = IsocOutBuff; + } + else + {/* Increment to the next sub-buffer */ + IsocOutRdPtr += AUDIO_OUT_PACKET; + } + + /* If all available buffers have been consumed, stop playing */ + if (IsocOutRdPtr == IsocOutWrPtr) + { + /* Pause the audio stream */ + AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutBuff), /* Samples buffer pointer */ + AUDIO_OUT_PACKET, /* Number of samples in Bytes */ + AUDIO_CMD_PAUSE); /* Command to be processed */ + + /* Stop entering play loop */ + PlayFlag = 0; + + /* Reset buffer pointers */ + IsocOutRdPtr = IsocOutBuff; + IsocOutWrPtr = IsocOutBuff; + } + } + + return USBD_OK; +} + +/** + * @brief usbd_audio_OUT_Incplt + * Handles the iso out incomplete event. + * @param pdev: instance + * @retval status + */ +static uint8_t usbd_audio_OUT_Incplt (void *pdev) +{ + return USBD_OK; +} + +/****************************************************************************** + AUDIO Class requests management +******************************************************************************/ +/** + * @brief AUDIO_Req_GetCurrent + * Handles the GET_CUR Audio control request. + * @param pdev: instance + * @param req: setup class request + * @retval status + */ +static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req) +{ + /* Send the current mute state */ + USBD_CtlSendData (pdev, + AudioCtl, + req->wLength); +} + +/** + * @brief AUDIO_Req_SetCurrent + * Handles the SET_CUR Audio control request. + * @param pdev: instance + * @param req: setup class request + * @retval status + */ +static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req) +{ + if (req->wLength) + { + /* Prepare the reception of the buffer over EP0 */ + USBD_CtlPrepareRx (pdev, + AudioCtl, + req->wLength); + + /* Set the global variables indicating current request and its length + to the function usbd_audio_EP0_RxReady() which will process the request */ + AudioCtlCmd = AUDIO_REQ_SET_CUR; /* Set the request value */ + AudioCtlLen = req->wLength; /* Set the request data length */ + AudioCtlUnit = HIBYTE(req->wIndex); /* Set the request target unit */ + } +} + +/** + * @brief USBD_audio_GetCfgDesc + * Returns configuration descriptor. + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_audio_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (usbd_audio_CfgDesc); + return usbd_audio_CfgDesc; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/src/usbd_audio_out_if.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/src/usbd_audio_out_if.c index 30e3fcb8c..93b163c81 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/src/usbd_audio_out_if.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/audio/src/usbd_audio_out_if.c @@ -1,333 +1,333 @@ -/** - ****************************************************************************** - * @file usbd_audio_out_if.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides the Audio Out (palyback) interface API. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_audio_core.h" -#include "usbd_audio_out_if.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup usbd_audio_out_if - * @brief usbd out interface module - * @{ - */ - -/** @defgroup usbd_audio_out_if_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_out_if_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_out_if_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_out_if_Private_FunctionPrototypes - * @{ - */ -static uint8_t Init (uint32_t AudioFreq, uint32_t Volume, uint32_t options); -static uint8_t DeInit (uint32_t options); -static uint8_t AudioCmd (uint8_t* pbuf, uint32_t size, uint8_t cmd); -static uint8_t VolumeCtl (uint8_t vol); -static uint8_t MuteCtl (uint8_t cmd); -static uint8_t PeriodicTC (uint8_t cmd); -static uint8_t GetState (void); - -/** - * @} - */ - -/** @defgroup usbd_audio_out_if_Private_Variables - * @{ - */ -AUDIO_FOPS_TypeDef AUDIO_OUT_fops = -{ - Init, - DeInit, - AudioCmd, - VolumeCtl, - MuteCtl, - PeriodicTC, - GetState -}; - -static uint8_t AudioState = AUDIO_STATE_INACTIVE; - -/** - * @} - */ - -/** @defgroup usbd_audio_out_if_Private_Functions - * @{ - */ - -/** - * @brief Init - * Initialize and configures all required resources for audio play function. - * @param AudioFreq: Startup audio frequency. - * @param Volume: Startup volume to be set. - * @param options: specific options passed to low layer function. - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t Init (uint32_t AudioFreq, - uint32_t Volume, - uint32_t options) -{ - static uint32_t Initialized = 0; - - /* Check if the low layer has already been initialized */ - if (Initialized == 0) - { - /* Call low layer function */ -#if defined (USE_STM324x9I_EVAL) - if (EVAL_AUDIO_Init(OUTPUT_DEVICE_BOTH, Volume, AudioFreq) != 0) -#else - if (EVAL_AUDIO_Init(OUTPUT_DEVICE_AUTO, Volume, AudioFreq) != 0) -#endif - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - - /* Set the Initialization flag to prevent reinitializing the interface again */ - Initialized = 1; - } - - /* Update the Audio state machine */ - AudioState = AUDIO_STATE_ACTIVE; - - return AUDIO_OK; -} - -/** - * @brief DeInit - * Free all resources used by low layer and stops audio-play function. - * @param options: options passed to low layer function. - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t DeInit (uint32_t options) -{ - /* Update the Audio state machine */ - AudioState = AUDIO_STATE_INACTIVE; - - return AUDIO_OK; -} - -/** - * @brief AudioCmd - * Play, Stop, Pause or Resume current file. - * @param pbuf: address from which file should be played. - * @param size: size of the current buffer/file. - * @param cmd: command to be executed, can be AUDIO_CMD_PLAY , AUDIO_CMD_PAUSE, - * AUDIO_CMD_RESUME or AUDIO_CMD_STOP. - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t AudioCmd(uint8_t* pbuf, - uint32_t size, - uint8_t cmd) -{ - /* Check the current state */ - if ((AudioState == AUDIO_STATE_INACTIVE) || (AudioState == AUDIO_STATE_ERROR)) - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - - switch (cmd) - { - /* Process the PLAY command ----------------------------*/ - case AUDIO_CMD_PLAY: - /* If current state is Active or Stopped */ - if ((AudioState == AUDIO_STATE_ACTIVE) || \ - (AudioState == AUDIO_STATE_STOPPED) || \ - (AudioState == AUDIO_STATE_PLAYING)) - { - Audio_MAL_Play((uint32_t)pbuf, (size/2)); - AudioState = AUDIO_STATE_PLAYING; - return AUDIO_OK; - } - /* If current state is Paused */ - else if (AudioState == AUDIO_STATE_PAUSED) - { -#if defined (USE_STM324x9I_EVAL) - if (EVAL_AUDIO_PauseResume(AUDIO_RESUME) != 0) -#else - if (EVAL_AUDIO_PauseResume(AUDIO_RESUME, (uint32_t)pbuf, (size/2)) != 0) -#endif - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - else - { - AudioState = AUDIO_STATE_PLAYING; - return AUDIO_OK; - } - } - else /* Not allowed command */ - { - return AUDIO_FAIL; - } - - /* Process the STOP command ----------------------------*/ - case AUDIO_CMD_STOP: - if (AudioState != AUDIO_STATE_PLAYING) - { - /* Unsupported command */ - return AUDIO_FAIL; - } - else if (EVAL_AUDIO_Stop(CODEC_PDWN_SW) != 0) - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - else - { - AudioState = AUDIO_STATE_STOPPED; - return AUDIO_OK; - } - - /* Process the PAUSE command ---------------------------*/ - case AUDIO_CMD_PAUSE: - if (AudioState != AUDIO_STATE_PLAYING) - { - /* Unsupported command */ - return AUDIO_FAIL; - } -#if defined (USE_STM324x9I_EVAL) - else if (EVAL_AUDIO_PauseResume(AUDIO_PAUSE) != 0) -#else - else if (EVAL_AUDIO_PauseResume(AUDIO_PAUSE, (uint32_t)pbuf, (size/2)) != 0) -#endif - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - else - { - AudioState = AUDIO_STATE_PAUSED; - return AUDIO_OK; - } - - /* Unsupported command ---------------------------------*/ - default: - return AUDIO_FAIL; - } -} - -/** - * @brief VolumeCtl - * Set the volume level in % - * @param vol: volume level to be set in % (from 0% to 100%) - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t VolumeCtl (uint8_t vol) -{ - /* Call low layer volume setting function */ - if (EVAL_AUDIO_VolumeCtl(vol) != 0) - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - - return AUDIO_OK; -} - -/** - * @brief MuteCtl - * Mute or Unmute the audio current output - * @param cmd: can be 0 to unmute, or 1 to mute. - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t MuteCtl (uint8_t cmd) -{ - /* Call low layer mute setting function */ - if (EVAL_AUDIO_Mute(cmd) != 0) - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - - return AUDIO_OK; -} - -/** - * @brief - * - * @param - * @param - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t PeriodicTC (uint8_t cmd) -{ - - - return AUDIO_OK; -} - - -/** - * @brief GetState - * Return the current state of the audio machine - * @param None - * @retval Current State. - */ -static uint8_t GetState (void) -{ - return AudioState; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_audio_out_if.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides the Audio Out (palyback) interface API. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_audio_core.h" +#include "usbd_audio_out_if.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup usbd_audio_out_if + * @brief usbd out interface module + * @{ + */ + +/** @defgroup usbd_audio_out_if_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup usbd_audio_out_if_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup usbd_audio_out_if_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup usbd_audio_out_if_Private_FunctionPrototypes + * @{ + */ +static uint8_t Init (uint32_t AudioFreq, uint32_t Volume, uint32_t options); +static uint8_t DeInit (uint32_t options); +static uint8_t AudioCmd (uint8_t* pbuf, uint32_t size, uint8_t cmd); +static uint8_t VolumeCtl (uint8_t vol); +static uint8_t MuteCtl (uint8_t cmd); +static uint8_t PeriodicTC (uint8_t cmd); +static uint8_t GetState (void); + +/** + * @} + */ + +/** @defgroup usbd_audio_out_if_Private_Variables + * @{ + */ +AUDIO_FOPS_TypeDef AUDIO_OUT_fops = +{ + Init, + DeInit, + AudioCmd, + VolumeCtl, + MuteCtl, + PeriodicTC, + GetState +}; + +static uint8_t AudioState = AUDIO_STATE_INACTIVE; + +/** + * @} + */ + +/** @defgroup usbd_audio_out_if_Private_Functions + * @{ + */ + +/** + * @brief Init + * Initialize and configures all required resources for audio play function. + * @param AudioFreq: Startup audio frequency. + * @param Volume: Startup volume to be set. + * @param options: specific options passed to low layer function. + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t Init (uint32_t AudioFreq, + uint32_t Volume, + uint32_t options) +{ + static uint32_t Initialized = 0; + + /* Check if the low layer has already been initialized */ + if (Initialized == 0) + { + /* Call low layer function */ +#if defined (USE_STM324x9I_EVAL) + if (EVAL_AUDIO_Init(OUTPUT_DEVICE_BOTH, Volume, AudioFreq) != 0) +#else + if (EVAL_AUDIO_Init(OUTPUT_DEVICE_AUTO, Volume, AudioFreq) != 0) +#endif + { + AudioState = AUDIO_STATE_ERROR; + return AUDIO_FAIL; + } + + /* Set the Initialization flag to prevent reinitializing the interface again */ + Initialized = 1; + } + + /* Update the Audio state machine */ + AudioState = AUDIO_STATE_ACTIVE; + + return AUDIO_OK; +} + +/** + * @brief DeInit + * Free all resources used by low layer and stops audio-play function. + * @param options: options passed to low layer function. + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t DeInit (uint32_t options) +{ + /* Update the Audio state machine */ + AudioState = AUDIO_STATE_INACTIVE; + + return AUDIO_OK; +} + +/** + * @brief AudioCmd + * Play, Stop, Pause or Resume current file. + * @param pbuf: address from which file should be played. + * @param size: size of the current buffer/file. + * @param cmd: command to be executed, can be AUDIO_CMD_PLAY , AUDIO_CMD_PAUSE, + * AUDIO_CMD_RESUME or AUDIO_CMD_STOP. + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t AudioCmd(uint8_t* pbuf, + uint32_t size, + uint8_t cmd) +{ + /* Check the current state */ + if ((AudioState == AUDIO_STATE_INACTIVE) || (AudioState == AUDIO_STATE_ERROR)) + { + AudioState = AUDIO_STATE_ERROR; + return AUDIO_FAIL; + } + + switch (cmd) + { + /* Process the PLAY command ----------------------------*/ + case AUDIO_CMD_PLAY: + /* If current state is Active or Stopped */ + if ((AudioState == AUDIO_STATE_ACTIVE) || \ + (AudioState == AUDIO_STATE_STOPPED) || \ + (AudioState == AUDIO_STATE_PLAYING)) + { + Audio_MAL_Play((uint32_t)pbuf, (size/2)); + AudioState = AUDIO_STATE_PLAYING; + return AUDIO_OK; + } + /* If current state is Paused */ + else if (AudioState == AUDIO_STATE_PAUSED) + { +#if defined (USE_STM324x9I_EVAL) + if (EVAL_AUDIO_PauseResume(AUDIO_RESUME) != 0) +#else + if (EVAL_AUDIO_PauseResume(AUDIO_RESUME, (uint32_t)pbuf, (size/2)) != 0) +#endif + { + AudioState = AUDIO_STATE_ERROR; + return AUDIO_FAIL; + } + else + { + AudioState = AUDIO_STATE_PLAYING; + return AUDIO_OK; + } + } + else /* Not allowed command */ + { + return AUDIO_FAIL; + } + + /* Process the STOP command ----------------------------*/ + case AUDIO_CMD_STOP: + if (AudioState != AUDIO_STATE_PLAYING) + { + /* Unsupported command */ + return AUDIO_FAIL; + } + else if (EVAL_AUDIO_Stop(CODEC_PDWN_SW) != 0) + { + AudioState = AUDIO_STATE_ERROR; + return AUDIO_FAIL; + } + else + { + AudioState = AUDIO_STATE_STOPPED; + return AUDIO_OK; + } + + /* Process the PAUSE command ---------------------------*/ + case AUDIO_CMD_PAUSE: + if (AudioState != AUDIO_STATE_PLAYING) + { + /* Unsupported command */ + return AUDIO_FAIL; + } +#if defined (USE_STM324x9I_EVAL) + else if (EVAL_AUDIO_PauseResume(AUDIO_PAUSE) != 0) +#else + else if (EVAL_AUDIO_PauseResume(AUDIO_PAUSE, (uint32_t)pbuf, (size/2)) != 0) +#endif + { + AudioState = AUDIO_STATE_ERROR; + return AUDIO_FAIL; + } + else + { + AudioState = AUDIO_STATE_PAUSED; + return AUDIO_OK; + } + + /* Unsupported command ---------------------------------*/ + default: + return AUDIO_FAIL; + } +} + +/** + * @brief VolumeCtl + * Set the volume level in % + * @param vol: volume level to be set in % (from 0% to 100%) + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t VolumeCtl (uint8_t vol) +{ + /* Call low layer volume setting function */ + if (EVAL_AUDIO_VolumeCtl(vol) != 0) + { + AudioState = AUDIO_STATE_ERROR; + return AUDIO_FAIL; + } + + return AUDIO_OK; +} + +/** + * @brief MuteCtl + * Mute or Unmute the audio current output + * @param cmd: can be 0 to unmute, or 1 to mute. + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t MuteCtl (uint8_t cmd) +{ + /* Call low layer mute setting function */ + if (EVAL_AUDIO_Mute(cmd) != 0) + { + AudioState = AUDIO_STATE_ERROR; + return AUDIO_FAIL; + } + + return AUDIO_OK; +} + +/** + * @brief + * + * @param + * @param + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t PeriodicTC (uint8_t cmd) +{ + + + return AUDIO_OK; +} + + +/** + * @brief GetState + * Return the current state of the audio machine + * @param None + * @retval Current State. + */ +static uint8_t GetState (void) +{ + return AudioState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h index a9711727e..9db15194b 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h @@ -1,141 +1,141 @@ -/** - ****************************************************************************** - * @file usbd_cdc_core.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header file for the usbd_cdc_core.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_CDC_CORE_H_ -#define __USB_CDC_CORE_H_ - -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_cdc - * @brief This file is the Header file for USBD_cdc.c - * @{ - */ - - -/** @defgroup usbd_cdc_Exported_Defines - * @{ - */ -#define USB_CDC_CONFIG_DESC_SIZ (67) -#define USB_CDC_DESC_SIZ (67-9) - -#define DEVICE_CLASS_CDC 0x02 -#define DEVICE_SUBCLASS_CDC 0x00 - - -#define USB_DEVICE_DESCRIPTOR_TYPE 0x01 -#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 -#define USB_STRING_DESCRIPTOR_TYPE 0x03 -#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 -#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 - -#define STANDARD_ENDPOINT_DESC_SIZE 0x09 - -#define CDC_DATA_IN_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE - -#define CDC_DATA_OUT_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE - -/*---------------------------------------------------------------------*/ -/* CDC definitions */ -/*---------------------------------------------------------------------*/ - -/**************************************************/ -/* CDC Requests */ -/**************************************************/ -#define SEND_ENCAPSULATED_COMMAND 0x00 -#define GET_ENCAPSULATED_RESPONSE 0x01 -#define SET_COMM_FEATURE 0x02 -#define GET_COMM_FEATURE 0x03 -#define CLEAR_COMM_FEATURE 0x04 -#define SET_LINE_CODING 0x20 -#define GET_LINE_CODING 0x21 -#define SET_CONTROL_LINE_STATE 0x22 -#define SEND_BREAK 0x23 -#define NO_CMD 0xFF - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ -typedef struct _CDC_IF_PROP -{ - uint16_t (*pIf_Init) (void); - uint16_t (*pIf_DeInit) (void); - uint16_t (*pIf_Ctrl) (uint32_t Cmd, uint8_t* Buf, uint32_t Len); - uint16_t (*pIf_DataTx) (void); - uint16_t (*pIf_DataRx) (uint8_t* Buf, uint32_t Len); -} -CDC_IF_Prop_TypeDef; -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern const USBD_Class_cb_TypeDef USBD_CDC_cb; // modified my OpenTX -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -/** - * @} - */ - -#endif /* __USB_CDC_CORE_H_ */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_cdc_core.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header file for the usbd_cdc_core.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +#ifndef __USB_CDC_CORE_H_ +#define __USB_CDC_CORE_H_ + +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup usbd_cdc + * @brief This file is the Header file for USBD_cdc.c + * @{ + */ + + +/** @defgroup usbd_cdc_Exported_Defines + * @{ + */ +#define USB_CDC_CONFIG_DESC_SIZ (67) +#define USB_CDC_DESC_SIZ (67-9) + +#define DEVICE_CLASS_CDC 0x02 +#define DEVICE_SUBCLASS_CDC 0x00 + + +#define USB_DEVICE_DESCRIPTOR_TYPE 0x01 +#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 +#define USB_STRING_DESCRIPTOR_TYPE 0x03 +#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 +#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 + +#define STANDARD_ENDPOINT_DESC_SIZE 0x09 + +#define CDC_DATA_IN_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE + +#define CDC_DATA_OUT_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE + +/*---------------------------------------------------------------------*/ +/* CDC definitions */ +/*---------------------------------------------------------------------*/ + +/**************************************************/ +/* CDC Requests */ +/**************************************************/ +#define SEND_ENCAPSULATED_COMMAND 0x00 +#define GET_ENCAPSULATED_RESPONSE 0x01 +#define SET_COMM_FEATURE 0x02 +#define GET_COMM_FEATURE 0x03 +#define CLEAR_COMM_FEATURE 0x04 +#define SET_LINE_CODING 0x20 +#define GET_LINE_CODING 0x21 +#define SET_CONTROL_LINE_STATE 0x22 +#define SEND_BREAK 0x23 +#define NO_CMD 0xFF + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ +typedef struct _CDC_IF_PROP +{ + uint16_t (*pIf_Init) (void); + uint16_t (*pIf_DeInit) (void); + uint16_t (*pIf_Ctrl) (uint32_t Cmd, uint8_t* Buf, uint32_t Len); + uint16_t (*pIf_DataTx) (void); + uint16_t (*pIf_DataRx) (uint8_t* Buf, uint32_t Len); +} +CDC_IF_Prop_TypeDef; +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern const USBD_Class_cb_TypeDef USBD_CDC_cb; // modified my OpenTX +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +/** + * @} + */ + +#endif /* __USB_CDC_CORE_H_ */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_if_template.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_if_template.h index 4e91a7d18..238ade8d1 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_if_template.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_if_template.h @@ -1,46 +1,46 @@ -/** - ****************************************************************************** - * @file usbd_cdc_if_template.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Header for dfu_mal.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CDC_IF_TEMPLATE_H -#define __USBD_CDC_IF_TEMPLATE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usbd_conf.h" -#include "usbd_cdc_core.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -extern CDC_IF_Prop_TypeDef TEMPLATE_fops; - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -#endif /* __USBD_CDC_IF_TEMPLATE_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_cdc_if_template.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Header for dfu_mal.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CDC_IF_TEMPLATE_H +#define __USBD_CDC_IF_TEMPLATE_H + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" +#include "usbd_conf.h" +#include "usbd_cdc_core.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +extern CDC_IF_Prop_TypeDef TEMPLATE_fops; + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +#endif /* __USBD_CDC_IF_TEMPLATE_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c index 448e4916f..f9f8e8e9f 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c @@ -1,838 +1,838 @@ -/** - ****************************************************************************** - * @file usbd_cdc_core.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides the high layer firmware functions to manage the - * following functionalities of the USB CDC Class: - * - Initialization and Configuration of high and low layer - * - Enumeration as CDC Device (and enumeration for each implemented memory interface) - * - OUT/IN data transfer - * - Command IN transfer (class requests management) - * - Error management - * - * @verbatim - * - * =================================================================== - * CDC Class Driver Description - * =================================================================== - * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices - * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus - * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" - * This driver implements the following aspects of the specification: - * - Device descriptor management - * - Configuration descriptor management - * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) - * - Requests management (as described in section 6.2 in specification) - * - Abstract Control Model compliant - * - Union Functional collection (using 1 IN endpoint for control) - * - Data interface class - - * @note - * For the Abstract Control Model, this core allows only transmitting the requests to - * lower layer dispatcher (ie. usbd_cdc_vcp.c/.h) which should manage each request and - * perform relative actions. - * - * These aspects may be enriched or modified for a specific user application. - * - * This driver doesn't implement the following aspects of the specification - * (but it is possible to manage these features with some modifications on this driver): - * - Any class-specific aspect relative to communication classes should be managed by user application. - * - All communication classes other than PSTN are not managed - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup usbd_cdc - * @brief usbd core module - * @{ - */ - -/** @defgroup usbd_cdc_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_cdc_Private_Defines - * @{ - */ - -#define USB_CDC_IDLE 0 -#define USB_CDC_BUSY 1 -#define USB_CDC_ZLP 2 - -/** - * @} - */ - - -/** @defgroup usbd_cdc_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_cdc_Private_FunctionPrototypes - * @{ - */ - -/********************************************* - CDC Device library callbacks - *********************************************/ -uint8_t usbd_cdc_Init (void *pdev, uint8_t cfgidx); -uint8_t usbd_cdc_DeInit (void *pdev, uint8_t cfgidx); -uint8_t usbd_cdc_Setup (void *pdev, USB_SETUP_REQ *req); -uint8_t usbd_cdc_EP0_RxReady (void *pdev); -uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum); -uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum); -uint8_t usbd_cdc_SOF (void *pdev); - -/********************************************* - CDC specific management functions - *********************************************/ -static void Handle_USBAsynchXfer (void *pdev); -static const uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length); // modified by OpenTX -#ifdef USE_USB_OTG_HS -static uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length); -#endif -/** - * @} - */ - -/** @defgroup usbd_cdc_Private_Variables - * @{ - */ -extern const CDC_IF_Prop_TypeDef APP_FOPS; // modified my OpenTX -extern const uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; // modified by OpenTX - -// modified my OpenTX -// #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED -// #if defined ( __ICCARM__ ) /*!< IAR Compiler */ -// #pragma data_alignment=4 -// #endif -// #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -// __ALIGN_BEGIN uint8_t usbd_cdc_CfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ; - -// modified my OpenTX -// #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED -// #if defined ( __ICCARM__ ) /*!< IAR Compiler */ -// #pragma data_alignment=4 -// #endif -// #endif USB_OTG_HS_INTERNAL_DMA_ENABLED -// __ALIGN_BEGIN uint8_t usbd_cdc_OtherCfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static __IO uint32_t usbd_cdc_AltSet __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t USB_Rx_Buffer [CDC_DATA_MAX_PACKET_SIZE] __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t APP_Rx_Buffer [APP_RX_DATA_SIZE] __ALIGN_END ; - - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t CmdBuff[CDC_CMD_PACKET_SZE] __ALIGN_END ; - -volatile uint32_t APP_Rx_ptr_in = 0; // modified by OpenTX -volatile uint32_t APP_Rx_ptr_out = 0; // modified by OpenTX -uint32_t APP_Rx_length = 0; - -uint8_t USB_Tx_State = USB_CDC_IDLE; - -static uint32_t cdcCmd = 0xFF; -static uint8_t cdcLen = 0; // modified by OpenTX - -/* CDC interface class callbacks structure */ -const USBD_Class_cb_TypeDef USBD_CDC_cb = // modified by OpenTX -{ - usbd_cdc_Init, - usbd_cdc_DeInit, - usbd_cdc_Setup, - NULL, /* EP0_TxSent, */ - usbd_cdc_EP0_RxReady, - usbd_cdc_DataIn, - usbd_cdc_DataOut, - usbd_cdc_SOF, - NULL, - NULL, - USBD_cdc_GetCfgDesc, -#ifdef USE_USB_OTG_HS - USBD_cdc_GetOtherCfgDesc, /* use same cobfig as per FS */ -#endif /* USE_USB_OTG_HS */ -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN const uint8_t usbd_cdc_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = // modified by OpenTX -{ - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ - 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - - /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SZE), -#ifdef USE_USB_OTG_HS - 0x10, /* bInterval: */ -#else - 0xFF, /* bInterval: */ -#endif /* USE_USB_OTG_HS */ - - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; - -#ifdef USE_USB_OTG_HS -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN const uint8_t usbd_cdc_OtherCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = // modified by OpenTX -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, - USB_CDC_CONFIG_DESC_SIZ, - 0x00, - 0x02, /* bNumInterfaces: 2 interfaces */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SZE), - 0xFF, /* bInterval: */ - - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00 /* bInterval */ -}; -#endif /* USE_USB_OTG_HS */ - -/** - * @} - */ - -/** @defgroup usbd_cdc_Private_Functions - * @{ - */ - -/** - * @brief usbd_cdc_Init - * Initialize the CDC interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -uint8_t usbd_cdc_Init (void *pdev, - uint8_t cfgidx) -{ - uint8_t *pbuf; - - APP_Rx_ptr_in = 0; // modified by OpenTX - APP_Rx_ptr_out = 0; // modified by OpenTX - APP_Rx_length = 0; // modified by OpenTX - USB_Tx_State = USB_CDC_IDLE; // modified by OpenTX - cdcCmd = 0xFF; // modified by OpenTX - cdcLen = 0; // modified by OpenTX - - /* Open EP IN */ - DCD_EP_Open(pdev, - CDC_IN_EP, - CDC_DATA_IN_PACKET_SIZE, - USB_OTG_EP_BULK); - - /* Open EP OUT */ - DCD_EP_Open(pdev, - CDC_OUT_EP, - CDC_DATA_OUT_PACKET_SIZE, - USB_OTG_EP_BULK); - - /* Open Command IN EP */ - DCD_EP_Open(pdev, - CDC_CMD_EP, - CDC_CMD_PACKET_SZE, - USB_OTG_EP_INT); - - pbuf = (uint8_t *)USBD_DeviceDesc; - pbuf[4] = DEVICE_CLASS_CDC; - pbuf[5] = DEVICE_SUBCLASS_CDC; - - /* Initialize the Interface physical components */ - APP_FOPS.pIf_Init(); - - /* Prepare Out endpoint to receive next packet */ - DCD_EP_PrepareRx(pdev, - CDC_OUT_EP, - (uint8_t*)(USB_Rx_Buffer), - CDC_DATA_OUT_PACKET_SIZE); - - return USBD_OK; -} - -/** - * @brief usbd_cdc_Init - * DeInitialize the CDC layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -uint8_t usbd_cdc_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* Open EP IN */ - DCD_EP_Close(pdev, - CDC_IN_EP); - - /* Open EP OUT */ - DCD_EP_Close(pdev, - CDC_OUT_EP); - - /* Open Command IN EP */ - DCD_EP_Close(pdev, - CDC_CMD_EP); - - /* Restore default state of the Interface physical components */ - APP_FOPS.pIf_DeInit(); - - return USBD_OK; -} - -/** - * @brief usbd_cdc_Setup - * Handle the CDC specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -uint8_t usbd_cdc_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - /* CDC Class Requests -------------------------------*/ - case USB_REQ_TYPE_CLASS : - /* Check if the request is a data setup packet */ - if (req->wLength) - { - /* Check if the request is Device-to-Host */ - if (req->bmRequest & 0x80) - { - /* Get the data to be sent to Host from interface layer */ - APP_FOPS.pIf_Ctrl(req->bRequest, CmdBuff, req->wLength); - - /* Send the data to the host */ - USBD_CtlSendData (pdev, - CmdBuff, - req->wLength); - } - else /* Host-to-Device request */ - { - /* Set the value of the current command to be processed */ - cdcCmd = req->bRequest; - cdcLen = req->wLength; - - /* Prepare the reception of the buffer over EP0 - Next step: the received data will be managed in usbd_cdc_EP0_TxSent() - function. */ - USBD_CtlPrepareRx (pdev, - CmdBuff, - req->wLength); - } - } - else /* No Data request */ - { - /* Transfer the command to the interface layer */ - APP_FOPS.pIf_Ctrl(req->bRequest, NULL, 0); - } - - return USBD_OK; - - default: - USBD_CtlError (pdev, req); - return USBD_FAIL; - - /* Standard Requests -------------------------------*/ - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - USBD_CtlError (pdev, req); - return USBD_FAIL; - - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - (uint8_t *)&usbd_cdc_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) - { - usbd_cdc_AltSet = (uint8_t)(req->wValue); - } - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - break; - } - } - return USBD_OK; -} - -/** - * @brief usbd_cdc_EP0_RxReady - * Data received on control endpoint - * @param pdev: device instance - * @retval status - */ -uint8_t usbd_cdc_EP0_RxReady (void *pdev) -{ - if (cdcCmd != NO_CMD) - { - /* Process the data */ - APP_FOPS.pIf_Ctrl(cdcCmd, CmdBuff, cdcLen); - - /* Reset the command variable to default value */ - cdcCmd = NO_CMD; - } - - return USBD_OK; -} - - -/** - * @brief usbd_audio_DataIn - * Data sent on non-control IN endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum) -{ - uint16_t USB_Tx_ptr; - uint16_t USB_Tx_length; - - if (USB_Tx_State == USB_CDC_BUSY) - { - if (APP_Rx_length == 0) - { - USB_Tx_State = USB_CDC_IDLE; - } - else - { - if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE){ - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = CDC_DATA_IN_PACKET_SIZE; - - APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE; - APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE; - } - else - { - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = APP_Rx_length; - - APP_Rx_ptr_out += APP_Rx_length; - APP_Rx_length = 0; - if(USB_Tx_length == CDC_DATA_IN_PACKET_SIZE) - { - USB_Tx_State = USB_CDC_ZLP; - } - } - - /* Prepare the available data buffer to be sent on IN endpoint */ - DCD_EP_Tx (pdev, - CDC_IN_EP, - (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr], - USB_Tx_length); - return USBD_OK; - } - } - - /* Avoid any asynchronous transfer during ZLP */ - if (USB_Tx_State == USB_CDC_ZLP) - { - /*Send ZLP to indicate the end of the current transfer */ - DCD_EP_Tx (pdev, - CDC_IN_EP, - NULL, - 0); - - USB_Tx_State = USB_CDC_IDLE; - } - return USBD_OK; -} - -/** - * @brief usbd_cdc_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum) -{ - uint16_t USB_Rx_Cnt; - - /* Get the received data buffer and update the counter */ - USB_Rx_Cnt = ((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].xfer_count; - - /* USB data will be immediately processed, this allow next USB traffic being - NAKed till the end of the application Xfer */ - APP_FOPS.pIf_DataRx(USB_Rx_Buffer, USB_Rx_Cnt); - - /* Prepare Out endpoint to receive next packet */ - DCD_EP_PrepareRx(pdev, - CDC_OUT_EP, - (uint8_t*)(USB_Rx_Buffer), - CDC_DATA_OUT_PACKET_SIZE); - - return USBD_OK; -} - -/** - * @brief usbd_audio_SOF - * Start Of Frame event management - * @param pdev: instance - * @param epnum: endpoint number - * @retval status - */ -uint8_t usbd_cdc_SOF (void *pdev) -{ - static uint8_t FrameCount = 0; // modified by OpenTX - - if (FrameCount++ >= CDC_IN_FRAME_INTERVAL) // modified by OpenTX - { - /* Reset the frame counter */ - FrameCount = 0; - - /* Check the data to be sent through IN pipe */ - Handle_USBAsynchXfer(pdev); - } - - return USBD_OK; -} - -/** - * @brief Handle_USBAsynchXfer - * Send data to USB - * @param pdev: instance - * @retval None - */ -static void Handle_USBAsynchXfer (void *pdev) -{ - uint16_t USB_Tx_ptr; - uint16_t USB_Tx_length; - - if(USB_Tx_State == USB_CDC_IDLE) - { - if (APP_Rx_ptr_out == APP_RX_DATA_SIZE) - { - APP_Rx_ptr_out = 0; - } - - if(APP_Rx_ptr_out == APP_Rx_ptr_in) - { - USB_Tx_State = USB_CDC_IDLE; - return; - } - - if(APP_Rx_ptr_out > APP_Rx_ptr_in) /* rollback */ - { - APP_Rx_length = APP_RX_DATA_SIZE - APP_Rx_ptr_out; - - } - else - { - APP_Rx_length = APP_Rx_ptr_in - APP_Rx_ptr_out; - - } -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - APP_Rx_length &= ~0x03; -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - - if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE) - { - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = CDC_DATA_IN_PACKET_SIZE; - - APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE; - APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE; - USB_Tx_State = USB_CDC_BUSY; - } - else - { - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = APP_Rx_length; - - APP_Rx_ptr_out += APP_Rx_length; - APP_Rx_length = 0; - if(USB_Tx_length == CDC_DATA_IN_PACKET_SIZE) - { - USB_Tx_State = USB_CDC_ZLP; - } - else - { - USB_Tx_State = USB_CDC_BUSY; - } - } - - DCD_EP_Tx (pdev, - CDC_IN_EP, - (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr], - USB_Tx_length); - } -} - -/** - * @brief USBD_cdc_GetCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static const uint8_t * USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length) // modified by OpenTX -{ - *length = sizeof (usbd_cdc_CfgDesc); - return usbd_cdc_CfgDesc; -} - -/** - * @brief USBD_cdc_GetOtherCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -#ifdef USE_USB_OTG_HS -static uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (usbd_cdc_OtherCfgDesc); - return usbd_cdc_OtherCfgDesc; -} -#endif -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_cdc_core.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides the high layer firmware functions to manage the + * following functionalities of the USB CDC Class: + * - Initialization and Configuration of high and low layer + * - Enumeration as CDC Device (and enumeration for each implemented memory interface) + * - OUT/IN data transfer + * - Command IN transfer (class requests management) + * - Error management + * + * @verbatim + * + * =================================================================== + * CDC Class Driver Description + * =================================================================== + * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices + * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus + * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" + * This driver implements the following aspects of the specification: + * - Device descriptor management + * - Configuration descriptor management + * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) + * - Requests management (as described in section 6.2 in specification) + * - Abstract Control Model compliant + * - Union Functional collection (using 1 IN endpoint for control) + * - Data interface class + + * @note + * For the Abstract Control Model, this core allows only transmitting the requests to + * lower layer dispatcher (ie. usbd_cdc_vcp.c/.h) which should manage each request and + * perform relative actions. + * + * These aspects may be enriched or modified for a specific user application. + * + * This driver doesn't implement the following aspects of the specification + * (but it is possible to manage these features with some modifications on this driver): + * - Any class-specific aspect relative to communication classes should be managed by user application. + * - All communication classes other than PSTN are not managed + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc_core.h" +#include "usbd_desc.h" +#include "usbd_req.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup usbd_cdc + * @brief usbd core module + * @{ + */ + +/** @defgroup usbd_cdc_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup usbd_cdc_Private_Defines + * @{ + */ + +#define USB_CDC_IDLE 0 +#define USB_CDC_BUSY 1 +#define USB_CDC_ZLP 2 + +/** + * @} + */ + + +/** @defgroup usbd_cdc_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup usbd_cdc_Private_FunctionPrototypes + * @{ + */ + +/********************************************* + CDC Device library callbacks + *********************************************/ +uint8_t usbd_cdc_Init (void *pdev, uint8_t cfgidx); +uint8_t usbd_cdc_DeInit (void *pdev, uint8_t cfgidx); +uint8_t usbd_cdc_Setup (void *pdev, USB_SETUP_REQ *req); +uint8_t usbd_cdc_EP0_RxReady (void *pdev); +uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum); +uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum); +uint8_t usbd_cdc_SOF (void *pdev); + +/********************************************* + CDC specific management functions + *********************************************/ +static void Handle_USBAsynchXfer (void *pdev); +static const uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length); // modified by OpenTX +#ifdef USE_USB_OTG_HS +static uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length); +#endif +/** + * @} + */ + +/** @defgroup usbd_cdc_Private_Variables + * @{ + */ +extern const CDC_IF_Prop_TypeDef APP_FOPS; // modified my OpenTX +extern const uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; // modified by OpenTX + +// modified my OpenTX +// #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED +// #if defined ( __ICCARM__ ) /*!< IAR Compiler */ +// #pragma data_alignment=4 +// #endif +// #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +// __ALIGN_BEGIN uint8_t usbd_cdc_CfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ; + +// modified my OpenTX +// #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED +// #if defined ( __ICCARM__ ) /*!< IAR Compiler */ +// #pragma data_alignment=4 +// #endif +// #endif USB_OTG_HS_INTERNAL_DMA_ENABLED +// __ALIGN_BEGIN uint8_t usbd_cdc_OtherCfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static __IO uint32_t usbd_cdc_AltSet __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USB_Rx_Buffer [CDC_DATA_MAX_PACKET_SIZE] __ALIGN_END ; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t APP_Rx_Buffer [APP_RX_DATA_SIZE] __ALIGN_END ; + + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t CmdBuff[CDC_CMD_PACKET_SZE] __ALIGN_END ; + +volatile uint32_t APP_Rx_ptr_in = 0; // modified by OpenTX +volatile uint32_t APP_Rx_ptr_out = 0; // modified by OpenTX +uint32_t APP_Rx_length = 0; + +uint8_t USB_Tx_State = USB_CDC_IDLE; + +static uint32_t cdcCmd = 0xFF; +static uint8_t cdcLen = 0; // modified by OpenTX + +/* CDC interface class callbacks structure */ +const USBD_Class_cb_TypeDef USBD_CDC_cb = // modified by OpenTX +{ + usbd_cdc_Init, + usbd_cdc_DeInit, + usbd_cdc_Setup, + NULL, /* EP0_TxSent, */ + usbd_cdc_EP0_RxReady, + usbd_cdc_DataIn, + usbd_cdc_DataOut, + usbd_cdc_SOF, + NULL, + NULL, + USBD_cdc_GetCfgDesc, +#ifdef USE_USB_OTG_HS + USBD_cdc_GetOtherCfgDesc, /* use same cobfig as per FS */ +#endif /* USE_USB_OTG_HS */ +}; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN const uint8_t usbd_cdc_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = // modified by OpenTX +{ + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SZE), +#ifdef USE_USB_OTG_HS + 0x10, /* bInterval: */ +#else + 0xFF, /* bInterval: */ +#endif /* USE_USB_OTG_HS */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00 /* bInterval: ignore for Bulk transfer */ +} ; + +#ifdef USE_USB_OTG_HS +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN const uint8_t usbd_cdc_OtherCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = // modified by OpenTX +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_CDC_CONFIG_DESC_SIZ, + 0x00, + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SZE), + 0xFF, /* bInterval: */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00 /* bInterval */ +}; +#endif /* USE_USB_OTG_HS */ + +/** + * @} + */ + +/** @defgroup usbd_cdc_Private_Functions + * @{ + */ + +/** + * @brief usbd_cdc_Init + * Initialize the CDC interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +uint8_t usbd_cdc_Init (void *pdev, + uint8_t cfgidx) +{ + uint8_t *pbuf; + + APP_Rx_ptr_in = 0; // modified by OpenTX + APP_Rx_ptr_out = 0; // modified by OpenTX + APP_Rx_length = 0; // modified by OpenTX + USB_Tx_State = USB_CDC_IDLE; // modified by OpenTX + cdcCmd = 0xFF; // modified by OpenTX + cdcLen = 0; // modified by OpenTX + + /* Open EP IN */ + DCD_EP_Open(pdev, + CDC_IN_EP, + CDC_DATA_IN_PACKET_SIZE, + USB_OTG_EP_BULK); + + /* Open EP OUT */ + DCD_EP_Open(pdev, + CDC_OUT_EP, + CDC_DATA_OUT_PACKET_SIZE, + USB_OTG_EP_BULK); + + /* Open Command IN EP */ + DCD_EP_Open(pdev, + CDC_CMD_EP, + CDC_CMD_PACKET_SZE, + USB_OTG_EP_INT); + + pbuf = (uint8_t *)USBD_DeviceDesc; + pbuf[4] = DEVICE_CLASS_CDC; + pbuf[5] = DEVICE_SUBCLASS_CDC; + + /* Initialize the Interface physical components */ + APP_FOPS.pIf_Init(); + + /* Prepare Out endpoint to receive next packet */ + DCD_EP_PrepareRx(pdev, + CDC_OUT_EP, + (uint8_t*)(USB_Rx_Buffer), + CDC_DATA_OUT_PACKET_SIZE); + + return USBD_OK; +} + +/** + * @brief usbd_cdc_Init + * DeInitialize the CDC layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +uint8_t usbd_cdc_DeInit (void *pdev, + uint8_t cfgidx) +{ + /* Open EP IN */ + DCD_EP_Close(pdev, + CDC_IN_EP); + + /* Open EP OUT */ + DCD_EP_Close(pdev, + CDC_OUT_EP); + + /* Open Command IN EP */ + DCD_EP_Close(pdev, + CDC_CMD_EP); + + /* Restore default state of the Interface physical components */ + APP_FOPS.pIf_DeInit(); + + return USBD_OK; +} + +/** + * @brief usbd_cdc_Setup + * Handle the CDC specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +uint8_t usbd_cdc_Setup (void *pdev, + USB_SETUP_REQ *req) +{ + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + /* CDC Class Requests -------------------------------*/ + case USB_REQ_TYPE_CLASS : + /* Check if the request is a data setup packet */ + if (req->wLength) + { + /* Check if the request is Device-to-Host */ + if (req->bmRequest & 0x80) + { + /* Get the data to be sent to Host from interface layer */ + APP_FOPS.pIf_Ctrl(req->bRequest, CmdBuff, req->wLength); + + /* Send the data to the host */ + USBD_CtlSendData (pdev, + CmdBuff, + req->wLength); + } + else /* Host-to-Device request */ + { + /* Set the value of the current command to be processed */ + cdcCmd = req->bRequest; + cdcLen = req->wLength; + + /* Prepare the reception of the buffer over EP0 + Next step: the received data will be managed in usbd_cdc_EP0_TxSent() + function. */ + USBD_CtlPrepareRx (pdev, + CmdBuff, + req->wLength); + } + } + else /* No Data request */ + { + /* Transfer the command to the interface layer */ + APP_FOPS.pIf_Ctrl(req->bRequest, NULL, 0); + } + + return USBD_OK; + + default: + USBD_CtlError (pdev, req); + return USBD_FAIL; + + /* Standard Requests -------------------------------*/ + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + USBD_CtlError (pdev, req); + return USBD_FAIL; + + case USB_REQ_GET_INTERFACE : + USBD_CtlSendData (pdev, + (uint8_t *)&usbd_cdc_AltSet, + 1); + break; + + case USB_REQ_SET_INTERFACE : + if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) + { + usbd_cdc_AltSet = (uint8_t)(req->wValue); + } + else + { + /* Call the error management function (command will be nacked */ + USBD_CtlError (pdev, req); + } + break; + } + } + return USBD_OK; +} + +/** + * @brief usbd_cdc_EP0_RxReady + * Data received on control endpoint + * @param pdev: device instance + * @retval status + */ +uint8_t usbd_cdc_EP0_RxReady (void *pdev) +{ + if (cdcCmd != NO_CMD) + { + /* Process the data */ + APP_FOPS.pIf_Ctrl(cdcCmd, CmdBuff, cdcLen); + + /* Reset the command variable to default value */ + cdcCmd = NO_CMD; + } + + return USBD_OK; +} + + +/** + * @brief usbd_audio_DataIn + * Data sent on non-control IN endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum) +{ + uint16_t USB_Tx_ptr; + uint16_t USB_Tx_length; + + if (USB_Tx_State == USB_CDC_BUSY) + { + if (APP_Rx_length == 0) + { + USB_Tx_State = USB_CDC_IDLE; + } + else + { + if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE){ + USB_Tx_ptr = APP_Rx_ptr_out; + USB_Tx_length = CDC_DATA_IN_PACKET_SIZE; + + APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE; + APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE; + } + else + { + USB_Tx_ptr = APP_Rx_ptr_out; + USB_Tx_length = APP_Rx_length; + + APP_Rx_ptr_out += APP_Rx_length; + APP_Rx_length = 0; + if(USB_Tx_length == CDC_DATA_IN_PACKET_SIZE) + { + USB_Tx_State = USB_CDC_ZLP; + } + } + + /* Prepare the available data buffer to be sent on IN endpoint */ + DCD_EP_Tx (pdev, + CDC_IN_EP, + (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr], + USB_Tx_length); + return USBD_OK; + } + } + + /* Avoid any asynchronous transfer during ZLP */ + if (USB_Tx_State == USB_CDC_ZLP) + { + /*Send ZLP to indicate the end of the current transfer */ + DCD_EP_Tx (pdev, + CDC_IN_EP, + NULL, + 0); + + USB_Tx_State = USB_CDC_IDLE; + } + return USBD_OK; +} + +/** + * @brief usbd_cdc_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum) +{ + uint16_t USB_Rx_Cnt; + + /* Get the received data buffer and update the counter */ + USB_Rx_Cnt = ((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].xfer_count; + + /* USB data will be immediately processed, this allow next USB traffic being + NAKed till the end of the application Xfer */ + APP_FOPS.pIf_DataRx(USB_Rx_Buffer, USB_Rx_Cnt); + + /* Prepare Out endpoint to receive next packet */ + DCD_EP_PrepareRx(pdev, + CDC_OUT_EP, + (uint8_t*)(USB_Rx_Buffer), + CDC_DATA_OUT_PACKET_SIZE); + + return USBD_OK; +} + +/** + * @brief usbd_audio_SOF + * Start Of Frame event management + * @param pdev: instance + * @param epnum: endpoint number + * @retval status + */ +uint8_t usbd_cdc_SOF (void *pdev) +{ + static uint8_t FrameCount = 0; // modified by OpenTX + + if (FrameCount++ >= CDC_IN_FRAME_INTERVAL) // modified by OpenTX + { + /* Reset the frame counter */ + FrameCount = 0; + + /* Check the data to be sent through IN pipe */ + Handle_USBAsynchXfer(pdev); + } + + return USBD_OK; +} + +/** + * @brief Handle_USBAsynchXfer + * Send data to USB + * @param pdev: instance + * @retval None + */ +static void Handle_USBAsynchXfer (void *pdev) +{ + uint16_t USB_Tx_ptr; + uint16_t USB_Tx_length; + + if(USB_Tx_State == USB_CDC_IDLE) + { + if (APP_Rx_ptr_out == APP_RX_DATA_SIZE) + { + APP_Rx_ptr_out = 0; + } + + if(APP_Rx_ptr_out == APP_Rx_ptr_in) + { + USB_Tx_State = USB_CDC_IDLE; + return; + } + + if(APP_Rx_ptr_out > APP_Rx_ptr_in) /* rollback */ + { + APP_Rx_length = APP_RX_DATA_SIZE - APP_Rx_ptr_out; + + } + else + { + APP_Rx_length = APP_Rx_ptr_in - APP_Rx_ptr_out; + + } +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + APP_Rx_length &= ~0x03; +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + + if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE) + { + USB_Tx_ptr = APP_Rx_ptr_out; + USB_Tx_length = CDC_DATA_IN_PACKET_SIZE; + + APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE; + APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE; + USB_Tx_State = USB_CDC_BUSY; + } + else + { + USB_Tx_ptr = APP_Rx_ptr_out; + USB_Tx_length = APP_Rx_length; + + APP_Rx_ptr_out += APP_Rx_length; + APP_Rx_length = 0; + if(USB_Tx_length == CDC_DATA_IN_PACKET_SIZE) + { + USB_Tx_State = USB_CDC_ZLP; + } + else + { + USB_Tx_State = USB_CDC_BUSY; + } + } + + DCD_EP_Tx (pdev, + CDC_IN_EP, + (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr], + USB_Tx_length); + } +} + +/** + * @brief USBD_cdc_GetCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static const uint8_t * USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length) // modified by OpenTX +{ + *length = sizeof (usbd_cdc_CfgDesc); + return usbd_cdc_CfgDesc; +} + +/** + * @brief USBD_cdc_GetOtherCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +#ifdef USE_USB_OTG_HS +static uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (usbd_cdc_OtherCfgDesc); + return usbd_cdc_OtherCfgDesc; +} +#endif +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_if_template.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_if_template.c index 698cc72f7..edba3eefa 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_if_template.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_if_template.c @@ -1,207 +1,207 @@ -/** - ****************************************************************************** - * @file usbd_cdc_if_template.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Generic media access Layer. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED -#pragma data_alignment = 4 -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc_if_template.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* These are external variables imported from CDC core to be used for IN - transfer management. */ -extern uint8_t APP_Rx_Buffer []; /* Write CDC received data in this buffer. - These data will be sent over USB IN endpoint - in the CDC core functions. */ -extern uint32_t APP_Rx_ptr_in; /* Increment this pointer or roll it back to - start address when writing received data - in the buffer APP_Rx_Buffer. */ - -/* Private function prototypes -----------------------------------------------*/ -static uint16_t TEMPLATE_Init (void); -static uint16_t TEMPLATE_DeInit (void); -static uint16_t TEMPLATE_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len); -static uint16_t TEMPLATE_DataTx (uint8_t* Buf, uint32_t Len); -static uint16_t TEMPLATE_DataRx (uint8_t* Buf, uint32_t Len); - -CDC_IF_Prop_TypeDef TEMPLATE_fops = -{ - TEMPLATE_Init, - TEMPLATE_DeInit, - TEMPLATE_Ctrl, - TEMPLATE_DataTx, - TEMPLATE_DataRx -}; - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief TEMPLATE_Init - * Initializes the CDC media low layer - * @param None - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL - */ -static uint16_t TEMPLATE_Init(void) -{ - /* - Add your initialization code here - */ - return USBD_OK; -} - -/** - * @brief TEMPLATE_DeInit - * DeInitializes the CDC media low layer - * @param None - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL - */ -static uint16_t TEMPLATE_DeInit(void) -{ - /* - Add your deinitialization code here - */ - return USBD_OK; -} - - -/** - * @brief TEMPLATE_Ctrl - * Manage the CDC class requests - * @param Cmd: Command code - * @param Buf: Buffer containing command data (request parameters) - * @param Len: Number of data to be sent (in bytes) - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL - */ -static uint16_t TEMPLATE_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len) -{ - switch (Cmd) - { - case SEND_ENCAPSULATED_COMMAND: - /* Add your code here */ - break; - - case GET_ENCAPSULATED_RESPONSE: - /* Add your code here */ - break; - - case SET_COMM_FEATURE: - /* Add your code here */ - break; - - case GET_COMM_FEATURE: - /* Add your code here */ - break; - - case CLEAR_COMM_FEATURE: - /* Add your code here */ - break; - - case SET_LINE_CODING: - /* Add your code here */ - break; - - case GET_LINE_CODING: - /* Add your code here */ - break; - - case SET_CONTROL_LINE_STATE: - /* Add your code here */ - break; - - case SEND_BREAK: - /* Add your code here */ - break; - - default: - break; - } - - return USBD_OK; -} - -/** - * @brief TEMPLATE_DataTx - * CDC received data to be send over USB IN endpoint are managed in - * this function. - * @param Buf: Buffer of data to be sent - * @param Len: Number of data to be sent (in bytes) - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL - */ -static uint16_t TEMPLATE_DataTx (uint8_t* Buf, uint32_t Len) -{ - - /* Get the data to be sent */ - for (i = 0; i < Len; i++) - { - /* APP_Rx_Buffer[APP_Rx_ptr_in] = XXX_ReceiveData(XXX); */ - } - - /* Increment the in pointer */ - APP_Rx_ptr_in++; - - /* To avoid buffer overflow */ - if(APP_Rx_ptr_in == APP_RX_DATA_SIZE) - { - APP_Rx_ptr_in = 0; - } - - return USBD_OK; -} - -/** - * @brief TEMPLATE_DataRx - * Data received over USB OUT endpoint are sent over CDC interface - * through this function. - * - * @note - * This function will block any OUT packet reception on USB endpoint - * untill exiting this function. If you exit this function before transfer - * is complete on CDC interface (ie. using DMA controller) it will result - * in receiving more data while previous ones are still not sent. - * - * @param Buf: Buffer of data to be received - * @param Len: Number of data received (in bytes) - * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL - */ -static uint16_t TEMPLATE_DataRx (uint8_t* Buf, uint32_t Len) -{ - uint32_t i; - - /* Send the received buffer */ - for (i = 0; i < Len; i++) - { - /* XXXX_SendData(XXXX, *(Buf + i) ); */ - } - - return USBD_OK; -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_cdc_if_template.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Generic media access Layer. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED +#pragma data_alignment = 4 +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc_if_template.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* These are external variables imported from CDC core to be used for IN + transfer management. */ +extern uint8_t APP_Rx_Buffer []; /* Write CDC received data in this buffer. + These data will be sent over USB IN endpoint + in the CDC core functions. */ +extern uint32_t APP_Rx_ptr_in; /* Increment this pointer or roll it back to + start address when writing received data + in the buffer APP_Rx_Buffer. */ + +/* Private function prototypes -----------------------------------------------*/ +static uint16_t TEMPLATE_Init (void); +static uint16_t TEMPLATE_DeInit (void); +static uint16_t TEMPLATE_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len); +static uint16_t TEMPLATE_DataTx (uint8_t* Buf, uint32_t Len); +static uint16_t TEMPLATE_DataRx (uint8_t* Buf, uint32_t Len); + +CDC_IF_Prop_TypeDef TEMPLATE_fops = +{ + TEMPLATE_Init, + TEMPLATE_DeInit, + TEMPLATE_Ctrl, + TEMPLATE_DataTx, + TEMPLATE_DataRx +}; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief TEMPLATE_Init + * Initializes the CDC media low layer + * @param None + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static uint16_t TEMPLATE_Init(void) +{ + /* + Add your initialization code here + */ + return USBD_OK; +} + +/** + * @brief TEMPLATE_DeInit + * DeInitializes the CDC media low layer + * @param None + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static uint16_t TEMPLATE_DeInit(void) +{ + /* + Add your deinitialization code here + */ + return USBD_OK; +} + + +/** + * @brief TEMPLATE_Ctrl + * Manage the CDC class requests + * @param Cmd: Command code + * @param Buf: Buffer containing command data (request parameters) + * @param Len: Number of data to be sent (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static uint16_t TEMPLATE_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len) +{ + switch (Cmd) + { + case SEND_ENCAPSULATED_COMMAND: + /* Add your code here */ + break; + + case GET_ENCAPSULATED_RESPONSE: + /* Add your code here */ + break; + + case SET_COMM_FEATURE: + /* Add your code here */ + break; + + case GET_COMM_FEATURE: + /* Add your code here */ + break; + + case CLEAR_COMM_FEATURE: + /* Add your code here */ + break; + + case SET_LINE_CODING: + /* Add your code here */ + break; + + case GET_LINE_CODING: + /* Add your code here */ + break; + + case SET_CONTROL_LINE_STATE: + /* Add your code here */ + break; + + case SEND_BREAK: + /* Add your code here */ + break; + + default: + break; + } + + return USBD_OK; +} + +/** + * @brief TEMPLATE_DataTx + * CDC received data to be send over USB IN endpoint are managed in + * this function. + * @param Buf: Buffer of data to be sent + * @param Len: Number of data to be sent (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static uint16_t TEMPLATE_DataTx (uint8_t* Buf, uint32_t Len) +{ + + /* Get the data to be sent */ + for (i = 0; i < Len; i++) + { + /* APP_Rx_Buffer[APP_Rx_ptr_in] = XXX_ReceiveData(XXX); */ + } + + /* Increment the in pointer */ + APP_Rx_ptr_in++; + + /* To avoid buffer overflow */ + if(APP_Rx_ptr_in == APP_RX_DATA_SIZE) + { + APP_Rx_ptr_in = 0; + } + + return USBD_OK; +} + +/** + * @brief TEMPLATE_DataRx + * Data received over USB OUT endpoint are sent over CDC interface + * through this function. + * + * @note + * This function will block any OUT packet reception on USB endpoint + * untill exiting this function. If you exit this function before transfer + * is complete on CDC interface (ie. using DMA controller) it will result + * in receiving more data while previous ones are still not sent. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL + */ +static uint16_t TEMPLATE_DataRx (uint8_t* Buf, uint32_t Len) +{ + uint32_t i; + + /* Send the received buffer */ + for (i = 0; i < Len; i++) + { + /* XXXX_SendData(XXXX, *(Buf + i) ); */ + } + + return USBD_OK; +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/customhid/inc/usbd_customhid_core.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/customhid/inc/usbd_customhid_core.h index fb2c79bd1..b126cc1b2 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/customhid/inc/usbd_customhid_core.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/customhid/inc/usbd_customhid_core.h @@ -1,129 +1,129 @@ -/** - ****************************************************************************** - * @file usbd_customhid_core.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header file for the usbd_customhid_core.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_CUSTOMHID_CORE_H_ -#define __USB_CUSTOMHID_CORE_H_ - -#include "usbd_ioreq.h" -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_CUSTOMHID - * @brief This file is the Header file for usbd_customhid_core.c - * @{ - */ - - -/** @defgroup USBD_CUSTOMHID_Exported_Defines - * @{ - */ -#define USBD_CUSTOM_HID_REPORT_DESC_SIZE 163 - -#define USB_CUSTOM_HID_CONFIG_DESC_SIZ 41 -#define USB_CUSTOM_HID_DESC_SIZ 9 - -#define CUSTOM_HID_DESCRIPTOR_TYPE 0x21 -#define CUSTOM_HID_REPORT_DESC 0x22 - - -#define CUSTOM_HID_REQ_SET_PROTOCOL 0x0B -#define CUSTOM_HID_REQ_GET_PROTOCOL 0x03 - -#define CUSTOM_HID_REQ_SET_IDLE 0x0A -#define CUSTOM_HID_REQ_GET_IDLE 0x02 - -#define CUSTOM_HID_REQ_SET_REPORT 0x09 -#define CUSTOM_HID_REQ_GET_REPORT 0x01 - -#define LED1_REPORT_ID 0x01 -#define LED1_REPORT_COUNT 0x01 - -#define LED2_REPORT_ID 0x02 -#define LED2_REPORT_COUNT 0x01 - -#define LED3_REPORT_ID 0x03 -#define LED3_REPORT_COUNT 0x01 - -#define LED4_REPORT_ID 0x04 -#define LED4_REPORT_COUNT 0x01 - -#define KEY_REPORT_ID 0x05 -#define TAMPER_REPORT_ID 0x06 -#define ADC_REPORT_ID 0x07 -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ -extern USBD_Class_cb_TypeDef USBD_CUSTOMHID_cb; -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -uint8_t USBD_CUSTOM_HID_SendReport (USB_OTG_CORE_HANDLE *pdev, - uint8_t *report, - uint16_t len); -/** - * @} - */ - -#endif /* __USB_CUSTOMHID_CORE_H_ */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_customhid_core.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header file for the usbd_customhid_core.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +#ifndef __USB_CUSTOMHID_CORE_H_ +#define __USB_CUSTOMHID_CORE_H_ + +#include "usbd_ioreq.h" +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_CUSTOMHID + * @brief This file is the Header file for usbd_customhid_core.c + * @{ + */ + + +/** @defgroup USBD_CUSTOMHID_Exported_Defines + * @{ + */ +#define USBD_CUSTOM_HID_REPORT_DESC_SIZE 163 + +#define USB_CUSTOM_HID_CONFIG_DESC_SIZ 41 +#define USB_CUSTOM_HID_DESC_SIZ 9 + +#define CUSTOM_HID_DESCRIPTOR_TYPE 0x21 +#define CUSTOM_HID_REPORT_DESC 0x22 + + +#define CUSTOM_HID_REQ_SET_PROTOCOL 0x0B +#define CUSTOM_HID_REQ_GET_PROTOCOL 0x03 + +#define CUSTOM_HID_REQ_SET_IDLE 0x0A +#define CUSTOM_HID_REQ_GET_IDLE 0x02 + +#define CUSTOM_HID_REQ_SET_REPORT 0x09 +#define CUSTOM_HID_REQ_GET_REPORT 0x01 + +#define LED1_REPORT_ID 0x01 +#define LED1_REPORT_COUNT 0x01 + +#define LED2_REPORT_ID 0x02 +#define LED2_REPORT_COUNT 0x01 + +#define LED3_REPORT_ID 0x03 +#define LED3_REPORT_COUNT 0x01 + +#define LED4_REPORT_ID 0x04 +#define LED4_REPORT_COUNT 0x01 + +#define KEY_REPORT_ID 0x05 +#define TAMPER_REPORT_ID 0x06 +#define ADC_REPORT_ID 0x07 +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ +extern USBD_Class_cb_TypeDef USBD_CUSTOMHID_cb; +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +uint8_t USBD_CUSTOM_HID_SendReport (USB_OTG_CORE_HANDLE *pdev, + uint8_t *report, + uint16_t len); +/** + * @} + */ + +#endif /* __USB_CUSTOMHID_CORE_H_ */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/customhid/src/usbd_customhid_core.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/customhid/src/usbd_customhid_core.c index 3e90d7a7a..bfb311f39 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/customhid/src/usbd_customhid_core.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/customhid/src/usbd_customhid_core.c @@ -1,718 +1,718 @@ -/** - ****************************************************************************** - * @file usbd_customhid_core.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides the CUSTOM_HID core functions. - * - * @verbatim - * - * =================================================================== - * CUSTOM_HID Class Description - * =================================================================== - * This module manages the HID class V1.11 following the "Device Class Definition - * for Human Interface Devices (CUSTOM_HID) Version 1.11 Jun 27, 2001". - * This driver implements the following aspects of the specification: - * - The Boot Interface Subclass - * - The Mouse protocol - * - Usage Page : Generic Desktop - * - Usage : Vendor - * - Collection : Application - * - * @note In HS mode and when the DMA is used, all variables and data structures - * dealing with the DMA during the transaction process should be 32-bit aligned. - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_customhid_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_CUSTOM_HID - * @brief usbd core module - * @{ - */ - -/** @defgroup USBD_CUSTOM_HID_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_CUSTOM_HID_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_CUSTOM_HID_Private_Macros - * @{ - */ -/** - * @} - */ - - - - -/** @defgroup USBD_CUSTOM_HID_Private_FunctionPrototypes - * @{ - */ - - -static uint8_t USBD_CUSTOM_HID_Init (void *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CUSTOM_HID_DeInit (void *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CUSTOM_HID_Setup (void *pdev, - USB_SETUP_REQ *req); - -static uint8_t *USBD_CUSTOM_HID_GetCfgDesc (uint8_t speed, uint16_t *length); - -static uint8_t USBD_CUSTOM_HID_DataIn (void *pdev, uint8_t epnum); -static uint8_t USBD_CUSTOM_HID_DataOut (void *pdev, uint8_t epnum); -static uint8_t USBD_CUSTOM_HID_EP0_RxReady (void *pdev); -/** - * @} - */ - -/** @defgroup USBD_HID_Private_Variables - * @{ - */ - -USBD_Class_cb_TypeDef USBD_CUSTOMHID_cb = -{ - USBD_CUSTOM_HID_Init, - USBD_CUSTOM_HID_DeInit, - USBD_CUSTOM_HID_Setup, - NULL, /*EP0_TxSent*/ - USBD_CUSTOM_HID_EP0_RxReady, /*EP0_RxReady*/ /* STATUS STAGE IN */ - USBD_CUSTOM_HID_DataIn, /*DataIn*/ - USBD_CUSTOM_HID_DataOut, - NULL, /*SOF */ - NULL, - NULL, - USBD_CUSTOM_HID_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_CUSTOM_HID_GetCfgDesc, /* use same config as per FS */ -#endif -}; - -uint8_t Report_buf[2]; -uint8_t USBD_HID_Report_ID=0; -__IO uint32_t IsReportAvailable = 0; -extern uint8_t PrevXferDone; - - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_AltSet __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_Protocol __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_IdleState __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB HID device Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_CfgDesc[USB_CUSTOM_HID_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ - USB_CUSTOM_HID_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ - 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xC0, /*bmAttributes: bus powered and Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - - /************** Descriptor of Custom HID interface ****************/ - /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ - 0x00, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x02, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x00, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x00, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ - /******************** Descriptor of Custom HID ********************/ - /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ - 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ - 0x00, - /******************** Descriptor of Custom HID endpoints ***********/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ - - HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_IN_PACKET, /* wMaxPacketSize: 2 Bytes max */ - 0x00, - 0x20, /* bInterval: Polling Interval (32 ms) */ - /* 34 */ - - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ - /* Endpoint descriptor type */ - HID_OUT_EP, /* bEndpointAddress: */ - /* Endpoint Address (OUT) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_OUT_PACKET, /* wMaxPacketSize: 2 Bytes max */ - 0x00, - 0x20, /* bInterval: Polling Interval (20 ms) */ - /* 41 */ -} ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif - -__ALIGN_BEGIN static uint8_t CustomHID_ReportDesc[USBD_CUSTOM_HID_REPORT_DESC_SIZE] __ALIGN_END = -{ - 0x06, 0xFF, 0x00, /* USAGE_PAGE (Vendor Page: 0xFF00) */ - 0x09, 0x01, /* USAGE (Demo Kit) */ - 0xa1, 0x01, /* COLLECTION (Application) */ - /* 6 */ - - /* Led 1 */ - 0x85, LED1_REPORT_ID, /* REPORT_ID (1) */ - 0x09, 0x01, /* USAGE (LED 1) */ - 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ - 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ - 0x75, 0x08, /* REPORT_SIZE (8) */ - 0x95, LED1_REPORT_COUNT, /* REPORT_COUNT (1) */ - 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ - - 0x85, LED1_REPORT_ID, /* REPORT_ID (1) */ - 0x09, 0x01, /* USAGE (LED 1) */ - 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ - /* 26 */ - - /* Led 2 */ - 0x85, LED2_REPORT_ID, /* REPORT_ID 2 */ - 0x09, 0x02, /* USAGE (LED 2) */ - 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ - 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ - 0x75, 0x08, /* REPORT_SIZE (8) */ - 0x95, LED2_REPORT_COUNT, /* REPORT_COUNT (1) */ - 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ - - 0x85, LED2_REPORT_ID, /* REPORT_ID (2) */ - 0x09, 0x02, /* USAGE (LED 2) */ - 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ - /* 46 */ - - /* Led 3 */ - 0x85, LED3_REPORT_ID, /* REPORT_ID (3) */ - 0x09, 0x03, /* USAGE (LED 3) */ - 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ - 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ - 0x75, 0x08, /* REPORT_SIZE (8) */ - 0x95, LED3_REPORT_COUNT, /* REPORT_COUNT (1) */ - 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ - - 0x85, LED3_REPORT_ID, /* REPORT_ID (3) */ - 0x09, 0x03, /* USAGE (LED 3) */ - 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ - /* 66 */ - - /* Led 4 */ - 0x85, LED4_REPORT_ID, /* REPORT_ID 4) */ - 0x09, 0x04, /* USAGE (LED 4) */ - 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ - 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ - 0x75, 0x08, /* REPORT_SIZE (8) */ - 0x95, LED4_REPORT_COUNT, /* REPORT_COUNT (1) */ - 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ - - 0x85, LED4_REPORT_ID, /* REPORT_ID (4) */ - 0x09, 0x04, /* USAGE (LED 4) */ - 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ - /* 86 */ - - /* key Push Button */ - 0x85, KEY_REPORT_ID, /* REPORT_ID (5) */ - 0x09, 0x05, /* USAGE (Push Button) */ - 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ - 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ - 0x75, 0x01, /* REPORT_SIZE (1) */ - 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */ - - 0x09, 0x05, /* USAGE (Push Button) */ - 0x75, 0x01, /* REPORT_SIZE (1) */ - 0xb1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ - - 0x75, 0x07, /* REPORT_SIZE (7) */ - 0x81, 0x83, /* INPUT (Cnst,Var,Abs,Vol) */ - 0x85, KEY_REPORT_ID, /* REPORT_ID (2) */ - - 0x75, 0x07, /* REPORT_SIZE (7) */ - 0xb1, 0x83, /* FEATURE (Cnst,Var,Abs,Vol) */ - /* 114 */ - - /* Tamper Push Button */ - 0x85, TAMPER_REPORT_ID,/* REPORT_ID (6) */ - 0x09, 0x06, /* USAGE (Tamper Push Button) */ - 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ - 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ - 0x75, 0x01, /* REPORT_SIZE (1) */ - 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */ - - 0x09, 0x06, /* USAGE (Tamper Push Button) */ - 0x75, 0x01, /* REPORT_SIZE (1) */ - 0xb1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ - - 0x75, 0x07, /* REPORT_SIZE (7) */ - 0x81, 0x83, /* INPUT (Cnst,Var,Abs,Vol) */ - 0x85, TAMPER_REPORT_ID,/* REPORT_ID (6) */ - - 0x75, 0x07, /* REPORT_SIZE (7) */ - 0xb1, 0x83, /* FEATURE (Cnst,Var,Abs,Vol) */ - /* 142 */ - - /* ADC IN */ - 0x85, ADC_REPORT_ID, /* REPORT_ID */ - 0x09, 0x07, /* USAGE (ADC IN) */ - 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ - 0x26, 0xff, 0x00, /* LOGICAL_MAXIMUM (255) */ - 0x75, 0x08, /* REPORT_SIZE (8) */ - 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */ - 0x85, ADC_REPORT_ID, /* REPORT_ID (7) */ - 0x09, 0x07, /* USAGE (ADC in) */ - 0xb1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ - /* 161 */ - - 0xc0 /* END_COLLECTION */ -}; - -/** - * @} - */ - -/** @defgroup USBD_HID_Private_Functions - * @{ - */ - -/** - * @brief USBD_HID_Init - * Initialize the HID interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_CUSTOM_HID_Init (void *pdev, - uint8_t cfgidx) -{ - /* Open EP IN */ - DCD_EP_Open(pdev, - HID_IN_EP, - HID_IN_PACKET, - USB_OTG_EP_INT); - - /* Open EP OUT */ - DCD_EP_Open(pdev, - HID_OUT_EP, - HID_OUT_PACKET, - USB_OTG_EP_INT); - - /*Receive Data*/ - DCD_EP_PrepareRx(pdev,HID_OUT_EP,Report_buf,2); - - return USBD_OK; -} - -/** - * @brief USBD_HID_Init - * DeInitialize the HID layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_CUSTOM_HID_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* Close HID EPs */ - DCD_EP_Close (pdev , HID_IN_EP); - DCD_EP_Close (pdev , HID_OUT_EP); - - - return USBD_OK; -} - -/** - * @brief USBD_HID_Setup - * Handle the HID specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t USBD_CUSTOM_HID_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - uint8_t USBD_HID_Report_LENGTH=0; - uint16_t len = 0; - uint8_t *pbuf = NULL; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - case CUSTOM_HID_REQ_SET_PROTOCOL: - USBD_HID_Protocol = (uint8_t)(req->wValue); - break; - - case CUSTOM_HID_REQ_GET_PROTOCOL: - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_Protocol, - 1); - break; - - case CUSTOM_HID_REQ_SET_IDLE: - USBD_HID_IdleState = (uint8_t)(req->wValue >> 8); - break; - - case CUSTOM_HID_REQ_GET_IDLE: - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_IdleState, - 1); - break; - - case CUSTOM_HID_REQ_SET_REPORT: - IsReportAvailable = 1; - USBD_HID_Report_ID = (uint8_t)(req->wValue); - USBD_HID_Report_LENGTH = (uint8_t)(req->wLength); - USBD_CtlPrepareRx (pdev, Report_buf, USBD_HID_Report_LENGTH); - - break; - - default: - USBD_CtlError (pdev, req); - return USBD_FAIL; - } - break; - - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - if( req->wValue >> 8 == CUSTOM_HID_REPORT_DESC) - { - len = MIN(USBD_CUSTOM_HID_REPORT_DESC_SIZE , req->wLength); - pbuf = (uint8_t*)CustomHID_ReportDesc; - } - else if( req->wValue >> 8 == CUSTOM_HID_DESCRIPTOR_TYPE) - { - pbuf = (uint8_t*)USBD_CUSTOM_HID_CfgDesc + 0x12; - len = MIN(USB_CUSTOM_HID_DESC_SIZ , req->wLength); - } - - USBD_CtlSendData (pdev, - pbuf, - len); - - break; - - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - USBD_HID_AltSet = (uint8_t)(req->wValue); - break; - } - } - return USBD_OK; -} - -/** - * @brief USBD_HID_SendReport - * Send HID Report - * @param pdev: device instance - * @param buff: pointer to report - * @retval status - */ -uint8_t USBD_CUSTOM_HID_SendReport (USB_OTG_CORE_HANDLE *pdev, - uint8_t *report, - uint16_t len) -{ - if (pdev->dev.device_status == USB_OTG_CONFIGURED ) - { - DCD_EP_Tx (pdev, HID_IN_EP, report, len); - } - return USBD_OK; -} - -/** - * @brief USBD_HID_GetCfgDesc - * return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_CUSTOM_HID_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (USBD_CUSTOM_HID_CfgDesc); - return USBD_CUSTOM_HID_CfgDesc; -} - -/** - * @brief USBD_HID_DataIn - * handle data IN Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_CUSTOM_HID_DataIn (void *pdev, - uint8_t epnum) -{ - - /* Ensure that the FIFO is empty before a new transfer, this condition could - be caused by a new transfer before the end of the previous transfer */ - DCD_EP_Flush(pdev, HID_IN_EP); - - if (epnum == 1) PrevXferDone = 1; - - return USBD_OK; -} - -/** - * @brief USBD_HID_DataOut - * handle data IN Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -uint8_t USBD_CUSTOM_HID_DataOut (void *pdev, - uint8_t epnum) -{ - - BitAction Led_State; - if (epnum == 1) - { - if (Report_buf[1] == 0) - { - Led_State = Bit_RESET; - } - else - { - Led_State = Bit_SET; - } - - switch (Report_buf[0]) - { - case 1: /* Led 1 */ - if (Led_State != Bit_RESET) - { - STM_EVAL_LEDOn(LED1); - } - else - { - STM_EVAL_LEDOff(LED1); - } - break; - - case 2: /* Led 2 */ - if (Led_State != Bit_RESET) - { - STM_EVAL_LEDOn(LED2); - } - else - { - STM_EVAL_LEDOff(LED2); - } - break; - case 3: /* Led 3 */ - if (Led_State != Bit_RESET) - { - STM_EVAL_LEDOn(LED3); - } - else - { - STM_EVAL_LEDOff(LED3); - } - break; - case 4: /* Led 4 */ - if (Led_State != Bit_RESET) - { - STM_EVAL_LEDOn(LED4); - } - else - { - STM_EVAL_LEDOff(LED4); - } - break; - default: - STM_EVAL_LEDOff(LED1); - STM_EVAL_LEDOff(LED2); - STM_EVAL_LEDOff(LED3); - STM_EVAL_LEDOff(LED4); - break; - } - } - - DCD_EP_PrepareRx(pdev,HID_IN_EP,Report_buf,2); - - return USBD_OK; -} - -/** - * @brief USBD_HID_EP0_RxReady - * Handles control request data. - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ - -uint8_t USBD_CUSTOM_HID_EP0_RxReady(void *pdev) -{ - BitAction Led_State; - - if (IsReportAvailable == 1) - { - IsReportAvailable = 0; - if (Report_buf[1] == 0) - { - Led_State = Bit_RESET; - } - else - { - Led_State = Bit_SET; - } - - switch (Report_buf[0]) - { - case 1: /* Led 1 */ - if (Led_State != Bit_RESET) - { - STM_EVAL_LEDOn(LED1); - } - else - { - STM_EVAL_LEDOff(LED1); - } - break; - - case 2: /* Led 2 */ - if (Led_State != Bit_RESET) - { - STM_EVAL_LEDOn(LED2); - } - else - { - STM_EVAL_LEDOff(LED2); - } - break; - case 3: /* Led 3 */ - if (Led_State != Bit_RESET) - { - STM_EVAL_LEDOn(LED3); - } - else - { - STM_EVAL_LEDOff(LED3); - } - break; - case 4: /* Led 4 */ - if (Led_State != Bit_RESET) - { - STM_EVAL_LEDOn(LED4); - } - else - { - STM_EVAL_LEDOff(LED4); - } - break; - default: - STM_EVAL_LEDOff(LED1); - STM_EVAL_LEDOff(LED2); - STM_EVAL_LEDOff(LED3); - STM_EVAL_LEDOff(LED4); - break; - } - } - return USBD_OK; -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_customhid_core.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides the CUSTOM_HID core functions. + * + * @verbatim + * + * =================================================================== + * CUSTOM_HID Class Description + * =================================================================== + * This module manages the HID class V1.11 following the "Device Class Definition + * for Human Interface Devices (CUSTOM_HID) Version 1.11 Jun 27, 2001". + * This driver implements the following aspects of the specification: + * - The Boot Interface Subclass + * - The Mouse protocol + * - Usage Page : Generic Desktop + * - Usage : Vendor + * - Collection : Application + * + * @note In HS mode and when the DMA is used, all variables and data structures + * dealing with the DMA during the transaction process should be 32-bit aligned. + * + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_customhid_core.h" +#include "usbd_desc.h" +#include "usbd_req.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_CUSTOM_HID + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_CUSTOM_HID_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CUSTOM_HID_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CUSTOM_HID_Private_Macros + * @{ + */ +/** + * @} + */ + + + + +/** @defgroup USBD_CUSTOM_HID_Private_FunctionPrototypes + * @{ + */ + + +static uint8_t USBD_CUSTOM_HID_Init (void *pdev, + uint8_t cfgidx); + +static uint8_t USBD_CUSTOM_HID_DeInit (void *pdev, + uint8_t cfgidx); + +static uint8_t USBD_CUSTOM_HID_Setup (void *pdev, + USB_SETUP_REQ *req); + +static uint8_t *USBD_CUSTOM_HID_GetCfgDesc (uint8_t speed, uint16_t *length); + +static uint8_t USBD_CUSTOM_HID_DataIn (void *pdev, uint8_t epnum); +static uint8_t USBD_CUSTOM_HID_DataOut (void *pdev, uint8_t epnum); +static uint8_t USBD_CUSTOM_HID_EP0_RxReady (void *pdev); +/** + * @} + */ + +/** @defgroup USBD_HID_Private_Variables + * @{ + */ + +USBD_Class_cb_TypeDef USBD_CUSTOMHID_cb = +{ + USBD_CUSTOM_HID_Init, + USBD_CUSTOM_HID_DeInit, + USBD_CUSTOM_HID_Setup, + NULL, /*EP0_TxSent*/ + USBD_CUSTOM_HID_EP0_RxReady, /*EP0_RxReady*/ /* STATUS STAGE IN */ + USBD_CUSTOM_HID_DataIn, /*DataIn*/ + USBD_CUSTOM_HID_DataOut, + NULL, /*SOF */ + NULL, + NULL, + USBD_CUSTOM_HID_GetCfgDesc, +#ifdef USB_OTG_HS_CORE + USBD_CUSTOM_HID_GetCfgDesc, /* use same config as per FS */ +#endif +}; + +uint8_t Report_buf[2]; +uint8_t USBD_HID_Report_ID=0; +__IO uint32_t IsReportAvailable = 0; +extern uint8_t PrevXferDone; + + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_AltSet __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_Protocol __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_IdleState __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +/* USB HID device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_CfgDesc[USB_CUSTOM_HID_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_CUSTOM_HID_CONFIG_DESC_SIZ, + /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /*bNumInterfaces: 1 interface*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x00, /*iConfiguration: Index of string descriptor describing + the configuration*/ + 0xC0, /*bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + + /************** Descriptor of Custom HID interface ****************/ + /* 09 */ + 0x09, /*bLength: Interface Descriptor size*/ + USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ + 0x00, /*bInterfaceNumber: Number of Interface*/ + 0x00, /*bAlternateSetting: Alternate setting*/ + 0x02, /*bNumEndpoints*/ + 0x03, /*bInterfaceClass: HID*/ + 0x00, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ + 0x00, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ + 0, /*iInterface: Index of string descriptor*/ + /******************** Descriptor of Custom HID ********************/ + /* 18 */ + 0x09, /*bLength: HID Descriptor size*/ + CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ + 0x11, /*bcdHID: HID Class Spec release number*/ + 0x01, + 0x00, /*bCountryCode: Hardware target country*/ + 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ + 0x22, /*bDescriptorType*/ + USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, + /******************** Descriptor of Custom HID endpoints ***********/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_IN_PACKET, /* wMaxPacketSize: 2 Bytes max */ + 0x00, + 0x20, /* bInterval: Polling Interval (32 ms) */ + /* 34 */ + + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + /* Endpoint descriptor type */ + HID_OUT_EP, /* bEndpointAddress: */ + /* Endpoint Address (OUT) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize: 2 Bytes max */ + 0x00, + 0x20, /* bInterval: Polling Interval (20 ms) */ + /* 41 */ +} ; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif + +__ALIGN_BEGIN static uint8_t CustomHID_ReportDesc[USBD_CUSTOM_HID_REPORT_DESC_SIZE] __ALIGN_END = +{ + 0x06, 0xFF, 0x00, /* USAGE_PAGE (Vendor Page: 0xFF00) */ + 0x09, 0x01, /* USAGE (Demo Kit) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + /* 6 */ + + /* Led 1 */ + 0x85, LED1_REPORT_ID, /* REPORT_ID (1) */ + 0x09, 0x01, /* USAGE (LED 1) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, LED1_REPORT_COUNT, /* REPORT_COUNT (1) */ + 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + + 0x85, LED1_REPORT_ID, /* REPORT_ID (1) */ + 0x09, 0x01, /* USAGE (LED 1) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + /* 26 */ + + /* Led 2 */ + 0x85, LED2_REPORT_ID, /* REPORT_ID 2 */ + 0x09, 0x02, /* USAGE (LED 2) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, LED2_REPORT_COUNT, /* REPORT_COUNT (1) */ + 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + + 0x85, LED2_REPORT_ID, /* REPORT_ID (2) */ + 0x09, 0x02, /* USAGE (LED 2) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + /* 46 */ + + /* Led 3 */ + 0x85, LED3_REPORT_ID, /* REPORT_ID (3) */ + 0x09, 0x03, /* USAGE (LED 3) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, LED3_REPORT_COUNT, /* REPORT_COUNT (1) */ + 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + + 0x85, LED3_REPORT_ID, /* REPORT_ID (3) */ + 0x09, 0x03, /* USAGE (LED 3) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + /* 66 */ + + /* Led 4 */ + 0x85, LED4_REPORT_ID, /* REPORT_ID 4) */ + 0x09, 0x04, /* USAGE (LED 4) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, LED4_REPORT_COUNT, /* REPORT_COUNT (1) */ + 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + + 0x85, LED4_REPORT_ID, /* REPORT_ID (4) */ + 0x09, 0x04, /* USAGE (LED 4) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + /* 86 */ + + /* key Push Button */ + 0x85, KEY_REPORT_ID, /* REPORT_ID (5) */ + 0x09, 0x05, /* USAGE (Push Button) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */ + + 0x09, 0x05, /* USAGE (Push Button) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0xb1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + + 0x75, 0x07, /* REPORT_SIZE (7) */ + 0x81, 0x83, /* INPUT (Cnst,Var,Abs,Vol) */ + 0x85, KEY_REPORT_ID, /* REPORT_ID (2) */ + + 0x75, 0x07, /* REPORT_SIZE (7) */ + 0xb1, 0x83, /* FEATURE (Cnst,Var,Abs,Vol) */ + /* 114 */ + + /* Tamper Push Button */ + 0x85, TAMPER_REPORT_ID,/* REPORT_ID (6) */ + 0x09, 0x06, /* USAGE (Tamper Push Button) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */ + + 0x09, 0x06, /* USAGE (Tamper Push Button) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0xb1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + + 0x75, 0x07, /* REPORT_SIZE (7) */ + 0x81, 0x83, /* INPUT (Cnst,Var,Abs,Vol) */ + 0x85, TAMPER_REPORT_ID,/* REPORT_ID (6) */ + + 0x75, 0x07, /* REPORT_SIZE (7) */ + 0xb1, 0x83, /* FEATURE (Cnst,Var,Abs,Vol) */ + /* 142 */ + + /* ADC IN */ + 0x85, ADC_REPORT_ID, /* REPORT_ID */ + 0x09, 0x07, /* USAGE (ADC IN) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x26, 0xff, 0x00, /* LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */ + 0x85, ADC_REPORT_ID, /* REPORT_ID (7) */ + 0x09, 0x07, /* USAGE (ADC in) */ + 0xb1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + /* 161 */ + + 0xc0 /* END_COLLECTION */ +}; + +/** + * @} + */ + +/** @defgroup USBD_HID_Private_Functions + * @{ + */ + +/** + * @brief USBD_HID_Init + * Initialize the HID interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CUSTOM_HID_Init (void *pdev, + uint8_t cfgidx) +{ + /* Open EP IN */ + DCD_EP_Open(pdev, + HID_IN_EP, + HID_IN_PACKET, + USB_OTG_EP_INT); + + /* Open EP OUT */ + DCD_EP_Open(pdev, + HID_OUT_EP, + HID_OUT_PACKET, + USB_OTG_EP_INT); + + /*Receive Data*/ + DCD_EP_PrepareRx(pdev,HID_OUT_EP,Report_buf,2); + + return USBD_OK; +} + +/** + * @brief USBD_HID_Init + * DeInitialize the HID layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CUSTOM_HID_DeInit (void *pdev, + uint8_t cfgidx) +{ + /* Close HID EPs */ + DCD_EP_Close (pdev , HID_IN_EP); + DCD_EP_Close (pdev , HID_OUT_EP); + + + return USBD_OK; +} + +/** + * @brief USBD_HID_Setup + * Handle the HID specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_CUSTOM_HID_Setup (void *pdev, + USB_SETUP_REQ *req) +{ + uint8_t USBD_HID_Report_LENGTH=0; + uint16_t len = 0; + uint8_t *pbuf = NULL; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case CUSTOM_HID_REQ_SET_PROTOCOL: + USBD_HID_Protocol = (uint8_t)(req->wValue); + break; + + case CUSTOM_HID_REQ_GET_PROTOCOL: + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_HID_Protocol, + 1); + break; + + case CUSTOM_HID_REQ_SET_IDLE: + USBD_HID_IdleState = (uint8_t)(req->wValue >> 8); + break; + + case CUSTOM_HID_REQ_GET_IDLE: + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_HID_IdleState, + 1); + break; + + case CUSTOM_HID_REQ_SET_REPORT: + IsReportAvailable = 1; + USBD_HID_Report_ID = (uint8_t)(req->wValue); + USBD_HID_Report_LENGTH = (uint8_t)(req->wLength); + USBD_CtlPrepareRx (pdev, Report_buf, USBD_HID_Report_LENGTH); + + break; + + default: + USBD_CtlError (pdev, req); + return USBD_FAIL; + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + if( req->wValue >> 8 == CUSTOM_HID_REPORT_DESC) + { + len = MIN(USBD_CUSTOM_HID_REPORT_DESC_SIZE , req->wLength); + pbuf = (uint8_t*)CustomHID_ReportDesc; + } + else if( req->wValue >> 8 == CUSTOM_HID_DESCRIPTOR_TYPE) + { + pbuf = (uint8_t*)USBD_CUSTOM_HID_CfgDesc + 0x12; + len = MIN(USB_CUSTOM_HID_DESC_SIZ , req->wLength); + } + + USBD_CtlSendData (pdev, + pbuf, + len); + + break; + + case USB_REQ_GET_INTERFACE : + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_HID_AltSet, + 1); + break; + + case USB_REQ_SET_INTERFACE : + USBD_HID_AltSet = (uint8_t)(req->wValue); + break; + } + } + return USBD_OK; +} + +/** + * @brief USBD_HID_SendReport + * Send HID Report + * @param pdev: device instance + * @param buff: pointer to report + * @retval status + */ +uint8_t USBD_CUSTOM_HID_SendReport (USB_OTG_CORE_HANDLE *pdev, + uint8_t *report, + uint16_t len) +{ + if (pdev->dev.device_status == USB_OTG_CONFIGURED ) + { + DCD_EP_Tx (pdev, HID_IN_EP, report, len); + } + return USBD_OK; +} + +/** + * @brief USBD_HID_GetCfgDesc + * return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CUSTOM_HID_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_CUSTOM_HID_CfgDesc); + return USBD_CUSTOM_HID_CfgDesc; +} + +/** + * @brief USBD_HID_DataIn + * handle data IN Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ +static uint8_t USBD_CUSTOM_HID_DataIn (void *pdev, + uint8_t epnum) +{ + + /* Ensure that the FIFO is empty before a new transfer, this condition could + be caused by a new transfer before the end of the previous transfer */ + DCD_EP_Flush(pdev, HID_IN_EP); + + if (epnum == 1) PrevXferDone = 1; + + return USBD_OK; +} + +/** + * @brief USBD_HID_DataOut + * handle data IN Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ +uint8_t USBD_CUSTOM_HID_DataOut (void *pdev, + uint8_t epnum) +{ + + BitAction Led_State; + if (epnum == 1) + { + if (Report_buf[1] == 0) + { + Led_State = Bit_RESET; + } + else + { + Led_State = Bit_SET; + } + + switch (Report_buf[0]) + { + case 1: /* Led 1 */ + if (Led_State != Bit_RESET) + { + STM_EVAL_LEDOn(LED1); + } + else + { + STM_EVAL_LEDOff(LED1); + } + break; + + case 2: /* Led 2 */ + if (Led_State != Bit_RESET) + { + STM_EVAL_LEDOn(LED2); + } + else + { + STM_EVAL_LEDOff(LED2); + } + break; + case 3: /* Led 3 */ + if (Led_State != Bit_RESET) + { + STM_EVAL_LEDOn(LED3); + } + else + { + STM_EVAL_LEDOff(LED3); + } + break; + case 4: /* Led 4 */ + if (Led_State != Bit_RESET) + { + STM_EVAL_LEDOn(LED4); + } + else + { + STM_EVAL_LEDOff(LED4); + } + break; + default: + STM_EVAL_LEDOff(LED1); + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + break; + } + } + + DCD_EP_PrepareRx(pdev,HID_IN_EP,Report_buf,2); + + return USBD_OK; +} + +/** + * @brief USBD_HID_EP0_RxReady + * Handles control request data. + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ + +uint8_t USBD_CUSTOM_HID_EP0_RxReady(void *pdev) +{ + BitAction Led_State; + + if (IsReportAvailable == 1) + { + IsReportAvailable = 0; + if (Report_buf[1] == 0) + { + Led_State = Bit_RESET; + } + else + { + Led_State = Bit_SET; + } + + switch (Report_buf[0]) + { + case 1: /* Led 1 */ + if (Led_State != Bit_RESET) + { + STM_EVAL_LEDOn(LED1); + } + else + { + STM_EVAL_LEDOff(LED1); + } + break; + + case 2: /* Led 2 */ + if (Led_State != Bit_RESET) + { + STM_EVAL_LEDOn(LED2); + } + else + { + STM_EVAL_LEDOff(LED2); + } + break; + case 3: /* Led 3 */ + if (Led_State != Bit_RESET) + { + STM_EVAL_LEDOn(LED3); + } + else + { + STM_EVAL_LEDOff(LED3); + } + break; + case 4: /* Led 4 */ + if (Led_State != Bit_RESET) + { + STM_EVAL_LEDOn(LED4); + } + else + { + STM_EVAL_LEDOff(LED4); + } + break; + default: + STM_EVAL_LEDOff(LED1); + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + break; + } + } + return USBD_OK; +} +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_core.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_core.h index 271e61e38..2acc0f85b 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_core.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_core.h @@ -1,193 +1,193 @@ -/** - ****************************************************************************** - * @file usbd_dfu_core.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header file for the usbd_dfu_core.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_DFU_CORE_H_ -#define __USB_DFU_CORE_H_ - -#include "usbd_ioreq.h" -#include "usbd_dfu_mal.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_dfu - * @brief This file is the Header file for USBD_dfu.c - * @{ - */ - - -/** @defgroup usbd_dfu_Exported_Defines - * @{ - */ -#define USB_DFU_CONFIG_DESC_SIZ (18 + (9 * USBD_ITF_MAX_NUM)) -#define USB_DFU_DESC_SIZ 9 - -#define DFU_DESCRIPTOR_TYPE 0x21 - - -/*---------------------------------------------------------------------*/ -/* DFU definitions */ -/*---------------------------------------------------------------------*/ - - - -/**************************************************/ -/* DFU Requests DFU states */ -/**************************************************/ - - -#define STATE_appIDLE 0 -#define STATE_appDETACH 1 -#define STATE_dfuIDLE 2 -#define STATE_dfuDNLOAD_SYNC 3 -#define STATE_dfuDNBUSY 4 -#define STATE_dfuDNLOAD_IDLE 5 -#define STATE_dfuMANIFEST_SYNC 6 -#define STATE_dfuMANIFEST 7 -#define STATE_dfuMANIFEST_WAIT_RESET 8 -#define STATE_dfuUPLOAD_IDLE 9 -#define STATE_dfuERROR 10 - -/**************************************************/ -/* DFU Requests DFU status */ -/**************************************************/ - -#define STATUS_OK 0x00 -#define STATUS_ERRTARGET 0x01 -#define STATUS_ERRFILE 0x02 -#define STATUS_ERRWRITE 0x03 -#define STATUS_ERRERASE 0x04 -#define STATUS_ERRCHECK_ERASED 0x05 -#define STATUS_ERRPROG 0x06 -#define STATUS_ERRVERIFY 0x07 -#define STATUS_ERRADDRESS 0x08 -#define STATUS_ERRNOTDONE 0x09 -#define STATUS_ERRFIRMWARE 0x0A -#define STATUS_ERRVENDOR 0x0B -#define STATUS_ERRUSBR 0x0C -#define STATUS_ERRPOR 0x0D -#define STATUS_ERRUNKNOWN 0x0E -#define STATUS_ERRSTALLEDPKT 0x0F - -/**************************************************/ -/* DFU Requests DFU states Manifestation State */ -/**************************************************/ - -#define Manifest_complete 0x00 -#define Manifest_In_Progress 0x01 - - -/**************************************************/ -/* Special Commands with Download Request */ -/**************************************************/ - -#define CMD_GETCOMMANDS 0x00 -#define CMD_SETADDRESSPOINTER 0x21 -#define CMD_ERASE 0x41 - -/**************************************************/ -/* Other defines */ -/**************************************************/ -/* Bit Detach capable = bit 3 in bmAttributes field */ -#define DFU_DETACH_MASK (uint8_t)(1 << 4) -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ -/**************************************************/ -/* DFU Requests */ -/**************************************************/ - -typedef enum _DFU_REQUESTS { - DFU_DETACH = 0, - DFU_DNLOAD = 1, - DFU_UPLOAD, - DFU_GETSTATUS, - DFU_CLRSTATUS, - DFU_GETSTATE, - DFU_ABORT -} DFU_REQUESTS; - -typedef void (*pFunction)(void); -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ -/********** Descriptor of DFU interface 0 Alternate setting n ****************/ -#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ - 0x00, /* bInterfaceNumber: Number of Interface */ \ - (n), /* bAlternateSetting: Alternate setting */ \ - 0x00, /* bNumEndpoints*/ \ - 0xFE, /* bInterfaceClass: Application Specific Class Code */ \ - 0x01, /* bInterfaceSubClass : Device Firmware Upgrade Code */ \ - 0x02, /* nInterfaceProtocol: DFU mode protocol */ \ - USBD_IDX_INTERFACE_STR + (n) + 1 /* iInterface: Index of string descriptor */ \ - /* 18 */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_Class_cb_TypeDef DFU_cb; -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -/** - * @} - */ - -#endif /* __USB_DFU_CORE_H_ */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_dfu_core.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header file for the usbd_dfu_core.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +#ifndef __USB_DFU_CORE_H_ +#define __USB_DFU_CORE_H_ + +#include "usbd_ioreq.h" +#include "usbd_dfu_mal.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup usbd_dfu + * @brief This file is the Header file for USBD_dfu.c + * @{ + */ + + +/** @defgroup usbd_dfu_Exported_Defines + * @{ + */ +#define USB_DFU_CONFIG_DESC_SIZ (18 + (9 * USBD_ITF_MAX_NUM)) +#define USB_DFU_DESC_SIZ 9 + +#define DFU_DESCRIPTOR_TYPE 0x21 + + +/*---------------------------------------------------------------------*/ +/* DFU definitions */ +/*---------------------------------------------------------------------*/ + + + +/**************************************************/ +/* DFU Requests DFU states */ +/**************************************************/ + + +#define STATE_appIDLE 0 +#define STATE_appDETACH 1 +#define STATE_dfuIDLE 2 +#define STATE_dfuDNLOAD_SYNC 3 +#define STATE_dfuDNBUSY 4 +#define STATE_dfuDNLOAD_IDLE 5 +#define STATE_dfuMANIFEST_SYNC 6 +#define STATE_dfuMANIFEST 7 +#define STATE_dfuMANIFEST_WAIT_RESET 8 +#define STATE_dfuUPLOAD_IDLE 9 +#define STATE_dfuERROR 10 + +/**************************************************/ +/* DFU Requests DFU status */ +/**************************************************/ + +#define STATUS_OK 0x00 +#define STATUS_ERRTARGET 0x01 +#define STATUS_ERRFILE 0x02 +#define STATUS_ERRWRITE 0x03 +#define STATUS_ERRERASE 0x04 +#define STATUS_ERRCHECK_ERASED 0x05 +#define STATUS_ERRPROG 0x06 +#define STATUS_ERRVERIFY 0x07 +#define STATUS_ERRADDRESS 0x08 +#define STATUS_ERRNOTDONE 0x09 +#define STATUS_ERRFIRMWARE 0x0A +#define STATUS_ERRVENDOR 0x0B +#define STATUS_ERRUSBR 0x0C +#define STATUS_ERRPOR 0x0D +#define STATUS_ERRUNKNOWN 0x0E +#define STATUS_ERRSTALLEDPKT 0x0F + +/**************************************************/ +/* DFU Requests DFU states Manifestation State */ +/**************************************************/ + +#define Manifest_complete 0x00 +#define Manifest_In_Progress 0x01 + + +/**************************************************/ +/* Special Commands with Download Request */ +/**************************************************/ + +#define CMD_GETCOMMANDS 0x00 +#define CMD_SETADDRESSPOINTER 0x21 +#define CMD_ERASE 0x41 + +/**************************************************/ +/* Other defines */ +/**************************************************/ +/* Bit Detach capable = bit 3 in bmAttributes field */ +#define DFU_DETACH_MASK (uint8_t)(1 << 4) +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ +/**************************************************/ +/* DFU Requests */ +/**************************************************/ + +typedef enum _DFU_REQUESTS { + DFU_DETACH = 0, + DFU_DNLOAD = 1, + DFU_UPLOAD, + DFU_GETSTATUS, + DFU_CLRSTATUS, + DFU_GETSTATE, + DFU_ABORT +} DFU_REQUESTS; + +typedef void (*pFunction)(void); +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ +/********** Descriptor of DFU interface 0 Alternate setting n ****************/ +#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + 0x00, /* bInterfaceNumber: Number of Interface */ \ + (n), /* bAlternateSetting: Alternate setting */ \ + 0x00, /* bNumEndpoints*/ \ + 0xFE, /* bInterfaceClass: Application Specific Class Code */ \ + 0x01, /* bInterfaceSubClass : Device Firmware Upgrade Code */ \ + 0x02, /* nInterfaceProtocol: DFU mode protocol */ \ + USBD_IDX_INTERFACE_STR + (n) + 1 /* iInterface: Index of string descriptor */ \ + /* 18 */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_Class_cb_TypeDef DFU_cb; +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +/** + * @} + */ + +#endif /* __USB_DFU_CORE_H_ */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_mal.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_mal.h index d2d2e6f27..c20ffa1f1 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_mal.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_mal.h @@ -1,81 +1,81 @@ -/** - ****************************************************************************** - * @file usbd_dfu_mal.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Header for usbd_dfu_mal.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __DFU_MAL_H -#define __DFU_MAL_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -#include "usbd_conf.h" -#include "usbd_dfu_core.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct _DFU_MAL_PROP -{ - const uint8_t* pStrDesc; - uint16_t (*pMAL_Init) (void); - uint16_t (*pMAL_DeInit) (void); - uint16_t (*pMAL_Erase) (uint32_t Add); - uint16_t (*pMAL_Write) (uint32_t Add, uint32_t Len); - uint8_t *(*pMAL_Read) (uint32_t Add, uint32_t Len); - uint16_t (*pMAL_CheckAdd) (uint32_t Add); - const uint32_t EraseTiming; - const uint32_t WriteTiming; -} -DFU_MAL_Prop_TypeDef; - - -/* Exported constants --------------------------------------------------------*/ -#define MAL_OK 0 -#define MAL_FAIL 1 - -/* useful macro ---------------------------------------------------------------*/ -#define _1st_BYTE(x) (uint8_t)((x)&0xFF) /* 1st addressing cycle */ -#define _2nd_BYTE(x) (uint8_t)(((x)&0xFF00)>>8) /* 2nd addressing cycle */ -#define _3rd_BYTE(x) (uint8_t)(((x)&0xFF0000)>>16) /* 3rd addressing cycle */ -#define _4th_BYTE(x) (uint8_t)(((x)&0xFF000000)>>24) /* 4th addressing cycle */ - -/* Exported macro ------------------------------------------------------------*/ -#define SET_POLLING_TIMING(x) buffer[1] = _1st_BYTE(x);\ - buffer[2] = _2nd_BYTE(x);\ - buffer[3] = _3rd_BYTE(x); - -/* Exported functions ------------------------------------------------------- */ - -uint16_t MAL_Init (void); -uint16_t MAL_DeInit (void); -uint16_t MAL_Erase (uint32_t SectorAddress); -uint16_t MAL_Write (uint32_t SectorAddress, uint32_t DataLength); -uint8_t *MAL_Read (uint32_t SectorAddress, uint32_t DataLength); -uint16_t MAL_GetStatus(uint32_t SectorAddress ,uint8_t Cmd, uint8_t *buffer); - -extern uint8_t MAL_Buffer[XFERSIZE]; /* RAM Buffer for Downloaded Data */ -#endif /* __DFU_MAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_dfu_mal.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Header for usbd_dfu_mal.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DFU_MAL_H +#define __DFU_MAL_H + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + +#include "usbd_conf.h" +#include "usbd_dfu_core.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct _DFU_MAL_PROP +{ + const uint8_t* pStrDesc; + uint16_t (*pMAL_Init) (void); + uint16_t (*pMAL_DeInit) (void); + uint16_t (*pMAL_Erase) (uint32_t Add); + uint16_t (*pMAL_Write) (uint32_t Add, uint32_t Len); + uint8_t *(*pMAL_Read) (uint32_t Add, uint32_t Len); + uint16_t (*pMAL_CheckAdd) (uint32_t Add); + const uint32_t EraseTiming; + const uint32_t WriteTiming; +} +DFU_MAL_Prop_TypeDef; + + +/* Exported constants --------------------------------------------------------*/ +#define MAL_OK 0 +#define MAL_FAIL 1 + +/* useful macro ---------------------------------------------------------------*/ +#define _1st_BYTE(x) (uint8_t)((x)&0xFF) /* 1st addressing cycle */ +#define _2nd_BYTE(x) (uint8_t)(((x)&0xFF00)>>8) /* 2nd addressing cycle */ +#define _3rd_BYTE(x) (uint8_t)(((x)&0xFF0000)>>16) /* 3rd addressing cycle */ +#define _4th_BYTE(x) (uint8_t)(((x)&0xFF000000)>>24) /* 4th addressing cycle */ + +/* Exported macro ------------------------------------------------------------*/ +#define SET_POLLING_TIMING(x) buffer[1] = _1st_BYTE(x);\ + buffer[2] = _2nd_BYTE(x);\ + buffer[3] = _3rd_BYTE(x); + +/* Exported functions ------------------------------------------------------- */ + +uint16_t MAL_Init (void); +uint16_t MAL_DeInit (void); +uint16_t MAL_Erase (uint32_t SectorAddress); +uint16_t MAL_Write (uint32_t SectorAddress, uint32_t DataLength); +uint8_t *MAL_Read (uint32_t SectorAddress, uint32_t DataLength); +uint16_t MAL_GetStatus(uint32_t SectorAddress ,uint8_t Cmd, uint8_t *buffer); + +extern uint8_t MAL_Buffer[XFERSIZE]; /* RAM Buffer for Downloaded Data */ +#endif /* __DFU_MAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_flash_if.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_flash_if.h index 24dd2e763..fc58da1e5 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_flash_if.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_flash_if.h @@ -1,64 +1,64 @@ -/** - ****************************************************************************** - * @file usbd_flash_if.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Header for usbd_flash_if.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FLASH_IF_MAL_H -#define __FLASH_IF_MAL_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_dfu_mal.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -#define FLASH_START_ADD 0x08000000 - -#ifdef STM32F2XX - #define FLASH_END_ADD 0x08100000 - #define FLASH_IF_STRING "@Internal Flash /0x08000000/03*016Ka,01*016Kg,01*064Kg,07*128Kg" -#elif defined(STM32F40_41xxx) - #define FLASH_END_ADD 0x08100000 - #define FLASH_IF_STRING "@Internal Flash /0x08000000/03*016Ka,01*016Kg,01*064Kg,07*128Kg" - -#elif defined(STM32F429_439xx) - #define FLASH_END_ADD 0x08200000 - #define FLASH_IF_STRING "@Internal Flash /0x08000000/03*016Ka,01*016Kg,01*064Kg,07*128Kg,04*016Kg,01*064Kg,07*128Kg" - - -#elif defined(STM32F10X_CL) - #define FLASH_END_ADD 0x08040000 - #define FLASH_IF_STRING "@Internal Flash /0x08000000/06*002Ka,122*002Kg" -#endif /* STM32F2XX */ - - -extern DFU_MAL_Prop_TypeDef DFU_Flash_cb; - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __FLASH_IF_MAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_flash_if.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Header for usbd_flash_if.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FLASH_IF_MAL_H +#define __FLASH_IF_MAL_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_dfu_mal.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define FLASH_START_ADD 0x08000000 + +#ifdef STM32F2XX + #define FLASH_END_ADD 0x08100000 + #define FLASH_IF_STRING "@Internal Flash /0x08000000/03*016Ka,01*016Kg,01*064Kg,07*128Kg" +#elif defined(STM32F40_41xxx) + #define FLASH_END_ADD 0x08100000 + #define FLASH_IF_STRING "@Internal Flash /0x08000000/03*016Ka,01*016Kg,01*064Kg,07*128Kg" + +#elif defined(STM32F429_439xx) + #define FLASH_END_ADD 0x08200000 + #define FLASH_IF_STRING "@Internal Flash /0x08000000/03*016Ka,01*016Kg,01*064Kg,07*128Kg,04*016Kg,01*064Kg,07*128Kg" + + +#elif defined(STM32F10X_CL) + #define FLASH_END_ADD 0x08040000 + #define FLASH_IF_STRING "@Internal Flash /0x08000000/06*002Ka,122*002Kg" +#endif /* STM32F2XX */ + + +extern DFU_MAL_Prop_TypeDef DFU_Flash_cb; + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __FLASH_IF_MAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_mem_if_template.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_mem_if_template.h index bb0428875..7bb624bc3 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_mem_if_template.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_mem_if_template.h @@ -1,51 +1,51 @@ -/** - ****************************************************************************** - * @file usbd_mem_if_template.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Header for usbd_mem_if_template.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MEM_IF_MAL_H -#define __MEM_IF_MAL_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -#include "usbd_dfu_mal.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -#define MEM_START_ADD 0x00000000 /* Dummy start address */ -#define MEM_END_ADD (uint32_t)(MEM_START_ADD + (5 * 1024)) /* Dummy Size = 5KB */ - -#define MEM_IF_STRING "@Dummy Memory /0x00000000/01*002Kg,03*001Kg" - -extern DFU_MAL_Prop_TypeDef DFU_Mem_cb; - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __MEM_IF_MAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_mem_if_template.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Header for usbd_mem_if_template.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MEM_IF_MAL_H +#define __MEM_IF_MAL_H + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + +#include "usbd_dfu_mal.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define MEM_START_ADD 0x00000000 /* Dummy start address */ +#define MEM_END_ADD (uint32_t)(MEM_START_ADD + (5 * 1024)) /* Dummy Size = 5KB */ + +#define MEM_IF_STRING "@Dummy Memory /0x00000000/01*002Kg,03*001Kg" + +extern DFU_MAL_Prop_TypeDef DFU_Mem_cb; + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __MEM_IF_MAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_otp_if.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_otp_if.h index b342d69d7..648e512c1 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_otp_if.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_otp_if.h @@ -1,49 +1,49 @@ -/** - ****************************************************************************** - * @file usbd_otp_if.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Header for usbd_otp_if.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __OTP_IF_MAL_H -#define __OTP_IF_MAL_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_dfu_mal.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -#define OTP_START_ADD 0x1FFF7800 -#define OTP_END_ADD (uint32_t)(OTP_START_ADD + 528) - -#define OTP_IF_STRING "@OTP Area /0x1FFF7800/01*512 g,01*016 g" - -extern DFU_MAL_Prop_TypeDef DFU_Otp_cb; - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __OTP_IF_MAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_otp_if.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Header for usbd_otp_if.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __OTP_IF_MAL_H +#define __OTP_IF_MAL_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_dfu_mal.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define OTP_START_ADD 0x1FFF7800 +#define OTP_END_ADD (uint32_t)(OTP_START_ADD + 528) + +#define OTP_IF_STRING "@OTP Area /0x1FFF7800/01*512 g,01*016 g" + +extern DFU_MAL_Prop_TypeDef DFU_Otp_cb; + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __OTP_IF_MAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_core.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_core.c index a464c07ef..e2ca669ad 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_core.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_core.c @@ -1,1052 +1,1052 @@ -/** - ****************************************************************************** - * @file usbd_dfu_core.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides the high layer firmware functions to manage the - * following functionalities of the USB DFU Class: - * - Initialization and Configuration of high and low layer - * - Enumeration as DFU Device (and enumeration for each implemented memory interface) - * - Transfers to/from memory interfaces - * - Easy-to-customize "plug-in-like" modules for adding/removing memory interfaces. - * - Error management - * - * @verbatim - * - * =================================================================== - * DFU Class Driver Description - * =================================================================== - * This driver manages the DFU class V1.1 following the "Device Class Specification for - * Device Firmware Upgrade Version 1.1 Aug 5, 2004". - * This driver implements the following aspects of the specification: - * - Device descriptor management - * - Configuration descriptor management - * - Enumeration as DFU device (in DFU mode only) - * - Requests management (supporting ST DFU sub-protocol) - * - Memory operations management (Download/Upload/Erase/Detach/GetState/GetStatus) - * - DFU state machine implementation. - * - * @note - * ST DFU sub-protocol is compliant with DFU protocol and use sub-requests to manage - * memory addressing, commands processing, specific memories operations (ie. Erase) ... - * As required by the DFU specification, only endpoint 0 is used in this application. - * Other endpoints and functions may be added to the application (ie. DFU ...) - * - * These aspects may be enriched or modified for a specific user application. - * - * This driver doesn't implement the following aspects of the specification - * (but it is possible to manage these features with some modifications on this driver): - * - Manifestation Tolerant mode - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_dfu_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" -#include "usb_bsp.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup usbd_dfu - * @brief usbd core module - * @{ - */ - -/** @defgroup usbd_dfu_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_dfu_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_dfu_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_dfu_Private_FunctionPrototypes - * @{ - */ - -/********************************************* - DFU Device library callbacks - *********************************************/ -static uint8_t usbd_dfu_Init (void *pdev, - uint8_t cfgidx); - -static uint8_t usbd_dfu_DeInit (void *pdev, - uint8_t cfgidx); - -static uint8_t usbd_dfu_Setup (void *pdev, - USB_SETUP_REQ *req); - -static uint8_t EP0_TxSent (void *pdev); - -static uint8_t EP0_RxReady (void *pdev); - - -static uint8_t *USBD_DFU_GetCfgDesc (uint8_t speed, - uint16_t *length); - - -#ifdef USB_OTG_HS_CORE -static uint8_t *USBD_DFU_GetOtherCfgDesc (uint8_t speed, - uint16_t *length); -#endif - -static uint8_t* USBD_DFU_GetUsrStringDesc (uint8_t speed, - uint8_t index , - uint16_t *length); - -/********************************************* - DFU Requests management functions - *********************************************/ -static void DFU_Req_DETACH (void *pdev, - USB_SETUP_REQ *req); - -static void DFU_Req_DNLOAD (void *pdev, - USB_SETUP_REQ *req); - -static void DFU_Req_UPLOAD (void *pdev, - USB_SETUP_REQ *req); - -static void DFU_Req_GETSTATUS (void *pdev); - -static void DFU_Req_CLRSTATUS (void *pdev); - -static void DFU_Req_GETSTATE (void *pdev); - -static void DFU_Req_ABORT (void *pdev); - -static void DFU_LeaveDFUMode (void *pdev); - -/** - * @} - */ - -/** @defgroup usbd_dfu_Private_Variables - * @{ - */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t usbd_dfu_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END ; - - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t usbd_dfu_OtherCfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END ; - -/* The list of Interface String descriptor pointers is defined in usbd_dfu_mal.c - file. This list can be updated whenever a memory has to be added or removed */ -extern const uint8_t* usbd_dfu_StringDesc[]; - -/* State Machine variables */ -uint8_t DeviceState; -uint8_t DeviceStatus[6]; -uint32_t Manifest_State = Manifest_complete; -/* Data Management variables */ -static uint32_t wBlockNum = 0, wlength = 0; -static uint32_t Pointer = APP_DEFAULT_ADD; /* Base Address to Erase, Program or Read */ -static __IO uint32_t usbd_dfu_AltSet = 0; - -extern uint8_t MAL_Buffer[]; - -/* DFU interface class callbacks structure */ -USBD_Class_cb_TypeDef DFU_cb = -{ - usbd_dfu_Init, - usbd_dfu_DeInit, - usbd_dfu_Setup, - EP0_TxSent, - EP0_RxReady, - NULL, /* DataIn, */ - NULL, /* DataOut, */ - NULL, /*SOF */ - NULL, - NULL, - USBD_DFU_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_DFU_GetOtherCfgDesc, /* use same cobfig as per FS */ -#endif - USBD_DFU_GetUsrStringDesc, -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB DFU device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t usbd_dfu_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ - USB_DFU_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ - 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/ - 0xC0, /*bmAttributes: bus powered and Supports Remote Wakeup */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - /* 09 */ - - /********** Descriptor of DFU interface 0 Alternate setting 0 **************/ - USBD_DFU_IF_DESC(0), /* This interface is mandatory for all devices */ - -#if (USBD_ITF_MAX_NUM > 1) - /********** Descriptor of DFU interface 0 Alternate setting 1 **************/ - USBD_DFU_IF_DESC(1), -#endif /* (USBD_ITF_MAX_NUM > 1) */ - -#if (USBD_ITF_MAX_NUM > 2) - /********** Descriptor of DFU interface 0 Alternate setting 2 **************/ - USBD_DFU_IF_DESC(2), -#endif /* (USBD_ITF_MAX_NUM > 2) */ - -#if (USBD_ITF_MAX_NUM > 3) - /********** Descriptor of DFU interface 0 Alternate setting 3 **************/ - USBD_DFU_IF_DESC(3), -#endif /* (USBD_ITF_MAX_NUM > 3) */ - -#if (USBD_ITF_MAX_NUM > 4) - /********** Descriptor of DFU interface 0 Alternate setting 4 **************/ - USBD_DFU_IF_DESC(4), -#endif /* (USBD_ITF_MAX_NUM > 4) */ - -#if (USBD_ITF_MAX_NUM > 5) - /********** Descriptor of DFU interface 0 Alternate setting 5 **************/ - USBD_DFU_IF_DESC(5), -#endif /* (USBD_ITF_MAX_NUM > 5) */ - -#if (USBD_ITF_MAX_NUM > 6) -#error "ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!" -#endif /* (USBD_ITF_MAX_NUM > 6) */ - - /******************** DFU Functional Descriptor********************/ - 0x09, /*blength = 9 Bytes*/ - DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/ - 0x0B, /*bmAttribute - bitCanDnload = 1 (bit 0) - bitCanUpload = 1 (bit 1) - bitManifestationTolerant = 0 (bit 2) - bitWillDetach = 1 (bit 3) - Reserved (bit4-6) - bitAcceleratedST = 0 (bit 7)*/ - 0xFF, /*DetachTimeOut= 255 ms*/ - 0x00, - /*WARNING: In DMA mode the multiple MPS packets feature is still not supported - ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */ - TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/ - 0x1A, /* bcdDFUVersion*/ - 0x01 - /***********************************************************/ - /* 9*/ -} ; - -#ifdef USE_USB_OTG_HS -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -__ALIGN_BEGIN uint8_t usbd_dfu_OtherCfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_DFU_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ - 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/ - 0xC0, /*bmAttributes: bus powered and Supports Remote Wakeup */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - /* 09 */ - - /********** Descriptor of DFU interface 0 Alternate setting 0 **************/ - USBD_DFU_IF_DESC(0), /* This interface is mandatory for all devices */ - -#if (USBD_ITF_MAX_NUM > 1) - /********** Descriptor of DFU interface 0 Alternate setting 1 **************/ - USBD_DFU_IF_DESC(1), -#endif /* (USBD_ITF_MAX_NUM > 1) */ - -#if (USBD_ITF_MAX_NUM > 2) - /********** Descriptor of DFU interface 0 Alternate setting 2 **************/ - USBD_DFU_IF_DESC(2), -#endif /* (USBD_ITF_MAX_NUM > 2) */ - -#if (USBD_ITF_MAX_NUM > 3) - /********** Descriptor of DFU interface 0 Alternate setting 3 **************/ - USBD_DFU_IF_DESC(3), -#endif /* (USBD_ITF_MAX_NUM > 3) */ - -#if (USBD_ITF_MAX_NUM > 4) - /********** Descriptor of DFU interface 0 Alternate setting 4 **************/ - USBD_DFU_IF_DESC(4), -#endif /* (USBD_ITF_MAX_NUM > 4) */ - -#if (USBD_ITF_MAX_NUM > 5) - /********** Descriptor of DFU interface 0 Alternate setting 5 **************/ - USBD_DFU_IF_DESC(5), -#endif /* (USBD_ITF_MAX_NUM > 5) */ - -#if (USBD_ITF_MAX_NUM > 6) -#error "ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!" -#endif /* (USBD_ITF_MAX_NUM > 6) */ - - /******************** DFU Functional Descriptor********************/ - 0x09, /*blength = 9 Bytes*/ - DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/ - 0x0B, /*bmAttribute - bitCanDnload = 1 (bit 0) - bitCanUpload = 1 (bit 1) - bitManifestationTolerant = 0 (bit 2) - bitWillDetach = 1 (bit 3) - Reserved (bit4-6) - bitAcceleratedST = 0 (bit 7)*/ - 0xFF, /*DetachTimeOut= 255 ms*/ - 0x00, - /*WARNING: In DMA mode the multiple MPS packets feature is still not supported - ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */ - TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/ - 0x1A, /* bcdDFUVersion*/ - 0x01 - /***********************************************************/ - /* 9*/ -}; -#endif /* USE_USB_OTG_HS */ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif - -__ALIGN_BEGIN static uint8_t usbd_dfu_Desc[USB_DFU_DESC_SIZ] __ALIGN_END = -{ - 0x09, /*blength = 9 Bytes*/ - DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/ - 0x0B, /*bmAttribute - bitCanDnload = 1 (bit 0) - bitCanUpload = 1 (bit 1) - bitManifestationTolerant = 0 (bit 2) - bitWillDetach = 1 (bit 3) - Reserved (bit4-6) - bitAcceleratedST = 0 (bit 7)*/ - 0xFF, /*DetachTimeOut= 255 ms*/ - 0x00, - /*WARNING: In DMA mode the multiple MPS packets feature is still not supported - ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */ - TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/ - 0x1A, /* bcdDFUVersion*/ - 0x01 -}; -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/** - * @} - */ - -/** @defgroup usbd_dfu_Private_Functions - * @{ - */ - -/** - * @brief usbd_dfu_Init - * Initializes the DFU interface. - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t usbd_dfu_Init (void *pdev, - uint8_t cfgidx) -{ - /* Initilialize the MAL(Media Access Layer) */ - MAL_Init(); - - /* Initialize the state of the DFU interface */ - DeviceState = STATE_dfuIDLE; - DeviceStatus[0] = STATUS_OK; - DeviceStatus[4] = DeviceState; - - return USBD_OK; -} - -/** - * @brief usbd_dfu_Init - * De-initializes the DFU layer. - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t usbd_dfu_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* Restore default state */ - DeviceState = STATE_dfuIDLE; - DeviceStatus[0] = STATUS_OK; - DeviceStatus[4] = DeviceState; - wBlockNum = 0; - wlength = 0; - - /* DeInitilialize the MAL(Media Access Layer) */ - MAL_DeInit(); - - return USBD_OK; -} - -/** - * @brief usbd_dfu_Setup - * Handles the DFU request parsing. - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t usbd_dfu_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len = 0; - uint8_t *pbuf = NULL; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - /* DFU Class Requests -------------------------------*/ - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - case DFU_DNLOAD: - DFU_Req_DNLOAD(pdev, req); - break; - - case DFU_UPLOAD: - DFU_Req_UPLOAD(pdev, req); - break; - - case DFU_GETSTATUS: - DFU_Req_GETSTATUS(pdev); - break; - - case DFU_CLRSTATUS: - DFU_Req_CLRSTATUS(pdev); - break; - - case DFU_GETSTATE: - DFU_Req_GETSTATE(pdev); - break; - - case DFU_ABORT: - DFU_Req_ABORT(pdev); - break; - - case DFU_DETACH: - DFU_Req_DETACH(pdev, req); - break; - - default: - USBD_CtlError (pdev, req); - return USBD_FAIL; - } - break; - - /* Standard Requests -------------------------------*/ - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - if( (req->wValue >> 8) == DFU_DESCRIPTOR_TYPE) - { -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pbuf = usbd_dfu_Desc; -#else - pbuf = usbd_dfu_CfgDesc + 9 + (9 * USBD_ITF_MAX_NUM); -#endif - len = MIN(USB_DFU_DESC_SIZ , req->wLength); - } - - USBD_CtlSendData (pdev, - pbuf, - len); - break; - - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - (uint8_t *)&usbd_dfu_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) - { - usbd_dfu_AltSet = (uint8_t)(req->wValue); - } - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - break; - } - } - return USBD_OK; -} - -/** - * @brief EP0_TxSent - * Handles the DFU control endpoint data IN stage. - * @param pdev: device instance - * @retval status - */ -static uint8_t EP0_TxSent (void *pdev) -{ - uint32_t Addr; - USB_SETUP_REQ req; - - if (DeviceState == STATE_dfuDNBUSY) - { - /* Decode the Special Command*/ - if (wBlockNum == 0) - { - if ((MAL_Buffer[0] == CMD_GETCOMMANDS) && (wlength == 1)) - {} - else if (( MAL_Buffer[0] == CMD_SETADDRESSPOINTER ) && (wlength == 5)) - { - Pointer = MAL_Buffer[1]; - Pointer += MAL_Buffer[2] << 8; - Pointer += MAL_Buffer[3] << 16; - Pointer += MAL_Buffer[4] << 24; - } - else if (( MAL_Buffer[0] == CMD_ERASE ) && (wlength == 5)) - { - Pointer = MAL_Buffer[1]; - Pointer += MAL_Buffer[2] << 8; - Pointer += MAL_Buffer[3] << 16; - Pointer += MAL_Buffer[4] << 24; - MAL_Erase(Pointer); - } - else - { - /* Reset the global length and block number */ - wlength = 0; - wBlockNum = 0; - /* Call the error management function (command will be nacked) */ - req.bmRequest = 0; - req.wLength = 1; - USBD_CtlError (pdev, &req); - } - } - /* Regular Download Command */ - else if (wBlockNum > 1) - { - /* Decode the required address */ - Addr = ((wBlockNum - 2) * XFERSIZE) + Pointer; - - /* Preform the write operation */ - MAL_Write(Addr, wlength); - } - /* Reset the global length and block number */ - wlength = 0; - wBlockNum = 0; - - /* Update the state machine */ - DeviceState = STATE_dfuDNLOAD_SYNC; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - return USBD_OK; - } - else if (DeviceState == STATE_dfuMANIFEST)/* Manifestation in progress*/ - { - /* Start leaving DFU mode */ - DFU_LeaveDFUMode(pdev); - } - - return USBD_OK; -} - -/** - * @brief EP0_RxReady - * Handles the DFU control endpoint data OUT stage. - * @param pdev: device instance - * @retval status - */ -static uint8_t EP0_RxReady (void *pdev) -{ - return USBD_OK; -} - - -/****************************************************************************** - DFU Class requests management -******************************************************************************/ -/** - * @brief DFU_Req_DETACH - * Handles the DFU DETACH request. - * @param pdev: device instance - * @param req: pointer to the request structure. - * @retval None. - */ -static void DFU_Req_DETACH(void *pdev, USB_SETUP_REQ *req) -{ - if (DeviceState == STATE_dfuIDLE || DeviceState == STATE_dfuDNLOAD_SYNC - || DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuMANIFEST_SYNC - || DeviceState == STATE_dfuUPLOAD_IDLE ) - { - /* Update the state machine */ - DeviceState = STATE_dfuIDLE; - DeviceStatus[0] = STATUS_OK; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ - DeviceStatus[4] = DeviceState; - DeviceStatus[5] = 0; /*iString*/ - wBlockNum = 0; - wlength = 0; - } - - /* Check the detach capability in the DFU functional descriptor */ - if ((usbd_dfu_CfgDesc[12 + (9 * USBD_ITF_MAX_NUM)]) & DFU_DETACH_MASK) - { - /* Perform an Attach-Detach operation on USB bus */ - DCD_DevDisconnect (pdev); - DCD_DevConnect (pdev); - } - else - { - /* Wait for the period of time specified in Detach request */ - USB_OTG_BSP_mDelay (req->wValue); - } -} - -/** - * @brief DFU_Req_DNLOAD - * Handles the DFU DNLOAD request. - * @param pdev: device instance - * @param req: pointer to the request structure - * @retval None - */ -static void DFU_Req_DNLOAD(void *pdev, USB_SETUP_REQ *req) -{ - /* Data setup request */ - if (req->wLength > 0) - { - if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuDNLOAD_IDLE)) - { - /* Update the global length and block number */ - wBlockNum = req->wValue; - wlength = req->wLength; - - /* Update the state machine */ - DeviceState = STATE_dfuDNLOAD_SYNC; - DeviceStatus[4] = DeviceState; - - /* Prepare the reception of the buffer over EP0 */ - USBD_CtlPrepareRx (pdev, - (uint8_t*)MAL_Buffer, - wlength); - } - /* Unsupported state */ - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - } - /* 0 Data DNLOAD request */ - else - { - /* End of DNLOAD operation*/ - if (DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuIDLE ) - { - Manifest_State = Manifest_In_Progress; - DeviceState = STATE_dfuMANIFEST_SYNC; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - DeviceStatus[4] = DeviceState; - } - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - } -} - -/** - * @brief DFU_Req_UPLOAD - * Handles the DFU UPLOAD request. - * @param pdev: instance - * @param req: pointer to the request structure - * @retval status - */ -static void DFU_Req_UPLOAD(void *pdev, USB_SETUP_REQ *req) -{ - uint8_t *Phy_Addr = NULL; - uint32_t Addr = 0; - - /* Data setup request */ - if (req->wLength > 0) - { - if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuUPLOAD_IDLE)) - { - /* Update the global length and block number */ - wBlockNum = req->wValue; - wlength = req->wLength; - - /* DFU Get Command */ - if (wBlockNum == 0) - { - /* Update the state machine */ - DeviceState = (wlength > 3)? STATE_dfuIDLE:STATE_dfuUPLOAD_IDLE; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - - /* Store the values of all supported commands */ - MAL_Buffer[0] = CMD_GETCOMMANDS; - MAL_Buffer[1] = CMD_SETADDRESSPOINTER; - MAL_Buffer[2] = CMD_ERASE; - - /* Send the status data over EP0 */ - USBD_CtlSendData (pdev, - (uint8_t *)(&(MAL_Buffer[0])), - 3); - } - else if (wBlockNum > 1) - { - DeviceState = STATE_dfuUPLOAD_IDLE ; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - Addr = ((wBlockNum - 2) * XFERSIZE) + Pointer; /* Change is Accelerated*/ - - /* Return the physical address where data are stored */ - Phy_Addr = MAL_Read(Addr, wlength); - - /* Send the status data over EP0 */ - USBD_CtlSendData (pdev, - Phy_Addr, - wlength); - } - else /* unsupported wBlockNum */ - { - DeviceState = STATUS_ERRSTALLEDPKT; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - } - /* Unsupported state */ - else - { - wlength = 0; - wBlockNum = 0; - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - } - /* No Data setup request */ - else - { - DeviceState = STATE_dfuIDLE; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - DeviceStatus[4] = DeviceState; - } -} - -/** - * @brief DFU_Req_GETSTATUS - * Handles the DFU GETSTATUS request. - * @param pdev: instance - * @retval status - */ -static void DFU_Req_GETSTATUS(void *pdev) -{ - switch (DeviceState) - { - case STATE_dfuDNLOAD_SYNC: - if (wlength != 0) - { - DeviceState = STATE_dfuDNBUSY; - DeviceStatus[4] = DeviceState; - if ((wBlockNum == 0) && (MAL_Buffer[0] == CMD_ERASE)) - { - MAL_GetStatus(Pointer, 0, DeviceStatus); - } - else - { - MAL_GetStatus(Pointer, 1, DeviceStatus); - } - } - else /* (wlength==0)*/ - { - DeviceState = STATE_dfuDNLOAD_IDLE; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - } - break; - - case STATE_dfuMANIFEST_SYNC : - if (Manifest_State == Manifest_In_Progress) - { - DeviceState = STATE_dfuMANIFEST; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 1; /*bwPollTimeout = 1ms*/ - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - //break; - } - else if ((Manifest_State == Manifest_complete) && \ - ((usbd_dfu_CfgDesc[(11 + (9 * USBD_ITF_MAX_NUM))]) & 0x04)) - { - DeviceState = STATE_dfuIDLE; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - //break; - } - break; - - default : - break; - } - - /* Send the status data over EP0 */ - USBD_CtlSendData (pdev, - (uint8_t *)(&(DeviceStatus[0])), - 6); -} - -/** - * @brief DFU_Req_CLRSTATUS - * Handles the DFU CLRSTATUS request. - * @param pdev: device instance - * @retval status - */ -static void DFU_Req_CLRSTATUS(void *pdev) -{ - if (DeviceState == STATE_dfuERROR) - { - DeviceState = STATE_dfuIDLE; - DeviceStatus[0] = STATUS_OK;/*bStatus*/ - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ - DeviceStatus[4] = DeviceState;/*bState*/ - DeviceStatus[5] = 0;/*iString*/ - } - else - { /*State Error*/ - DeviceState = STATE_dfuERROR; - DeviceStatus[0] = STATUS_ERRUNKNOWN;/*bStatus*/ - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ - DeviceStatus[4] = DeviceState;/*bState*/ - DeviceStatus[5] = 0;/*iString*/ - } -} - -/** - * @brief DFU_Req_GETSTATE - * Handles the DFU GETSTATE request. - * @param pdev: device instance - * @retval None - */ -static void DFU_Req_GETSTATE(void *pdev) -{ - /* Return the current state of the DFU interface */ - USBD_CtlSendData (pdev, - &DeviceState, - 1); -} - -/** - * @brief DFU_Req_ABORT - * Handles the DFU ABORT request. - * @param pdev: device instance - * @retval None - */ -static void DFU_Req_ABORT(void *pdev) -{ - if (DeviceState == STATE_dfuIDLE || DeviceState == STATE_dfuDNLOAD_SYNC - || DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuMANIFEST_SYNC - || DeviceState == STATE_dfuUPLOAD_IDLE ) - { - DeviceState = STATE_dfuIDLE; - DeviceStatus[0] = STATUS_OK; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ - DeviceStatus[4] = DeviceState; - DeviceStatus[5] = 0; /*iString*/ - wBlockNum = 0; - wlength = 0; - } -} - -/** - * @brief DFU_LeaveDFUMode - * Handles the sub-protocol DFU leave DFU mode request (leaves DFU mode - * and resets device to jump to user loaded code). - * @param pdev: device instance - * @retval None - */ -void DFU_LeaveDFUMode(void *pdev) -{ - Manifest_State = Manifest_complete; - - if ((usbd_dfu_CfgDesc[(11 + (9 * USBD_ITF_MAX_NUM))]) & 0x04) - { - DeviceState = STATE_dfuMANIFEST_SYNC; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - return; - } - else - { - DeviceState = STATE_dfuMANIFEST_WAIT_RESET; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - - /* Disconnect the USB device */ - DCD_DevDisconnect (pdev); - - /* DeInitilialize the MAL(Media Access Layer) */ - MAL_DeInit(); - - /* Generate system reset to allow jumping to the user code */ - NVIC_SystemReset(); - - /* This instruction will not be reached (system reset) */ - return; - } -} - -/** - * @brief USBD_DFU_GetCfgDesc - * Returns configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_DFU_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (usbd_dfu_CfgDesc); - return usbd_dfu_CfgDesc; -} - -#ifdef USB_OTG_HS_CORE -/** - * @brief USBD_DFU_GetOtherCfgDesc - * Returns other speed configuration descriptor. - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_DFU_GetOtherCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (usbd_dfu_OtherCfgDesc); - return usbd_dfu_OtherCfgDesc; -} -#endif - -/** - * @brief USBD_DFU_GetUsrStringDesc - * Manages the transfer of memory interfaces string descriptors. - * @param speed : current device speed - * @param index: descriptor index - * @param length : pointer data length - * @retval pointer to the descriptor table or NULL if the descriptor is not supported. - */ -static uint8_t* USBD_DFU_GetUsrStringDesc (uint8_t speed, uint8_t index , uint16_t *length) -{ - /* Check if the requested string interface is supported */ - if (index <= (USBD_IDX_INTERFACE_STR + USBD_ITF_MAX_NUM)) - { - - - USBD_GetString ((uint8_t *)usbd_dfu_StringDesc[index - USBD_IDX_INTERFACE_STR - 1], USBD_StrDesc, length); - return USBD_StrDesc; - } - /* Not supported Interface Descriptor index */ - else - { - return NULL; - } -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_dfu_core.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides the high layer firmware functions to manage the + * following functionalities of the USB DFU Class: + * - Initialization and Configuration of high and low layer + * - Enumeration as DFU Device (and enumeration for each implemented memory interface) + * - Transfers to/from memory interfaces + * - Easy-to-customize "plug-in-like" modules for adding/removing memory interfaces. + * - Error management + * + * @verbatim + * + * =================================================================== + * DFU Class Driver Description + * =================================================================== + * This driver manages the DFU class V1.1 following the "Device Class Specification for + * Device Firmware Upgrade Version 1.1 Aug 5, 2004". + * This driver implements the following aspects of the specification: + * - Device descriptor management + * - Configuration descriptor management + * - Enumeration as DFU device (in DFU mode only) + * - Requests management (supporting ST DFU sub-protocol) + * - Memory operations management (Download/Upload/Erase/Detach/GetState/GetStatus) + * - DFU state machine implementation. + * + * @note + * ST DFU sub-protocol is compliant with DFU protocol and use sub-requests to manage + * memory addressing, commands processing, specific memories operations (ie. Erase) ... + * As required by the DFU specification, only endpoint 0 is used in this application. + * Other endpoints and functions may be added to the application (ie. DFU ...) + * + * These aspects may be enriched or modified for a specific user application. + * + * This driver doesn't implement the following aspects of the specification + * (but it is possible to manage these features with some modifications on this driver): + * - Manifestation Tolerant mode + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_dfu_core.h" +#include "usbd_desc.h" +#include "usbd_req.h" +#include "usb_bsp.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup usbd_dfu + * @brief usbd core module + * @{ + */ + +/** @defgroup usbd_dfu_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup usbd_dfu_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup usbd_dfu_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup usbd_dfu_Private_FunctionPrototypes + * @{ + */ + +/********************************************* + DFU Device library callbacks + *********************************************/ +static uint8_t usbd_dfu_Init (void *pdev, + uint8_t cfgidx); + +static uint8_t usbd_dfu_DeInit (void *pdev, + uint8_t cfgidx); + +static uint8_t usbd_dfu_Setup (void *pdev, + USB_SETUP_REQ *req); + +static uint8_t EP0_TxSent (void *pdev); + +static uint8_t EP0_RxReady (void *pdev); + + +static uint8_t *USBD_DFU_GetCfgDesc (uint8_t speed, + uint16_t *length); + + +#ifdef USB_OTG_HS_CORE +static uint8_t *USBD_DFU_GetOtherCfgDesc (uint8_t speed, + uint16_t *length); +#endif + +static uint8_t* USBD_DFU_GetUsrStringDesc (uint8_t speed, + uint8_t index , + uint16_t *length); + +/********************************************* + DFU Requests management functions + *********************************************/ +static void DFU_Req_DETACH (void *pdev, + USB_SETUP_REQ *req); + +static void DFU_Req_DNLOAD (void *pdev, + USB_SETUP_REQ *req); + +static void DFU_Req_UPLOAD (void *pdev, + USB_SETUP_REQ *req); + +static void DFU_Req_GETSTATUS (void *pdev); + +static void DFU_Req_CLRSTATUS (void *pdev); + +static void DFU_Req_GETSTATE (void *pdev); + +static void DFU_Req_ABORT (void *pdev); + +static void DFU_LeaveDFUMode (void *pdev); + +/** + * @} + */ + +/** @defgroup usbd_dfu_Private_Variables + * @{ + */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t usbd_dfu_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END ; + + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t usbd_dfu_OtherCfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END ; + +/* The list of Interface String descriptor pointers is defined in usbd_dfu_mal.c + file. This list can be updated whenever a memory has to be added or removed */ +extern const uint8_t* usbd_dfu_StringDesc[]; + +/* State Machine variables */ +uint8_t DeviceState; +uint8_t DeviceStatus[6]; +uint32_t Manifest_State = Manifest_complete; +/* Data Management variables */ +static uint32_t wBlockNum = 0, wlength = 0; +static uint32_t Pointer = APP_DEFAULT_ADD; /* Base Address to Erase, Program or Read */ +static __IO uint32_t usbd_dfu_AltSet = 0; + +extern uint8_t MAL_Buffer[]; + +/* DFU interface class callbacks structure */ +USBD_Class_cb_TypeDef DFU_cb = +{ + usbd_dfu_Init, + usbd_dfu_DeInit, + usbd_dfu_Setup, + EP0_TxSent, + EP0_RxReady, + NULL, /* DataIn, */ + NULL, /* DataOut, */ + NULL, /*SOF */ + NULL, + NULL, + USBD_DFU_GetCfgDesc, +#ifdef USB_OTG_HS_CORE + USBD_DFU_GetOtherCfgDesc, /* use same cobfig as per FS */ +#endif + USBD_DFU_GetUsrStringDesc, +}; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +/* USB DFU device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t usbd_dfu_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_DFU_CONFIG_DESC_SIZ, + /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /*bNumInterfaces: 1 interface*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/ + 0xC0, /*bmAttributes: bus powered and Supports Remote Wakeup */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + /* 09 */ + + /********** Descriptor of DFU interface 0 Alternate setting 0 **************/ + USBD_DFU_IF_DESC(0), /* This interface is mandatory for all devices */ + +#if (USBD_ITF_MAX_NUM > 1) + /********** Descriptor of DFU interface 0 Alternate setting 1 **************/ + USBD_DFU_IF_DESC(1), +#endif /* (USBD_ITF_MAX_NUM > 1) */ + +#if (USBD_ITF_MAX_NUM > 2) + /********** Descriptor of DFU interface 0 Alternate setting 2 **************/ + USBD_DFU_IF_DESC(2), +#endif /* (USBD_ITF_MAX_NUM > 2) */ + +#if (USBD_ITF_MAX_NUM > 3) + /********** Descriptor of DFU interface 0 Alternate setting 3 **************/ + USBD_DFU_IF_DESC(3), +#endif /* (USBD_ITF_MAX_NUM > 3) */ + +#if (USBD_ITF_MAX_NUM > 4) + /********** Descriptor of DFU interface 0 Alternate setting 4 **************/ + USBD_DFU_IF_DESC(4), +#endif /* (USBD_ITF_MAX_NUM > 4) */ + +#if (USBD_ITF_MAX_NUM > 5) + /********** Descriptor of DFU interface 0 Alternate setting 5 **************/ + USBD_DFU_IF_DESC(5), +#endif /* (USBD_ITF_MAX_NUM > 5) */ + +#if (USBD_ITF_MAX_NUM > 6) +#error "ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!" +#endif /* (USBD_ITF_MAX_NUM > 6) */ + + /******************** DFU Functional Descriptor********************/ + 0x09, /*blength = 9 Bytes*/ + DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/ + 0x0B, /*bmAttribute + bitCanDnload = 1 (bit 0) + bitCanUpload = 1 (bit 1) + bitManifestationTolerant = 0 (bit 2) + bitWillDetach = 1 (bit 3) + Reserved (bit4-6) + bitAcceleratedST = 0 (bit 7)*/ + 0xFF, /*DetachTimeOut= 255 ms*/ + 0x00, + /*WARNING: In DMA mode the multiple MPS packets feature is still not supported + ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */ + TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/ + 0x1A, /* bcdDFUVersion*/ + 0x01 + /***********************************************************/ + /* 9*/ +} ; + +#ifdef USE_USB_OTG_HS +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +__ALIGN_BEGIN uint8_t usbd_dfu_OtherCfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_DFU_CONFIG_DESC_SIZ, + /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /*bNumInterfaces: 1 interface*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/ + 0xC0, /*bmAttributes: bus powered and Supports Remote Wakeup */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + /* 09 */ + + /********** Descriptor of DFU interface 0 Alternate setting 0 **************/ + USBD_DFU_IF_DESC(0), /* This interface is mandatory for all devices */ + +#if (USBD_ITF_MAX_NUM > 1) + /********** Descriptor of DFU interface 0 Alternate setting 1 **************/ + USBD_DFU_IF_DESC(1), +#endif /* (USBD_ITF_MAX_NUM > 1) */ + +#if (USBD_ITF_MAX_NUM > 2) + /********** Descriptor of DFU interface 0 Alternate setting 2 **************/ + USBD_DFU_IF_DESC(2), +#endif /* (USBD_ITF_MAX_NUM > 2) */ + +#if (USBD_ITF_MAX_NUM > 3) + /********** Descriptor of DFU interface 0 Alternate setting 3 **************/ + USBD_DFU_IF_DESC(3), +#endif /* (USBD_ITF_MAX_NUM > 3) */ + +#if (USBD_ITF_MAX_NUM > 4) + /********** Descriptor of DFU interface 0 Alternate setting 4 **************/ + USBD_DFU_IF_DESC(4), +#endif /* (USBD_ITF_MAX_NUM > 4) */ + +#if (USBD_ITF_MAX_NUM > 5) + /********** Descriptor of DFU interface 0 Alternate setting 5 **************/ + USBD_DFU_IF_DESC(5), +#endif /* (USBD_ITF_MAX_NUM > 5) */ + +#if (USBD_ITF_MAX_NUM > 6) +#error "ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!" +#endif /* (USBD_ITF_MAX_NUM > 6) */ + + /******************** DFU Functional Descriptor********************/ + 0x09, /*blength = 9 Bytes*/ + DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/ + 0x0B, /*bmAttribute + bitCanDnload = 1 (bit 0) + bitCanUpload = 1 (bit 1) + bitManifestationTolerant = 0 (bit 2) + bitWillDetach = 1 (bit 3) + Reserved (bit4-6) + bitAcceleratedST = 0 (bit 7)*/ + 0xFF, /*DetachTimeOut= 255 ms*/ + 0x00, + /*WARNING: In DMA mode the multiple MPS packets feature is still not supported + ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */ + TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/ + 0x1A, /* bcdDFUVersion*/ + 0x01 + /***********************************************************/ + /* 9*/ +}; +#endif /* USE_USB_OTG_HS */ + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif + +__ALIGN_BEGIN static uint8_t usbd_dfu_Desc[USB_DFU_DESC_SIZ] __ALIGN_END = +{ + 0x09, /*blength = 9 Bytes*/ + DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/ + 0x0B, /*bmAttribute + bitCanDnload = 1 (bit 0) + bitCanUpload = 1 (bit 1) + bitManifestationTolerant = 0 (bit 2) + bitWillDetach = 1 (bit 3) + Reserved (bit4-6) + bitAcceleratedST = 0 (bit 7)*/ + 0xFF, /*DetachTimeOut= 255 ms*/ + 0x00, + /*WARNING: In DMA mode the multiple MPS packets feature is still not supported + ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */ + TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/ + 0x1A, /* bcdDFUVersion*/ + 0x01 +}; +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +/** + * @} + */ + +/** @defgroup usbd_dfu_Private_Functions + * @{ + */ + +/** + * @brief usbd_dfu_Init + * Initializes the DFU interface. + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t usbd_dfu_Init (void *pdev, + uint8_t cfgidx) +{ + /* Initilialize the MAL(Media Access Layer) */ + MAL_Init(); + + /* Initialize the state of the DFU interface */ + DeviceState = STATE_dfuIDLE; + DeviceStatus[0] = STATUS_OK; + DeviceStatus[4] = DeviceState; + + return USBD_OK; +} + +/** + * @brief usbd_dfu_Init + * De-initializes the DFU layer. + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t usbd_dfu_DeInit (void *pdev, + uint8_t cfgidx) +{ + /* Restore default state */ + DeviceState = STATE_dfuIDLE; + DeviceStatus[0] = STATUS_OK; + DeviceStatus[4] = DeviceState; + wBlockNum = 0; + wlength = 0; + + /* DeInitilialize the MAL(Media Access Layer) */ + MAL_DeInit(); + + return USBD_OK; +} + +/** + * @brief usbd_dfu_Setup + * Handles the DFU request parsing. + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t usbd_dfu_Setup (void *pdev, + USB_SETUP_REQ *req) +{ + uint16_t len = 0; + uint8_t *pbuf = NULL; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + /* DFU Class Requests -------------------------------*/ + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case DFU_DNLOAD: + DFU_Req_DNLOAD(pdev, req); + break; + + case DFU_UPLOAD: + DFU_Req_UPLOAD(pdev, req); + break; + + case DFU_GETSTATUS: + DFU_Req_GETSTATUS(pdev); + break; + + case DFU_CLRSTATUS: + DFU_Req_CLRSTATUS(pdev); + break; + + case DFU_GETSTATE: + DFU_Req_GETSTATE(pdev); + break; + + case DFU_ABORT: + DFU_Req_ABORT(pdev); + break; + + case DFU_DETACH: + DFU_Req_DETACH(pdev, req); + break; + + default: + USBD_CtlError (pdev, req); + return USBD_FAIL; + } + break; + + /* Standard Requests -------------------------------*/ + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + if( (req->wValue >> 8) == DFU_DESCRIPTOR_TYPE) + { +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + pbuf = usbd_dfu_Desc; +#else + pbuf = usbd_dfu_CfgDesc + 9 + (9 * USBD_ITF_MAX_NUM); +#endif + len = MIN(USB_DFU_DESC_SIZ , req->wLength); + } + + USBD_CtlSendData (pdev, + pbuf, + len); + break; + + case USB_REQ_GET_INTERFACE : + USBD_CtlSendData (pdev, + (uint8_t *)&usbd_dfu_AltSet, + 1); + break; + + case USB_REQ_SET_INTERFACE : + if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) + { + usbd_dfu_AltSet = (uint8_t)(req->wValue); + } + else + { + /* Call the error management function (command will be nacked */ + USBD_CtlError (pdev, req); + } + break; + } + } + return USBD_OK; +} + +/** + * @brief EP0_TxSent + * Handles the DFU control endpoint data IN stage. + * @param pdev: device instance + * @retval status + */ +static uint8_t EP0_TxSent (void *pdev) +{ + uint32_t Addr; + USB_SETUP_REQ req; + + if (DeviceState == STATE_dfuDNBUSY) + { + /* Decode the Special Command*/ + if (wBlockNum == 0) + { + if ((MAL_Buffer[0] == CMD_GETCOMMANDS) && (wlength == 1)) + {} + else if (( MAL_Buffer[0] == CMD_SETADDRESSPOINTER ) && (wlength == 5)) + { + Pointer = MAL_Buffer[1]; + Pointer += MAL_Buffer[2] << 8; + Pointer += MAL_Buffer[3] << 16; + Pointer += MAL_Buffer[4] << 24; + } + else if (( MAL_Buffer[0] == CMD_ERASE ) && (wlength == 5)) + { + Pointer = MAL_Buffer[1]; + Pointer += MAL_Buffer[2] << 8; + Pointer += MAL_Buffer[3] << 16; + Pointer += MAL_Buffer[4] << 24; + MAL_Erase(Pointer); + } + else + { + /* Reset the global length and block number */ + wlength = 0; + wBlockNum = 0; + /* Call the error management function (command will be nacked) */ + req.bmRequest = 0; + req.wLength = 1; + USBD_CtlError (pdev, &req); + } + } + /* Regular Download Command */ + else if (wBlockNum > 1) + { + /* Decode the required address */ + Addr = ((wBlockNum - 2) * XFERSIZE) + Pointer; + + /* Preform the write operation */ + MAL_Write(Addr, wlength); + } + /* Reset the global length and block number */ + wlength = 0; + wBlockNum = 0; + + /* Update the state machine */ + DeviceState = STATE_dfuDNLOAD_SYNC; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + return USBD_OK; + } + else if (DeviceState == STATE_dfuMANIFEST)/* Manifestation in progress*/ + { + /* Start leaving DFU mode */ + DFU_LeaveDFUMode(pdev); + } + + return USBD_OK; +} + +/** + * @brief EP0_RxReady + * Handles the DFU control endpoint data OUT stage. + * @param pdev: device instance + * @retval status + */ +static uint8_t EP0_RxReady (void *pdev) +{ + return USBD_OK; +} + + +/****************************************************************************** + DFU Class requests management +******************************************************************************/ +/** + * @brief DFU_Req_DETACH + * Handles the DFU DETACH request. + * @param pdev: device instance + * @param req: pointer to the request structure. + * @retval None. + */ +static void DFU_Req_DETACH(void *pdev, USB_SETUP_REQ *req) +{ + if (DeviceState == STATE_dfuIDLE || DeviceState == STATE_dfuDNLOAD_SYNC + || DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuMANIFEST_SYNC + || DeviceState == STATE_dfuUPLOAD_IDLE ) + { + /* Update the state machine */ + DeviceState = STATE_dfuIDLE; + DeviceStatus[0] = STATUS_OK; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ + DeviceStatus[4] = DeviceState; + DeviceStatus[5] = 0; /*iString*/ + wBlockNum = 0; + wlength = 0; + } + + /* Check the detach capability in the DFU functional descriptor */ + if ((usbd_dfu_CfgDesc[12 + (9 * USBD_ITF_MAX_NUM)]) & DFU_DETACH_MASK) + { + /* Perform an Attach-Detach operation on USB bus */ + DCD_DevDisconnect (pdev); + DCD_DevConnect (pdev); + } + else + { + /* Wait for the period of time specified in Detach request */ + USB_OTG_BSP_mDelay (req->wValue); + } +} + +/** + * @brief DFU_Req_DNLOAD + * Handles the DFU DNLOAD request. + * @param pdev: device instance + * @param req: pointer to the request structure + * @retval None + */ +static void DFU_Req_DNLOAD(void *pdev, USB_SETUP_REQ *req) +{ + /* Data setup request */ + if (req->wLength > 0) + { + if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuDNLOAD_IDLE)) + { + /* Update the global length and block number */ + wBlockNum = req->wValue; + wlength = req->wLength; + + /* Update the state machine */ + DeviceState = STATE_dfuDNLOAD_SYNC; + DeviceStatus[4] = DeviceState; + + /* Prepare the reception of the buffer over EP0 */ + USBD_CtlPrepareRx (pdev, + (uint8_t*)MAL_Buffer, + wlength); + } + /* Unsupported state */ + else + { + /* Call the error management function (command will be nacked */ + USBD_CtlError (pdev, req); + } + } + /* 0 Data DNLOAD request */ + else + { + /* End of DNLOAD operation*/ + if (DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuIDLE ) + { + Manifest_State = Manifest_In_Progress; + DeviceState = STATE_dfuMANIFEST_SYNC; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + DeviceStatus[4] = DeviceState; + } + else + { + /* Call the error management function (command will be nacked */ + USBD_CtlError (pdev, req); + } + } +} + +/** + * @brief DFU_Req_UPLOAD + * Handles the DFU UPLOAD request. + * @param pdev: instance + * @param req: pointer to the request structure + * @retval status + */ +static void DFU_Req_UPLOAD(void *pdev, USB_SETUP_REQ *req) +{ + uint8_t *Phy_Addr = NULL; + uint32_t Addr = 0; + + /* Data setup request */ + if (req->wLength > 0) + { + if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuUPLOAD_IDLE)) + { + /* Update the global length and block number */ + wBlockNum = req->wValue; + wlength = req->wLength; + + /* DFU Get Command */ + if (wBlockNum == 0) + { + /* Update the state machine */ + DeviceState = (wlength > 3)? STATE_dfuIDLE:STATE_dfuUPLOAD_IDLE; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + + /* Store the values of all supported commands */ + MAL_Buffer[0] = CMD_GETCOMMANDS; + MAL_Buffer[1] = CMD_SETADDRESSPOINTER; + MAL_Buffer[2] = CMD_ERASE; + + /* Send the status data over EP0 */ + USBD_CtlSendData (pdev, + (uint8_t *)(&(MAL_Buffer[0])), + 3); + } + else if (wBlockNum > 1) + { + DeviceState = STATE_dfuUPLOAD_IDLE ; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + Addr = ((wBlockNum - 2) * XFERSIZE) + Pointer; /* Change is Accelerated*/ + + /* Return the physical address where data are stored */ + Phy_Addr = MAL_Read(Addr, wlength); + + /* Send the status data over EP0 */ + USBD_CtlSendData (pdev, + Phy_Addr, + wlength); + } + else /* unsupported wBlockNum */ + { + DeviceState = STATUS_ERRSTALLEDPKT; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + + /* Call the error management function (command will be nacked */ + USBD_CtlError (pdev, req); + } + } + /* Unsupported state */ + else + { + wlength = 0; + wBlockNum = 0; + /* Call the error management function (command will be nacked */ + USBD_CtlError (pdev, req); + } + } + /* No Data setup request */ + else + { + DeviceState = STATE_dfuIDLE; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + DeviceStatus[4] = DeviceState; + } +} + +/** + * @brief DFU_Req_GETSTATUS + * Handles the DFU GETSTATUS request. + * @param pdev: instance + * @retval status + */ +static void DFU_Req_GETSTATUS(void *pdev) +{ + switch (DeviceState) + { + case STATE_dfuDNLOAD_SYNC: + if (wlength != 0) + { + DeviceState = STATE_dfuDNBUSY; + DeviceStatus[4] = DeviceState; + if ((wBlockNum == 0) && (MAL_Buffer[0] == CMD_ERASE)) + { + MAL_GetStatus(Pointer, 0, DeviceStatus); + } + else + { + MAL_GetStatus(Pointer, 1, DeviceStatus); + } + } + else /* (wlength==0)*/ + { + DeviceState = STATE_dfuDNLOAD_IDLE; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + } + break; + + case STATE_dfuMANIFEST_SYNC : + if (Manifest_State == Manifest_In_Progress) + { + DeviceState = STATE_dfuMANIFEST; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 1; /*bwPollTimeout = 1ms*/ + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + //break; + } + else if ((Manifest_State == Manifest_complete) && \ + ((usbd_dfu_CfgDesc[(11 + (9 * USBD_ITF_MAX_NUM))]) & 0x04)) + { + DeviceState = STATE_dfuIDLE; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + //break; + } + break; + + default : + break; + } + + /* Send the status data over EP0 */ + USBD_CtlSendData (pdev, + (uint8_t *)(&(DeviceStatus[0])), + 6); +} + +/** + * @brief DFU_Req_CLRSTATUS + * Handles the DFU CLRSTATUS request. + * @param pdev: device instance + * @retval status + */ +static void DFU_Req_CLRSTATUS(void *pdev) +{ + if (DeviceState == STATE_dfuERROR) + { + DeviceState = STATE_dfuIDLE; + DeviceStatus[0] = STATUS_OK;/*bStatus*/ + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ + DeviceStatus[4] = DeviceState;/*bState*/ + DeviceStatus[5] = 0;/*iString*/ + } + else + { /*State Error*/ + DeviceState = STATE_dfuERROR; + DeviceStatus[0] = STATUS_ERRUNKNOWN;/*bStatus*/ + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ + DeviceStatus[4] = DeviceState;/*bState*/ + DeviceStatus[5] = 0;/*iString*/ + } +} + +/** + * @brief DFU_Req_GETSTATE + * Handles the DFU GETSTATE request. + * @param pdev: device instance + * @retval None + */ +static void DFU_Req_GETSTATE(void *pdev) +{ + /* Return the current state of the DFU interface */ + USBD_CtlSendData (pdev, + &DeviceState, + 1); +} + +/** + * @brief DFU_Req_ABORT + * Handles the DFU ABORT request. + * @param pdev: device instance + * @retval None + */ +static void DFU_Req_ABORT(void *pdev) +{ + if (DeviceState == STATE_dfuIDLE || DeviceState == STATE_dfuDNLOAD_SYNC + || DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuMANIFEST_SYNC + || DeviceState == STATE_dfuUPLOAD_IDLE ) + { + DeviceState = STATE_dfuIDLE; + DeviceStatus[0] = STATUS_OK; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ + DeviceStatus[4] = DeviceState; + DeviceStatus[5] = 0; /*iString*/ + wBlockNum = 0; + wlength = 0; + } +} + +/** + * @brief DFU_LeaveDFUMode + * Handles the sub-protocol DFU leave DFU mode request (leaves DFU mode + * and resets device to jump to user loaded code). + * @param pdev: device instance + * @retval None + */ +void DFU_LeaveDFUMode(void *pdev) +{ + Manifest_State = Manifest_complete; + + if ((usbd_dfu_CfgDesc[(11 + (9 * USBD_ITF_MAX_NUM))]) & 0x04) + { + DeviceState = STATE_dfuMANIFEST_SYNC; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + return; + } + else + { + DeviceState = STATE_dfuMANIFEST_WAIT_RESET; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + + /* Disconnect the USB device */ + DCD_DevDisconnect (pdev); + + /* DeInitilialize the MAL(Media Access Layer) */ + MAL_DeInit(); + + /* Generate system reset to allow jumping to the user code */ + NVIC_SystemReset(); + + /* This instruction will not be reached (system reset) */ + return; + } +} + +/** + * @brief USBD_DFU_GetCfgDesc + * Returns configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_DFU_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (usbd_dfu_CfgDesc); + return usbd_dfu_CfgDesc; +} + +#ifdef USB_OTG_HS_CORE +/** + * @brief USBD_DFU_GetOtherCfgDesc + * Returns other speed configuration descriptor. + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_DFU_GetOtherCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (usbd_dfu_OtherCfgDesc); + return usbd_dfu_OtherCfgDesc; +} +#endif + +/** + * @brief USBD_DFU_GetUsrStringDesc + * Manages the transfer of memory interfaces string descriptors. + * @param speed : current device speed + * @param index: descriptor index + * @param length : pointer data length + * @retval pointer to the descriptor table or NULL if the descriptor is not supported. + */ +static uint8_t* USBD_DFU_GetUsrStringDesc (uint8_t speed, uint8_t index , uint16_t *length) +{ + /* Check if the requested string interface is supported */ + if (index <= (USBD_IDX_INTERFACE_STR + USBD_ITF_MAX_NUM)) + { + + + USBD_GetString ((uint8_t *)usbd_dfu_StringDesc[index - USBD_IDX_INTERFACE_STR - 1], USBD_StrDesc, length); + return USBD_StrDesc; + } + /* Not supported Interface Descriptor index */ + else + { + return NULL; + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_mal.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_mal.c index 691206c40..c490d517a 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_mal.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_mal.c @@ -1,287 +1,287 @@ -/** - ****************************************************************************** - * @file usbd_dfu_mal.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Generic media access Layer. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_dfu_mal.h" - -#include "usbd_flash_if.h" - -#ifdef DFU_MAL_SUPPORT_OTP - #include "usbd_otp_if.h" -#endif - -#ifdef DFU_MAL_SUPPORT_MEM - #include "usbd_mem_if_template.h" -#endif - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Global Memories callback and string descriptors reference tables. - To add a new memory, modify the value of MAX_USED_MEDIA in usbd_dfu_mal.h - and add the pointer to the callback structure in this table. - Then add the pointer to the memory string descriptor in usbd_dfu_StringDesc table. - No other operation is required. */ -DFU_MAL_Prop_TypeDef* tMALTab[MAX_USED_MEDIA] = { - &DFU_Flash_cb -#ifdef DFU_MAL_SUPPORT_OTP - , &DFU_Otp_cb -#endif -#ifdef DFU_MAL_SUPPORT_MEM - , &DFU_Mem_cb -#endif -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -__ALIGN_BEGIN const uint8_t* usbd_dfu_StringDesc[MAX_USED_MEDIA] __ALIGN_END = { - FLASH_IF_STRING -#ifdef DFU_MAL_SUPPORT_OTP - , OTP_IF_STRING -#endif -#ifdef DFU_MAL_SUPPORT_MEM - , MEM_IF_STRING -#endif -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* RAM Buffer for Downloaded Data */ -__ALIGN_BEGIN uint8_t MAL_Buffer[XFERSIZE] __ALIGN_END ; - -/* Private function prototypes -----------------------------------------------*/ -static uint8_t MAL_CheckAdd (uint32_t Add); -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief MAL_Init - * Initializes the Media on the STM32 - * @param None - * @retval Result of the operation (MAL_OK in all cases) - */ -uint16_t MAL_Init(void) -{ - uint32_t memIdx = 0; - - /* Init all supported memories */ - for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++) - { - /* If the check addres is positive, exit with the memory index */ - if (tMALTab[memIdx]->pMAL_Init != NULL) - { - tMALTab[memIdx]->pMAL_Init(); - } - } - - return MAL_OK; -} - -/** - * @brief MAL_DeInit - * DeInitializes the Media on the STM32 - * @param None - * @retval Result of the operation (MAL_OK in all cases) - */ -uint16_t MAL_DeInit(void) -{ - uint32_t memIdx = 0; - - /* Init all supported memories */ - for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++) - { - /* Check if the command is supported */ - if (tMALTab[memIdx]->pMAL_DeInit != NULL) - { - tMALTab[memIdx]->pMAL_DeInit(); - } - } - - return MAL_OK; -} - -/** - * @brief MAL_Erase - * Erase a sector of memory. - * @param Add: Sector address/code - * @retval Result of the operation: MAL_OK if all operations are OK else MAL_FAIL - */ -uint16_t MAL_Erase(uint32_t Add) -{ - uint32_t memIdx = MAL_CheckAdd(Add); - - /* Check if the area is protected */ - if (DFU_MAL_IS_PROTECTED_AREA(Add)) - { - return MAL_FAIL; - } - - if (memIdx < MAX_USED_MEDIA) - { - /* Check if the command is supported */ - if (tMALTab[memIdx]->pMAL_Erase != NULL) - { - return tMALTab[memIdx]->pMAL_Erase(Add); - } - else - { - return MAL_FAIL; - } - } - else - { - return MAL_FAIL; - } -} - -/** - * @brief MAL_Write - * Write sectors of memory. - * @param Add: Sector address/code - * @param Len: Number of data to be written (in bytes) - * @retval Result of the operation: MAL_OK if all operations are OK else MAL_FAIL - */ -uint16_t MAL_Write (uint32_t Add, uint32_t Len) -{ - uint32_t memIdx = MAL_CheckAdd(Add); - - /* Check if the area is protected */ - if (DFU_MAL_IS_PROTECTED_AREA(Add)) - { - return MAL_FAIL; - } - - if (memIdx < MAX_USED_MEDIA) - { - /* Check if the command is supported */ - if (tMALTab[memIdx]->pMAL_Write != NULL) - { - return tMALTab[memIdx]->pMAL_Write(Add, Len); - } - else - { - return MAL_FAIL; - } - } - else - { - return MAL_FAIL; - } -} - -/** - * @brief MAL_Read - * Read sectors of memory. - * @param Add: Sector address/code - * @param Len: Number of data to be written (in bytes) - * @retval Buffer pointer - */ -uint8_t *MAL_Read (uint32_t Add, uint32_t Len) -{ - uint32_t memIdx = MAL_CheckAdd(Add); - - if (memIdx < MAX_USED_MEDIA) - { - /* Check if the command is supported */ - if (tMALTab[memIdx]->pMAL_Read != NULL) - { - return tMALTab[memIdx]->pMAL_Read(Add, Len); - } - else - { - return MAL_Buffer; - } - } - else - { - return MAL_Buffer; - } -} - -/** - * @brief MAL_GetStatus - * Get the status of a given memory. - * @param Add: Sector address/code (allow to determine which memory will be addressed) - * @param Cmd: 0 for erase and 1 for write - * @param buffer: pointer to the buffer where the status data will be stored. - * @retval Buffer pointer - */ -uint16_t MAL_GetStatus(uint32_t Add , uint8_t Cmd, uint8_t *buffer) -{ - uint32_t memIdx = MAL_CheckAdd(Add); - - if (memIdx < MAX_USED_MEDIA) - { - if (Cmd & 0x01) - { - SET_POLLING_TIMING(tMALTab[memIdx]->EraseTiming); - } - else - { - SET_POLLING_TIMING(tMALTab[memIdx]->WriteTiming); - } - - return MAL_OK; - } - else - { - return MAL_FAIL; - } -} - -/** - * @brief MAL_CheckAdd - * Determine which memory should be managed. - * @param Add: Sector address/code (allow to determine which memory will be addressed) - * @retval Index of the addressed memory. - */ -static uint8_t MAL_CheckAdd(uint32_t Add) -{ - uint32_t memIdx = 0; - - /* Check with all supported memories */ - for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++) - { - /* If the check addres is positive, exit with the memory index */ - if (tMALTab[memIdx]->pMAL_CheckAdd(Add) == MAL_OK) - { - return memIdx; - } - } - /* If no memory found, return MAX_USED_MEDIA */ - return (MAX_USED_MEDIA); -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_dfu_mal.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Generic media access Layer. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_dfu_mal.h" + +#include "usbd_flash_if.h" + +#ifdef DFU_MAL_SUPPORT_OTP + #include "usbd_otp_if.h" +#endif + +#ifdef DFU_MAL_SUPPORT_MEM + #include "usbd_mem_if_template.h" +#endif + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Global Memories callback and string descriptors reference tables. + To add a new memory, modify the value of MAX_USED_MEDIA in usbd_dfu_mal.h + and add the pointer to the callback structure in this table. + Then add the pointer to the memory string descriptor in usbd_dfu_StringDesc table. + No other operation is required. */ +DFU_MAL_Prop_TypeDef* tMALTab[MAX_USED_MEDIA] = { + &DFU_Flash_cb +#ifdef DFU_MAL_SUPPORT_OTP + , &DFU_Otp_cb +#endif +#ifdef DFU_MAL_SUPPORT_MEM + , &DFU_Mem_cb +#endif +}; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +__ALIGN_BEGIN const uint8_t* usbd_dfu_StringDesc[MAX_USED_MEDIA] __ALIGN_END = { + FLASH_IF_STRING +#ifdef DFU_MAL_SUPPORT_OTP + , OTP_IF_STRING +#endif +#ifdef DFU_MAL_SUPPORT_MEM + , MEM_IF_STRING +#endif +}; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +/* RAM Buffer for Downloaded Data */ +__ALIGN_BEGIN uint8_t MAL_Buffer[XFERSIZE] __ALIGN_END ; + +/* Private function prototypes -----------------------------------------------*/ +static uint8_t MAL_CheckAdd (uint32_t Add); +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief MAL_Init + * Initializes the Media on the STM32 + * @param None + * @retval Result of the operation (MAL_OK in all cases) + */ +uint16_t MAL_Init(void) +{ + uint32_t memIdx = 0; + + /* Init all supported memories */ + for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++) + { + /* If the check addres is positive, exit with the memory index */ + if (tMALTab[memIdx]->pMAL_Init != NULL) + { + tMALTab[memIdx]->pMAL_Init(); + } + } + + return MAL_OK; +} + +/** + * @brief MAL_DeInit + * DeInitializes the Media on the STM32 + * @param None + * @retval Result of the operation (MAL_OK in all cases) + */ +uint16_t MAL_DeInit(void) +{ + uint32_t memIdx = 0; + + /* Init all supported memories */ + for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++) + { + /* Check if the command is supported */ + if (tMALTab[memIdx]->pMAL_DeInit != NULL) + { + tMALTab[memIdx]->pMAL_DeInit(); + } + } + + return MAL_OK; +} + +/** + * @brief MAL_Erase + * Erase a sector of memory. + * @param Add: Sector address/code + * @retval Result of the operation: MAL_OK if all operations are OK else MAL_FAIL + */ +uint16_t MAL_Erase(uint32_t Add) +{ + uint32_t memIdx = MAL_CheckAdd(Add); + + /* Check if the area is protected */ + if (DFU_MAL_IS_PROTECTED_AREA(Add)) + { + return MAL_FAIL; + } + + if (memIdx < MAX_USED_MEDIA) + { + /* Check if the command is supported */ + if (tMALTab[memIdx]->pMAL_Erase != NULL) + { + return tMALTab[memIdx]->pMAL_Erase(Add); + } + else + { + return MAL_FAIL; + } + } + else + { + return MAL_FAIL; + } +} + +/** + * @brief MAL_Write + * Write sectors of memory. + * @param Add: Sector address/code + * @param Len: Number of data to be written (in bytes) + * @retval Result of the operation: MAL_OK if all operations are OK else MAL_FAIL + */ +uint16_t MAL_Write (uint32_t Add, uint32_t Len) +{ + uint32_t memIdx = MAL_CheckAdd(Add); + + /* Check if the area is protected */ + if (DFU_MAL_IS_PROTECTED_AREA(Add)) + { + return MAL_FAIL; + } + + if (memIdx < MAX_USED_MEDIA) + { + /* Check if the command is supported */ + if (tMALTab[memIdx]->pMAL_Write != NULL) + { + return tMALTab[memIdx]->pMAL_Write(Add, Len); + } + else + { + return MAL_FAIL; + } + } + else + { + return MAL_FAIL; + } +} + +/** + * @brief MAL_Read + * Read sectors of memory. + * @param Add: Sector address/code + * @param Len: Number of data to be written (in bytes) + * @retval Buffer pointer + */ +uint8_t *MAL_Read (uint32_t Add, uint32_t Len) +{ + uint32_t memIdx = MAL_CheckAdd(Add); + + if (memIdx < MAX_USED_MEDIA) + { + /* Check if the command is supported */ + if (tMALTab[memIdx]->pMAL_Read != NULL) + { + return tMALTab[memIdx]->pMAL_Read(Add, Len); + } + else + { + return MAL_Buffer; + } + } + else + { + return MAL_Buffer; + } +} + +/** + * @brief MAL_GetStatus + * Get the status of a given memory. + * @param Add: Sector address/code (allow to determine which memory will be addressed) + * @param Cmd: 0 for erase and 1 for write + * @param buffer: pointer to the buffer where the status data will be stored. + * @retval Buffer pointer + */ +uint16_t MAL_GetStatus(uint32_t Add , uint8_t Cmd, uint8_t *buffer) +{ + uint32_t memIdx = MAL_CheckAdd(Add); + + if (memIdx < MAX_USED_MEDIA) + { + if (Cmd & 0x01) + { + SET_POLLING_TIMING(tMALTab[memIdx]->EraseTiming); + } + else + { + SET_POLLING_TIMING(tMALTab[memIdx]->WriteTiming); + } + + return MAL_OK; + } + else + { + return MAL_FAIL; + } +} + +/** + * @brief MAL_CheckAdd + * Determine which memory should be managed. + * @param Add: Sector address/code (allow to determine which memory will be addressed) + * @retval Index of the addressed memory. + */ +static uint8_t MAL_CheckAdd(uint32_t Add) +{ + uint32_t memIdx = 0; + + /* Check with all supported memories */ + for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++) + { + /* If the check addres is positive, exit with the memory index */ + if (tMALTab[memIdx]->pMAL_CheckAdd(Add) == MAL_OK) + { + return memIdx; + } + } + /* If no memory found, return MAX_USED_MEDIA */ + return (MAX_USED_MEDIA); +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_flash_if.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_flash_if.c index 18bb8918f..110934f36 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_flash_if.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_flash_if.c @@ -1,227 +1,227 @@ -/** - ****************************************************************************** - * @file usbd_flash_if.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Specific media access Layer for internal flash. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_flash_if.h" -#include "usbd_dfu_mal.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -uint16_t FLASH_If_Init(void); -uint16_t FLASH_If_Erase (uint32_t Add); -uint16_t FLASH_If_Write (uint32_t Add, uint32_t Len); -uint8_t *FLASH_If_Read (uint32_t Add, uint32_t Len); -uint16_t FLASH_If_DeInit(void); -uint16_t FLASH_If_CheckAdd(uint32_t Add); - - -/* Private variables ---------------------------------------------------------*/ -DFU_MAL_Prop_TypeDef DFU_Flash_cb = - { - FLASH_IF_STRING, - FLASH_If_Init, - FLASH_If_DeInit, - FLASH_If_Erase, - FLASH_If_Write, - FLASH_If_Read, - FLASH_If_CheckAdd, - 50, /* Erase Time in ms */ - 50 /* Programming Time in ms */ - }; - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief FLASH_If_Init - * Memory initialization routine. - * @param None - * @retval MAL_OK if operation is successful, MAL_FAIL else. - */ -uint16_t FLASH_If_Init(void) -{ - /* Unlock the internal flash */ - FLASH_Unlock(); - - return MAL_OK; -} - -/** - * @brief FLASH_If_DeInit - * Memory deinitialization routine. - * @param None - * @retval MAL_OK if operation is successful, MAL_FAIL else. - */ -uint16_t FLASH_If_DeInit(void) -{ - /* Lock the internal flash */ - FLASH_Lock(); - - return MAL_OK; -} - -/******************************************************************************* -* Function Name : FLASH_If_Erase -* Description : Erase sector -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -uint16_t FLASH_If_Erase(uint32_t Add) -{ -#if !defined(STM32F10X_CL) - /* Check which sector has to be erased */ - if (Add < 0x08004000) - { - FLASH_EraseSector(FLASH_Sector_0, VoltageRange_3); - } - else if (Add < 0x08008000) - { - FLASH_EraseSector(FLASH_Sector_1, VoltageRange_3); - } - else if (Add < 0x0800C000) - { - FLASH_EraseSector(FLASH_Sector_2, VoltageRange_3); - } - else if (Add < 0x08010000) - { - FLASH_EraseSector(FLASH_Sector_3, VoltageRange_3); - } - else if (Add < 0x08020000) - { - FLASH_EraseSector(FLASH_Sector_4, VoltageRange_3); - } - else if (Add < 0x08040000) - { - FLASH_EraseSector(FLASH_Sector_5, VoltageRange_3); - } - else if (Add < 0x08060000) - { - FLASH_EraseSector(FLASH_Sector_6, VoltageRange_3); - } - else if (Add < 0x08080000) - { - FLASH_EraseSector(FLASH_Sector_7, VoltageRange_3); - } - else if (Add < 0x080A0000) - { - FLASH_EraseSector(FLASH_Sector_8, VoltageRange_3); - } - else if (Add < 0x080C0000) - { - FLASH_EraseSector(FLASH_Sector_9, VoltageRange_3); - } - else if (Add < 0x080E0000) - { - FLASH_EraseSector(FLASH_Sector_10, VoltageRange_3); - } - else if (Add < 0x08100000) - { - FLASH_EraseSector(FLASH_Sector_11, VoltageRange_3); - } - else - { - return MAL_FAIL; - } -#else - /* Call the standard Flash erase function */ - FLASH_ErasePage(Add); -#endif /* STM32F10X_CL */ - - return MAL_OK; -} - -/** - * @brief FLASH_If_Write - * Memory write routine. - * @param Add: Address to be written to. - * @param Len: Number of data to be written (in bytes). - * @retval MAL_OK if operation is successful, MAL_FAIL else. - */ -uint16_t FLASH_If_Write(uint32_t Add, uint32_t Len) -{ - uint32_t idx = 0; - - if (Len & 0x3) /* Not an aligned data */ - { - for (idx = Len; idx < ((Len & 0xFFFC) + 4); idx++) - { - MAL_Buffer[idx] = 0xFF; - } - } - - /* Data received are Word multiple */ - for (idx = 0; idx < Len; idx = idx + 4) - { - FLASH_ProgramWord(Add, *(uint32_t *)(MAL_Buffer + idx)); - Add += 4; - } - return MAL_OK; -} - -/** - * @brief FLASH_If_Read - * Memory read routine. - * @param Add: Address to be read from. - * @param Len: Number of data to be read (in bytes). - * @retval Pointer to the physical address where data should be read. - */ -uint8_t *FLASH_If_Read (uint32_t Add, uint32_t Len) -{ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - uint32_t idx = 0; - for (idx = 0; idx < Len; idx += 4) - { - *(uint32_t*)(MAL_Buffer + idx) = *(uint32_t *)(Add + idx); - } - return (uint8_t*)(MAL_Buffer); -#else - return (uint8_t *)(Add); -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -} - -/** - * @brief FLASH_If_CheckAdd - * Check if the address is an allowed address for this memory. - * @param Add: Address to be checked. - * @param Len: Number of data to be read (in bytes). - * @retval MAL_OK if the address is allowed, MAL_FAIL else. - */ -uint16_t FLASH_If_CheckAdd(uint32_t Add) -{ - if ((Add >= FLASH_START_ADD) && (Add < FLASH_END_ADD)) - { - return MAL_OK; - } - else - { - return MAL_FAIL; - } -} -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_flash_if.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Specific media access Layer for internal flash. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_flash_if.h" +#include "usbd_dfu_mal.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +uint16_t FLASH_If_Init(void); +uint16_t FLASH_If_Erase (uint32_t Add); +uint16_t FLASH_If_Write (uint32_t Add, uint32_t Len); +uint8_t *FLASH_If_Read (uint32_t Add, uint32_t Len); +uint16_t FLASH_If_DeInit(void); +uint16_t FLASH_If_CheckAdd(uint32_t Add); + + +/* Private variables ---------------------------------------------------------*/ +DFU_MAL_Prop_TypeDef DFU_Flash_cb = + { + FLASH_IF_STRING, + FLASH_If_Init, + FLASH_If_DeInit, + FLASH_If_Erase, + FLASH_If_Write, + FLASH_If_Read, + FLASH_If_CheckAdd, + 50, /* Erase Time in ms */ + 50 /* Programming Time in ms */ + }; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief FLASH_If_Init + * Memory initialization routine. + * @param None + * @retval MAL_OK if operation is successful, MAL_FAIL else. + */ +uint16_t FLASH_If_Init(void) +{ + /* Unlock the internal flash */ + FLASH_Unlock(); + + return MAL_OK; +} + +/** + * @brief FLASH_If_DeInit + * Memory deinitialization routine. + * @param None + * @retval MAL_OK if operation is successful, MAL_FAIL else. + */ +uint16_t FLASH_If_DeInit(void) +{ + /* Lock the internal flash */ + FLASH_Lock(); + + return MAL_OK; +} + +/******************************************************************************* +* Function Name : FLASH_If_Erase +* Description : Erase sector +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +uint16_t FLASH_If_Erase(uint32_t Add) +{ +#if !defined(STM32F10X_CL) + /* Check which sector has to be erased */ + if (Add < 0x08004000) + { + FLASH_EraseSector(FLASH_Sector_0, VoltageRange_3); + } + else if (Add < 0x08008000) + { + FLASH_EraseSector(FLASH_Sector_1, VoltageRange_3); + } + else if (Add < 0x0800C000) + { + FLASH_EraseSector(FLASH_Sector_2, VoltageRange_3); + } + else if (Add < 0x08010000) + { + FLASH_EraseSector(FLASH_Sector_3, VoltageRange_3); + } + else if (Add < 0x08020000) + { + FLASH_EraseSector(FLASH_Sector_4, VoltageRange_3); + } + else if (Add < 0x08040000) + { + FLASH_EraseSector(FLASH_Sector_5, VoltageRange_3); + } + else if (Add < 0x08060000) + { + FLASH_EraseSector(FLASH_Sector_6, VoltageRange_3); + } + else if (Add < 0x08080000) + { + FLASH_EraseSector(FLASH_Sector_7, VoltageRange_3); + } + else if (Add < 0x080A0000) + { + FLASH_EraseSector(FLASH_Sector_8, VoltageRange_3); + } + else if (Add < 0x080C0000) + { + FLASH_EraseSector(FLASH_Sector_9, VoltageRange_3); + } + else if (Add < 0x080E0000) + { + FLASH_EraseSector(FLASH_Sector_10, VoltageRange_3); + } + else if (Add < 0x08100000) + { + FLASH_EraseSector(FLASH_Sector_11, VoltageRange_3); + } + else + { + return MAL_FAIL; + } +#else + /* Call the standard Flash erase function */ + FLASH_ErasePage(Add); +#endif /* STM32F10X_CL */ + + return MAL_OK; +} + +/** + * @brief FLASH_If_Write + * Memory write routine. + * @param Add: Address to be written to. + * @param Len: Number of data to be written (in bytes). + * @retval MAL_OK if operation is successful, MAL_FAIL else. + */ +uint16_t FLASH_If_Write(uint32_t Add, uint32_t Len) +{ + uint32_t idx = 0; + + if (Len & 0x3) /* Not an aligned data */ + { + for (idx = Len; idx < ((Len & 0xFFFC) + 4); idx++) + { + MAL_Buffer[idx] = 0xFF; + } + } + + /* Data received are Word multiple */ + for (idx = 0; idx < Len; idx = idx + 4) + { + FLASH_ProgramWord(Add, *(uint32_t *)(MAL_Buffer + idx)); + Add += 4; + } + return MAL_OK; +} + +/** + * @brief FLASH_If_Read + * Memory read routine. + * @param Add: Address to be read from. + * @param Len: Number of data to be read (in bytes). + * @retval Pointer to the physical address where data should be read. + */ +uint8_t *FLASH_If_Read (uint32_t Add, uint32_t Len) +{ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + uint32_t idx = 0; + for (idx = 0; idx < Len; idx += 4) + { + *(uint32_t*)(MAL_Buffer + idx) = *(uint32_t *)(Add + idx); + } + return (uint8_t*)(MAL_Buffer); +#else + return (uint8_t *)(Add); +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +} + +/** + * @brief FLASH_If_CheckAdd + * Check if the address is an allowed address for this memory. + * @param Add: Address to be checked. + * @param Len: Number of data to be read (in bytes). + * @retval MAL_OK if the address is allowed, MAL_FAIL else. + */ +uint16_t FLASH_If_CheckAdd(uint32_t Add) +{ + if ((Add >= FLASH_START_ADD) && (Add < FLASH_END_ADD)) + { + return MAL_OK; + } + else + { + return MAL_FAIL; + } +} +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_mem_if_template.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_mem_if_template.c index a1771515d..e43baad25 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_mem_if_template.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_mem_if_template.c @@ -1,139 +1,139 @@ -/** - ****************************************************************************** - * @file usbd_mem_if_template.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Specific media access Layer for a template memory. This file is - provided as template example showing how to implement a new memory - interface based on pre-defined API. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_mem_if_template.h" -#include "usbd_dfu_mal.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -uint16_t MEM_If_Init(void); -uint16_t MEM_If_Erase (uint32_t Add); -uint16_t MEM_If_Write (uint32_t Add, uint32_t Len); -uint8_t *MEM_If_Read (uint32_t Add, uint32_t Len); -uint16_t MEM_If_DeInit(void); -uint16_t MEM_If_CheckAdd(uint32_t Add); - - -/* Private variables ---------------------------------------------------------*/ -DFU_MAL_Prop_TypeDef DFU_Mem_cb = - { - MEM_IF_STRING, - MEM_If_Init, - MEM_If_DeInit, - MEM_If_Erase, - MEM_If_Write, - MEM_If_Read, - MEM_If_CheckAdd, - 10, /* Erase Time in ms */ - 10 /* Programming Time in ms */ - }; - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief MEM_If_Init - * Memory initialization routine. - * @param None - * @retval MAL_OK if operation is successful, MAL_FAIL else. - */ -uint16_t MEM_If_Init(void) -{ - return MAL_OK; -} - -/** - * @brief MEM_If_DeInit - * Memory deinitialization routine. - * @param None - * @retval MAL_OK if operation is successful, MAL_FAIL else. - */ -uint16_t MEM_If_DeInit(void) -{ - return MAL_OK; -} - -/** - * @brief MEM_If_Erase - * Erase sector. - * @param Add: Address of sector to be erased. - * @retval MAL_OK if operation is successful, MAL_FAIL else. - */ -uint16_t MEM_If_Erase(uint32_t Add) -{ - return MAL_OK; -} - -/** - * @brief MEM_If_Write - * Memory write routine. - * @param Add: Address to be written to. - * @param Len: Number of data to be written (in bytes). - * @retval MAL_OK if operation is successful, MAL_FAIL else. - */ -uint16_t MEM_If_Write(uint32_t Add, uint32_t Len) -{ - return MAL_OK; -} - -/** - * @brief MEM_If_Read - * Memory read routine. - * @param Add: Address to be read from. - * @param Len: Number of data to be read (in bytes). - * @retval Pointer to the physical address where data should be read. - */ -uint8_t *MEM_If_Read (uint32_t Add, uint32_t Len) -{ - /* Return a valid address to avoid HardFault */ - return (uint8_t*)(MAL_Buffer); -} - -/** - * @brief MEM_If_CheckAdd - * Check if the address is an allowed address for this memory. - * @param Add: Address to be checked. - * @param Len: Number of data to be read (in bytes). - * @retval MAL_OK if the address is allowed, MAL_FAIL else. - */ -uint16_t MEM_If_CheckAdd(uint32_t Add) -{ - if ((Add >= MEM_START_ADD) && (Add < MEM_END_ADD)) - { - return MAL_OK; - } - else - { - return MAL_FAIL; - } -} -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_mem_if_template.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Specific media access Layer for a template memory. This file is + provided as template example showing how to implement a new memory + interface based on pre-defined API. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_mem_if_template.h" +#include "usbd_dfu_mal.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +uint16_t MEM_If_Init(void); +uint16_t MEM_If_Erase (uint32_t Add); +uint16_t MEM_If_Write (uint32_t Add, uint32_t Len); +uint8_t *MEM_If_Read (uint32_t Add, uint32_t Len); +uint16_t MEM_If_DeInit(void); +uint16_t MEM_If_CheckAdd(uint32_t Add); + + +/* Private variables ---------------------------------------------------------*/ +DFU_MAL_Prop_TypeDef DFU_Mem_cb = + { + MEM_IF_STRING, + MEM_If_Init, + MEM_If_DeInit, + MEM_If_Erase, + MEM_If_Write, + MEM_If_Read, + MEM_If_CheckAdd, + 10, /* Erase Time in ms */ + 10 /* Programming Time in ms */ + }; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief MEM_If_Init + * Memory initialization routine. + * @param None + * @retval MAL_OK if operation is successful, MAL_FAIL else. + */ +uint16_t MEM_If_Init(void) +{ + return MAL_OK; +} + +/** + * @brief MEM_If_DeInit + * Memory deinitialization routine. + * @param None + * @retval MAL_OK if operation is successful, MAL_FAIL else. + */ +uint16_t MEM_If_DeInit(void) +{ + return MAL_OK; +} + +/** + * @brief MEM_If_Erase + * Erase sector. + * @param Add: Address of sector to be erased. + * @retval MAL_OK if operation is successful, MAL_FAIL else. + */ +uint16_t MEM_If_Erase(uint32_t Add) +{ + return MAL_OK; +} + +/** + * @brief MEM_If_Write + * Memory write routine. + * @param Add: Address to be written to. + * @param Len: Number of data to be written (in bytes). + * @retval MAL_OK if operation is successful, MAL_FAIL else. + */ +uint16_t MEM_If_Write(uint32_t Add, uint32_t Len) +{ + return MAL_OK; +} + +/** + * @brief MEM_If_Read + * Memory read routine. + * @param Add: Address to be read from. + * @param Len: Number of data to be read (in bytes). + * @retval Pointer to the physical address where data should be read. + */ +uint8_t *MEM_If_Read (uint32_t Add, uint32_t Len) +{ + /* Return a valid address to avoid HardFault */ + return (uint8_t*)(MAL_Buffer); +} + +/** + * @brief MEM_If_CheckAdd + * Check if the address is an allowed address for this memory. + * @param Add: Address to be checked. + * @param Len: Number of data to be read (in bytes). + * @retval MAL_OK if the address is allowed, MAL_FAIL else. + */ +uint16_t MEM_If_CheckAdd(uint32_t Add) +{ + if ((Add >= MEM_START_ADD) && (Add < MEM_END_ADD)) + { + return MAL_OK; + } + else + { + return MAL_FAIL; + } +} +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_otp_if.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_otp_if.c index 665e5d060..26fdf0716 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_otp_if.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_otp_if.c @@ -1,126 +1,126 @@ -/** - ****************************************************************************** - * @file usbd_otp_if.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Specific media access Layer for OTP (One Time Programming) memory. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_otp_if.h" -#include "usbd_dfu_mal.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -uint16_t OTP_If_Write (uint32_t Add, uint32_t Len); -uint8_t *OTP_If_Read (uint32_t Add, uint32_t Len); -uint16_t OTP_If_DeInit(void); -uint16_t OTP_If_CheckAdd(uint32_t Add); - - -/* Private variables ---------------------------------------------------------*/ -DFU_MAL_Prop_TypeDef DFU_Otp_cb = - { - OTP_IF_STRING, - NULL, /* Init not supported*/ - NULL, /* DeInit not supported */ - NULL, /* Erase not supported */ - OTP_If_Write, - OTP_If_Read, - OTP_If_CheckAdd, - 1, /* Erase Time in ms */ - 10 /* Programming Time in ms */ - }; - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief OTP_If_Write - * Memory write routine. - * @param Add: Address to be written to. - * @param Len: Number of data to be written (in bytes). - * @retval MAL_OK if operation is successful, MAL_FAIL else. - */ -uint16_t OTP_If_Write(uint32_t Add, uint32_t Len) -{ - uint32_t idx = 0; - - if (Len & 0x3) /* Not an aligned data */ - { - for (idx = Len; idx < ((Len & 0xFFFC) + 4); idx++) - { - MAL_Buffer[idx] = 0xFF; - } - } - - /* Data received are Word multiple */ - for (idx = 0; idx < Len; idx = idx + 4) - { - FLASH_ProgramWord(Add, *(uint32_t *)(MAL_Buffer + idx)); - Add += 4; - } - return MAL_OK; -} - -/** - * @brief OTP_If_Read - * Memory read routine. - * @param Add: Address to be read from. - * @param Len: Number of data to be read (in bytes). - * @retval Pointer to the physical address where data should be read. - */ -uint8_t *OTP_If_Read (uint32_t Add, uint32_t Len) -{ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - uint32_t idx = 0; - for (idx = 0; idx < Len; idx += 4) - { - *(uint32_t*)(MAL_Buffer + idx) = *(uint32_t *)(Add + idx); - } - return (uint8_t*)(MAL_Buffer); -#else - return (uint8_t*)(Add); -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -} - -/** - * @brief OTP_If_CheckAdd - * Check if the address is an allowed address for this memory. - * @param Add: Address to be checked. - * @param Len: Number of data to be read (in bytes). - * @retval MAL_OK if the address is allowed, MAL_FAIL else. - */ -uint16_t OTP_If_CheckAdd(uint32_t Add) -{ - if ((Add >= OTP_START_ADD) && (Add < OTP_END_ADD)) - { - return MAL_OK; - } - else - { - return MAL_FAIL; - } -} -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_otp_if.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Specific media access Layer for OTP (One Time Programming) memory. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_otp_if.h" +#include "usbd_dfu_mal.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +uint16_t OTP_If_Write (uint32_t Add, uint32_t Len); +uint8_t *OTP_If_Read (uint32_t Add, uint32_t Len); +uint16_t OTP_If_DeInit(void); +uint16_t OTP_If_CheckAdd(uint32_t Add); + + +/* Private variables ---------------------------------------------------------*/ +DFU_MAL_Prop_TypeDef DFU_Otp_cb = + { + OTP_IF_STRING, + NULL, /* Init not supported*/ + NULL, /* DeInit not supported */ + NULL, /* Erase not supported */ + OTP_If_Write, + OTP_If_Read, + OTP_If_CheckAdd, + 1, /* Erase Time in ms */ + 10 /* Programming Time in ms */ + }; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief OTP_If_Write + * Memory write routine. + * @param Add: Address to be written to. + * @param Len: Number of data to be written (in bytes). + * @retval MAL_OK if operation is successful, MAL_FAIL else. + */ +uint16_t OTP_If_Write(uint32_t Add, uint32_t Len) +{ + uint32_t idx = 0; + + if (Len & 0x3) /* Not an aligned data */ + { + for (idx = Len; idx < ((Len & 0xFFFC) + 4); idx++) + { + MAL_Buffer[idx] = 0xFF; + } + } + + /* Data received are Word multiple */ + for (idx = 0; idx < Len; idx = idx + 4) + { + FLASH_ProgramWord(Add, *(uint32_t *)(MAL_Buffer + idx)); + Add += 4; + } + return MAL_OK; +} + +/** + * @brief OTP_If_Read + * Memory read routine. + * @param Add: Address to be read from. + * @param Len: Number of data to be read (in bytes). + * @retval Pointer to the physical address where data should be read. + */ +uint8_t *OTP_If_Read (uint32_t Add, uint32_t Len) +{ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + uint32_t idx = 0; + for (idx = 0; idx < Len; idx += 4) + { + *(uint32_t*)(MAL_Buffer + idx) = *(uint32_t *)(Add + idx); + } + return (uint8_t*)(MAL_Buffer); +#else + return (uint8_t*)(Add); +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +} + +/** + * @brief OTP_If_CheckAdd + * Check if the address is an allowed address for this memory. + * @param Add: Address to be checked. + * @param Len: Number of data to be read (in bytes). + * @retval MAL_OK if the address is allowed, MAL_FAIL else. + */ +uint16_t OTP_If_CheckAdd(uint32_t Add) +{ + if ((Add >= OTP_START_ADD) && (Add < OTP_END_ADD)) + { + return MAL_OK; + } + else + { + return MAL_FAIL; + } +} +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid/inc/usbd_hid_core.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid/inc/usbd_hid_core.h index 0fbfa416b..e8501a973 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid/inc/usbd_hid_core.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid/inc/usbd_hid_core.h @@ -1,121 +1,121 @@ -/** - ****************************************************************************** - * @file usbd_hid_core.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header file for the usbd_hid_core.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_HID_CORE_H_ -#define __USB_HID_CORE_H_ - -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_HID - * @brief This file is the Header file for USBD_msc.c - * @{ - */ - - -/** @defgroup USBD_HID_Exported_Defines - * @{ - */ -#define USB_HID_CONFIG_DESC_SIZ 34 -#define USB_HID_DESC_SIZ 9 -#define HID_MOUSE_REPORT_DESC_SIZE 74 - -#define HID_DESCRIPTOR_TYPE 0x21 -#define HID_REPORT_DESC 0x22 - -#define HID_HS_BINTERVAL 0x07 -#define HID_FS_BINTERVAL 0x0A - -#define HID_REQ_SET_PROTOCOL 0x0B -#define HID_REQ_GET_PROTOCOL 0x03 - -#define HID_REQ_SET_IDLE 0x0A -#define HID_REQ_GET_IDLE 0x02 - -#define HID_REQ_SET_REPORT 0x09 -#define HID_REQ_GET_REPORT 0x01 -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern const USBD_Class_cb_TypeDef USBD_HID_cb; // modified by OpenTX -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -uint8_t USBD_HID_SendReport (USB_OTG_CORE_HANDLE *pdev, - uint8_t *report, - uint16_t len); - -uint32_t USBD_HID_GetPollingInterval (USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - -#endif /* __USB_HID_CORE_H_ */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_hid_core.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header file for the usbd_hid_core.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +#ifndef __USB_HID_CORE_H_ +#define __USB_HID_CORE_H_ + +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_HID + * @brief This file is the Header file for USBD_msc.c + * @{ + */ + + +/** @defgroup USBD_HID_Exported_Defines + * @{ + */ +#define USB_HID_CONFIG_DESC_SIZ 34 +#define USB_HID_DESC_SIZ 9 +#define HID_MOUSE_REPORT_DESC_SIZE 74 + +#define HID_DESCRIPTOR_TYPE 0x21 +#define HID_REPORT_DESC 0x22 + +#define HID_HS_BINTERVAL 0x07 +#define HID_FS_BINTERVAL 0x0A + +#define HID_REQ_SET_PROTOCOL 0x0B +#define HID_REQ_GET_PROTOCOL 0x03 + +#define HID_REQ_SET_IDLE 0x0A +#define HID_REQ_GET_IDLE 0x02 + +#define HID_REQ_SET_REPORT 0x09 +#define HID_REQ_GET_REPORT 0x01 +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern const USBD_Class_cb_TypeDef USBD_HID_cb; // modified by OpenTX +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +uint8_t USBD_HID_SendReport (USB_OTG_CORE_HANDLE *pdev, + uint8_t *report, + uint16_t len); + +uint32_t USBD_HID_GetPollingInterval (USB_OTG_CORE_HANDLE *pdev); + +/** + * @} + */ + +#endif /* __USB_HID_CORE_H_ */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c index e451fba9d..d5ff68328 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c @@ -1,519 +1,519 @@ -/** - ****************************************************************************** - * @file usbd_hid_core.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides the HID core functions. - * - * @verbatim - * - * =================================================================== - * HID Class Description - * =================================================================== - * This module manages the HID class V1.11 following the "Device Class Definition - * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001". - * This driver implements the following aspects of the specification: - * - The Boot Interface Subclass - * - The Mouse protocol - * - Usage Page : Generic Desktop - * - Usage : Joystick) - * - Collection : Application - * - * @note In HS mode and when the DMA is used, all variables and data structures - * dealing with the DMA during the transaction process should be 32-bit aligned. - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_hid_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_HID - * @brief usbd core module - * @{ - */ - -/** @defgroup USBD_HID_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_HID_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_HID_Private_Macros - * @{ - */ -/** - * @} - */ - - - - -/** @defgroup USBD_HID_Private_FunctionPrototypes - * @{ - */ - - -uint8_t USBD_HID_Init (void *pdev, - uint8_t cfgidx); - -uint8_t USBD_HID_DeInit (void *pdev, - uint8_t cfgidx); - -uint8_t USBD_HID_Setup (void *pdev, - USB_SETUP_REQ *req); - -static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length); - -uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum); -/** - * @} - */ - -/** @defgroup USBD_HID_Private_Variables - * @{ - */ - -USBD_Class_cb_TypeDef USBD_HID_cb = -{ - USBD_HID_Init, - USBD_HID_DeInit, - USBD_HID_Setup, - NULL, /*EP0_TxSent*/ - NULL, /*EP0_RxReady*/ - USBD_HID_DataIn, /*DataIn*/ - NULL, /*DataOut*/ - NULL, /*SOF */ - NULL, - NULL, - USBD_HID_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_HID_GetCfgDesc, /* use same config as per FS */ -#endif -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_AltSet __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_Protocol __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_IdleState __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB HID device Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ - USB_HID_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ - 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ - 0x00, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ - 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ - - HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */ - 0x00, - HID_FS_BINTERVAL, /*bInterval: Polling Interval (10 ms)*/ - /* 34 */ -} ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -/* USB HID device Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_DESC_SIZ] __ALIGN_END= -{ - /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ - 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ - 0x00, -}; -#endif - - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END = -{ - 0x05, 0x01, - 0x09, 0x02, - 0xA1, 0x01, - 0x09, 0x01, - - 0xA1, 0x00, - 0x05, 0x09, - 0x19, 0x01, - 0x29, 0x03, - - 0x15, 0x00, - 0x25, 0x01, - 0x95, 0x03, - 0x75, 0x01, - - 0x81, 0x02, - 0x95, 0x01, - 0x75, 0x05, - 0x81, 0x01, - - 0x05, 0x01, - 0x09, 0x30, - 0x09, 0x31, - 0x09, 0x38, - - 0x15, 0x81, - 0x25, 0x7F, - 0x75, 0x08, - 0x95, 0x03, - - 0x81, 0x06, - 0xC0, 0x09, - 0x3c, 0x05, - 0xff, 0x09, - - 0x01, 0x15, - 0x00, 0x25, - 0x01, 0x75, - 0x01, 0x95, - - 0x02, 0xb1, - 0x22, 0x75, - 0x06, 0x95, - 0x01, 0xb1, - - 0x01, 0xc0 -}; - -/** - * @} - */ - -/** @defgroup USBD_HID_Private_Functions - * @{ - */ - -/** - * @brief USBD_HID_Init - * Initialize the HID interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -uint8_t USBD_HID_Init (void *pdev, - uint8_t cfgidx) -{ - - /* Open EP IN */ - DCD_EP_Open(pdev, - HID_IN_EP, - HID_IN_PACKET, - USB_OTG_EP_INT); - - return USBD_OK; -} - -/** - * @brief USBD_HID_Init - * DeInitialize the HID layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -uint8_t USBD_HID_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* Close HID EPs */ - DCD_EP_Close (pdev , HID_IN_EP); - return USBD_OK; -} - -/** - * @brief USBD_HID_Setup - * Handle the HID specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -uint8_t USBD_HID_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len = 0; - uint8_t *pbuf = NULL; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - case HID_REQ_SET_PROTOCOL: - USBD_HID_Protocol = (uint8_t)(req->wValue); - break; - - case HID_REQ_GET_PROTOCOL: - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_Protocol, - 1); - break; - - case HID_REQ_SET_IDLE: - USBD_HID_IdleState = (uint8_t)(req->wValue >> 8); - break; - - case HID_REQ_GET_IDLE: - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_IdleState, - 1); - break; - - default: - USBD_CtlError (pdev, req); - return USBD_FAIL; - } - break; - - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - if( req->wValue >> 8 == HID_REPORT_DESC) - { - len = MIN(HID_MOUSE_REPORT_DESC_SIZE , req->wLength); - pbuf = HID_MOUSE_ReportDesc; - } - else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE) - { - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pbuf = USBD_HID_Desc; -#else - pbuf = USBD_HID_CfgDesc + 0x12; -#endif - len = MIN(USB_HID_DESC_SIZ , req->wLength); - } - else - { - /* Do Nothing */ - } - - USBD_CtlSendData (pdev, - pbuf, - len); - - break; - - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - USBD_HID_AltSet = (uint8_t)(req->wValue); - break; - - default: - USBD_HID_AltSet = (uint8_t)(req->wValue); - break; - } - break; - - default: - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_AltSet, - 1); - break; - } - return USBD_OK; -} - -/** - * @brief USBD_HID_SendReport - * Send HID Report - * @param pdev: device instance - * @param buff: pointer to report - * @retval status - */ -uint8_t USBD_HID_SendReport (USB_OTG_CORE_HANDLE *pdev, - uint8_t *report, - uint16_t len) -{ - if (pdev->dev.device_status == USB_OTG_CONFIGURED ) - { - DCD_EP_Tx (pdev, HID_IN_EP, report, len); - } - return USBD_OK; -} - -/** - * @brief USBD_HID_GetCfgDesc - * return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (USBD_HID_CfgDesc); - return USBD_HID_CfgDesc; -} - -/** - * @brief USBD_HID_DataIn - * handle data IN Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -uint8_t USBD_HID_DataIn (void *pdev, - uint8_t epnum) -{ - - /* Ensure that the FIFO is empty before a new transfer, this condition could - be caused by a new transfer before the end of the previous transfer */ - DCD_EP_Flush(pdev, HID_IN_EP); - return USBD_OK; -} - -/** - * @brief USBD_HID_GetPollingInterval - * return polling interval from endpoint descriptor - * @param pdev: device instance - * @retval polling interval - */ -uint32_t USBD_HID_GetPollingInterval (USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t polling_interval = 0; - - /* HIGH-speed endpoints */ - if(pdev->cfg.speed == USB_OTG_SPEED_HIGH) - { - /* Sets the data transfer polling interval for high speed transfers. - Values between 1..16 are allowed. Values correspond to interval - of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */ - polling_interval = (((1 <<(HID_HS_BINTERVAL - 1)))/8); - } - else /* LOW and FULL-speed endpoints */ - { - /* Sets the data transfer polling interval for low and full - speed transfers */ - polling_interval = HID_FS_BINTERVAL; - } - - return ((uint32_t)(polling_interval)); -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_hid_core.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides the HID core functions. + * + * @verbatim + * + * =================================================================== + * HID Class Description + * =================================================================== + * This module manages the HID class V1.11 following the "Device Class Definition + * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001". + * This driver implements the following aspects of the specification: + * - The Boot Interface Subclass + * - The Mouse protocol + * - Usage Page : Generic Desktop + * - Usage : Joystick) + * - Collection : Application + * + * @note In HS mode and when the DMA is used, all variables and data structures + * dealing with the DMA during the transaction process should be 32-bit aligned. + * + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_hid_core.h" +#include "usbd_desc.h" +#include "usbd_req.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_HID + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_HID_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_HID_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_HID_Private_Macros + * @{ + */ +/** + * @} + */ + + + + +/** @defgroup USBD_HID_Private_FunctionPrototypes + * @{ + */ + + +uint8_t USBD_HID_Init (void *pdev, + uint8_t cfgidx); + +uint8_t USBD_HID_DeInit (void *pdev, + uint8_t cfgidx); + +uint8_t USBD_HID_Setup (void *pdev, + USB_SETUP_REQ *req); + +static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length); + +uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum); +/** + * @} + */ + +/** @defgroup USBD_HID_Private_Variables + * @{ + */ + +USBD_Class_cb_TypeDef USBD_HID_cb = +{ + USBD_HID_Init, + USBD_HID_DeInit, + USBD_HID_Setup, + NULL, /*EP0_TxSent*/ + NULL, /*EP0_RxReady*/ + USBD_HID_DataIn, /*DataIn*/ + NULL, /*DataOut*/ + NULL, /*SOF */ + NULL, + NULL, + USBD_HID_GetCfgDesc, +#ifdef USB_OTG_HS_CORE + USBD_HID_GetCfgDesc, /* use same config as per FS */ +#endif +}; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_AltSet __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_Protocol __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_IdleState __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +/* USB HID device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_HID_CONFIG_DESC_SIZ, + /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /*bNumInterfaces: 1 interface*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x00, /*iConfiguration: Index of string descriptor describing + the configuration*/ + 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /*bLength: Interface Descriptor size*/ + USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ + 0x00, /*bInterfaceNumber: Number of Interface*/ + 0x00, /*bAlternateSetting: Alternate setting*/ + 0x01, /*bNumEndpoints*/ + 0x03, /*bInterfaceClass: HID*/ + 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ + 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ + 0, /*iInterface: Index of string descriptor*/ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /*bLength: HID Descriptor size*/ + HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ + 0x11, /*bcdHID: HID Class Spec release number*/ + 0x01, + 0x00, /*bCountryCode: Hardware target country*/ + 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ + 0x22, /*bDescriptorType*/ + HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /*bLength: Endpoint Descriptor size*/ + USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ + + HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ + 0x03, /*bmAttributes: Interrupt endpoint*/ + HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */ + 0x00, + HID_FS_BINTERVAL, /*bInterval: Polling Interval (10 ms)*/ + /* 34 */ +} ; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +/* USB HID device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_DESC_SIZ] __ALIGN_END= +{ + /* 18 */ + 0x09, /*bLength: HID Descriptor size*/ + HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ + 0x11, /*bcdHID: HID Class Spec release number*/ + 0x01, + 0x00, /*bCountryCode: Hardware target country*/ + 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ + 0x22, /*bDescriptorType*/ + HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, +}; +#endif + + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END = +{ + 0x05, 0x01, + 0x09, 0x02, + 0xA1, 0x01, + 0x09, 0x01, + + 0xA1, 0x00, + 0x05, 0x09, + 0x19, 0x01, + 0x29, 0x03, + + 0x15, 0x00, + 0x25, 0x01, + 0x95, 0x03, + 0x75, 0x01, + + 0x81, 0x02, + 0x95, 0x01, + 0x75, 0x05, + 0x81, 0x01, + + 0x05, 0x01, + 0x09, 0x30, + 0x09, 0x31, + 0x09, 0x38, + + 0x15, 0x81, + 0x25, 0x7F, + 0x75, 0x08, + 0x95, 0x03, + + 0x81, 0x06, + 0xC0, 0x09, + 0x3c, 0x05, + 0xff, 0x09, + + 0x01, 0x15, + 0x00, 0x25, + 0x01, 0x75, + 0x01, 0x95, + + 0x02, 0xb1, + 0x22, 0x75, + 0x06, 0x95, + 0x01, 0xb1, + + 0x01, 0xc0 +}; + +/** + * @} + */ + +/** @defgroup USBD_HID_Private_Functions + * @{ + */ + +/** + * @brief USBD_HID_Init + * Initialize the HID interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +uint8_t USBD_HID_Init (void *pdev, + uint8_t cfgidx) +{ + + /* Open EP IN */ + DCD_EP_Open(pdev, + HID_IN_EP, + HID_IN_PACKET, + USB_OTG_EP_INT); + + return USBD_OK; +} + +/** + * @brief USBD_HID_Init + * DeInitialize the HID layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +uint8_t USBD_HID_DeInit (void *pdev, + uint8_t cfgidx) +{ + /* Close HID EPs */ + DCD_EP_Close (pdev , HID_IN_EP); + return USBD_OK; +} + +/** + * @brief USBD_HID_Setup + * Handle the HID specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +uint8_t USBD_HID_Setup (void *pdev, + USB_SETUP_REQ *req) +{ + uint16_t len = 0; + uint8_t *pbuf = NULL; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case HID_REQ_SET_PROTOCOL: + USBD_HID_Protocol = (uint8_t)(req->wValue); + break; + + case HID_REQ_GET_PROTOCOL: + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_HID_Protocol, + 1); + break; + + case HID_REQ_SET_IDLE: + USBD_HID_IdleState = (uint8_t)(req->wValue >> 8); + break; + + case HID_REQ_GET_IDLE: + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_HID_IdleState, + 1); + break; + + default: + USBD_CtlError (pdev, req); + return USBD_FAIL; + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + if( req->wValue >> 8 == HID_REPORT_DESC) + { + len = MIN(HID_MOUSE_REPORT_DESC_SIZE , req->wLength); + pbuf = HID_MOUSE_ReportDesc; + } + else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE) + { + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + pbuf = USBD_HID_Desc; +#else + pbuf = USBD_HID_CfgDesc + 0x12; +#endif + len = MIN(USB_HID_DESC_SIZ , req->wLength); + } + else + { + /* Do Nothing */ + } + + USBD_CtlSendData (pdev, + pbuf, + len); + + break; + + case USB_REQ_GET_INTERFACE : + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_HID_AltSet, + 1); + break; + + case USB_REQ_SET_INTERFACE : + USBD_HID_AltSet = (uint8_t)(req->wValue); + break; + + default: + USBD_HID_AltSet = (uint8_t)(req->wValue); + break; + } + break; + + default: + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_HID_AltSet, + 1); + break; + } + return USBD_OK; +} + +/** + * @brief USBD_HID_SendReport + * Send HID Report + * @param pdev: device instance + * @param buff: pointer to report + * @retval status + */ +uint8_t USBD_HID_SendReport (USB_OTG_CORE_HANDLE *pdev, + uint8_t *report, + uint16_t len) +{ + if (pdev->dev.device_status == USB_OTG_CONFIGURED ) + { + DCD_EP_Tx (pdev, HID_IN_EP, report, len); + } + return USBD_OK; +} + +/** + * @brief USBD_HID_GetCfgDesc + * return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_HID_CfgDesc); + return USBD_HID_CfgDesc; +} + +/** + * @brief USBD_HID_DataIn + * handle data IN Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ +uint8_t USBD_HID_DataIn (void *pdev, + uint8_t epnum) +{ + + /* Ensure that the FIFO is empty before a new transfer, this condition could + be caused by a new transfer before the end of the previous transfer */ + DCD_EP_Flush(pdev, HID_IN_EP); + return USBD_OK; +} + +/** + * @brief USBD_HID_GetPollingInterval + * return polling interval from endpoint descriptor + * @param pdev: device instance + * @retval polling interval + */ +uint32_t USBD_HID_GetPollingInterval (USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t polling_interval = 0; + + /* HIGH-speed endpoints */ + if(pdev->cfg.speed == USB_OTG_SPEED_HIGH) + { + /* Sets the data transfer polling interval for high speed transfers. + Values between 1..16 are allowed. Values correspond to interval + of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */ + polling_interval = (((1 <<(HID_HS_BINTERVAL - 1)))/8); + } + else /* LOW and FULL-speed endpoints */ + { + /* Sets the data transfer polling interval for low and full + speed transfers */ + polling_interval = HID_FS_BINTERVAL; + } + + return ((uint32_t)(polling_interval)); +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/inc/usbd_hid_cdc_wrapper.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/inc/usbd_hid_cdc_wrapper.h index 79d246914..b22708729 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/inc/usbd_hid_cdc_wrapper.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/inc/usbd_hid_cdc_wrapper.h @@ -1,96 +1,96 @@ -/** - ****************************************************************************** - * @file usbd_hid_cdc_wrapper.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header file for the usbd_hid_cdc_wrapper.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_HID_CDC_WRAPPER_H_ -#define __USB_HID_CDC_WRAPPER_H_ - -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_HID_CDC - * @brief This file is the Header file for usbd_msc_cdc_wrapper.c - * @{ - */ - - -/** @defgroup USBD_HID_MSC_Exported_Defines - * @{ - */ - - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_Class_cb_TypeDef USBD_HID_CDC_cb; -/** - * @} - */ - -/** - * @} - */ - -#endif /* __USB_MSC_CDC_WRAPPER_H_ */ -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_hid_cdc_wrapper.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header file for the usbd_hid_cdc_wrapper.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +#ifndef __USB_HID_CDC_WRAPPER_H_ +#define __USB_HID_CDC_WRAPPER_H_ + +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_HID_CDC + * @brief This file is the Header file for usbd_msc_cdc_wrapper.c + * @{ + */ + + +/** @defgroup USBD_HID_MSC_Exported_Defines + * @{ + */ + + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_Class_cb_TypeDef USBD_HID_CDC_cb; +/** + * @} + */ + +/** + * @} + */ + +#endif /* __USB_MSC_CDC_WRAPPER_H_ */ +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/src/usbd_hid_cdc_wrapper.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/src/usbd_hid_cdc_wrapper.c index 235f6f704..6183ac00a 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/src/usbd_hid_cdc_wrapper.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/src/usbd_hid_cdc_wrapper.c @@ -1,461 +1,461 @@ -/** - ****************************************************************************** - * @file usbd_hid_cdc_wrapper.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief - * - * @verbatim - * - * =================================================================== - * composite HID_CDC - * =================================================================== - * - * @note In HS mode and when the DMA is used, all variables and data structures - * dealing with the DMA during the transaction process should be 32-bit aligned. - * - * - * @endverbatim - * - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_hid_core.h" -#include "usbd_cdc_core.h" -#include "usbd_hid_cdc_wrapper.h" -#include "usbd_desc.h" -#include "usbd_req.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_MSC_VCP - * @brief usbd core module - * @{ - */ - -/** @defgroup USBD_MSC_VCP_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_MSC_VCP_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_MSC_VCP_Private_Macros - * @{ - */ -/** - * @} - */ - - - - -/** @defgroup USBD_MSC_VCP_Private_FunctionPrototypes - * @{ - */ - -/********************************************* - CDC Device library callbacks - *********************************************/ -extern uint8_t usbd_cdc_Init (void *pdev, uint8_t cfgidx); -extern uint8_t usbd_cdc_DeInit (void *pdev, uint8_t cfgidx); -extern uint8_t usbd_cdc_Setup (void *pdev, USB_SETUP_REQ *req); -extern uint8_t usbd_cdc_EP0_RxReady (void *pdev); -extern uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum); -extern uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum); -extern uint8_t usbd_cdc_SOF (void *pdev); - -extern uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length); -#ifdef USE_USB_OTG_HS -extern uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length); -#endif - -/********************************************* - MSC Device library callbacks - *********************************************/ -extern uint8_t USBD_HID_Init (void *pdev, uint8_t cfgidx); -extern uint8_t USBD_HID_DeInit (void *pdev, uint8_t cfgidx); -extern uint8_t USBD_HID_Setup (void *pdev, USB_SETUP_REQ *req); -extern uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum); -extern uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length); -extern uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ]; - -/** - * @} - */ - -/** @defgroup USBD_MSC_CDC_Private_Variables - * @{ - */ - - -static uint8_t USBD_HID_CDC_Init (void *pdev , uint8_t cfgidx); -static uint8_t USBD_HID_CDC_DeInit (void *pdev , uint8_t cfgidx); - -/* Control Endpoints*/ -static uint8_t USBD_HID_CDC_Setup (void *pdev , USB_SETUP_REQ *req); -static uint8_t USBD_HID_CDC_EP0_RxReady (void *pdev ); - -/* Class Specific Endpoints*/ -static uint8_t USBD_HID_CDC_DataIn (void *pdev , uint8_t epnum); -static uint8_t USBD_HID_CDC_DataOut (void *pdev , uint8_t epnum); -static uint8_t USBD_HID_CDC_SOF (void *pdev); -static uint8_t* USBD_HID_CDC_GetConfigDescriptor( uint8_t speed , uint16_t *length); - -#define USB_HID_CDC_CONFIG_DESC_SIZ (USB_HID_CONFIG_DESC_SIZ -9 + USB_CDC_CONFIG_DESC_SIZ + 8) - -#define HID_INTERFACE 0x0 -#define CDC_COM_INTERFACE 0x1 - - -USBD_Class_cb_TypeDef USBD_HID_CDC_cb = -{ - USBD_HID_CDC_Init, - USBD_HID_CDC_DeInit, - USBD_HID_CDC_Setup, - NULL, - USBD_HID_CDC_EP0_RxReady, - USBD_HID_CDC_DataIn, - USBD_HID_CDC_DataOut, - USBD_HID_CDC_SOF, - NULL, - NULL, - USBD_HID_CDC_GetConfigDescriptor, -}; - - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB MSC/CDC device Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_CDC_CfgDesc[USB_HID_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ - USB_HID_CDC_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ - 0x00, - 0x03, /*bNumInterfaces: 3 interfaces (2 for CDC, 1 for MSC)*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ - HID_INTERFACE, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ - 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ - - HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */ - 0x00, - 0x0A, /*bInterval: Polling Interval (10 ms)*/ - /* 34 */ - - /******** /IAD should be positioned just before the CDC interfaces ****** - IAD to associate the two CDC interfaces */ - - 0x08, /* bLength */ - 0x0B, /* bDescriptorType */ - 0x01, /* bFirstInterface */ - 0x02, /* bInterfaceCount */ - 0x02, /* bFunctionClass */ - 0x02, /* bFunctionSubClass */ - 0x01, /* bFunctionProtocol */ - 0x00, /* iFunction (Index of string descriptor describing this function) */ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - CDC_COM_INTERFACE, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x01, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x02, /* bDataInterface: 2 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x01, /* bMasterInterface: Communication class interface */ - 0x02, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SZE), - 0xFF, /* bInterval: */ - - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ - 0x02, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_MAX_PACKET_SIZE), - 0x00, /* bInterval */ - -} ; - - -/** - * @} - */ - -/** @defgroup USBD_CDC_MSC_Private_Functions - * @{ - */ - -/** - * @brief USBD_MSC_CDC_Init - * Initialize the MSC & CDC interfaces - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_HID_CDC_Init (void *pdev, - uint8_t cfgidx) -{ - - /* HID initialization */ - USBD_HID_Init (pdev,cfgidx); - - /* CDC initialization */ - usbd_cdc_Init (pdev,cfgidx); - - return USBD_OK; - -} - -/** - * @brief USBD_MSC_CDC_Init - * DeInitialize the MSC/CDC interfaces - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_HID_CDC_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* MSC De-initialization */ - USBD_HID_DeInit (pdev,cfgidx); - - /* CDC De-initialization */ - usbd_cdc_DeInit (pdev,cfgidx); - - - return USBD_OK; -} - -/** - * @brief USBD_MSC_CDC_Setup - * Handle the MSC/CDC specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t USBD_HID_CDC_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) - { - case USB_REQ_RECIPIENT_INTERFACE: - if (req->wIndex == HID_INTERFACE) - { - return (USBD_HID_Setup (pdev, req)); - } - else - { - return (usbd_cdc_Setup(pdev, req)); - } - - case USB_REQ_RECIPIENT_ENDPOINT: - if (req->wIndex == HID_IN_EP) - { - return (USBD_HID_Setup (pdev, req)); - } - else - { - return (usbd_cdc_Setup(pdev, req)); - } - } - return USBD_OK; -} - -/** - * @brief USBD_MSC_CDC_GetCfgDesc - * return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -uint8_t *USBD_HID_CDC_GetConfigDescriptor (uint8_t speed, uint16_t *length) -{ - *length = sizeof (USBD_HID_CDC_CfgDesc); - return USBD_HID_CDC_CfgDesc; -} - -/** - * @brief USBD_MSC_CDC_DataIn - * handle data IN Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_HID_CDC_DataIn (void *pdev, - uint8_t epnum) -{ - /*DataIN can be for CDC or MSC */ - - if (epnum == (CDC_IN_EP&~0x80) ) - { - return (usbd_cdc_DataIn(pdev, epnum)); - } - else - { - return (USBD_HID_DataIn(pdev, epnum)); - } -} - - -uint8_t USBD_HID_CDC_DataOut(void *pdev , uint8_t epnum) -{ - /*DataOut can be for CDC */ - return (usbd_cdc_DataOut(pdev, epnum)); -} - - -uint8_t USBD_HID_CDC_SOF (void *pdev) -{ - /*SOF processing needed for CDC */ - return (usbd_cdc_SOF(pdev)); -} - - -uint8_t USBD_HID_CDC_EP0_RxReady (void *pdev ) -{ - /*RxReady processing needed for CDC only*/ - return (usbd_cdc_EP0_RxReady(pdev)); -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_hid_cdc_wrapper.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief + * + * @verbatim + * + * =================================================================== + * composite HID_CDC + * =================================================================== + * + * @note In HS mode and when the DMA is used, all variables and data structures + * dealing with the DMA during the transaction process should be 32-bit aligned. + * + * + * @endverbatim + * + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_hid_core.h" +#include "usbd_cdc_core.h" +#include "usbd_hid_cdc_wrapper.h" +#include "usbd_desc.h" +#include "usbd_req.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_MSC_VCP + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_MSC_VCP_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_MSC_VCP_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_MSC_VCP_Private_Macros + * @{ + */ +/** + * @} + */ + + + + +/** @defgroup USBD_MSC_VCP_Private_FunctionPrototypes + * @{ + */ + +/********************************************* + CDC Device library callbacks + *********************************************/ +extern uint8_t usbd_cdc_Init (void *pdev, uint8_t cfgidx); +extern uint8_t usbd_cdc_DeInit (void *pdev, uint8_t cfgidx); +extern uint8_t usbd_cdc_Setup (void *pdev, USB_SETUP_REQ *req); +extern uint8_t usbd_cdc_EP0_RxReady (void *pdev); +extern uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum); +extern uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum); +extern uint8_t usbd_cdc_SOF (void *pdev); + +extern uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length); +#ifdef USE_USB_OTG_HS +extern uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length); +#endif + +/********************************************* + MSC Device library callbacks + *********************************************/ +extern uint8_t USBD_HID_Init (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_HID_DeInit (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_HID_Setup (void *pdev, USB_SETUP_REQ *req); +extern uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum); +extern uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length); +extern uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ]; + +/** + * @} + */ + +/** @defgroup USBD_MSC_CDC_Private_Variables + * @{ + */ + + +static uint8_t USBD_HID_CDC_Init (void *pdev , uint8_t cfgidx); +static uint8_t USBD_HID_CDC_DeInit (void *pdev , uint8_t cfgidx); + +/* Control Endpoints*/ +static uint8_t USBD_HID_CDC_Setup (void *pdev , USB_SETUP_REQ *req); +static uint8_t USBD_HID_CDC_EP0_RxReady (void *pdev ); + +/* Class Specific Endpoints*/ +static uint8_t USBD_HID_CDC_DataIn (void *pdev , uint8_t epnum); +static uint8_t USBD_HID_CDC_DataOut (void *pdev , uint8_t epnum); +static uint8_t USBD_HID_CDC_SOF (void *pdev); +static uint8_t* USBD_HID_CDC_GetConfigDescriptor( uint8_t speed , uint16_t *length); + +#define USB_HID_CDC_CONFIG_DESC_SIZ (USB_HID_CONFIG_DESC_SIZ -9 + USB_CDC_CONFIG_DESC_SIZ + 8) + +#define HID_INTERFACE 0x0 +#define CDC_COM_INTERFACE 0x1 + + +USBD_Class_cb_TypeDef USBD_HID_CDC_cb = +{ + USBD_HID_CDC_Init, + USBD_HID_CDC_DeInit, + USBD_HID_CDC_Setup, + NULL, + USBD_HID_CDC_EP0_RxReady, + USBD_HID_CDC_DataIn, + USBD_HID_CDC_DataOut, + USBD_HID_CDC_SOF, + NULL, + NULL, + USBD_HID_CDC_GetConfigDescriptor, +}; + + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +/* USB MSC/CDC device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_HID_CDC_CfgDesc[USB_HID_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_HID_CDC_CONFIG_DESC_SIZ, + /* wTotalLength: Bytes returned */ + 0x00, + 0x03, /*bNumInterfaces: 3 interfaces (2 for CDC, 1 for MSC)*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x00, /*iConfiguration: Index of string descriptor describing + the configuration*/ + 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /*bLength: Interface Descriptor size*/ + USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ + HID_INTERFACE, /*bInterfaceNumber: Number of Interface*/ + 0x00, /*bAlternateSetting: Alternate setting*/ + 0x01, /*bNumEndpoints*/ + 0x03, /*bInterfaceClass: HID*/ + 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ + 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ + 0, /*iInterface: Index of string descriptor*/ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /*bLength: HID Descriptor size*/ + HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ + 0x11, /*bcdHID: HID Class Spec release number*/ + 0x01, + 0x00, /*bCountryCode: Hardware target country*/ + 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ + 0x22, /*bDescriptorType*/ + HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /*bLength: Endpoint Descriptor size*/ + USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ + + HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ + 0x03, /*bmAttributes: Interrupt endpoint*/ + HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /*bInterval: Polling Interval (10 ms)*/ + /* 34 */ + + /******** /IAD should be positioned just before the CDC interfaces ****** + IAD to associate the two CDC interfaces */ + + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x01, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass */ + 0x02, /* bFunctionSubClass */ + 0x01, /* bFunctionProtocol */ + 0x00, /* iFunction (Index of string descriptor describing this function) */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + CDC_COM_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x01, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x02, /* bDataInterface: 2 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x01, /* bMasterInterface: Communication class interface */ + 0x02, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SZE), + 0xFF, /* bInterval: */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + 0x02, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval */ + +} ; + + +/** + * @} + */ + +/** @defgroup USBD_CDC_MSC_Private_Functions + * @{ + */ + +/** + * @brief USBD_MSC_CDC_Init + * Initialize the MSC & CDC interfaces + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_HID_CDC_Init (void *pdev, + uint8_t cfgidx) +{ + + /* HID initialization */ + USBD_HID_Init (pdev,cfgidx); + + /* CDC initialization */ + usbd_cdc_Init (pdev,cfgidx); + + return USBD_OK; + +} + +/** + * @brief USBD_MSC_CDC_Init + * DeInitialize the MSC/CDC interfaces + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_HID_CDC_DeInit (void *pdev, + uint8_t cfgidx) +{ + /* MSC De-initialization */ + USBD_HID_DeInit (pdev,cfgidx); + + /* CDC De-initialization */ + usbd_cdc_DeInit (pdev,cfgidx); + + + return USBD_OK; +} + +/** + * @brief USBD_MSC_CDC_Setup + * Handle the MSC/CDC specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_HID_CDC_Setup (void *pdev, + USB_SETUP_REQ *req) +{ + switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_INTERFACE: + if (req->wIndex == HID_INTERFACE) + { + return (USBD_HID_Setup (pdev, req)); + } + else + { + return (usbd_cdc_Setup(pdev, req)); + } + + case USB_REQ_RECIPIENT_ENDPOINT: + if (req->wIndex == HID_IN_EP) + { + return (USBD_HID_Setup (pdev, req)); + } + else + { + return (usbd_cdc_Setup(pdev, req)); + } + } + return USBD_OK; +} + +/** + * @brief USBD_MSC_CDC_GetCfgDesc + * return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +uint8_t *USBD_HID_CDC_GetConfigDescriptor (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_HID_CDC_CfgDesc); + return USBD_HID_CDC_CfgDesc; +} + +/** + * @brief USBD_MSC_CDC_DataIn + * handle data IN Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ +static uint8_t USBD_HID_CDC_DataIn (void *pdev, + uint8_t epnum) +{ + /*DataIN can be for CDC or MSC */ + + if (epnum == (CDC_IN_EP&~0x80) ) + { + return (usbd_cdc_DataIn(pdev, epnum)); + } + else + { + return (USBD_HID_DataIn(pdev, epnum)); + } +} + + +uint8_t USBD_HID_CDC_DataOut(void *pdev , uint8_t epnum) +{ + /*DataOut can be for CDC */ + return (usbd_cdc_DataOut(pdev, epnum)); +} + + +uint8_t USBD_HID_CDC_SOF (void *pdev) +{ + /*SOF processing needed for CDC */ + return (usbd_cdc_SOF(pdev)); +} + + +uint8_t USBD_HID_CDC_EP0_RxReady (void *pdev ) +{ + /*RxReady processing needed for CDC only*/ + return (usbd_cdc_EP0_RxReady(pdev)); +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/inc/usbd_msc_hid_core.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/inc/usbd_msc_hid_core.h index 344b799eb..2233c3b2a 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/inc/usbd_msc_hid_core.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/inc/usbd_msc_hid_core.h @@ -1,100 +1,100 @@ -/** - ****************************************************************************** - * @file usbd_msc_hid_core.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header file for the usbd_msc_hid_core.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_MSC_HID_CORE_H_ -#define __USB_MSC_HID_CORE_H_ - -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_HID - * @brief This file is the Header file for USBD_msc.c - * @{ - */ -#define HID_INTERFACE 0x0 -#define MSC_INTERFACE 0x1 - -/** @defgroup USBD_HID_Exported_Defines - * @{ - */ -#define USB_MSC_HID_CONFIG_DESC_SIZ (USB_HID_CONFIG_DESC_SIZ -9 + USB_MSC_CONFIG_DESC_SIZ) -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_Class_cb_TypeDef USBD_MSC_HID_cb; -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ - -/** - * @} - */ - -#endif /* __USB_HID_CORE_H_ */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_msc_hid_core.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header file for the usbd_msc_hid_core.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +#ifndef __USB_MSC_HID_CORE_H_ +#define __USB_MSC_HID_CORE_H_ + +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_HID + * @brief This file is the Header file for USBD_msc.c + * @{ + */ +#define HID_INTERFACE 0x0 +#define MSC_INTERFACE 0x1 + +/** @defgroup USBD_HID_Exported_Defines + * @{ + */ +#define USB_MSC_HID_CONFIG_DESC_SIZ (USB_HID_CONFIG_DESC_SIZ -9 + USB_MSC_CONFIG_DESC_SIZ) +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_Class_cb_TypeDef USBD_MSC_HID_cb; +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ + +/** + * @} + */ + +#endif /* __USB_HID_CORE_H_ */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/src/usbd_msc_hid_core.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/src/usbd_msc_hid_core.c index 2b04247ef..109057ae2 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/src/usbd_msc_hid_core.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/src/usbd_msc_hid_core.c @@ -1,378 +1,378 @@ -/** - ****************************************************************************** - * @file usbd_msc_hid_core.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides the HID core functions. - * - * @verbatim - * - * =================================================================== - * composite HID_MSC - * =================================================================== - * - * @note In HS mode and when the DMA is used, all variables and data structures - * dealing with the DMA during the transaction process should be 32-bit aligned. - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_hid_core.h" -#include "usbd_msc_core.h" -#include "usbd_hid_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_HID - * @brief usbd core module - * @{ - */ - -/** @defgroup USBD_HID_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_HID_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_HID_Private_Macros - * @{ - */ -/** - * @} - */ - - - - -/** @defgroup USBD_HID_Private_FunctionPrototypes - * @{ - */ - - -static uint8_t USBD_MSC_HID_Init (void *pdev, - uint8_t cfgidx); - -static uint8_t USBD_MSC_HID_DeInit (void *pdev, - uint8_t cfgidx); - -static uint8_t USBD_MSC_HID_Setup (void *pdev, - USB_SETUP_REQ *req); - -static uint8_t *USBD_MSC_HID_GetCfgDesc (uint8_t speed, uint16_t *length); - -static uint8_t USBD_MSC_HID_DataIn (void *pdev, uint8_t epnum); -static uint8_t USBD_MSC_HID_DataOut(void *pdev , uint8_t epnum); -/** - * @} - */ - -/** @defgroup USBD_HID_Private_Variables - * @{ - */ - -USBD_Class_cb_TypeDef USBD_MSC_HID_cb = -{ - USBD_MSC_HID_Init, - USBD_MSC_HID_DeInit, - USBD_MSC_HID_Setup, - NULL, /*EP0_TxSent*/ - NULL, /*EP0_RxReady*/ - USBD_MSC_HID_DataIn, /*DataIn*/ - USBD_MSC_HID_DataOut, /*DataOut*/ - NULL, /*SOF */ - NULL, - NULL, - USBD_MSC_HID_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_MSC_HID_GetCfgDesc, /* use same config as per FS */ -#endif -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB HID device Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_MSC_HID_CfgDesc[USB_MSC_HID_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ - USB_MSC_HID_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ - 0x00, - 0x02, /*bNumInterfaces: 2 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ - HID_INTERFACE, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ - 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ - - HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */ - 0x00, - 0x0A, /*bInterval: Polling Interval (10 ms)*/ - /* 34 */ - - /******************** Mass Storage interface ********************/ - 0x09, /* bLength: Interface Descriptor size */ - 0x04, /* bDescriptorType: */ - MSC_INTERFACE, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints*/ - 0x08, /* bInterfaceClass: MSC Class */ - 0x06, /* bInterfaceSubClass : SCSI transparent*/ - 0x50, /* nInterfaceProtocol */ - 0x05, /* iInterface: */ - /******************** Mass Storage Endpoints ********************/ - 0x07, /*Endpoint descriptor length = 7*/ - 0x05, /*Endpoint descriptor type */ - MSC_IN_EP, /*Endpoint address (IN, address 1) */ - 0x02, /*Bulk endpoint type */ - LOBYTE(MSC_MAX_PACKET), - HIBYTE(MSC_MAX_PACKET), - 0x00, /*Polling interval in milliseconds */ - - 0x07, /*Endpoint descriptor length = 7 */ - 0x05, /*Endpoint descriptor type */ - MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ - 0x02, /*Bulk endpoint type */ - LOBYTE(MSC_MAX_PACKET), - HIBYTE(MSC_MAX_PACKET), - 0x00 /*Polling interval in milliseconds*/ -} ; - -/* Private function prototypes -----------------------------------------------*/ - -/********************************************* - MSC Device library callbacks -*********************************************/ -extern uint8_t USBD_MSC_Init (void *pdev, uint8_t cfgidx); -extern uint8_t USBD_MSC_DeInit (void *pdev, uint8_t cfgidx); -extern uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req); -extern uint8_t USBD_MSC_DataIn (void *pdev, uint8_t epnum); -extern uint8_t USBD_MSC_DataOut (void *pdev, uint8_t epnum); -extern uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length); -extern uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ]; - -/********************************************* - HID Device library callbacks -*********************************************/ -extern uint8_t USBD_HID_Init (void *pdev, uint8_t cfgidx); -extern uint8_t USBD_HID_DeInit (void *pdev, uint8_t cfgidx); -extern uint8_t USBD_HID_Setup (void *pdev, USB_SETUP_REQ *req); -extern uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length); -extern uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum); -extern uint8_t USBD_HID_DataOut (void *pdev, uint8_t epnum); - -/** - * @} - */ - -/** @defgroup USBD_MSC_HID_Private_Functions - * @{ - */ - -/** - * @brief USBD_MSC_HID_Init - * Initialize the MSC-HID interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_MSC_HID_Init (void *pdev, - uint8_t cfgidx) -{ - /* HID initialization */ - USBD_HID_Init (pdev,cfgidx); - - /* MSC initialization */ - USBD_MSC_Init (pdev,cfgidx); - - return USBD_OK; -} - -/** - * @brief USBD_MSC_HID_DeInit - * DeInitialize the MSC_HID layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_MSC_HID_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* HID De-initialization */ - USBD_HID_DeInit (pdev,cfgidx); - - /* MSC De-initialization */ - USBD_MSC_DeInit (pdev,cfgidx); - - return USBD_OK; -} - -/** - * @brief USBD_MSC_HID_Setup - * Handle the MSC_HID specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t USBD_MSC_HID_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) - { - case USB_REQ_RECIPIENT_INTERFACE: - if (req->wIndex == HID_INTERFACE) - { - return (USBD_HID_Setup (pdev, req)); - } - else - { - return (USBD_MSC_Setup(pdev, req)); - } - - case USB_REQ_RECIPIENT_ENDPOINT: - if (req->wIndex == HID_IN_EP) - { - return (USBD_HID_Setup (pdev, req)); - } - else - { - return (USBD_MSC_Setup(pdev, req)); - } - } - return USBD_OK; -} - -/** - * @brief USBD_MSC_HID_GetCfgDesc - * return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_MSC_HID_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (USBD_MSC_HID_CfgDesc); - return USBD_MSC_HID_CfgDesc; -} - -/** - * @brief USBD_MSC_HID_DataIn - * handle data IN Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_MSC_HID_DataIn (void *pdev, - uint8_t epnum) -{ - /*DataIN can be for MSC or HID */ - - if (epnum == (MSC_IN_EP&~0x80) ) - { - return (USBD_MSC_DataIn(pdev, epnum)); - } - else - { - return (USBD_HID_DataIn(pdev, epnum)); - } -} - -/** - * @brief USBD_MSC_HID_DataOut - * handle data OUT Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_MSC_HID_DataOut(void *pdev , uint8_t epnum) -{ - /*DataOut can be for MSC*/ - return (USBD_MSC_DataOut(pdev, epnum)); -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_msc_hid_core.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides the HID core functions. + * + * @verbatim + * + * =================================================================== + * composite HID_MSC + * =================================================================== + * + * @note In HS mode and when the DMA is used, all variables and data structures + * dealing with the DMA during the transaction process should be 32-bit aligned. + * + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_msc_hid_core.h" +#include "usbd_msc_core.h" +#include "usbd_hid_core.h" +#include "usbd_desc.h" +#include "usbd_req.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_HID + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_HID_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_HID_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_HID_Private_Macros + * @{ + */ +/** + * @} + */ + + + + +/** @defgroup USBD_HID_Private_FunctionPrototypes + * @{ + */ + + +static uint8_t USBD_MSC_HID_Init (void *pdev, + uint8_t cfgidx); + +static uint8_t USBD_MSC_HID_DeInit (void *pdev, + uint8_t cfgidx); + +static uint8_t USBD_MSC_HID_Setup (void *pdev, + USB_SETUP_REQ *req); + +static uint8_t *USBD_MSC_HID_GetCfgDesc (uint8_t speed, uint16_t *length); + +static uint8_t USBD_MSC_HID_DataIn (void *pdev, uint8_t epnum); +static uint8_t USBD_MSC_HID_DataOut(void *pdev , uint8_t epnum); +/** + * @} + */ + +/** @defgroup USBD_HID_Private_Variables + * @{ + */ + +USBD_Class_cb_TypeDef USBD_MSC_HID_cb = +{ + USBD_MSC_HID_Init, + USBD_MSC_HID_DeInit, + USBD_MSC_HID_Setup, + NULL, /*EP0_TxSent*/ + NULL, /*EP0_RxReady*/ + USBD_MSC_HID_DataIn, /*DataIn*/ + USBD_MSC_HID_DataOut, /*DataOut*/ + NULL, /*SOF */ + NULL, + NULL, + USBD_MSC_HID_GetCfgDesc, +#ifdef USB_OTG_HS_CORE + USBD_MSC_HID_GetCfgDesc, /* use same config as per FS */ +#endif +}; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +/* USB HID device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_MSC_HID_CfgDesc[USB_MSC_HID_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_MSC_HID_CONFIG_DESC_SIZ, + /* wTotalLength: Bytes returned */ + 0x00, + 0x02, /*bNumInterfaces: 2 interface*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x00, /*iConfiguration: Index of string descriptor describing + the configuration*/ + 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /*bLength: Interface Descriptor size*/ + USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ + HID_INTERFACE, /*bInterfaceNumber: Number of Interface*/ + 0x00, /*bAlternateSetting: Alternate setting*/ + 0x01, /*bNumEndpoints*/ + 0x03, /*bInterfaceClass: HID*/ + 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ + 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ + 0, /*iInterface: Index of string descriptor*/ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /*bLength: HID Descriptor size*/ + HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ + 0x11, /*bcdHID: HID Class Spec release number*/ + 0x01, + 0x00, /*bCountryCode: Hardware target country*/ + 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ + 0x22, /*bDescriptorType*/ + HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /*bLength: Endpoint Descriptor size*/ + USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ + + HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ + 0x03, /*bmAttributes: Interrupt endpoint*/ + HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /*bInterval: Polling Interval (10 ms)*/ + /* 34 */ + + /******************** Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + MSC_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints ********************/ + 0x07, /*Endpoint descriptor length = 7*/ + 0x05, /*Endpoint descriptor type */ + MSC_IN_EP, /*Endpoint address (IN, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /*Polling interval in milliseconds */ + + 0x07, /*Endpoint descriptor length = 7 */ + 0x05, /*Endpoint descriptor type */ + MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00 /*Polling interval in milliseconds*/ +} ; + +/* Private function prototypes -----------------------------------------------*/ + +/********************************************* + MSC Device library callbacks +*********************************************/ +extern uint8_t USBD_MSC_Init (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_MSC_DeInit (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req); +extern uint8_t USBD_MSC_DataIn (void *pdev, uint8_t epnum); +extern uint8_t USBD_MSC_DataOut (void *pdev, uint8_t epnum); +extern uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length); +extern uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ]; + +/********************************************* + HID Device library callbacks +*********************************************/ +extern uint8_t USBD_HID_Init (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_HID_DeInit (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_HID_Setup (void *pdev, USB_SETUP_REQ *req); +extern uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length); +extern uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum); +extern uint8_t USBD_HID_DataOut (void *pdev, uint8_t epnum); + +/** + * @} + */ + +/** @defgroup USBD_MSC_HID_Private_Functions + * @{ + */ + +/** + * @brief USBD_MSC_HID_Init + * Initialize the MSC-HID interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_MSC_HID_Init (void *pdev, + uint8_t cfgidx) +{ + /* HID initialization */ + USBD_HID_Init (pdev,cfgidx); + + /* MSC initialization */ + USBD_MSC_Init (pdev,cfgidx); + + return USBD_OK; +} + +/** + * @brief USBD_MSC_HID_DeInit + * DeInitialize the MSC_HID layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_MSC_HID_DeInit (void *pdev, + uint8_t cfgidx) +{ + /* HID De-initialization */ + USBD_HID_DeInit (pdev,cfgidx); + + /* MSC De-initialization */ + USBD_MSC_DeInit (pdev,cfgidx); + + return USBD_OK; +} + +/** + * @brief USBD_MSC_HID_Setup + * Handle the MSC_HID specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_MSC_HID_Setup (void *pdev, + USB_SETUP_REQ *req) +{ + switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_INTERFACE: + if (req->wIndex == HID_INTERFACE) + { + return (USBD_HID_Setup (pdev, req)); + } + else + { + return (USBD_MSC_Setup(pdev, req)); + } + + case USB_REQ_RECIPIENT_ENDPOINT: + if (req->wIndex == HID_IN_EP) + { + return (USBD_HID_Setup (pdev, req)); + } + else + { + return (USBD_MSC_Setup(pdev, req)); + } + } + return USBD_OK; +} + +/** + * @brief USBD_MSC_HID_GetCfgDesc + * return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_MSC_HID_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_MSC_HID_CfgDesc); + return USBD_MSC_HID_CfgDesc; +} + +/** + * @brief USBD_MSC_HID_DataIn + * handle data IN Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ +static uint8_t USBD_MSC_HID_DataIn (void *pdev, + uint8_t epnum) +{ + /*DataIN can be for MSC or HID */ + + if (epnum == (MSC_IN_EP&~0x80) ) + { + return (USBD_MSC_DataIn(pdev, epnum)); + } + else + { + return (USBD_HID_DataIn(pdev, epnum)); + } +} + +/** + * @brief USBD_MSC_HID_DataOut + * handle data OUT Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ +static uint8_t USBD_MSC_HID_DataOut(void *pdev , uint8_t epnum) +{ + /*DataOut can be for MSC*/ + return (USBD_MSC_DataOut(pdev, epnum)); +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_bot.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_bot.h index 14d0d62fb..cf960ad4f 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_bot.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_bot.h @@ -1,153 +1,153 @@ -/** - ****************************************************************************** - * @file usbd_msc_bot.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header for the usbd_msc_bot.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#include "usbd_core.h" - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_MSC_BOT_H -#define __USBD_MSC_BOT_H - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup MSC_BOT - * @brief This file is the Header file for usbd_bot.c - * @{ - */ - - -/** @defgroup USBD_CORE_Exported_Defines - * @{ - */ -#define BOT_IDLE 0 /* Idle state */ -#define BOT_DATA_OUT 1 /* Data Out state */ -#define BOT_DATA_IN 2 /* Data In state */ -#define BOT_LAST_DATA_IN 3 /* Last Data In Last */ -#define BOT_SEND_DATA 4 /* Send Immediate data */ - -#define BOT_CBW_SIGNATURE 0x43425355 -#define BOT_CSW_SIGNATURE 0x53425355 -#define BOT_CBW_LENGTH 31 -#define BOT_CSW_LENGTH 13 - -/* CSW Status Definitions */ -#define CSW_CMD_PASSED 0x00 -#define CSW_CMD_FAILED 0x01 -#define CSW_PHASE_ERROR 0x02 - -/* BOT Status */ -#define BOT_STATE_NORMAL 0 -#define BOT_STATE_RECOVERY 1 -#define BOT_STATE_ERROR 2 - - -#define DIR_IN 0 -#define DIR_OUT 1 -#define BOTH_DIR 2 - -/** - * @} - */ - -/** @defgroup MSC_CORE_Private_TypesDefinitions - * @{ - */ - -typedef struct _MSC_BOT_CBW -{ - uint32_t dSignature; - uint32_t dTag; - uint32_t dDataLength; - uint8_t bmFlags; - uint8_t bLUN; - uint8_t bCBLength; - uint8_t CB[16]; -} -MSC_BOT_CBW_TypeDef; - - -typedef struct _MSC_BOT_CSW -{ - uint32_t dSignature; - uint32_t dTag; - uint32_t dDataResidue; - uint8_t bStatus; -} -MSC_BOT_CSW_TypeDef; - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_Types - * @{ - */ - -extern uint8_t MSC_BOT_Data[]; -extern uint16_t MSC_BOT_DataLen; -extern uint8_t MSC_BOT_State; -extern uint8_t MSC_BOT_BurstMode; -extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw; -extern MSC_BOT_CSW_TypeDef MSC_BOT_csw; -/** - * @} - */ -/** @defgroup USBD_CORE_Exported_FunctionsPrototypes - * @{ - */ -void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); - -void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); - -void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, - uint8_t CSW_Status); - -void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -/** - * @} - */ - -#endif /* __USBD_MSC_BOT_H */ -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usbd_msc_bot.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header for the usbd_msc_bot.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#include "usbd_core.h" + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_MSC_BOT_H +#define __USBD_MSC_BOT_H + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup MSC_BOT + * @brief This file is the Header file for usbd_bot.c + * @{ + */ + + +/** @defgroup USBD_CORE_Exported_Defines + * @{ + */ +#define BOT_IDLE 0 /* Idle state */ +#define BOT_DATA_OUT 1 /* Data Out state */ +#define BOT_DATA_IN 2 /* Data In state */ +#define BOT_LAST_DATA_IN 3 /* Last Data In Last */ +#define BOT_SEND_DATA 4 /* Send Immediate data */ + +#define BOT_CBW_SIGNATURE 0x43425355 +#define BOT_CSW_SIGNATURE 0x53425355 +#define BOT_CBW_LENGTH 31 +#define BOT_CSW_LENGTH 13 + +/* CSW Status Definitions */ +#define CSW_CMD_PASSED 0x00 +#define CSW_CMD_FAILED 0x01 +#define CSW_PHASE_ERROR 0x02 + +/* BOT Status */ +#define BOT_STATE_NORMAL 0 +#define BOT_STATE_RECOVERY 1 +#define BOT_STATE_ERROR 2 + + +#define DIR_IN 0 +#define DIR_OUT 1 +#define BOTH_DIR 2 + +/** + * @} + */ + +/** @defgroup MSC_CORE_Private_TypesDefinitions + * @{ + */ + +typedef struct _MSC_BOT_CBW +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataLength; + uint8_t bmFlags; + uint8_t bLUN; + uint8_t bCBLength; + uint8_t CB[16]; +} +MSC_BOT_CBW_TypeDef; + + +typedef struct _MSC_BOT_CSW +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataResidue; + uint8_t bStatus; +} +MSC_BOT_CSW_TypeDef; + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_Types + * @{ + */ + +extern uint8_t MSC_BOT_Data[]; +extern uint16_t MSC_BOT_DataLen; +extern uint8_t MSC_BOT_State; +extern uint8_t MSC_BOT_BurstMode; +extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw; +extern MSC_BOT_CSW_TypeDef MSC_BOT_csw; +/** + * @} + */ +/** @defgroup USBD_CORE_Exported_FunctionsPrototypes + * @{ + */ +void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev); +void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev); +void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev); +void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); + +void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); + +void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, + uint8_t CSW_Status); + +void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); +/** + * @} + */ + +#endif /* __USBD_MSC_BOT_H */ +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h index f6bc1b247..8b339001c 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h @@ -1,77 +1,77 @@ -/** - ****************************************************************************** - * @file usbd_msc_core.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header for the usbd_msc_core.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef _USB_MSC_CORE_H_ -#define _USB_MSC_CORE_H_ - -#include "usbd_ioreq.h" - -/** @addtogroup USBD_MSC_BOT - * @{ - */ - -/** @defgroup USBD_MSC - * @brief This file is the Header file for USBD_msc.c - * @{ - */ - - -/** @defgroup USBD_BOT_Exported_Defines - * @{ - */ - - -#define BOT_GET_MAX_LUN 0xFE -#define BOT_RESET 0xFF -#define USB_MSC_CONFIG_DESC_SIZ 32 - -#define MSC_EPIN_SIZE MSC_MAX_PACKET -#define MSC_EPOUT_SIZE MSC_MAX_PACKET - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Types - * @{ - */ - -extern const USBD_Class_cb_TypeDef USBD_MSC_cb; // modified my OpenTX -/** - * @} - */ - -/** - * @} - */ -#endif /* _USB_MSC_CORE_H_ */ -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_msc_core.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header for the usbd_msc_core.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _USB_MSC_CORE_H_ +#define _USB_MSC_CORE_H_ + +#include "usbd_ioreq.h" + +/** @addtogroup USBD_MSC_BOT + * @{ + */ + +/** @defgroup USBD_MSC + * @brief This file is the Header file for USBD_msc.c + * @{ + */ + + +/** @defgroup USBD_BOT_Exported_Defines + * @{ + */ + + +#define BOT_GET_MAX_LUN 0xFE +#define BOT_RESET 0xFF +#define USB_MSC_CONFIG_DESC_SIZ 32 + +#define MSC_EPIN_SIZE MSC_MAX_PACKET +#define MSC_EPOUT_SIZE MSC_MAX_PACKET + +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Types + * @{ + */ + +extern const USBD_Class_cb_TypeDef USBD_MSC_cb; // modified my OpenTX +/** + * @} + */ + +/** + * @} + */ +#endif /* _USB_MSC_CORE_H_ */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_data.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_data.h index 588f06edf..f004e3b89 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_data.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_data.h @@ -1,104 +1,104 @@ -/** - ****************************************************************************** - * @file usbd_msc_data.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header for the usbd_msc_data.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef _USBD_MSC_DATA_H_ -#define _USBD_MSC_DATA_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_INFO - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_INFO_Exported_Defines - * @{ - */ -#define MODE_SENSE6_LEN 8 -#define MODE_SENSE10_LEN 8 -#define LENGTH_INQUIRY_PAGE00 7 -#define LENGTH_FORMAT_CAPACITIES 20 - -/** - * @} - */ - - -/** @defgroup USBD_INFO_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_INFO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_INFO_Exported_Variables - * @{ - */ -extern const uint8_t MSC_Page00_Inquiry_Data[]; -extern const uint8_t MSC_Mode_Sense6_data[]; -extern const uint8_t MSC_Mode_Sense10_data[] ; - -/** - * @} - */ - -/** @defgroup USBD_INFO_Exported_FunctionsPrototypes - * @{ - */ - -/** - * @} - */ - -#endif /* _USBD_MSC_DATA_H_ */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_msc_data.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header for the usbd_msc_data.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef _USBD_MSC_DATA_H_ +#define _USBD_MSC_DATA_H_ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_INFO + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_INFO_Exported_Defines + * @{ + */ +#define MODE_SENSE6_LEN 8 +#define MODE_SENSE10_LEN 8 +#define LENGTH_INQUIRY_PAGE00 7 +#define LENGTH_FORMAT_CAPACITIES 20 + +/** + * @} + */ + + +/** @defgroup USBD_INFO_Exported_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_INFO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_INFO_Exported_Variables + * @{ + */ +extern const uint8_t MSC_Page00_Inquiry_Data[]; +extern const uint8_t MSC_Mode_Sense6_data[]; +extern const uint8_t MSC_Mode_Sense10_data[] ; + +/** + * @} + */ + +/** @defgroup USBD_INFO_Exported_FunctionsPrototypes + * @{ + */ + +/** + * @} + */ + +#endif /* _USBD_MSC_DATA_H_ */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_mem.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_mem.h index a31e18632..9dba3ef6e 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_mem.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_mem.h @@ -1,112 +1,112 @@ -/** - ****************************************************************************** - * @file usbd_msc_mem.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header for the STORAGE DISK file file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_MEM_H -#define __USBD_MEM_H -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_MEM - * @brief header file for the storage disk file - * @{ - */ - -/** @defgroup USBD_MEM_Exported_Defines - * @{ - */ -#define USBD_STD_INQUIRY_LENGTH 36 -/** - * @} - */ - - -/** @defgroup USBD_MEM_Exported_TypesDefinitions - * @{ - */ - -typedef struct _USBD_STORAGE -{ - int8_t (* Init) (uint8_t lun); - int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint32_t *block_size); - int8_t (* IsReady) (uint8_t lun); - int8_t (* IsWriteProtected) (uint8_t lun); - int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); - int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); - int8_t (* GetMaxLun)(void); - int8_t *pInquiry; - -}USBD_STORAGE_cb_TypeDef; -/** - * @} - */ - - - -/** @defgroup USBD_MEM_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_MEM_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_MEM_Exported_FunctionsPrototype - * @{ - */ -extern const USBD_STORAGE_cb_TypeDef * const USBD_STORAGE_fops; // modified my OpenTX -/** - * @} - */ - -#endif /* __USBD_MEM_H */ -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_msc_mem.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header for the STORAGE DISK file file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USBD_MEM_H +#define __USBD_MEM_H +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_MEM + * @brief header file for the storage disk file + * @{ + */ + +/** @defgroup USBD_MEM_Exported_Defines + * @{ + */ +#define USBD_STD_INQUIRY_LENGTH 36 +/** + * @} + */ + + +/** @defgroup USBD_MEM_Exported_TypesDefinitions + * @{ + */ + +typedef struct _USBD_STORAGE +{ + int8_t (* Init) (uint8_t lun); + int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint32_t *block_size); + int8_t (* IsReady) (uint8_t lun); + int8_t (* IsWriteProtected) (uint8_t lun); + int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); + int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); + int8_t (* GetMaxLun)(void); + int8_t *pInquiry; + +}USBD_STORAGE_cb_TypeDef; +/** + * @} + */ + + + +/** @defgroup USBD_MEM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_MEM_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_MEM_Exported_FunctionsPrototype + * @{ + */ +extern const USBD_STORAGE_cb_TypeDef * const USBD_STORAGE_fops; // modified my OpenTX +/** + * @} + */ + +#endif /* __USBD_MEM_H */ +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_scsi.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_scsi.h index a66dfe14f..d4cb2fd06 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_scsi.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_scsi.h @@ -1,195 +1,195 @@ -/** - ****************************************************************************** - * @file usbd_msc_scsi.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header for the usbd_msc_scsi.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_MSC_SCSI_H -#define __USBD_MSC_SCSI_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_SCSI - * @brief header file for the storage disk file - * @{ - */ - -/** @defgroup USBD_SCSI_Exported_Defines - * @{ - */ - -#define SENSE_LIST_DEEPTH 4 - -/* SCSI Commands */ -#define SCSI_FORMAT_UNIT 0x04 -#define SCSI_INQUIRY 0x12 -#define SCSI_MODE_SELECT6 0x15 -#define SCSI_MODE_SELECT10 0x55 -#define SCSI_MODE_SENSE6 0x1A -#define SCSI_MODE_SENSE10 0x5A -#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E -#define SCSI_READ6 0x08 -#define SCSI_READ10 0x28 -#define SCSI_READ12 0xA8 -#define SCSI_READ16 0x88 - -#define SCSI_READ_CAPACITY10 0x25 -#define SCSI_READ_CAPACITY16 0x9E - -#define SCSI_REQUEST_SENSE 0x03 -#define SCSI_START_STOP_UNIT 0x1B -#define SCSI_TEST_UNIT_READY 0x00 -#define SCSI_WRITE6 0x0A -#define SCSI_WRITE10 0x2A -#define SCSI_WRITE12 0xAA -#define SCSI_WRITE16 0x8A - -#define SCSI_VERIFY10 0x2F -#define SCSI_VERIFY12 0xAF -#define SCSI_VERIFY16 0x8F - -#define SCSI_SEND_DIAGNOSTIC 0x1D -#define SCSI_READ_FORMAT_CAPACITIES 0x23 - -#define NO_SENSE 0 -#define RECOVERED_ERROR 1 -#define NOT_READY 2 -#define MEDIUM_ERROR 3 -#define HARDWARE_ERROR 4 -#define ILLEGAL_REQUEST 5 -#define UNIT_ATTENTION 6 -#define DATA_PROTECT 7 -#define BLANK_CHECK 8 -#define VENDOR_SPECIFIC 9 -#define COPY_ABORTED 10 -#define ABORTED_COMMAND 11 -#define VOLUME_OVERFLOW 13 -#define MISCOMPARE 14 - - -#define INVALID_CDB 0x20 -#define INVALID_FIELED_IN_COMMAND 0x24 -#define PARAMETER_LIST_LENGTH_ERROR 0x1A -#define INVALID_FIELD_IN_PARAMETER_LIST 0x26 -#define ADDRESS_OUT_OF_RANGE 0x21 -#define MEDIUM_NOT_PRESENT 0x3A -#define MEDIUM_HAVE_CHANGED 0x28 -#define WRITE_PROTECTED 0x27 -#define UNRECOVERED_READ_ERROR 0x11 -#define WRITE_FAULT 0x03 - -#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C -#define READ_CAPACITY10_DATA_LEN 0x08 -#define MODE_SENSE10_DATA_LEN 0x08 -#define MODE_SENSE6_DATA_LEN 0x04 -#define REQUEST_SENSE_DATA_LEN 0x12 -#define STANDARD_INQUIRY_DATA_LEN 0x24 -#define BLKVFY 0x04 - -extern uint8_t Page00_Inquiry_Data[]; -extern uint8_t Standard_Inquiry_Data[]; -extern uint8_t Standard_Inquiry_Data2[]; -extern uint8_t Mode_Sense6_data[]; -extern uint8_t Mode_Sense10_data[]; -extern uint8_t Scsi_Sense_Data[]; -extern uint8_t ReadCapacity10_Data[]; -extern uint8_t ReadFormatCapacity_Data []; -/** - * @} - */ - - -/** @defgroup USBD_SCSI_Exported_TypesDefinitions - * @{ - */ - -typedef struct _SENSE_ITEM { - char Skey; - union { - struct _ASCs { - char ASC; - char ASCQ; - }b; - unsigned int ASC; - char *pData; - } w; -} SCSI_Sense_TypeDef; -/** - * @} - */ - -/** @defgroup USBD_SCSI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_SCSI_Exported_Variables - * @{ - */ -extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; -extern uint8_t SCSI_Sense_Head; -extern uint8_t SCSI_Sense_Tail; - -/** - * @} - */ -/** @defgroup USBD_SCSI_Exported_FunctionsPrototype - * @{ - */ -int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, - uint8_t lun, - uint8_t *cmd); - -void SCSI_SenseCode(uint8_t lun, - uint8_t sKey, - uint8_t ASC); - -/** - * @} - */ - -#endif /* __USBD_MSC_SCSI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usbd_msc_scsi.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header for the usbd_msc_scsi.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_MSC_SCSI_H +#define __USBD_MSC_SCSI_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_SCSI + * @brief header file for the storage disk file + * @{ + */ + +/** @defgroup USBD_SCSI_Exported_Defines + * @{ + */ + +#define SENSE_LIST_DEEPTH 4 + +/* SCSI Commands */ +#define SCSI_FORMAT_UNIT 0x04 +#define SCSI_INQUIRY 0x12 +#define SCSI_MODE_SELECT6 0x15 +#define SCSI_MODE_SELECT10 0x55 +#define SCSI_MODE_SENSE6 0x1A +#define SCSI_MODE_SENSE10 0x5A +#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E +#define SCSI_READ6 0x08 +#define SCSI_READ10 0x28 +#define SCSI_READ12 0xA8 +#define SCSI_READ16 0x88 + +#define SCSI_READ_CAPACITY10 0x25 +#define SCSI_READ_CAPACITY16 0x9E + +#define SCSI_REQUEST_SENSE 0x03 +#define SCSI_START_STOP_UNIT 0x1B +#define SCSI_TEST_UNIT_READY 0x00 +#define SCSI_WRITE6 0x0A +#define SCSI_WRITE10 0x2A +#define SCSI_WRITE12 0xAA +#define SCSI_WRITE16 0x8A + +#define SCSI_VERIFY10 0x2F +#define SCSI_VERIFY12 0xAF +#define SCSI_VERIFY16 0x8F + +#define SCSI_SEND_DIAGNOSTIC 0x1D +#define SCSI_READ_FORMAT_CAPACITIES 0x23 + +#define NO_SENSE 0 +#define RECOVERED_ERROR 1 +#define NOT_READY 2 +#define MEDIUM_ERROR 3 +#define HARDWARE_ERROR 4 +#define ILLEGAL_REQUEST 5 +#define UNIT_ATTENTION 6 +#define DATA_PROTECT 7 +#define BLANK_CHECK 8 +#define VENDOR_SPECIFIC 9 +#define COPY_ABORTED 10 +#define ABORTED_COMMAND 11 +#define VOLUME_OVERFLOW 13 +#define MISCOMPARE 14 + + +#define INVALID_CDB 0x20 +#define INVALID_FIELED_IN_COMMAND 0x24 +#define PARAMETER_LIST_LENGTH_ERROR 0x1A +#define INVALID_FIELD_IN_PARAMETER_LIST 0x26 +#define ADDRESS_OUT_OF_RANGE 0x21 +#define MEDIUM_NOT_PRESENT 0x3A +#define MEDIUM_HAVE_CHANGED 0x28 +#define WRITE_PROTECTED 0x27 +#define UNRECOVERED_READ_ERROR 0x11 +#define WRITE_FAULT 0x03 + +#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C +#define READ_CAPACITY10_DATA_LEN 0x08 +#define MODE_SENSE10_DATA_LEN 0x08 +#define MODE_SENSE6_DATA_LEN 0x04 +#define REQUEST_SENSE_DATA_LEN 0x12 +#define STANDARD_INQUIRY_DATA_LEN 0x24 +#define BLKVFY 0x04 + +extern uint8_t Page00_Inquiry_Data[]; +extern uint8_t Standard_Inquiry_Data[]; +extern uint8_t Standard_Inquiry_Data2[]; +extern uint8_t Mode_Sense6_data[]; +extern uint8_t Mode_Sense10_data[]; +extern uint8_t Scsi_Sense_Data[]; +extern uint8_t ReadCapacity10_Data[]; +extern uint8_t ReadFormatCapacity_Data []; +/** + * @} + */ + + +/** @defgroup USBD_SCSI_Exported_TypesDefinitions + * @{ + */ + +typedef struct _SENSE_ITEM { + char Skey; + union { + struct _ASCs { + char ASC; + char ASCQ; + }b; + unsigned int ASC; + char *pData; + } w; +} SCSI_Sense_TypeDef; +/** + * @} + */ + +/** @defgroup USBD_SCSI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_SCSI_Exported_Variables + * @{ + */ +extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; +extern uint8_t SCSI_Sense_Head; +extern uint8_t SCSI_Sense_Tail; + +/** + * @} + */ +/** @defgroup USBD_SCSI_Exported_FunctionsPrototype + * @{ + */ +int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, + uint8_t lun, + uint8_t *cmd); + +void SCSI_SenseCode(uint8_t lun, + uint8_t sKey, + uint8_t ASC); + +/** + * @} + */ + +#endif /* __USBD_MSC_SCSI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c index c994a5cb6..5aff1a9c4 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c @@ -1,402 +1,402 @@ -/** - ****************************************************************************** - * @file usbd_msc_bot.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides all the BOT protocol core functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_bot.h" -#include "usbd_msc_scsi.h" -#include "usbd_ioreq.h" -#include "usbd_msc_mem.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_BOT - * @brief BOT protocol module - * @{ - */ - -/** @defgroup MSC_BOT_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Variables - * @{ - */ -uint16_t MSC_BOT_DataLen; -uint8_t MSC_BOT_State; -uint8_t MSC_BOT_Status; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -#include "definitions.h" -uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET] __DMA; // modified by OpenTX - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw __ALIGN_END ; -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_FunctionPrototypes - * @{ - */ -static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev); - -static void MSC_BOT_SendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t* pbuf, - uint16_t len); - -static void MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev); -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Functions - * @{ - */ - - - -/** -* @brief MSC_BOT_Init -* Initialize the BOT Process -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; - MSC_BOT_Status = BOT_STATE_NORMAL; - USBD_STORAGE_fops->Init(0); - - DCD_EP_Flush(pdev, MSC_OUT_EP); - DCD_EP_Flush(pdev, MSC_IN_EP); - /* Prapare EP to Receive First BOT Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); -} - -/** -* @brief MSC_BOT_Reset -* Reset the BOT Machine -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; - MSC_BOT_Status = BOT_STATE_RECOVERY; - /* Prapare EP to Receive First BOT Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); -} - -/** -* @brief MSC_BOT_DeInit -* Uninitialize the BOT Machine -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; -} - -/** -* @brief MSC_BOT_DataIn -* Handle BOT IN data stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ -void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum) -{ - - switch (MSC_BOT_State) - { - case BOT_DATA_IN: - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - break; - - case BOT_SEND_DATA: - case BOT_LAST_DATA_IN: - MSC_BOT_SendCSW (pdev, CSW_CMD_PASSED); - - break; - - default: - break; - } -} -/** -* @brief MSC_BOT_DataOut -* Proccess MSC OUT data -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ -void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum) -{ - switch (MSC_BOT_State) - { - case BOT_IDLE: - MSC_BOT_CBW_Decode(pdev); - break; - - case BOT_DATA_OUT: - - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - - break; - - default: - break; - } - -} - -/** -* @brief MSC_BOT_CBW_Decode -* Decode the CBW command and set the BOT state machine accordingtly -* @param pdev: device instance -* @retval None -*/ -static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev) -{ - - MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag; - MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength; - - if ((USBD_GetRxCount (pdev ,MSC_OUT_EP) != BOT_CBW_LENGTH) || - (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE)|| - (MSC_BOT_cbw.bLUN > 1) || - (MSC_BOT_cbw.bCBLength < 1) || - (MSC_BOT_cbw.bCBLength > 16)) - { - - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - MSC_BOT_Status = BOT_STATE_ERROR; - MSC_BOT_Abort(pdev); - - } - else - { - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_Abort(pdev); - } - /*Burst xfer handled internally*/ - else if ((MSC_BOT_State != BOT_DATA_IN) && - (MSC_BOT_State != BOT_DATA_OUT) && - (MSC_BOT_State != BOT_LAST_DATA_IN)) - { - if (MSC_BOT_DataLen > 0) - { - MSC_BOT_SendData(pdev, - MSC_BOT_Data, - MSC_BOT_DataLen); - } - else if (MSC_BOT_DataLen == 0) - { - MSC_BOT_SendCSW (pdev, - CSW_CMD_PASSED); - } - } - } -} - -/** -* @brief MSC_BOT_SendData -* Send the requested data -* @param pdev: device instance -* @param buf: pointer to data buffer -* @param len: Data Length -* @retval None -*/ -static void MSC_BOT_SendData(USB_OTG_CORE_HANDLE *pdev, - uint8_t* buf, - uint16_t len) -{ - - len = MIN (MSC_BOT_cbw.dDataLength, len); - MSC_BOT_csw.dDataResidue -= len; - MSC_BOT_csw.bStatus = CSW_CMD_PASSED; - MSC_BOT_State = BOT_SEND_DATA; - - DCD_EP_Tx (pdev, MSC_IN_EP, buf, len); -} - -/** -* @brief MSC_BOT_SendCSW -* Send the Command Status Wrapper -* @param pdev: device instance -* @param status : CSW status -* @retval None -*/ -void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, - uint8_t CSW_Status) -{ - MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE; - MSC_BOT_csw.bStatus = CSW_Status; - MSC_BOT_State = BOT_IDLE; - - DCD_EP_Tx (pdev, - MSC_IN_EP, - (uint8_t *)&MSC_BOT_csw, - BOT_CSW_LENGTH); - - /* Prepare EP to Receive next Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); - -} - -/** -* @brief MSC_BOT_Abort -* Abort the current transfer -* @param pdev: device instance -* @retval status -*/ - -static void MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev) -{ - - if ((MSC_BOT_cbw.bmFlags == 0) && - (MSC_BOT_cbw.dDataLength != 0) && - (MSC_BOT_Status == BOT_STATE_NORMAL) ) - { - DCD_EP_Stall(pdev, MSC_OUT_EP ); - } - DCD_EP_Stall(pdev, MSC_IN_EP); - - if(MSC_BOT_Status == BOT_STATE_ERROR) - { - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); - } -} - -/** -* @brief MSC_BOT_CplClrFeature -* Complete the clear feature request -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ - -void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - if(MSC_BOT_Status == BOT_STATE_ERROR )/* Bad CBW Signature */ - { - DCD_EP_Stall(pdev, MSC_IN_EP); - MSC_BOT_Status = BOT_STATE_NORMAL; - } - else if(((epnum & 0x80) == 0x80) && ( MSC_BOT_Status != BOT_STATE_RECOVERY)) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_msc_bot.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides all the BOT protocol core functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_msc_bot.h" +#include "usbd_msc_scsi.h" +#include "usbd_ioreq.h" +#include "usbd_msc_mem.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup MSC_BOT + * @brief BOT protocol module + * @{ + */ + +/** @defgroup MSC_BOT_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_BOT_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup MSC_BOT_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_BOT_Private_Variables + * @{ + */ +uint16_t MSC_BOT_DataLen; +uint8_t MSC_BOT_State; +uint8_t MSC_BOT_Status; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +#include "definitions.h" +uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET] __DMA; // modified by OpenTX + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw __ALIGN_END ; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw __ALIGN_END ; +/** + * @} + */ + + +/** @defgroup MSC_BOT_Private_FunctionPrototypes + * @{ + */ +static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev); + +static void MSC_BOT_SendData (USB_OTG_CORE_HANDLE *pdev, + uint8_t* pbuf, + uint16_t len); + +static void MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev); +/** + * @} + */ + + +/** @defgroup MSC_BOT_Private_Functions + * @{ + */ + + + +/** +* @brief MSC_BOT_Init +* Initialize the BOT Process +* @param pdev: device instance +* @retval None +*/ +void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev) +{ + MSC_BOT_State = BOT_IDLE; + MSC_BOT_Status = BOT_STATE_NORMAL; + USBD_STORAGE_fops->Init(0); + + DCD_EP_Flush(pdev, MSC_OUT_EP); + DCD_EP_Flush(pdev, MSC_IN_EP); + /* Prapare EP to Receive First BOT Cmd */ + DCD_EP_PrepareRx (pdev, + MSC_OUT_EP, + (uint8_t *)&MSC_BOT_cbw, + BOT_CBW_LENGTH); +} + +/** +* @brief MSC_BOT_Reset +* Reset the BOT Machine +* @param pdev: device instance +* @retval None +*/ +void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev) +{ + MSC_BOT_State = BOT_IDLE; + MSC_BOT_Status = BOT_STATE_RECOVERY; + /* Prapare EP to Receive First BOT Cmd */ + DCD_EP_PrepareRx (pdev, + MSC_OUT_EP, + (uint8_t *)&MSC_BOT_cbw, + BOT_CBW_LENGTH); +} + +/** +* @brief MSC_BOT_DeInit +* Uninitialize the BOT Machine +* @param pdev: device instance +* @retval None +*/ +void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev) +{ + MSC_BOT_State = BOT_IDLE; +} + +/** +* @brief MSC_BOT_DataIn +* Handle BOT IN data stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval None +*/ +void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum) +{ + + switch (MSC_BOT_State) + { + case BOT_DATA_IN: + if(SCSI_ProcessCmd(pdev, + MSC_BOT_cbw.bLUN, + &MSC_BOT_cbw.CB[0]) < 0) + { + MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); + } + break; + + case BOT_SEND_DATA: + case BOT_LAST_DATA_IN: + MSC_BOT_SendCSW (pdev, CSW_CMD_PASSED); + + break; + + default: + break; + } +} +/** +* @brief MSC_BOT_DataOut +* Proccess MSC OUT data +* @param pdev: device instance +* @param epnum: endpoint index +* @retval None +*/ +void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum) +{ + switch (MSC_BOT_State) + { + case BOT_IDLE: + MSC_BOT_CBW_Decode(pdev); + break; + + case BOT_DATA_OUT: + + if(SCSI_ProcessCmd(pdev, + MSC_BOT_cbw.bLUN, + &MSC_BOT_cbw.CB[0]) < 0) + { + MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); + } + + break; + + default: + break; + } + +} + +/** +* @brief MSC_BOT_CBW_Decode +* Decode the CBW command and set the BOT state machine accordingtly +* @param pdev: device instance +* @retval None +*/ +static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev) +{ + + MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag; + MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength; + + if ((USBD_GetRxCount (pdev ,MSC_OUT_EP) != BOT_CBW_LENGTH) || + (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE)|| + (MSC_BOT_cbw.bLUN > 1) || + (MSC_BOT_cbw.bCBLength < 1) || + (MSC_BOT_cbw.bCBLength > 16)) + { + + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + MSC_BOT_Status = BOT_STATE_ERROR; + MSC_BOT_Abort(pdev); + + } + else + { + if(SCSI_ProcessCmd(pdev, + MSC_BOT_cbw.bLUN, + &MSC_BOT_cbw.CB[0]) < 0) + { + MSC_BOT_Abort(pdev); + } + /*Burst xfer handled internally*/ + else if ((MSC_BOT_State != BOT_DATA_IN) && + (MSC_BOT_State != BOT_DATA_OUT) && + (MSC_BOT_State != BOT_LAST_DATA_IN)) + { + if (MSC_BOT_DataLen > 0) + { + MSC_BOT_SendData(pdev, + MSC_BOT_Data, + MSC_BOT_DataLen); + } + else if (MSC_BOT_DataLen == 0) + { + MSC_BOT_SendCSW (pdev, + CSW_CMD_PASSED); + } + } + } +} + +/** +* @brief MSC_BOT_SendData +* Send the requested data +* @param pdev: device instance +* @param buf: pointer to data buffer +* @param len: Data Length +* @retval None +*/ +static void MSC_BOT_SendData(USB_OTG_CORE_HANDLE *pdev, + uint8_t* buf, + uint16_t len) +{ + + len = MIN (MSC_BOT_cbw.dDataLength, len); + MSC_BOT_csw.dDataResidue -= len; + MSC_BOT_csw.bStatus = CSW_CMD_PASSED; + MSC_BOT_State = BOT_SEND_DATA; + + DCD_EP_Tx (pdev, MSC_IN_EP, buf, len); +} + +/** +* @brief MSC_BOT_SendCSW +* Send the Command Status Wrapper +* @param pdev: device instance +* @param status : CSW status +* @retval None +*/ +void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, + uint8_t CSW_Status) +{ + MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE; + MSC_BOT_csw.bStatus = CSW_Status; + MSC_BOT_State = BOT_IDLE; + + DCD_EP_Tx (pdev, + MSC_IN_EP, + (uint8_t *)&MSC_BOT_csw, + BOT_CSW_LENGTH); + + /* Prepare EP to Receive next Cmd */ + DCD_EP_PrepareRx (pdev, + MSC_OUT_EP, + (uint8_t *)&MSC_BOT_cbw, + BOT_CBW_LENGTH); + +} + +/** +* @brief MSC_BOT_Abort +* Abort the current transfer +* @param pdev: device instance +* @retval status +*/ + +static void MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev) +{ + + if ((MSC_BOT_cbw.bmFlags == 0) && + (MSC_BOT_cbw.dDataLength != 0) && + (MSC_BOT_Status == BOT_STATE_NORMAL) ) + { + DCD_EP_Stall(pdev, MSC_OUT_EP ); + } + DCD_EP_Stall(pdev, MSC_IN_EP); + + if(MSC_BOT_Status == BOT_STATE_ERROR) + { + DCD_EP_PrepareRx (pdev, + MSC_OUT_EP, + (uint8_t *)&MSC_BOT_cbw, + BOT_CBW_LENGTH); + } +} + +/** +* @brief MSC_BOT_CplClrFeature +* Complete the clear feature request +* @param pdev: device instance +* @param epnum: endpoint index +* @retval None +*/ + +void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) +{ + if(MSC_BOT_Status == BOT_STATE_ERROR )/* Bad CBW Signature */ + { + DCD_EP_Stall(pdev, MSC_IN_EP); + MSC_BOT_Status = BOT_STATE_NORMAL; + } + else if(((epnum & 0x80) == 0x80) && ( MSC_BOT_Status != BOT_STATE_RECOVERY)) + { + MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); + } + +} +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c index f642b19be..e5c307ad0 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c @@ -1,497 +1,497 @@ -/** - ****************************************************************************** - * @file usbd_msc_core.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides all the MSC core functions. - * - * @verbatim - * - * =================================================================== - * MSC Class Description - * =================================================================== - * This module manages the MSC class V1.0 following the "Universal - * Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0 - * Sep. 31, 1999". - * This driver implements the following aspects of the specification: - * - Bulk-Only Transport protocol - * - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3)) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_mem.h" -#include "usbd_msc_core.h" -#include "usbd_msc_bot.h" -#include "usbd_req.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_CORE - * @brief Mass storage core module - * @{ - */ - -/** @defgroup MSC_CORE_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_FunctionPrototypes - * @{ - */ -uint8_t USBD_MSC_Init (void *pdev, - uint8_t cfgidx); - -uint8_t USBD_MSC_DeInit (void *pdev, - uint8_t cfgidx); - -uint8_t USBD_MSC_Setup (void *pdev, - USB_SETUP_REQ *req); - -uint8_t USBD_MSC_DataIn (void *pdev, - uint8_t epnum); - - -uint8_t USBD_MSC_DataOut (void *pdev, - uint8_t epnum); - -const uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, - uint16_t *length); // modified by OpenTX - -#ifdef USB_OTG_HS_CORE -uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, - uint16_t *length); -#endif - - -// uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ]; // modified by OpenTX - - - - -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Variables - * @{ - */ - - -const USBD_Class_cb_TypeDef USBD_MSC_cb = // modified by OpenTX -{ - USBD_MSC_Init, - USBD_MSC_DeInit, - USBD_MSC_Setup, - NULL, /*EP0_TxSent*/ - NULL, /*EP0_RxReady*/ - USBD_MSC_DataIn, - USBD_MSC_DataOut, - NULL, /*SOF */ - NULL, - NULL, - USBD_MSC_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_MSC_GetOtherCfgDesc, -#endif -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB Mass storage device Configuration Descriptor */ -/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ -__ALIGN_BEGIN const uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = // modified by OpenTX -{ - - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_MSC_CONFIG_DESC_SIZ, - - 0x00, - 0x01, /* bNumInterfaces: 1 interface */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /******************** Mass Storage interface ********************/ - 0x09, /* bLength: Interface Descriptor size */ - 0x04, /* bDescriptorType: */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints*/ - 0x08, /* bInterfaceClass: MSC Class */ - 0x06, /* bInterfaceSubClass : SCSI transparent*/ - 0x50, /* nInterfaceProtocol */ - 0x05, /* iInterface: */ - /******************** Mass Storage Endpoints ********************/ - 0x07, /*Endpoint descriptor length = 7*/ - 0x05, /*Endpoint descriptor type */ - MSC_IN_EP, /*Endpoint address (IN, address 1) */ - 0x02, /*Bulk endpoint type */ - LOBYTE(MSC_MAX_PACKET), - HIBYTE(MSC_MAX_PACKET), - 0x00, /*Polling interval in milliseconds */ - - 0x07, /*Endpoint descriptor length = 7 */ - 0x05, /*Endpoint descriptor type */ - MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ - 0x02, /*Bulk endpoint type */ - LOBYTE(MSC_MAX_PACKET), - HIBYTE(MSC_MAX_PACKET), - 0x00 /*Polling interval in milliseconds*/ -}; -#ifdef USB_OTG_HS_CORE - #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif - #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t USBD_MSC_OtherCfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, - USB_MSC_CONFIG_DESC_SIZ, - - 0x00, - 0x01, /* bNumInterfaces: 1 interface */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /******************** Mass Storage interface ********************/ - 0x09, /* bLength: Interface Descriptor size */ - 0x04, /* bDescriptorType: */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints*/ - 0x08, /* bInterfaceClass: MSC Class */ - 0x06, /* bInterfaceSubClass : SCSI transparent command set*/ - 0x50, /* nInterfaceProtocol */ - 0x05, /* iInterface: */ - /******************** Mass Storage Endpoints ********************/ - 0x07, /*Endpoint descriptor length = 7*/ - 0x05, /*Endpoint descriptor type */ - MSC_IN_EP, /*Endpoint address (IN, address 1) */ - 0x02, /*Bulk endpoint type */ - 0x40, - 0x00, - 0x00, /*Polling interval in milliseconds */ - - 0x07, /*Endpoint descriptor length = 7 */ - 0x05, /*Endpoint descriptor type */ - MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ - 0x02, /*Bulk endpoint type */ - 0x40, - 0x00, - 0x00 /*Polling interval in milliseconds*/ -}; -#endif - -// modified my OpenTX -// #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED -// #if defined ( __ICCARM__ ) /*!< IAR Compiler */ -// #pragma data_alignment=4 -// #endif -// #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -// __ALIGN_BEGIN static uint8_t USBD_MSC_MaxLun __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint8_t USBD_MSC_AltSet __ALIGN_END = 0; - -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Functions - * @{ - */ - -/** -* @brief USBD_MSC_Init -* Initialize the mass storage configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ -uint8_t USBD_MSC_Init (void *pdev, - uint8_t cfgidx) -{ - USBD_MSC_DeInit(pdev , cfgidx ); - - /* Open EP IN */ - DCD_EP_Open(pdev, - MSC_IN_EP, - MSC_EPIN_SIZE, - USB_OTG_EP_BULK); - - /* Open EP OUT */ - DCD_EP_Open(pdev, - MSC_OUT_EP, - MSC_EPOUT_SIZE, - USB_OTG_EP_BULK); - - /* Init the BOT layer */ - MSC_BOT_Init(pdev); - - return USBD_OK; -} - -/** -* @brief USBD_MSC_DeInit -* DeInitilaize the mass storage configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ -uint8_t USBD_MSC_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* Close MSC EPs */ - DCD_EP_Close (pdev , MSC_IN_EP); - DCD_EP_Close (pdev , MSC_OUT_EP); - - /* Un Init the BOT layer */ - MSC_BOT_DeInit(pdev); - return USBD_OK; -} -/** -* @brief USBD_MSC_Setup -* Handle the MSC specific requests -* @param pdev: device instance -* @param req: USB request -* @retval status -*/ -uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req) -{ - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - - /* Class request */ - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - case BOT_GET_MAX_LUN : - - if((req->wValue == 0) && - (req->wLength == 1) && - ((req->bmRequest & 0x80) == 0x80)) - { - __ALIGN_BEGIN uint8_t USBD_MSC_MaxLun __ALIGN_END; // modified by OpenTX - USBD_MSC_MaxLun = USBD_STORAGE_fops->GetMaxLun(); - if(USBD_MSC_MaxLun > 0) - { - USBD_CtlSendData (pdev, - &USBD_MSC_MaxLun, - 1); - } - else - { - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - } - else - { - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - break; - - case BOT_RESET : - if((req->wValue == 0) && - (req->wLength == 0) && - ((req->bmRequest & 0x80) != 0x80)) - { - MSC_BOT_Reset(pdev); - } - else - { - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - break; - - default: - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - break; - /* Interface & Endpoint request */ - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - &USBD_MSC_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - USBD_MSC_AltSet = (uint8_t)(req->wValue); - break; - - case USB_REQ_CLEAR_FEATURE: - - /* Flush the FIFO and Clear the stall status */ - DCD_EP_Flush(pdev, (uint8_t)req->wIndex); - - /* Re-activate the EP */ - DCD_EP_Close (pdev , (uint8_t)req->wIndex); - if((((uint8_t)req->wIndex) & 0x80) == 0x80) - { - DCD_EP_Open(pdev, - ((uint8_t)req->wIndex), - MSC_EPIN_SIZE, - USB_OTG_EP_BULK); - } - else - { - DCD_EP_Open(pdev, - ((uint8_t)req->wIndex), - MSC_EPOUT_SIZE, - USB_OTG_EP_BULK); - } - - /* Handle BOT error */ - MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex); - break; - - } - break; - - default: - break; - } - return USBD_OK; -} - -/** -* @brief USBD_MSC_DataIn -* handle data IN Stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -uint8_t USBD_MSC_DataIn (void *pdev, - uint8_t epnum) -{ - MSC_BOT_DataIn(pdev , epnum); - return USBD_OK; -} - -/** -* @brief USBD_MSC_DataOut -* handle data OUT Stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -uint8_t USBD_MSC_DataOut (void *pdev, - uint8_t epnum) -{ - MSC_BOT_DataOut(pdev , epnum); - return USBD_OK; -} - -/** -* @brief USBD_MSC_GetCfgDesc -* return configuration descriptor -* @param speed : current device speed -* @param length : pointer data length -* @retval pointer to descriptor buffer -*/ -const uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length) // modified by OpenTX -{ - *length = sizeof (USBD_MSC_CfgDesc); - return USBD_MSC_CfgDesc; -} - -/** -* @brief USBD_MSC_GetOtherCfgDesc -* return other speed configuration descriptor -* @param speed : current device speed -* @param length : pointer data length -* @retval pointer to descriptor buffer -*/ -#ifdef USB_OTG_HS_CORE -uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, - uint16_t *length) -{ - *length = sizeof (USBD_MSC_OtherCfgDesc); - return USBD_MSC_OtherCfgDesc; -} -#endif -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_msc_core.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides all the MSC core functions. + * + * @verbatim + * + * =================================================================== + * MSC Class Description + * =================================================================== + * This module manages the MSC class V1.0 following the "Universal + * Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0 + * Sep. 31, 1999". + * This driver implements the following aspects of the specification: + * - Bulk-Only Transport protocol + * - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3)) + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_msc_mem.h" +#include "usbd_msc_core.h" +#include "usbd_msc_bot.h" +#include "usbd_req.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup MSC_CORE + * @brief Mass storage core module + * @{ + */ + +/** @defgroup MSC_CORE_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_CORE_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup MSC_CORE_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_CORE_Private_FunctionPrototypes + * @{ + */ +uint8_t USBD_MSC_Init (void *pdev, + uint8_t cfgidx); + +uint8_t USBD_MSC_DeInit (void *pdev, + uint8_t cfgidx); + +uint8_t USBD_MSC_Setup (void *pdev, + USB_SETUP_REQ *req); + +uint8_t USBD_MSC_DataIn (void *pdev, + uint8_t epnum); + + +uint8_t USBD_MSC_DataOut (void *pdev, + uint8_t epnum); + +const uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, + uint16_t *length); // modified by OpenTX + +#ifdef USB_OTG_HS_CORE +uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, + uint16_t *length); +#endif + + +// uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ]; // modified by OpenTX + + + + +/** + * @} + */ + + +/** @defgroup MSC_CORE_Private_Variables + * @{ + */ + + +const USBD_Class_cb_TypeDef USBD_MSC_cb = // modified by OpenTX +{ + USBD_MSC_Init, + USBD_MSC_DeInit, + USBD_MSC_Setup, + NULL, /*EP0_TxSent*/ + NULL, /*EP0_RxReady*/ + USBD_MSC_DataIn, + USBD_MSC_DataOut, + NULL, /*SOF */ + NULL, + NULL, + USBD_MSC_GetCfgDesc, +#ifdef USB_OTG_HS_CORE + USBD_MSC_GetOtherCfgDesc, +#endif +}; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +/* USB Mass storage device Configuration Descriptor */ +/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ +__ALIGN_BEGIN const uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = // modified by OpenTX +{ + + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_MSC_CONFIG_DESC_SIZ, + + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /******************** Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints ********************/ + 0x07, /*Endpoint descriptor length = 7*/ + 0x05, /*Endpoint descriptor type */ + MSC_IN_EP, /*Endpoint address (IN, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /*Polling interval in milliseconds */ + + 0x07, /*Endpoint descriptor length = 7 */ + 0x05, /*Endpoint descriptor type */ + MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00 /*Polling interval in milliseconds*/ +}; +#ifdef USB_OTG_HS_CORE + #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif + #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBD_MSC_OtherCfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_MSC_CONFIG_DESC_SIZ, + + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /******************** Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent command set*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints ********************/ + 0x07, /*Endpoint descriptor length = 7*/ + 0x05, /*Endpoint descriptor type */ + MSC_IN_EP, /*Endpoint address (IN, address 1) */ + 0x02, /*Bulk endpoint type */ + 0x40, + 0x00, + 0x00, /*Polling interval in milliseconds */ + + 0x07, /*Endpoint descriptor length = 7 */ + 0x05, /*Endpoint descriptor type */ + MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ + 0x02, /*Bulk endpoint type */ + 0x40, + 0x00, + 0x00 /*Polling interval in milliseconds*/ +}; +#endif + +// modified my OpenTX +// #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED +// #if defined ( __ICCARM__ ) /*!< IAR Compiler */ +// #pragma data_alignment=4 +// #endif +// #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +// __ALIGN_BEGIN static uint8_t USBD_MSC_MaxLun __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint8_t USBD_MSC_AltSet __ALIGN_END = 0; + +/** + * @} + */ + + +/** @defgroup MSC_CORE_Private_Functions + * @{ + */ + +/** +* @brief USBD_MSC_Init +* Initialize the mass storage configuration +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status +*/ +uint8_t USBD_MSC_Init (void *pdev, + uint8_t cfgidx) +{ + USBD_MSC_DeInit(pdev , cfgidx ); + + /* Open EP IN */ + DCD_EP_Open(pdev, + MSC_IN_EP, + MSC_EPIN_SIZE, + USB_OTG_EP_BULK); + + /* Open EP OUT */ + DCD_EP_Open(pdev, + MSC_OUT_EP, + MSC_EPOUT_SIZE, + USB_OTG_EP_BULK); + + /* Init the BOT layer */ + MSC_BOT_Init(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_MSC_DeInit +* DeInitilaize the mass storage configuration +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status +*/ +uint8_t USBD_MSC_DeInit (void *pdev, + uint8_t cfgidx) +{ + /* Close MSC EPs */ + DCD_EP_Close (pdev , MSC_IN_EP); + DCD_EP_Close (pdev , MSC_OUT_EP); + + /* Un Init the BOT layer */ + MSC_BOT_DeInit(pdev); + return USBD_OK; +} +/** +* @brief USBD_MSC_Setup +* Handle the MSC specific requests +* @param pdev: device instance +* @param req: USB request +* @retval status +*/ +uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req) +{ + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + + /* Class request */ + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case BOT_GET_MAX_LUN : + + if((req->wValue == 0) && + (req->wLength == 1) && + ((req->bmRequest & 0x80) == 0x80)) + { + __ALIGN_BEGIN uint8_t USBD_MSC_MaxLun __ALIGN_END; // modified by OpenTX + USBD_MSC_MaxLun = USBD_STORAGE_fops->GetMaxLun(); + if(USBD_MSC_MaxLun > 0) + { + USBD_CtlSendData (pdev, + &USBD_MSC_MaxLun, + 1); + } + else + { + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + } + else + { + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + break; + + case BOT_RESET : + if((req->wValue == 0) && + (req->wLength == 0) && + ((req->bmRequest & 0x80) != 0x80)) + { + MSC_BOT_Reset(pdev); + } + else + { + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + break; + + default: + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + break; + /* Interface & Endpoint request */ + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_INTERFACE : + USBD_CtlSendData (pdev, + &USBD_MSC_AltSet, + 1); + break; + + case USB_REQ_SET_INTERFACE : + USBD_MSC_AltSet = (uint8_t)(req->wValue); + break; + + case USB_REQ_CLEAR_FEATURE: + + /* Flush the FIFO and Clear the stall status */ + DCD_EP_Flush(pdev, (uint8_t)req->wIndex); + + /* Re-activate the EP */ + DCD_EP_Close (pdev , (uint8_t)req->wIndex); + if((((uint8_t)req->wIndex) & 0x80) == 0x80) + { + DCD_EP_Open(pdev, + ((uint8_t)req->wIndex), + MSC_EPIN_SIZE, + USB_OTG_EP_BULK); + } + else + { + DCD_EP_Open(pdev, + ((uint8_t)req->wIndex), + MSC_EPOUT_SIZE, + USB_OTG_EP_BULK); + } + + /* Handle BOT error */ + MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex); + break; + + } + break; + + default: + break; + } + return USBD_OK; +} + +/** +* @brief USBD_MSC_DataIn +* handle data IN Stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +uint8_t USBD_MSC_DataIn (void *pdev, + uint8_t epnum) +{ + MSC_BOT_DataIn(pdev , epnum); + return USBD_OK; +} + +/** +* @brief USBD_MSC_DataOut +* handle data OUT Stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +uint8_t USBD_MSC_DataOut (void *pdev, + uint8_t epnum) +{ + MSC_BOT_DataOut(pdev , epnum); + return USBD_OK; +} + +/** +* @brief USBD_MSC_GetCfgDesc +* return configuration descriptor +* @param speed : current device speed +* @param length : pointer data length +* @retval pointer to descriptor buffer +*/ +const uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length) // modified by OpenTX +{ + *length = sizeof (USBD_MSC_CfgDesc); + return USBD_MSC_CfgDesc; +} + +/** +* @brief USBD_MSC_GetOtherCfgDesc +* return other speed configuration descriptor +* @param speed : current device speed +* @param length : pointer data length +* @retval pointer to descriptor buffer +*/ +#ifdef USB_OTG_HS_CORE +uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, + uint16_t *length) +{ + *length = sizeof (USBD_MSC_OtherCfgDesc); + return USBD_MSC_OtherCfgDesc; +} +#endif +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c index e1d3dda0b..155e9889f 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c @@ -1,134 +1,134 @@ -/** - ****************************************************************************** - * @file usbd_msc_data.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides all the vital inquiry pages and sense data. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_data.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_DATA - * @brief Mass storage info/data module - * @{ - */ - -/** @defgroup MSC_DATA_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Variables - * @{ - */ - - -/* USB Mass storage Page 0 Inquiry Data */ -const uint8_t MSC_Page00_Inquiry_Data[] = {//7 - 0x00, - 0x00, - 0x00, - (LENGTH_INQUIRY_PAGE00 - 4), - 0x00, - 0x80, - 0x83 -}; -/* USB Mass storage sense 6 Data */ -const uint8_t MSC_Mode_Sense6_data[] = { - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 -}; -/* USB Mass storage sense 10 Data */ -const uint8_t MSC_Mode_Sense10_data[] = { - 0x00, - 0x06, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 -}; -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Functions - * @{ - */ - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_msc_data.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides all the vital inquiry pages and sense data. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_msc_data.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup MSC_DATA + * @brief Mass storage info/data module + * @{ + */ + +/** @defgroup MSC_DATA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_DATA_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_DATA_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_DATA_Private_Variables + * @{ + */ + + +/* USB Mass storage Page 0 Inquiry Data */ +const uint8_t MSC_Page00_Inquiry_Data[] = {//7 + 0x00, + 0x00, + 0x00, + (LENGTH_INQUIRY_PAGE00 - 4), + 0x00, + 0x80, + 0x83 +}; +/* USB Mass storage sense 6 Data */ +const uint8_t MSC_Mode_Sense6_data[] = { + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; +/* USB Mass storage sense 10 Data */ +const uint8_t MSC_Mode_Sense10_data[] = { + 0x00, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; +/** + * @} + */ + + +/** @defgroup MSC_DATA_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_DATA_Private_Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c index 08409a03c..d552a89ec 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c @@ -1,768 +1,768 @@ -/** - ****************************************************************************** - * @file usbd_msc_scsi.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides all the USBD SCSI layer functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_bot.h" -#include "usbd_msc_scsi.h" -#include "usbd_msc_mem.h" -#include "usbd_msc_data.h" - - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_SCSI - * @brief Mass storage SCSI layer module - * @{ - */ - -/** @defgroup MSC_SCSI_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Variables - * @{ - */ - -SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; -uint8_t SCSI_Sense_Head; -uint8_t SCSI_Sense_Tail; - -uint32_t SCSI_blk_size; -uint32_t SCSI_blk_nbr; - -uint32_t SCSI_blk_addr; -uint32_t SCSI_blk_len; - -USB_OTG_CORE_HANDLE *cdev; -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_FunctionPrototypes - * @{ - */ -static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params); -static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params); -static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params); -static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params); -static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params); -static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params); -static int8_t SCSI_AllowRemoval(uint8_t lun, uint8_t *params); // modified by OpenTX -static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params); -static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params); -static int8_t SCSI_Write10(uint8_t lun , uint8_t *params); -static int8_t SCSI_Read10(uint8_t lun , uint8_t *params); -static int8_t SCSI_Verify10(uint8_t lun, uint8_t *params); -static int8_t SCSI_CheckAddressRange (uint8_t lun , - uint32_t blk_offset , - uint16_t blk_nbr); -static int8_t SCSI_ProcessRead (uint8_t lun); - -static int8_t SCSI_ProcessWrite (uint8_t lun); -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Functions - * @{ - */ - - -/** -* @brief SCSI_ProcessCmd -* Process SCSI commands -* @param pdev: device instance -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, - uint8_t lun, - uint8_t *params) -{ - cdev = pdev; - - switch (params[0]) - { - case SCSI_TEST_UNIT_READY: - return SCSI_TestUnitReady(lun, params); - - case SCSI_REQUEST_SENSE: - return SCSI_RequestSense (lun, params); - case SCSI_INQUIRY: - return SCSI_Inquiry(lun, params); - - case SCSI_START_STOP_UNIT: - return SCSI_StartStopUnit(lun, params); - - case SCSI_ALLOW_MEDIUM_REMOVAL: - return SCSI_AllowRemoval( lun, params); // ST lib 2.2.0 uses SCSI_StartStopUnit which doesn't work // modified by OpenTX - - case SCSI_MODE_SENSE6: - return SCSI_ModeSense6 (lun, params); - - case SCSI_MODE_SENSE10: - return SCSI_ModeSense10 (lun, params); - - case SCSI_READ_FORMAT_CAPACITIES: - return SCSI_ReadFormatCapacity(lun, params); - - case SCSI_READ_CAPACITY10: - return SCSI_ReadCapacity10(lun, params); - - case SCSI_READ10: - return SCSI_Read10(lun, params); - - case SCSI_WRITE10: - return SCSI_Write10(lun, params); - - case SCSI_VERIFY10: - return SCSI_Verify10(lun, params); - - default: - SCSI_SenseCode(lun, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } -} - - -/** -* @brief SCSI_TestUnitReady -* Process SCSI Test Unit Ready Command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params) -{ - - /* case 9 : Hi > D0 */ - if (MSC_BOT_cbw.dDataLength != 0) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_Inquiry -* Process Inquiry command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params) -{ - uint8_t* pPage; - uint16_t len; - - if (params[1] & 0x01)/*Evpd is set*/ - { - pPage = (uint8_t *)MSC_Page00_Inquiry_Data; - len = LENGTH_INQUIRY_PAGE00; - } - else - { - - pPage = (uint8_t *)&USBD_STORAGE_fops->pInquiry[lun * USBD_STD_INQUIRY_LENGTH]; - len = pPage[4] + 5; - - if (params[4] <= len) - { - len = params[4]; - } - } - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = pPage[len]; - } - return 0; -} - -/** -* @brief SCSI_ReadCapacity10 -* Process Read Capacity 10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params) -{ - - if(USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - else - { - - MSC_BOT_Data[0] = (uint8_t)((SCSI_blk_nbr - 1) >> 24); - MSC_BOT_Data[1] = (uint8_t)((SCSI_blk_nbr - 1) >> 16); - MSC_BOT_Data[2] = (uint8_t)((SCSI_blk_nbr - 1) >> 8); - MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1); - - MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24); - MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16); - MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8); - MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size); - - MSC_BOT_DataLen = 8; - return 0; - } -} -/** -* @brief SCSI_ReadFormatCapacity -* Process Read Format Capacity command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params) -{ - - uint32_t blk_size; - uint32_t blk_nbr; - uint16_t i; - - for(i=0 ; i < 12 ; i++) - { - MSC_BOT_Data[i] = 0; - } - - if(USBD_STORAGE_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - else - { - MSC_BOT_Data[3] = 0x08; - MSC_BOT_Data[4] = (uint8_t)((blk_nbr - 1) >> 24); - MSC_BOT_Data[5] = (uint8_t)((blk_nbr - 1) >> 16); - MSC_BOT_Data[6] = (uint8_t)((blk_nbr - 1) >> 8); - MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1); - - MSC_BOT_Data[8] = 0x02; - MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16); - MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8); - MSC_BOT_Data[11] = (uint8_t)(blk_size); - - MSC_BOT_DataLen = 12; - return 0; - } -} -/** -* @brief SCSI_ModeSense6 -* Process Mode Sense6 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params) -{ - - uint16_t len = 8 ; - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len]; - } - return 0; -} - -/** -* @brief SCSI_ModeSense10 -* Process Mode Sense10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params) -{ - uint16_t len = 8; - - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len]; - } - return 0; -} - -/** -* @brief SCSI_RequestSense -* Process Request Sense command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params) -{ - uint8_t i; - - for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++) - { - MSC_BOT_Data[i] = 0; - } - - MSC_BOT_Data[0] = 0x70; - MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6; - - if((SCSI_Sense_Head != SCSI_Sense_Tail)) { - - MSC_BOT_Data[2] = SCSI_Sense[SCSI_Sense_Head].Skey; - MSC_BOT_Data[12] = SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ; - MSC_BOT_Data[13] = SCSI_Sense[SCSI_Sense_Head].w.b.ASC; - SCSI_Sense_Head++; - - if (SCSI_Sense_Head == SENSE_LIST_DEEPTH) - { - SCSI_Sense_Head = 0; - } - } - MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN; - - if (params[4] <= REQUEST_SENSE_DATA_LEN) - { - MSC_BOT_DataLen = params[4]; - } - return 0; -} - -/** -* @brief SCSI_SenseCode -* Load the last error code in the error list -* @param lun: Logical unit number -* @param sKey: Sense Key -* @param ASC: Additional Sense Key -* @retval none - -*/ -void SCSI_SenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC) -{ - SCSI_Sense[SCSI_Sense_Tail].Skey = sKey; - SCSI_Sense[SCSI_Sense_Tail].w.ASC = ASC << 8; - SCSI_Sense_Tail++; - if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH) - { - SCSI_Sense_Tail = 0; - } -} -/** -* @brief SCSI_StartStopUnit -* Process Start Stop Unit command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -extern uint8_t lunReady[]; // modified by OpenTX - -static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params) -{ - MSC_BOT_DataLen = 0; - -#if defined(BOOT) // modified by OpenTX - if (lun < 2) -#else - if (lun < 1) -#endif - { - if (params[4] & 1) { - // lun to be active - lunReady[lun] = 1 ; - } - else { - // lun to be ejected - lunReady[lun] = 0 ; - } - } - - return 0; -} - -static int8_t SCSI_AllowRemoval(uint8_t lun, uint8_t *params) -{ - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_Read10 -* Process Read10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_Read10(uint8_t lun , uint8_t *params) -{ - if(MSC_BOT_State == BOT_IDLE) /* Idle */ - { - - /* case 10 : Ho <> Di */ - - if ((MSC_BOT_cbw.bmFlags & 0x80) != 0x80) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - - SCSI_blk_addr = (params[2] << 24) | \ - (params[3] << 16) | \ - (params[4] << 8) | \ - params[5]; - - SCSI_blk_len = (params[7] << 8) | \ - params[8]; - - - - if( SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - - MSC_BOT_State = BOT_DATA_IN; - // SCSI_blk_addr *= SCSI_blk_size; // modified by OpenTX - SCSI_blk_len *= SCSI_blk_size; - - /* cases 4,5 : Hi <> Dn */ - if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - } - MSC_BOT_DataLen = MSC_MEDIA_PACKET; - - return SCSI_ProcessRead(lun); -} - -/** -* @brief SCSI_Write10 -* Process Write10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_Write10 (uint8_t lun , uint8_t *params) -{ - if (MSC_BOT_State == BOT_IDLE) /* Idle */ - { - - /* case 8 : Hi <> Do */ - - if ((MSC_BOT_cbw.bmFlags & 0x80) == 0x80) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - /* Check whether Media is ready */ - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - - /* Check If media is write-protected */ - if(USBD_STORAGE_fops->IsWriteProtected(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - WRITE_PROTECTED); - return -1; - } - - - SCSI_blk_addr = (params[2] << 24) | \ - (params[3] << 16) | \ - (params[4] << 8) | \ - params[5]; - SCSI_blk_len = (params[7] << 8) | \ - params[8]; - - /* check if LBA address is in the right range */ - if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - - // SCSI_blk_addr *= SCSI_blk_size; // modified by OpenTX - SCSI_blk_len *= SCSI_blk_size; - - /* cases 3,11,13 : Hn,Ho <> D0 */ - if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - /* Prepare EP to receive first data packet */ - MSC_BOT_State = BOT_DATA_OUT; - DCD_EP_PrepareRx (cdev, - MSC_OUT_EP, - MSC_BOT_Data, - MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); - } - else /* Write Process ongoing */ - { - return SCSI_ProcessWrite(lun); - } - return 0; -} - - -/** -* @brief SCSI_Verify10 -* Process Verify10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_Verify10(uint8_t lun , uint8_t *params){ - if ((params[1]& 0x02) == 0x02) - { - SCSI_SenseCode (lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); - return -1; /* Error, Verify Mode Not supported*/ - } - - SCSI_blk_addr = (params[2] << 24) | \ - (params[3] << 16) | \ - (params[4] << 8) | \ - params[5]; - SCSI_blk_len = (params[7] << 8) | \ - params[8]; - - if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_CheckAddressRange -* Check address range -* @param lun: Logical unit number -* @param blk_offset: first block address -* @param blk_nbr: number of block to be processed -* @retval status -*/ -static int8_t SCSI_CheckAddressRange (uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr) -{ - if (USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0) // modified by OpenTX - { - SCSI_SenseCode(lun, NOT_READY, MEDIUM_NOT_PRESENT); - return -1; - } - - if ((blk_offset + blk_nbr) > SCSI_blk_nbr ) - { - SCSI_SenseCode(lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); - return -1; - } - - return 0; -} - -/** -* @brief SCSI_ProcessRead -* Handle Read Process -* @param lun: Logical unit number -* @retval status -*/ -static int8_t SCSI_ProcessRead (uint8_t lun) -{ - uint32_t len; - - len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); - - if( USBD_STORAGE_fops->Read(lun , - MSC_BOT_Data, - SCSI_blk_addr, // modified by OpenTX - len / SCSI_blk_size) < 0) - { - - SCSI_SenseCode(lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR); - return -1; - } - - - DCD_EP_Tx (cdev, - MSC_IN_EP, - MSC_BOT_Data, - len); - - - SCSI_blk_addr += len / SCSI_blk_size; // modified by OpenTX - SCSI_blk_len -= len; - - /* case 6 : Hi = Di */ - MSC_BOT_csw.dDataResidue -= len; - - if (SCSI_blk_len == 0) - { - MSC_BOT_State = BOT_LAST_DATA_IN; - } - return 0; -} - -/** -* @brief SCSI_ProcessWrite -* Handle Write Process -* @param lun: Logical unit number -* @retval status -*/ - -static int8_t SCSI_ProcessWrite (uint8_t lun) -{ - uint32_t len; - - len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); - - if(USBD_STORAGE_fops->Write(lun , - MSC_BOT_Data, - SCSI_blk_addr, // modified by OpenTX - len / SCSI_blk_size) < 0) - { - SCSI_SenseCode(lun, HARDWARE_ERROR, WRITE_FAULT); - return -1; - } - - - SCSI_blk_addr += len / SCSI_blk_size; // modified by OpenTX - SCSI_blk_len -= len; - - /* case 12 : Ho = Do */ - MSC_BOT_csw.dDataResidue -= len; - - if (SCSI_blk_len == 0) - { - MSC_BOT_SendCSW (cdev, CSW_CMD_PASSED); - } - else - { - /* Prapare EP to Receive next packet */ - DCD_EP_PrepareRx (cdev, - MSC_OUT_EP, - MSC_BOT_Data, - MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); - } - - return 0; -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_msc_scsi.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides all the USBD SCSI layer functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_msc_bot.h" +#include "usbd_msc_scsi.h" +#include "usbd_msc_mem.h" +#include "usbd_msc_data.h" + + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup MSC_SCSI + * @brief Mass storage SCSI layer module + * @{ + */ + +/** @defgroup MSC_SCSI_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_SCSI_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup MSC_SCSI_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_SCSI_Private_Variables + * @{ + */ + +SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; +uint8_t SCSI_Sense_Head; +uint8_t SCSI_Sense_Tail; + +uint32_t SCSI_blk_size; +uint32_t SCSI_blk_nbr; + +uint32_t SCSI_blk_addr; +uint32_t SCSI_blk_len; + +USB_OTG_CORE_HANDLE *cdev; +/** + * @} + */ + + +/** @defgroup MSC_SCSI_Private_FunctionPrototypes + * @{ + */ +static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params); +static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params); +static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params); +static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params); +static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params); +static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params); +static int8_t SCSI_AllowRemoval(uint8_t lun, uint8_t *params); // modified by OpenTX +static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params); +static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params); +static int8_t SCSI_Write10(uint8_t lun , uint8_t *params); +static int8_t SCSI_Read10(uint8_t lun , uint8_t *params); +static int8_t SCSI_Verify10(uint8_t lun, uint8_t *params); +static int8_t SCSI_CheckAddressRange (uint8_t lun , + uint32_t blk_offset , + uint16_t blk_nbr); +static int8_t SCSI_ProcessRead (uint8_t lun); + +static int8_t SCSI_ProcessWrite (uint8_t lun); +/** + * @} + */ + + +/** @defgroup MSC_SCSI_Private_Functions + * @{ + */ + + +/** +* @brief SCSI_ProcessCmd +* Process SCSI commands +* @param pdev: device instance +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, + uint8_t lun, + uint8_t *params) +{ + cdev = pdev; + + switch (params[0]) + { + case SCSI_TEST_UNIT_READY: + return SCSI_TestUnitReady(lun, params); + + case SCSI_REQUEST_SENSE: + return SCSI_RequestSense (lun, params); + case SCSI_INQUIRY: + return SCSI_Inquiry(lun, params); + + case SCSI_START_STOP_UNIT: + return SCSI_StartStopUnit(lun, params); + + case SCSI_ALLOW_MEDIUM_REMOVAL: + return SCSI_AllowRemoval( lun, params); // ST lib 2.2.0 uses SCSI_StartStopUnit which doesn't work // modified by OpenTX + + case SCSI_MODE_SENSE6: + return SCSI_ModeSense6 (lun, params); + + case SCSI_MODE_SENSE10: + return SCSI_ModeSense10 (lun, params); + + case SCSI_READ_FORMAT_CAPACITIES: + return SCSI_ReadFormatCapacity(lun, params); + + case SCSI_READ_CAPACITY10: + return SCSI_ReadCapacity10(lun, params); + + case SCSI_READ10: + return SCSI_Read10(lun, params); + + case SCSI_WRITE10: + return SCSI_Write10(lun, params); + + case SCSI_VERIFY10: + return SCSI_Verify10(lun, params); + + default: + SCSI_SenseCode(lun, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } +} + + +/** +* @brief SCSI_TestUnitReady +* Process SCSI Test Unit Ready Command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params) +{ + + /* case 9 : Hi > D0 */ + if (MSC_BOT_cbw.dDataLength != 0) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } + + if(USBD_STORAGE_fops->IsReady(lun) !=0 ) + { + SCSI_SenseCode(lun, + NOT_READY, + MEDIUM_NOT_PRESENT); + return -1; + } + MSC_BOT_DataLen = 0; + return 0; +} + +/** +* @brief SCSI_Inquiry +* Process Inquiry command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params) +{ + uint8_t* pPage; + uint16_t len; + + if (params[1] & 0x01)/*Evpd is set*/ + { + pPage = (uint8_t *)MSC_Page00_Inquiry_Data; + len = LENGTH_INQUIRY_PAGE00; + } + else + { + + pPage = (uint8_t *)&USBD_STORAGE_fops->pInquiry[lun * USBD_STD_INQUIRY_LENGTH]; + len = pPage[4] + 5; + + if (params[4] <= len) + { + len = params[4]; + } + } + MSC_BOT_DataLen = len; + + while (len) + { + len--; + MSC_BOT_Data[len] = pPage[len]; + } + return 0; +} + +/** +* @brief SCSI_ReadCapacity10 +* Process Read Capacity 10 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params) +{ + + if(USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0) + { + SCSI_SenseCode(lun, + NOT_READY, + MEDIUM_NOT_PRESENT); + return -1; + } + else + { + + MSC_BOT_Data[0] = (uint8_t)((SCSI_blk_nbr - 1) >> 24); + MSC_BOT_Data[1] = (uint8_t)((SCSI_blk_nbr - 1) >> 16); + MSC_BOT_Data[2] = (uint8_t)((SCSI_blk_nbr - 1) >> 8); + MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1); + + MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24); + MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16); + MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8); + MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size); + + MSC_BOT_DataLen = 8; + return 0; + } +} +/** +* @brief SCSI_ReadFormatCapacity +* Process Read Format Capacity command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params) +{ + + uint32_t blk_size; + uint32_t blk_nbr; + uint16_t i; + + for(i=0 ; i < 12 ; i++) + { + MSC_BOT_Data[i] = 0; + } + + if(USBD_STORAGE_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0) + { + SCSI_SenseCode(lun, + NOT_READY, + MEDIUM_NOT_PRESENT); + return -1; + } + else + { + MSC_BOT_Data[3] = 0x08; + MSC_BOT_Data[4] = (uint8_t)((blk_nbr - 1) >> 24); + MSC_BOT_Data[5] = (uint8_t)((blk_nbr - 1) >> 16); + MSC_BOT_Data[6] = (uint8_t)((blk_nbr - 1) >> 8); + MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1); + + MSC_BOT_Data[8] = 0x02; + MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16); + MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8); + MSC_BOT_Data[11] = (uint8_t)(blk_size); + + MSC_BOT_DataLen = 12; + return 0; + } +} +/** +* @brief SCSI_ModeSense6 +* Process Mode Sense6 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params) +{ + + uint16_t len = 8 ; + MSC_BOT_DataLen = len; + + while (len) + { + len--; + MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len]; + } + return 0; +} + +/** +* @brief SCSI_ModeSense10 +* Process Mode Sense10 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params) +{ + uint16_t len = 8; + + MSC_BOT_DataLen = len; + + while (len) + { + len--; + MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len]; + } + return 0; +} + +/** +* @brief SCSI_RequestSense +* Process Request Sense command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ + +static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params) +{ + uint8_t i; + + for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++) + { + MSC_BOT_Data[i] = 0; + } + + MSC_BOT_Data[0] = 0x70; + MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6; + + if((SCSI_Sense_Head != SCSI_Sense_Tail)) { + + MSC_BOT_Data[2] = SCSI_Sense[SCSI_Sense_Head].Skey; + MSC_BOT_Data[12] = SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ; + MSC_BOT_Data[13] = SCSI_Sense[SCSI_Sense_Head].w.b.ASC; + SCSI_Sense_Head++; + + if (SCSI_Sense_Head == SENSE_LIST_DEEPTH) + { + SCSI_Sense_Head = 0; + } + } + MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN; + + if (params[4] <= REQUEST_SENSE_DATA_LEN) + { + MSC_BOT_DataLen = params[4]; + } + return 0; +} + +/** +* @brief SCSI_SenseCode +* Load the last error code in the error list +* @param lun: Logical unit number +* @param sKey: Sense Key +* @param ASC: Additional Sense Key +* @retval none + +*/ +void SCSI_SenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC) +{ + SCSI_Sense[SCSI_Sense_Tail].Skey = sKey; + SCSI_Sense[SCSI_Sense_Tail].w.ASC = ASC << 8; + SCSI_Sense_Tail++; + if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH) + { + SCSI_Sense_Tail = 0; + } +} +/** +* @brief SCSI_StartStopUnit +* Process Start Stop Unit command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ + +extern uint8_t lunReady[]; // modified by OpenTX + +static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params) +{ + MSC_BOT_DataLen = 0; + +#if defined(BOOT) // modified by OpenTX + if (lun < 2) +#else + if (lun < 1) +#endif + { + if (params[4] & 1) { + // lun to be active + lunReady[lun] = 1 ; + } + else { + // lun to be ejected + lunReady[lun] = 0 ; + } + } + + return 0; +} + +static int8_t SCSI_AllowRemoval(uint8_t lun, uint8_t *params) +{ + MSC_BOT_DataLen = 0; + return 0; +} + +/** +* @brief SCSI_Read10 +* Process Read10 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_Read10(uint8_t lun , uint8_t *params) +{ + if(MSC_BOT_State == BOT_IDLE) /* Idle */ + { + + /* case 10 : Ho <> Di */ + + if ((MSC_BOT_cbw.bmFlags & 0x80) != 0x80) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } + + if(USBD_STORAGE_fops->IsReady(lun) !=0 ) + { + SCSI_SenseCode(lun, + NOT_READY, + MEDIUM_NOT_PRESENT); + return -1; + } + + SCSI_blk_addr = (params[2] << 24) | \ + (params[3] << 16) | \ + (params[4] << 8) | \ + params[5]; + + SCSI_blk_len = (params[7] << 8) | \ + params[8]; + + + + if( SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) + { + return -1; /* error */ + } + + MSC_BOT_State = BOT_DATA_IN; + // SCSI_blk_addr *= SCSI_blk_size; // modified by OpenTX + SCSI_blk_len *= SCSI_blk_size; + + /* cases 4,5 : Hi <> Dn */ + if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } + } + MSC_BOT_DataLen = MSC_MEDIA_PACKET; + + return SCSI_ProcessRead(lun); +} + +/** +* @brief SCSI_Write10 +* Process Write10 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ + +static int8_t SCSI_Write10 (uint8_t lun , uint8_t *params) +{ + if (MSC_BOT_State == BOT_IDLE) /* Idle */ + { + + /* case 8 : Hi <> Do */ + + if ((MSC_BOT_cbw.bmFlags & 0x80) == 0x80) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } + + /* Check whether Media is ready */ + if(USBD_STORAGE_fops->IsReady(lun) !=0 ) + { + SCSI_SenseCode(lun, + NOT_READY, + MEDIUM_NOT_PRESENT); + return -1; + } + + /* Check If media is write-protected */ + if(USBD_STORAGE_fops->IsWriteProtected(lun) !=0 ) + { + SCSI_SenseCode(lun, + NOT_READY, + WRITE_PROTECTED); + return -1; + } + + + SCSI_blk_addr = (params[2] << 24) | \ + (params[3] << 16) | \ + (params[4] << 8) | \ + params[5]; + SCSI_blk_len = (params[7] << 8) | \ + params[8]; + + /* check if LBA address is in the right range */ + if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) + { + return -1; /* error */ + } + + // SCSI_blk_addr *= SCSI_blk_size; // modified by OpenTX + SCSI_blk_len *= SCSI_blk_size; + + /* cases 3,11,13 : Hn,Ho <> D0 */ + if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } + + /* Prepare EP to receive first data packet */ + MSC_BOT_State = BOT_DATA_OUT; + DCD_EP_PrepareRx (cdev, + MSC_OUT_EP, + MSC_BOT_Data, + MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); + } + else /* Write Process ongoing */ + { + return SCSI_ProcessWrite(lun); + } + return 0; +} + + +/** +* @brief SCSI_Verify10 +* Process Verify10 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ + +static int8_t SCSI_Verify10(uint8_t lun , uint8_t *params){ + if ((params[1]& 0x02) == 0x02) + { + SCSI_SenseCode (lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); + return -1; /* Error, Verify Mode Not supported*/ + } + + SCSI_blk_addr = (params[2] << 24) | \ + (params[3] << 16) | \ + (params[4] << 8) | \ + params[5]; + SCSI_blk_len = (params[7] << 8) | \ + params[8]; + + if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) + { + return -1; /* error */ + } + MSC_BOT_DataLen = 0; + return 0; +} + +/** +* @brief SCSI_CheckAddressRange +* Check address range +* @param lun: Logical unit number +* @param blk_offset: first block address +* @param blk_nbr: number of block to be processed +* @retval status +*/ +static int8_t SCSI_CheckAddressRange (uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr) +{ + if (USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0) // modified by OpenTX + { + SCSI_SenseCode(lun, NOT_READY, MEDIUM_NOT_PRESENT); + return -1; + } + + if ((blk_offset + blk_nbr) > SCSI_blk_nbr ) + { + SCSI_SenseCode(lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); + return -1; + } + + return 0; +} + +/** +* @brief SCSI_ProcessRead +* Handle Read Process +* @param lun: Logical unit number +* @retval status +*/ +static int8_t SCSI_ProcessRead (uint8_t lun) +{ + uint32_t len; + + len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); + + if( USBD_STORAGE_fops->Read(lun , + MSC_BOT_Data, + SCSI_blk_addr, // modified by OpenTX + len / SCSI_blk_size) < 0) + { + + SCSI_SenseCode(lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR); + return -1; + } + + + DCD_EP_Tx (cdev, + MSC_IN_EP, + MSC_BOT_Data, + len); + + + SCSI_blk_addr += len / SCSI_blk_size; // modified by OpenTX + SCSI_blk_len -= len; + + /* case 6 : Hi = Di */ + MSC_BOT_csw.dDataResidue -= len; + + if (SCSI_blk_len == 0) + { + MSC_BOT_State = BOT_LAST_DATA_IN; + } + return 0; +} + +/** +* @brief SCSI_ProcessWrite +* Handle Write Process +* @param lun: Logical unit number +* @retval status +*/ + +static int8_t SCSI_ProcessWrite (uint8_t lun) +{ + uint32_t len; + + len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); + + if(USBD_STORAGE_fops->Write(lun , + MSC_BOT_Data, + SCSI_blk_addr, // modified by OpenTX + len / SCSI_blk_size) < 0) + { + SCSI_SenseCode(lun, HARDWARE_ERROR, WRITE_FAULT); + return -1; + } + + + SCSI_blk_addr += len / SCSI_blk_size; // modified by OpenTX + SCSI_blk_len -= len; + + /* case 12 : Ho = Do */ + MSC_BOT_csw.dDataResidue -= len; + + if (SCSI_blk_len == 0) + { + MSC_BOT_SendCSW (cdev, CSW_CMD_PASSED); + } + else + { + /* Prapare EP to Receive next packet */ + DCD_EP_PrepareRx (cdev, + MSC_OUT_EP, + MSC_BOT_Data, + MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); + } + + return 0; +} +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_conf_template.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_conf_template.h index 9809f3596..4d35c1928 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_conf_template.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_conf_template.h @@ -1,82 +1,82 @@ -/** - ****************************************************************************** - * @file usbd_conf_template.h - * @author MCD Application Team - * @version V1.2.0 - * @date 30-June-2015 - * @brief usb device configuration template file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CONF__H__ -#define __USBD_CONF__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -/** @defgroup USB_CONF_Exported_Defines - * @{ - */ -#define USE_USB_OTG_HS - -#define USBD_CFG_MAX_NUM 1 -#define USB_MAX_STR_DESC_SIZ 64 -#define USBD_EP0_MAX_PACKET_SIZE 64 - -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USBD_CONF__H__ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usbd_conf_template.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-June-2015 + * @brief usb device configuration template file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CONF__H__ +#define __USBD_CONF__H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + +/** @defgroup USB_CONF_Exported_Defines + * @{ + */ +#define USE_USB_OTG_HS + +#define USBD_CFG_MAX_NUM 1 +#define USB_MAX_STR_DESC_SIZ 64 +#define USBD_EP0_MAX_PACKET_SIZE 64 + +/** + * @} + */ + + +/** @defgroup USB_CONF_Exported_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_CONF_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_CONF_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_CONF_Exported_FunctionsPrototype + * @{ + */ +/** + * @} + */ + + +#endif //__USBD_CONF__H__ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_core.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_core.h index f31bb27e2..df7e4a6c3 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_core.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_core.h @@ -1,120 +1,120 @@ -/** - ****************************************************************************** - * @file usbd_core.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Header file for usbd_core.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CORE_H -#define __USBD_CORE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" -#include "usbd_def.h" -#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_CORE - * @brief This file is the Header file for usbd_core.c file - * @{ - */ - - -/** @defgroup USBD_CORE_Exported_Defines - * @{ - */ - -typedef enum { - USBD_OK = 0, - USBD_BUSY, - USBD_FAIL, -}USBD_Status; -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_FunctionsPrototype - * @{ - */ -void USBD_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - const USBD_DEVICE *pDevice, - const USBD_Class_cb_TypeDef *class_cb, - const USBD_Usr_cb_TypeDef *usr_cb); // modified by OpenTX - -USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev); - -USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); - -USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); - -/** - * @} - */ - -#endif /* __USBD_CORE_H */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - +/** + ****************************************************************************** + * @file usbd_core.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Header file for usbd_core.c + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + +/* Includes ------------------------------------------------------------------*/ +#include "usb_dcd.h" +#include "usbd_def.h" +#include "usbd_conf.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_CORE + * @brief This file is the Header file for usbd_core.c file + * @{ + */ + + +/** @defgroup USBD_CORE_Exported_Defines + * @{ + */ + +typedef enum { + USBD_OK = 0, + USBD_BUSY, + USBD_FAIL, +}USBD_Status; +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_FunctionsPrototype + * @{ + */ +void USBD_Init(USB_OTG_CORE_HANDLE *pdev, + USB_OTG_CORE_ID_TypeDef coreID, + const USBD_DEVICE *pDevice, + const USBD_Class_cb_TypeDef *class_cb, + const USBD_Usr_cb_TypeDef *usr_cb); // modified by OpenTX + +USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev); + +USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); + +USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); + +/** + * @} + */ + +#endif /* __USBD_CORE_H */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_def.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_def.h index 5b10d2ca3..965989cf2 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_def.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_def.h @@ -1,156 +1,156 @@ -/** - ****************************************************************************** - * @file usbd_def.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief general defines for the usb device library - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_DEF_H -#define __USBD_DEF_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_DEF - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_DEF_Exported_Defines - * @{ - */ - -#ifndef NULL -#define NULL 0 -#endif - -#define USB_LEN_DEV_QUALIFIER_DESC 0x0A -#define USB_LEN_DEV_DESC 0x12 -#define USB_LEN_CFG_DESC 0x09 -#define USB_LEN_IF_DESC 0x09 -#define USB_LEN_EP_DESC 0x07 -#define USB_LEN_OTG_DESC 0x03 - -#define USBD_IDX_LANGID_STR 0x00 -#define USBD_IDX_MFC_STR 0x01 -#define USBD_IDX_PRODUCT_STR 0x02 -#define USBD_IDX_SERIAL_STR 0x03 -#define USBD_IDX_CONFIG_STR 0x04 -#define USBD_IDX_INTERFACE_STR 0x05 - -#define USB_REQ_TYPE_STANDARD 0x00 -#define USB_REQ_TYPE_CLASS 0x20 -#define USB_REQ_TYPE_VENDOR 0x40 -#define USB_REQ_TYPE_MASK 0x60 - -#define USB_REQ_RECIPIENT_DEVICE 0x00 -#define USB_REQ_RECIPIENT_INTERFACE 0x01 -#define USB_REQ_RECIPIENT_ENDPOINT 0x02 -#define USB_REQ_RECIPIENT_MASK 0x03 - -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C - -#define USB_DESC_TYPE_DEVICE 1 -#define USB_DESC_TYPE_CONFIGURATION 2 -#define USB_DESC_TYPE_STRING 3 -#define USB_DESC_TYPE_INTERFACE 4 -#define USB_DESC_TYPE_ENDPOINT 5 -#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 -#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 -#define USB_DESC_TYPE_BOS 0x0F - -#define USB_CONFIG_REMOTE_WAKEUP 2 -#define USB_CONFIG_SELF_POWERED 1 - -#define USB_FEATURE_EP_HALT 0 -#define USB_FEATURE_REMOTE_WAKEUP 1 -#define USB_FEATURE_TEST_MODE 2 - -/** - * @} - */ - - -/** @defgroup USBD_DEF_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_DEF_Exported_Macros - * @{ - */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) - -#define LOBYTE(x) ((uint8_t)((x) & 0x00FF)) -#define HIBYTE(x) ((uint8_t)(((x) & 0xFF00) >>8)) -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_FunctionsPrototype - * @{ - */ - -/** - * @} - */ - -#endif /* __USBD_DEF_H */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_def.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief general defines for the usb device library + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USBD_DEF_H +#define __USBD_DEF_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_DEF + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_DEF_Exported_Defines + * @{ + */ + +#ifndef NULL +#define NULL 0 +#endif + +#define USB_LEN_DEV_QUALIFIER_DESC 0x0A +#define USB_LEN_DEV_DESC 0x12 +#define USB_LEN_CFG_DESC 0x09 +#define USB_LEN_IF_DESC 0x09 +#define USB_LEN_EP_DESC 0x07 +#define USB_LEN_OTG_DESC 0x03 + +#define USBD_IDX_LANGID_STR 0x00 +#define USBD_IDX_MFC_STR 0x01 +#define USBD_IDX_PRODUCT_STR 0x02 +#define USBD_IDX_SERIAL_STR 0x03 +#define USBD_IDX_CONFIG_STR 0x04 +#define USBD_IDX_INTERFACE_STR 0x05 + +#define USB_REQ_TYPE_STANDARD 0x00 +#define USB_REQ_TYPE_CLASS 0x20 +#define USB_REQ_TYPE_VENDOR 0x40 +#define USB_REQ_TYPE_MASK 0x60 + +#define USB_REQ_RECIPIENT_DEVICE 0x00 +#define USB_REQ_RECIPIENT_INTERFACE 0x01 +#define USB_REQ_RECIPIENT_ENDPOINT 0x02 +#define USB_REQ_RECIPIENT_MASK 0x03 + +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIGURATION 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 +#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 +#define USB_DESC_TYPE_BOS 0x0F + +#define USB_CONFIG_REMOTE_WAKEUP 2 +#define USB_CONFIG_SELF_POWERED 1 + +#define USB_FEATURE_EP_HALT 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 + +/** + * @} + */ + + +/** @defgroup USBD_DEF_Exported_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_DEF_Exported_Macros + * @{ + */ +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) + +#define LOBYTE(x) ((uint8_t)((x) & 0x00FF)) +#define HIBYTE(x) ((uint8_t)(((x) & 0xFF00) >>8)) +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ + +#endif /* __USBD_DEF_H */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_ioreq.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_ioreq.h index 896f26db0..f83cfb51d 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_ioreq.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_ioreq.h @@ -1,121 +1,121 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header file for the usbd_ioreq.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_IOREQ_H_ -#define __USBD_IOREQ_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" -#include "usbd_core.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_IOREQ - * @brief header file for the usbd_ioreq.c file - * @{ - */ - -/** @defgroup USBD_IOREQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Exported_Types - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_IOREQ_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, - const uint8_t *buf, - uint16_t len); // modified by OpenTX - -USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev); - -USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev); - -uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum); - -/** - * @} - */ - -#endif /* __USBD_IOREQ_H_ */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_ioreq.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header file for the usbd_ioreq.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USBD_IOREQ_H_ +#define __USBD_IOREQ_H_ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" +#include "usbd_core.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_IOREQ + * @brief header file for the usbd_ioreq.c file + * @{ + */ + +/** @defgroup USBD_IOREQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Exported_Types + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_IOREQ_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, + const uint8_t *buf, + uint16_t len); // modified by OpenTX + +USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev); + +USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev); + +uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , + uint8_t epnum); + +/** + * @} + */ + +#endif /* __USBD_IOREQ_H_ */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_req.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_req.h index 9ba30ab56..8b8582b3a 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_req.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_req.h @@ -1,108 +1,108 @@ -/** - ****************************************************************************** - * @file usbd_req.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief header file for the usbd_req.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USB_REQUEST_H_ -#define __USB_REQUEST_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" -#include "usbd_core.h" -#include "usbd_conf.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_REQ - * @brief header file for the usbd_ioreq.c file - * @{ - */ - -/** @defgroup USBD_REQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Exported_Types - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_REQ_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len); -/** - * @} - */ - -#endif /* __USB_REQUEST_H_ */ - -/** - * @} - */ - -/** -* @} -*/ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_req.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief header file for the usbd_req.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USB_REQUEST_H_ +#define __USB_REQUEST_H_ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" +#include "usbd_core.h" +#include "usbd_conf.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_REQ + * @brief header file for the usbd_ioreq.c file + * @{ + */ + +/** @defgroup USBD_REQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Exported_Types + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_REQ_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); +USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); +USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); +void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len); +/** + * @} + */ + +#endif /* __USB_REQUEST_H_ */ + +/** + * @} + */ + +/** +* @} +*/ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_usr.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_usr.h index bb42f277d..df58d2ade 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_usr.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_usr.h @@ -1,141 +1,141 @@ -/** - ****************************************************************************** - * @file usbd_usr.h - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief Header file for usbd_usr.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_USR_H__ -#define __USBD_USR_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" - - -/** @addtogroup USBD_USER - * @{ - */ - -/** @addtogroup USBD_MSC_DEMO_USER_CALLBACKS - * @{ - */ - -/** @defgroup USBD_USR - * @brief This file is the Header file for usbd_usr.c - * @{ - */ - - -/** @defgroup USBD_USR_Exported_Types - * @{ - */ - -extern const USBD_Usr_cb_TypeDef USR_cb; // modified by OpenTX -extern const USBD_Usr_cb_TypeDef USR_FS_cb; // modified by OpenTX -extern const USBD_Usr_cb_TypeDef USR_HS_cb; // modified by OpenTX - - - -/** - * @} - */ - - - -/** @defgroup USBD_USR_Exported_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_Variables - * @{ - */ - -void USBD_USR_Init(void); -void USBD_USR_DeviceReset (uint8_t speed); -void USBD_USR_DeviceConfigured (void); -void USBD_USR_DeviceSuspended(void); -void USBD_USR_DeviceResumed(void); - -void USBD_USR_DeviceConnected(void); -void USBD_USR_DeviceDisconnected(void); - -void USBD_USR_FS_Init(void); -void USBD_USR_FS_DeviceReset (uint8_t speed); -void USBD_USR_FS_DeviceConfigured (void); -void USBD_USR_FS_DeviceSuspended(void); -void USBD_USR_FS_DeviceResumed(void); - -void USBD_USR_FS_DeviceConnected(void); -void USBD_USR_FS_DeviceDisconnected(void); - -void USBD_USR_HS_Init(void); -void USBD_USR_HS_DeviceReset (uint8_t speed); -void USBD_USR_HS_DeviceConfigured (void); -void USBD_USR_HS_DeviceSuspended(void); -void USBD_USR_HS_DeviceResumed(void); - -void USBD_USR_HS_DeviceConnected(void); -void USBD_USR_HS_DeviceDisconnected(void); - -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - -#endif /*__USBD_USR_H__*/ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - +/** + ****************************************************************************** + * @file usbd_usr.h + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief Header file for usbd_usr.c + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_USR_H__ +#define __USBD_USR_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + + +/** @addtogroup USBD_USER + * @{ + */ + +/** @addtogroup USBD_MSC_DEMO_USER_CALLBACKS + * @{ + */ + +/** @defgroup USBD_USR + * @brief This file is the Header file for usbd_usr.c + * @{ + */ + + +/** @defgroup USBD_USR_Exported_Types + * @{ + */ + +extern const USBD_Usr_cb_TypeDef USR_cb; // modified by OpenTX +extern const USBD_Usr_cb_TypeDef USR_FS_cb; // modified by OpenTX +extern const USBD_Usr_cb_TypeDef USR_HS_cb; // modified by OpenTX + + + +/** + * @} + */ + + + +/** @defgroup USBD_USR_Exported_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_USR_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_USR_Exported_Variables + * @{ + */ + +void USBD_USR_Init(void); +void USBD_USR_DeviceReset (uint8_t speed); +void USBD_USR_DeviceConfigured (void); +void USBD_USR_DeviceSuspended(void); +void USBD_USR_DeviceResumed(void); + +void USBD_USR_DeviceConnected(void); +void USBD_USR_DeviceDisconnected(void); + +void USBD_USR_FS_Init(void); +void USBD_USR_FS_DeviceReset (uint8_t speed); +void USBD_USR_FS_DeviceConfigured (void); +void USBD_USR_FS_DeviceSuspended(void); +void USBD_USR_FS_DeviceResumed(void); + +void USBD_USR_FS_DeviceConnected(void); +void USBD_USR_FS_DeviceDisconnected(void); + +void USBD_USR_HS_Init(void); +void USBD_USR_HS_DeviceReset (uint8_t speed); +void USBD_USR_HS_DeviceConfigured (void); +void USBD_USR_HS_DeviceSuspended(void); +void USBD_USR_HS_DeviceResumed(void); + +void USBD_USR_HS_DeviceConnected(void); +void USBD_USR_HS_DeviceDisconnected(void); + +/** + * @} + */ + +/** @defgroup USBD_USR_Exported_FunctionsPrototype + * @{ + */ +/** + * @} + */ + +#endif /*__USBD_USR_H__*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c index c3c9c8741..fbf821899 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c @@ -1,530 +1,530 @@ -/** - ****************************************************************************** - * @file usbd_core.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides all the USBD core functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" -#include "usbd_req.h" -#include "usbd_ioreq.h" -#include "usb_dcd_int.h" -#include "usb_bsp.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY -* @{ -*/ - - -/** @defgroup USBD_CORE -* @brief usbd core module -* @{ -*/ - -/** @defgroup USBD_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - - - -/** @defgroup USBD_CORE_Private_FunctionPrototypes -* @{ -*/ -static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev); -#ifdef VBUS_SENSING_ENABLED -static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev); -#endif -static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev) ; -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Variables -* @{ -*/ - -__IO USB_OTG_DCTL_TypeDef SET_TEST_MODE; - -const USBD_DCD_INT_cb_TypeDef USBD_DCD_INT_cb = -{ - USBD_DataOutStage, - USBD_DataInStage, - USBD_SetupStage, - USBD_SOF, - USBD_Reset, - USBD_Suspend, - USBD_Resume, - USBD_IsoINIncomplete, - USBD_IsoOUTIncomplete, -#ifdef VBUS_SENSING_ENABLED -USBD_DevConnected, -USBD_DevDisconnected, -#endif -}; // modified by OpenTX - -const USBD_DCD_INT_cb_TypeDef * const USBD_DCD_INT_fops = &USBD_DCD_INT_cb; // modified by OpenTX -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USBD_Init -* Initializes the device stack and load the class driver -* @param pdev: device instance -* @param core_address: USB OTG core ID -* @param class_cb: Class callback structure address -* @param usr_cb: User callback structure address -* @retval None -*/ -void USBD_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - const USBD_DEVICE *pDevice, - const USBD_Class_cb_TypeDef *class_cb, - const USBD_Usr_cb_TypeDef *usr_cb) // modified by OpenTX -{ - /* Hardware Init */ - USB_OTG_BSP_Init(pdev); - - USBD_DeInit(pdev); - - /*Register class and user callbacks */ - pdev->dev.class_cb = class_cb; - pdev->dev.usr_cb = usr_cb; - pdev->dev.usr_device = pDevice; - - /* set USB OTG core params */ - DCD_Init(pdev , coreID); - - /* Upon Init call usr callback */ - pdev->dev.usr_cb->Init(); - - /* Enable Interrupts */ - USB_OTG_BSP_EnableInterrupt(pdev); -} - -/** -* @brief USBD_DeInit -* Re-Initialize the device library -* @param pdev: device instance -* @retval status: status -*/ -USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev) -{ - /*Disable Interrupts*/ - USB_OTG_BSP_DisableInterrupt(pdev); // modified by OpenTX - USB_OTG_DisableGlobalInt(pdev); - USB_OTG_BSP_Deinit(pdev); - return USBD_OK; -} - -/** -* @brief USBD_SetupStage -* Handle the setup stage -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev) -{ - USB_SETUP_REQ req; - - USBD_ParseSetupRequest(pdev , &req); - - switch (req.bmRequest & 0x1F) - { - case USB_REQ_RECIPIENT_DEVICE: - USBD_StdDevReq (pdev, &req); - break; - - case USB_REQ_RECIPIENT_INTERFACE: - USBD_StdItfReq(pdev, &req); - break; - - case USB_REQ_RECIPIENT_ENDPOINT: - USBD_StdEPReq(pdev, &req); - break; - - default: - DCD_EP_Stall(pdev , req.bmRequest & 0x80); - break; - } - return USBD_OK; -} - -/** -* @brief USBD_DataOutStage -* Handle data out stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - USB_OTG_EP *ep; - - if(epnum == 0) - { - ep = &pdev->dev.out_ep[0]; - if ( pdev->dev.device_state == USB_OTG_EP0_DATA_OUT) - { - if(ep->rem_data_len > ep->maxpacket) - { - ep->rem_data_len -= ep->maxpacket; - - if(pdev->cfg.dma_enable == 1) - { - /* in slave mode this, is handled by the RxSTSQLvl ISR */ - ep->xfer_buff += ep->maxpacket; - } - USBD_CtlContinueRx (pdev, - ep->xfer_buff, - MIN(ep->rem_data_len ,ep->maxpacket)); - } - else - { - if((pdev->dev.class_cb->EP0_RxReady != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->EP0_RxReady(pdev); - } - USBD_CtlSendStatus(pdev); - } - } - } - else if((pdev->dev.class_cb->DataOut != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->DataOut(pdev, epnum); - } - - else - { - /* Do Nothing */ - } - return USBD_OK; -} - -/** -* @brief USBD_DataInStage -* Handle data in stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - USB_OTG_EP *ep; - - if(epnum == 0) - { - ep = &pdev->dev.in_ep[0]; - if ( pdev->dev.device_state == USB_OTG_EP0_DATA_IN) - { - if(ep->rem_data_len > ep->maxpacket) - { - ep->rem_data_len -= ep->maxpacket; - if(pdev->cfg.dma_enable == 1) - { - /* in slave mode this, is handled by the TxFifoEmpty ISR */ - ep->xfer_buff += ep->maxpacket; - } - USBD_CtlContinueSendData (pdev, - ep->xfer_buff, - ep->rem_data_len); - - /* Start the transfer */ - DCD_EP_PrepareRx (pdev, - 0, - NULL, - 0); - } - else - { /* last packet is MPS multiple, so send ZLP packet */ - if((ep->total_data_len % ep->maxpacket == 0) && - (ep->total_data_len >= ep->maxpacket) && - (ep->total_data_len < ep->ctl_data_len )) - { - - USBD_CtlContinueSendData(pdev , NULL, 0); - ep->ctl_data_len = 0; - - /* Start the transfer */ - DCD_EP_PrepareRx (pdev, - 0, - NULL, - 0); - } - else - { - if((pdev->dev.class_cb->EP0_TxSent != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->EP0_TxSent(pdev); - } - USBD_CtlReceiveStatus(pdev); - } - } - } - if (pdev->dev.test_mode == 1) - { - USBD_RunTestMode(pdev); - pdev->dev.test_mode = 0; - } - } - else if((pdev->dev.class_cb->DataIn != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->DataIn(pdev, epnum); - } - - else - { - /* Do Nothing */ - } - return USBD_OK; -} - - - - -/** -* @brief USBD_RunTestMode -* Launch test mode process -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, SET_TEST_MODE.d32); - return USBD_OK; -} - -/** -* @brief USBD_Reset -* Handle Reset event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev) -{ - /* Open EP0 OUT */ - DCD_EP_Open(pdev, - 0x00, - USB_OTG_MAX_EP0_SIZE, - EP_TYPE_CTRL); - - /* Open EP0 IN */ - DCD_EP_Open(pdev, - 0x80, - USB_OTG_MAX_EP0_SIZE, - EP_TYPE_CTRL); - - /* Upon Reset call usr call back */ - pdev->dev.device_status = USB_OTG_DEFAULT; - pdev->dev.usr_cb->DeviceReset(pdev->cfg.speed); - - return USBD_OK; -} - -/** -* @brief USBD_Resume -* Handle Resume event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev) -{ - /* Upon Resume call usr call back */ - pdev->dev.usr_cb->DeviceResumed(); - pdev->dev.device_status = pdev->dev.device_old_status; - pdev->dev.device_status = USB_OTG_CONFIGURED; - return USBD_OK; -} - - -/** -* @brief USBD_Suspend -* Handle Suspend event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.device_old_status = pdev->dev.device_status; - pdev->dev.device_status = USB_OTG_SUSPENDED; - /* Upon Resume call usr call back */ - pdev->dev.usr_cb->DeviceSuspended(); - return USBD_OK; -} - - -/** -* @brief USBD_SOF -* Handle SOF event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev) -{ - if(pdev->dev.class_cb->SOF) - { - pdev->dev.class_cb->SOF(pdev); - } - return USBD_OK; -} -/** -* @brief USBD_SetCfg -* Configure device and start the interface -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ - -USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) -{ - pdev->dev.class_cb->Init(pdev, cfgidx); - - /* Upon set config call usr call back */ - pdev->dev.usr_cb->DeviceConfigured(); - return USBD_OK; -} - -/** -* @brief USBD_ClrCfg -* Clear current configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status: USBD_Status -*/ -USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) -{ - pdev->dev.class_cb->DeInit(pdev, cfgidx); - return USBD_OK; -} - -/** -* @brief USBD_IsoINIncomplete -* Handle iso in incomplete event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.class_cb->IsoINIncomplete(pdev); - return USBD_OK; -} - -/** -* @brief USBD_IsoOUTIncomplete -* Handle iso out incomplete event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.class_cb->IsoOUTIncomplete(pdev); - return USBD_OK; -} - -#ifdef VBUS_SENSING_ENABLED -/** -* @brief USBD_DevConnected -* Handle device connection event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.usr_cb->DeviceConnected(); - pdev->dev.connection_status = 1; - return USBD_OK; -} - -/** -* @brief USBD_DevDisconnected -* Handle device disconnection event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.usr_cb->DeviceDisconnected(); - pdev->dev.class_cb->DeInit(pdev, 0); - pdev->dev.connection_status = 0; - return USBD_OK; -} -#endif -/** -* @} -*/ - - -/** -* @} -*/ - - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usbd_core.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides all the USBD core functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" +#include "usbd_req.h" +#include "usbd_ioreq.h" +#include "usb_dcd_int.h" +#include "usb_bsp.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY +* @{ +*/ + + +/** @defgroup USBD_CORE +* @brief usbd core module +* @{ +*/ + +/** @defgroup USBD_CORE_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Defines +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Macros +* @{ +*/ +/** +* @} +*/ + + + + +/** @defgroup USBD_CORE_Private_FunctionPrototypes +* @{ +*/ +static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); +static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); +static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev); +#ifdef VBUS_SENSING_ENABLED +static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev); +#endif +static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev) ; +/** +* @} +*/ + +/** @defgroup USBD_CORE_Private_Variables +* @{ +*/ + +__IO USB_OTG_DCTL_TypeDef SET_TEST_MODE; + +const USBD_DCD_INT_cb_TypeDef USBD_DCD_INT_cb = +{ + USBD_DataOutStage, + USBD_DataInStage, + USBD_SetupStage, + USBD_SOF, + USBD_Reset, + USBD_Suspend, + USBD_Resume, + USBD_IsoINIncomplete, + USBD_IsoOUTIncomplete, +#ifdef VBUS_SENSING_ENABLED +USBD_DevConnected, +USBD_DevDisconnected, +#endif +}; // modified by OpenTX + +const USBD_DCD_INT_cb_TypeDef * const USBD_DCD_INT_fops = &USBD_DCD_INT_cb; // modified by OpenTX +/** +* @} +*/ + +/** @defgroup USBD_CORE_Private_Functions +* @{ +*/ + +/** +* @brief USBD_Init +* Initializes the device stack and load the class driver +* @param pdev: device instance +* @param core_address: USB OTG core ID +* @param class_cb: Class callback structure address +* @param usr_cb: User callback structure address +* @retval None +*/ +void USBD_Init(USB_OTG_CORE_HANDLE *pdev, + USB_OTG_CORE_ID_TypeDef coreID, + const USBD_DEVICE *pDevice, + const USBD_Class_cb_TypeDef *class_cb, + const USBD_Usr_cb_TypeDef *usr_cb) // modified by OpenTX +{ + /* Hardware Init */ + USB_OTG_BSP_Init(pdev); + + USBD_DeInit(pdev); + + /*Register class and user callbacks */ + pdev->dev.class_cb = class_cb; + pdev->dev.usr_cb = usr_cb; + pdev->dev.usr_device = pDevice; + + /* set USB OTG core params */ + DCD_Init(pdev , coreID); + + /* Upon Init call usr callback */ + pdev->dev.usr_cb->Init(); + + /* Enable Interrupts */ + USB_OTG_BSP_EnableInterrupt(pdev); +} + +/** +* @brief USBD_DeInit +* Re-Initialize the device library +* @param pdev: device instance +* @retval status: status +*/ +USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev) +{ + /*Disable Interrupts*/ + USB_OTG_BSP_DisableInterrupt(pdev); // modified by OpenTX + USB_OTG_DisableGlobalInt(pdev); + USB_OTG_BSP_Deinit(pdev); + return USBD_OK; +} + +/** +* @brief USBD_SetupStage +* Handle the setup stage +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev) +{ + USB_SETUP_REQ req; + + USBD_ParseSetupRequest(pdev , &req); + + switch (req.bmRequest & 0x1F) + { + case USB_REQ_RECIPIENT_DEVICE: + USBD_StdDevReq (pdev, &req); + break; + + case USB_REQ_RECIPIENT_INTERFACE: + USBD_StdItfReq(pdev, &req); + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + USBD_StdEPReq(pdev, &req); + break; + + default: + DCD_EP_Stall(pdev , req.bmRequest & 0x80); + break; + } + return USBD_OK; +} + +/** +* @brief USBD_DataOutStage +* Handle data out stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) +{ + USB_OTG_EP *ep; + + if(epnum == 0) + { + ep = &pdev->dev.out_ep[0]; + if ( pdev->dev.device_state == USB_OTG_EP0_DATA_OUT) + { + if(ep->rem_data_len > ep->maxpacket) + { + ep->rem_data_len -= ep->maxpacket; + + if(pdev->cfg.dma_enable == 1) + { + /* in slave mode this, is handled by the RxSTSQLvl ISR */ + ep->xfer_buff += ep->maxpacket; + } + USBD_CtlContinueRx (pdev, + ep->xfer_buff, + MIN(ep->rem_data_len ,ep->maxpacket)); + } + else + { + if((pdev->dev.class_cb->EP0_RxReady != NULL)&& + (pdev->dev.device_status == USB_OTG_CONFIGURED)) + { + pdev->dev.class_cb->EP0_RxReady(pdev); + } + USBD_CtlSendStatus(pdev); + } + } + } + else if((pdev->dev.class_cb->DataOut != NULL)&& + (pdev->dev.device_status == USB_OTG_CONFIGURED)) + { + pdev->dev.class_cb->DataOut(pdev, epnum); + } + + else + { + /* Do Nothing */ + } + return USBD_OK; +} + +/** +* @brief USBD_DataInStage +* Handle data in stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) +{ + USB_OTG_EP *ep; + + if(epnum == 0) + { + ep = &pdev->dev.in_ep[0]; + if ( pdev->dev.device_state == USB_OTG_EP0_DATA_IN) + { + if(ep->rem_data_len > ep->maxpacket) + { + ep->rem_data_len -= ep->maxpacket; + if(pdev->cfg.dma_enable == 1) + { + /* in slave mode this, is handled by the TxFifoEmpty ISR */ + ep->xfer_buff += ep->maxpacket; + } + USBD_CtlContinueSendData (pdev, + ep->xfer_buff, + ep->rem_data_len); + + /* Start the transfer */ + DCD_EP_PrepareRx (pdev, + 0, + NULL, + 0); + } + else + { /* last packet is MPS multiple, so send ZLP packet */ + if((ep->total_data_len % ep->maxpacket == 0) && + (ep->total_data_len >= ep->maxpacket) && + (ep->total_data_len < ep->ctl_data_len )) + { + + USBD_CtlContinueSendData(pdev , NULL, 0); + ep->ctl_data_len = 0; + + /* Start the transfer */ + DCD_EP_PrepareRx (pdev, + 0, + NULL, + 0); + } + else + { + if((pdev->dev.class_cb->EP0_TxSent != NULL)&& + (pdev->dev.device_status == USB_OTG_CONFIGURED)) + { + pdev->dev.class_cb->EP0_TxSent(pdev); + } + USBD_CtlReceiveStatus(pdev); + } + } + } + if (pdev->dev.test_mode == 1) + { + USBD_RunTestMode(pdev); + pdev->dev.test_mode = 0; + } + } + else if((pdev->dev.class_cb->DataIn != NULL)&& + (pdev->dev.device_status == USB_OTG_CONFIGURED)) + { + pdev->dev.class_cb->DataIn(pdev, epnum); + } + + else + { + /* Do Nothing */ + } + return USBD_OK; +} + + + + +/** +* @brief USBD_RunTestMode +* Launch test mode process +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, SET_TEST_MODE.d32); + return USBD_OK; +} + +/** +* @brief USBD_Reset +* Handle Reset event +* @param pdev: device instance +* @retval status +*/ + +static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev) +{ + /* Open EP0 OUT */ + DCD_EP_Open(pdev, + 0x00, + USB_OTG_MAX_EP0_SIZE, + EP_TYPE_CTRL); + + /* Open EP0 IN */ + DCD_EP_Open(pdev, + 0x80, + USB_OTG_MAX_EP0_SIZE, + EP_TYPE_CTRL); + + /* Upon Reset call usr call back */ + pdev->dev.device_status = USB_OTG_DEFAULT; + pdev->dev.usr_cb->DeviceReset(pdev->cfg.speed); + + return USBD_OK; +} + +/** +* @brief USBD_Resume +* Handle Resume event +* @param pdev: device instance +* @retval status +*/ + +static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev) +{ + /* Upon Resume call usr call back */ + pdev->dev.usr_cb->DeviceResumed(); + pdev->dev.device_status = pdev->dev.device_old_status; + pdev->dev.device_status = USB_OTG_CONFIGURED; + return USBD_OK; +} + + +/** +* @brief USBD_Suspend +* Handle Suspend event +* @param pdev: device instance +* @retval status +*/ + +static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->dev.device_old_status = pdev->dev.device_status; + pdev->dev.device_status = USB_OTG_SUSPENDED; + /* Upon Resume call usr call back */ + pdev->dev.usr_cb->DeviceSuspended(); + return USBD_OK; +} + + +/** +* @brief USBD_SOF +* Handle SOF event +* @param pdev: device instance +* @retval status +*/ + +static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev) +{ + if(pdev->dev.class_cb->SOF) + { + pdev->dev.class_cb->SOF(pdev); + } + return USBD_OK; +} +/** +* @brief USBD_SetCfg +* Configure device and start the interface +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status +*/ + +USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) +{ + pdev->dev.class_cb->Init(pdev, cfgidx); + + /* Upon set config call usr call back */ + pdev->dev.usr_cb->DeviceConfigured(); + return USBD_OK; +} + +/** +* @brief USBD_ClrCfg +* Clear current configuration +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status: USBD_Status +*/ +USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) +{ + pdev->dev.class_cb->DeInit(pdev, cfgidx); + return USBD_OK; +} + +/** +* @brief USBD_IsoINIncomplete +* Handle iso in incomplete event +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->dev.class_cb->IsoINIncomplete(pdev); + return USBD_OK; +} + +/** +* @brief USBD_IsoOUTIncomplete +* Handle iso out incomplete event +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->dev.class_cb->IsoOUTIncomplete(pdev); + return USBD_OK; +} + +#ifdef VBUS_SENSING_ENABLED +/** +* @brief USBD_DevConnected +* Handle device connection event +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->dev.usr_cb->DeviceConnected(); + pdev->dev.connection_status = 1; + return USBD_OK; +} + +/** +* @brief USBD_DevDisconnected +* Handle device disconnection event +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->dev.usr_cb->DeviceDisconnected(); + pdev->dev.class_cb->DeInit(pdev, 0); + pdev->dev.connection_status = 0; + return USBD_OK; +} +#endif +/** +* @} +*/ + + +/** +* @} +*/ + + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c index 8feb4f198..bbca7c7d3 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c @@ -1,244 +1,244 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides the IO requests APIs for control endpoints. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_IOREQ - * @brief control I/O requests module - * @{ - */ - -/** @defgroup USBD_IOREQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Functions - * @{ - */ - -/** -* @brief USBD_CtlSendData -* send data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, - const uint8_t *pbuf, - uint16_t len) // modified by OpenTX -{ - USBD_Status ret = USBD_OK; - - pdev->dev.in_ep[0].total_data_len = len; - pdev->dev.in_ep[0].rem_data_len = len; - pdev->dev.device_state = USB_OTG_EP0_DATA_IN; - - DCD_EP_Tx (pdev, 0, pbuf, len); - - return ret; -} - -/** -* @brief USBD_CtlContinueSendData -* continue sending data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - DCD_EP_Tx (pdev, 0, pbuf, len); - - - return ret; -} - -/** -* @brief USBD_CtlPrepareRx -* receive data on the ctl pipe -* @param pdev: USB OTG device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - pdev->dev.out_ep[0].total_data_len = len; - pdev->dev.out_ep[0].rem_data_len = len; - pdev->dev.device_state = USB_OTG_EP0_DATA_OUT; - - DCD_EP_PrepareRx (pdev, - 0, - pbuf, - len); - - - return ret; -} - -/** -* @brief USBD_CtlContinueRx -* continue receive data on the ctl pipe -* @param pdev: USB OTG device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - DCD_EP_PrepareRx (pdev, - 0, - pbuf, - len); - return ret; -} -/** -* @brief USBD_CtlSendStatus -* send zero length packet on the ctl pipe -* @param pdev: USB OTG device instance -* @retval status -*/ -USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev) -{ - USBD_Status ret = USBD_OK; - pdev->dev.device_state = USB_OTG_EP0_STATUS_IN; - DCD_EP_Tx (pdev, - 0, - NULL, - 0); - - USB_OTG_EP0_OutStart(pdev); - - return ret; -} - -/** -* @brief USBD_CtlReceiveStatus -* receive zero length packet on the ctl pipe -* @param pdev: USB OTG device instance -* @retval status -*/ -USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev) -{ - USBD_Status ret = USBD_OK; - pdev->dev.device_state = USB_OTG_EP0_STATUS_OUT; - DCD_EP_PrepareRx ( pdev, - 0, - NULL, - 0); - - USB_OTG_EP0_OutStart(pdev); - - return ret; -} - - -/** -* @brief USBD_GetRxCount -* returns the received data length -* @param pdev: USB OTG device instance -* epnum: endpoint index -* @retval Rx Data blength -*/ -uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - return pdev->dev.out_ep[epnum].xfer_count; -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_ioreq.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides the IO requests APIs for control endpoints. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_IOREQ + * @brief control I/O requests module + * @{ + */ + +/** @defgroup USBD_IOREQ_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Functions + * @{ + */ + +/** +* @brief USBD_CtlSendData +* send data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, + const uint8_t *pbuf, + uint16_t len) // modified by OpenTX +{ + USBD_Status ret = USBD_OK; + + pdev->dev.in_ep[0].total_data_len = len; + pdev->dev.in_ep[0].rem_data_len = len; + pdev->dev.device_state = USB_OTG_EP0_DATA_IN; + + DCD_EP_Tx (pdev, 0, pbuf, len); + + return ret; +} + +/** +* @brief USBD_CtlContinueSendData +* continue sending data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len) +{ + USBD_Status ret = USBD_OK; + + DCD_EP_Tx (pdev, 0, pbuf, len); + + + return ret; +} + +/** +* @brief USBD_CtlPrepareRx +* receive data on the ctl pipe +* @param pdev: USB OTG device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len) +{ + USBD_Status ret = USBD_OK; + + pdev->dev.out_ep[0].total_data_len = len; + pdev->dev.out_ep[0].rem_data_len = len; + pdev->dev.device_state = USB_OTG_EP0_DATA_OUT; + + DCD_EP_PrepareRx (pdev, + 0, + pbuf, + len); + + + return ret; +} + +/** +* @brief USBD_CtlContinueRx +* continue receive data on the ctl pipe +* @param pdev: USB OTG device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len) +{ + USBD_Status ret = USBD_OK; + + DCD_EP_PrepareRx (pdev, + 0, + pbuf, + len); + return ret; +} +/** +* @brief USBD_CtlSendStatus +* send zero length packet on the ctl pipe +* @param pdev: USB OTG device instance +* @retval status +*/ +USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev) +{ + USBD_Status ret = USBD_OK; + pdev->dev.device_state = USB_OTG_EP0_STATUS_IN; + DCD_EP_Tx (pdev, + 0, + NULL, + 0); + + USB_OTG_EP0_OutStart(pdev); + + return ret; +} + +/** +* @brief USBD_CtlReceiveStatus +* receive zero length packet on the ctl pipe +* @param pdev: USB OTG device instance +* @retval status +*/ +USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev) +{ + USBD_Status ret = USBD_OK; + pdev->dev.device_state = USB_OTG_EP0_STATUS_OUT; + DCD_EP_PrepareRx ( pdev, + 0, + NULL, + 0); + + USB_OTG_EP0_OutStart(pdev); + + return ret; +} + + +/** +* @brief USBD_GetRxCount +* returns the received data length +* @param pdev: USB OTG device instance +* epnum: endpoint index +* @retval Rx Data blength +*/ +uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) +{ + return pdev->dev.out_ep[epnum].xfer_count; +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c index 296afc818..2e11c4400 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c @@ -1,880 +1,880 @@ -/** - ****************************************************************************** - * @file usbd_req.c - * @author MCD Application Team - * @version V1.2.0 - * @date 09-November-2015 - * @brief This file provides the standard USB requests following chapter 9. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_req.h" -#include "usbd_ioreq.h" -#include "usbd_desc.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_REQ - * @brief USB standard requests module - * @{ - */ - -/** @defgroup USBD_REQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Variables - * @{ - */ -extern __IO USB_OTG_DCTL_TypeDef SET_TEST_MODE; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint32_t USBD_ep_status __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN const uint32_t USBD_default_cfg __ALIGN_END = 0; // modified by OpenTX - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint32_t USBD_cfg_status __ALIGN_END = 0; - -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_FunctionPrototypes - * @{ - */ -static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static uint8_t USBD_GetLen(uint8_t *buf); -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Functions - * @{ - */ - - -/** -* @brief USBD_StdDevReq -* Handle standard usb device requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - USBD_Status ret = USBD_OK; - - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - - USBD_GetDescriptor (pdev, req) ; - break; - - case USB_REQ_SET_ADDRESS: - USBD_SetAddress(pdev, req); - break; - - case USB_REQ_SET_CONFIGURATION: - USBD_SetConfig (pdev , req); - break; - - case USB_REQ_GET_CONFIGURATION: - USBD_GetConfig (pdev , req); - break; - - case USB_REQ_GET_STATUS: - USBD_GetStatus (pdev , req); - break; - - - case USB_REQ_SET_FEATURE: - USBD_SetFeature (pdev , req); - break; - - case USB_REQ_CLEAR_FEATURE: - USBD_ClrFeature (pdev , req); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - - return ret; -} - -/** -* @brief USBD_StdItfReq -* Handle standard usb interface requests -* @param pdev: USB OTG device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - USBD_Status ret = USBD_OK; - - switch (pdev->dev.device_status) - { - case USB_OTG_CONFIGURED: - - if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) - { - pdev->dev.class_cb->Setup (pdev, req); - - if((req->wLength == 0)&& (ret == USBD_OK)) - { - USBD_CtlSendStatus(pdev); - } - } - else - { - USBD_CtlError(pdev , req); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - return ret; -} - -/** -* @brief USBD_StdEPReq -* Handle standard usb endpoint requests -* @param pdev: USB OTG device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - - uint8_t ep_addr; - USBD_Status ret = USBD_OK; - - ep_addr = LOBYTE(req->wIndex); - - /* Check the class specific requests before going to standard request */ - if ((req->bmRequest & USB_REQ_TYPE_MASK) == USB_REQ_TYPE_CLASS) - { - pdev->dev.class_cb->Setup (pdev, req); - return ret; - } - - switch (req->bRequest) - { - case USB_REQ_SET_FEATURE : - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - - } - } - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_CLEAR_FEATURE : - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_ClrStall(pdev , ep_addr); - pdev->dev.class_cb->Setup (pdev, req); - } - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_GET_STATUS: - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - - - if ((ep_addr & 0x80)== 0x80) - { - if(pdev->dev.in_ep[ep_addr & 0x7F].is_stall) - { - USBD_ep_status = 0x0001; - } - else - { - USBD_ep_status = 0x0000; - } - } - else if ((ep_addr & 0x80)== 0x00) - { - if(pdev->dev.out_ep[ep_addr].is_stall) - { - USBD_ep_status = 0x0001; - } - - else - { - USBD_ep_status = 0x0000; - } - } - - else - { - /* Do Nothing */ - } - - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_ep_status, - 2); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - default: - break; - } - return ret; -} -/** -* @brief USBD_GetDescriptor -* Handle Get Descriptor requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len; - uint8_t *pbuf; - len = req->wLength ; - - switch (req->wValue >> 8) - { -#if (USBD_LPM_ENABLED == 1) - case USB_DESC_TYPE_BOS: - pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); - break; -#endif - case USB_DESC_TYPE_DEVICE: - pbuf = pdev->dev.usr_device->GetDeviceDescriptor(pdev->cfg.speed, &len); - break; - - case USB_DESC_TYPE_CONFIGURATION: - pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); -#ifdef USB_OTG_HS_CORE - if((pdev->cfg.speed == USB_OTG_SPEED_FULL )&& - (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)) - { - pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); - } -#endif - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - pdev->dev.pConfig_descriptor = pbuf; - break; - - case USB_DESC_TYPE_STRING: - switch ((uint8_t)(req->wValue)) - { - case USBD_IDX_LANGID_STR: - pbuf = pdev->dev.usr_device->GetLangIDStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_MFC_STR: - pbuf = pdev->dev.usr_device->GetManufacturerStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_PRODUCT_STR: - pbuf = pdev->dev.usr_device->GetProductStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_SERIAL_STR: - pbuf = pdev->dev.usr_device->GetSerialStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_CONFIG_STR: - pbuf = pdev->dev.usr_device->GetConfigurationStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_INTERFACE_STR: - pbuf = pdev->dev.usr_device->GetInterfaceStrDescriptor(pdev->cfg.speed, &len); - break; - - default: -#ifdef USB_SUPPORT_USER_STRING_DESC - pbuf = pdev->dev.class_cb->GetUsrStrDescriptor(pdev->cfg.speed, (req->wValue) , &len); - break; -#else - USBD_CtlError(pdev , req); - return; -#endif /* USBD_CtlError(pdev , req)*/ - } - break; - case USB_DESC_TYPE_DEVICE_QUALIFIER: -#ifdef USB_OTG_HS_CORE - if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) - { - - pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); - - USBD_DeviceQualifierDesc[4]= pbuf[14]; - USBD_DeviceQualifierDesc[5]= pbuf[15]; - USBD_DeviceQualifierDesc[6]= pbuf[16]; - - pbuf = USBD_DeviceQualifierDesc; - len = USB_LEN_DEV_QUALIFIER_DESC; - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } -#else - USBD_CtlError(pdev , req); - return; -#endif - - case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: -#ifdef USB_OTG_HS_CORE - - if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); - pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } -#else - USBD_CtlError(pdev , req); - return; -#endif - default: - USBD_CtlError(pdev , req); - return; - } - - if((len != 0)&& (req->wLength != 0)) - { - - len = MIN(len , req->wLength); - - USBD_CtlSendData (pdev, - pbuf, - len); - } - -} - -/** -* @brief USBD_SetAddress -* Set device address -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - uint8_t dev_addr; - - if ((req->wIndex == 0) && (req->wLength == 0)) - { - dev_addr = (uint8_t)(req->wValue) & 0x7F; - - if (pdev->dev.device_status == USB_OTG_CONFIGURED) - { - USBD_CtlError(pdev , req); - } - else - { - pdev->dev.device_address = dev_addr; - DCD_EP_SetAddress(pdev, dev_addr); - USBD_CtlSendStatus(pdev); - - if (dev_addr != 0) - { - pdev->dev.device_status = USB_OTG_ADDRESSED; - } - else - { - pdev->dev.device_status = USB_OTG_DEFAULT; - } - } - } - else - { - USBD_CtlError(pdev , req); - } -} - -/** -* @brief USBD_SetConfig -* Handle Set device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_CFG_MAX_NUM ) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if (cfgidx) - { - pdev->dev.device_config = cfgidx; - pdev->dev.device_status = USB_OTG_CONFIGURED; - USBD_SetCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - case USB_OTG_CONFIGURED: - if (cfgidx == 0) - { - pdev->dev.device_status = USB_OTG_ADDRESSED; - pdev->dev.device_config = cfgidx; - USBD_ClrCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - - } - else if (cfgidx != pdev->dev.device_config) - { - /* Clear old configuration */ - USBD_ClrCfg(pdev , pdev->dev.device_config); - - /* set new configuration */ - pdev->dev.device_config = cfgidx; - USBD_SetCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetConfig -* Handle Get device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - if (req->wLength != 1) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev.device_status ) - { - case USB_OTG_ADDRESSED: - - USBD_CtlSendData (pdev, - (const uint8_t *)&USBD_default_cfg, - 1); // modified by OpenTX - break; - - case USB_OTG_CONFIGURED: - - USBD_CtlSendData (pdev, - &pdev->dev.device_config, - 1); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetStatus -* Handle Get Status request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - case USB_OTG_CONFIGURED: - -#ifdef USBD_SELF_POWERED - USBD_cfg_status = USB_CONFIG_SELF_POWERED; -#else - USBD_cfg_status = 0x00; -#endif - - if (pdev->dev.DevRemoteWakeup) - { - USBD_cfg_status |= USB_CONFIG_REMOTE_WAKEUP; - } - - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_cfg_status, - 2); - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - - -/** -* @brief USBD_SetFeature -* Handle Set device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - USB_OTG_DCTL_TypeDef dctl; - uint8_t test_mode = 0; - - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev.DevRemoteWakeup = 1; - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - - else if ((req->wValue == USB_FEATURE_TEST_MODE) && - ((req->wIndex & 0xFF) == 0)) - { - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - - test_mode = req->wIndex >> 8; - switch (test_mode) - { - case 1: /* TEST_J */ - dctl.b.tstctl = 1; - break; - - case 2: /* TEST_K */ - dctl.b.tstctl = 2; - break; - - case 3: /* TEST_SE0_NAK */ - dctl.b.tstctl = 3; - break; - - case 4: /* TEST_PACKET */ - dctl.b.tstctl = 4; - break; - - case 5: /* TEST_FORCE_ENABLE */ - dctl.b.tstctl = 5; - break; - - default : - dctl.b.tstctl = 1; - break; - } - SET_TEST_MODE = dctl; - pdev->dev.test_mode = 1; - USBD_CtlSendStatus(pdev); - } - else - { - /* Do Nothing */ - } -} - - -/** -* @brief USBD_ClrFeature -* Handle clear device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev.DevRemoteWakeup = 0; - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - -/** -* @brief USBD_ParseSetupRequest -* Copy buffer into setup structure -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - req->bmRequest = *(uint8_t *) (pdev->dev.setup_packet); - req->bRequest = *(uint8_t *) (pdev->dev.setup_packet + 1); - req->wValue = SWAPBYTE (pdev->dev.setup_packet + 2); - req->wIndex = SWAPBYTE (pdev->dev.setup_packet + 4); - req->wLength = SWAPBYTE (pdev->dev.setup_packet + 6); - - pdev->dev.in_ep[0].ctl_data_len = req->wLength ; - pdev->dev.device_state = USB_OTG_EP0_SETUP; -} - -/** -* @brief USBD_CtlError -* Handle USB low level Error -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - DCD_EP_Stall(pdev , 0x80); - DCD_EP_Stall(pdev , 0); - USB_OTG_EP0_OutStart(pdev); -} - - -/** - * @brief USBD_GetString - * Convert Ascii string into unicode one - * @param desc : descriptor buffer - * @param unicode : Formatted string buffer (unicode) - * @param len : descriptor length - * @retval None - */ -void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) -{ - uint8_t idx = 0; - - if (desc != NULL) - { - *len = USBD_GetLen(desc) * 2 + 2; - unicode[idx++] = *len; - unicode[idx++] = USB_DESC_TYPE_STRING; - - while (*desc != NULL) - { - unicode[idx++] = *desc++; - unicode[idx++] = 0x00; - } - } -} - -/** - * @brief USBD_GetLen - * return the string length - * @param buf : pointer to the ascii string buffer - * @retval string length - */ -static uint8_t USBD_GetLen(uint8_t *buf) -{ - uint8_t len = 0; - - while (*buf != NULL) - { - len++; - buf++; - } - - return len; -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_req.c + * @author MCD Application Team + * @version V1.2.0 + * @date 09-November-2015 + * @brief This file provides the standard USB requests following chapter 9. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_req.h" +#include "usbd_ioreq.h" +#include "usbd_desc.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_REQ + * @brief USB standard requests module + * @{ + */ + +/** @defgroup USBD_REQ_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Variables + * @{ + */ +extern __IO USB_OTG_DCTL_TypeDef SET_TEST_MODE; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint32_t USBD_ep_status __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN const uint32_t USBD_default_cfg __ALIGN_END = 0; // modified by OpenTX + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint32_t USBD_cfg_status __ALIGN_END = 0; + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_FunctionPrototypes + * @{ + */ +static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static uint8_t USBD_GetLen(uint8_t *buf); +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Functions + * @{ + */ + + +/** +* @brief USBD_StdDevReq +* Handle standard usb device requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) +{ + USBD_Status ret = USBD_OK; + + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + + USBD_GetDescriptor (pdev, req) ; + break; + + case USB_REQ_SET_ADDRESS: + USBD_SetAddress(pdev, req); + break; + + case USB_REQ_SET_CONFIGURATION: + USBD_SetConfig (pdev , req); + break; + + case USB_REQ_GET_CONFIGURATION: + USBD_GetConfig (pdev , req); + break; + + case USB_REQ_GET_STATUS: + USBD_GetStatus (pdev , req); + break; + + + case USB_REQ_SET_FEATURE: + USBD_SetFeature (pdev , req); + break; + + case USB_REQ_CLEAR_FEATURE: + USBD_ClrFeature (pdev , req); + break; + + default: + USBD_CtlError(pdev , req); + break; + } + + return ret; +} + +/** +* @brief USBD_StdItfReq +* Handle standard usb interface requests +* @param pdev: USB OTG device instance +* @param req: usb request +* @retval status +*/ +USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) +{ + USBD_Status ret = USBD_OK; + + switch (pdev->dev.device_status) + { + case USB_OTG_CONFIGURED: + + if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) + { + pdev->dev.class_cb->Setup (pdev, req); + + if((req->wLength == 0)&& (ret == USBD_OK)) + { + USBD_CtlSendStatus(pdev); + } + } + else + { + USBD_CtlError(pdev , req); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + return ret; +} + +/** +* @brief USBD_StdEPReq +* Handle standard usb endpoint requests +* @param pdev: USB OTG device instance +* @param req: usb request +* @retval status +*/ +USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) +{ + + uint8_t ep_addr; + USBD_Status ret = USBD_OK; + + ep_addr = LOBYTE(req->wIndex); + + /* Check the class specific requests before going to standard request */ + if ((req->bmRequest & USB_REQ_TYPE_MASK) == USB_REQ_TYPE_CLASS) + { + pdev->dev.class_cb->Setup (pdev, req); + return ret; + } + + switch (req->bRequest) + { + case USB_REQ_SET_FEATURE : + + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + DCD_EP_Stall(pdev , ep_addr); + } + break; + + case USB_OTG_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + DCD_EP_Stall(pdev , ep_addr); + + } + } + pdev->dev.class_cb->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + case USB_REQ_CLEAR_FEATURE : + + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + DCD_EP_Stall(pdev , ep_addr); + } + break; + + case USB_OTG_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + DCD_EP_ClrStall(pdev , ep_addr); + pdev->dev.class_cb->Setup (pdev, req); + } + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + case USB_REQ_GET_STATUS: + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + DCD_EP_Stall(pdev , ep_addr); + } + break; + + case USB_OTG_CONFIGURED: + + + if ((ep_addr & 0x80)== 0x80) + { + if(pdev->dev.in_ep[ep_addr & 0x7F].is_stall) + { + USBD_ep_status = 0x0001; + } + else + { + USBD_ep_status = 0x0000; + } + } + else if ((ep_addr & 0x80)== 0x00) + { + if(pdev->dev.out_ep[ep_addr].is_stall) + { + USBD_ep_status = 0x0001; + } + + else + { + USBD_ep_status = 0x0000; + } + } + + else + { + /* Do Nothing */ + } + + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_ep_status, + 2); + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + default: + break; + } + return ret; +} +/** +* @brief USBD_GetDescriptor +* Handle Get Descriptor requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + uint16_t len; + uint8_t *pbuf; + len = req->wLength ; + + switch (req->wValue >> 8) + { +#if (USBD_LPM_ENABLED == 1) + case USB_DESC_TYPE_BOS: + pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); + break; +#endif + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->dev.usr_device->GetDeviceDescriptor(pdev->cfg.speed, &len); + break; + + case USB_DESC_TYPE_CONFIGURATION: + pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); +#ifdef USB_OTG_HS_CORE + if((pdev->cfg.speed == USB_OTG_SPEED_FULL )&& + (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)) + { + pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); + } +#endif + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + pdev->dev.pConfig_descriptor = pbuf; + break; + + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) + { + case USBD_IDX_LANGID_STR: + pbuf = pdev->dev.usr_device->GetLangIDStrDescriptor(pdev->cfg.speed, &len); + break; + + case USBD_IDX_MFC_STR: + pbuf = pdev->dev.usr_device->GetManufacturerStrDescriptor(pdev->cfg.speed, &len); + break; + + case USBD_IDX_PRODUCT_STR: + pbuf = pdev->dev.usr_device->GetProductStrDescriptor(pdev->cfg.speed, &len); + break; + + case USBD_IDX_SERIAL_STR: + pbuf = pdev->dev.usr_device->GetSerialStrDescriptor(pdev->cfg.speed, &len); + break; + + case USBD_IDX_CONFIG_STR: + pbuf = pdev->dev.usr_device->GetConfigurationStrDescriptor(pdev->cfg.speed, &len); + break; + + case USBD_IDX_INTERFACE_STR: + pbuf = pdev->dev.usr_device->GetInterfaceStrDescriptor(pdev->cfg.speed, &len); + break; + + default: +#ifdef USB_SUPPORT_USER_STRING_DESC + pbuf = pdev->dev.class_cb->GetUsrStrDescriptor(pdev->cfg.speed, (req->wValue) , &len); + break; +#else + USBD_CtlError(pdev , req); + return; +#endif /* USBD_CtlError(pdev , req)*/ + } + break; + case USB_DESC_TYPE_DEVICE_QUALIFIER: +#ifdef USB_OTG_HS_CORE + if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) + { + + pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); + + USBD_DeviceQualifierDesc[4]= pbuf[14]; + USBD_DeviceQualifierDesc[5]= pbuf[15]; + USBD_DeviceQualifierDesc[6]= pbuf[16]; + + pbuf = USBD_DeviceQualifierDesc; + len = USB_LEN_DEV_QUALIFIER_DESC; + break; + } + else + { + USBD_CtlError(pdev , req); + return; + } +#else + USBD_CtlError(pdev , req); + return; +#endif + + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: +#ifdef USB_OTG_HS_CORE + + if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) + { + pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + break; + } + else + { + USBD_CtlError(pdev , req); + return; + } +#else + USBD_CtlError(pdev , req); + return; +#endif + default: + USBD_CtlError(pdev , req); + return; + } + + if((len != 0)&& (req->wLength != 0)) + { + + len = MIN(len , req->wLength); + + USBD_CtlSendData (pdev, + pbuf, + len); + } + +} + +/** +* @brief USBD_SetAddress +* Set device address +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + uint8_t dev_addr; + + if ((req->wIndex == 0) && (req->wLength == 0)) + { + dev_addr = (uint8_t)(req->wValue) & 0x7F; + + if (pdev->dev.device_status == USB_OTG_CONFIGURED) + { + USBD_CtlError(pdev , req); + } + else + { + pdev->dev.device_address = dev_addr; + DCD_EP_SetAddress(pdev, dev_addr); + USBD_CtlSendStatus(pdev); + + if (dev_addr != 0) + { + pdev->dev.device_status = USB_OTG_ADDRESSED; + } + else + { + pdev->dev.device_status = USB_OTG_DEFAULT; + } + } + } + else + { + USBD_CtlError(pdev , req); + } +} + +/** +* @brief USBD_SetConfig +* Handle Set device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + + if (cfgidx > USBD_CFG_MAX_NUM ) + { + USBD_CtlError(pdev , req); + } + else + { + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + if (cfgidx) + { + pdev->dev.device_config = cfgidx; + pdev->dev.device_status = USB_OTG_CONFIGURED; + USBD_SetCfg(pdev , cfgidx); + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + case USB_OTG_CONFIGURED: + if (cfgidx == 0) + { + pdev->dev.device_status = USB_OTG_ADDRESSED; + pdev->dev.device_config = cfgidx; + USBD_ClrCfg(pdev , cfgidx); + USBD_CtlSendStatus(pdev); + + } + else if (cfgidx != pdev->dev.device_config) + { + /* Clear old configuration */ + USBD_ClrCfg(pdev , pdev->dev.device_config); + + /* set new configuration */ + pdev->dev.device_config = cfgidx; + USBD_SetCfg(pdev , cfgidx); + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + } +} + +/** +* @brief USBD_GetConfig +* Handle Get device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + + if (req->wLength != 1) + { + USBD_CtlError(pdev , req); + } + else + { + switch (pdev->dev.device_status ) + { + case USB_OTG_ADDRESSED: + + USBD_CtlSendData (pdev, + (const uint8_t *)&USBD_default_cfg, + 1); // modified by OpenTX + break; + + case USB_OTG_CONFIGURED: + + USBD_CtlSendData (pdev, + &pdev->dev.device_config, + 1); + break; + + default: + USBD_CtlError(pdev , req); + break; + } + } +} + +/** +* @brief USBD_GetStatus +* Handle Get Status request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + + + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + case USB_OTG_CONFIGURED: + +#ifdef USBD_SELF_POWERED + USBD_cfg_status = USB_CONFIG_SELF_POWERED; +#else + USBD_cfg_status = 0x00; +#endif + + if (pdev->dev.DevRemoteWakeup) + { + USBD_cfg_status |= USB_CONFIG_REMOTE_WAKEUP; + } + + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_cfg_status, + 2); + break; + + default : + USBD_CtlError(pdev , req); + break; + } +} + + +/** +* @brief USBD_SetFeature +* Handle Set device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + + USB_OTG_DCTL_TypeDef dctl; + uint8_t test_mode = 0; + + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + pdev->dev.DevRemoteWakeup = 1; + pdev->dev.class_cb->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + } + + else if ((req->wValue == USB_FEATURE_TEST_MODE) && + ((req->wIndex & 0xFF) == 0)) + { + dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); + + test_mode = req->wIndex >> 8; + switch (test_mode) + { + case 1: /* TEST_J */ + dctl.b.tstctl = 1; + break; + + case 2: /* TEST_K */ + dctl.b.tstctl = 2; + break; + + case 3: /* TEST_SE0_NAK */ + dctl.b.tstctl = 3; + break; + + case 4: /* TEST_PACKET */ + dctl.b.tstctl = 4; + break; + + case 5: /* TEST_FORCE_ENABLE */ + dctl.b.tstctl = 5; + break; + + default : + dctl.b.tstctl = 1; + break; + } + SET_TEST_MODE = dctl; + pdev->dev.test_mode = 1; + USBD_CtlSendStatus(pdev); + } + else + { + /* Do Nothing */ + } +} + + +/** +* @brief USBD_ClrFeature +* Handle clear device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + case USB_OTG_CONFIGURED: + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + pdev->dev.DevRemoteWakeup = 0; + pdev->dev.class_cb->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + } + break; + + default : + USBD_CtlError(pdev , req); + break; + } +} + +/** +* @brief USBD_ParseSetupRequest +* Copy buffer into setup structure +* @param pdev: device instance +* @param req: usb request +* @retval None +*/ + +void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + req->bmRequest = *(uint8_t *) (pdev->dev.setup_packet); + req->bRequest = *(uint8_t *) (pdev->dev.setup_packet + 1); + req->wValue = SWAPBYTE (pdev->dev.setup_packet + 2); + req->wIndex = SWAPBYTE (pdev->dev.setup_packet + 4); + req->wLength = SWAPBYTE (pdev->dev.setup_packet + 6); + + pdev->dev.in_ep[0].ctl_data_len = req->wLength ; + pdev->dev.device_state = USB_OTG_EP0_SETUP; +} + +/** +* @brief USBD_CtlError +* Handle USB low level Error +* @param pdev: device instance +* @param req: usb request +* @retval None +*/ + +void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + + DCD_EP_Stall(pdev , 0x80); + DCD_EP_Stall(pdev , 0); + USB_OTG_EP0_OutStart(pdev); +} + + +/** + * @brief USBD_GetString + * Convert Ascii string into unicode one + * @param desc : descriptor buffer + * @param unicode : Formatted string buffer (unicode) + * @param len : descriptor length + * @retval None + */ +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) +{ + uint8_t idx = 0; + + if (desc != NULL) + { + *len = USBD_GetLen(desc) * 2 + 2; + unicode[idx++] = *len; + unicode[idx++] = USB_DESC_TYPE_STRING; + + while (*desc != NULL) + { + unicode[idx++] = *desc++; + unicode[idx++] = 0x00; + } + } +} + +/** + * @brief USBD_GetLen + * return the string length + * @param buf : pointer to the ascii string buffer + * @retval string length + */ +static uint8_t USBD_GetLen(uint8_t *buf) +{ + uint8_t len = 0; + + while (*buf != NULL) + { + len++; + buf++; + } + + return len; +} +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Release_Notes.html b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Release_Notes.html index 9c70d65f0..1e20bce54 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Release_Notes.html +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_Device_Library/Release_Notes.html @@ -1,971 +1,971 @@ - - - - - -Release Notes for STM32F105/7xx, STM32F2xx and STM32F4xx USB Device Library - - - - - - - - -
- -

 

- -
- - - - - -
- - - - - - - -
-

Back to Release page

-
-

Release Notes for STM32F105/7xx, STM32F2xx and STM32F4xx USB Device Library

-

Copyright - 2015 STMicroelectronics

-

-
-

 

- - - - -
- - -

Update History

V1.2.0 / 09-November-2015

Main -Changes

- - - - - - - - - - - - - - - - - -
  • Add composite class
    • -
  • Core Driver
    • -
    • usbd_core.c: -Fix bug of unsupported premature Host Out stage during data In stage -(ie. when endpoint 0 maximum data size is 8 and Host requests -GetDeviceDescriptor for the first time)
    • usbd_req.c: 
      • Fix bug of unsupported Endpoint Class requests (ie. Audio SetCurrent request for endpoint sampling rate setting)
      • Initialize the len variable before the switch case in USBD_GetDescriptor function
  • HID Class
    • Add Polling time API USBD_HID_GetPollingInterval() to query this period for HS and FS
  • CDC Class
    • usbd_cdc.core.c: 
      • Fix bug for not handling the ZLP (zero length packet). A new state to handle the ZLP case are added
      • Remove USB_REQ_GET_DESCRIPTOR case Handling from CDC-specific SETUP requests
      • Call USBD_CtlSendData() inside the if block in the  USB_REQ_GET_DESCRIPTOR case
  • MSC Class
    • usbd_msc_scsi.c: 
      • Define values for SCSI_blk_addr, SCSI_blk_len variables.

V1.1.0 / 19-March-2012

-

Main -Changes

- -
  • Official support of STM32F4xx devices
  • All source files: license disclaimer text update and add link to the License file on ST Internet.
  • Handle test mode in the set feature request
  • Handle dynamically the USB SELF POWERED feature
  • Handle correctly the USBD_CtlError process to take into account error during Control OUT stage
  • Miscellaneous bug fix

V1.0.0 / 22-July-2011

Main -Changes

-
  • First official version for STM32F105/7xx and STM32F2xx devices

-

License

-

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless -required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See -the License for the specific language governing permissions and -limitations under the License. -
-
-
-

For - complete documentation on STM32 - Microcontrollers visit www.st.com/STM32

-
-

-
- -
- -

 

- -
- + + + + + +Release Notes for STM32F105/7xx, STM32F2xx and STM32F4xx USB Device Library + + + + + + + + +
+ +

 

+ +
+ + + + + +
+ + + + + + + +
+

Back to Release page

+
+

Release Notes for STM32F105/7xx, STM32F2xx and STM32F4xx USB Device Library

+

Copyright + 2015 STMicroelectronics

+

+
+

 

+ + + + +
+ + +

Update History

V1.2.0 / 09-November-2015

Main +Changes

+ + + + + + + + + + + + + + + + + +
  • Add composite class
    • +
  • Core Driver
    • +
    • usbd_core.c: +Fix bug of unsupported premature Host Out stage during data In stage +(ie. when endpoint 0 maximum data size is 8 and Host requests +GetDeviceDescriptor for the first time)
    • usbd_req.c: 
      • Fix bug of unsupported Endpoint Class requests (ie. Audio SetCurrent request for endpoint sampling rate setting)
      • Initialize the len variable before the switch case in USBD_GetDescriptor function
  • HID Class
    • Add Polling time API USBD_HID_GetPollingInterval() to query this period for HS and FS
  • CDC Class
    • usbd_cdc.core.c: 
      • Fix bug for not handling the ZLP (zero length packet). A new state to handle the ZLP case are added
      • Remove USB_REQ_GET_DESCRIPTOR case Handling from CDC-specific SETUP requests
      • Call USBD_CtlSendData() inside the if block in the  USB_REQ_GET_DESCRIPTOR case
  • MSC Class
    • usbd_msc_scsi.c: 
      • Define values for SCSI_blk_addr, SCSI_blk_len variables.

V1.1.0 / 19-March-2012

+

Main +Changes

+ +
  • Official support of STM32F4xx devices
  • All source files: license disclaimer text update and add link to the License file on ST Internet.
  • Handle test mode in the set feature request
  • Handle dynamically the USB SELF POWERED feature
  • Handle correctly the USBD_CtlError process to take into account error during Control OUT stage
  • Miscellaneous bug fix

V1.0.0 / 22-July-2011

Main +Changes

+
  • First official version for STM32F105/7xx and STM32F2xx devices

+

License

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License. +
+
+
+

For + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32

+
+

+
+ +
+ +

 

+ +
+ \ No newline at end of file diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/Release_Notes.html b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/Release_Notes.html index 4aa1e5aa9..2edf8d383 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/Release_Notes.html +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/Release_Notes.html @@ -1,952 +1,952 @@ - - - - -Release Notes for STM32F105/7xx, STM32F2xx and STM32F4xx USB OTG Driver - - - - - - - - -
- -

 

- -
- - - - - -
- - - - - - - -
-

Back to Release page

-
-

Release Notes for STM32F105/7xx, STM32F2xx and STM32F4xx USB OTG Driver

-

Copyright - 2015 STMicroelectronics

-

-
-

 

- - - - -
-

Update History

V2.2.0 / 09-November-2015

Main -Changes

- -
    -
  • Add support of  STM32F469/479xx and  STM32F446 devices
    • -
  • usb_dcd_int.c
    • Bug -Fix: Masking the TxFIFOempty interrupt of the endpoint after -finishing writing data packet to TxFIFO in DCD_WriteEmptyTxFifo function
    • Bug Fix: The USB TRD (Turnaround) is configured depending on AHB frequency used by application.
    • Bug Fix: Handle multi-packet for OUT transfer with DMA in HS mode
    • Remove CLEAR_IN_EP_INTR(epnum, emptyintr) in USBD_OTG_EP1IN_ISR_Handler and DCD_HandleInEP_ISR
    • Correct PCFCCTL register access
  • usb_core.c
    • USB_OTG_HC_Halt function: Modify Channel halt function to disable the channel at the end
    • Correct PCFCCTL register access
    • Bug Fix: Handle multi-packet for OUT transfer with DMA in HS mode
    • Bug Fix: Keep the disconnect interrupt maskedIn function  USB_OTG_EnableHostInt for correct handling of connection/disconnection
    • In function USB_OTG_ResetPort change reset time to 100ms instead of 10ms for better stability during enumeration
  • usb_hcd.c
    •  Add function HCD_IsPortEnabled to check portenabled for correct handling of connection/disconnection
  • usb_hcd_int.c 
    • Remove USB_OTG_ResetPort(pdev) calling 
    • Update USB_OTG_USBH_handle_port_ISR for correct handling of connection/disconnection
    • Disconnect interrupt is unmasked after a connection
    • Creation of PortEnabled event (need to wait for this event before starting enumerating device)
    • Halt channel and restart transfer is removed When using DMA (HS) In case of NAK or NYET in USB_OTG_USBH_handle_hc_n_Out_ISR and USB_OTG_USBH_handle_hc_n_In_ISR
    • Clearing the NAK interrupt flag before re-enabling the channel for a new transfer in USB_OTG_USBH_handle_hc_n_In_ISR function

V2.1.0 / 19-March-2012

-

Main -Changes

- -
  • Official support of STM32F4xx devices
  • All source files: license disclaimer text update and add link to the License file on ST Internet
  • Unmask Session request interrupt to handle the connect event during the core start-up
  • Remove any reference to the USB HS external I2C PHY
  • Update optimization pragma for AR Compiler
  • Handle Correctly the Low Speed device connection in HS mode
  • Add a wrapper to isolate the library from the low level driver: connection done through ISR structure
  • Miscellaneous bug fix

V2.0.0 / 22-July-2011

Main -Changes

-
  • Second official version supporting STM32F105/7 and STM32F2xx devices
  • Rename the Library from "STM32_USB_HOST_Driver" to "STM32_USB_OTG_Driver"
  • Add support for STM32F2xx devices
  • Add support for Device and OTG modes
  • Change HCD layer to support High speed core
  • Change the Low level driver to support multi core support for Host mode
  • Add Stop mechanism for Host and Device modes
  • Change VBUS enabling method, to use the external or the internal VBUS when using the ULPI

V1.0.0 - 11/29/2010

-
  • Created 

License

-

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless -required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See -the License for the specific language governing permissions and -limitations under the License. -
-
-
-

For - complete documentation on STM32 - Microcontrollers visit www.st.com/STM32

-
-

-
- -
- -

 

- -
- + + + + +Release Notes for STM32F105/7xx, STM32F2xx and STM32F4xx USB OTG Driver + + + + + + + + +
+ +

 

+ +
+ + + + + +
+ + + + + + + +
+

Back to Release page

+
+

Release Notes for STM32F105/7xx, STM32F2xx and STM32F4xx USB OTG Driver

+

Copyright + 2015 STMicroelectronics

+

+
+

 

+ + + + +
+

Update History

V2.2.0 / 09-November-2015

Main +Changes

+ +
    +
  • Add support of  STM32F469/479xx and  STM32F446 devices
    • +
  • usb_dcd_int.c
    • Bug +Fix: Masking the TxFIFOempty interrupt of the endpoint after +finishing writing data packet to TxFIFO in DCD_WriteEmptyTxFifo function
    • Bug Fix: The USB TRD (Turnaround) is configured depending on AHB frequency used by application.
    • Bug Fix: Handle multi-packet for OUT transfer with DMA in HS mode
    • Remove CLEAR_IN_EP_INTR(epnum, emptyintr) in USBD_OTG_EP1IN_ISR_Handler and DCD_HandleInEP_ISR
    • Correct PCFCCTL register access
  • usb_core.c
    • USB_OTG_HC_Halt function: Modify Channel halt function to disable the channel at the end
    • Correct PCFCCTL register access
    • Bug Fix: Handle multi-packet for OUT transfer with DMA in HS mode
    • Bug Fix: Keep the disconnect interrupt maskedIn function  USB_OTG_EnableHostInt for correct handling of connection/disconnection
    • In function USB_OTG_ResetPort change reset time to 100ms instead of 10ms for better stability during enumeration
  • usb_hcd.c
    •  Add function HCD_IsPortEnabled to check portenabled for correct handling of connection/disconnection
  • usb_hcd_int.c 
    • Remove USB_OTG_ResetPort(pdev) calling 
    • Update USB_OTG_USBH_handle_port_ISR for correct handling of connection/disconnection
    • Disconnect interrupt is unmasked after a connection
    • Creation of PortEnabled event (need to wait for this event before starting enumerating device)
    • Halt channel and restart transfer is removed When using DMA (HS) In case of NAK or NYET in USB_OTG_USBH_handle_hc_n_Out_ISR and USB_OTG_USBH_handle_hc_n_In_ISR
    • Clearing the NAK interrupt flag before re-enabling the channel for a new transfer in USB_OTG_USBH_handle_hc_n_In_ISR function

V2.1.0 / 19-March-2012

+

Main +Changes

+ +
  • Official support of STM32F4xx devices
  • All source files: license disclaimer text update and add link to the License file on ST Internet
  • Unmask Session request interrupt to handle the connect event during the core start-up
  • Remove any reference to the USB HS external I2C PHY
  • Update optimization pragma for AR Compiler
  • Handle Correctly the Low Speed device connection in HS mode
  • Add a wrapper to isolate the library from the low level driver: connection done through ISR structure
  • Miscellaneous bug fix

V2.0.0 / 22-July-2011

Main +Changes

+
  • Second official version supporting STM32F105/7 and STM32F2xx devices
  • Rename the Library from "STM32_USB_HOST_Driver" to "STM32_USB_OTG_Driver"
  • Add support for STM32F2xx devices
  • Add support for Device and OTG modes
  • Change HCD layer to support High speed core
  • Change the Low level driver to support multi core support for Host mode
  • Add Stop mechanism for Host and Device modes
  • Change VBUS enabling method, to use the external or the internal VBUS when using the ULPI

V1.0.0 - 11/29/2010

+
  • Created 

License

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License. +
+
+
+

For + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32

+
+

+
+ +
+ +

 

+ +
+ \ No newline at end of file diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_bsp.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_bsp.h index ccf2232dc..3044f9240 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_bsp.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_bsp.h @@ -1,108 +1,108 @@ -/** - ****************************************************************************** - * @file usb_bsp.h - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief Specific api's relative to the used hardware platform - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_BSP__H__ -#define __USB_BSP__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_BSP - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_BSP_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_BSP_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_BSP_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_BSP_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_BSP_Exported_FunctionsPrototype - * @{ - */ -void BSP_Init(void); - -void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_BSP_Deinit(USB_OTG_CORE_HANDLE *pdev); // modified by OpenTX -void USB_OTG_BSP_uDelay (const uint32_t usec); -void USB_OTG_BSP_mDelay (const uint32_t msec); -void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_BSP_TimerIRQ (void); -void USB_OTG_BSP_DisableInterrupt (USB_OTG_CORE_HANDLE *pdev); // modified by OpenTX -#ifdef USE_HOST_MODE -void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state); -void USB_OTG_BSP_Resume(USB_OTG_CORE_HANDLE *pdev) ; -void USB_OTG_BSP_Suspend(USB_OTG_CORE_HANDLE *pdev); - -#endif /* USE_HOST_MODE */ -/** - * @} - */ - -#endif /* __USB_BSP__H__ */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usb_bsp.h + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief Specific api's relative to the used hardware platform + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_BSP__H__ +#define __USB_BSP__H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_core.h" + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_BSP + * @brief This file is the + * @{ + */ + + +/** @defgroup USB_BSP_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_BSP_Exported_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_BSP_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_BSP_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_BSP_Exported_FunctionsPrototype + * @{ + */ +void BSP_Init(void); + +void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_BSP_Deinit(USB_OTG_CORE_HANDLE *pdev); // modified by OpenTX +void USB_OTG_BSP_uDelay (const uint32_t usec); +void USB_OTG_BSP_mDelay (const uint32_t msec); +void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_BSP_TimerIRQ (void); +void USB_OTG_BSP_DisableInterrupt (USB_OTG_CORE_HANDLE *pdev); // modified by OpenTX +#ifdef USE_HOST_MODE +void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state); +void USB_OTG_BSP_Resume(USB_OTG_CORE_HANDLE *pdev) ; +void USB_OTG_BSP_Suspend(USB_OTG_CORE_HANDLE *pdev); + +#endif /* USE_HOST_MODE */ +/** + * @} + */ + +#endif /* __USB_BSP__H__ */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_conf_template.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_conf_template.h index 23a6c62d3..53c9edb1e 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_conf_template.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_conf_template.h @@ -1,306 +1,306 @@ -/** - ****************************************************************************** - * @file usb_conf.h - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief General low level driver configuration - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CONF__H__ -#define __USB_CONF__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_CONF - * @brief USB low level driver configuration file - * @{ - */ - -/** @defgroup USB_CONF_Exported_Defines - * @{ - */ - -/* USB Core and PHY interface configuration. - Tip: To avoid modifying these defines each time you need to change the USB - configuration, you can declare the needed define in your toolchain - compiler preprocessor. - */ -/****************** USB OTG FS PHY CONFIGURATION ******************************* -* The USB OTG FS Core supports one on-chip Full Speed PHY. -* -* The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor -* when FS core is used. -*******************************************************************************/ -#ifndef USE_USB_OTG_FS - //#define USE_USB_OTG_FS -#endif /* USE_USB_OTG_FS */ - -#ifdef USE_USB_OTG_FS - #define USB_OTG_FS_CORE -#endif - -/****************** USB OTG HS PHY CONFIGURATION ******************************* -* The USB OTG HS Core supports two PHY interfaces: -* (i) An ULPI interface for the external High Speed PHY: the USB HS Core will -* operate in High speed mode -* (ii) An on-chip Full Speed PHY: the USB HS Core will operate in Full speed mode -* -* You can select the PHY to be used using one of these two defines: -* (i) USE_ULPI_PHY: if the USB OTG HS Core is to be used in High speed mode -* (ii) USE_EMBEDDED_PHY: if the USB OTG HS Core is to be used in Full speed mode -* -* Notes: -* - The USE_ULPI_PHY symbol is defined in the project compiler preprocessor as -* default PHY when HS core is used. -* - On STM322xG-EVAL and STM324xG-EVAL boards, only configuration(i) is available. -* Configuration (ii) need a different hardware, for more details refer to your -* STM32 device datasheet. -*******************************************************************************/ -#ifndef USE_USB_OTG_HS - //#define USE_USB_OTG_HS -#endif /* USE_USB_OTG_HS */ - -#ifndef USE_ULPI_PHY - //#define USE_ULPI_PHY -#endif /* USE_ULPI_PHY */ - -#ifndef USE_EMBEDDED_PHY - //#define USE_EMBEDDED_PHY -#endif /* USE_EMBEDDED_PHY */ - -#ifdef USE_USB_OTG_HS - #define USB_OTG_HS_CORE -#endif - -/******************************************************************************* -* FIFO Size Configuration in Device mode -* -* (i) Receive data FIFO size = RAM for setup packets + -* OUT endpoint control information + -* data OUT packets + miscellaneous -* Space = ONE 32-bits words -* --> RAM for setup packets = 10 spaces -* (n is the nbr of CTRL EPs the device core supports) -* --> OUT EP CTRL info = 1 space -* (one space for status information written to the FIFO along with each -* received packet) -* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces -* (MINIMUM to receive packets) -* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces -* (if high-bandwidth EP is enabled or multiple isochronous EPs) -* --> miscellaneous = 1 space per OUT EP -* (one space for transfer complete status information also pushed to the -* FIFO with each endpoint's last packet) -* -* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for -* that particular IN EP. More space allocated in the IN EP Tx FIFO results -* in a better performance on the USB and can hide latencies on the AHB. -* -* (iii) TXn min size = 16 words. (n : Transmit FIFO index) -* (iv) When a TxFIFO is not used, the Configuration should be as follows: -* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txm can use the space allocated for Txn. -* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txn should be configured with the minimum space of 16 words -* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top -* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. -*******************************************************************************/ - -/******************************************************************************* -* FIFO Size Configuration in Host mode -* -* (i) Receive data FIFO size = (Largest Packet Size / 4) + 1 or -* 2x (Largest Packet Size / 4) + 1, If a -* high-bandwidth channel or multiple isochronous -* channels are enabled -* -* (ii) For the host nonperiodic Transmit FIFO is the largest maximum packet size -* for all supported nonperiodic OUT channels. Typically, a space -* corresponding to two Largest Packet Size is recommended. -* -* (iii) The minimum amount of RAM required for Host periodic Transmit FIFO is -* the largest maximum packet size for all supported periodic OUT channels. -* If there is at least one High Bandwidth Isochronous OUT endpoint, -* then the space must be at least two times the maximum packet size for -* that channel. -*******************************************************************************/ - -/****************** USB OTG HS CONFIGURATION **********************************/ -#ifdef USB_OTG_HS_CORE - #define RX_FIFO_HS_SIZE 512 - #define TX0_FIFO_HS_SIZE 512 - #define TX1_FIFO_HS_SIZE 512 - #define TX2_FIFO_HS_SIZE 0 - #define TX3_FIFO_HS_SIZE 0 - #define TX4_FIFO_HS_SIZE 0 - #define TX5_FIFO_HS_SIZE 0 - #define TXH_NP_HS_FIFOSIZ 96 - #define TXH_P_HS_FIFOSIZ 96 - -// #define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT -// #define USB_OTG_HS_SOF_OUTPUT_ENABLED - -// #define USB_OTG_INTERNAL_VBUS_ENABLED - #define USB_OTG_EXTERNAL_VBUS_ENABLED - - #ifdef USE_ULPI_PHY - #define USB_OTG_ULPI_PHY_ENABLED - #endif - #ifdef USE_EMBEDDED_PHY - #define USB_OTG_EMBEDDED_PHY_ENABLED - #endif - #define USB_OTG_HS_INTERNAL_DMA_ENABLED - #define USB_OTG_HS_DEDICATED_EP1_ENABLED -#endif - -/****************** USB OTG FS CONFIGURATION **********************************/ -#ifdef USB_OTG_FS_CORE - #define RX_FIFO_FS_SIZE 128 - #define TX0_FIFO_FS_SIZE 64 - #define TX1_FIFO_FS_SIZE 128 - #define TX2_FIFO_FS_SIZE 0 - #define TX3_FIFO_FS_SIZE 0 - #define TXH_NP_HS_FIFOSIZ 96 - #define TXH_P_HS_FIFOSIZ 96 - -// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT -// #define USB_OTG_FS_SOF_OUTPUT_ENABLED -#endif - -/****************** USB OTG MISC CONFIGURATION ********************************/ -//#define VBUS_SENSING_ENABLED - -/****************** USB OTG MODE CONFIGURATION ********************************/ -//#define USE_HOST_MODE -#define USE_DEVICE_MODE -//#define USE_OTG_MODE - -#ifndef USB_OTG_FS_CORE - #ifndef USB_OTG_HS_CORE - #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined" - #endif -#endif - -#ifndef USE_DEVICE_MODE - #ifndef USE_HOST_MODE - #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" - #endif -#endif - -#ifndef USE_USB_OTG_HS - #ifndef USE_USB_OTG_FS - #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined" - #endif -#else //USE_USB_OTG_HS - #ifndef USE_ULPI_PHY - #ifndef USE_EMBEDDED_PHY - #error "USE_ULPI_PHY or USE_EMBEDDED_PHY should be defined" - #endif - #endif -#endif - -/****************** C Compilers dependant keywords ****************************/ -/* In HS mode and when the DMA is used, all variables and data structures dealing - with the DMA during the transaction process should be 4-bytes aligned */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined (__GNUC__) /* GNU Compiler */ - #define __ALIGN_END __attribute__ ((aligned (4))) - #define __ALIGN_BEGIN - #else - #define __ALIGN_END - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __ALIGN_BEGIN __align(4) - #endif /* __CC_ARM */ - #endif /* __GNUC__ */ -#else - #define __ALIGN_BEGIN - #define __ALIGN_END -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/* __packed keyword used to decrease the data type alignment to 1-byte */ -#if defined (__CC_ARM) /* ARM Compiler */ - #define __packed __packed -#elif defined (__ICCARM__) /* IAR Compiler */ - #define __packed __packed -#elif defined ( __GNUC__ ) /* GNU Compiler */ - #define __packed __attribute__ ((__packed__)) -#elif defined (__TASKING__) /* TASKING Compiler */ - #define __packed __unaligned -#endif /* __CC_ARM */ - -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USB_CONF__H__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usb_conf.h + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief General low level driver configuration + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CONF__H__ +#define __USB_CONF__H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_CONF + * @brief USB low level driver configuration file + * @{ + */ + +/** @defgroup USB_CONF_Exported_Defines + * @{ + */ + +/* USB Core and PHY interface configuration. + Tip: To avoid modifying these defines each time you need to change the USB + configuration, you can declare the needed define in your toolchain + compiler preprocessor. + */ +/****************** USB OTG FS PHY CONFIGURATION ******************************* +* The USB OTG FS Core supports one on-chip Full Speed PHY. +* +* The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor +* when FS core is used. +*******************************************************************************/ +#ifndef USE_USB_OTG_FS + //#define USE_USB_OTG_FS +#endif /* USE_USB_OTG_FS */ + +#ifdef USE_USB_OTG_FS + #define USB_OTG_FS_CORE +#endif + +/****************** USB OTG HS PHY CONFIGURATION ******************************* +* The USB OTG HS Core supports two PHY interfaces: +* (i) An ULPI interface for the external High Speed PHY: the USB HS Core will +* operate in High speed mode +* (ii) An on-chip Full Speed PHY: the USB HS Core will operate in Full speed mode +* +* You can select the PHY to be used using one of these two defines: +* (i) USE_ULPI_PHY: if the USB OTG HS Core is to be used in High speed mode +* (ii) USE_EMBEDDED_PHY: if the USB OTG HS Core is to be used in Full speed mode +* +* Notes: +* - The USE_ULPI_PHY symbol is defined in the project compiler preprocessor as +* default PHY when HS core is used. +* - On STM322xG-EVAL and STM324xG-EVAL boards, only configuration(i) is available. +* Configuration (ii) need a different hardware, for more details refer to your +* STM32 device datasheet. +*******************************************************************************/ +#ifndef USE_USB_OTG_HS + //#define USE_USB_OTG_HS +#endif /* USE_USB_OTG_HS */ + +#ifndef USE_ULPI_PHY + //#define USE_ULPI_PHY +#endif /* USE_ULPI_PHY */ + +#ifndef USE_EMBEDDED_PHY + //#define USE_EMBEDDED_PHY +#endif /* USE_EMBEDDED_PHY */ + +#ifdef USE_USB_OTG_HS + #define USB_OTG_HS_CORE +#endif + +/******************************************************************************* +* FIFO Size Configuration in Device mode +* +* (i) Receive data FIFO size = RAM for setup packets + +* OUT endpoint control information + +* data OUT packets + miscellaneous +* Space = ONE 32-bits words +* --> RAM for setup packets = 10 spaces +* (n is the nbr of CTRL EPs the device core supports) +* --> OUT EP CTRL info = 1 space +* (one space for status information written to the FIFO along with each +* received packet) +* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces +* (MINIMUM to receive packets) +* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces +* (if high-bandwidth EP is enabled or multiple isochronous EPs) +* --> miscellaneous = 1 space per OUT EP +* (one space for transfer complete status information also pushed to the +* FIFO with each endpoint's last packet) +* +* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for +* that particular IN EP. More space allocated in the IN EP Tx FIFO results +* in a better performance on the USB and can hide latencies on the AHB. +* +* (iii) TXn min size = 16 words. (n : Transmit FIFO index) +* (iv) When a TxFIFO is not used, the Configuration should be as follows: +* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) +* --> Txm can use the space allocated for Txn. +* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) +* --> Txn should be configured with the minimum space of 16 words +* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top +* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. +*******************************************************************************/ + +/******************************************************************************* +* FIFO Size Configuration in Host mode +* +* (i) Receive data FIFO size = (Largest Packet Size / 4) + 1 or +* 2x (Largest Packet Size / 4) + 1, If a +* high-bandwidth channel or multiple isochronous +* channels are enabled +* +* (ii) For the host nonperiodic Transmit FIFO is the largest maximum packet size +* for all supported nonperiodic OUT channels. Typically, a space +* corresponding to two Largest Packet Size is recommended. +* +* (iii) The minimum amount of RAM required for Host periodic Transmit FIFO is +* the largest maximum packet size for all supported periodic OUT channels. +* If there is at least one High Bandwidth Isochronous OUT endpoint, +* then the space must be at least two times the maximum packet size for +* that channel. +*******************************************************************************/ + +/****************** USB OTG HS CONFIGURATION **********************************/ +#ifdef USB_OTG_HS_CORE + #define RX_FIFO_HS_SIZE 512 + #define TX0_FIFO_HS_SIZE 512 + #define TX1_FIFO_HS_SIZE 512 + #define TX2_FIFO_HS_SIZE 0 + #define TX3_FIFO_HS_SIZE 0 + #define TX4_FIFO_HS_SIZE 0 + #define TX5_FIFO_HS_SIZE 0 + #define TXH_NP_HS_FIFOSIZ 96 + #define TXH_P_HS_FIFOSIZ 96 + +// #define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT +// #define USB_OTG_HS_SOF_OUTPUT_ENABLED + +// #define USB_OTG_INTERNAL_VBUS_ENABLED + #define USB_OTG_EXTERNAL_VBUS_ENABLED + + #ifdef USE_ULPI_PHY + #define USB_OTG_ULPI_PHY_ENABLED + #endif + #ifdef USE_EMBEDDED_PHY + #define USB_OTG_EMBEDDED_PHY_ENABLED + #endif + #define USB_OTG_HS_INTERNAL_DMA_ENABLED + #define USB_OTG_HS_DEDICATED_EP1_ENABLED +#endif + +/****************** USB OTG FS CONFIGURATION **********************************/ +#ifdef USB_OTG_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 128 + #define TX2_FIFO_FS_SIZE 0 + #define TX3_FIFO_FS_SIZE 0 + #define TXH_NP_HS_FIFOSIZ 96 + #define TXH_P_HS_FIFOSIZ 96 + +// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT +// #define USB_OTG_FS_SOF_OUTPUT_ENABLED +#endif + +/****************** USB OTG MISC CONFIGURATION ********************************/ +//#define VBUS_SENSING_ENABLED + +/****************** USB OTG MODE CONFIGURATION ********************************/ +//#define USE_HOST_MODE +#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_OTG_FS_CORE + #ifndef USB_OTG_HS_CORE + #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_OTG_HS + #ifndef USE_USB_OTG_FS + #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined" + #endif +#else //USE_USB_OTG_HS + #ifndef USE_ULPI_PHY + #ifndef USE_EMBEDDED_PHY + #error "USE_ULPI_PHY or USE_EMBEDDED_PHY should be defined" + #endif + #endif +#endif + +/****************** C Compilers dependant keywords ****************************/ +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned (4))) + #define __ALIGN_BEGIN + #else + #define __ALIGN_END + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #elif defined (__TASKING__) /* TASKING Compiler */ + #define __ALIGN_BEGIN __align(4) + #endif /* __CC_ARM */ + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +/* __packed keyword used to decrease the data type alignment to 1-byte */ +#if defined (__CC_ARM) /* ARM Compiler */ + #define __packed __packed +#elif defined (__ICCARM__) /* IAR Compiler */ + #define __packed __packed +#elif defined ( __GNUC__ ) /* GNU Compiler */ + #define __packed __attribute__ ((__packed__)) +#elif defined (__TASKING__) /* TASKING Compiler */ + #define __packed __unaligned +#endif /* __CC_ARM */ + +/** + * @} + */ + + +/** @defgroup USB_CONF_Exported_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_CONF_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_CONF_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_CONF_Exported_FunctionsPrototype + * @{ + */ +/** + * @} + */ + + +#endif //__USB_CONF__H__ + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_core.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_core.h index c63d6ae4a..b3bde4fd0 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_core.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_core.h @@ -1,411 +1,411 @@ -/** - ****************************************************************************** - * @file usb_core.h - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief Header of the Core Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CORE_H__ -#define __USB_CORE_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usb_regs.h" -#include "usb_defines.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_CORE - * @brief usb otg driver core layer - * @{ - */ - - -/** @defgroup USB_CORE_Exported_Defines - * @{ - */ - -#define USB_OTG_EP0_IDLE 0 -#define USB_OTG_EP0_SETUP 1 -#define USB_OTG_EP0_DATA_IN 2 -#define USB_OTG_EP0_DATA_OUT 3 -#define USB_OTG_EP0_STATUS_IN 4 -#define USB_OTG_EP0_STATUS_OUT 5 -#define USB_OTG_EP0_STALL 6 - -#define USB_OTG_EP_TX_DIS 0x0000 -#define USB_OTG_EP_TX_STALL 0x0010 -#define USB_OTG_EP_TX_NAK 0x0020 -#define USB_OTG_EP_TX_VALID 0x0030 - -#define USB_OTG_EP_RX_DIS 0x0000 -#define USB_OTG_EP_RX_STALL 0x1000 -#define USB_OTG_EP_RX_NAK 0x2000 -#define USB_OTG_EP_RX_VALID 0x3000 -/** - * @} - */ -#define MAX_DATA_LENGTH 0x200 - -/** @defgroup USB_CORE_Exported_Types - * @{ - */ - - -typedef enum { - USB_OTG_OK = 0, - USB_OTG_FAIL -}USB_OTG_STS; - -typedef enum { - HC_IDLE = 0, - HC_XFRC, - HC_HALTED, - HC_NAK, - HC_NYET, - HC_STALL, - HC_XACTERR, - HC_BBLERR, - HC_DATATGLERR, -}HC_STATUS; - -typedef enum { - URB_IDLE = 0, - URB_DONE, - URB_NOTREADY, - URB_ERROR, - URB_STALL -}URB_STATE; - -typedef enum { - CTRL_START = 0, - CTRL_XFRC, - CTRL_HALTED, - CTRL_NAK, - CTRL_STALL, - CTRL_XACTERR, - CTRL_BBLERR, - CTRL_DATATGLERR, - CTRL_FAIL -}CTRL_STATUS; - - -typedef struct USB_OTG_hc -{ - uint8_t dev_addr ; - uint8_t ep_num; - uint8_t ep_is_in; - uint8_t speed; - uint8_t do_ping; - uint8_t ep_type; - uint16_t max_packet; - uint8_t data_pid; - uint8_t *xfer_buff; - uint32_t xfer_len; - uint32_t xfer_count; - uint8_t toggle_in; - uint8_t toggle_out; - uint32_t dma_addr; -} -USB_OTG_HC , *PUSB_OTG_HC; - -typedef struct USB_OTG_ep -{ - uint8_t num; - uint8_t is_in; - uint8_t is_stall; - uint8_t type; - uint8_t data_pid_start; - uint8_t even_odd_frame; - uint16_t tx_fifo_num; - uint32_t maxpacket; - /* transaction level variables*/ - uint8_t *xfer_buff; - uint32_t dma_addr; - uint32_t xfer_len; - uint32_t xfer_count; - /* Transfer level variables*/ - uint32_t rem_data_len; - uint32_t total_data_len; - uint32_t ctl_data_len; - -} - -USB_OTG_EP , *PUSB_OTG_EP; - - - -typedef struct USB_OTG_core_cfg -{ - uint8_t host_channels; - uint8_t dev_endpoints; - uint8_t speed; - uint8_t dma_enable; - uint16_t mps; - uint16_t TotalFifoSize; - uint8_t phy_itface; - uint8_t Sof_output; - uint8_t low_power; - uint8_t coreID; - -} -USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS; - - - -typedef struct usb_setup_req { - - uint8_t bmRequest; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} USB_SETUP_REQ; - -typedef struct _Device_TypeDef -{ - uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length); - -#if (USBD_LPM_ENABLED == 1) - uint8_t *(*GetBOSDescriptor)( uint8_t speed , uint16_t *length); -#endif -} USBD_DEVICE, *pUSBD_DEVICE; - -typedef struct _Device_cb -{ - uint8_t (*Init) (void *pdev , uint8_t cfgidx); - uint8_t (*DeInit) (void *pdev , uint8_t cfgidx); - /* Control Endpoints*/ - uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req); - uint8_t (*EP0_TxSent) (void *pdev ); - uint8_t (*EP0_RxReady) (void *pdev ); - /* Class Specific Endpoints*/ - uint8_t (*DataIn) (void *pdev , uint8_t epnum); - uint8_t (*DataOut) (void *pdev , uint8_t epnum); - uint8_t (*SOF) (void *pdev); - uint8_t (*IsoINIncomplete) (void *pdev); - uint8_t (*IsoOUTIncomplete) (void *pdev); - - const uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length); // modified by OpenTX -#ifdef USB_OTG_HS_CORE - const uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length); // modified by OpenTX -#endif - -#ifdef USB_SUPPORT_USER_STRING_DESC - uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length); -#endif - -} USBD_Class_cb_TypeDef; - - - -typedef struct _USBD_USR_PROP -{ - void (*Init)(void); - void (*DeviceReset)(uint8_t speed); - void (*DeviceConfigured)(void); - void (*DeviceSuspended)(void); - void (*DeviceResumed)(void); - - void (*DeviceConnected)(void); - void (*DeviceDisconnected)(void); - -} -USBD_Usr_cb_TypeDef; - -typedef struct _DCD -{ - uint8_t device_config; - uint8_t device_state; - uint8_t device_status; - uint8_t device_old_status; - uint8_t device_address; - uint8_t connection_status; - uint8_t test_mode; - uint32_t DevRemoteWakeup; - USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS]; - USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS]; - uint8_t setup_packet [8*3]; - const USBD_Class_cb_TypeDef *class_cb; - const USBD_Usr_cb_TypeDef *usr_cb; - const USBD_DEVICE *usr_device; - uint8_t *pConfig_descriptor; - } -DCD_DEV , *DCD_PDEV; // modified by OpenTX - - -typedef struct _HCD -{ - uint8_t Rx_Buffer [MAX_DATA_LENGTH]; - __IO uint32_t ConnSts; - __IO uint32_t PortEnabled; - __IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS]; - __IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS]; - __IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS]; - uint16_t channel [USB_OTG_MAX_TX_FIFOS]; -} -HCD_DEV , *USB_OTG_USBH_PDEV; - - -typedef struct _OTG -{ - uint8_t OTG_State; - uint8_t OTG_PrevState; - uint8_t OTG_Mode; -} -OTG_DEV , *USB_OTG_USBO_PDEV; - -typedef struct USB_OTG_handle -{ - USB_OTG_CORE_CFGS cfg; - USB_OTG_CORE_REGS regs; -#ifdef USE_DEVICE_MODE - DCD_DEV dev; -#endif -#ifdef USE_HOST_MODE - HCD_DEV host; -#endif -#ifdef USE_OTG_MODE - OTG_DEV otg; -#endif -} -USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE; - -/** - * @} - */ - - -/** @defgroup USB_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_FunctionsPrototype - * @{ - */ - - -USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID); -USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev); -void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev , - uint8_t *dest, - uint16_t len); -USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev , - uint8_t *src, - uint8_t ch_ep_num, - uint16_t len); -USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num); -USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev); - -uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev); -uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev); -uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev, - uint8_t mode); - -/*********************** HOST APIs ********************************************/ -#ifdef USE_HOST_MODE -USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num); -uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state); -void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq); -uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ; -void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev); -#endif -/********************* DEVICE APIs ********************************************/ -#ifdef USE_DEVICE_MODE -USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); -enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed); -uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status); -uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep); -#endif -/** - * @} - */ - -#endif /* __USB_CORE_H__ */ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usb_core.h + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief Header of the Core Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CORE_H__ +#define __USB_CORE_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" +#include "usb_regs.h" +#include "usb_defines.h" + + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_CORE + * @brief usb otg driver core layer + * @{ + */ + + +/** @defgroup USB_CORE_Exported_Defines + * @{ + */ + +#define USB_OTG_EP0_IDLE 0 +#define USB_OTG_EP0_SETUP 1 +#define USB_OTG_EP0_DATA_IN 2 +#define USB_OTG_EP0_DATA_OUT 3 +#define USB_OTG_EP0_STATUS_IN 4 +#define USB_OTG_EP0_STATUS_OUT 5 +#define USB_OTG_EP0_STALL 6 + +#define USB_OTG_EP_TX_DIS 0x0000 +#define USB_OTG_EP_TX_STALL 0x0010 +#define USB_OTG_EP_TX_NAK 0x0020 +#define USB_OTG_EP_TX_VALID 0x0030 + +#define USB_OTG_EP_RX_DIS 0x0000 +#define USB_OTG_EP_RX_STALL 0x1000 +#define USB_OTG_EP_RX_NAK 0x2000 +#define USB_OTG_EP_RX_VALID 0x3000 +/** + * @} + */ +#define MAX_DATA_LENGTH 0x200 + +/** @defgroup USB_CORE_Exported_Types + * @{ + */ + + +typedef enum { + USB_OTG_OK = 0, + USB_OTG_FAIL +}USB_OTG_STS; + +typedef enum { + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR, +}HC_STATUS; + +typedef enum { + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_ERROR, + URB_STALL +}URB_STATE; + +typedef enum { + CTRL_START = 0, + CTRL_XFRC, + CTRL_HALTED, + CTRL_NAK, + CTRL_STALL, + CTRL_XACTERR, + CTRL_BBLERR, + CTRL_DATATGLERR, + CTRL_FAIL +}CTRL_STATUS; + + +typedef struct USB_OTG_hc +{ + uint8_t dev_addr ; + uint8_t ep_num; + uint8_t ep_is_in; + uint8_t speed; + uint8_t do_ping; + uint8_t ep_type; + uint16_t max_packet; + uint8_t data_pid; + uint8_t *xfer_buff; + uint32_t xfer_len; + uint32_t xfer_count; + uint8_t toggle_in; + uint8_t toggle_out; + uint32_t dma_addr; +} +USB_OTG_HC , *PUSB_OTG_HC; + +typedef struct USB_OTG_ep +{ + uint8_t num; + uint8_t is_in; + uint8_t is_stall; + uint8_t type; + uint8_t data_pid_start; + uint8_t even_odd_frame; + uint16_t tx_fifo_num; + uint32_t maxpacket; + /* transaction level variables*/ + uint8_t *xfer_buff; + uint32_t dma_addr; + uint32_t xfer_len; + uint32_t xfer_count; + /* Transfer level variables*/ + uint32_t rem_data_len; + uint32_t total_data_len; + uint32_t ctl_data_len; + +} + +USB_OTG_EP , *PUSB_OTG_EP; + + + +typedef struct USB_OTG_core_cfg +{ + uint8_t host_channels; + uint8_t dev_endpoints; + uint8_t speed; + uint8_t dma_enable; + uint16_t mps; + uint16_t TotalFifoSize; + uint8_t phy_itface; + uint8_t Sof_output; + uint8_t low_power; + uint8_t coreID; + +} +USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS; + + + +typedef struct usb_setup_req { + + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ; + +typedef struct _Device_TypeDef +{ + uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length); + +#if (USBD_LPM_ENABLED == 1) + uint8_t *(*GetBOSDescriptor)( uint8_t speed , uint16_t *length); +#endif +} USBD_DEVICE, *pUSBD_DEVICE; + +typedef struct _Device_cb +{ + uint8_t (*Init) (void *pdev , uint8_t cfgidx); + uint8_t (*DeInit) (void *pdev , uint8_t cfgidx); + /* Control Endpoints*/ + uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req); + uint8_t (*EP0_TxSent) (void *pdev ); + uint8_t (*EP0_RxReady) (void *pdev ); + /* Class Specific Endpoints*/ + uint8_t (*DataIn) (void *pdev , uint8_t epnum); + uint8_t (*DataOut) (void *pdev , uint8_t epnum); + uint8_t (*SOF) (void *pdev); + uint8_t (*IsoINIncomplete) (void *pdev); + uint8_t (*IsoOUTIncomplete) (void *pdev); + + const uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length); // modified by OpenTX +#ifdef USB_OTG_HS_CORE + const uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length); // modified by OpenTX +#endif + +#ifdef USB_SUPPORT_USER_STRING_DESC + uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length); +#endif + +} USBD_Class_cb_TypeDef; + + + +typedef struct _USBD_USR_PROP +{ + void (*Init)(void); + void (*DeviceReset)(uint8_t speed); + void (*DeviceConfigured)(void); + void (*DeviceSuspended)(void); + void (*DeviceResumed)(void); + + void (*DeviceConnected)(void); + void (*DeviceDisconnected)(void); + +} +USBD_Usr_cb_TypeDef; + +typedef struct _DCD +{ + uint8_t device_config; + uint8_t device_state; + uint8_t device_status; + uint8_t device_old_status; + uint8_t device_address; + uint8_t connection_status; + uint8_t test_mode; + uint32_t DevRemoteWakeup; + USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS]; + USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS]; + uint8_t setup_packet [8*3]; + const USBD_Class_cb_TypeDef *class_cb; + const USBD_Usr_cb_TypeDef *usr_cb; + const USBD_DEVICE *usr_device; + uint8_t *pConfig_descriptor; + } +DCD_DEV , *DCD_PDEV; // modified by OpenTX + + +typedef struct _HCD +{ + uint8_t Rx_Buffer [MAX_DATA_LENGTH]; + __IO uint32_t ConnSts; + __IO uint32_t PortEnabled; + __IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS]; + __IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS]; + __IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS]; + __IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS]; + USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS]; + uint16_t channel [USB_OTG_MAX_TX_FIFOS]; +} +HCD_DEV , *USB_OTG_USBH_PDEV; + + +typedef struct _OTG +{ + uint8_t OTG_State; + uint8_t OTG_PrevState; + uint8_t OTG_Mode; +} +OTG_DEV , *USB_OTG_USBO_PDEV; + +typedef struct USB_OTG_handle +{ + USB_OTG_CORE_CFGS cfg; + USB_OTG_CORE_REGS regs; +#ifdef USE_DEVICE_MODE + DCD_DEV dev; +#endif +#ifdef USE_HOST_MODE + HCD_DEV host; +#endif +#ifdef USE_OTG_MODE + OTG_DEV otg; +#endif +} +USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE; + +/** + * @} + */ + + +/** @defgroup USB_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_FunctionsPrototype + * @{ + */ + + +USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev, + USB_OTG_CORE_ID_TypeDef coreID); +USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev); +void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev , + uint8_t *dest, + uint16_t len); +USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev , + uint8_t *src, + uint8_t ch_ep_num, + uint16_t len); +USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num); +USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev); + +uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev); +uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev); +uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev, + uint8_t mode); + +/*********************** HOST APIs ********************************************/ +#ifdef USE_HOST_MODE +USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); +USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); +USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); +USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num); +uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state); +void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq); +uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ; +void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev); +#endif +/********************* DEVICE APIs ********************************************/ +#ifdef USE_DEVICE_MODE +USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); +enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); +uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed); +uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status); +uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep); +#endif +/** + * @} + */ + +#endif /* __USB_CORE_H__ */ + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_dcd.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_dcd.h index a35125879..1433794ea 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_dcd.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_dcd.h @@ -1,164 +1,164 @@ -/** - ****************************************************************************** - * @file usb_dcd.h - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief Peripheral Driver Header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __DCD_H__ -#define __DCD_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD -* @brief This file is the -* @{ -*/ - - -/** @defgroup USB_DCD_Exported_Defines -* @{ -*/ -#define USB_OTG_EP_CONTROL 0 -#define USB_OTG_EP_ISOC 1 -#define USB_OTG_EP_BULK 2 -#define USB_OTG_EP_INT 3 -#define USB_OTG_EP_MASK 3 - -/* Device Status */ -#define USB_OTG_DEFAULT 1 -#define USB_OTG_ADDRESSED 2 -#define USB_OTG_CONFIGURED 3 -#define USB_OTG_SUSPENDED 4 - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Exported_Types -* @{ -*/ -/******************************************************************************** -Data structure type -********************************************************************************/ -typedef struct -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - uint16_t wMaxPacketSize; - uint8_t bInterval; -} -EP_DESCRIPTOR , *PEP_DESCRIPTOR; - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Exported_Macros -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USB_DCD_Exported_Variables -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USB_DCD_Exported_FunctionsPrototype -* @{ -*/ -/******************************************************************************** -EXPORTED FUNCTION FROM THE USB-OTG LAYER -********************************************************************************/ -void DCD_Init(USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID); - -void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev); -void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev); -void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, - uint8_t address); -uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , - uint8_t ep_addr, - uint16_t ep_mps, - uint8_t ep_type); - -uint32_t DCD_EP_Close (USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr); - - -uint32_t DCD_EP_PrepareRx ( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t buf_len); - -uint32_t DCD_EP_Tx (USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - const uint8_t *pbuf, - uint32_t buf_len); // modified by OpenTX -uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_Handle_ISR(USB_OTG_CORE_HANDLE *pdev); - -uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum); - -void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum , - uint32_t Status); - -/** -* @} -*/ - - -#endif /* __DCD_H__ */ - - -/** -* @} -*/ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usb_dcd.h + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief Peripheral Driver Header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DCD_H__ +#define __DCD_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_core.h" + + +/** @addtogroup USB_OTG_DRIVER +* @{ +*/ + +/** @defgroup USB_DCD +* @brief This file is the +* @{ +*/ + + +/** @defgroup USB_DCD_Exported_Defines +* @{ +*/ +#define USB_OTG_EP_CONTROL 0 +#define USB_OTG_EP_ISOC 1 +#define USB_OTG_EP_BULK 2 +#define USB_OTG_EP_INT 3 +#define USB_OTG_EP_MASK 3 + +/* Device Status */ +#define USB_OTG_DEFAULT 1 +#define USB_OTG_ADDRESSED 2 +#define USB_OTG_CONFIGURED 3 +#define USB_OTG_SUSPENDED 4 + +/** +* @} +*/ + + +/** @defgroup USB_DCD_Exported_Types +* @{ +*/ +/******************************************************************************** +Data structure type +********************************************************************************/ +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; +} +EP_DESCRIPTOR , *PEP_DESCRIPTOR; + +/** +* @} +*/ + + +/** @defgroup USB_DCD_Exported_Macros +* @{ +*/ +/** +* @} +*/ + +/** @defgroup USB_DCD_Exported_Variables +* @{ +*/ +/** +* @} +*/ + +/** @defgroup USB_DCD_Exported_FunctionsPrototype +* @{ +*/ +/******************************************************************************** +EXPORTED FUNCTION FROM THE USB-OTG LAYER +********************************************************************************/ +void DCD_Init(USB_OTG_CORE_HANDLE *pdev , + USB_OTG_CORE_ID_TypeDef coreID); + +void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev); +void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev); +void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, + uint8_t address); +uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , + uint8_t ep_addr, + uint16_t ep_mps, + uint8_t ep_type); + +uint32_t DCD_EP_Close (USB_OTG_CORE_HANDLE *pdev, + uint8_t ep_addr); + + +uint32_t DCD_EP_PrepareRx ( USB_OTG_CORE_HANDLE *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t buf_len); + +uint32_t DCD_EP_Tx (USB_OTG_CORE_HANDLE *pdev, + uint8_t ep_addr, + const uint8_t *pbuf, + uint32_t buf_len); // modified by OpenTX +uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); +uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); +uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); +uint32_t DCD_Handle_ISR(USB_OTG_CORE_HANDLE *pdev); + +uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev , + uint8_t epnum); + +void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , + uint8_t epnum , + uint32_t Status); + +/** +* @} +*/ + + +#endif /* __DCD_H__ */ + + +/** +* @} +*/ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_dcd_int.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_dcd_int.h index 221e15855..0860bbb7d 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_dcd_int.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_dcd_int.h @@ -1,128 +1,128 @@ -/** - ****************************************************************************** - * @file usb_dcd_int.h - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief Peripheral Device Interface Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef USB_DCD_INT_H__ -#define USB_DCD_INT_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" - - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_DCD_INT - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_DCD_INT_Exported_Defines - * @{ - */ - -typedef struct _USBD_DCD_INT -{ - uint8_t (* DataOutStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); - uint8_t (* DataInStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); - uint8_t (* SetupStage) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Reset) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Suspend) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Resume) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* IsoINIncomplete) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* IsoOUTIncomplete) (USB_OTG_CORE_HANDLE *pdev); - - uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev); - -}USBD_DCD_INT_cb_TypeDef; - -extern const USBD_DCD_INT_cb_TypeDef * const USBD_DCD_INT_fops; // modified by OpenTX -/** - * @} - */ - - -/** @defgroup USB_DCD_INT_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_Macros - * @{ - */ - -#define CLEAR_IN_EP_INTR(epnum,intr) \ - diepint.d32=0; \ - diepint.b.intr = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT,diepint.d32); - -#define CLEAR_OUT_EP_INTR(epnum,intr) \ - doepint.d32=0; \ - doepint.b.intr = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[(epnum)]->DOEPINT,doepint.d32); - -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_FunctionsPrototype - * @{ - */ - -uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); -uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); -uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); -/** - * @} - */ - - -#endif /* USB_DCD_INT_H__ */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usb_dcd_int.h + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief Peripheral Device Interface Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef USB_DCD_INT_H__ +#define USB_DCD_INT_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_dcd.h" + + + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_DCD_INT + * @brief This file is the + * @{ + */ + + +/** @defgroup USB_DCD_INT_Exported_Defines + * @{ + */ + +typedef struct _USBD_DCD_INT +{ + uint8_t (* DataOutStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); + uint8_t (* DataInStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); + uint8_t (* SetupStage) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* Reset) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* Suspend) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* Resume) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* IsoINIncomplete) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* IsoOUTIncomplete) (USB_OTG_CORE_HANDLE *pdev); + + uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev); + +}USBD_DCD_INT_cb_TypeDef; + +extern const USBD_DCD_INT_cb_TypeDef * const USBD_DCD_INT_fops; // modified by OpenTX +/** + * @} + */ + + +/** @defgroup USB_DCD_INT_Exported_Types + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_DCD_INT_Exported_Macros + * @{ + */ + +#define CLEAR_IN_EP_INTR(epnum,intr) \ + diepint.d32=0; \ + diepint.b.intr = 1; \ + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT,diepint.d32); + +#define CLEAR_OUT_EP_INTR(epnum,intr) \ + doepint.d32=0; \ + doepint.b.intr = 1; \ + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[(epnum)]->DOEPINT,doepint.d32); + +/** + * @} + */ + +/** @defgroup USB_DCD_INT_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_DCD_INT_Exported_FunctionsPrototype + * @{ + */ + +uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); +uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); +uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); +/** + * @} + */ + + +#endif /* USB_DCD_INT_H__ */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_defines.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_defines.h index 8e2782a3f..479afbc8e 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_defines.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_defines.h @@ -1,249 +1,249 @@ -/** - ****************************************************************************** - * @file usb_defines.h - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief Header of the Core Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_DEF_H__ -#define __USB_DEF_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_DEFINES - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_DEFINES_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup _CORE_DEFINES_ - * @{ - */ - -#define USB_OTG_SPEED_PARAM_HIGH 0 -#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL 1 -#define USB_OTG_SPEED_PARAM_FULL 3 - -#define USB_OTG_SPEED_HIGH 0 -#define USB_OTG_SPEED_FULL 1 - -#define USB_OTG_ULPI_PHY 1 -#define USB_OTG_EMBEDDED_PHY 2 - -/** - * @} - */ - - -/** @defgroup _GLOBAL_DEFINES_ - * @{ - */ -#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 -#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 -#define GAHBCFG_GLBINT_ENABLE 1 -#define GAHBCFG_INT_DMA_BURST_SINGLE 0 -#define GAHBCFG_INT_DMA_BURST_INCR 1 -#define GAHBCFG_INT_DMA_BURST_INCR4 3 -#define GAHBCFG_INT_DMA_BURST_INCR8 5 -#define GAHBCFG_INT_DMA_BURST_INCR16 7 -#define GAHBCFG_DMAENABLE 1 -#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 -#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 -#define GRXSTS_PKTSTS_IN 2 -#define GRXSTS_PKTSTS_IN_XFER_COMP 3 -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 -#define GRXSTS_PKTSTS_CH_HALTED 7 -/** - * @} - */ - - -/** @defgroup _OnTheGo_DEFINES_ - * @{ - */ -#define MODE_HNP_SRP_CAPABLE 0 -#define MODE_SRP_ONLY_CAPABLE 1 -#define MODE_NO_HNP_SRP_CAPABLE 2 -#define MODE_SRP_CAPABLE_DEVICE 3 -#define MODE_NO_SRP_CAPABLE_DEVICE 4 -#define MODE_SRP_CAPABLE_HOST 5 -#define MODE_NO_SRP_CAPABLE_HOST 6 -#define A_HOST 1 -#define A_SUSPEND 2 -#define A_PERIPHERAL 3 -#define B_PERIPHERAL 4 -#define B_HOST 5 -#define DEVICE_MODE 0 -#define HOST_MODE 1 -#define OTG_MODE 2 -/** - * @} - */ - - -/** @defgroup __DEVICE_DEFINES_ - * @{ - */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 -#define DSTS_ENUMSPD_LS_PHY_6MHZ 2 -#define DSTS_ENUMSPD_FS_PHY_48MHZ 3 - -#define DCFG_FRAME_INTERVAL_80 0 -#define DCFG_FRAME_INTERVAL_85 1 -#define DCFG_FRAME_INTERVAL_90 2 -#define DCFG_FRAME_INTERVAL_95 3 - -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 - -#define EP_SPEED_LOW 0 -#define EP_SPEED_FULL 1 -#define EP_SPEED_HIGH 2 - -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 - -#define STS_GOUT_NAK 1 -#define STS_DATA_UPDT 2 -#define STS_XFER_COMP 3 -#define STS_SETUP_COMP 4 -#define STS_SETUP_UPDT 6 -/** - * @} - */ - - -/** @defgroup __HOST_DEFINES_ - * @{ - */ -#define HC_PID_DATA0 0 -#define HC_PID_DATA2 1 -#define HC_PID_DATA1 2 -#define HC_PID_SETUP 3 - -#define HPRT0_PRTSPD_HIGH_SPEED 0 -#define HPRT0_PRTSPD_FULL_SPEED 1 -#define HPRT0_PRTSPD_LOW_SPEED 2 - -#define HCFG_30_60_MHZ 0 -#define HCFG_48_MHZ 1 -#define HCFG_6_MHZ 2 - -#define HCCHAR_CTRL 0 -#define HCCHAR_ISOC 1 -#define HCCHAR_BULK 2 -#define HCCHAR_INTR 3 - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -/** - * @} - */ - - -/** @defgroup USB_DEFINES_Exported_Types - * @{ - */ - -typedef enum -{ - USB_OTG_HS_CORE_ID = 0, - USB_OTG_FS_CORE_ID = 1 -}USB_OTG_CORE_ID_TypeDef; -/** - * @} - */ - - -/** @defgroup USB_DEFINES_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DEFINES_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DEFINES_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -/** @defgroup Internal_Macro's - * @{ - */ -#define USB_OTG_READ_REG32(reg) (*(__IO uint32_t *)(reg)) -#define USB_OTG_WRITE_REG32(reg,value) (*(__IO uint32_t *)(reg) = (value)) -#define USB_OTG_MODIFY_REG32(reg,clear_mask,set_mask) \ - USB_OTG_WRITE_REG32((reg), (((USB_OTG_READ_REG32(reg)) & ~(clear_mask)) | (set_mask)) ) - -/******************************************************************************** - ENUMERATION TYPE -********************************************************************************/ -enum USB_OTG_SPEED { - USB_SPEED_UNKNOWN = 0, - USB_SPEED_LOW, - USB_SPEED_FULL, - USB_SPEED_HIGH -}; - -#endif /* __USB_DEFINES__H__ */ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usb_defines.h + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief Header of the Core Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_DEF_H__ +#define __USB_DEF_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_DEFINES + * @brief This file is the + * @{ + */ + + +/** @defgroup USB_DEFINES_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup _CORE_DEFINES_ + * @{ + */ + +#define USB_OTG_SPEED_PARAM_HIGH 0 +#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL 1 +#define USB_OTG_SPEED_PARAM_FULL 3 + +#define USB_OTG_SPEED_HIGH 0 +#define USB_OTG_SPEED_FULL 1 + +#define USB_OTG_ULPI_PHY 1 +#define USB_OTG_EMBEDDED_PHY 2 + +/** + * @} + */ + + +/** @defgroup _GLOBAL_DEFINES_ + * @{ + */ +#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 +#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 +#define GAHBCFG_GLBINT_ENABLE 1 +#define GAHBCFG_INT_DMA_BURST_SINGLE 0 +#define GAHBCFG_INT_DMA_BURST_INCR 1 +#define GAHBCFG_INT_DMA_BURST_INCR4 3 +#define GAHBCFG_INT_DMA_BURST_INCR8 5 +#define GAHBCFG_INT_DMA_BURST_INCR16 7 +#define GAHBCFG_DMAENABLE 1 +#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 +#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 +#define GRXSTS_PKTSTS_IN 2 +#define GRXSTS_PKTSTS_IN_XFER_COMP 3 +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 +#define GRXSTS_PKTSTS_CH_HALTED 7 +/** + * @} + */ + + +/** @defgroup _OnTheGo_DEFINES_ + * @{ + */ +#define MODE_HNP_SRP_CAPABLE 0 +#define MODE_SRP_ONLY_CAPABLE 1 +#define MODE_NO_HNP_SRP_CAPABLE 2 +#define MODE_SRP_CAPABLE_DEVICE 3 +#define MODE_NO_SRP_CAPABLE_DEVICE 4 +#define MODE_SRP_CAPABLE_HOST 5 +#define MODE_NO_SRP_CAPABLE_HOST 6 +#define A_HOST 1 +#define A_SUSPEND 2 +#define A_PERIPHERAL 3 +#define B_PERIPHERAL 4 +#define B_HOST 5 +#define DEVICE_MODE 0 +#define HOST_MODE 1 +#define OTG_MODE 2 +/** + * @} + */ + + +/** @defgroup __DEVICE_DEFINES_ + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 +#define DSTS_ENUMSPD_LS_PHY_6MHZ 2 +#define DSTS_ENUMSPD_FS_PHY_48MHZ 3 + +#define DCFG_FRAME_INTERVAL_80 0 +#define DCFG_FRAME_INTERVAL_85 1 +#define DCFG_FRAME_INTERVAL_90 2 +#define DCFG_FRAME_INTERVAL_95 3 + +#define DEP0CTL_MPS_64 0 +#define DEP0CTL_MPS_32 1 +#define DEP0CTL_MPS_16 2 +#define DEP0CTL_MPS_8 3 + +#define EP_SPEED_LOW 0 +#define EP_SPEED_FULL 1 +#define EP_SPEED_HIGH 2 + +#define EP_TYPE_CTRL 0 +#define EP_TYPE_ISOC 1 +#define EP_TYPE_BULK 2 +#define EP_TYPE_INTR 3 +#define EP_TYPE_MSK 3 + +#define STS_GOUT_NAK 1 +#define STS_DATA_UPDT 2 +#define STS_XFER_COMP 3 +#define STS_SETUP_COMP 4 +#define STS_SETUP_UPDT 6 +/** + * @} + */ + + +/** @defgroup __HOST_DEFINES_ + * @{ + */ +#define HC_PID_DATA0 0 +#define HC_PID_DATA2 1 +#define HC_PID_DATA1 2 +#define HC_PID_SETUP 3 + +#define HPRT0_PRTSPD_HIGH_SPEED 0 +#define HPRT0_PRTSPD_FULL_SPEED 1 +#define HPRT0_PRTSPD_LOW_SPEED 2 + +#define HCFG_30_60_MHZ 0 +#define HCFG_48_MHZ 1 +#define HCFG_6_MHZ 2 + +#define HCCHAR_CTRL 0 +#define HCCHAR_ISOC 1 +#define HCCHAR_BULK 2 +#define HCCHAR_INTR 3 + +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) + +/** + * @} + */ + + +/** @defgroup USB_DEFINES_Exported_Types + * @{ + */ + +typedef enum +{ + USB_OTG_HS_CORE_ID = 0, + USB_OTG_FS_CORE_ID = 1 +}USB_OTG_CORE_ID_TypeDef; +/** + * @} + */ + + +/** @defgroup USB_DEFINES_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_DEFINES_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_DEFINES_Exported_FunctionsPrototype + * @{ + */ +/** + * @} + */ + + +/** @defgroup Internal_Macro's + * @{ + */ +#define USB_OTG_READ_REG32(reg) (*(__IO uint32_t *)(reg)) +#define USB_OTG_WRITE_REG32(reg,value) (*(__IO uint32_t *)(reg) = (value)) +#define USB_OTG_MODIFY_REG32(reg,clear_mask,set_mask) \ + USB_OTG_WRITE_REG32((reg), (((USB_OTG_READ_REG32(reg)) & ~(clear_mask)) | (set_mask)) ) + +/******************************************************************************** + ENUMERATION TYPE +********************************************************************************/ +enum USB_OTG_SPEED { + USB_SPEED_UNKNOWN = 0, + USB_SPEED_LOW, + USB_SPEED_FULL, + USB_SPEED_HIGH +}; + +#endif /* __USB_DEFINES__H__ */ + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_hcd.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_hcd.h index 4136f5a65..9462d284e 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_hcd.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_hcd.h @@ -1,110 +1,110 @@ -/** - ****************************************************************************** - * @file usb_hcd.h - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief Host layer Header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_HCD_H__ -#define __USB_HCD_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_regs.h" -#include "usb_core.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_HCD - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_HCD_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_HCD_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_HCD_Exported_FunctionsPrototype - * @{ - */ -uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID); -uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , - uint8_t hc_num); -uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , - uint8_t hc_num) ; -uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev); -uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev); -uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev); -uint32_t HCD_IsPortEnabled (USB_OTG_CORE_HANDLE *pdev); - -uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) ; -URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num); -uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num); -HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) ; -/** - * @} - */ - -#endif //__USB_HCD_H__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usb_hcd.h + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief Host layer Header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_HCD_H__ +#define __USB_HCD_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_regs.h" +#include "usb_core.h" + + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_HCD + * @brief This file is the + * @{ + */ + + +/** @defgroup USB_HCD_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_HCD_Exported_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_HCD_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_HCD_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_HCD_Exported_FunctionsPrototype + * @{ + */ +uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev , + USB_OTG_CORE_ID_TypeDef coreID); +uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , + uint8_t hc_num); +uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , + uint8_t hc_num) ; +uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev); +uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev); +uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev); +uint32_t HCD_IsPortEnabled (USB_OTG_CORE_HANDLE *pdev); + +uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) ; +URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num); +uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num); +HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) ; +/** + * @} + */ + +#endif //__USB_HCD_H__ + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_hcd_int.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_hcd_int.h index 2219407a1..5ce74d36b 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_hcd_int.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_hcd_int.h @@ -1,143 +1,143 @@ -/** - ****************************************************************************** - * @file usb_hcd_int.h - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief Peripheral Device Interface Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __HCD_INT_H__ -#define __HCD_INT_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_hcd.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_HCD_INT - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_HCD_INT_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_INT_Exported_Types - * @{ - */ - -typedef struct _USBH_HCD_INT -{ - uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* DevPortEnabled) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* DevPortDisabled) (USB_OTG_CORE_HANDLE *pdev); - -}USBH_HCD_INT_cb_TypeDef; - -extern USBH_HCD_INT_cb_TypeDef *USBH_HCD_INT_fops; -/** - * @} - */ - - -/** @defgroup USB_HCD_INT_Exported_Macros - * @{ - */ - -#define CLEAR_HC_INT(HC_REGS, intr) \ - {\ - USB_OTG_HCINTn_TypeDef hcint_clear; \ - hcint_clear.d32 = 0; \ - hcint_clear.b.intr = 1; \ - USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\ - }\ - -#define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \ - INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ - INTMSK.b.chhltd = 0; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);} - -#define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \ - INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ - INTMSK.b.chhltd = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);} - -#define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \ - INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ - INTMSK.b.ack = 0; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, GINTMSK.d32);} - -#define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef INTMSK; \ - INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ - INTMSK.b.ack = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);} - -/** - * @} - */ - -/** @defgroup USB_HCD_INT_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_HCD_INT_Exported_FunctionsPrototype - * @{ - */ -/* Callbacks handler */ -void ConnectCallback_Handler(USB_OTG_CORE_HANDLE *pdev); -void Disconnect_Callback_Handler(USB_OTG_CORE_HANDLE *pdev); -void Overcurrent_Callback_Handler(USB_OTG_CORE_HANDLE *pdev); -uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - - - -#endif //__HCD_INT_H__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usb_hcd_int.h + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief Peripheral Device Interface Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HCD_INT_H__ +#define __HCD_INT_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_hcd.h" + + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_HCD_INT + * @brief This file is the + * @{ + */ + + +/** @defgroup USB_HCD_INT_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_HCD_INT_Exported_Types + * @{ + */ + +typedef struct _USBH_HCD_INT +{ + uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* DevPortEnabled) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* DevPortDisabled) (USB_OTG_CORE_HANDLE *pdev); + +}USBH_HCD_INT_cb_TypeDef; + +extern USBH_HCD_INT_cb_TypeDef *USBH_HCD_INT_fops; +/** + * @} + */ + + +/** @defgroup USB_HCD_INT_Exported_Macros + * @{ + */ + +#define CLEAR_HC_INT(HC_REGS, intr) \ + {\ + USB_OTG_HCINTn_TypeDef hcint_clear; \ + hcint_clear.d32 = 0; \ + hcint_clear.b.intr = 1; \ + USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\ + }\ + +#define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \ + INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ + INTMSK.b.chhltd = 0; \ + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);} + +#define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \ + INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ + INTMSK.b.chhltd = 1; \ + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);} + +#define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \ + INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ + INTMSK.b.ack = 0; \ + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, GINTMSK.d32);} + +#define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef INTMSK; \ + INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ + INTMSK.b.ack = 1; \ + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);} + +/** + * @} + */ + +/** @defgroup USB_HCD_INT_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_HCD_INT_Exported_FunctionsPrototype + * @{ + */ +/* Callbacks handler */ +void ConnectCallback_Handler(USB_OTG_CORE_HANDLE *pdev); +void Disconnect_Callback_Handler(USB_OTG_CORE_HANDLE *pdev); +void Overcurrent_Callback_Handler(USB_OTG_CORE_HANDLE *pdev); +uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); + +/** + * @} + */ + + + +#endif //__HCD_INT_H__ + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_otg.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_otg.h index 34ca6b16b..44be2cf36 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_otg.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_otg.h @@ -1,99 +1,99 @@ -/** - ****************************************************************************** - * @file usb_otg.h - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief OTG Core Header - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_OTG__ -#define __USB_OTG__ - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_OTG - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_OTG_Exported_Defines - * @{ - */ - - -void USB_OTG_InitiateSRP(void); -void USB_OTG_InitiateHNP(uint8_t state , uint8_t mode); -void USB_OTG_Switchback (USB_OTG_CORE_DEVICE *pdev); -uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_DEVICE *pdev); - -/** - * @} - */ - - -/** @defgroup USB_OTG_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_OTG_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_OTG_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USB_OTG__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usb_otg.h + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief OTG Core Header + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_OTG__ +#define __USB_OTG__ + + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_OTG + * @brief This file is the + * @{ + */ + + +/** @defgroup USB_OTG_Exported_Defines + * @{ + */ + + +void USB_OTG_InitiateSRP(void); +void USB_OTG_InitiateHNP(uint8_t state , uint8_t mode); +void USB_OTG_Switchback (USB_OTG_CORE_DEVICE *pdev); +uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_DEVICE *pdev); + +/** + * @} + */ + + +/** @defgroup USB_OTG_Exported_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_OTG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_OTG_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_OTG_Exported_FunctionsPrototype + * @{ + */ +/** + * @} + */ + + +#endif //__USB_OTG__ + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_regs.h b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_regs.h index e9c62080d..8a22d3a5f 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_regs.h +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/inc/usb_regs.h @@ -1,1189 +1,1189 @@ -/** - ****************************************************************************** - * @file usb_regs.h - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief hardware registers - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_OTG_REGS_H__ -#define __USB_OTG_REGS_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_REGS - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_REGS_Exported_Defines - * @{ - */ - -#define USB_OTG_HS_BASE_ADDR 0x40040000 -#define USB_OTG_FS_BASE_ADDR 0x50000000 - -#define USB_OTG_CORE_GLOBAL_REGS_OFFSET 0x000 -#define USB_OTG_DEV_GLOBAL_REG_OFFSET 0x800 -#define USB_OTG_DEV_IN_EP_REG_OFFSET 0x900 -#define USB_OTG_EP_REG_OFFSET 0x20 -#define USB_OTG_DEV_OUT_EP_REG_OFFSET 0xB00 -#define USB_OTG_HOST_GLOBAL_REG_OFFSET 0x400 -#define USB_OTG_HOST_PORT_REGS_OFFSET 0x440 -#define USB_OTG_HOST_CHAN_REGS_OFFSET 0x500 -#define USB_OTG_CHAN_REGS_OFFSET 0x20 -#define USB_OTG_PCGCCTL_OFFSET 0xE00 -#define USB_OTG_DATA_FIFO_OFFSET 0x1000 -#define USB_OTG_DATA_FIFO_SIZE 0x1000 - - -#define USB_OTG_MAX_TX_FIFOS 15 - -#define USB_OTG_HS_MAX_PACKET_SIZE 512 -#define USB_OTG_FS_MAX_PACKET_SIZE 64 -#define USB_OTG_MAX_EP0_SIZE 64 -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_Types - * @{ - */ - -/** @defgroup __USB_OTG_Core_register - * @{ - */ -typedef struct _USB_OTG_GREGS /* 000h */ -{ - __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/ - __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/ - __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/ - __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/ - __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/ - __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/ - __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/ - __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/ - __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/ - __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[USB_OTG_MAX_TX_FIFOS];/* dev Periodic Transmit FIFO */ -} -USB_OTG_GREGS; -/** - * @} - */ - - -/** @defgroup __device_Registers - * @{ - */ -typedef struct _USB_OTG_DREGS /* 800h */ -{ - __IO uint32_t DCFG; /* dev Configuration Register 800h*/ - __IO uint32_t DCTL; /* dev Control Register 804h*/ - __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ - uint32_t Reserved0C; /* Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ - __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ - __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ - __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ - __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ - __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ - __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ - __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ - __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ -} -USB_OTG_DREGS; -/** - * @} - */ - - -/** @defgroup __IN_Endpoint-Specific_Register - * @{ - */ -typedef struct _USB_OTG_INEPREGS -{ - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ -} -USB_OTG_INEPREGS; -/** - * @} - */ - - -/** @defgroup __OUT_Endpoint-Specific_Registers - * @{ - */ -typedef struct _USB_OTG_OUTEPREGS -{ - __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} -USB_OTG_OUTEPREGS; -/** - * @} - */ - - -/** @defgroup __Host_Mode_Register_Structures - * @{ - */ -typedef struct _USB_OTG_HREGS -{ - __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ -} -USB_OTG_HREGS; -/** - * @} - */ - - -/** @defgroup __Host_Channel_Specific_Registers - * @{ - */ -typedef struct _USB_OTG_HC_REGS -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} -USB_OTG_HC_REGS; -/** - * @} - */ - - -/** @defgroup __otg_Core_registers - * @{ - */ -typedef struct USB_OTG_core_regs /* 000h */ -{ - USB_OTG_GREGS *GREGS; - USB_OTG_DREGS *DREGS; - USB_OTG_HREGS *HREGS; - USB_OTG_INEPREGS *INEP_REGS[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_OUTEPREGS *OUTEP_REGS[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_HC_REGS *HC_REGS[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t *HPRT0; - __IO uint32_t *DFIFO[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t *PCGCCTL; -} -USB_OTG_CORE_REGS , *PUSB_OTG_CORE_REGS; -typedef union _USB_OTG_GOTGCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t sesreqscs : - 1; -uint32_t sesreq : - 1; -uint32_t Reserved2_7 : - 6; -uint32_t hstnegscs : - 1; -uint32_t hnpreq : - 1; -uint32_t hstsethnpen : - 1; -uint32_t devhnpen : - 1; -uint32_t Reserved12_15 : - 4; -uint32_t conidsts : - 1; -uint32_t dbct : - 1; -uint32_t asesvld : - 1; -uint32_t bsesvld : - 1; -uint32_t Reserved20_31 : - 12; - } - b; -} USB_OTG_GOTGCTL_TypeDef ; - -typedef union _USB_OTG_GOTGINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved0_1 : - 2; -uint32_t sesenddet : - 1; -uint32_t Reserved3_7 : - 5; -uint32_t sesreqsucstschng : - 1; -uint32_t hstnegsucstschng : - 1; -uint32_t reserver10_16 : - 7; -uint32_t hstnegdet : - 1; -uint32_t adevtoutchng : - 1; -uint32_t debdone : - 1; -uint32_t Reserved31_20 : - 12; - } - b; -} USB_OTG_GOTGINT_TypeDef ; -typedef union _USB_OTG_GAHBCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t glblintrmsk : - 1; -uint32_t hburstlen : - 4; -uint32_t dmaenable : - 1; -uint32_t Reserved : - 1; -uint32_t nptxfemplvl_txfemplvl : - 1; -uint32_t ptxfemplvl : - 1; -uint32_t Reserved9_31 : - 23; - } - b; -} USB_OTG_GAHBCFG_TypeDef ; -typedef union _USB_OTG_GUSBCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t toutcal : - 3; -uint32_t Reserved3_5 : - 3; -uint32_t physel : - 1; -uint32_t Reserved7 : - 1; -uint32_t srpcap : - 1; -uint32_t hnpcap : - 1; -uint32_t usbtrdtim : - 4; -uint32_t Reserved14 : - 1; -uint32_t phylpwrclksel : - 1; -uint32_t Reserved16 : - 1; -uint32_t ulpi_fsls : - 1; -uint32_t ulpi_auto_res : - 1; -uint32_t ulpi_clk_sus_m : - 1; -uint32_t ulpi_ext_vbus_drv : - 1; -uint32_t ulpi_int_vbus_ind : - 1; -uint32_t term_sel_dl_pulse : - 1; -uint32_t ulpi_ind_cpl : - 1; -uint32_t ulpi_passthrough : - 1; -uint32_t ulpi_protect_disable : - 1; -uint32_t Reserved26_28 : - 3; -uint32_t force_host : - 1; -uint32_t force_dev : - 1; -uint32_t corrupt_tx : - 1; - } - b; -} USB_OTG_GUSBCFG_TypeDef ; -typedef union _USB_OTG_GRSTCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t csftrst : - 1; -uint32_t hsftrst : - 1; -uint32_t hstfrm : - 1; -uint32_t Reserved3 : - 1; -uint32_t rxfflsh : - 1; -uint32_t txfflsh : - 1; -uint32_t txfnum : - 5; -uint32_t Reserved11_29 : - 19; -uint32_t dmareq : - 1; -uint32_t ahbidle : - 1; - } - b; -} USB_OTG_GRSTCTL_TypeDef ; -typedef union _USB_OTG_GINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved0 : - 1; -uint32_t modemismatch : - 1; -uint32_t otgintr : - 1; -uint32_t sofintr : - 1; -uint32_t rxstsqlvl : - 1; -uint32_t nptxfempty : - 1; -uint32_t ginnakeff : - 1; -uint32_t goutnakeff : - 1; -uint32_t Reserved8_9 : - 2; -uint32_t erlysuspend : - 1; -uint32_t usbsuspend : - 1; -uint32_t usbreset : - 1; -uint32_t enumdone : - 1; -uint32_t isooutdrop : - 1; -uint32_t eopframe : - 1; -uint32_t Reserved16 : - 1; -uint32_t epmismatch : - 1; -uint32_t inepintr : - 1; -uint32_t outepintr : - 1; -uint32_t incomplisoin : - 1; -uint32_t incomplisoout : - 1; -uint32_t Reserved22_23 : - 2; -uint32_t portintr : - 1; -uint32_t hcintr : - 1; -uint32_t ptxfempty : - 1; -uint32_t Reserved27 : - 1; -uint32_t conidstschng : - 1; -uint32_t disconnect : - 1; -uint32_t sessreqintr : - 1; -uint32_t wkupintr : - 1; - } - b; -} USB_OTG_GINTMSK_TypeDef ; -typedef union _USB_OTG_GINTSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t curmode : - 1; -uint32_t modemismatch : - 1; -uint32_t otgintr : - 1; -uint32_t sofintr : - 1; -uint32_t rxstsqlvl : - 1; -uint32_t nptxfempty : - 1; -uint32_t ginnakeff : - 1; -uint32_t goutnakeff : - 1; -uint32_t Reserved8_9 : - 2; -uint32_t erlysuspend : - 1; -uint32_t usbsuspend : - 1; -uint32_t usbreset : - 1; -uint32_t enumdone : - 1; -uint32_t isooutdrop : - 1; -uint32_t eopframe : - 1; -uint32_t Reserved16_17 : - 2; -uint32_t inepint: - 1; -uint32_t outepintr : - 1; -uint32_t incomplisoin : - 1; -uint32_t incomplisoout : - 1; -uint32_t Reserved22_23 : - 2; -uint32_t portintr : - 1; -uint32_t hcintr : - 1; -uint32_t ptxfempty : - 1; -uint32_t Reserved27 : - 1; -uint32_t conidstschng : - 1; -uint32_t disconnect : - 1; -uint32_t sessreqintr : - 1; -uint32_t wkupintr : - 1; - } - b; -} USB_OTG_GINTSTS_TypeDef ; -typedef union _USB_OTG_DRXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t epnum : - 4; -uint32_t bcnt : - 11; -uint32_t dpid : - 2; -uint32_t pktsts : - 4; -uint32_t fn : - 4; -uint32_t Reserved : - 7; - } - b; -} USB_OTG_DRXSTS_TypeDef ; -typedef union _USB_OTG_GRXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chnum : - 4; -uint32_t bcnt : - 11; -uint32_t dpid : - 2; -uint32_t pktsts : - 4; -uint32_t Reserved : - 11; - } - b; -} USB_OTG_GRXFSTS_TypeDef ; -typedef union _USB_OTG_FSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t startaddr : - 16; -uint32_t depth : - 16; - } - b; -} USB_OTG_FSIZ_TypeDef ; -typedef union _USB_OTG_HNPTXSTS_TypeDef -{ - uint32_t d32; - struct - { - uint32_t nptxfspcavail : - 16; - uint32_t nptxqspcavail : - 8; - struct - { - uint32_t terminate : - 1; - uint32_t token : - 2; - uint32_t chnum : - 4; - } nptxqtop; - uint32_t Reserved : - 1; - } - b; -} USB_OTG_HNPTXSTS_TypeDef ; -typedef union _USB_OTG_DTXFSTSn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t txfspcavail : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_DTXFSTSn_TypeDef ; - -typedef union _USB_OTG_GCCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved_in : - 16; -uint32_t pwdn : - 1; -uint32_t Reserved_17 : - 1; -uint32_t vbussensingA : - 1; -uint32_t vbussensingB : - 1; -uint32_t sofouten : - 1; -uint32_t disablevbussensing : - 1; -uint32_t Reserved_out : - 10; - } - b; -} USB_OTG_GCCFG_TypeDef ; - -typedef union _USB_OTG_DCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t devspd : - 2; -uint32_t nzstsouthshk : - 1; -uint32_t Reserved3 : - 1; -uint32_t devaddr : - 7; -uint32_t perfrint : - 2; -uint32_t Reserved12_31 : - 19; - } - b; -} USB_OTG_DCFG_TypeDef ; -typedef union _USB_OTG_DCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t rmtwkupsig : - 1; -uint32_t sftdiscon : - 1; -uint32_t gnpinnaksts : - 1; -uint32_t goutnaksts : - 1; -uint32_t tstctl : - 3; -uint32_t sgnpinnak : - 1; -uint32_t cgnpinnak : - 1; -uint32_t sgoutnak : - 1; -uint32_t cgoutnak : - 1; -uint32_t poprg_done : - 1; -uint32_t Reserved : - 20; - } - b; -} USB_OTG_DCTL_TypeDef ; -typedef union _USB_OTG_DSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t suspsts : - 1; -uint32_t enumspd : - 2; -uint32_t errticerr : - 1; -uint32_t Reserved4_7: - 4; -uint32_t soffn : - 14; -uint32_t Reserved22_31 : - 10; - } - b; -} USB_OTG_DSTS_TypeDef ; -typedef union _USB_OTG_DIEPINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t epdisabled : - 1; -uint32_t Reserved2 : - 1; -uint32_t timeout : - 1; -uint32_t intktxfemp : - 1; -uint32_t Reserved5 : - 1; -uint32_t inepnakeff : - 1; -uint32_t emptyintr : - 1; -uint32_t txfifoundrn : - 1; -uint32_t Reserved14_31 : - 23; - } - b; -} USB_OTG_DIEPINTn_TypeDef ; -typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPMSK_TypeDef ; -typedef union _USB_OTG_DOEPINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t epdisabled : - 1; -uint32_t Reserved2 : - 1; -uint32_t setup : - 1; -uint32_t Reserved04_31 : - 28; - } - b; -} USB_OTG_DOEPINTn_TypeDef ; -typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPMSK_TypeDef ; - -typedef union _USB_OTG_DAINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t in : - 16; -uint32_t out : - 16; - } - ep; -} USB_OTG_DAINT_TypeDef ; - -typedef union _USB_OTG_DTHRCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t non_iso_thr_en : - 1; -uint32_t iso_thr_en : - 1; -uint32_t tx_thr_len : - 9; -uint32_t Reserved11_15 : - 5; -uint32_t rx_thr_en : - 1; -uint32_t rx_thr_len : - 9; -uint32_t Reserved26 : - 1; -uint32_t arp_en : - 1; -uint32_t Reserved28_31 : - 4; - } - b; -} USB_OTG_DTHRCTL_TypeDef ; -typedef union _USB_OTG_DEPCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t mps : - 11; -uint32_t reserved : - 4; -uint32_t usbactep : - 1; -uint32_t dpid : - 1; -uint32_t naksts : - 1; -uint32_t eptype : - 2; -uint32_t snp : - 1; -uint32_t stall : - 1; -uint32_t txfnum : - 4; -uint32_t cnak : - 1; -uint32_t snak : - 1; -uint32_t setd0pid : - 1; -uint32_t setd1pid : - 1; -uint32_t epdis : - 1; -uint32_t epena : - 1; - } - b; -} USB_OTG_DEPCTL_TypeDef ; -typedef union _USB_OTG_DEPXFRSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 19; -uint32_t pktcnt : - 10; -uint32_t mc : - 2; -uint32_t Reserved : - 1; - } - b; -} USB_OTG_DEPXFRSIZ_TypeDef ; -typedef union _USB_OTG_DEP0XFRSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 7; -uint32_t Reserved7_18 : - 12; -uint32_t pktcnt : - 1; -uint32_t Reserved20_28 : - 9; -uint32_t supcnt : - 2; -uint32_t Reserved31 : - 1; - } - b; -} USB_OTG_DEP0XFRSIZ_TypeDef ; -typedef union _USB_OTG_HCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t fslspclksel : - 2; -uint32_t fslssupp : - 1; - } - b; -} USB_OTG_HCFG_TypeDef ; -typedef union _USB_OTG_HFRMINTRVL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t frint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HFRMINTRVL_TypeDef ; - -typedef union _USB_OTG_HFNUM_TypeDef -{ - uint32_t d32; - struct - { -uint32_t frnum : - 16; -uint32_t frrem : - 16; - } - b; -} USB_OTG_HFNUM_TypeDef ; -typedef union _USB_OTG_HPTXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t ptxfspcavail : - 16; -uint32_t ptxqspcavail : - 8; - struct - { - uint32_t terminate : - 1; - uint32_t token : - 2; - uint32_t chnum : - 4; - uint32_t odd_even : - 1; - } ptxqtop; - } - b; -} USB_OTG_HPTXSTS_TypeDef ; -typedef union _USB_OTG_HPRT0_TypeDef -{ - uint32_t d32; - struct - { -uint32_t prtconnsts : - 1; -uint32_t prtconndet : - 1; -uint32_t prtena : - 1; -uint32_t prtenchng : - 1; -uint32_t prtovrcurract : - 1; -uint32_t prtovrcurrchng : - 1; -uint32_t prtres : - 1; -uint32_t prtsusp : - 1; -uint32_t prtrst : - 1; -uint32_t Reserved9 : - 1; -uint32_t prtlnsts : - 2; -uint32_t prtpwr : - 1; -uint32_t prttstctl : - 4; -uint32_t prtspd : - 2; -uint32_t Reserved19_31 : - 13; - } - b; -} USB_OTG_HPRT0_TypeDef ; -typedef union _USB_OTG_HAINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HAINT_TypeDef ; -typedef union _USB_OTG_HAINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HAINTMSK_TypeDef ; -typedef union _USB_OTG_HCCHAR_TypeDef -{ - uint32_t d32; - struct - { -uint32_t mps : - 11; -uint32_t epnum : - 4; -uint32_t epdir : - 1; -uint32_t Reserved : - 1; -uint32_t lspddev : - 1; -uint32_t eptype : - 2; -uint32_t multicnt : - 2; -uint32_t devaddr : - 7; -uint32_t oddfrm : - 1; -uint32_t chdis : - 1; -uint32_t chen : - 1; - } - b; -} USB_OTG_HCCHAR_TypeDef ; -typedef union _USB_OTG_HCSPLT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t prtaddr : - 7; -uint32_t hubaddr : - 7; -uint32_t xactpos : - 2; -uint32_t compsplt : - 1; -uint32_t Reserved : - 14; -uint32_t spltena : - 1; - } - b; -} USB_OTG_HCSPLT_TypeDef ; -typedef union _USB_OTG_HCINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t chhltd : - 1; -uint32_t ahberr : - 1; -uint32_t stall : - 1; -uint32_t nak : - 1; -uint32_t ack : - 1; -uint32_t nyet : - 1; -uint32_t xacterr : - 1; -uint32_t bblerr : - 1; -uint32_t frmovrun : - 1; -uint32_t datatglerr : - 1; -uint32_t Reserved : - 21; - } - b; -} USB_OTG_HCINTn_TypeDef ; -typedef union _USB_OTG_HCTSIZn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 19; -uint32_t pktcnt : - 10; -uint32_t pid : - 2; -uint32_t dopng : - 1; - } - b; -} USB_OTG_HCTSIZn_TypeDef ; -typedef union _USB_OTG_HCINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t chhltd : - 1; -uint32_t ahberr : - 1; -uint32_t stall : - 1; -uint32_t nak : - 1; -uint32_t ack : - 1; -uint32_t nyet : - 1; -uint32_t xacterr : - 1; -uint32_t bblerr : - 1; -uint32_t frmovrun : - 1; -uint32_t datatglerr : - 1; -uint32_t Reserved : - 21; - } - b; -} USB_OTG_HCINTMSK_TypeDef ; - -typedef union _USB_OTG_PCGCCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t stoppclk : - 1; -uint32_t gatehclk : - 1; -uint32_t Reserved2_3 : - 2; -uint32_t phy_susp : - 1; -uint32_t Reserved5_31 : - 27; - } - b; -} USB_OTG_PCGCCTL_TypeDef ; - -/** - * @} - */ - - -/** @defgroup USB_REGS_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif /* __USB_OTG_REGS_H__ */ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usb_regs.h + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief hardware registers + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_OTG_REGS_H__ +#define __USB_OTG_REGS_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_REGS + * @brief This file is the + * @{ + */ + + +/** @defgroup USB_REGS_Exported_Defines + * @{ + */ + +#define USB_OTG_HS_BASE_ADDR 0x40040000 +#define USB_OTG_FS_BASE_ADDR 0x50000000 + +#define USB_OTG_CORE_GLOBAL_REGS_OFFSET 0x000 +#define USB_OTG_DEV_GLOBAL_REG_OFFSET 0x800 +#define USB_OTG_DEV_IN_EP_REG_OFFSET 0x900 +#define USB_OTG_EP_REG_OFFSET 0x20 +#define USB_OTG_DEV_OUT_EP_REG_OFFSET 0xB00 +#define USB_OTG_HOST_GLOBAL_REG_OFFSET 0x400 +#define USB_OTG_HOST_PORT_REGS_OFFSET 0x440 +#define USB_OTG_HOST_CHAN_REGS_OFFSET 0x500 +#define USB_OTG_CHAN_REGS_OFFSET 0x20 +#define USB_OTG_PCGCCTL_OFFSET 0xE00 +#define USB_OTG_DATA_FIFO_OFFSET 0x1000 +#define USB_OTG_DATA_FIFO_SIZE 0x1000 + + +#define USB_OTG_MAX_TX_FIFOS 15 + +#define USB_OTG_HS_MAX_PACKET_SIZE 512 +#define USB_OTG_FS_MAX_PACKET_SIZE 64 +#define USB_OTG_MAX_EP0_SIZE 64 +/** + * @} + */ + +/** @defgroup USB_REGS_Exported_Types + * @{ + */ + +/** @defgroup __USB_OTG_Core_register + * @{ + */ +typedef struct _USB_OTG_GREGS /* 000h */ +{ + __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/ + __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/ + __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/ + __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/ + __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/ + __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/ + __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/ + __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/ + __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/ + __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ + uint32_t Reserved30[2]; /* Reserved 030h*/ + __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ + __IO uint32_t CID; /* User ID Register 03Ch*/ + uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ + __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[USB_OTG_MAX_TX_FIFOS];/* dev Periodic Transmit FIFO */ +} +USB_OTG_GREGS; +/** + * @} + */ + + +/** @defgroup __device_Registers + * @{ + */ +typedef struct _USB_OTG_DREGS /* 800h */ +{ + __IO uint32_t DCFG; /* dev Configuration Register 800h*/ + __IO uint32_t DCTL; /* dev Control Register 804h*/ + __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ + uint32_t Reserved0C; /* Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ + __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ + __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ + __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved9; /* Reserved 824h*/ + __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ + __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ + __IO uint32_t DTHRCTL; /* dev thr 830h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ + __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ + uint32_t Reserved40; /* dedicated EP mask 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ +} +USB_OTG_DREGS; +/** + * @} + */ + + +/** @defgroup __IN_Endpoint-Specific_Register + * @{ + */ +typedef struct _USB_OTG_INEPREGS +{ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ + __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} +USB_OTG_INEPREGS; +/** + * @} + */ + + +/** @defgroup __OUT_Endpoint-Specific_Registers + * @{ + */ +typedef struct _USB_OTG_OUTEPREGS +{ + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} +USB_OTG_OUTEPREGS; +/** + * @} + */ + + +/** @defgroup __Host_Mode_Register_Structures + * @{ + */ +typedef struct _USB_OTG_HREGS +{ + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} +USB_OTG_HREGS; +/** + * @} + */ + + +/** @defgroup __Host_Channel_Specific_Registers + * @{ + */ +typedef struct _USB_OTG_HC_REGS +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} +USB_OTG_HC_REGS; +/** + * @} + */ + + +/** @defgroup __otg_Core_registers + * @{ + */ +typedef struct USB_OTG_core_regs /* 000h */ +{ + USB_OTG_GREGS *GREGS; + USB_OTG_DREGS *DREGS; + USB_OTG_HREGS *HREGS; + USB_OTG_INEPREGS *INEP_REGS[USB_OTG_MAX_TX_FIFOS]; + USB_OTG_OUTEPREGS *OUTEP_REGS[USB_OTG_MAX_TX_FIFOS]; + USB_OTG_HC_REGS *HC_REGS[USB_OTG_MAX_TX_FIFOS]; + __IO uint32_t *HPRT0; + __IO uint32_t *DFIFO[USB_OTG_MAX_TX_FIFOS]; + __IO uint32_t *PCGCCTL; +} +USB_OTG_CORE_REGS , *PUSB_OTG_CORE_REGS; +typedef union _USB_OTG_GOTGCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t sesreqscs : + 1; +uint32_t sesreq : + 1; +uint32_t Reserved2_7 : + 6; +uint32_t hstnegscs : + 1; +uint32_t hnpreq : + 1; +uint32_t hstsethnpen : + 1; +uint32_t devhnpen : + 1; +uint32_t Reserved12_15 : + 4; +uint32_t conidsts : + 1; +uint32_t dbct : + 1; +uint32_t asesvld : + 1; +uint32_t bsesvld : + 1; +uint32_t Reserved20_31 : + 12; + } + b; +} USB_OTG_GOTGCTL_TypeDef ; + +typedef union _USB_OTG_GOTGINT_TypeDef +{ + uint32_t d32; + struct + { +uint32_t Reserved0_1 : + 2; +uint32_t sesenddet : + 1; +uint32_t Reserved3_7 : + 5; +uint32_t sesreqsucstschng : + 1; +uint32_t hstnegsucstschng : + 1; +uint32_t reserver10_16 : + 7; +uint32_t hstnegdet : + 1; +uint32_t adevtoutchng : + 1; +uint32_t debdone : + 1; +uint32_t Reserved31_20 : + 12; + } + b; +} USB_OTG_GOTGINT_TypeDef ; +typedef union _USB_OTG_GAHBCFG_TypeDef +{ + uint32_t d32; + struct + { +uint32_t glblintrmsk : + 1; +uint32_t hburstlen : + 4; +uint32_t dmaenable : + 1; +uint32_t Reserved : + 1; +uint32_t nptxfemplvl_txfemplvl : + 1; +uint32_t ptxfemplvl : + 1; +uint32_t Reserved9_31 : + 23; + } + b; +} USB_OTG_GAHBCFG_TypeDef ; +typedef union _USB_OTG_GUSBCFG_TypeDef +{ + uint32_t d32; + struct + { +uint32_t toutcal : + 3; +uint32_t Reserved3_5 : + 3; +uint32_t physel : + 1; +uint32_t Reserved7 : + 1; +uint32_t srpcap : + 1; +uint32_t hnpcap : + 1; +uint32_t usbtrdtim : + 4; +uint32_t Reserved14 : + 1; +uint32_t phylpwrclksel : + 1; +uint32_t Reserved16 : + 1; +uint32_t ulpi_fsls : + 1; +uint32_t ulpi_auto_res : + 1; +uint32_t ulpi_clk_sus_m : + 1; +uint32_t ulpi_ext_vbus_drv : + 1; +uint32_t ulpi_int_vbus_ind : + 1; +uint32_t term_sel_dl_pulse : + 1; +uint32_t ulpi_ind_cpl : + 1; +uint32_t ulpi_passthrough : + 1; +uint32_t ulpi_protect_disable : + 1; +uint32_t Reserved26_28 : + 3; +uint32_t force_host : + 1; +uint32_t force_dev : + 1; +uint32_t corrupt_tx : + 1; + } + b; +} USB_OTG_GUSBCFG_TypeDef ; +typedef union _USB_OTG_GRSTCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t csftrst : + 1; +uint32_t hsftrst : + 1; +uint32_t hstfrm : + 1; +uint32_t Reserved3 : + 1; +uint32_t rxfflsh : + 1; +uint32_t txfflsh : + 1; +uint32_t txfnum : + 5; +uint32_t Reserved11_29 : + 19; +uint32_t dmareq : + 1; +uint32_t ahbidle : + 1; + } + b; +} USB_OTG_GRSTCTL_TypeDef ; +typedef union _USB_OTG_GINTMSK_TypeDef +{ + uint32_t d32; + struct + { +uint32_t Reserved0 : + 1; +uint32_t modemismatch : + 1; +uint32_t otgintr : + 1; +uint32_t sofintr : + 1; +uint32_t rxstsqlvl : + 1; +uint32_t nptxfempty : + 1; +uint32_t ginnakeff : + 1; +uint32_t goutnakeff : + 1; +uint32_t Reserved8_9 : + 2; +uint32_t erlysuspend : + 1; +uint32_t usbsuspend : + 1; +uint32_t usbreset : + 1; +uint32_t enumdone : + 1; +uint32_t isooutdrop : + 1; +uint32_t eopframe : + 1; +uint32_t Reserved16 : + 1; +uint32_t epmismatch : + 1; +uint32_t inepintr : + 1; +uint32_t outepintr : + 1; +uint32_t incomplisoin : + 1; +uint32_t incomplisoout : + 1; +uint32_t Reserved22_23 : + 2; +uint32_t portintr : + 1; +uint32_t hcintr : + 1; +uint32_t ptxfempty : + 1; +uint32_t Reserved27 : + 1; +uint32_t conidstschng : + 1; +uint32_t disconnect : + 1; +uint32_t sessreqintr : + 1; +uint32_t wkupintr : + 1; + } + b; +} USB_OTG_GINTMSK_TypeDef ; +typedef union _USB_OTG_GINTSTS_TypeDef +{ + uint32_t d32; + struct + { +uint32_t curmode : + 1; +uint32_t modemismatch : + 1; +uint32_t otgintr : + 1; +uint32_t sofintr : + 1; +uint32_t rxstsqlvl : + 1; +uint32_t nptxfempty : + 1; +uint32_t ginnakeff : + 1; +uint32_t goutnakeff : + 1; +uint32_t Reserved8_9 : + 2; +uint32_t erlysuspend : + 1; +uint32_t usbsuspend : + 1; +uint32_t usbreset : + 1; +uint32_t enumdone : + 1; +uint32_t isooutdrop : + 1; +uint32_t eopframe : + 1; +uint32_t Reserved16_17 : + 2; +uint32_t inepint: + 1; +uint32_t outepintr : + 1; +uint32_t incomplisoin : + 1; +uint32_t incomplisoout : + 1; +uint32_t Reserved22_23 : + 2; +uint32_t portintr : + 1; +uint32_t hcintr : + 1; +uint32_t ptxfempty : + 1; +uint32_t Reserved27 : + 1; +uint32_t conidstschng : + 1; +uint32_t disconnect : + 1; +uint32_t sessreqintr : + 1; +uint32_t wkupintr : + 1; + } + b; +} USB_OTG_GINTSTS_TypeDef ; +typedef union _USB_OTG_DRXSTS_TypeDef +{ + uint32_t d32; + struct + { +uint32_t epnum : + 4; +uint32_t bcnt : + 11; +uint32_t dpid : + 2; +uint32_t pktsts : + 4; +uint32_t fn : + 4; +uint32_t Reserved : + 7; + } + b; +} USB_OTG_DRXSTS_TypeDef ; +typedef union _USB_OTG_GRXSTS_TypeDef +{ + uint32_t d32; + struct + { +uint32_t chnum : + 4; +uint32_t bcnt : + 11; +uint32_t dpid : + 2; +uint32_t pktsts : + 4; +uint32_t Reserved : + 11; + } + b; +} USB_OTG_GRXFSTS_TypeDef ; +typedef union _USB_OTG_FSIZ_TypeDef +{ + uint32_t d32; + struct + { +uint32_t startaddr : + 16; +uint32_t depth : + 16; + } + b; +} USB_OTG_FSIZ_TypeDef ; +typedef union _USB_OTG_HNPTXSTS_TypeDef +{ + uint32_t d32; + struct + { + uint32_t nptxfspcavail : + 16; + uint32_t nptxqspcavail : + 8; + struct + { + uint32_t terminate : + 1; + uint32_t token : + 2; + uint32_t chnum : + 4; + } nptxqtop; + uint32_t Reserved : + 1; + } + b; +} USB_OTG_HNPTXSTS_TypeDef ; +typedef union _USB_OTG_DTXFSTSn_TypeDef +{ + uint32_t d32; + struct + { +uint32_t txfspcavail : + 16; +uint32_t Reserved : + 16; + } + b; +} USB_OTG_DTXFSTSn_TypeDef ; + +typedef union _USB_OTG_GCCFG_TypeDef +{ + uint32_t d32; + struct + { +uint32_t Reserved_in : + 16; +uint32_t pwdn : + 1; +uint32_t Reserved_17 : + 1; +uint32_t vbussensingA : + 1; +uint32_t vbussensingB : + 1; +uint32_t sofouten : + 1; +uint32_t disablevbussensing : + 1; +uint32_t Reserved_out : + 10; + } + b; +} USB_OTG_GCCFG_TypeDef ; + +typedef union _USB_OTG_DCFG_TypeDef +{ + uint32_t d32; + struct + { +uint32_t devspd : + 2; +uint32_t nzstsouthshk : + 1; +uint32_t Reserved3 : + 1; +uint32_t devaddr : + 7; +uint32_t perfrint : + 2; +uint32_t Reserved12_31 : + 19; + } + b; +} USB_OTG_DCFG_TypeDef ; +typedef union _USB_OTG_DCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t rmtwkupsig : + 1; +uint32_t sftdiscon : + 1; +uint32_t gnpinnaksts : + 1; +uint32_t goutnaksts : + 1; +uint32_t tstctl : + 3; +uint32_t sgnpinnak : + 1; +uint32_t cgnpinnak : + 1; +uint32_t sgoutnak : + 1; +uint32_t cgoutnak : + 1; +uint32_t poprg_done : + 1; +uint32_t Reserved : + 20; + } + b; +} USB_OTG_DCTL_TypeDef ; +typedef union _USB_OTG_DSTS_TypeDef +{ + uint32_t d32; + struct + { +uint32_t suspsts : + 1; +uint32_t enumspd : + 2; +uint32_t errticerr : + 1; +uint32_t Reserved4_7: + 4; +uint32_t soffn : + 14; +uint32_t Reserved22_31 : + 10; + } + b; +} USB_OTG_DSTS_TypeDef ; +typedef union _USB_OTG_DIEPINTn_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfercompl : + 1; +uint32_t epdisabled : + 1; +uint32_t Reserved2 : + 1; +uint32_t timeout : + 1; +uint32_t intktxfemp : + 1; +uint32_t Reserved5 : + 1; +uint32_t inepnakeff : + 1; +uint32_t emptyintr : + 1; +uint32_t txfifoundrn : + 1; +uint32_t Reserved14_31 : + 23; + } + b; +} USB_OTG_DIEPINTn_TypeDef ; +typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPMSK_TypeDef ; +typedef union _USB_OTG_DOEPINTn_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfercompl : + 1; +uint32_t epdisabled : + 1; +uint32_t Reserved2 : + 1; +uint32_t setup : + 1; +uint32_t Reserved04_31 : + 28; + } + b; +} USB_OTG_DOEPINTn_TypeDef ; +typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPMSK_TypeDef ; + +typedef union _USB_OTG_DAINT_TypeDef +{ + uint32_t d32; + struct + { +uint32_t in : + 16; +uint32_t out : + 16; + } + ep; +} USB_OTG_DAINT_TypeDef ; + +typedef union _USB_OTG_DTHRCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t non_iso_thr_en : + 1; +uint32_t iso_thr_en : + 1; +uint32_t tx_thr_len : + 9; +uint32_t Reserved11_15 : + 5; +uint32_t rx_thr_en : + 1; +uint32_t rx_thr_len : + 9; +uint32_t Reserved26 : + 1; +uint32_t arp_en : + 1; +uint32_t Reserved28_31 : + 4; + } + b; +} USB_OTG_DTHRCTL_TypeDef ; +typedef union _USB_OTG_DEPCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t mps : + 11; +uint32_t reserved : + 4; +uint32_t usbactep : + 1; +uint32_t dpid : + 1; +uint32_t naksts : + 1; +uint32_t eptype : + 2; +uint32_t snp : + 1; +uint32_t stall : + 1; +uint32_t txfnum : + 4; +uint32_t cnak : + 1; +uint32_t snak : + 1; +uint32_t setd0pid : + 1; +uint32_t setd1pid : + 1; +uint32_t epdis : + 1; +uint32_t epena : + 1; + } + b; +} USB_OTG_DEPCTL_TypeDef ; +typedef union _USB_OTG_DEPXFRSIZ_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfersize : + 19; +uint32_t pktcnt : + 10; +uint32_t mc : + 2; +uint32_t Reserved : + 1; + } + b; +} USB_OTG_DEPXFRSIZ_TypeDef ; +typedef union _USB_OTG_DEP0XFRSIZ_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfersize : + 7; +uint32_t Reserved7_18 : + 12; +uint32_t pktcnt : + 1; +uint32_t Reserved20_28 : + 9; +uint32_t supcnt : + 2; +uint32_t Reserved31 : + 1; + } + b; +} USB_OTG_DEP0XFRSIZ_TypeDef ; +typedef union _USB_OTG_HCFG_TypeDef +{ + uint32_t d32; + struct + { +uint32_t fslspclksel : + 2; +uint32_t fslssupp : + 1; + } + b; +} USB_OTG_HCFG_TypeDef ; +typedef union _USB_OTG_HFRMINTRVL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t frint : + 16; +uint32_t Reserved : + 16; + } + b; +} USB_OTG_HFRMINTRVL_TypeDef ; + +typedef union _USB_OTG_HFNUM_TypeDef +{ + uint32_t d32; + struct + { +uint32_t frnum : + 16; +uint32_t frrem : + 16; + } + b; +} USB_OTG_HFNUM_TypeDef ; +typedef union _USB_OTG_HPTXSTS_TypeDef +{ + uint32_t d32; + struct + { +uint32_t ptxfspcavail : + 16; +uint32_t ptxqspcavail : + 8; + struct + { + uint32_t terminate : + 1; + uint32_t token : + 2; + uint32_t chnum : + 4; + uint32_t odd_even : + 1; + } ptxqtop; + } + b; +} USB_OTG_HPTXSTS_TypeDef ; +typedef union _USB_OTG_HPRT0_TypeDef +{ + uint32_t d32; + struct + { +uint32_t prtconnsts : + 1; +uint32_t prtconndet : + 1; +uint32_t prtena : + 1; +uint32_t prtenchng : + 1; +uint32_t prtovrcurract : + 1; +uint32_t prtovrcurrchng : + 1; +uint32_t prtres : + 1; +uint32_t prtsusp : + 1; +uint32_t prtrst : + 1; +uint32_t Reserved9 : + 1; +uint32_t prtlnsts : + 2; +uint32_t prtpwr : + 1; +uint32_t prttstctl : + 4; +uint32_t prtspd : + 2; +uint32_t Reserved19_31 : + 13; + } + b; +} USB_OTG_HPRT0_TypeDef ; +typedef union _USB_OTG_HAINT_TypeDef +{ + uint32_t d32; + struct + { +uint32_t chint : + 16; +uint32_t Reserved : + 16; + } + b; +} USB_OTG_HAINT_TypeDef ; +typedef union _USB_OTG_HAINTMSK_TypeDef +{ + uint32_t d32; + struct + { +uint32_t chint : + 16; +uint32_t Reserved : + 16; + } + b; +} USB_OTG_HAINTMSK_TypeDef ; +typedef union _USB_OTG_HCCHAR_TypeDef +{ + uint32_t d32; + struct + { +uint32_t mps : + 11; +uint32_t epnum : + 4; +uint32_t epdir : + 1; +uint32_t Reserved : + 1; +uint32_t lspddev : + 1; +uint32_t eptype : + 2; +uint32_t multicnt : + 2; +uint32_t devaddr : + 7; +uint32_t oddfrm : + 1; +uint32_t chdis : + 1; +uint32_t chen : + 1; + } + b; +} USB_OTG_HCCHAR_TypeDef ; +typedef union _USB_OTG_HCSPLT_TypeDef +{ + uint32_t d32; + struct + { +uint32_t prtaddr : + 7; +uint32_t hubaddr : + 7; +uint32_t xactpos : + 2; +uint32_t compsplt : + 1; +uint32_t Reserved : + 14; +uint32_t spltena : + 1; + } + b; +} USB_OTG_HCSPLT_TypeDef ; +typedef union _USB_OTG_HCINTn_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfercompl : + 1; +uint32_t chhltd : + 1; +uint32_t ahberr : + 1; +uint32_t stall : + 1; +uint32_t nak : + 1; +uint32_t ack : + 1; +uint32_t nyet : + 1; +uint32_t xacterr : + 1; +uint32_t bblerr : + 1; +uint32_t frmovrun : + 1; +uint32_t datatglerr : + 1; +uint32_t Reserved : + 21; + } + b; +} USB_OTG_HCINTn_TypeDef ; +typedef union _USB_OTG_HCTSIZn_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfersize : + 19; +uint32_t pktcnt : + 10; +uint32_t pid : + 2; +uint32_t dopng : + 1; + } + b; +} USB_OTG_HCTSIZn_TypeDef ; +typedef union _USB_OTG_HCINTMSK_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfercompl : + 1; +uint32_t chhltd : + 1; +uint32_t ahberr : + 1; +uint32_t stall : + 1; +uint32_t nak : + 1; +uint32_t ack : + 1; +uint32_t nyet : + 1; +uint32_t xacterr : + 1; +uint32_t bblerr : + 1; +uint32_t frmovrun : + 1; +uint32_t datatglerr : + 1; +uint32_t Reserved : + 21; + } + b; +} USB_OTG_HCINTMSK_TypeDef ; + +typedef union _USB_OTG_PCGCCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t stoppclk : + 1; +uint32_t gatehclk : + 1; +uint32_t Reserved2_3 : + 2; +uint32_t phy_susp : + 1; +uint32_t Reserved5_31 : + 27; + } + b; +} USB_OTG_PCGCCTL_TypeDef ; + +/** + * @} + */ + + +/** @defgroup USB_REGS_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_REGS_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_REGS_Exported_FunctionsPrototype + * @{ + */ +/** + * @} + */ + + +#endif /* __USB_OTG_REGS_H__ */ + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c index c4b479518..f228e2a5a 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c @@ -1,2232 +1,2232 @@ -/** - ****************************************************************************** - * @file usb_core.c - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief USB-OTG Core Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_bsp.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_CORE -* @brief This file includes the USB-OTG Core Layer -* @{ -*/ - - -/** @defgroup USB_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_FunctionPrototypes -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USB_OTG_EnableCommonInt -* Initializes the commmon interrupts, used in both device and modes -* @param pdev : Selected device -* @retval None -*/ -static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef int_mask; - - int_mask.d32 = 0; - /* Clear any pending USB_OTG Interrupts */ -#ifndef USE_OTG_MODE - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF); -#endif - /* Clear any pending interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); - /* Enable the interrupts in the INTMSK */ - int_mask.b.wkupintr = 1; - int_mask.b.usbsuspend = 1; - -#ifdef USE_OTG_MODE - int_mask.b.otgintr = 1; - int_mask.b.sessreqintr = 1; - int_mask.b.conidstschng = 1; -#endif - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32); -} - -/** -* @brief USB_OTG_CoreReset : Soft reset of the core -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - uint32_t count = 0; - - greset.d32 = 0; - /* Wait for AHB master IDLE state. */ - do - { - USB_OTG_BSP_uDelay(3); - greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - return USB_OTG_OK; - } - } - while (greset.b.ahbidle == 0); - /* Core Soft Reset */ - count = 0; - greset.b.csftrst = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.csftrst == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - -/** -* @brief USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated -* with the EP -* @param pdev : Selected device -* @param src : source pointer -* @param ch_ep_num : end point number -* @param bytes : No. of bytes -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *src, - uint8_t ch_ep_num, - uint16_t len) -{ - USB_OTG_STS status = USB_OTG_OK; - if (pdev->cfg.dma_enable == 0) - { - uint32_t count32b= 0 , i= 0; - __IO uint32_t *fifo; - - count32b = (len + 3) / 4; - fifo = pdev->regs.DFIFO[ch_ep_num]; - for (i = 0; i < count32b; i++) - { - USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) ); - src+=4; - } - } - return status; -} - - -/** -* @brief USB_OTG_ReadPacket : Reads a packet from the Rx FIFO -* @param pdev : Selected device -* @param dest : Destination Pointer -* @param bytes : No. of bytes -* @retval None -*/ -void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *dest, - uint16_t len) -{ - uint32_t i=0; - uint32_t count32b = (len + 3) / 4; - - __IO uint32_t *fifo = pdev->regs.DFIFO[0]; - - for( i = 0; i < count32b; i++) - { - *(__packed uint32_t *)dest = USB_OTG_READ_REG32(fifo); - dest += 4 ; - } - return ((void *)dest); -} - -/** -* @brief USB_OTG_SelectCore -* Initialize core registers address. -* @param pdev : Selected device -* @param coreID : USB OTG Core ID -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint32_t i , baseAddress = 0; - USB_OTG_STS status = USB_OTG_OK; - - pdev->cfg.dma_enable = 0; - - /* at startup the core is in FS mode */ - pdev->cfg.speed = USB_OTG_SPEED_FULL; - pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; - - /* initialize device cfg following its address */ - if (coreID == USB_OTG_FS_CORE_ID) - { - baseAddress = USB_OTG_FS_BASE_ADDR; - pdev->cfg.coreID = USB_OTG_FS_CORE_ID; - pdev->cfg.host_channels = 8 ; - pdev->cfg.dev_endpoints = 4 ; - pdev->cfg.TotalFifoSize = 320; /* in 32-bits */ - pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; - -#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif - } - else if (coreID == USB_OTG_HS_CORE_ID) - { - baseAddress = USB_OTG_HS_BASE_ADDR; - pdev->cfg.coreID = USB_OTG_HS_CORE_ID; - pdev->cfg.host_channels = 12 ; - pdev->cfg.dev_endpoints = 6 ; - pdev->cfg.TotalFifoSize = 1280;/* in 32-bits */ - -#ifdef USB_OTG_ULPI_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_ULPI_PHY; -#else -#ifdef USB_OTG_EMBEDDED_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; -#endif -#endif - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pdev->cfg.dma_enable = 1; -#endif - -#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif - - } - - else - { - /* Do Nothing */ - } - - pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \ - USB_OTG_CORE_GLOBAL_REGS_OFFSET); - pdev->regs.DREGS = (USB_OTG_DREGS *) (baseAddress + \ - USB_OTG_DEV_GLOBAL_REG_OFFSET); - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - pdev->regs.INEP_REGS[i] = (USB_OTG_INEPREGS *) \ - (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \ - (i * USB_OTG_EP_REG_OFFSET)); - pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \ - (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \ - (i * USB_OTG_EP_REG_OFFSET)); - } - pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \ - USB_OTG_HOST_GLOBAL_REG_OFFSET); - pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET); - - for (i = 0; i < pdev->cfg.host_channels; i++) - { - pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \ - USB_OTG_HOST_CHAN_REGS_OFFSET + \ - (i * USB_OTG_CHAN_REGS_OFFSET)); - } - for (i = 0; i < pdev->cfg.host_channels; i++) - { - pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\ - (i * USB_OTG_DATA_FIFO_SIZE)); - } - pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET); - - return status; -} - - -/** -* @brief USB_OTG_CoreInit -* Initializes the USB_OTG controller registers and prepares the core -* device mode or host mode operation. -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GUSBCFG_TypeDef usbcfg; - USB_OTG_GCCFG_TypeDef gccfg; - USB_OTG_GAHBCFG_TypeDef ahbcfg; -#if defined (STM32F446xx) || defined (STM32F469_479xx) - USB_OTG_DCTL_TypeDef dctl; -#endif - usbcfg.d32 = 0; - gccfg.d32 = 0; - ahbcfg.d32 = 0; - - if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG); - gccfg.b.pwdn = 0; - - if (pdev->cfg.Sof_output) - { - gccfg.b.sofouten = 1; - } - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); - - /* Init The ULPI Interface */ - usbcfg.d32 = 0; - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - usbcfg.b.physel = 0; /* HS Interface */ -#ifdef USB_OTG_INTERNAL_VBUS_ENABLED - usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */ -#else -#ifdef USB_OTG_EXTERNAL_VBUS_ENABLED - usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */ -#endif -#endif - usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */ - - usbcfg.b.ulpi_fsls = 0; - usbcfg.b.ulpi_clk_sus_m = 0; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - - /* Reset after a PHY select */ - USB_OTG_CoreReset(pdev); - - if(pdev->cfg.dma_enable == 1) - { - - ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ - ahbcfg.b.dmaenable = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - - } - } - else /* FS interface (embedded Phy) */ - { - - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);; - usbcfg.b.physel = 1; /* FS Interface */ - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - /* Reset after a PHY select and set Host mode */ - USB_OTG_CoreReset(pdev); - /* Deactivate the power down*/ - gccfg.d32 = 0; - gccfg.b.pwdn = 1; - gccfg.b.vbussensingA = 1 ; - gccfg.b.vbussensingB = 1 ; - -#ifndef VBUS_SENSING_ENABLED - gccfg.b.disablevbussensing = 1; -#endif - - if(pdev->cfg.Sof_output) - { - gccfg.b.sofouten = 1; - } - - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); - USB_OTG_BSP_mDelay(20); - } - /* case the HS core is working in FS mode */ - if(pdev->cfg.dma_enable == 1) - { - - ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG); - ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ - ahbcfg.b.dmaenable = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - - } - /* initialize OTG features */ -#ifdef USE_OTG_MODE - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - usbcfg.b.hnpcap = 1; - usbcfg.b.srpcap = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - USB_OTG_EnableCommonInt(pdev); -#endif - -#if defined (STM32F446xx) || defined (STM32F469_479xx) - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - usbcfg.b.srpcap = 1; - /*clear sdis bit in dctl */ - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - /* Connect device */ - dctl.b.sftdiscon = 0; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - USB_OTG_EnableCommonInt(pdev); -#endif - - return status; -} -/** -* @brief USB_OTG_EnableGlobalInt -* Enables the controller's Global Int in the AHB Config reg -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - - ahbcfg.d32 = 0; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32); - return status; -} - - -/** -* @brief USB_OTG_DisableGlobalInt -* Enables the controller's Global Int in the AHB Config reg -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - ahbcfg.d32 = 0; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0); - return status; -} - - -/** -* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO -* @param pdev : Selected device -* @param num : FO num -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num ) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - - uint32_t count = 0; - greset.d32 = 0; - greset.b.txfflsh = 1; - greset.b.txfnum = num; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.txfflsh == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - - -/** -* @brief USB_OTG_FlushRxFifo : Flush a Rx FIFO -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev ) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - uint32_t count = 0; - - greset.d32 = 0; - greset.b.rxfflsh = 1; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.rxfflsh == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - - -/** -* @brief USB_OTG_SetCurrentMode : Set ID line -* @param pdev : Selected device -* @param mode : (Host/device) -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GUSBCFG_TypeDef usbcfg; - - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - usbcfg.b.force_host = 0; - usbcfg.b.force_dev = 0; - - if ( mode == HOST_MODE) - { - usbcfg.b.force_host = 1; - } - else if ( mode == DEVICE_MODE) - { - usbcfg.b.force_dev = 1; - } - - else - { - /* Do Nothing */ - } - - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - USB_OTG_BSP_mDelay(50); - return status; -} - - -/** -* @brief USB_OTG_GetMode : Get current mode -* @param pdev : Selected device -* @retval current mode -*/ -uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1); -} - - -/** -* @brief USB_OTG_IsDeviceMode : Check if it is device mode -* @param pdev : Selected device -* @retval num_in_ep -*/ -uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_GetMode(pdev) != HOST_MODE); -} - - -/** -* @brief USB_OTG_IsHostMode : Check if it is host mode -* @param pdev : Selected device -* @retval num_in_ep -*/ -uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_GetMode(pdev) == HOST_MODE); -} - - -/** -* @brief USB_OTG_ReadCoreItr : returns the Core Interrupt register -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v = 0; - v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS); - v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK); - return v; -} - - -/** -* @brief USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT)); -} - -#ifdef USE_HOST_MODE -/** -* @brief USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode -* @param pdev : Selected device -* @retval status -*/ -USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_FSIZ_TypeDef nptxfifosize; - USB_OTG_FSIZ_TypeDef ptxfifosize; - USB_OTG_HCFG_TypeDef hcfg; - -#ifdef USE_OTG_MODE - USB_OTG_OTGCTL_TypeDef gotgctl; -#endif - - uint32_t i = 0; - - nptxfifosize.d32 = 0; - ptxfifosize.d32 = 0; -#ifdef USE_OTG_MODE - gotgctl.d32 = 0; -#endif - hcfg.d32 = 0; - - - /* configure charge pump IO */ - USB_OTG_BSP_ConfigVBUS(pdev); - - /* Restart the Phy Clock */ - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); - - /* Initialize Host Configuration Register */ - if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - USB_OTG_InitFSLSPClkSel(pdev , HCFG_30_60_MHZ); - } - else - { - USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); - } - USB_OTG_ResetPort(pdev); - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - hcfg.b.fslssupp = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); - - /* Configure data FIFO sizes */ - /* Rx FIFO */ -#ifdef USB_OTG_FS_CORE - if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID) - { - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; - nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - - ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ; - ptxfifosize.b.depth = TXH_P_FS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); - } -#endif -#ifdef USB_OTG_HS_CORE - if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID) - { - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; - nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - - ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ; - ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); - } -#endif - -#ifdef USE_OTG_MODE - /* Clear Host Set HNP Enable in the USB_OTG Control Register */ - gotgctl.b.hstsethnpen = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0); -#endif - - /* Make sure the FIFOs are flushed. */ - USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */ - USB_OTG_FlushRxFifo(pdev); - - - /* Clear all pending HC Interrupts */ - for (i = 0; i < pdev->cfg.host_channels; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF ); - USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINTMSK, 0 ); - } -#ifndef USE_OTG_MODE - USB_OTG_DriveVbus(pdev, 1); -#endif - - USB_OTG_EnableHostInt(pdev); - return status; -} - -/** -* @brief USB_OTG_IsEvenFrame -* This function returns the frame number for sof packet -* @param pdev : Selected device -* @retval Frame number -*/ -uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) -{ - return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1); -} - -/** -* @brief USB_OTG_DriveVbus : set/reset vbus -* @param pdev : Selected device -* @param state : VBUS state -* @retval None -*/ -void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = 0; - - /* enable disable the external charge pump */ - USB_OTG_BSP_DriveVBUS(pdev, state); - - /* Turn on the Host port power. */ - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - if ((hprt0.b.prtpwr == 0 ) && (state == 1 )) - { - hprt0.b.prtpwr = 1; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - if ((hprt0.b.prtpwr == 1 ) && (state == 0 )) - { - hprt0.b.prtpwr = 0; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - - USB_OTG_BSP_mDelay(200); -} -/** -* @brief USB_OTG_EnableHostInt: Enables the Host mode interrupts -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GINTMSK_TypeDef intmsk; - intmsk.d32 = 0; - /* Disable all interrupts. */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0); - - /* Clear any pending interrupts. */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); - - /* Enable the common interrupts */ - USB_OTG_EnableCommonInt(pdev); - - if (pdev->cfg.dma_enable == 0) - { - intmsk.b.rxstsqlvl = 1; - } - - - intmsk.b.incomplisoout = 1; - intmsk.b.hcintr = 1; - intmsk.b.portintr = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); - - intmsk.d32 = 0; - - intmsk.b.disconnect = 1; - - intmsk.b.sofintr = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); - return status; -} - -/** -* @brief USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the -* HCFG register on the PHY type -* @param pdev : Selected device -* @param freq : clock frequency -* @retval None -*/ -void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq) -{ - USB_OTG_HCFG_TypeDef hcfg; - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - hcfg.b.fslspclksel = freq; - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); -} - - -/** -* @brief USB_OTG_ReadHPRT0 : Reads HPRT0 to modify later -* @param pdev : Selected device -* @retval HPRT0 value -*/ -uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - hprt0.b.prtena = 0; - hprt0.b.prtconndet = 0; - hprt0.b.prtenchng = 0; - hprt0.b.prtovrcurrchng = 0; - return hprt0.d32; -} - - -/** -* @brief USB_OTG_ReadHostAllChannels_intr : Register PCD Callbacks -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT)); -} - - -/** -* @brief USB_OTG_ResetPort : Reset Host Port -* @param pdev : Selected device -* @retval status -* @note : (1)The application must wait at least 10 ms (+ 10 ms security) -* before clearing the reset bit. -*/ -uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - hprt0.b.prtrst = 1; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - USB_OTG_BSP_mDelay (100); /* See Note #1 */ - hprt0.b.prtrst = 0; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - USB_OTG_BSP_mDelay (20); - return 1; -} - - -/** -* @brief USB_OTG_HC_Init : Prepares a host channel for transferring packets -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - uint32_t intr_enable = 0; - USB_OTG_HCINTMSK_TypeDef hcintmsk; - USB_OTG_GINTMSK_TypeDef gintmsk; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCINTn_TypeDef hcint; - - - gintmsk.d32 = 0; - hcintmsk.d32 = 0; - hcchar.d32 = 0; - - /* Clear old interrupt conditions for this host channel. */ - hcint.d32 = 0xFFFFFFFF; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32); - - /* Enable channel interrupts required for this transfer. */ - hcintmsk.d32 = 0; - - if (pdev->cfg.dma_enable == 1) - { - hcintmsk.b.ahberr = 1; - } - - switch (pdev->host.hc[hc_num].ep_type) - { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.stall = 1; - hcintmsk.b.xacterr = 1; - hcintmsk.b.datatglerr = 1; - hcintmsk.b.nak = 1; - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.bblerr = 1; - } - else - { - hcintmsk.b.nyet = 1; - if (pdev->host.hc[hc_num].do_ping) - { - hcintmsk.b.ack = 1; - } - } - break; - case EP_TYPE_INTR: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.nak = 1; - hcintmsk.b.stall = 1; - hcintmsk.b.xacterr = 1; - hcintmsk.b.datatglerr = 1; - hcintmsk.b.frmovrun = 1; - - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.bblerr = 1; - } - - break; - case EP_TYPE_ISOC: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.frmovrun = 1; - hcintmsk.b.ack = 1; - - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.xacterr = 1; - hcintmsk.b.bblerr = 1; - } - break; - } - - - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, hcintmsk.d32); - - - /* Enable the top level host channel interrupt. */ - intr_enable = (1 << hc_num); - USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable); - - /* Make sure host channel interrupts are enabled. */ - gintmsk.b.hcintr = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32); - - /* Program the HCCHAR register */ - hcchar.d32 = 0; - hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr; - hcchar.b.epnum = pdev->host.hc[hc_num].ep_num; - hcchar.b.epdir = pdev->host.hc[hc_num].ep_is_in; - hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED); - hcchar.b.eptype = pdev->host.hc[hc_num].ep_type; - hcchar.b.mps = pdev->host.hc[hc_num].max_packet; - if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR) - { - hcchar.b.oddfrm = 1; - } - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - - -/** -* @brief USB_OTG_HC_StartXfer : Start transfer -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HNPTXSTS_TypeDef hnptxsts; - USB_OTG_HPTXSTS_TypeDef hptxsts; - USB_OTG_GINTMSK_TypeDef intmsk; - uint16_t len_words = 0; - - uint16_t num_packets; - uint16_t max_hc_pkt_count; - - max_hc_pkt_count = 256; - hctsiz.d32 = 0; - hcchar.d32 = 0; - intmsk.d32 = 0; - - /* Compute the expected number of packets associated to the transfer */ - if (pdev->host.hc[hc_num].xfer_len > 0) - { - num_packets = (pdev->host.hc[hc_num].xfer_len + \ - pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet; - - if (num_packets > max_hc_pkt_count) - { - num_packets = max_hc_pkt_count; - pdev->host.hc[hc_num].xfer_len = num_packets * \ - pdev->host.hc[hc_num].max_packet; - } - } - else - { - num_packets = 1; - } - if (pdev->host.hc[hc_num].ep_is_in) - { - pdev->host.hc[hc_num].xfer_len = num_packets * \ - pdev->host.hc[hc_num].max_packet; - } - /* Initialize the HCTSIZn register */ - hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len; - hctsiz.b.pktcnt = num_packets; - hctsiz.b.pid = pdev->host.hc[hc_num].data_pid; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff); - } - - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev); - - /* Set host channel enable */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - - if (pdev->cfg.dma_enable == 0) /* Slave mode */ - { - if((pdev->host.hc[hc_num].ep_is_in == 0) && - (pdev->host.hc[hc_num].xfer_len > 0)) - { - switch(pdev->host.hc[hc_num].ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; - - /* check if there is enough space in FIFO space */ - if(len_words > hnptxsts.b.nptxfspcavail) - { - /* need to process data in nptxfempty interrupt */ - intmsk.b.nptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - } - - break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; - /* check if there is enough space in FIFO space */ - if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - intmsk.b.ptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - } - break; - - default: - break; - } - - /* Write packet into the Tx FIFO. */ - USB_OTG_WritePacket(pdev, - pdev->host.hc[hc_num].xfer_buff , - hc_num, pdev->host.hc[hc_num].xfer_len); - } - } - return status; -} - - -/** -* @brief USB_OTG_HC_Halt : Halt channel -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HNPTXSTS_TypeDef nptxsts; - USB_OTG_HPTXSTS_TypeDef hptxsts; - USB_OTG_HCCHAR_TypeDef hcchar; - - nptxsts.d32 = 0; - hptxsts.d32 = 0; - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - - hcchar.b.chdis = 1; - - /* Check for space in the request queue to issue the halt. */ - if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK) - { - nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - if (nptxsts.b.nptxqspcavail == 0) - { - hcchar.b.chen = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - } - } - else - { - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - if (hptxsts.b.ptxqspcavail == 0) - { - hcchar.b.chen = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - } - } - hcchar.b.chen = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - -/** -* @brief Issue a ping token -* @param None -* @retval : None -*/ -USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - - hctsiz.d32 = 0; - hctsiz.b.dopng = 1; - hctsiz.b.pktcnt = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - -/** -* @brief Stop the device and clean up fifo's -* @param None -* @retval : None -*/ -void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HCCHAR_TypeDef hcchar; - uint32_t i; - - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0); - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF); - /* Flush out any leftover queued requests. */ - - for (i = 0; i < pdev->cfg.host_channels; i++) - { - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); - hcchar.b.chen = 0; - hcchar.b.chdis = 1; - hcchar.b.epdir = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32); - } - - /* Flush the FIFO */ - USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); -} -#endif -#ifdef USE_DEVICE_MODE -/* PCD Core Layer */ - -/** -* @brief USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register -* depending the PHY type and the enumeration speed of the device. -* @param pdev : Selected device -* @retval : None -*/ -void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed) -{ - USB_OTG_DCFG_TypeDef dcfg; - - dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG); - dcfg.b.devspd = speed; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32); -} - - -/** -* @brief USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers -* for device mode -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - uint32_t i; - USB_OTG_DCFG_TypeDef dcfg; - USB_OTG_FSIZ_TypeDef nptxfifosize; - USB_OTG_FSIZ_TypeDef txfifosize; - USB_OTG_DIEPMSK_TypeDef msk; - USB_OTG_DTHRCTL_TypeDef dthrctl; - - depctl.d32 = 0; - dcfg.d32 = 0; - nptxfifosize.d32 = 0; - txfifosize.d32 = 0; - msk.d32 = 0; - - /* Restart the Phy Clock */ - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); - /* Device configuration register */ - dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); - dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 ); - -#ifdef USB_OTG_FS_CORE - if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID ) - { - - /* Set Full speed phy */ - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL); - - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - - /* EP0 TX*/ - nptxfifosize.b.depth = TX0_FIFO_FS_SIZE; - nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - - /* EP1 TX*/ - txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - txfifosize.b.depth = TX1_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - - /* EP2 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX2_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX3_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); - } -#endif -#ifdef USB_OTG_HS_CORE - if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID ) - { - - /* Set High speed phy */ - - if(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH); - } - else /* set High speed phy in Full speed mode */ - { - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL); - } - - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - - /* EP0 TX*/ - nptxfifosize.b.depth = TX0_FIFO_HS_SIZE; - nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - - /* EP1 TX*/ - txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - txfifosize.b.depth = TX1_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - - /* EP2 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX2_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX3_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); - - /* EP4 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX4_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 ); - - - /* EP5 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX5_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 ); - } -#endif - /* Flush the FIFOs */ - USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */ - USB_OTG_FlushRxFifo(pdev); - /* Clear all pending Device Interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL); - if (depctl.b.epena) - { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else - { - depctl.d32 = 0; - } - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32); - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0); - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - } - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - USB_OTG_DEPCTL_TypeDef depctl; - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL); - if (depctl.b.epena) - { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else - { - depctl.d32 = 0; - } - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - msk.d32 = 0; - msk.b.txfifoundrn = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32); - - if (pdev->cfg.dma_enable == 1) - { - dthrctl.d32 = 0; - dthrctl.b.non_iso_thr_en = 1; - dthrctl.b.iso_thr_en = 1; - dthrctl.b.tx_thr_len = 64; - dthrctl.b.rx_thr_en = 1; - dthrctl.b.rx_thr_len = 64; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32); - } - USB_OTG_EnableDevInt(pdev); - return status; -} - - -/** -* @brief USB_OTG_EnableDevInt : Enables the Device mode interrupts -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GINTMSK_TypeDef intmsk; - - intmsk.d32 = 0; - - /* Disable all interrupts. */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0); - /* Clear any pending interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); - /* Enable the common interrupts */ - USB_OTG_EnableCommonInt(pdev); - - if (pdev->cfg.dma_enable == 0) - { - intmsk.b.rxstsqlvl = 1; - } - - /* Enable interrupts matching to the Device mode ONLY */ - intmsk.b.usbsuspend = 1; - intmsk.b.usbreset = 1; - intmsk.b.enumdone = 1; - intmsk.b.inepintr = 1; - intmsk.b.outepintr = 1; - intmsk.b.sofintr = 1; - - intmsk.b.incomplisoin = 1; - intmsk.b.incomplisoout = 1; -#ifdef VBUS_SENSING_ENABLED - intmsk.b.sessreqintr = 1; - intmsk.b.otgintr = 1; -#endif - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); - return status; -} - - -/** -* @brief USB_OTG_GetDeviceSpeed -* Get the device speed from the device status register -* @param None -* @retval status -*/ -enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DSTS_TypeDef dsts; - enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN; - - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - switch (dsts.b.enumspd) - { - case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - speed = USB_SPEED_HIGH; - break; - case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_48MHZ: - speed = USB_SPEED_FULL; - break; - - case DSTS_ENUMSPD_LS_PHY_6MHZ: - speed = USB_SPEED_LOW; - break; - default: - speed = USB_SPEED_FULL; - break; - } - - return speed; -} - -/** -* @brief enables EP0 OUT to receive SETUP packets and configures EP0 -* for transmitting packets -* @param None -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_DEPCTL_TypeDef diepctl; - USB_OTG_DCTL_TypeDef dctl; - - dctl.d32 = 0; - /* Read the Device Status and Endpoint 0 Control registers */ - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL); - /* Set the MPS of the IN EP based on the enumeration speed */ - switch (dsts.b.enumspd) - { - case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_48MHZ: - diepctl.b.mps = DEP0CTL_MPS_64; - break; - case DSTS_ENUMSPD_LS_PHY_6MHZ: - diepctl.b.mps = DEP0CTL_MPS_8; - break; - default: - diepctl.b.mps = DEP0CTL_MPS_64; - break; - } - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32); - dctl.b.cgnpinnak = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32); - return status; -} - - -/** -* @brief USB_OTG_EPActivate : Activates an EP -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DAINT_TypeDef daintmsk; - __IO uint32_t *addr; - - - depctl.d32 = 0; - daintmsk.d32 = 0; - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; - daintmsk.ep.in = 1 << ep->num; - } - else - { - addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; - daintmsk.ep.out = 1 << ep->num; - } - /* If the EP is already active don't change the EP Control - * register. */ - depctl.d32 = USB_OTG_READ_REG32(addr); - if (!depctl.b.usbactep) - { - depctl.b.mps = ep->maxpacket; - depctl.b.eptype = ep->type; - depctl.b.txfnum = ep->tx_fifo_num; - depctl.b.setd0pid = 1; - depctl.b.usbactep = 1; - USB_OTG_WRITE_REG32(addr, depctl.d32); - } - /* Enable the Interrupt for this EP */ -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) - { - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32); - } - else -#endif - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32); - return status; -} - - -/** -* @brief USB_OTG_EPDeactivate : Deactivates an EP -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DAINT_TypeDef daintmsk; - __IO uint32_t *addr; - - depctl.d32 = 0; - daintmsk.d32 = 0; - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; - daintmsk.ep.in = 1 << ep->num; - } - else - { - addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; - daintmsk.ep.out = 1 << ep->num; - } - depctl.b.usbactep = 0; - USB_OTG_WRITE_REG32(addr, depctl.d32); - /* Disable the Interrupt for this EP */ - -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) - { - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0); - } - else -#endif - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0); - return status; -} - - -/** -* @brief USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and -* starts the xfer -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - USB_OTG_DSTS_TypeDef dsts; - uint32_t fifoemptymsk = 0; - - depctl.d32 = 0; - deptsiz.d32 = 0; - /* IN endpoint */ - if (ep->is_in == 1) - { - depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL)); - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ)); - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - deptsiz.b.xfersize = ep->xfer_len; - deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; - - if (ep->type == EP_TYPE_ISOC) - { - deptsiz.b.mc = 1; - } - } - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); - } - else - { - if (ep->type != EP_TYPE_ISOC) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - fifoemptymsk = 1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); - } - } - } - - - if (ep->type == EP_TYPE_ISOC) - { - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - if (((dsts.b.soffn)&0x1) == 0) - { - depctl.b.setd1pid = 1; - } - else - { - depctl.b.setd0pid = 1; - } - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32); - - if (ep->type == EP_TYPE_ISOC) - { - USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len); - } - } - else - { - /* OUT endpoint */ - depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL)); - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ)); - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - else - { - deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; - deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; - ep->xfer_len = deptsiz.b.xfersize ; - } - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); - } - - if (ep->type == EP_TYPE_ISOC) - { - if (ep->even_odd_frame) - { - depctl.b.setd1pid = 1; - } - else - { - depctl.b.setd0pid = 1; - } - } - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32); - } - return status; -} - - -/** -* @brief USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and -* starts the xfer -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DEP0XFRSIZ_TypeDef deptsiz; - USB_OTG_INEPREGS *in_regs; - uint32_t fifoemptymsk = 0; - - depctl.d32 = 0; - deptsiz.d32 = 0; - /* IN endpoint */ - if (ep->is_in == 1) - { - in_regs = pdev->regs.INEP_REGS[0]; - depctl.d32 = USB_OTG_READ_REG32(&in_regs->DIEPCTL); - deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ); - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - - } - else - { - if (ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - deptsiz.b.xfersize = ep->maxpacket; - } - else - { - deptsiz.b.xfersize = ep->xfer_len; - } - deptsiz.b.pktcnt = 1; - } - USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32); - - - - if (pdev->cfg.dma_enable == 0) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - { - fifoemptymsk |= 1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); - } - } - } - } - else - { - /* OUT endpoint */ - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ); - /* Program the transfer size and packet count as follows: - * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) - * pktcnt = N */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - else - { - ep->xfer_len = ep->maxpacket; - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); - } - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32); - - } - return status; -} - - -/** -* @brief USB_OTG_EPSetStall : Set the EP STALL -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* set the disable and stall bits */ - if (depctl.b.epena) - { - depctl.b.epdis = 1; - } - depctl.b.stall = 1; - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* set the stall bit */ - depctl.b.stall = 1; - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - } - return status; -} - - -/** -* @brief Clear the EP STALL -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - } - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* clear the stall bits */ - depctl.b.stall = 0; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) - { - depctl.b.setd0pid = 1; /* DATA0 */ - } - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - return status; -} - - -/** -* @brief USB_OTG_ReadDevAllOutEp_itr : returns OUT endpoint interrupt bits -* @param pdev : Selected device -* @retval OUT endpoint interrupt bits -*/ -uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); - return ((v & 0xffff0000) >> 16); -} - - -/** -* @brief USB_OTG_ReadDevOutEP_itr : returns Device OUT EP Interrupt register -* @param pdev : Selected device -* @param ep : end point number -* @retval Device OUT EP Interrupt register -*/ -uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK); - return v; -} - - -/** -* @brief USB_OTG_ReadDevAllInEPItr : Get int status register -* @param pdev : Selected device -* @retval int status register -*/ -uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); - return (v & 0xffff); -} - -/** -* @brief configures EPO to receive SETUP packets -* @param None -* @retval : None -*/ -void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DEP0XFRSIZ_TypeDef doeptsize0; - doeptsize0.d32 = 0; - doeptsize0.b.supcnt = 3; - doeptsize0.b.pktcnt = 1; - doeptsize0.b.xfersize = 8 * 3; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 ); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_DEPCTL_TypeDef doepctl; - doepctl.d32 = 0; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA, - (uint32_t)&pdev->dev.setup_packet); - - /* EP enable */ - doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL); - doepctl.b.epena = 1; - doepctl.d32 = 0x80008000; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32); - } -} - -/** -* @brief USB_OTG_RemoteWakeup : active remote wakeup signalling -* @param None -* @retval : None -*/ -void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DCTL_TypeDef dctl; - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - - if (pdev->dev.DevRemoteWakeup) - { - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - if(dsts.b.suspsts == 1) - { - if(pdev->cfg.low_power) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - } - /* active Remote wakeup signaling */ - dctl.d32 = 0; - dctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32); - USB_OTG_BSP_mDelay(5); - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); - } - } -} - - -/** -* @brief USB_OTG_UngateClock : active USB Core clock -* @param None -* @retval : None -*/ -void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev) -{ - if(pdev->cfg.low_power) - { - - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - if(dsts.b.suspsts == 1) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - - } - } -} - -/** -* @brief Stop the device and clean up fifo's -* @param None -* @retval : None -*/ -void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t i; - - pdev->dev.device_status = 1; - - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - - /* Flush the FIFO */ - USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); -} - -/** -* @brief returns the EP Status -* @param pdev : Selected device -* ep : endpoint structure -* @retval : EP status -*/ - -uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep) -{ - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - uint32_t Status = 0; - - depctl.d32 = 0; - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (depctl.b.stall == 1) - { - Status = USB_OTG_EP_TX_STALL; - } - else if (depctl.b.naksts == 1) - { - Status = USB_OTG_EP_TX_NAK; - } - else - { - Status = USB_OTG_EP_TX_VALID; - } - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - if (depctl.b.stall == 1) - { - Status = USB_OTG_EP_RX_STALL; - } - else if (depctl.b.naksts == 1) - { - Status = USB_OTG_EP_RX_NAK; - } - else - { - Status = USB_OTG_EP_RX_VALID; - } - } - - /* Return the current status */ - return Status; -} - -/** -* @brief Set the EP Status -* @param pdev : Selected device -* Status : new Status -* ep : EP structure -* @retval : None -*/ -void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status) -{ - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - - /* Process for IN endpoint */ - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (Status == USB_OTG_EP_TX_STALL) - { - USB_OTG_EPSetStall(pdev, ep); return; - } - else if (Status == USB_OTG_EP_TX_NAK) - { - depctl.b.snak = 1; - } - else if (Status == USB_OTG_EP_TX_VALID) - { - if (depctl.b.stall == 1) - { - ep->even_odd_frame = 0; - USB_OTG_EPClearStall(pdev, ep); - return; - } - depctl.b.cnak = 1; - depctl.b.usbactep = 1; - depctl.b.epena = 1; - } - else if (Status == USB_OTG_EP_TX_DIS) - { - depctl.b.usbactep = 0; - } - - else - { - /* Do Nothing */ - } - } - else /* Process for OUT endpoint */ - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (Status == USB_OTG_EP_RX_STALL) { - depctl.b.stall = 1; - } - else if (Status == USB_OTG_EP_RX_NAK) - { - depctl.b.snak = 1; - } - else if (Status == USB_OTG_EP_RX_VALID) - { - if (depctl.b.stall == 1) - { - ep->even_odd_frame = 0; - USB_OTG_EPClearStall(pdev, ep); - return; - } - depctl.b.cnak = 1; - depctl.b.usbactep = 1; - depctl.b.epena = 1; - } - else if (Status == USB_OTG_EP_RX_DIS) - { - depctl.b.usbactep = 0; - } - - else - { - /* Do Nothing */ - } - } - - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); -} - -#endif -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usb_core.c + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief USB-OTG Core Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_core.h" +#include "usb_bsp.h" + + +/** @addtogroup USB_OTG_DRIVER +* @{ +*/ + +/** @defgroup USB_CORE +* @brief This file includes the USB-OTG Core Layer +* @{ +*/ + + +/** @defgroup USB_CORE_Private_Defines +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USB_CORE_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + + +/** @defgroup USB_CORE_Private_Macros +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_CORE_Private_Variables +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_CORE_Private_FunctionPrototypes +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_CORE_Private_Functions +* @{ +*/ + +/** +* @brief USB_OTG_EnableCommonInt +* Initializes the commmon interrupts, used in both device and modes +* @param pdev : Selected device +* @retval None +*/ +static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTMSK_TypeDef int_mask; + + int_mask.d32 = 0; + /* Clear any pending USB_OTG Interrupts */ +#ifndef USE_OTG_MODE + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF); +#endif + /* Clear any pending interrupts */ + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); + /* Enable the interrupts in the INTMSK */ + int_mask.b.wkupintr = 1; + int_mask.b.usbsuspend = 1; + +#ifdef USE_OTG_MODE + int_mask.b.otgintr = 1; + int_mask.b.sessreqintr = 1; + int_mask.b.conidstschng = 1; +#endif + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32); +} + +/** +* @brief USB_OTG_CoreReset : Soft reset of the core +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + __IO USB_OTG_GRSTCTL_TypeDef greset; + uint32_t count = 0; + + greset.d32 = 0; + /* Wait for AHB master IDLE state. */ + do + { + USB_OTG_BSP_uDelay(3); + greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); + if (++count > 200000) + { + return USB_OTG_OK; + } + } + while (greset.b.ahbidle == 0); + /* Core Soft Reset */ + count = 0; + greset.b.csftrst = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 ); + do + { + greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); + if (++count > 200000) + { + break; + } + } + while (greset.b.csftrst == 1); + /* Wait for 3 PHY Clocks*/ + USB_OTG_BSP_uDelay(3); + return status; +} + +/** +* @brief USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated +* with the EP +* @param pdev : Selected device +* @param src : source pointer +* @param ch_ep_num : end point number +* @param bytes : No. of bytes +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, + uint8_t *src, + uint8_t ch_ep_num, + uint16_t len) +{ + USB_OTG_STS status = USB_OTG_OK; + if (pdev->cfg.dma_enable == 0) + { + uint32_t count32b= 0 , i= 0; + __IO uint32_t *fifo; + + count32b = (len + 3) / 4; + fifo = pdev->regs.DFIFO[ch_ep_num]; + for (i = 0; i < count32b; i++) + { + USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) ); + src+=4; + } + } + return status; +} + + +/** +* @brief USB_OTG_ReadPacket : Reads a packet from the Rx FIFO +* @param pdev : Selected device +* @param dest : Destination Pointer +* @param bytes : No. of bytes +* @retval None +*/ +void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, + uint8_t *dest, + uint16_t len) +{ + uint32_t i=0; + uint32_t count32b = (len + 3) / 4; + + __IO uint32_t *fifo = pdev->regs.DFIFO[0]; + + for( i = 0; i < count32b; i++) + { + *(__packed uint32_t *)dest = USB_OTG_READ_REG32(fifo); + dest += 4 ; + } + return ((void *)dest); +} + +/** +* @brief USB_OTG_SelectCore +* Initialize core registers address. +* @param pdev : Selected device +* @param coreID : USB OTG Core ID +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, + USB_OTG_CORE_ID_TypeDef coreID) +{ + uint32_t i , baseAddress = 0; + USB_OTG_STS status = USB_OTG_OK; + + pdev->cfg.dma_enable = 0; + + /* at startup the core is in FS mode */ + pdev->cfg.speed = USB_OTG_SPEED_FULL; + pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; + + /* initialize device cfg following its address */ + if (coreID == USB_OTG_FS_CORE_ID) + { + baseAddress = USB_OTG_FS_BASE_ADDR; + pdev->cfg.coreID = USB_OTG_FS_CORE_ID; + pdev->cfg.host_channels = 8 ; + pdev->cfg.dev_endpoints = 4 ; + pdev->cfg.TotalFifoSize = 320; /* in 32-bits */ + pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; + +#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED + pdev->cfg.Sof_output = 1; +#endif + +#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT + pdev->cfg.low_power = 1; +#endif + } + else if (coreID == USB_OTG_HS_CORE_ID) + { + baseAddress = USB_OTG_HS_BASE_ADDR; + pdev->cfg.coreID = USB_OTG_HS_CORE_ID; + pdev->cfg.host_channels = 12 ; + pdev->cfg.dev_endpoints = 6 ; + pdev->cfg.TotalFifoSize = 1280;/* in 32-bits */ + +#ifdef USB_OTG_ULPI_PHY_ENABLED + pdev->cfg.phy_itface = USB_OTG_ULPI_PHY; +#else +#ifdef USB_OTG_EMBEDDED_PHY_ENABLED + pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; +#endif +#endif + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + pdev->cfg.dma_enable = 1; +#endif + +#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED + pdev->cfg.Sof_output = 1; +#endif + +#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT + pdev->cfg.low_power = 1; +#endif + + } + + else + { + /* Do Nothing */ + } + + pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \ + USB_OTG_CORE_GLOBAL_REGS_OFFSET); + pdev->regs.DREGS = (USB_OTG_DREGS *) (baseAddress + \ + USB_OTG_DEV_GLOBAL_REG_OFFSET); + + for (i = 0; i < pdev->cfg.dev_endpoints; i++) + { + pdev->regs.INEP_REGS[i] = (USB_OTG_INEPREGS *) \ + (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \ + (i * USB_OTG_EP_REG_OFFSET)); + pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \ + (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \ + (i * USB_OTG_EP_REG_OFFSET)); + } + pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \ + USB_OTG_HOST_GLOBAL_REG_OFFSET); + pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET); + + for (i = 0; i < pdev->cfg.host_channels; i++) + { + pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \ + USB_OTG_HOST_CHAN_REGS_OFFSET + \ + (i * USB_OTG_CHAN_REGS_OFFSET)); + } + for (i = 0; i < pdev->cfg.host_channels; i++) + { + pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\ + (i * USB_OTG_DATA_FIFO_SIZE)); + } + pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET); + + return status; +} + + +/** +* @brief USB_OTG_CoreInit +* Initializes the USB_OTG controller registers and prepares the core +* device mode or host mode operation. +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GUSBCFG_TypeDef usbcfg; + USB_OTG_GCCFG_TypeDef gccfg; + USB_OTG_GAHBCFG_TypeDef ahbcfg; +#if defined (STM32F446xx) || defined (STM32F469_479xx) + USB_OTG_DCTL_TypeDef dctl; +#endif + usbcfg.d32 = 0; + gccfg.d32 = 0; + ahbcfg.d32 = 0; + + if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) + { + gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG); + gccfg.b.pwdn = 0; + + if (pdev->cfg.Sof_output) + { + gccfg.b.sofouten = 1; + } + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); + + /* Init The ULPI Interface */ + usbcfg.d32 = 0; + usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); + + usbcfg.b.physel = 0; /* HS Interface */ +#ifdef USB_OTG_INTERNAL_VBUS_ENABLED + usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */ +#else +#ifdef USB_OTG_EXTERNAL_VBUS_ENABLED + usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */ +#endif +#endif + usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */ + + usbcfg.b.ulpi_fsls = 0; + usbcfg.b.ulpi_clk_sus_m = 0; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); + + /* Reset after a PHY select */ + USB_OTG_CoreReset(pdev); + + if(pdev->cfg.dma_enable == 1) + { + + ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ + ahbcfg.b.dmaenable = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); + + } + } + else /* FS interface (embedded Phy) */ + { + + usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);; + usbcfg.b.physel = 1; /* FS Interface */ + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); + /* Reset after a PHY select and set Host mode */ + USB_OTG_CoreReset(pdev); + /* Deactivate the power down*/ + gccfg.d32 = 0; + gccfg.b.pwdn = 1; + gccfg.b.vbussensingA = 1 ; + gccfg.b.vbussensingB = 1 ; + +#ifndef VBUS_SENSING_ENABLED + gccfg.b.disablevbussensing = 1; +#endif + + if(pdev->cfg.Sof_output) + { + gccfg.b.sofouten = 1; + } + + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); + USB_OTG_BSP_mDelay(20); + } + /* case the HS core is working in FS mode */ + if(pdev->cfg.dma_enable == 1) + { + + ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG); + ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ + ahbcfg.b.dmaenable = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); + + } + /* initialize OTG features */ +#ifdef USE_OTG_MODE + usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); + usbcfg.b.hnpcap = 1; + usbcfg.b.srpcap = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); + USB_OTG_EnableCommonInt(pdev); +#endif + +#if defined (STM32F446xx) || defined (STM32F469_479xx) + usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); + usbcfg.b.srpcap = 1; + /*clear sdis bit in dctl */ + dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); + /* Connect device */ + dctl.b.sftdiscon = 0; + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); + dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); + USB_OTG_EnableCommonInt(pdev); +#endif + + return status; +} +/** +* @brief USB_OTG_EnableGlobalInt +* Enables the controller's Global Int in the AHB Config reg +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GAHBCFG_TypeDef ahbcfg; + + ahbcfg.d32 = 0; + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32); + return status; +} + + +/** +* @brief USB_OTG_DisableGlobalInt +* Enables the controller's Global Int in the AHB Config reg +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GAHBCFG_TypeDef ahbcfg; + ahbcfg.d32 = 0; + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0); + return status; +} + + +/** +* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO +* @param pdev : Selected device +* @param num : FO num +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num ) +{ + USB_OTG_STS status = USB_OTG_OK; + __IO USB_OTG_GRSTCTL_TypeDef greset; + + uint32_t count = 0; + greset.d32 = 0; + greset.b.txfflsh = 1; + greset.b.txfnum = num; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); + do + { + greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); + if (++count > 200000) + { + break; + } + } + while (greset.b.txfflsh == 1); + /* Wait for 3 PHY Clocks*/ + USB_OTG_BSP_uDelay(3); + return status; +} + + +/** +* @brief USB_OTG_FlushRxFifo : Flush a Rx FIFO +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev ) +{ + USB_OTG_STS status = USB_OTG_OK; + __IO USB_OTG_GRSTCTL_TypeDef greset; + uint32_t count = 0; + + greset.d32 = 0; + greset.b.rxfflsh = 1; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); + do + { + greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); + if (++count > 200000) + { + break; + } + } + while (greset.b.rxfflsh == 1); + /* Wait for 3 PHY Clocks*/ + USB_OTG_BSP_uDelay(3); + return status; +} + + +/** +* @brief USB_OTG_SetCurrentMode : Set ID line +* @param pdev : Selected device +* @param mode : (Host/device) +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GUSBCFG_TypeDef usbcfg; + + usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); + + usbcfg.b.force_host = 0; + usbcfg.b.force_dev = 0; + + if ( mode == HOST_MODE) + { + usbcfg.b.force_host = 1; + } + else if ( mode == DEVICE_MODE) + { + usbcfg.b.force_dev = 1; + } + + else + { + /* Do Nothing */ + } + + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); + USB_OTG_BSP_mDelay(50); + return status; +} + + +/** +* @brief USB_OTG_GetMode : Get current mode +* @param pdev : Selected device +* @retval current mode +*/ +uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev) +{ + return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1); +} + + +/** +* @brief USB_OTG_IsDeviceMode : Check if it is device mode +* @param pdev : Selected device +* @retval num_in_ep +*/ +uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev) +{ + return (USB_OTG_GetMode(pdev) != HOST_MODE); +} + + +/** +* @brief USB_OTG_IsHostMode : Check if it is host mode +* @param pdev : Selected device +* @retval num_in_ep +*/ +uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev) +{ + return (USB_OTG_GetMode(pdev) == HOST_MODE); +} + + +/** +* @brief USB_OTG_ReadCoreItr : returns the Core Interrupt register +* @param pdev : Selected device +* @retval Status +*/ +uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t v = 0; + v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS); + v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK); + return v; +} + + +/** +* @brief USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register +* @param pdev : Selected device +* @retval Status +*/ +uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev) +{ + return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT)); +} + +#ifdef USE_HOST_MODE +/** +* @brief USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode +* @param pdev : Selected device +* @retval status +*/ +USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_FSIZ_TypeDef nptxfifosize; + USB_OTG_FSIZ_TypeDef ptxfifosize; + USB_OTG_HCFG_TypeDef hcfg; + +#ifdef USE_OTG_MODE + USB_OTG_OTGCTL_TypeDef gotgctl; +#endif + + uint32_t i = 0; + + nptxfifosize.d32 = 0; + ptxfifosize.d32 = 0; +#ifdef USE_OTG_MODE + gotgctl.d32 = 0; +#endif + hcfg.d32 = 0; + + + /* configure charge pump IO */ + USB_OTG_BSP_ConfigVBUS(pdev); + + /* Restart the Phy Clock */ + USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); + + /* Initialize Host Configuration Register */ + if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) + { + USB_OTG_InitFSLSPClkSel(pdev , HCFG_30_60_MHZ); + } + else + { + USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); + } + USB_OTG_ResetPort(pdev); + + hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); + hcfg.b.fslssupp = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); + + /* Configure data FIFO sizes */ + /* Rx FIFO */ +#ifdef USB_OTG_FS_CORE + if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID) + { + /* set Rx FIFO size */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); + nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; + nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); + + ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ; + ptxfifosize.b.depth = TXH_P_FS_FIFOSIZ; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); + } +#endif +#ifdef USB_OTG_HS_CORE + if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID) + { + /* set Rx FIFO size */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); + nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; + nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); + + ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ; + ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); + } +#endif + +#ifdef USE_OTG_MODE + /* Clear Host Set HNP Enable in the USB_OTG Control Register */ + gotgctl.b.hstsethnpen = 1; + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0); +#endif + + /* Make sure the FIFOs are flushed. */ + USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */ + USB_OTG_FlushRxFifo(pdev); + + + /* Clear all pending HC Interrupts */ + for (i = 0; i < pdev->cfg.host_channels; i++) + { + USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF ); + USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINTMSK, 0 ); + } +#ifndef USE_OTG_MODE + USB_OTG_DriveVbus(pdev, 1); +#endif + + USB_OTG_EnableHostInt(pdev); + return status; +} + +/** +* @brief USB_OTG_IsEvenFrame +* This function returns the frame number for sof packet +* @param pdev : Selected device +* @retval Frame number +*/ +uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) +{ + return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1); +} + +/** +* @brief USB_OTG_DriveVbus : set/reset vbus +* @param pdev : Selected device +* @param state : VBUS state +* @retval None +*/ +void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state) +{ + USB_OTG_HPRT0_TypeDef hprt0; + + hprt0.d32 = 0; + + /* enable disable the external charge pump */ + USB_OTG_BSP_DriveVBUS(pdev, state); + + /* Turn on the Host port power. */ + hprt0.d32 = USB_OTG_ReadHPRT0(pdev); + if ((hprt0.b.prtpwr == 0 ) && (state == 1 )) + { + hprt0.b.prtpwr = 1; + USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); + } + if ((hprt0.b.prtpwr == 1 ) && (state == 0 )) + { + hprt0.b.prtpwr = 0; + USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); + } + + USB_OTG_BSP_mDelay(200); +} +/** +* @brief USB_OTG_EnableHostInt: Enables the Host mode interrupts +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GINTMSK_TypeDef intmsk; + intmsk.d32 = 0; + /* Disable all interrupts. */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0); + + /* Clear any pending interrupts. */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); + + /* Enable the common interrupts */ + USB_OTG_EnableCommonInt(pdev); + + if (pdev->cfg.dma_enable == 0) + { + intmsk.b.rxstsqlvl = 1; + } + + + intmsk.b.incomplisoout = 1; + intmsk.b.hcintr = 1; + intmsk.b.portintr = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); + + intmsk.d32 = 0; + + intmsk.b.disconnect = 1; + + intmsk.b.sofintr = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); + return status; +} + +/** +* @brief USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the +* HCFG register on the PHY type +* @param pdev : Selected device +* @param freq : clock frequency +* @retval None +*/ +void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq) +{ + USB_OTG_HCFG_TypeDef hcfg; + + hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); + hcfg.b.fslspclksel = freq; + USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); +} + + +/** +* @brief USB_OTG_ReadHPRT0 : Reads HPRT0 to modify later +* @param pdev : Selected device +* @retval HPRT0 value +*/ +uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_HPRT0_TypeDef hprt0; + + hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); + hprt0.b.prtena = 0; + hprt0.b.prtconndet = 0; + hprt0.b.prtenchng = 0; + hprt0.b.prtovrcurrchng = 0; + return hprt0.d32; +} + + +/** +* @brief USB_OTG_ReadHostAllChannels_intr : Register PCD Callbacks +* @param pdev : Selected device +* @retval Status +*/ +uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev) +{ + return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT)); +} + + +/** +* @brief USB_OTG_ResetPort : Reset Host Port +* @param pdev : Selected device +* @retval status +* @note : (1)The application must wait at least 10 ms (+ 10 ms security) +* before clearing the reset bit. +*/ +uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_HPRT0_TypeDef hprt0; + + hprt0.d32 = USB_OTG_ReadHPRT0(pdev); + hprt0.b.prtrst = 1; + USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); + USB_OTG_BSP_mDelay (100); /* See Note #1 */ + hprt0.b.prtrst = 0; + USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); + USB_OTG_BSP_mDelay (20); + return 1; +} + + +/** +* @brief USB_OTG_HC_Init : Prepares a host channel for transferring packets +* @param pdev : Selected device +* @param hc_num : channel number +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) +{ + USB_OTG_STS status = USB_OTG_OK; + uint32_t intr_enable = 0; + USB_OTG_HCINTMSK_TypeDef hcintmsk; + USB_OTG_GINTMSK_TypeDef gintmsk; + USB_OTG_HCCHAR_TypeDef hcchar; + USB_OTG_HCINTn_TypeDef hcint; + + + gintmsk.d32 = 0; + hcintmsk.d32 = 0; + hcchar.d32 = 0; + + /* Clear old interrupt conditions for this host channel. */ + hcint.d32 = 0xFFFFFFFF; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32); + + /* Enable channel interrupts required for this transfer. */ + hcintmsk.d32 = 0; + + if (pdev->cfg.dma_enable == 1) + { + hcintmsk.b.ahberr = 1; + } + + switch (pdev->host.hc[hc_num].ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + hcintmsk.b.xfercompl = 1; + hcintmsk.b.stall = 1; + hcintmsk.b.xacterr = 1; + hcintmsk.b.datatglerr = 1; + hcintmsk.b.nak = 1; + if (pdev->host.hc[hc_num].ep_is_in) + { + hcintmsk.b.bblerr = 1; + } + else + { + hcintmsk.b.nyet = 1; + if (pdev->host.hc[hc_num].do_ping) + { + hcintmsk.b.ack = 1; + } + } + break; + case EP_TYPE_INTR: + hcintmsk.b.xfercompl = 1; + hcintmsk.b.nak = 1; + hcintmsk.b.stall = 1; + hcintmsk.b.xacterr = 1; + hcintmsk.b.datatglerr = 1; + hcintmsk.b.frmovrun = 1; + + if (pdev->host.hc[hc_num].ep_is_in) + { + hcintmsk.b.bblerr = 1; + } + + break; + case EP_TYPE_ISOC: + hcintmsk.b.xfercompl = 1; + hcintmsk.b.frmovrun = 1; + hcintmsk.b.ack = 1; + + if (pdev->host.hc[hc_num].ep_is_in) + { + hcintmsk.b.xacterr = 1; + hcintmsk.b.bblerr = 1; + } + break; + } + + + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, hcintmsk.d32); + + + /* Enable the top level host channel interrupt. */ + intr_enable = (1 << hc_num); + USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable); + + /* Make sure host channel interrupts are enabled. */ + gintmsk.b.hcintr = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32); + + /* Program the HCCHAR register */ + hcchar.d32 = 0; + hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr; + hcchar.b.epnum = pdev->host.hc[hc_num].ep_num; + hcchar.b.epdir = pdev->host.hc[hc_num].ep_is_in; + hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED); + hcchar.b.eptype = pdev->host.hc[hc_num].ep_type; + hcchar.b.mps = pdev->host.hc[hc_num].max_packet; + if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR) + { + hcchar.b.oddfrm = 1; + } + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); + return status; +} + + +/** +* @brief USB_OTG_HC_StartXfer : Start transfer +* @param pdev : Selected device +* @param hc_num : channel number +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_HCCHAR_TypeDef hcchar; + USB_OTG_HCTSIZn_TypeDef hctsiz; + USB_OTG_HNPTXSTS_TypeDef hnptxsts; + USB_OTG_HPTXSTS_TypeDef hptxsts; + USB_OTG_GINTMSK_TypeDef intmsk; + uint16_t len_words = 0; + + uint16_t num_packets; + uint16_t max_hc_pkt_count; + + max_hc_pkt_count = 256; + hctsiz.d32 = 0; + hcchar.d32 = 0; + intmsk.d32 = 0; + + /* Compute the expected number of packets associated to the transfer */ + if (pdev->host.hc[hc_num].xfer_len > 0) + { + num_packets = (pdev->host.hc[hc_num].xfer_len + \ + pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet; + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + pdev->host.hc[hc_num].xfer_len = num_packets * \ + pdev->host.hc[hc_num].max_packet; + } + } + else + { + num_packets = 1; + } + if (pdev->host.hc[hc_num].ep_is_in) + { + pdev->host.hc[hc_num].xfer_len = num_packets * \ + pdev->host.hc[hc_num].max_packet; + } + /* Initialize the HCTSIZn register */ + hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len; + hctsiz.b.pktcnt = num_packets; + hctsiz.b.pid = pdev->host.hc[hc_num].data_pid; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); + + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff); + } + + + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); + hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev); + + /* Set host channel enable */ + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); + + if (pdev->cfg.dma_enable == 0) /* Slave mode */ + { + if((pdev->host.hc[hc_num].ep_is_in == 0) && + (pdev->host.hc[hc_num].xfer_len > 0)) + { + switch(pdev->host.hc[hc_num].ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); + len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; + + /* check if there is enough space in FIFO space */ + if(len_words > hnptxsts.b.nptxfspcavail) + { + /* need to process data in nptxfempty interrupt */ + intmsk.b.nptxfempty = 1; + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); + } + + break; + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); + len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; + /* check if there is enough space in FIFO space */ + if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + intmsk.b.ptxfempty = 1; + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + USB_OTG_WritePacket(pdev, + pdev->host.hc[hc_num].xfer_buff , + hc_num, pdev->host.hc[hc_num].xfer_len); + } + } + return status; +} + + +/** +* @brief USB_OTG_HC_Halt : Halt channel +* @param pdev : Selected device +* @param hc_num : channel number +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_HNPTXSTS_TypeDef nptxsts; + USB_OTG_HPTXSTS_TypeDef hptxsts; + USB_OTG_HCCHAR_TypeDef hcchar; + + nptxsts.d32 = 0; + hptxsts.d32 = 0; + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); + + hcchar.b.chdis = 1; + + /* Check for space in the request queue to issue the halt. */ + if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK) + { + nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); + if (nptxsts.b.nptxqspcavail == 0) + { + hcchar.b.chen = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); + } + } + else + { + hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); + if (hptxsts.b.ptxqspcavail == 0) + { + hcchar.b.chen = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); + } + } + hcchar.b.chen = 1; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); + return status; +} + +/** +* @brief Issue a ping token +* @param None +* @retval : None +*/ +USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_HCCHAR_TypeDef hcchar; + USB_OTG_HCTSIZn_TypeDef hctsiz; + + hctsiz.d32 = 0; + hctsiz.b.dopng = 1; + hctsiz.b.pktcnt = 1; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); + + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); + return status; +} + +/** +* @brief Stop the device and clean up fifo's +* @param None +* @retval : None +*/ +void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_HCCHAR_TypeDef hcchar; + uint32_t i; + + USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0); + USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF); + /* Flush out any leftover queued requests. */ + + for (i = 0; i < pdev->cfg.host_channels; i++) + { + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); + hcchar.b.chen = 0; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32); + } + + /* Flush the FIFO */ + USB_OTG_FlushRxFifo(pdev); + USB_OTG_FlushTxFifo(pdev , 0x10 ); +} +#endif +#ifdef USE_DEVICE_MODE +/* PCD Core Layer */ + +/** +* @brief USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register +* depending the PHY type and the enumeration speed of the device. +* @param pdev : Selected device +* @retval : None +*/ +void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed) +{ + USB_OTG_DCFG_TypeDef dcfg; + + dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG); + dcfg.b.devspd = speed; + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32); +} + + +/** +* @brief USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers +* for device mode +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + uint32_t i; + USB_OTG_DCFG_TypeDef dcfg; + USB_OTG_FSIZ_TypeDef nptxfifosize; + USB_OTG_FSIZ_TypeDef txfifosize; + USB_OTG_DIEPMSK_TypeDef msk; + USB_OTG_DTHRCTL_TypeDef dthrctl; + + depctl.d32 = 0; + dcfg.d32 = 0; + nptxfifosize.d32 = 0; + txfifosize.d32 = 0; + msk.d32 = 0; + + /* Restart the Phy Clock */ + USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); + /* Device configuration register */ + dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); + dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80; + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 ); + +#ifdef USB_OTG_FS_CORE + if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID ) + { + + /* Set Full speed phy */ + USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL); + + /* set Rx FIFO size */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); + + /* EP0 TX*/ + nptxfifosize.b.depth = TX0_FIFO_FS_SIZE; + nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); + + + /* EP1 TX*/ + txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; + txfifosize.b.depth = TX1_FIFO_FS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); + + + /* EP2 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX2_FIFO_FS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); + + + /* EP3 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX3_FIFO_FS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); + } +#endif +#ifdef USB_OTG_HS_CORE + if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID ) + { + + /* Set High speed phy */ + + if(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) + { + USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH); + } + else /* set High speed phy in Full speed mode */ + { + USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL); + } + + /* set Rx FIFO size */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); + + /* EP0 TX*/ + nptxfifosize.b.depth = TX0_FIFO_HS_SIZE; + nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); + + + /* EP1 TX*/ + txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; + txfifosize.b.depth = TX1_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); + + + /* EP2 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX2_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); + + + /* EP3 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX3_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); + + /* EP4 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX4_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 ); + + + /* EP5 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX5_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 ); + } +#endif + /* Flush the FIFOs */ + USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */ + USB_OTG_FlushRxFifo(pdev); + /* Clear all pending Device Interrupts */ + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); + + for (i = 0; i < pdev->cfg.dev_endpoints; i++) + { + depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL); + if (depctl.b.epena) + { + depctl.d32 = 0; + depctl.b.epdis = 1; + depctl.b.snak = 1; + } + else + { + depctl.d32 = 0; + } + USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32); + USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0); + USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); + } + for (i = 0; i < pdev->cfg.dev_endpoints; i++) + { + USB_OTG_DEPCTL_TypeDef depctl; + depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL); + if (depctl.b.epena) + { + depctl.d32 = 0; + depctl.b.epdis = 1; + depctl.b.snak = 1; + } + else + { + depctl.d32 = 0; + } + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32); + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0); + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); + } + msk.d32 = 0; + msk.b.txfifoundrn = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32); + + if (pdev->cfg.dma_enable == 1) + { + dthrctl.d32 = 0; + dthrctl.b.non_iso_thr_en = 1; + dthrctl.b.iso_thr_en = 1; + dthrctl.b.tx_thr_len = 64; + dthrctl.b.rx_thr_en = 1; + dthrctl.b.rx_thr_len = 64; + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32); + } + USB_OTG_EnableDevInt(pdev); + return status; +} + + +/** +* @brief USB_OTG_EnableDevInt : Enables the Device mode interrupts +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GINTMSK_TypeDef intmsk; + + intmsk.d32 = 0; + + /* Disable all interrupts. */ + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0); + /* Clear any pending interrupts */ + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); + /* Enable the common interrupts */ + USB_OTG_EnableCommonInt(pdev); + + if (pdev->cfg.dma_enable == 0) + { + intmsk.b.rxstsqlvl = 1; + } + + /* Enable interrupts matching to the Device mode ONLY */ + intmsk.b.usbsuspend = 1; + intmsk.b.usbreset = 1; + intmsk.b.enumdone = 1; + intmsk.b.inepintr = 1; + intmsk.b.outepintr = 1; + intmsk.b.sofintr = 1; + + intmsk.b.incomplisoin = 1; + intmsk.b.incomplisoout = 1; +#ifdef VBUS_SENSING_ENABLED + intmsk.b.sessreqintr = 1; + intmsk.b.otgintr = 1; +#endif + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); + return status; +} + + +/** +* @brief USB_OTG_GetDeviceSpeed +* Get the device speed from the device status register +* @param None +* @retval status +*/ +enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_DSTS_TypeDef dsts; + enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN; + + + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + + switch (dsts.b.enumspd) + { + case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: + speed = USB_SPEED_HIGH; + break; + case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: + case DSTS_ENUMSPD_FS_PHY_48MHZ: + speed = USB_SPEED_FULL; + break; + + case DSTS_ENUMSPD_LS_PHY_6MHZ: + speed = USB_SPEED_LOW; + break; + default: + speed = USB_SPEED_FULL; + break; + } + + return speed; +} + +/** +* @brief enables EP0 OUT to receive SETUP packets and configures EP0 +* for transmitting packets +* @param None +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DSTS_TypeDef dsts; + USB_OTG_DEPCTL_TypeDef diepctl; + USB_OTG_DCTL_TypeDef dctl; + + dctl.d32 = 0; + /* Read the Device Status and Endpoint 0 Control registers */ + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL); + /* Set the MPS of the IN EP based on the enumeration speed */ + switch (dsts.b.enumspd) + { + case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: + case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: + case DSTS_ENUMSPD_FS_PHY_48MHZ: + diepctl.b.mps = DEP0CTL_MPS_64; + break; + case DSTS_ENUMSPD_LS_PHY_6MHZ: + diepctl.b.mps = DEP0CTL_MPS_8; + break; + default: + diepctl.b.mps = DEP0CTL_MPS_64; + break; + } + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32); + dctl.b.cgnpinnak = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32); + return status; +} + + +/** +* @brief USB_OTG_EPActivate : Activates an EP +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + USB_OTG_DAINT_TypeDef daintmsk; + __IO uint32_t *addr; + + + depctl.d32 = 0; + daintmsk.d32 = 0; + /* Read DEPCTLn register */ + if (ep->is_in == 1) + { + addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; + daintmsk.ep.in = 1 << ep->num; + } + else + { + addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; + daintmsk.ep.out = 1 << ep->num; + } + /* If the EP is already active don't change the EP Control + * register. */ + depctl.d32 = USB_OTG_READ_REG32(addr); + if (!depctl.b.usbactep) + { + depctl.b.mps = ep->maxpacket; + depctl.b.eptype = ep->type; + depctl.b.txfnum = ep->tx_fifo_num; + depctl.b.setd0pid = 1; + depctl.b.usbactep = 1; + USB_OTG_WRITE_REG32(addr, depctl.d32); + } + /* Enable the Interrupt for this EP */ +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) + { + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32); + } + else +#endif + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32); + return status; +} + + +/** +* @brief USB_OTG_EPDeactivate : Deactivates an EP +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + USB_OTG_DAINT_TypeDef daintmsk; + __IO uint32_t *addr; + + depctl.d32 = 0; + daintmsk.d32 = 0; + /* Read DEPCTLn register */ + if (ep->is_in == 1) + { + addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; + daintmsk.ep.in = 1 << ep->num; + } + else + { + addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; + daintmsk.ep.out = 1 << ep->num; + } + depctl.b.usbactep = 0; + USB_OTG_WRITE_REG32(addr, depctl.d32); + /* Disable the Interrupt for this EP */ + +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) + { + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0); + } + else +#endif + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0); + return status; +} + + +/** +* @brief USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and +* starts the xfer +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + USB_OTG_DEPXFRSIZ_TypeDef deptsiz; + USB_OTG_DSTS_TypeDef dsts; + uint32_t fifoemptymsk = 0; + + depctl.d32 = 0; + deptsiz.d32 = 0; + /* IN endpoint */ + if (ep->is_in == 1) + { + depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL)); + deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ)); + /* Zero Length Packet? */ + if (ep->xfer_len == 0) + { + deptsiz.b.xfersize = 0; + deptsiz.b.pktcnt = 1; + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + deptsiz.b.xfersize = ep->xfer_len; + deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; + + if (ep->type == EP_TYPE_ISOC) + { + deptsiz.b.mc = 1; + } + } + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32); + + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); + } + else + { + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0) + { + fifoemptymsk = 1 << ep->num; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); + } + } + } + + + if (ep->type == EP_TYPE_ISOC) + { + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + + if (((dsts.b.soffn)&0x1) == 0) + { + depctl.b.setd1pid = 1; + } + else + { + depctl.b.setd0pid = 1; + } + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32); + + if (ep->type == EP_TYPE_ISOC) + { + USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len); + } + } + else + { + /* OUT endpoint */ + depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL)); + deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ)); + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + if (ep->xfer_len == 0) + { + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; + } + else + { + deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; + ep->xfer_len = deptsiz.b.xfersize ; + } + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); + + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); + } + + if (ep->type == EP_TYPE_ISOC) + { + if (ep->even_odd_frame) + { + depctl.b.setd1pid = 1; + } + else + { + depctl.b.setd0pid = 1; + } + } + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32); + } + return status; +} + + +/** +* @brief USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and +* starts the xfer +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + USB_OTG_DEP0XFRSIZ_TypeDef deptsiz; + USB_OTG_INEPREGS *in_regs; + uint32_t fifoemptymsk = 0; + + depctl.d32 = 0; + deptsiz.d32 = 0; + /* IN endpoint */ + if (ep->is_in == 1) + { + in_regs = pdev->regs.INEP_REGS[0]; + depctl.d32 = USB_OTG_READ_REG32(&in_regs->DIEPCTL); + deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ); + /* Zero Length Packet? */ + if (ep->xfer_len == 0) + { + deptsiz.b.xfersize = 0; + deptsiz.b.pktcnt = 1; + + } + else + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + deptsiz.b.xfersize = ep->maxpacket; + } + else + { + deptsiz.b.xfersize = ep->xfer_len; + } + deptsiz.b.pktcnt = 1; + } + USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32); + + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32); + + + + if (pdev->cfg.dma_enable == 0) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0) + { + { + fifoemptymsk |= 1 << ep->num; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); + } + } + } + } + else + { + /* OUT endpoint */ + depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); + deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ); + /* Program the transfer size and packet count as follows: + * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) + * pktcnt = N */ + if (ep->xfer_len == 0) + { + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; + } + else + { + ep->xfer_len = ep->maxpacket; + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; + } + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); + } + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32); + + } + return status; +} + + +/** +* @brief USB_OTG_EPSetStall : Set the EP STALL +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + __IO uint32_t *depctl_addr; + + depctl.d32 = 0; + if (ep->is_in == 1) + { + depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + /* set the disable and stall bits */ + if (depctl.b.epena) + { + depctl.b.epdis = 1; + } + depctl.b.stall = 1; + USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); + } + else + { + depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + /* set the stall bit */ + depctl.b.stall = 1; + USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); + } + return status; +} + + +/** +* @brief Clear the EP STALL +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + __IO uint32_t *depctl_addr; + + depctl.d32 = 0; + + if (ep->is_in == 1) + { + depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); + } + else + { + depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); + } + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + /* clear the stall bits */ + depctl.b.stall = 0; + if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + { + depctl.b.setd0pid = 1; /* DATA0 */ + } + USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); + return status; +} + + +/** +* @brief USB_OTG_ReadDevAllOutEp_itr : returns OUT endpoint interrupt bits +* @param pdev : Selected device +* @retval OUT endpoint interrupt bits +*/ +uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t v; + v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); + v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); + return ((v & 0xffff0000) >> 16); +} + + +/** +* @brief USB_OTG_ReadDevOutEP_itr : returns Device OUT EP Interrupt register +* @param pdev : Selected device +* @param ep : end point number +* @retval Device OUT EP Interrupt register +*/ +uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) +{ + uint32_t v; + v = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT); + v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK); + return v; +} + + +/** +* @brief USB_OTG_ReadDevAllInEPItr : Get int status register +* @param pdev : Selected device +* @retval int status register +*/ +uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t v; + v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); + v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); + return (v & 0xffff); +} + +/** +* @brief configures EPO to receive SETUP packets +* @param None +* @retval : None +*/ +void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_DEP0XFRSIZ_TypeDef doeptsize0; + doeptsize0.d32 = 0; + doeptsize0.b.supcnt = 3; + doeptsize0.b.pktcnt = 1; + doeptsize0.b.xfersize = 8 * 3; + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 ); + + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_DEPCTL_TypeDef doepctl; + doepctl.d32 = 0; + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA, + (uint32_t)&pdev->dev.setup_packet); + + /* EP enable */ + doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL); + doepctl.b.epena = 1; + doepctl.d32 = 0x80008000; + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32); + } +} + +/** +* @brief USB_OTG_RemoteWakeup : active remote wakeup signalling +* @param None +* @retval : None +*/ +void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev) +{ + + USB_OTG_DCTL_TypeDef dctl; + USB_OTG_DSTS_TypeDef dsts; + USB_OTG_PCGCCTL_TypeDef power; + + if (pdev->dev.DevRemoteWakeup) + { + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + if(dsts.b.suspsts == 1) + { + if(pdev->cfg.low_power) + { + /* un-gate USB Core clock */ + power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL); + power.b.gatehclk = 0; + power.b.stoppclk = 0; + USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); + } + /* active Remote wakeup signaling */ + dctl.d32 = 0; + dctl.b.rmtwkupsig = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32); + USB_OTG_BSP_mDelay(5); + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); + } + } +} + + +/** +* @brief USB_OTG_UngateClock : active USB Core clock +* @param None +* @retval : None +*/ +void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev) +{ + if(pdev->cfg.low_power) + { + + USB_OTG_DSTS_TypeDef dsts; + USB_OTG_PCGCCTL_TypeDef power; + + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + + if(dsts.b.suspsts == 1) + { + /* un-gate USB Core clock */ + power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL); + power.b.gatehclk = 0; + power.b.stoppclk = 0; + USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); + + } + } +} + +/** +* @brief Stop the device and clean up fifo's +* @param None +* @retval : None +*/ +void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t i; + + pdev->dev.device_status = 1; + + for (i = 0; i < pdev->cfg.dev_endpoints ; i++) + { + USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); + } + + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); + + /* Flush the FIFO */ + USB_OTG_FlushRxFifo(pdev); + USB_OTG_FlushTxFifo(pdev , 0x10 ); +} + +/** +* @brief returns the EP Status +* @param pdev : Selected device +* ep : endpoint structure +* @retval : EP status +*/ + +uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep) +{ + USB_OTG_DEPCTL_TypeDef depctl; + __IO uint32_t *depctl_addr; + uint32_t Status = 0; + + depctl.d32 = 0; + if (ep->is_in == 1) + { + depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + + if (depctl.b.stall == 1) + { + Status = USB_OTG_EP_TX_STALL; + } + else if (depctl.b.naksts == 1) + { + Status = USB_OTG_EP_TX_NAK; + } + else + { + Status = USB_OTG_EP_TX_VALID; + } + } + else + { + depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + if (depctl.b.stall == 1) + { + Status = USB_OTG_EP_RX_STALL; + } + else if (depctl.b.naksts == 1) + { + Status = USB_OTG_EP_RX_NAK; + } + else + { + Status = USB_OTG_EP_RX_VALID; + } + } + + /* Return the current status */ + return Status; +} + +/** +* @brief Set the EP Status +* @param pdev : Selected device +* Status : new Status +* ep : EP structure +* @retval : None +*/ +void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status) +{ + USB_OTG_DEPCTL_TypeDef depctl; + __IO uint32_t *depctl_addr; + + depctl.d32 = 0; + + /* Process for IN endpoint */ + if (ep->is_in == 1) + { + depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + + if (Status == USB_OTG_EP_TX_STALL) + { + USB_OTG_EPSetStall(pdev, ep); return; + } + else if (Status == USB_OTG_EP_TX_NAK) + { + depctl.b.snak = 1; + } + else if (Status == USB_OTG_EP_TX_VALID) + { + if (depctl.b.stall == 1) + { + ep->even_odd_frame = 0; + USB_OTG_EPClearStall(pdev, ep); + return; + } + depctl.b.cnak = 1; + depctl.b.usbactep = 1; + depctl.b.epena = 1; + } + else if (Status == USB_OTG_EP_TX_DIS) + { + depctl.b.usbactep = 0; + } + + else + { + /* Do Nothing */ + } + } + else /* Process for OUT endpoint */ + { + depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + + if (Status == USB_OTG_EP_RX_STALL) { + depctl.b.stall = 1; + } + else if (Status == USB_OTG_EP_RX_NAK) + { + depctl.b.snak = 1; + } + else if (Status == USB_OTG_EP_RX_VALID) + { + if (depctl.b.stall == 1) + { + ep->even_odd_frame = 0; + USB_OTG_EPClearStall(pdev, ep); + return; + } + depctl.b.cnak = 1; + depctl.b.usbactep = 1; + depctl.b.epena = 1; + } + else if (Status == USB_OTG_EP_RX_DIS) + { + depctl.b.usbactep = 0; + } + + else + { + /* Do Nothing */ + } + } + + USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); +} + +#endif +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd.c index 8ddabcd7f..5fe6e55e2 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd.c @@ -1,488 +1,488 @@ -/** - ****************************************************************************** - * @file usb_dcd.c - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief Peripheral Device Interface Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" -#include "usb_bsp.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD -* @brief This file is the interface between EFSL ans Host mass-storage class -* @{ -*/ - - -/** @defgroup USB_DCD_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_DCD_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_FunctionPrototypes -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_Functions -* @{ -*/ - - - -void DCD_Init(USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint32_t i; - USB_OTG_EP *ep; - - USB_OTG_SelectCore (pdev , coreID); - - pdev->dev.device_status = USB_OTG_DEFAULT; - pdev->dev.device_address = 0; - - /* Init ep structure */ - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - ep = &pdev->dev.in_ep[i]; - /* Init ep structure */ - ep->is_in = 1; - ep->num = i; - ep->tx_fifo_num = i; - /* Control until ep is activated */ - ep->type = EP_TYPE_CTRL; - ep->maxpacket = USB_OTG_MAX_EP0_SIZE; - ep->xfer_buff = 0; - ep->xfer_len = 0; - } - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - ep = &pdev->dev.out_ep[i]; - /* Init ep structure */ - ep->is_in = 0; - ep->num = i; - ep->tx_fifo_num = i; - /* Control until ep is activated */ - ep->type = EP_TYPE_CTRL; - ep->maxpacket = USB_OTG_MAX_EP0_SIZE; - ep->xfer_buff = 0; - ep->xfer_len = 0; - } - - USB_OTG_DisableGlobalInt(pdev); - -#if defined (STM32F446xx) || defined (STM32F469_479xx) - - /* Force Device Mode*/ - USB_OTG_SetCurrentMode(pdev, DEVICE_MODE); - - /*Init the Core (common init.) */ - USB_OTG_CoreInit(pdev); - -#else - - /*Init the Core (common init.) */ - USB_OTG_CoreInit(pdev); - - /* Force Device Mode*/ - USB_OTG_SetCurrentMode(pdev, DEVICE_MODE); - -#endif - - /* Init Device */ - USB_OTG_CoreInitDev(pdev); - - /* Enable USB Global interrupt */ - USB_OTG_EnableGlobalInt(pdev); -} - - -/** -* @brief Configure an EP -* @param pdev : Device instance -* @param epdesc : Endpoint Descriptor -* @retval : status -*/ -uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , - uint8_t ep_addr, - uint16_t ep_mps, - uint8_t ep_type) -{ - USB_OTG_EP *ep; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - ep->maxpacket = ep_mps; - ep->type = ep_type; - if (ep->is_in) - { - /* Assign a Tx FIFO */ - ep->tx_fifo_num = ep->num; - } - /* Set initial data PID. */ - if (ep_type == USB_OTG_EP_BULK ) - { - ep->data_pid_start = 0; - } - USB_OTG_EPActivate(pdev , ep ); - return 0; -} -/** -* @brief called when an EP is disabled -* @param pdev: device instance -* @param ep_addr: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Close(USB_OTG_CORE_HANDLE *pdev , uint8_t ep_addr) -{ - USB_OTG_EP *ep; - - if ((ep_addr&0x80) == 0x80) - { - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - ep->is_in = (0x80 & ep_addr) != 0; - USB_OTG_EPDeactivate(pdev , ep ); - return 0; -} - - -/** -* @brief DCD_EP_PrepareRx -* @param pdev: device instance -* @param ep_addr: endpoint address -* @param pbuf: pointer to Rx buffer -* @param buf_len: data length -* @retval : status -*/ -uint32_t DCD_EP_PrepareRx( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t buf_len) -{ - USB_OTG_EP *ep; - - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; - - if (pdev->cfg.dma_enable == 1) - { - ep->dma_addr = (uint32_t)pbuf; - } - - if ( ep->num == 0 ) - { - USB_OTG_EP0StartXfer(pdev , ep); - } - else - { - USB_OTG_EPStartXfer(pdev, ep ); - } - return 0; -} - -/** -* @brief Transmit data over USB -* @param pdev: device instance -* @param ep_addr: endpoint address -* @param pbuf: pointer to Tx buffer -* @param buf_len: data length -* @retval : status -*/ -uint32_t DCD_EP_Tx ( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - const uint8_t *pbuf, - uint32_t buf_len) // modified by OpenTX -{ - USB_OTG_EP *ep; - - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - - /* Setup and start the Transfer */ - ep->is_in = 1; - ep->num = ep_addr & 0x7F; - ep->xfer_buff = (uint8_t*)pbuf; //remove const qualifier, safe to do because we are sending // modified by OpenTX - ep->dma_addr = (uint32_t)pbuf; - ep->xfer_count = 0; - ep->xfer_len = buf_len; - - if ( ep->num == 0 ) - { - USB_OTG_EP0StartXfer(pdev , ep); - } - else - { - USB_OTG_EPStartXfer(pdev, ep ); - } - return 0; -} - - -/** -* @brief Stall an endpoint. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - USB_OTG_EP *ep; - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - ep->is_stall = 1; - ep->num = epnum & 0x7F; - ep->is_in = ((epnum & 0x80) == 0x80); - - USB_OTG_EPSetStall(pdev , ep); - return (0); -} - - -/** -* @brief Clear stall condition on endpoints. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - USB_OTG_EP *ep; - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - ep->is_stall = 0; - ep->num = epnum & 0x7F; - ep->is_in = ((epnum & 0x80) == 0x80); - - USB_OTG_EPClearStall(pdev , ep); - return (0); -} - - -/** -* @brief This Function flushes the FIFOs. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - - if ((epnum & 0x80) == 0x80) - { - USB_OTG_FlushTxFifo(pdev, epnum & 0x7F); - } - else - { - USB_OTG_FlushRxFifo(pdev); - } - - return (0); -} - - -/** -* @brief This Function set USB device address -* @param pdev: device instance -* @param address: new device address -* @retval : status -*/ -void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, uint8_t address) -{ - USB_OTG_DCFG_TypeDef dcfg; - dcfg.d32 = 0; - dcfg.b.devaddr = address; - USB_OTG_MODIFY_REG32( &pdev->regs.DREGS->DCFG, 0, dcfg.d32); -} - -/** -* @brief Connect device (enable internal pull-up) -* @param pdev: device instance -* @retval : None -*/ -void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev) -{ -#ifndef USE_OTG_MODE - USB_OTG_DCTL_TypeDef dctl; - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - /* Connect device */ - dctl.b.sftdiscon = 0; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); - USB_OTG_BSP_mDelay(3); -#endif -} - - -/** -* @brief Disconnect device (disable internal pull-up) -* @param pdev: device instance -* @retval : None -*/ -void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev) -{ -#ifndef USE_OTG_MODE - USB_OTG_DCTL_TypeDef dctl; - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - /* Disconnect device for 3ms */ - dctl.b.sftdiscon = 1; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); - USB_OTG_BSP_mDelay(3); -#endif -} - - -/** -* @brief returns the EP Status -* @param pdev : Selected device -* epnum : endpoint address -* @retval : EP status -*/ - -uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,uint8_t epnum) -{ - USB_OTG_EP *ep; - uint32_t Status = 0; - - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - Status = USB_OTG_GetEPStatus(pdev ,ep); - - /* Return the current status */ - return Status; -} - -/** -* @brief Set the EP Status -* @param pdev : Selected device -* Status : new Status -* epnum : EP address -* @retval : None -*/ -void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum , uint32_t Status) -{ - USB_OTG_EP *ep; - - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - USB_OTG_SetEPStatus(pdev ,ep , Status); -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usb_dcd.c + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief Peripheral Device Interface Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_dcd.h" +#include "usb_bsp.h" + + +/** @addtogroup USB_OTG_DRIVER +* @{ +*/ + +/** @defgroup USB_DCD +* @brief This file is the interface between EFSL ans Host mass-storage class +* @{ +*/ + + +/** @defgroup USB_DCD_Private_Defines +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + + +/** @defgroup USB_DCD_Private_Macros +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_Private_Variables +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USB_DCD_Private_Functions +* @{ +*/ + + + +void DCD_Init(USB_OTG_CORE_HANDLE *pdev , + USB_OTG_CORE_ID_TypeDef coreID) +{ + uint32_t i; + USB_OTG_EP *ep; + + USB_OTG_SelectCore (pdev , coreID); + + pdev->dev.device_status = USB_OTG_DEFAULT; + pdev->dev.device_address = 0; + + /* Init ep structure */ + for (i = 0; i < pdev->cfg.dev_endpoints ; i++) + { + ep = &pdev->dev.in_ep[i]; + /* Init ep structure */ + ep->is_in = 1; + ep->num = i; + ep->tx_fifo_num = i; + /* Control until ep is activated */ + ep->type = EP_TYPE_CTRL; + ep->maxpacket = USB_OTG_MAX_EP0_SIZE; + ep->xfer_buff = 0; + ep->xfer_len = 0; + } + + for (i = 0; i < pdev->cfg.dev_endpoints; i++) + { + ep = &pdev->dev.out_ep[i]; + /* Init ep structure */ + ep->is_in = 0; + ep->num = i; + ep->tx_fifo_num = i; + /* Control until ep is activated */ + ep->type = EP_TYPE_CTRL; + ep->maxpacket = USB_OTG_MAX_EP0_SIZE; + ep->xfer_buff = 0; + ep->xfer_len = 0; + } + + USB_OTG_DisableGlobalInt(pdev); + +#if defined (STM32F446xx) || defined (STM32F469_479xx) + + /* Force Device Mode*/ + USB_OTG_SetCurrentMode(pdev, DEVICE_MODE); + + /*Init the Core (common init.) */ + USB_OTG_CoreInit(pdev); + +#else + + /*Init the Core (common init.) */ + USB_OTG_CoreInit(pdev); + + /* Force Device Mode*/ + USB_OTG_SetCurrentMode(pdev, DEVICE_MODE); + +#endif + + /* Init Device */ + USB_OTG_CoreInitDev(pdev); + + /* Enable USB Global interrupt */ + USB_OTG_EnableGlobalInt(pdev); +} + + +/** +* @brief Configure an EP +* @param pdev : Device instance +* @param epdesc : Endpoint Descriptor +* @retval : status +*/ +uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , + uint8_t ep_addr, + uint16_t ep_mps, + uint8_t ep_type) +{ + USB_OTG_EP *ep; + + if ((ep_addr & 0x80) == 0x80) + { + ep = &pdev->dev.in_ep[ep_addr & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[ep_addr & 0x7F]; + } + ep->num = ep_addr & 0x7F; + + ep->is_in = (0x80 & ep_addr) != 0; + ep->maxpacket = ep_mps; + ep->type = ep_type; + if (ep->is_in) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + /* Set initial data PID. */ + if (ep_type == USB_OTG_EP_BULK ) + { + ep->data_pid_start = 0; + } + USB_OTG_EPActivate(pdev , ep ); + return 0; +} +/** +* @brief called when an EP is disabled +* @param pdev: device instance +* @param ep_addr: endpoint address +* @retval : status +*/ +uint32_t DCD_EP_Close(USB_OTG_CORE_HANDLE *pdev , uint8_t ep_addr) +{ + USB_OTG_EP *ep; + + if ((ep_addr&0x80) == 0x80) + { + ep = &pdev->dev.in_ep[ep_addr & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[ep_addr & 0x7F]; + } + ep->num = ep_addr & 0x7F; + ep->is_in = (0x80 & ep_addr) != 0; + USB_OTG_EPDeactivate(pdev , ep ); + return 0; +} + + +/** +* @brief DCD_EP_PrepareRx +* @param pdev: device instance +* @param ep_addr: endpoint address +* @param pbuf: pointer to Rx buffer +* @param buf_len: data length +* @retval : status +*/ +uint32_t DCD_EP_PrepareRx( USB_OTG_CORE_HANDLE *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t buf_len) +{ + USB_OTG_EP *ep; + + ep = &pdev->dev.out_ep[ep_addr & 0x7F]; + + /*setup and start the Xfer */ + ep->xfer_buff = pbuf; + ep->xfer_len = buf_len; + ep->xfer_count = 0; + ep->is_in = 0; + ep->num = ep_addr & 0x7F; + + if (pdev->cfg.dma_enable == 1) + { + ep->dma_addr = (uint32_t)pbuf; + } + + if ( ep->num == 0 ) + { + USB_OTG_EP0StartXfer(pdev , ep); + } + else + { + USB_OTG_EPStartXfer(pdev, ep ); + } + return 0; +} + +/** +* @brief Transmit data over USB +* @param pdev: device instance +* @param ep_addr: endpoint address +* @param pbuf: pointer to Tx buffer +* @param buf_len: data length +* @retval : status +*/ +uint32_t DCD_EP_Tx ( USB_OTG_CORE_HANDLE *pdev, + uint8_t ep_addr, + const uint8_t *pbuf, + uint32_t buf_len) // modified by OpenTX +{ + USB_OTG_EP *ep; + + ep = &pdev->dev.in_ep[ep_addr & 0x7F]; + + /* Setup and start the Transfer */ + ep->is_in = 1; + ep->num = ep_addr & 0x7F; + ep->xfer_buff = (uint8_t*)pbuf; //remove const qualifier, safe to do because we are sending // modified by OpenTX + ep->dma_addr = (uint32_t)pbuf; + ep->xfer_count = 0; + ep->xfer_len = buf_len; + + if ( ep->num == 0 ) + { + USB_OTG_EP0StartXfer(pdev , ep); + } + else + { + USB_OTG_EPStartXfer(pdev, ep ); + } + return 0; +} + + +/** +* @brief Stall an endpoint. +* @param pdev: device instance +* @param epnum: endpoint address +* @retval : status +*/ +uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) +{ + USB_OTG_EP *ep; + if ((0x80 & epnum) == 0x80) + { + ep = &pdev->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[epnum]; + } + + ep->is_stall = 1; + ep->num = epnum & 0x7F; + ep->is_in = ((epnum & 0x80) == 0x80); + + USB_OTG_EPSetStall(pdev , ep); + return (0); +} + + +/** +* @brief Clear stall condition on endpoints. +* @param pdev: device instance +* @param epnum: endpoint address +* @retval : status +*/ +uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) +{ + USB_OTG_EP *ep; + if ((0x80 & epnum) == 0x80) + { + ep = &pdev->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[epnum]; + } + + ep->is_stall = 0; + ep->num = epnum & 0x7F; + ep->is_in = ((epnum & 0x80) == 0x80); + + USB_OTG_EPClearStall(pdev , ep); + return (0); +} + + +/** +* @brief This Function flushes the FIFOs. +* @param pdev: device instance +* @param epnum: endpoint address +* @retval : status +*/ +uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) +{ + + if ((epnum & 0x80) == 0x80) + { + USB_OTG_FlushTxFifo(pdev, epnum & 0x7F); + } + else + { + USB_OTG_FlushRxFifo(pdev); + } + + return (0); +} + + +/** +* @brief This Function set USB device address +* @param pdev: device instance +* @param address: new device address +* @retval : status +*/ +void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, uint8_t address) +{ + USB_OTG_DCFG_TypeDef dcfg; + dcfg.d32 = 0; + dcfg.b.devaddr = address; + USB_OTG_MODIFY_REG32( &pdev->regs.DREGS->DCFG, 0, dcfg.d32); +} + +/** +* @brief Connect device (enable internal pull-up) +* @param pdev: device instance +* @retval : None +*/ +void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev) +{ +#ifndef USE_OTG_MODE + USB_OTG_DCTL_TypeDef dctl; + dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); + /* Connect device */ + dctl.b.sftdiscon = 0; + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); + USB_OTG_BSP_mDelay(3); +#endif +} + + +/** +* @brief Disconnect device (disable internal pull-up) +* @param pdev: device instance +* @retval : None +*/ +void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev) +{ +#ifndef USE_OTG_MODE + USB_OTG_DCTL_TypeDef dctl; + dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); + /* Disconnect device for 3ms */ + dctl.b.sftdiscon = 1; + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); + USB_OTG_BSP_mDelay(3); +#endif +} + + +/** +* @brief returns the EP Status +* @param pdev : Selected device +* epnum : endpoint address +* @retval : EP status +*/ + +uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,uint8_t epnum) +{ + USB_OTG_EP *ep; + uint32_t Status = 0; + + if ((0x80 & epnum) == 0x80) + { + ep = &pdev->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[epnum]; + } + + Status = USB_OTG_GetEPStatus(pdev ,ep); + + /* Return the current status */ + return Status; +} + +/** +* @brief Set the EP Status +* @param pdev : Selected device +* Status : new Status +* epnum : EP address +* @retval : None +*/ +void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum , uint32_t Status) +{ + USB_OTG_EP *ep; + + if ((0x80 & epnum) == 0x80) + { + ep = &pdev->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[epnum]; + } + + USB_OTG_SetEPStatus(pdev ,ep , Status); +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c index f1db9adaf..dbfd76d01 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c @@ -1,963 +1,963 @@ -/** - ****************************************************************************** - * @file usb_dcd_int.c - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief Peripheral Device interrupt subroutines - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd_int.h" -#include "board.h" // modified by OpenTX -#include "debug.h" // modified by OpenTX - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD_INT -* @brief This file contains the interrupt subroutines for the Device mode. -* @{ -*/ - - -/** @defgroup USB_DCD_INT_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_DCD_INT_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_FunctionPrototypes -* @{ -*/ -/* static functions */ -static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum); - -/* Interrupt Handlers */ -static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev); - -static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum); - -static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev); - -static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); -#ifdef VBUS_SENSING_ENABLED -static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev); -#endif - -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_Functions -* @{ -*/ - - -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED -/** -* @brief USBD_OTG_EP1OUT_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DOEPINTn_TypeDef doepint; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - - doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT); - doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK); - - /* Transfer complete */ - if ( doepint.b.xfercompl ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(1, xfercompl); - if (pdev->cfg.dma_enable == 1) - { - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ)); - pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].xfer_len- \ - deptsiz.b.xfersize; - } - /* Inform upper layer: data ready */ - /* RX COMPLETE */ - USBD_DCD_INT_fops->DataOutStage(pdev , 1); - - } - - /* Endpoint disable */ - if ( doepint.b.epdisabled ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(1, epdisabled); - } - - return 1; -} - -/** -* @brief USBD_OTG_EP1IN_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DIEPINTn_TypeDef diepint; - uint32_t fifoemptymsk, msk, emp; - - msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK); - emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); - msk |= ((emp >> 1 ) & 0x1) << 7; - diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk; - - if ( diepint.b.xfercompl ) - { - fifoemptymsk = 0x1 << 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); - CLEAR_IN_EP_INTR(1, xfercompl); - /* TX COMPLETE */ - USBD_DCD_INT_fops->DataInStage(pdev , 1); - } - if ( diepint.b.epdisabled ) - { - CLEAR_IN_EP_INTR(1, epdisabled); - } - if ( diepint.b.timeout ) - { - CLEAR_IN_EP_INTR(1, timeout); - } - if (diepint.b.intktxfemp) - { - CLEAR_IN_EP_INTR(1, intktxfemp); - } - if (diepint.b.inepnakeff) - { - CLEAR_IN_EP_INTR(1, inepnakeff); - } - if (diepint.b.emptyintr) - { - DCD_WriteEmptyTxFifo(pdev , 1); - } - return 1; -} -#endif - -/** -* @brief STM32_USBF_OTG_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintr_status; - uint32_t retval = 0; - - if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */ - { - gintr_status.d32 = USB_OTG_ReadCoreItr(pdev); - if (!gintr_status.d32) /* avoid spurious interrupt */ - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_SPURIOUS); // modified by OpenTX - return 0; - } - - if (gintr_status.b.outepintr) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_OUT_EP); // modified by OpenTX - retval |= DCD_HandleOutEP_ISR(pdev); - } - - if (gintr_status.b.inepint) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_IN_EP); // modified by OpenTX - retval |= DCD_HandleInEP_ISR(pdev); - } - - if (gintr_status.b.modemismatch) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_MODEMISMATCH); // modified by OpenTX - USB_OTG_GINTSTS_TypeDef gintsts; - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.modemismatch = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - } - - if (gintr_status.b.wkupintr) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_WAKEUP); // modified by OpenTX - retval |= DCD_HandleResume_ISR(pdev); - } - - if (gintr_status.b.usbsuspend) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_SUSPEND); // modified by OpenTX - retval |= DCD_HandleUSBSuspend_ISR(pdev); - } - if (gintr_status.b.sofintr) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_SOF); // modified by OpenTX - retval |= DCD_HandleSof_ISR(pdev); - - } - - if (gintr_status.b.rxstsqlvl) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_RX_STAT); // modified by OpenTX - retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev); - - } - - if (gintr_status.b.usbreset) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_RESET); // modified by OpenTX - retval |= DCD_HandleUsbReset_ISR(pdev); - - } - if (gintr_status.b.enumdone) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_ENUM); // modified by OpenTX - retval |= DCD_HandleEnumDone_ISR(pdev); - } - - if (gintr_status.b.incomplisoin) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_INCOMPLETE_IN); // modified by OpenTX - retval |= DCD_IsoINIncomplete_ISR(pdev); - } - - if (gintr_status.b.incomplisoout) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_INCOMPLETE_OUT); // modified by OpenTX - retval |= DCD_IsoOUTIncomplete_ISR(pdev); - } -#ifdef VBUS_SENSING_ENABLED - if (gintr_status.b.sessreqintr) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_SESSION); // modified by OpenTX - retval |= DCD_SessionRequest_ISR(pdev); - } - - if (gintr_status.b.otgintr) - { - DEBUG_USB_INTERRUPT(INT_OTG_FS_OTG); // modified by OpenTX - retval |= DCD_OTG_ISR(pdev); - } -#endif - } - else { - DEBUG_USB_INTERRUPT(INT_OTG_FS_RX_NOT_DEVICE); // modified by OpenTX - } - return retval; -} - -#ifdef VBUS_SENSING_ENABLED -/** -* @brief DCD_SessionRequest_ISR -* Indicates that the USB_OTG controller has detected a connection -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USBD_DCD_INT_fops->DevConnected (pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.sessreqintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - -/** -* @brief DCD_OTG_ISR -* Indicates that the USB_OTG controller has detected an OTG event: -* used to detect the end of session i.e. disconnection -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_GOTGINT_TypeDef gotgint; - - gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT); - - if (gotgint.b.sesenddet) - { - USBD_DCD_INT_fops->DevDisconnected (pdev); - } - /* Clear OTG interrupt */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); - return 1; -} -#endif -/** -* @brief DCD_HandleResume_ISR -* Indicates that the USB_OTG controller has detected a resume or -* remote Wake-up sequence -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_DCTL_TypeDef devctl; - USB_OTG_PCGCCTL_TypeDef power; - - if(pdev->cfg.low_power) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - } - - /* Clear the Remote Wake-up Signaling */ - devctl.d32 = 0; - devctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0); - - /* Inform upper layer by the Resume Event */ - USBD_DCD_INT_fops->Resume (pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.wkupintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - -/** -* @brief USB_OTG_HandleUSBSuspend_ISR -* Indicates that SUSPEND state has been detected on the USB -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_PCGCCTL_TypeDef power; - USB_OTG_DSTS_TypeDef dsts; - __IO uint8_t prev_status = 0; - - prev_status = pdev->dev.device_status; - USBD_DCD_INT_fops->Suspend (pdev); - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.usbsuspend = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) && - (pdev->dev.connection_status == 1) && - (prev_status == USB_OTG_CONFIGURED)) - { - /* switch-off the clocks */ - power.d32 = 0; - power.b.stoppclk = 1; - USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); - - power.b.gatehclk = 1; - USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); - - /* Request to enter Sleep mode after exit from current ISR */ - SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk); - } - return 1; -} - -/** -* @brief DCD_HandleInEP_ISR -* Indicates that an IN EP has a pending Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DIEPINTn_TypeDef diepint; - - uint32_t ep_intr; - uint32_t epnum = 0; - uint32_t fifoemptymsk; - diepint.d32 = 0; - ep_intr = USB_OTG_ReadDevAllInEPItr(pdev); - - while ( ep_intr ) - { - if ((ep_intr & 0x1) == 0x01) /* In ITR */ - { - diepint.d32 = DCD_ReadDevInEP(pdev , epnum); /* Get In ITR status */ - if ( diepint.b.xfercompl ) - { - fifoemptymsk = 0x1 << epnum; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); - CLEAR_IN_EP_INTR(epnum, xfercompl); - /* TX COMPLETE */ - USBD_DCD_INT_fops->DataInStage(pdev , epnum); - - if (pdev->cfg.dma_enable == 1) - { - if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN)) - { - /* prepare to rx more setup packets */ - USB_OTG_EP0_OutStart(pdev); - } - } - } - if ( diepint.b.timeout ) - { - CLEAR_IN_EP_INTR(epnum, timeout); - } - if (diepint.b.intktxfemp) - { - CLEAR_IN_EP_INTR(epnum, intktxfemp); - } - if (diepint.b.inepnakeff) - { - CLEAR_IN_EP_INTR(epnum, inepnakeff); - } - if ( diepint.b.epdisabled ) - { - CLEAR_IN_EP_INTR(epnum, epdisabled); - } - if (diepint.b.emptyintr) - { - DCD_WriteEmptyTxFifo(pdev , epnum); - } - } - epnum++; - ep_intr >>= 1; - } - - return 1; -} - -/** -* @brief DCD_HandleOutEP_ISR -* Indicates that an OUT EP has a pending Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t ep_intr; - USB_OTG_DOEPINTn_TypeDef doepint; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - uint32_t epnum = 0; - - doepint.d32 = 0; - - /* Read in the device interrupt bits */ - ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev); - - while ( ep_intr ) - { - if (ep_intr&0x1) - { - - doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum); - - /* Transfer complete */ - if ( doepint.b.xfercompl ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(epnum, xfercompl); - if (pdev->cfg.dma_enable == 1) - { - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[epnum]->DOEPTSIZ)); - /*ToDo : handle more than one single MPS size packet */ - pdev->dev.out_ep[epnum].xfer_count = pdev->dev.out_ep[epnum].maxpacket - \ - deptsiz.b.xfersize; - } - /* Inform upper layer: data ready */ - /* RX COMPLETE */ - USBD_DCD_INT_fops->DataOutStage(pdev , epnum); - - if (pdev->cfg.dma_enable == 1) - { - if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT)) - { - /* prepare to rx more setup packets */ - USB_OTG_EP0_OutStart(pdev); - } - } - } - /* Endpoint disable */ - if ( doepint.b.epdisabled ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(epnum, epdisabled); - } - /* Setup Phase Done (control EPs) */ - if ( doepint.b.setup ) - { - - /* inform the upper layer that a setup packet is available */ - /* SETUP COMPLETE */ - USBD_DCD_INT_fops->SetupStage(pdev); - CLEAR_OUT_EP_INTR(epnum, setup); - } - } - epnum++; - ep_intr >>= 1; - } - return 1; -} - -/** -* @brief DCD_HandleSof_ISR -* Handles the SOF Interrupts -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef GINTSTS; - - - USBD_DCD_INT_fops->SOF(pdev); - - /* Clear interrupt */ - GINTSTS.d32 = 0; - GINTSTS.b.sofintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32); - - return 1; -} - -/** -* @brief DCD_HandleRxStatusQueueLevel_ISR -* Handles the Rx Status Queue Level Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef int_mask; - USB_OTG_DRXSTS_TypeDef status; - USB_OTG_EP *ep; - - /* Disable the Rx Status Queue Level interrupt */ - int_mask.d32 = 0; - int_mask.b.rxstsqlvl = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0); - - /* Get the Status from the top of the FIFO */ - status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP ); - - ep = &pdev->dev.out_ep[status.b.epnum]; - - switch (status.b.pktsts) - { - case STS_GOUT_NAK: - break; - case STS_DATA_UPDT: - if (status.b.bcnt) - { - USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt); - ep->xfer_buff += status.b.bcnt; - ep->xfer_count += status.b.bcnt; - } - break; - case STS_XFER_COMP: - break; - case STS_SETUP_COMP: - break; - case STS_SETUP_UPDT: - /* Copy the setup packet received in FIFO into the setup buffer in RAM */ - USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8); - ep->xfer_count += status.b.bcnt; - break; - default: - break; - } - - /* Enable the Rx Status Queue Level interrupt */ - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32); - - return 1; -} - -/** -* @brief DCD_WriteEmptyTxFifo -* check FIFO for the next packet to be loaded -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum) -{ - USB_OTG_DTXFSTSn_TypeDef txstatus; - USB_OTG_EP *ep; - uint32_t len = 0; - uint32_t len32b; - txstatus.d32 = 0; - uint32_t fifoemptymsk; - - ep = &pdev->dev.in_ep[epnum]; - - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - - len32b = (len + 3) / 4; - txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS); - - while (txstatus.b.txfspcavail > len32b && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) - { - /* Write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - len32b = (len + 3) / 4; - - USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len); - - ep->xfer_buff += len; - ep->xfer_count += len; - - txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS); - - /* Mask the TxFIFOEmpty interrupt */ - if (ep->xfer_len == ep->xfer_count) - { - fifoemptymsk = 0x1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, - fifoemptymsk, 0); - } - } - - return 1; -} - -/** -* @brief DCD_HandleUsbReset_ISR -* This interrupt occurs when a USB Reset is detected -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DAINT_TypeDef daintmsk; - USB_OTG_DOEPMSK_TypeDef doepmsk; - USB_OTG_DIEPMSK_TypeDef diepmsk; - USB_OTG_DCFG_TypeDef dcfg; - USB_OTG_DCTL_TypeDef dctl; - USB_OTG_GINTSTS_TypeDef gintsts; - uint32_t i; - - dctl.d32 = 0; - daintmsk.d32 = 0; - doepmsk.d32 = 0; - diepmsk.d32 = 0; - dcfg.d32 = 0; - gintsts.d32 = 0; - - /* Clear the Remote Wake-up Signaling */ - dctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); - - /* Flush the Tx FIFO */ - USB_OTG_FlushTxFifo(pdev , 0 ); - - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - - daintmsk.ep.in = 1; - daintmsk.ep.out = 1; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 ); - - doepmsk.b.setup = 1; - doepmsk.b.xfercompl = 1; - doepmsk.b.epdisabled = 1; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 ); -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 ); -#endif - diepmsk.b.xfercompl = 1; - diepmsk.b.timeout = 1; - diepmsk.b.epdisabled = 1; - - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 ); -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 ); -#endif - /* Reset Device Address */ - dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); - dcfg.b.devaddr = 0; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32); - - - /* setup EP0 to receive SETUP packets */ - USB_OTG_EP0_OutStart(pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.usbreset = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - /*Reset internal state machine */ - USBD_DCD_INT_fops->Reset(pdev); - return 1; -} - -/** -* @brief DCD_HandleEnumDone_ISR -* Read the device status register and set the device speed -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t hclk = 168000000; - - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_GUSBCFG_TypeDef gusbcfg; - RCC_ClocksTypeDef RCC_Clocks; - USB_OTG_EP0Activate(pdev); - - /* Get HCLK frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - hclk = RCC_Clocks.HCLK_Frequency; - - /* Clear default TRDT value and Set USB turn-around time based on device speed and PHY interface. */ - gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - gusbcfg.b.usbtrdtim = 0; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32); - - /* Full or High speed */ - if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH) - { - pdev->cfg.speed = USB_OTG_SPEED_HIGH; - pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ; - - /*USBTRD min For HS device*/ - gusbcfg.b.usbtrdtim = 9; - } - else - { - pdev->cfg.speed = USB_OTG_SPEED_FULL; - pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; - - /* The USBTRD is configured according to the tables below, depending on AHB frequency - used by application. In the low AHB frequency range it is used to stretch enough the USB response - time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access - latency to the Data FIFO */ - - if((hclk >= 15000000)&&(hclk < 16000000)) - { - /* hclk Clock Range between 15-16 MHz */ - gusbcfg.b.usbtrdtim = 0xE; - } - - else if((hclk >= 16000000)&&(hclk < 17100000)) - { - /* hclk Clock Range between 16-17.1 MHz */ - gusbcfg.b.usbtrdtim = 0xD; - } - - else if((hclk >= 17100000)&&(hclk < 18400000)) - { - /* hclk Clock Range between 17-18.4 MHz */ - gusbcfg.b.usbtrdtim = 0xC; - } - - else if((hclk >= 18400000)&&(hclk < 20000000)) - { - /* hclk Clock Range between 18.4-20 MHz */ - gusbcfg.b.usbtrdtim = 0xB; - } - - else if((hclk >= 20000000)&&(hclk < 21800000)) - { - /* hclk Clock Range between 20-21.8 MHz */ - gusbcfg.b.usbtrdtim = 0xA; - } - - else if((hclk >= 21800000)&&(hclk < 24000000)) - { - /* hclk Clock Range between 21.8-24 MHz */ - gusbcfg.b.usbtrdtim = 0x9; - } - - else if((hclk >= 24000000)&&(hclk < 26600000)) - { - /* hclk Clock Range between 24-26.6 MHz */ - gusbcfg.b.usbtrdtim = 0x8; - } - - else if((hclk >= 26600000)&&(hclk < 30000000)) - { - /* hclk Clock Range between 26.6-30 MHz */ - gusbcfg.b.usbtrdtim = 0x7; - } - - else if((hclk >= 30000000)&&(hclk < 34300000)) - { - /* hclk Clock Range between 30-34.3 MHz */ - gusbcfg.b.usbtrdtim= 0x6; - } - - else /* if(hclk >= 34300000) */ - { - /* hclk Clock Range between 34.3-168 MHz */ - gusbcfg.b.usbtrdtim = 0x5; - } - } - - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.enumdone = 1; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, gintsts.d32 ); - return 1; -} - - -/** -* @brief DCD_IsoINIncomplete_ISR -* handle the ISO IN incomplete interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0; - - USBD_DCD_INT_fops->IsoINIncomplete (pdev); - - /* Clear interrupt */ - gintsts.b.incomplisoin = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} - -/** -* @brief DCD_IsoOUTIncomplete_ISR -* handle the ISO OUT incomplete interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0; - - USBD_DCD_INT_fops->IsoOUTIncomplete (pdev); - - /* Clear interrupt */ - gintsts.b.incomplisoout = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} -/** -* @brief DCD_ReadDevInEP -* Reads ep flags -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - uint32_t v, msk, emp; - msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPMSK); - emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); - msk |= ((emp >> epnum) & 0x1) << 7; - v = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT) & msk; - return v; -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usb_dcd_int.c + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief Peripheral Device interrupt subroutines + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_dcd_int.h" +#include "board.h" // modified by OpenTX +#include "debug.h" // modified by OpenTX + +/** @addtogroup USB_OTG_DRIVER +* @{ +*/ + +/** @defgroup USB_DCD_INT +* @brief This file contains the interrupt subroutines for the Device mode. +* @{ +*/ + + +/** @defgroup USB_DCD_INT_Private_Defines +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_INT_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + + +/** @defgroup USB_DCD_INT_Private_Macros +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_INT_Private_Variables +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_INT_Private_FunctionPrototypes +* @{ +*/ +/* static functions */ +static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum); + +/* Interrupt Handlers */ +static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev); + +static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum); + +static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev); + +static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); +#ifdef VBUS_SENSING_ENABLED +static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev); +#endif + +/** +* @} +*/ + + +/** @defgroup USB_DCD_INT_Private_Functions +* @{ +*/ + + +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED +/** +* @brief USBD_OTG_EP1OUT_ISR_Handler +* handles all USB Interrupts +* @param pdev: device instance +* @retval status +*/ +uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) +{ + + USB_OTG_DOEPINTn_TypeDef doepint; + USB_OTG_DEPXFRSIZ_TypeDef deptsiz; + + doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT); + doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK); + + /* Transfer complete */ + if ( doepint.b.xfercompl ) + { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(1, xfercompl); + if (pdev->cfg.dma_enable == 1) + { + deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ)); + pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].xfer_len- \ + deptsiz.b.xfersize; + } + /* Inform upper layer: data ready */ + /* RX COMPLETE */ + USBD_DCD_INT_fops->DataOutStage(pdev , 1); + + } + + /* Endpoint disable */ + if ( doepint.b.epdisabled ) + { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(1, epdisabled); + } + + return 1; +} + +/** +* @brief USBD_OTG_EP1IN_ISR_Handler +* handles all USB Interrupts +* @param pdev: device instance +* @retval status +*/ +uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) +{ + + USB_OTG_DIEPINTn_TypeDef diepint; + uint32_t fifoemptymsk, msk, emp; + + msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK); + emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); + msk |= ((emp >> 1 ) & 0x1) << 7; + diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk; + + if ( diepint.b.xfercompl ) + { + fifoemptymsk = 0x1 << 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); + CLEAR_IN_EP_INTR(1, xfercompl); + /* TX COMPLETE */ + USBD_DCD_INT_fops->DataInStage(pdev , 1); + } + if ( diepint.b.epdisabled ) + { + CLEAR_IN_EP_INTR(1, epdisabled); + } + if ( diepint.b.timeout ) + { + CLEAR_IN_EP_INTR(1, timeout); + } + if (diepint.b.intktxfemp) + { + CLEAR_IN_EP_INTR(1, intktxfemp); + } + if (diepint.b.inepnakeff) + { + CLEAR_IN_EP_INTR(1, inepnakeff); + } + if (diepint.b.emptyintr) + { + DCD_WriteEmptyTxFifo(pdev , 1); + } + return 1; +} +#endif + +/** +* @brief STM32_USBF_OTG_ISR_Handler +* handles all USB Interrupts +* @param pdev: device instance +* @retval status +*/ +uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintr_status; + uint32_t retval = 0; + + if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */ + { + gintr_status.d32 = USB_OTG_ReadCoreItr(pdev); + if (!gintr_status.d32) /* avoid spurious interrupt */ + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_SPURIOUS); // modified by OpenTX + return 0; + } + + if (gintr_status.b.outepintr) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_OUT_EP); // modified by OpenTX + retval |= DCD_HandleOutEP_ISR(pdev); + } + + if (gintr_status.b.inepint) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_IN_EP); // modified by OpenTX + retval |= DCD_HandleInEP_ISR(pdev); + } + + if (gintr_status.b.modemismatch) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_MODEMISMATCH); // modified by OpenTX + USB_OTG_GINTSTS_TypeDef gintsts; + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.modemismatch = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); + } + + if (gintr_status.b.wkupintr) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_WAKEUP); // modified by OpenTX + retval |= DCD_HandleResume_ISR(pdev); + } + + if (gintr_status.b.usbsuspend) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_SUSPEND); // modified by OpenTX + retval |= DCD_HandleUSBSuspend_ISR(pdev); + } + if (gintr_status.b.sofintr) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_SOF); // modified by OpenTX + retval |= DCD_HandleSof_ISR(pdev); + + } + + if (gintr_status.b.rxstsqlvl) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_RX_STAT); // modified by OpenTX + retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev); + + } + + if (gintr_status.b.usbreset) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_RESET); // modified by OpenTX + retval |= DCD_HandleUsbReset_ISR(pdev); + + } + if (gintr_status.b.enumdone) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_ENUM); // modified by OpenTX + retval |= DCD_HandleEnumDone_ISR(pdev); + } + + if (gintr_status.b.incomplisoin) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_INCOMPLETE_IN); // modified by OpenTX + retval |= DCD_IsoINIncomplete_ISR(pdev); + } + + if (gintr_status.b.incomplisoout) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_INCOMPLETE_OUT); // modified by OpenTX + retval |= DCD_IsoOUTIncomplete_ISR(pdev); + } +#ifdef VBUS_SENSING_ENABLED + if (gintr_status.b.sessreqintr) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_SESSION); // modified by OpenTX + retval |= DCD_SessionRequest_ISR(pdev); + } + + if (gintr_status.b.otgintr) + { + DEBUG_USB_INTERRUPT(INT_OTG_FS_OTG); // modified by OpenTX + retval |= DCD_OTG_ISR(pdev); + } +#endif + } + else { + DEBUG_USB_INTERRUPT(INT_OTG_FS_RX_NOT_DEVICE); // modified by OpenTX + } + return retval; +} + +#ifdef VBUS_SENSING_ENABLED +/** +* @brief DCD_SessionRequest_ISR +* Indicates that the USB_OTG controller has detected a connection +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + USBD_DCD_INT_fops->DevConnected (pdev); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.sessreqintr = 1; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); + return 1; +} + +/** +* @brief DCD_OTG_ISR +* Indicates that the USB_OTG controller has detected an OTG event: +* used to detect the end of session i.e. disconnection +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + + USB_OTG_GOTGINT_TypeDef gotgint; + + gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT); + + if (gotgint.b.sesenddet) + { + USBD_DCD_INT_fops->DevDisconnected (pdev); + } + /* Clear OTG interrupt */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); + return 1; +} +#endif +/** +* @brief DCD_HandleResume_ISR +* Indicates that the USB_OTG controller has detected a resume or +* remote Wake-up sequence +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + USB_OTG_DCTL_TypeDef devctl; + USB_OTG_PCGCCTL_TypeDef power; + + if(pdev->cfg.low_power) + { + /* un-gate USB Core clock */ + power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL); + power.b.gatehclk = 0; + power.b.stoppclk = 0; + USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); + } + + /* Clear the Remote Wake-up Signaling */ + devctl.d32 = 0; + devctl.b.rmtwkupsig = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0); + + /* Inform upper layer by the Resume Event */ + USBD_DCD_INT_fops->Resume (pdev); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.wkupintr = 1; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); + return 1; +} + +/** +* @brief USB_OTG_HandleUSBSuspend_ISR +* Indicates that SUSPEND state has been detected on the USB +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + USB_OTG_PCGCCTL_TypeDef power; + USB_OTG_DSTS_TypeDef dsts; + __IO uint8_t prev_status = 0; + + prev_status = pdev->dev.device_status; + USBD_DCD_INT_fops->Suspend (pdev); + + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.usbsuspend = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); + + if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) && + (pdev->dev.connection_status == 1) && + (prev_status == USB_OTG_CONFIGURED)) + { + /* switch-off the clocks */ + power.d32 = 0; + power.b.stoppclk = 1; + USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); + + power.b.gatehclk = 1; + USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); + + /* Request to enter Sleep mode after exit from current ISR */ + SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk); + } + return 1; +} + +/** +* @brief DCD_HandleInEP_ISR +* Indicates that an IN EP has a pending Interrupt +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_DIEPINTn_TypeDef diepint; + + uint32_t ep_intr; + uint32_t epnum = 0; + uint32_t fifoemptymsk; + diepint.d32 = 0; + ep_intr = USB_OTG_ReadDevAllInEPItr(pdev); + + while ( ep_intr ) + { + if ((ep_intr & 0x1) == 0x01) /* In ITR */ + { + diepint.d32 = DCD_ReadDevInEP(pdev , epnum); /* Get In ITR status */ + if ( diepint.b.xfercompl ) + { + fifoemptymsk = 0x1 << epnum; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); + CLEAR_IN_EP_INTR(epnum, xfercompl); + /* TX COMPLETE */ + USBD_DCD_INT_fops->DataInStage(pdev , epnum); + + if (pdev->cfg.dma_enable == 1) + { + if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN)) + { + /* prepare to rx more setup packets */ + USB_OTG_EP0_OutStart(pdev); + } + } + } + if ( diepint.b.timeout ) + { + CLEAR_IN_EP_INTR(epnum, timeout); + } + if (diepint.b.intktxfemp) + { + CLEAR_IN_EP_INTR(epnum, intktxfemp); + } + if (diepint.b.inepnakeff) + { + CLEAR_IN_EP_INTR(epnum, inepnakeff); + } + if ( diepint.b.epdisabled ) + { + CLEAR_IN_EP_INTR(epnum, epdisabled); + } + if (diepint.b.emptyintr) + { + DCD_WriteEmptyTxFifo(pdev , epnum); + } + } + epnum++; + ep_intr >>= 1; + } + + return 1; +} + +/** +* @brief DCD_HandleOutEP_ISR +* Indicates that an OUT EP has a pending Interrupt +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t ep_intr; + USB_OTG_DOEPINTn_TypeDef doepint; + USB_OTG_DEPXFRSIZ_TypeDef deptsiz; + uint32_t epnum = 0; + + doepint.d32 = 0; + + /* Read in the device interrupt bits */ + ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev); + + while ( ep_intr ) + { + if (ep_intr&0x1) + { + + doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum); + + /* Transfer complete */ + if ( doepint.b.xfercompl ) + { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(epnum, xfercompl); + if (pdev->cfg.dma_enable == 1) + { + deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[epnum]->DOEPTSIZ)); + /*ToDo : handle more than one single MPS size packet */ + pdev->dev.out_ep[epnum].xfer_count = pdev->dev.out_ep[epnum].maxpacket - \ + deptsiz.b.xfersize; + } + /* Inform upper layer: data ready */ + /* RX COMPLETE */ + USBD_DCD_INT_fops->DataOutStage(pdev , epnum); + + if (pdev->cfg.dma_enable == 1) + { + if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT)) + { + /* prepare to rx more setup packets */ + USB_OTG_EP0_OutStart(pdev); + } + } + } + /* Endpoint disable */ + if ( doepint.b.epdisabled ) + { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(epnum, epdisabled); + } + /* Setup Phase Done (control EPs) */ + if ( doepint.b.setup ) + { + + /* inform the upper layer that a setup packet is available */ + /* SETUP COMPLETE */ + USBD_DCD_INT_fops->SetupStage(pdev); + CLEAR_OUT_EP_INTR(epnum, setup); + } + } + epnum++; + ep_intr >>= 1; + } + return 1; +} + +/** +* @brief DCD_HandleSof_ISR +* Handles the SOF Interrupts +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef GINTSTS; + + + USBD_DCD_INT_fops->SOF(pdev); + + /* Clear interrupt */ + GINTSTS.d32 = 0; + GINTSTS.b.sofintr = 1; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32); + + return 1; +} + +/** +* @brief DCD_HandleRxStatusQueueLevel_ISR +* Handles the Rx Status Queue Level Interrupt +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTMSK_TypeDef int_mask; + USB_OTG_DRXSTS_TypeDef status; + USB_OTG_EP *ep; + + /* Disable the Rx Status Queue Level interrupt */ + int_mask.d32 = 0; + int_mask.b.rxstsqlvl = 1; + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0); + + /* Get the Status from the top of the FIFO */ + status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP ); + + ep = &pdev->dev.out_ep[status.b.epnum]; + + switch (status.b.pktsts) + { + case STS_GOUT_NAK: + break; + case STS_DATA_UPDT: + if (status.b.bcnt) + { + USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt); + ep->xfer_buff += status.b.bcnt; + ep->xfer_count += status.b.bcnt; + } + break; + case STS_XFER_COMP: + break; + case STS_SETUP_COMP: + break; + case STS_SETUP_UPDT: + /* Copy the setup packet received in FIFO into the setup buffer in RAM */ + USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8); + ep->xfer_count += status.b.bcnt; + break; + default: + break; + } + + /* Enable the Rx Status Queue Level interrupt */ + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32); + + return 1; +} + +/** +* @brief DCD_WriteEmptyTxFifo +* check FIFO for the next packet to be loaded +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum) +{ + USB_OTG_DTXFSTSn_TypeDef txstatus; + USB_OTG_EP *ep; + uint32_t len = 0; + uint32_t len32b; + txstatus.d32 = 0; + uint32_t fifoemptymsk; + + ep = &pdev->dev.in_ep[epnum]; + + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32b = (len + 3) / 4; + txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS); + + while (txstatus.b.txfspcavail > len32b && + ep->xfer_count < ep->xfer_len && + ep->xfer_len != 0) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32b = (len + 3) / 4; + + USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len); + + ep->xfer_buff += len; + ep->xfer_count += len; + + txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS); + + /* Mask the TxFIFOEmpty interrupt */ + if (ep->xfer_len == ep->xfer_count) + { + fifoemptymsk = 0x1 << ep->num; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, + fifoemptymsk, 0); + } + } + + return 1; +} + +/** +* @brief DCD_HandleUsbReset_ISR +* This interrupt occurs when a USB Reset is detected +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_DAINT_TypeDef daintmsk; + USB_OTG_DOEPMSK_TypeDef doepmsk; + USB_OTG_DIEPMSK_TypeDef diepmsk; + USB_OTG_DCFG_TypeDef dcfg; + USB_OTG_DCTL_TypeDef dctl; + USB_OTG_GINTSTS_TypeDef gintsts; + uint32_t i; + + dctl.d32 = 0; + daintmsk.d32 = 0; + doepmsk.d32 = 0; + diepmsk.d32 = 0; + dcfg.d32 = 0; + gintsts.d32 = 0; + + /* Clear the Remote Wake-up Signaling */ + dctl.b.rmtwkupsig = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); + + /* Flush the Tx FIFO */ + USB_OTG_FlushTxFifo(pdev , 0 ); + + for (i = 0; i < pdev->cfg.dev_endpoints ; i++) + { + USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); + } + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); + + daintmsk.ep.in = 1; + daintmsk.ep.out = 1; + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 ); + + doepmsk.b.setup = 1; + doepmsk.b.xfercompl = 1; + doepmsk.b.epdisabled = 1; + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 ); +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 ); +#endif + diepmsk.b.xfercompl = 1; + diepmsk.b.timeout = 1; + diepmsk.b.epdisabled = 1; + + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 ); +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 ); +#endif + /* Reset Device Address */ + dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); + dcfg.b.devaddr = 0; + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32); + + + /* setup EP0 to receive SETUP packets */ + USB_OTG_EP0_OutStart(pdev); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.usbreset = 1; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); + + /*Reset internal state machine */ + USBD_DCD_INT_fops->Reset(pdev); + return 1; +} + +/** +* @brief DCD_HandleEnumDone_ISR +* Read the device status register and set the device speed +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t hclk = 168000000; + + USB_OTG_GINTSTS_TypeDef gintsts; + USB_OTG_GUSBCFG_TypeDef gusbcfg; + RCC_ClocksTypeDef RCC_Clocks; + USB_OTG_EP0Activate(pdev); + + /* Get HCLK frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + hclk = RCC_Clocks.HCLK_Frequency; + + /* Clear default TRDT value and Set USB turn-around time based on device speed and PHY interface. */ + gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); + gusbcfg.b.usbtrdtim = 0; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32); + + /* Full or High speed */ + if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH) + { + pdev->cfg.speed = USB_OTG_SPEED_HIGH; + pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ; + + /*USBTRD min For HS device*/ + gusbcfg.b.usbtrdtim = 9; + } + else + { + pdev->cfg.speed = USB_OTG_SPEED_FULL; + pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + + if((hclk >= 15000000)&&(hclk < 16000000)) + { + /* hclk Clock Range between 15-16 MHz */ + gusbcfg.b.usbtrdtim = 0xE; + } + + else if((hclk >= 16000000)&&(hclk < 17100000)) + { + /* hclk Clock Range between 16-17.1 MHz */ + gusbcfg.b.usbtrdtim = 0xD; + } + + else if((hclk >= 17100000)&&(hclk < 18400000)) + { + /* hclk Clock Range between 17-18.4 MHz */ + gusbcfg.b.usbtrdtim = 0xC; + } + + else if((hclk >= 18400000)&&(hclk < 20000000)) + { + /* hclk Clock Range between 18.4-20 MHz */ + gusbcfg.b.usbtrdtim = 0xB; + } + + else if((hclk >= 20000000)&&(hclk < 21800000)) + { + /* hclk Clock Range between 20-21.8 MHz */ + gusbcfg.b.usbtrdtim = 0xA; + } + + else if((hclk >= 21800000)&&(hclk < 24000000)) + { + /* hclk Clock Range between 21.8-24 MHz */ + gusbcfg.b.usbtrdtim = 0x9; + } + + else if((hclk >= 24000000)&&(hclk < 26600000)) + { + /* hclk Clock Range between 24-26.6 MHz */ + gusbcfg.b.usbtrdtim = 0x8; + } + + else if((hclk >= 26600000)&&(hclk < 30000000)) + { + /* hclk Clock Range between 26.6-30 MHz */ + gusbcfg.b.usbtrdtim = 0x7; + } + + else if((hclk >= 30000000)&&(hclk < 34300000)) + { + /* hclk Clock Range between 30-34.3 MHz */ + gusbcfg.b.usbtrdtim= 0x6; + } + + else /* if(hclk >= 34300000) */ + { + /* hclk Clock Range between 34.3-168 MHz */ + gusbcfg.b.usbtrdtim = 0x5; + } + } + + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.enumdone = 1; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, gintsts.d32 ); + return 1; +} + + +/** +* @brief DCD_IsoINIncomplete_ISR +* handle the ISO IN incomplete interrupt +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + + gintsts.d32 = 0; + + USBD_DCD_INT_fops->IsoINIncomplete (pdev); + + /* Clear interrupt */ + gintsts.b.incomplisoin = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); + + return 1; +} + +/** +* @brief DCD_IsoOUTIncomplete_ISR +* handle the ISO OUT incomplete interrupt +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + + gintsts.d32 = 0; + + USBD_DCD_INT_fops->IsoOUTIncomplete (pdev); + + /* Clear interrupt */ + gintsts.b.incomplisoout = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); + return 1; +} +/** +* @brief DCD_ReadDevInEP +* Reads ep flags +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) +{ + uint32_t v, msk, emp; + msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPMSK); + emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); + msk |= ((emp >> epnum) & 0x1) << 7; + v = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT) & msk; + return v; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_hcd.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_hcd.c index 7308a4bf7..95f5c5ea0 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_hcd.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_hcd.c @@ -1,275 +1,275 @@ -/** - ****************************************************************************** - * @file usb_hcd.c - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief Host Interface Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_hcd.h" -#include "usb_conf.h" -#include "usb_bsp.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_HCD - * @brief This file is the interface between EFSL ans Host mass-storage class - * @{ - */ - - -/** @defgroup USB_HCD_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USB_HCD_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_Functions - * @{ - */ - -/** - * @brief HCD_Init - * Initialize the HOST portion of the driver. - * @param pdev: Selected device - * @param base_address: OTG base address - * @retval Status - */ -uint32_t HCD_Init(USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint8_t i = 0; - pdev->host.ConnSts = 0; - - for (i= 0; i< USB_OTG_MAX_TX_FIFOS; i++) - { - pdev->host.ErrCnt[i] = 0; - pdev->host.XferCnt[i] = 0; - pdev->host.HC_Status[i] = HC_IDLE; - } - pdev->host.hc[0].max_packet = 8; - - USB_OTG_SelectCore(pdev, coreID); -#ifndef DUAL_ROLE_MODE_ENABLED - USB_OTG_DisableGlobalInt(pdev); - USB_OTG_CoreInit(pdev); - - /* Force Host Mode*/ - USB_OTG_SetCurrentMode(pdev , HOST_MODE); - USB_OTG_CoreInitHost(pdev); - USB_OTG_EnableGlobalInt(pdev); -#endif - - return 0; -} - - -/** - * @brief HCD_GetCurrentSpeed - * Get Current device Speed. - * @param pdev : Selected device - * @retval Status - */ - -uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef HPRT0; - HPRT0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - - return HPRT0.b.prtspd; -} - -/** - * @brief HCD_ResetPort - * Issues the reset command to device - * @param pdev : Selected device - * @retval Status - */ -uint32_t HCD_ResetPort(USB_OTG_CORE_HANDLE *pdev) -{ - /* - Before starting to drive a USB reset, the application waits for the OTG - interrupt triggered by the debounce done bit (DBCDNE bit in OTG_FS_GOTGINT), - which indicates that the bus is stable again after the electrical debounce - caused by the attachment of a pull-up resistor on DP (FS) or DM (LS). - */ - - USB_OTG_ResetPort(pdev); - return 0; -} - -/** - * @brief HCD_IsDeviceConnected - * Check if the device is connected. - * @param pdev : Selected device - * @retval Device connection status. 1 -> connected and 0 -> disconnected - * - */ -uint32_t HCD_IsDeviceConnected(USB_OTG_CORE_HANDLE *pdev) -{ - return (pdev->host.ConnSts); -} - - -/** - * @brief HCD_IsPortEnabled - * This function checks if port is enabled - * @param pdev : Selected device - * @retval Frame number - * - */ -uint32_t HCD_IsPortEnabled(USB_OTG_CORE_HANDLE *pdev) -{ - return (pdev->host.PortEnabled); -} - -/** - * @brief HCD_GetCurrentFrame - * This function returns the frame number for sof packet - * @param pdev : Selected device - * @retval Frame number - * - */ -uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0xFFFF) ; -} - -/** - * @brief HCD_GetURB_State - * This function returns the last URBstate - * @param pdev: Selected device - * @retval URB_STATE - * - */ -URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num) -{ - return pdev->host.URB_State[ch_num] ; -} - -/** - * @brief HCD_GetXferCnt - * This function returns the last URBstate - * @param pdev: Selected device - * @retval No. of data bytes transferred - * - */ -uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) -{ - return pdev->host.XferCnt[ch_num] ; -} - - - -/** - * @brief HCD_GetHCState - * This function returns the HC Status - * @param pdev: Selected device - * @retval HC_STATUS - * - */ -HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num) -{ - return pdev->host.HC_Status[ch_num] ; -} - -/** - * @brief HCD_HC_Init - * This function prepare a HC and start a transfer - * @param pdev: Selected device - * @param hc_num: Channel number - * @retval status - */ -uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - return USB_OTG_HC_Init(pdev, hc_num); -} - -/** - * @brief HCD_SubmitRequest - * This function prepare a HC and start a transfer - * @param pdev: Selected device - * @param hc_num: Channel number - * @retval status - */ -uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - - pdev->host.URB_State[hc_num] = URB_IDLE; - pdev->host.hc[hc_num].xfer_count = 0 ; - return USB_OTG_HC_StartXfer(pdev, hc_num); -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usb_hcd.c + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief Host Interface Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_core.h" +#include "usb_hcd.h" +#include "usb_conf.h" +#include "usb_bsp.h" + + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_HCD + * @brief This file is the interface between EFSL ans Host mass-storage class + * @{ + */ + + +/** @defgroup USB_HCD_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_HCD_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USB_HCD_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_HCD_Private_Variables + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_HCD_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_HCD_Private_Functions + * @{ + */ + +/** + * @brief HCD_Init + * Initialize the HOST portion of the driver. + * @param pdev: Selected device + * @param base_address: OTG base address + * @retval Status + */ +uint32_t HCD_Init(USB_OTG_CORE_HANDLE *pdev , + USB_OTG_CORE_ID_TypeDef coreID) +{ + uint8_t i = 0; + pdev->host.ConnSts = 0; + + for (i= 0; i< USB_OTG_MAX_TX_FIFOS; i++) + { + pdev->host.ErrCnt[i] = 0; + pdev->host.XferCnt[i] = 0; + pdev->host.HC_Status[i] = HC_IDLE; + } + pdev->host.hc[0].max_packet = 8; + + USB_OTG_SelectCore(pdev, coreID); +#ifndef DUAL_ROLE_MODE_ENABLED + USB_OTG_DisableGlobalInt(pdev); + USB_OTG_CoreInit(pdev); + + /* Force Host Mode*/ + USB_OTG_SetCurrentMode(pdev , HOST_MODE); + USB_OTG_CoreInitHost(pdev); + USB_OTG_EnableGlobalInt(pdev); +#endif + + return 0; +} + + +/** + * @brief HCD_GetCurrentSpeed + * Get Current device Speed. + * @param pdev : Selected device + * @retval Status + */ + +uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_HPRT0_TypeDef HPRT0; + HPRT0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); + + return HPRT0.b.prtspd; +} + +/** + * @brief HCD_ResetPort + * Issues the reset command to device + * @param pdev : Selected device + * @retval Status + */ +uint32_t HCD_ResetPort(USB_OTG_CORE_HANDLE *pdev) +{ + /* + Before starting to drive a USB reset, the application waits for the OTG + interrupt triggered by the debounce done bit (DBCDNE bit in OTG_FS_GOTGINT), + which indicates that the bus is stable again after the electrical debounce + caused by the attachment of a pull-up resistor on DP (FS) or DM (LS). + */ + + USB_OTG_ResetPort(pdev); + return 0; +} + +/** + * @brief HCD_IsDeviceConnected + * Check if the device is connected. + * @param pdev : Selected device + * @retval Device connection status. 1 -> connected and 0 -> disconnected + * + */ +uint32_t HCD_IsDeviceConnected(USB_OTG_CORE_HANDLE *pdev) +{ + return (pdev->host.ConnSts); +} + + +/** + * @brief HCD_IsPortEnabled + * This function checks if port is enabled + * @param pdev : Selected device + * @retval Frame number + * + */ +uint32_t HCD_IsPortEnabled(USB_OTG_CORE_HANDLE *pdev) +{ + return (pdev->host.PortEnabled); +} + +/** + * @brief HCD_GetCurrentFrame + * This function returns the frame number for sof packet + * @param pdev : Selected device + * @retval Frame number + * + */ +uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) +{ + return (USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0xFFFF) ; +} + +/** + * @brief HCD_GetURB_State + * This function returns the last URBstate + * @param pdev: Selected device + * @retval URB_STATE + * + */ +URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num) +{ + return pdev->host.URB_State[ch_num] ; +} + +/** + * @brief HCD_GetXferCnt + * This function returns the last URBstate + * @param pdev: Selected device + * @retval No. of data bytes transferred + * + */ +uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) +{ + return pdev->host.XferCnt[ch_num] ; +} + + + +/** + * @brief HCD_GetHCState + * This function returns the HC Status + * @param pdev: Selected device + * @retval HC_STATUS + * + */ +HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num) +{ + return pdev->host.HC_Status[ch_num] ; +} + +/** + * @brief HCD_HC_Init + * This function prepare a HC and start a transfer + * @param pdev: Selected device + * @param hc_num: Channel number + * @retval status + */ +uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) +{ + return USB_OTG_HC_Init(pdev, hc_num); +} + +/** + * @brief HCD_SubmitRequest + * This function prepare a HC and start a transfer + * @param pdev: Selected device + * @param hc_num: Channel number + * @retval status + */ +uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) +{ + + pdev->host.URB_State[hc_num] = URB_IDLE; + pdev->host.hc[hc_num].xfer_count = 0 ; + return USB_OTG_HC_StartXfer(pdev, hc_num); +} + + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_hcd_int.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_hcd_int.c index 3c12161f1..7366d155f 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_hcd_int.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_hcd_int.c @@ -1,858 +1,858 @@ -/** - ****************************************************************************** - * @file usb_hcd_int.c - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief Host driver interrupt subroutines - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_defines.h" -#include "usb_hcd_int.h" - -#if defined (__CC_ARM) /*!< ARM Compiler */ -#pragma O0 -#elif defined (__GNUC__) /*!< GNU Compiler */ -#pragma GCC optimize ("O0") -#elif defined (__TASKING__) /*!< TASKING Compiler */ -#pragma optimize=0 - -#endif /* __CC_ARM */ - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_HCD_INT -* @brief This file contains the interrupt subroutines for the Host mode. -* @{ -*/ - - -/** @defgroup USB_HCD_INT_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_HCD_INT_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_HCD_INT_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_HCD_INT_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_HCD_INT_Private_FunctionPrototypes -* @{ -*/ - -static uint32_t USB_OTG_USBH_handle_sof_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_port_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , - uint32_t num); -static uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , - uint32_t num); -static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev); - -/** -* @} -*/ - - -/** @defgroup USB_HCD_INT_Private_Functions -* @{ -*/ - -/** -* @brief HOST_Handle_ISR -* This function handles all USB Host Interrupts -* @param pdev: Selected device -* @retval status -*/ - -uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - uint32_t retval = 0; - - gintsts.d32 = 0; - - /* Check if HOST Mode */ - if (USB_OTG_IsHostMode(pdev)) - { - gintsts.d32 = USB_OTG_ReadCoreItr(pdev); - if (!gintsts.d32) - { - return 0; - } - - if (gintsts.b.sofintr) - { - retval |= USB_OTG_USBH_handle_sof_ISR (pdev); - } - - if (gintsts.b.rxstsqlvl) - { - retval |= USB_OTG_USBH_handle_rx_qlvl_ISR (pdev); - } - - if (gintsts.b.nptxfempty) - { - retval |= USB_OTG_USBH_handle_nptxfempty_ISR (pdev); - } - - if (gintsts.b.ptxfempty) - { - retval |= USB_OTG_USBH_handle_ptxfempty_ISR (pdev); - } - - if (gintsts.b.hcintr) - { - retval |= USB_OTG_USBH_handle_hc_ISR (pdev); - } - - if (gintsts.b.portintr) - { - retval |= USB_OTG_USBH_handle_port_ISR (pdev); - } - - if (gintsts.b.disconnect) - { - retval |= USB_OTG_USBH_handle_Disconnect_ISR (pdev); - - } - - if (gintsts.b.incomplisoout) - { - retval |= USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (pdev); - } - - - } - return retval; -} - -/** -* @brief USB_OTG_USBH_handle_hc_ISR -* This function indicates that one or more host channels has a pending -* @param pdev: Selected device -* @retval status -*/ -static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HAINT_TypeDef haint; - USB_OTG_HCCHAR_TypeDef hcchar; - uint32_t i = 0; - uint32_t retval = 0; - - /* Clear appropriate bits in HCINTn to clear the interrupt bit in - * GINTSTS */ - - haint.d32 = USB_OTG_ReadHostAllChannels_intr(pdev); - - for (i = 0; i < pdev->cfg.host_channels ; i++) - { - if (haint.b.chint & (1 << i)) - { - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); - - if (hcchar.b.epdir) - { - retval |= USB_OTG_USBH_handle_hc_n_In_ISR (pdev, i); - } - else - { - retval |= USB_OTG_USBH_handle_hc_n_Out_ISR (pdev, i); - } - } - } - - return retval; -} - -/** -* @brief USB_OTG_otg_hcd_handle_sof_intr -* Handles the start-of-frame interrupt in host mode. -* @param pdev: Selected device -* @retval status -*/ -static uint32_t USB_OTG_USBH_handle_sof_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - gintsts.d32 = 0; - - USBH_HCD_INT_fops->SOF(pdev); - - /* Clear interrupt */ - gintsts.b.sofintr = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} - -/** -* @brief USB_OTG_USBH_handle_Disconnect_ISR -* Handles disconnect event. -* @param pdev: Selected device -* @retval status -*/ -static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0; - - USBH_HCD_INT_fops->DevDisconnected(pdev); - - /* Clear interrupt */ - gintsts.b.disconnect = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -/** -* @brief USB_OTG_USBH_handle_nptxfempty_ISR -* Handles non periodic tx fifo empty. -* @param pdev: Selected device -* @retval status -*/ -static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef intmsk; - USB_OTG_HNPTXSTS_TypeDef hnptxsts; - uint16_t len_words , len; - - hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - - len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4; - - while ((hnptxsts.b.nptxfspcavail > len_words)&& - (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len != 0)) - { - - len = hnptxsts.b.nptxfspcavail * 4; - - if (len > pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len) - { - /* Last packet */ - len = pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len; - - intmsk.d32 = 0; - intmsk.b.nptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); - } - - len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4; - - USB_OTG_WritePacket (pdev , pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff, hnptxsts.b.nptxqtop.chnum, len); - - pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff += len; - pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len -= len; - pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_count += len; - - hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - } - - return 1; -} -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -/** -* @brief USB_OTG_USBH_handle_ptxfempty_ISR -* Handles periodic tx fifo empty -* @param pdev: Selected device -* @retval status -*/ -static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef intmsk; - USB_OTG_HPTXSTS_TypeDef hptxsts; - uint16_t len_words , len; - - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - - len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4; - - while ((hptxsts.b.ptxfspcavail > len_words)&& - (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len != 0)) - { - - len = hptxsts.b.ptxfspcavail * 4; - - if (len > pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len) - { - len = pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len; - /* Last packet */ - intmsk.d32 = 0; - intmsk.b.ptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); - } - - len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4; - - USB_OTG_WritePacket (pdev , pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff, hptxsts.b.ptxqtop.chnum, len); - - pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff += len; - pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len -= len; - pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_count += len; - - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - } - - return 1; -} - -/** -* @brief USB_OTG_USBH_handle_port_ISR -* This function determines which interrupt conditions have occurred -* @param pdev: Selected device -* @retval status -*/ -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - USB_OTG_HPRT0_TypeDef hprt0_dup; - USB_OTG_HCFG_TypeDef hcfg; - uint32_t retval = 0; - USB_OTG_GINTMSK_TypeDef intmsk; - - intmsk.d32 = 0; - hcfg.d32 = 0; - hprt0.d32 = 0; - hprt0_dup.d32 = 0; - - hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - hprt0_dup.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - - /* Clear the interrupt bits in GINTSTS */ - - hprt0_dup.b.prtena = 0; - hprt0_dup.b.prtconndet = 0; - hprt0_dup.b.prtenchng = 0; - hprt0_dup.b.prtovrcurrchng = 0; - - /* Port Connect Detected */ - if (hprt0.b.prtconndet) - { - hprt0_dup.b.prtconndet = 1; - USBH_HCD_INT_fops->DevConnected(pdev); - retval |= 1; - } - - /* Port Enable Changed */ - if (hprt0.b.prtenchng) - { - hprt0_dup.b.prtenchng = 1; - - if (hprt0.b.prtena == 1) - { - if ((hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) || - (hprt0.b.prtspd == HPRT0_PRTSPD_FULL_SPEED)) - { - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - - if (hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) - { - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 6000 ); - if (hcfg.b.fslspclksel != HCFG_6_MHZ) - { - if(pdev->cfg.phy_itface == USB_OTG_EMBEDDED_PHY) - { - USB_OTG_InitFSLSPClkSel(pdev , HCFG_6_MHZ); - } - - else - { - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 48000 ); - if (hcfg.b.fslspclksel != HCFG_48_MHZ) - { - USB_OTG_InitFSLSPClkSel(pdev ,HCFG_48_MHZ ); - } - } - } - } - } - - USBH_HCD_INT_fops->DevPortEnabled(pdev); - - /*unmask disconnect interrupt */ - intmsk.d32 = 0; - intmsk.b.disconnect = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); - } - else - { - USBH_HCD_INT_fops->DevPortDisabled(pdev); - - } - } - - /* Overcurrent Change Interrupt */ - if (hprt0.b.prtovrcurrchng) - { - hprt0_dup.b.prtovrcurrchng = 1; - retval |= 1; - } - - /* Clear Port Interrupts */ - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0_dup.d32); - - return retval; -} -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -/** -* @brief USB_OTG_USBH_handle_hc_n_Out_ISR -* Handles interrupt for a specific Host Channel -* @param pdev: Selected device -* @param hc_num: Channel number -* @retval status -*/ -uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num) -{ - - USB_OTG_HCINTn_TypeDef hcint; - USB_OTG_HCINTMSK_TypeDef hcintmsk; - USB_OTG_HC_REGS *hcreg; - USB_OTG_HCCHAR_TypeDef hcchar; - - hcreg = pdev->regs.HC_REGS[num]; - hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT); - hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK); - hcint.d32 = hcint.d32 & hcintmsk.d32; - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR); - - if (hcint.b.ahberr) - { - CLEAR_HC_INT(hcreg ,ahberr); - UNMASK_HOST_INT_CHH (num); - } - else if (hcint.b.ack) - { - CLEAR_HC_INT(hcreg , ack); - } - else if (hcint.b.frmovrun) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg ,frmovrun); - } - else if (hcint.b.xfercompl) - { - pdev->host.ErrCnt[num] = 0; - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , xfercompl); - pdev->host.HC_Status[num] = HC_XFRC; - } - - else if (hcint.b.stall) - { - CLEAR_HC_INT(hcreg , stall); - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - pdev->host.HC_Status[num] = HC_STALL; - } - - else if (hcint.b.nak) - { - pdev->host.ErrCnt[num] = 0; - UNMASK_HOST_INT_CHH (num); - if (pdev->cfg.dma_enable == 0) - { - USB_OTG_HC_Halt(pdev, num); - } - CLEAR_HC_INT(hcreg , nak); - pdev->host.HC_Status[num] = HC_NAK; - } - - else if (hcint.b.xacterr) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - pdev->host.HC_Status[num] = HC_XACTERR; - CLEAR_HC_INT(hcreg , xacterr); - } - else if (hcint.b.nyet) - { - pdev->host.ErrCnt[num] = 0; - UNMASK_HOST_INT_CHH (num); - if (pdev->cfg.dma_enable == 0) - { - USB_OTG_HC_Halt(pdev, num); - } - CLEAR_HC_INT(hcreg , nyet); - pdev->host.HC_Status[num] = HC_NYET; - } - else if (hcint.b.datatglerr) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - pdev->host.HC_Status[num] = HC_DATATGLERR; - - CLEAR_HC_INT(hcreg , datatglerr); - } - else if (hcint.b.chhltd) - { - MASK_HOST_INT_CHH (num); - - if(pdev->host.HC_Status[num] == HC_XFRC) - { - pdev->host.URB_State[num] = URB_DONE; - - if (hcchar.b.eptype == EP_TYPE_BULK) - { - pdev->host.hc[num].toggle_out ^= 1; - } - } - else if(pdev->host.HC_Status[num] == HC_NAK) - { - pdev->host.URB_State[num] = URB_NOTREADY; - } - else if(pdev->host.HC_Status[num] == HC_NYET) - { - if(pdev->host.hc[num].do_ping == 1) - { - USB_OTG_HC_DoPing(pdev, num); - } - pdev->host.URB_State[num] = URB_NOTREADY; - } - else if(pdev->host.HC_Status[num] == HC_STALL) - { - pdev->host.URB_State[num] = URB_STALL; - } - else if(pdev->host.HC_Status[num] == HC_XACTERR) - { - { - pdev->host.URB_State[num] = URB_ERROR; - } - } - CLEAR_HC_INT(hcreg , chhltd); - } - - - return 1; -} -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -/** -* @brief USB_OTG_USBH_handle_hc_n_In_ISR -* Handles interrupt for a specific Host Channel -* @param pdev: Selected device -* @param hc_num: Channel number -* @retval status -*/ -uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num) -{ - USB_OTG_HCINTn_TypeDef hcint; - USB_OTG_HCINTMSK_TypeDef hcintmsk; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HC_REGS *hcreg; - - hcreg = pdev->regs.HC_REGS[num]; - hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT); - hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK); - hcint.d32 = hcint.d32 & hcintmsk.d32; - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR); - hcintmsk.d32 = 0; - - if (hcint.b.ahberr) - { - CLEAR_HC_INT(hcreg ,ahberr); - UNMASK_HOST_INT_CHH (num); - } - else if (hcint.b.ack) - { - CLEAR_HC_INT(hcreg ,ack); - } - - else if (hcint.b.stall) - { - UNMASK_HOST_INT_CHH (num); - pdev->host.HC_Status[num] = HC_STALL; - CLEAR_HC_INT(hcreg , nak); /* Clear the NAK Condition */ - CLEAR_HC_INT(hcreg , stall); /* Clear the STALL Condition */ - hcint.b.nak = 0; /* NOTE: When there is a 'stall', reset also nak, - else, the pdev->host.HC_Status = HC_STALL - will be overwritten by 'nak' in code below */ - USB_OTG_HC_Halt(pdev, num); - } - else if (hcint.b.datatglerr) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - pdev->host.HC_Status[num] = HC_DATATGLERR; - CLEAR_HC_INT(hcreg , datatglerr); - } - - if (hcint.b.frmovrun) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg ,frmovrun); - } - - else if (hcint.b.xfercompl) - { - if (pdev->cfg.dma_enable == 1) - { - hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCTSIZ); - pdev->host.XferCnt[num] = pdev->host.hc[num].xfer_len - hctsiz.b.xfersize; - } - - pdev->host.HC_Status[num] = HC_XFRC; - pdev->host.ErrCnt [num]= 0; - CLEAR_HC_INT(hcreg , xfercompl); - - if ((hcchar.b.eptype == EP_TYPE_CTRL)|| - (hcchar.b.eptype == EP_TYPE_BULK)) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - pdev->host.hc[num].toggle_in ^= 1; - - } - else if(hcchar.b.eptype == EP_TYPE_INTR) - { - hcchar.b.oddfrm = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32); - pdev->host.URB_State[num] = URB_DONE; - } - } - else if (hcint.b.chhltd) - { - MASK_HOST_INT_CHH (num); - - if(pdev->host.HC_Status[num] == HC_XFRC) - { - pdev->host.URB_State[num] = URB_DONE; - } - - else if (pdev->host.HC_Status[num] == HC_STALL) - { - pdev->host.URB_State[num] = URB_STALL; - } - - else if((pdev->host.HC_Status[num] == HC_XACTERR) || - (pdev->host.HC_Status[num] == HC_DATATGLERR)) - { - pdev->host.ErrCnt[num] = 0; - pdev->host.URB_State[num] = URB_ERROR; - - } - else if(hcchar.b.eptype == EP_TYPE_INTR) - { - pdev->host.hc[num].toggle_in ^= 1; - } - - CLEAR_HC_INT(hcreg , chhltd); - - } - else if (hcint.b.xacterr) - { - UNMASK_HOST_INT_CHH (num); - pdev->host.HC_Status[num] = HC_XACTERR; - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , xacterr); - } - else if (hcint.b.nak) - { - if(hcchar.b.eptype == EP_TYPE_INTR) - { - UNMASK_HOST_INT_CHH (num); - if (pdev->cfg.dma_enable == 0) - { - USB_OTG_HC_Halt(pdev, num); - } - } - - pdev->host.HC_Status[num] = HC_NAK; - CLEAR_HC_INT(hcreg , nak); - - if ((hcchar.b.eptype == EP_TYPE_CTRL)|| - (hcchar.b.eptype == EP_TYPE_BULK)) - { - /* re-activate the channel */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32); - } - } - - - return 1; - -} - -/** -* @brief USB_OTG_USBH_handle_rx_qlvl_ISR -* Handles the Rx Status Queue Level Interrupt -* @param pdev: Selected device -* @retval status -*/ -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GRXFSTS_TypeDef grxsts; - USB_OTG_GINTMSK_TypeDef intmsk; - USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HCCHAR_TypeDef hcchar; - __IO uint8_t channelnum =0; - uint32_t count; - - /* Disable the Rx Status Queue Level interrupt */ - intmsk.d32 = 0; - intmsk.b.rxstsqlvl = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); - - grxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRXSTSP); - channelnum = grxsts.b.chnum; - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR); - - switch (grxsts.b.pktsts) - { - case GRXSTS_PKTSTS_IN: - /* Read the data into the host buffer. */ - if ((grxsts.b.bcnt > 0) && (pdev->host.hc[channelnum].xfer_buff != (void *)0)) - { - - USB_OTG_ReadPacket(pdev, pdev->host.hc[channelnum].xfer_buff, grxsts.b.bcnt); - /*manage multiple Xfer */ - pdev->host.hc[grxsts.b.chnum].xfer_buff += grxsts.b.bcnt; - pdev->host.hc[grxsts.b.chnum].xfer_count += grxsts.b.bcnt; - - - count = pdev->host.hc[channelnum].xfer_count; - pdev->host.XferCnt[channelnum] = count; - - hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCTSIZ); - if(hctsiz.b.pktcnt > 0) - { - /* re-activate the channel when more packets are expected */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR, hcchar.d32); - } - } - break; - - case GRXSTS_PKTSTS_IN_XFER_COMP: - - case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: - case GRXSTS_PKTSTS_CH_HALTED: - default: - break; - } - - /* Enable the Rx Status Queue Level interrupt */ - intmsk.b.rxstsqlvl = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - return 1; -} - -/** -* @brief USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR -* Handles the incomplete Periodic transfer Interrupt -* @param pdev: Selected device -* @retval status -*/ -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_HCCHAR_TypeDef hcchar; - - - - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[0]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[0]->HCCHAR, hcchar.d32); - - gintsts.d32 = 0; - /* Clear interrupt */ - gintsts.b.incomplisoout = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usb_hcd_int.c + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief Host driver interrupt subroutines + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_core.h" +#include "usb_defines.h" +#include "usb_hcd_int.h" + +#if defined (__CC_ARM) /*!< ARM Compiler */ +#pragma O0 +#elif defined (__GNUC__) /*!< GNU Compiler */ +#pragma GCC optimize ("O0") +#elif defined (__TASKING__) /*!< TASKING Compiler */ +#pragma optimize=0 + +#endif /* __CC_ARM */ + +/** @addtogroup USB_OTG_DRIVER +* @{ +*/ + +/** @defgroup USB_HCD_INT +* @brief This file contains the interrupt subroutines for the Host mode. +* @{ +*/ + + +/** @defgroup USB_HCD_INT_Private_Defines +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_HCD_INT_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + + +/** @defgroup USB_HCD_INT_Private_Macros +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_HCD_INT_Private_Variables +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_HCD_INT_Private_FunctionPrototypes +* @{ +*/ + +static uint32_t USB_OTG_USBH_handle_sof_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t USB_OTG_USBH_handle_port_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev); +static uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , + uint32_t num); +static uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , + uint32_t num); +static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev); +static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev); +static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev); +static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev); +static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev); + +/** +* @} +*/ + + +/** @defgroup USB_HCD_INT_Private_Functions +* @{ +*/ + +/** +* @brief HOST_Handle_ISR +* This function handles all USB Host Interrupts +* @param pdev: Selected device +* @retval status +*/ + +uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + uint32_t retval = 0; + + gintsts.d32 = 0; + + /* Check if HOST Mode */ + if (USB_OTG_IsHostMode(pdev)) + { + gintsts.d32 = USB_OTG_ReadCoreItr(pdev); + if (!gintsts.d32) + { + return 0; + } + + if (gintsts.b.sofintr) + { + retval |= USB_OTG_USBH_handle_sof_ISR (pdev); + } + + if (gintsts.b.rxstsqlvl) + { + retval |= USB_OTG_USBH_handle_rx_qlvl_ISR (pdev); + } + + if (gintsts.b.nptxfempty) + { + retval |= USB_OTG_USBH_handle_nptxfempty_ISR (pdev); + } + + if (gintsts.b.ptxfempty) + { + retval |= USB_OTG_USBH_handle_ptxfempty_ISR (pdev); + } + + if (gintsts.b.hcintr) + { + retval |= USB_OTG_USBH_handle_hc_ISR (pdev); + } + + if (gintsts.b.portintr) + { + retval |= USB_OTG_USBH_handle_port_ISR (pdev); + } + + if (gintsts.b.disconnect) + { + retval |= USB_OTG_USBH_handle_Disconnect_ISR (pdev); + + } + + if (gintsts.b.incomplisoout) + { + retval |= USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (pdev); + } + + + } + return retval; +} + +/** +* @brief USB_OTG_USBH_handle_hc_ISR +* This function indicates that one or more host channels has a pending +* @param pdev: Selected device +* @retval status +*/ +static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_HAINT_TypeDef haint; + USB_OTG_HCCHAR_TypeDef hcchar; + uint32_t i = 0; + uint32_t retval = 0; + + /* Clear appropriate bits in HCINTn to clear the interrupt bit in + * GINTSTS */ + + haint.d32 = USB_OTG_ReadHostAllChannels_intr(pdev); + + for (i = 0; i < pdev->cfg.host_channels ; i++) + { + if (haint.b.chint & (1 << i)) + { + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); + + if (hcchar.b.epdir) + { + retval |= USB_OTG_USBH_handle_hc_n_In_ISR (pdev, i); + } + else + { + retval |= USB_OTG_USBH_handle_hc_n_Out_ISR (pdev, i); + } + } + } + + return retval; +} + +/** +* @brief USB_OTG_otg_hcd_handle_sof_intr +* Handles the start-of-frame interrupt in host mode. +* @param pdev: Selected device +* @retval status +*/ +static uint32_t USB_OTG_USBH_handle_sof_ISR (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + gintsts.d32 = 0; + + USBH_HCD_INT_fops->SOF(pdev); + + /* Clear interrupt */ + gintsts.b.sofintr = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); + + return 1; +} + +/** +* @brief USB_OTG_USBH_handle_Disconnect_ISR +* Handles disconnect event. +* @param pdev: Selected device +* @retval status +*/ +static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + + gintsts.d32 = 0; + + USBH_HCD_INT_fops->DevDisconnected(pdev); + + /* Clear interrupt */ + gintsts.b.disconnect = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); + + return 1; +} +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ +/** +* @brief USB_OTG_USBH_handle_nptxfempty_ISR +* Handles non periodic tx fifo empty. +* @param pdev: Selected device +* @retval status +*/ +static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTMSK_TypeDef intmsk; + USB_OTG_HNPTXSTS_TypeDef hnptxsts; + uint16_t len_words , len; + + hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); + + len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4; + + while ((hnptxsts.b.nptxfspcavail > len_words)&& + (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len != 0)) + { + + len = hnptxsts.b.nptxfspcavail * 4; + + if (len > pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len) + { + /* Last packet */ + len = pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len; + + intmsk.d32 = 0; + intmsk.b.nptxfempty = 1; + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); + } + + len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4; + + USB_OTG_WritePacket (pdev , pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff, hnptxsts.b.nptxqtop.chnum, len); + + pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff += len; + pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len -= len; + pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_count += len; + + hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); + } + + return 1; +} +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ +/** +* @brief USB_OTG_USBH_handle_ptxfempty_ISR +* Handles periodic tx fifo empty +* @param pdev: Selected device +* @retval status +*/ +static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTMSK_TypeDef intmsk; + USB_OTG_HPTXSTS_TypeDef hptxsts; + uint16_t len_words , len; + + hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); + + len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4; + + while ((hptxsts.b.ptxfspcavail > len_words)&& + (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len != 0)) + { + + len = hptxsts.b.ptxfspcavail * 4; + + if (len > pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len) + { + len = pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len; + /* Last packet */ + intmsk.d32 = 0; + intmsk.b.ptxfempty = 1; + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); + } + + len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4; + + USB_OTG_WritePacket (pdev , pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff, hptxsts.b.ptxqtop.chnum, len); + + pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff += len; + pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len -= len; + pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_count += len; + + hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); + } + + return 1; +} + +/** +* @brief USB_OTG_USBH_handle_port_ISR +* This function determines which interrupt conditions have occurred +* @param pdev: Selected device +* @retval status +*/ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ +static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_HPRT0_TypeDef hprt0; + USB_OTG_HPRT0_TypeDef hprt0_dup; + USB_OTG_HCFG_TypeDef hcfg; + uint32_t retval = 0; + USB_OTG_GINTMSK_TypeDef intmsk; + + intmsk.d32 = 0; + hcfg.d32 = 0; + hprt0.d32 = 0; + hprt0_dup.d32 = 0; + + hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); + hprt0_dup.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); + + /* Clear the interrupt bits in GINTSTS */ + + hprt0_dup.b.prtena = 0; + hprt0_dup.b.prtconndet = 0; + hprt0_dup.b.prtenchng = 0; + hprt0_dup.b.prtovrcurrchng = 0; + + /* Port Connect Detected */ + if (hprt0.b.prtconndet) + { + hprt0_dup.b.prtconndet = 1; + USBH_HCD_INT_fops->DevConnected(pdev); + retval |= 1; + } + + /* Port Enable Changed */ + if (hprt0.b.prtenchng) + { + hprt0_dup.b.prtenchng = 1; + + if (hprt0.b.prtena == 1) + { + if ((hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) || + (hprt0.b.prtspd == HPRT0_PRTSPD_FULL_SPEED)) + { + hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); + + if (hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) + { + USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 6000 ); + if (hcfg.b.fslspclksel != HCFG_6_MHZ) + { + if(pdev->cfg.phy_itface == USB_OTG_EMBEDDED_PHY) + { + USB_OTG_InitFSLSPClkSel(pdev , HCFG_6_MHZ); + } + + else + { + USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 48000 ); + if (hcfg.b.fslspclksel != HCFG_48_MHZ) + { + USB_OTG_InitFSLSPClkSel(pdev ,HCFG_48_MHZ ); + } + } + } + } + } + + USBH_HCD_INT_fops->DevPortEnabled(pdev); + + /*unmask disconnect interrupt */ + intmsk.d32 = 0; + intmsk.b.disconnect = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); + } + else + { + USBH_HCD_INT_fops->DevPortDisabled(pdev); + + } + } + + /* Overcurrent Change Interrupt */ + if (hprt0.b.prtovrcurrchng) + { + hprt0_dup.b.prtovrcurrchng = 1; + retval |= 1; + } + + /* Clear Port Interrupts */ + USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0_dup.d32); + + return retval; +} +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ +/** +* @brief USB_OTG_USBH_handle_hc_n_Out_ISR +* Handles interrupt for a specific Host Channel +* @param pdev: Selected device +* @param hc_num: Channel number +* @retval status +*/ +uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num) +{ + + USB_OTG_HCINTn_TypeDef hcint; + USB_OTG_HCINTMSK_TypeDef hcintmsk; + USB_OTG_HC_REGS *hcreg; + USB_OTG_HCCHAR_TypeDef hcchar; + + hcreg = pdev->regs.HC_REGS[num]; + hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT); + hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK); + hcint.d32 = hcint.d32 & hcintmsk.d32; + + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR); + + if (hcint.b.ahberr) + { + CLEAR_HC_INT(hcreg ,ahberr); + UNMASK_HOST_INT_CHH (num); + } + else if (hcint.b.ack) + { + CLEAR_HC_INT(hcreg , ack); + } + else if (hcint.b.frmovrun) + { + UNMASK_HOST_INT_CHH (num); + USB_OTG_HC_Halt(pdev, num); + CLEAR_HC_INT(hcreg ,frmovrun); + } + else if (hcint.b.xfercompl) + { + pdev->host.ErrCnt[num] = 0; + UNMASK_HOST_INT_CHH (num); + USB_OTG_HC_Halt(pdev, num); + CLEAR_HC_INT(hcreg , xfercompl); + pdev->host.HC_Status[num] = HC_XFRC; + } + + else if (hcint.b.stall) + { + CLEAR_HC_INT(hcreg , stall); + UNMASK_HOST_INT_CHH (num); + USB_OTG_HC_Halt(pdev, num); + pdev->host.HC_Status[num] = HC_STALL; + } + + else if (hcint.b.nak) + { + pdev->host.ErrCnt[num] = 0; + UNMASK_HOST_INT_CHH (num); + if (pdev->cfg.dma_enable == 0) + { + USB_OTG_HC_Halt(pdev, num); + } + CLEAR_HC_INT(hcreg , nak); + pdev->host.HC_Status[num] = HC_NAK; + } + + else if (hcint.b.xacterr) + { + UNMASK_HOST_INT_CHH (num); + USB_OTG_HC_Halt(pdev, num); + pdev->host.HC_Status[num] = HC_XACTERR; + CLEAR_HC_INT(hcreg , xacterr); + } + else if (hcint.b.nyet) + { + pdev->host.ErrCnt[num] = 0; + UNMASK_HOST_INT_CHH (num); + if (pdev->cfg.dma_enable == 0) + { + USB_OTG_HC_Halt(pdev, num); + } + CLEAR_HC_INT(hcreg , nyet); + pdev->host.HC_Status[num] = HC_NYET; + } + else if (hcint.b.datatglerr) + { + UNMASK_HOST_INT_CHH (num); + USB_OTG_HC_Halt(pdev, num); + CLEAR_HC_INT(hcreg , nak); + pdev->host.HC_Status[num] = HC_DATATGLERR; + + CLEAR_HC_INT(hcreg , datatglerr); + } + else if (hcint.b.chhltd) + { + MASK_HOST_INT_CHH (num); + + if(pdev->host.HC_Status[num] == HC_XFRC) + { + pdev->host.URB_State[num] = URB_DONE; + + if (hcchar.b.eptype == EP_TYPE_BULK) + { + pdev->host.hc[num].toggle_out ^= 1; + } + } + else if(pdev->host.HC_Status[num] == HC_NAK) + { + pdev->host.URB_State[num] = URB_NOTREADY; + } + else if(pdev->host.HC_Status[num] == HC_NYET) + { + if(pdev->host.hc[num].do_ping == 1) + { + USB_OTG_HC_DoPing(pdev, num); + } + pdev->host.URB_State[num] = URB_NOTREADY; + } + else if(pdev->host.HC_Status[num] == HC_STALL) + { + pdev->host.URB_State[num] = URB_STALL; + } + else if(pdev->host.HC_Status[num] == HC_XACTERR) + { + { + pdev->host.URB_State[num] = URB_ERROR; + } + } + CLEAR_HC_INT(hcreg , chhltd); + } + + + return 1; +} +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ +/** +* @brief USB_OTG_USBH_handle_hc_n_In_ISR +* Handles interrupt for a specific Host Channel +* @param pdev: Selected device +* @param hc_num: Channel number +* @retval status +*/ +uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num) +{ + USB_OTG_HCINTn_TypeDef hcint; + USB_OTG_HCINTMSK_TypeDef hcintmsk; + USB_OTG_HCCHAR_TypeDef hcchar; + USB_OTG_HCTSIZn_TypeDef hctsiz; + USB_OTG_HC_REGS *hcreg; + + hcreg = pdev->regs.HC_REGS[num]; + hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT); + hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK); + hcint.d32 = hcint.d32 & hcintmsk.d32; + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR); + hcintmsk.d32 = 0; + + if (hcint.b.ahberr) + { + CLEAR_HC_INT(hcreg ,ahberr); + UNMASK_HOST_INT_CHH (num); + } + else if (hcint.b.ack) + { + CLEAR_HC_INT(hcreg ,ack); + } + + else if (hcint.b.stall) + { + UNMASK_HOST_INT_CHH (num); + pdev->host.HC_Status[num] = HC_STALL; + CLEAR_HC_INT(hcreg , nak); /* Clear the NAK Condition */ + CLEAR_HC_INT(hcreg , stall); /* Clear the STALL Condition */ + hcint.b.nak = 0; /* NOTE: When there is a 'stall', reset also nak, + else, the pdev->host.HC_Status = HC_STALL + will be overwritten by 'nak' in code below */ + USB_OTG_HC_Halt(pdev, num); + } + else if (hcint.b.datatglerr) + { + UNMASK_HOST_INT_CHH (num); + USB_OTG_HC_Halt(pdev, num); + CLEAR_HC_INT(hcreg , nak); + pdev->host.HC_Status[num] = HC_DATATGLERR; + CLEAR_HC_INT(hcreg , datatglerr); + } + + if (hcint.b.frmovrun) + { + UNMASK_HOST_INT_CHH (num); + USB_OTG_HC_Halt(pdev, num); + CLEAR_HC_INT(hcreg ,frmovrun); + } + + else if (hcint.b.xfercompl) + { + if (pdev->cfg.dma_enable == 1) + { + hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCTSIZ); + pdev->host.XferCnt[num] = pdev->host.hc[num].xfer_len - hctsiz.b.xfersize; + } + + pdev->host.HC_Status[num] = HC_XFRC; + pdev->host.ErrCnt [num]= 0; + CLEAR_HC_INT(hcreg , xfercompl); + + if ((hcchar.b.eptype == EP_TYPE_CTRL)|| + (hcchar.b.eptype == EP_TYPE_BULK)) + { + UNMASK_HOST_INT_CHH (num); + USB_OTG_HC_Halt(pdev, num); + CLEAR_HC_INT(hcreg , nak); + pdev->host.hc[num].toggle_in ^= 1; + + } + else if(hcchar.b.eptype == EP_TYPE_INTR) + { + hcchar.b.oddfrm = 1; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32); + pdev->host.URB_State[num] = URB_DONE; + } + } + else if (hcint.b.chhltd) + { + MASK_HOST_INT_CHH (num); + + if(pdev->host.HC_Status[num] == HC_XFRC) + { + pdev->host.URB_State[num] = URB_DONE; + } + + else if (pdev->host.HC_Status[num] == HC_STALL) + { + pdev->host.URB_State[num] = URB_STALL; + } + + else if((pdev->host.HC_Status[num] == HC_XACTERR) || + (pdev->host.HC_Status[num] == HC_DATATGLERR)) + { + pdev->host.ErrCnt[num] = 0; + pdev->host.URB_State[num] = URB_ERROR; + + } + else if(hcchar.b.eptype == EP_TYPE_INTR) + { + pdev->host.hc[num].toggle_in ^= 1; + } + + CLEAR_HC_INT(hcreg , chhltd); + + } + else if (hcint.b.xacterr) + { + UNMASK_HOST_INT_CHH (num); + pdev->host.HC_Status[num] = HC_XACTERR; + USB_OTG_HC_Halt(pdev, num); + CLEAR_HC_INT(hcreg , xacterr); + } + else if (hcint.b.nak) + { + if(hcchar.b.eptype == EP_TYPE_INTR) + { + UNMASK_HOST_INT_CHH (num); + if (pdev->cfg.dma_enable == 0) + { + USB_OTG_HC_Halt(pdev, num); + } + } + + pdev->host.HC_Status[num] = HC_NAK; + CLEAR_HC_INT(hcreg , nak); + + if ((hcchar.b.eptype == EP_TYPE_CTRL)|| + (hcchar.b.eptype == EP_TYPE_BULK)) + { + /* re-activate the channel */ + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32); + } + } + + + return 1; + +} + +/** +* @brief USB_OTG_USBH_handle_rx_qlvl_ISR +* Handles the Rx Status Queue Level Interrupt +* @param pdev: Selected device +* @retval status +*/ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ +static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GRXFSTS_TypeDef grxsts; + USB_OTG_GINTMSK_TypeDef intmsk; + USB_OTG_HCTSIZn_TypeDef hctsiz; + USB_OTG_HCCHAR_TypeDef hcchar; + __IO uint8_t channelnum =0; + uint32_t count; + + /* Disable the Rx Status Queue Level interrupt */ + intmsk.d32 = 0; + intmsk.b.rxstsqlvl = 1; + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); + + grxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRXSTSP); + channelnum = grxsts.b.chnum; + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR); + + switch (grxsts.b.pktsts) + { + case GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if ((grxsts.b.bcnt > 0) && (pdev->host.hc[channelnum].xfer_buff != (void *)0)) + { + + USB_OTG_ReadPacket(pdev, pdev->host.hc[channelnum].xfer_buff, grxsts.b.bcnt); + /*manage multiple Xfer */ + pdev->host.hc[grxsts.b.chnum].xfer_buff += grxsts.b.bcnt; + pdev->host.hc[grxsts.b.chnum].xfer_count += grxsts.b.bcnt; + + + count = pdev->host.hc[channelnum].xfer_count; + pdev->host.XferCnt[channelnum] = count; + + hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCTSIZ); + if(hctsiz.b.pktcnt > 0) + { + /* re-activate the channel when more packets are expected */ + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR, hcchar.d32); + } + } + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; + } + + /* Enable the Rx Status Queue Level interrupt */ + intmsk.b.rxstsqlvl = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); + return 1; +} + +/** +* @brief USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR +* Handles the incomplete Periodic transfer Interrupt +* @param pdev: Selected device +* @retval status +*/ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ +static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev) +{ + + USB_OTG_GINTSTS_TypeDef gintsts; + USB_OTG_HCCHAR_TypeDef hcchar; + + + + + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[0]->HCCHAR); + hcchar.b.chen = 1; + hcchar.b.chdis = 1; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[0]->HCCHAR, hcchar.d32); + + gintsts.d32 = 0; + /* Clear interrupt */ + gintsts.b.incomplisoout = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); + + return 1; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_otg.c b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_otg.c index 8ca2fd7c9..a3b9eabfd 100644 --- a/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_otg.c +++ b/radio/src/thirdparty/STM32_USB-Host-Device_Lib_V2.2.0/Libraries/STM32_USB_OTG_Driver/src/usb_otg.c @@ -1,418 +1,418 @@ -/** - ****************************************************************************** - * @file usb_otg.c - * @author MCD Application Team - * @version V2.2.0 - * @date 09-November-2015 - * @brief OTG Core Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_defines.h" -#include "usb_regs.h" -#include "usb_core.h" -#include "usb_otg.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_OTG - * @brief This file is the interface between EFSL ans Host mass-storage class - * @{ - */ - - -/** @defgroup USB_OTG_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USB_OTG_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_FunctionPrototypes - * @{ - */ - -uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev); - -static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_Functions - * @{ - */ - - -/* OTG Interrupt Handler */ - - -/** - * @brief STM32_USBO_OTG_ISR_Handler - * - * @param None - * @retval : None - */ -uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t retval = 0; - USB_OTG_GINTSTS_TypeDef gintsts ; - gintsts.d32 = 0; - - gintsts.d32 = USB_OTG_Read_itr(pdev); - if (gintsts.d32 == 0) - { - return 0; - } - if (gintsts.b.otgintr) - { - retval |= USB_OTG_HandleOTG_ISR(pdev); - } - if (gintsts.b.conidstschng) - { - retval |= USB_OTG_HandleConnectorIDStatusChange_ISR(pdev); - } - if (gintsts.b.sessreqintr) - { - retval |= USB_OTG_HandleSessionRequest_ISR(pdev); - } - return retval; -} - - -/** - * @brief USB_OTG_Read_itr - * returns the Core Interrupt register - * @param None - * @retval : status - */ -static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_GINTMSK_TypeDef gintmsk; - USB_OTG_GINTMSK_TypeDef gintmsk_common; - - - gintsts.d32 = 0; - gintmsk.d32 = 0; - gintmsk_common.d32 = 0; - - /* OTG interrupts */ - gintmsk_common.b.sessreqintr = 1; - gintmsk_common.b.conidstschng = 1; - gintmsk_common.b.otgintr = 1; - - gintsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS); - gintmsk.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK); - return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32); -} - - -/** - * @brief USB_OTG_HandleOTG_ISR - * handles the OTG Interrupts - * @param None - * @retval : status - */ -static uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GOTGINT_TypeDef gotgint; - USB_OTG_GOTGCTL_TypeDef gotgctl; - - - gotgint.d32 = 0; - gotgctl.d32 = 0; - - gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT); - gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); - - if (gotgint.b.sesenddet) - { - gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); - - - if (USB_OTG_IsDeviceMode(pdev)) - { - - } - else if (USB_OTG_IsHostMode(pdev)) - { - - } - } - - /* ----> SRP SUCCESS or FAILURE INTERRUPT <---- */ - if (gotgint.b.sesreqsucstschng) - { - gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); - if (gotgctl.b.sesreqscs) /* Session request success */ - { - if (USB_OTG_IsDeviceMode(pdev)) - { - - } - /* Clear Session Request */ - gotgctl.d32 = 0; - gotgctl.b.sesreq = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0); - } - else /* Session request failure */ - { - if (USB_OTG_IsDeviceMode(pdev)) - { - - } - } - } - /* ----> HNP SUCCESS or FAILURE INTERRUPT <---- */ - if (gotgint.b.hstnegsucstschng) - { - gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); - - if (gotgctl.b.hstnegscs) /* Host negotiation success */ - { - if (USB_OTG_IsHostMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */ - { - - } - } - else /* Host negotiation failure */ - { - - } - gotgint.b.hstnegsucstschng = 1; /* Ack "Host Negotiation Success Status Change" interrupt. */ - } - /* ----> HOST NEGOTIATION DETECTED INTERRUPT <---- */ - if (gotgint.b.hstnegdet) - { - if (USB_OTG_IsDeviceMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */ - { - - } - else - { - - } - } - if (gotgint.b.adevtoutchng) - {} - if (gotgint.b.debdone) - { - USB_OTG_ResetPort(pdev); - } - /* Clear OTG INT */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); - return 1; -} - - -/** - * @brief USB_OTG_HandleConnectorIDStatusChange_ISR - * handles the Connector ID Status Change Interrupt - * @param None - * @retval : status - */ -static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef gintmsk; - USB_OTG_GOTGCTL_TypeDef gotgctl; - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0 ; - gintmsk.d32 = 0 ; - gotgctl.d32 = 0 ; - gintmsk.b.sofintr = 1; - - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, gintmsk.d32, 0); - gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); - - /* B-Device connector (Device Mode) */ - if (gotgctl.b.conidsts) - { - USB_OTG_DisableGlobalInt(pdev); - USB_OTG_CoreInitDev(pdev); - USB_OTG_EnableGlobalInt(pdev); - pdev->otg.OTG_State = B_PERIPHERAL; - } - else - { - USB_OTG_DisableGlobalInt(pdev); - USB_OTG_CoreInitHost(pdev); - USB_OTG_EnableGlobalInt(pdev); - pdev->otg.OTG_State = A_HOST; - } - /* Set flag and clear interrupt */ - gintsts.b.conidstschng = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - - -/** - * @brief USB_OTG_HandleSessionRequest_ISR - * Initiating the Session Request Protocol - * @param None - * @retval : status - */ -static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_GOTGCTL_TypeDef gotgctl; - - - gotgctl.d32 = 0; - gintsts.d32 = 0; - - gotgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL ); - if (USB_OTG_IsDeviceMode(pdev) && (gotgctl.b.bsesvld)) - { - - } - else if (gotgctl.b.asesvld) - { - } - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.sessreqintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - - -/** - * @brief USB_OTG_InitiateSRP - * Initiate an srp session - * @param None - * @retval : None - */ -void USB_OTG_InitiateSRP(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GOTGCTL_TypeDef otgctl; - - otgctl.d32 = 0; - - otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL ); - if (otgctl.b.sesreq) - { - return; /* SRP in progress */ - } - otgctl.b.sesreq = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32); -} - - -/** - * @brief USB_OTG_InitiateHNP - * Initiate HNP - * @param None - * @retval : None - */ -void USB_OTG_InitiateHNP(USB_OTG_CORE_HANDLE *pdev , uint8_t state, uint8_t mode) -{ - USB_OTG_GOTGCTL_TypeDef otgctl; - USB_OTG_HPRT0_TypeDef hprt0; - - otgctl.d32 = 0; - hprt0.d32 = 0; - - otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL ); - if (mode) - { /* Device mode */ - if (state) - { - - otgctl.b.devhnpen = 1; /* B-Dev has been enabled to perform HNP */ - otgctl.b.hnpreq = 1; /* Initiate an HNP req. to the connected USB host*/ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32); - } - } - else - { /* Host mode */ - if (state) - { - otgctl.b.hstsethnpen = 1; /* A-Dev has enabled B-device for HNP */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32); - /* Suspend the bus so that B-dev will disconnect indicating the initial condition for HNP to DWC_Core */ - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - hprt0.b.prtsusp = 1; /* The core clear this bit when disconnect interrupt generated (GINTSTS.DisconnInt = '1') */ - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - } -} - - -/** - * @brief USB_OTG_GetCurrentState - * Return current OTG State - * @param None - * @retval : None - */ -uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev) -{ - return pdev->otg.OTG_State; -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usb_otg.c + * @author MCD Application Team + * @version V2.2.0 + * @date 09-November-2015 + * @brief OTG Core Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_defines.h" +#include "usb_regs.h" +#include "usb_core.h" +#include "usb_otg.h" + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_OTG + * @brief This file is the interface between EFSL ans Host mass-storage class + * @{ + */ + + +/** @defgroup USB_OTG_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_OTG_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USB_OTG_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_OTG_Private_Variables + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_OTG_Private_FunctionPrototypes + * @{ + */ + +uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev); + +static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev); + +/** + * @} + */ + + +/** @defgroup USB_OTG_Private_Functions + * @{ + */ + + +/* OTG Interrupt Handler */ + + +/** + * @brief STM32_USBO_OTG_ISR_Handler + * + * @param None + * @retval : None + */ +uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t retval = 0; + USB_OTG_GINTSTS_TypeDef gintsts ; + gintsts.d32 = 0; + + gintsts.d32 = USB_OTG_Read_itr(pdev); + if (gintsts.d32 == 0) + { + return 0; + } + if (gintsts.b.otgintr) + { + retval |= USB_OTG_HandleOTG_ISR(pdev); + } + if (gintsts.b.conidstschng) + { + retval |= USB_OTG_HandleConnectorIDStatusChange_ISR(pdev); + } + if (gintsts.b.sessreqintr) + { + retval |= USB_OTG_HandleSessionRequest_ISR(pdev); + } + return retval; +} + + +/** + * @brief USB_OTG_Read_itr + * returns the Core Interrupt register + * @param None + * @retval : status + */ +static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + USB_OTG_GINTMSK_TypeDef gintmsk; + USB_OTG_GINTMSK_TypeDef gintmsk_common; + + + gintsts.d32 = 0; + gintmsk.d32 = 0; + gintmsk_common.d32 = 0; + + /* OTG interrupts */ + gintmsk_common.b.sessreqintr = 1; + gintmsk_common.b.conidstschng = 1; + gintmsk_common.b.otgintr = 1; + + gintsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS); + gintmsk.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK); + return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32); +} + + +/** + * @brief USB_OTG_HandleOTG_ISR + * handles the OTG Interrupts + * @param None + * @retval : status + */ +static uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GOTGINT_TypeDef gotgint; + USB_OTG_GOTGCTL_TypeDef gotgctl; + + + gotgint.d32 = 0; + gotgctl.d32 = 0; + + gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT); + gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); + + if (gotgint.b.sesenddet) + { + gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); + + + if (USB_OTG_IsDeviceMode(pdev)) + { + + } + else if (USB_OTG_IsHostMode(pdev)) + { + + } + } + + /* ----> SRP SUCCESS or FAILURE INTERRUPT <---- */ + if (gotgint.b.sesreqsucstschng) + { + gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); + if (gotgctl.b.sesreqscs) /* Session request success */ + { + if (USB_OTG_IsDeviceMode(pdev)) + { + + } + /* Clear Session Request */ + gotgctl.d32 = 0; + gotgctl.b.sesreq = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0); + } + else /* Session request failure */ + { + if (USB_OTG_IsDeviceMode(pdev)) + { + + } + } + } + /* ----> HNP SUCCESS or FAILURE INTERRUPT <---- */ + if (gotgint.b.hstnegsucstschng) + { + gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); + + if (gotgctl.b.hstnegscs) /* Host negotiation success */ + { + if (USB_OTG_IsHostMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */ + { + + } + } + else /* Host negotiation failure */ + { + + } + gotgint.b.hstnegsucstschng = 1; /* Ack "Host Negotiation Success Status Change" interrupt. */ + } + /* ----> HOST NEGOTIATION DETECTED INTERRUPT <---- */ + if (gotgint.b.hstnegdet) + { + if (USB_OTG_IsDeviceMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */ + { + + } + else + { + + } + } + if (gotgint.b.adevtoutchng) + {} + if (gotgint.b.debdone) + { + USB_OTG_ResetPort(pdev); + } + /* Clear OTG INT */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); + return 1; +} + + +/** + * @brief USB_OTG_HandleConnectorIDStatusChange_ISR + * handles the Connector ID Status Change Interrupt + * @param None + * @retval : status + */ +static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTMSK_TypeDef gintmsk; + USB_OTG_GOTGCTL_TypeDef gotgctl; + USB_OTG_GINTSTS_TypeDef gintsts; + + gintsts.d32 = 0 ; + gintmsk.d32 = 0 ; + gotgctl.d32 = 0 ; + gintmsk.b.sofintr = 1; + + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, gintmsk.d32, 0); + gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); + + /* B-Device connector (Device Mode) */ + if (gotgctl.b.conidsts) + { + USB_OTG_DisableGlobalInt(pdev); + USB_OTG_CoreInitDev(pdev); + USB_OTG_EnableGlobalInt(pdev); + pdev->otg.OTG_State = B_PERIPHERAL; + } + else + { + USB_OTG_DisableGlobalInt(pdev); + USB_OTG_CoreInitHost(pdev); + USB_OTG_EnableGlobalInt(pdev); + pdev->otg.OTG_State = A_HOST; + } + /* Set flag and clear interrupt */ + gintsts.b.conidstschng = 1; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); + return 1; +} + + +/** + * @brief USB_OTG_HandleSessionRequest_ISR + * Initiating the Session Request Protocol + * @param None + * @retval : status + */ +static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + USB_OTG_GOTGCTL_TypeDef gotgctl; + + + gotgctl.d32 = 0; + gintsts.d32 = 0; + + gotgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL ); + if (USB_OTG_IsDeviceMode(pdev) && (gotgctl.b.bsesvld)) + { + + } + else if (gotgctl.b.asesvld) + { + } + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.sessreqintr = 1; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); + return 1; +} + + +/** + * @brief USB_OTG_InitiateSRP + * Initiate an srp session + * @param None + * @retval : None + */ +void USB_OTG_InitiateSRP(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GOTGCTL_TypeDef otgctl; + + otgctl.d32 = 0; + + otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL ); + if (otgctl.b.sesreq) + { + return; /* SRP in progress */ + } + otgctl.b.sesreq = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32); +} + + +/** + * @brief USB_OTG_InitiateHNP + * Initiate HNP + * @param None + * @retval : None + */ +void USB_OTG_InitiateHNP(USB_OTG_CORE_HANDLE *pdev , uint8_t state, uint8_t mode) +{ + USB_OTG_GOTGCTL_TypeDef otgctl; + USB_OTG_HPRT0_TypeDef hprt0; + + otgctl.d32 = 0; + hprt0.d32 = 0; + + otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL ); + if (mode) + { /* Device mode */ + if (state) + { + + otgctl.b.devhnpen = 1; /* B-Dev has been enabled to perform HNP */ + otgctl.b.hnpreq = 1; /* Initiate an HNP req. to the connected USB host*/ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32); + } + } + else + { /* Host mode */ + if (state) + { + otgctl.b.hstsethnpen = 1; /* A-Dev has enabled B-device for HNP */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32); + /* Suspend the bus so that B-dev will disconnect indicating the initial condition for HNP to DWC_Core */ + hprt0.d32 = USB_OTG_ReadHPRT0(pdev); + hprt0.b.prtsusp = 1; /* The core clear this bit when disconnect interrupt generated (GINTSTS.DisconnInt = '1') */ + USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); + } + } +} + + +/** + * @brief USB_OTG_GetCurrentState + * Return current OTG State + * @param None + * @retval : None + */ +uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev) +{ + return pdev->otg.OTG_State; +} + + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/translations.h b/radio/src/translations.h index 5b8682e55..2dfd7b536 100644 --- a/radio/src/translations.h +++ b/radio/src/translations.h @@ -1,1077 +1,1077 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _TRANSLATIONS_H_ -#define _TRANSLATIONS_H_ - -#if defined(TRANSLATIONS_FR) -#include "translations/fr.h" -#define LEN_SPECIAL_CHARS 3 -#elif defined(TRANSLATIONS_IT) -#include "translations/it.h" -#define LEN_SPECIAL_CHARS 1 -#elif defined(TRANSLATIONS_SE) -#include "translations/se.h" -#define LEN_SPECIAL_CHARS 6 -#elif defined(TRANSLATIONS_FI) -#include "translations/fi.h" -#define LEN_SPECIAL_CHARS 6 -#elif defined(TRANSLATIONS_DE) -#include "translations/de.h" -#define LEN_SPECIAL_CHARS 6 -#elif defined(TRANSLATIONS_CZ) -#include "translations/cz.h" -#define LEN_SPECIAL_CHARS 17 -#elif defined(TRANSLATIONS_ES) -#include "translations/es.h" -#define LEN_SPECIAL_CHARS 0 -#elif defined(TRANSLATIONS_PL) -#include "translations/pl.h" -#define LEN_SPECIAL_CHARS 0 -#elif defined(TRANSLATIONS_PT) -#include "translations/pt.h" -#define LEN_SPECIAL_CHARS 0 -#elif defined(TRANSLATIONS_NL) -#include "translations/nl.h" -#define LEN_SPECIAL_CHARS 0 -#else -#include "translations/en.h" -#define LEN_SPECIAL_CHARS 0 -#endif - -#define PSIZE(x) ( sizeof(x) - 1 ) -#define EOFS(x) ( OFS_##x + sizeof(TR_##x) ) - -#if defined(PCBTARANIS) -#define HINT(s) " " s " " -#else -#define HINT(s) s -#endif - -#if LCD_W >= 480 - #define TR3(x, y, z) z - #define TR2(x, y) y -#elif LCD_W >= 212 - #define TR3(x, y, z) y - #define TR2(x, y) y -#else - #define TR3(x, y, z) x - #define TR2(x, y) x -#endif - -#define TR(x, y) TR2(x, y) // for compatibility - -#if defined(COLORLCD) - #define BUTTON(x) x -#else - #define BUTTON(x) "[" x "]" -#endif - -#if defined(PCBHORUS) -#define TR_VTRAINERMODES TR_VTRAINER_MASTER_JACK TR_VTRAINER_SLAVE_JACK TR_VTRAINER_MASTER_BATTERY -#elif defined(PCBTARANIS) -#define TR_VTRAINERMODES TR_VTRAINER_MASTER_JACK TR_VTRAINER_SLAVE_JACK TR_VTRAINER_MASTER_SBUS_MODULE TR_VTRAINER_MASTER_CPPM_MODULE TR_VTRAINER_MASTER_BATTERY -#elif defined(CPUARM) -#define TR_VTRAINERMODES TR_VTRAINER_MASTER_JACK TR_VTRAINER_SLAVE_JACK TR_VTRAINER_MASTER_CPPM_MODULE TR_VTRAINER_MASTER_BATTERY -#endif - -// The non-0-terminated-strings - -extern const pm_char STR_OPEN9X[]; - -#define OFS_OFFON 0 -#define OFS_MMMINV (OFS_OFFON + sizeof(TR_OFFON)) -#define OFS_NCHANNELS (OFS_MMMINV + sizeof(TR_MMMINV)) -#if defined(GRAPHICS) -#define OFS_VBEEPMODE (OFS_NCHANNELS + sizeof(TR_NCHANNELS)) -#else -#define OFS_VBEEPLEN (OFS_NCHANNELS + sizeof(TR_NCHANNELS)) -#define OFS_VBEEPMODE (OFS_VBEEPLEN + sizeof(TR_VBEEPLEN)) -#endif -#if defined(ROTARY_ENCODERS) -#define OFS_VRENAVIG (OFS_VBEEPMODE + sizeof(TR_VBEEPMODE)) -#define OFS_VRENCODERS (OFS_VRENAVIG + sizeof(TR_VRENAVIG)) -#define OFS_TRNMODE (OFS_VRENCODERS + sizeof(TR_VRENCODERS)) -#elif defined(ROTARY_ENCODER_NAVIGATION) -#define OFS_VRENCODERS (OFS_VBEEPMODE + sizeof(TR_VBEEPMODE)) -#define OFS_TRNMODE (OFS_VRENCODERS + sizeof(TR_VRENCODERS)) -#else -#define OFS_TRNMODE (OFS_VBEEPMODE + sizeof(TR_VBEEPMODE)) -#endif -#define OFS_TRNCHN (OFS_TRNMODE + sizeof(TR_TRNMODE)) -#if defined(PCBTARANIS) || defined(PCBHORUS) - #define OFS_UART3MODES (OFS_TRNCHN + sizeof(TR_TRNCHN)) - #define OFS_SWTYPES (OFS_UART3MODES + sizeof(TR_UART3MODES)) - #define OFS_POTTYPES (OFS_SWTYPES + sizeof(TR_SWTYPES)) - #define OFS_SLIDERTYPES (OFS_POTTYPES + sizeof(TR_POTTYPES)) - #define OFS_VTRIMINC (OFS_SLIDERTYPES + sizeof(TR_SLIDERTYPES)) -#else - #define OFS_VTRIMINC (OFS_TRNCHN + sizeof(TR_TRNCHN)) -#endif -#if defined(CPUARM) - #define OFS_VDISPLAYTRIMS (OFS_VTRIMINC + sizeof(TR_VTRIMINC)) - #define OFS_RETA123 (OFS_VDISPLAYTRIMS + sizeof(TR_VDISPLAYTRIMS)) -#else - #define OFS_RETA123 (OFS_VTRIMINC + sizeof(TR_VTRIMINC)) -#endif -#define OFS_VPROTOS (OFS_RETA123 + sizeof(TR_RETA123)) -#define OFS_POSNEG (OFS_VPROTOS + sizeof(TR_VPROTOS)) -#if defined(PCBSKY9X) && defined(REVX) - #define OFS_VOUTPUT_TYPE (OFS_POSNEG + sizeof(TR_POSNEG)) - #define OFS_VBLMODE (OFS_VOUTPUT_TYPE + sizeof(TR_VOUTPUT_TYPE)) -#else - #define OFS_VBLMODE (OFS_POSNEG + sizeof(TR_POSNEG)) -#endif -#define OFS_VCURVEFUNC (OFS_VBLMODE + sizeof(TR_VBLMODE)) -#define OFS_VMLTPX (OFS_VCURVEFUNC + sizeof(TR_VCURVEFUNC)) -#define OFS_VMLTPX2 (OFS_VMLTPX + sizeof(TR_VMLTPX)) -#define OFS_VMIXTRIMS (OFS_VMLTPX2 + sizeof(TR_VMLTPX2)) -#define OFS_VCSWFUNC (OFS_VMIXTRIMS + sizeof(TR_VMIXTRIMS)) -#define OFS_VFSWFUNC (OFS_VCSWFUNC + sizeof(TR_VCSWFUNC)) -#define OFS_VFSWRESET (OFS_VFSWFUNC + sizeof(TR_VFSWFUNC)) -#define OFS_FUNCSOUNDS (OFS_VFSWRESET + sizeof(TR_VFSWRESET)) -#define OFS_VTELEMCHNS (OFS_FUNCSOUNDS + sizeof(TR_FUNCSOUNDS)) -#if defined(TELEMETRY_FRSKY) || defined(CPUARM) - #if defined(CPUARM) - #define OFS_VTELEMUNIT (OFS_VTELEMCHNS) - #define OFS_VALARM (OFS_VTELEMUNIT + sizeof(TR_VTELEMUNIT)) - #else - #define OFS_VTELEMUNIT (OFS_VTELEMCHNS + sizeof(TR_VTELEMCHNS)) - #define OFS_VALARM (OFS_VTELEMUNIT + sizeof(TR_VTELEMUNIT)) - #endif - #define OFS_VALARMFN (OFS_VALARM + sizeof(TR_VALARM)) - #define OFS_VTELPROTO (OFS_VALARMFN + sizeof(TR_VALARMFN)) - #define OFS_GPSFORMAT (OFS_VTELPROTO + sizeof(TR_VTELPROTO)) - #define OFS_AMPSRC (OFS_GPSFORMAT + sizeof(TR_GPSFORMAT)) - #define OFS_VARIOSRC (OFS_AMPSRC + sizeof(TR_AMPSRC)) - #define OFS_VSCREEN (OFS_VARIOSRC + sizeof(TR_VARIOSRC)) - #define OFS_VTEMPLATES (OFS_VSCREEN + sizeof(TR_VTELEMSCREENTYPE)) -#else - #define OFS_VTEMPLATES (OFS_VTELEMCHNS + sizeof(TR_VTELEMCHNS)) -#endif -#if defined(TEMPLATES) - #define OFS_VSWASHTYPE (OFS_VTEMPLATES + sizeof(TR_VTEMPLATES)) -#else - #define OFS_VSWASHTYPE (OFS_VTEMPLATES) -#endif -#if defined(HELI) - #define OFS_VKEYS (OFS_VSWASHTYPE + sizeof(TR_VSWASHTYPE)) -#else - #define OFS_VKEYS (OFS_VSWASHTYPE) -#endif -#define OFS_VSWITCHES (OFS_VKEYS + sizeof(TR_VKEYS)) -#define OFS_VSRCRAW (OFS_VSWITCHES + sizeof(TR_VSWITCHES)) -#if defined(TRANSLATIONS_CZ) && defined(CPUARM) - #define OFS_INPUTNAMES (OFS_VSRCRAW + sizeof(TR_VSRCRAW)) - #define OFS_VTMRMODES (OFS_INPUTNAMES + sizeof(TR_INPUTNAMES)) -#else - #define OFS_VTMRMODES (OFS_VSRCRAW + sizeof(TR_VSRCRAW)) -#endif -#define OFS_DATETIME (OFS_VTMRMODES + sizeof(TR_VTMRMODES)) -#if defined(CPUM2560) || defined(CPUARM) - #define OFS_VPERSISTENT (OFS_DATETIME + sizeof(TR_DATETIME)) - #define OFS_VLCD (OFS_VPERSISTENT + sizeof(TR_VPERSISTENT)) -#else - #define OFS_VLCD (OFS_DATETIME) -#endif -#if defined(CPUARM) - #define OFS_VUNITSSYSTEM (OFS_VLCD + sizeof(TR_VLCD)) - #define OFS_VBEEPCOUNTDOWN (OFS_VUNITSSYSTEM + sizeof(TR_VUNITSSYSTEM)) - #define OFS_VVARIOCENTER (OFS_VBEEPCOUNTDOWN + sizeof(TR_VBEEPCOUNTDOWN)) - #define OFS_COUNTRYCODES (OFS_VVARIOCENTER + sizeof(TR_VVARIOCENTER)) -#else - #define OFS_COUNTRYCODES (OFS_VLCD) -#endif -#if defined(PXX) || defined(CPUARM) - #define OFS_VFAILSAFE (OFS_COUNTRYCODES + sizeof(TR_COUNTRYCODES)) - #define OFS_VTRAINERMODES (OFS_VFAILSAFE + sizeof(TR_VFAILSAFE)) -#else - #define OFS_VFAILSAFE (OFS_COUNTRYCODES) - #define OFS_VTRAINERMODES (OFS_VFAILSAFE) -#endif -#if defined(CPUARM) - #define OFS_TARANIS_PROTOCOLS (OFS_VTRAINERMODES + sizeof(TR_VTRAINERMODES)) - #define OFS_TELEMETRY_PROTOCOLS (OFS_TARANIS_PROTOCOLS + sizeof(TR_TARANIS_PROTOCOLS)) - #define OFS_XJT_PROTOCOLS (OFS_TELEMETRY_PROTOCOLS + sizeof(TR_TELEMETRY_PROTOCOLS)) - #define OFS_DSM_PROTOCOLS (OFS_XJT_PROTOCOLS + sizeof(TR_XJT_PROTOCOLS)) -#if defined(MULTIMODULE) - #define OFS_MULTI_PROTOCOLS (OFS_DSM_PROTOCOLS + sizeof(TR_DSM_PROTOCOLS)) +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _TRANSLATIONS_H_ +#define _TRANSLATIONS_H_ + +#if defined(TRANSLATIONS_FR) +#include "translations/fr.h" +#define LEN_SPECIAL_CHARS 3 +#elif defined(TRANSLATIONS_IT) +#include "translations/it.h" +#define LEN_SPECIAL_CHARS 1 +#elif defined(TRANSLATIONS_SE) +#include "translations/se.h" +#define LEN_SPECIAL_CHARS 6 +#elif defined(TRANSLATIONS_FI) +#include "translations/fi.h" +#define LEN_SPECIAL_CHARS 6 +#elif defined(TRANSLATIONS_DE) +#include "translations/de.h" +#define LEN_SPECIAL_CHARS 6 +#elif defined(TRANSLATIONS_CZ) +#include "translations/cz.h" +#define LEN_SPECIAL_CHARS 17 +#elif defined(TRANSLATIONS_ES) +#include "translations/es.h" +#define LEN_SPECIAL_CHARS 0 +#elif defined(TRANSLATIONS_PL) +#include "translations/pl.h" +#define LEN_SPECIAL_CHARS 0 +#elif defined(TRANSLATIONS_PT) +#include "translations/pt.h" +#define LEN_SPECIAL_CHARS 0 +#elif defined(TRANSLATIONS_NL) +#include "translations/nl.h" +#define LEN_SPECIAL_CHARS 0 +#else +#include "translations/en.h" +#define LEN_SPECIAL_CHARS 0 +#endif + +#define PSIZE(x) ( sizeof(x) - 1 ) +#define EOFS(x) ( OFS_##x + sizeof(TR_##x) ) + +#if defined(PCBTARANIS) +#define HINT(s) " " s " " +#else +#define HINT(s) s +#endif + +#if LCD_W >= 480 + #define TR3(x, y, z) z + #define TR2(x, y) y +#elif LCD_W >= 212 + #define TR3(x, y, z) y + #define TR2(x, y) y +#else + #define TR3(x, y, z) x + #define TR2(x, y) x +#endif + +#define TR(x, y) TR2(x, y) // for compatibility + +#if defined(COLORLCD) + #define BUTTON(x) x +#else + #define BUTTON(x) "[" x "]" +#endif + +#if defined(PCBHORUS) +#define TR_VTRAINERMODES TR_VTRAINER_MASTER_JACK TR_VTRAINER_SLAVE_JACK TR_VTRAINER_MASTER_BATTERY +#elif defined(PCBTARANIS) +#define TR_VTRAINERMODES TR_VTRAINER_MASTER_JACK TR_VTRAINER_SLAVE_JACK TR_VTRAINER_MASTER_SBUS_MODULE TR_VTRAINER_MASTER_CPPM_MODULE TR_VTRAINER_MASTER_BATTERY +#elif defined(CPUARM) +#define TR_VTRAINERMODES TR_VTRAINER_MASTER_JACK TR_VTRAINER_SLAVE_JACK TR_VTRAINER_MASTER_CPPM_MODULE TR_VTRAINER_MASTER_BATTERY +#endif + +// The non-0-terminated-strings + +extern const pm_char STR_OPEN9X[]; + +#define OFS_OFFON 0 +#define OFS_MMMINV (OFS_OFFON + sizeof(TR_OFFON)) +#define OFS_NCHANNELS (OFS_MMMINV + sizeof(TR_MMMINV)) +#if defined(GRAPHICS) +#define OFS_VBEEPMODE (OFS_NCHANNELS + sizeof(TR_NCHANNELS)) +#else +#define OFS_VBEEPLEN (OFS_NCHANNELS + sizeof(TR_NCHANNELS)) +#define OFS_VBEEPMODE (OFS_VBEEPLEN + sizeof(TR_VBEEPLEN)) +#endif +#if defined(ROTARY_ENCODERS) +#define OFS_VRENAVIG (OFS_VBEEPMODE + sizeof(TR_VBEEPMODE)) +#define OFS_VRENCODERS (OFS_VRENAVIG + sizeof(TR_VRENAVIG)) +#define OFS_TRNMODE (OFS_VRENCODERS + sizeof(TR_VRENCODERS)) +#elif defined(ROTARY_ENCODER_NAVIGATION) +#define OFS_VRENCODERS (OFS_VBEEPMODE + sizeof(TR_VBEEPMODE)) +#define OFS_TRNMODE (OFS_VRENCODERS + sizeof(TR_VRENCODERS)) +#else +#define OFS_TRNMODE (OFS_VBEEPMODE + sizeof(TR_VBEEPMODE)) +#endif +#define OFS_TRNCHN (OFS_TRNMODE + sizeof(TR_TRNMODE)) +#if defined(PCBTARANIS) || defined(PCBHORUS) + #define OFS_UART3MODES (OFS_TRNCHN + sizeof(TR_TRNCHN)) + #define OFS_SWTYPES (OFS_UART3MODES + sizeof(TR_UART3MODES)) + #define OFS_POTTYPES (OFS_SWTYPES + sizeof(TR_SWTYPES)) + #define OFS_SLIDERTYPES (OFS_POTTYPES + sizeof(TR_POTTYPES)) + #define OFS_VTRIMINC (OFS_SLIDERTYPES + sizeof(TR_SLIDERTYPES)) +#else + #define OFS_VTRIMINC (OFS_TRNCHN + sizeof(TR_TRNCHN)) +#endif +#if defined(CPUARM) + #define OFS_VDISPLAYTRIMS (OFS_VTRIMINC + sizeof(TR_VTRIMINC)) + #define OFS_RETA123 (OFS_VDISPLAYTRIMS + sizeof(TR_VDISPLAYTRIMS)) +#else + #define OFS_RETA123 (OFS_VTRIMINC + sizeof(TR_VTRIMINC)) +#endif +#define OFS_VPROTOS (OFS_RETA123 + sizeof(TR_RETA123)) +#define OFS_POSNEG (OFS_VPROTOS + sizeof(TR_VPROTOS)) +#if defined(PCBSKY9X) && defined(REVX) + #define OFS_VOUTPUT_TYPE (OFS_POSNEG + sizeof(TR_POSNEG)) + #define OFS_VBLMODE (OFS_VOUTPUT_TYPE + sizeof(TR_VOUTPUT_TYPE)) +#else + #define OFS_VBLMODE (OFS_POSNEG + sizeof(TR_POSNEG)) +#endif +#define OFS_VCURVEFUNC (OFS_VBLMODE + sizeof(TR_VBLMODE)) +#define OFS_VMLTPX (OFS_VCURVEFUNC + sizeof(TR_VCURVEFUNC)) +#define OFS_VMLTPX2 (OFS_VMLTPX + sizeof(TR_VMLTPX)) +#define OFS_VMIXTRIMS (OFS_VMLTPX2 + sizeof(TR_VMLTPX2)) +#define OFS_VCSWFUNC (OFS_VMIXTRIMS + sizeof(TR_VMIXTRIMS)) +#define OFS_VFSWFUNC (OFS_VCSWFUNC + sizeof(TR_VCSWFUNC)) +#define OFS_VFSWRESET (OFS_VFSWFUNC + sizeof(TR_VFSWFUNC)) +#define OFS_FUNCSOUNDS (OFS_VFSWRESET + sizeof(TR_VFSWRESET)) +#define OFS_VTELEMCHNS (OFS_FUNCSOUNDS + sizeof(TR_FUNCSOUNDS)) +#if defined(TELEMETRY_FRSKY) || defined(CPUARM) + #if defined(CPUARM) + #define OFS_VTELEMUNIT (OFS_VTELEMCHNS) + #define OFS_VALARM (OFS_VTELEMUNIT + sizeof(TR_VTELEMUNIT)) + #else + #define OFS_VTELEMUNIT (OFS_VTELEMCHNS + sizeof(TR_VTELEMCHNS)) + #define OFS_VALARM (OFS_VTELEMUNIT + sizeof(TR_VTELEMUNIT)) + #endif + #define OFS_VALARMFN (OFS_VALARM + sizeof(TR_VALARM)) + #define OFS_VTELPROTO (OFS_VALARMFN + sizeof(TR_VALARMFN)) + #define OFS_GPSFORMAT (OFS_VTELPROTO + sizeof(TR_VTELPROTO)) + #define OFS_AMPSRC (OFS_GPSFORMAT + sizeof(TR_GPSFORMAT)) + #define OFS_VARIOSRC (OFS_AMPSRC + sizeof(TR_AMPSRC)) + #define OFS_VSCREEN (OFS_VARIOSRC + sizeof(TR_VARIOSRC)) + #define OFS_VTEMPLATES (OFS_VSCREEN + sizeof(TR_VTELEMSCREENTYPE)) +#else + #define OFS_VTEMPLATES (OFS_VTELEMCHNS + sizeof(TR_VTELEMCHNS)) +#endif +#if defined(TEMPLATES) + #define OFS_VSWASHTYPE (OFS_VTEMPLATES + sizeof(TR_VTEMPLATES)) +#else + #define OFS_VSWASHTYPE (OFS_VTEMPLATES) +#endif +#if defined(HELI) + #define OFS_VKEYS (OFS_VSWASHTYPE + sizeof(TR_VSWASHTYPE)) +#else + #define OFS_VKEYS (OFS_VSWASHTYPE) +#endif +#define OFS_VSWITCHES (OFS_VKEYS + sizeof(TR_VKEYS)) +#define OFS_VSRCRAW (OFS_VSWITCHES + sizeof(TR_VSWITCHES)) +#if defined(TRANSLATIONS_CZ) && defined(CPUARM) + #define OFS_INPUTNAMES (OFS_VSRCRAW + sizeof(TR_VSRCRAW)) + #define OFS_VTMRMODES (OFS_INPUTNAMES + sizeof(TR_INPUTNAMES)) +#else + #define OFS_VTMRMODES (OFS_VSRCRAW + sizeof(TR_VSRCRAW)) +#endif +#define OFS_DATETIME (OFS_VTMRMODES + sizeof(TR_VTMRMODES)) +#if defined(CPUM2560) || defined(CPUARM) + #define OFS_VPERSISTENT (OFS_DATETIME + sizeof(TR_DATETIME)) + #define OFS_VLCD (OFS_VPERSISTENT + sizeof(TR_VPERSISTENT)) +#else + #define OFS_VLCD (OFS_DATETIME) +#endif +#if defined(CPUARM) + #define OFS_VUNITSSYSTEM (OFS_VLCD + sizeof(TR_VLCD)) + #define OFS_VBEEPCOUNTDOWN (OFS_VUNITSSYSTEM + sizeof(TR_VUNITSSYSTEM)) + #define OFS_VVARIOCENTER (OFS_VBEEPCOUNTDOWN + sizeof(TR_VBEEPCOUNTDOWN)) + #define OFS_COUNTRYCODES (OFS_VVARIOCENTER + sizeof(TR_VVARIOCENTER)) +#else + #define OFS_COUNTRYCODES (OFS_VLCD) +#endif +#if defined(PXX) || defined(CPUARM) + #define OFS_VFAILSAFE (OFS_COUNTRYCODES + sizeof(TR_COUNTRYCODES)) + #define OFS_VTRAINERMODES (OFS_VFAILSAFE + sizeof(TR_VFAILSAFE)) +#else + #define OFS_VFAILSAFE (OFS_COUNTRYCODES) + #define OFS_VTRAINERMODES (OFS_VFAILSAFE) +#endif +#if defined(CPUARM) + #define OFS_TARANIS_PROTOCOLS (OFS_VTRAINERMODES + sizeof(TR_VTRAINERMODES)) + #define OFS_TELEMETRY_PROTOCOLS (OFS_TARANIS_PROTOCOLS + sizeof(TR_TARANIS_PROTOCOLS)) + #define OFS_XJT_PROTOCOLS (OFS_TELEMETRY_PROTOCOLS + sizeof(TR_TELEMETRY_PROTOCOLS)) + #define OFS_DSM_PROTOCOLS (OFS_XJT_PROTOCOLS + sizeof(TR_XJT_PROTOCOLS)) +#if defined(MULTIMODULE) + #define OFS_MULTI_PROTOCOLS (OFS_DSM_PROTOCOLS + sizeof(TR_DSM_PROTOCOLS)) #define OFS_VOLTSRC (OFS_MULTI_PROTOCOLS + sizeof(TR_MULTI_PROTOCOLS)) -#else - #define OFS_VOLTSRC (OFS_DSM_PROTOCOLS + sizeof(TR_DSM_PROTOCOLS)) -#endif - #define OFS_CURVE_TYPES (OFS_VOLTSRC + sizeof(TR_VOLTSRC)) - #define OFS_VSENSORTYPES (OFS_CURVE_TYPES + sizeof(TR_CURVE_TYPES)) - #define OFS_VFORMULAS (OFS_VSENSORTYPES + sizeof(TR_VSENSORTYPES)) - #define OFS_VPREC (OFS_VFORMULAS + sizeof(TR_VFORMULAS)) - #define OFS_VCELLINDEX (OFS_VPREC + sizeof(TR_VPREC)) - #define OFS_VANTENNATYPES (OFS_VCELLINDEX + sizeof(TR_VCELLINDEX)) - #define OFS_MAVLINK_BAUDS (OFS_VANTENNATYPES + sizeof(TR_VANTENNATYPES)) -#else - #define OFS_MAVLINK_BAUDS (OFS_VTRAINERMODES) -#endif -#if defined(TELEMETRY_MAVLINK) - #define OFS_MAVLINK_AC_MODES (OFS_MAVLINK_BAUDS + sizeof(TR_MAVLINK_BAUDS)) - #define OFS_MAVLINK_AP_MODES (OFS_MAVLINK_AC_MODES + sizeof(TR_MAVLINK_AC_MODES)) - #define OFS_SPARE (OFS_MAVLINK_AP_MODES + sizeof(TR_MAVLINK_AP_MODES)) -#else - #define OFS_SPARE (OFS_MAVLINK_BAUDS) -#endif - -#define STR_OFFON (STR_OPEN9X + OFS_OFFON) -#define STR_MMMINV (STR_OPEN9X + OFS_MMMINV) -#define STR_NCHANNELS (STR_OPEN9X + OFS_NCHANNELS) -#if !defined(GRAPHICS) -#define STR_VBEEPLEN (STR_OPEN9X + OFS_VBEEPLEN) -#endif -#define STR_VBEEPMODE (STR_OPEN9X + OFS_VBEEPMODE) -#define STR_TRNMODE (STR_OPEN9X + OFS_TRNMODE) -#define STR_TRNCHN (STR_OPEN9X + OFS_TRNCHN) -#define STR_UART3MODES (STR_OPEN9X + OFS_UART3MODES) -#define STR_SWTYPES (STR_OPEN9X + OFS_SWTYPES) -#define STR_POTTYPES (STR_OPEN9X + OFS_POTTYPES) -#define STR_SLIDERTYPES (STR_OPEN9X + OFS_SLIDERTYPES) -#define STR_VTRIMINC (STR_OPEN9X + OFS_VTRIMINC) -#define STR_VDISPLAYTRIMS (STR_OPEN9X + OFS_VDISPLAYTRIMS) -#define STR_RETA123 (STR_OPEN9X + OFS_RETA123) -#define STR_VPROTOS (STR_OPEN9X + OFS_VPROTOS) -#define STR_POSNEG (STR_OPEN9X + OFS_POSNEG) -#if defined(PCBSKY9X) && defined(REVX) - #define STR_VOUTPUT_TYPE (STR_OPEN9X + OFS_VOUTPUT_TYPE) -#endif -#define STR_VBLMODE (STR_OPEN9X + OFS_VBLMODE) -#define STR_VCURVEFUNC (STR_OPEN9X + OFS_VCURVEFUNC) -#define STR_VSIDE STR_VCURVEFUNC -#define LEN_VSIDE LEN_VCURVEFUNC -#define STR_VMLTPX (STR_OPEN9X + OFS_VMLTPX) -#define STR_VMLTPX2 (STR_OPEN9X + OFS_VMLTPX2) -#define STR_VMIXTRIMS (STR_OPEN9X + OFS_VMIXTRIMS) -#define STR_VCSWFUNC (STR_OPEN9X + OFS_VCSWFUNC) -#define STR_VFSWFUNC (STR_OPEN9X + OFS_VFSWFUNC) -#define STR_VFSWRESET (STR_OPEN9X + OFS_VFSWRESET) -#define STR_FUNCSOUNDS (STR_OPEN9X + OFS_FUNCSOUNDS) -#define STR_VTELEMCHNS (STR_OPEN9X + OFS_VTELEMCHNS) - -#if defined(TELEMETRY_FRSKY) || defined(CPUARM) - #if defined(CPUARM) - #define STR_VTELEMUNIT (STR_OPEN9X + OFS_VTELEMUNIT) - #define STR_VOLTSRC (STR_OPEN9X + OFS_VOLTSRC) - #else - #define STR_VTELEMUNIT (STR_OPEN9X + OFS_VTELEMUNIT) - #endif -#define STR_VALARM (STR_OPEN9X + OFS_VALARM) -#define STR_VALARMFN (STR_OPEN9X + OFS_VALARMFN) -#define STR_VTELPROTO (STR_OPEN9X + OFS_VTELPROTO) -#define STR_GPSFORMAT (STR_OPEN9X + OFS_GPSFORMAT) -#define STR_AMPSRC (STR_OPEN9X + OFS_AMPSRC) -#define STR_VARIOSRC (STR_OPEN9X + OFS_VARIOSRC) -#define STR_VTELEMSCREENTYPE (STR_OPEN9X + OFS_VSCREEN) -#define STR_TELEMCHNS (STR_OPEN9X + OFS_TELEMCHNS) -#endif - -#if defined(TEMPLATES) - #define STR_VTEMPLATES (STR_OPEN9X + OFS_VTEMPLATES) -#endif - -#if defined(HELI) - #define STR_VSWASHTYPE (STR_OPEN9X + OFS_VSWASHTYPE) -#endif - -#define STR_VKEYS (STR_OPEN9X + OFS_VKEYS) -#define STR_VSWITCHES (STR_OPEN9X + OFS_VSWITCHES) -#define STR_VSRCRAW (STR_OPEN9X + OFS_VSRCRAW) -#if defined(TRANSLATIONS_CZ) && defined(CPUARM) -#define STR_INPUTNAMES (STR_OPEN9X + OFS_INPUTNAMES) -#endif -#define STR_VTMRMODES (STR_OPEN9X + OFS_VTMRMODES) - -#if defined(ROTARY_ENCODERS) - #define STR_VRENAVIG (STR_OPEN9X + OFS_VRENAVIG) -#endif - -#if defined(ROTARY_ENCODER_NAVIGATION) - #define STR_VRENCODERS (STR_OPEN9X + OFS_VRENCODERS) -#endif - -#if defined(CPUM2560) || defined(CPUARM) - #define STR_DATETIME (STR_OPEN9X + OFS_DATETIME) - #define STR_VPERSISTENT (STR_OPEN9X + OFS_VPERSISTENT) -#endif - -#if defined(CPUARM) - #define STR_VLCD (STR_OPEN9X + OFS_VLCD) - #define STR_VUNITSSYSTEM (STR_OPEN9X + OFS_VUNITSSYSTEM) - #define STR_VBEEPCOUNTDOWN (STR_OPEN9X + OFS_VBEEPCOUNTDOWN) - #define STR_VVARIOCENTER (STR_OPEN9X + OFS_VVARIOCENTER) -#endif - -#if defined(PXX) || defined(CPUARM) - #define STR_COUNTRYCODES (STR_OPEN9X + OFS_COUNTRYCODES) - #define STR_VFAILSAFE (STR_OPEN9X + OFS_VFAILSAFE) -#endif - -#if defined(CPUARM) - #define STR_VTRAINERMODES (STR_OPEN9X + OFS_VTRAINERMODES) - #define STR_TARANIS_PROTOCOLS (STR_OPEN9X + OFS_TARANIS_PROTOCOLS) - #define STR_TELEMETRY_PROTOCOLS (STR_OPEN9X + OFS_TELEMETRY_PROTOCOLS) - #define STR_XJT_PROTOCOLS (STR_OPEN9X + OFS_XJT_PROTOCOLS) - #define STR_DSM_PROTOCOLS (STR_OPEN9X + OFS_DSM_PROTOCOLS) -#if defined(MULTIMODULE) - #define STR_MULTI_PROTOCOLS (STR_OPEN9X + OFS_MULTI_PROTOCOLS) -#endif - #define STR_CURVE_TYPES (STR_OPEN9X + OFS_CURVE_TYPES) - #define STR_VSENSORTYPES (STR_OPEN9X + OFS_VSENSORTYPES) - #define STR_VFORMULAS (STR_OPEN9X + OFS_VFORMULAS) - #define STR_VPREC (STR_OPEN9X + OFS_VPREC) - #define STR_VCELLINDEX (STR_OPEN9X + OFS_VCELLINDEX) - #define STR_VANTENNATYPES (STR_OPEN9X + OFS_VANTENNATYPES) -#endif - -#if defined(TELEMETRY_MAVLINK) - #define STR_MAVLINK_BAUDS (STR_OPEN9X + OFS_MAVLINK_BAUDS) - #define STR_MAVLINK_AC_MODES (STR_OPEN9X + OFS_MAVLINK_AC_MODES) - #define STR_MAVLINK_AP_MODES (STR_OPEN9X + OFS_MAVLINK_AP_MODES) -#endif - -// The 0-terminated-strings -#define NO_INDENT(x) (x)+LEN_INDENT - -extern const pm_char STR_POPUPS[]; - -#if defined(OFS_EXIT) - #define STR_EXIT (STR_POPUPS + OFS_EXIT) -#else - extern const pm_char STR_EXIT[]; -#endif - -#if !defined(PCBHORUS) - extern const pm_char STR_MENUWHENDONE[]; -#endif - -extern const pm_char STR_FREE[]; -#define LEN_FREE PSIZE(TR_FREE) -extern const pm_char STR_DELETEMODEL[]; -extern const pm_char STR_COPYINGMODEL[]; -extern const pm_char STR_MOVINGMODEL[]; -extern const pm_char STR_LOADINGMODEL[]; -extern const pm_char STR_NAME[]; -extern const pm_char STR_BITMAP[]; -extern const pm_char STR_TIMER[]; -extern const pm_char STR_ELIMITS[]; -extern const pm_char STR_ETRIMS[]; -extern const pm_char STR_TRIMINC[]; -extern const pm_char STR_DISPLAY_TRIMS[]; -extern const pm_char STR_TTRACE[]; -extern const pm_char STR_TTRIM[]; -extern const pm_char STR_BEEPCTR[]; -extern const pm_char STR_USE_GLOBAL_FUNCS[]; -#if defined(PCBSKY9X) && defined(REVX) - extern const pm_char STR_OUTPUT_TYPE[]; -#endif -extern const pm_char STR_PROTO[]; -extern const pm_char STR_PPMFRAME[]; -extern const pm_char STR_MS[]; -extern const pm_char STR_SWITCH[]; -extern const pm_char STR_TRIMS[]; -extern const pm_char STR_FADEIN[]; -extern const pm_char STR_FADEOUT[]; -extern const pm_char STR_DEFAULT[]; -extern const pm_char STR_CHECKTRIMS[]; -extern const pm_char STR_SWASHTYPE[]; -extern const pm_char STR_COLLECTIVE[]; -extern const pm_char STR_AILERON[]; -extern const pm_char STR_ELEVATOR[]; -extern const pm_char STR_SWASHRING[]; -extern const pm_char STR_ELEDIRECTION[]; -extern const pm_char STR_AILDIRECTION[]; -extern const pm_char STR_COLDIRECTION[]; -extern const pm_char STR_MODE[]; -#if defined(AUDIO) && defined(BUZZER) -extern const pm_char STR_SPEAKER[]; -extern const pm_char STR_BUZZER[]; -#else -#define STR_SPEAKER STR_MODE -#define STR_BUZZER STR_MODE -#endif -extern const pm_char STR_NOFREEEXPO[]; -extern const pm_char STR_NOFREEMIXER[]; -extern const pm_char STR_SOURCE[]; -extern const pm_char STR_WEIGHT[]; -extern const pm_char STR_EXPO[]; -extern const pm_char STR_SIDE[]; -extern const pm_char STR_DIFFERENTIAL[]; -extern const pm_char STR_OFFSET[]; -extern const pm_char STR_TRIM[]; -extern const pm_char STR_DREX[]; -extern const pm_char STR_CURVE[]; -extern const pm_char STR_FLMODE[]; -extern const pm_char STR_MIXWARNING[]; -extern const pm_char STR_OFF[]; -extern const pm_char STR_MULTPX[]; -extern const pm_char STR_DELAYDOWN[]; -extern const pm_char STR_DELAYUP[]; -extern const pm_char STR_SLOWDOWN[]; -extern const pm_char STR_SLOWUP[]; -extern const pm_char STR_MIXER[]; -extern const pm_char STR_CV[]; -extern const pm_char STR_GV[]; -extern const pm_char STR_ACHANNEL[]; -extern const pm_char STR_RANGE[]; -extern const pm_char STR_CENTER[]; -extern const pm_char STR_BAR[]; -extern const pm_char STR_ALARM[]; -extern const pm_char STR_USRDATA[]; -extern const pm_char STR_BLADES[]; -extern const pm_char STR_SCREEN[]; -extern const pm_char STR_SOUND_LABEL[]; -extern const pm_char STR_LENGTH[]; -extern const pm_char STR_BEEP_LENGTH[]; -#if defined(CPUARM) -extern const pm_char STR_BEEP_LENGTH[]; -#else -#define STR_BEEP_LENGTH STR_LENGTH -#endif -extern const pm_char STR_SPKRPITCH[]; -extern const pm_char STR_HAPTIC_LABEL[]; -extern const pm_char STR_HAPTICSTRENGTH[]; -extern const pm_char STR_CONTRAST[]; -extern const pm_char STR_ALARMS_LABEL[]; -#if defined(BATTGRAPH) || defined(CPUARM) -extern const pm_char STR_BATTERY_RANGE[]; -#endif -extern const pm_char STR_BATTERYWARNING[]; -extern const pm_char STR_INACTIVITYALARM[]; -extern const pm_char STR_MEMORYWARNING[]; -extern const pm_char STR_ALARMWARNING[]; -extern const pm_char STR_RENAVIG[]; -extern const pm_char STR_THROTTLEREVERSE[]; -extern const pm_char STR_TIMER_NAME[]; -extern const pm_char STR_MINUTEBEEP[]; -extern const pm_char STR_BEEPCOUNTDOWN[]; -extern const pm_char STR_PERSISTENT[]; -extern const pm_char STR_BACKLIGHT_LABEL[]; -extern const pm_char STR_BLDELAY[]; -#if defined(PWM_BACKLIGHT) || defined(PCBHORUS) -extern const pm_char STR_BLONBRIGHTNESS[]; -extern const pm_char STR_BLOFFBRIGHTNESS[]; -#endif -extern const pm_char STR_SPLASHSCREEN[]; -extern const pm_char STR_THROTTLEWARNING[]; -extern const pm_char STR_SWITCHWARNING[]; -extern const pm_char STR_POTWARNINGSTATE[]; -extern const pm_char STR_POTWARNING[]; -extern const pm_char STR_SLIDERWARNING[]; -extern const pm_char STR_TIMEZONE[]; -extern const pm_char STR_ADJUST_RTC[]; -extern const pm_char STR_GPS[]; -extern const pm_char STR_GPSCOORD[]; -extern const pm_char STR_VARIO[]; -extern const pm_char STR_PITCH_AT_ZERO[]; -extern const pm_char STR_PITCH_AT_MAX[]; -extern const pm_char STR_REPEAT_AT_ZERO[]; -extern const pm_char STR_RXCHANNELORD[]; -extern const pm_char STR_STICKS[]; -extern const pm_char STR_POTS[]; -extern const pm_char STR_SWITCHES[]; -extern const pm_char STR_SWITCHES_DELAY[]; -extern const pm_char STR_SLAVE[]; -extern const pm_char STR_MODESRC[]; -extern const pm_char STR_MULTIPLIER[]; -#define LEN_MULTIPLIER PSIZE(TR_MULTIPLIER) -extern const pm_char STR_CAL[]; -extern const pm_char STR_VTRIM[]; -extern const pm_char STR_BG[]; -extern const pm_char STR_MENUTOSTART[]; -extern const pm_char STR_SETMIDPOINT[]; -extern const pm_char STR_MOVESTICKSPOTS[]; -extern const pm_char STR_RXBATT[]; -extern const pm_char STR_TX[]; -#define STR_RX (STR_TX+OFS_RX) -extern const pm_char STR_ACCEL[]; -extern const pm_char STR_NODATA[]; -extern const pm_char STR_TOTTM1TM2THRTHP[]; -extern const pm_char STR_TMR1LATMAXUS[]; -extern const pm_char STR_TMR1LATMINUS[]; -extern const pm_char STR_TMR1JITTERUS[]; -extern const pm_char STR_TMIXMAXMS[]; -extern const pm_char STR_FREESTACKMINB[]; -extern const pm_char STR_MENUTORESET[]; -extern const pm_char STR_PPM_TRAINER[]; -extern const pm_char STR_CH[]; -extern const pm_char STR_MODEL[]; -extern const pm_char STR_FP[]; -#if defined(CPUARM) -extern const pm_char STR_MIX[]; -#endif -extern const pm_char STR_EEPROMLOWMEM[]; -extern const pm_char STR_ALERT[]; -extern const pm_char STR_PRESSANYKEYTOSKIP[]; -extern const pm_char STR_THROTTLENOTIDLE[]; -extern const pm_char STR_ALARMSDISABLED[]; -extern const pm_char STR_PRESSANYKEY[]; -#define LEN_PRESSANYKEY PSIZE(TR_PRESSANYKEY) -extern const pm_char STR_BAD_RADIO_DATA[]; -extern const pm_char STR_STORAGE_FORMAT[]; -extern const pm_char STR_EEPROMOVERFLOW[]; -extern const pm_char STR_TRIMS2OFFSETS[]; -extern const pm_char STR_MENURADIOSETUP[]; -extern const pm_char STR_MENUDATEANDTIME[]; -extern const pm_char STR_MENUTRAINER[]; -extern const pm_char STR_MENUSPECIALFUNCS[]; -extern const pm_char STR_MENUVERSION[]; -extern const pm_char STR_MENU_RADIO_SWITCHES[]; -extern const pm_char STR_MENU_RADIO_ANALOGS[]; -extern const pm_char STR_MENUCALIBRATION[]; -extern const pm_char STR_MENUMODELSEL[]; -extern const pm_char STR_MENUSETUP[]; -extern const pm_char STR_MENUFLIGHTMODE[]; -extern const pm_char STR_MENUFLIGHTMODES[]; -extern const pm_char STR_MENUHELISETUP[]; -extern const pm_char STR_MENUINPUTS[]; -extern const pm_char STR_MENULIMITS[]; -extern const pm_char STR_MENUCURVES[]; -extern const pm_char STR_MENUCURVE[]; -extern const pm_char STR_MENULOGICALSWITCH[]; -extern const pm_char STR_MENULOGICALSWITCHES[]; -extern const pm_char STR_MENUCUSTOMFUNC[]; -extern const pm_char STR_MENUCUSTOMSCRIPTS[]; -extern const pm_char STR_MENUTELEMETRY[]; -extern const pm_char STR_MENUTEMPLATES[]; -extern const pm_char STR_MENUSTAT[]; -extern const pm_char STR_MENUDEBUG[]; -extern const char * const STR_MONITOR_CHANNELS[]; -extern const pm_char STR_MONITOR_SWITCHES[]; -extern const pm_char STR_MONITOR_OUTPUT_DESC[]; -extern const pm_char STR_MONITOR_MIXER_DESC[]; -extern const pm_char STR_MENUGLOBALVARS[]; -extern const pm_char STR_INVERT_THR[]; -extern const pm_char STR_AND_SWITCH[]; -extern const pm_char STR_SF[]; -extern const pm_char STR_GF[]; - -#if defined(FAS_OFFSET) || !defined(CPUM64) -extern const pm_char STR_FAS_OFFSET[]; -#endif - -#if defined(MULTIMODULE) -extern const pm_char STR_MULTI_CUSTOM[]; -extern const pm_char STR_MULTI_OPTION[]; -extern const pm_char STR_MULTI_VIDFREQ[]; -extern const pm_char STR_MULTI_RFPOWER[]; -extern const pm_char STR_MULTI_RFTUNE[]; -extern const pm_char STR_MULTI_TELEMETRY[]; -extern const pm_char STR_MULTI_AUTOBIND[]; -extern const pm_char STR_MULTI_DSM_AUTODTECT[]; -extern const pm_char STR_MULTI_LOWPOWER[]; -extern const pm_char STR_DISABLE_INTERNAL[]; -extern const pm_char STR_MODULE_NO_SERIAL_MODE[]; -extern const pm_char STR_MODULE_NO_INPUT[]; -extern const pm_char STR_MODULE_NO_TELEMETRY[]; -extern const pm_char STR_MODULE_BINDING[]; -extern const pm_char STR_PROTOCOL_INVALID[]; -extern const pm_char STR_MODULE_STATUS[]; -extern const pm_char STR_MULTI_SERVOFREQ[]; -#if LCD_W < 212 -extern const pm_char STR_SUBTYPE[]; -#endif -#endif -#if defined(DSM2) || defined(PXX) -extern const pm_char STR_RECEIVER_NUM[]; -extern const pm_char STR_RECEIVER[]; -#endif - -#if defined(PXX) || defined(CPUARM) -extern const pm_char STR_SYNCMENU[]; -extern const pm_char STR_INTERNALRF[]; -extern const pm_char STR_EXTERNALRF[]; -extern const pm_char STR_FAILSAFE[]; -extern const pm_char STR_FAILSAFESET[]; -extern const pm_char STR_HOLD[]; -extern const pm_char STR_NONE[]; -extern const pm_char STR_MENUSENSOR[]; -extern const pm_char STR_SENSOR[]; -extern const pm_char STR_COUNTRYCODE[]; -#endif - -#if defined(TELEMETRY_FRSKY) -extern const pm_char STR_LIMIT[]; -#endif - -#ifdef FRSKY_HUB -extern const pm_char STR_MINRSSI[]; -extern const pm_char STR_LATITUDE[]; -extern const pm_char STR_LONGITUDE[]; -#endif - -#if defined(CPUARM) || defined(CPUM2560) -extern const pm_char STR_SHUTDOWN[]; -extern const pm_char STR_SAVEMODEL[]; -#endif - -#if defined(PCBX9E) -extern const pm_char STR_POWEROFF[]; -#endif - -extern const pm_char STR_BATT_CALIB[]; - -#if defined(CPUARM) || defined(TELEMETRY_FRSKY) -extern const pm_char STR_VOLTAGE[]; -extern const pm_char STR_CURRENT[]; -#endif - -#if defined(CPUARM) -extern const pm_char STR_CURRENT_CALIB[]; -extern const pm_char STR_UNITSSYSTEM[]; -extern const pm_char STR_VOICELANG[]; -extern const pm_char STR_MODELIDUSED[]; -extern const pm_char STR_BEEP_VOLUME[]; -extern const pm_char STR_WAV_VOLUME[]; -extern const pm_char STR_BG_VOLUME[]; -extern const pm_char STR_PERSISTENT_MAH[]; -#endif - -#if defined(PCBSKY9X) -#define LEN_CALIB_FIELDS (PSIZE(TR_BATT_CALIB) > PSIZE(TR_CURRENT_CALIB) ? PSIZE(TR_BATT_CALIB) : PSIZE(TR_CURRENT_CALIB)) -#else -#define LEN_CALIB_FIELDS PSIZE(TR_BATT_CALIB) -#endif - -#if defined(NAVIGATION_MENUS) - extern const pm_char STR_SELECT_MODEL[]; - extern const pm_char STR_CREATE_CATEGORY[]; - extern const pm_char STR_RENAME_CATEGORY[]; - extern const pm_char STR_DELETE_CATEGORY[]; - extern const pm_char STR_CREATE_MODEL[]; - extern const pm_char STR_DUPLICATE_MODEL[]; - extern const pm_char STR_COPY_MODEL[]; - extern const pm_char STR_MOVE_MODEL[]; - extern const pm_char STR_DELETE_MODEL[]; - extern const pm_char STR_EDIT[]; - extern const pm_char STR_INSERT_BEFORE[]; - extern const pm_char STR_INSERT_AFTER[]; - extern const pm_char STR_COPY[]; - extern const pm_char STR_MOVE[]; - extern const pm_char STR_PASTE[]; - extern const pm_char STR_INSERT[]; - extern const pm_char STR_DELETE[]; - extern const pm_char STR_RESET_FLIGHT[]; - extern const pm_char STR_RESET_TIMER1[]; - extern const pm_char STR_RESET_TIMER2[]; - extern const pm_char STR_RESET_TIMER3[]; - extern const pm_char STR_RESET_TELEMETRY[]; - extern const pm_char STR_STATISTICS[]; - extern const pm_char STR_ABOUT_US[]; - extern const pm_char STR_SETUP_SCREENS[]; - extern const pm_char STR_MONITOR_SCREENS[]; -#endif - -extern const pm_char STR_RESET_BTN[]; - -#if defined(SDCARD) - extern const pm_char STR_BACKUP_MODEL[]; - extern const pm_char STR_RESTORE_MODEL[]; - extern const pm_char STR_DELETE_ERROR[]; - extern const pm_char STR_SDCARD_ERROR[]; - extern const pm_char STR_NO_SDCARD[]; - extern const pm_char STR_SDCARD_FULL[]; - extern const pm_char STR_INCOMPATIBLE[]; - extern const pm_char STR_LOGS_PATH[]; - extern const pm_char STR_LOGS_EXT[]; - extern const pm_char STR_MODELS_PATH[]; - extern const pm_char STR_MODELS_EXT[]; - #define STR_UPDATE_LIST STR_DELAYDOWN -#endif - -extern const pm_char STR_CAT_NOT_EMPTY[]; -extern const pm_char STR_WARNING[]; -extern const pm_char STR_STORAGE_WARNING[]; -extern const pm_char STR_EEPROM_CONVERTING[]; -extern const pm_char STR_THROTTLEWARN[]; -extern const pm_char STR_ALARMSWARN[]; -extern const pm_char STR_SWITCHWARN[]; -extern const pm_char STR_FAILSAFEWARN[]; -extern const pm_char STR_WRONG_SDCARDVERSION[]; -extern const pm_char STR_WRONG_PCBREV[]; -extern const pm_char STR_EMERGENCY_MODE[]; -extern const pm_char STR_PCBREV_ERROR[]; -extern const pm_char STR_NO_FAILSAFE[]; -extern const pm_char STR_KEYSTUCK[]; - -extern const pm_char STR_SPEAKER_VOLUME[]; -extern const pm_char STR_LCD[]; -extern const pm_char STR_BRIGHTNESS[]; -extern const pm_char STR_CPU_TEMP[]; -extern const pm_char STR_CPU_CURRENT[]; -extern const pm_char STR_CPU_MAH[]; -extern const pm_char STR_COPROC[]; -extern const pm_char STR_COPROC_TEMP[]; -extern const pm_char STR_CAPAWARNING[]; -extern const pm_char STR_TEMPWARNING[]; -extern const pm_char STR_FUNC[]; -extern const pm_char STR_V1[]; -extern const pm_char STR_V2[]; -extern const pm_char STR_DURATION[]; -extern const pm_char STR_DELAY[]; -extern const pm_char STR_SD_CARD[]; -extern const pm_char STR_SDHC_CARD[]; -extern const pm_char STR_NO_SOUNDS_ON_SD[]; -extern const pm_char STR_NO_MODELS_ON_SD[]; -extern const pm_char STR_NO_BITMAPS_ON_SD[]; -extern const pm_char STR_NO_SCRIPTS_ON_SD[]; -extern const pm_char STR_SCRIPT_SYNTAX_ERROR[]; -extern const pm_char STR_SCRIPT_PANIC[]; -extern const pm_char STR_SCRIPT_KILLED[]; -extern const pm_char STR_SCRIPT_ERROR[]; -extern const pm_char STR_PLAY_FILE[]; -extern const pm_char STR_ASSIGN_BITMAP[]; -extern const pm_char STR_EXECUTE_FILE[]; -extern const pm_char STR_DELETE_FILE[]; -extern const pm_char STR_COPY_FILE[]; -extern const pm_char STR_RENAME_FILE[]; -extern const pm_char STR_REMOVED[]; -extern const pm_char STR_SD_INFO[]; -extern const pm_char STR_SD_FORMAT[]; -extern const pm_char STR_NA[]; -extern const pm_char STR_HARDWARE[]; -extern const pm_char STR_FORMATTING[]; -extern const pm_char STR_TEMP_CALIB[]; -extern const pm_char STR_TIME[]; -extern const pm_char STR_BAUDRATE[]; -extern const pm_char STR_SD_INFO_TITLE[]; -extern const pm_char STR_SD_TYPE[]; -extern const pm_char STR_SD_SPEED[]; -extern const pm_char STR_SD_SECTORS[]; -extern const pm_char STR_SD_SIZE[]; -extern const pm_char STR_TYPE[]; -extern const pm_char STR_GLOBAL_VARS[]; -extern const pm_char STR_GVARS[]; -extern const pm_char STR_GLOBAL_VAR[]; -extern const pm_char STR_OWN[]; -extern const pm_char STR_ROTARY_ENCODER[]; -extern const pm_char STR_DATE[]; -extern const pm_char STR_CHANNELS_MONITOR[]; -extern const pm_char STR_MIXERS_MONITOR[]; -extern const pm_char STR_PATH_TOO_LONG[]; -extern const pm_char STR_VIEW_TEXT[]; -extern const pm_char STR_FLASH_BOOTLOADER[]; -extern const pm_char STR_FLASH_EXTERNAL_DEVICE[]; -extern const pm_char STR_FLASH_INTERNAL_MODULE[]; -extern const pm_char STR_FIRMWARE_UPDATE_ERROR[]; -extern const pm_char STR_WRITING[]; -extern const pm_char STR_CONFIRM_FORMAT[]; -extern const pm_char STR_EEBACKUP[]; -extern const pm_char STR_FACTORYRESET[]; -extern const pm_char STR_CONFIRMRESET[]; -extern const pm_char STR_TOO_MANY_LUA_SCRIPTS[]; -extern const pm_char STR_BLCOLOR[]; - -#if defined(CPUARM) && defined(VOICE) - struct LanguagePack { - const char * id; - const char * name; - void (*playNumber)(getvalue_t number, uint8_t unit, uint8_t flags, uint8_t id); - void (*playDuration)(int seconds, uint8_t flags, uint8_t id); - }; - - extern const LanguagePack * currentLanguagePack; - extern uint8_t currentLanguagePackIdx; - - extern const LanguagePack czLanguagePack; - extern const LanguagePack enLanguagePack; - extern const LanguagePack esLanguagePack; - extern const LanguagePack frLanguagePack; - extern const LanguagePack deLanguagePack; - extern const LanguagePack itLanguagePack; - extern const LanguagePack plLanguagePack; - extern const LanguagePack ptLanguagePack; - extern const LanguagePack skLanguagePack; - extern const LanguagePack seLanguagePack; - extern const LanguagePack huLanguagePack; - extern const LanguagePack * const languagePacks[]; - #if defined(LANGUAGE_PACKS_DEFINITION) - const LanguagePack * const languagePacks[] = { - // alphabetical order - &czLanguagePack, - &deLanguagePack, - &enLanguagePack, - &esLanguagePack, - &frLanguagePack, - &huLanguagePack, - &itLanguagePack, - &plLanguagePack, - &ptLanguagePack, - &seLanguagePack, - &skLanguagePack, - NULL - }; - #endif -#if defined(SIMU) - #define LANGUAGE_PACK_DECLARE(lng, name) const LanguagePack lng ## LanguagePack = { #lng, name, lng ## _ ## playNumber, lng ## _ ## playDuration } -#else - #define LANGUAGE_PACK_DECLARE(lng, name) extern const LanguagePack lng ## LanguagePack = { #lng, name, lng ## _ ## playNumber, lng ## _ ## playDuration } -#endif - #define LANGUAGE_PACK_DECLARE_DEFAULT(lng, name) LANGUAGE_PACK_DECLARE(lng, name); const LanguagePack * currentLanguagePack = & lng ## LanguagePack; uint8_t currentLanguagePackIdx - inline PLAY_FUNCTION(playNumber, getvalue_t number, uint8_t unit, uint8_t flags) { currentLanguagePack->playNumber(number, unit, flags, id); } - inline PLAY_FUNCTION(playDuration, int seconds, uint8_t flags) { currentLanguagePack->playDuration(seconds, flags, id); } -#elif defined(VOICE) - PLAY_FUNCTION(playNumber, getvalue_t number, uint8_t unit, uint8_t att); - PLAY_FUNCTION(playDuration, int seconds); - #define LANGUAGE_PACK_DECLARE(lng, name) - #define LANGUAGE_PACK_DECLARE_DEFAULT(lng, name) -#else - #define LANGUAGE_PACK_DECLARE(lng, name) - #define LANGUAGE_PACK_DECLARE_DEFAULT(lng, name) -#endif - -#if defined(CPUARM) - extern const pm_char STR_MODELNAME[]; - extern const pm_char STR_PHASENAME[]; - extern const pm_char STR_MIXNAME[]; - extern const pm_char STR_INPUTNAME[]; - extern const pm_char STR_EXPONAME[]; -#else - #define STR_MODELNAME STR_NAME - #define STR_PHASENAME STR_NAME - #define STR_MIXNAME STR_NAME - #define STR_EXPONAME STR_NAME -#endif - -#if defined(COLORLCD) - #define TR_PHASES_HEADERS { TR_PHASES_HEADERS_NAME, TR_PHASES_HEADERS_SW, TR_PHASES_HEADERS_RUD_TRIM, TR_PHASES_HEADERS_ELE_TRIM, TR_PHASES_HEADERS_THT_TRIM, TR_PHASES_HEADERS_AIL_TRIM, TR_PHASES_HEADERS_CH5_TRIM, TR_PHASES_HEADERS_CH6_TRIM, TR_PHASES_HEADERS_FAD_IN, TR_PHASES_HEADERS_FAD_OUT } -#elif defined(PCBTARANIS) - #define TR_PHASES_HEADERS { HINT(TR_PHASES_HEADERS_NAME), HINT(TR_PHASES_HEADERS_SW), HINT(TR_PHASES_HEADERS_RUD_TRIM), HINT(TR_PHASES_HEADERS_ELE_TRIM), HINT(TR_PHASES_HEADERS_THT_TRIM), HINT(TR_PHASES_HEADERS_AIL_TRIM), HINT(TR_PHASES_HEADERS_FAD_IN), HINT(TR_PHASES_HEADERS_FAD_OUT) } -#endif - -#define TR_LIMITS_HEADERS { HINT(TR_LIMITS_HEADERS_NAME), HINT(TR_LIMITS_HEADERS_SUBTRIM), HINT(TR_LIMITS_HEADERS_MIN), HINT(TR_LIMITS_HEADERS_MAX), HINT(TR_LIMITS_HEADERS_DIRECTION), HINT(TR_LIMITS_HEADERS_CURVE), HINT(TR_LIMITS_HEADERS_PPMCENTER), HINT(TR_LIMITS_HEADERS_SUBTRIMMODE) } -#define TR_LSW_HEADERS { HINT(TR_LSW_HEADERS_FUNCTION), HINT(TR_LSW_HEADERS_V1), HINT(TR_LSW_HEADERS_V2), HINT(TR_LSW_HEADERS_V2), HINT(TR_LSW_HEADERS_ANDSW), HINT(TR_LSW_HEADERS_DURATION), HINT(TR_LSW_HEADERS_DELAY) } -#define TR_GVAR_HEADERS { HINT(TR_GVAR_HEADERS_NAME), HINT(TR_GVAR_HEADERS_FM0), HINT(TR_GVAR_HEADERS_FM1), HINT(TR_GVAR_HEADERS_FM2), HINT(TR_GVAR_HEADERS_FM3), HINT(TR_GVAR_HEADERS_FM4), HINT(TR_GVAR_HEADERS_FM5), HINT(TR_GVAR_HEADERS_FM6), HINT(TR_GVAR_HEADERS_FM7), HINT(TR_GVAR_HEADERS_FM8) } - -#if LCD_W >= 212 - extern const char * const STR_PHASES_HEADERS[]; - extern const char * const STR_LIMITS_HEADERS[]; - extern const char * const STR_LSW_HEADERS[]; - extern const char * const STR_LSW_DESCRIPTIONS[]; - extern const char * const STR_GVAR_HEADERS[]; -#endif - -#if defined(CPUARM) - extern const pm_char STR_TRAINER[]; - extern const pm_char STR_MODULE_BIND[]; - extern const pm_char STR_BINDING_1_8_TELEM_ON[]; - extern const pm_char STR_BINDING_1_8_TELEM_OFF[]; - extern const pm_char STR_BINDING_9_16_TELEM_ON[]; - extern const pm_char STR_BINDING_9_16_TELEM_OFF[]; - extern const pm_char STR_CHANNELRANGE[]; - extern const pm_char STR_ANTENNASELECTION[]; - extern const pm_char STR_ANTENNACONFIRM1[]; - extern const pm_char STR_ANTENNACONFIRM2[]; - extern const pm_char STR_SET[]; - extern const pm_char STR_PREFLIGHT[]; - extern const pm_char STR_CHECKLIST[]; - extern const pm_char STR_VIEW_NOTES[]; - extern const pm_char STR_MODEL_SELECT[]; - extern const pm_char STR_RESET_SUBMENU[]; - extern const pm_char STR_LOWALARM[]; - extern const pm_char STR_CRITICALALARM[]; - extern const pm_char STR_TELEMETRY_TYPE[]; - extern const pm_char STR_TELEMETRY_SENSORS[]; - extern const pm_char STR_VALUE[]; - extern const pm_char STR_TOPLCDTIMER[]; - extern const pm_char STR_UNIT[] PROGMEM; - extern const pm_char STR_TELEMETRY_NEWSENSOR[]; - extern const pm_char STR_ID[]; - extern const pm_char STR_PRECISION[]; - extern const pm_char STR_RATIO[]; - extern const pm_char STR_FORMULA[]; - extern const pm_char STR_CELLINDEX[]; - extern const pm_char STR_LOGS[]; - extern const pm_char STR_OPTIONS[]; - extern const pm_char STR_ALTSENSOR[]; - extern const pm_char STR_CELLSENSOR[]; - extern const pm_char STR_GPSSENSOR[]; - extern const pm_char STR_CURRENTSENSOR[]; - extern const pm_char STR_AUTOOFFSET[]; - extern const pm_char STR_ONLYPOSITIVE[]; - extern const pm_char STR_FILTER[]; - extern const pm_char STR_TELEMETRYFULL[]; - extern const pm_char STR_SERVOS_OK[]; - extern const pm_char STR_SERVOS_KO[]; - extern const pm_char STR_INVERTED_SERIAL[]; - extern const pm_char STR_IGNORE_INSTANCE[]; - extern const pm_char STR_DISCOVER_SENSORS[]; - extern const pm_char STR_STOP_DISCOVER_SENSORS[]; - extern const pm_char STR_DELETE_ALL_SENSORS[]; - extern const pm_char STR_CONFIRMDELETE[]; - extern const pm_char STR_SELECT_WIDGET[]; - extern const pm_char STR_REMOVE_WIDGET[]; - extern const pm_char STR_WIDGET_SETTINGS[]; - extern const pm_char STR_REMOVE_SCREEN[]; - extern const pm_char STR_SETUP_WIDGETS[]; - extern const pm_char STR_USER_INTERFACE[]; - extern const pm_char STR_THEME[]; - extern const pm_char STR_SETUP[]; - extern const pm_char STR_MAINVIEWX[]; - extern const pm_char STR_LAYOUT[]; - extern const pm_char STR_ADDMAINVIEW[]; - extern const pm_char STR_BACKGROUND_COLOR[]; - extern const pm_char STR_MAIN_COLOR[]; -#endif - -#if defined(CPUARM) - extern const pm_char STR_BYTES[]; - extern const pm_char STR_ANTENNAPROBLEM[]; - extern const pm_char STR_MODULE[]; - extern const pm_char STR_ENABLE_POPUP[]; - extern const pm_char STR_DISABLE_POPUP[]; - extern const pm_char STR_POPUP[]; - extern const pm_char STR_MIN[]; - extern const pm_char STR_MAX[]; - extern const pm_char STR_CURVE_PRESET[]; - extern const pm_char STR_PRESET[]; - extern const pm_char STR_MIRROR[]; - extern const pm_char STR_CLEAR[]; - extern const pm_char STR_RESET[]; - extern const pm_char STR_COUNT[]; - extern const pm_char STR_PT[]; - extern const pm_char STR_PTS[]; - extern const pm_char STR_SMOOTH[]; - extern const pm_char STR_COPY_STICKS_TO_OFS[]; - extern const pm_char STR_COPY_TRIMS_TO_OFS[]; - extern const pm_char STR_INCDEC[]; - extern const pm_char STR_GLOBALVAR[]; - extern const pm_char STR_MIXSOURCE[]; - extern const pm_char STR_CONSTANT[]; - extern const pm_char STR_TOP_BAR[]; - extern const pm_char STR_ALTITUDE[]; - extern const pm_char STR_SCALE[]; - extern const pm_char STR_VIEW_CHANNELS[]; - extern const pm_char STR_POTWARNING[]; - extern const pm_char STR_UART3MODE[]; - extern const pm_char STR_THROTTLE_LABEL[]; - extern const pm_char STR_SCRIPT[]; - extern const pm_char STR_INPUTS[]; - extern const pm_char STR_OUTPUTS[]; - extern const pm_char STR_MENU_INPUTS[]; - extern const pm_char STR_MENU_LUA[]; - extern const pm_char STR_MENU_STICKS[]; - extern const pm_char STR_MENU_POTS[]; - extern const pm_char STR_MENU_MAX[]; - extern const pm_char STR_MENU_HELI[]; - extern const pm_char STR_MENU_TRIMS[]; - extern const pm_char STR_MENU_SWITCHES[]; - extern const pm_char STR_MENU_LOGICAL_SWITCHES[]; - extern const pm_char STR_MENU_TRAINER[]; - extern const pm_char STR_MENU_CHANNELS[]; - extern const pm_char STR_MENU_GVARS[]; - extern const pm_char STR_MENU_TELEMETRY[]; - extern const pm_char STR_MENU_DISPLAY[]; - extern const pm_char STR_MENU_OTHER[]; - extern const pm_char STR_MENU_INVERT[]; - extern const pm_char STR_JITTER_FILTER[]; -#endif - -#if MENUS_LOCK == 1 - extern const pm_char STR_UNLOCKED[]; - extern const pm_char STR_MODS_FORBIDDEN[]; -#endif - -#if defined(PCBTARANIS) || defined(DSM2) - extern const pm_char STR_MODULE_RANGE[]; -#endif - -#if defined(TELEMETRY_MAVLINK) - extern const pm_char STR_MAVLINK_RC_RSSI_SCALE_LABEL[]; - extern const pm_char STR_MAVLINK_PC_RSSI_EN_LABEL[]; - extern const pm_char STR_MAVMENUSETUP_TITLE[]; - extern const pm_char STR_MAVLINK_BAUD_LABEL[]; - extern const pm_char STR_MAVLINK_INFOS[]; - extern const pm_char STR_MAVLINK_MODE[]; - extern const pm_char STR_MAVLINK_CUR_MODE[]; - extern const pm_char STR_MAVLINK_ARMED[]; - extern const pm_char STR_MAVLINK_BAT_MENU_TITLE[]; - extern const pm_char STR_MAVLINK_BATTERY_LABEL[]; - extern const pm_char STR_MAVLINK_RC_RSSI_LABEL[]; - extern const pm_char STR_MAVLINK_PC_RSSI_LABEL[]; - extern const pm_char STR_MAVLINK_NAV_MENU_TITLE[]; - extern const pm_char STR_MAVLINK_COURSE[]; - extern const pm_char STR_MAVLINK_HEADING[]; - extern const pm_char STR_MAVLINK_BEARING[]; - extern const pm_char STR_MAVLINK_ALTITUDE[]; - extern const pm_char STR_MAVLINK_GPS[]; - extern const pm_char STR_MAVLINK_NO_FIX[]; - extern const pm_char STR_MAVLINK_SAT[]; - extern const pm_char STR_MAVLINK_HDOP[]; - extern const pm_char STR_MAVLINK_LAT[]; - extern const pm_char STR_MAVLINK_LON[]; -#endif - -#if !defined(CPUM64) - extern const pm_char STR_ABOUTUS[]; - extern const pm_char STR_ABOUT_OPENTX_1[]; - extern const pm_char STR_ABOUT_OPENTX_2[]; - extern const pm_char STR_ABOUT_OPENTX_3[]; - extern const pm_char STR_ABOUT_OPENTX_4[]; - extern const pm_char STR_ABOUT_OPENTX_5[]; - - extern const pm_char STR_ABOUT_BERTRAND_1[]; - extern const pm_char STR_ABOUT_BERTRAND_2[]; - extern const pm_char STR_ABOUT_BERTRAND_3[]; - - extern const pm_char STR_ABOUT_MIKE_1[]; - extern const pm_char STR_ABOUT_MIKE_2[]; - extern const pm_char STR_ABOUT_MIKE_3[]; - extern const pm_char STR_ABOUT_MIKE_4[]; - - extern const pm_char STR_ABOUT_ROMOLO_1[]; - extern const pm_char STR_ABOUT_ROMOLO_2[]; - extern const pm_char STR_ABOUT_ROMOLO_3[]; - - extern const pm_char STR_ABOUT_ANDRE_1[]; - extern const pm_char STR_ABOUT_ANDRE_2[]; - extern const pm_char STR_ABOUT_ANDRE_3[]; - - extern const pm_char STR_ABOUT_ROB_1[]; - extern const pm_char STR_ABOUT_ROB_2[]; - - extern const pm_char STR_ABOUT_MARTIN_1[]; - extern const pm_char STR_ABOUT_MARTIN_2[]; - - extern const pm_char STR_ABOUT_KJELL_1[]; - extern const pm_char STR_ABOUT_KJELL_2[]; - extern const pm_char STR_ABOUT_KJELL_3[]; - extern const pm_char STR_ABOUT_KJELL_4[]; - - extern const pm_char STR_ABOUT_HARDWARE_1[]; - extern const pm_char STR_ABOUT_HARDWARE_2[]; - extern const pm_char STR_ABOUT_HARDWARE_3[]; - - extern const pm_char STR_ABOUT_PARENTS_1[]; - extern const pm_char STR_ABOUT_PARENTS_2[]; - extern const pm_char STR_ABOUT_PARENTS_3[]; - extern const pm_char STR_ABOUT_PARENTS_4[]; -#endif - -#define CHR_SHORT TR_CHR_SHORT -#define CHR_LONG TR_CHR_LONG -#define CHR_TOGGLE TR_CHR_TOGGLE -#define CHR_HOUR TR_CHR_HOUR -#define CHR_INPUT TR_CHR_INPUT - -#endif // _TRANSLATIONS_H_ +#else + #define OFS_VOLTSRC (OFS_DSM_PROTOCOLS + sizeof(TR_DSM_PROTOCOLS)) +#endif + #define OFS_CURVE_TYPES (OFS_VOLTSRC + sizeof(TR_VOLTSRC)) + #define OFS_VSENSORTYPES (OFS_CURVE_TYPES + sizeof(TR_CURVE_TYPES)) + #define OFS_VFORMULAS (OFS_VSENSORTYPES + sizeof(TR_VSENSORTYPES)) + #define OFS_VPREC (OFS_VFORMULAS + sizeof(TR_VFORMULAS)) + #define OFS_VCELLINDEX (OFS_VPREC + sizeof(TR_VPREC)) + #define OFS_VANTENNATYPES (OFS_VCELLINDEX + sizeof(TR_VCELLINDEX)) + #define OFS_MAVLINK_BAUDS (OFS_VANTENNATYPES + sizeof(TR_VANTENNATYPES)) +#else + #define OFS_MAVLINK_BAUDS (OFS_VTRAINERMODES) +#endif +#if defined(TELEMETRY_MAVLINK) + #define OFS_MAVLINK_AC_MODES (OFS_MAVLINK_BAUDS + sizeof(TR_MAVLINK_BAUDS)) + #define OFS_MAVLINK_AP_MODES (OFS_MAVLINK_AC_MODES + sizeof(TR_MAVLINK_AC_MODES)) + #define OFS_SPARE (OFS_MAVLINK_AP_MODES + sizeof(TR_MAVLINK_AP_MODES)) +#else + #define OFS_SPARE (OFS_MAVLINK_BAUDS) +#endif + +#define STR_OFFON (STR_OPEN9X + OFS_OFFON) +#define STR_MMMINV (STR_OPEN9X + OFS_MMMINV) +#define STR_NCHANNELS (STR_OPEN9X + OFS_NCHANNELS) +#if !defined(GRAPHICS) +#define STR_VBEEPLEN (STR_OPEN9X + OFS_VBEEPLEN) +#endif +#define STR_VBEEPMODE (STR_OPEN9X + OFS_VBEEPMODE) +#define STR_TRNMODE (STR_OPEN9X + OFS_TRNMODE) +#define STR_TRNCHN (STR_OPEN9X + OFS_TRNCHN) +#define STR_UART3MODES (STR_OPEN9X + OFS_UART3MODES) +#define STR_SWTYPES (STR_OPEN9X + OFS_SWTYPES) +#define STR_POTTYPES (STR_OPEN9X + OFS_POTTYPES) +#define STR_SLIDERTYPES (STR_OPEN9X + OFS_SLIDERTYPES) +#define STR_VTRIMINC (STR_OPEN9X + OFS_VTRIMINC) +#define STR_VDISPLAYTRIMS (STR_OPEN9X + OFS_VDISPLAYTRIMS) +#define STR_RETA123 (STR_OPEN9X + OFS_RETA123) +#define STR_VPROTOS (STR_OPEN9X + OFS_VPROTOS) +#define STR_POSNEG (STR_OPEN9X + OFS_POSNEG) +#if defined(PCBSKY9X) && defined(REVX) + #define STR_VOUTPUT_TYPE (STR_OPEN9X + OFS_VOUTPUT_TYPE) +#endif +#define STR_VBLMODE (STR_OPEN9X + OFS_VBLMODE) +#define STR_VCURVEFUNC (STR_OPEN9X + OFS_VCURVEFUNC) +#define STR_VSIDE STR_VCURVEFUNC +#define LEN_VSIDE LEN_VCURVEFUNC +#define STR_VMLTPX (STR_OPEN9X + OFS_VMLTPX) +#define STR_VMLTPX2 (STR_OPEN9X + OFS_VMLTPX2) +#define STR_VMIXTRIMS (STR_OPEN9X + OFS_VMIXTRIMS) +#define STR_VCSWFUNC (STR_OPEN9X + OFS_VCSWFUNC) +#define STR_VFSWFUNC (STR_OPEN9X + OFS_VFSWFUNC) +#define STR_VFSWRESET (STR_OPEN9X + OFS_VFSWRESET) +#define STR_FUNCSOUNDS (STR_OPEN9X + OFS_FUNCSOUNDS) +#define STR_VTELEMCHNS (STR_OPEN9X + OFS_VTELEMCHNS) + +#if defined(TELEMETRY_FRSKY) || defined(CPUARM) + #if defined(CPUARM) + #define STR_VTELEMUNIT (STR_OPEN9X + OFS_VTELEMUNIT) + #define STR_VOLTSRC (STR_OPEN9X + OFS_VOLTSRC) + #else + #define STR_VTELEMUNIT (STR_OPEN9X + OFS_VTELEMUNIT) + #endif +#define STR_VALARM (STR_OPEN9X + OFS_VALARM) +#define STR_VALARMFN (STR_OPEN9X + OFS_VALARMFN) +#define STR_VTELPROTO (STR_OPEN9X + OFS_VTELPROTO) +#define STR_GPSFORMAT (STR_OPEN9X + OFS_GPSFORMAT) +#define STR_AMPSRC (STR_OPEN9X + OFS_AMPSRC) +#define STR_VARIOSRC (STR_OPEN9X + OFS_VARIOSRC) +#define STR_VTELEMSCREENTYPE (STR_OPEN9X + OFS_VSCREEN) +#define STR_TELEMCHNS (STR_OPEN9X + OFS_TELEMCHNS) +#endif + +#if defined(TEMPLATES) + #define STR_VTEMPLATES (STR_OPEN9X + OFS_VTEMPLATES) +#endif + +#if defined(HELI) + #define STR_VSWASHTYPE (STR_OPEN9X + OFS_VSWASHTYPE) +#endif + +#define STR_VKEYS (STR_OPEN9X + OFS_VKEYS) +#define STR_VSWITCHES (STR_OPEN9X + OFS_VSWITCHES) +#define STR_VSRCRAW (STR_OPEN9X + OFS_VSRCRAW) +#if defined(TRANSLATIONS_CZ) && defined(CPUARM) +#define STR_INPUTNAMES (STR_OPEN9X + OFS_INPUTNAMES) +#endif +#define STR_VTMRMODES (STR_OPEN9X + OFS_VTMRMODES) + +#if defined(ROTARY_ENCODERS) + #define STR_VRENAVIG (STR_OPEN9X + OFS_VRENAVIG) +#endif + +#if defined(ROTARY_ENCODER_NAVIGATION) + #define STR_VRENCODERS (STR_OPEN9X + OFS_VRENCODERS) +#endif + +#if defined(CPUM2560) || defined(CPUARM) + #define STR_DATETIME (STR_OPEN9X + OFS_DATETIME) + #define STR_VPERSISTENT (STR_OPEN9X + OFS_VPERSISTENT) +#endif + +#if defined(CPUARM) + #define STR_VLCD (STR_OPEN9X + OFS_VLCD) + #define STR_VUNITSSYSTEM (STR_OPEN9X + OFS_VUNITSSYSTEM) + #define STR_VBEEPCOUNTDOWN (STR_OPEN9X + OFS_VBEEPCOUNTDOWN) + #define STR_VVARIOCENTER (STR_OPEN9X + OFS_VVARIOCENTER) +#endif + +#if defined(PXX) || defined(CPUARM) + #define STR_COUNTRYCODES (STR_OPEN9X + OFS_COUNTRYCODES) + #define STR_VFAILSAFE (STR_OPEN9X + OFS_VFAILSAFE) +#endif + +#if defined(CPUARM) + #define STR_VTRAINERMODES (STR_OPEN9X + OFS_VTRAINERMODES) + #define STR_TARANIS_PROTOCOLS (STR_OPEN9X + OFS_TARANIS_PROTOCOLS) + #define STR_TELEMETRY_PROTOCOLS (STR_OPEN9X + OFS_TELEMETRY_PROTOCOLS) + #define STR_XJT_PROTOCOLS (STR_OPEN9X + OFS_XJT_PROTOCOLS) + #define STR_DSM_PROTOCOLS (STR_OPEN9X + OFS_DSM_PROTOCOLS) +#if defined(MULTIMODULE) + #define STR_MULTI_PROTOCOLS (STR_OPEN9X + OFS_MULTI_PROTOCOLS) +#endif + #define STR_CURVE_TYPES (STR_OPEN9X + OFS_CURVE_TYPES) + #define STR_VSENSORTYPES (STR_OPEN9X + OFS_VSENSORTYPES) + #define STR_VFORMULAS (STR_OPEN9X + OFS_VFORMULAS) + #define STR_VPREC (STR_OPEN9X + OFS_VPREC) + #define STR_VCELLINDEX (STR_OPEN9X + OFS_VCELLINDEX) + #define STR_VANTENNATYPES (STR_OPEN9X + OFS_VANTENNATYPES) +#endif + +#if defined(TELEMETRY_MAVLINK) + #define STR_MAVLINK_BAUDS (STR_OPEN9X + OFS_MAVLINK_BAUDS) + #define STR_MAVLINK_AC_MODES (STR_OPEN9X + OFS_MAVLINK_AC_MODES) + #define STR_MAVLINK_AP_MODES (STR_OPEN9X + OFS_MAVLINK_AP_MODES) +#endif + +// The 0-terminated-strings +#define NO_INDENT(x) (x)+LEN_INDENT + +extern const pm_char STR_POPUPS[]; + +#if defined(OFS_EXIT) + #define STR_EXIT (STR_POPUPS + OFS_EXIT) +#else + extern const pm_char STR_EXIT[]; +#endif + +#if !defined(PCBHORUS) + extern const pm_char STR_MENUWHENDONE[]; +#endif + +extern const pm_char STR_FREE[]; +#define LEN_FREE PSIZE(TR_FREE) +extern const pm_char STR_DELETEMODEL[]; +extern const pm_char STR_COPYINGMODEL[]; +extern const pm_char STR_MOVINGMODEL[]; +extern const pm_char STR_LOADINGMODEL[]; +extern const pm_char STR_NAME[]; +extern const pm_char STR_BITMAP[]; +extern const pm_char STR_TIMER[]; +extern const pm_char STR_ELIMITS[]; +extern const pm_char STR_ETRIMS[]; +extern const pm_char STR_TRIMINC[]; +extern const pm_char STR_DISPLAY_TRIMS[]; +extern const pm_char STR_TTRACE[]; +extern const pm_char STR_TTRIM[]; +extern const pm_char STR_BEEPCTR[]; +extern const pm_char STR_USE_GLOBAL_FUNCS[]; +#if defined(PCBSKY9X) && defined(REVX) + extern const pm_char STR_OUTPUT_TYPE[]; +#endif +extern const pm_char STR_PROTO[]; +extern const pm_char STR_PPMFRAME[]; +extern const pm_char STR_MS[]; +extern const pm_char STR_SWITCH[]; +extern const pm_char STR_TRIMS[]; +extern const pm_char STR_FADEIN[]; +extern const pm_char STR_FADEOUT[]; +extern const pm_char STR_DEFAULT[]; +extern const pm_char STR_CHECKTRIMS[]; +extern const pm_char STR_SWASHTYPE[]; +extern const pm_char STR_COLLECTIVE[]; +extern const pm_char STR_AILERON[]; +extern const pm_char STR_ELEVATOR[]; +extern const pm_char STR_SWASHRING[]; +extern const pm_char STR_ELEDIRECTION[]; +extern const pm_char STR_AILDIRECTION[]; +extern const pm_char STR_COLDIRECTION[]; +extern const pm_char STR_MODE[]; +#if defined(AUDIO) && defined(BUZZER) +extern const pm_char STR_SPEAKER[]; +extern const pm_char STR_BUZZER[]; +#else +#define STR_SPEAKER STR_MODE +#define STR_BUZZER STR_MODE +#endif +extern const pm_char STR_NOFREEEXPO[]; +extern const pm_char STR_NOFREEMIXER[]; +extern const pm_char STR_SOURCE[]; +extern const pm_char STR_WEIGHT[]; +extern const pm_char STR_EXPO[]; +extern const pm_char STR_SIDE[]; +extern const pm_char STR_DIFFERENTIAL[]; +extern const pm_char STR_OFFSET[]; +extern const pm_char STR_TRIM[]; +extern const pm_char STR_DREX[]; +extern const pm_char STR_CURVE[]; +extern const pm_char STR_FLMODE[]; +extern const pm_char STR_MIXWARNING[]; +extern const pm_char STR_OFF[]; +extern const pm_char STR_MULTPX[]; +extern const pm_char STR_DELAYDOWN[]; +extern const pm_char STR_DELAYUP[]; +extern const pm_char STR_SLOWDOWN[]; +extern const pm_char STR_SLOWUP[]; +extern const pm_char STR_MIXER[]; +extern const pm_char STR_CV[]; +extern const pm_char STR_GV[]; +extern const pm_char STR_ACHANNEL[]; +extern const pm_char STR_RANGE[]; +extern const pm_char STR_CENTER[]; +extern const pm_char STR_BAR[]; +extern const pm_char STR_ALARM[]; +extern const pm_char STR_USRDATA[]; +extern const pm_char STR_BLADES[]; +extern const pm_char STR_SCREEN[]; +extern const pm_char STR_SOUND_LABEL[]; +extern const pm_char STR_LENGTH[]; +extern const pm_char STR_BEEP_LENGTH[]; +#if defined(CPUARM) +extern const pm_char STR_BEEP_LENGTH[]; +#else +#define STR_BEEP_LENGTH STR_LENGTH +#endif +extern const pm_char STR_SPKRPITCH[]; +extern const pm_char STR_HAPTIC_LABEL[]; +extern const pm_char STR_HAPTICSTRENGTH[]; +extern const pm_char STR_CONTRAST[]; +extern const pm_char STR_ALARMS_LABEL[]; +#if defined(BATTGRAPH) || defined(CPUARM) +extern const pm_char STR_BATTERY_RANGE[]; +#endif +extern const pm_char STR_BATTERYWARNING[]; +extern const pm_char STR_INACTIVITYALARM[]; +extern const pm_char STR_MEMORYWARNING[]; +extern const pm_char STR_ALARMWARNING[]; +extern const pm_char STR_RENAVIG[]; +extern const pm_char STR_THROTTLEREVERSE[]; +extern const pm_char STR_TIMER_NAME[]; +extern const pm_char STR_MINUTEBEEP[]; +extern const pm_char STR_BEEPCOUNTDOWN[]; +extern const pm_char STR_PERSISTENT[]; +extern const pm_char STR_BACKLIGHT_LABEL[]; +extern const pm_char STR_BLDELAY[]; +#if defined(PWM_BACKLIGHT) || defined(PCBHORUS) +extern const pm_char STR_BLONBRIGHTNESS[]; +extern const pm_char STR_BLOFFBRIGHTNESS[]; +#endif +extern const pm_char STR_SPLASHSCREEN[]; +extern const pm_char STR_THROTTLEWARNING[]; +extern const pm_char STR_SWITCHWARNING[]; +extern const pm_char STR_POTWARNINGSTATE[]; +extern const pm_char STR_POTWARNING[]; +extern const pm_char STR_SLIDERWARNING[]; +extern const pm_char STR_TIMEZONE[]; +extern const pm_char STR_ADJUST_RTC[]; +extern const pm_char STR_GPS[]; +extern const pm_char STR_GPSCOORD[]; +extern const pm_char STR_VARIO[]; +extern const pm_char STR_PITCH_AT_ZERO[]; +extern const pm_char STR_PITCH_AT_MAX[]; +extern const pm_char STR_REPEAT_AT_ZERO[]; +extern const pm_char STR_RXCHANNELORD[]; +extern const pm_char STR_STICKS[]; +extern const pm_char STR_POTS[]; +extern const pm_char STR_SWITCHES[]; +extern const pm_char STR_SWITCHES_DELAY[]; +extern const pm_char STR_SLAVE[]; +extern const pm_char STR_MODESRC[]; +extern const pm_char STR_MULTIPLIER[]; +#define LEN_MULTIPLIER PSIZE(TR_MULTIPLIER) +extern const pm_char STR_CAL[]; +extern const pm_char STR_VTRIM[]; +extern const pm_char STR_BG[]; +extern const pm_char STR_MENUTOSTART[]; +extern const pm_char STR_SETMIDPOINT[]; +extern const pm_char STR_MOVESTICKSPOTS[]; +extern const pm_char STR_RXBATT[]; +extern const pm_char STR_TX[]; +#define STR_RX (STR_TX+OFS_RX) +extern const pm_char STR_ACCEL[]; +extern const pm_char STR_NODATA[]; +extern const pm_char STR_TOTTM1TM2THRTHP[]; +extern const pm_char STR_TMR1LATMAXUS[]; +extern const pm_char STR_TMR1LATMINUS[]; +extern const pm_char STR_TMR1JITTERUS[]; +extern const pm_char STR_TMIXMAXMS[]; +extern const pm_char STR_FREESTACKMINB[]; +extern const pm_char STR_MENUTORESET[]; +extern const pm_char STR_PPM_TRAINER[]; +extern const pm_char STR_CH[]; +extern const pm_char STR_MODEL[]; +extern const pm_char STR_FP[]; +#if defined(CPUARM) +extern const pm_char STR_MIX[]; +#endif +extern const pm_char STR_EEPROMLOWMEM[]; +extern const pm_char STR_ALERT[]; +extern const pm_char STR_PRESSANYKEYTOSKIP[]; +extern const pm_char STR_THROTTLENOTIDLE[]; +extern const pm_char STR_ALARMSDISABLED[]; +extern const pm_char STR_PRESSANYKEY[]; +#define LEN_PRESSANYKEY PSIZE(TR_PRESSANYKEY) +extern const pm_char STR_BAD_RADIO_DATA[]; +extern const pm_char STR_STORAGE_FORMAT[]; +extern const pm_char STR_EEPROMOVERFLOW[]; +extern const pm_char STR_TRIMS2OFFSETS[]; +extern const pm_char STR_MENURADIOSETUP[]; +extern const pm_char STR_MENUDATEANDTIME[]; +extern const pm_char STR_MENUTRAINER[]; +extern const pm_char STR_MENUSPECIALFUNCS[]; +extern const pm_char STR_MENUVERSION[]; +extern const pm_char STR_MENU_RADIO_SWITCHES[]; +extern const pm_char STR_MENU_RADIO_ANALOGS[]; +extern const pm_char STR_MENUCALIBRATION[]; +extern const pm_char STR_MENUMODELSEL[]; +extern const pm_char STR_MENUSETUP[]; +extern const pm_char STR_MENUFLIGHTMODE[]; +extern const pm_char STR_MENUFLIGHTMODES[]; +extern const pm_char STR_MENUHELISETUP[]; +extern const pm_char STR_MENUINPUTS[]; +extern const pm_char STR_MENULIMITS[]; +extern const pm_char STR_MENUCURVES[]; +extern const pm_char STR_MENUCURVE[]; +extern const pm_char STR_MENULOGICALSWITCH[]; +extern const pm_char STR_MENULOGICALSWITCHES[]; +extern const pm_char STR_MENUCUSTOMFUNC[]; +extern const pm_char STR_MENUCUSTOMSCRIPTS[]; +extern const pm_char STR_MENUTELEMETRY[]; +extern const pm_char STR_MENUTEMPLATES[]; +extern const pm_char STR_MENUSTAT[]; +extern const pm_char STR_MENUDEBUG[]; +extern const char * const STR_MONITOR_CHANNELS[]; +extern const pm_char STR_MONITOR_SWITCHES[]; +extern const pm_char STR_MONITOR_OUTPUT_DESC[]; +extern const pm_char STR_MONITOR_MIXER_DESC[]; +extern const pm_char STR_MENUGLOBALVARS[]; +extern const pm_char STR_INVERT_THR[]; +extern const pm_char STR_AND_SWITCH[]; +extern const pm_char STR_SF[]; +extern const pm_char STR_GF[]; + +#if defined(FAS_OFFSET) || !defined(CPUM64) +extern const pm_char STR_FAS_OFFSET[]; +#endif + +#if defined(MULTIMODULE) +extern const pm_char STR_MULTI_CUSTOM[]; +extern const pm_char STR_MULTI_OPTION[]; +extern const pm_char STR_MULTI_VIDFREQ[]; +extern const pm_char STR_MULTI_RFPOWER[]; +extern const pm_char STR_MULTI_RFTUNE[]; +extern const pm_char STR_MULTI_TELEMETRY[]; +extern const pm_char STR_MULTI_AUTOBIND[]; +extern const pm_char STR_MULTI_DSM_AUTODTECT[]; +extern const pm_char STR_MULTI_LOWPOWER[]; +extern const pm_char STR_DISABLE_INTERNAL[]; +extern const pm_char STR_MODULE_NO_SERIAL_MODE[]; +extern const pm_char STR_MODULE_NO_INPUT[]; +extern const pm_char STR_MODULE_NO_TELEMETRY[]; +extern const pm_char STR_MODULE_BINDING[]; +extern const pm_char STR_PROTOCOL_INVALID[]; +extern const pm_char STR_MODULE_STATUS[]; +extern const pm_char STR_MULTI_SERVOFREQ[]; +#if LCD_W < 212 +extern const pm_char STR_SUBTYPE[]; +#endif +#endif +#if defined(DSM2) || defined(PXX) +extern const pm_char STR_RECEIVER_NUM[]; +extern const pm_char STR_RECEIVER[]; +#endif + +#if defined(PXX) || defined(CPUARM) +extern const pm_char STR_SYNCMENU[]; +extern const pm_char STR_INTERNALRF[]; +extern const pm_char STR_EXTERNALRF[]; +extern const pm_char STR_FAILSAFE[]; +extern const pm_char STR_FAILSAFESET[]; +extern const pm_char STR_HOLD[]; +extern const pm_char STR_NONE[]; +extern const pm_char STR_MENUSENSOR[]; +extern const pm_char STR_SENSOR[]; +extern const pm_char STR_COUNTRYCODE[]; +#endif + +#if defined(TELEMETRY_FRSKY) +extern const pm_char STR_LIMIT[]; +#endif + +#ifdef FRSKY_HUB +extern const pm_char STR_MINRSSI[]; +extern const pm_char STR_LATITUDE[]; +extern const pm_char STR_LONGITUDE[]; +#endif + +#if defined(CPUARM) || defined(CPUM2560) +extern const pm_char STR_SHUTDOWN[]; +extern const pm_char STR_SAVEMODEL[]; +#endif + +#if defined(PCBX9E) +extern const pm_char STR_POWEROFF[]; +#endif + +extern const pm_char STR_BATT_CALIB[]; + +#if defined(CPUARM) || defined(TELEMETRY_FRSKY) +extern const pm_char STR_VOLTAGE[]; +extern const pm_char STR_CURRENT[]; +#endif + +#if defined(CPUARM) +extern const pm_char STR_CURRENT_CALIB[]; +extern const pm_char STR_UNITSSYSTEM[]; +extern const pm_char STR_VOICELANG[]; +extern const pm_char STR_MODELIDUSED[]; +extern const pm_char STR_BEEP_VOLUME[]; +extern const pm_char STR_WAV_VOLUME[]; +extern const pm_char STR_BG_VOLUME[]; +extern const pm_char STR_PERSISTENT_MAH[]; +#endif + +#if defined(PCBSKY9X) +#define LEN_CALIB_FIELDS (PSIZE(TR_BATT_CALIB) > PSIZE(TR_CURRENT_CALIB) ? PSIZE(TR_BATT_CALIB) : PSIZE(TR_CURRENT_CALIB)) +#else +#define LEN_CALIB_FIELDS PSIZE(TR_BATT_CALIB) +#endif + +#if defined(NAVIGATION_MENUS) + extern const pm_char STR_SELECT_MODEL[]; + extern const pm_char STR_CREATE_CATEGORY[]; + extern const pm_char STR_RENAME_CATEGORY[]; + extern const pm_char STR_DELETE_CATEGORY[]; + extern const pm_char STR_CREATE_MODEL[]; + extern const pm_char STR_DUPLICATE_MODEL[]; + extern const pm_char STR_COPY_MODEL[]; + extern const pm_char STR_MOVE_MODEL[]; + extern const pm_char STR_DELETE_MODEL[]; + extern const pm_char STR_EDIT[]; + extern const pm_char STR_INSERT_BEFORE[]; + extern const pm_char STR_INSERT_AFTER[]; + extern const pm_char STR_COPY[]; + extern const pm_char STR_MOVE[]; + extern const pm_char STR_PASTE[]; + extern const pm_char STR_INSERT[]; + extern const pm_char STR_DELETE[]; + extern const pm_char STR_RESET_FLIGHT[]; + extern const pm_char STR_RESET_TIMER1[]; + extern const pm_char STR_RESET_TIMER2[]; + extern const pm_char STR_RESET_TIMER3[]; + extern const pm_char STR_RESET_TELEMETRY[]; + extern const pm_char STR_STATISTICS[]; + extern const pm_char STR_ABOUT_US[]; + extern const pm_char STR_SETUP_SCREENS[]; + extern const pm_char STR_MONITOR_SCREENS[]; +#endif + +extern const pm_char STR_RESET_BTN[]; + +#if defined(SDCARD) + extern const pm_char STR_BACKUP_MODEL[]; + extern const pm_char STR_RESTORE_MODEL[]; + extern const pm_char STR_DELETE_ERROR[]; + extern const pm_char STR_SDCARD_ERROR[]; + extern const pm_char STR_NO_SDCARD[]; + extern const pm_char STR_SDCARD_FULL[]; + extern const pm_char STR_INCOMPATIBLE[]; + extern const pm_char STR_LOGS_PATH[]; + extern const pm_char STR_LOGS_EXT[]; + extern const pm_char STR_MODELS_PATH[]; + extern const pm_char STR_MODELS_EXT[]; + #define STR_UPDATE_LIST STR_DELAYDOWN +#endif + +extern const pm_char STR_CAT_NOT_EMPTY[]; +extern const pm_char STR_WARNING[]; +extern const pm_char STR_STORAGE_WARNING[]; +extern const pm_char STR_EEPROM_CONVERTING[]; +extern const pm_char STR_THROTTLEWARN[]; +extern const pm_char STR_ALARMSWARN[]; +extern const pm_char STR_SWITCHWARN[]; +extern const pm_char STR_FAILSAFEWARN[]; +extern const pm_char STR_WRONG_SDCARDVERSION[]; +extern const pm_char STR_WRONG_PCBREV[]; +extern const pm_char STR_EMERGENCY_MODE[]; +extern const pm_char STR_PCBREV_ERROR[]; +extern const pm_char STR_NO_FAILSAFE[]; +extern const pm_char STR_KEYSTUCK[]; + +extern const pm_char STR_SPEAKER_VOLUME[]; +extern const pm_char STR_LCD[]; +extern const pm_char STR_BRIGHTNESS[]; +extern const pm_char STR_CPU_TEMP[]; +extern const pm_char STR_CPU_CURRENT[]; +extern const pm_char STR_CPU_MAH[]; +extern const pm_char STR_COPROC[]; +extern const pm_char STR_COPROC_TEMP[]; +extern const pm_char STR_CAPAWARNING[]; +extern const pm_char STR_TEMPWARNING[]; +extern const pm_char STR_FUNC[]; +extern const pm_char STR_V1[]; +extern const pm_char STR_V2[]; +extern const pm_char STR_DURATION[]; +extern const pm_char STR_DELAY[]; +extern const pm_char STR_SD_CARD[]; +extern const pm_char STR_SDHC_CARD[]; +extern const pm_char STR_NO_SOUNDS_ON_SD[]; +extern const pm_char STR_NO_MODELS_ON_SD[]; +extern const pm_char STR_NO_BITMAPS_ON_SD[]; +extern const pm_char STR_NO_SCRIPTS_ON_SD[]; +extern const pm_char STR_SCRIPT_SYNTAX_ERROR[]; +extern const pm_char STR_SCRIPT_PANIC[]; +extern const pm_char STR_SCRIPT_KILLED[]; +extern const pm_char STR_SCRIPT_ERROR[]; +extern const pm_char STR_PLAY_FILE[]; +extern const pm_char STR_ASSIGN_BITMAP[]; +extern const pm_char STR_EXECUTE_FILE[]; +extern const pm_char STR_DELETE_FILE[]; +extern const pm_char STR_COPY_FILE[]; +extern const pm_char STR_RENAME_FILE[]; +extern const pm_char STR_REMOVED[]; +extern const pm_char STR_SD_INFO[]; +extern const pm_char STR_SD_FORMAT[]; +extern const pm_char STR_NA[]; +extern const pm_char STR_HARDWARE[]; +extern const pm_char STR_FORMATTING[]; +extern const pm_char STR_TEMP_CALIB[]; +extern const pm_char STR_TIME[]; +extern const pm_char STR_BAUDRATE[]; +extern const pm_char STR_SD_INFO_TITLE[]; +extern const pm_char STR_SD_TYPE[]; +extern const pm_char STR_SD_SPEED[]; +extern const pm_char STR_SD_SECTORS[]; +extern const pm_char STR_SD_SIZE[]; +extern const pm_char STR_TYPE[]; +extern const pm_char STR_GLOBAL_VARS[]; +extern const pm_char STR_GVARS[]; +extern const pm_char STR_GLOBAL_VAR[]; +extern const pm_char STR_OWN[]; +extern const pm_char STR_ROTARY_ENCODER[]; +extern const pm_char STR_DATE[]; +extern const pm_char STR_CHANNELS_MONITOR[]; +extern const pm_char STR_MIXERS_MONITOR[]; +extern const pm_char STR_PATH_TOO_LONG[]; +extern const pm_char STR_VIEW_TEXT[]; +extern const pm_char STR_FLASH_BOOTLOADER[]; +extern const pm_char STR_FLASH_EXTERNAL_DEVICE[]; +extern const pm_char STR_FLASH_INTERNAL_MODULE[]; +extern const pm_char STR_FIRMWARE_UPDATE_ERROR[]; +extern const pm_char STR_WRITING[]; +extern const pm_char STR_CONFIRM_FORMAT[]; +extern const pm_char STR_EEBACKUP[]; +extern const pm_char STR_FACTORYRESET[]; +extern const pm_char STR_CONFIRMRESET[]; +extern const pm_char STR_TOO_MANY_LUA_SCRIPTS[]; +extern const pm_char STR_BLCOLOR[]; + +#if defined(CPUARM) && defined(VOICE) + struct LanguagePack { + const char * id; + const char * name; + void (*playNumber)(getvalue_t number, uint8_t unit, uint8_t flags, uint8_t id); + void (*playDuration)(int seconds, uint8_t flags, uint8_t id); + }; + + extern const LanguagePack * currentLanguagePack; + extern uint8_t currentLanguagePackIdx; + + extern const LanguagePack czLanguagePack; + extern const LanguagePack enLanguagePack; + extern const LanguagePack esLanguagePack; + extern const LanguagePack frLanguagePack; + extern const LanguagePack deLanguagePack; + extern const LanguagePack itLanguagePack; + extern const LanguagePack plLanguagePack; + extern const LanguagePack ptLanguagePack; + extern const LanguagePack skLanguagePack; + extern const LanguagePack seLanguagePack; + extern const LanguagePack huLanguagePack; + extern const LanguagePack * const languagePacks[]; + #if defined(LANGUAGE_PACKS_DEFINITION) + const LanguagePack * const languagePacks[] = { + // alphabetical order + &czLanguagePack, + &deLanguagePack, + &enLanguagePack, + &esLanguagePack, + &frLanguagePack, + &huLanguagePack, + &itLanguagePack, + &plLanguagePack, + &ptLanguagePack, + &seLanguagePack, + &skLanguagePack, + NULL + }; + #endif +#if defined(SIMU) + #define LANGUAGE_PACK_DECLARE(lng, name) const LanguagePack lng ## LanguagePack = { #lng, name, lng ## _ ## playNumber, lng ## _ ## playDuration } +#else + #define LANGUAGE_PACK_DECLARE(lng, name) extern const LanguagePack lng ## LanguagePack = { #lng, name, lng ## _ ## playNumber, lng ## _ ## playDuration } +#endif + #define LANGUAGE_PACK_DECLARE_DEFAULT(lng, name) LANGUAGE_PACK_DECLARE(lng, name); const LanguagePack * currentLanguagePack = & lng ## LanguagePack; uint8_t currentLanguagePackIdx + inline PLAY_FUNCTION(playNumber, getvalue_t number, uint8_t unit, uint8_t flags) { currentLanguagePack->playNumber(number, unit, flags, id); } + inline PLAY_FUNCTION(playDuration, int seconds, uint8_t flags) { currentLanguagePack->playDuration(seconds, flags, id); } +#elif defined(VOICE) + PLAY_FUNCTION(playNumber, getvalue_t number, uint8_t unit, uint8_t att); + PLAY_FUNCTION(playDuration, int seconds); + #define LANGUAGE_PACK_DECLARE(lng, name) + #define LANGUAGE_PACK_DECLARE_DEFAULT(lng, name) +#else + #define LANGUAGE_PACK_DECLARE(lng, name) + #define LANGUAGE_PACK_DECLARE_DEFAULT(lng, name) +#endif + +#if defined(CPUARM) + extern const pm_char STR_MODELNAME[]; + extern const pm_char STR_PHASENAME[]; + extern const pm_char STR_MIXNAME[]; + extern const pm_char STR_INPUTNAME[]; + extern const pm_char STR_EXPONAME[]; +#else + #define STR_MODELNAME STR_NAME + #define STR_PHASENAME STR_NAME + #define STR_MIXNAME STR_NAME + #define STR_EXPONAME STR_NAME +#endif + +#if defined(COLORLCD) + #define TR_PHASES_HEADERS { TR_PHASES_HEADERS_NAME, TR_PHASES_HEADERS_SW, TR_PHASES_HEADERS_RUD_TRIM, TR_PHASES_HEADERS_ELE_TRIM, TR_PHASES_HEADERS_THT_TRIM, TR_PHASES_HEADERS_AIL_TRIM, TR_PHASES_HEADERS_CH5_TRIM, TR_PHASES_HEADERS_CH6_TRIM, TR_PHASES_HEADERS_FAD_IN, TR_PHASES_HEADERS_FAD_OUT } +#elif defined(PCBTARANIS) + #define TR_PHASES_HEADERS { HINT(TR_PHASES_HEADERS_NAME), HINT(TR_PHASES_HEADERS_SW), HINT(TR_PHASES_HEADERS_RUD_TRIM), HINT(TR_PHASES_HEADERS_ELE_TRIM), HINT(TR_PHASES_HEADERS_THT_TRIM), HINT(TR_PHASES_HEADERS_AIL_TRIM), HINT(TR_PHASES_HEADERS_FAD_IN), HINT(TR_PHASES_HEADERS_FAD_OUT) } +#endif + +#define TR_LIMITS_HEADERS { HINT(TR_LIMITS_HEADERS_NAME), HINT(TR_LIMITS_HEADERS_SUBTRIM), HINT(TR_LIMITS_HEADERS_MIN), HINT(TR_LIMITS_HEADERS_MAX), HINT(TR_LIMITS_HEADERS_DIRECTION), HINT(TR_LIMITS_HEADERS_CURVE), HINT(TR_LIMITS_HEADERS_PPMCENTER), HINT(TR_LIMITS_HEADERS_SUBTRIMMODE) } +#define TR_LSW_HEADERS { HINT(TR_LSW_HEADERS_FUNCTION), HINT(TR_LSW_HEADERS_V1), HINT(TR_LSW_HEADERS_V2), HINT(TR_LSW_HEADERS_V2), HINT(TR_LSW_HEADERS_ANDSW), HINT(TR_LSW_HEADERS_DURATION), HINT(TR_LSW_HEADERS_DELAY) } +#define TR_GVAR_HEADERS { HINT(TR_GVAR_HEADERS_NAME), HINT(TR_GVAR_HEADERS_FM0), HINT(TR_GVAR_HEADERS_FM1), HINT(TR_GVAR_HEADERS_FM2), HINT(TR_GVAR_HEADERS_FM3), HINT(TR_GVAR_HEADERS_FM4), HINT(TR_GVAR_HEADERS_FM5), HINT(TR_GVAR_HEADERS_FM6), HINT(TR_GVAR_HEADERS_FM7), HINT(TR_GVAR_HEADERS_FM8) } + +#if LCD_W >= 212 + extern const char * const STR_PHASES_HEADERS[]; + extern const char * const STR_LIMITS_HEADERS[]; + extern const char * const STR_LSW_HEADERS[]; + extern const char * const STR_LSW_DESCRIPTIONS[]; + extern const char * const STR_GVAR_HEADERS[]; +#endif + +#if defined(CPUARM) + extern const pm_char STR_TRAINER[]; + extern const pm_char STR_MODULE_BIND[]; + extern const pm_char STR_BINDING_1_8_TELEM_ON[]; + extern const pm_char STR_BINDING_1_8_TELEM_OFF[]; + extern const pm_char STR_BINDING_9_16_TELEM_ON[]; + extern const pm_char STR_BINDING_9_16_TELEM_OFF[]; + extern const pm_char STR_CHANNELRANGE[]; + extern const pm_char STR_ANTENNASELECTION[]; + extern const pm_char STR_ANTENNACONFIRM1[]; + extern const pm_char STR_ANTENNACONFIRM2[]; + extern const pm_char STR_SET[]; + extern const pm_char STR_PREFLIGHT[]; + extern const pm_char STR_CHECKLIST[]; + extern const pm_char STR_VIEW_NOTES[]; + extern const pm_char STR_MODEL_SELECT[]; + extern const pm_char STR_RESET_SUBMENU[]; + extern const pm_char STR_LOWALARM[]; + extern const pm_char STR_CRITICALALARM[]; + extern const pm_char STR_TELEMETRY_TYPE[]; + extern const pm_char STR_TELEMETRY_SENSORS[]; + extern const pm_char STR_VALUE[]; + extern const pm_char STR_TOPLCDTIMER[]; + extern const pm_char STR_UNIT[] PROGMEM; + extern const pm_char STR_TELEMETRY_NEWSENSOR[]; + extern const pm_char STR_ID[]; + extern const pm_char STR_PRECISION[]; + extern const pm_char STR_RATIO[]; + extern const pm_char STR_FORMULA[]; + extern const pm_char STR_CELLINDEX[]; + extern const pm_char STR_LOGS[]; + extern const pm_char STR_OPTIONS[]; + extern const pm_char STR_ALTSENSOR[]; + extern const pm_char STR_CELLSENSOR[]; + extern const pm_char STR_GPSSENSOR[]; + extern const pm_char STR_CURRENTSENSOR[]; + extern const pm_char STR_AUTOOFFSET[]; + extern const pm_char STR_ONLYPOSITIVE[]; + extern const pm_char STR_FILTER[]; + extern const pm_char STR_TELEMETRYFULL[]; + extern const pm_char STR_SERVOS_OK[]; + extern const pm_char STR_SERVOS_KO[]; + extern const pm_char STR_INVERTED_SERIAL[]; + extern const pm_char STR_IGNORE_INSTANCE[]; + extern const pm_char STR_DISCOVER_SENSORS[]; + extern const pm_char STR_STOP_DISCOVER_SENSORS[]; + extern const pm_char STR_DELETE_ALL_SENSORS[]; + extern const pm_char STR_CONFIRMDELETE[]; + extern const pm_char STR_SELECT_WIDGET[]; + extern const pm_char STR_REMOVE_WIDGET[]; + extern const pm_char STR_WIDGET_SETTINGS[]; + extern const pm_char STR_REMOVE_SCREEN[]; + extern const pm_char STR_SETUP_WIDGETS[]; + extern const pm_char STR_USER_INTERFACE[]; + extern const pm_char STR_THEME[]; + extern const pm_char STR_SETUP[]; + extern const pm_char STR_MAINVIEWX[]; + extern const pm_char STR_LAYOUT[]; + extern const pm_char STR_ADDMAINVIEW[]; + extern const pm_char STR_BACKGROUND_COLOR[]; + extern const pm_char STR_MAIN_COLOR[]; +#endif + +#if defined(CPUARM) + extern const pm_char STR_BYTES[]; + extern const pm_char STR_ANTENNAPROBLEM[]; + extern const pm_char STR_MODULE[]; + extern const pm_char STR_ENABLE_POPUP[]; + extern const pm_char STR_DISABLE_POPUP[]; + extern const pm_char STR_POPUP[]; + extern const pm_char STR_MIN[]; + extern const pm_char STR_MAX[]; + extern const pm_char STR_CURVE_PRESET[]; + extern const pm_char STR_PRESET[]; + extern const pm_char STR_MIRROR[]; + extern const pm_char STR_CLEAR[]; + extern const pm_char STR_RESET[]; + extern const pm_char STR_COUNT[]; + extern const pm_char STR_PT[]; + extern const pm_char STR_PTS[]; + extern const pm_char STR_SMOOTH[]; + extern const pm_char STR_COPY_STICKS_TO_OFS[]; + extern const pm_char STR_COPY_TRIMS_TO_OFS[]; + extern const pm_char STR_INCDEC[]; + extern const pm_char STR_GLOBALVAR[]; + extern const pm_char STR_MIXSOURCE[]; + extern const pm_char STR_CONSTANT[]; + extern const pm_char STR_TOP_BAR[]; + extern const pm_char STR_ALTITUDE[]; + extern const pm_char STR_SCALE[]; + extern const pm_char STR_VIEW_CHANNELS[]; + extern const pm_char STR_POTWARNING[]; + extern const pm_char STR_UART3MODE[]; + extern const pm_char STR_THROTTLE_LABEL[]; + extern const pm_char STR_SCRIPT[]; + extern const pm_char STR_INPUTS[]; + extern const pm_char STR_OUTPUTS[]; + extern const pm_char STR_MENU_INPUTS[]; + extern const pm_char STR_MENU_LUA[]; + extern const pm_char STR_MENU_STICKS[]; + extern const pm_char STR_MENU_POTS[]; + extern const pm_char STR_MENU_MAX[]; + extern const pm_char STR_MENU_HELI[]; + extern const pm_char STR_MENU_TRIMS[]; + extern const pm_char STR_MENU_SWITCHES[]; + extern const pm_char STR_MENU_LOGICAL_SWITCHES[]; + extern const pm_char STR_MENU_TRAINER[]; + extern const pm_char STR_MENU_CHANNELS[]; + extern const pm_char STR_MENU_GVARS[]; + extern const pm_char STR_MENU_TELEMETRY[]; + extern const pm_char STR_MENU_DISPLAY[]; + extern const pm_char STR_MENU_OTHER[]; + extern const pm_char STR_MENU_INVERT[]; + extern const pm_char STR_JITTER_FILTER[]; +#endif + +#if MENUS_LOCK == 1 + extern const pm_char STR_UNLOCKED[]; + extern const pm_char STR_MODS_FORBIDDEN[]; +#endif + +#if defined(PCBTARANIS) || defined(DSM2) + extern const pm_char STR_MODULE_RANGE[]; +#endif + +#if defined(TELEMETRY_MAVLINK) + extern const pm_char STR_MAVLINK_RC_RSSI_SCALE_LABEL[]; + extern const pm_char STR_MAVLINK_PC_RSSI_EN_LABEL[]; + extern const pm_char STR_MAVMENUSETUP_TITLE[]; + extern const pm_char STR_MAVLINK_BAUD_LABEL[]; + extern const pm_char STR_MAVLINK_INFOS[]; + extern const pm_char STR_MAVLINK_MODE[]; + extern const pm_char STR_MAVLINK_CUR_MODE[]; + extern const pm_char STR_MAVLINK_ARMED[]; + extern const pm_char STR_MAVLINK_BAT_MENU_TITLE[]; + extern const pm_char STR_MAVLINK_BATTERY_LABEL[]; + extern const pm_char STR_MAVLINK_RC_RSSI_LABEL[]; + extern const pm_char STR_MAVLINK_PC_RSSI_LABEL[]; + extern const pm_char STR_MAVLINK_NAV_MENU_TITLE[]; + extern const pm_char STR_MAVLINK_COURSE[]; + extern const pm_char STR_MAVLINK_HEADING[]; + extern const pm_char STR_MAVLINK_BEARING[]; + extern const pm_char STR_MAVLINK_ALTITUDE[]; + extern const pm_char STR_MAVLINK_GPS[]; + extern const pm_char STR_MAVLINK_NO_FIX[]; + extern const pm_char STR_MAVLINK_SAT[]; + extern const pm_char STR_MAVLINK_HDOP[]; + extern const pm_char STR_MAVLINK_LAT[]; + extern const pm_char STR_MAVLINK_LON[]; +#endif + +#if !defined(CPUM64) + extern const pm_char STR_ABOUTUS[]; + extern const pm_char STR_ABOUT_OPENTX_1[]; + extern const pm_char STR_ABOUT_OPENTX_2[]; + extern const pm_char STR_ABOUT_OPENTX_3[]; + extern const pm_char STR_ABOUT_OPENTX_4[]; + extern const pm_char STR_ABOUT_OPENTX_5[]; + + extern const pm_char STR_ABOUT_BERTRAND_1[]; + extern const pm_char STR_ABOUT_BERTRAND_2[]; + extern const pm_char STR_ABOUT_BERTRAND_3[]; + + extern const pm_char STR_ABOUT_MIKE_1[]; + extern const pm_char STR_ABOUT_MIKE_2[]; + extern const pm_char STR_ABOUT_MIKE_3[]; + extern const pm_char STR_ABOUT_MIKE_4[]; + + extern const pm_char STR_ABOUT_ROMOLO_1[]; + extern const pm_char STR_ABOUT_ROMOLO_2[]; + extern const pm_char STR_ABOUT_ROMOLO_3[]; + + extern const pm_char STR_ABOUT_ANDRE_1[]; + extern const pm_char STR_ABOUT_ANDRE_2[]; + extern const pm_char STR_ABOUT_ANDRE_3[]; + + extern const pm_char STR_ABOUT_ROB_1[]; + extern const pm_char STR_ABOUT_ROB_2[]; + + extern const pm_char STR_ABOUT_MARTIN_1[]; + extern const pm_char STR_ABOUT_MARTIN_2[]; + + extern const pm_char STR_ABOUT_KJELL_1[]; + extern const pm_char STR_ABOUT_KJELL_2[]; + extern const pm_char STR_ABOUT_KJELL_3[]; + extern const pm_char STR_ABOUT_KJELL_4[]; + + extern const pm_char STR_ABOUT_HARDWARE_1[]; + extern const pm_char STR_ABOUT_HARDWARE_2[]; + extern const pm_char STR_ABOUT_HARDWARE_3[]; + + extern const pm_char STR_ABOUT_PARENTS_1[]; + extern const pm_char STR_ABOUT_PARENTS_2[]; + extern const pm_char STR_ABOUT_PARENTS_3[]; + extern const pm_char STR_ABOUT_PARENTS_4[]; +#endif + +#define CHR_SHORT TR_CHR_SHORT +#define CHR_LONG TR_CHR_LONG +#define CHR_TOGGLE TR_CHR_TOGGLE +#define CHR_HOUR TR_CHR_HOUR +#define CHR_INPUT TR_CHR_INPUT + +#endif // _TRANSLATIONS_H_ diff --git a/radio/src/translations/tts_nl.cpp b/radio/src/translations/tts_nl.cpp index d2a8c6dab..170f945cf 100644 --- a/radio/src/translations/tts_nl.cpp +++ b/radio/src/translations/tts_nl.cpp @@ -1,162 +1,162 @@ -/* - * Authors (alphabetical order) - * - Andre Bernet - * - Bertrand Songis - * - Jean-Pierre van Melis - * - * opentx is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include "opentx.h" - -enum DutchPrompts { - NL_PROMPT_NUMBERS_BASE = 0, - NL_PROMPT_ZERO = NL_PROMPT_NUMBERS_BASE+0, //02-99 - NL_PROMPT_HUNDRED = NL_PROMPT_NUMBERS_BASE+100, //100,200 .. 900 - NL_PROMPT_THOUSAND = NL_PROMPT_NUMBERS_BASE+109, //1000 - NL_PROMPT_AND = NL_PROMPT_NUMBERS_BASE+110, - NL_PROMPT_MINUS = NL_PROMPT_NUMBERS_BASE+111, - NL_PROMPT_POINT = NL_PROMPT_NUMBERS_BASE+112, - NL_PROMPT_UNITS_BASE = 113, - NL_PROMPT_POINT_BASE = 165, //.0 - .9 -}; - -#if defined(VOICE) - -#if defined(CPUARM) - #define NL_PUSH_UNIT_PROMPT(p, u) nl_pushUnitPrompt((p), (u), id) -#else - #define NL_PUSH_UNIT_PROMPT(p, u) pushUnitPrompt((p), (u)) -#endif - -I18N_PLAY_FUNCTION(nl, pushUnitPrompt, int16_t number, uint8_t unitprompt) -{ -#if defined(CPUARM) - if (number == 1) - PUSH_UNIT_PROMPT(unitprompt, 0); - else - PUSH_UNIT_PROMPT(unitprompt, 1); -#else - unitprompt = NL_PROMPT_UNITS_BASE + unitprompt*2; - if (number == 1) - PUSH_NUMBER_PROMPT(unitprompt); - else - PUSH_NUMBER_PROMPT(unitprompt+1); -#endif -} - -I18N_PLAY_FUNCTION(nl, playNumber, getvalue_t number, uint8_t unit, uint8_t att) -{ - if (number < 0) { - PUSH_NUMBER_PROMPT(NL_PROMPT_MINUS); - number = -number; - } - -#if !defined(CPUARM) - if (unit) { - unit--; - convertUnit(number, unit); - if (IS_IMPERIAL_ENABLE()) { - if (unit == UNIT_DIST) { - unit = UNIT_FEET; - } - if (unit == UNIT_SPEED) { - unit = UNIT_KTS; - } - } - unit++; - } -#endif - - int8_t mode = MODE(att); - if (mode > 0) { -#if defined(CPUARM) - if (mode == 2) { - number /= 10; - } -#else - // we assume that we are PREC1 -#endif - div_t qr = div(number, 10); - if (qr.rem) { - PLAY_NUMBER(qr.quot, 0, 0); - PUSH_NUMBER_PROMPT(NL_PROMPT_POINT_BASE + qr.rem); - number = -1; - } - else { - number = qr.quot; - } - } - - int16_t tmp = number; - - if (number >= 1000) { - PLAY_NUMBER(number / 1000, 0, 0); - PUSH_NUMBER_PROMPT(NL_PROMPT_THOUSAND); - - number %= 1000; - if (number == 0) - number = -1; - } - if (number >= 100) { - PUSH_NUMBER_PROMPT(NL_PROMPT_HUNDRED + (number/100)-1); - number %= 100; - if (number == 0) - number = -1; - } - if (number >= 0) { - PUSH_NUMBER_PROMPT(NL_PROMPT_ZERO + number); - } - - if (unit) { - NL_PUSH_UNIT_PROMPT(tmp, unit); - } -} - -I18N_PLAY_FUNCTION(nl, playDuration, int seconds PLAY_DURATION_ATT) -{ - if (seconds == 0) { - PLAY_NUMBER(seconds, 0, 0); - return; - } - - if (seconds < 0) { - PUSH_NUMBER_PROMPT(NL_PROMPT_MINUS); - seconds = -seconds; - } - - uint8_t tmp = seconds / 3600; - seconds %= 3600; - if (tmp > 0 || IS_PLAY_TIME()) { - PLAY_NUMBER(tmp, UNIT_HOURS, 0); - } - - tmp = seconds / 60; - seconds %= 60; - if (tmp > 0) { - PLAY_NUMBER(tmp, UNIT_MINUTES, 0); - if (seconds > 0) - PUSH_NUMBER_PROMPT(NL_PROMPT_AND); - } - if (seconds > 0) { - PLAY_NUMBER(seconds, UNIT_SECONDS, 0); - } -} - -LANGUAGE_PACK_DECLARE(nl, "Nederlands"); - -#endif +/* + * Authors (alphabetical order) + * - Andre Bernet + * - Bertrand Songis + * - Jean-Pierre van Melis + * + * opentx is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "opentx.h" + +enum DutchPrompts { + NL_PROMPT_NUMBERS_BASE = 0, + NL_PROMPT_ZERO = NL_PROMPT_NUMBERS_BASE+0, //02-99 + NL_PROMPT_HUNDRED = NL_PROMPT_NUMBERS_BASE+100, //100,200 .. 900 + NL_PROMPT_THOUSAND = NL_PROMPT_NUMBERS_BASE+109, //1000 + NL_PROMPT_AND = NL_PROMPT_NUMBERS_BASE+110, + NL_PROMPT_MINUS = NL_PROMPT_NUMBERS_BASE+111, + NL_PROMPT_POINT = NL_PROMPT_NUMBERS_BASE+112, + NL_PROMPT_UNITS_BASE = 113, + NL_PROMPT_POINT_BASE = 165, //.0 - .9 +}; + +#if defined(VOICE) + +#if defined(CPUARM) + #define NL_PUSH_UNIT_PROMPT(p, u) nl_pushUnitPrompt((p), (u), id) +#else + #define NL_PUSH_UNIT_PROMPT(p, u) pushUnitPrompt((p), (u)) +#endif + +I18N_PLAY_FUNCTION(nl, pushUnitPrompt, int16_t number, uint8_t unitprompt) +{ +#if defined(CPUARM) + if (number == 1) + PUSH_UNIT_PROMPT(unitprompt, 0); + else + PUSH_UNIT_PROMPT(unitprompt, 1); +#else + unitprompt = NL_PROMPT_UNITS_BASE + unitprompt*2; + if (number == 1) + PUSH_NUMBER_PROMPT(unitprompt); + else + PUSH_NUMBER_PROMPT(unitprompt+1); +#endif +} + +I18N_PLAY_FUNCTION(nl, playNumber, getvalue_t number, uint8_t unit, uint8_t att) +{ + if (number < 0) { + PUSH_NUMBER_PROMPT(NL_PROMPT_MINUS); + number = -number; + } + +#if !defined(CPUARM) + if (unit) { + unit--; + convertUnit(number, unit); + if (IS_IMPERIAL_ENABLE()) { + if (unit == UNIT_DIST) { + unit = UNIT_FEET; + } + if (unit == UNIT_SPEED) { + unit = UNIT_KTS; + } + } + unit++; + } +#endif + + int8_t mode = MODE(att); + if (mode > 0) { +#if defined(CPUARM) + if (mode == 2) { + number /= 10; + } +#else + // we assume that we are PREC1 +#endif + div_t qr = div(number, 10); + if (qr.rem) { + PLAY_NUMBER(qr.quot, 0, 0); + PUSH_NUMBER_PROMPT(NL_PROMPT_POINT_BASE + qr.rem); + number = -1; + } + else { + number = qr.quot; + } + } + + int16_t tmp = number; + + if (number >= 1000) { + PLAY_NUMBER(number / 1000, 0, 0); + PUSH_NUMBER_PROMPT(NL_PROMPT_THOUSAND); + + number %= 1000; + if (number == 0) + number = -1; + } + if (number >= 100) { + PUSH_NUMBER_PROMPT(NL_PROMPT_HUNDRED + (number/100)-1); + number %= 100; + if (number == 0) + number = -1; + } + if (number >= 0) { + PUSH_NUMBER_PROMPT(NL_PROMPT_ZERO + number); + } + + if (unit) { + NL_PUSH_UNIT_PROMPT(tmp, unit); + } +} + +I18N_PLAY_FUNCTION(nl, playDuration, int seconds PLAY_DURATION_ATT) +{ + if (seconds == 0) { + PLAY_NUMBER(seconds, 0, 0); + return; + } + + if (seconds < 0) { + PUSH_NUMBER_PROMPT(NL_PROMPT_MINUS); + seconds = -seconds; + } + + uint8_t tmp = seconds / 3600; + seconds %= 3600; + if (tmp > 0 || IS_PLAY_TIME()) { + PLAY_NUMBER(tmp, UNIT_HOURS, 0); + } + + tmp = seconds / 60; + seconds %= 60; + if (tmp > 0) { + PLAY_NUMBER(tmp, UNIT_MINUTES, 0); + if (seconds > 0) + PUSH_NUMBER_PROMPT(NL_PROMPT_AND); + } + if (seconds > 0) { + PLAY_NUMBER(seconds, UNIT_SECONDS, 0); + } +} + +LANGUAGE_PACK_DECLARE(nl, "Nederlands"); + +#endif diff --git a/radio/util/maxvolume.cmd b/radio/util/maxvolume.cmd index 221ddafd7..b3b24c9cc 100644 --- a/radio/util/maxvolume.cmd +++ b/radio/util/maxvolume.cmd @@ -1,16 +1,16 @@ -echo off - - -echo Getting max amplitude.. -sox %1.wav -n stat -v 2> %1_apl.txt -Set /P apl_value= < %1_apl.txt - -echo Normalizing audio.. gain: %apl_value% -sox --show-progress -v %apl_value% %1.wav %1_norm.wav - -copy %1_norm.wav %1.wav - -echo Cleaning.. -del %1_norm.wav -del %1_apl.txt - +echo off + + +echo Getting max amplitude.. +sox %1.wav -n stat -v 2> %1_apl.txt +Set /P apl_value= < %1_apl.txt + +echo Normalizing audio.. gain: %apl_value% +sox --show-progress -v %apl_value% %1.wav %1_norm.wav + +copy %1_norm.wav %1.wav + +echo Cleaning.. +del %1_norm.wav +del %1_apl.txt + diff --git a/tools/eeprom_upgd_check/check.lua b/tools/eeprom_upgd_check/check.lua index 6a6ee194a..eaf1bb875 100644 --- a/tools/eeprom_upgd_check/check.lua +++ b/tools/eeprom_upgd_check/check.lua @@ -1,29 +1,29 @@ -local function checktable(actual, reference) - for k, v in pairs( actual ) do - if v == reference[k] then - print("OK ", k, v, reference[k]) - else - print("ISSUE ", k, v, reference[k]) - end - end -end - -local function run(event) - inputt= {name = "In1", source = 1, weight = 50, offset = 10, switch = 3} - mixt= {name = "Mix1", source = 1, weight = 50, offset = 10, curveType = 1, curveValue = 50, flightModes = 3, delayUp = 5, speedDown = 5, speedUp = 2, delayDown = 5, mixWarn = 1 , carryTrim = true , multiplex = 1, switch = 3} - outputt = {name = "Out1", min = -800, max = 800, offset = 10, ppmCenter = 10, symetrical = 1, revert = 1, switch = 3} - timert = {mode = 4, start = 0, countdownBeep = 2, persistent = 1, minuteBeep = true, value = 10 } - lst = {func = 2, v1 = 2, v2 = 2, v3 = 2, duration = 3, delay = 2, ["and"] = 2} - input = model.getInput(4,0) - mix = model.getMix(4,0) - output = model.getOutput(4) - ls = model.getLogicalSwitch(0) - timer = model.getTimer(0) - checktable(input,inputt) - checktable(mix, mixt) - checktable(output, outputt) - checktable(ls, lst) - checktable(timer, timert) - return 2 -end -return {run=run} +local function checktable(actual, reference) + for k, v in pairs( actual ) do + if v == reference[k] then + print("OK ", k, v, reference[k]) + else + print("ISSUE ", k, v, reference[k]) + end + end +end + +local function run(event) + inputt= {name = "In1", source = 1, weight = 50, offset = 10, switch = 3} + mixt= {name = "Mix1", source = 1, weight = 50, offset = 10, curveType = 1, curveValue = 50, flightModes = 3, delayUp = 5, speedDown = 5, speedUp = 2, delayDown = 5, mixWarn = 1 , carryTrim = true , multiplex = 1, switch = 3} + outputt = {name = "Out1", min = -800, max = 800, offset = 10, ppmCenter = 10, symetrical = 1, revert = 1, switch = 3} + timert = {mode = 4, start = 0, countdownBeep = 2, persistent = 1, minuteBeep = true, value = 10 } + lst = {func = 2, v1 = 2, v2 = 2, v3 = 2, duration = 3, delay = 2, ["and"] = 2} + input = model.getInput(4,0) + mix = model.getMix(4,0) + output = model.getOutput(4) + ls = model.getLogicalSwitch(0) + timer = model.getTimer(0) + checktable(input,inputt) + checktable(mix, mixt) + checktable(output, outputt) + checktable(ls, lst) + checktable(timer, timert) + return 2 +end +return {run=run} diff --git a/tools/eeprom_upgd_check/create.lua b/tools/eeprom_upgd_check/create.lua index bbeff9ca9..67d577bb8 100644 --- a/tools/eeprom_upgd_check/create.lua +++ b/tools/eeprom_upgd_check/create.lua @@ -1,14 +1,14 @@ -local function run(event) - inputt= {name = "In1", source = 1, weight = 50, offset = 10, switch = 3} - mixt= {name = "Mix1", source = 1, weight = 50, offset = 10, curveType = 1, curveValue = 50, flightModes = 3, delayUp = 5, speedDown = 5, speedUp = 2, delayDown = 5, mixWarn = 1 , carryTrim = true , multiplex = 1, switch = 3} - outputt = {name = "Out1", min = -800, max = 800, offset = 10, ppmCenter = 10, symetrical = 1, revert = 1, switch = 3} - timert = {mode = 4, start = 0, countdownBeep = 2, persistent = 1, minuteBeep = true, value = 10 } - lst = {func = 2, v1 = 2, v2 = 2, v3 = 2, duration = 3, delay = 2, ["and"] = 2} - model.insertInput(4,0,inputt) - model.insertMix(4,0,mixt) - model.setOutput(4, outputt) - model.setLogicalSwitch(0, lst) - model.setTimer(0, timert) - return 2 -end -return {run=run} +local function run(event) + inputt= {name = "In1", source = 1, weight = 50, offset = 10, switch = 3} + mixt= {name = "Mix1", source = 1, weight = 50, offset = 10, curveType = 1, curveValue = 50, flightModes = 3, delayUp = 5, speedDown = 5, speedUp = 2, delayDown = 5, mixWarn = 1 , carryTrim = true , multiplex = 1, switch = 3} + outputt = {name = "Out1", min = -800, max = 800, offset = 10, ppmCenter = 10, symetrical = 1, revert = 1, switch = 3} + timert = {mode = 4, start = 0, countdownBeep = 2, persistent = 1, minuteBeep = true, value = 10 } + lst = {func = 2, v1 = 2, v2 = 2, v3 = 2, duration = 3, delay = 2, ["and"] = 2} + model.insertInput(4,0,inputt) + model.insertMix(4,0,mixt) + model.setOutput(4, outputt) + model.setLogicalSwitch(0, lst) + model.setTimer(0, timert) + return 2 +end +return {run=run} From b5f5e64d95d0e7a9c0e9efd19b94321e5841a5bb Mon Sep 17 00:00:00 2001 From: reichi Date: Wed, 19 Apr 2017 10:55:48 +0200 Subject: [PATCH 147/203] Fix DS3231 RTC read/write on AR9X (#4819) --- radio/src/targets/sky9x/rtc_ds3231_driver.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/radio/src/targets/sky9x/rtc_ds3231_driver.cpp b/radio/src/targets/sky9x/rtc_ds3231_driver.cpp index 46af618af..656b074eb 100644 --- a/radio/src/targets/sky9x/rtc_ds3231_driver.cpp +++ b/radio/src/targets/sky9x/rtc_ds3231_driver.cpp @@ -21,14 +21,14 @@ #include "opentx.h" #include "i2c_driver.h" -#define DS3231_I2C_ADDR 0x68 +#define DS3231_I2C_CHIPID 0x68 void readRtc() { uint8_t buffer[7]; - uint8_t readBuffer[7]; + uint8_t address[]= {0}; gtm utm; - int res = i2cReadBuffer(DS3231_I2C_ADDR, readBuffer, 2, buffer, 7); + int res = i2cReadBuffer(DS3231_I2C_CHIPID, address, 1, buffer, 7); if (res != 0) return; @@ -46,7 +46,7 @@ void writeRtc(const gtm* ptr) { g_ms100 = 0; // start of next second begins now uint8_t buffer[7]; - uint8_t read_buffer[7]; + uint8_t address[]= {0}; buffer[0] = toBCD(ptr->tm_sec); buffer[1] = toBCD(ptr->tm_min); @@ -56,7 +56,7 @@ void writeRtc(const gtm* ptr) buffer[5] = toBCD(ptr->tm_mon + 1); uint8_t offset = ptr->tm_year >= 100 ? 100 : 0; buffer[6] = toBCD(ptr->tm_year - offset); - i2cWriteBuffer(DS3231_I2C_ADDR, read_buffer, 1, buffer, 7); + i2cWriteBuffer(DS3231_I2C_CHIPID, address, 1, buffer, 7); } void rtcSetTime(const struct gtm * t) From bc6ed93b0fdb8e67d6f5770d7fd945ed3fc6ce9f Mon Sep 17 00:00:00 2001 From: Sebastien Charpentier Date: Wed, 19 Apr 2017 10:57:31 +0200 Subject: [PATCH 148/203] Updated Frencht ranslation for "SimulatorMain". (#4817) --- companion/src/translations/companion_fr.ts | 395 ++++++++------------- 1 file changed, 140 insertions(+), 255 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 6a97bdd3c..d2019dd21 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -7343,7 +7343,6 @@ Mixage actif par défaut si non-renseigné. - Uknown error during Simulator startup. Erreur inconnue pendant le démarrage du simulateur. @@ -8568,59 +8567,59 @@ Mixage actif par défaut si non-renseigné. Le simulateur n'est pas encore disponible pour ce firmware - + Switch Inter - + Switch L'inter - + cannot be exported on this board! n'est pas supporté sur cette carte ! - + Source %1 cannot be exported on this board! La source %1 n'est pas supportée sur cette plateforme ! - + OpenTX only accepts %1 points in all curves OpenTX n'accepte que %1 points au maximum entre toutes les courbes - + OpenTx only accepts %1 points in all curves OpenTX n'accepte que %1 points au maximum entre toutes les courbes - - - - - - + + + + + + OpenTX on this board doesn't accept this function OpenTX ne supporte pas cette fonction sur cette carte - + OpenTX doesn't accept this telemetry protocol OpenTX ne supporte pas ce protocole de télémesure - - - + + + OpenTX doesn't accept this radio protocol OpenTX ne supporte pas ce protocole radio - + OpenTX doesn't allow this number of channels OpenTX ne supporte pas ce nombre de voies @@ -8809,79 +8808,6 @@ L'équipe OpenTX. Select SD Card Image Folder Slelectionnez le répertoire image carte SD - - - Available profiles: - Profils disponibles: - - - - ID: - - - - - Name: - Nom: - - - - Available radios: - Radio disponibles: - - - - WARNING: couldn't initialize SDL: -%1 - ATTENTION: erreur initialisation SDL: -%1 - - - - ERROR: No simulator libraries available. - ERREUR: pas de simulateur disponible. - - - - Radio profile ID or Name to use for simulator. - Nom du profil radio pour le simulateur. - - - - Radio type to simulate (usually defined in profile). - Type de radio à simuler (souvent défini dans le profil). - - - - show this help text - afficher ce texte d'aide - - - - Usage: simulator [OPTION]... [EEPROM.BIN FILE OR DATA FOLDER] - Utilisation: simulator [OPTION]... [EEPROM.BIN FICHIER OUT REPERTOIRE DE DONNER] - - - - Options: - - - - - ERROR: Couldn't start simulator, missing radio/profile/data file/folder. - Profile ID: [%1]; Radio ID: [%2]; -Data File: [%3] - ERREUR : Impossible de démarer le simulateur, radio/profile/fichier de données/répertoire manquant. - Profil ID: [%1]; Radio ID: [%2]; -Fichier de Données: [%3] - - - - ERROR: Radio profile or simulator firmware not found. -Profile ID: [%1]; Radio ID: [%2] - ERREUR: Profil radio ou firmware du simulateur non trouvé -Profil ID: [%1]; Radio ID: [%2] - Error reading %1: %2 @@ -8997,170 +8923,6 @@ Profil ID: [%1]; Radio ID: [%2] Erreur de conversion du champ %1 - - QxtCommandOptions - - - sets the application GUI style - Définir le thème graphique de l'application - - - - sets the application stylesheet - Définir le style des feuilles de l'application - - - - restores the application from an earlier session - restaure l'application depuis la dernière session - - - - displays debugging information about widgets - affiche les infos de débogage sur les widgets - - - - use right-to-left layout - utilise la disposition de droite-à-gauche - - - - never grab the mouse or keyboard - ne jamais utiliser la souris ou le clavier - - - - grab the mouse/keyboard even in a debugger - utiliser la souris ou le clavier même en mode débogage - - - - run in synchronous mode for debugging - exécuter en mode synchrone pour le débogage - - - - use Direct3D by default - utiliser Direct3D par défaut - - - - sets the X11 display - sélectionner l'affichage X11 - - - - sets the geometry of the first window - définir la taille de la 1ère fenêtre - - - - sets the default font - définir la police par défaut - - - - sets the default background color - définir la couleur par défaut de l'arrière plan - - - - sets the default foreground color - définir la couleur par défaut du premier plan - - - - sets the default button color - définir la couleur par défaut des boutons - - - - sets the application name - définir le nom de l'application - - - - sets the application title - définir le titre de l'application - - - - sets the X11 visual type - définir le visuel de l'affichage X11 - - - - limit the number of colors on an 8-bit display - limiter le nombre de couleur sur un écran 8-bit - - - - use a private color map - utiliser un code couleur personnel - - - - sets the input method server - définir la méthode d'entrée du serveur - - - - disable the X Input Method - désactiver la méthode d'entrée X - - - - sets the style used by the input method - définir le style utilisé pour la méthode d'entrée - - - - - option "%1" not found - option "%1" introuvable - - - - Short options cannot have optional parameters - Les options courtes ne peuvent pas avoir de paramètres optionnels - - - - positional() called before parse() - positional() appelé avant parse() - - - - unrecognized() called before parse() - unrecognized() appelé avant parse() - - - - count() called before parse() - count() appelé avant parse() - - - - value() called before parse() - value() appelé avant parse() - - - - parameters() called before parse() - parameters() appelé avant parse() - - - - unrecognized parameters: - paramètres inconnus: - - - - %1 requires a parameter - %1 nécessite un paramètre - - RadioKnobWidget @@ -9710,6 +9472,129 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo + + SimulatorMain + + + Available profiles: + Profils disponibles: + + + + ID: + + + + + Name: + Nom: + + + + Available radios: + Radio disponibles: + + + + Radio profile ID or Name to use for simulator. + ID ou nom du profil radio pour le simulateur. + + + + profile + profil + + + + Radio type to simulate (usually defined in profile). + Type de radio à simuler (souvent défini dans le profil). + + + + radio + + + + + Directory containing the SD card image to use. The default is configured in the chosen Radio Profile. + Répertoire contenant l'image de la carte SD. La valeur par défaut est configurée dans le profil radio sélectionné. + + + + path + chemin + + + + Data source type to use (applicable to Horus only). One of: + Type de source de données à utiliser (applicable uniquement à la Horus). Un des: + + + + type + + + + + data-source + source-données + + + + Radio data (.bin/.eeprom/.otx) image file to use OR data folder path (for Horus-style radios). +NOTE: any existing EEPROM data incompatible with the selected radio type may be overwritten! + Fichier de données utilisé (.bin/.eeprom/.otx) OU chemin du répertoire de données (pour les radios de type Horus). +NOTE: toutes les données EEPROM existantes non compatible avec le type de radio sélectionné peuvent être écrasées ! + + + + [data-source] + [source-données] + + + + Error: Profile ID %1 was not found. + Erreur: ID Profil %1 non trouvé. + + + + Unrecognized startup data source type: %1 + Type de données source non reconnue au démarrage: %1 + + + + WARNING: couldn't initialize SDL: +%1 + ATTENTION: erreur initialisation SDL: +%1 + + + + ERROR: No simulator libraries available. + ERREUR: pas de simulateur disponible. + + + + ERROR: Couldn't start simulator, missing radio/profile/data file/folder. + Profile ID: [%1]; Radio ID: [%2]; +Data File: [%3] + ERREUR : Impossible de démarer le simulateur, radio/profile/fichier de données/répertoire manquant. + Profil ID: [%1]; Radio ID: [%2]; +Fichier de Données: [%3] + + + + ERROR: Radio profile or simulator firmware not found. +Profile ID: [%1]; Radio ID: [%2] + ERREUR: Profil radio ou firmware du simulateur non trouvé +Profil ID: [%1]; Radio ID: [%2] + + + + Uknown error during Simulator startup. + Erreur inconnue pendant le démarrage du simulateur. + + SimulatorMainWindow From 902473fe6f352536abfa60df950dbb2c41c35753 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Thu, 20 Apr 2017 09:39:44 +0200 Subject: [PATCH 149/203] Update --- DONATIONS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index 92af6bd87..a7993c76e 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1173,3 +1173,4 @@ Nektarios Ntikmpasanis Derek Gates John Alsbrooks Jürgen Deininger +Bruce Jones From ea5401084c420ddbab3eb0fb11ac44a7eada224c Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Sat, 22 Apr 2017 20:50:50 +0200 Subject: [PATCH 150/203] Update DONATIONS.txt --- DONATIONS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index a7993c76e..30d68fe03 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1174,3 +1174,4 @@ Derek Gates John Alsbrooks Jürgen Deininger Bruce Jones +Meinhard Schöll From fbc3bac6d3c384485d3250ac0240a609b721b54b Mon Sep 17 00:00:00 2001 From: 3djc Date: Sun, 23 Apr 2017 10:10:43 +0200 Subject: [PATCH 151/203] Review handling of combine INTERNAL_PPM and MULTIMODULE (#4826) * First attempt * Fix * Review IS_INTERNAL_MODULE_ENABLED() macro --- radio/src/dataconstants.h | 4 ++++ radio/src/gui/212x64/model_setup.cpp | 18 ++++++++---------- radio/src/telemetry/multi.cpp | 2 +- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/radio/src/dataconstants.h b/radio/src/dataconstants.h index 3a01f6b6b..c41c8ee1d 100644 --- a/radio/src/dataconstants.h +++ b/radio/src/dataconstants.h @@ -297,7 +297,11 @@ enum BeeperMode { #endif #if defined(PCBTARANIS) || defined(PCBHORUS) +#if defined(TARANIS_INTERNAL_PPM) + #define IS_INTERNAL_MODULE_ENABLED() (!(g_model.moduleData[INTERNAL_MODULE].rfProtocol == RF_PROTO_OFF && g_model.moduleData[INTERNAL_MODULE].type == MODULE_TYPE_XJT) && (g_model.moduleData[INTERNAL_MODULE].type != MODULE_TYPE_NONE)) +#else #define IS_INTERNAL_MODULE_ENABLED() (g_model.moduleData[INTERNAL_MODULE].rfProtocol != RF_PROTO_OFF) +#endif #elif defined(PCBSKY9X) #define IS_INTERNAL_MODULE_ENABLED() (false) #endif diff --git a/radio/src/gui/212x64/model_setup.cpp b/radio/src/gui/212x64/model_setup.cpp index df041161c..4156dc5ee 100644 --- a/radio/src/gui/212x64/model_setup.cpp +++ b/radio/src/gui/212x64/model_setup.cpp @@ -230,15 +230,12 @@ int getSwitchWarningsCount() return count; } -#if !defined(TARANIS_INTERNAL_PPM) - #define INTERNAL_MODULE_MODE_ROWS 0 // (OFF / RF protocols) -#else - #define INTERNAL_MODULE_MODE_ROWS (IS_MODULE_XJT(INTERNAL_MODULE) ? (uint8_t)1 : (uint8_t)0) // Module type + RF protocols -#endif #if defined(TARANIS_INTERNAL_PPM) #define IF_INTERNAL_MODULE_ON(x) (g_model.moduleData[INTERNAL_MODULE].type == MODULE_TYPE_NONE ? HIDDEN_ROW : (uint8_t)(x)) + #define INTERNAL_MODULE_MODE_ROWS (IS_MODULE_XJT(INTERNAL_MODULE) ? (uint8_t)1 : (uint8_t)0) // Module type + RF protocols #else #define IF_INTERNAL_MODULE_ON(x) (g_model.moduleData[INTERNAL_MODULE].rfProtocol == RF_PROTO_OFF ? HIDDEN_ROW : (uint8_t)(x)) + #define INTERNAL_MODULE_MODE_ROWS 0 // (OFF / RF protocols) #endif #define IF_EXTERNAL_MODULE_ON(x) (g_model.moduleData[EXTERNAL_MODULE].type == MODULE_TYPE_NONE ? HIDDEN_ROW : (uint8_t)(x)) #define IF_EXTERNAL_MODULE_XJT(x) (IS_MODULE_XJT(EXTERNAL_MODULE) ? (uint8_t)x : HIDDEN_ROW) @@ -283,15 +280,16 @@ void menuModelSetup(event_t event) IF_INTERNAL_MODULE_ON(IS_MODULE_XJT(INTERNAL_MODULE) ? (HAS_RF_PROTOCOL_MODELINDEX(g_model.moduleData[INTERNAL_MODULE].rfProtocol) ? (uint8_t)2 : (uint8_t)1) : (IS_MODULE_PPM(INTERNAL_MODULE) ? (uint8_t)1 : HIDDEN_ROW)), IF_INTERNAL_MODULE_ON((IS_MODULE_XJT(INTERNAL_MODULE)) ? FAILSAFE_ROWS(INTERNAL_MODULE) : HIDDEN_ROW), LABEL(ExternalModule), - (IS_MODULE_XJT(EXTERNAL_MODULE) || IS_MODULE_DSM2(EXTERNAL_MODULE) || IS_MODULE_MULTIMODULE(EXTERNAL_MODULE)) ? (uint8_t)1 : (uint8_t)0, + EXTERNAL_MODULE_MODE_ROWS, MULTIMODULE_STATUS_ROW EXTERNAL_MODULE_CHANNELS_ROWS, - (IS_MODULE_XJT(EXTERNAL_MODULE) && !HAS_RF_PROTOCOL_MODELINDEX(g_model.moduleData[EXTERNAL_MODULE].rfProtocol)) ? (uint8_t)1 : (IS_MODULE_PPM(EXTERNAL_MODULE) || IS_MODULE_XJT(EXTERNAL_MODULE) || IS_MODULE_DSM2(EXTERNAL_MODULE) || IS_MODULE_MULTIMODULE(EXTERNAL_MODULE)) ? (uint8_t)2 : HIDDEN_ROW, - IF_EXTERNAL_MODULE_XJT(FAILSAFE_ROWS(EXTERNAL_MODULE)), + (IS_MODULE_XJT(EXTERNAL_MODULE) && !HAS_RF_PROTOCOL_FAILSAFE(g_model.moduleData[EXTERNAL_MODULE].rfProtocol)) ? (uint8_t)1 : (IS_MODULE_PPM(EXTERNAL_MODULE) || IS_MODULE_XJT(EXTERNAL_MODULE) || IS_MODULE_DSM2(EXTERNAL_MODULE) || IS_MODULE_MULTIMODULE(EXTERNAL_MODULE)) ? (uint8_t)2 : HIDDEN_ROW, + FAILSAFE_ROWS(EXTERNAL_MODULE), MULTIMODULE_MODULE_ROWS LABEL(Trainer), 0, TRAINER_CHANNELS_ROWS(), IF_TRAINER_ON(2)}); #else - MENU_TAB({ 0, 0, TIMERS_ROWS, TOPLCD_ROWS 0, 1, 0, 0, LABEL(Throttle), 0, 0, 0, LABEL(PreflightCheck), 0, 0, SW_WARN_ITEMS(), POT_WARN_ITEMS(), - NAVIGATION_LINE_BY_LINE|(NUM_STICKS+NUM_POTS+NUM_SLIDERS+NUM_ROTARY_ENCODERS-1), 0, + MENU_TAB({ 0, 0, TIMERS_ROWS, TOPLCD_ROWS 0, 1, 0, 0, + LABEL(Throttle), 0, 0, 0, + LABEL(PreflightCheck), 0, 0, SW_WARN_ITEMS(), POT_WARN_ITEMS(), NAVIGATION_LINE_BY_LINE|(NUM_STICKS+NUM_POTS+NUM_SLIDERS+NUM_ROTARY_ENCODERS-1), 0, LABEL(InternalModule), INTERNAL_MODULE_MODE_ROWS, INTERNAL_MODULE_CHANNELS_ROWS, diff --git a/radio/src/telemetry/multi.cpp b/radio/src/telemetry/multi.cpp index 2c9596de6..86fd04210 100644 --- a/radio/src/telemetry/multi.cpp +++ b/radio/src/telemetry/multi.cpp @@ -147,7 +147,7 @@ void MultiModuleStatus::getStatusString(char *statusText) { if (get_tmr10ms() - lastUpdate > 200) { #if defined(PCBTARANIS) || defined(PCBHORUS) - if (g_model.moduleData[INTERNAL_MODULE].rfProtocol != RF_PROTO_OFF) + if (IS_INTERNAL_MODULE_ENABLED()) strcpy(statusText, STR_DISABLE_INTERNAL); else #endif From 1ad8769fff12bd471fb9ba080e01925df1be5d8b Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Sun, 23 Apr 2017 10:11:01 +0200 Subject: [PATCH 152/203] [Horus] Vector table updated (#4842) --- radio/src/targets/horus/CMakeLists.txt | 2 +- ...32f40_41xxx.s => startup_stm32f42_43xxx.s} | 38 ++++++++++++++++++- 2 files changed, 38 insertions(+), 2 deletions(-) rename radio/src/targets/horus/{startup_stm32f40_41xxx.s => startup_stm32f42_43xxx.s} (94%) diff --git a/radio/src/targets/horus/CMakeLists.txt b/radio/src/targets/horus/CMakeLists.txt index f7fc600d6..cb480b3b7 100644 --- a/radio/src/targets/horus/CMakeLists.txt +++ b/radio/src/targets/horus/CMakeLists.txt @@ -118,7 +118,7 @@ set(FIRMWARE_TARGET_SRC backlight_driver.cpp pwr_driver.cpp sdram_driver.c - startup_stm32f40_41xxx.s + startup_stm32f42_43xxx.s ) if(PCB STREQUAL X12S) set(FIRMWARE_TARGET_SRC diff --git a/radio/src/targets/horus/startup_stm32f40_41xxx.s b/radio/src/targets/horus/startup_stm32f42_43xxx.s similarity index 94% rename from radio/src/targets/horus/startup_stm32f40_41xxx.s rename to radio/src/targets/horus/startup_stm32f42_43xxx.s index 899b1ab45..e87226bf2 100644 --- a/radio/src/targets/horus/startup_stm32f40_41xxx.s +++ b/radio/src/targets/horus/startup_stm32f42_43xxx.s @@ -245,7 +245,16 @@ g_pfnVectors: .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ - + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. @@ -526,4 +535,31 @@ g_pfnVectors: .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ From 9193604aff16e0d6dd3bcf643cdd989f4b444707 Mon Sep 17 00:00:00 2001 From: 3djc Date: Sun, 23 Apr 2017 12:38:50 +0200 Subject: [PATCH 153/203] X7 : fix calibration interuption (#4835) * Fix 4833 * Less worse fix ? * Trying something else --- radio/src/gui/128x64/navigation.cpp | 6 +++--- radio/src/gui/128x64/radio_calibration.cpp | 9 ++++----- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/radio/src/gui/128x64/navigation.cpp b/radio/src/gui/128x64/navigation.cpp index a9d40ad65..16fd60f5b 100644 --- a/radio/src/gui/128x64/navigation.cpp +++ b/radio/src/gui/128x64/navigation.cpp @@ -575,7 +575,7 @@ void check(event_t event, uint8_t curr, const MenuHandlerFunc * menuTab, uint8_t } break; #endif - + case EVT_KEY_LONG(KEY_PAGE): if (curr > 0) cc = curr - 1; @@ -833,7 +833,7 @@ void check(event_t event, uint8_t curr, const MenuHandlerFunc *menuTab, uint8_t if (menuTab) { uint8_t attr = 0; - + if (l_posVert==0 && !menuCalibrationState) { attr = INVERS; @@ -1007,7 +1007,7 @@ void check(event_t event, uint8_t curr, const MenuHandlerFunc *menuTab, uint8_t INC(l_posHorz, 0, maxcol); break; #endif - + #if !defined(PCBX7) case EVT_KEY_REPT(KEY_DOWN): if (!IS_ROTARY_RIGHT(event) && l_posVert==maxrow) break; diff --git a/radio/src/gui/128x64/radio_calibration.cpp b/radio/src/gui/128x64/radio_calibration.cpp index 0029c5887..88d543055 100644 --- a/radio/src/gui/128x64/radio_calibration.cpp +++ b/radio/src/gui/128x64/radio_calibration.cpp @@ -2,7 +2,7 @@ * Copyright (C) OpenTX * * Based on code named - * th9x - http://code.google.com/p/th9x + * th9x - http://code.google.com/p/th9x * er9x - http://code.google.com/p/er9x * gruvin9x - http://code.google.com/p/gruvin9x * @@ -49,6 +49,7 @@ void menuCommonCalib(event_t event) switch (event) { case EVT_ENTRY: + case EVT_KEY_BREAK(KEY_EXIT): reusableBuffer.calib.state = CALIB_START; break; @@ -111,13 +112,11 @@ void menuCommonCalib(event_t event) void menuRadioCalibration(event_t event) { check_simple(event, MENU_RADIO_CALIBRATION, menuTabGeneral, DIM(menuTabGeneral), 0); - + TITLE(STR_MENUCALIBRATION); + menuCommonCalib(READ_ONLY() ? 0 : event); if (menuEvent) { menuCalibrationState = CALIB_START; } - - TITLE(STR_MENUCALIBRATION); - menuCommonCalib(READ_ONLY() ? 0 : event); } void menuFirstCalib(event_t event) From 591522c25a08f51adb5ed1bbf3c0764a42141bf1 Mon Sep 17 00:00:00 2001 From: 3djc Date: Sun, 23 Apr 2017 18:00:11 +0200 Subject: [PATCH 154/203] fix drawSource (#4843) --- radio/src/gui/128x64/lcd.cpp | 2 +- radio/src/gui/212x64/lcd.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/radio/src/gui/128x64/lcd.cpp b/radio/src/gui/128x64/lcd.cpp index 09673710a..7b1c9272d 100644 --- a/radio/src/gui/128x64/lcd.cpp +++ b/radio/src/gui/128x64/lcd.cpp @@ -873,7 +873,7 @@ void drawSource(coord_t x, coord_t y, uint32_t idx, LcdFlags att) } } #endif - else if (idx < MIXSRC_LAST_POT) { + else if (idx <= MIXSRC_LAST_POT) { idx = idx - MIXSRC_Rud; if (ZEXIST(g_eeGeneral.anaNames[idx])) { if (idx < MIXSRC_FIRST_POT-MIXSRC_Rud ) diff --git a/radio/src/gui/212x64/lcd.cpp b/radio/src/gui/212x64/lcd.cpp index 58154ea3c..c297095d1 100644 --- a/radio/src/gui/212x64/lcd.cpp +++ b/radio/src/gui/212x64/lcd.cpp @@ -607,7 +607,7 @@ void drawSource(coord_t x, coord_t y, uint32_t idx, LcdFlags att) } } - else if (idx < MIXSRC_LAST_POT) { + else if (idx <= MIXSRC_LAST_POT) { idx = idx-MIXSRC_Rud; if (ZEXIST(g_eeGeneral.anaNames[idx])) { if (idx < MIXSRC_FIRST_POT-MIXSRC_Rud ) From f9b7f567c3f3893b573b211b5bca6f43ba6dfa5c Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sun, 23 Apr 2017 21:09:00 -0400 Subject: [PATCH 155/203] [Companion] Fix Special/Global Functions action selector being reset for all lines when one line is deleted/cut/pasted (closes #4825). --- companion/src/modeledit/customfunctions.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/companion/src/modeledit/customfunctions.cpp b/companion/src/modeledit/customfunctions.cpp index 26e618ac9..514ea01d0 100644 --- a/companion/src/modeledit/customfunctions.cpp +++ b/companion/src/modeledit/customfunctions.cpp @@ -599,9 +599,8 @@ void CustomFunctionsPanel::fswPaste() CustomFunctionData *fsw = &functions[selectedFunction]; memcpy(fsw, fswData.constData(), sizeof(CustomFunctionData)); lock = true; - fswtchSwtch[selectedFunction]->setModel(rawSwitchItemModel); fswtchSwtch[selectedFunction]->setCurrentIndex(fswtchSwtch[selectedFunction]->findData(functions[selectedFunction].swtch.toValue())); - populateFuncCB(fswtchFunc[selectedFunction], functions[selectedFunction].func); + fswtchFunc[selectedFunction]->setCurrentIndex(fswtchFunc[selectedFunction]->findData(functions[selectedFunction].func)); populateGVmodeCB(fswtchGVmode[selectedFunction], functions[selectedFunction].adjustMode); populateFuncParamCB(fswtchParamT[selectedFunction], functions[selectedFunction].func, functions[selectedFunction].param, functions[selectedFunction].adjustMode); refreshCustomFunction(selectedFunction); @@ -615,9 +614,8 @@ void CustomFunctionsPanel::fswDelete() functions[selectedFunction].clear(); // TODO update switch and func lock = true; - fswtchSwtch[selectedFunction]->setModel(rawSwitchItemModel); fswtchSwtch[selectedFunction]->setCurrentIndex(fswtchSwtch[selectedFunction]->findData(functions[selectedFunction].swtch.toValue())); - populateFuncCB(fswtchFunc[selectedFunction], functions[selectedFunction].func); + fswtchFunc[selectedFunction]->setCurrentIndex(fswtchFunc[selectedFunction]->findData(functions[selectedFunction].func)); refreshCustomFunction(selectedFunction); lock = false; emit modified(); From faacf7f9c5ce81bde9a8e26165b8e94618770f1e Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Mon, 24 Apr 2017 18:00:45 +0200 Subject: [PATCH 156/203] Update DONATIONS.txt --- DONATIONS.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index 30d68fe03..57c208657 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -10,6 +10,7 @@ 3D Robotics RC Studio (monthly) Craft & Theory (monthly) +OpenTX Manuals by Lothar Thole Mario Sette Felice Baratto @@ -1175,3 +1176,5 @@ John Alsbrooks Jürgen Deininger Bruce Jones Meinhard Schöll +Rolf Lemb +Casey Layton From b790a844f1436f31f741cf157b010bbba48b2fcf Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Mon, 24 Apr 2017 19:33:06 +0200 Subject: [PATCH 157/203] Fixes #4806 --- companion/src/customizesplashdialog.cpp | 48 +++++++++---------- companion/src/customizesplashdialog.h | 10 ++-- companion/src/customizesplashdialog.ui | 4 +- companion/src/mainwindow.cpp | 3 +- companion/src/translations/companion_cs.ts | 2 +- companion/src/translations/companion_de.ts | 2 +- companion/src/translations/companion_en.ts | 2 +- companion/src/translations/companion_es.ts | 2 +- companion/src/translations/companion_fi.ts | 2 +- companion/src/translations/companion_fr.ts | 2 +- companion/src/translations/companion_he.ts | 2 +- companion/src/translations/companion_it.ts | 2 +- companion/src/translations/companion_nl.ts | 2 +- companion/src/translations/companion_pl.ts | 2 +- companion/src/translations/companion_pt.ts | 2 +- companion/src/translations/companion_ru.ts | 2 +- companion/src/translations/companion_sv.ts | 2 +- companion/src/translations/companion_zh_CN.ts | 2 +- 18 files changed, 46 insertions(+), 47 deletions(-) diff --git a/companion/src/customizesplashdialog.cpp b/companion/src/customizesplashdialog.cpp index 6aaa6c773..751bfe1df 100644 --- a/companion/src/customizesplashdialog.cpp +++ b/companion/src/customizesplashdialog.cpp @@ -150,11 +150,9 @@ bool Side::saveImage() return true; } -//*** customizeSplashDialog Class *** - -customizeSplashDialog::customizeSplashDialog(QWidget *parent) : +CustomizeSplashDialog::CustomizeSplashDialog(QWidget *parent) : QDialog(parent), - ui(new Ui::customizeSplashDialog) + ui(new Ui::CustomizeSplashDialog) { ui->setupUi(this); setWindowIcon(CompanionIcon("paintbrush.png")); @@ -185,22 +183,22 @@ customizeSplashDialog::customizeSplashDialog(QWidget *parent) : resize(0,0); } -customizeSplashDialog::~customizeSplashDialog() +CustomizeSplashDialog::~CustomizeSplashDialog() { delete ui; } -void customizeSplashDialog::on_copyRightToLeftButton_clicked() { +void CustomizeSplashDialog::on_copyRightToLeftButton_clicked() { left.copyImage(right); } -void customizeSplashDialog::on_copyLeftToRightButton_clicked() { +void CustomizeSplashDialog::on_copyLeftToRightButton_clicked() { right.copyImage(left); } -void customizeSplashDialog::on_leftLoadFwButton_clicked() {loadFirmware(left);} -void customizeSplashDialog::on_rightLoadFwButton_clicked() {loadFirmware(right);} -void customizeSplashDialog::loadFirmware(Side side) +void CustomizeSplashDialog::on_leftLoadFwButton_clicked() {loadFirmware(left);} +void CustomizeSplashDialog::on_rightLoadFwButton_clicked() {loadFirmware(right);} +void CustomizeSplashDialog::loadFirmware(Side side) { QString fileName = QFileDialog::getOpenFileName(this, tr("Open Firmware File"), g.flashDir(), FLASH_FILES_FILTER); if (!fileName.isEmpty()) { @@ -212,9 +210,9 @@ void customizeSplashDialog::loadFirmware(Side side) side.markSourceButton(); } -void customizeSplashDialog::on_leftLoadPictButton_clicked() {loadPicture(left);} -void customizeSplashDialog::on_rightLoadPictButton_clicked() {loadPicture(right);} -void customizeSplashDialog::loadPicture(Side side) +void CustomizeSplashDialog::on_leftLoadPictButton_clicked() {loadPicture(left);} +void CustomizeSplashDialog::on_rightLoadPictButton_clicked() {loadPicture(right);} +void CustomizeSplashDialog::loadPicture(Side side) { QString supportedImageFormats; for (int formatIndex = 0; formatIndex < QImageReader::supportedImageFormats().count(); formatIndex++) { @@ -232,9 +230,9 @@ void customizeSplashDialog::loadPicture(Side side) side.markSourceButton(); } -void customizeSplashDialog::on_leftLoadProfileButton_clicked() {loadProfile(left);} -void customizeSplashDialog::on_rightLoadProfileButton_clicked() {loadProfile(right);} -void customizeSplashDialog::loadProfile(Side side) +void CustomizeSplashDialog::on_leftLoadProfileButton_clicked() {loadProfile(left);} +void CustomizeSplashDialog::on_rightLoadProfileButton_clicked() {loadProfile(right);} +void CustomizeSplashDialog::loadProfile(Side side) { QString fileName=g.profile[g.id()].splashFile(); @@ -245,9 +243,9 @@ void customizeSplashDialog::loadProfile(Side side) side.markSourceButton(); } -void customizeSplashDialog::on_leftLibraryButton_clicked(){libraryButton_clicked(left);} -void customizeSplashDialog::on_rightLibraryButton_clicked(){libraryButton_clicked(right);} -void customizeSplashDialog::libraryButton_clicked( Side side ) +void CustomizeSplashDialog::on_leftLibraryButton_clicked(){libraryButton_clicked(left);} +void CustomizeSplashDialog::on_rightLibraryButton_clicked(){libraryButton_clicked(right);} +void CustomizeSplashDialog::libraryButton_clicked( Side side ) { QString fileName; SplashLibraryDialog *ld = new SplashLibraryDialog(this,&fileName); @@ -258,9 +256,9 @@ void customizeSplashDialog::libraryButton_clicked( Side side ) } } -void customizeSplashDialog::on_leftSaveButton_clicked(){saveButton_clicked(left);} -void customizeSplashDialog::on_rightSaveButton_clicked(){saveButton_clicked(right);} -void customizeSplashDialog::saveButton_clicked( Side side ) +void CustomizeSplashDialog::on_leftSaveButton_clicked(){saveButton_clicked(left);} +void CustomizeSplashDialog::on_rightSaveButton_clicked(){saveButton_clicked(right);} +void CustomizeSplashDialog::saveButton_clicked( Side side ) { if (side.saveImage()){ QMessageBox::information(this, tr("File Saved"), tr("The image was saved to the file %1").arg(*side.saveToFileName)); @@ -272,9 +270,9 @@ void customizeSplashDialog::saveButton_clicked( Side side ) QMessageBox::critical(this, tr("File Save Error"), tr("Failed to write image to %1").arg(*side.saveToFileName)); } -void customizeSplashDialog::on_leftInvertButton_clicked(){invertButton_clicked(left);} -void customizeSplashDialog::on_rightInvertButton_clicked(){invertButton_clicked(right);} -void customizeSplashDialog::invertButton_clicked(Side side) +void CustomizeSplashDialog::on_leftInvertButton_clicked(){invertButton_clicked(left);} +void CustomizeSplashDialog::on_rightInvertButton_clicked(){invertButton_clicked(right);} +void CustomizeSplashDialog::invertButton_clicked(Side side) { QImage image = side.imageLabel->pixmap()->toImage(); image.invertPixels(); diff --git a/companion/src/customizesplashdialog.h b/companion/src/customizesplashdialog.h index be77a8d8b..76419d9f8 100644 --- a/companion/src/customizesplashdialog.h +++ b/companion/src/customizesplashdialog.h @@ -26,7 +26,7 @@ namespace Ui { - class customizeSplashDialog; + class CustomizeSplashDialog; } const int WIDTH_TARANIS = 212; @@ -63,15 +63,15 @@ private: LCDFormat *format; }; -class customizeSplashDialog : public QDialog +class CustomizeSplashDialog : public QDialog { Q_OBJECT Side left; Side right; public: - explicit customizeSplashDialog(QWidget *parent = 0); - ~customizeSplashDialog(); + explicit CustomizeSplashDialog(QWidget *parent = 0); + ~CustomizeSplashDialog(); private slots: void on_leftLoadFwButton_clicked(); @@ -99,7 +99,7 @@ private: void saveButton_clicked( Side ); void invertButton_clicked( Side ); - Ui::customizeSplashDialog *ui; + Ui::CustomizeSplashDialog *ui; enum sideEnum { LEFT, RIGHT }; }; diff --git a/companion/src/customizesplashdialog.ui b/companion/src/customizesplashdialog.ui index 9a6971893..b9a4023cc 100644 --- a/companion/src/customizesplashdialog.ui +++ b/companion/src/customizesplashdialog.ui @@ -1,7 +1,7 @@ - customizeSplashDialog - + CustomizeSplashDialog + true diff --git a/companion/src/mainwindow.cpp b/companion/src/mainwindow.cpp index 443efa8ac..371710e60 100644 --- a/companion/src/mainwindow.cpp +++ b/companion/src/mainwindow.cpp @@ -780,7 +780,7 @@ void MainWindow::fwchangelog() void MainWindow::customizeSplash() { - customizeSplashDialog * dialog = new customizeSplashDialog(this); + CustomizeSplashDialog * dialog = new CustomizeSplashDialog(this); dialog->exec(); dialog->deleteLater(); } @@ -944,6 +944,7 @@ void MainWindow::updateMenus() readEepromAct->setEnabled(true); writeBUToRadioAct->setEnabled(true); readBUToFileAct->setEnabled(true); + editSplashAct->setDisabled(IS_HORUS(getCurrentBoard())); foreach (QAction * act, fileWindowActions) { if (!act) diff --git a/companion/src/translations/companion_cs.ts b/companion/src/translations/companion_cs.ts index 5b790bcbb..76b2edf5e 100644 --- a/companion/src/translations/companion_cs.ts +++ b/companion/src/translations/companion_cs.ts @@ -12337,7 +12337,7 @@ m2560 pro V4 desky - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_de.ts b/companion/src/translations/companion_de.ts index c47361872..4a3809d3e 100644 --- a/companion/src/translations/companion_de.ts +++ b/companion/src/translations/companion_de.ts @@ -12264,7 +12264,7 @@ Please only use this if you know what you are doing. There are no error checks - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_en.ts b/companion/src/translations/companion_en.ts index 86d33fe45..77eee80a3 100644 --- a/companion/src/translations/companion_en.ts +++ b/companion/src/translations/companion_en.ts @@ -12119,7 +12119,7 @@ m2560 for v4.1 boards - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_es.ts b/companion/src/translations/companion_es.ts index 93f12875d..2c962c910 100644 --- a/companion/src/translations/companion_es.ts +++ b/companion/src/translations/companion_es.ts @@ -12284,7 +12284,7 @@ m2560 para las placas v4.1 - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_fi.ts b/companion/src/translations/companion_fi.ts index ed14c66b1..f3c6d828d 100644 --- a/companion/src/translations/companion_fi.ts +++ b/companion/src/translations/companion_fi.ts @@ -12332,7 +12332,7 @@ m2560 joka on v4.1 lähettimessä - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index d2019dd21..a8c5a1e05 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -12248,7 +12248,7 @@ m2560 for v4.1 boards - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_he.ts b/companion/src/translations/companion_he.ts index dbd8e59f2..f9740f5df 100644 --- a/companion/src/translations/companion_he.ts +++ b/companion/src/translations/companion_he.ts @@ -10505,7 +10505,7 @@ m2560 for v4.1 boards - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_it.ts b/companion/src/translations/companion_it.ts index cf8f56fc0..0579e7c1b 100644 --- a/companion/src/translations/companion_it.ts +++ b/companion/src/translations/companion_it.ts @@ -12354,7 +12354,7 @@ m2560 per le schede v4.1 - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_nl.ts b/companion/src/translations/companion_nl.ts index 6df042131..3095fdd06 100644 --- a/companion/src/translations/companion_nl.ts +++ b/companion/src/translations/companion_nl.ts @@ -10499,7 +10499,7 @@ m2560 for v4.1 boards - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_pl.ts b/companion/src/translations/companion_pl.ts index bdc3e2999..0e214bd8e 100644 --- a/companion/src/translations/companion_pl.ts +++ b/companion/src/translations/companion_pl.ts @@ -12564,7 +12564,7 @@ m2560 dla platformy V4 - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_pt.ts b/companion/src/translations/companion_pt.ts index 580fca7d7..ef00f62a7 100644 --- a/companion/src/translations/companion_pt.ts +++ b/companion/src/translations/companion_pt.ts @@ -10505,7 +10505,7 @@ m2560 for v4.1 boards - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_ru.ts b/companion/src/translations/companion_ru.ts index 83edec0e9..148edd16c 100644 --- a/companion/src/translations/companion_ru.ts +++ b/companion/src/translations/companion_ru.ts @@ -10549,7 +10549,7 @@ m2560 for v4.1 boards - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor diff --git a/companion/src/translations/companion_sv.ts b/companion/src/translations/companion_sv.ts index ce8b77d04..f10bc161b 100644 --- a/companion/src/translations/companion_sv.ts +++ b/companion/src/translations/companion_sv.ts @@ -9622,7 +9622,7 @@ m2560 för v4.1-kort - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor Startbildsredigerare diff --git a/companion/src/translations/companion_zh_CN.ts b/companion/src/translations/companion_zh_CN.ts index 61a2d4b99..81adbfd3c 100644 --- a/companion/src/translations/companion_zh_CN.ts +++ b/companion/src/translations/companion_zh_CN.ts @@ -12595,7 +12595,7 @@ v4.1版电路板应为m2560 - customizeSplashDialog + CustomizeSplashDialog Transmitter Splash Screen Editor From c15a86dc19ccf09abaddb3654d5ad56907fc4c53 Mon Sep 17 00:00:00 2001 From: Martin Hotar Date: Mon, 24 Apr 2017 20:53:09 +0200 Subject: [PATCH 158/203] cz rtanslation fixes and mode sources aligned a bit -it fixes EN version as well (#4854) --- radio/src/gui/128x64/radio_setup.cpp | 2 +- radio/src/translations/cz.h.txt | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/radio/src/gui/128x64/radio_setup.cpp b/radio/src/gui/128x64/radio_setup.cpp index 9c6c6d429..60377c892 100644 --- a/radio/src/gui/128x64/radio_setup.cpp +++ b/radio/src/gui/128x64/radio_setup.cpp @@ -572,7 +572,7 @@ void menuRadioSetup(event_t event) case ITEM_SETUP_STICK_MODE: lcdDrawChar(2*FW, y, '1'+reusableBuffer.generalSettings.stickMode, attr); for (uint8_t i=0; i0) { CHECK_INCDEC_GENVAR(event, reusableBuffer.generalSettings.stickMode, 0, 3); diff --git a/radio/src/translations/cz.h.txt b/radio/src/translations/cz.h.txt index 67e630715..25928023d 100644 --- a/radio/src/translations/cz.h.txt +++ b/radio/src/translations/cz.h.txt @@ -718,7 +718,7 @@ #define TR_BLONBRIGHTNESS TR3(INDENT"Jas Zap.", INDENT"Jas Zap.", INDENT"Jas zapnutého LCD") #define TR_BLOFFBRIGHTNESS TR3(INDENT"Jas Vyp.", INDENT"Jas Vyp.", INDENT"Jas vypnutého LCD") #define TR_BLCOLOR INDENT "Barva" -#define TR_SPLASHSCREEN TR("úvodníLogo", "Zobrazit úvodní logo") +#define TR_SPLASHSCREEN TR("úvodní logo", "Zobrazit úvodní logo") #define TR_THROTTLEWARNING TR("* Plyn", INDENT "Kontrola plynu") #define TR_SWITCHWARNING TR("* Spínače", INDENT "Polohy spínačů") #define TR_POTWARNINGSTATE TR("* Pot&Slid.", INDENT "Kontrola Pot&Slid.") @@ -731,7 +731,7 @@ #define TR_STICKS "Páky" #define TR_POTS "Potenciometry" #define TR_SWITCHES "Spínače" -#define TR_SWITCHES_DELAY TR3("Přechod středu přepínače", "Přechod středu přepínače", "Přechod poloh přepínače") +#define TR_SWITCHES_DELAY TR3("Filtr přepínače", "Filtr přepínače", "Filtr poloh přepínače") #define TR_SLAVE "Podřízený" #define TR_MODESRC " Mód\006% Zdroj" #define TR_MULTIPLIER "Násobič" @@ -1058,8 +1058,8 @@ #define TR_EEBACKUP "Záloha EEPROM" #define TR_FACTORYRESET "Factory reset" #else -#define TR_EEBACKUP "\010[dlouze ENTER] zálohuje EEPROM" -#define TR_FACTORYRESET "\012[dlouze MENU]: Factory reset" +#define TR_EEBACKUP TR("[dlouze ENTER]: Záloha", "\010[dlouze ENTER] zálohuje EEPROM") +#define TR_FACTORYRESET TR("[dlouze MENU]: Fact.reset", "\012[dlouze MENU]: Factory reset") #endif #define TR_CONFIRMRESET "Smazat modely a nastavení?" #define TR_TO_MANY_LUA_SCRIPTS "Příliš mnoho skriptů!" From be20e906309fb64f87f5f0f3d5118724c1e08d7d Mon Sep 17 00:00:00 2001 From: 3djc Date: Tue, 25 Apr 2017 12:06:40 +0200 Subject: [PATCH 159/203] 3djc/gps display fixes (#4852) * Remove top GPS coord display on X7 sensor edit (not enough space for it) * Improve GPS coord display on X9 --- radio/src/gui/128x64/model_telemetry.cpp | 2 +- radio/src/gui/212x64/lcd.cpp | 2 +- radio/src/gui/212x64/view_telemetry.cpp | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/radio/src/gui/128x64/model_telemetry.cpp b/radio/src/gui/128x64/model_telemetry.cpp index 60f2ca9df..c6ac64e6a 100644 --- a/radio/src/gui/128x64/model_telemetry.cpp +++ b/radio/src/gui/128x64/model_telemetry.cpp @@ -231,7 +231,7 @@ void menuModelSensor(event_t event) SUBMENU(STR_MENUSENSOR, SENSOR_FIELD_MAX, {0, 0, sensor->type == TELEM_TYPE_CALCULATED ? (uint8_t)0 : (uint8_t)1, SENSOR_UNIT_ROWS, SENSOR_PREC_ROWS, SENSOR_PARAM1_ROWS, SENSOR_PARAM2_ROWS, SENSOR_PARAM3_ROWS, SENSOR_PARAM4_ROWS, SENSOR_AUTOOFFSET_ROWS, SENSOR_FILTER_ROWS, SENSOR_PERSISTENT_ROWS, 0 }); lcdDrawNumber(PSIZE(TR_MENUSENSOR)*FW+1, 0, s_currIdx+1, INVERS|LEFT); - drawSensorCustomValue(SENSOR_2ND_COLUMN, 0, s_currIdx, getValue(MIXSRC_FIRST_TELEM+3*s_currIdx), LEFT); + if (!isGPSSensor(s_currIdx+1)) drawSensorCustomValue(SENSOR_2ND_COLUMN, 0, s_currIdx, getValue(MIXSRC_FIRST_TELEM+3*s_currIdx), LEFT); int8_t sub = menuVerticalPosition; diff --git a/radio/src/gui/212x64/lcd.cpp b/radio/src/gui/212x64/lcd.cpp index c297095d1..2b53fd2ba 100644 --- a/radio/src/gui/212x64/lcd.cpp +++ b/radio/src/gui/212x64/lcd.cpp @@ -797,7 +797,7 @@ void drawGPSSensorValue(coord_t x, coord_t y, TelemetryItem & telemetryItem, Lcd } else { drawGPSCoord(x, y, telemetryItem.gps.latitude, "NS", att, false); - drawGPSCoord(lcdNextPos+FWNUM, y, telemetryItem.gps.longitude, "EW", att, false); + drawGPSCoord(lcdLastRightPos+2*FWNUM, y, telemetryItem.gps.longitude, "EW", att, false); } } diff --git a/radio/src/gui/212x64/view_telemetry.cpp b/radio/src/gui/212x64/view_telemetry.cpp index df78817c0..9820af59b 100644 --- a/radio/src/gui/212x64/view_telemetry.cpp +++ b/radio/src/gui/212x64/view_telemetry.cpp @@ -127,7 +127,8 @@ bool displayNumbersTelemetryScreen(FrSkyScreenData & screen) } } else if (field >= MIXSRC_FIRST_TELEM && isGPSSensor(1+(field-MIXSRC_FIRST_TELEM)/3) && telemetryItems[(field-MIXSRC_FIRST_TELEM)/3].isAvailable()) { - // we don't display GPS name, no space for it + // we don't display GPS name, no space for it, but we shift x by some pixel to allow it to fit on max coord + x -=2; } else { drawSource(pos[j], 1+FH+2*FH*i, field, 0); From 50cb102a348b8e83bab0c357961f5dacbe2821bb Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Tue, 25 Apr 2017 12:07:34 +0200 Subject: [PATCH 160/203] [MULTI] Fix fallback to Flysky and Spektrum telemetry without MULTI_TELEMETRY (#4851) --- radio/src/telemetry/multi.cpp | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/radio/src/telemetry/multi.cpp b/radio/src/telemetry/multi.cpp index 86fd04210..66fe58add 100644 --- a/radio/src/telemetry/multi.cpp +++ b/radio/src/telemetry/multi.cpp @@ -39,6 +39,7 @@ enum MultiBufferState : uint8_t { ReceivingMultiProtocol, ReceivingMultiStatus, SpektrumTelemetryFallback, + FrskyTelemetryFallback, FrskyTelemetryFallbackFirstByte, FrskyTelemetryFallbackNextBytes, FlyskyTelemetryFallback @@ -51,7 +52,7 @@ MultiBufferState guessProtocol() else if (g_model.moduleData[EXTERNAL_MODULE].getMultiProtocol(false) == MM_RF_PROTO_FS_AFHDS2A) return FlyskyTelemetryFallback; else - return FrskyTelemetryFallbackFirstByte; + return FrskyTelemetryFallback; } static void processMultiStatusPacket(const uint8_t *data) @@ -215,17 +216,25 @@ void processMultiTelemetryData(const uint8_t data) case NoProtocolDetected: if (data == 'M') { multiTelemetryBufferState = MultiFirstByteReceived; - } else if (data == 0x55 || data == 0x7e) { + } else if (data == 0xAA || data == 0x7e) { multiTelemetryBufferState = guessProtocol(); - if (multiTelemetryBufferState == FrskyTelemetryFallbackFirstByte) - processFrskyTelemetryData(data); + + // Process the first byte by the protocol + processMultiTelemetryData(data); } else { TRACE("[MP] invalid start byte 0x%02X", data); } break; + case FrskyTelemetryFallback: + multiTelemetryBufferState = FrskyTelemetryFallbackFirstByte; + processFrskyTelemetryData(data); + break; + case FrskyTelemetryFallbackFirstByte: + processFrskyTelemetryData(data); multiTelemetryBufferState = FrskyTelemetryFallbackNextBytes; + break; case FrskyTelemetryFallbackNextBytes: processFrskyTelemetryData(data); From 6dd8524ea5968c1978f715f13f79e4c6af655d2f Mon Sep 17 00:00:00 2001 From: 3djc Date: Tue, 25 Apr 2017 12:08:20 +0200 Subject: [PATCH 161/203] Differentiate message despite so little space :s (#4850) --- radio/src/io/frsky_sport.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/radio/src/io/frsky_sport.cpp b/radio/src/io/frsky_sport.cpp index 284668038..593570e24 100644 --- a/radio/src/io/frsky_sport.cpp +++ b/radio/src/io/frsky_sport.cpp @@ -203,8 +203,16 @@ const char * sportUpdatePowerOn(ModuleIndex module) if (!IS_FRSKY_SPORT_PROTOCOL()) { return TR("Not responding", "Not S.Port 2"); } - +#if defined(PCBX7) + if (IS_PCBREV_40()) { + return TR("Bottom pin no resp", "Bottom pin not responding"); + } + else { + return TR("Module pin no resp", "Module pin not responding"); + } +#else return TR("Not responding", "Module not responding"); +#endif } const char * sportUpdateReqVersion() From b0183efaf112f59b0135534f0964a01052fc98aa Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Tue, 25 Apr 2017 21:25:46 +0200 Subject: [PATCH 162/203] Fixes #4841 --- companion/src/eeprominterface.cpp | 14 ++++++++++++-- companion/src/radiodata.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/companion/src/eeprominterface.cpp b/companion/src/eeprominterface.cpp index d13b0e108..ae8bad2bc 100644 --- a/companion/src/eeprominterface.cpp +++ b/companion/src/eeprominterface.cpp @@ -552,8 +552,8 @@ QString RawSource::toString(const ModelData * model, const GeneralSettings * con result = QString(generalSettings->potName[genAryIdx]); else if (isSlider(&genAryIdx)) result = QString(generalSettings->sliderName[genAryIdx]); - else - result = QString(generalSettings->stickName[index]); + else if (isStick(&genAryIdx)) + result = QString(generalSettings->stickName[genAryIdx]); } if (result.isEmpty()) result = getCurrentFirmware()->getAnalogInputName(index);; @@ -608,6 +608,16 @@ QString RawSource::toString(const ModelData * model, const GeneralSettings * con } } +bool RawSource::isStick(int * stickIndex) const +{ + if (type == SOURCE_TYPE_STICK && index < getBoardCapability(getCurrentBoard(), Board::Sticks)) { + if (stickIndex) + *stickIndex = index; + return true; + } + return false; +} + bool RawSource::isPot(int * potsIndex) const { if (type == SOURCE_TYPE_STICK && diff --git a/companion/src/radiodata.h b/companion/src/radiodata.h index d04dbabd4..9fe15f7b9 100644 --- a/companion/src/radiodata.h +++ b/companion/src/radiodata.h @@ -231,6 +231,7 @@ class RawSource { } bool isTimeBased() const; + bool isStick(int * potsIndex = NULL) const; bool isPot(int * potsIndex = NULL) const; bool isSlider(int * sliderIndex = NULL) const; From 37155363ffc3613b742153dff78e36d75fc45443 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Wed, 26 Apr 2017 12:33:12 +0200 Subject: [PATCH 163/203] [TTS] gTTS method added --- tools/nightly22/tts.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/tools/nightly22/tts.py b/tools/nightly22/tts.py index 03780db49..aba07a4ac 100755 --- a/tools/nightly22/tts.py +++ b/tools/nightly22/tts.py @@ -22,21 +22,24 @@ import zipfile from tts_common import * board = "taranis" -lib_path = os.path.abspath(os.path.join('code', 'radio', 'util')) +SOURCE_DIRECTORY = os.path.dirname(os.path.realpath(__file__)) +lib_path = os.path.abspath(os.path.join(SOURCE_DIRECTORY, '..', '..', 'radio', 'util')) sys.path.append(lib_path) def generate(str, filename): - - command = "pico2wave -l=" + voice + " -w=output.wav \"" + str + "\"" + if 1: + output = "output.wav" + command = 'pico2wave -l=%s -w=%s ""' % (voice, output, str) + else: + output = "output.mp3" + command = 'gtts-cli -l %s -o %s "%s"' % (voice[:2], output, str) os.system(command.encode('utf-8')) - command = "sox output.wav " + filename + " reverse silence 1 0.1 0.1% reverse" + command = "sox %s %s reverse silence 1 0.1 0.1% reverse" % (output, filename) os.system(command.encode('utf-8')) ################################################################ if __name__ == "__main__": - - if "en" in sys.argv: from tts_en import systemSounds, sounds From c2a6a20fc1b6116fc8f8e1b579a6da6e2cf15a86 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Wed, 26 Apr 2017 13:13:55 +0200 Subject: [PATCH 164/203] [TTS] Fixes --- tools/nightly22/tts.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/nightly22/tts.py b/tools/nightly22/tts.py index aba07a4ac..4841981db 100755 --- a/tools/nightly22/tts.py +++ b/tools/nightly22/tts.py @@ -29,12 +29,12 @@ sys.path.append(lib_path) def generate(str, filename): if 1: output = "output.wav" - command = 'pico2wave -l=%s -w=%s ""' % (voice, output, str) + command = 'pico2wave -l=%s -w=%s "%s"' % (voice, output, str) else: output = "output.mp3" command = 'gtts-cli -l %s -o %s "%s"' % (voice[:2], output, str) os.system(command.encode('utf-8')) - command = "sox %s %s reverse silence 1 0.1 0.1% reverse" % (output, filename) + command = "sox %s -r 32000 %s reverse silence 1 0.1 0.1%% reverse" % (output, filename) os.system(command.encode('utf-8')) ################################################################ From c15922a9421230de2430a4b6743db3fe1a4f7325 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Wed, 26 Apr 2017 17:30:34 +0200 Subject: [PATCH 165/203] Update DONATIONS.txt --- DONATIONS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index 57c208657..7e104a9e6 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1178,3 +1178,4 @@ Bruce Jones Meinhard Schöll Rolf Lemb Casey Layton +Robert Bates From f10bad7abede1da688ad250cbb0cb667885b8d7a Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Wed, 26 Apr 2017 21:42:01 +0200 Subject: [PATCH 166/203] Proposal to fix #4831 (CZ TTS problem with PREC1 and units) (#4856) * Proposal to fix #4831 * Next fix for #4831 * Initiate some CZ docs * Some more structure, still a workframe * My attempt to help with #4831 * Update tts_doc_cz.md * copy/paste error * Update tts_doc_cz.md * missed one number/qr.quot * Cosmetics * Consistency in parameters order * Nearly complete doc * Cosmetics to facilitate coding for non CZ devs * Fix integer+unit, cosmetics * Update tts_doc Radians and Mililiters are Male gender * Radian and Millimeter are Male (so i've been told) * Cosmetics * Invers pushUnitPrompt parameters as per bsongis request --- radio/src/translations/tts_cz.cpp | 151 +++++++++++++----------------- radio/src/translations/tts_en.cpp | 10 +- radio/src/translations/tts_hu.cpp | 10 +- radio/src/translations/tts_it.cpp | 8 +- radio/src/translations/tts_nl.cpp | 10 +- radio/src/translations/tts_pl.cpp | 30 +++--- radio/src/translations/tts_se.cpp | 14 +-- radio/src/translations/tts_sk.cpp | 28 +++--- radio/util/tts_doc_cz.md | 84 +++++++++++++++++ 9 files changed, 206 insertions(+), 139 deletions(-) create mode 100644 radio/util/tts_doc_cz.md diff --git a/radio/src/translations/tts_cz.cpp b/radio/src/translations/tts_cz.cpp index 2f3428b7e..971888431 100644 --- a/radio/src/translations/tts_cz.cpp +++ b/radio/src/translations/tts_cz.cpp @@ -24,9 +24,9 @@ enum CzechPrompts { CZ_PROMPT_NUMBERS_BASE = 0, - CZ_PROMPT_NULA = CZ_PROMPT_NUMBERS_BASE+0, //0-99 - CZ_PROMPT_STO = CZ_PROMPT_NUMBERS_BASE+100, //100,200 .. 900 - CZ_PROMPT_TISIC = CZ_PROMPT_NUMBERS_BASE+109, //1000 + CZ_PROMPT_NULA = CZ_PROMPT_NUMBERS_BASE+0, // 0-99 + CZ_PROMPT_STO = CZ_PROMPT_NUMBERS_BASE+100, // 100,200 .. 900 + CZ_PROMPT_TISIC = CZ_PROMPT_NUMBERS_BASE+109, // 1000 CZ_PROMPT_TISICE = CZ_PROMPT_NUMBERS_BASE+110, CZ_PROMPT_JEDEN = CZ_PROMPT_NUMBERS_BASE+111, CZ_PROMPT_JEDNO = CZ_PROMPT_NUMBERS_BASE+112, @@ -36,45 +36,44 @@ enum CzechPrompts { CZ_PROMPT_CELYCH = CZ_PROMPT_NUMBERS_BASE+116, CZ_PROMPT_MINUS = CZ_PROMPT_NUMBERS_BASE+117, - CZ_PROMPT_UNITS_BASE = 118, //(jeden)volt,(dva)volty,(pet)voltu,(desetina)voltu - + CZ_PROMPT_UNITS_BASE = 118, // (jeden)volt,(dva)volty,(pet)voltu,(desetina)voltu }; #if defined(VOICE) #if defined(CPUARM) - #define CZ_PUSH_UNIT_PROMPT(p, u) cz_pushUnitPrompt((p), (u), id) + #define CZ_PUSH_UNIT_PROMPT(u, p) cz_pushUnitPrompt((u), (p), id) #else - #define CZ_PUSH_UNIT_PROMPT(p, u) pushUnitPrompt((p), (u)) + #define CZ_PUSH_UNIT_PROMPT(u, p) pushUnitPrompt((u), (p)) #endif -#define MUZSKY 0x80 -#define ZENSKY 0x81 -#define STREDNI 0x82 +#define MALE 0x80 +#define FEMALE 0x81 +#define NEUTRAL 0x82 -I18N_PLAY_FUNCTION(cz, pushUnitPrompt, int16_t number, uint8_t unitprompt) +I18N_PLAY_FUNCTION(cz, pushUnitPrompt, uint8_t unit, int16_t number) { #if defined(CPUARM) + TRACE("CZSAY unit:%d number:%d", unit, number); if (number == 1) - PUSH_UNIT_PROMPT(unitprompt, 0); + PUSH_UNIT_PROMPT(unit, 0); else if (number > 1 && number < 5) - PUSH_UNIT_PROMPT(unitprompt, 1); + PUSH_UNIT_PROMPT(unit, 1); else - PUSH_UNIT_PROMPT(unitprompt, 2); + PUSH_UNIT_PROMPT(unit, 2); #else - unitprompt = CZ_PROMPT_UNITS_BASE+((unitprompt-1)*4); + unitprompt = CZ_PROMPT_UNITS_BASE+((unit-1)*4); if (number == 1) - PUSH_NUMBER_PROMPT(unitprompt); + PUSH_NUMBER_PROMPT(unit); else if (number > 1 && number < 5) - PUSH_NUMBER_PROMPT(unitprompt+1); + PUSH_NUMBER_PROMPT(unit+1); else - PUSH_NUMBER_PROMPT(unitprompt+2); + PUSH_NUMBER_PROMPT(unit+2); #endif } I18N_PLAY_FUNCTION(cz, playNumber, getvalue_t number, uint8_t unit, uint8_t att) { - if (number < 0) { PUSH_NUMBER_PROMPT(CZ_PROMPT_MINUS); number = -number; @@ -105,88 +104,72 @@ I18N_PLAY_FUNCTION(cz, playNumber, getvalue_t number, uint8_t unit, uint8_t att) #else // we assume that we are PREC1 #endif - div_t qr = div((int)number, 10); - if (qr.rem) { - PLAY_NUMBER(qr.quot, 0, ZENSKY); - if (qr.quot == 0) - PUSH_NUMBER_PROMPT(CZ_PROMPT_CELA); - else - CZ_PUSH_UNIT_PROMPT(qr.quot, CZ_PROMPT_CELA); - PLAY_NUMBER(qr.rem, 0, ZENSKY); - PUSH_NUMBER_PROMPT(CZ_PROMPT_UNITS_BASE+((unit-1)*4)+3); - return; + div_t qr = div((int)number, 10); + if (qr.rem) { + PLAY_NUMBER(qr.quot, 0, FEMALE); + if (qr.quot < 2) { + PUSH_NUMBER_PROMPT(CZ_PROMPT_CELA); } - else - number = qr.quot; + else if (qr.quot > 1 && qr.quot < 5) { + PUSH_NUMBER_PROMPT(CZ_PROMPT_CELE); + } + else { + PUSH_NUMBER_PROMPT(CZ_PROMPT_CELYCH); + }; + PLAY_NUMBER(qr.rem, 0, FEMALE); +#if defined(CPUARM) + PUSH_UNIT_PROMPT(unit, 3); +#else + PUSH_NUMBER_PROMPT(CZ_PROMPT_UNITS_BASE+((unit-1)*4)+3); +#endif + return; + } + else { + number = qr.quot; + } } int16_t tmp = number; -#if defined(CPUARM) switch(unit) { - case 0: + case UNIT_RAW: break; - case 6: - case 8: - case 10: - case 14: - case 18: - case 21: - case 22: - case 23: - case 24: - case 25: - case 26: - att = ZENSKY; + case UNIT_FEET_PER_SECOND: + case UNIT_MPH: + case UNIT_FEET: + case UNIT_MAH: + case UNIT_RPMS: + case UNIT_FLOZ: + case UNIT_HOURS: + case UNIT_MINUTES: + case UNIT_SECONDS: + att = FEMALE; break; - case 13: - case 19: - att = STREDNI; + case UNIT_PERCENT: + case UNIT_G: + att = NEUTRAL; break; default: - att = MUZSKY; + att = MALE; break; } -#else - switch(unit) { - case 0: - break; - case 4: - case 10: - case 13: - case 14: - case 15: - case 16: - case 17: - case 18: - att = ZENSKY; - break; - case 8: - case 19: - att = STREDNI; - break; - default: - att = MUZSKY; - break; - } -#endif - if ((number == 1) && (att == MUZSKY)) { + if ((number == 1) && (att == MALE)) { PUSH_NUMBER_PROMPT(CZ_PROMPT_JEDEN); number = -1; } - - if ((number == 1) && (att == STREDNI)) { + + if ((number == 1) && (att == NEUTRAL)) { PUSH_NUMBER_PROMPT(CZ_PROMPT_JEDNO); number = -1; } - - if ((number == 2) && ((att == ZENSKY) || (att == STREDNI))) { + + if ((number == 2) && ((att == FEMALE) || (att == NEUTRAL))) { PUSH_NUMBER_PROMPT(CZ_PROMPT_DVE); number = -1; } - + if (number >= 1000) { - if (number >= 2000) + if (number >= 2000) PLAY_NUMBER(number / 1000, 0, 0); if (number >= 2000 && number < 5000) PUSH_NUMBER_PROMPT(CZ_PROMPT_TISICE); @@ -202,13 +185,13 @@ I18N_PLAY_FUNCTION(cz, playNumber, getvalue_t number, uint8_t unit, uint8_t att) if (number == 0) number = -1; } - + if (number >= 0) { PUSH_NUMBER_PROMPT(CZ_PROMPT_NULA+number); } if (unit) { - CZ_PUSH_UNIT_PROMPT(tmp, unit); + CZ_PUSH_UNIT_PROMPT(unit, tmp); } } @@ -222,17 +205,17 @@ I18N_PLAY_FUNCTION(cz, playDuration, int seconds PLAY_DURATION_ATT) uint8_t tmp = seconds / 3600; seconds %= 3600; if (tmp > 0 || IS_PLAY_TIME()) { - PLAY_NUMBER(tmp, UNIT_HOURS, ZENSKY); + PLAY_NUMBER(tmp, UNIT_HOURS, FEMALE); } tmp = seconds / 60; seconds %= 60; if (tmp > 0) { - PLAY_NUMBER(tmp, UNIT_MINUTES, ZENSKY); + PLAY_NUMBER(tmp, UNIT_MINUTES, FEMALE); } if (seconds > 0) { - PLAY_NUMBER(seconds, UNIT_SECONDS, ZENSKY); + PLAY_NUMBER(seconds, UNIT_SECONDS, FEMALE); } } diff --git a/radio/src/translations/tts_en.cpp b/radio/src/translations/tts_en.cpp index f52570731..15b4f7bd9 100644 --- a/radio/src/translations/tts_en.cpp +++ b/radio/src/translations/tts_en.cpp @@ -51,12 +51,12 @@ enum EnglishPrompts { #if defined(VOICE) #if defined(CPUARM) - #define EN_PUSH_UNIT_PROMPT(p, u) en_pushUnitPrompt((p), (u), id) + #define EN_PUSH_UNIT_PROMPT(u, p) en_pushUnitPrompt((u), (p), id) #else - #define EN_PUSH_UNIT_PROMPT(p, u) pushUnitPrompt((p), (u)) + #define EN_PUSH_UNIT_PROMPT(u, p) pushUnitPrompt((u), (p)) #endif -I18N_PLAY_FUNCTION(en, pushUnitPrompt, int16_t number, uint8_t unitprompt) +I18N_PLAY_FUNCTION(en, pushUnitPrompt, uint8_t unitprompt, int16_t number) { #if defined(CPUARM) if (number == 1) @@ -133,9 +133,9 @@ I18N_PLAY_FUNCTION(en, playNumber, getvalue_t number, uint8_t unit, uint8_t att) if (number >= 0) { PUSH_NUMBER_PROMPT(EN_PROMPT_ZERO + number); } - + if (unit) { - EN_PUSH_UNIT_PROMPT(tmp, unit); + EN_PUSH_UNIT_PROMPT(unit, tmp); } } diff --git a/radio/src/translations/tts_hu.cpp b/radio/src/translations/tts_hu.cpp index 9d9349d8a..ecf0549cc 100644 --- a/radio/src/translations/tts_hu.cpp +++ b/radio/src/translations/tts_hu.cpp @@ -51,12 +51,12 @@ enum HungarianPrompts { #if defined(VOICE) #if defined(CPUARM) - #define HU_PUSH_UNIT_PROMPT(p, u) hu_pushUnitPrompt((p), (u), id) + #define HU_PUSH_UNIT_PROMPT(u, p) hu_pushUnitPrompt((u), (p), id) #else - #define HU_PUSH_UNIT_PROMPT(p, u) pushUnitPrompt((p), (u)) + #define HU_PUSH_UNIT_PROMPT(u, p) pushUnitPrompt((u), (p)) #endif -I18N_PLAY_FUNCTION(hu, pushUnitPrompt, int16_t number, uint8_t unitprompt) +I18N_PLAY_FUNCTION(hu, pushUnitPrompt, uint8_t unitprompt, int16_t number) { #if defined(CPUARM) if (number == 1) @@ -133,9 +133,9 @@ I18N_PLAY_FUNCTION(hu, playNumber, getvalue_t number, uint8_t unit, uint8_t att) if (number >= 0) { PUSH_NUMBER_PROMPT(HU_PROMPT_ZERO + number); } - + if (unit) { - HU_PUSH_UNIT_PROMPT(tmp, unit); + HU_PUSH_UNIT_PROMPT(unit, tmp); } } diff --git a/radio/src/translations/tts_it.cpp b/radio/src/translations/tts_it.cpp index 7d5149fe1..ecac135af 100644 --- a/radio/src/translations/tts_it.cpp +++ b/radio/src/translations/tts_it.cpp @@ -63,12 +63,12 @@ enum ItalianPrompts { #if defined(VOICE) #if defined(CPUARM) - #define IT_PUSH_UNIT_PROMPT(p, u) it_pushUnitPrompt((p), (u), id) + #define IT_PUSH_UNIT_PROMPT(u, p) it_pushUnitPrompt((u), (p), id) #else - #define IT_PUSH_UNIT_PROMPT(p, u) pushUnitPrompt((p), (u)) + #define IT_PUSH_UNIT_PROMPT(u, p) pushUnitPrompt((u), (p)) #endif -I18N_PLAY_FUNCTION(it, pushUnitPrompt, int16_t number, uint8_t unitprompt) +I18N_PLAY_FUNCTION(it, pushUnitPrompt, uint8_t unitprompt, int16_t number) { #if defined(CPUARM) if (number == 1) @@ -173,7 +173,7 @@ I18N_PLAY_FUNCTION(it, playNumber, getvalue_t number, uint8_t unit, uint8_t att) } } if (unit) { - IT_PUSH_UNIT_PROMPT(orignumber, unit); + IT_PUSH_UNIT_PROMPT(unit, orignumber); } } diff --git a/radio/src/translations/tts_nl.cpp b/radio/src/translations/tts_nl.cpp index 170f945cf..e436723e5 100644 --- a/radio/src/translations/tts_nl.cpp +++ b/radio/src/translations/tts_nl.cpp @@ -38,12 +38,12 @@ enum DutchPrompts { #if defined(VOICE) #if defined(CPUARM) - #define NL_PUSH_UNIT_PROMPT(p, u) nl_pushUnitPrompt((p), (u), id) + #define NL_PUSH_UNIT_PROMPT(u, p) nl_pushUnitPrompt((u), (p), id) #else - #define NL_PUSH_UNIT_PROMPT(p, u) pushUnitPrompt((p), (u)) + #define NL_PUSH_UNIT_PROMPT(u, p) pushUnitPrompt((u), (p)) #endif -I18N_PLAY_FUNCTION(nl, pushUnitPrompt, int16_t number, uint8_t unitprompt) +I18N_PLAY_FUNCTION(nl, pushUnitPrompt, uint8_t unitprompt, int16_t number) { #if defined(CPUARM) if (number == 1) @@ -121,9 +121,9 @@ I18N_PLAY_FUNCTION(nl, playNumber, getvalue_t number, uint8_t unit, uint8_t att) if (number >= 0) { PUSH_NUMBER_PROMPT(NL_PROMPT_ZERO + number); } - + if (unit) { - NL_PUSH_UNIT_PROMPT(tmp, unit); + NL_PUSH_UNIT_PROMPT(unit, tmp); } } diff --git a/radio/src/translations/tts_pl.cpp b/radio/src/translations/tts_pl.cpp index 39ed2e93f..48cb5554f 100644 --- a/radio/src/translations/tts_pl.cpp +++ b/radio/src/translations/tts_pl.cpp @@ -68,16 +68,16 @@ enum PolishPrompts { #if defined(VOICE) #if defined(CPUARM) - #define PL_PUSH_UNIT_PROMPT(p, u) pl_pushUnitPrompt((p), (u), id) + #define PL_PUSH_UNIT_PROMPT(u, p) pl_pushUnitPrompt((u), (p), id) #else - #define PL_PUSH_UNIT_PROMPT(p, u) pushUnitPrompt((p), (u)) + #define PL_PUSH_UNIT_PROMPT(u, p) pushUnitPrompt((u), (p)) #endif #define MESKI 0x80 #define ZENSKI 0x81 #define NIJAKI 0x82 -I18N_PLAY_FUNCTION(pl, pushUnitPrompt, int16_t number, uint8_t unitprompt) +I18N_PLAY_FUNCTION(pl, pushUnitPrompt, uint8_t unitprompt, int16_t number) { #if defined(CPUARM) if (number == 1) @@ -146,13 +146,13 @@ I18N_PLAY_FUNCTION(pl, playNumber, getvalue_t number, uint8_t unit, uint8_t att) #else // we assume that we are PREC1 #endif - div_t qr = div((int)number, 10); + div_t qr = div((int)number, 10); if (qr.rem) { PLAY_NUMBER(qr.quot, 0, ZENSKI); if (qr.quot == 0) PUSH_NUMBER_PROMPT(PL_PROMPT_CALA); else - PL_PUSH_UNIT_PROMPT(qr.quot, PL_PROMPT_CALA); + PL_PUSH_UNIT_PROMPT(PL_PROMPT_CALA, qr.quot); PLAY_NUMBER(qr.rem, 0, ZENSKI); PUSH_NUMBER_PROMPT(PL_PROMPT_UNITS_BASE+((unit-1)*4)+3); return; @@ -163,7 +163,7 @@ I18N_PLAY_FUNCTION(pl, playNumber, getvalue_t number, uint8_t unit, uint8_t att) } int16_t tmp = number; - + switch(unit) { case 0: break; @@ -197,26 +197,26 @@ I18N_PLAY_FUNCTION(pl, playNumber, getvalue_t number, uint8_t unit, uint8_t att) PUSH_NUMBER_PROMPT(PL_PROMPT_JEDNA); number = -1; } - + if ((number == 1) && (att == NIJAKI)) { PUSH_NUMBER_PROMPT(PL_PROMPT_JEDNO); number = -1; } - + if ((number == 2) && (att == ZENSKI)) { PUSH_NUMBER_PROMPT(PL_PROMPT_DWIE); number = -1; } - + if (number >= 1000) { - if (number >= 2000) + if (number >= 2000) PLAY_NUMBER(number / 1000, 0, 0); if (number >= 2000 && number < 5000) PUSH_NUMBER_PROMPT(PL_PROMPT_TYSIACE); else if (number >= 5000) PUSH_NUMBER_PROMPT(PL_PROMPT_TYSIECY); - else + else PUSH_NUMBER_PROMPT(PL_PROMPT_TYSIAC); number %= 1000; @@ -229,21 +229,21 @@ I18N_PLAY_FUNCTION(pl, playNumber, getvalue_t number, uint8_t unit, uint8_t att) if (number == 0) number = -1; } - + if (number >= 0) { int test_2 =0; test_2 =number % 10; int ten=0; ten=(number - (number % 10))/10; if (att == ZENSKI && test_2==2 && ten >= 2 ) { - + PUSH_NUMBER_PROMPT(PL_PROMPT_DZIESIATKI_ZENSKIE+ten); - }else + }else PUSH_NUMBER_PROMPT(PL_PROMPT_ZERO+number); } if (unit) { - PL_PUSH_UNIT_PROMPT(tmp, unit); + PL_PUSH_UNIT_PROMPT(unit, tmp); } } diff --git a/radio/src/translations/tts_se.cpp b/radio/src/translations/tts_se.cpp index 025f529bf..27c1600a3 100644 --- a/radio/src/translations/tts_se.cpp +++ b/radio/src/translations/tts_se.cpp @@ -52,12 +52,12 @@ enum SwedishPrompts { #if defined(VOICE) #if defined(CPUARM) - #define SE_PUSH_UNIT_PROMPT(p, u) se_pushUnitPrompt((p), (u), id) + #define SE_PUSH_UNIT_PROMPT(u, p) se_pushUnitPrompt((u), (p), id) #else - #define SE_PUSH_UNIT_PROMPT(p, u) pushUnitPrompt((p), (u)) + #define SE_PUSH_UNIT_PROMPT(u, p) pushUnitPrompt((u), (p)) #endif -I18N_PLAY_FUNCTION(se, pushUnitPrompt, int16_t number, uint8_t unitprompt) +I18N_PLAY_FUNCTION(se, pushUnitPrompt, uint8_t unitprompt, int16_t number) { #if defined(CPUARM) if (number == 1) @@ -115,9 +115,9 @@ I18N_PLAY_FUNCTION(se, playNumber, getvalue_t number, uint8_t unit, uint8_t att) number = qr.quot; } } - + int16_t tmpNumber = number; - + if (number >= 1000) { PLAY_NUMBER(number / 1000, 0, 0); PUSH_NUMBER_PROMPT(SE_PROMPT_THOUSAND); @@ -134,9 +134,9 @@ I18N_PLAY_FUNCTION(se, playNumber, getvalue_t number, uint8_t unit, uint8_t att) if (number >= 0) { PUSH_NUMBER_PROMPT(SE_PROMPT_ZERO + number); } - + if (unit) { - SE_PUSH_UNIT_PROMPT(tmpNumber, unit); + SE_PUSH_UNIT_PROMPT(unit, tmpNumber); } } diff --git a/radio/src/translations/tts_sk.cpp b/radio/src/translations/tts_sk.cpp index 13f04a397..abfa77c9d 100644 --- a/radio/src/translations/tts_sk.cpp +++ b/radio/src/translations/tts_sk.cpp @@ -58,16 +58,16 @@ enum SlovakPrompts { #if defined(VOICE) #if defined(CPUARM) - #define SK_PUSH_UNIT_PROMPT(p, u) sk_pushUnitPrompt((p), (u), id) + #define SK_PUSH_UNIT_PROMPT(u, p) sk_pushUnitPrompt((u), (p), id) #else - #define SK_PUSH_UNIT_PROMPT(p, u) pushUnitPrompt((p), (u)) + #define SK_PUSH_UNIT_PROMPT(u, p) pushUnitPrompt((u), (p)) #endif #define MUZSKY 0x80 #define ZENSKY 0x81 #define STREDNI 0x82 -I18N_PLAY_FUNCTION(sk, pushUnitPrompt, int16_t number, uint8_t unitprompt) +I18N_PLAY_FUNCTION(sk, pushUnitPrompt, uint8_t unitprompt, int16_t number) { #if defined(CPUARM) if (number == 1) @@ -120,13 +120,13 @@ I18N_PLAY_FUNCTION(sk, playNumber, getvalue_t number, uint8_t unit, uint8_t att) #else // we assume that we are PREC1 #endif - div_t qr = div((int)number, 10); + div_t qr = div((int)number, 10); if (qr.rem) { PLAY_NUMBER(qr.quot, 0, ZENSKY); if (qr.quot == 0) PUSH_NUMBER_PROMPT(SK_PROMPT_CELA); else - SK_PUSH_UNIT_PROMPT(qr.quot, SK_PROMPT_CELA); + SK_PUSH_UNIT_PROMPT(SK_PROMPT_CELA, qr.quot); PLAY_NUMBER(qr.rem, 0, ZENSKY); PUSH_NUMBER_PROMPT(SK_PROMPT_UNITS_BASE+((unit-1)*4)+3); return; @@ -137,8 +137,8 @@ I18N_PLAY_FUNCTION(sk, playNumber, getvalue_t number, uint8_t unit, uint8_t att) } int16_t tmp = number; - -#if defined(CPUARM) + +#if defined(CPUARM) switch(unit) { case 0: break; @@ -189,20 +189,20 @@ I18N_PLAY_FUNCTION(sk, playNumber, getvalue_t number, uint8_t unit, uint8_t att) PUSH_NUMBER_PROMPT(SK_PROMPT_JEDEN); number = -1; } - + if ((number == 1) && (att == STREDNI)) { PUSH_NUMBER_PROMPT(SK_PROMPT_JEDNO); number = -1; } - + if ((number == 2) && ((att == ZENSKY) || (att == STREDNI))) { PUSH_NUMBER_PROMPT(SK_PROMPT_DVE); number = -1; } - - if (number >= 1000) { + + if (number >= 1000) { if (number >= 3000) - PLAY_NUMBER(number / 1000, 0, 0); + PLAY_NUMBER(number / 1000, 0, 0); if (number >= 2000 && number < 3000) PUSH_NUMBER_PROMPT(SK_PROMPT_DVETISIC); else @@ -218,13 +218,13 @@ I18N_PLAY_FUNCTION(sk, playNumber, getvalue_t number, uint8_t unit, uint8_t att) if (number == 0) number = -1; } - + if (number >= 0) { PUSH_NUMBER_PROMPT(SK_PROMPT_NULA+number); } if (unit) { - SK_PUSH_UNIT_PROMPT(tmp, unit); + SK_PUSH_UNIT_PROMPT(unit, tmp); } } diff --git a/radio/util/tts_doc_cz.md b/radio/util/tts_doc_cz.md new file mode 100644 index 000000000..5aac5660e --- /dev/null +++ b/radio/util/tts_doc_cz.md @@ -0,0 +1,84 @@ +The purpose of this document is to document the principle of TTS for CZ languages to non CZ speaker, with a strict focus on OpenTX TTS + +## Large 'multiparts' numbers +This is for numbers requiring assembly of basic number blocks, like 110 in english : `ONE` `HUNDRED` `TEN` + +## Plural units forms + +4 forms of plural exist in otx cz tts, bellow is the exemple for volts + +`(u"volt", u"volt0"), (u"volty", u"volt1"), (u"voltů", u"volt2"),(u"voltu", u"volt3")` + +In this document, we will use unit0 to unit3 to describe those 4 variations + +## Interger numbers with unit + +The number takes a from like X UNIT + +#### "one ..." +The number "one" has 3 gender depending on the unit F/M/N +The forms are "jedna","jeden", "jedno" + +See unit table bellow to find out wich gender of one should be used + +unit0 is used with the 3 gender of one. + +#### "two ..." +The number "two" has 3 gender depending on the unit +The forms are "dva","dvě" + +See unit table bellow to find out wich gender of two should be used + +unit1 is used with the 2 gender of two. + +### "tree to five" + +unit1 is used + +### "five and more" + +unit2 is used + + +## decimal numbers with unit +X.Y UNIT +In this case unit is unit3. X and Y is allways FEM. + +"point" has three forms depending on the value of X : +0 and 1 : "celá" +2, 3 , 4 : "celé" +5 :"celých" + +Note : opentx audio only deals with PREC1 numbers, so Y can only be integer 1 to 9 + +# Unit table + +| Index | Unit | Defined as | One | Two | Gender +| --- | --- |--- |--- |--- |--- +| 0 | Raw unit (no unit) | UNIT_RAW | jedna | dvě | Female +| 1 | Volts | UNIT_VOLTS | jeden | dva | Male +| 2 | Amps | UNIT_AMPS | jeden | dva | Male +| 3 | Milliamps | UNIT_MILLIAMPS | jeden | dva | Male +| 4 | Knots | UNIT_KTS | jeden | dva | Male +| 5 | Meters per Second | UNIT_METERS_PER_SECOND | jeden | dva | Male +| 6 | Feet per Second | UNIT_FEET_PER_SECOND | jedna | dvě | Female +| 7 | Kilometers per Hour| UNIT_KMH | jeden | dva | Male +| 8 | Miles per Hour | UNIT_MPH | jedna | dvě | Female +| 9 | Meters | UNIT_METERS | jeden | dva | Male +| 10 | Feet | UNIT_FEET | jedna | dvě | Female +| 11 | Degrees Celsius | UNIT_CELSIUS | jeden | dva | Male +| 12 | Degrees Fahrenheit | UNIT_FAHRENHEIT | jeden | dva | Male +| 13 | Percent | UNIT_PERCENT | jedno | dvě | Neutral +| 14 | Milliamp per Hour | UNIT_MAH | jedna | dvě | Female +| 15 | Watts | UNIT_WATTS | jeden | dva | Male +| 16 | Milliwatts | UNIT_MILLIWATTS | jeden | dva | Male +| 17 | dB | UNIT_DB | jeden | dva | Male +| 18 | RPM | UNIT_RPMS | jedna | dvě | Female +| 19 | G | UNIT_G | jedno | dvě | Neutral +| 20 | Degrees | UNIT_DEGREE | jeden | dva | Male +| 21 | Radians | UNIT_RADIANS | jeden | dva | Male +| 22 | Milliliters | UNIT_MILLILITERS | jeden | dva | Male +| 23 | Fluid Ounces | UNIT_FLOZ | jedna | dvě | Female +| 24 | Hours | UNIT_HOURS | jedna | dvě | Female +| 25 | Minutes | UNIT_MINUTES | jedna | dvě | Female +| 26 | Seconds | UNIT_SECONDS | jedna | dvě | Female From 3aceed62c9ef139d836c79db53187f216ccd81b4 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Wed, 26 Apr 2017 21:43:35 +0200 Subject: [PATCH 167/203] [Companion] Fixes #4777 (#4860) --- .../src/firmwares/opentx/opentxeeprom.cpp | 2 +- .../src/firmwares/opentx/opentxinterface.cpp | 33 +++-------------- .../src/firmwares/opentx/opentxinterface.h | 2 - companion/src/mdichild.cpp | 2 +- companion/src/storage/storage.h | 37 +++++++++++++++---- 5 files changed, 37 insertions(+), 39 deletions(-) diff --git a/companion/src/firmwares/opentx/opentxeeprom.cpp b/companion/src/firmwares/opentx/opentxeeprom.cpp index 65abe0833..14d70483e 100644 --- a/companion/src/firmwares/opentx/opentxeeprom.cpp +++ b/companion/src/firmwares/opentx/opentxeeprom.cpp @@ -1595,7 +1595,7 @@ class CurvesField: public TransformedField { for (int i=0; i #include #include +#include using namespace Board; @@ -95,30 +96,6 @@ const char * OpenTxEepromInterface::getName() } } -uint32_t OpenTxEepromInterface::getFourCC() -{ - switch (board) { - case BOARD_X12S: - case BOARD_X10: - return 0x3478746F; - case BOARD_TARANIS_X7: - return 0x3678746F; - case BOARD_TARANIS_X9E: - return 0x3578746F; - case BOARD_TARANIS_X9D: - case BOARD_TARANIS_X9DP: - return 0x3378746F; - case BOARD_SKY9X: - case BOARD_AR9X: - return 0x3278746F; - case BOARD_MEGA2560: - case BOARD_GRUVIN9X: - return 0x3178746F; - default: - return 0; - } -} - bool OpenTxEepromInterface::loadRadioSettingsFromRLE(GeneralSettings & settings, RleFile * rleFile, uint8_t version) { QByteArray data(sizeof(settings), 0); // GeneralSettings should be always bigger than the EEPROM struct @@ -163,7 +140,7 @@ bool OpenTxEepromInterface::saveToByteArray(const T & src, QByteArray & data, ui // manager.Dump(); manager.Export(raw); data.resize(8); - *((uint32_t*)&data.data()[0]) = getFourCC(); + *((uint32_t*)&data.data()[0]) = StorageFormat::getFourCC(board); data[4] = version; data[5] = 'M'; *((uint16_t*)&data.data()[6]) = raw.size(); @@ -186,12 +163,12 @@ template bool OpenTxEepromInterface::loadFromByteArray(T & dest, const QByteArray & data) { uint32_t fourcc = *((uint32_t*)&data.data()[0]); - if (getFourCC() != fourcc) { + if (StorageFormat::getFourCC(board) != fourcc) { if (IS_HORUS(board) && fourcc == 0x3178396F) { - qDebug() << QString().sprintf("%s: Deprecated fourcc used %x vs %x", getName(), fourcc, getFourCC()); + qDebug() << QString().sprintf("%s: Deprecated fourcc used %x vs %x", getName(), fourcc, StorageFormat::getFourCC(board)); } else { - qDebug() << QString().sprintf("%s: Wrong fourcc %x vs %x", getName(), fourcc, getFourCC()); + qDebug() << QString().sprintf("%s: Wrong fourcc %x vs %x", getName(), fourcc, StorageFormat::getFourCC(board)); return false; } } diff --git a/companion/src/firmwares/opentx/opentxinterface.h b/companion/src/firmwares/opentx/opentxinterface.h index f9cfdf745..c8f659de1 100644 --- a/companion/src/firmwares/opentx/opentxinterface.h +++ b/companion/src/firmwares/opentx/opentxinterface.h @@ -72,8 +72,6 @@ class OpenTxEepromInterface : public EEPROMInterface uint8_t getLastDataVersion(Board::Type board); - uint32_t getFourCC(); - RleFile * efile; OpenTxFirmware * firmware; diff --git a/companion/src/mdichild.cpp b/companion/src/mdichild.cpp index 7676e9b49..bddacd7ef 100644 --- a/companion/src/mdichild.cpp +++ b/companion/src/mdichild.cpp @@ -702,7 +702,7 @@ void MdiChild::onFirmwareChanged() Firmware * previous = firmware; firmware = getCurrentFirmware(); //qDebug() << "onFirmwareChanged" << previous->getName() << "=>" << firmware->getName(); - if (previous->getBoard() != firmware->getBoard()) { + if (StorageFormat::getFourCC(previous->getBoard()) != StorageFormat::getFourCC(firmware->getBoard())) { convertStorage(previous->getBoard(), firmware->getBoard()); setModified(); } diff --git a/companion/src/storage/storage.h b/companion/src/storage/storage.h index e1af73b5c..aa288451f 100644 --- a/companion/src/storage/storage.h +++ b/companion/src/storage/storage.h @@ -67,15 +67,38 @@ class StorageFormat return board; } + static uint32_t getFourCC(Board::Type board) + { + switch (board) { + case Board::BOARD_X12S: + case Board::BOARD_X10: + return 0x3478746F; + case Board::BOARD_TARANIS_X7: + return 0x3678746F; + case Board::BOARD_TARANIS_X9E: + return 0x3578746F; + case Board::BOARD_TARANIS_X9D: + case Board::BOARD_TARANIS_X9DP: + return 0x3378746F; + case Board::BOARD_SKY9X: + case Board::BOARD_AR9X: + return 0x3278746F; + case Board::BOARD_MEGA2560: + case Board::BOARD_GRUVIN9X: + return 0x3178746F; + default: + return 0; + } + } + + uint32_t getFourCC() + { + return getFourCC(board); + } + virtual bool isBoardCompatible(Board::Type board) { - if (this->board == board) - return true; - - if (IS_TARANIS_X9D(this->board) && IS_TARANIS_X9D(board)) - return true; - - return false; + return getFourCC() == getFourCC(board); } protected: From 73f4b8f172a1eb0d68bf64af149fabdf82212de4 Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Wed, 26 Apr 2017 21:45:46 +0200 Subject: [PATCH 168/203] Projectkk2glider/issue 4827 (#4855) * Reverting a part of f94b4c743d6720641f985790d71d99d976b831c9 that deals with the size of table hash. Fixes 4827, but uses more memory and CPU. * New internal Lua traces --- radio/src/debug.h | 10 ++++++++++ radio/src/thirdparty/Lua/src/lobject.h | 4 ++-- radio/src/thirdparty/Lua/src/lparser.c | 2 ++ radio/src/thirdparty/Lua/src/ltable.c | 17 ++++++++--------- 4 files changed, 22 insertions(+), 11 deletions(-) diff --git a/radio/src/debug.h b/radio/src/debug.h index 41cdfda30..90aca3d88 100644 --- a/radio/src/debug.h +++ b/radio/src/debug.h @@ -70,8 +70,18 @@ extern "C" { #if defined(TRACE_LUA_INTERNALS_ENABLED) #define TRACE_LUA_INTERNALS(f_, ...) debugPrintf(("[LUA INT] " f_ "\r\n"), ##__VA_ARGS__) + + #define TRACE_LUA_INTERNALS_WITH_LINEINFO(L, f_, ...) do { \ + lua_Debug ar; \ + if (lua_getstack(L, 1, &ar)) { \ + lua_getinfo(L, ">Sl", &ar); \ + debugPrintf("%s:%d: ", ar.short_src, ar.currentline); \ + } \ + debugPrintf(("[LUA INT] " f_ "\r\n"), ##__VA_ARGS__); \ + } while(0) #else #define TRACE_LUA_INTERNALS(...) + #define TRACE_LUA_INTERNALS_WITH_LINEINFO(L, f_, ...) #endif #if defined(DEBUG) && !defined(SIMU) diff --git a/radio/src/thirdparty/Lua/src/lobject.h b/radio/src/thirdparty/Lua/src/lobject.h index 7e5c03ab4..919b2c304 100644 --- a/radio/src/thirdparty/Lua/src/lobject.h +++ b/radio/src/thirdparty/Lua/src/lobject.h @@ -569,7 +569,7 @@ typedef struct Node { typedef struct Table { CommonHeader; lu_byte flags; /* 1<

lsizenode) +#define sizenode(t) (twoto((t)->lsizenode)) /* diff --git a/radio/src/thirdparty/Lua/src/lparser.c b/radio/src/thirdparty/Lua/src/lparser.c index d8f5b4ffc..43a8967ff 100644 --- a/radio/src/thirdparty/Lua/src/lparser.c +++ b/radio/src/thirdparty/Lua/src/lparser.c @@ -181,6 +181,7 @@ static void new_localvar (LexState *ls, TString *name) { int reg = registerlocalvar(ls, name); checklimit(fs, dyd->actvar.n + 1 - fs->firstlocal, MAXVARS, "local variables"); + TRACE_LUA_INTERNALS("new_localvar %s %d", getstr(name), dyd->actvar.n + 1 - fs->firstlocal); luaM_growvector(ls->L, dyd->actvar.arr, dyd->actvar.n + 1, dyd->actvar.size, Vardesc, MAX_INT, "local variables"); dyd->actvar.arr[dyd->actvar.n++].idx = cast(short, reg); @@ -1529,6 +1530,7 @@ static void retstat (LexState *ls) { static void statement (LexState *ls) { int line = ls->linenumber; /* may be needed for error messages */ enterlevel(ls); + TRACE_LUA_INTERNALS("statement %02x at line %d", ls->t.token, line); switch (ls->t.token) { case ';': { /* stat -> ';' (empty statement) */ luaX_next(ls); /* skip ';' */ diff --git a/radio/src/thirdparty/Lua/src/ltable.c b/radio/src/thirdparty/Lua/src/ltable.c index 6cea6e5e2..902e09fae 100644 --- a/radio/src/thirdparty/Lua/src/ltable.c +++ b/radio/src/thirdparty/Lua/src/ltable.c @@ -282,16 +282,14 @@ static void setnodevector (lua_State *L, Table *t, int size) { int lsize; if (size == 0) { /* no elements to hash part? */ t->node = cast(Node *, dummynode); /* use common `dummynode' */ - lsize = 1; + lsize = 0; } else { int i; - // lsize = luaO_ceillog2(size); - // if (lsize > MAXBITS) - // luaG_runerror(L, "table overflow"); - // size = twoto(lsize); - // size += size/2; - lsize = size; + lsize = luaO_ceillog2(size); + if (lsize > MAXBITS) + luaG_runerror(L, "table overflow"); + size = twoto(lsize); t->node = luaM_newvector(L, size, Node); for (i=0; isizearray; int oldhsize = t->lsizenode; + TRACE_LUA_INTERNALS_WITH_LINEINFO(L, "luaH_resize table %p %d(%d) %d(%d)", t, nasize, oldasize, nhsize, twoto(oldhsize)); Node *nold = t->node; /* save old hash ... */ if (nasize > oldasize) /* array part must grow? */ setarrayvector(L, t, nasize); @@ -324,7 +323,7 @@ void luaH_resize (lua_State *L, Table *t, int nasize, int nhsize) { luaM_reallocvector(L, t->array, oldasize, nasize, TValue); } /* re-insert elements from hash part */ - for (i = oldhsize - 1; i >= 0; i--) { + for (i = twoto(oldhsize) - 1; i >= 0; i--) { Node *old = nold+i; if (!ttisnil(gval(old))) { /* doesn't need barrier/invalidate cache, as entry was @@ -333,7 +332,7 @@ void luaH_resize (lua_State *L, Table *t, int nasize, int nhsize) { } } if (!isdummy(nold)) - luaM_freearray(L, nold, cast(size_t, oldhsize)); /* free old array */ + luaM_freearray(L, nold, cast(size_t, twoto(oldhsize))); /* free old array */ } From c6d15c6f371e99e61cb19271c09324e174fcd959 Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Thu, 27 Apr 2017 11:19:57 +0200 Subject: [PATCH 169/203] Launchpad changelogs for 2.2.0 RC17 --- launchpad/trusty/changelog | 6 ++++++ launchpad/xenial/changelog | 6 ++++++ launchpad/yakkety/changelog | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/launchpad/trusty/changelog b/launchpad/trusty/changelog index b928ddbf0..8ca4b10d5 100644 --- a/launchpad/trusty/changelog +++ b/launchpad/trusty/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N370~trusty) trusty; urgency=low + + * New release 2.2.0~N370 RC17 + + -- projectkk2glider Thu, 27 Apr 2017 10:59:16 +0200 + opentx-companion22 (2.2.0~N369~trusty) trusty; urgency=low * New release 2.2.0~N369 RC16 diff --git a/launchpad/xenial/changelog b/launchpad/xenial/changelog index 1fe96e105..adb6390aa 100644 --- a/launchpad/xenial/changelog +++ b/launchpad/xenial/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N370~xenial) xenial; urgency=low + + * New release 2.2.0~N370 RC17 + + -- projectkk2glider Thu, 27 Apr 2017 10:59:20 +0200 + opentx-companion22 (2.2.0~N369~xenial) xenial; urgency=low * New release 2.2.0~N369 RC16 diff --git a/launchpad/yakkety/changelog b/launchpad/yakkety/changelog index 4eb2dd6a2..de1ac2f56 100644 --- a/launchpad/yakkety/changelog +++ b/launchpad/yakkety/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N370~yakkety) yakkety; urgency=low + + * New release 2.2.0~N370 RC17 + + -- projectkk2glider Thu, 27 Apr 2017 10:59:10 +0200 + opentx-companion22 (2.2.0~N369~yakkety) yakkety; urgency=low * New release 2.2.0~N369 RC16 From 37b0dab9dadadfa8d39fb0af491526680c832175 Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Thu, 27 Apr 2017 20:31:00 +0200 Subject: [PATCH 170/203] Add RAS to X7 analogs screen (#4865) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Add RAS to X7 analogs screen * Also fix SWR->RAS in simulator UI * Only display RAS for external XJT module The „this is almost useless but I have done the work, now it stays commit“ --- companion/src/simulation/telemetrysimu.ui | 2 +- radio/src/gui/128x64/radio_diaganas.cpp | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/companion/src/simulation/telemetrysimu.ui b/companion/src/simulation/telemetrysimu.ui index fbc909e2a..3ad9ae83e 100644 --- a/companion/src/simulation/telemetrysimu.ui +++ b/companion/src/simulation/telemetrysimu.ui @@ -528,7 +528,7 @@ Timestamp - SWR + RAS diff --git a/radio/src/gui/128x64/radio_diaganas.cpp b/radio/src/gui/128x64/radio_diaganas.cpp index 61ea3b46e..da1e83bed 100644 --- a/radio/src/gui/128x64/radio_diaganas.cpp +++ b/radio/src/gui/128x64/radio_diaganas.cpp @@ -65,6 +65,11 @@ void menuRadioDiagAnalogs(event_t event) #if defined(PCBX7) lcdDrawTextAlignedLeft(MENU_HEADER_HEIGHT + 1 + (NUM_STICKS+NUM_POTS+NUM_SLIDERS+1)/2 * FH + 2, STR_BATT_CALIB); putsVolts(LEN_CALIB_FIELDS*FW+FW, MENU_HEADER_HEIGHT + 1 + (NUM_STICKS+NUM_POTS+NUM_SLIDERS+1)/2 * FH + 2, getBatteryVoltage(), (menuVerticalPosition==HEADER_LINE ? INVERS | (s_editMode > 0 ? BLINK : 0) : 0) | PREC2 | LEFT); + // SWR + if(IS_MODULE_XJT(EXTERNAL_MODULE)) { + lcdDrawTextAlignedLeft(MENU_HEADER_HEIGHT + 1 + (NUM_STICKS+NUM_POTS+NUM_SLIDERS+1)/2 * FH + 1 * FH + 2, "RAS"); + lcdDrawNumber(LEN_CALIB_FIELDS*FW+FW, MENU_HEADER_HEIGHT + 1 + (NUM_STICKS+NUM_POTS+NUM_SLIDERS+1)/2 * FH + 1 * FH + 2, telemetryData.swr.value, LEFT); + } #elif defined(PCBSKY9X) lcdDrawTextAlignedLeft(MENU_HEADER_HEIGHT+1+4*FH, STR_BATT_CALIB); static int32_t adcBatt; From f3cbc37067f855f8406173ece9f0e4f486ab8bf2 Mon Sep 17 00:00:00 2001 From: Sebastien Charpentier Date: Thu, 27 Apr 2017 21:06:40 +0200 Subject: [PATCH 171/203] Fix French translation (#4862) * Fixed too long French translation for the Horus. * Fixed some French translations. --- companion/src/translations/companion_fr.ts | 1326 ++++++++++---------- 1 file changed, 664 insertions(+), 662 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index a8c5a1e05..ba43158d4 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -1026,46 +1026,171 @@ Peut être différente de la langue du firmware Impossible de trouver le fichier son %1 ! - + &Delete &Supprimer - + Delete Supprimer - + &Copy &Copier - + Ctrl+C - + &Cut &Couper - + Ctrl+X - + &Paste &Coller - + Ctrl+V + + CustomizeSplashDialog + + + Transmitter Splash Screen Editor + Éditeur d'écran d'accueil + + + + + Invert + Inverser + + + + + Load FW + Ouvrir le firmware + + + + + Load Pict + Ouvrir l'image + + + + + Load Profile + Charger le profil + + + + + Save + Sauvegarder + + + + + Open Splash Library + Ouvrir la bibliothèque des écrans d'accueil + + + + + + + ... + + + + + + + + Error + Erreur + + + + Open Firmware File + Sélectionner le firmware + + + + Can not load embedded image from firmware file %1. + Impossible d'enregistrer l'image %1 dans le firmware. + + + + Open Image to load + Ouvrir l'image à charger + + + + Images (%1) + Images (%1) + + + + Cannot load the image file %1. + Impossible d'ouvrir l'image %1. + + + + Cannot load profile image %1. + Impossible d'ouvrir l'image du profil %1. + + + + Cannot load the library image %1. + Impossible d'ouvrir l'image de bibliothèque %1. + + + + File Saved + Fichier sauvegardé + + + + The image was saved to the file %1 + L'image a été enregistrée dans le fichier %1 + + + + Image Refresh Error + Erreur de rafraîchissement de l'image + + + + Failed to refresh image from file %1 + Impossible de rafraîchir l'image %1 + + + + File Save Error + Erreur à la sauvegarde du fichier + + + + Failed to write image to %1 + Erreur à l'écriture du fichier %1 + + CyclicPage @@ -1177,78 +1302,78 @@ Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le EepromInterface - + Possible causes for this: Causes possibles: - + - Eeprom is from a newer version of OpenTX - L'EEPROM peut avoir été créée avec une version d'OpenTX plus récente - + - Eeprom is not from OpenTX - L'EEPROM peut avoir été créée avec un firmware autre qu'OpenTX - + - Eeprom is not from Th9X - L'EEPROM n'est pas une EEPROM TX9X - + - Eeprom is not from Gruvin9X - L'EEPROM n'est pas une EEPROM Gruvin9X - + - Eeprom is not from ErSky9X - L'EEPROM n'est pas une EEPROM ErSky9X - + - Eeprom is not from Er9X - L'EEPROM n'est pas une EEPROM ER9X - + - Eeprom size is invalid - La taille de l'EEPROM est invalide - + - Eeprom file system is invalid - Le système de fichier de l'EEPROM est invalide - + - Eeprom is from a unknown board - L'EEPROM ne correspond à aucune carte supportée - + - Eeprom is from the wrong board - L'EEPROM ne correspond pas au type de radio sélectionné - + - Eeprom backup not supported - Sauvegarde d'EEPROM non supportée - + - Something that couldn't be guessed, sorry - Erreur inconnue - + Warning: Avertissement: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - Le firmware de la radio est probablement incorrect, @@ -1256,14 +1381,14 @@ la taille de l'EEPROM est de 4096 mais seulement 2048 bytes sont utilisés. Vérifier la sélection (M64/M128) - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - Le fichier qui vient d'être ouvert provient d'une ancienne verison d'OpenTX et a été converti. Il est recommandé d'"Enregistrer Sous" au plus vite pour ne pas risquer d'écraser votre ancien fichier. - + Warnings! Avertissements ! @@ -3903,14 +4028,14 @@ Les colonnes contenant l'altitude "GAlt" et la vitesse "GSpd MainWindow - - + + Edit Édition - - + + File Fichier @@ -3987,17 +4112,17 @@ Les colonnes contenant l'altitude "GAlt" et la vitesse "GSpd Le firmware actuel ne contient pas de notes de version. - + Compare models Comparer les modèles - + Show fuses dialog Afficher les réglages des fusibles - + A monochrome black icon theme Thème avec icônes monochromes noires @@ -4033,220 +4158,220 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b - + Synchronize SD Synchroniser la carte SD - + New Nouveau - + Open... Ouvrir... - + A monochrome white icon theme Thème avec icônes monochromes blanches - + A monochrome blue icon theme Thème avec icônes monochromes bleues - + Small Petites - + Use small toolbar icons Petites icônes de barre d'outils - + Use normal size toolbar icons Icônes de barre d'outils normales - + Normal Normales - + Use big toolbar icons Grosses icônes de barre d'outils - + Big Grandes - + Use huge toolbar icons Immenses icônes de barre d'outils - + Huge Immenses - + List programmers... Lister les programmateurs... - + Fuses... Fusibles... - + Read Firmware from Radio Lire le firmware de la radio - + Read firmware from Radio Lire le firmware de la radio - + Write Firmware to Radio Transférer le firmware à la radio - + Write firmware to Radio Transférer le firmware à la radio - + Add Radio Profile Ajouter un profil de radio - + Manuals and other Documents Manuels et documents - + Open the OpenTX document page in a web browser Ouvre la page de documentation d'OpenTX dans un navigateur - + Write Models and Settings To Radio Transférer les réglages et modèles vers la radio - + Write Models and Settings to Radio Transférer les réglages et modèles vers la radio - + Companion - + Read Models and Settings from Radio Lire les réglages et modèles depuis la radio - + OpenTX Companion %1 - Radio: %2 - Profile: %3 OpenTX Companion %1 - Radio: %2 - Profil: %3 - + List of recently used files Liste des fichiers récemment utilisés - + Radio Profiles Profil radio - + Create or Select Radio Profiles Créer ou Sélectionner un profil radio - + Configure Communications... Configurer les communications... - + Configure software for communicating with the Radio Configurer le programme gérant les communications avec la radio - + Write Backup to Radio Transférer une sauvegarde à la radio - + Write Backup from file to Radio Transférer une sauvegarde à la radio - + Backup Radio to File Sauvegarder la radio - + Save a complete backup file of all settings and model data in the Radio Créer une copie de sauvegarde de tous les réglages et modèles de la radio - + Contributors... Contributeurs... - + A tribute to those who have contributed to OpenTX and Companion Remerciements à tout ceux qui ont contribué à OpenTX et Companion - + SD card synchronization Synchronisation de la carte SD - + Recent Files Fichiers récents - + Set Icon Theme Choisir le thème d'icônes - + Set Icon Size Choisir la taille des icônes - + Write Ecrire @@ -4266,12 +4391,12 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Si vous trouvez ce programme utile, merci de le supporter par une <a href='%1'>donation</a> - + Ready Prêt - + Show the application's About box Afficher la fenêtre "A propos" de l'application @@ -4288,7 +4413,7 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b - + Open Models and Settings file Ouvrir un fichier de réglages et modèles @@ -4299,7 +4424,7 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Fichier sauvegardé - + Read Models and Settings From Radio Lire les réglages et modèles depuis la radio @@ -4339,7 +4464,7 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Language non valide - + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. Certains textes ne seront pas traduits avant le prochain redémarrage de Companion. Veuillez noter que certaines traductions peuvent ne pas être complètes. @@ -4375,298 +4500,298 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b - + Create a new Models and Settings file Créer un nouveau fichier de réglages et modèles - + Save Models and Settings file Enregistrer le fichier de réglages et modèles - + Save Enregistrer - + Save As... Enregistrer sous... - + Close Fermer - + Close Models and Settings file Fermer le fichier de réglages et modèles - + Exit the application Quitter l'application - + Exit Quitter - + Create a new Radio Settings Profile Créer un nouveau profil de réglages et modèles - + Copy Current Radio Profile Copier le profil radio actuel - + Duplicate current Radio Settings Profile Dupliquer les réglages radio du profil actuel - + Delete the current Radio Settings Profile Supprimer les réglages radio du profil actuel - + Use default system language. Utiliser le langage système par défaut. - + Use %1 language (some translations may not be complete). Utiliser la langue %1 (certaines traductions peuvent être incomplètes). - + Classical Classique - + Delete Current Radio Profile... Supprimer le profil radio actuel... - + Tabbed Windows Fenêtres à onglets - + Use tabs to arrange open windows. Utilisez les onglets pour organiser les fenêtres ouvertes. - + Tile Windows Titre de la fenêtre - + Arrange open windows across all the available space. Disposez les fenêtres ouvertes sur tout l'espace disponible. - + Cascade Windows Fenêtres en cascade - + Arrange all open windows in a stack. Organisez toutes les fenêtres ouvertes dans une pile. - + Close All Windows Fermer toutes les fenêtres - + Closes all open files (prompts to save if necessary. Fermer tous les fichiers ouverts (proposer de sauvegarder si nécessaire). - + Window Fenêtre - + Ctrl+Shift+S - + Ctrl+Alt+L - + Ctrl+Alt+D - + Ctrl+Alt+R - + The classic companion9x icon theme Thème d'icônes classique de Companion - + Yerico - + Yellow round honey sweet icon theme Thème d'icônes rondes jaunes - + Monochrome - + MonoWhite Monochrome Blanc - + Alt+%1 - + - Copy - Copier - + Not possible to remove profile Impossible de supprimer le profil - + The default profile can not be removed. Le profil par défaut ne peut pas être supprimé. - + Confirm Delete Profile Confirmer la suppression du profil - + Are you sure you wish to delete the "%1" radio profile? There is no way to undo this action! Etes-vous sûr de vouloir supprimer le profil radio %1 ? Cette action est irréversible ! - + MonoBlue Monochrome Bleu - + System language Langue du système - + About... A propos... - + View Log File... Ouvrir un Log... - + Open and view log file Ouvrir et visualiser un log - + Settings... Préférences... - + Edit Settings Éditier les réglages - + Download... Télécharger... - + Download firmware and voice files Télécharger firmware et fichiers son - + Check for Updates... Vérifier les mises à jour... - + Check OpenTX and Companion updates Vérifier les mises à jour d'OpenTX et Companion - + Companion Changes... Changements de Companion... - + Show Companion change log Voir l'historique des changements de Companion - + Firmware Changes... Changements du firmware... - + Show firmware change log Voir l'historique des changements du firmware - + Compare Models... Comparer 2 modèles... - + Edit Radio Splash Image... Éditier l'écran d'accueil de la radio... - + Edit the splash image of your Radio Éditier l'écran d'accueil de la radio - + List available programmers Lister les programmateurs supportés @@ -4698,8 +4823,8 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Voulez-vous lancer l'installation ? - - + + Help Aide @@ -4719,27 +4844,27 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b A propos de Companion - + Set Menu Language Choisir la langue des menus - + Settings Réglages - + Read/Write Transfert - + %2 - + New Radio Nouvelle radio @@ -4877,7 +5002,7 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Edit Radio Settings - Éditer les réglages radio + Éditer réglages radio @@ -4892,7 +5017,7 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Simulate Radio - Simuler la radio + Simuler radio @@ -4988,7 +5113,8 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b New model Translators: do NOT use accents here, this is a default model name. - Nouveau modele + No accent, but no more than 15 characters!! + Nve modele @@ -5093,7 +5219,8 @@ et choisissez la bonne radio avant de l'ouvrir.à nouveau. New category Translators do NOT use accent for this, this is the default category name on Horus. - Nouvelle categorie + No accent, but no more than 15 characters!! + Nlle categorie @@ -6574,47 +6701,47 @@ Mixage actif par défaut si non-renseigné. Sel.Rot. E - + Trainer Écolage - + Trainer RUD Écolage Direction - + Trainer ELE Écolage Profondeur - + Trainer THR Écolage Gaz - + Trainer AIL Écolage Ailerons - + Instant Trim Trims instantanés - + Play Sound Jouer Son - + Haptic Vibreur - + S3 @@ -6719,12 +6846,12 @@ Mixage actif par défaut si non-renseigné. Heure GPS - + L1 - + L2 @@ -6740,7 +6867,7 @@ Mixage actif par défaut si non-renseigné. - + L%1 @@ -6750,167 +6877,167 @@ Mixage actif par défaut si non-renseigné. - + FM0 PV0 - + FM1 PV1 - + FM2 PV2 - + FM3 PV3 - + FM4 PV4 - + FM5 PV5 - + FM6 PV6 - + FM7 PV7 - + FM8 PV8 - + Trim 5 Down Trim 5 Bas - + Trim 5 Up Trim 5 Haut - + Trim 6 Down Trim 6 Bas - + Trim 6 Up Trim 6 Haut - + One Un - + a>x - + a<x - + |a|>x - + |a|<x - + AND ET - + OR OU - + XOR OUX - + a=b - + a!=b - + a>b - + a<b - + a>=b - + a<=b - + d>=x - + |d|>=x - + a=x - + a~x - + Timer Chrono - + Sticky Bistable @@ -6946,77 +7073,77 @@ Mixage actif par défaut si non-renseigné. - + Unknown Inconnu - + SD Logs Logs SD - + played once, not during startup !1x Lu une fois, mais pas à la mise en route - + repeat(%1s) Répéter chaque %1s - + DISABLED DESACTIVE - + INV - + NOR - + Reset Remise à zéro - + Set Timer %1 Définir chrono %1 - + Vario - + Volume - + Play Value Lire valeur - + Backlight Rétroéclairage - + Play Track Jouer fichier - + --- @@ -7108,64 +7235,64 @@ Mixage actif par défaut si non-renseigné. 1x Lu une fois - + Play Both Jouer les 2 - + Override %1 Remplacer %1 - + Play Script Exécuter script - + Screenshot Capture d'écran - + Background Music Musique de fond - + Background Music Pause Pause musique de fond - + Edge Flanc - - - + + + <font color=red><b>Inconsistent parameter</b></font> <font color=red><b>Paramètre inconsistant</b></font> - + Telemetry Télémesure - + Value Valeur - + Decr: Décr: - + Incr: Incr: @@ -7180,27 +7307,27 @@ Mixage actif par défaut si non-renseigné. - + Value Valeur - + Source - + GVAR VG - + Increment Incrément - + Flight Vol @@ -7247,42 +7374,42 @@ Mixage actif par défaut si non-renseigné. -VG%1 - + Adjust GV%1 Ajuster VG%1 - + SetFailsafe Int. Module Déf. failsafe module interne - + SetFailsafe Ext. Module Déf. failsafe module externe - + RangeCheck Int. Module Test portée module interne - + RangeCheck Ext. Module Test portée module externe - + Bind Int. Module Bind module interne - + Bind Ext. Module Bind module externe - + Rotary Encoder Sélecteur Rotatif @@ -7371,7 +7498,7 @@ Mixage actif par défaut si non-renseigné. - + ---- @@ -7393,7 +7520,7 @@ Mixage actif par défaut si non-renseigné. - + P1 @@ -7405,13 +7532,13 @@ Mixage actif par défaut si non-renseigné. - + V - + s @@ -7495,13 +7622,13 @@ Mixage actif par défaut si non-renseigné. - + P2 - + P3 @@ -7512,111 +7639,111 @@ Mixage actif par défaut si non-renseigné. - + RudTrim Left TrmD Gauche - + RudTrim Right TrmD Droite - + EleTrim Down TrmP Bas - + EleTrim Up TrmP Haut - + ThrTrim Down TrmG Bas - + ThrTrim Up TrmG Haut - + AilTrim Left TrmA Gauche - + AilTrim Right TrmA Droite - + THs GZs - + TH% GZ% - + THt GZt - - + + ??? - + Diff(%1) - + Expo(%1) - + Function(%1) Fonction(%1) - + Curve(%1) Courbe(%1) - + !Curve(%1) !Courbe(%1) - + Rud Dir - + Ele Prf - + Thr Gaz - + Ail Ail @@ -7642,9 +7769,9 @@ Mixage actif par défaut si non-renseigné. TrmA - - - + + + S1 @@ -7714,57 +7841,57 @@ Mixage actif par défaut si non-renseigné. - - - + + + S2 - - - + + + LS - - - + + + RS - + F1 - + F2 - + F3 - + F4 - - + + REa - - + + REb @@ -7781,7 +7908,7 @@ Mixage actif par défaut si non-renseigné. - + Timer3 Chrono 3 @@ -7907,631 +8034,631 @@ Mixage actif par défaut si non-renseigné. - - + + ON - - + + OFF - - + + Support for frsky telemetry mod Support de la télémétrie FrSky - - + + Support for jeti telemetry mod Support de la télémétrie JETI - - + + Support for receiving ardupilot data Support de la télémétrie ARDUPILOT - - + + Support for receiving NMEA data Support de la télémétrie NMEA - + Support for telemetry easy board Support de la carte TelemetrEZ - - + + Support for MAVLINK devices Support du protocole MAVLINK - + Rotary Encoder use in menus navigation Utiliser le sélecteur rotatif pour la navigation - - - - - - + + + + + + Enable heli menu and cyclic mix support Activer le menu hélico et les mixages CCPM - - - - - - + + + + + + Enable TEMPLATES menu Inclure les gabarits - + 6P - + Enable Lua compiler Active le compilateur Lua - + Support for the DIY-Multiprotocol-TX-Module Support du module Multiprotocol - + Unknown error Erreur inconnue - + ... plus %1 errors ... plus %1 erreurs - + Cannot write radio settings Impossible d'écrire les paramètres de la radio - + Cannot write model %1 Impossible d'écrire le modèle %1 - + JSx - + JSy - + Enable bindings options Activer les options de Bind (désactiver la télémétrie pour les XSR, etc...) - + KS108 LCD - + WTV20 voice module Module voix WTV20 - + JQ6500 voice module Module voix JQ6500 - + FrSky Taranis X9D+ - + FrSky Taranis X9D - + Horus gimbals installed (Hall sensors) Manches à effet HALL de Horus installés - + FrSky Taranis X7 - + FrSky Horus - + Use ONLY with first DEV pcb version Exclusivement pour les Horus DEV - + Turnigy 9XR-PRO - + Turnigy 9XR with m128 chip Turnigy 9XR avec une puce m128 - - - - + + + + No splash screen Pas d'écran de démarrage - - - - - - + + + + + + Disable curves menus Désactiver le menu des courbes - - - - - + + + + + Support for radio modified with regular speaker Haut-parleur au lieu du buzzer d'origine - - - - - + + + + + Used if you have modified your radio with voice mode Support du module vocal - - - - - + + + + + Used if you have modified your radio with haptic mode Support du vibreur - + Channel values displayed in us Positions de voies affichées en µs - - - - - - - - - + + + + + + + + + Battery graph Graphique de batterie - - - - - - - - - - - + + + + + + + + + + + Use alternative SQT5 font Utiliser la police alternative SQT5 - + Possibility to enable FAI MODE (no telemetry) at field Possibilité d'activer le mode FAI (télémétrie désactivée) sur le terrain - + FAI MODE (no telemetry) always enabled Mode FAI (télémétrie désactivée) toujours actif - + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) Le port USB connecte les disques virtuels au lieu du Joystick (comme dans le bootloader) - + Instead of Joystick emulation, USB connection is Command Line Interface Le port USB est utilisé pour un port série avec interface par ligne de commande au lieu du Joystick - + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 Masque le protocole D8. Légalement obligatoire sur les radios Européennes importées après le 1er janvier 2015 - - + + Support for PPM internal module hack Support du remplacement du module interne par un module PPM - + ST7565P LCD or compatible ST7565P LCD ou compatible - + ST7565R LCD or compatible ST7565R LCD ou compatible - + ERC12864FSF LCD LCD ERC12864FSF - + ST7920 LCD LCD ST7920 - - - - + + + + Enable the throttle trace in Statistics Activer l'historique du manche des gaz dans les statistiques - + EEprom write progress bar Barre de progression pour l'écriture de l'EEPROM - - + + No Winged Shadow How High support Supprimer le support du variomètre Winged Shadow How High - + Turnigy 9XR - - + + No vario support Supprimer la fonction variomètre audio - - + + No GPS support Supprimer le support du GPS - - + + No gauges in the custom telemetry screen Supprimer l'affichage des valeurs de télémesure par barres - + 9X with stock board 9X avec carte mère d'origine - + Allow compensating for offset errors in FrSky FAS current sensors Permettre la compensation d'un décalage des capteurs de courant FASxx FrSky - - + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) Ajoute le support de l'inversion des manches (nécessaire pour l'utilisation de manches FrSky) - + DIY MEGA2560 radio - + Power management by soft-off circuitry Gestion alim. par software - + FrSky Taranis X9E - + Confirmation before radio shutdown Confirmation avant l'arrêt de la radio - + Haptic module installed Module vibreur installé - + Support for Lua model scripts Support des scripts Lua + - Support of FrSky PXX protocol Support du protocole PXX FrSky - + Disable HELI menu and cyclic mix support Supprimer le menu HELICO et les mixages cycliques - + Disable Global variables Supprimer le support des variables globales - - - - - + + + + + Support for DSM2 modules Support du protocole DSM2 - - - - - - + + + + + + PPM center adjustment in limits Neutres PPM ajustables - - - - - - + + + + + + Symetrical Limits Limites symétriques - - - - - - - + + + + + + + Pots use in menus navigation Support de la navigation dans les menus avec les POTS - + No OverrideCH functions available Désactive la fonction spéciale "Remplacer VOIEx" - - - - - - - - - + + + + + + + + + No flight modes Pas de phases de vol - - + + SmartieParts 2.2 Backlight support Support du rétroéclairage pour la carte SmartieParts 2.2 - - - - - - + + + + + + Enable resetting values by pressing up and down at the same time Permet la remise à zéro des valeurs en pressant haut-bas en même temps, valeur min avec gauche/bas, valeur max avec haut/droite, inversion avec gauche/droite - - - - - - - - - + + + + + + + + + No graphical check boxes and sliders Pas de cases à cocher et de curseurs graphiques - - - - - - - - - + + + + + + + + + Don't use bold font for highlighting active items Ne pas mettre les lignes actives en gras - - - - - + + + + + EEprom write Progress bar Barre de progression affichée lors des écritures EEPROM - - - - - - + + + + + + Imperial units Unités Impériales - - - + + + Bluetooth interface Interface Bluetooth - - - - - - - - - + + + + + + + + + Global variables Variables globales - - - - - - - - - + + + + + + + + + In model setup menus automatically set source by moving the control Sélectionner les sources des mixeurs en bougeant le contrôle désiré - - - - - - - - - + + + + + + + + + In model setup menus automatically set switch by moving the control Sélectionner les interrupteurs en bougeant le contrôle désiré - + 9X with stock board and m128 chip Carte 9x avec un chip m128 - + 9X with AR9X board 9X avec carte AR9X - + 9X with Sky9x board 9X avec carte Sky9x - + 9X with Gruvin9x board 9X avec carte Gruvin9x - - + + Support for SD memory card Support de la carte SD - + Support for DSM2 modules using ppm instead of true serial Support pour les modules DSM2 par le signal PPM - - - + + + Enable HELI menu and cyclic mix support Activer le menu hélico et les mixages CCPM - + Timer1 Chrono 1 - + Timer2 Chrono 2 @@ -8556,7 +8683,7 @@ Mixage actif par défaut si non-renseigné. - + Warning Avertissement @@ -8723,7 +8850,7 @@ L'équipe OpenTX. L'écriture de %1 a échoué - + @@ -8762,12 +8889,12 @@ L'équipe OpenTX. Impossible de trouver la carte SD Horus ! - + Positive - + Negative Négative @@ -12247,131 +12374,6 @@ m2560 for v4.1 boards Port série de SAM-BA - - CustomizeSplashDialog - - - Transmitter Splash Screen Editor - Éditeur d'écran d'accueil - - - - - Invert - Inverser - - - - - Load FW - Ouvrir le firmware - - - - - Load Pict - Ouvrir l'image - - - - - Load Profile - Charger le profil - - - - - Save - Sauvegarder - - - - - Open Splash Library - Ouvrir la bibliothèque des écrans d'accueil - - - - - - - ... - - - - - - - - Error - Erreur - - - - Open Firmware File - Sélectionner le firmware - - - - Can not load embedded image from firmware file %1. - Impossible d'enregistrer l'image %1 dans le firmware. - - - - Open Image to load - Ouvrir l'image à charger - - - - Images (%1) - Images (%1) - - - - Cannot load the image file %1. - Impossible d'ouvrir l'image %1. - - - - Cannot load profile image %1. - Impossible d'ouvrir l'image du profil %1. - - - - Cannot load the library image %1. - Impossible d'ouvrir l'image de bibliothèque %1. - - - - File Saved - Fichier sauvegardé - - - - The image was saved to the file %1 - L'image a été enregistrée dans le fichier %1 - - - - Image Refresh Error - Erreur de rafraîchissement de l'image - - - - Failed to refresh image from file %1 - Impossible de rafraîchir l'image %1 - - - - File Save Error - Erreur à la sauvegarde du fichier - - - - Failed to write image to %1 - Erreur à l'écriture du fichier %1 - - downloadDialog From 6f066253f09d4a26f1ac34cbb5209fb06da24a21 Mon Sep 17 00:00:00 2001 From: 3djc Date: Thu, 27 Apr 2017 21:08:46 +0200 Subject: [PATCH 172/203] Proper (?) fix (#4868) --- radio/src/gui/128x64/model_special_functions.cpp | 6 +++--- radio/src/gui/212x64/model_special_functions.cpp | 2 +- radio/src/gui/480x272/model_special_functions.cpp | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/radio/src/gui/128x64/model_special_functions.cpp b/radio/src/gui/128x64/model_special_functions.cpp index 962f63424..ca72bca25 100644 --- a/radio/src/gui/128x64/model_special_functions.cpp +++ b/radio/src/gui/128x64/model_special_functions.cpp @@ -187,11 +187,11 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF #if defined(CPUARM) if (sub==k && menuHorizontalPosition < 1 && CFN_SWITCH(cfn) == SWSRC_NONE) { drawSwitch(MODEL_SPECIAL_FUNC_1ST_COLUMN, y, CFN_SWITCH(cfn), attr | INVERS | ((functionsContext->activeSwitches & ((MASK_CFN_TYPE)1 << k)) ? BOLD : 0)); - if (active) CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); + if (active) CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, functionsContext == &globalFunctionsContext ? SWSRC_TELEMETRY_STREAMING : SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); } else { drawSwitch(MODEL_SPECIAL_FUNC_1ST_COLUMN, y, CFN_SWITCH(cfn), attr | ((functionsContext->activeSwitches & ((MASK_CFN_TYPE)1 << k)) ? BOLD : 0)); - if (active || AUTOSWITCH_ENTER_LONG()) CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, g_eeGeneral.customFn ? SWSRC_TELEMETRY_STREAMING : SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); + if (active || AUTOSWITCH_ENTER_LONG()) CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, functionsContext == &globalFunctionsContext ? SWSRC_TELEMETRY_STREAMING : SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); } #else drawSwitch(MODEL_SPECIAL_FUNC_1ST_COLUMN, y, CFN_SWITCH(cfn), attr | ((functionsContext->activeSwitches & ((MASK_CFN_TYPE)1 << k)) ? BOLD : 0)); @@ -358,7 +358,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF drawSource(MODEL_SPECIAL_FUNC_3RD_COLUMN, y, val_displayed, attr); if (active) { INCDEC_SET_FLAG(eeFlags | INCDEC_SOURCE); - INCDEC_ENABLE_CHECK(isSourceAvailable); + INCDEC_ENABLE_CHECK(functionsContext == &globalFunctionsContext ? isSourceAvailableInGlobalFunctions : isSourceAvailable); } } #endif // CPUARM && SDCARD diff --git a/radio/src/gui/212x64/model_special_functions.cpp b/radio/src/gui/212x64/model_special_functions.cpp index 242edc9ae..f9a12c868 100644 --- a/radio/src/gui/212x64/model_special_functions.cpp +++ b/radio/src/gui/212x64/model_special_functions.cpp @@ -182,7 +182,7 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF switch (j) { case ITEM_CUSTOM_FUNCTIONS_SWITCH: drawSwitch(MODEL_SPECIAL_FUNC_1ST_COLUMN, y, CFN_SWITCH(cfn), attr | ((functionsContext->activeSwitches & ((MASK_CFN_TYPE)1 << k)) ? BOLD : 0)); - if (active || AUTOSWITCH_ENTER_LONG()) CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, g_eeGeneral.customFn ? SWSRC_TELEMETRY_STREAMING : SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); + if (active || AUTOSWITCH_ENTER_LONG()) CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, functionsContext == &globalFunctionsContext ? SWSRC_TELEMETRY_STREAMING : SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); if (func == FUNC_OVERRIDE_CHANNEL && functions != g_model.customFn) { func = CFN_FUNC(cfn) = func+1; } diff --git a/radio/src/gui/480x272/model_special_functions.cpp b/radio/src/gui/480x272/model_special_functions.cpp index a31208d3e..b12a7d943 100644 --- a/radio/src/gui/480x272/model_special_functions.cpp +++ b/radio/src/gui/480x272/model_special_functions.cpp @@ -182,7 +182,7 @@ bool menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF case ITEM_SPECIAL_FUNCTIONS_SWITCH: drawSwitch(MODEL_SPECIAL_FUNC_1ST_COLUMN, y, CFN_SWITCH(cfn), attr | ((functionsContext.activeSwitches & ((MASK_CFN_TYPE)1 << k)) ? BOLD : 0)); if (active || AUTOSWITCH_ENTER_LONG()) { - CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, g_eeGeneral.customFn ? SWSRC_TELEMETRY_STREAMING : SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); + CHECK_INCDEC_SWITCH(event, CFN_SWITCH(cfn), SWSRC_FIRST, functions == g_eeGeneral.customFn ? SWSRC_TELEMETRY_STREAMING : SWSRC_LAST, eeFlags, isSwitchAvailableInCustomFunctions); } if (func == FUNC_OVERRIDE_CHANNEL && functions != g_model.customFn) { func = CFN_FUNC(cfn) = func+1; From 572463bb0d7ed1b69fd00bdbdb8e176475c944dd Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Thu, 27 Apr 2017 21:13:09 +0200 Subject: [PATCH 173/203] Update DONATIONS.txt --- DONATIONS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index 7e104a9e6..a4962bb35 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1179,3 +1179,4 @@ Meinhard Schöll Rolf Lemb Casey Layton Robert Bates +Udo Nowakowski From 36afe4127c1c2680b3050a41728fd50cc0b5ef11 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Fri, 28 Apr 2017 16:12:41 +0200 Subject: [PATCH 174/203] Update DONATIONS.txt --- DONATIONS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index a4962bb35..f53a7267d 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1180,3 +1180,4 @@ Rolf Lemb Casey Layton Robert Bates Udo Nowakowski +William Hallman From d5eec9b8dc55e9916d635d0aa2b64a664c1fadc9 Mon Sep 17 00:00:00 2001 From: Sebastien Charpentier Date: Fri, 28 Apr 2017 16:13:19 +0200 Subject: [PATCH 175/203] Fixed typo. (#4870) --- companion/src/translations/companion_fr.ts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index ba43158d4..66a822e1c 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -4733,7 +4733,7 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Edit Settings - Éditier les réglages + Éditer les réglages @@ -4783,12 +4783,12 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Edit Radio Splash Image... - Éditier l'écran d'accueil de la radio... + Éditer l'écran d'accueil de la radio... Edit the splash image of your Radio - Éditier l'écran d'accueil de la radio + Éditer l'écran d'accueil de la radio @@ -11029,11 +11029,6 @@ La valeur par défaut est configurée dans le profil radio sélectionné.RSSI - - - SWR - - Simulate @@ -11208,6 +11203,11 @@ Horodatage Tmp1 + + + RAS + + Deg. C From 04bcc70422cbbecd393cf664fbfc0b1aa79ffac8 Mon Sep 17 00:00:00 2001 From: 3djc Date: Fri, 28 Apr 2017 16:14:48 +0200 Subject: [PATCH 176/203] X7 output main view : dynamic PREC also for PPM_US (#4871) * Differentiate PREC threshold for PPM_US and PPM_PERCENT * Cosmetics --- radio/src/gui/128x64/model_outputs_arm.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/radio/src/gui/128x64/model_outputs_arm.cpp b/radio/src/gui/128x64/model_outputs_arm.cpp index ee5add03d..2547a150e 100644 --- a/radio/src/gui/128x64/model_outputs_arm.cpp +++ b/radio/src/gui/128x64/model_outputs_arm.cpp @@ -35,8 +35,10 @@ enum MenuModelOutputsItems { #if defined(PPM_UNIT_US) #define LIMITS_MIN_POS 12*FW+1 + #define PREC_THRESHOLD 804 #else #define LIMITS_MIN_POS 12*FW-2 + #define PREC_THRESHOLD 0 #endif #define LIMITS_OFFSET_POS 8*FW-1 @@ -280,7 +282,7 @@ void menuModelLimits(event_t event) break; } #endif - if (ld->min <= 0) { + if (ld->min <= PREC_THRESHOLD) { lcdDrawNumber(LIMITS_MIN_POS, y, MIN_MAX_DISPLAY(ld->min-LIMITS_MIN_MAX_OFFSET)/10, RIGHT); } else { @@ -295,7 +297,7 @@ void menuModelLimits(event_t event) break; } #endif - if (ld->max >= 0) { + if (ld->max >= -PREC_THRESHOLD) { lcdDrawNumber(LIMITS_MAX_POS, y, MIN_MAX_DISPLAY(ld->max+LIMITS_MIN_MAX_OFFSET)/10, RIGHT); } else { From 72b1ad085f7b994b7fb5b63a88f57564a040fb31 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sat, 29 Apr 2017 03:03:53 -0400 Subject: [PATCH 177/203] [Companion] Show custom channel, G-Var, and Curve names throughout UI. (#4874) * [Companion] Move RadioData constructor. * [Companion] Move getCapability(SwitchPositions) to Boards class. * [Companion] Show custom channel, g-var, & curve names throughout UI; Remove redundant name formatting and other unused functions in ModelPrinter and Helpers; Add CustomFunctionData::isEmpty(). * [Companion] Add LogicalSwitchData::isEmpty(). * [Companion] Fix small bug in HardwarePanel. * [Companion] Rename logical switches to "LSw##" in selections lists to avoid confusion with "L#" and "LS" hardware controls; remove unused RotaryEncoderString(). --- companion/src/boards.cpp | 5 + companion/src/boards.h | 1 + companion/src/eeprominterface.cpp | 127 ++++++++++-------- companion/src/eeprominterface.h | 6 - .../src/firmwares/opentx/opentxinterface.cpp | 5 - companion/src/generaledit/hardware.cpp | 6 +- companion/src/generaledit/hardware.h | 2 +- companion/src/helpers.cpp | 97 ++++++------- companion/src/helpers.h | 3 +- companion/src/modeledit/channels.cpp | 2 +- companion/src/modeledit/customfunctions.cpp | 20 +-- companion/src/modeledit/logicalswitches.cpp | 2 +- companion/src/modeledit/mixes.cpp | 4 +- companion/src/modeledit/setup.cpp | 2 +- companion/src/modelprinter.cpp | 56 +++----- companion/src/modelprinter.h | 6 +- companion/src/multimodelprinter.cpp | 13 +- companion/src/radiodata.cpp | 12 +- companion/src/radiodata.h | 10 +- 19 files changed, 180 insertions(+), 199 deletions(-) diff --git a/companion/src/boards.cpp b/companion/src/boards.cpp index d5d885b6a..2214e4c1d 100644 --- a/companion/src/boards.cpp +++ b/companion/src/boards.cpp @@ -211,6 +211,11 @@ const int Boards::getCapability(Board::Type board, Board::Capability capability) return 8; else return 7; + case SwitchPositions: + if (IS_HORUS_OR_TARANIS(board)) + return getCapability(board, Switches) * 3; + else + return 9; case NumTrims: if (IS_HORUS(board)) return 6; diff --git a/companion/src/boards.h b/companion/src/boards.h index d399b7a09..ce9e15695 100644 --- a/companion/src/boards.h +++ b/companion/src/boards.h @@ -111,6 +111,7 @@ namespace Board { Sliders, MouseAnalogs, Switches, + SwitchPositions, FactoryInstalledSwitches, NumTrims, NumTrimSwitches diff --git a/companion/src/eeprominterface.cpp b/companion/src/eeprominterface.cpp index ae8bad2bc..05cfb4c0d 100644 --- a/companion/src/eeprominterface.cpp +++ b/companion/src/eeprominterface.cpp @@ -134,27 +134,6 @@ int TimToVal(float value) return (temp-129); } -QString getSignedStr(int value) -{ - return value > 0 ? QString("+%1").arg(value) : QString("%1").arg(value); -} - -QString getGVarString(int16_t val, bool sign) -{ - if (val >= -10000 && val <= 10000) { - if (sign) - return QString("%1%").arg(getSignedStr(val)); - else - return QString("%1%").arg(val); - } - else { - if (val<0) - return QObject::tr("-GV%1").arg(-val-10000); - else - return QObject::tr("GV%1").arg(val-10000); - } -} - void SensorData::updateUnit() { if (type == TELEM_TYPE_CALCULATED) { @@ -494,17 +473,6 @@ RawSourceRange RawSource::getRange(const ModelData * model, const GeneralSetting return result; } -QString RotaryEncoderString(int index) -{ - static const QString rotary[] = { QObject::tr("REa"), QObject::tr("REb") }; - return CHECK_IN_ARRAY(rotary, index); -} - - -/* - * RawSource - */ - QString RawSource::toString(const ModelData * model, const GeneralSettings * const generalSettings) const { static const QString trims[] = { @@ -530,6 +498,8 @@ QString RawSource::toString(const ModelData * model, const GeneralSettings * con QObject::tr("ACC"), QObject::tr("GPS Time"), }; + static const QString rotary[] = { QObject::tr("REa"), QObject::tr("REb") }; + if (index<0) { return QObject::tr("----"); } @@ -539,8 +509,8 @@ QString RawSource::toString(const ModelData * model, const GeneralSettings * con switch (type) { case SOURCE_TYPE_VIRTUAL_INPUT: result = QObject::tr("[I%1]").arg(index+1); - if (model) - result += QString(model->inputNames[index]); + if (model && model->inputNames[index][0]) + result.append(":" + QString(model->inputNames[index]).trimmed()); return result; case SOURCE_TYPE_LUA_OUTPUT: @@ -562,7 +532,7 @@ QString RawSource::toString(const ModelData * model, const GeneralSettings * con case SOURCE_TYPE_TRIM: return CHECK_IN_ARRAY(trims, index); case SOURCE_TYPE_ROTARY_ENCODER: - return RotaryEncoderString(index); + return CHECK_IN_ARRAY(rotary, index); case SOURCE_TYPE_MAX: return QObject::tr("MAX"); @@ -574,7 +544,7 @@ QString RawSource::toString(const ModelData * model, const GeneralSettings * con return result; case SOURCE_TYPE_CUSTOM_SWITCH: - return QObject::tr("L%1").arg(index+1); + return QObject::tr("LSw%1").arg(index+1, 2, 10, QChar('0')); case SOURCE_TYPE_CYC: return QObject::tr("CYC%1").arg(index+1); @@ -583,7 +553,10 @@ QString RawSource::toString(const ModelData * model, const GeneralSettings * con return QObject::tr("TR%1").arg(index+1); case SOURCE_TYPE_CH: - return QObject::tr("CH%1").arg(index+1); + result = QObject::tr("CH%1").arg(index+1, 2, 10, QChar('0')); + if (getCurrentFirmware()->getCapability(ChannelsName) && model && model->limitData[index].name[0]) + result.append(":" + QString(model->limitData[index].name).trimmed()); + return result; case SOURCE_TYPE_SPECIAL: return CHECK_IN_ARRAY(special, index); @@ -601,7 +574,10 @@ QString RawSource::toString(const ModelData * model, const GeneralSettings * con } case SOURCE_TYPE_GVAR: - return QObject::tr("GV%1").arg(index+1); + result = QObject::tr("GV%1").arg(index+1); + if (getCurrentFirmware()->getCapability(GvarsName) && model && model->gvars_names[index][0]) + result.append(":" + QString(model->gvars_names[index]).trimmed()); + return result; default: return QObject::tr("----"); @@ -706,7 +682,7 @@ QString RawSwitch::toString(Board::Type board, const GeneralSettings * const gen } case SWITCH_TYPE_VIRTUAL: - return QObject::tr("L%1").arg(index); + return QObject::tr("LSw%1").arg(index, 2, 10, QChar('0')); case SWITCH_TYPE_MULTIPOS_POT: if (!getCurrentFirmware()->getCapability(MultiposPotsPositions)) @@ -753,23 +729,48 @@ QString RawSwitch::toString(Board::Type board, const GeneralSettings * const gen * CurveReference */ -QString CurveReference::toString() const +QString CurveReference::toString(const ModelData * model, bool verbose) const { if (value == 0) { return "----"; } - else { - switch(type) { - case CURVE_REF_DIFF: - return QObject::tr("Diff(%1)").arg(getGVarString(value)); - case CURVE_REF_EXPO: - return QObject::tr("Expo(%1)").arg(getGVarString(value)); - case CURVE_REF_FUNC: - return QObject::tr("Function(%1)").arg(QString("x>0" "x<0" "|x|" "f>0" "f<0" "|f|").mid(3*(value-1), 3)); - default: - return QString(value > 0 ? QObject::tr("Curve(%1)") : QObject::tr("!Curve(%1)")).arg(abs(value)); - } + + QString ret; + unsigned idx = abs(value) - 1; + + switch(type) { + case CURVE_REF_DIFF: + ret = QObject::tr("Diff(%1)").arg(Helpers::getAdjustmentString(value, model)); + break; + + case CURVE_REF_EXPO: + ret = QObject::tr("Expo(%1)").arg(Helpers::getAdjustmentString(value, model)); + break; + + case CURVE_REF_FUNC: + ret = QString("x>0" "x<0" "|x|" "f>0" "f<0" "|f|").mid(3*(value-1), 3); + if (verbose) + ret = QObject::tr("Function(%1)").arg(ret); + break; + + default: + if (model) + ret = model->curves[idx].nameToString(idx); + else + ret = CurveData().nameToString(idx); + if (verbose) + ret = QObject::tr("Curve(%1)").arg(ret); + if (value < 0) + ret.prepend(CPN_STR_SW_INDICATOR_REV); + break; } + + return ret; +} + +bool LogicalSwitchData::isEmpty() const +{ + return (func == 0); } CSFunctionFamily LogicalSwitchData::getFunctionFamily() const @@ -856,10 +857,15 @@ void CustomFunctionData::clear() } } -QString CustomFunctionData::funcToString() const +bool CustomFunctionData::isEmpty() const +{ + return (swtch.type == SWITCH_TYPE_NONE); +} + +QString CustomFunctionData::funcToString(const ModelData * model) const { if (func >= FuncOverrideCH1 && func <= FuncOverrideCH32) - return QObject::tr("Override %1").arg(RawSource(SOURCE_TYPE_CH, func).toString()); + return QObject::tr("Override %1").arg(RawSource(SOURCE_TYPE_CH, func).toString(model)); else if (func == FuncTrainer) return QObject::tr("Trainer"); else if (func == FuncTrainerRUD) @@ -903,7 +909,7 @@ QString CustomFunctionData::funcToString() const else if (func == FuncBackgroundMusicPause) return QObject::tr("Background Music Pause"); else if (func >= FuncAdjustGV1 && func <= FuncAdjustGVLast) - return QObject::tr("Adjust GV%1").arg(func-FuncAdjustGV1+1); + return QObject::tr("Adjust %1").arg(RawSource(SOURCE_TYPE_GVAR, func-FuncAdjustGV1).toString(model)); else if (func == FuncSetFailsafeInternalModule) return QObject::tr("SetFailsafe Int. Module"); else if (func == FuncSetFailsafeExternalModule) @@ -1078,6 +1084,14 @@ bool CurveData::isEmpty() const return true; } +QString CurveData::nameToString(const int idx) const +{ + QString ret = QCoreApplication::translate("CurveData", "CV%1").arg(idx+1, 2, 10, QChar('0')); + if (name[0]) + ret.append(":" + QString(name).trimmed()); + return ret; +} + QString LimitData::minToString() const { return QString::number((qreal)min/10); @@ -1504,11 +1518,6 @@ void ModelData::clearMixes() mixData[i].clear(); } -RadioData::RadioData() -{ - models.resize(getCurrentFirmware()->getCapability(Models)); -} - void ModelData::clear() { memset(this, 0, sizeof(ModelData)); diff --git a/companion/src/eeprominterface.h b/companion/src/eeprominterface.h index 1857cf410..0674f29dc 100644 --- a/companion/src/eeprominterface.h +++ b/companion/src/eeprominterface.h @@ -30,8 +30,6 @@ #include #include -QString RotaryEncoderString(int index); - const uint8_t modn12x3[4][4]= { {1, 2, 3, 4}, {1, 3, 2, 4}, @@ -52,7 +50,6 @@ enum Capability { VoicesMaxLength, MultiLangVoice, ModelImage, - SwitchesPositions, CustomFunctions, SafetyChannelCustomFunction, LogicalSwitches, @@ -187,9 +184,6 @@ void getEEPROMString(char *dst, const char *src, int size); float ValToTim(int value); int TimToVal(float value); -QString getSignedStr(int value); -QString getGVarString(int16_t val, bool sign=false); - inline int applyStickMode(int stick, unsigned int mode) { if (mode == 0 || mode > 4) { diff --git a/companion/src/firmwares/opentx/opentxinterface.cpp b/companion/src/firmwares/opentx/opentxinterface.cpp index 874cf46d3..c5e6bebf3 100644 --- a/companion/src/firmwares/opentx/opentxinterface.cpp +++ b/companion/src/firmwares/opentx/opentxinterface.cpp @@ -489,11 +489,6 @@ int OpenTxFirmware::getCapability(::Capability capability) return 0; case PermTimers: return (IS_2560(board) || IS_ARM(board)); - case SwitchesPositions: - if (IS_HORUS_OR_TARANIS(board)) - return getBoardCapability(board, Board::Switches) * 3; - else - return 9; case CustomFunctions: if (IS_ARM(board)) return 64; diff --git a/companion/src/generaledit/hardware.cpp b/companion/src/generaledit/hardware.cpp index db714a8da..3851e2a0c 100644 --- a/companion/src/generaledit/hardware.cpp +++ b/companion/src/generaledit/hardware.cpp @@ -21,7 +21,7 @@ #include "hardware.h" #include "ui_hardware.h" -void HardwarePanel::setupSwitchType(int index, QLabel * label, AutoLineEdit * name, AutoComboBox * type, bool threePos = true) +void HardwarePanel::setupSwitchType(int index, QLabel * label, AutoLineEdit * name, AutoComboBox * type, bool threePos) { Board::Type board = getCurrentBoard(); if (IS_STM32(board) && index < getBoardCapability(board, Board::Switches)) { @@ -92,7 +92,7 @@ HardwarePanel::HardwarePanel(QWidget * parent, GeneralSettings & generalSettings ui(new Ui::Hardware) { ui->setupUi(this); - + Board::Type board = firmware->getBoard(); if (IS_STM32(board)) { @@ -163,7 +163,7 @@ HardwarePanel::HardwarePanel(QWidget * parent, GeneralSettings & generalSettings ui->bluetoothEnable->hide(); ui->bluetoothName->hide(); } - + if (IS_HORUS_OR_TARANIS(board)) { ui->filterEnable->setChecked(!generalSettings.jitterFilter); } diff --git a/companion/src/generaledit/hardware.h b/companion/src/generaledit/hardware.h index a067e4431..af7a2237a 100644 --- a/companion/src/generaledit/hardware.h +++ b/companion/src/generaledit/hardware.h @@ -56,7 +56,7 @@ class HardwarePanel : public GeneralPanel protected: void setupPotType(int index, QLabel * label, AutoLineEdit * name, AutoComboBox * type); void setupSliderType(int index, QLabel * label, AutoLineEdit * name, AutoComboBox * type); - void setupSwitchType(int index, QLabel * label, AutoLineEdit * name, AutoComboBox * type, bool threePos); + void setupSwitchType(int index, QLabel * label, AutoLineEdit * name, AutoComboBox * type, bool threePos = true); private: Ui::Hardware *ui; diff --git a/companion/src/helpers.cpp b/companion/src/helpers.cpp index 68afcc79d..a566b2d93 100644 --- a/companion/src/helpers.cpp +++ b/companion/src/helpers.cpp @@ -225,7 +225,7 @@ void CurveGroup::update() lastType = curve.type; curveValueCB->clear(); for (int i=0; i<=6/*TODO constant*/; i++) { - curveValueCB->addItem(CurveReference(CurveReference::CURVE_REF_FUNC, i).toString()); + curveValueCB->addItem(CurveReference(CurveReference::CURVE_REF_FUNC, i).toString(&model, false)); } } curveValueCB->setCurrentIndex(curve.value); @@ -237,7 +237,7 @@ void CurveGroup::update() lastType = curve.type; curveValueCB->clear(); for (int i= ((flags & HIDE_NEGATIVE_CURVES) ? 0 : -numcurves); i<=numcurves; i++) { - curveValueCB->addItem(CurveReference(CurveReference::CURVE_REF_CUSTOM, i).toString(), i); + curveValueCB->addItem(CurveReference(CurveReference::CURVE_REF_CUSTOM, i).toString(&model, false), i); if (i == curve.value) { curveValueCB->setCurrentIndex(curveValueCB->count() - 1); } @@ -324,38 +324,43 @@ void CurveGroup::valuesChanged() void Helpers::populateGVCB(QComboBox & b, int value, const ModelData & model) { - bool selected = false; + int count = getCurrentFirmware()->getCapability(Gvars); b.clear(); - int count = getCurrentFirmware()->getCapability(Gvars); for (int i=-count; i<=-1; i++) { int16_t gval = (int16_t)(-10000+i); - if (strlen(model.gvars_names[-i-1]) > 0) - b.addItem(QObject::tr("-GV%1 (%2)").arg(-i).arg(model.gvars_names[-i-1]), gval); - else - b.addItem(QObject::tr("-GV%1").arg(-i), gval); - if (value == gval) { - b.setCurrentIndex(b.count()-1); - selected = true; - } + b.addItem("-" + RawSource(SOURCE_TYPE_GVAR, abs(i)-1).toString(&model), gval); } for (int i=1; i<=count; i++) { int16_t gval = (int16_t)(10000+i); - if (strlen(model.gvars_names[i-1]) > 0) - b.addItem(QObject::tr("GV%1 (%2)").arg(i).arg(model.gvars_names[i-1]), gval); - else - b.addItem(QObject::tr("GV%1").arg(i), gval); - if (value == gval) { - b.setCurrentIndex(b.count()-1); - selected = true; - } + b.addItem(RawSource(SOURCE_TYPE_GVAR, i-1).toString(&model), gval); } - if (!selected) { + b.setCurrentIndex(b.findData(value)); + if (b.currentIndex() == -1) b.setCurrentIndex(count); +} + +// Returns Diff/Expo/Weight/Offset adjustment value as either a percentage or a global variable name. +QString Helpers::getAdjustmentString(int16_t val, const ModelData * model, bool sign) +{ + QString ret; + if (val >= -10000 && val <= 10000) { + ret = "%1%"; + if (sign && val > 0) + ret.prepend("+"); + ret = ret.arg(val); } + else { + ret = RawSource(SOURCE_TYPE_GVAR, abs(val) - 10001).toString(model); + if (val < 0) + ret.prepend("-"); + else if (sign) + ret.prepend("+"); + } + return ret; } void Helpers::populateGvarUseCB(QComboBox * b, unsigned int phase) @@ -368,29 +373,6 @@ void Helpers::populateGvarUseCB(QComboBox * b, unsigned int phase) } } -void Helpers::populateGvSourceCB(QComboBox * b, int value) -{ - QString strings[] = { QObject::tr("---"), QObject::tr("Rud Trim"), QObject::tr("Ele Trim"), QObject::tr("Thr Trim"), QObject::tr("Ail Trim"), QObject::tr("Rot Enc"), QObject::tr("Rud"), QObject::tr("Ele"), QObject::tr("Thr"), QObject::tr("Ail"), QObject::tr("P1"), QObject::tr("P2"), QObject::tr("P3")}; - b->clear(); - for (int i=0; i<= 12; i++) { - b->addItem(strings[i]); - } - b->setCurrentIndex(value); -} - -void Helpers::populatePhasesCB(QComboBox * b, int value) -{ - for (int i=-getCurrentFirmware()->getCapability(FlightModes); i<=getCurrentFirmware()->getCapability(FlightModes); i++) { - if (i < 0) - b->addItem(QObject::tr("!Flight mode %1").arg(-i-1), i); - else if (i > 0) - b->addItem(QObject::tr("Flight mode %1").arg(i-1), i); - else - b->addItem(QObject::tr("----"), 0); - } - b->setCurrentIndex(value + getCurrentFirmware()->getCapability(FlightModes)); -} - void Helpers::populateFileComboBox(QComboBox * b, const QSet & set, const QString & current) { b->clear(); @@ -456,21 +438,22 @@ void Helpers::addRawSwitchItems(QStandardItemModel * itemModel, const RawSwitchT QStandardItemModel * Helpers::getRawSwitchItemModel(const GeneralSettings * const generalSettings, SwitchContext context) { QStandardItemModel * itemModel = new QStandardItemModel(); - Board::Type board = getCurrentBoard(); + Boards board = Boards(getCurrentBoard()); + Board::Type btype = board.getBoardType(); Firmware * fw = getCurrentFirmware(); // Descending switch direction: NOT (!) switches - if (context != MixesContext && context != GlobalFunctionsContext && IS_ARM(board)) { + if (context != MixesContext && context != GlobalFunctionsContext && IS_ARM(btype)) { addRawSwitchItems(itemModel, SWITCH_TYPE_FLIGHT_MODE, -fw->getCapability(FlightModes), generalSettings); } if (context != GlobalFunctionsContext) { addRawSwitchItems(itemModel, SWITCH_TYPE_VIRTUAL, -fw->getCapability(LogicalSwitches), generalSettings); } addRawSwitchItems(itemModel, SWITCH_TYPE_ROTARY_ENCODER, -fw->getCapability(RotaryEncoders), generalSettings); - addRawSwitchItems(itemModel, SWITCH_TYPE_TRIM, -getBoardCapability(board, Board::NumTrimSwitches), generalSettings); + addRawSwitchItems(itemModel, SWITCH_TYPE_TRIM, -board.getCapability(Board::NumTrimSwitches), generalSettings); addRawSwitchItems(itemModel, SWITCH_TYPE_MULTIPOS_POT, -(fw->getCapability(MultiposPots) * fw->getCapability(MultiposPotsPositions)), generalSettings); - addRawSwitchItems(itemModel, SWITCH_TYPE_SWITCH, -fw->getCapability(SwitchesPositions), generalSettings); + addRawSwitchItems(itemModel, SWITCH_TYPE_SWITCH, -board.getCapability(Board::SwitchPositions), generalSettings); // Ascending switch direction (including zero) @@ -481,14 +464,14 @@ QStandardItemModel * Helpers::getRawSwitchItemModel(const GeneralSettings * cons addRawSwitchItems(itemModel, SWITCH_TYPE_NONE, 1); } - addRawSwitchItems(itemModel, SWITCH_TYPE_SWITCH, fw->getCapability(SwitchesPositions), generalSettings); + addRawSwitchItems(itemModel, SWITCH_TYPE_SWITCH, board.getCapability(Board::SwitchPositions), generalSettings); addRawSwitchItems(itemModel, SWITCH_TYPE_MULTIPOS_POT, fw->getCapability(MultiposPots) * fw->getCapability(MultiposPotsPositions), generalSettings); - addRawSwitchItems(itemModel, SWITCH_TYPE_TRIM, getBoardCapability(board, Board::NumTrimSwitches), generalSettings); + addRawSwitchItems(itemModel, SWITCH_TYPE_TRIM, board.getCapability(Board::NumTrimSwitches), generalSettings); addRawSwitchItems(itemModel, SWITCH_TYPE_ROTARY_ENCODER, fw->getCapability(RotaryEncoders), generalSettings); if (context != GlobalFunctionsContext) { addRawSwitchItems(itemModel, SWITCH_TYPE_VIRTUAL, fw->getCapability(LogicalSwitches), generalSettings); } - if (context != MixesContext && context != GlobalFunctionsContext && IS_ARM(board)) { + if (context != MixesContext && context != GlobalFunctionsContext && IS_ARM(btype)) { addRawSwitchItems(itemModel, SWITCH_TYPE_FLIGHT_MODE, fw->getCapability(FlightModes), generalSettings); } if (context == SpecialFunctionsContext || context == GlobalFunctionsContext) { @@ -530,7 +513,7 @@ void Helpers::addRawSourceItems(QStandardItemModel * itemModel, const RawSourceT QStandardItemModel * Helpers::getRawSourceItemModel(const GeneralSettings * const generalSettings, const ModelData * const model, unsigned int flags) { QStandardItemModel * itemModel = new QStandardItemModel(); - Board::Type board = getCurrentBoard(); + Boards board = Boards(getCurrentBoard()); Firmware * fw = getCurrentFirmware(); if (flags & POPULATE_NONE) { @@ -548,13 +531,13 @@ QStandardItemModel * Helpers::getRawSourceItemModel(const GeneralSettings * cons } if (flags & POPULATE_SOURCES) { - int totalSources = CPN_MAX_STICKS + getBoardCapability(board, Board::Pots) + getBoardCapability(board, Board::Sliders) + getBoardCapability(board, Board::MouseAnalogs); + int totalSources = CPN_MAX_STICKS + board.getCapability(Board::Pots) + board.getCapability(Board::Sliders) + board.getCapability(Board::MouseAnalogs); addRawSourceItems(itemModel, SOURCE_TYPE_STICK, totalSources, generalSettings, model); addRawSourceItems(itemModel, SOURCE_TYPE_ROTARY_ENCODER, fw->getCapability(RotaryEncoders), generalSettings, model); } if (flags & POPULATE_TRIMS) { - addRawSourceItems(itemModel, SOURCE_TYPE_TRIM, getBoardCapability(board, Board::NumTrims), generalSettings, model); + addRawSourceItems(itemModel, SOURCE_TYPE_TRIM, board.getCapability(Board::NumTrims), generalSettings, model); } if (flags & POPULATE_SOURCES) { @@ -562,7 +545,7 @@ QStandardItemModel * Helpers::getRawSourceItemModel(const GeneralSettings * cons } if (flags & POPULATE_SWITCHES) { - addRawSourceItems(itemModel, SOURCE_TYPE_SWITCH, getBoardCapability(board, Board::Switches), generalSettings, model); + addRawSourceItems(itemModel, SOURCE_TYPE_SWITCH, board.getCapability(Board::Switches), generalSettings, model); addRawSourceItems(itemModel, SOURCE_TYPE_CUSTOM_SWITCH, fw->getCapability(LogicalSwitches), generalSettings, model); } @@ -573,7 +556,7 @@ QStandardItemModel * Helpers::getRawSourceItemModel(const GeneralSettings * cons } if (flags & POPULATE_TELEMETRY) { - if (IS_ARM(board)) { + if (IS_ARM(board.getBoardType())) { addRawSourceItems(itemModel, SOURCE_TYPE_SPECIAL, 5, generalSettings, model); if (model) { @@ -593,7 +576,7 @@ QStandardItemModel * Helpers::getRawSourceItemModel(const GeneralSettings * cons exclude << TELEMETRY_SOURCE_TX_TIME; if (!fw->getCapability(SportTelemetry)) exclude << TELEMETRY_SOURCE_SWR; - if (!IS_ARM(board)) + if (!IS_ARM(board.getBoardType())) exclude << TELEMETRY_SOURCE_TIMER3; int count = ((flags & POPULATE_TELEMETRYEXT) ? TELEMETRY_SOURCES_STATUS_COUNT : TELEMETRY_SOURCES_COUNT); addRawSourceItems(itemModel, SOURCE_TYPE_TELEMETRY, count, generalSettings, model, 0, exclude); diff --git a/companion/src/helpers.h b/companion/src/helpers.h index 24e2375b2..ebfe970ff 100644 --- a/companion/src/helpers.h +++ b/companion/src/helpers.h @@ -146,9 +146,8 @@ namespace Helpers QStandardItemModel * getRawSourceItemModel(const GeneralSettings * const generalSettings = NULL, const ModelData * const model = NULL, unsigned int flags = 0); void populateGvarUseCB(QComboBox *b, unsigned int phase); - void populateGvSourceCB(QComboBox *b, int value); - void populatePhasesCB(QComboBox *b, int value); void populateGVCB(QComboBox & b, int value, const ModelData & model); + QString getAdjustmentString(int16_t val, const ModelData * model = NULL, bool sign = false); void populateFileComboBox(QComboBox * b, const QSet & set, const QString & current); void getFileComboBoxValue(QComboBox * b, char * dest, int length); diff --git a/companion/src/modeledit/channels.cpp b/companion/src/modeledit/channels.cpp index 1cdfd5376..8fe25b010 100644 --- a/companion/src/modeledit/channels.cpp +++ b/companion/src/modeledit/channels.cpp @@ -156,7 +156,7 @@ Channels::Channels(QWidget * parent, ModelData & model, GeneralSettings & genera curveCB->setProperty("index", i); int numcurves = firmware->getCapability(NumCurves); for (int j=-numcurves; j<=numcurves; j++) { - curveCB->addItem(CurveReference(CurveReference::CURVE_REF_CUSTOM, j).toString(), j); + curveCB->addItem(CurveReference(CurveReference::CURVE_REF_CUSTOM, j).toString(&model, false), j); } curveCB->setCurrentIndex(model.limitData[i].curve.value+numcurves); connect(curveCB, SIGNAL(currentIndexChanged(int)), this, SLOT(curveEdited())); diff --git a/companion/src/modeledit/customfunctions.cpp b/companion/src/modeledit/customfunctions.cpp index 514ea01d0..07576ff96 100644 --- a/companion/src/modeledit/customfunctions.cpp +++ b/companion/src/modeledit/customfunctions.cpp @@ -337,6 +337,7 @@ void CustomFunctionsPanel::playMusic() #define CUSTOM_FUNCTION_REPEAT (1<<7) #define CUSTOM_FUNCTION_PLAY (1<<8) #define CUSTOM_FUNCTION_BL_COLOR (1<<9) +#define CUSTOM_FUNCTION_SHOW_FUNC (1<<10) void CustomFunctionsPanel::customFunctionEdited() { @@ -357,7 +358,7 @@ void CustomFunctionsPanel::functionEdited() RawSwitch swtch = functions[index].swtch; functions[index].clear(); functions[index].swtch = swtch; - functions[index].func = (AssignFunc)fswtchFunc[index]->itemData(fswtchFunc[index]->currentIndex()).toInt(); + functions[index].func = (AssignFunc)fswtchFunc[index]->currentData().toInt(); refreshCustomFunction(index); emit modified(); lock = false; @@ -382,7 +383,8 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) cfn.adjustMode = (AssignFunc)fswtchGVmode[i]->currentIndex(); } - if (cfn.swtch.toValue()) { + if (!cfn.isEmpty()) { + widgetsMask |= CUSTOM_FUNCTION_SHOW_FUNC; if (func>=FuncOverrideCH1 && func<=FuncOverrideCH32) { if (model) { @@ -395,7 +397,7 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) cfn.param = fswtchParam[i]->value(); } fswtchParam[i]->setValue(cfn.param); - widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM + CUSTOM_FUNCTION_ENABLE; + widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM | CUSTOM_FUNCTION_ENABLE; } } else if (func==FuncLogs) { @@ -456,7 +458,7 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) if (modified) cfn.param = fswtchParamT[i]->currentData().toInt(); populateFuncParamCB(fswtchParamT[i], func, cfn.param); - widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM + CUSTOM_FUNCTION_ENABLE; + widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM | CUSTOM_FUNCTION_ENABLE; } else if (func==FuncPlaySound || func==FuncPlayHaptic || func==FuncPlayValue || func==FuncPlayPrompt || func==FuncPlayBoth || func==FuncBackgroundMusic) { if (func != FuncBackgroundMusic) { @@ -467,7 +469,7 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) if (modified) cfn.param = fswtchParamT[i]->currentData().toInt(); populateFuncParamCB(fswtchParamT[i], func, cfn.param); - widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM + CUSTOM_FUNCTION_REPEAT; + widgetsMask |= CUSTOM_FUNCTION_SOURCE_PARAM | CUSTOM_FUNCTION_REPEAT; } else if (func==FuncPlayPrompt || func==FuncPlayBoth) { if (firmware->getCapability(VoicesAsNumbers)) { @@ -475,10 +477,10 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) fswtchParam[i]->setSingleStep(1); fswtchParam[i]->setMinimum(0); if (func==FuncPlayPrompt) { - widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM + CUSTOM_FUNCTION_REPEAT + CUSTOM_FUNCTION_GV_TOOGLE; + widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM | CUSTOM_FUNCTION_REPEAT | CUSTOM_FUNCTION_GV_TOOGLE; } else { - widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM + CUSTOM_FUNCTION_REPEAT; + widgetsMask |= CUSTOM_FUNCTION_NUMERIC_PARAM | CUSTOM_FUNCTION_REPEAT; fswtchParamGV[i]->setChecked(false); } fswtchParam[i]->setMaximum(func==FuncPlayBoth ? 254 : 255); @@ -563,7 +565,7 @@ void CustomFunctionsPanel::refreshCustomFunction(int i, bool modified) } - fswtchFunc[i]->setVisible(cfn.swtch.toValue()); + fswtchFunc[i]->setVisible(widgetsMask & CUSTOM_FUNCTION_SHOW_FUNC); fswtchParam[i]->setVisible(widgetsMask & CUSTOM_FUNCTION_NUMERIC_PARAM); fswtchParamTime[i]->setVisible(widgetsMask & CUSTOM_FUNCTION_TIME_PARAM); fswtchParamGV[i]->setVisible(widgetsMask & CUSTOM_FUNCTION_GV_TOOGLE); @@ -678,7 +680,7 @@ void CustomFunctionsPanel::populateFuncCB(QComboBox *b, unsigned int value) // b->model()->setData(index, v, Qt::UserRole - 1); } else { - b->addItem(CustomFunctionData(AssignFunc(i)).funcToString(), i); + b->addItem(CustomFunctionData(AssignFunc(i)).funcToString(model), i); if (i == value) { b->setCurrentIndex(b->count()-1); } diff --git a/companion/src/modeledit/logicalswitches.cpp b/companion/src/modeledit/logicalswitches.cpp index c60616633..60b535549 100644 --- a/companion/src/modeledit/logicalswitches.cpp +++ b/companion/src/modeledit/logicalswitches.cpp @@ -468,7 +468,7 @@ void LogicalSwitchesPanel::populateAndSwitchCB(QComboBox *b, const RawSwitch & v b->addItem(item.toString(), item.toValue()); if (item == value) b->setCurrentIndex(b->count()-1); - for (int i=1; i<=firmware->getCapability(SwitchesPositions); i++) { + for (int i=1; i <= Boards::getCapability(firmware->getBoard(), Board::SwitchPositions); i++) { item = RawSwitch(SWITCH_TYPE_SWITCH, i); b->addItem(item.toString(), item.toValue()); if (item == value) b->setCurrentIndex(b->count()-1); diff --git a/companion/src/modeledit/mixes.cpp b/companion/src/modeledit/mixes.cpp index 08427b4f8..26a8399c9 100644 --- a/companion/src/modeledit/mixes.cpp +++ b/companion/src/modeledit/mixes.cpp @@ -140,7 +140,7 @@ QString MixesPanel::getMixerText(int dest, bool * new_ch) QString str; bool newChannel = false; if (dest < 0) { - str = modelPrinter.printMixerName(-dest); + str = modelPrinter.printChannelName(abs(dest)-1); //highlight channel if needed if (-dest == (int)highlightedSource) { str = "" + str + ""; @@ -150,7 +150,7 @@ QString MixesPanel::getMixerText(int dest, bool * new_ch) else { MixData & mix = model->mixData[dest]; //mix->destCh from 1 to 32 - str = modelPrinter.printMixerName(mix.destCh); + str = modelPrinter.printChannelName(mix.destCh-1); if ((dest == 0) || (model->mixData[dest-1].destCh != mix.destCh)) { newChannel = true; diff --git a/companion/src/modeledit/setup.cpp b/companion/src/modeledit/setup.cpp index ec27a331f..64aee0af8 100644 --- a/companion/src/modeledit/setup.cpp +++ b/companion/src/modeledit/setup.cpp @@ -1104,7 +1104,7 @@ void SetupPanel::populateThrottleSourceCB() ui->throttleSource->addItem(firmware->getAnalogInputName(4+i), i); } for (int i=0; igetCapability(Outputs); i++) { - ui->throttleSource->addItem(ModelPrinter::printChannelName(i)); + ui->throttleSource->addItem(RawSource(SOURCE_TYPE_CH, i).toString(model, &generalSettings)); } ui->throttleSource->setCurrentIndex(model->thrTraceSrc); lock = false; diff --git a/companion/src/modelprinter.cpp b/companion/src/modelprinter.cpp index 79d26dbd0..b7e0a1e95 100644 --- a/companion/src/modelprinter.cpp +++ b/companion/src/modelprinter.cpp @@ -76,18 +76,12 @@ QString ModelPrinter::printEEpromSize() QString ModelPrinter::printChannelName(int idx) { - return tr("CH%1").arg(idx+1, 2, 10, QChar('0')); -} - -QString ModelPrinter::printOutputName(int idx) -{ - QString name = QString(model.limitData[idx].name).trimmed(); - if (firmware->getCapability(ChannelsName) > 0 && !name.isEmpty()) { - return name; - } - else { - return ""; + QString str = RawSource(SOURCE_TYPE_CH, idx).toString(&model, &generalSettings); + if (firmware->getCapability(ChannelsName)) { + str = str.leftJustified(firmware->getCapability(ChannelsName) + 5, ' ', false); } + str.append(' '); + return str.toHtmlEscaped(); } QString ModelPrinter::printTrimIncrementMode() @@ -368,9 +362,9 @@ QString ModelPrinter::printInputLine(const ExpoData & input) str += input.srcRaw.toString(&model, &generalSettings).toHtmlEscaped(); } - str += " " + tr("Weight").toHtmlEscaped() + QString("(%1)").arg(getGVarString(input.weight,true).toHtmlEscaped()); + str += " " + tr("Weight").toHtmlEscaped() + QString("(%1)").arg(Helpers::getAdjustmentString(input.weight, &model, true).toHtmlEscaped()); if (input.curve.value) - str += " " + input.curve.toString().toHtmlEscaped(); + str += " " + input.curve.toString(&model).toHtmlEscaped(); QString flightModesStr = printFlightModes(input.flightModes); if (!flightModesStr.isEmpty()) @@ -388,7 +382,7 @@ QString ModelPrinter::printInputLine(const ExpoData & input) } if (input.offset) - str += " " + tr("Offset(%1)").arg(getGVarString(input.offset)).toHtmlEscaped(); + str += " " + tr("Offset(%1)").arg(Helpers::getAdjustmentString(input.offset, &model)).toHtmlEscaped(); if (firmware->getCapability(HasExpoNames) && input.name[0]) str += QString(" [%1]").arg(input.name).toHtmlEscaped(); @@ -396,25 +390,6 @@ QString ModelPrinter::printInputLine(const ExpoData & input) return str; } -QString ModelPrinter::printMixerName(int curDest) -{ - QString str = printChannelName(curDest-1) + " "; - if (firmware->getCapability(ChannelsName) > 0) { - QString name = model.limitData[curDest-1].name; - if (!name.isEmpty()) { - name = QString("(") + name + QString(")"); - } - name.append(" "); - str += name.left(8); - } - return str.toHtmlEscaped(); -} - -QString ModelPrinter::printMixerLine(int idx, bool showMultiplex, int highlightedSource) -{ - return printMixerLine(model.mixData[idx], highlightedSource, showMultiplex); -} - QString ModelPrinter::printMixerLine(const MixData & mix, bool showMultiplex, int highlightedSource) { QString str = " "; @@ -439,7 +414,7 @@ QString ModelPrinter::printMixerLine(const MixData & mix, bool showMultiplex, in if (mix.mltpx == MLTPX_MUL && !showMultiplex) str += " " + QString("MULT!").toHtmlEscaped(); else - str += " " + tr("Weight(%1)").arg(getGVarString(mix.weight, true)).toHtmlEscaped(); + str += " " + tr("Weight(%1)").arg(Helpers::getAdjustmentString(mix.weight, &model, true)).toHtmlEscaped(); QString flightModesStr = printFlightModes(mix.flightModes); if (!flightModesStr.isEmpty()) @@ -456,9 +431,9 @@ QString ModelPrinter::printMixerLine(const MixData & mix, bool showMultiplex, in if (firmware->getCapability(HasNoExpo) && mix.noExpo) str += " " + tr("No DR/Expo").toHtmlEscaped(); if (mix.sOffset) - str += " " + tr("Offset(%1)").arg(getGVarString(mix.sOffset)).toHtmlEscaped(); + str += " " + tr("Offset(%1)").arg(Helpers::getAdjustmentString(mix.sOffset, &model)).toHtmlEscaped(); if (mix.curve.value) - str += " " + mix.curve.toString().toHtmlEscaped(); + str += " " + mix.curve.toString(&model).toHtmlEscaped(); int scale = firmware->getCapability(SlowScale); if (scale == 0) scale = 1; @@ -519,7 +494,7 @@ QString ModelPrinter::printLogicalSwitchLine(int idx) const QString sw1Name = RawSwitch(ls.val1).toString(getCurrentBoard(), &generalSettings); const QString sw2Name = RawSwitch(ls.val2).toString(getCurrentBoard(), &generalSettings); - if (!ls.func) + if (ls.isEmpty()) return result; if (ls.andsw!=0) { @@ -642,7 +617,7 @@ QString ModelPrinter::printCustomFunctionLine(int idx) return result; result += cf.swtch.toString(getCurrentBoard(), &generalSettings) + " - "; - result += cf.funcToString() + "("; + result += cf.funcToString(&model) + " ("; result += cf.paramToString(&model) + ")"; if (!cf.repeatToString().isEmpty()) result += " " + cf.repeatToString(); @@ -651,6 +626,11 @@ QString ModelPrinter::printCustomFunctionLine(int idx) return result; } +QString ModelPrinter::printCurveName(int idx) +{ + return model.curves[idx].nameToString(idx).toHtmlEscaped(); +} + QString ModelPrinter::printCurve(int idx) { QString result; diff --git a/companion/src/modelprinter.h b/companion/src/modelprinter.h index 68c38105a..2da443de7 100644 --- a/companion/src/modelprinter.h +++ b/companion/src/modelprinter.h @@ -75,13 +75,11 @@ class ModelPrinter: public QObject QString printInputName(int idx); QString printInputLine(int idx); QString printInputLine(const ExpoData & ed); - QString printMixerName(int curDest); - QString printMixerLine(int idx, bool showMultiplex, int highlightedSource = 0); QString printMixerLine(const MixData & md, bool showMultiplex, int highlightedSource = 0); QString printLogicalSwitchLine(int idx); QString printCustomFunctionLine(int idx); - static QString printChannelName(int idx); - QString printOutputName(int idx); + QString printChannelName(int idx); + QString printCurveName(int idx); QString printCurve(int idx); QString createCurveImage(int idx, QTextDocument * document); diff --git a/companion/src/multimodelprinter.cpp b/companion/src/multimodelprinter.cpp index 73df83002..615bd5897 100644 --- a/companion/src/multimodelprinter.cpp +++ b/companion/src/multimodelprinter.cpp @@ -351,7 +351,6 @@ QString MultiModelPrinter::printLimits() columns.append("" \ "" \ " " \ - " " \ " " \ " " \ " " \ @@ -365,8 +364,6 @@ QString MultiModelPrinter::printLimits() continue; columns.append("
" + tr("Channel") + "" + (firmware->getCapability(ChannelsName) > 0 ? tr("Name") : "") + "" + tr("Offset") + "" + tr("Min") + "" + tr("Max") + "
"); COMPARE(modelPrinter->printChannelName(i)); - columns.append(""); - COMPARE(modelPrinter->printOutputName(i)); columns.append(""); COMPARE(model->limitData[i].offsetToString()); columns.append(""); @@ -441,7 +438,7 @@ QString MultiModelPrinter::printMixers() } if (count > 0) { columns.append("
"); - COMPARE(modelPrinter->printMixerName(i+1)); + COMPARE(modelPrinter->printChannelName(i)); columns.append(""); for (int j=0; j 0) @@ -471,7 +468,9 @@ QString MultiModelPrinter::printCurves(QTextDocument * document) } if (!curveEmpty) { count++; - columns.append("
" + tr("CV%1").arg(i+1) + ""); + columns.append("
"); + COMPARE(modelPrinter->printCurveName(i)); + columns.append(""); COMPARE(modelPrinter->printCurve(i)); for (int k=0; k < modelPrinterMap.size(); k++) columns.append(k, QString("
").arg(modelPrinterMap.value(k).second->createCurveImage(i, document))); @@ -495,7 +494,7 @@ QString MultiModelPrinter::printLogicalSwitches() for (int i=0; igetCapability(LogicalSwitches); i++) { bool lsEmpty = true; for (int k=0; k < modelPrinterMap.size(); k++) { - if (!modelPrinterMap.value(k).second->printLogicalSwitchLine(i).isEmpty()) { + if (!modelPrinterMap.value(k).first->logicalSw[i].isEmpty()) { lsEmpty = false; break; } @@ -524,7 +523,7 @@ QString MultiModelPrinter::printCustomFunctions() for (int i=0; i < firmware->getCapability(CustomFunctions); i++) { bool sfEmpty = true; for (int k=0; k < modelPrinterMap.size(); k++) { - if (modelPrinterMap.value(k).first->customFn[i].swtch.type != SWITCH_TYPE_NONE) { + if (!modelPrinterMap.value(k).first->customFn[i].isEmpty()) { sfEmpty = false; break; } diff --git a/companion/src/radiodata.cpp b/companion/src/radiodata.cpp index 6a284b5c5..dfddfa71a 100644 --- a/companion/src/radiodata.cpp +++ b/companion/src/radiodata.cpp @@ -171,6 +171,16 @@ void GeneralSettings::convert(Board::Type before, Board::Type after) } } + +/* + * RadioData +*/ + +RadioData::RadioData() +{ + models.resize(getCurrentFirmware()->getCapability(Models)); +} + void RadioData::setCurrentModel(unsigned int index) { generalSettings.currModelIndex = index; @@ -244,4 +254,4 @@ void RadioData::convert(Board::Type before, Board::Type after) if (IS_HORUS(after)) { fixModelFilenames(); } -} \ No newline at end of file +} diff --git a/companion/src/radiodata.h b/companion/src/radiodata.h index 9fe15f7b9..15d029af8 100644 --- a/companion/src/radiodata.h +++ b/companion/src/radiodata.h @@ -316,7 +316,7 @@ class CurveReference { CurveRefType type; int value; - QString toString() const; + QString toString(const ModelData * model = NULL, bool verbose = true) const; }; enum InputMode { @@ -361,6 +361,8 @@ class CurveData { CurveData(); void clear(int count); bool isEmpty() const; + QString nameToString(const int idx) const; + CurveType type; bool smooth; int count; @@ -468,7 +470,9 @@ class LogicalSwitchData { // Logical Switches data unsigned int delay; unsigned int duration; int andsw; + void clear() { memset(this, 0, sizeof(LogicalSwitchData)); } + bool isEmpty() const; CSFunctionFamily getFunctionFamily() const; unsigned int getRangeFlags() const; QString funcToString() const; @@ -531,8 +535,10 @@ class CustomFunctionData { // Function Switches data unsigned int enabled; // TODO perhaps not any more the right name unsigned int adjustMode; int repeatParam; + void clear(); - QString funcToString() const; + bool isEmpty() const; + QString funcToString(const ModelData * model = NULL) const; QString paramToString(const ModelData * model) const; QString repeatToString() const; QString enabledToString() const; From 0cff67e032ffb3c6cdabf53a6ff2d6b38c3566dd Mon Sep 17 00:00:00 2001 From: 3djc Date: Sat, 29 Apr 2017 09:04:23 +0200 Subject: [PATCH 178/203] Fix some too long translation (#4873) * Fix FR, DE, PL * Such a better fix thanks to @mhotar ! * Create conditional linebreak for 128pixels and Horus, but not X9 * CosmeticsCo --- radio/src/translations.h | 6 ++++++ radio/src/translations/cz.h.txt | 4 +--- radio/src/translations/de.h.txt | 2 +- radio/src/translations/en.h.txt | 2 +- radio/src/translations/es.h.txt | 2 +- radio/src/translations/fi.h.txt | 2 +- radio/src/translations/fr.h.txt | 2 +- radio/src/translations/it.h.txt | 2 +- radio/src/translations/pl.h.txt | 2 +- radio/src/translations/pt.h.txt | 2 +- 10 files changed, 15 insertions(+), 11 deletions(-) diff --git a/radio/src/translations.h b/radio/src/translations.h index 2dfd7b536..fbe7cc953 100644 --- a/radio/src/translations.h +++ b/radio/src/translations.h @@ -92,6 +92,12 @@ #define TR_VTRAINERMODES TR_VTRAINER_MASTER_JACK TR_VTRAINER_SLAVE_JACK TR_VTRAINER_MASTER_CPPM_MODULE TR_VTRAINER_MASTER_BATTERY #endif +#if (LCD_W == 212) + #define LCDW_128_480_LINEBREAK "" +#else + #define LCDW_128_480_LINEBREAK "\036" +#endif + // The non-0-terminated-strings extern const pm_char STR_OPEN9X[]; diff --git a/radio/src/translations/cz.h.txt b/radio/src/translations/cz.h.txt index 25928023d..d31a80589 100644 --- a/radio/src/translations/cz.h.txt +++ b/radio/src/translations/cz.h.txt @@ -40,8 +40,6 @@ * \0 -ends current string */ - - // NON ZERO TERMINATED STRINGS #define LEN_OFFON "\003" #define TR_OFFON "VYP""ZAP" @@ -1227,7 +1225,7 @@ #define TR_DISCOVER_SENSORS INDENT "Detekovat nové senzory" #define TR_STOP_DISCOVER_SENSORS INDENT "Zastavit autodetekci" #define TR_DELETE_ALL_SENSORS INDENT "Odebrat všechny senzory" -#define TR_CONFIRMDELETE "Opravdu odstranit vše?" +#define TR_CONFIRMDELETE "Opravdu " LCDW_128_480_LINEBREAK "odstranit vše ?" #define TR_SELECT_WIDGET "Zvolit widget" #define TR_REMOVE_WIDGET "Odstranit widget" #define TR_WIDGET_SETTINGS "Nastavení widgetu" diff --git a/radio/src/translations/de.h.txt b/radio/src/translations/de.h.txt index 0de76049a..6a3fff20e 100644 --- a/radio/src/translations/de.h.txt +++ b/radio/src/translations/de.h.txt @@ -1243,7 +1243,7 @@ #define TR_DISCOVER_SENSORS INDENT "Start Sensorsuche" #define TR_STOP_DISCOVER_SENSORS INDENT "Stop Sensorsuche" #define TR_DELETE_ALL_SENSORS INDENT "Lösche alle Sensoren" -#define TR_CONFIRMDELETE "Wirklich alle löschen?" +#define TR_CONFIRMDELETE "Wirklich alle " LCDW_128_480_LINEBREAK "löschen ?" #define TR_SELECT_WIDGET "Widget auswählen" // grafisches Element #define TR_REMOVE_WIDGET "Widget löschen" #define TR_WIDGET_SETTINGS "Widget einstellen" diff --git a/radio/src/translations/en.h.txt b/radio/src/translations/en.h.txt index 026344c01..c27b27067 100644 --- a/radio/src/translations/en.h.txt +++ b/radio/src/translations/en.h.txt @@ -1231,7 +1231,7 @@ #define TR_DISCOVER_SENSORS INDENT "Discover new sensors" #define TR_STOP_DISCOVER_SENSORS INDENT "Stop discovery" #define TR_DELETE_ALL_SENSORS INDENT "Delete all sensors" -#define TR_CONFIRMDELETE "Really delete all?" +#define TR_CONFIRMDELETE "Really " LCDW_128_480_LINEBREAK "delete all ?" #define TR_SELECT_WIDGET "Select widget" #define TR_REMOVE_WIDGET "Remove widget" #define TR_WIDGET_SETTINGS "Widget settings" diff --git a/radio/src/translations/es.h.txt b/radio/src/translations/es.h.txt index 2d330ecb5..eb46d0dd7 100644 --- a/radio/src/translations/es.h.txt +++ b/radio/src/translations/es.h.txt @@ -1198,7 +1198,7 @@ #define TR_DISCOVER_SENSORS INDENT "Discover new sensors" #define TR_STOP_DISCOVER_SENSORS INDENT "Stop discovery" #define TR_DELETE_ALL_SENSORS INDENT "Delete all sensors" -#define TR_CONFIRMDELETE "Really delete all?" +#define TR_CONFIRMDELETE "Really " LCDW_128_480_LINEBREAK "delete all ?" #define TR_SELECT_WIDGET "Select widget" #define TR_REMOVE_WIDGET "Remove widget" #define TR_WIDGET_SETTINGS "Widget settings" diff --git a/radio/src/translations/fi.h.txt b/radio/src/translations/fi.h.txt index 6fcc4c61a..f0e38f95f 100644 --- a/radio/src/translations/fi.h.txt +++ b/radio/src/translations/fi.h.txt @@ -1194,7 +1194,7 @@ #define TR_DISCOVER_SENSORS INDENT "Discover new sensors" #define TR_STOP_DISCOVER_SENSORS INDENT "Stop discovery" #define TR_DELETE_ALL_SENSORS INDENT "Delete all sensors" -#define TR_CONFIRMDELETE "Really delete all?" +#define TR_CONFIRMDELETE "Really " LCDW_128_480_LINEBREAK "delete all ?" #define TR_SELECT_WIDGET "Select widget" #define TR_REMOVE_WIDGET "Remove widget" #define TR_WIDGET_SETTINGS "Widget settings" diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index 6ba238856..0355d2980 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -1221,7 +1221,7 @@ #define TR_DISCOVER_SENSORS INDENT "Découvrir capteurs" #define TR_STOP_DISCOVER_SENSORS INDENT "Terminer découverte" #define TR_DELETE_ALL_SENSORS TR(INDENT "Suppr. tous capteurs", INDENT "Supprimer tous capteurs") -#define TR_CONFIRMDELETE TR("Tout effacer?", "Vraiment tout effacer?") +#define TR_CONFIRMDELETE TR("Tout effacer?", "Vraiment tout " LCDW_128_480_LINEBREAK "effacer ?") #define TR_SELECT_WIDGET "Sélect. widget" #define TR_REMOVE_WIDGET "Supprimer widget" #define TR_WIDGET_SETTINGS "Réglages widget" diff --git a/radio/src/translations/it.h.txt b/radio/src/translations/it.h.txt index d7311a827..7c84ab49d 100644 --- a/radio/src/translations/it.h.txt +++ b/radio/src/translations/it.h.txt @@ -1224,7 +1224,7 @@ #define TR_DISCOVER_SENSORS INDENT "Cerca nuovi sensori" #define TR_STOP_DISCOVER_SENSORS INDENT "Ferma ricerca.." #define TR_DELETE_ALL_SENSORS INDENT "Elimina tutti i sensori" -#define TR_CONFIRMDELETE "Confermi eliminazione?" +#define TR_CONFIRMDELETE "Confermi " LCDW_128_480_LINEBREAK "eliminazione ?" #define TR_SELECT_WIDGET "Select widget" #define TR_REMOVE_WIDGET "Remove widget" #define TR_WIDGET_SETTINGS "Widget settings" diff --git a/radio/src/translations/pl.h.txt b/radio/src/translations/pl.h.txt index 37a868b77..b26da31b0 100644 --- a/radio/src/translations/pl.h.txt +++ b/radio/src/translations/pl.h.txt @@ -1225,7 +1225,7 @@ #define TR_DISCOVER_SENSORS INDENT "Znajdź nowe czujniki" #define TR_STOP_DISCOVER_SENSORS INDENT "Szukanie STOP " #define TR_DELETE_ALL_SENSORS INDENT "Usuń czujniki " -#define TR_CONFIRMDELETE "Usunąć wszystkie ?" +#define TR_CONFIRMDELETE "Usunąć wszystkie?" #define TR_SELECT_WIDGET "Select widget" #define TR_REMOVE_WIDGET "Remove widget" #define TR_WIDGET_SETTINGS "Widget settings" diff --git a/radio/src/translations/pt.h.txt b/radio/src/translations/pt.h.txt index 586589a48..87a363d5f 100644 --- a/radio/src/translations/pt.h.txt +++ b/radio/src/translations/pt.h.txt @@ -1191,7 +1191,7 @@ #define TR_DISCOVER_SENSORS INDENT "Discover new sensors" #define TR_STOP_DISCOVER_SENSORS INDENT "Stop discovery" #define TR_DELETE_ALL_SENSORS INDENT "Delete all sensors" -#define TR_CONFIRMDELETE "Really delete all?" +#define TR_CONFIRMDELETE "Really " LCDW_128_480_LINEBREAK "delete all ?" #define TR_SELECT_WIDGET "Select widget" #define TR_REMOVE_WIDGET "Remove widget" #define TR_WIDGET_SETTINGS "Widget settings" From a58a541bb6f25c5131cf505076e2a3717b77711e Mon Sep 17 00:00:00 2001 From: 3djc Date: Sat, 29 Apr 2017 09:10:15 +0200 Subject: [PATCH 179/203] Only display RAS for XJT modules (#4869) --- radio/src/gui/128x64/radio_diaganas.cpp | 8 ++++---- radio/src/gui/212x64/radio_diaganas.cpp | 6 ++++-- radio/src/gui/480x272/view_statistics.cpp | 6 ++++-- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/radio/src/gui/128x64/radio_diaganas.cpp b/radio/src/gui/128x64/radio_diaganas.cpp index da1e83bed..1e686ef87 100644 --- a/radio/src/gui/128x64/radio_diaganas.cpp +++ b/radio/src/gui/128x64/radio_diaganas.cpp @@ -2,7 +2,7 @@ * Copyright (C) OpenTX * * Based on code named - * th9x - http://code.google.com/p/th9x + * th9x - http://code.google.com/p/th9x * er9x - http://code.google.com/p/er9x * gruvin9x - http://code.google.com/p/gruvin9x * @@ -61,12 +61,12 @@ void menuRadioDiagAnalogs(event_t event) lcdDrawText(64+5, MENU_HEADER_HEIGHT+1+3*FH, STR_BG); lcdDrawNumber(64+5+6*FW-3, 1+4*FH, BandGap, RIGHT); #endif - + #if defined(PCBX7) lcdDrawTextAlignedLeft(MENU_HEADER_HEIGHT + 1 + (NUM_STICKS+NUM_POTS+NUM_SLIDERS+1)/2 * FH + 2, STR_BATT_CALIB); putsVolts(LEN_CALIB_FIELDS*FW+FW, MENU_HEADER_HEIGHT + 1 + (NUM_STICKS+NUM_POTS+NUM_SLIDERS+1)/2 * FH + 2, getBatteryVoltage(), (menuVerticalPosition==HEADER_LINE ? INVERS | (s_editMode > 0 ? BLINK : 0) : 0) | PREC2 | LEFT); // SWR - if(IS_MODULE_XJT(EXTERNAL_MODULE)) { + if(IS_MODULE_XJT(EXTERNAL_MODULE) && !IS_INTERNAL_MODULE_ON()) { lcdDrawTextAlignedLeft(MENU_HEADER_HEIGHT + 1 + (NUM_STICKS+NUM_POTS+NUM_SLIDERS+1)/2 * FH + 1 * FH + 2, "RAS"); lcdDrawNumber(LEN_CALIB_FIELDS*FW+FW, MENU_HEADER_HEIGHT + 1 + (NUM_STICKS+NUM_POTS+NUM_SLIDERS+1)/2 * FH + 1 * FH + 2, telemetryData.swr.value, LEFT); } @@ -90,7 +90,7 @@ void menuRadioDiagAnalogs(event_t event) lcdDrawTextAlignedLeft(MENU_HEADER_HEIGHT + 1 + (NUM_STICKS+NUM_POTS+NUM_SLIDERS+1)/2 * FH, STR_BATT_CALIB); putsVolts(LEN_CALIB_FIELDS*FW+4*FW, MENU_HEADER_HEIGHT + 1 + (NUM_STICKS+NUM_POTS+NUM_SLIDERS+1)/2 * FH, g_vbat100mV, (menuVerticalPosition==HEADER_LINE ? INVERS : 0)); #endif - + if (menuVerticalPosition == HEADER_LINE) { CHECK_INCDEC_GENVAR(event, g_eeGeneral.txVoltageCalibration, -127, 127); } diff --git a/radio/src/gui/212x64/radio_diaganas.cpp b/radio/src/gui/212x64/radio_diaganas.cpp index 4ea4a2639..0df5cef4b 100644 --- a/radio/src/gui/212x64/radio_diaganas.cpp +++ b/radio/src/gui/212x64/radio_diaganas.cpp @@ -42,6 +42,8 @@ void menuRadioDiagAnalogs(event_t event) } // SWR - lcdDrawTextAlignedLeft(MENU_HEADER_HEIGHT+6*FH, "RAS"); - lcdDrawNumber(10*FW-1, MENU_HEADER_HEIGHT+6*FH, telemetryData.swr.value, RIGHT); + if((IS_MODULE_XJT(INTERNAL_MODULE) && IS_INTERNAL_MODULE_ON()) || (IS_MODULE_XJT(EXTERNAL_MODULE) && !IS_INTERNAL_MODULE_ON())) { + lcdDrawTextAlignedLeft(MENU_HEADER_HEIGHT+6*FH, "RAS"); + lcdDrawNumber(10*FW-1, MENU_HEADER_HEIGHT+6*FH, telemetryData.swr.value, RIGHT); + } } diff --git a/radio/src/gui/480x272/view_statistics.cpp b/radio/src/gui/480x272/view_statistics.cpp index a63e5eaf1..c7c5a5930 100644 --- a/radio/src/gui/480x272/view_statistics.cpp +++ b/radio/src/gui/480x272/view_statistics.cpp @@ -178,8 +178,10 @@ bool menuStatsAnalogs(event_t event) } // SWR - lcdDrawText(MENUS_MARGIN_LEFT, MENU_CONTENT_TOP+7*FH, "RAS"); - lcdDrawNumber(MENUS_MARGIN_LEFT+100, MENU_CONTENT_TOP+7*FH, telemetryData.swr.value); + if((IS_MODULE_XJT(INTERNAL_MODULE) && IS_INTERNAL_MODULE_ON()) || (IS_MODULE_XJT(EXTERNAL_MODULE) && !IS_INTERNAL_MODULE_ON())) { + lcdDrawText(MENUS_MARGIN_LEFT, MENU_CONTENT_TOP+7*FH, "RAS"); + lcdDrawNumber(MENUS_MARGIN_LEFT+100, MENU_CONTENT_TOP+7*FH, telemetryData.swr.value); + } return true; } From 630dec62f56f2c77d40cd76d918069549e51d585 Mon Sep 17 00:00:00 2001 From: Sebastien Charpentier Date: Sat, 29 Apr 2017 10:34:50 +0200 Subject: [PATCH 180/203] Fixed French translations (#4875) * Updated French .ts file. * Updated French translations. --- companion/src/translations/companion_fr.ts | 1680 ++++++++++---------- 1 file changed, 803 insertions(+), 877 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 66a822e1c..7cf6c233a 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -801,6 +801,14 @@ Peut être différente de la langue du firmware Impossible d'ouvrir %1 (raison: %2) + + CurveData + + + CV%1 + CB%1 + + CurveGroup @@ -1026,42 +1034,42 @@ Peut être différente de la langue du firmware Impossible de trouver le fichier son %1 ! - + &Delete &Supprimer - + Delete Supprimer - + &Copy &Copier - + Ctrl+C - + &Cut &Couper - + Ctrl+X - + &Paste &Coller - + Ctrl+V @@ -1302,78 +1310,78 @@ Pour <b>retirer un filtre de l'historique</b>, sélectionnez-le EepromInterface - + Possible causes for this: Causes possibles: - + - Eeprom is from a newer version of OpenTX - L'EEPROM peut avoir été créée avec une version d'OpenTX plus récente - + - Eeprom is not from OpenTX - L'EEPROM peut avoir été créée avec un firmware autre qu'OpenTX - + - Eeprom is not from Th9X - L'EEPROM n'est pas une EEPROM TX9X - + - Eeprom is not from Gruvin9X - L'EEPROM n'est pas une EEPROM Gruvin9X - + - Eeprom is not from ErSky9X - L'EEPROM n'est pas une EEPROM ErSky9X - + - Eeprom is not from Er9X - L'EEPROM n'est pas une EEPROM ER9X - + - Eeprom size is invalid - La taille de l'EEPROM est invalide - + - Eeprom file system is invalid - Le système de fichier de l'EEPROM est invalide - + - Eeprom is from a unknown board - L'EEPROM ne correspond à aucune carte supportée - + - Eeprom is from the wrong board - L'EEPROM ne correspond pas au type de radio sélectionné - + - Eeprom backup not supported - Sauvegarde d'EEPROM non supportée - + - Something that couldn't be guessed, sorry - Erreur inconnue - + Warning: Avertissement: - - + + - Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used - Le firmware de la radio est probablement incorrect, @@ -1381,14 +1389,14 @@ la taille de l'EEPROM est de 4096 mais seulement 2048 bytes sont utilisés. Vérifier la sélection (M64/M128) - + - Your eeprom is from an old version of OpenTX, upgrading! You should 'save as' to keep the old file as a backup. - Le fichier qui vient d'être ouvert provient d'une ancienne verison d'OpenTX et a été converti. Il est recommandé d'"Enregistrer Sous" au plus vite pour ne pas risquer d'écraser votre ancien fichier. - + Warnings! Avertissements ! @@ -5685,303 +5693,298 @@ Mixage actif par défaut si non-renseigné. %1 octets - - CH%1 - VOIE%1 - - - + Exponential Exponentiel - + Extra Fine Extra fin - + Fine Fin - + Medium Moyen - + Coarse Grossier - + Unknown Inconnu - + Enabled Actif - + Disabled Inactif - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) %1, Voies(%2-%3), Impulsion(%4µs), Polarité(%5) - + %1, Channels(%2-%3) %1, Voies(%2-%3) - + Receiver number(%1) No. de récepteur(%1) - + radio Protocol %1, subType %2, option value %3 radio Protocol %1, sousType %2, option %3 - + Slave/Jack Elève/Jack - + Master/SBUS Module Maître/SBUS module - + Master/CPPM Module Maître/CPPM Module - + Master/SBUS in battery compartment Maître/SBUS compartiment batterie - + Master/Jack Maître/Jack - + 90 - + 120 - + 120X - + 140 - + Rudder Dérive - + Elevator Profondeur - + Throttle Gaz - + Aileron Ailerons - + Name(%1) Nom(%1) - + Persistent Persistant - + MinuteBeep Bip minutes - + CountDown(Beeps) Cpte à rebours(bips) - + CountDown(Voice) Cpte à rebours(voix) - + CountDown(Haptic) Cpte à rebours(vibreur) - - + + Off - - - - + + + + FM%1 PV%1 - + FM%1%2 PV%1%2 - + FM%1+%2 PV%1+%2 - + [I%1] [E%1] - + Input%1 Entrée%1 - + Weight Ratio - + Switch Inter - - + + NoTrim Pas de trim - + Weight(%1) Ratio(%1) - + Switch(%1) Inter(%1) - + No DR/Expo Pas d'expo/DR - - + + Offset(%1) Décalage(%1) - + Delay(u%1:d%2) Délai(h%1:b%2) - + Slow(u%1:d%2) Ralenti(h%1:b%2) - + Warn(%1) Alerte(%1) - + Disabled in all flight modes Désactivé pour toutes les phases de vol - + Flight modes(%1) Phases de vol(%1) - + Flight mode(%1) Phase de vol(%1) - + Edge(%1, [%2:%3]) Flanc(%1, [%2:%3]) - + instant - + Sticky(%1, %2) Bistable(%1, %2) - + Timer(%1, %2) Chrono(%1, %2) - + Duration(%1s) Durée(%1s) - + Delay(%1s) Délai(%1s) - + Custom Prédéfini - + Standard @@ -6384,7 +6387,7 @@ Mixage actif par défaut si non-renseigné. - + GV%1 VG%1 @@ -6405,112 +6408,102 @@ Mixage actif par défaut si non-renseigné. - Name - Nom - - - - + Offset Décalage - + Min - + Max - + Invert Inversé - + Global Variables Variables globales - + Inputs Entrées - + Mixers Mixages - - CV%1 - CB%1 - - - + Curves Courbes - + L%1 - + Logical Switches Inters logiques - + SF%1 FS%1 - + Special Functions Fonctions spéciales - + Telemetry Settings Paramètres de télémesure - + Analogs Analogiques - + Unit Unité - + Scale Echelle - + A%1 - + RSSI Alarms Alarmes RSSI - + Low Alarm Alarme basse - + Critical Alarm Alarme critique @@ -6666,7 +6659,7 @@ Mixage actif par défaut si non-renseigné. Polonais - + CH%1 VOIE%1 @@ -6701,479 +6694,452 @@ Mixage actif par défaut si non-renseigné. Sel.Rot. E - + Trainer Écolage - + Trainer RUD Écolage Direction - + Trainer ELE Écolage Profondeur - + Trainer THR Écolage Gaz - + Trainer AIL Écolage Ailerons - + Instant Trim Trims instantanés - + Play Sound Jouer Son - + Haptic Vibreur - + S3 - + RSSI Tx - + RSSI Rx - + A3 - + A4 - + Cells Velm - + dTE - + Hdg Cap - + AirSpeed Vitesse Air - + A3- - + A4- - + Speed+ Vit+ - + Dist+ - + AirSpeed+ VitA+ - + Cell- Elem- - + Cells- Velm- - + Vfas- - + Curr+ Cour+ - + Powr+ Puis+ - + ACC - + GPS Time Heure GPS - + L1 - + L2 - + [I%1] [E%1] - + LUA%1%2 - - - L%1 - - - - + TR%1 - + FM0 PV0 - + FM1 PV1 - + FM2 PV2 - + FM3 PV3 - + FM4 PV4 - + FM5 PV5 - + FM6 PV6 - + FM7 PV7 - + FM8 PV8 - + Trim 5 Down Trim 5 Bas - + Trim 5 Up Trim 5 Haut - + Trim 6 Down Trim 6 Bas - + Trim 6 Up Trim 6 Haut - + One Un - + a>x - + a<x - + |a|>x - + |a|<x - + AND ET - + OR OU - + XOR OUX - + a=b - + a!=b - + a>b - + a<b - + a>=b - + a<=b - + d>=x - + |d|>=x - + a=x - + a~x - + Timer Chrono - + Sticky Bistable - + Left Horizontal Gauche Horizontal - + Left Vertical Gauche Vertical - + Right Vertical Droit Vertical - + Right Horizontal Droit Horizontal - + Aux. 1 - + Aux. 2 - - + + Unknown Inconnu - + SD Logs Logs SD - + + Adjust %1 + Ajuster %1 + + + played once, not during startup !1x Lu une fois, mais pas à la mise en route - + repeat(%1s) Répéter chaque %1s - + DISABLED DESACTIVE - + INV - + NOR - + Reset Remise à zéro - + Set Timer %1 Définir chrono %1 - + Vario - + Volume - + Play Value Lire valeur - + Backlight Rétroéclairage - + Play Track Jouer fichier - - - + + --- - - - Rud Trim - Trim Dir - - - - Ele Trim - Trim Prf - - - - Thr Trim - Trim Gaz - - - - Ail Trim - Trim Ail - - - - Rot Enc - Mol Enc - English @@ -7235,64 +7201,64 @@ Mixage actif par défaut si non-renseigné. 1x Lu une fois - + Play Both Jouer les 2 - + Override %1 Remplacer %1 - + Play Script Exécuter script - + Screenshot Capture d'écran - + Background Music Musique de fond - + Background Music Pause Pause musique de fond - + Edge Flanc - - - + + + <font color=red><b>Inconsistent parameter</b></font> <font color=red><b>Paramètre inconsistant</b></font> - + Telemetry Télémesure - + Value Valeur - + Decr: Décr: - + Incr: Incr: @@ -7307,47 +7273,37 @@ Mixage actif par défaut si non-renseigné. - + Value Valeur - + Source - + GVAR VG - + Increment Incrément - + Flight Vol - - !Flight mode %1 - !Phase de vol %1 - - - - Flight mode %1 - Phase de vol %1 - - - + Own value Valeur indépendante - + Flight mode %1 value Flight phase %1 value Valeur de la phase de vol %1 @@ -7368,138 +7324,114 @@ Mixage actif par défaut si non-renseigné. Touches + manches - - - -GV%1 - -VG%1 - - - - Adjust GV%1 - Ajuster VG%1 - - - + SetFailsafe Int. Module Déf. failsafe module interne - + SetFailsafe Ext. Module Déf. failsafe module externe - + RangeCheck Int. Module Test portée module interne - + RangeCheck Ext. Module Test portée module externe - + Bind Int. Module Bind module interne - + Bind Ext. Module Bind module externe - + Rotary Encoder Sélecteur Rotatif - - -GV%1 (%2) - -VG%1 (%2) - - - - GV%1 (%2) - VG%1 (%2) - - - + Yellow Jaune - + Orange Orange - + Red Rouge - + Winged Shadow How High - + Winged Shadow How High (not supported) Winged Shadow How High (non supporté) - + FrSky Sensor Hub Sensor Hub FrSky - + None Aucun - + Imperial Impérial - + Metric Métrique - + Uknown error during Simulator startup. Erreur inconnue pendant le démarrage du simulateur. - + Simulator Error Erreur Simulateur - + Data Load Error Erreur de lecture des données - + Error occurred while starting simulator. Une erreur s'est produite lors du démarrage du simulateur. - - - + GV%1 VG%1 - - - - + + + ---- @@ -7509,616 +7441,610 @@ Mixage actif par défaut si non-renseigné. GAZ - - + + Batt - + SWR - - + P1 - - - - - - - + + + + + + + V - - + + s - + ft - - - + + + m - - + + °C - - + + ° - - + + % - - - + + + mph - - - + + + km/h - - + + m/s - - + + A - + °F - - + + mAh - - + + W - - + + g - - + P2 - - + P3 - + MAX - + + + LSw%1 + + + + RudTrim Left TrmD Gauche - + RudTrim Right TrmD Droite - + EleTrim Down TrmP Bas - + EleTrim Up TrmP Haut - + ThrTrim Down TrmG Bas - + ThrTrim Up TrmG Haut - + AilTrim Left TrmA Gauche - + AilTrim Right TrmA Droite - + THs GZs - + TH% GZ% - + THt GZt - - + + ??? - + Diff(%1) - + Expo(%1) - + Function(%1) Fonction(%1) - + Curve(%1) Courbe(%1) - - !Curve(%1) - !Courbe(%1) - - - - + Rud Dir - - + Ele Prf - - + Thr Gaz - - + Ail Ail - + TrmR TrmD - + TrmE TrmP - + TrmT TrmG - + TrmA TrmA - - - + + + S1 - + mA - + kts - + f - + mW mW - + dB - + rpms - + Rad - + hours heures - + minutes - + seconds secondes - + h:m - + m:s - + h:m:s - - - + + + S2 - - - + + + LS - - - + + + RS - + F1 - + F2 - + F3 - + F4 - - - + + + REa - - - + + + REb - + Trm5 - + Trm6 - - - + + + Timer3 Chrono 3 - + Alt Altitude - + Rpm - + Fuel Carburant - + Speed Vitesse - + Dist Distance - + GPS Alt Altitude GPS - + Cell Element LiPo - + Vfas Vfas - + Curr Courant - + Cnsp Consommation - + Powr Puissance - + AccX - + AccY - + AccZ - + VSpd Vitesse Verticale - + A1- - + A2- - + Alt- - + Alt+ - + Rpm+ - + T1+ - + T2+ - - + + Time Temps - + CYC%1 - - + + ON - - + + OFF - - + + Support for frsky telemetry mod Support de la télémétrie FrSky - - + + Support for jeti telemetry mod Support de la télémétrie JETI - - + + Support for receiving ardupilot data Support de la télémétrie ARDUPILOT - - + + Support for receiving NMEA data Support de la télémétrie NMEA - + Support for telemetry easy board Support de la carte TelemetrEZ - - + + Support for MAVLINK devices Support du protocole MAVLINK - + Rotary Encoder use in menus navigation Utiliser le sélecteur rotatif pour la navigation - - - - - - + + + + + + Enable heli menu and cyclic mix support Activer le menu hélico et les mixages CCPM - - - - - - + + + + + + Enable TEMPLATES menu Inclure les gabarits - + 6P - + Enable Lua compiler Active le compilateur Lua - + Support for the DIY-Multiprotocol-TX-Module Support du module Multiprotocol @@ -8143,553 +8069,553 @@ Mixage actif par défaut si non-renseigné. Impossible d'écrire le modèle %1 - + JSx - + JSy - + Enable bindings options Activer les options de Bind (désactiver la télémétrie pour les XSR, etc...) - + KS108 LCD - + WTV20 voice module Module voix WTV20 - + JQ6500 voice module Module voix JQ6500 - + FrSky Taranis X9D+ - + FrSky Taranis X9D - + Horus gimbals installed (Hall sensors) Manches à effet HALL de Horus installés - + FrSky Taranis X7 - + FrSky Horus - + Use ONLY with first DEV pcb version Exclusivement pour les Horus DEV - + Turnigy 9XR-PRO - + Turnigy 9XR with m128 chip Turnigy 9XR avec une puce m128 + + + + + + No splash screen + Pas d'écran de démarrage + + + + + + + + + Disable curves menus + Désactiver le menu des courbes + + + + + + + + Support for radio modified with regular speaker + Haut-parleur au lieu du buzzer d'origine + + + + + + + + Used if you have modified your radio with voice mode + Support du module vocal + - No splash screen - Pas d'écran de démarrage + + Used if you have modified your radio with haptic mode + Support du vibreur + + Channel values displayed in us + Positions de voies affichées en µs + + + + + + + + + + + + Battery graph + Graphique de batterie + + + + + + + + + + + + + + Use alternative SQT5 font + Utiliser la police alternative SQT5 + + + + Possibility to enable FAI MODE (no telemetry) at field + Possibilité d'activer le mode FAI (télémétrie désactivée) sur le terrain + + + + FAI MODE (no telemetry) always enabled + Mode FAI (télémétrie désactivée) toujours actif + + + + Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) + Le port USB connecte les disques virtuels au lieu du Joystick (comme dans le bootloader) + + + + Instead of Joystick emulation, USB connection is Command Line Interface + Le port USB est utilisé pour un port série avec interface par ligne de commande au lieu du Joystick + + + + Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 + Masque le protocole D8. Légalement obligatoire sur les radios Européennes importées après le 1er janvier 2015 + + + + + Support for PPM internal module hack + Support du remplacement du module interne par un module PPM + + + + ST7565P LCD or compatible + ST7565P LCD ou compatible + + + + ST7565R LCD or compatible + ST7565R LCD ou compatible + + + + ERC12864FSF LCD + LCD ERC12864FSF + + + + ST7920 LCD + LCD ST7920 + + + + + + + Enable the throttle trace in Statistics + Activer l'historique du manche des gaz dans les statistiques + + + + EEprom write progress bar + Barre de progression pour l'écriture de l'EEPROM + + + + + No Winged Shadow How High support + Supprimer le support du variomètre Winged Shadow How High + + + + Turnigy 9XR + + + + + + No vario support + Supprimer la fonction variomètre audio + + + + + No GPS support + Supprimer le support du GPS + + + + + No gauges in the custom telemetry screen + Supprimer l'affichage des valeurs de télémesure par barres + + + + 9X with stock board + 9X avec carte mère d'origine + + + + Allow compensating for offset errors in FrSky FAS current sensors + Permettre la compensation d'un décalage des capteurs de courant FASxx FrSky + + + + + Add support for reversing stick inputs (e.g. needed for FrSky gimbals) + Ajoute le support de l'inversion des manches (nécessaire pour l'utilisation de manches FrSky) + + + + DIY MEGA2560 radio + + + + + Power management by soft-off circuitry + Gestion alim. par software + + + + FrSky Taranis X9E + + + + + Confirmation before radio shutdown + Confirmation avant l'arrêt de la radio + + + + Haptic module installed + Module vibreur installé + + + + Support for Lua model scripts + Support des scripts Lua + + + + + Support of FrSky PXX protocol + Support du protocole PXX FrSky + + + + Disable HELI menu and cyclic mix support + Supprimer le menu HELICO et les mixages cycliques + + + + Disable Global variables + Supprimer le support des variables globales + + + - - - Disable curves menus - Désactiver le menu des courbes + Support for DSM2 modules + Support du protocole DSM2 - - Support for radio modified with regular speaker - Haut-parleur au lieu du buzzer d'origine - - - - - - - - Used if you have modified your radio with voice mode - Support du module vocal + + + PPM center adjustment in limits + Neutres PPM ajustables - - Used if you have modified your radio with haptic mode - Support du vibreur - - - - Channel values displayed in us - Positions de voies affichées en µs - - - - - - - - - - - - Battery graph - Graphique de batterie - - - - - - - - - - - - - - Use alternative SQT5 font - Utiliser la police alternative SQT5 - - - - Possibility to enable FAI MODE (no telemetry) at field - Possibilité d'activer le mode FAI (télémétrie désactivée) sur le terrain - - - - FAI MODE (no telemetry) always enabled - Mode FAI (télémétrie désactivée) toujours actif - - - - Instead of Joystick emulation, USB connection is Mass Storage (as in the Bootloader) - Le port USB connecte les disques virtuels au lieu du Joystick (comme dans le bootloader) - - - - Instead of Joystick emulation, USB connection is Command Line Interface - Le port USB est utilisé pour un port série avec interface par ligne de commande au lieu du Joystick - - - - Removes D8 FrSky protocol support which is not legal for use in the EU on radios sold after Jan 1st, 2015 - Masque le protocole D8. Légalement obligatoire sur les radios Européennes importées après le 1er janvier 2015 - - - - - Support for PPM internal module hack - Support du remplacement du module interne par un module PPM - - - - ST7565P LCD or compatible - ST7565P LCD ou compatible - - - - ST7565R LCD or compatible - ST7565R LCD ou compatible - - - - ERC12864FSF LCD - LCD ERC12864FSF - - - - ST7920 LCD - LCD ST7920 - - - - - - - Enable the throttle trace in Statistics - Activer l'historique du manche des gaz dans les statistiques - - - - EEprom write progress bar - Barre de progression pour l'écriture de l'EEPROM - - - - - No Winged Shadow How High support - Supprimer le support du variomètre Winged Shadow How High - - - - Turnigy 9XR - - - - - - No vario support - Supprimer la fonction variomètre audio - - - - - No GPS support - Supprimer le support du GPS - - - - - No gauges in the custom telemetry screen - Supprimer l'affichage des valeurs de télémesure par barres - - - - 9X with stock board - 9X avec carte mère d'origine - - - - Allow compensating for offset errors in FrSky FAS current sensors - Permettre la compensation d'un décalage des capteurs de courant FASxx FrSky - - - - - Add support for reversing stick inputs (e.g. needed for FrSky gimbals) - Ajoute le support de l'inversion des manches (nécessaire pour l'utilisation de manches FrSky) - - - - DIY MEGA2560 radio - - - - - Power management by soft-off circuitry - Gestion alim. par software - - - - FrSky Taranis X9E - - - - - Confirmation before radio shutdown - Confirmation avant l'arrêt de la radio - - - - Haptic module installed - Module vibreur installé - - - - Support for Lua model scripts - Support des scripts Lua - - - - - Support of FrSky PXX protocol - Support du protocole PXX FrSky - - - - Disable HELI menu and cyclic mix support - Supprimer le menu HELICO et les mixages cycliques - - - - Disable Global variables - Supprimer le support des variables globales - - - - - - - - Support for DSM2 modules - Support du protocole DSM2 - - - - - - - - - PPM center adjustment in limits - Neutres PPM ajustables - - - - - - - - + + Symetrical Limits Limites symétriques - - - - - - - + + + + + + + Pots use in menus navigation Support de la navigation dans les menus avec les POTS - + No OverrideCH functions available Désactive la fonction spéciale "Remplacer VOIEx" - - - - - - - - - + + + + + + + + + No flight modes Pas de phases de vol - - + + SmartieParts 2.2 Backlight support Support du rétroéclairage pour la carte SmartieParts 2.2 - - - - - - + + + + + + Enable resetting values by pressing up and down at the same time Permet la remise à zéro des valeurs en pressant haut-bas en même temps, valeur min avec gauche/bas, valeur max avec haut/droite, inversion avec gauche/droite - - - - - - - - - + + + + + + + + + No graphical check boxes and sliders Pas de cases à cocher et de curseurs graphiques - - - - - - - - - - Don't use bold font for highlighting active items - Ne pas mettre les lignes actives en gras - - - - - - - - EEprom write Progress bar - Barre de progression affichée lors des écritures EEPROM - - - - - - - - - Imperial units - Unités Impériales - - - - - - Bluetooth interface - Interface Bluetooth - - - - - - - - - - - - Global variables - Variables globales - - - - - + + + + Don't use bold font for highlighting active items + Ne pas mettre les lignes actives en gras + + + + + + + + EEprom write Progress bar + Barre de progression affichée lors des écritures EEPROM + + + + + + + + + Imperial units + Unités Impériales + + + + + + Bluetooth interface + Interface Bluetooth + + + + + + + + + + + + Global variables + Variables globales + + + + + + + + + + + In model setup menus automatically set source by moving the control Sélectionner les sources des mixeurs en bougeant le contrôle désiré - - - - - - - - - + + + + + + + + + In model setup menus automatically set switch by moving the control Sélectionner les interrupteurs en bougeant le contrôle désiré - + 9X with stock board and m128 chip Carte 9x avec un chip m128 - + 9X with AR9X board 9X avec carte AR9X - + 9X with Sky9x board 9X avec carte Sky9x - + 9X with Gruvin9x board 9X avec carte Gruvin9x - - + + Support for SD memory card Support de la carte SD - + Support for DSM2 modules using ppm instead of true serial Support pour les modules DSM2 par le signal PPM - - - + + + Enable HELI menu and cyclic mix support Activer le menu hélico et les mixages CCPM - - - + + + Timer1 Chrono 1 - - - + + + Timer2 Chrono 2 - + A1 - + A2 - + T1 - + T2 - + Warning Avertissement - + Simulator for this firmware is not yet available Le simulateur n'est pas encore disponible pour ce firmware @@ -8889,12 +8815,12 @@ L'équipe OpenTX. Impossible de trouver la carte SD Horus ! - + Positive - + Negative Négative @@ -8915,7 +8841,7 @@ L'équipe OpenTX. - + Models Translators do NOT use accent for this, this is the default category name on Horus. Modeles From 4df32f82470525542f863a2e2245a8729ffe79ca Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sat, 29 Apr 2017 07:29:53 -0400 Subject: [PATCH 181/203] [Companion] Prevent crash when importing (converting) more models than current radio can handle. --- companion/src/firmwares/opentx/opentxinterface.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/companion/src/firmwares/opentx/opentxinterface.cpp b/companion/src/firmwares/opentx/opentxinterface.cpp index c5e6bebf3..67fff2d16 100644 --- a/companion/src/firmwares/opentx/opentxinterface.cpp +++ b/companion/src/firmwares/opentx/opentxinterface.cpp @@ -250,7 +250,7 @@ unsigned long OpenTxEepromInterface::load(RadioData &radioData, const uint8_t * radioData.models.resize(firmware->getCapability(Models)); } for (int i = 0; i < firmware->getCapability(Models); i++) { - if (!loadModelFromRLE(radioData.models[i], efile, i, version, radioData.generalSettings.variant)) { + if (i < (int)radioData.models.size() && !loadModelFromRLE(radioData.models[i], efile, i, version, radioData.generalSettings.variant)) { std::cout << " ko\n"; errors.set(UNKNOWN_ERROR); if (getCurrentFirmware()->getCapability(Models) == 0) { From 975023bdc735ef6663b1489f2e55a6d8f1d91d3d Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Sat, 29 Apr 2017 16:02:37 +0200 Subject: [PATCH 182/203] Update DONATIONS.txt --- DONATIONS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index f53a7267d..e8ec78374 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1181,3 +1181,4 @@ Casey Layton Robert Bates Udo Nowakowski William Hallman +Paul Stein From c1e72353756825e97f0ecbf459c58fb61827745a Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Sat, 29 Apr 2017 19:26:49 +0200 Subject: [PATCH 183/203] Launchpad changelogs for 2.2.0 RC18 --- launchpad/trusty/changelog | 6 ++++++ launchpad/xenial/changelog | 6 ++++++ launchpad/yakkety/changelog | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/launchpad/trusty/changelog b/launchpad/trusty/changelog index 8ca4b10d5..3f94ad41f 100644 --- a/launchpad/trusty/changelog +++ b/launchpad/trusty/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N371~trusty) trusty; urgency=low + + * New release 2.2.0~N371 RC18 + + -- projectkk2glider Sat, 29 Apr 2017 18:57:42 +0200 + opentx-companion22 (2.2.0~N370~trusty) trusty; urgency=low * New release 2.2.0~N370 RC17 diff --git a/launchpad/xenial/changelog b/launchpad/xenial/changelog index adb6390aa..239c0145f 100644 --- a/launchpad/xenial/changelog +++ b/launchpad/xenial/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N371~xenial) xenial; urgency=low + + * New release 2.2.0~N371 RC18 + + -- projectkk2glider Sat, 29 Apr 2017 18:57:37 +0200 + opentx-companion22 (2.2.0~N370~xenial) xenial; urgency=low * New release 2.2.0~N370 RC17 diff --git a/launchpad/yakkety/changelog b/launchpad/yakkety/changelog index de1ac2f56..014f68918 100644 --- a/launchpad/yakkety/changelog +++ b/launchpad/yakkety/changelog @@ -1,3 +1,9 @@ +opentx-companion22 (2.2.0~N371~yakkety) yakkety; urgency=low + + * New release 2.2.0~N371 RC18 + + -- projectkk2glider Sat, 29 Apr 2017 18:57:47 +0200 + opentx-companion22 (2.2.0~N370~yakkety) yakkety; urgency=low * New release 2.2.0~N370 RC17 From 582546f8edbe27bf50812eb3136cb6495c848244 Mon Sep 17 00:00:00 2001 From: Damjan Adamic Date: Sat, 29 Apr 2017 22:18:11 +0200 Subject: [PATCH 184/203] Fixes #4839: path buffer overflow if LUA widget or theme directory name was too long (max length of directory name is 13 characters) (#4876) --- radio/src/lua/widgets.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/radio/src/lua/widgets.cpp b/radio/src/lua/widgets.cpp index fcedeaefd..3df0faf4d 100644 --- a/radio/src/lua/widgets.cpp +++ b/radio/src/lua/widgets.cpp @@ -31,6 +31,7 @@ lua_State *lsWidgets = NULL; extern int custom_lua_atpanic(lua_State *L); +#define LUA_WIDGET_FILENAME "/main.lua" #define LUA_FULLPATH_MAXLEN (LEN_FILE_PATH_MAX + LEN_SCRIPT_FILENAME + LEN_FILE_EXTENSION_MAX) // max length (example: /SCRIPTS/THEMES/mytheme.lua) void exec(int function, int nresults=0) @@ -496,9 +497,10 @@ void luaLoadFiles(const char * directory, void (*callback)()) res = f_readdir(&dir, &fno); /* Read a directory item */ if (res != FR_OK || fno.fname[0] == 0) break; /* Break on error or end of dir */ uint8_t len = strlen(fno.fname); - if (len > 0 && fno.fname[0]!='.' && (fno.fattrib & AM_DIR)) { + if (len > 0 && (unsigned int)(len + pathlen + sizeof(LUA_WIDGET_FILENAME)) <= sizeof(path) && + fno.fname[0]!='.' && (fno.fattrib & AM_DIR)) { strcpy(&path[pathlen], fno.fname); - strcat(&path[pathlen], "/main.lua"); + strcat(&path[pathlen], LUA_WIDGET_FILENAME); if (isFileAvailable(path)) { luaLoadFile(path, callback); } From 6abd36d62804e160f740a795fcf1764b37da4525 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sat, 29 Apr 2017 20:48:22 -0400 Subject: [PATCH 185/203] [Simulator] Revert logic switch names in Radio Outputs view to numbers-only (since @72b1ad0, closes #4877). --- companion/src/simulation/radiooutputswidget.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/companion/src/simulation/radiooutputswidget.cpp b/companion/src/simulation/radiooutputswidget.cpp index 775a517e6..d51eba7fc 100644 --- a/companion/src/simulation/radiooutputswidget.cpp +++ b/companion/src/simulation/radiooutputswidget.cpp @@ -267,7 +267,7 @@ QWidget * RadioOutputsWidget::createLogicalSwitch(QWidget * parent, int switchNo swtch->setMinimumWidth(swtch->fontMetrics().width("99") + 10); font.setBold(false); swtch->setFont(font); - swtch->setText(QString("%1").arg(RawSwitch(SWITCH_TYPE_VIRTUAL, switchNo+1).toString().remove("L"), 2, QLatin1Char('0'))); + swtch->setText(QString("%1").arg(switchNo+1, 2, 10, QChar('0'))); swtch->setAlignment(Qt::AlignCenter); m_logicSwitchMap.insert(switchNo, swtch); return swtch; From e053abfc3e3375a2b691dbee11da98720a46ffed Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Sun, 30 Apr 2017 08:57:36 +0200 Subject: [PATCH 186/203] Max added to the CREDITS.txt --- CREDITS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/CREDITS.txt b/CREDITS.txt index 202b88a8a..290582d75 100644 --- a/CREDITS.txt +++ b/CREDITS.txt @@ -5,6 +5,7 @@ Damjan Adamic (projectkk2glider) Franck Aguerre (jivarofad) Romolo Manfredini (romoloman) Martin Hotař (mhotar) +Maxim (Max) Paperno (mpaperno) Rob Thomson Bryan J. Rentoul (gruvin) From 054c87c91e49120431edf02173e63e6dec214fbd Mon Sep 17 00:00:00 2001 From: 3djc Date: Sun, 30 Apr 2017 12:53:25 +0200 Subject: [PATCH 187/203] Fix adjust GVAR and Volume (#4880) --- radio/src/gui/128x64/model_special_functions.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/radio/src/gui/128x64/model_special_functions.cpp b/radio/src/gui/128x64/model_special_functions.cpp index ca72bca25..1111f3b67 100644 --- a/radio/src/gui/128x64/model_special_functions.cpp +++ b/radio/src/gui/128x64/model_special_functions.cpp @@ -366,8 +366,10 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF else if (func == FUNC_VOLUME) { val_max = MIXSRC_LAST_CH; drawSource(MODEL_SPECIAL_FUNC_3RD_COLUMN, y, val_displayed, attr); - INCDEC_SET_FLAG(eeFlags | INCDEC_SOURCE); - INCDEC_ENABLE_CHECK(isSourceAvailable); + if (active) { + INCDEC_SET_FLAG(eeFlags | INCDEC_SOURCE); + INCDEC_ENABLE_CHECK(isSourceAvailable); + } } #elif defined(VOICE) else if (func == FUNC_PLAY_TRACK) { @@ -421,8 +423,10 @@ void menuSpecialFunctions(event_t event, CustomFunctionData * functions, CustomF case FUNC_ADJUST_GVAR_SOURCE: val_max = MIXSRC_LAST_CH; drawSource(MODEL_SPECIAL_FUNC_3RD_COLUMN, y, val_displayed, attr); - INCDEC_SET_FLAG(eeFlags | INCDEC_SOURCE); - INCDEC_ENABLE_CHECK(isSourceAvailable); + if (active) { + INCDEC_SET_FLAG(eeFlags | INCDEC_SOURCE); + INCDEC_ENABLE_CHECK(isSourceAvailable); + } break; case FUNC_ADJUST_GVAR_GVAR: val_max = MAX_GVARS-1; From 0b25332171cebeca691b8d7157680c4a2d36b3c6 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Sun, 30 Apr 2017 12:58:49 +0200 Subject: [PATCH 188/203] Add @schwabe to CREDITS.txt --- CREDITS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/CREDITS.txt b/CREDITS.txt index 290582d75..88286dd5e 100644 --- a/CREDITS.txt +++ b/CREDITS.txt @@ -6,6 +6,7 @@ Franck Aguerre (jivarofad) Romolo Manfredini (romoloman) Martin Hotař (mhotar) Maxim (Max) Paperno (mpaperno) +Arne Schwabe (schwabe) Rob Thomson Bryan J. Rentoul (gruvin) From 4f5f241669eadfa34d1d446ff651c3d9b6b084bd Mon Sep 17 00:00:00 2001 From: 3djc Date: Sun, 30 Apr 2017 23:19:43 +0200 Subject: [PATCH 189/203] Fix opentx-9x-autoswitch-autosource-dblkeys-battgraph-telemetrez-sp22-stickrev-pgbar-en.hex (#4883) --- radio/src/targets/common/avr/CMakeLists.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/radio/src/targets/common/avr/CMakeLists.txt b/radio/src/targets/common/avr/CMakeLists.txt index a3953b35c..d94bac83f 100644 --- a/radio/src/targets/common/avr/CMakeLists.txt +++ b/radio/src/targets/common/avr/CMakeLists.txt @@ -93,7 +93,7 @@ elseif(TELEMETRY STREQUAL MAVLINK) WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}) if(NOT ${GIT_SUBMODULE_RESULT} EQUAL 0) message(FATAL_ERROR "Error: Cannot clone submodule at ${THIRDPARTY_DIR}/GCS_MAVLink/include_v1.0 -If you downloaded this project as a ZIP file, please instead run +If you downloaded this project as a ZIP file, please instead run 'git clone --recursive https://github.com/opentx/opentx.git'") endif() endif() @@ -106,7 +106,6 @@ If you downloaded this project as a ZIP file, please instead run math(EXPR EEPROM_VARIANT ${EEPROM_VARIANT}+${MAVLINK_VARIANT}) elseif(TELEMETRY STREQUAL TELEMETREZ) add_definitions(-DTELEMETRY_TELEMETREZ) - set(SRC ${SRC} telemetry/jeti.cpp) elseif(TELEMETRY STREQUAL FRSKY_SPORT) add_definitions(-DTELEMETRY_FRSKY_SPORT) set(SRC ${SRC} crc16.cpp telemetry/frsky_sport.cpp) From f525b1762bdee813e008a7dcaa2f4542760ebe43 Mon Sep 17 00:00:00 2001 From: Arne Schwabe Date: Mon, 1 May 2017 00:33:45 +0200 Subject: [PATCH 190/203] Fix #4881 (#4884) Thanks Mike for noticing: In pxx_arm.cpp, the pulse duration is set to either 48 or 32. This value gets put into the ARR register of the timer (via DMA). Counters count from 0 to the ARR value, then go back to 0. This will result in either 49 or 33 counts for the pulse width, thus making the pulses 0.5uS too long. Tested only with external PXX --- radio/src/pulses/pxx_arm.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/pulses/pxx_arm.cpp b/radio/src/pulses/pxx_arm.cpp index cbb4f4585..b0f15155e 100644 --- a/radio/src/pulses/pxx_arm.cpp +++ b/radio/src/pulses/pxx_arm.cpp @@ -134,7 +134,7 @@ void pxxPutPcmTail(uint8_t port) #else void pxxPutPcmPart(uint8_t port, uint8_t value) { - pulse_duration_t duration = value ? 48 : 32; + pulse_duration_t duration = value ? 47 : 31; *modulePulsesData[port].pxx.ptr++ = duration; modulePulsesData[port].pxx.rest -= duration + 1; } From 6edc3b61ff432b7f20036ffd2ba83b53c648b86e Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Mon, 1 May 2017 08:29:22 +0200 Subject: [PATCH 191/203] Update DONATIONS.txt --- DONATIONS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index e8ec78374..1a019782d 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1182,3 +1182,4 @@ Robert Bates Udo Nowakowski William Hallman Paul Stein +Nurflügel & Modelltechnik From 4b2b5a9d372f758145d7a02db4470c94b6b857b9 Mon Sep 17 00:00:00 2001 From: Sebastien Charpentier Date: Mon, 1 May 2017 17:44:08 +0200 Subject: [PATCH 192/203] Logical switch `L%` or `LSw%` are now translated in `IL%` (Interrupteur Logique). (#4886) --- companion/src/translations/companion_fr.ts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 7cf6c233a..977953422 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -3804,7 +3804,7 @@ Extra long : bips extra longs. L%1 - + IL%1 @@ -6450,7 +6450,7 @@ Mixage actif par défaut si non-renseigné. L%1 - + IL%1 @@ -7571,7 +7571,7 @@ Mixage actif par défaut si non-renseigné. LSw%1 - + IL%1 From d3b8133ee2483c9d4bdf31d5dc796446c1f45dfc Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Tue, 2 May 2017 07:33:10 +0200 Subject: [PATCH 193/203] Add LapinFou to CREDITS.txt --- CREDITS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/CREDITS.txt b/CREDITS.txt index 88286dd5e..d9ab95fbe 100644 --- a/CREDITS.txt +++ b/CREDITS.txt @@ -19,3 +19,4 @@ Karl Szmutny Michal Hlavinka Pat Mackenzie Michael Byrne +Sebastien Charpentier (LapinFou) From 2bec60517ab1a2bf8f06cd5772f3e5773371cbc5 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Fri, 5 May 2017 07:28:32 +0200 Subject: [PATCH 194/203] Update DONATIONS.txt --- DONATIONS.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index 1a019782d..f33df3563 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1183,3 +1183,5 @@ Udo Nowakowski William Hallman Paul Stein Nurflügel & Modelltechnik +Gary Wild +James A Davey From 38d8f6a326aa4507fe169bd8f3d9fe60865a0f86 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Sat, 6 May 2017 00:13:12 +0200 Subject: [PATCH 195/203] Update DONATIONS.txt --- DONATIONS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index f33df3563..de1c76bf5 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -1185,3 +1185,4 @@ Paul Stein Nurflügel & Modelltechnik Gary Wild James A Davey +Marco Giuseppe Colturi From 3f06037e1b178701de1fe651648acb0e6ec93699 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Sat, 6 May 2017 17:55:03 +0200 Subject: [PATCH 196/203] [Companion] Credits dialog refactoring --- CREDITS.txt | 1198 ++++++++++++++++- DONATIONS.txt | 1188 ---------------- companion/src/CMakeLists.txt | 4 +- companion/src/companion.qrc | 1 - ...ntributorsdialog.cpp => creditsdialog.cpp} | 85 +- .../{contributorsdialog.h => creditsdialog.h} | 31 +- companion/src/mainwindow.cpp | 4 +- 7 files changed, 1268 insertions(+), 1243 deletions(-) delete mode 100644 DONATIONS.txt rename companion/src/{contributorsdialog.cpp => creditsdialog.cpp} (70%) rename companion/src/{contributorsdialog.h => creditsdialog.h} (62%) diff --git a/CREDITS.txt b/CREDITS.txt index d9ab95fbe..0335dc652 100644 --- a/CREDITS.txt +++ b/CREDITS.txt @@ -1,3 +1,4 @@ +[Main developers] Bertrand Songis (bsongis) André Bernet (kilrah) Michael Blandford @@ -8,6 +9,10 @@ Martin Hotař (mhotar) Maxim (Max) Paperno (mpaperno) Arne Schwabe (schwabe) +[Translators] +[fr] Sebastien Charpentier (LapinFou) + +[Other contributors] Rob Thomson Bryan J. Rentoul (gruvin) Cameron Weeks (th9xer) @@ -19,4 +24,1195 @@ Karl Szmutny Michal Hlavinka Pat Mackenzie Michael Byrne -Sebastien Charpentier (LapinFou) + +[Companies and projects who have donated to OpenTX] +FrSky (monthly) +Aloft Hobbies +Jonathan Modellismo +WsTech +Aviomotive +BoltRC +Aerial Tech Hobbies +LitePilots +David Ankers (OpenPilot) +3D Robotics +RC Studio (monthly) +Craft & Theory (monthly) +OpenTX Manuals by Lothar Thole + +[People who have donated to OpenTX] +Mario Sette +Felice Baratto +Alessandro Mari +Gianpiero Spontina +Ingo Kuzniak +Hans-Åke Rahm +Tamas Varga +Thomas Gregg +Didier Christien +Alain Pinard +Sergio Melas +Paul Montenot +Chris Guy +Adrien Gravouille +Thomas Black +Marc Lucht +Zdenek Trojanek +Martin Hotar +Stefan Grundevik +Fabio Eboli +Federico Zotti +Albin Esbjörnsson +Kilian Hüttenhofer +Stephen Stough +Adilson Oliveira +Robert Saint Marie +Tad Leake +Andreas Weitl +Chan Lofland +Dirk Kasten +Denisov Alexander +Timo Varppee +Ondrej Hatapka +Valérie Billon +R. Scott Page +Johan Cronje +Renato Aranghelovici +Jeffrey Irvin +Kenneth Crump +Damjan Adamic +Martin Wilson +John Holdsworth +Daniel Schwartz +Dean Church (monthly) +Michael Halse +David Mark +Ted Moss +Jim Wagner +Nicola Porzi +Michael Halse +Chewytm +Espen Solbu +Mike Frizell +Bruce Jones +Stefano Airaghi +Dan Eeckhout +Alex Calderhead +Leonard MacKey +Heung Jin Choi +Mike Retterer +Keith Wood +Viljo Liukku +Eric Beier +Burt Pickard-Richardson +Helmut Renz +Rick Harms +Vincenzo Vavala +Patricia Martin +Harald Klein +Carl Petersen +Douglas Burkett +Clifford Evans +Teodor Yantchev +Jarad Berkman +Christian Schulz +Gregory J Shepherd +Michael Shellim +Ming Wang +Bernard Lukaschek +Nigel Chippindale +Mike Perkins +Ted Hammond +David Beanland +Bernd Koehler +Frédéric Duflos +Dave Fasken +Heinrich Illig +Michael Collins +Michael Manning +Craig Lorentz +André Lasseret +Felipe Alexandre de Oliveira +Brian Harris +Philippe Herbots +Rainer Nelte +Franck Bernhard +Erhard Werner +Stig Jøran Moen +Keith Hertzog +Christophe Dauvergne +Tauno Rautakorpi +Sven Assmus +Paul Dittman +Mike Matheny +Cheryl Wynne +Emay Toha +Don Nolder +André Lasseret +Filip Lowette +Arnaldo Gabella +Fiorenzo Agnelli +Michele Villa +Christophe Rodriguez +Larisa Filocamo +Hartmut Sahm +Åke Brodin +Ted Moss +Filippos Tigarakis +Chewytm +Eric Burdis +Nigel Chippindale +Michael Deasy +Stephen Stough +Kenneth Lilja (monthly) +Robert Jero +Gary Bancroft +Robert Cotsford +NorthSide +George Constandinides +Robert Schonk Jr +Kevin Berkefeld +Peter Webster +Mike Matheny +Martin Sniedze +Fernando Rimoldi +Sidney Fisher +John Rodgers +Ed Pare +Thomas Kilduff +Robert Ferguson +Bryan Green +Kevin Berkefeld +Julien Michel +Krittikun Chiraphanda +Douglas Law +Alberto Scotti +Oliver Kunkel +D. Joseph Frazier +Heiko Polig +Andrew Fernie +Marco Lange +Nick McMillan +Michel Baily (monthly) +Patrick Mullen +Scott Campbell +Erich Roeder +Wayne Davy +Michael Fontenot +Willie Swanepoel +Satoru Sasaki +Tyler Darby +Nicholas Crego +Johan Moelich +Timo Esser +Brian Paddock +Jean Pierre Parisy +Norbert Martsch +Jean-Marie Guitard +Tilman Baumann +Fred Larssen +Ari Aalto +Robert Sams +Kirk Robertson +John Koontz +Jeffery Golias +Paul Robinson +Dave Matison +Mike Matheny +Pino Agostino +Graham Boucher +Nelson Noura +Joel Allamy +Philip David Martin +Sean Stephen +Bruce Mackay +Blake Spilman +Timothy Pelletier +Glen Roe (ShowMaster) +Jan Van Ooteghem +Lawrence Christensen +Leo Duflou +Bruce Wood +Arnd Feige +Tauno Rautakorpi +Steve Coley +Stefan Kiendl +Gregory Nuspel +Mitchell Brenner +Ronnnie DePrez +Ferenc Koller +Robert Sessler +Didier Lanot +Rodney Hunt +Steve Bernard +Paul Nazaroff +Gordon Ernenputsch +Ksamak +Marc Gittelman +David Poole +Ralph Sauer +Karl-Heinz Gansel +Michels Bernhard +Thomas Demmelbauer +Felice Baratto +Michael Halse +Horst Kampen +Ian Gough +Matthew Brett +Lexington S Morley +Clemens Drews +Axel Stöckle +Roberto Orsello +Richard Ruck +Hugh Caldwell +Christian Marauli +Albin Esbjörnsson +Per Esbjörnsson +Bernd Hohmann +Sławomir Juszczak +Stephen Henderson +David Morgan +Aloft Hobbies +Netanel Hobara +Cameron Galipo +Doug Schafer +Pietro Rossin +Earl Killingsworth +Victor B Wright +Terry McKinley +Марков Алексей +Offer Shmuely +Ian Lobley +Stéphane Fortas +Peter Mitrik +Thomas Majewski +ANF King +Henrik Hammarström +Kenneth Lilja +R Wells +Uwe Jordt +Harald Wilczak +Bernhard Lohmann +Ferenc Koller +Robert Ferguson +Daniel Byers +Tyler Darby +Miguel Villalpando +Kim Dong Hoon +Terry McKinley +Walter Bell +Clinton Linck +Josep Clodas Sola +Thierry Martin +Peter Mauro +Mitchell Brenner +Yak +Lluis Bullich Rañe +Steffen Rohr +Eric Jacquin +Harvest Lane +Ville Kuvaja +DK-System +Heinz Vogel +Heung Jin Choi +MMJS van der Helm +Dan Neelands +Yashiro Masayuki +Isaac Sloan +Harold Baird +Roy Bender +Bradley Murchie +Maximilian Süß +Dean Jansa +Ronald Donker +Paul Oldenkamp +Dietmar Drees +Bradley Murchie +Richard Fahie +James Kaufman +Henry Deucker +Christian Fuchs +Arold Reinders +Robert Miller +Mark Gaskievicz +Roland Müller +Frank Gewalt +Remi Viard +Reginald H Millsom +Pierluigi Sommaruga +A Harris +Stefan Grunenberg +Francisco Gutierrez Muñoz +Steve Coley +Sean Cull +Roberto Orsello +David Finger +Jean-Marie Oddo +Mike Matheny +Glen Roe (Showmaster) +Arron Bates +Tim Spurr +Daniel Morgan +Trent Ready +Mark Maskiell +Robert Crockford +Mark Illum +David McGuire +Martyn Coles +Jose Sobral +Heung Jin Choi +Tomasz Janiak +Fabien Gagné +Micha Ronen +Albert Blondin +Klaus Schuebel +Evening Shade Pottery +Thomas Kilduff +Sven Assmus +Markus Eberl +Nicholas Field +Harald Wilczak +John Grepps +Anthony Burbidge +Sherba Baine +Gordon Evans +Fred Figge +Uwe Kuehn +David Beatty +Aaron Stringer +Alan J Wasserman +Wolfgang Rauser +Samuel Cook +Friedrich Ipolt +Barrington Cole +Charles Lakins +Thos. O'Meara Photography +Adam Chevalier +Mike Mulligan +Serge Michaux +Robert Young +Wilco Hijink +Roy Nixon +Lexington S Morley +Daryl Dacko +Beat Zurflueh +Piotr Kundu +Kevin Berkefeld +Tomasz Klys +Mirco Didone' +Christoph Schroeter +Zdenek Trojanek +Bryan Anderson +Kamco Enterprises +Robert Bates +Robert Brown +Dennis Marinus +Ronald Van Putte +Thomas Kvitle Jenssen +Patrick Tuxbury +Istvan Magi +Sasaki Satoru +David Laburthe +Vit Jelinek +Pablo Gomez Martinez +Alan Thoren +Jack Clodfelter +William Simon +James Houck +Peter Fithern +Thomas Svedman +TechFixPros +Rafael Eric Suarez Nordlow +Colin Rycroft +Emanuel Stassar +Michael Gregory +Robert Russell +Felix Kaiser +Joshua Bardwell +Davd Goodall +Leonard MacKey +Miles Kelly +Sergio Robledo +Mikael Wallbäck +Daniel Malcman +Paul Dittman +Attilio Rausse +Sidney Gates +Andrea Montefusco +Paul Luby +Donald L Webster +Kenneth Frehafer +Matthias Hase +Markus Wolf +Andrew Fazio +Stefan Künst +Stephen Adams +Tauno Rautakorpi +Frank Houvenaghel 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Associates +Johannes Wollenweber +Fred Page +Jean Trouche +Patrick Blanc +Jean-Louis Tonnellier +Masoud +Mustafa Güven +William Waters +Joël Allamy +William Mckinstry +Jean-Jacques Pointel +Frédéric Rouyre +Jonathan Pruett +Jörg Zieren +Christopher Rhodes +Marco Strack +Stefano Boggia +Dwayne Myers +Stavros Papathanasiou +Roland Nittby +Courtney Puskas +NorthSide +Martin Polák +Ulf Reinhardt +Wolfgang Renisch +Trevor Hinze +Mohammad Zargari +Dr. Willutzki +Jean Pierre Bernard +Patrick Castellan +Udo Tödter +Marc J Merlin +Paul Chitonu +Wolfgang Rauser +Emmanuel Dallery +James Lyons +Tauno Rautakorpi +Gerald Peklar +Fabien Gagné +David Cox +Philip Cork +Kevin Wright +John Scott +Yves Berger +Otto Fröhlich +Kenneth Lilja +Benjamin Johnson +Brad Kelley +Michel Biancki +Lynn Laycock +Claude Godefroy +Gérald Joubert +Wayne J Podaima +Philippe Peyron +Julien Kieffer +Gregor Walter +Carlos Viegas +Roberto Orsello +Steve Murray (monthly) +Marcel Schäfer +Sean Cull +Holger Bothmer +Michael Manning +Martin Risik +ZEN Computer Services +Egbert Stohlmann +Martin Peryea +Nathan James +Luis Suarez +Artur Uzieblo +InTheTubeDeep +Jaap Greve +Peter Glassey +David Reynolds +David Frazier +Donald L Singer +George Carnie +Susan Holbert +Richard Garrett +Paco Galván +Matthew Sylvester +Robert Bates +Hans-Peter Endres +Axel Stöckle +Leonard MacKey +Andrew Fernie +Mark McCoy +Damir Pooshs +Jeff Dillingham +Brent Hampton +Arkadiusz Milewski +Garry Ogilvie +Donald Porter +William Simon +Thomas Sandner +Pascal Pochard +Helmut Renz +T S Pung +Jorge Trinidad +Yeo Jonathan +David Olivier +Thierry Martin +Udo Nowakowski +Philippe Stofleth +Alain Labonne +Atam Gangaram Panday +Sajjad Rahman +Giovanni Carnesecchi +Lorenzo Frassy +Reinaldo Perez +Christian Aussillou +Christopher Potts +Eric Tremblet +Bernard Hunt +Evening Shade Pottery +Brian Cole +George McGinnis +Egid Schabl +Harold Henn +Chris VanCaeseele +Denis Novomlintsev +Pascal Amidey +Hermann Klampferer +Philippe Faure +Dean Berg +Sven Assmus +Gary Potter +Moritz Suerdieck +Eric Olivi +Jean-Jacques Pointel +Vianney Levesque +Fred Carlisle +Pierre Duvezin-Caubet +Pascal Dugué +Burt Pickard-Richardson +Robert Wilhelm +Thomas Kilduff +Hans-Rudolf Riniker +Arkadiusz Milewski +Kenneth Frehafer +Jens Ziegler +Peter Arnold +Jason Cole +Richard Vollkommer +Sherwood Drumheller +Jean-Christophe Gardaz +Igor Pongrac +James Mare +Kerry Cochrell +Florian Derriennic +HLL Vogels +Gordon Evans +Gaines Smith +Daniel Vogel +RCdiy +Joseph S Robinson +Jack Dunkley +Hannes Niethammer +Thierry Laligand +Pierre Duvezin-Caubet +Hannes Mössler +Petr Kysela +Calvin McCarthy +Piet Bomberg +Arne Johan Helle +Cees de Greef +Marc Gittelman +Scott Pritchett +Konstantinos Katsaklis +William Tortorello +Mark Maskiell +Gerald Peklar +Sidney Gates +Jörg Zander +Bryan Anderson +Stephane Monfette +Paul Poschen +Marco Lange +Peter Foto +Antonio Munuera +Vasil Petrov +Robert Wilhelm +Richard Hodgson +Manny Tau +Leonard MacKey +Johannes Wollenweber +Rodney Huddleston +Glen Roe +Chad Cranford +Tom Figge +Joerg-Dieter Rothfuchs +David Lorenzo +Chris Conroy +Fernando Wascheck +Martin Schoitsch +André Curci +Lukas Fischer +Larry Truesdale +Bernd Koehler +David Newton +Stephen Lesage +Mona Sturgis +Russell G Shanks +CY Enterprise +William Tortorello +André Lasseret +Lothar Thole +Stuart Olson +Paweł Stróż +Tim Buss +Christian Schaefer +Willyp +David Owens (monthly) +Willem Reij +Arthur Costerus +Martin Oldershaw +Robin Wienke +Jeffrey Johnson +Franz Josef Hahn +Burt Gray +Daniel Dupont +Felix Kaiser +Nicola Claudio Rossi +Gary Clayton +John Bitzer +Scott Campbell +Martin Polák +Jonathan Pruett +Charles Nowell +Randy Melton +Jo Jung +Chris Monk +Alvin Burke +Georges d'Haussy +Philippe Lhomme +Carsten Ullerup +Wolfgang Schneider-Reif +Anselm Schopplick +Georgios Papadopoulos +Thorsten Weber +Alexander Röhlich +Karl-Heinz Behn +Stefan Köhler +Jochen Kaphengst +Hans-Jüergen Duwe +Christoph Dalloz +Alexander Wimmer +Horst Efftinge +Nektarios Ntikmpasanis +Derek Gates +John Alsbrooks +Jürgen Deininger +Bruce Jones +Meinhard Schöll +Rolf Lemb +Casey Layton +Robert Bates +Udo Nowakowski +William Hallman +Paul Stein +Nurflügel & Modelltechnik +Gary Wild +James A Davey +Marco Giuseppe Colturi + diff --git a/DONATIONS.txt b/DONATIONS.txt deleted file mode 100644 index de1c76bf5..000000000 --- a/DONATIONS.txt +++ /dev/null @@ -1,1188 +0,0 @@ -FrSky (monthly) -Aloft Hobbies -Jonathan Modellismo -WsTech -Aviomotive -BoltRC -Aerial Tech Hobbies -LitePilots -David Ankers (OpenPilot) -3D Robotics -RC Studio (monthly) -Craft & Theory (monthly) -OpenTX Manuals by Lothar Thole - -Mario Sette -Felice Baratto -Alessandro Mari -Gianpiero Spontina -Ingo Kuzniak -Hans-Åke Rahm -Tamas Varga -Thomas Gregg -Didier Christien -Alain Pinard -Sergio Melas -Paul Montenot -Chris Guy -Adrien Gravouille -Thomas Black -Marc Lucht -Zdenek Trojanek -Martin Hotar -Stefan Grundevik -Fabio Eboli -Federico Zotti -Albin Esbjörnsson -Kilian Hüttenhofer -Stephen Stough -Adilson Oliveira -Robert Saint Marie -Tad Leake -Andreas Weitl -Chan Lofland -Dirk Kasten -Denisov Alexander -Timo Varppee -Ondrej Hatapka -Valérie Billon -R. Scott Page -Johan Cronje -Renato Aranghelovici -Jeffrey Irvin -Kenneth Crump -Damjan Adamic -Martin Wilson -John Holdsworth -Daniel Schwartz -Dean Church (monthly) -Michael Halse -David Mark -Ted Moss -Jim Wagner -Nicola Porzi -Michael Halse -Chewytm -Espen Solbu -Mike Frizell -Bruce Jones -Stefano Airaghi -Dan Eeckhout -Alex Calderhead -Leonard MacKey -Heung Jin Choi -Mike Retterer -Keith Wood -Viljo Liukku -Eric Beier -Burt Pickard-Richardson -Helmut Renz -Rick Harms -Vincenzo Vavala -Patricia Martin -Harald Klein -Carl Petersen -Douglas Burkett -Clifford Evans -Teodor Yantchev -Jarad Berkman -Christian Schulz -Gregory J Shepherd -Michael Shellim -Ming Wang -Bernard Lukaschek -Nigel Chippindale -Mike Perkins -Ted Hammond -David Beanland -Bernd Koehler -Frédéric Duflos -Dave Fasken -Heinrich Illig -Michael Collins -Michael Manning -Craig Lorentz -André Lasseret -Felipe Alexandre de Oliveira -Brian Harris -Philippe Herbots -Rainer Nelte -Franck Bernhard -Erhard Werner -Stig Jøran Moen -Keith Hertzog -Christophe Dauvergne -Tauno Rautakorpi -Sven Assmus -Paul Dittman -Mike Matheny -Cheryl Wynne -Emay Toha -Don Nolder -André Lasseret -Filip Lowette -Arnaldo Gabella -Fiorenzo Agnelli -Michele Villa -Christophe Rodriguez -Larisa Filocamo -Hartmut Sahm -Åke Brodin -Ted Moss -Filippos Tigarakis -Chewytm -Eric Burdis -Nigel Chippindale -Michael Deasy -Stephen Stough -Kenneth Lilja (monthly) -Robert Jero -Gary Bancroft -Robert Cotsford -NorthSide -George Constandinides -Robert Schonk Jr -Kevin Berkefeld -Peter Webster -Mike Matheny -Martin Sniedze -Fernando Rimoldi -Sidney Fisher -John Rodgers -Ed Pare -Thomas Kilduff -Robert Ferguson -Bryan Green -Kevin Berkefeld -Julien Michel -Krittikun Chiraphanda -Douglas Law -Alberto Scotti -Oliver Kunkel -D. Joseph Frazier -Heiko Polig -Andrew Fernie -Marco Lange -Nick McMillan -Michel Baily (monthly) -Patrick Mullen -Scott Campbell -Erich Roeder -Wayne Davy -Michael Fontenot -Willie Swanepoel -Satoru Sasaki -Tyler Darby -Nicholas Crego -Johan Moelich -Timo Esser -Brian Paddock -Jean Pierre Parisy -Norbert Martsch -Jean-Marie Guitard -Tilman Baumann -Fred Larssen -Ari Aalto -Robert Sams -Kirk Robertson -John Koontz -Jeffery Golias -Paul Robinson -Dave Matison -Mike Matheny -Pino Agostino -Graham Boucher -Nelson Noura -Joel Allamy -Philip David Martin -Sean Stephen -Bruce Mackay -Blake Spilman -Timothy Pelletier -Glen Roe (ShowMaster) -Jan Van Ooteghem -Lawrence Christensen -Leo Duflou -Bruce Wood -Arnd Feige -Tauno Rautakorpi -Steve Coley -Stefan Kiendl -Gregory Nuspel -Mitchell Brenner -Ronnnie DePrez -Ferenc Koller -Robert Sessler -Didier Lanot -Rodney Hunt -Steve Bernard -Paul Nazaroff -Gordon Ernenputsch -Ksamak -Marc Gittelman -David Poole -Ralph Sauer -Karl-Heinz Gansel -Michels Bernhard -Thomas Demmelbauer -Felice Baratto -Michael Halse -Horst Kampen -Ian Gough -Matthew Brett -Lexington S Morley -Clemens Drews -Axel Stöckle -Roberto Orsello -Richard Ruck -Hugh Caldwell -Christian Marauli -Albin Esbjörnsson -Per Esbjörnsson -Bernd Hohmann -Sławomir Juszczak -Stephen Henderson -David Morgan -Aloft Hobbies -Netanel Hobara -Cameron Galipo -Doug Schafer -Pietro Rossin -Earl Killingsworth -Victor B Wright -Terry McKinley -Марков Алексей -Offer Shmuely -Ian Lobley -Stéphane Fortas -Peter Mitrik -Thomas Majewski -ANF King -Henrik Hammarström -Kenneth Lilja -R Wells -Uwe Jordt -Harald Wilczak -Bernhard Lohmann -Ferenc Koller -Robert Ferguson -Daniel Byers -Tyler Darby -Miguel Villalpando -Kim Dong Hoon -Terry McKinley -Walter Bell -Clinton Linck -Josep Clodas Sola -Thierry Martin -Peter Mauro -Mitchell Brenner -Yak -Lluis Bullich Rañe -Steffen Rohr -Eric Jacquin -Harvest Lane -Ville Kuvaja -DK-System -Heinz Vogel -Heung Jin Choi -MMJS van der Helm -Dan Neelands -Yashiro Masayuki -Isaac Sloan -Harold Baird -Roy Bender -Bradley Murchie -Maximilian Süß -Dean Jansa -Ronald Donker -Paul Oldenkamp -Dietmar Drees -Bradley Murchie -Richard Fahie -James Kaufman -Henry Deucker -Christian Fuchs -Arold Reinders -Robert Miller -Mark Gaskievicz -Roland Müller -Frank Gewalt -Remi Viard -Reginald H Millsom -Pierluigi Sommaruga -A Harris -Stefan Grunenberg -Francisco Gutierrez Muñoz -Steve Coley -Sean Cull -Roberto Orsello -David Finger -Jean-Marie Oddo -Mike Matheny -Glen Roe (Showmaster) -Arron Bates -Tim Spurr -Daniel Morgan -Trent Ready -Mark Maskiell -Robert Crockford -Mark Illum -David McGuire -Martyn Coles -Jose Sobral -Heung Jin Choi -Tomasz Janiak -Fabien Gagné -Micha Ronen -Albert Blondin -Klaus Schuebel -Evening Shade Pottery -Thomas Kilduff -Sven Assmus -Markus Eberl -Nicholas Field -Harald Wilczak -John Grepps -Anthony Burbidge -Sherba Baine -Gordon Evans -Fred Figge -Uwe Kuehn -David Beatty -Aaron Stringer -Alan J Wasserman -Wolfgang Rauser -Samuel Cook -Friedrich Ipolt -Barrington Cole -Charles Lakins -Thos. O'Meara Photography -Adam Chevalier -Mike Mulligan -Serge Michaux -Robert Young -Wilco Hijink -Roy Nixon -Lexington S Morley -Daryl Dacko -Beat Zurflueh -Piotr Kundu -Kevin Berkefeld -Tomasz Klys -Mirco Didone' -Christoph Schroeter -Zdenek Trojanek -Bryan Anderson -Kamco Enterprises -Robert Bates -Robert Brown -Dennis Marinus -Ronald Van Putte -Thomas Kvitle Jenssen -Patrick Tuxbury -Istvan Magi -Sasaki Satoru -David Laburthe -Vit Jelinek -Pablo Gomez Martinez -Alan Thoren -Jack Clodfelter -William Simon -James Houck -Peter Fithern -Thomas Svedman -TechFixPros -Rafael Eric Suarez Nordlow -Colin Rycroft -Emanuel Stassar -Michael Gregory -Robert Russell -Felix Kaiser -Joshua Bardwell -Davd Goodall -Leonard MacKey -Miles Kelly -Sergio Robledo -Mikael Wallbäck -Daniel Malcman -Paul Dittman -Attilio Rausse -Sidney Gates -Andrea Montefusco -Paul Luby -Donald L Webster -Kenneth Frehafer -Matthias Hase -Markus Wolf -Andrew Fazio -Stefan Künst -Stephen Adams -Tauno Rautakorpi -Frank Houvenaghel -George Neusse -Andreja Rusjakovski -Axel Stöckle -Erwin Störrle -Rodger Hopper -Fernando Cesar -Jonathan Gillis -DK-System -Lexington S Morley -Bernd Koehler -Davis RC -Pete Johnson -Patricia Martin -Florian Tschacher -Brian Spearing -Craig Hall -Joseph Case -Harald Klein -Robert Crockford -Chris Boultinghouse -Kitsew -Georgios Papadopoulos -Fourmost Products -Dennis Miller -Dave Matison -Maximilian Radig -Juan Rodriguez -Robert Sessler -John Murray -Martin Sniedze -David Poole -Manfred Delakowitz -Martijn Kruissen -Jörgen Norman -Nathan Kinney -John Godden -Larry Roper -Mike Frizell -Daniel Pospolita -Peter Herz -Don Mondrik -Paul Fram -Charles Knight -Matthew Adams -Kenneth Reed -Gary Wild -Christof Ramm -Bruno Bedard -Salih Samim Aydin -Alexander Pils -Andrew Scerbina -Donovan Bodishbaugh -Ray Dunn -Burt Pickard-Richardson -Robert Ferguson -CY Enterprise -Michel Stathakis Neto -Beat Zurflueh -Portstate Pty Ltd -Jens Hoffmann -Ricardo Santos -Jean-Francois Le Breton -Michael Deasy -Anindya Mukerjee -Emay Toha -Kamco Enterprises -Peter Mueller -Giovanni Trentini -Cecil Porter -Robert Canavan -Greg Higginbottom -Tim Walker -Spis Ltd/TurboNote -Patricia Cox -Matthew Lukes -Sabine Witte -Phillip Perry -Beat Zurflueh -Russell Stutzman -Dietmar Drees -Kenneth Ward -Jens Lochmüller -Anthony Witham -Peter Hauke -Arizona Action Photos -Francis F Dale -Willie Swanepoel -Edward Hauser -Adilson Oliveira -Joseph Ordille -Michael Shellim -Teddie Holmes -Alexandre Rault -Eric Albin -Lukas Kliment -Bernard Philippe -Bernard Delpy -Didier Klein -Arnaldo Guedes -Cyberauto Systems -John Alsbrooks -John Kearney -Christopher Borden -Marc Virgilio Ricci -Frederick Davie -Jürgen Enders -Terrence Pitts -Thomas Sandner -Marco Coltorti -Harald Wilczak -Rodney Lorimor -Richard Davis -Stephen Palmer -Michael Napolitan -Joshua Bardwell -Fred Dawson -Jim Wagner -Peter Johnson -Fredrik Lewerth -Arvin Stenersen -Daniel Morgan -Roy Nixon -Joachim Blunck -Karl-Heinz Gansel -Monrovia Mountain Enterprises -Alessandro Villa -Jan-Åke Nilsson -Matthias Rei -DVR Solutions BV -Bertrand Condevaux Lanloy -Henri Mirra -Aurélien Planiol -Kevin Caldwell -Andrew Garello -Tomasz Maziarz -Russell Flack -Fernando Rimoldi -Greg Reid -Dietmar Drees -Holger Landwehr -Arno Loehdorf -Boon Sripattha -Patrik Åkerfeldt -Alonzo Fretwell -Renjith Chandrasekharan -Ruben Gomez Hernandez -Michael Gardner -Judith Green -Timo Ruppell -John Lipscomb -Norbert Wenke -Erik Frieberg -Raimo Ruotsalainen -Brian Harris -Sebastian Blüml -Efisio Maxia -Jeff Theobald -Anthony Rizzo -Rodney Huddleston -Dietmar Drees -Jürgen Monden -David Morgan -Andrew Fernie -Donald Burke -Ronald Donker -Fredie Singh -Patrizio Simoncini -Harald Gabler -Michael Brown -Julien Gérard -Alexandre d'Alton -Peter Mergaerts -Jan Houwers -Christian Grandjean -Roger Bergevin -NorthSide -Sigmund Martinsen -Lionel Lafraise -Gisli Ofeigsson -The Gruvin9x Project -Manuel McLure -Fernando Rimoldi -Hiltenkamp Stephan -Sandeep Kishore Jain -Greg Parker -Norman Maaß -Adriano Del Ben -Justin Poole -Kenneth Harrison -Eugene LaFaille -John O'Shaughnessy -Uwe Jordt -Stuart Olson -Frédéric Devillard -Cheung Leo -Peter Webster -Jean-Claude Bachetta -Delfin Perena -Sae-wook Yoon -Focus on Excellence -Jeffery Golias -Nick Milton -Paul Zasso -Reidar Johannes Lillebotn -Handley William -Luke Williams -Michael Shellim -Brian Spearing -Derek Foster -Pasi Pitkänen -Lexington S Morley -Jeff Roberson -Volkov Victor -Bryan Anderson -Daniel Garber -Pavel Stein -Ravi Gupta -Patrick Tuxbury -Mark Deverell -John Capell -Neil McVean -Matthew Elyash -Kerry Cochrell -Willem Aandewiel -Reg Bell -Jean Chenoz -Philippe Grand -Tauno Rautakorpi -Jeff Dillingham -Brad Kelley -Shaun Currier -Danilo Schiara -John Hennig -RK Custom Homes -James Houck -Piet Teekens -Tommy Widenflycht -Johan Petrus Theophilus -Maria van Melis -Ralph Gustafson -Paul Luby -Andrew Duncan -Stephen Crowther -Edward Glover -Kelly Byrd -Brad Curtis -Wolfgang Kuhl -John Beidl -Roy Nixon -Glen Roe -CY Enterprise -Evening Shade Pottery -Gilles Dando -Patrick Richard -Justin Altemeier -Constant Dupuis -Tony Kenward -Pierre Rondel -Ernest Luguera Sanchez -Adam Brackney -Joe Baker -单 雷平 -Ben Fay -Chris Monk -Stan von Miller -Christian Krebs -Michel Motte -Graziano Rampinelli -Joe Baker -Jean-Philippe Laurent -Romain Rouzaud -Michel Garbarino -Henri Mirra -Otto Fröhlich -Thomas Cramer -Anthony Trombetta -Fernando Rimoldi -Dietmar Drees -Michal Kowalski -Ivan Correa -Modellbau -Massimo Luigi Stara -Graham Baldwin -Tomasz Rejman -Wolfgang Lang -John Greenwood -Till von Reumont -Paul Pereira Brunner -Donald L Singer -Junsun Lee -Guy Lamaison -Erwin Dulken -Mike H Dailey -Jon Cammarata -Martin Krueger -Adolfo Perogio -Sylvain Techer -Wes Warner -Kevin Caldwell -Ali Ersan Gur -Hans-Rudolf Riniker -Sébastien Boutard -Jean Chessé -Mike H Dailey -Don Polk -Roberto Orsello -Borovikov Dmitriy -John Lipscomb -Peter Glassey -Joseph Kramer -F.Javier Martinez Velasco -Claudio Piccinini -John Jackson -John Beech -Rene TraaJohn Jackson -Sebastien Charpentier (monthly) -Nigel Hendriks -Frédéric Devillard -Albert Herzog -Anindya Mukerjee -Kenny Stanberry -Tauno Rautakorpi -Mathias Krapp -Fernando Rimoldi -Wolfgang Rauser -Richard Shagam -Stephen Bailey -DK-System -Casa Kuxtal -Christopher Potts -Douglas George -Michael Banks -Jon Wiltshire -David Green -Guy Willems -Xavier Mestelan Pinon -Maik Gottschalk -Scott Sparks -John Dunning -RAD51 -Ron Powell -Alain Labonne -Carol Sills -Franck Aßmann -Larry Anderson -Mikael Wallbäck -Wes Warner -Christoffer H Henni -Donna Bayer -Garry Ogilvie -Karlheinz Sirsch -Fred Larssen -Rob Coppock -Franz Josef Hahn -Serge Ribault -Tanguy Le Moign -Barrett Powell -Patrice Lafeuille -Martin Blume -Marek Kopyto -Marco Lange -Gary Nix -Jack Oliphant -John Lever -Adolphe Montefiore -Steven De Weerdt -Håkan Berggen -Ayelet Egosi -Jean-Frederic Gaudreault -Jim Wagner -Lee Scott -Roger Keatley -Sherman Lovell -Hugh Caldwell -JB Fisher Company -Michels Bernhard -Pietro Rossin -Carsten Wache -Brock White -Steven Poretz -David Huelster -Gordon Stahl (monthly) -John Mathison -Richard Duczmal -Gregory Barron -Marcel Fischer -Klas Mälman -Viljo Liukku -Eric Smith -Sven Assmus -Luke Mole -NorthSide -Hannes Mössler -James Kaufman -Ravi Gupta -Lexington S Morley -Ralph Segar -Frédéric Devillard -Cory Theurer -Valentinos Zachariou -Garrett Paquette -Heung Jin Choi -Kerry Cochrell -Doug Miller -Andrzej Weydmann -Chair-man.nl -Eric Beier -Jay Warren -Marian Matej -Alastair Smith -Timothy Senecal -Dietmar Drees -Bruce Jones -Adil Busaidy -Herman Hofman -Jean Paul Michel -Peter McHenry -Julien lecoquierre -Jean-Marie Clay -Robert Nicoll -Dan Nixon -Ewald Moehring -Giovanni Carnesecchi -Paul Dumsday -Tadeusz Adamowski -Andrew Newton -Neil Horne -Kerstin Appelqvist -John Curran -Gerald Thiel -Jürg Bingisser -George Emer -Jerzy Manarczyk -Gerard Braakhuis -Nicolas Leblond -Burt Pickard-Richardson -Jiri Petrzelka -RK Custom Homes -David Semeria -Philip Lewis -William Kim -Dean Berg -Tim Spurr -Clifton Hipsher -Mike Frizell -Oliver Jacob -Pawel Stepien -Thomas Kilduff -Barry Fox -Anatoly Bakalenko -Bruce Anderson -Jeremy Cowgar -Edward Hauser -Stuart Brown -Anton Glock -Roger Ritchie -George Carnie -Philippe Stofleth -Tim Dzugan -Illia Izotov -Richard Miles (monthly) -Attila Kapolnai -Gilles Dando -Denis Roussille -Olivier Anken -Michel Motte -David McDonald -Tauno Rautakorpi -Carsten Schlassa -Angel de la Dehesa Calles -Michel Garbarin -Algirdas Tamosiunas -Petr Kysela -Pascal Roux -Robert Whitfield -InTheTubeDeep -Jaromir Malek -Joe Street -Regin Poulsen -Hervé Laveyssiere -Walter Fowler -Richard Wagner -Kevin Hyman -Herald Reichel -Frederic Rouyre -David Libby -Hans Timmermans -Adrian De Zee -John Hanagan -Didier van Steensel -Julius Vicze -Cristiano Merighi -James Holley -Chris Merry -Jiri Fojtasek -Thierry Laligand -Hassouna Cherif -Fred Thijssen -Andrew Gardiner -Christian Niß -Douglas Penney -Starck Associates -Johannes Wollenweber -Fred Page -Jean Trouche -Patrick Blanc -Jean-Louis Tonnellier -Masoud -Mustafa Güven -William Waters -Joël Allamy -William Mckinstry -Jean-Jacques Pointel -Frédéric Rouyre -Jonathan Pruett -Jörg Zieren -Christopher Rhodes -Marco Strack -Stefano Boggia -Dwayne Myers -Stavros Papathanasiou -Roland Nittby -Courtney Puskas -NorthSide -Martin Polák -Ulf Reinhardt -Wolfgang Renisch -Trevor Hinze -Mohammad Zargari -Dr. Willutzki -Jean Pierre Bernard -Patrick Castellan -Udo Tödter -Marc J Merlin -Paul Chitonu -Wolfgang Rauser -Emmanuel Dallery -James Lyons -Tauno Rautakorpi -Gerald Peklar -Fabien Gagné -David Cox -Philip Cork -Kevin Wright -John Scott -Yves Berger -Otto Fröhlich -Kenneth Lilja -Benjamin Johnson -Brad Kelley -Michel Biancki -Lynn Laycock -Claude Godefroy -Gérald Joubert -Wayne J Podaima -Philippe Peyron -Julien Kieffer -Gregor Walter -Carlos Viegas -Roberto Orsello -Steve Murray (monthly) -Marcel Schäfer -Sean Cull -Holger Bothmer -Michael Manning -Martin Risik -ZEN Computer Services -Egbert Stohlmann -Martin Peryea -Nathan James -Luis Suarez -Artur Uzieblo -InTheTubeDeep -Jaap Greve -Peter Glassey -David Reynolds -David Frazier -Donald L Singer -George Carnie -Susan Holbert -Richard Garrett -Paco Galván -Matthew Sylvester -Robert Bates -Hans-Peter Endres -Axel Stöckle -Leonard MacKey -Andrew Fernie -Mark McCoy -Damir Pooshs -Jeff Dillingham -Brent Hampton -Arkadiusz Milewski -Garry Ogilvie -Donald Porter -William Simon -Thomas Sandner -Pascal Pochard -Helmut Renz -T S Pung -Jorge Trinidad -Yeo Jonathan -David Olivier -Thierry Martin -Udo Nowakowski -Philippe Stofleth -Alain Labonne -Atam Gangaram Panday -Sajjad Rahman -Giovanni Carnesecchi -Lorenzo Frassy -Reinaldo Perez -Christian Aussillou -Christopher Potts -Eric Tremblet -Bernard Hunt -Evening Shade Pottery -Brian Cole -George McGinnis -Egid Schabl -Harold Henn -Chris VanCaeseele -Denis Novomlintsev -Pascal Amidey -Hermann Klampferer -Philippe Faure -Dean Berg -Sven Assmus -Gary Potter -Moritz Suerdieck -Eric Olivi -Jean-Jacques Pointel -Vianney Levesque -Fred Carlisle -Pierre Duvezin-Caubet -Pascal Dugué -Burt Pickard-Richardson -Robert Wilhelm -Thomas Kilduff -Hans-Rudolf Riniker -Arkadiusz Milewski -Kenneth Frehafer -Jens Ziegler -Peter Arnold -Jason Cole -Richard Vollkommer -Sherwood Drumheller -Jean-Christophe Gardaz -Igor Pongrac -James Mare -Kerry Cochrell -Florian Derriennic -HLL Vogels -Gordon Evans -Gaines Smith -Daniel Vogel -RCdiy -Joseph S Robinson -Jack Dunkley -Hannes Niethammer -Thierry Laligand -Pierre Duvezin-Caubet -Hannes Mössler -Petr Kysela -Calvin McCarthy -Piet Bomberg -Arne Johan Helle -Cees de Greef -Marc Gittelman -Scott Pritchett -Konstantinos Katsaklis -William Tortorello -Mark Maskiell -Gerald Peklar -Sidney Gates -Jörg Zander -Bryan Anderson -Stephane Monfette -Paul Poschen -Marco Lange -Peter Foto -Antonio Munuera -Vasil Petrov -Robert Wilhelm -Richard Hodgson -Manny Tau -Leonard MacKey -Johannes Wollenweber -Rodney Huddleston -Glen Roe -Chad Cranford -Tom Figge -Joerg-Dieter Rothfuchs -David Lorenzo -Chris Conroy -Fernando Wascheck -Martin Schoitsch -André Curci -Lukas Fischer -Larry Truesdale -Bernd Koehler -David Newton -Stephen Lesage -Mona Sturgis -Russell G Shanks -CY Enterprise -William Tortorello -André Lasseret -Lothar Thole -Stuart Olson -Paweł Stróż -Tim Buss -Christian Schaefer -Willyp -David Owens (monthly) -Willem Reij -Arthur Costerus -Martin Oldershaw -Robin Wienke -Jeffrey Johnson -Franz Josef Hahn -Burt Gray -Daniel Dupont -Felix Kaiser -Nicola Claudio Rossi -Gary Clayton -John Bitzer -Scott Campbell -Martin Polák -Jonathan Pruett -Charles Nowell -Randy Melton -Jo Jung -Chris Monk -Alvin Burke -Georges d'Haussy -Philippe Lhomme -Carsten Ullerup -Wolfgang Schneider-Reif -Anselm Schopplick -Georgios Papadopoulos -Thorsten Weber -Alexander Röhlich -Karl-Heinz Behn -Stefan Köhler -Jochen Kaphengst -Hans-Jüergen Duwe -Christoph Dalloz -Alexander Wimmer -Horst Efftinge -Nektarios Ntikmpasanis -Derek Gates -John Alsbrooks -Jürgen Deininger -Bruce Jones -Meinhard Schöll -Rolf Lemb -Casey Layton -Robert Bates -Udo Nowakowski -William Hallman -Paul Stein -Nurflügel & Modelltechnik -Gary Wild -James A Davey -Marco Giuseppe Colturi diff --git a/companion/src/CMakeLists.txt b/companion/src/CMakeLists.txt index cad619d2f..e0b4ed601 100644 --- a/companion/src/CMakeLists.txt +++ b/companion/src/CMakeLists.txt @@ -218,7 +218,7 @@ set(companion_SRCS burnconfigdialog.cpp multimodelprinter.cpp comparedialog.cpp - contributorsdialog.cpp + creditsdialog.cpp releasenotesdialog.cpp releasenotesfirmwaredialog.cpp customizesplashdialog.cpp @@ -252,7 +252,7 @@ set(companion_MOC_HDRS printdialog.h fusesdialog.h logsdialog.h - contributorsdialog.h + creditsdialog.h releasenotesdialog.h releasenotesfirmwaredialog.h customizesplashdialog.h diff --git a/companion/src/companion.qrc b/companion/src/companion.qrc index 18b46f26a..5e96a88cb 100644 --- a/companion/src/companion.qrc +++ b/companion/src/companion.qrc @@ -3,7 +3,6 @@ images/customize.png icon.png ../../CREDITS.txt - ../../DONATIONS.txt ../releasenotes.txt images/screenshot.png images/splash.png diff --git a/companion/src/contributorsdialog.cpp b/companion/src/creditsdialog.cpp similarity index 70% rename from companion/src/contributorsdialog.cpp rename to companion/src/creditsdialog.cpp index dc882be81..29b6b79bc 100644 --- a/companion/src/contributorsdialog.cpp +++ b/companion/src/creditsdialog.cpp @@ -18,12 +18,12 @@ * GNU General Public License for more details. */ -#include "contributorsdialog.h" +#include "creditsdialog.h" #include "ui_htmldialog.h" #include "helpers.h" #include -ContributorsDialog::ContributorsDialog(QWidget * parent): +CreditsDialog::CreditsDialog(QWidget * parent): QDialog(parent), ui(new Ui::HtmlDialog) { @@ -42,42 +42,8 @@ ContributorsDialog::ContributorsDialog(QWidget * parent): "" ""; - QFile credits(":/CREDITS.txt"); - if (credits.open(QIODevice::ReadOnly | QIODevice::Text)) { - QStringList names; - while (!credits.atEnd()) { - QByteArray line = credits.readLine(); - if (line.trimmed() == "") - break; - names.append(line.trimmed()); - } - str.append(formatTable(tr("Main Developers"), names, 3)); - - names.clear(); - while (!credits.atEnd()) { - QByteArray line = credits.readLine(); - names.append(line.trimmed()); - } - str.append(formatTable(tr("Other contributors"), names, 3)); - } - - QFile donations(":/DONATIONS.txt"); - if (donations.open(QIODevice::ReadOnly | QIODevice::Text)) { - QStringList names; - while (!donations.atEnd()) { - QByteArray line = donations.readLine(); - if (line.trimmed() == "") - break; - names.append(line.trimmed()); - } - str.append(formatTable(tr("Companies and projects who have donated to OpenTX"), names, 3)); - - names.clear(); - while (!donations.atEnd()) { - QByteArray line = donations.readLine(); - names.append(line); - } - str.append(formatTable(tr("People who have donated to OpenTX"), names, 6)); + foreach(CreditsSection section, readCredits()) { + str.append(formatTable(sectionTitle(section.title), section.names, 3)); } str.append("" \ @@ -87,9 +53,9 @@ ContributorsDialog::ContributorsDialog(QWidget * parent): #if 0 QFile blacklist(":/BLACKLIST.txt"); if (blacklist.open(QIODevice::ReadOnly | QIODevice::Text)) { - QStringList names; - names << blacklist.readAll(); - str.append(formatTable(tr("OpenTX Blacklist"), names, 1)); + QStringList names; + names << blacklist.readAll(); + str.append(formatTable(tr("OpenTX Blacklist"), names, 1)); } #endif @@ -99,12 +65,45 @@ ContributorsDialog::ContributorsDialog(QWidget * parent): ui->textEditor->setOpenExternalLinks(true); } -ContributorsDialog::~ContributorsDialog() +CreditsDialog::~CreditsDialog() { delete ui; } -QString ContributorsDialog::formatTable(const QString & title, const QStringList & names, int columns) +QList CreditsDialog::readCredits() +{ + QFile credits(":/CREDITS.txt"); + QList result; + if (credits.open(QIODevice::ReadOnly | QIODevice::Text)) { + while (!credits.atEnd()) { + QByteArray line = credits.readLine().trimmed(); + if (line.size() >= 2) { + if (line.startsWith("[") && line.endsWith("]")) { + result.push_back(CreditsSection(line.mid(1, line.size() - 2))); + } else { + result.back().addName(line); + } + } + } + } + return result; +} + +QString CreditsDialog::sectionTitle(const QString & title) +{ + if (title == "Main developers") + return tr("Main developers"); + else if (title == "Translators") + return tr("Translators"); + else if (title == "Companies and projects who have donated to OpenTX") + return tr("Companies and projects who have donated to OpenTX"); + else if (title == "People who have donated to OpenTX") + return tr("People who have donated to OpenTX"); + else + return tr("Other contributors"); +} + +QString CreditsDialog::formatTable(const QString & title, const QStringList & names, int columns) { const float cwidth = 100.0 / columns; QString str = "
 
" \ diff --git a/companion/src/contributorsdialog.h b/companion/src/creditsdialog.h similarity index 62% rename from companion/src/contributorsdialog.h rename to companion/src/creditsdialog.h index 801984923..c1327aeea 100644 --- a/companion/src/contributorsdialog.h +++ b/companion/src/creditsdialog.h @@ -18,8 +18,8 @@ * GNU General Public License for more details. */ -#ifndef _CONTRIBUTORSDIALOG_H_ -#define _CONTRIBUTORSDIALOG_H_ +#ifndef _CREDITSDIALOG_H_ +#define _CREDITSDIALOG_H_ #include @@ -27,17 +27,36 @@ namespace Ui { class HtmlDialog; } -class ContributorsDialog : public QDialog +class CreditsDialog : public QDialog { Q_OBJECT + class CreditsSection + { + public: + CreditsSection(const QString & title): + title(title) + { + } + + void addName(const QString & name) + { + names.push_back(name); + } + + QString title; + QStringList names; + }; + public: - explicit ContributorsDialog(QWidget * parent = 0); - ~ContributorsDialog(); + explicit CreditsDialog(QWidget * parent = 0); + ~CreditsDialog(); private: Ui::HtmlDialog * ui; + QList readCredits(); + QString sectionTitle(const QString & title); QString formatTable(const QString & title, const QStringList & names, int colums); }; -#endif // _CONTRIBUTORSDIALOG_H_ +#endif // _CREDITSDIALOG_H_ diff --git a/companion/src/mainwindow.cpp b/companion/src/mainwindow.cpp index 371710e60..a046ee9e7 100644 --- a/companion/src/mainwindow.cpp +++ b/companion/src/mainwindow.cpp @@ -30,7 +30,7 @@ #include "downloaddialog.h" #include "printdialog.h" #include "version.h" -#include "contributorsdialog.h" +#include "creditsdialog.h" #include "releasenotesdialog.h" #include "releasenotesfirmwaredialog.h" #include "customizesplashdialog.h" @@ -732,7 +732,7 @@ void MainWindow::fwPrefs() void MainWindow::contributors() { - ContributorsDialog * dialog = new ContributorsDialog(this); + CreditsDialog * dialog = new CreditsDialog(this); dialog->exec(); dialog->deleteLater(); } From 96ccb4cb3fc110feb2b83c500ba2c62536e7af4f Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sat, 6 May 2017 12:04:51 -0400 Subject: [PATCH 197/203] [Companion] Fix a few translations. (#4890) * [Simulator] Fix keymap translations. * [Companion] Fix translations in file type selector dialogs. * [Simulator] Fix inadvertent help text delimiter change. --- companion/src/constants.h | 30 ++--- companion/src/flasheepromdialog.cpp | 2 +- companion/src/mainwindow.cpp | 8 +- companion/src/mdichild.cpp | 2 +- .../src/simulation/simulateduiwidget9X.cpp | 18 +-- .../src/simulation/simulateduiwidgetX12.cpp | 18 +-- .../src/simulation/simulateduiwidgetX7.cpp | 12 +- .../src/simulation/simulateduiwidgetX9.cpp | 12 +- .../src/simulation/simulateduiwidgetX9E.cpp | 12 +- companion/src/simulation/simulator_strings.h | 104 +++++++++--------- .../src/simulation/simulatorstartupdialog.cpp | 2 +- 11 files changed, 110 insertions(+), 110 deletions(-) diff --git a/companion/src/constants.h b/companion/src/constants.h index 322b016a1..6b8eac456 100644 --- a/companion/src/constants.h +++ b/companion/src/constants.h @@ -21,6 +21,8 @@ #ifndef _CONSTANTS_H_ #define _CONSTANTS_H_ +#include + #define CPN_MAX_MODELS 60 #define CPN_MAX_TIMERS 3 #define CPN_MAX_FLIGHT_MODES 9 @@ -47,23 +49,23 @@ #define CPN_MAX_MOUSE_ANALOGS 2 #define CPN_MAX_ANALOGS (CPN_MAX_STICKS + CPN_MAX_POTS + CPN_MAX_MOUSE_ANALOGS) -#define CPN_STR_FILES QT_TRANSLATE_NOOP("CompanionMacros", "files") -#define CPN_STR_RAD_MOD_SETTINGS QT_TRANSLATE_NOOP("CompanionMacros", "Radio and Models settings") -#define HEX_FILES_FILTER "HEX " CPN_STR_FILES " (*.hex);;" -#define BIN_FILES_FILTER "BIN " CPN_STR_FILES " (*.bin);;" -#define DFU_FILES_FILTER "DFU " CPN_STR_FILES " (*.dfu);;" -#define EEPE_FILES_FILTER "EEPE " CPN_STR_FILES " (*.eepe);;" -#define OTX_FILES_FILTER "OpenTX " CPN_STR_FILES " (*.otx);;" -#define EEPROM_FILES_FILTER CPN_STR_RAD_MOD_SETTINGS " " CPN_STR_FILES " (*.otx *.eepe *.bin *.hex);;" OTX_FILES_FILTER EEPE_FILES_FILTER BIN_FILES_FILTER HEX_FILES_FILTER -#define FLASH_FILES_FILTER "FLASH " CPN_STR_FILES " (*.bin *.hex *.dfu);;" BIN_FILES_FILTER HEX_FILES_FILTER DFU_FILES_FILTER -#define EXTERNAL_EEPROM_FILES_FILTER "EEPROM " CPN_STR_FILES " (*.bin *.hex);;" BIN_FILES_FILTER HEX_FILES_FILTER +#define CPN_STR_FILES QCoreApplication::translate("Companion", "files") +#define CPN_STR_RAD_MOD_SETTINGS QCoreApplication::translate("Companion", "Radio and Models settings") +#define HEX_FILES_FILTER "HEX " % CPN_STR_FILES % " (*.hex);;" +#define BIN_FILES_FILTER "BIN " % CPN_STR_FILES % " (*.bin);;" +#define DFU_FILES_FILTER "DFU " % CPN_STR_FILES % " (*.dfu);;" +#define EEPE_FILES_FILTER "EEPE " % CPN_STR_FILES % " (*.eepe);;" +#define OTX_FILES_FILTER "OpenTX " % CPN_STR_FILES % " (*.otx);;" +#define EEPROM_FILES_FILTER CPN_STR_RAD_MOD_SETTINGS % " " % CPN_STR_FILES % " (*.otx *.eepe *.bin *.hex);;" % OTX_FILES_FILTER % EEPE_FILES_FILTER % BIN_FILES_FILTER % HEX_FILES_FILTER +#define FLASH_FILES_FILTER "FLASH " % CPN_STR_FILES % " (*.bin *.hex *.dfu);;" % BIN_FILES_FILTER % HEX_FILES_FILTER % DFU_FILES_FILTER +#define EXTERNAL_EEPROM_FILES_FILTER "EEPROM " % CPN_STR_FILES % " (*.bin *.hex);;" % BIN_FILES_FILTER % HEX_FILES_FILTER #define ER9X_EEPROM_FILE_TYPE "ER9X_EEPROM_FILE" #define EEPE_EEPROM_FILE_HEADER "EEPE EEPROM FILE" #define EEPE_MODEL_FILE_HEADER "EEPE MODEL FILE" -#define CPN_STR_SW_INDICATOR_UP QT_TRANSLATE_NOOP("RawSwitch", "\xE2\x86\x91") // Switch up position indicator: Up arrow, or similar. -#define CPN_STR_SW_INDICATOR_DN QT_TRANSLATE_NOOP("RawSwitch", "\xE2\x86\x93") // Switch down position indicator: Down arrow, or similar. -#define CPN_STR_SW_INDICATOR_NEUT QT_TRANSLATE_NOOP("RawSwitch", "-") // Switch neutral (middle) position indicator. -#define CPN_STR_SW_INDICATOR_REV QT_TRANSLATE_NOOP("RawSwitch", "!") // Switch reversed logic (NOT) indicator. +#define CPN_STR_SW_INDICATOR_UP QCoreApplication::translate("RawSwitch", "\xE2\x86\x91") // Switch up position indicator: Up arrow, or similar. +#define CPN_STR_SW_INDICATOR_DN QCoreApplication::translate("RawSwitch", "\xE2\x86\x93") // Switch down position indicator: Down arrow, or similar. +#define CPN_STR_SW_INDICATOR_NEUT QCoreApplication::translate("RawSwitch", "-") // Switch neutral (middle) position indicator. +#define CPN_STR_SW_INDICATOR_REV QCoreApplication::translate("RawSwitch", "!") // Switch reversed logic (NOT) indicator. #endif // _CONSTANTS_H_ diff --git a/companion/src/flasheepromdialog.cpp b/companion/src/flasheepromdialog.cpp index 4621e9e9f..add1a697c 100644 --- a/companion/src/flasheepromdialog.cpp +++ b/companion/src/flasheepromdialog.cpp @@ -102,7 +102,7 @@ void FlashEEpromDialog::updateUI() void FlashEEpromDialog::on_eepromLoad_clicked() { - QString filename = QFileDialog::getOpenFileName(this, tr("Choose Radio Backup file"), g.eepromDir(), tr(EXTERNAL_EEPROM_FILES_FILTER)); + QString filename = QFileDialog::getOpenFileName(this, tr("Choose Radio Backup file"), g.eepromDir(), EXTERNAL_EEPROM_FILES_FILTER); if (!filename.isEmpty()) { eepromFilename = filename; updateUI(); diff --git a/companion/src/mainwindow.cpp b/companion/src/mainwindow.cpp index a046ee9e7..e363cc526 100644 --- a/companion/src/mainwindow.cpp +++ b/companion/src/mainwindow.cpp @@ -657,9 +657,7 @@ void MainWindow::openFile(const QString & fileName, bool updateLastUsedDir) void MainWindow::openFile() { - QString fileFilter; - fileFilter = tr(EEPROM_FILES_FILTER); - QString fileName = QFileDialog::getOpenFileName(this, tr("Open Models and Settings file"), g.eepromDir(), fileFilter); + QString fileName = QFileDialog::getOpenFileName(this, tr("Open Models and Settings file"), g.eepromDir(), EEPROM_FILES_FILTER); openFile(fileName); } @@ -861,7 +859,7 @@ void MainWindow::readBackup() return; // TODO implementation } - QString fileName = QFileDialog::getSaveFileName(this, tr("Save Radio Backup to File"), g.eepromDir(), tr(EXTERNAL_EEPROM_FILES_FILTER)); + QString fileName = QFileDialog::getSaveFileName(this, tr("Save Radio Backup to File"), g.eepromDir(), EXTERNAL_EEPROM_FILES_FILTER); if (!fileName.isEmpty()) { if (!readEepromFromRadio(fileName)) return; @@ -870,7 +868,7 @@ void MainWindow::readBackup() void MainWindow::readFlash() { - QString fileName = QFileDialog::getSaveFileName(this,tr("Read Radio Firmware to File"), g.flashDir(),tr(FLASH_FILES_FILTER)); + QString fileName = QFileDialog::getSaveFileName(this,tr("Read Radio Firmware to File"), g.flashDir(), FLASH_FILES_FILTER); if (!fileName.isEmpty()) { readFirmwareFromRadio(fileName); } diff --git a/companion/src/mdichild.cpp b/companion/src/mdichild.cpp index bddacd7ef..1440ffc8e 100644 --- a/companion/src/mdichild.cpp +++ b/companion/src/mdichild.cpp @@ -1480,7 +1480,7 @@ void MdiChild::writeEeprom() // write to Tx bool MdiChild::loadBackup() { - QString fileName = QFileDialog::getOpenFileName(this, tr("Open backup Models and Settings file"), g.eepromDir(), tr(EEPROM_FILES_FILTER)); + QString fileName = QFileDialog::getOpenFileName(this, tr("Open backup Models and Settings file"), g.eepromDir(), EEPROM_FILES_FILTER); if (fileName.isEmpty()) return false; QFile file(fileName); diff --git a/companion/src/simulation/simulateduiwidget9X.cpp b/companion/src/simulation/simulateduiwidget9X.cpp index daa809a20..398593cf6 100644 --- a/companion/src/simulation/simulateduiwidget9X.cpp +++ b/companion/src/simulation/simulateduiwidget9X.cpp @@ -38,40 +38,40 @@ SimulatedUIWidget9X::SimulatedUIWidget9X(SimulatorInterface * simulator, QWidget int x = 68, y = 91, oR = 63; polygon << QPoint(x, y) << polyArc(x, y, oR, -45, 45); - act = new RadioUiAction(3, QList() << Qt::Key_Up << Qt::Key_PageUp, tr(SIMU_STR_HLP_KEYS_GO_UP) % (hasRotEnc ? "" : tr("|" SIMU_STR_HLP_MOUSE_UP)), tr(SIMU_STR_HLP_ACT_UP)); + act = new RadioUiAction(3, QList() << Qt::Key_Up << Qt::Key_PageUp, SIMU_STR_HLP_KEYS_GO_UP % (hasRotEnc ? QString("") : "|" % SIMU_STR_HLP_MOUSE_UP), SIMU_STR_HLP_ACT_UP); addRadioWidget(ui->leftbuttons->addArea(polygon, "9X/9xcursup.png", act)); polygon.clear(); polygon << QPoint(x, y) << polyArc(x, y, oR, 135, 225); - act = new RadioUiAction(2, QList() << Qt::Key_Down << Qt::Key_PageDown, tr(SIMU_STR_HLP_KEYS_GO_DN) % (hasRotEnc ? "" : tr("|" SIMU_STR_HLP_MOUSE_DN)), tr(SIMU_STR_HLP_ACT_DN)); + act = new RadioUiAction(2, QList() << Qt::Key_Down << Qt::Key_PageDown, SIMU_STR_HLP_KEYS_GO_DN % (hasRotEnc ? QString("") : "|" % SIMU_STR_HLP_MOUSE_DN), SIMU_STR_HLP_ACT_DN); addRadioWidget(ui->leftbuttons->addArea(polygon, "9X/9xcursdown.png", act)); polygon.clear(); polygon << QPoint(x, y) << polyArc(x, y, oR, 45, 135); - act = new RadioUiAction(4, QList() << Qt::Key_Right << Qt::Key_Minus, tr(SIMU_STR_HLP_KEY_RGT "|" SIMU_STR_HLP_KEY_MIN), tr(SIMU_STR_HLP_ACT_MIN)); + act = new RadioUiAction(4, QList() << Qt::Key_Right << Qt::Key_Minus, SIMU_STR_HLP_KEY_RGT % "|" % SIMU_STR_HLP_KEY_MIN, SIMU_STR_HLP_ACT_MIN); addRadioWidget(ui->leftbuttons->addArea(polygon, "9X/9xcursmin.png", act)); polygon.clear(); polygon << QPoint(x, y) << polyArc(x, y, oR, 225, 315); - act = new RadioUiAction(5, QList() << Qt::Key_Left << Qt::Key_Plus << Qt::Key_Equal, tr(SIMU_STR_HLP_KEY_LFT "|" SIMU_STR_HLP_KEY_PLS), tr(SIMU_STR_HLP_ACT_PLS)); + act = new RadioUiAction(5, QList() << Qt::Key_Left << Qt::Key_Plus << Qt::Key_Equal, SIMU_STR_HLP_KEY_LFT % "|" % SIMU_STR_HLP_KEY_PLS, SIMU_STR_HLP_ACT_PLS); addRadioWidget(ui->leftbuttons->addArea(polygon, "9X/9xcursplus.png", act)); - act = new RadioUiAction(0, QList() << Qt::Key_Enter << Qt::Key_Return, tr(SIMU_STR_HLP_KEY_ENTER), tr(SIMU_STR_HLP_ACT_MENU)); + act = new RadioUiAction(0, QList() << Qt::Key_Enter << Qt::Key_Return, SIMU_STR_HLP_KEY_ENTER, SIMU_STR_HLP_ACT_MENU); addRadioWidget(ui->rightbuttons->addArea(QRect(16, 54, 60, 34), "9X/9xmenumenu.png", act)); if (!hasRotEnc) { m_mouseMidClickAction = act; - m_mouseMidClickAction->setText(act->getText() % "|" SIMU_STR_HLP_MOUSE_MID); + m_mouseMidClickAction->setText(act->getText() % "|" % SIMU_STR_HLP_MOUSE_MID); } - act = new RadioUiAction(1, QList() << Qt::Key_Delete << Qt::Key_Escape << Qt::Key_Backspace, tr(SIMU_STR_HLP_KEYS_EXIT), tr(SIMU_STR_HLP_ACT_EXIT)); + act = new RadioUiAction(1, QList() << Qt::Key_Delete << Qt::Key_Escape << Qt::Key_Backspace, SIMU_STR_HLP_KEYS_EXIT, SIMU_STR_HLP_ACT_EXIT); addRadioWidget(ui->rightbuttons->addArea(QRect(16, 114, 60, 34), "9X/9xmenuexit.png", act)); addRadioWidget(ui->leftbuttons->addArea(QRect(6, 149, 30, 30), "9X/9xcursphoto.png", m_screenshotAction)); if (hasRotEnc) { - addRadioAction(new RadioUiAction(-1, 0, tr(SIMU_STR_HLP_MOUSE_SCRL), tr(SIMU_STR_HLP_ROTENC " " SIMU_STR_HLP_ROTENC_LR))); - m_mouseMidClickAction = new RadioUiAction(14, Qt::Key_Insert, tr(SIMU_STR_HLP_KEY_INS "|" SIMU_STR_HLP_MOUSE_MID), tr(SIMU_STR_HLP_ACT_ROT_DN)); + addRadioAction(new RadioUiAction(-1, 0, SIMU_STR_HLP_MOUSE_SCRL, SIMU_STR_HLP_ROTENC % "|" % SIMU_STR_HLP_ROTENC_LR)); + m_mouseMidClickAction = new RadioUiAction(14, Qt::Key_Insert, SIMU_STR_HLP_KEY_INS % "|" % SIMU_STR_HLP_MOUSE_MID, SIMU_STR_HLP_ACT_ROT_DN); addRadioWidget(ui->leftbuttons->addArea(QRect(0, 0, 0, 0), "9X/9xcurs.png", m_mouseMidClickAction)); } diff --git a/companion/src/simulation/simulateduiwidgetX12.cpp b/companion/src/simulation/simulateduiwidgetX12.cpp index 6b58fd962..6511e4393 100644 --- a/companion/src/simulation/simulateduiwidgetX12.cpp +++ b/companion/src/simulation/simulateduiwidgetX12.cpp @@ -35,40 +35,40 @@ SimulatedUIWidgetX12::SimulatedUIWidgetX12(SimulatorInterface *simulator, QWidge int x = 74, y = 190, oR = 63, iR = 40; polygon << polyArc(x, y, oR, 225, 315) << polyArc(x, y, iR, 225, 315); - act = new RadioUiAction(0, QList() << Qt::Key_PageUp, tr(SIMU_STR_HLP_KEY_PGUP), tr(SIMU_STR_HLP_ACT_PGUP)); + act = new RadioUiAction(0, QList() << Qt::Key_PageUp, SIMU_STR_HLP_KEY_PGUP, SIMU_STR_HLP_ACT_PGUP); addRadioWidget(ui->leftbuttons->addArea(polygon, "Horus/left_btn1.png", act)); polygon.clear(); polygon << polyArc(x, y, oR, 135, 225) << polyArc(x, y, iR, 135, 225); - act = new RadioUiAction(1, QList() << Qt::Key_PageDown, tr(SIMU_STR_HLP_KEY_PGDN), tr(SIMU_STR_HLP_ACT_PGDN)); + act = new RadioUiAction(1, QList() << Qt::Key_PageDown, SIMU_STR_HLP_KEY_PGDN, SIMU_STR_HLP_ACT_PGDN); addRadioWidget(ui->leftbuttons->addArea(polygon, "Horus/left_btn2.png", act)); polygon.clear(); polygon << polyArc(x, y, oR, -45, 45) << polyArc(x, y, iR, -45, 45); - act = new RadioUiAction(3, QList() << Qt::Key_Up, tr(SIMU_STR_HLP_KEY_UP), tr(SIMU_STR_HLP_ACT_MDL)); + act = new RadioUiAction(3, QList() << Qt::Key_Up, SIMU_STR_HLP_KEY_UP, SIMU_STR_HLP_ACT_MDL); addRadioWidget(ui->rightbuttons->addArea(polygon, "Horus/right_btnU.png", act)); polygon.clear(); polygon << polyArc(x, y, oR, 225, 315) << polyArc(x, y, iR, 225, 315); - act = new RadioUiAction(6, QList() << Qt::Key_Left, tr(SIMU_STR_HLP_KEY_LFT), tr(SIMU_STR_HLP_ACT_SYS)); + act = new RadioUiAction(6, QList() << Qt::Key_Left, SIMU_STR_HLP_KEY_LFT, SIMU_STR_HLP_ACT_SYS); addRadioWidget(ui->rightbuttons->addArea(polygon, "Horus/right_btnL.png", act)); polygon.clear(); polygon << polyArc(x, y, oR, 45, 135) << polyArc(x, y, iR, 45, 135); - act = new RadioUiAction(5, QList() << Qt::Key_Right, tr(SIMU_STR_HLP_KEY_RGT), tr(SIMU_STR_HLP_ACT_TELE)); + act = new RadioUiAction(5, QList() << Qt::Key_Right, SIMU_STR_HLP_KEY_RGT, SIMU_STR_HLP_ACT_TELE); addRadioWidget(ui->rightbuttons->addArea(polygon, "Horus/right_btnR.png", act)); polygon.clear(); polygon << polyArc(x, y, oR, 135, 225) << polyArc(x, y, iR, 135, 225); act = new RadioUiAction(4, QList() << Qt::Key_Down << Qt::Key_Delete << Qt::Key_Escape << Qt::Key_Backspace, - tr(SIMU_STR_HLP_KEY_DN "
" SIMU_STR_HLP_KEYS_EXIT), tr(SIMU_STR_HLP_ACT_RTN)); + SIMU_STR_HLP_KEY_DN % "
" % SIMU_STR_HLP_KEYS_EXIT, SIMU_STR_HLP_ACT_RTN); addRadioWidget(ui->rightbuttons->addArea(polygon, "Horus/right_btnD.png", act)); - m_scrollUpAction = new RadioUiAction(-1, QList() << Qt::Key_Minus, tr(SIMU_STR_HLP_KEY_MIN "|" SIMU_STR_HLP_MOUSE_UP), tr(SIMU_STR_HLP_ACT_ROT_LFT)); - m_scrollDnAction = new RadioUiAction(-1, QList() << Qt::Key_Plus << Qt::Key_Equal, tr(SIMU_STR_HLP_KEY_PLS "|" SIMU_STR_HLP_MOUSE_DN), tr(SIMU_STR_HLP_ACT_ROT_RGT)); + m_scrollUpAction = new RadioUiAction(-1, QList() << Qt::Key_Minus, SIMU_STR_HLP_KEY_MIN % "|" % SIMU_STR_HLP_MOUSE_UP, SIMU_STR_HLP_ACT_ROT_LFT); + m_scrollDnAction = new RadioUiAction(-1, QList() << Qt::Key_Plus << Qt::Key_Equal, SIMU_STR_HLP_KEY_PLS % "|" % SIMU_STR_HLP_MOUSE_DN, SIMU_STR_HLP_ACT_ROT_RGT); connectScrollActions(); - m_mouseMidClickAction = new RadioUiAction(2, QList() << Qt::Key_Enter << Qt::Key_Return, tr(SIMU_STR_HLP_KEYS_ACTIVATE), tr(SIMU_STR_HLP_ACT_ROT_DN)); + m_mouseMidClickAction = new RadioUiAction(2, QList() << Qt::Key_Enter << Qt::Key_Return, SIMU_STR_HLP_KEYS_ACTIVATE, SIMU_STR_HLP_ACT_ROT_DN); addRadioWidget(ui->rightbuttons->addArea(polyArc(x, y, iR), "Horus/right_ent.png", m_mouseMidClickAction)); addRadioWidget(ui->leftbuttons->addArea(QRect(9, 259, 30, 30), "Horus/left_scrnsht.png", m_screenshotAction)); diff --git a/companion/src/simulation/simulateduiwidgetX7.cpp b/companion/src/simulation/simulateduiwidgetX7.cpp index 0da8dc89e..ee37a0621 100644 --- a/companion/src/simulation/simulateduiwidgetX7.cpp +++ b/companion/src/simulation/simulateduiwidgetX7.cpp @@ -14,22 +14,22 @@ SimulatedUIWidgetX7::SimulatedUIWidgetX7(SimulatorInterface *simulator, QWidget QPoint ctr(70, 91); polygon << polyArc(ctr.x(), ctr.y(), 50, -90, 90) << polyArc(ctr.x(), ctr.y(), 22, -90, 90); - act = new RadioUiAction(3, QList() << Qt::Key_PageUp << Qt::Key_Up, tr(SIMU_STR_HLP_KEYS_GO_UP), tr(SIMU_STR_HLP_ACT_PAGE)); + act = new RadioUiAction(3, QList() << Qt::Key_PageUp << Qt::Key_Up, SIMU_STR_HLP_KEYS_GO_UP, SIMU_STR_HLP_ACT_PAGE); addRadioWidget(ui->leftbuttons->addArea(polygon, "X7/left_page.png", act)); - act = new RadioUiAction(0, QList() << Qt::Key_PageDown << Qt::Key_Down, tr(SIMU_STR_HLP_KEYS_GO_DN), tr(SIMU_STR_HLP_ACT_MENU_ICN)); + act = new RadioUiAction(0, QList() << Qt::Key_PageDown << Qt::Key_Down, SIMU_STR_HLP_KEYS_GO_DN, SIMU_STR_HLP_ACT_MENU_ICN); addRadioWidget(ui->leftbuttons->addArea(polyArc(ctr.x(), ctr.y(), 20), "X7/left_menu.png", act)); polygon.clear(); polygon << polyArc(ctr.x(), ctr.y(), 50, 90, 270) << polyArc(ctr.x(), ctr.y(), 22, 90, 270); - act = new RadioUiAction(1, QList() << Qt::Key_Delete << Qt::Key_Escape << Qt::Key_Backspace, tr(SIMU_STR_HLP_KEYS_EXIT), tr(SIMU_STR_HLP_ACT_EXIT)); + act = new RadioUiAction(1, QList() << Qt::Key_Delete << Qt::Key_Escape << Qt::Key_Backspace, SIMU_STR_HLP_KEYS_EXIT, SIMU_STR_HLP_ACT_EXIT); addRadioWidget(ui->leftbuttons->addArea(polygon, "X7/left_exit.png", act)); - m_scrollUpAction = new RadioUiAction(-1, QList() << Qt::Key_Minus << Qt::Key_Equal << Qt::Key_Left, tr(SIMU_STR_HLP_KEYS_GO_LFT), tr(SIMU_STR_HLP_ACT_ROT_LFT)); - m_scrollDnAction = new RadioUiAction(-1, QList() << Qt::Key_Plus << Qt::Key_Right, tr(SIMU_STR_HLP_KEYS_GO_RGT), tr(SIMU_STR_HLP_ACT_ROT_RGT)); + m_scrollUpAction = new RadioUiAction(-1, QList() << Qt::Key_Minus << Qt::Key_Equal << Qt::Key_Left, SIMU_STR_HLP_KEYS_GO_LFT, SIMU_STR_HLP_ACT_ROT_LFT); + m_scrollDnAction = new RadioUiAction(-1, QList() << Qt::Key_Plus << Qt::Key_Right, SIMU_STR_HLP_KEYS_GO_RGT, SIMU_STR_HLP_ACT_ROT_RGT); connectScrollActions(); - m_mouseMidClickAction = new RadioUiAction(2, QList() << Qt::Key_Enter << Qt::Key_Return, tr(SIMU_STR_HLP_KEYS_ACTIVATE), tr(SIMU_STR_HLP_ACT_ROT_DN)); + m_mouseMidClickAction = new RadioUiAction(2, QList() << Qt::Key_Enter << Qt::Key_Return, SIMU_STR_HLP_KEYS_ACTIVATE, SIMU_STR_HLP_ACT_ROT_DN); addRadioWidget(ui->rightbuttons->addArea(polyArc(88, 92, 33), "X7/right_ent.png", m_mouseMidClickAction)); addRadioWidget(ui->leftbuttons->addArea(QRect(9, 154, 30, 30), "X7/left_scrnshot.png", m_screenshotAction)); diff --git a/companion/src/simulation/simulateduiwidgetX9.cpp b/companion/src/simulation/simulateduiwidgetX9.cpp index 0e3e3948c..b274089bd 100644 --- a/companion/src/simulation/simulateduiwidgetX9.cpp +++ b/companion/src/simulation/simulateduiwidgetX9.cpp @@ -37,21 +37,21 @@ SimulatedUIWidgetX9::SimulatedUIWidgetX9(SimulatorInterface *simulator, QWidget // left side - act = new RadioUiAction(0, QList() << Qt::Key_Up << Qt::Key_PageUp, tr(SIMU_STR_HLP_KEYS_GO_UP), tr(SIMU_STR_HLP_ACT_MENU)); + act = new RadioUiAction(0, QList() << Qt::Key_Up << Qt::Key_PageUp, SIMU_STR_HLP_KEYS_GO_UP, SIMU_STR_HLP_ACT_MENU); addRadioWidget(ui->leftbuttons->addArea(btn, "Taranis/x9l1.png", act)); btn.moveTop(btn.top() + btn.height() + vsp); - act = new RadioUiAction(3, QList() << Qt::Key_Down << Qt::Key_PageDown, tr(SIMU_STR_HLP_KEYS_GO_DN), tr(SIMU_STR_HLP_ACT_PAGE)); + act = new RadioUiAction(3, QList() << Qt::Key_Down << Qt::Key_PageDown, SIMU_STR_HLP_KEYS_GO_DN, SIMU_STR_HLP_ACT_PAGE); addRadioWidget(ui->leftbuttons->addArea(btn, "Taranis/x9l2.png", act)); btn.moveTop(btn.top() + btn.height() + vsp); - act = new RadioUiAction(1, QList() << Qt::Key_Delete << Qt::Key_Escape << Qt::Key_Backspace, tr(SIMU_STR_HLP_KEYS_EXIT), tr(SIMU_STR_HLP_ACT_EXIT)); + act = new RadioUiAction(1, QList() << Qt::Key_Delete << Qt::Key_Escape << Qt::Key_Backspace, SIMU_STR_HLP_KEYS_EXIT, SIMU_STR_HLP_ACT_EXIT); addRadioWidget(ui->leftbuttons->addArea(btn, "Taranis/x9l3.png", act)); m_scrollUpAction = new RadioUiAction(4, QList() << Qt::Key_Plus << Qt::Key_Equal << Qt::Key_Left, - tr(SIMU_STR_HLP_KEY_LFT "|" SIMU_STR_HLP_KEY_PLS "|" SIMU_STR_HLP_MOUSE_UP), tr(SIMU_STR_HLP_ACT_PLS)); + SIMU_STR_HLP_KEY_LFT % "|" % SIMU_STR_HLP_KEY_PLS % "|" % SIMU_STR_HLP_MOUSE_UP, SIMU_STR_HLP_ACT_PLS); m_scrollDnAction = new RadioUiAction(5, QList() << Qt::Key_Minus << Qt::Key_Right, - tr(SIMU_STR_HLP_KEY_RGT "|" SIMU_STR_HLP_KEY_MIN "|" SIMU_STR_HLP_MOUSE_DN), tr(SIMU_STR_HLP_ACT_MIN)); + SIMU_STR_HLP_KEY_RGT % "|" % SIMU_STR_HLP_KEY_MIN % "|" % SIMU_STR_HLP_MOUSE_DN, SIMU_STR_HLP_ACT_MIN); // right side btn.moveTopLeft(QPoint(58, btop)); @@ -62,7 +62,7 @@ SimulatedUIWidgetX9::SimulatedUIWidgetX9(SimulatorInterface *simulator, QWidget addRadioWidget(ui->rightbuttons->addArea(btn, "Taranis/x9r2.png", m_scrollDnAction)); btn.moveTop(btn.top() + btn.height() + vsp); - m_mouseMidClickAction = new RadioUiAction(2, QList() << Qt::Key_Enter << Qt::Key_Return, tr(SIMU_STR_HLP_KEYS_ACTIVATE), tr(SIMU_STR_HLP_ACT_ENT)); + m_mouseMidClickAction = new RadioUiAction(2, QList() << Qt::Key_Enter << Qt::Key_Return, SIMU_STR_HLP_KEYS_ACTIVATE, SIMU_STR_HLP_ACT_ENT); addRadioWidget(ui->rightbuttons->addArea(btn, "Taranis/x9r3.png", m_mouseMidClickAction)); addRadioWidget(ui->leftbuttons->addArea(QRect(89, 177, 30, 20), "Taranis/x9l4.png", m_screenshotAction)); diff --git a/companion/src/simulation/simulateduiwidgetX9E.cpp b/companion/src/simulation/simulateduiwidgetX9E.cpp index 58d307d3d..2c0d6adfa 100644 --- a/companion/src/simulation/simulateduiwidgetX9E.cpp +++ b/companion/src/simulation/simulateduiwidgetX9E.cpp @@ -35,24 +35,24 @@ SimulatedUIWidgetX9E::SimulatedUIWidgetX9E(SimulatorInterface *simulator, QWidge QPoint ctr(70, 100); polygon << polyArc(ctr.x(), ctr.y(), 60, -90, 0) << ctr; - act = new RadioUiAction(0, QList() << Qt::Key_Up << Qt::Key_PageUp, tr(SIMU_STR_HLP_KEYS_GO_UP), tr(SIMU_STR_HLP_ACT_MENU)); + act = new RadioUiAction(0, QList() << Qt::Key_Up << Qt::Key_PageUp, SIMU_STR_HLP_KEYS_GO_UP, SIMU_STR_HLP_ACT_MENU); addRadioWidget(ui->leftbuttons->addArea(polygon, "X9E/left_menu.png", act)); polygon.clear(); polygon << polyArc(ctr.x(), ctr.y(), 45, 0, 180); - act = new RadioUiAction(3, QList() << Qt::Key_Down << Qt::Key_PageDown, tr(SIMU_STR_HLP_KEYS_GO_DN), tr(SIMU_STR_HLP_ACT_PAGE)); + act = new RadioUiAction(3, QList() << Qt::Key_Down << Qt::Key_PageDown, SIMU_STR_HLP_KEYS_GO_DN, SIMU_STR_HLP_ACT_PAGE); addRadioWidget(ui->leftbuttons->addArea(polygon, "X9E/left_page.png", act)); polygon.clear(); polygon << polyArc(ctr.x(), ctr.y(), 60, 180, 270) << ctr; - act = new RadioUiAction(1, QList() << Qt::Key_Delete << Qt::Key_Escape << Qt::Key_Backspace, tr(SIMU_STR_HLP_KEYS_EXIT), tr(SIMU_STR_HLP_ACT_EXIT)); + act = new RadioUiAction(1, QList() << Qt::Key_Delete << Qt::Key_Escape << Qt::Key_Backspace, SIMU_STR_HLP_KEYS_EXIT, SIMU_STR_HLP_ACT_EXIT); addRadioWidget(ui->leftbuttons->addArea(polygon, "X9E/left_exit.png", act)); - m_scrollUpAction = addRadioAction(new RadioUiAction(-1, QList() << Qt::Key_Minus << Qt::Key_Left, tr(SIMU_STR_HLP_KEYS_GO_LFT), tr(SIMU_STR_HLP_ACT_ROT_LFT))); - m_scrollDnAction = addRadioAction(new RadioUiAction(-1, QList() << Qt::Key_Plus << Qt::Key_Equal << Qt::Key_Right, tr(SIMU_STR_HLP_KEYS_GO_RGT), tr(SIMU_STR_HLP_ACT_ROT_RGT))); + m_scrollUpAction = addRadioAction(new RadioUiAction(-1, QList() << Qt::Key_Minus << Qt::Key_Left, SIMU_STR_HLP_KEYS_GO_LFT, SIMU_STR_HLP_ACT_ROT_LFT)); + m_scrollDnAction = addRadioAction(new RadioUiAction(-1, QList() << Qt::Key_Plus << Qt::Key_Equal << Qt::Key_Right, SIMU_STR_HLP_KEYS_GO_RGT, SIMU_STR_HLP_ACT_ROT_RGT)); connectScrollActions(); - m_mouseMidClickAction = new RadioUiAction(2, QList() << Qt::Key_Enter << Qt::Key_Return, tr(SIMU_STR_HLP_KEYS_ACTIVATE), tr(SIMU_STR_HLP_ACT_ROT_DN)); + m_mouseMidClickAction = new RadioUiAction(2, QList() << Qt::Key_Enter << Qt::Key_Return, SIMU_STR_HLP_KEYS_ACTIVATE, SIMU_STR_HLP_ACT_ROT_DN); addRadioWidget(ui->rightbuttons->addArea(polyArc(90, 100, 50), "X9E/right_enter.png", m_mouseMidClickAction)); addRadioWidget(ui->leftbuttons->addArea(QRect(10, 170, 30, 30), "X9E/left_scrnshot.png", m_screenshotAction)); diff --git a/companion/src/simulation/simulator_strings.h b/companion/src/simulation/simulator_strings.h index 4a6982d77..795901048 100644 --- a/companion/src/simulation/simulator_strings.h +++ b/companion/src/simulation/simulator_strings.h @@ -1,66 +1,66 @@ #ifndef SIMULATOR_STRINGS_H #define SIMULATOR_STRINGS_H -#include +#include -#define SIMU_STR_HLP_KEY_ENTER QT_TRANSLATE_NOOP("SimulatedUIWidget", "ENTER") -#define SIMU_STR_HLP_KEY_PGUP QT_TRANSLATE_NOOP("SimulatedUIWidget", "PG-UP") -#define SIMU_STR_HLP_KEY_PGDN QT_TRANSLATE_NOOP("SimulatedUIWidget", "PG-DN") -#define SIMU_STR_HLP_KEY_DEL QT_TRANSLATE_NOOP("SimulatedUIWidget", "DEL") -#define SIMU_STR_HLP_KEY_BKSP QT_TRANSLATE_NOOP("SimulatedUIWidget", "BKSP") -#define SIMU_STR_HLP_KEY_ESC QT_TRANSLATE_NOOP("SimulatedUIWidget", "ESC") -#define SIMU_STR_HLP_KEY_INS QT_TRANSLATE_NOOP("SimulatedUIWidget", "INS") -#define SIMU_STR_HLP_KEY_PLS QT_TRANSLATE_NOOP("SimulatedUIWidget", "+") -#define SIMU_STR_HLP_KEY_MIN QT_TRANSLATE_NOOP("SimulatedUIWidget", "-") +#define SIMU_STR_HLP_KEY_ENTER QCoreApplication::translate("SimulatedUIWidget", "ENTER") +#define SIMU_STR_HLP_KEY_PGUP QCoreApplication::translate("SimulatedUIWidget", "PG-UP") +#define SIMU_STR_HLP_KEY_PGDN QCoreApplication::translate("SimulatedUIWidget", "PG-DN") +#define SIMU_STR_HLP_KEY_DEL QCoreApplication::translate("SimulatedUIWidget", "DEL") +#define SIMU_STR_HLP_KEY_BKSP QCoreApplication::translate("SimulatedUIWidget", "BKSP") +#define SIMU_STR_HLP_KEY_ESC QCoreApplication::translate("SimulatedUIWidget", "ESC") +#define SIMU_STR_HLP_KEY_INS QCoreApplication::translate("SimulatedUIWidget", "INS") +#define SIMU_STR_HLP_KEY_PLS QCoreApplication::translate("SimulatedUIWidget", "+") +#define SIMU_STR_HLP_KEY_MIN QCoreApplication::translate("SimulatedUIWidget", "-") -#define SIMU_STR_HLP_KEY_LFT QT_TRANSLATE_NOOP("SimulatedUIWidget", "←") // ← -#define SIMU_STR_HLP_KEY_RGT QT_TRANSLATE_NOOP("SimulatedUIWidget", "→") // → -#define SIMU_STR_HLP_KEY_UP QT_TRANSLATE_NOOP("SimulatedUIWidget", "↑") // ↑ -#define SIMU_STR_HLP_KEY_DN QT_TRANSLATE_NOOP("SimulatedUIWidget", "↓") // ↓ +#define SIMU_STR_HLP_KEY_LFT QCoreApplication::translate("SimulatedUIWidget", "←") // ← +#define SIMU_STR_HLP_KEY_RGT QCoreApplication::translate("SimulatedUIWidget", "→") // → +#define SIMU_STR_HLP_KEY_UP QCoreApplication::translate("SimulatedUIWidget", "↑") // ↑ +#define SIMU_STR_HLP_KEY_DN QCoreApplication::translate("SimulatedUIWidget", "↓") // ↓ -#define SIMU_STR_HLP_ROTENC QT_TRANSLATE_NOOP("SimulatedUIWidget", "⚆") // ⚆ -#define SIMU_STR_HLP_ROTENC_LFT QT_TRANSLATE_NOOP("SimulatedUIWidget", "↶") // ↶ -#define SIMU_STR_HLP_ROTENC_RGT QT_TRANSLATE_NOOP("SimulatedUIWidget", "↷") // ↷ -#define SIMU_STR_HLP_ROTENC_LR QT_TRANSLATE_NOOP("SimulatedUIWidget", "⇆") // ⇆ -#define SIMU_STR_HLP_ROTENC_DN QT_TRANSLATE_NOOP("SimulatedUIWidget", "⇓") // ⇓ +#define SIMU_STR_HLP_ROTENC QCoreApplication::translate("SimulatedUIWidget", "⚆") // ⚆ +#define SIMU_STR_HLP_ROTENC_LFT QCoreApplication::translate("SimulatedUIWidget", "↶") // ↶ +#define SIMU_STR_HLP_ROTENC_RGT QCoreApplication::translate("SimulatedUIWidget", "↷") // ↷ +#define SIMU_STR_HLP_ROTENC_LR QCoreApplication::translate("SimulatedUIWidget", "⇆") // ⇆ +#define SIMU_STR_HLP_ROTENC_DN QCoreApplication::translate("SimulatedUIWidget", "⇓") // ⇓ -#define SIMU_STR_HLP_SCRL_UP QT_TRANSLATE_NOOP("SimulatedUIWidget", "⇑") // ⇑ -#define SIMU_STR_HLP_SCRL_DN QT_TRANSLATE_NOOP("SimulatedUIWidget", "⇓") // ⇓ -#define SIMU_STR_HLP_SCRL_UD QT_TRANSLATE_NOOP("SimulatedUIWidget", "⇕") // ⇕ +#define SIMU_STR_HLP_SCRL_UP QCoreApplication::translate("SimulatedUIWidget", "⇑") // ⇑ +#define SIMU_STR_HLP_SCRL_DN QCoreApplication::translate("SimulatedUIWidget", "⇓") // ⇓ +#define SIMU_STR_HLP_SCRL_UD QCoreApplication::translate("SimulatedUIWidget", "⇕") // ⇕ -#define SIMU_STR_HLP_MOUSE QT_TRANSLATE_NOOP("SimulatedUIWidget", "") -#define SIMU_STR_HLP_CLICK QT_TRANSLATE_NOOP("SimulatedUIWidget", "") -#define SIMU_STR_HLP_MOUSE_MID SIMU_STR_HLP_MOUSE SIMU_STR_HLP_CLICK -#define SIMU_STR_HLP_MOUSE_UP SIMU_STR_HLP_MOUSE SIMU_STR_HLP_SCRL_UP -#define SIMU_STR_HLP_MOUSE_DN SIMU_STR_HLP_MOUSE SIMU_STR_HLP_SCRL_DN -#define SIMU_STR_HLP_MOUSE_SCRL SIMU_STR_HLP_MOUSE SIMU_STR_HLP_SCRL_UD +#define SIMU_STR_HLP_MOUSE QCoreApplication::translate("SimulatedUIWidget", "") +#define SIMU_STR_HLP_CLICK QCoreApplication::translate("SimulatedUIWidget", "") +#define SIMU_STR_HLP_MOUSE_MID SIMU_STR_HLP_MOUSE % SIMU_STR_HLP_CLICK +#define SIMU_STR_HLP_MOUSE_UP SIMU_STR_HLP_MOUSE % SIMU_STR_HLP_SCRL_UP +#define SIMU_STR_HLP_MOUSE_DN SIMU_STR_HLP_MOUSE % SIMU_STR_HLP_SCRL_DN +#define SIMU_STR_HLP_MOUSE_SCRL SIMU_STR_HLP_MOUSE % SIMU_STR_HLP_SCRL_UD -#define SIMU_STR_HLP_ACT_MENU QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ MENU ]
") -#define SIMU_STR_HLP_ACT_PAGE QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ PAGE ]
") -#define SIMU_STR_HLP_ACT_EXIT QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ EXIT ]
") -#define SIMU_STR_HLP_ACT_ENT QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ ENT ]
") -#define SIMU_STR_HLP_ACT_UP QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ UP ]
") -#define SIMU_STR_HLP_ACT_DN QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ DN ]
") -#define SIMU_STR_HLP_ACT_PLS QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ + ]
") -#define SIMU_STR_HLP_ACT_MIN QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ - ]
") -#define SIMU_STR_HLP_ACT_PGUP QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ PgUp ]
") -#define SIMU_STR_HLP_ACT_PGDN QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ PgDn ]
") -#define SIMU_STR_HLP_ACT_MDL QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ MDL ]
") -#define SIMU_STR_HLP_ACT_RTN QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ RTN ]
") -#define SIMU_STR_HLP_ACT_SYS QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ SYS ]
") -#define SIMU_STR_HLP_ACT_TELE QT_TRANSLATE_NOOP("SimulatedUIWidget", "
[ TELE ]
") -#define SIMU_STR_HLP_ACT_MENU_ICN QT_TRANSLATE_NOOP("SimulatedUIWidget", "≡") // ≡ +#define SIMU_STR_HLP_ACT_MENU QCoreApplication::translate("SimulatedUIWidget", "
[ MENU ]
") +#define SIMU_STR_HLP_ACT_PAGE QCoreApplication::translate("SimulatedUIWidget", "
[ PAGE ]
") +#define SIMU_STR_HLP_ACT_EXIT QCoreApplication::translate("SimulatedUIWidget", "
[ EXIT ]
") +#define SIMU_STR_HLP_ACT_ENT QCoreApplication::translate("SimulatedUIWidget", "
[ ENT ]
") +#define SIMU_STR_HLP_ACT_UP QCoreApplication::translate("SimulatedUIWidget", "
[ UP ]
") +#define SIMU_STR_HLP_ACT_DN QCoreApplication::translate("SimulatedUIWidget", "
[ DN ]
") +#define SIMU_STR_HLP_ACT_PLS QCoreApplication::translate("SimulatedUIWidget", "
[ + ]
") +#define SIMU_STR_HLP_ACT_MIN QCoreApplication::translate("SimulatedUIWidget", "
[ - ]
") +#define SIMU_STR_HLP_ACT_PGUP QCoreApplication::translate("SimulatedUIWidget", "
[ PgUp ]
") +#define SIMU_STR_HLP_ACT_PGDN QCoreApplication::translate("SimulatedUIWidget", "
[ PgDn ]
") +#define SIMU_STR_HLP_ACT_MDL QCoreApplication::translate("SimulatedUIWidget", "
[ MDL ]
") +#define SIMU_STR_HLP_ACT_RTN QCoreApplication::translate("SimulatedUIWidget", "
[ RTN ]
") +#define SIMU_STR_HLP_ACT_SYS QCoreApplication::translate("SimulatedUIWidget", "
[ SYS ]
") +#define SIMU_STR_HLP_ACT_TELE QCoreApplication::translate("SimulatedUIWidget", "
[ TELE ]
") +#define SIMU_STR_HLP_ACT_MENU_ICN QCoreApplication::translate("SimulatedUIWidget", "≡") // ≡ -#define SIMU_STR_HLP_KEYS_EXIT SIMU_STR_HLP_KEY_DEL "|" SIMU_STR_HLP_KEY_BKSP "|" SIMU_STR_HLP_KEY_ESC -#define SIMU_STR_HLP_KEYS_ACTIVATE SIMU_STR_HLP_KEY_ENTER "|" SIMU_STR_HLP_MOUSE_MID -#define SIMU_STR_HLP_KEYS_GO_UP SIMU_STR_HLP_KEY_UP "|" SIMU_STR_HLP_KEY_PGUP -#define SIMU_STR_HLP_KEYS_GO_DN SIMU_STR_HLP_KEY_DN "|" SIMU_STR_HLP_KEY_PGDN -#define SIMU_STR_HLP_KEYS_GO_LFT SIMU_STR_HLP_KEY_LFT "|" SIMU_STR_HLP_KEY_MIN "|" SIMU_STR_HLP_MOUSE_UP -#define SIMU_STR_HLP_KEYS_GO_RGT SIMU_STR_HLP_KEY_RGT "|" SIMU_STR_HLP_KEY_PLS "|" SIMU_STR_HLP_MOUSE_DN +#define SIMU_STR_HLP_KEYS_EXIT SIMU_STR_HLP_KEY_DEL % "|" % SIMU_STR_HLP_KEY_BKSP % "|" % SIMU_STR_HLP_KEY_ESC +#define SIMU_STR_HLP_KEYS_ACTIVATE SIMU_STR_HLP_KEY_ENTER % "|" % SIMU_STR_HLP_MOUSE_MID +#define SIMU_STR_HLP_KEYS_GO_UP SIMU_STR_HLP_KEY_UP % "|" % SIMU_STR_HLP_KEY_PGUP +#define SIMU_STR_HLP_KEYS_GO_DN SIMU_STR_HLP_KEY_DN % "|" % SIMU_STR_HLP_KEY_PGDN +#define SIMU_STR_HLP_KEYS_GO_LFT SIMU_STR_HLP_KEY_LFT % "|" % SIMU_STR_HLP_KEY_MIN % "|" % SIMU_STR_HLP_MOUSE_UP +#define SIMU_STR_HLP_KEYS_GO_RGT SIMU_STR_HLP_KEY_RGT % "|" % SIMU_STR_HLP_KEY_PLS % "|" % SIMU_STR_HLP_MOUSE_DN -#define SIMU_STR_HLP_ACT_ROT_LFT SIMU_STR_HLP_ROTENC " " SIMU_STR_HLP_ROTENC_LFT -#define SIMU_STR_HLP_ACT_ROT_RGT SIMU_STR_HLP_ROTENC " " SIMU_STR_HLP_ROTENC_RGT -#define SIMU_STR_HLP_ACT_ROT_DN SIMU_STR_HLP_ROTENC " " SIMU_STR_HLP_ROTENC_DN +#define SIMU_STR_HLP_ACT_ROT_LFT SIMU_STR_HLP_ROTENC % " " % SIMU_STR_HLP_ROTENC_LFT +#define SIMU_STR_HLP_ACT_ROT_RGT SIMU_STR_HLP_ROTENC % " " % SIMU_STR_HLP_ROTENC_RGT +#define SIMU_STR_HLP_ACT_ROT_DN SIMU_STR_HLP_ROTENC % " " % SIMU_STR_HLP_ROTENC_DN #endif // SIMULATOR_STRINGS_H diff --git a/companion/src/simulation/simulatorstartupdialog.cpp b/companion/src/simulation/simulatorstartupdialog.cpp index be67d7a90..c87da3399 100644 --- a/companion/src/simulation/simulatorstartupdialog.cpp +++ b/companion/src/simulation/simulatorstartupdialog.cpp @@ -227,7 +227,7 @@ void SimulatorStartupDialog::onRadioTypeChanged(int index) void SimulatorStartupDialog::onDataFileSelect(bool) { - QString filter = tr(EEPROM_FILES_FILTER) + tr("All files (*.*)"); + QString filter = EEPROM_FILES_FILTER % tr("All files (*.*)"); QString file = QFileDialog::getSaveFileName(this, QObject::tr("Select a data file"), ui->dataFile->text(), filter, NULL, QFileDialog::DontConfirmOverwrite); if (!file.isEmpty()) { From efe53eb0340c412aaa0e5f3fc54dd61abf670d3c Mon Sep 17 00:00:00 2001 From: 3djc Date: Sat, 6 May 2017 18:08:28 +0200 Subject: [PATCH 198/203] Fix translation for audio files (#4889) Switch the time mechanic to english one (may not be perfect, but current italian is not working at all) --- radio/src/translations/tts_it.cpp | 63 ++++++++----------------------- radio/util/tts_it.py | 6 +-- 2 files changed, 19 insertions(+), 50 deletions(-) diff --git a/radio/src/translations/tts_it.cpp b/radio/src/translations/tts_it.cpp index ecac135af..33a417be3 100644 --- a/radio/src/translations/tts_it.cpp +++ b/radio/src/translations/tts_it.cpp @@ -179,63 +179,32 @@ I18N_PLAY_FUNCTION(it, playNumber, getvalue_t number, uint8_t unit, uint8_t att) I18N_PLAY_FUNCTION(it, playDuration, int seconds PLAY_DURATION_ATT) { + if (seconds == 0) { + PLAY_NUMBER(seconds, 0, 0); + return; + } + if (seconds < 0) { PUSH_NUMBER_PROMPT(IT_PROMPT_MENO); seconds = -seconds; } - uint8_t ore = 0; uint8_t tmp = seconds / 3600; seconds %= 3600; + if (tmp > 0 || IS_PLAY_TIME()) { + PLAY_NUMBER(tmp, UNIT_HOURS, 0); + } + + tmp = seconds / 60; + seconds %= 60; if (tmp > 0) { - ore=tmp; - if (tmp > 1 || IS_PLAY_TIME()) { -#if defined(CPUARM) - PLAY_NUMBER(tmp, UNIT_HOURS, 0); -#else - PLAY_NUMBER(tmp, 0, 0); - PUSH_NUMBER_PROMPT(IT_PROMPT_ORE); - } else { - PUSH_NUMBER_PROMPT(IT_PROMPT_UN); - PUSH_NUMBER_PROMPT(IT_PROMPT_ORA); -#endif - } - } - if (seconds>0) { - tmp = seconds / 60; - seconds %= 60; - if (tmp>0 && seconds==0 && ore>0) { + PLAY_NUMBER(tmp, UNIT_MINUTES, 0); + if (seconds > 0) PUSH_NUMBER_PROMPT(IT_PROMPT_E); - } - if (tmp > 0) { - if (tmp != 1) { -#if defined(CPUARM) - PLAY_NUMBER(tmp, UNIT_MINUTES, 0); -#else - PLAY_NUMBER(tmp, 0, 0); - PUSH_NUMBER_PROMPT(IT_PROMPT_MINUTI); - } else { - PUSH_NUMBER_PROMPT(IT_PROMPT_UN); - PUSH_NUMBER_PROMPT(IT_PROMPT_MINUTO); -#endif - } - } - if ((tmp>0 || ore>0) && seconds>0) { - PUSH_NUMBER_PROMPT(IT_PROMPT_E); - } } - if (seconds != 0 || (ore==0 && tmp==0)) { - if (seconds != 1) { -#if defined(CPUARM) - PLAY_NUMBER(tmp, UNIT_SECONDS, 0); -#else - PLAY_NUMBER(seconds, 0, 0); - PUSH_NUMBER_PROMPT(IT_PROMPT_SECONDI); - } else { - PUSH_NUMBER_PROMPT(IT_PROMPT_UN); - PUSH_NUMBER_PROMPT(IT_PROMPT_SECONDO); -#endif - } + + if (seconds > 0) { + PLAY_NUMBER(seconds, UNIT_SECONDS, 0); } } diff --git a/radio/util/tts_it.py b/radio/util/tts_it.py index 1ecf94340..6df6c9e05 100755 --- a/radio/util/tts_it.py +++ b/radio/util/tts_it.py @@ -37,9 +37,9 @@ for i, (s, f) in enumerate([(u"volt", "volt0"), (u"radian", "rad0"), ("radians", "rad1"), (u"millilitro", "m10"), ("millilitri", "m11"), (u"oncia", "founce0"), ("once", "founce1"), - (u"hour", "hour0"), ("hours", "hour1"), - (u"minute", "minute0"), ("minutes", "minute1"), - (u"second", "second0"), ("seconds", "second1"), + (u"ora", "hour0"), ("ore", "hour1"), + (u"minuto", "minute0"), ("minuti", "minute1"), + (u"secondo", "second0"), ("secondi", "second1"), ]): systemSounds.append((s, filename(f, PROMPT_SYSTEM_BASE + 113 + i))) for s, f, a in [(u"radio inattiva controllare", "inactiv", 486), From 24de312a30d8c718504719b5356648e3d7085c36 Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sat, 6 May 2017 12:08:55 -0400 Subject: [PATCH 199/203] [Companion] Some radio settings Hardware tab fixes. (#4895) * [Companion] Radio -> General Settings -> Hardware: Hide external serial port option for Horus; Fix battery voltage and current calibration changes not registering (wrong signal handler name); Prevent modified() event if edited value wasn't actually changed (this is a problem in all panels with onEditingFinished() signals); Fix some cosmetic layout issues when no hardware names are editable. * [HardwarePanel] Minor layout fix for BT option. * [HardwarePanel] Fix comparison issue. --- companion/src/generaledit/hardware.cpp | 55 +++++--- companion/src/generaledit/hardware.h | 4 +- companion/src/generaledit/hardware.ui | 185 ++++++++++++++++--------- 3 files changed, 158 insertions(+), 86 deletions(-) diff --git a/companion/src/generaledit/hardware.cpp b/companion/src/generaledit/hardware.cpp index 3851e2a0c..770a226c2 100644 --- a/companion/src/generaledit/hardware.cpp +++ b/companion/src/generaledit/hardware.cpp @@ -110,6 +110,8 @@ HardwarePanel::HardwarePanel(QWidget * parent, GeneralSettings & generalSettings ui->thrName->hide(); ui->ailLabel->hide(); ui->ailName->hide(); + ui->potsTypeSeparator_1->hide(); + ui->potsTypeSeparator_2->hide(); } setupPotType(0, ui->pot1Label, ui->pot1Name, ui->pot1Type); @@ -141,10 +143,11 @@ HardwarePanel::HardwarePanel(QWidget * parent, GeneralSettings & generalSettings setupSwitchType(16, ui->sqLabel, ui->sqName, ui->sqType); setupSwitchType(17, ui->srLabel, ui->srName, ui->srType); - if (IS_HORUS_OR_TARANIS(board) && !IS_TARANIS_X7(board)) { + if (IS_TARANIS(board) && !IS_TARANIS_X7(board)) { ui->serialPortMode->setCurrentIndex(generalSettings.hw_uartMode); } else { + ui->serialPortMode->setCurrentIndex(0); ui->serialPortMode->hide(); ui->serialPortLabel->hide(); } @@ -160,8 +163,7 @@ HardwarePanel::HardwarePanel(QWidget * parent, GeneralSettings & generalSettings } else { ui->bluetoothLabel->hide(); - ui->bluetoothEnable->hide(); - ui->bluetoothName->hide(); + ui->bluetoothWidget->hide(); } if (IS_HORUS_OR_TARANIS(board)) { @@ -188,39 +190,52 @@ void HardwarePanel::on_filterEnable_stateChanged() void HardwarePanel::on_PPM_MultiplierDSB_editingFinished() { - generalSettings.PPM_Multiplier = (int)(ui->PPM_MultiplierDSB->value()*10)-10; - emit modified(); + int val = (int)(ui->PPM_MultiplierDSB->value()*10)-10; + if (generalSettings.PPM_Multiplier != val) { + generalSettings.PPM_Multiplier = val; + emit modified(); + } } void HardwarePanel::on_PPM1_editingFinished() { - generalSettings.trainer.calib[0] = ui->PPM1->value(); - emit modified(); + if (generalSettings.trainer.calib[0] != ui->PPM1->value()) { + generalSettings.trainer.calib[0] = ui->PPM1->value(); + emit modified(); + } } void HardwarePanel::on_PPM2_editingFinished() { - generalSettings.trainer.calib[1] = ui->PPM2->value(); - emit modified(); + if (generalSettings.trainer.calib[1] != ui->PPM2->value()) { + generalSettings.trainer.calib[1] = ui->PPM2->value(); + emit modified(); + } } void HardwarePanel::on_PPM3_editingFinished() { - generalSettings.trainer.calib[2] = ui->PPM3->value(); - emit modified(); + if (generalSettings.trainer.calib[2] != ui->PPM3->value()) { + generalSettings.trainer.calib[2] = ui->PPM3->value(); + emit modified(); + } } void HardwarePanel::on_PPM4_editingFinished() { - generalSettings.trainer.calib[3] = ui->PPM4->value(); - emit modified(); + if (generalSettings.trainer.calib[3] != ui->PPM4->value()) { + generalSettings.trainer.calib[3] = ui->PPM4->value(); + emit modified(); + } } -void HardwarePanel::on_txCurrentHardware_editingFinished() +void HardwarePanel::on_txCurrentCalibration_editingFinished() { - generalSettings.txCurrentCalibration = ui->txCurrentCalibration->value(); - emit modified(); + if (generalSettings.txCurrentCalibration != ui->txCurrentCalibration->value()) { + generalSettings.txCurrentCalibration = ui->txCurrentCalibration->value(); + emit modified(); + } } void HardwarePanel::on_bluetoothEnable_stateChanged(int) @@ -241,10 +256,12 @@ void HardwarePanel::setValues() ui->PPM_MultiplierDSB->setValue((qreal)(generalSettings.PPM_Multiplier+10)/10); } -void HardwarePanel::on_txVoltageHardware_editingFinished() +void HardwarePanel::on_txVoltageCalibration_editingFinished() { - generalSettings.txVoltageCalibration = ui->txVoltageCalibration->value()*10; - emit modified(); + if (generalSettings.txVoltageCalibration != ui->txVoltageCalibration->value()*10) { + generalSettings.txVoltageCalibration = ui->txVoltageCalibration->value()*10; + emit modified(); + } } void HardwarePanel::on_serialPortMode_currentIndexChanged(int index) diff --git a/companion/src/generaledit/hardware.h b/companion/src/generaledit/hardware.h index af7a2237a..7d53a6d14 100644 --- a/companion/src/generaledit/hardware.h +++ b/companion/src/generaledit/hardware.h @@ -40,14 +40,14 @@ class HardwarePanel : public GeneralPanel virtual ~HardwarePanel(); private slots: - void on_txVoltageHardware_editingFinished(); void on_PPM1_editingFinished(); void on_PPM2_editingFinished(); void on_PPM3_editingFinished(); void on_PPM4_editingFinished(); void on_PPM_MultiplierDSB_editingFinished(); - void on_txCurrentHardware_editingFinished(); + void on_txCurrentCalibration_editingFinished(); + void on_txVoltageCalibration_editingFinished(); void on_bluetoothEnable_stateChanged(int); void on_filterEnable_stateChanged(); diff --git a/companion/src/generaledit/hardware.ui b/companion/src/generaledit/hardware.ui index c7e70c10a..72fe4ba15 100644 --- a/companion/src/generaledit/hardware.ui +++ b/companion/src/generaledit/hardware.ui @@ -6,14 +6,23 @@ 0 0 - 359 - 1594 + 470 + 1095 + + + 0 + 0 + + Form - + + + 6 + @@ -125,19 +134,6 @@ - - - - - 0 - 10 - - - - Qt::Horizontal - - - @@ -730,32 +726,6 @@ - - - - - 0 - 10 - - - - Qt::Horizontal - - - - - - - - 0 - 10 - - - - Qt::Horizontal - - - @@ -1075,6 +1045,12 @@ + + + 0 + 0 + + Bluetooth @@ -1090,24 +1066,6 @@ - - - - - - - - - - - - - 10 - - - - - @@ -1122,19 +1080,116 @@ + + + + + 6 + + + 0 + + + 0 + + + 0 + + + 0 + + + + + + + + + + + + Qt::Horizontal + + + QSizePolicy::Fixed + + + + 5 + 20 + + + + + + + + Device Name: + + + + + + + 10 + + + + + + + + + + + 0 + 10 + + + + Qt::Horizontal + + + + + + + + 0 + 10 + + + + Qt::Horizontal + + + + + + + + 0 + 10 + + + + Qt::Horizontal + + + - - AutoLineEdit - QLineEdit -
autolineedit.h
- AutoComboBox QComboBox
autocombobox.h
 + + AutoLineEdit + QLineEdit +
autolineedit.h
+ From e2502772cbaee573684fef0556d0174fbf473b0f Mon Sep 17 00:00:00 2001 From: Max Paperno Date: Sat, 6 May 2017 12:09:20 -0400 Subject: [PATCH 200/203] [Companion] Model Setup: Prevent bogus modification signals. (#4896) * [Companion] Model editor Setup panel: Prevent bogus modification signals, eg. when populating protocols box or when removing focus from some fields w/out the value actually changing; Remove unnecessary function. * [SetupPanel] Fix comparison warning and also a translation issue with Multiprotocols subtype and option names. * [ModelPrinter] Add a missing include. --- companion/src/modeledit/setup.cpp | 76 +++++++++++++++++-------------- companion/src/modeledit/setup.h | 5 +- companion/src/modelprinter.cpp | 3 +- 3 files changed, 46 insertions(+), 38 deletions(-) diff --git a/companion/src/modeledit/setup.cpp b/companion/src/modeledit/setup.cpp index 64aee0af8..657b891fe 100644 --- a/companion/src/modeledit/setup.cpp +++ b/companion/src/modeledit/setup.cpp @@ -51,7 +51,6 @@ TimerPanel::TimerPanel(QWidget *parent, ModelData & model, TimerData & timer, Ge // Mode ui->mode->setModel(Helpers::getRawSwitchItemModel(&generalSettings, Helpers::TimersContext)); ui->mode->setCurrentIndex(ui->mode->findData(timer.mode.toValue())); - //Helpers::populateSwitchCB(ui->mode, timer.mode, generalSettings, Helpers::TimersContext); if (!firmware->getCapability(PermTimers)) { ui->persistent->hide(); @@ -121,8 +120,11 @@ QWidget * TimerPanel::getLastFocus() void TimerPanel::on_value_editingFinished() { - timer.val = ui->value->time().hour()*3600 + ui->value->time().minute()*60 + ui->value->time().second(); - emit modified(); + unsigned val = ui->value->time().hour()*3600 + ui->value->time().minute()*60 + ui->value->time().second(); + if (timer.val != val) { + timer.val = val; + emit modified(); + } } void TimerPanel::on_mode_currentIndexChanged(int index) @@ -141,9 +143,11 @@ void TimerPanel::on_minuteBeep_toggled(bool checked) void TimerPanel::on_name_editingFinished() { - int length = ui->name->maxLength(); - strncpy(timer.name, ui->name->text().toLatin1(), length); - emit modified(); + if (QString(timer.name) != ui->name->text()) { + int length = ui->name->maxLength(); + strncpy(timer.name, ui->name->text().toLatin1(), length); + emit modified(); + } } /******************************************************************************/ @@ -234,15 +238,15 @@ ModulePanel::ModulePanel(QWidget * parent, ModelData & model, ModuleData & modul disableMouseScrolling(); + update(); + + connect(ui->protocol, static_cast(&QComboBox::currentIndexChanged), this, &ModulePanel::onProtocolChanged); + connect(ui->multiProtocol, static_cast(&QComboBox::currentIndexChanged), this, &ModulePanel::onMultiProtocolChanged); connect(this, &ModulePanel::channelsRangeChanged, this, &ModulePanel::setupFailsafes); connect(ui->btnGrpValueType, static_cast(&QButtonGroup::buttonClicked), this, &ModulePanel::onFailsafesDisplayValueTypeChanged); lock = false; - // a change will not register if only one item was added - if (ui->protocol->count() == 1) { - on_protocol_currentIndexChanged(ui->protocol->currentIndex()); - } } ModulePanel::~ModulePanel() @@ -476,7 +480,7 @@ void ModulePanel::update() ui->optionValue->setMinimum(pdef.getOptionMin()); ui->optionValue->setMaximum(pdef.getOptionMax()); ui->optionValue->setValue(module.multi.optionValue); - ui->label_option->setText(pdef.optionsstr); + ui->label_option->setText(qApp->translate("Multiprotocols", qPrintable(pdef.optionsstr))); } ui->multiSubType->setCurrentIndex(module.subType); @@ -533,7 +537,7 @@ void ModulePanel::on_trainerMode_currentIndexChanged(int index) } } -void ModulePanel::on_protocol_currentIndexChanged(int index) +void ModulePanel::onProtocolChanged(int index) { if (!lock) { module.protocol = ui->protocol->itemData(index).toInt(); @@ -562,7 +566,7 @@ void ModulePanel::on_ppmOutputType_currentIndexChanged(int index) void ModulePanel::on_channelsCount_editingFinished() { - if (!lock) { + if (!lock && module.channelsCount != ui->channelsCount->value()) { module.channelsCount = ui->channelsCount->value(); update(); emit channelsRangeChanged(); @@ -572,8 +576,8 @@ void ModulePanel::on_channelsCount_editingFinished() void ModulePanel::on_channelsStart_editingFinished() { - if (!lock) { - module.channelsStart = ui->channelsStart->value() - 1; + if (!lock && module.channelsStart != (unsigned)ui->channelsStart->value() - 1) { + module.channelsStart = (unsigned)ui->channelsStart->value() - 1; update(); emit channelsRangeChanged(); emit modified(); @@ -582,7 +586,7 @@ void ModulePanel::on_channelsStart_editingFinished() void ModulePanel::on_ppmDelay_editingFinished() { - if (!lock) { + if (!lock && module.ppm.delay != ui->ppmDelay->value()) { // TODO only accept valid values module.ppm.delay = ui->ppmDelay->value(); emit modified(); @@ -591,14 +595,19 @@ void ModulePanel::on_ppmDelay_editingFinished() void ModulePanel::on_rxNumber_editingFinished() { - module.modelId = ui->rxNumber->value(); - emit modified(); + if (module.modelId != (unsigned)ui->rxNumber->value()) { + module.modelId = (unsigned)ui->rxNumber->value(); + emit modified(); + } } void ModulePanel::on_ppmFrameLength_editingFinished() { - module.ppm.frameLength = (ui->ppmFrameLength->value()-22.5) / 0.5; - emit modified(); + int val = (ui->ppmFrameLength->value()-22.5) / 0.5; + if (module.ppm.frameLength != val) { + module.ppm.frameLength = val; + emit modified(); + } } void ModulePanel::on_failsafeMode_currentIndexChanged(int value) @@ -610,7 +619,7 @@ void ModulePanel::on_failsafeMode_currentIndexChanged(int value) } } -void ModulePanel::on_multiProtocol_currentIndexChanged(int index) +void ModulePanel::onMultiProtocolChanged(int index) { if (!lock) { lock=true; @@ -627,8 +636,10 @@ void ModulePanel::on_multiProtocol_currentIndexChanged(int index) void ModulePanel::on_optionValue_editingFinished() { - module.multi.optionValue = ui->optionValue->value(); - emit modified(); + if (module.multi.optionValue != ui->optionValue->value()) { + module.multi.optionValue = ui->optionValue->value(); + emit modified(); + } } void ModulePanel::on_multiSubType_currentIndexChanged(int index) @@ -855,7 +866,7 @@ SetupPanel::SetupPanel(QWidget * parent, ModelData & model, GeneralSettings & ge if (igetCapability(Timers)) { timers[i] = new TimerPanel(this, model, model.timers[i], generalSettings, firmware, prevFocus); ui->gridLayout->addWidget(timers[i], 1+i, 1); - connect(timers[i], SIGNAL(modified()), this, SLOT(onChildModified())); + connect(timers[i], &TimerPanel::modified, this, &SetupPanel::modified); prevFocus = timers[i]->getLastFocus(); } else { @@ -987,14 +998,14 @@ SetupPanel::SetupPanel(QWidget * parent, ModelData & model, GeneralSettings & ge for (int i=0; igetCapability(NumModules); i++) { modules[i] = new ModulePanel(this, model, model.moduleData[i], generalSettings, firmware, i); ui->modulesLayout->addWidget(modules[i]); - connect(modules[i], SIGNAL(modified()), this, SLOT(onChildModified())); + connect(modules[i], &ModulePanel::modified, this, &SetupPanel::modified); connect(this, &SetupPanel::extendedLimitsToggled, modules[i], &ModulePanel::onExtendedLimitsToggled); } if (firmware->getCapability(ModelTrainerEnable)) { modules[CPN_MAX_MODULES] = new ModulePanel(this, model, model.moduleData[CPN_MAX_MODULES], generalSettings, firmware, -1); ui->modulesLayout->addWidget(modules[CPN_MAX_MODULES]); - connect(modules[CPN_MAX_MODULES], SIGNAL(modified()), this, SLOT(onChildModified())); + connect(modules[CPN_MAX_MODULES], &ModulePanel::modified, this, &SetupPanel::modified); } disableMouseScrolling(); @@ -1048,9 +1059,11 @@ void SetupPanel::on_throttleSource_currentIndexChanged(int index) void SetupPanel::on_name_editingFinished() { - int length = ui->name->maxLength(); - strncpy(model->name, ui->name->text().toLatin1(), length); - emit modified(); + if (QString(model->name) != ui->name->text()) { + int length = ui->name->maxLength(); + strncpy(model->name, ui->name->text().toLatin1(), length); + emit modified(); + } } void SetupPanel::on_image_currentIndexChanged(int index) @@ -1293,8 +1306,3 @@ void SetupPanel::onBeepCenterToggled(bool checked) emit modified(); } } - -void SetupPanel::onChildModified() -{ - emit modified(); -} diff --git a/companion/src/modeledit/setup.h b/companion/src/modeledit/setup.h index d31155f14..66e819c2e 100644 --- a/companion/src/modeledit/setup.h +++ b/companion/src/modeledit/setup.h @@ -71,7 +71,7 @@ class ModulePanel : public ModelPanel private slots: void setupFailsafes(); void on_trainerMode_currentIndexChanged(int index); - void on_protocol_currentIndexChanged(int index); + void onProtocolChanged(int index); void on_ppmDelay_editingFinished(); void on_channelsCount_editingFinished(); void on_channelsStart_editingFinished(); @@ -81,7 +81,7 @@ class ModulePanel : public ModelPanel void on_antennaMode_currentIndexChanged(int index); void on_rxNumber_editingFinished(); void on_failsafeMode_currentIndexChanged(int value); - void on_multiProtocol_currentIndexChanged(int index); + void onMultiProtocolChanged(int index); void on_multiSubType_currentIndexChanged(int index); void on_autoBind_stateChanged(int state); void on_lowPower_stateChanged(int state); @@ -140,7 +140,6 @@ class SetupPanel : public ModelPanel void startupSwitchToggled(bool checked); void potWarningToggled(bool checked); void on_potWarningMode_currentIndexChanged(int index); - void onChildModified(); private: Ui::Setup *ui; diff --git a/companion/src/modelprinter.cpp b/companion/src/modelprinter.cpp index b7e0a1e95..ebdfb69fa 100644 --- a/companion/src/modelprinter.cpp +++ b/companion/src/modelprinter.cpp @@ -22,6 +22,7 @@ #include "modelprinter.h" #include "multiprotocols.h" +#include #include #include #include @@ -146,7 +147,7 @@ QString ModelPrinter::printMultiSubType(int rfProtocol, bool custom, unsigned in Multiprotocols::MultiProtocolDefinition pdef = multiProtocols.getProtocol(rfProtocol); if (subType < (unsigned int) pdef.subTypeStrings.size()) - return pdef.subTypeStrings[subType]; + return qApp->translate("Multiprotocols", qPrintable(pdef.subTypeStrings[subType])); else return "???"; } From 53bb8bc6c37946b0c20ac622ce4eaff53ea6f450 Mon Sep 17 00:00:00 2001 From: Sebastien Charpentier Date: Sun, 7 May 2017 17:39:06 +0200 Subject: [PATCH 201/203] Updated French translation. (#4902) * Generate nex French .ts file. * Updated French translation. --- companion/src/translations/companion_fr.ts | 687 +++++++++++---------- 1 file changed, 344 insertions(+), 343 deletions(-) diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 977953422..6e8720c00 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -665,14 +665,14 @@ Peut être différente de la langue du firmware - CompanionMacros + Companion - + files fichiers - + Radio and Models settings Réglages Radio et Modèles @@ -733,49 +733,6 @@ Peut être différente de la langue du firmware OK, compris. - - ContributorsDialog - - - OpenTX Contributors - Contributeurs d'OpenTX - - - - Main Developers - Principaux développeurs - - - - Other contributors - Autres contributeurs - - - - Companies and projects who have donated to OpenTX - Entreprises et projets qui ont fait un don à OpenTX - - - - People who have donated to OpenTX - Personnes qui ont fait un don à OpenTX - - - - Honors go to Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) - Les honneurs vont à Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) - - - - OpenTX Blacklist - - - - - monthly - don mensuel - - CopyProcess @@ -801,6 +758,54 @@ Peut être différente de la langue du firmware Impossible d'ouvrir %1 (raison: %2) + + CreditsDialog + + + OpenTX Contributors + Contributeurs d'OpenTX + + + + Honors go to Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) + Les honneurs vont à Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) + + + + OpenTX Blacklist + Liste noire d'OpenTX + + + + Main developers + Principaux développeurs + + + + Translators + Traducteurs + + + + Companies and projects who have donated to OpenTX + Entreprises et projets qui ont fait un don à OpenTX + + + + People who have donated to OpenTX + Personnes qui ont fait un don à OpenTX + + + + Other contributors + Autres contributeurs + + + + monthly + don mensuel + + CurveData @@ -3245,66 +3250,66 @@ Are you sure ? Hardware - + Form Formulaire - + SQ - + SR - + LS2 - + SP - + SO - + S4 - + RS - + SB - + PPM 2 - - - - - - - - - - + + + + + + + + + + Beeper volume 0 - Quiet. No beeps at all. @@ -3321,190 +3326,195 @@ Long : bips plus longs. Extra long : bips extra longs. - + OFF Eteint - + S-Port Mirror Recopie S. Port - + Telemetry Télémetrie - + SBUS Trainer Écolage SBUS - + Debug Débogage - + Rud Dir - + PPM 3 - + S1 - + S2 - + S3 - + PPM 1 - + Serial Port Port série - + v - + PPM Multiplier Coeff. multiplicateur PPM - + Current Offset Correction courant - + PPM 4 - + SA - + Ele Prf - + Ail Ail - + Thr Gaz - + SC - + LS - + SD - + Battery Offset Correction tension - + SE - + SF - + SG - + SH - + SI - + SJ - + SK - + SL - + SM - + SN - + RS2 - + Bluetooth - + ADC Filter Filtre ADC + + + Device Name: + Nom de l'appareil: + HardwarePanel @@ -4036,14 +4046,14 @@ Les colonnes contenant l'altitude "GAlt" et la vitesse "GSpd MainWindow - - + + Edit Édition - - + + File Fichier @@ -4110,27 +4120,27 @@ Les colonnes contenant l'altitude "GAlt" et la vitesse "GSpd Voulez-vous télécharger la version %1 maintenant ? - + Firmware updates Mises à jour de firmware - + Current firmware does not provide release notes informations. Le firmware actuel ne contient pas de notes de version. - + Compare models Comparer les modèles - + Show fuses dialog Afficher les réglages des fusibles - + A monochrome black icon theme Thème avec icônes monochromes noires @@ -4165,221 +4175,221 @@ Voulez vous la télécharger maintenant ? Nous recommandons de lire attentivement les notes de version à l'aide du bouton ci-dessous, celles-ci peuvent contenir des infos importantes concernant les changements effectués depuis la version précédente. - - + + Synchronize SD Synchroniser la carte SD - + New Nouveau - + Open... Ouvrir... - + A monochrome white icon theme Thème avec icônes monochromes blanches - + A monochrome blue icon theme Thème avec icônes monochromes bleues - + Small Petites - + Use small toolbar icons Petites icônes de barre d'outils - + Use normal size toolbar icons Icônes de barre d'outils normales - + Normal Normales - + Use big toolbar icons Grosses icônes de barre d'outils - + Big Grandes - + Use huge toolbar icons Immenses icônes de barre d'outils - + Huge Immenses - + List programmers... Lister les programmateurs... - + Fuses... Fusibles... - - + + Read Firmware from Radio Lire le firmware de la radio - + Read firmware from Radio Lire le firmware de la radio - + Write Firmware to Radio Transférer le firmware à la radio - + Write firmware to Radio Transférer le firmware à la radio - + Add Radio Profile Ajouter un profil de radio - + Manuals and other Documents Manuels et documents - + Open the OpenTX document page in a web browser Ouvre la page de documentation d'OpenTX dans un navigateur - + Write Models and Settings To Radio Transférer les réglages et modèles vers la radio - + Write Models and Settings to Radio Transférer les réglages et modèles vers la radio - + Companion - - + + Read Models and Settings from Radio Lire les réglages et modèles depuis la radio - + OpenTX Companion %1 - Radio: %2 - Profile: %3 OpenTX Companion %1 - Radio: %2 - Profil: %3 - + List of recently used files Liste des fichiers récemment utilisés - + Radio Profiles Profil radio - + Create or Select Radio Profiles Créer ou Sélectionner un profil radio - + Configure Communications... Configurer les communications... - + Configure software for communicating with the Radio Configurer le programme gérant les communications avec la radio - + Write Backup to Radio Transférer une sauvegarde à la radio - + Write Backup from file to Radio Transférer une sauvegarde à la radio - + Backup Radio to File Sauvegarder la radio - + Save a complete backup file of all settings and model data in the Radio Créer une copie de sauvegarde de tous les réglages et modèles de la radio - + Contributors... Contributeurs... - + A tribute to those who have contributed to OpenTX and Companion Remerciements à tout ceux qui ont contribué à OpenTX et Companion - + SD card synchronization Synchronisation de la carte SD - + Recent Files Fichiers récents - + Set Icon Theme Choisir le thème d'icônes - + Set Icon Size Choisir la taille des icônes - + Write Ecrire @@ -4389,22 +4399,22 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Une nouvelle version de Companion est disponible (version %1)<br>Voulez-vous la télécharger ? - + OpenTX Home Page: <a href='%1'>%1</a> Page d'accueil d'OpenTX: <a href='%1'>%1</a> - + If you've found this program useful, please support by <a href='%1'>donating</a> Si vous trouvez ce programme utile, merci de le supporter par une <a href='%1'>donation</a> - + Ready Prêt - + Show the application's About box Afficher la fenêtre "A propos" de l'application @@ -4420,19 +4430,19 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Une nouvelle version de Companion est disponible, veuillez vous référer au site web d'OpenTX ! - - + + Open Models and Settings file Ouvrir un fichier de réglages et modèles - - + + File saved Fichier sauvegardé - + Read Models and Settings From Radio Lire les réglages et modèles depuis la radio @@ -4472,334 +4482,334 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Language non valide - + Some text will not be translated until the next time you start Companion. Please note that some translations may not be complete. Certains textes ne seront pas traduits avant le prochain redémarrage de Companion. Veuillez noter que certaines traductions peuvent ne pas être complètes. - + Models and Settings read Lecture des modèles et réglages - - + + This function is not yet implemented Cette fonction n'est pas implémentée pour l'instant - + Save Radio Backup to File Sauvegarder la radio - + Read Radio Firmware to File Sauvegarder le firmware de la radio - + The OpenTX Companion project was originally forked from <a href='%1'>eePe</a> Le projet OpenTX Companion a été créé à partir d'<a href='%1'>eePe</a> - + Copyright OpenTX Team - + Create a new Models and Settings file Créer un nouveau fichier de réglages et modèles - - + + Save Models and Settings file Enregistrer le fichier de réglages et modèles - + Save Enregistrer - + Save As... Enregistrer sous... - + Close Fermer - + Close Models and Settings file Fermer le fichier de réglages et modèles - + Exit the application Quitter l'application - + Exit Quitter - + Create a new Radio Settings Profile Créer un nouveau profil de réglages et modèles - + Copy Current Radio Profile Copier le profil radio actuel - + Duplicate current Radio Settings Profile Dupliquer les réglages radio du profil actuel - + Delete the current Radio Settings Profile Supprimer les réglages radio du profil actuel - + Use default system language. Utiliser le langage système par défaut. - + Use %1 language (some translations may not be complete). Utiliser la langue %1 (certaines traductions peuvent être incomplètes). - + Classical Classique - + Delete Current Radio Profile... Supprimer le profil radio actuel... - + Tabbed Windows Fenêtres à onglets - + Use tabs to arrange open windows. Utilisez les onglets pour organiser les fenêtres ouvertes. - + Tile Windows Titre de la fenêtre - + Arrange open windows across all the available space. Disposez les fenêtres ouvertes sur tout l'espace disponible. - + Cascade Windows Fenêtres en cascade - + Arrange all open windows in a stack. Organisez toutes les fenêtres ouvertes dans une pile. - + Close All Windows Fermer toutes les fenêtres - + Closes all open files (prompts to save if necessary. Fermer tous les fichiers ouverts (proposer de sauvegarder si nécessaire). - + Window Fenêtre - + Ctrl+Shift+S - + Ctrl+Alt+L - + Ctrl+Alt+D - + Ctrl+Alt+R - + The classic companion9x icon theme Thème d'icônes classique de Companion - + Yerico - + Yellow round honey sweet icon theme Thème d'icônes rondes jaunes - + Monochrome - + MonoWhite Monochrome Blanc - + Alt+%1 - + - Copy - Copier - + Not possible to remove profile Impossible de supprimer le profil - + The default profile can not be removed. Le profil par défaut ne peut pas être supprimé. - + Confirm Delete Profile Confirmer la suppression du profil - + Are you sure you wish to delete the "%1" radio profile? There is no way to undo this action! Etes-vous sûr de vouloir supprimer le profil radio %1 ? Cette action est irréversible ! - + MonoBlue Monochrome Bleu - + System language Langue du système - + About... A propos... - + View Log File... Ouvrir un Log... - + Open and view log file Ouvrir et visualiser un log - + Settings... Préférences... - + Edit Settings Éditer les réglages - + Download... Télécharger... - + Download firmware and voice files Télécharger firmware et fichiers son - + Check for Updates... Vérifier les mises à jour... - + Check OpenTX and Companion updates Vérifier les mises à jour d'OpenTX et Companion - + Companion Changes... Changements de Companion... - + Show Companion change log Voir l'historique des changements de Companion - + Firmware Changes... Changements du firmware... - + Show firmware change log Voir l'historique des changements du firmware - + Compare Models... Comparer 2 modèles... - + Edit Radio Splash Image... Éditer l'écran d'accueil de la radio... - + Edit the splash image of your Radio Éditer l'écran d'accueil de la radio - + List available programmers Lister les programmateurs supportés @@ -4831,8 +4841,8 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Voulez-vous lancer l'installation ? - - + + Help Aide @@ -4847,32 +4857,32 @@ Nous recommandons de lire attentivement les notes de version à l'aide du b Le nouveau thème sera utilisé lors du prochain lancement de Companion. - + About Companion A propos de Companion - + Set Menu Language Choisir la langue des menus - + Settings Réglages - + Read/Write Transfert - + %2 - + New Radio Nouvelle radio @@ -5688,303 +5698,303 @@ Mixage actif par défaut si non-renseigné. ModelPrinter - + %1 bytes %1 octets - + Exponential Exponentiel - + Extra Fine Extra fin - + Fine Fin - + Medium Moyen - + Coarse Grossier - + Unknown Inconnu - + Enabled Actif - + Disabled Inactif - + %1, Channels(%2-%3), PPM delay(%4usec), Pulse polarity(%5) %1, Voies(%2-%3), Impulsion(%4µs), Polarité(%5) - + %1, Channels(%2-%3) %1, Voies(%2-%3) - + Receiver number(%1) No. de récepteur(%1) - + radio Protocol %1, subType %2, option value %3 radio Protocol %1, sousType %2, option %3 - + Slave/Jack Elève/Jack - + Master/SBUS Module Maître/SBUS module - + Master/CPPM Module Maître/CPPM Module - + Master/SBUS in battery compartment Maître/SBUS compartiment batterie - + Master/Jack Maître/Jack - + 90 - + 120 - + 120X - + 140 - + Rudder Dérive - + Elevator Profondeur - + Throttle Gaz - + Aileron Ailerons - + Name(%1) Nom(%1) - + Persistent Persistant - + MinuteBeep Bip minutes - + CountDown(Beeps) Cpte à rebours(bips) - + CountDown(Voice) Cpte à rebours(voix) - + CountDown(Haptic) Cpte à rebours(vibreur) - - + + Off - - - - + + + + FM%1 PV%1 - + FM%1%2 PV%1%2 - + FM%1+%2 PV%1+%2 - + [I%1] [E%1] - + Input%1 Entrée%1 - + Weight Ratio - + Switch Inter - - + + NoTrim Pas de trim - + Weight(%1) Ratio(%1) - + Switch(%1) Inter(%1) - + No DR/Expo Pas d'expo/DR - - + + Offset(%1) Décalage(%1) - + Delay(u%1:d%2) Délai(h%1:b%2) - + Slow(u%1:d%2) Ralenti(h%1:b%2) - + Warn(%1) Alerte(%1) - + Disabled in all flight modes Désactivé pour toutes les phases de vol - + Flight modes(%1) Phases de vol(%1) - + Flight mode(%1) Phase de vol(%1) - + Edge(%1, [%2:%3]) Flanc(%1, [%2:%3]) - + instant - + Sticky(%1, %2) Bistable(%1, %2) - + Timer(%1, %2) Chrono(%1, %2) - + Duration(%1s) Durée(%1s) - + Delay(%1s) Délai(%1s) - + Custom Prédéfini - + Standard @@ -6220,43 +6230,43 @@ Mixage actif par défaut si non-renseigné. ModulePanel - + Trainer Port Port écolage - + Internal Radio System Module HF interne - + External Radio Module Module HF externe - - + + Radio System Module HF - + Extra Radio System Module HF supplémentaire - + Value Valeur - + Hold Maintien - + No Pulse Pas d'impulsion @@ -7436,7 +7446,7 @@ Mixage actif par défaut si non-renseigné. - + THR GAZ @@ -8721,8 +8731,8 @@ The OpenTX Team. L'équipe OpenTX. - - + + @@ -8730,12 +8740,12 @@ L'équipe OpenTX. Erreur de synchronisation - + No SD directory configured! Aucun dossier SD configuré ! - + No Radio connected! Aucune radio connectée ! @@ -9082,22 +9092,22 @@ E RawSwitch - + ↑ - + ↓ - + - - + ! @@ -9308,7 +9318,7 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo SetupPanel - + Timer %1 Chrono %1 @@ -9516,15 +9526,6 @@ Si cette option est cochée, la voie des gaz est inversée: le ralenti est &apo - - SimulatedUIWidget9X - - - - | - - - SimulatorMain @@ -11517,37 +11518,37 @@ hh:mm:ss TimerPanel - + Silent Aucun - + Beeps Bips - + Voice Voix - + Haptic Vibreur - + Not persistent Non persistant - + Persistent (flight) Persistant (vol) - + Persistent (manual reset) Persistant (RAZ manuelle) From 301e33a27147aa808c4857ed0f53dfd209a4679c Mon Sep 17 00:00:00 2001 From: 3djc Date: Sun, 7 May 2017 17:39:31 +0200 Subject: [PATCH 202/203] gTTS (#4899) * Release prep work * Add CZ support * Prep for release * No more need to prefix unicode strings (we use python3) Some fixes Italian fixes --- CMakeLists.txt | 2 +- radio/util/tts_cz.py | 184 ++++++++++++++++---------------- radio/util/tts_de.py | 164 ++++++++++++++-------------- radio/util/tts_en.py | 134 +++++++++++------------ radio/util/tts_es.py | 160 +++++++++++++-------------- radio/util/tts_fr.py | 147 +++++++++++++++---------- radio/util/tts_it.py | 166 ++++++++++++++-------------- radio/util/tts_pt.py | 102 +++++++++--------- tools/nightly22/build-sdcard.sh | 2 + tools/nightly22/tts.py | 23 +++- tools/release22/tts.py | 32 ++++-- 11 files changed, 591 insertions(+), 525 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 2327a84bb..f5629bc2d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -6,7 +6,7 @@ set(VERSION_REVISION "0") set(VERSION_SUFFIX $ENV{OPENTX_VERSION_SUFFIX}) set(VERSION_FAMILY ${VERSION_MAJOR}.${VERSION_MINOR}) set(VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_REVISION}${VERSION_SUFFIX}) -set(SDCARD_REVISION "0009") +set(SDCARD_REVISION "0010") set(SDCARD_VERSION ${VERSION_MAJOR}.${VERSION_MINOR}V${SDCARD_REVISION}) cmake_minimum_required(VERSION 2.8) diff --git a/radio/util/tts_cz.py b/radio/util/tts_cz.py index 549b83b1a..b9dd75c3a 100755 --- a/radio/util/tts_cz.py +++ b/radio/util/tts_cz.py @@ -12,103 +12,103 @@ for i, s in enumerate(["nula", "jedna", "dva"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + i))) for i in range(97): systemSounds.append((str(3 + i), filename(PROMPT_SYSTEM_BASE + 3 + i))) -for i, s in enumerate(["sto", u"dvěsta", u"třista", u"čtyřista", u"pětset", u"šestset", "sedmset", "osmset", - u"devětset", u"tisíc"]): +for i, s in enumerate(["sto", "dvěsta", "třista", "čtyřista", "pětset", "šestset", "sedmset", "osmset", + "devětset", "tisíc"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 100 + i))) -for i, s in enumerate([u"tisíce", "jeden", "jedno", u"dvě", u"celá", u"celé", u"celých", u"mínus"]): +for i, s in enumerate(["tisíce", "jeden", "jedno", "dvě", "celá", "celé", "celých", "mínus"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 110 + i))) -for i, (s, f) in enumerate([(u"volt", u"volt0"), (u"volty", u"volt1"), (u"voltů", u"volt2"),(u"voltu", u"volt3"), - (u"ampér", "amp0"), (u"ampéry", u"amp1"), (u"ampérů", u"amp2"), (u"ampéru", u"amp3"), - (u"miliampér", "mamp0"), (u"miliampéry", u"mamp1"), (u"miliampérů", u"mamp2"), (u"miliampéru", u"mamp3"), - (u"uzel", "knot0"), (u"uzly", u"knot1"), (u"uzlů", u"knot2"), (u"uzlu", u"knot3"), - (u"metr za sekundu", "mps0"), (u"metry za sekundu", u"mps1"), (u"metrů za sekundu", u"mps2"), (u"metru za sekundu", u"mps3"), - (u"stopa za sekundu", "fps0"), (u"stopy za sekundu", u"fps1"), (u"stop za sekundu", u"fps2"), (u"stopy za sekundu", u"fps3"), - (u"kilometr za hodinu", "kph0"), (u"kilometry za hodinu", u"kph1"), (u"kilometrů za hodinu", u"kph2"), (u"kilometru za hodinu", u"kph3"), - (u"míle za hodinu", "mph0"), (u"míle za hodinu", u"mph1"), (u"mil za hodinu", u"mph2"), (u"míle za hodinu", u"mph3"), - (u"metr", "meter0"), (u"metry", u"meter1"), (u"metrů", u"meter2"), (u"metru", u"meter3"), - (u"stopa", "foot0"), (u"stopy", u"foot1"), (u"stop", u"foot2"),(u"stopy", u"foot3"), - (u"stupeň celsia", "celsius0"), (u"stupně celsia", u"celsius1"), (u"stupňů celsia", u"celsius2"), (u"stupně celsia", u"celsius3"), - (u"stupeň fahrenheita", "fahr0"), (u"stupně fahrenheita", u"fahr1"), (u"stupňů fahrenheita", u"fahr2"), (u"stupně fahrenheita", u"fahr3"), - (u"procento", "percent0"), (u"procenta", u"percent1"), (u"procent", u"percent2"), (u"procenta", u"percent3"), - (u"miliampérhodina", "mamph0"), (u"miliampérhodiny", u"mamph1"), (u"miliampérhodin", u"mamph2"), (u"miliampérhodiny", u"mamph3"), - (u"vat", "watt0"), (u"vaty", u"watt1"), (u"vatů", u"watt2"), (u"vatu", u"watt3"), - (u"milivat", "mwatt0"), (u"milivaty", u"mwatt1"), (u"milivatů", u"mwatt2"), (u"milivatu", u"mwatt3"), - (u"decibel", "db0"), (u"decibely", u"db1"), (u"decibelů", u"db2"), (u"decibelu", u"db3"), - (u"otáčka za minutu", "rpm0"), (u"otáčky za minutu", u"rpm1"), (u"otáček za minutu", u"rpm2"), (u"otáčky za minutu", u"rpm3"), - (u"gé", "g0"), (u"gé", "g1"), (u"gé", "g2"), (u"gé", "g3"), - (u"stupeň", "degree0"), (u"stupně", u"degree1"), (u"stupňů", u"degree2"), (u"stupně", u"degree3"), - (u"radián", "rad0"), (u"radiány", "rad1"), (u"radiánů", "rad2"), (u"radiánu", "rad3"), - (u"mililitr", "ml0"), (u"mililitry", u"ml1"), (u"mililitrů", u"ml2"), (u"mililitru", u"ml3"), - (u"dutá unce", "founce0"), (u"duté unce", u"founce1"), (u"dutých uncí", u"founce2"), (u"duté unce", u"founce3"), - (u"hodina", "hour0"), (u"hodiny", u"hour1"), (u"hodin", u"hour2"), (u"hodiny", u"hour3"), - (u"minuta", "minute0"), (u"minuty", u"minute1"), (u"minut", u"minute2"), (u"minuty", u"minute3"), - (u"sekunda", "second0"), (u"sekundy", u"second1"), (u"sekund", u"second2"), (u"sekundy", u"second3"), +for i, (s, f) in enumerate([("volt", "volt0"), ("volty", "volt1"), ("voltů", "volt2"),("voltu", "volt3"), + ("ampér", "amp0"), ("ampéry", "amp1"), ("ampérů", "amp2"), ("ampéru", "amp3"), + ("miliampér", "mamp0"), ("miliampéry", "mamp1"), ("miliampérů", "mamp2"), ("miliampéru", "mamp3"), + ("uzel", "knot0"), ("uzly", "knot1"), ("uzlů", "knot2"), ("uzlu", "knot3"), + ("metr za sekundu", "mps0"), ("metry za sekundu", "mps1"), ("metrů za sekundu", "mps2"), ("metru za sekundu", "mps3"), + ("stopa za sekundu", "fps0"), ("stopy za sekundu", "fps1"), ("stop za sekundu", "fps2"), ("stopy za sekundu", "fps3"), + ("kilometr za hodinu", "kph0"), ("kilometry za hodinu", "kph1"), ("kilometrů za hodinu", "kph2"), ("kilometru za hodinu", "kph3"), + ("míle za hodinu", "mph0"), ("míle za hodinu", "mph1"), ("mil za hodinu", "mph2"), ("míle za hodinu", "mph3"), + ("metr", "meter0"), ("metry", "meter1"), ("metrů", "meter2"), ("metru", "meter3"), + ("stopa", "foot0"), ("stopy", "foot1"), ("stop", "foot2"),("stopy", "foot3"), + ("stupeň celsia", "celsius0"), ("stupně celsia", "celsius1"), ("stupňů celsia", "celsius2"), ("stupně celsia", "celsius3"), + ("stupeň fahrenheita", "fahr0"), ("stupně fahrenheita", "fahr1"), ("stupňů fahrenheita", "fahr2"), ("stupně fahrenheita", "fahr3"), + ("procento", "percent0"), ("procenta", "percent1"), ("procent", "percent2"), ("procenta", "percent3"), + ("miliampérhodina", "mamph0"), ("miliampérhodiny", "mamph1"), ("miliampérhodin", "mamph2"), ("miliampérhodiny", "mamph3"), + ("vat", "watt0"), ("vaty", "watt1"), ("vatů", "watt2"), ("vatu", "watt3"), + ("milivat", "mwatt0"), ("milivaty", "mwatt1"), ("milivatů", "mwatt2"), ("milivatu", "mwatt3"), + ("decibel", "db0"), ("decibely", "db1"), ("decibelů", "db2"), ("decibelu", "db3"), + ("otáčka za minutu", "rpm0"), ("otáčky za minutu", "rpm1"), ("otáček za minutu", "rpm2"), ("otáčky za minutu", "rpm3"), + ("gé", "g0"), ("gé", "g1"), ("gé", "g2"), ("gé", "g3"), + ("stupeň", "degree0"), ("stupně", "degree1"), ("stupňů", "degree2"), ("stupně", "degree3"), + ("radián", "rad0"), ("radiány", "rad1"), ("radiánů", "rad2"), ("radiánu", "rad3"), + ("mililitr", "ml0"), ("mililitry", "ml1"), ("mililitrů", "ml2"), ("mililitru", "ml3"), + ("dutá unce", "founce0"), ("duté unce", "founce1"), ("dutých uncí", "founce2"), ("duté unce", "founce3"), + ("hodina", "hour0"), ("hodiny", "hour1"), ("hodin", "hour2"), ("hodiny", "hour3"), + ("minuta", "minute0"), ("minuty", "minute1"), ("minut", "minute2"), ("minuty", "minute3"), + ("sekunda", "second0"), ("sekundy", "second1"), ("sekund", "second2"), ("sekundy", "second3"), ]): systemSounds.append((s, filename(f, PROMPT_SYSTEM_BASE + 118 + i))) -for s, f, a in [(u"střed trimu", "midtrim", 495), - (u"maximum trimu", "maxtrim", NO_ALTERNATE), - (u"minimum trimu", "mintrim", NO_ALTERNATE), - (u"stopky 1 doběhly", "timovr1", NO_ALTERNATE), - (u"stopky 2 doběhly", "timovr2", NO_ALTERNATE), - (u"stopky 3 doběhly", "timovr3", NO_ALTERNATE), - (u"baterie rádia je vybitá", "lowbatt", 485), - (u"zapoměl jsi na mě!", "inactiv", 486), - (u"plyn není na nule", "thralert", 481), - (u"přepínače nejsou ve výchozí poloze", "swalert", 482), - (u"neplatná eeprom", "eebad", 483), - (u"Oupn najn iks", "hello", 480), - (u"Tak zase příště!", "bye", 480), - (u"dvacet sekund", "timer20", 500), - (u"třicet sekund", "timer30", 501), - (u"A1,nízká", "a1_org", NO_ALTERNATE), - (u"A1,kritická", "a1_red", NO_ALTERNATE), - (u"A2,nízká", "a2_org", NO_ALTERNATE), - (u"A2,kritická", "a2_red", NO_ALTERNATE), - (u"A3,nízká", "a3_org", NO_ALTERNATE), - (u"A3,kritická", "a3_red", NO_ALTERNATE), - (u"A4,nízká", "a4_org", NO_ALTERNATE), - (u"A4,kritická", "a4_red", NO_ALTERNATE), - (u"nízký RF signál", "rssi_org", NO_ALTERNATE), - (u"kritický RF signál", "rssi_red", NO_ALTERNATE), - (u"problém s anténou rádia", "swr_red", NO_ALTERNATE), - (u"telemetrie ztracena", "telemko", NO_ALTERNATE), - (u"telemetrie je funkční", "telemok", NO_ALTERNATE), - (u"trenér port odpojen", "trainko", NO_ALTERNATE), - (u"trenér port připojen", "trainok", NO_ALTERNATE), - (u"senzor ztracen", "sensorko", NO_ALTERNATE), - (u"servo přetíženo", "servoko", NO_ALTERNATE), - (u"r f přebuzeno", "rxko", NO_ALTERNATE), +for s, f, a in [("střed trimu", "midtrim", 495), + ("maximum trimu", "maxtrim", NO_ALTERNATE), + ("minimum trimu", "mintrim", NO_ALTERNATE), + ("stopky 1 doběhly", "timovr1", NO_ALTERNATE), + ("stopky 2 doběhly", "timovr2", NO_ALTERNATE), + ("stopky 3 doběhly", "timovr3", NO_ALTERNATE), + ("baterie rádia je vybitá", "lowbatt", 485), + ("zapoměl jsi na mě!", "inactiv", 486), + ("plyn není na nule", "thralert", 481), + ("přepínače nejsou ve výchozí poloze", "swalert", 482), + ("neplatná eeprom", "eebad", 483), + ("Oupn najn iks", "hello", 480), + ("Tak zase příště!", "bye", 480), + ("dvacet sekund", "timer20", 500), + ("třicet sekund", "timer30", 501), + ("A1,nízká", "a1_org", NO_ALTERNATE), + ("A1,kritická", "a1_red", NO_ALTERNATE), + ("A2,nízká", "a2_org", NO_ALTERNATE), + ("A2,kritická", "a2_red", NO_ALTERNATE), + ("A3,nízká", "a3_org", NO_ALTERNATE), + ("A3,kritická", "a3_red", NO_ALTERNATE), + ("A4,nízká", "a4_org", NO_ALTERNATE), + ("A4,kritická", "a4_red", NO_ALTERNATE), + ("nízký RF signál", "rssi_org", NO_ALTERNATE), + ("kritický RF signál", "rssi_red", NO_ALTERNATE), + ("problém s anténou rádia", "swr_red", NO_ALTERNATE), + ("telemetrie ztracena", "telemko", NO_ALTERNATE), + ("telemetrie je funkční", "telemok", NO_ALTERNATE), + ("trenér port odpojen", "trainko", NO_ALTERNATE), + ("trenér port připojen", "trainok", NO_ALTERNATE), + ("senzor ztracen", "sensorko", NO_ALTERNATE), + ("servo přetíženo", "servoko", NO_ALTERNATE), + ("r f přebuzeno", "rxko", NO_ALTERNATE), ]: systemSounds.append((s, filename(f, a))) -for i, (s, f) in enumerate([(u"podvozek je zasunut", "podvo0"), - (u"podvozek je vysunut", "podvo1"), - (u"klapky jsou zapnuty", "klapk1"), - (u"klapky jsou vypnuty", "klapk0"), - (u"trenér je zapnut", "trene1"), - (u"trenér je vypnutý", "trene0"), - (u"motor je vypnut", "motor0"), - (u"motor je aktivován", "motor1"), - (u"jsi příliš vysoko", "vysoko"), - (u"jsi příliš nízko", "nizko"), - (u"baterie modelu je vybitá", "bat0"), - (u"dochází palivo", "palivo"), - (u"nízký signál!", "nsigna"), - (u"kritický signál!", "ksigna"), - (u"rychlý režim aktivován", "rrychl"), - (u"termický režim aktivován", "rtermi"), - (u"normální režim aktivován", "rnorm"), - (u"režim start aktivován", "rstart"), - (u"režim přistání aktivován", "prista"), - (u"vario je zapnuto", "vario0"), - (u"vario je vypnuto", "vario1"), - (u"start povolen", "start1"), - (u"letový režim jedna", "fm-1"), - (u"letový režim dva", "fm-2"), - (u"letový režim tři", "fm-3"), - (u"letový režim čtyři", "fm-4"), - (u"letový režim pět", "fm-5"), - (u"letový režim šest", "fm-6"), - (u"letový režim sedm", "fm-7"), - (u"letový režim osm", "fm-8"), +for i, (s, f) in enumerate([("podvozek je zasunut", "podvo0"), + ("podvozek je vysunut", "podvo1"), + ("klapky jsou zapnuty", "klapk1"), + ("klapky jsou vypnuty", "klapk0"), + ("trenér je zapnut", "trene1"), + ("trenér je vypnutý", "trene0"), + ("motor je vypnut", "motor0"), + ("motor je aktivován", "motor1"), + ("jsi příliš vysoko", "vysoko"), + ("jsi příliš nízko", "nizko"), + ("baterie modelu je vybitá", "bat0"), + ("dochází palivo", "palivo"), + ("nízký signál!", "nsigna"), + ("kritický signál!", "ksigna"), + ("rychlý režim aktivován", "rrychl"), + ("termický režim aktivován", "rtermi"), + ("normální režim aktivován", "rnorm"), + ("režim start aktivován", "rstart"), + ("režim přistání aktivován", "prista"), + ("vario je zapnuto", "vario0"), + ("vario je vypnuto", "vario1"), + ("start povolen", "start1"), + ("letový režim jedna", "fm-1"), + ("letový režim dva", "fm-2"), + ("letový režim tři", "fm-3"), + ("letový režim čtyři", "fm-4"), + ("letový režim pět", "fm-5"), + ("letový režim šest", "fm-6"), + ("letový režim sedm", "fm-7"), + ("letový režim osm", "fm-8"), ]): sounds.append((s, filename(f, PROMPT_CUSTOM_BASE + i))) diff --git a/radio/util/tts_de.py b/radio/util/tts_de.py index e33732c5e..2e087fa24 100755 --- a/radio/util/tts_de.py +++ b/radio/util/tts_de.py @@ -16,64 +16,64 @@ systemSounds.append(("hundert", filename(PROMPT_SYSTEM_BASE + 102))) systemSounds.append(("tausend", filename(PROMPT_SYSTEM_BASE + 103))) for i, s in enumerate(["komma", "und", "minus", "uhr", "minute", "minuten", "sekunde", "sekunden", "stunde", "stunden"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 104 + i))) -for i, (s, f) in enumerate([(u"Wolt","volt0"), - (u"Ampär", "amp0"), - (u"MilliAmpär", "mamp0"), - (u"Knoten", "knot0"), - (u"Meter pro sekunde", "mps0"), - (u"Fuss pro sekunde", "fps0"), - (u"Kilometer pro stunde", "kph0"), - (u"Meilen pro Stunde", "mph0"), - (u"Meter", "meter0"), - (u"Fuesse", "foot0"), - (u"Grad Celsius", "celsius0"), - (u"Grad Fahrenheit", "fahr0"), - (u"Prozent", "percent0"), - (u"Milliampär pro stunde", "mamph0"), - (u"Watt", "watt0"), - (u"Milli Watt", "mwatt0"), - (u"D B", "db0"), - (u"Drehzahl", "rpm0"), - (u"g", "g0"), - (u"Grad", "degree0"), - (u"radians", "rad0"), - (u"Milliliter", "ml0"), - (u"Unze", "founce0"), - (u"Stunde", "hour0"), (u"Stunden", "hour1"), - (u"Minute", "minute0"), (u"Minuten", "minute1"), - (u"Sekunde", "second0"), (u"Sekunden", "second1"), +for i, (s, f) in enumerate([("Wolt","volt0"), + ("Ampär", "amp0"), + ("MilliAmpär", "mamp0"), + ("Knoten", "knot0"), + ("Meter pro sekunde", "mps0"), + ("Fuss pro sekunde", "fps0"), + ("Kilometer pro stunde", "kph0"), + ("Meilen pro Stunde", "mph0"), + ("Meter", "meter0"), + ("Fuesse", "foot0"), + ("Grad Celsius", "celsius0"), + ("Grad Fahrenheit", "fahr0"), + ("Prozent", "percent0"), + ("Milliampär pro stunde", "mamph0"), + ("Watt", "watt0"), + ("Milli Watt", "mwatt0"), + ("D B", "db0"), + ("Drehzahl", "rpm0"), + ("g", "g0"), + ("Grad", "degree0"), + ("radians", "rad0"), + ("Milliliter", "ml0"), + ("Unze", "founce0"), + ("Stunde", "hour0"), ("Stunden", "hour1"), + ("Minute", "minute0"), ("Minuten", "minute1"), + ("Sekunde", "second0"), ("Sekunden", "second1"), ]): systemSounds.append((s, filename(f, PROMPT_SYSTEM_BASE + 114 + i))) -for s, f, a in [(u"Inaktivitätsalarm", "inactiv", 486), - (u"Senderspannung schwach", "lowbatt", 485), - (u"Gaskanal nicht Null, bitte prüfen", "thralert", 481), - (u"Schalter fehlpositioniert, bitte prüfen", "swalert", 482), - (u"EEPROM fehlerhaft", "eebad", NO_ALTERNATE), - (u"EEPROM formatiert", "eeformat", NO_ALTERNATE), - (u"Fehler", "error", NO_ALTERNATE), - (u"Trim zentriert", "midtrim", 495), - (u"Poti zentriert", "midpot", 496), - (u"Obere Trimmungsgrenze erreicht", "maxtrim", NO_ALTERNATE), - (u"Untere Trimmungsgrenze erreicht", "mintrim", NO_ALTERNATE), - (u"20 Sekunden", "timer20", 500), - (u"30 Sekunden", "timer30", 501), - (u"Senderstrom zu hoch!", "highmah", NO_ALTERNATE), - (u"Sendertemperatur zu hoch!", "hightemp", NO_ALTERNATE), - (u"A1 schwach!", "a1_org", NO_ALTERNATE), - (u"A1 kritisch!", "a1_red", NO_ALTERNATE), - (u"A2 schwach!", "a2_org", NO_ALTERNATE), - (u"A2 kritisch!", "a2_red", NO_ALTERNATE), - (u"A3 schwach!", "a3_org", NO_ALTERNATE), - (u"A3 kritisch!", "a3_red", NO_ALTERNATE), - (u"A4 schwach!", "a4_org", NO_ALTERNATE), - (u"A4 kritisch!", "a4_red", NO_ALTERNATE), - (u"Funksignal schwach!", "rssi_org", NO_ALTERNATE), - (u"Funksignal kritisch!", "rssi_red", NO_ALTERNATE), - (u"Problem mit der Sender Antenne", "swr_red", NO_ALTERNATE), - (u"Telemetrie verloren", "telemko", NO_ALTERNATE), - (u"Telemetrie wiederhergestellt", "telemok", NO_ALTERNATE), - (u"Schülersignal verloren", "trainko", NO_ALTERNATE), - (u"Schülersignal wiederhergestellt", "trainok", NO_ALTERNATE), +for s, f, a in [("Inaktivitätsalarm", "inactiv", 486), + ("Senderspannung schwach", "lowbatt", 485), + ("Gaskanal nicht Null, bitte prüfen", "thralert", 481), + ("Schalter fehlpositioniert, bitte prüfen", "swalert", 482), + ("EEPROM fehlerhaft", "eebad", NO_ALTERNATE), + ("EEPROM formatiert", "eeformat", NO_ALTERNATE), + ("Fehler", "error", NO_ALTERNATE), + ("Trim zentriert", "midtrim", 495), + ("Poti zentriert", "midpot", 496), + ("Obere Trimmungsgrenze erreicht", "maxtrim", NO_ALTERNATE), + ("Untere Trimmungsgrenze erreicht", "mintrim", NO_ALTERNATE), + ("20 Sekunden", "timer20", 500), + ("30 Sekunden", "timer30", 501), + ("Senderstrom zu hoch!", "highmah", NO_ALTERNATE), + ("Sendertemperatur zu hoch!", "hightemp", NO_ALTERNATE), + ("A1 schwach!", "a1_org", NO_ALTERNATE), + ("A1 kritisch!", "a1_red", NO_ALTERNATE), + ("A2 schwach!", "a2_org", NO_ALTERNATE), + ("A2 kritisch!", "a2_red", NO_ALTERNATE), + ("A3 schwach!", "a3_org", NO_ALTERNATE), + ("A3 kritisch!", "a3_red", NO_ALTERNATE), + ("A4 schwach!", "a4_org", NO_ALTERNATE), + ("A4 kritisch!", "a4_red", NO_ALTERNATE), + ("Funksignal schwach!", "rssi_org", NO_ALTERNATE), + ("Funksignal kritisch!", "rssi_red", NO_ALTERNATE), + ("Problem mit der Sender Antenne", "swr_red", NO_ALTERNATE), + ("Telemetrie verloren", "telemko", NO_ALTERNATE), + ("Telemetrie wiederhergestellt", "telemok", NO_ALTERNATE), + ("Schülersignal verloren", "trainko", NO_ALTERNATE), + ("Schülersignal wiederhergestellt", "trainok", NO_ALTERNATE), ]: systemSounds.append((s, filename(f, a))) for i, s in enumerate(["Uhr", "Uhr", "Sender", "Empfang", "A1", "A2", "Hoehe", "Motor", @@ -81,31 +81,31 @@ for i, s in enumerate(["Uhr", "Uhr", "Sender", "Empfang", "A1", "A2", "Hoehe", " "Zellen gesamt", "Spannung", "Strom", "Verbrauch", "Power", "Beschleunigung X", "Beschleunigung Y", "Beschleunigung Z", "Richtung", "Variometer", "Minimum", "Maximum"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 134 + i))) -for i, (s, f) in enumerate([(u"Fahrwerk eingezogen", "gearup"), - (u"Fahrwerk ausgefahren", "geardn"), - (u"Klappen eingefahren", "flapup"), - (u"Klappen ausgefahren", "flapdn"), - (u"Landung", "lnding"), - (u"Trainer-Modus ein", "trnon"), - (u"Trainer-Modus aus", "trnoff"), - (u"Motor aus", "engoff"), - (u"Motor an", "engon"), - (u"zu hoch", "tohigh"), - (u"zu niedrig", "tolow"), - (u"Batterie schwach", "lowbatt"), - (u"Butterfly ein", "crowon"), - (u"Butterfly aus", "crowof"), - (u"Geschwindigkeits-Modus ist aktiviert", "fm-spd"), - (u"Thermik-Modus ist aktiviert", "fm-thm"), - (u"Normal-Modus ist aktiviert", "fm-nrm"), - (u"Flugmodus 1", "fm-1"), - (u"Flugmodus 2", "fm-2"), - (u"Flugmodus 3", "fm-3"), - (u"Flugmodus 4", "fm-4"), - (u"Flugmodus 5", "fm-5"), - (u"Flugmodus 6", "fm-6"), - (u"Flugmodus 7", "fm-7"), - (u"Flugmodus 8", "fm-8"), - (u"Flugmodus 9", "fm-9"), +for i, (s, f) in enumerate([("Fahrwerk eingezogen", "gearup"), + ("Fahrwerk ausgefahren", "geardn"), + ("Klappen eingefahren", "flapup"), + ("Klappen ausgefahren", "flapdn"), + ("Landung", "lnding"), + ("Trainer-Modus ein", "trnon"), + ("Trainer-Modus aus", "trnoff"), + ("Motor aus", "engoff"), + ("Motor an", "engon"), + ("zu hoch", "tohigh"), + ("zu niedrig", "tolow"), + ("Batterie schwach", "lowbatt"), + ("Butterfly ein", "crowon"), + ("Butterfly aus", "crowof"), + ("Geschwindigkeits-Modus ist aktiviert", "fm-spd"), + ("Thermik-Modus ist aktiviert", "fm-thm"), + ("Normal-Modus ist aktiviert", "fm-nrm"), + ("Flugmodus 1", "fm-1"), + ("Flugmodus 2", "fm-2"), + ("Flugmodus 3", "fm-3"), + ("Flugmodus 4", "fm-4"), + ("Flugmodus 5", "fm-5"), + ("Flugmodus 6", "fm-6"), + ("Flugmodus 7", "fm-7"), + ("Flugmodus 8", "fm-8"), + ("Flugmodus 9", "fm-9"), ]): sounds.append((s, filename(f, PROMPT_CUSTOM_BASE + i))) diff --git a/radio/util/tts_en.py b/radio/util/tts_en.py index ff35cfe8c..0447c915c 100755 --- a/radio/util/tts_en.py +++ b/radio/util/tts_en.py @@ -46,74 +46,74 @@ for i, s in enumerate(["point zero", "point one", "point two", "point three", "point four", "point five", "point six", "point seven", "point eight", "point nine"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 167 + i))) -for s, f, a in [(u"trim center", "midtrim", 495), - (u"maximum trim reached", "maxtrim", NO_ALTERNATE), - (u"minimum trim reached", "mintrim", NO_ALTERNATE), - (u"timer 1 elapsed", "timovr1", NO_ALTERNATE), - (u"timer 2 elapsed", "timovr2", NO_ALTERNATE), - (u"timer 3 elapsed", "timovr3", NO_ALTERNATE), - (u"transmitter battery low", "lowbatt", 485), - (u"inactivity alarm", "inactiv", 486), - (u"throttle warning", "thralert", 481), - (u"switch warning", "swalert", 482), - (u"bad eeprom", "eebad", 483), - (u"Welcome to open tea ex!", "hello", 480), - (u"RF signal, low", "rssi_org", NO_ALTERNATE), - (u"RF signal, critical", "rssi_red", NO_ALTERNATE), - (u"radio antenna defective", "swr_red", NO_ALTERNATE), - (u"telemetry lost", "telemko", NO_ALTERNATE), - (u"telemetry recovered", "telemok", NO_ALTERNATE), - (u"trainer signal lost", "trainko", NO_ALTERNATE), - (u"trainer signal recovered", "trainok", NO_ALTERNATE), - (u"sensor lost", "sensorko", NO_ALTERNATE), - (u"servo overload", "servoko", NO_ALTERNATE), - (u"power overload", "rxko", NO_ALTERNATE), +for s, f, a in [("trim center", "midtrim", 495), + ("maximum trim reached", "maxtrim", NO_ALTERNATE), + ("minimum trim reached", "mintrim", NO_ALTERNATE), + ("timer 1 elapsed", "timovr1", NO_ALTERNATE), + ("timer 2 elapsed", "timovr2", NO_ALTERNATE), + ("timer 3 elapsed", "timovr3", NO_ALTERNATE), + ("transmitter battery low", "lowbatt", 485), + ("inactivity alarm", "inactiv", 486), + ("throttle warning", "thralert", 481), + ("switch warning", "swalert", 482), + ("bad eeprom", "eebad", 483), + ("Welcome to open tea ex!", "hello", 480), + ("RF signal, low", "rssi_org", NO_ALTERNATE), + ("RF signal, critical", "rssi_red", NO_ALTERNATE), + ("radio antenna defective", "swr_red", NO_ALTERNATE), + ("telemetry lost", "telemko", NO_ALTERNATE), + ("telemetry recovered", "telemok", NO_ALTERNATE), + ("trainer signal lost", "trainko", NO_ALTERNATE), + ("trainer signal recovered", "trainok", NO_ALTERNATE), + ("sensor lost", "sensorko", NO_ALTERNATE), + ("servo overload", "servoko", NO_ALTERNATE), + ("power overload", "rxko", NO_ALTERNATE), ]: systemSounds.append((s, filename(f, a))) -for i, (s, f) in enumerate([(u"gear!, up!", "gearup"), - (u"gear!, down!", "geardn"), - (u"flaps!, up!", "flapup"), - (u"flaps!, down!", "flapdn"), - (u"spoiler!, up!", "splrup"), - (u"spoiler!, down!", "splrdn"), - (u"trainer!, on!", "trnon"), - (u"trainer!, off!", "trnoff"), - (u"engine!, off!", "engoff"), - (u"too. high!", "tohigh"), - (u"too. low!", "tolow"), - (u"low. battery!", "lowbat"), - (u"crow!, on!", "crowon"), - (u"crow!, off!", "crowof"), - (u"rf. signal!, low!", "siglow"), - (u"rf. signal!, critical!", "sigcrt"), - (u"high. speed. mode!, active", "spdmod"), - (u"thermal. mode!, on", "thmmod"), - (u"normal. mode!, on", "nrmmod"), - (u"landing. mode!, on", "lnding"), - (u"acro. mode!, on", "acro"), - (u"flight. mode!, one", "fm-1"), - (u"flight. mode!, two", "fm-2"), - (u"flight. mode!, three", "fm-3"), - (u"flight. mode!, four", "fm-4"), - (u"flight. mode!, five", "fm-5"), - (u"flight. mode!, six", "fm-6"), - (u"flight. mode!, seven", "fm-7"), - (u"flight. mode!, eight", "fm-8"), - (u"vario!, on", "vrion"), - (u"vario!, off", "vrioff"), - (u"flight mode!, power", "fm-pwr"), - (u"flight mode!, land", "fm-lnd"), - (u"flight mode!, float", "fm-flt"), - (u"flight mode!, speed", "fm-spd"), - (u"flight mode!, fast", "fm-fst"), - (u"flight mode!, normal", "fm-nrm"), - (u"flight mode!, cruise", "fm-crs"), - (u"flight mode!, acro", "fm-acr"), - (u"flight mode!, race", "fm-rce"), - (u"flight mode!, launch", "fm-lch"), - (u"flight mode!, ping", "fm-png"), - (u"flight mode!, thermal", "fm-thm"), - (u"flight mode!, thermal left", "fm-thl"), - (u"flight mode!, thermal right", "fm-thr"), +for i, (s, f) in enumerate([("gear!, up!", "gearup"), + ("gear!, down!", "geardn"), + ("flaps!, up!", "flapup"), + ("flaps!, down!", "flapdn"), + ("spoiler!, up!", "splrup"), + ("spoiler!, down!", "splrdn"), + ("trainer!, on!", "trnon"), + ("trainer!, off!", "trnoff"), + ("engine!, off!", "engoff"), + ("too. high!", "tohigh"), + ("too. low!", "tolow"), + ("low. battery!", "lowbat"), + ("crow!, on!", "crowon"), + ("crow!, off!", "crowof"), + ("rf. signal!, low!", "siglow"), + ("rf. signal!, critical!", "sigcrt"), + ("high. speed. mode!, active", "spdmod"), + ("thermal. mode!, on", "thmmod"), + ("normal. mode!, on", "nrmmod"), + ("landing. mode!, on", "lnding"), + ("acro. mode!, on", "acro"), + ("flight mode one", "fm-1"), + ("flight mode two", "fm-2"), + ("flight mode three", "fm-3"), + ("flight mode four", "fm-4"), + ("flight mode five", "fm-5"), + ("flight mode six", "fm-6"), + ("flight mode seven", "fm-7"), + ("flight mode eight", "fm-8"), + ("vario!, on", "vrion"), + ("vario!, off", "vrioff"), + ("flight mode power", "fm-pwr"), + ("flight mode land", "fm-lnd"), + ("flight mode float", "fm-flt"), + ("flight mode speed", "fm-spd"), + ("flight mode fast", "fm-fst"), + ("flight mode normal", "fm-nrm"), + ("flight mode cruise", "fm-crs"), + ("flight mode acro", "fm-acr"), + ("flight mode race", "fm-rce"), + ("flight mode launch", "fm-lch"), + ("flight mode ping", "fm-png"), + ("flight mode thermal", "fm-thm"), + ("flight mode thermal left", "fm-thl"), + ("flight mode thermal right", "fm-thr"), ]): sounds.append((s, filename(f, PROMPT_CUSTOM_BASE + i))) diff --git a/radio/util/tts_es.py b/radio/util/tts_es.py index 8fdcc67f0..aa1a22b8a 100755 --- a/radio/util/tts_es.py +++ b/radio/util/tts_es.py @@ -22,89 +22,89 @@ systemSounds.append(("nuevecientos", filename(PROMPT_SYSTEM_BASE + 109))) systemSounds.append(("mil", filename(PROMPT_SYSTEM_BASE + 110))) for i, s in enumerate(["coma", "un", "una", "y", "meno", "hora", "horas", "minuto", "minutos", "segundo", "segundos"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 111 + i))) -for i, (s, f) in enumerate([(u"Voltio","volt0"), - (u"ampério", "amp0"), - (u"miliamperios", "mamp0"), - (u"knots", "knot0"), - (u"metros por segundo", "mps0"), - (u"pie por segundo", "fps0"), - (u"kilómetro por hora", "kph0"), - (u"millas por hora", "mph0"), - (u"metros", "meter0"), - (u"pie", "foot0"), - (u"grados", "celsius0"), - (u"fahrenheit", "fahr0"), - (u"por ciento", "percent0"), - (u"miliamperios por hora", "mamph0"), - (u"vatio", "watt0"), - (u"millivatio", "mwatt0"), - (u"D B", "db0"), - (u"R P M", "rpm0"), - (u"g", "g0"), - (u"grados", "degree0"), - (u"radianes ", "rad0"), - (u"mililitro", "ml0"), - (u"onzas", "founce0"), - (u"horas", "hour0"), - (u"minutos", "minute0"), - (u"segundos", "second0"), +for i, (s, f) in enumerate([("Voltio","volt0"), + ("ampério", "amp0"), + ("miliamperios", "mamp0"), + ("knots", "knot0"), + ("metros por segundo", "mps0"), + ("pie por segundo", "fps0"), + ("kilómetro por hora", "kph0"), + ("millas por hora", "mph0"), + ("metros", "meter0"), + ("pie", "foot0"), + ("grados", "celsius0"), + ("fahrenheit", "fahr0"), + ("por ciento", "percent0"), + ("miliamperios por hora", "mamph0"), + ("vatio", "watt0"), + ("millivatio", "mwatt0"), + ("D B", "db0"), + ("R P M", "rpm0"), + ("g", "g0"), + ("grados", "degree0"), + ("radianes ", "rad0"), + ("mililitro", "ml0"), + ("onzas", "founce0"), + ("horas", "hour0"), + ("minutos", "minute0"), + ("segundos", "second0"), ]): - systemSounds.append((s, filename(f, PROMPT_SYSTEM_BASE + 122 + i))) -for s, f, a in [(u"me tienes abandonada", "inactiv", 486), - (u"batería del transmisor baja", "lowbatt", 485), - (u"El acelerador está activado, por favor, corrijalo", "thralert", 481), - (u"Los interruptores no están en la posición correcta, por favor corrijalo", "swalert", 482), - (u"eeprom corrompida", "eebad", NO_ALTERNATE), - (u"Formateo de eeprom en curso", "eeformat", NO_ALTERNATE), - (u"error", "error", NO_ALTERNATE), - (u"trim centrado", "midtrim", 495), - (u"potenciómetro centrado", "midpot", 496), - (u"trim al máximo", "maxtrim", NO_ALTERNATE), - (u"trim al mínima", "mintrim", NO_ALTERNATE), - (u"20 segundos", "timer20", 500), - (u"30 segundos", "timer30", 501), - (u"assorbimiento elevado", "highmah", NO_ALTERNATE), - (u"temperatura elevada", "hightemp", NO_ALTERNATE), - (u"Alarma A1", "a1_org", NO_ALTERNATE), - (u"A1 crítica", "a1_red", NO_ALTERNATE), - (u"Alarma A2", "a2_org", NO_ALTERNATE), - (u"A2 crítica", "a2_red", NO_ALTERNATE), - (u"recepcion de señal baja", "rssi_org", NO_ALTERNATE), - (u"recepción de señal crítica", "rssi_red", NO_ALTERNATE), - (u"Problemas con la antena del transmisor", "swr_red", NO_ALTERNATE), - (u"Sin telemetría", "telemko", NO_ALTERNATE), - (u"Telemetría disponible", "telemok", NO_ALTERNATE), + systemSounds.append((s, filename(f, PROMPT_SYSTEM_BASE + 122 + i))) +for s, f, a in [("me tienes abandonada", "inactiv", 486), + ("batería del transmisor baja", "lowbatt", 485), + ("El acelerador está activado, por favor, corrijalo", "thralert", 481), + ("Los interruptores no están en la posición correcta, por favor corrijalo", "swalert", 482), + ("eeprom corrompida", "eebad", NO_ALTERNATE), + ("Formateo de eeprom en curso", "eeformat", NO_ALTERNATE), + ("error", "error", NO_ALTERNATE), + ("trim centrado", "midtrim", 495), + ("potenciómetro centrado", "midpot", 496), + ("trim al máximo", "maxtrim", NO_ALTERNATE), + ("trim al mínima", "mintrim", NO_ALTERNATE), + ("20 segundos", "timer20", 500), + ("30 segundos", "timer30", 501), + ("assorbimiento elevado", "highmah", NO_ALTERNATE), + ("temperatura elevada", "hightemp", NO_ALTERNATE), + ("Alarma A1", "a1_org", NO_ALTERNATE), + ("A1 crítica", "a1_red", NO_ALTERNATE), + ("Alarma A2", "a2_org", NO_ALTERNATE), + ("A2 crítica", "a2_red", NO_ALTERNATE), + ("recepcion de señal baja", "rssi_org", NO_ALTERNATE), + ("recepción de señal crítica", "rssi_red", NO_ALTERNATE), + ("Problemas con la antena del transmisor", "swr_red", NO_ALTERNATE), + ("Sin telemetría", "telemko", NO_ALTERNATE), + ("Telemetría disponible", "telemok", NO_ALTERNATE), ]: systemSounds.append((s, filename(f, a))) -for i, s in enumerate([u"cronómetro", u"cronómetro", u"transmisión", u"recepción", u"A1", u"A2", u"altitud", u"motor", - u"combustible", u"temperatura", u"temperatura", u"velocidad", u"distancia", u"altitude", u"célula lipo", - u"Total lipo", u"voltaje", u"corriente", u"consumo", u"potencia", u"aceleración X", u"aceleración Y", u"aceleración Z", - u"dirección", u"variómetro", u"minimo", u"máximo"]): +for i, s in enumerate(["cronómetro", "cronómetro", "transmisión", "recepción", "A1", "A2", "altitud", "motor", + "combustible", "temperatura", "temperatura", "velocidad", "distancia", "altitude", "célula lipo", + "Total lipo", "voltaje", "corriente", "consumo", "potencia", "aceleración X", "aceleración Y", "aceleración Z", + "dirección", "variómetro", "minimo", "máximo"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 141 + i))) -for i, (s, f) in enumerate([(u"tren arriba.", "gearup"), - (u"tren abajo.", "geardn"), - (u"flaps arriba", "flapup"), - (u"flaps abajo", "flapdn"), - (u"aterrizaje", "attero"), - (u"modo de entrenamiento activado", "trnon"), - (u"modo de entrenamiento deshabilitado", "trnoff"), - (u"motor apagado", "engoff"), - (u"muy alto", "tohigh"), - (u"muy bajo", "tolow"), - (u"bateria baja", "lowbat"), - (u"crou, activo", "crowon"), - (u"crou, desligado", "crowof"), - (u"modo de velocidad", "spdmod"), - (u"modo de térmica", "thmmod"), - (u"modo de vuelo normal", "nrmmod"), - (u"fase de vuelo 1", "fltmd1"), - (u"fase de vuelo 2", "fltmd2"), - (u"fase de vuelo 3", "fltmd3"), - (u"fase de vuelo 4", "fltmd4"), - (u"fase de vuelo 5", "fltmd5"), - (u"fase de vuelo 6", "fltmd6"), - (u"fase de vuelo 7", "fltmd7"), - (u"fase de vuelo 8", "fltmd8"), - (u"fase de vuelo 9", "fltmd9"), +for i, (s, f) in enumerate([("tren arriba.", "gearup"), + ("tren abajo.", "geardn"), + ("flaps arriba", "flapup"), + ("flaps abajo", "flapdn"), + ("aterrizaje", "attero"), + ("modo de entrenamiento activado", "trnon"), + ("modo de entrenamiento deshabilitado", "trnoff"), + ("motor apagado", "engoff"), + ("muy alto", "tohigh"), + ("muy bajo", "tolow"), + ("bateria baja", "lowbat"), + ("crou, activo", "crowon"), + ("crou, desligado", "crowof"), + ("modo de velocidad", "spdmod"), + ("modo de térmica", "thmmod"), + ("modo de vuelo normal", "nrmmod"), + ("fase de vuelo 1", "fltmd1"), + ("fase de vuelo 2", "fltmd2"), + ("fase de vuelo 3", "fltmd3"), + ("fase de vuelo 4", "fltmd4"), + ("fase de vuelo 5", "fltmd5"), + ("fase de vuelo 6", "fltmd6"), + ("fase de vuelo 7", "fltmd7"), + ("fase de vuelo 8", "fltmd8"), + ("fase de vuelo 9", "fltmd9"), ]): sounds.append((s, filename(f, PROMPT_CUSTOM_BASE + i))) diff --git a/radio/util/tts_fr.py b/radio/util/tts_fr.py index e80b8957b..0336ddc92 100755 --- a/radio/util/tts_fr.py +++ b/radio/util/tts_fr.py @@ -15,70 +15,99 @@ for i, s in enumerate(["une", "onze", "vingt et une", "trente et une", "quarante systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 110 + i))) for i, s in enumerate(["virgule", "et", "moins", "minuit", "midi"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 119 + i))) -for i, (s, f) in enumerate([(u"volts","volt0"), - (u"ampères", "amp0"), - (u"milli ampères", "mamp0"), - (u"noeud", "knot0"), - (u"mètres seconde", "mps0"), - (u"pieds par seconde", "fps0"), - (u"kilomètre heure", "kph0"), - (u"miles par heure", "mph0"), - (u"mètres", "meter0"), - (u"pieds", "foot0"), - (u"degrés", "celsius0"), - (u"degrés fahrenheit", "degf0"), - (u"pourcents", "percent0"), - (u"milli ampères heure", "mamph0"), - (u"watt", "watt0"), - (u"milli watt", "mwatt0"), - (u"d b", "db0"), - (u"tours minute", "rpm0"), - (u"g", "g0"), - (u"degrés", "degree0"), - (u"radians", "rad0"), - (u"millilitres", "ml0"), - (u"onces", "founce0"), - (u"heure", "hour0"), - (u"minute", "minute0"), - (u"seconde", "second0"), +for i, (s, f) in enumerate([("volts","volt0"), + ("ampères", "amp0"), + ("milli ampères", "mamp0"), + ("noeud", "knot0"), + ("mètres seconde", "mps0"), + ("pieds par seconde", "fps0"), + ("kilomètre heure", "kph0"), + ("miles par heure", "mph0"), + ("mètres", "meter0"), + ("pieds", "foot0"), + ("degrés", "celsius0"), + ("degrés fahrenheit", "degf0"), + ("pourcents", "percent0"), + ("milli ampères heure", "mamph0"), + ("watt", "watt0"), + ("milli watt", "mwatt0"), + ("d b", "db0"), + ("tours minute", "rpm0"), + ("g", "g0"), + ("degrés", "degree0"), + ("radians", "rad0"), + ("millilitres", "ml0"), + ("onces", "founce0"), + ("heure", "hour0"), + ("minute", "minute0"), + ("seconde", "second0"), ]): systemSounds.append((s, filename(f, PROMPT_SYSTEM_BASE + 125 + i))) for i, s in enumerate(["virgule 0", "virgule 1", "virgule 2", "virgule 3", "virgule 4", "virgule 5", "virgule 6", "virgule 7", "virgule 8", "virgule 9"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 180 + i))) -for s, f, a in [(u"Trim centré", "midtrim", 495), - (u"Trim maximum atteint", "maxtrim", NO_ALTERNATE), - (u"Trim minimum atteint", "mintrim", NO_ALTERNATE), - (u"Chrono 1 à 0", "timovr1", NO_ALTERNATE), - (u"Chrono 2 à 0", "timovr2", NO_ALTERNATE), - (u"Chrono 3 à 0", "timovr3", NO_ALTERNATE), - (u"Batterie radio faible !", "lowbatt", 485), - (u"Radio inactive !", "inactiv", 486), - (u"Alerte manche des gaz", "thralert", 481), - (u"Alerte inters", "swalert", 482), - (u"éprome corrompue", "eebad", 483), - (u"Bienvenue sur Open Thé Hix!", "hello", 480), - (u"Signal RF, faible", "rssi_org", NO_ALTERNATE), - (u"Signal RF, critique", "rssi_red", NO_ALTERNATE), - (u"Antenne défectueuse", "swr_red", NO_ALTERNATE), - (u"Plus de télémétrie", "telemko", NO_ALTERNATE), - (u"Télémétrie retrouvée", "telemok", NO_ALTERNATE), - (u"Signal écolage perdu", "trainko", NO_ALTERNATE), - (u"Signal écolage retrouvé", "trainok", NO_ALTERNATE), - (u"Sonde de télémétrie perdue", "sensorko", NO_ALTERNATE), - (u"Servo en surcharge", "servoko", NO_ALTERNATE), - (u"Surcharge réception", "rxko", NO_ALTERNATE), +for s, f, a in [("Trim centré", "midtrim", 495), + ("Trim maximum atteint", "maxtrim", NO_ALTERNATE), + ("Trim minimum atteint", "mintrim", NO_ALTERNATE), + ("Chrono 1 à 0", "timovr1", NO_ALTERNATE), + ("Chrono 2 à 0", "timovr2", NO_ALTERNATE), + ("Chrono 3 à 0", "timovr3", NO_ALTERNATE), + ("Batterie radio faible !", "lowbatt", 485), + ("Radio inactive !", "inactiv", 486), + ("Alerte manche des gaz", "thralert", 481), + ("Alerte inters", "swalert", 482), + ("éprome corrompue", "eebad", 483), + ("Bienvenue sur o pun t x", "hello", 480), + ("Signal RF, faible", "rssi_org", NO_ALTERNATE), + ("Signal RF, critique", "rssi_red", NO_ALTERNATE), + ("Antenne défectueuse", "swr_red", NO_ALTERNATE), + ("Plus de télémétrie", "telemko", NO_ALTERNATE), + ("Télémétrie retrouvée", "telemok", NO_ALTERNATE), + ("Signal écolage perdu", "trainko", NO_ALTERNATE), + ("Signal écolage retrouvé", "trainok", NO_ALTERNATE), + ("Sonde de télémétrie perdue", "sensorko", NO_ALTERNATE), + ("Servo en surcharge", "servoko", NO_ALTERNATE), + ("Surcharge réception", "rxko", NO_ALTERNATE), ]: systemSounds.append((s, filename(f, a))) -for i, (s, f) in enumerate([(u"altitude", "altitude"), - (u"température moteur", "moteur"), - (u"température contrôleur", "cntrleur"), - (u"train rentré", "gearup"), - (u"train sorti", "geardn"), - (u"volets rentrés", "flapup"), - (u"volets sortis", "flapdn"), - (u"atterrissage", "attero"), - (u"écolage", "trnon"), - (u"fin écolage", "trnoff"), - (u"moteur coupé", "engoff"), +for i, (s, f) in enumerate([("altitude", "altitude"), + ("température moteur", "moteur"), + ("température contrôleur", "cntrleur"), + ("train rentré", "gearup"), + ("train sorti", "geardn"), + ("volets rentrés", "flapup"), + ("volets sortis", "flapdn"), + ("atterrissage", "attero"), + ("écolage", "trnon"), + ("fin écolage", "trnoff"), + ("moteur coupé", "engoff"), + ("high. speed. mode!, active", "spdmod"), + ("thermal. mode!, on", "thmmod"), + ("normal. mode!, on", "nrmmod"), + ("landing. mode!, on", "lnding"), + ("mode acro", "acro"), + ("mode de vol un", "fm-1"), + ("mode de vol deux", "fm-2"), + ("mode de vol trois", "fm-3"), + ("mode de vol quatre", "fm-4"), + ("mode de vol 5", "fm-5"), + ("mode de vol 6", "fm-6"), + ("mode de vol sept", "fm-7"), + ("mode de vol 8", "fm-8"), + ("vario activé", "vrion"), + ("vario désactivé", "vrioff"), + ("mode de vol puissance", "fm-pwr"), + ("mode de vol attérissage", "fm-lnd"), + ("mode de vol amérissage", "fm-flt"), + ("mode de vol vitesse", "fm-spd"), + ("mode de vol rapide", "fm-fst"), + ("mode de vol normal", "fm-nrm"), + ("mode de vol de croisière", "fm-crs"), + ("mode de vol acro", "fm-acr"), + ("mode de vol course", "fm-rce"), + ("mode de vol lancé", "fm-lch"), + ("mode de vol ping", "fm-png"), + ("mode de vol thermique", "fm-thm"), + ("mode de vol thermique gauche", "fm-thl"), + ("mode de vol thermique droit", "fm-thr"), ]): sounds.append((s, filename(f, PROMPT_CUSTOM_BASE + i))) diff --git a/radio/util/tts_it.py b/radio/util/tts_it.py index 6df6c9e05..1dba1559f 100755 --- a/radio/util/tts_it.py +++ b/radio/util/tts_it.py @@ -14,93 +14,93 @@ systemSounds.append(("mila", filename(PROMPT_SYSTEM_BASE + 101))) systemSounds.append(("mille", filename(PROMPT_SYSTEM_BASE + 102))) for i, s in enumerate(["virgola", "un", "e", "meno", "ora", "ore", "minuto", "minuti", "secondo", "secondi"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 103 + i))) -for i, (s, f) in enumerate([(u"volt", "volt0"), - (u"ampere", "amp0"), - (u"milliampers", "mamp0"), - (u"nodo", "knot0"), ("nodi", "knot1"), - (u"metro al secondo", "mps0"), ("metri al secondo", "msp1"), - (u"piede al secondo", "fps0"), ("piedi al secondo", "fps1"), - (u"chilometro ora", "kph0"), ("kilometers per hour", "kph1"), - (u"miglio per ora", "mph0"), ("miglia per ora", "mph1"), - (u"metro", "meter0"), ("metri", "meter1"), - (u"piede", "foot0"), ("piedi", "foot1"), - (u"grado celsius", "celsius0"), ("gradi celsius", "celsius1"), - (u"grado fahrenheit", "fahr0"), ("gradi fahrenheit", "fahr1"), - (u"percento", "percent0"), (u"percento", "percent1"), - (u"milliampere ora", "mamph0"), (u"milliampere ora", "mamph1"), - (u"watt", "watt0"), (u"watt", "watt1"), - (u"milli-watt", "mwatt0"), ("milli-watts", "mwatt1"), - (u"d b", "db0"), (u"d b", "db1"), - (u"r p m", "rpm0"), (u"r p m", "rpm1"), - (u"g", "g0"), (u"g", "g1"), - (u"grado", "degree0"), ("gradi", "degree1"), - (u"radian", "rad0"), ("radians", "rad1"), - (u"millilitro", "m10"), ("millilitri", "m11"), - (u"oncia", "founce0"), ("once", "founce1"), - (u"ora", "hour0"), ("ore", "hour1"), - (u"minuto", "minute0"), ("minuti", "minute1"), - (u"secondo", "second0"), ("secondi", "second1"), +for i, (s, f) in enumerate([("volt", "volt0"), + ("ampere", "amp0"), + ("milliampers", "mamp0"), + ("nodo", "knot0"), ("nodi", "knot1"), + ("metro al secondo", "mps0"), ("metri al secondo", "msp1"), + ("piede al secondo", "fps0"), ("piedi al secondo", "fps1"), + ("chilometro ora", "kph0"), ("chilometri orari", "kph1"), + ("miglio per ora", "mph0"), ("miglia per ora", "mph1"), + ("metro", "meter0"), ("metri", "meter1"), + ("piede", "foot0"), ("piedi", "foot1"), + ("grado celsius", "celsius0"), ("gradi celsius", "celsius1"), + ("grado fahrenheit", "fahr0"), ("gradi fahrenheit", "fahr1"), + ("percento", "percent0"), ("percento", "percent1"), + ("milliampere ora", "mamph0"), ("milliampere ora", "mamph1"), + ("watt", "watt0"), ("watt", "watt1"), + ("milli-watt", "mwatt0"), ("milli-watt", "mwatt1"), + ("d b", "db0"), ("d b", "db1"), + ("r p m", "rpm0"), ("r p m", "rpm1"), + ("g", "g0"), ("g", "g1"), + ("grado", "degree0"), ("gradi", "degree1"), + ("radian", "rad0"), ("radians", "rad1"), + ("millilitro", "m10"), ("millilitri", "m11"), + ("oncia", "founce0"), ("once", "founce1"), + ("ora", "hour0"), ("ore", "hour1"), + ("minuto", "minute0"), ("minuti", "minute1"), + ("secondo", "second0"), ("secondi", "second1"), ]): systemSounds.append((s, filename(f, PROMPT_SYSTEM_BASE + 113 + i))) -for s, f, a in [(u"radio inattiva controllare", "inactiv", 486), - (u"batteria della radio scarica", "lowbatt", 485), - (u"controllo motore non in posizione, verificare", "thralert", 481), - (u"interruttori non in posizione, verificare", "swalert", 482), - (u"eeprom corrotta", "eebad", NO_ALTERNATE), - (u"formattazone eeprom in corso", "eeformat", NO_ALTERNATE), - (u"errore", "error", NO_ALTERNATE), - (u"trim centrato", "midtrim", 495), - (u"potenziometro centrato", "midpot", 496), - (u"massimo trim raggiunto", "maxtrim", NO_ALTERNATE), - (u"minimo trim raggiunto", "mintrim", NO_ALTERNATE), - (u"venti secondi", "timer20", 500), - (u"trenta secondi", "timer30", 501), - (u"assorbimento elevato", "highmah", NO_ALTERNATE), - (u"temperatura elevata", "hightemp", NO_ALTERNATE), - (u"A1 in allarme", "a1_org", NO_ALTERNATE), - (u"A1 critico", "a1_red", NO_ALTERNATE), - (u"A2 in allarme", "a2_org", NO_ALTERNATE), - (u"A2 critico", "a2_red", NO_ALTERNATE), - (u"A3 in allarme", "a3_org", NO_ALTERNATE), - (u"A3 critico", "a3_red", NO_ALTERNATE), - (u"A4 in allarme", "a4_org", NO_ALTERNATE), - (u"A4 critico", "a4_red", NO_ALTERNATE), - (u"Segnale radio basso", "rssi_org", NO_ALTERNATE), - (u"Segnale radio critico", "rssi_red", NO_ALTERNATE), - (u"Problema all'antenna della radio", "swr_red", NO_ALTERNATE), - (u"Telemetria assente", "telemko", NO_ALTERNATE), - (u"Telemetria disponibile", "telemok", NO_ALTERNATE), +for s, f, a in [("radio inattiva controllare", "inactiv", 486), + ("batteria della radio scarica", "lowbatt", 485), + ("controllo motore non in posizione, verificare", "thralert", 481), + ("interruttori non in posizione, verificare", "swalert", 482), + ("eeprom corrotta", "eebad", NO_ALTERNATE), + ("formattazzione eeprom in corso", "eeformat", NO_ALTERNATE), + ("errore", "error", NO_ALTERNATE), + ("trim centrato", "midtrim", 495), + ("potenziometro centrato", "midpot", 496), + ("massimo trim raggiunto", "maxtrim", NO_ALTERNATE), + ("minimo trim raggiunto", "mintrim", NO_ALTERNATE), + ("venti secondi", "timer20", 500), + ("trenta secondi", "timer30", 501), + ("assorbimento elevato", "highmah", NO_ALTERNATE), + ("temperatura elevata", "hightemp", NO_ALTERNATE), + ("A1 in allarme", "a1_org", NO_ALTERNATE), + ("A1 critico", "a1_red", NO_ALTERNATE), + ("A2 in allarme", "a2_org", NO_ALTERNATE), + ("A2 critico", "a2_red", NO_ALTERNATE), + ("A3 in allarme", "a3_org", NO_ALTERNATE), + ("A3 critico", "a3_red", NO_ALTERNATE), + ("A4 in allarme", "a4_org", NO_ALTERNATE), + ("A4 critico", "a4_red", NO_ALTERNATE), + ("Segnale radio basso", "rssi_org", NO_ALTERNATE), + ("Segnale radio critico", "rssi_red", NO_ALTERNATE), + ("Problema all'antenna della radio", "swr_red", NO_ALTERNATE), + ("Telemetria assente", "telemko", NO_ALTERNATE), + ("Telemetria disponibile", "telemok", NO_ALTERNATE), ]: systemSounds.append((s, filename(f, a))) -for i, s in enumerate([u"timer", u"", u"tensione", u"tensione", u"trasmissione", u"ricezione", u"altitudine", u"motore", - u"carburante", u"temperatura", u"temperatura", u"velocità", "distanza", u"altitudine", u"cella lipo", - u"totale lipo", u"tensione", u"corrente", u"consumo", u"potenza", u"accellerazione X", u"accellerazione Y", u"accellerazione Z", - u"direzione", u"variometro", u"minimo", u"massimo"]): +for i, s in enumerate(["timer", "", "tensione", "tensione", "trasmissione", "ricezione", "altitudine", "motore", + "carburante", "temperatura", "temperatura", "velocità", "distanza", "altitudine", "cella lipo", + "totale lipo", "tensione", "corrente", "consumo", "potenza", "accellerazione X", "accellerazione Y", "accellerazione Z", + "direzione", "variometro", "minimo", "massimo"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 135 + i))) -for i, (s, f) in enumerate([(u"carrello chiuso", "gearup"), - (u"carrello aperto", "geardn"), - (u"flap rientrati", "flapup"), - (u"flap estesi", "flapdn"), - (u"atterraggiio", "attero"), - (u"modalità maestro attiva", "trnon"), - (u"modalità maestro disattiva", "trnoff"), - (u"motore spento", "engoff"), - (u"troppo alto", "tohigh"), - (u"troppo basso", "tolow"), - (u"batteria scarica", "lowbat"), - (u"crow on", "crowon"), - (u"crow off", "crowof"), - (u"modo velocità", "spdmod"), - (u"modo termica", "thmmod"), - (u"modo volo normale", "nrmmod"), - (u"fase di volo 1", "fltmd1"), - (u"fase di volo 2", "fltmd2"), - (u"fase di volo 3", "fltmd3"), - (u"fase di volo 4", "fltmd4"), - (u"fase di volo 5", "fltmd5"), - (u"fase di volo 6", "fltmd6"), - (u"fase di volo 7", "fltmd7"), - (u"fase di volo 8", "fltmd8"), - (u"fase di volo 9", "fltmd9"), +for i, (s, f) in enumerate([("carrello chiuso", "gearup"), + ("carrello aperto", "geardn"), + ("flap rientrati", "flapup"), + ("flap estesi", "flapdn"), + ("atterraggio", "attero"), + ("modalità maestro attiva", "trnon"), + ("modalità maestro disattiva", "trnoff"), + ("motore spento", "engoff"), + ("troppo alto", "tohigh"), + ("troppo basso", "tolow"), + ("batteria scarica", "lowbat"), + ("crow on", "crowon"), + ("crow off", "crowof"), + ("modo velocità", "spdmod"), + ("modo termica", "thmmod"), + ("modo volo normale", "nrmmod"), + ("fase di volo 1", "fltmd1"), + ("fase di volo 2", "fltmd2"), + ("fase di volo 3", "fltmd3"), + ("fase di volo 4", "fltmd4"), + ("fase di volo 5", "fltmd5"), + ("fase di volo 6", "fltmd6"), + ("fase di volo 7", "fltmd7"), + ("fase di volo 8", "fltmd8"), + ("fase di volo 9", "fltmd9"), ]): sounds.append((s, filename(f, PROMPT_CUSTOM_BASE + i))) diff --git a/radio/util/tts_pt.py b/radio/util/tts_pt.py index 298d8b107..d708d6aa8 100755 --- a/radio/util/tts_pt.py +++ b/radio/util/tts_pt.py @@ -50,59 +50,59 @@ for i, (s, f) in enumerate([("Volt", "volt0"), ("segundos", "second0"), ]): systemSounds.append((s, filename(f, PROMPT_SYSTEM_BASE + 122 + i))) -for s, f, a in [(u"atenção, o rádio foi esquecido ligado, por favor desligue-o", "inactiv", 486), - (u"bateria do rádio fraca", "lowbatt", 485), - (u"atenção,acelerador não está no mínimo", "thralert", 481), - (u"atenção, certifique-se que os interruptores estão na posição certa", "swalert", 482), - (u"eeprom corrompida", "eebad", NO_ALTERNATE), - (u"formatação da eeprom em curso", "eeformat", NO_ALTERNATE), - (u"erro", "error", NO_ALTERNATE), - (u"trim centrado", "midtrim", 495), - (u"potenciómetro centrado", "midpot", 496), - (u"trim no máximo", "maxtrim", NO_ALTERNATE), - (u"trim no mínimo", "mintrim", NO_ALTERNATE), - (u"20 segundos", "timer20", 500), - (u"30 segundos", "timer30", 501), - (u"assorbimento elevato", "highmah", NO_ALTERNATE), - (u"temperatura elevata", "hightemp", NO_ALTERNATE), - (u"Alarme A1", "a1_org", NO_ALTERNATE), - (u"A1 critica", "a1_red", NO_ALTERNATE), - (u"Alarme A2", "a2_org", NO_ALTERNATE), - (u"A2 critica", "a2_red", NO_ALTERNATE), - (u"recepção de sinal muito baixa", "rssi_org", NO_ALTERNATE), - (u"recepção de sinal crítica", "rssi_red", NO_ALTERNATE), - (u"Problema com a antena do transmissor", "swr_red", NO_ALTERNATE), +for s, f, a in [("atenção, o rádio foi esquecido ligado, por favor desligue-o", "inactiv", 486), + ("bateria do rádio fraca", "lowbatt", 485), + ("atenção,acelerador não está no mínimo", "thralert", 481), + ("atenção, certifique-se que os interruptores estão na posição certa", "swalert", 482), + ("eeprom corrompida", "eebad", NO_ALTERNATE), + ("formatação da eeprom em curso", "eeformat", NO_ALTERNATE), + ("erro", "error", NO_ALTERNATE), + ("trim centrado", "midtrim", 495), + ("potenciómetro centrado", "midpot", 496), + ("trim no máximo", "maxtrim", NO_ALTERNATE), + ("trim no mínimo", "mintrim", NO_ALTERNATE), + ("20 segundos", "timer20", 500), + ("30 segundos", "timer30", 501), + ("assorbimento elevato", "highmah", NO_ALTERNATE), + ("temperatura elevata", "hightemp", NO_ALTERNATE), + ("Alarme A1", "a1_org", NO_ALTERNATE), + ("A1 critica", "a1_red", NO_ALTERNATE), + ("Alarme A2", "a2_org", NO_ALTERNATE), + ("A2 critica", "a2_red", NO_ALTERNATE), + ("recepção de sinal muito baixa", "rssi_org", NO_ALTERNATE), + ("recepção de sinal crítica", "rssi_red", NO_ALTERNATE), + ("Problema com a antena do transmissor", "swr_red", NO_ALTERNATE), ]: systemSounds.append((s, filename(f, a))) -for i, s in enumerate([u"cronómetro", u"cronómetro", u"transmissão", u"recepção", u"A1", u"A2", u"altitude", u"motor", - u"combustível", u"temperatura", u"temperatura", u"velocidade", u"distância", u"altitude", u"célula lipo", - u"Total lipo", u"tensão", u"corrente", u"consumo", u"potência", u"aceleração X", u"aceleração Y", u"aceleração Z", - u"Direcção", u"variómetro", u"mínimo", u"máximo"]): +for i, s in enumerate(["cronómetro", "cronómetro", "transmissão", "recepção", "A1", "A2", "altitude", "motor", + "combustível", "temperatura", "temperatura", "velocidade", "distância", "altitude", "célula lipo", + "Total lipo", "tensão", "corrente", "consumo", "potência", "aceleração X", "aceleração Y", "aceleração Z", + "Direcção", "variómetro", "mínimo", "máximo"]): systemSounds.append((s, filename(PROMPT_SYSTEM_BASE + 141 + i))) -for i, (s, f) in enumerate([(u"trem, em cima.", "gearup"), - (u"trem, em baixo.", "geardn"), - (u"flaps recolhidos", "flapup"), - (u"flaps estendidos", "flapdn"), - (u"aterragem", "attero"), - (u"modo de treino ligado", "trnon"), - (u"modo de treino desligado", "trnoff"), - (u"motor desligado", "engoff"), - (u"muito alto", "tohigh"), - (u"muito baixo", "tolow"), - (u"bateria fraca", "lowbat"), - (u"crou, activo", "crowon"), - (u"crou, desligado", "crowof"), - (u"modo de velocidade", "spdmod"), - (u"modo de térmica", "thmmod"), - (u"modo de voo normal", "nrmmod"), - (u"fase de voo 1", "fltmd1"), - (u"fase de voo 2", "fltmd2"), - (u"fase de voo 3", "fltmd3"), - (u"fase de voo 4", "fltmd4"), - (u"fase de voo 5", "fltmd5"), - (u"fase de vôo 6", "fltmd6"), - (u"fase de voo 7", "fltmd7"), - (u"fase de voo 8", "fltmd8"), - (u"fase de voo 9", "fltmd9"), +for i, (s, f) in enumerate([("trem, em cima.", "gearup"), + ("trem, em baixo.", "geardn"), + ("flaps recolhidos", "flapup"), + ("flaps estendidos", "flapdn"), + ("aterragem", "attero"), + ("modo de treino ligado", "trnon"), + ("modo de treino desligado", "trnoff"), + ("motor desligado", "engoff"), + ("muito alto", "tohigh"), + ("muito baixo", "tolow"), + ("bateria fraca", "lowbat"), + ("crou, activo", "crowon"), + ("crou, desligado", "crowof"), + ("modo de velocidade", "spdmod"), + ("modo de térmica", "thmmod"), + ("modo de voo normal", "nrmmod"), + ("fase de voo 1", "fltmd1"), + ("fase de voo 2", "fltmd2"), + ("fase de voo 3", "fltmd3"), + ("fase de voo 4", "fltmd4"), + ("fase de voo 5", "fltmd5"), + ("fase de vôo 6", "fltmd6"), + ("fase de voo 7", "fltmd7"), + ("fase de voo 8", "fltmd8"), + ("fase de voo 9", "fltmd9"), ]): sounds.append((s, filename(f, PROMPT_CUSTOM_BASE + i))) diff --git a/tools/nightly22/build-sdcard.sh b/tools/nightly22/build-sdcard.sh index 897401350..968ff10ad 100644 --- a/tools/nightly22/build-sdcard.sh +++ b/tools/nightly22/build-sdcard.sh @@ -33,6 +33,8 @@ else python3 -B ${workdir}/code/tools/nightly22/tts.py es csv files python3 -B ${workdir}/code/tools/nightly22/tts.py it csv files python3 -B ${workdir}/code/tools/nightly22/tts.py de csv files + python3 -B ${workdir}/code/tools/nightly22/tts.py cz csv files + python3 -B ${workdir}/code/tools/nightly22/tts.py pt csv files # Create sdcards.zips for supported platforms mv /tmp/SOUNDS ${workdir}/sdcard/horus/ diff --git a/tools/nightly22/tts.py b/tools/nightly22/tts.py index 4841981db..b456367da 100755 --- a/tools/nightly22/tts.py +++ b/tools/nightly22/tts.py @@ -27,15 +27,18 @@ lib_path = os.path.abspath(os.path.join(SOURCE_DIRECTORY, '..', '..', 'radio', ' sys.path.append(lib_path) def generate(str, filename): - if 1: + if 0: output = "output.wav" command = 'pico2wave -l=%s -w=%s "%s"' % (voice, output, str) + os.system(command.encode('utf-8')) + command = "sox %s -r 32000 %s reverse silence 1 0.1 0.1%% reverse" % (output, filename) + os.system(command.encode('utf-8')) else: output = "output.mp3" command = 'gtts-cli -l %s -o %s "%s"' % (voice[:2], output, str) - os.system(command.encode('utf-8')) - command = "sox %s -r 32000 %s reverse silence 1 0.1 0.1%% reverse" % (output, filename) - os.system(command.encode('utf-8')) + os.system(command.encode('utf-8')) + command = "sox %s -r 32000 %s" % (output, filename) + os.system(command.encode('utf-8')) ################################################################ @@ -70,6 +73,18 @@ if __name__ == "__main__": directory = "es" voice = "es-ES" + elif "cz" in sys.argv: + from tts_cz import systemSounds, sounds + + directory = "cz" + voice = "cs-CZ" + + elif "pt" in sys.argv: + from tts_pt import systemSounds, sounds + + directory = "pt" + voice = "pt-PT" + else: print("which language?") exit() diff --git a/tools/release22/tts.py b/tools/release22/tts.py index 4f2bbcfe0..1e683566b 100755 --- a/tools/release22/tts.py +++ b/tools/release22/tts.py @@ -22,19 +22,27 @@ import zipfile from tts_common import * board = "taranis" -lib_path = os.path.abspath(os.path.join('code', 'radio', 'util')) +SOURCE_DIRECTORY = os.path.dirname(os.path.realpath(__file__)) +lib_path = os.path.abspath(os.path.join(SOURCE_DIRECTORY, '..', '..', 'radio', 'util')) sys.path.append(lib_path) def generate(str, filename): - - command = "pico2wave -l=" + voice + " -w=" + filename + " \"" + str + "\"" - os.system(command.encode('utf-8')) + if 0: + output = "output.wav" + command = 'pico2wave -l=%s -w=%s "%s"' % (voice, output, str) + os.system(command.encode('utf-8')) + command = "sox %s -r 32000 %s reverse silence 1 0.1 0.1%% reverse" % (output, filename) + os.system(command.encode('utf-8')) + else: + output = "output.mp3" + command = 'gtts-cli -l %s -o %s "%s"' % (voice[:2], output, str) + os.system(command.encode('utf-8')) + command = "sox %s -r 32000 %s" % (output, filename) + os.system(command.encode('utf-8')) ################################################################ if __name__ == "__main__": - - if "en" in sys.argv: from tts_en import systemSounds, sounds @@ -65,6 +73,18 @@ if __name__ == "__main__": directory = "es" voice = "es-ES" + elif "cz" in sys.argv: + from tts_cz import systemSounds, sounds + + directory = "cz" + voice = "cs-CZ" + + elif "pt" in sys.argv: + from tts_pt import systemSounds, sounds + + directory = "pt" + voice = "pt-PT" + else: print("which language?") exit() From 93dbdf868045f103673e702e0a2ef65cbe72d790 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Sun, 7 May 2017 22:25:06 +0200 Subject: [PATCH 203/203] Just some comments, the very minimum --- radio/src/maths.cpp | 5 ++++- radio/src/opentx.h | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/radio/src/maths.cpp b/radio/src/maths.cpp index 01d228cb1..f1244b1af 100644 --- a/radio/src/maths.cpp +++ b/radio/src/maths.cpp @@ -128,6 +128,7 @@ uint16_t isqrt32(uint32_t n) */ #if defined(FRSKY_HUB) && !defined(CPUARM) +// convert latitude and longitude to 1/10^6 degrees void extractLatitudeLongitude(uint32_t * latitude, uint32_t * longitude) { div_t qr = div(telemetryData.hub.gpsLatitude_bp, 100); @@ -140,10 +141,12 @@ void extractLatitudeLongitude(uint32_t * latitude, uint32_t * longitude) void getGpsPilotPosition() { extractLatitudeLongitude(&telemetryData.hub.pilotLatitude, &telemetryData.hub.pilotLongitude); + // distFromEarthAxis = cos(lat) * EARTH_RADIUS + // 1 - x2/2 + x4/24 uint32_t lat = telemetryData.hub.pilotLatitude / 10000; uint32_t angle2 = (lat*lat) / 10000; uint32_t angle4 = angle2 * angle2; - telemetryData.hub.distFromEarthAxis = 139*(((uint32_t)10000000-((angle2*(uint32_t)123370)/81)+(angle4/25))/12500); + telemetryData.hub.distFromEarthAxis = 139 * (((uint32_t)10000000-((angle2*(uint32_t)123370)/81)+(angle4/25)) / 12500); // TRACE("telemetryData.hub.distFromEarthAxis=%d", telemetryData.hub.distFromEarthAxis); } diff --git a/radio/src/opentx.h b/radio/src/opentx.h index 89e099521..7357971f0 100644 --- a/radio/src/opentx.h +++ b/radio/src/opentx.h @@ -1557,7 +1557,7 @@ extern uint8_t s_frsky_view; #endif #define EARTH_RADIUSKM ((uint32_t)6371) -#define EARTH_RADIUS ((uint32_t)111194) +#define EARTH_RADIUS ((uint32_t)111194) // meters * pi / 180° void getGpsPilotPosition(); void getGpsDistance();